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fix(interrupts): honor delegation when selecting in-order interrupts - #13
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RossComputerGuy merged 7 commits intoOct 8, 2026
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Supervisor software, timer and external interrupts currently participate in selection only through
sip/sie. When theirmidelegbit is clear, those views hide the source, so an enabled pending interrupt is dropped instead of targeting M-mode. For example, setting STIP, STIE and MIE withmideleg.STI=0never reachesmtvec.Select the six standard sources from the canonical
mip & miestate and use delegation plus the current privilege to determine eligibility. This also gives M-target interrupts priority over S-target interrupts: an undelegated SSI must outrank a delegated SEI, despite its lower source priority.The candidate remains registered, but is offered to the executor only while it matches the currently eligible winner. Writes to interrupt masks/delegation, privilege changes, or a newly pending higher-priority source therefore cannot leave a stale candidate available for acceptance. Once the executor accepts a trap, its existing completion and retirement path is unchanged.
Scope
Non-H in-order cores, with both static and microcoded execution. The H/OoO selector is unchanged. WFI remains a legal NOP, and there are no status-stack or reservation-policy changes.
Tests
Added RV32/RV64 cases for M/S/U delivery, global and local masks, target/source priority, candidate revalidation during CSR instructions, and completion after an accepted interrupt's source deasserts. Separate controls exercise WFI progress and M/S trap/return status preservation.
All 269 cases pass, including 129 existing controls for interrupt register integrity, AMO indivisibility, CSR aliases, MPRV, FCSR and VS trap delegation. Baseline fails 32 architectural delivery/priority assertions and 16 candidate-interface checks; all 221 baseline passes are preserved.