KaidenHsu

Follow

Kaiden KaidenHsu

Follow

An Electrical Engineering (SoC subgroup) graduate, studying system co-design and digital IC design in "System Co-Design Lab" at NSYSU, Taiwan.

5 followers · 11 following

National Sun-Yat Sen University
Kaohsiung, Taiwan
12:23 (UTC +08:00)
in/hong-yu-hsu-a8a9b6361

Achievements

Achievements

Highlights

Pro

KaidenHsu/README.md

Hi there, I'm Kaiden! 👋

🏫 M.S.: Electrical Engineering (SoC subgroup) @ NSYSU, Taiwan (System Co-Design Lab)
- research focus: combine system co-design, FPGA acceleration, digital IC design with biomedical applications
- tools: Gem5, Verilator, RISC-V, Xilinx Alveo U250 FPGA
- keywords: domain specific architecuture (DSA), electronic system level (ESL), digital IC design, FPGA prototyping, system co-design, hardware-software co-design, HBM
🏫 B.S.: Computer Science (AI subgroup) @ NCCU, Taiwan
📧 reach out to me: email
🎯2026 goal: familiarizing myself with ESL methodology and VLSI backend flow

</> Languages

🔨 Tools

📈 GitHub Stats

Pinned Loading

STN-Network STN-Network Public

Forked from hankshyu/STN-Network

Code to my ISASD, 2024 paper "An Improved Spatial Transformer Network based on Lightweight Localization Net (L-STN)"

Jupyter Notebook 1
Back-Angle-Measurement-Using-YOLOv8 Back-Angle-Measurement-Using-YOLOv8 Public

Code to my IJETI, 2026 paper "Real-Time Video-Based Measurement of Back Angles Using YOLOv8 and Edge Detection for Strength Training"

Python
DLab DLab Public

An implementation-oriented digital FPGA design course in NYCU

Verilog
SOPC-System-Design SOPC-System-Design Public

hws and labs for "SOPC Design Practice and FPGA System Design (2026 Spring)" in NSYSU, Taiwan

Verilog
Open-Source-Prototype-Systems Open-Source-Prototype-Systems Public

course projects for "Open Source Prototyping Systems and Applications (2026 Spring)" at NSYSU

SystemVerilog
ICLab ICLab Public

A digital IC design course implemented on FPGA in NYCU.

Verilog 1