v0.4.0

What's Changed

• feat: Add CXXRTL-based simulation infrastructure by @robtaylor in #161
• feat(rtl): support Verilog module parameters in RTLWrapper by @lanserge in #162
• feat(submit): pack design + pins.lock + manifest into a single bundle.zip by @lanserge in #165
• fix(auth): suggest 'gh auth refresh -s user:email' when token lacks the scope by @lanserge in #166
• feat(packaging): add BlockPackageDef for hard-macro builds by @lanserge in #167
• feat(packaging): add chipflow pin swap and chipflow pin show by @lanserge in #168
• feat(rtl): add load_blackbox_wrapper for NDA hard macros by @lanserge in #163

Full Changelog: v0.3.2...v0.4.0

v0.2.1-alpha

Point update to fix start of day instructions to use 'release' branch

v0.2-alpha

ChipFlow Platform v0.2-alpha enables RTL-designs, created and stored in GitHub repository, to be processed to GDSII
file, ready to be sent to the Fab.

Try our tutorial: https://docs.chipflow.io/
Installation requirements and readme: https://github.com/ChipFlow/chipflow-examples?tab=readme-ov-file#chipflow-examples
For the support head to: https://docs.chipflow.io/support.html

Features:
Support of edition of RTL example-files
Support of iHP130 node
Provide SRAM IP
The platform partially works in cloud and local machines

Limitations:
Support of other Nodes, incl. GF130
Send of GDSII file to the Fab
Access to GDSII file for the review or edition