Simple microcontroller based on the Ibex core
- RV32IM instruction set
- 8 kB SRAM instruction memory (IMEM)
- 4 kB SRAM data memory (DMEM)
- I2C bootloader
- Peripherals:
- I2C master
- UART master
- Programmable timer
- 10 GPIOs
- All peripherals suport interrupts
| Peripheral | Base Address |
|---|---|
| PIT | 0x20000000 |
| I2C | 0x30000000 |
| GPIO | 0x40000000 |
| UART | 0x50000000 |
| IMEM | 0x80000000 |
| DMEM | 0x90000000 |
Contains documentation for peripheral IPs, the boot EEPROM and the SRAM memories.
Contains scripts for Place and Route, MMMC configuration file.
SystemVerilog RTL for the MCU, where ibex_simple_system.sv contains the top module.
Contains scripts for simulating the design at different stages, scripts for launching synthesis and P&R tools.
Simulations are performed in this directory. Here you will find the xrun logs and waveform restore files for the three stages of simulation (RTL, post synthesis and post P&R).
Directory for the MCU software. This directory contains C code for the MCU and all the files necessary for compilation (linker, startup, make).
Contains script for synthesis and the SDC constraint file.
Contains testbenches for the RTL.
Before simulation the processor software has to be compiled (see sw/README.md).
Start simulation by executing xrun_sim_run.sh script in the terminal:
./script/xrun_sim_run.sh -gui -t gpio_simpleRestore waveform configuration with File -> Source Command Script -> Select restore.tcl.svcf.
If any RTL source files changed or processor software is recompiled – reload simulator (Simulation -> Reinvoke Simulator).