From e9ecadb0c151d838e7b6146facabde6d816caedf Mon Sep 17 00:00:00 2001 From: night1rider Date: Wed, 4 Nov 2026 16:28:24 -0700 Subject: [PATCH 1/4] [reg, test] Use 32-bit register accesses on all targets The whal_Reg_* helpers read and wrote through size_t, which is 64 bits on AArch64, so a write also changed the next register. They now always access one 32-bit register, as the header already said. Value and mask bits above bit 31 are dropped; reg.h and the driver guide say so. Adds core reg tests that check each helper touches only its own register and drops bits above bit 31, that an update clears field bits, and that a poll ignores bits outside the mask, retries until the field matches, waits for bits to clear, and times out. Builds src/reg.c in the core tests. --- docs/writing_a_driver.md | 3 + tests/README.md | 4 +- tests/core/Makefile | 5 +- tests/core/main.c | 2 + tests/core/test_reg.c | 221 +++++++++++++++++++++++++++++++++++++++ wolfHAL/reg.h | 20 ++-- 6 files changed, 245 insertions(+), 10 deletions(-) create mode 100644 tests/core/test_reg.c diff --git a/docs/writing_a_driver.md b/docs/writing_a_driver.md index 156ec555..b5437860 100644 --- a/docs/writing_a_driver.md +++ b/docs/writing_a_driver.md @@ -243,6 +243,9 @@ Use `Write` and `Read` for whole-register access. Use `Update` and `Get` when you need to modify or read individual fields within a register without disturbing other bits. +Every access is 32 bits wide, also on 64-bit targets where `size_t` is 64 +bits. Value and mask bits above bit 31 are dropped. + ### Timeouts Most drivers poll hardware status registers in busy-wait loops (e.g., waiting diff --git a/tests/README.md b/tests/README.md index da6bdc6e..8cd7c016 100644 --- a/tests/README.md +++ b/tests/README.md @@ -67,8 +67,8 @@ use `g_peripheralSensor[]`). ## Core Tests -Host-side unit tests (bitops, dispatch, endian) live in `core/` and build with -the native compiler: +Host-side unit tests (bitops, dispatch, endian, reg, timeout) live in `core/` +and build with the native compiler: ``` cd core && make && make run diff --git a/tests/core/Makefile b/tests/core/Makefile index f1d6b532..937ca2c0 100644 --- a/tests/core/Makefile +++ b/tests/core/Makefile @@ -24,9 +24,10 @@ WHAL_DIR = $(CURDIR)/../.. INCLUDE = -I$(WHAL_DIR) CFLAGS += -Wall -Werror $(INCLUDE) -g3 -TEST_SRC = main.c test_bitops.c test_dispatch.c test_endian.c test_timeout.c +TEST_SRC = main.c test_bitops.c test_dispatch.c test_endian.c test_reg.c test_timeout.c -WHAL_SRC = $(WHAL_DIR)/src/gpio/gpio.c \ +WHAL_SRC = $(WHAL_DIR)/src/reg.c \ + $(WHAL_DIR)/src/gpio/gpio.c \ $(WHAL_DIR)/src/uart/uart.c \ $(WHAL_DIR)/src/flash/flash.c \ $(WHAL_DIR)/src/timer/timer.c \ diff --git a/tests/core/main.c b/tests/core/main.c index 1eb94beb..00db0c9a 100644 --- a/tests/core/main.c +++ b/tests/core/main.c @@ -36,6 +36,7 @@ void whal_Test_Puts(const char *s) void whal_Test_Bitops(void); void whal_Test_Dispatch(void); void whal_Test_Endian(void); +void whal_Test_Reg(void); #ifndef WHAL_CFG_NO_TIMEOUT void whal_Test_Timeout(void); #endif @@ -49,6 +50,7 @@ int main(void) whal_Test_Bitops(); whal_Test_Dispatch(); whal_Test_Endian(); + whal_Test_Reg(); #ifndef WHAL_CFG_NO_TIMEOUT whal_Test_Timeout(); #endif diff --git a/tests/core/test_reg.c b/tests/core/test_reg.c new file mode 100644 index 00000000..9812496e --- /dev/null +++ b/tests/core/test_reg.c @@ -0,0 +1,221 @@ +/* test_reg.c + * + * Copyright (C) 2026 wolfSSL Inc. + * + * This file is part of wolfHAL. + * + * wolfHAL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfHAL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ + + +#include +#include +#include "../test.h" + +/* Each helper must touch only its own 32-bit word, also where size_t is + * 64 bits. */ + +#define SENTINEL 0xA5A5A5A5UL + +static uint32_t g_regs[3]; + +static size_t RegBase(void) +{ + return (size_t)(uintptr_t)g_regs; +} + +static void ResetRegs(void) +{ + g_regs[0] = SENTINEL; + g_regs[1] = 0; + g_regs[2] = SENTINEL; +} + +static void Test_Reg_WriteOnlyItsWord(void) +{ + ResetRegs(); + whal_Reg_Write(RegBase(), 4, 0x12345678); + WHAL_ASSERT_EQ(g_regs[1], 0x12345678); + WHAL_ASSERT_EQ(g_regs[0], SENTINEL); + WHAL_ASSERT_EQ(g_regs[2], SENTINEL); +} + +static void Test_Reg_ReadOnlyItsWord(void) +{ + ResetRegs(); + g_regs[1] = 0x0000BEEF; + /* Compare the full size_t; WHAL_ASSERT_EQ would cut it to int */ + WHAL_ASSERT_EQ(whal_Reg_Read(RegBase(), 4) == 0x0000BEEF, 1); +} + +static void Test_Reg_UpdateOnlyItsField(void) +{ + ResetRegs(); + /* Field bits start set, so the update must clear them */ + g_regs[1] = 0xFFFF00F0; + whal_Reg_Update(RegBase(), 4, 0x000000F0, 0x00000050); + WHAL_ASSERT_EQ(g_regs[1], 0xFFFF0050); + WHAL_ASSERT_EQ(g_regs[0], SENTINEL); + WHAL_ASSERT_EQ(g_regs[2], SENTINEL); +} + +static void Test_Reg_GetField(void) +{ + size_t val = 0; + + ResetRegs(); + g_regs[1] = 0x00003C00; + whal_Reg_Get(RegBase(), 4, 0x00003C00, 10, &val); + WHAL_ASSERT_EQ(val, 0xF); +} + +/* Upper and lower halves differ, so keeping the wrong half fails. The + * double shift is 0 where size_t is 32 bits. */ +#define REG_WIDE_VALUE (((size_t)0xA5A5A5A5 << 16 << 16) | 0x12345678) + +/* Bits above 31 are dropped. Compare full size_t values; WHAL_ASSERT_EQ + * cuts them to int. */ +static void Test_Reg_HighBitsDropped(void) +{ + size_t val = 0; + + ResetRegs(); + whal_Reg_Write(RegBase(), 4, REG_WIDE_VALUE); + WHAL_ASSERT_EQ(g_regs[1] == 0x12345678UL, 1); + WHAL_ASSERT_EQ(g_regs[2], SENTINEL); + WHAL_ASSERT_EQ(whal_Reg_Read(RegBase(), 4) == 0x12345678UL, 1); + g_regs[1] = 0xFFFFFFFF; + whal_Reg_Get(RegBase(), 4, (size_t)-1, 0, &val); + WHAL_ASSERT_EQ(val == 0xFFFFFFFFUL, 1); + + g_regs[1] = 0; + whal_Reg_Update(RegBase(), 4, (size_t)-1, REG_WIDE_VALUE); + WHAL_ASSERT_EQ(g_regs[1] == 0x12345678UL, 1); + WHAL_ASSERT_EQ(g_regs[0], SENTINEL); + WHAL_ASSERT_EQ(g_regs[2], SENTINEL); +} + +#ifndef WHAL_CFG_NO_TIMEOUT + +#ifdef WHAL_CFG_64BIT_TICK +typedef uint64_t RegTick_t; +#else +typedef uint32_t RegTick_t; +#endif + +static RegTick_t g_regTick; +static RegTick_t g_regSetAt; +static whal_Timeout g_regTimeout; + +/* Advances on each read so a poll can time out. Sets bit 0x80 at tick + * g_regSetAt when that is not 0. */ +static RegTick_t RegTick(void) +{ + if (g_regSetAt != 0 && g_regTick == g_regSetAt) { + g_regs[1] |= 0x80; + } + return g_regTick++; +} + +static whal_Timeout *RegTimeout(RegTick_t setAt) +{ + g_regTick = 0; + g_regSetAt = setAt; + g_regTimeout.timeoutTicks = 10; + g_regTimeout.GetTick = RegTick; + return &g_regTimeout; +} + +#endif /* !WHAL_CFG_NO_TIMEOUT */ + +static void Test_Reg_ReadPoll(void) +{ + whal_Timeout *timeout = NULL; + + ResetRegs(); + /* Bits outside the mask are set and must be ignored */ + g_regs[1] = 0xFF; +#ifndef WHAL_CFG_NO_TIMEOUT + /* A bounded wait, so a broken poll fails instead of hanging */ + timeout = RegTimeout(0); +#endif + WHAL_ASSERT_EQ(whal_Reg_ReadPoll(RegBase(), 4, 0x80, 0x80, timeout), + WHAL_SUCCESS); +} + +/* Value 0 waits for the masked bits to clear */ +static void Test_Reg_ReadPollClear(void) +{ + whal_Timeout *timeout = NULL; + + ResetRegs(); + g_regs[1] = 0x7F; +#ifndef WHAL_CFG_NO_TIMEOUT + timeout = RegTimeout(0); +#endif + WHAL_ASSERT_EQ(whal_Reg_ReadPoll(RegBase(), 4, 0x80, 0, timeout), + WHAL_SUCCESS); +} + +#ifndef WHAL_CFG_NO_TIMEOUT + +static void Test_Reg_ReadPollRetry(void) +{ + ResetRegs(); + /* Bit 0x80 sets at tick 3; the other bits are already set */ + g_regs[1] = 0x7F; + WHAL_ASSERT_EQ(whal_Reg_ReadPoll(RegBase(), 4, 0x80, 0x80, + RegTimeout(3)), + WHAL_SUCCESS); + /* The poll read the register again until the bit was set */ + WHAL_ASSERT_EQ(g_regTick > 3, 1); +} + +static void Test_Reg_ReadPollTimeout(void) +{ + ResetRegs(); + WHAL_ASSERT_EQ(whal_Reg_ReadPoll(RegBase(), 4, 0x80, 0x80, + RegTimeout(0)), + WHAL_ETIMEOUT); +} + +/* A set bit never clears, so the wait for clear times out */ +static void Test_Reg_ReadPollClearTimeout(void) +{ + ResetRegs(); + g_regs[1] = 0x80; + WHAL_ASSERT_EQ(whal_Reg_ReadPoll(RegBase(), 4, 0x80, 0, RegTimeout(0)), + WHAL_ETIMEOUT); +} + +#endif /* !WHAL_CFG_NO_TIMEOUT */ + +void whal_Test_Reg(void) +{ + WHAL_TEST_SUITE_START("reg"); + WHAL_TEST(Test_Reg_WriteOnlyItsWord); + WHAL_TEST(Test_Reg_ReadOnlyItsWord); + WHAL_TEST(Test_Reg_UpdateOnlyItsField); + WHAL_TEST(Test_Reg_GetField); + WHAL_TEST(Test_Reg_HighBitsDropped); + WHAL_TEST(Test_Reg_ReadPoll); + WHAL_TEST(Test_Reg_ReadPollClear); +#ifndef WHAL_CFG_NO_TIMEOUT + WHAL_TEST(Test_Reg_ReadPollRetry); + WHAL_TEST(Test_Reg_ReadPollTimeout); + WHAL_TEST(Test_Reg_ReadPollClearTimeout); +#endif + WHAL_TEST_SUITE_END(); +} diff --git a/wolfHAL/reg.h b/wolfHAL/reg.h index 607a3b51..f978c58b 100644 --- a/wolfHAL/reg.h +++ b/wolfHAL/reg.h @@ -23,6 +23,7 @@ #define WHAL_REG_H #include +#include #include #include #include @@ -30,6 +31,9 @@ /* * @file reg.h * @brief Helpers for accessing and manipulating memory-mapped registers. + * + * Every access is 32 bits wide, also where size_t is 64 bits. Value and + * mask bits above bit 31 are dropped. */ /* @@ -49,8 +53,8 @@ static inline void whal_Reg_Update(size_t base, size_t offset, size_t mask, size_t value) { - volatile size_t *reg = (size_t *)(base + offset); - *reg = (*reg & ~mask) | (value & mask); + volatile uint32_t *reg = (volatile uint32_t *)(base + offset); + *reg = (uint32_t)((*reg & ~mask) | (value & mask)); } /* @@ -67,7 +71,7 @@ static inline void whal_Reg_Update(size_t base, size_t offset, size_t mask, static inline void whal_Reg_Get(size_t base, size_t offset, size_t msk, size_t pos, size_t *value) { - size_t val = *(volatile size_t *)(base + offset); + size_t val = *(volatile uint32_t *)(base + offset); *value = whal_GetBits(msk, pos, val); } @@ -80,7 +84,7 @@ static inline void whal_Reg_Get(size_t base, size_t offset, size_t msk, */ static inline void whal_Reg_Write(size_t base, size_t offset, size_t value) { - *(volatile size_t *)(base + offset) = value; + *(volatile uint32_t *)(base + offset) = (uint32_t)value; } /* @@ -93,7 +97,7 @@ static inline void whal_Reg_Write(size_t base, size_t offset, size_t value) */ static inline size_t whal_Reg_Read(size_t base, size_t offset) { - return *(volatile size_t *)(base + offset); + return *(volatile uint32_t *)(base + offset); } /* @@ -102,8 +106,12 @@ static inline size_t whal_Reg_Read(size_t base, size_t offset) * @param base Register block base address. * @param offset Register offset. * @param mask Bit mask to extract the field. - * @param value Expected value of the masked field. + * @param value Expected value of the masked field. Must fit in @p mask + * and in 32 bits, or the poll never matches. * @param timeout Timeout instance (NULL for unbounded wait). + * + * @retval WHAL_SUCCESS The masked field matched @p value. + * @retval WHAL_ETIMEOUT The timeout expired first. */ whal_Error whal_Reg_ReadPoll(size_t base, size_t offset, size_t mask, size_t value, From 065c98febc6e30382bf803b5d7bc243b8da6d51b Mon Sep 17 00:00:00 2001 From: night1rider Date: Thu, 5 Nov 2026 13:05:32 -0700 Subject: [PATCH 2/4] [reg, test, docs] Add whal_Reg32_* and whal_Reg64_*; make whal_Reg_* opt-in whal_Reg32_* and whal_Reg64_* take a uintptr_t base, a uint32_t offset and values of the register's width, so the access width is explicit and no value is cast. whal_Reg64_* exists only where a 64-bit access is one access (WHAL_HAVE_REG64). The size_t whal_Reg_* API is now only built with WHAL_CFG_REG_LEGACY. It does 32-bit accesses through whal_Reg32_*. Where size_t is 64 bits, a value or mask above bit 31 returns WHAL_EINVAL and nothing is written; Write, Update and Get now return whal_Error. Where size_t is 32 bits there is no check, and the code is the same as before. The boards in boards/ define WHAL_CFG_REG_LEGACY, so the existing drivers build unchanged. Core tests cover Reg32, Reg64 and the legacy API, including the range checks, and check that whal_Reg_* is not defined without WHAL_CFG_REG_LEGACY. The driver and test guides use whal_Reg32_*. --- boards/pic32cz_curiosity_ultra/board.mk | 2 + boards/stm32c031_nucleo/board.mk | 2 + boards/stm32f091rc_nucleo/board.mk | 2 + boards/stm32f302r8_nucleo/board.mk | 2 + boards/stm32f411_blackpill/board.mk | 2 + boards/stm32h563zi_nucleo/board.mk | 2 + boards/stm32l152re_nucleo/board.mk | 2 + boards/stm32n657a0_nucleo/board.mk | 2 + boards/stm32u5a5zj_nucleo/board.mk | 2 + boards/stm32wb05kz_nucleo/board.mk | 2 + boards/stm32wb55xx_nucleo/board.mk | 2 + boards/stm32wba55cg_nucleo/board.mk | 2 + docs/adding_a_test.md | 6 +- docs/writing_a_driver.md | 73 ++-- src/reg.c | 42 ++- tests/core/Makefile | 18 +- tests/core/test_reg.c | 444 ++++++++++++++++++------ wolfHAL/reg.h | 258 ++++++++++++-- 18 files changed, 699 insertions(+), 166 deletions(-) diff --git a/boards/pic32cz_curiosity_ultra/board.mk b/boards/pic32cz_curiosity_ultra/board.mk index 929481ee..3865566b 100644 --- a/boards/pic32cz_curiosity_ultra/board.mk +++ b/boards/pic32cz_curiosity_ultra/board.mk @@ -28,6 +28,8 @@ GCC = $(GCC_PATH)arm-none-eabi-gcc LD = $(GCC_PATH)arm-none-eabi-ld OBJCOPY = $(GCC_PATH)arm-none-eabi-objcopy +# Drivers here use the legacy whal_Reg_* API +CFLAGS += -DWHAL_CFG_REG_LEGACY CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -ffreestanding -nostdlib -mcpu=cortex-m7 \ -DPLATFORM_PIC32CZ -MMD -MP \ diff --git a/boards/stm32c031_nucleo/board.mk b/boards/stm32c031_nucleo/board.mk index 48df459b..d93e758e 100644 --- a/boards/stm32c031_nucleo/board.mk +++ b/boards/stm32c031_nucleo/board.mk @@ -28,6 +28,8 @@ GCC = $(GCC_PATH)arm-none-eabi-gcc LD = $(GCC_PATH)arm-none-eabi-gcc OBJCOPY = $(GCC_PATH)arm-none-eabi-objcopy +# Drivers here use the legacy whal_Reg_* API +CFLAGS += -DWHAL_CFG_REG_LEGACY CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -ffreestanding -nostdlib -mcpu=cortex-m0plus -mthumb \ -DPLATFORM_STM32C0 -MMD -MP \ diff --git a/boards/stm32f091rc_nucleo/board.mk b/boards/stm32f091rc_nucleo/board.mk index 294ab717..f54d84fa 100644 --- a/boards/stm32f091rc_nucleo/board.mk +++ b/boards/stm32f091rc_nucleo/board.mk @@ -28,6 +28,8 @@ GCC = $(GCC_PATH)arm-none-eabi-gcc LD = $(GCC_PATH)arm-none-eabi-gcc OBJCOPY = $(GCC_PATH)arm-none-eabi-objcopy +# Drivers here use the legacy whal_Reg_* API +CFLAGS += -DWHAL_CFG_REG_LEGACY CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -ffreestanding -nostdlib -mcpu=cortex-m0 -mthumb \ -DPLATFORM_STM32F0 -MMD -MP \ diff --git a/boards/stm32f302r8_nucleo/board.mk b/boards/stm32f302r8_nucleo/board.mk index ebbccd11..f3995a6f 100644 --- a/boards/stm32f302r8_nucleo/board.mk +++ b/boards/stm32f302r8_nucleo/board.mk @@ -28,6 +28,8 @@ GCC = $(GCC_PATH)arm-none-eabi-gcc LD = $(GCC_PATH)arm-none-eabi-gcc OBJCOPY = $(GCC_PATH)arm-none-eabi-objcopy +# Drivers here use the legacy whal_Reg_* API +CFLAGS += -DWHAL_CFG_REG_LEGACY CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -ffreestanding -nostdlib \ -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 \ diff --git a/boards/stm32f411_blackpill/board.mk b/boards/stm32f411_blackpill/board.mk index a3e6fe26..5d7aecb2 100644 --- a/boards/stm32f411_blackpill/board.mk +++ b/boards/stm32f411_blackpill/board.mk @@ -28,6 +28,8 @@ GCC = $(GCC_PATH)arm-none-eabi-gcc LD = $(GCC_PATH)arm-none-eabi-ld OBJCOPY = $(GCC_PATH)arm-none-eabi-objcopy +# Drivers here use the legacy whal_Reg_* API +CFLAGS += -DWHAL_CFG_REG_LEGACY CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -ffreestanding -nostdlib -mcpu=cortex-m4 -mfloat-abi=hard \ -mfpu=fpv4-sp-d16 -mthumb \ diff --git a/boards/stm32h563zi_nucleo/board.mk b/boards/stm32h563zi_nucleo/board.mk index 9564bfdc..3f0b78ff 100644 --- a/boards/stm32h563zi_nucleo/board.mk +++ b/boards/stm32h563zi_nucleo/board.mk @@ -28,6 +28,8 @@ GCC = $(GCC_PATH)arm-none-eabi-gcc LD = $(GCC_PATH)arm-none-eabi-ld OBJCOPY = $(GCC_PATH)arm-none-eabi-objcopy +# Drivers here use the legacy whal_Reg_* API +CFLAGS += -DWHAL_CFG_REG_LEGACY CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -ffreestanding -nostdlib -mcpu=cortex-m33 \ -DPLATFORM_STM32H5 -MMD -MP \ diff --git a/boards/stm32l152re_nucleo/board.mk b/boards/stm32l152re_nucleo/board.mk index 205c17f6..9b345c03 100644 --- a/boards/stm32l152re_nucleo/board.mk +++ b/boards/stm32l152re_nucleo/board.mk @@ -28,6 +28,8 @@ GCC = $(GCC_PATH)arm-none-eabi-gcc LD = $(GCC_PATH)arm-none-eabi-gcc OBJCOPY = $(GCC_PATH)arm-none-eabi-objcopy +# Drivers here use the legacy whal_Reg_* API +CFLAGS += -DWHAL_CFG_REG_LEGACY CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -ffreestanding -nostdlib \ -mcpu=cortex-m3 -mthumb \ diff --git a/boards/stm32n657a0_nucleo/board.mk b/boards/stm32n657a0_nucleo/board.mk index 4484f405..b7bd60a9 100644 --- a/boards/stm32n657a0_nucleo/board.mk +++ b/boards/stm32n657a0_nucleo/board.mk @@ -28,6 +28,8 @@ GCC = $(GCC_PATH)arm-none-eabi-gcc LD = $(GCC_PATH)arm-none-eabi-ld OBJCOPY = $(GCC_PATH)arm-none-eabi-objcopy +# Drivers here use the legacy whal_Reg_* API +CFLAGS += -DWHAL_CFG_REG_LEGACY CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -ffreestanding -nostdlib -mcpu=cortex-m55 -mthumb \ -DPLATFORM_STM32N6 -MMD -MP \ diff --git a/boards/stm32u5a5zj_nucleo/board.mk b/boards/stm32u5a5zj_nucleo/board.mk index 4aea426f..b3e00662 100644 --- a/boards/stm32u5a5zj_nucleo/board.mk +++ b/boards/stm32u5a5zj_nucleo/board.mk @@ -28,6 +28,8 @@ GCC = $(GCC_PATH)arm-none-eabi-gcc LD = $(GCC_PATH)arm-none-eabi-ld OBJCOPY = $(GCC_PATH)arm-none-eabi-objcopy +# Drivers here use the legacy whal_Reg_* API +CFLAGS += -DWHAL_CFG_REG_LEGACY CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -ffreestanding -nostdlib -mcpu=cortex-m33 -mthumb \ -DPLATFORM_STM32U5 -MMD -MP \ diff --git a/boards/stm32wb05kz_nucleo/board.mk b/boards/stm32wb05kz_nucleo/board.mk index 0a54348e..930b8bd9 100644 --- a/boards/stm32wb05kz_nucleo/board.mk +++ b/boards/stm32wb05kz_nucleo/board.mk @@ -28,6 +28,8 @@ GCC = $(GCC_PATH)arm-none-eabi-gcc LD = $(GCC_PATH)arm-none-eabi-gcc OBJCOPY = $(GCC_PATH)arm-none-eabi-objcopy +# Drivers here use the legacy whal_Reg_* API +CFLAGS += -DWHAL_CFG_REG_LEGACY CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -ffreestanding -nostdlib -mcpu=cortex-m0plus -mthumb \ -DPLATFORM_STM32WB0 -MMD -MP \ diff --git a/boards/stm32wb55xx_nucleo/board.mk b/boards/stm32wb55xx_nucleo/board.mk index c65dc0a9..a96a0303 100644 --- a/boards/stm32wb55xx_nucleo/board.mk +++ b/boards/stm32wb55xx_nucleo/board.mk @@ -28,6 +28,8 @@ GCC = $(GCC_PATH)arm-none-eabi-gcc LD = $(GCC_PATH)arm-none-eabi-ld OBJCOPY = $(GCC_PATH)arm-none-eabi-objcopy +# Drivers here use the legacy whal_Reg_* API +CFLAGS += -DWHAL_CFG_REG_LEGACY CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -ffreestanding -nostdlib -mcpu=cortex-m4 \ -DPLATFORM_STM32WB -MMD -MP \ diff --git a/boards/stm32wba55cg_nucleo/board.mk b/boards/stm32wba55cg_nucleo/board.mk index 91158415..9d07d4eb 100644 --- a/boards/stm32wba55cg_nucleo/board.mk +++ b/boards/stm32wba55cg_nucleo/board.mk @@ -28,6 +28,8 @@ GCC = $(GCC_PATH)arm-none-eabi-gcc LD = $(GCC_PATH)arm-none-eabi-ld OBJCOPY = $(GCC_PATH)arm-none-eabi-objcopy +# Drivers here use the legacy whal_Reg_* API +CFLAGS += -DWHAL_CFG_REG_LEGACY CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -ffreestanding -nostdlib -mcpu=cortex-m33 -mthumb \ -DPLATFORM_STM32WBA -MMD -MP \ diff --git a/docs/adding_a_test.md b/docs/adding_a_test.md index d107467c..8c107f1d 100644 --- a/docs/adding_a_test.md +++ b/docs/adding_a_test.md @@ -61,7 +61,7 @@ name). Individual test functions are static and named `Test__`. Platform-specific tests verify that the driver correctly manipulates hardware registers. They include platform-specific headers and read registers directly -using `whal_Reg_Get()` to confirm that Init configured the right fields, that +using `whal_Reg32_Get()` to confirm that Init configured the right fields, that Set wrote to the correct output register, etc. These tests are automatically detected and compiled when building for the @@ -80,12 +80,12 @@ Create `tests//test__.c`: static void Test_Foo_SomeRegister(void) { - size_t val = 0; + uint32_t val = 0; /* Read the register block base from the platform's singleton (extern-declared * in the driver header; defined in the driver .c from the WHAL_CFG___DEV * initializer in wolfHAL_board.h). For vtable-dispatched drivers, use * BOARD_FOO_DEV->base instead. */ - whal_Reg_Get(whal__Foo_Dev.base, REG_OFFSET, MASK, POS, &val); + whal_Reg32_Get(whal__Foo_Dev.base, REG_OFFSET, MASK, POS, &val); WHAL_ASSERT_EQ(val, EXPECTED); } diff --git a/docs/writing_a_driver.md b/docs/writing_a_driver.md index b5437860..926c31ca 100644 --- a/docs/writing_a_driver.md +++ b/docs/writing_a_driver.md @@ -44,7 +44,8 @@ wolfHAL has three categories of drivers: **Platform drivers** operate directly on SoC hardware registers at fixed memory addresses. They are tied to a specific microcontroller family and use the -`whal_Reg_*` helpers to read and write peripheral registers. Examples: +`whal_Reg32_*` / `whal_Reg64_*` helpers to read and write peripheral +registers. Examples: `stm32wb_uart`, `stm32wb_gpio`, `stm32wb_dma`. **Peripheral drivers** communicate with external chips over a bus (SPI, I2C, @@ -232,19 +233,46 @@ There are two exceptions: ### Register Access -wolfHAL provides register access helpers in `wolfHAL/reg.h`: +wolfHAL provides register access helpers in `wolfHAL/reg.h`. Pick the set +that matches the register's width in the reference manual: -- `whal_Reg_Write()` — write a full register value -- `whal_Reg_Read()` — read a full register value -- `whal_Reg_Update()` — read-modify-write a specific field within a register -- `whal_Reg_Get()` — read and extract a masked field from a register +- `whal_Reg32_*` — 32-bit registers, `uint32_t` values. Always available. +- `whal_Reg64_*` — 64-bit registers, `uint64_t` values. Only where a 64-bit + access is a single access (`WHAL_HAVE_REG64`, set when `uintptr_t` is + wider than 32 bits). + +Each set has: + +- `Write()` — write a full register value +- `Read()` — read a full register value +- `Update()` — read-modify-write a specific field within a register +- `Get()` — read a masked field from a register, shifted down to bit 0 +- `ReadPoll()` — poll a register until a field matches (see below) Use `Write` and `Read` for whole-register access. Use `Update` and `Get` when you need to modify or read individual fields within a register without disturbing other bits. -Every access is 32 bits wide, also on 64-bit targets where `size_t` is 64 -bits. Value and mask bits above bit 31 are dropped. +```c +whal_Reg32_Update(base, UART_CR_REG, UART_CR_EN_Msk, UART_CR_EN_Msk); +whal_Reg32_Get(base, UART_FR_REG, UART_FR_CNT_Msk, UART_FR_CNT_Pos, + &rxCount); +``` + +The base is a `uintptr_t` and the offset a `uint32_t`. + +#### Legacy whal_Reg_* API + +The older `whal_Reg_Write`, `whal_Reg_Read`, `whal_Reg_Update`, +`whal_Reg_Get` and `whal_Reg_ReadPoll` take `size_t` arguments. They are +only available when `WHAL_CFG_REG_LEGACY` is defined, and do 32-bit +accesses through `whal_Reg32_*`. Where `size_t` is wider than 32 bits, a +value or mask above bit 31 returns `WHAL_EINVAL` and nothing is written. +`Write`, `Update` and `Get` return `whal_Error`. + +The boards in `boards/` define `WHAL_CFG_REG_LEGACY` because the existing +drivers still use this API. New drivers should use `whal_Reg32_*` / +`whal_Reg64_*`. ### Timeouts @@ -273,28 +301,29 @@ do not need to know the tick rate. The tick fields are 32-bit by default; define `WHAL_CFG_64BIT_TICK` to widen them to 64-bit (see "64-bit Ticks" below). -#### whal_Reg_ReadPoll +#### whal_Reg32_ReadPoll -For the common case of polling a register bit, use `whal_Reg_ReadPoll` from -`wolfHAL/reg.h`: +For the common case of polling a register bit, use `whal_Reg32_ReadPoll` +(or `whal_Reg64_ReadPoll`) from `wolfHAL/reg.h`: ```c -whal_Error whal_Reg_ReadPoll(size_t base, size_t offset, - size_t mask, size_t value, - whal_Timeout *timeout); +whal_Error whal_Reg32_ReadPoll(uintptr_t base, uint32_t offset, + uint32_t mask, uint32_t value, + whal_Timeout *timeout); ``` This polls until `(reg & mask) == value` or the timeout expires. Pass the mask -as the value to wait for bits to be set, or `0` to wait for bits to be clear: +as the value to wait for bits to be set, or `0` to wait for bits to be clear. +A value with bits outside the mask never matches: ```c /* Wait for TXE flag to be set */ -err = whal_Reg_ReadPoll(base, SPI_SR_REG, SPI_SR_TXE_Msk, - SPI_SR_TXE_Msk, cfg->timeout); +err = whal_Reg32_ReadPoll(base, SPI_SR_REG, SPI_SR_TXE_Msk, + SPI_SR_TXE_Msk, cfg->timeout); /* Wait for BSY flag to be clear */ -err = whal_Reg_ReadPoll(base, SPI_SR_REG, SPI_SR_BSY_Msk, - 0, cfg->timeout); +err = whal_Reg32_ReadPoll(base, SPI_SR_REG, SPI_SR_BSY_Msk, + 0, cfg->timeout); ``` A NULL timeout pointer means unbounded wait (poll forever). @@ -308,16 +337,16 @@ before returning. Use a `goto cleanup` pattern: ```c whal_Error err = WHAL_SUCCESS; -whal_Reg_Update(base, CR_REG, PG_Msk, 1); /* enable programming mode */ +whal_Reg32_Update(base, CR_REG, PG_Msk, PG_Msk); /* enable programming */ for (...) { - err = whal_Reg_ReadPoll(base, SR_REG, BSY_Msk, 0, cfg->timeout); + err = whal_Reg32_ReadPoll(base, SR_REG, BSY_Msk, 0, cfg->timeout); if (err) goto cleanup; } cleanup: - whal_Reg_Update(base, CR_REG, PG_Msk, 0); /* always disable */ + whal_Reg32_Update(base, CR_REG, PG_Msk, 0); /* always disable */ return err; ``` diff --git a/src/reg.c b/src/reg.c index ae3a4239..994d502f 100644 --- a/src/reg.c +++ b/src/reg.c @@ -21,17 +21,49 @@ #include -whal_Error whal_Reg_ReadPoll(size_t base, size_t offset, - size_t mask, size_t value, - whal_Timeout *timeout) +whal_Error whal_Reg32_ReadPoll(uintptr_t base, uint32_t offset, + uint32_t mask, uint32_t value, + whal_Timeout *timeout) +{ +#ifdef WHAL_CFG_NO_TIMEOUT + (void)(timeout); +#endif + WHAL_TIMEOUT_START(timeout); + while ((whal_Reg32_Read(base, offset) & mask) != value) { + if (WHAL_TIMEOUT_EXPIRED(timeout)) { + return WHAL_ETIMEOUT; + } + } + return WHAL_SUCCESS; +} + +#ifdef WHAL_HAVE_REG64 +whal_Error whal_Reg64_ReadPoll(uintptr_t base, uint32_t offset, + uint64_t mask, uint64_t value, + whal_Timeout *timeout) { #ifdef WHAL_CFG_NO_TIMEOUT (void)(timeout); #endif WHAL_TIMEOUT_START(timeout); - while ((whal_Reg_Read(base, offset) & mask) != value) { - if (WHAL_TIMEOUT_EXPIRED(timeout)) + while ((whal_Reg64_Read(base, offset) & mask) != value) { + if (WHAL_TIMEOUT_EXPIRED(timeout)) { return WHAL_ETIMEOUT; + } } return WHAL_SUCCESS; } +#endif /* WHAL_HAVE_REG64 */ + +#ifdef WHAL_CFG_REG_LEGACY +whal_Error whal_Reg_ReadPoll(size_t base, size_t offset, + size_t mask, size_t value, + whal_Timeout *timeout) +{ + if (!WHAL_REG_FITS32(mask) || !WHAL_REG_FITS32(value)) { + return WHAL_EINVAL; + } + return whal_Reg32_ReadPoll(base + offset, 0, mask & 0xFFFFFFFFu, + value & 0xFFFFFFFFu, timeout); +} +#endif /* WHAL_CFG_REG_LEGACY */ diff --git a/tests/core/Makefile b/tests/core/Makefile index 937ca2c0..57f9ac13 100644 --- a/tests/core/Makefile +++ b/tests/core/Makefile @@ -23,6 +23,9 @@ WHAL_DIR = $(CURDIR)/../.. INCLUDE = -I$(WHAL_DIR) CFLAGS += -Wall -Werror $(INCLUDE) -g3 +NOLEGACY_CFLAGS := $(CFLAGS) +# The core tests also cover the legacy whal_Reg_* API +CFLAGS += -DWHAL_CFG_REG_LEGACY TEST_SRC = main.c test_bitops.c test_dispatch.c test_endian.c test_reg.c test_timeout.c @@ -63,9 +66,20 @@ all: $(TARGET) $(TARGET): $(OBJECTS) $(CC) $(CFLAGS) -o $@ $(OBJECTS) -.PHONY: run clean +.PHONY: run clean legacy-off -run: $(TARGET) +# Without WHAL_CFG_REG_LEGACY, reg.c and whal_Reg32_* build and whal_Reg_* +# does not exist. +legacy-off: + $(CC) $(NOLEGACY_CFLAGS) -c -o /dev/null $(WHAL_DIR)/src/reg.c + printf '#include \nvoid f(void);\nvoid f(void) { whal_Reg32_Write(0, 0, 0); }\n' | \ + $(CC) $(NOLEGACY_CFLAGS) -x c -c -o /dev/null - + @if printf '#include \nvoid f(void);\nvoid f(void) { whal_Reg_Write(0, 0, 0); }\n' | \ + $(CC) $(NOLEGACY_CFLAGS) -x c -c -o /dev/null - 2>/dev/null; then \ + echo "legacy-off: FAIL, whal_Reg_Write exists"; exit 1; fi + @echo "legacy-off: PASS" + +run: legacy-off $(TARGET) ./$(TARGET) clean: diff --git a/tests/core/test_reg.c b/tests/core/test_reg.c index 9812496e..7ffc478c 100644 --- a/tests/core/test_reg.c +++ b/tests/core/test_reg.c @@ -24,16 +24,16 @@ #include #include "../test.h" -/* Each helper must touch only its own 32-bit word, also where size_t is - * 64 bits. */ +/* Each helper must touch only its own register. Wide values are compared + * with == because WHAL_ASSERT_EQ cuts them to int. */ #define SENTINEL 0xA5A5A5A5UL static uint32_t g_regs[3]; -static size_t RegBase(void) +static uintptr_t RegBase(void) { - return (size_t)(uintptr_t)g_regs; + return (uintptr_t)g_regs; } static void ResetRegs(void) @@ -43,69 +43,24 @@ static void ResetRegs(void) g_regs[2] = SENTINEL; } -static void Test_Reg_WriteOnlyItsWord(void) -{ - ResetRegs(); - whal_Reg_Write(RegBase(), 4, 0x12345678); - WHAL_ASSERT_EQ(g_regs[1], 0x12345678); - WHAL_ASSERT_EQ(g_regs[0], SENTINEL); - WHAL_ASSERT_EQ(g_regs[2], SENTINEL); -} +#ifdef WHAL_HAVE_REG64 +#define SENTINEL64 0xA5A5A5A5A5A5A5A5ULL +#define REG64_BIT ((uint64_t)1 << 40) -static void Test_Reg_ReadOnlyItsWord(void) -{ - ResetRegs(); - g_regs[1] = 0x0000BEEF; - /* Compare the full size_t; WHAL_ASSERT_EQ would cut it to int */ - WHAL_ASSERT_EQ(whal_Reg_Read(RegBase(), 4) == 0x0000BEEF, 1); -} +static uint64_t g_regs64[3]; -static void Test_Reg_UpdateOnlyItsField(void) +static uintptr_t Reg64Base(void) { - ResetRegs(); - /* Field bits start set, so the update must clear them */ - g_regs[1] = 0xFFFF00F0; - whal_Reg_Update(RegBase(), 4, 0x000000F0, 0x00000050); - WHAL_ASSERT_EQ(g_regs[1], 0xFFFF0050); - WHAL_ASSERT_EQ(g_regs[0], SENTINEL); - WHAL_ASSERT_EQ(g_regs[2], SENTINEL); + return (uintptr_t)g_regs64; } -static void Test_Reg_GetField(void) +static void ResetRegs64(void) { - size_t val = 0; - - ResetRegs(); - g_regs[1] = 0x00003C00; - whal_Reg_Get(RegBase(), 4, 0x00003C00, 10, &val); - WHAL_ASSERT_EQ(val, 0xF); -} - -/* Upper and lower halves differ, so keeping the wrong half fails. The - * double shift is 0 where size_t is 32 bits. */ -#define REG_WIDE_VALUE (((size_t)0xA5A5A5A5 << 16 << 16) | 0x12345678) - -/* Bits above 31 are dropped. Compare full size_t values; WHAL_ASSERT_EQ - * cuts them to int. */ -static void Test_Reg_HighBitsDropped(void) -{ - size_t val = 0; - - ResetRegs(); - whal_Reg_Write(RegBase(), 4, REG_WIDE_VALUE); - WHAL_ASSERT_EQ(g_regs[1] == 0x12345678UL, 1); - WHAL_ASSERT_EQ(g_regs[2], SENTINEL); - WHAL_ASSERT_EQ(whal_Reg_Read(RegBase(), 4) == 0x12345678UL, 1); - g_regs[1] = 0xFFFFFFFF; - whal_Reg_Get(RegBase(), 4, (size_t)-1, 0, &val); - WHAL_ASSERT_EQ(val == 0xFFFFFFFFUL, 1); - - g_regs[1] = 0; - whal_Reg_Update(RegBase(), 4, (size_t)-1, REG_WIDE_VALUE); - WHAL_ASSERT_EQ(g_regs[1] == 0x12345678UL, 1); - WHAL_ASSERT_EQ(g_regs[0], SENTINEL); - WHAL_ASSERT_EQ(g_regs[2], SENTINEL); + g_regs64[0] = SENTINEL64; + g_regs64[1] = 0; + g_regs64[2] = SENTINEL64; } +#endif /* WHAL_HAVE_REG64 */ #ifndef WHAL_CFG_NO_TIMEOUT @@ -117,105 +72,396 @@ typedef uint32_t RegTick_t; static RegTick_t g_regTick; static RegTick_t g_regSetAt; +static void (*g_regSetFn)(void); static whal_Timeout g_regTimeout; -/* Advances on each read so a poll can time out. Sets bit 0x80 at tick - * g_regSetAt when that is not 0. */ +/* Advances on each read so a poll can time out. Calls g_regSetFn at tick + * g_regSetAt to set the polled bit. */ static RegTick_t RegTick(void) { - if (g_regSetAt != 0 && g_regTick == g_regSetAt) { - g_regs[1] |= 0x80; + if (g_regSetFn != NULL && g_regTick == g_regSetAt) { + g_regSetFn(); } return g_regTick++; } -static whal_Timeout *RegTimeout(RegTick_t setAt) +static whal_Timeout *RegTimeout(RegTick_t setAt, void (*setFn)(void)) { g_regTick = 0; g_regSetAt = setAt; + g_regSetFn = setFn; g_regTimeout.timeoutTicks = 10; g_regTimeout.GetTick = RegTick; return &g_regTimeout; } +static void SetBit32(void) +{ + g_regs[1] |= 0x80; +} + +#ifdef WHAL_HAVE_REG64 +static void SetBit64(void) +{ + g_regs64[1] |= REG64_BIT; +} +#endif + #endif /* !WHAL_CFG_NO_TIMEOUT */ -static void Test_Reg_ReadPoll(void) +/* A bounded wait, so a broken poll fails instead of hanging. NULL when + * timeouts are compiled out. */ +static whal_Timeout *Bounded(void) { - whal_Timeout *timeout = NULL; +#ifdef WHAL_CFG_NO_TIMEOUT + return NULL; +#else + return RegTimeout(0, NULL); +#endif +} +/* whal_Reg32_* */ + +static void Test_Reg32_WriteOnlyItsWord(void) +{ + ResetRegs(); + whal_Reg32_Write(RegBase(), 4, 0x12345678); + WHAL_ASSERT_EQ(g_regs[1], 0x12345678); + WHAL_ASSERT_EQ(g_regs[0], SENTINEL); + WHAL_ASSERT_EQ(g_regs[2], SENTINEL); +} + +static void Test_Reg32_ReadOnlyItsWord(void) +{ + ResetRegs(); + g_regs[1] = 0x8000BEEF; + WHAL_ASSERT_EQ(whal_Reg32_Read(RegBase(), 4) == 0x8000BEEFUL, 1); +} + +static void Test_Reg32_UpdateOnlyItsField(void) +{ + ResetRegs(); + /* Field bits start set, so the update must clear them */ + g_regs[1] = 0xFFFF00F0; + whal_Reg32_Update(RegBase(), 4, 0x000000F0, 0x00000050); + WHAL_ASSERT_EQ(g_regs[1], 0xFFFF0050); + WHAL_ASSERT_EQ(g_regs[0], SENTINEL); + WHAL_ASSERT_EQ(g_regs[2], SENTINEL); +} + +static void Test_Reg32_GetField(void) +{ + uint32_t val = 0; + + ResetRegs(); + g_regs[1] = 0xFFFFFFFF; + whal_Reg32_Get(RegBase(), 4, 0x00003C00, 10, &val); + WHAL_ASSERT_EQ(val, 0xF); + whal_Reg32_Get(RegBase(), 4, 0x80000000, 31, &val); + WHAL_ASSERT_EQ(val, 1); +} + +static void Test_Reg32_ReadPoll(void) +{ ResetRegs(); /* Bits outside the mask are set and must be ignored */ g_regs[1] = 0xFF; -#ifndef WHAL_CFG_NO_TIMEOUT - /* A bounded wait, so a broken poll fails instead of hanging */ - timeout = RegTimeout(0); -#endif - WHAL_ASSERT_EQ(whal_Reg_ReadPoll(RegBase(), 4, 0x80, 0x80, timeout), + WHAL_ASSERT_EQ(whal_Reg32_ReadPoll(RegBase(), 4, 0x80, 0x80, Bounded()), WHAL_SUCCESS); } /* Value 0 waits for the masked bits to clear */ -static void Test_Reg_ReadPollClear(void) +static void Test_Reg32_ReadPollClear(void) { - whal_Timeout *timeout = NULL; - ResetRegs(); g_regs[1] = 0x7F; -#ifndef WHAL_CFG_NO_TIMEOUT - timeout = RegTimeout(0); -#endif - WHAL_ASSERT_EQ(whal_Reg_ReadPoll(RegBase(), 4, 0x80, 0, timeout), + WHAL_ASSERT_EQ(whal_Reg32_ReadPoll(RegBase(), 4, 0x80, 0, Bounded()), WHAL_SUCCESS); } #ifndef WHAL_CFG_NO_TIMEOUT -static void Test_Reg_ReadPollRetry(void) +static void Test_Reg32_ReadPollRetry(void) { ResetRegs(); /* Bit 0x80 sets at tick 3; the other bits are already set */ g_regs[1] = 0x7F; - WHAL_ASSERT_EQ(whal_Reg_ReadPoll(RegBase(), 4, 0x80, 0x80, - RegTimeout(3)), + WHAL_ASSERT_EQ(whal_Reg32_ReadPoll(RegBase(), 4, 0x80, 0x80, + RegTimeout(3, SetBit32)), WHAL_SUCCESS); - /* The poll read the register again until the bit was set */ WHAL_ASSERT_EQ(g_regTick > 3, 1); } -static void Test_Reg_ReadPollTimeout(void) +static void Test_Reg32_ReadPollTimeout(void) { ResetRegs(); - WHAL_ASSERT_EQ(whal_Reg_ReadPoll(RegBase(), 4, 0x80, 0x80, - RegTimeout(0)), + WHAL_ASSERT_EQ(whal_Reg32_ReadPoll(RegBase(), 4, 0x80, 0x80, + RegTimeout(0, NULL)), WHAL_ETIMEOUT); } -/* A set bit never clears, so the wait for clear times out */ -static void Test_Reg_ReadPollClearTimeout(void) +static void Test_Reg32_ReadPollClearTimeout(void) { ResetRegs(); g_regs[1] = 0x80; - WHAL_ASSERT_EQ(whal_Reg_ReadPoll(RegBase(), 4, 0x80, 0, RegTimeout(0)), + WHAL_ASSERT_EQ(whal_Reg32_ReadPoll(RegBase(), 4, 0x80, 0, + RegTimeout(0, NULL)), WHAL_ETIMEOUT); } #endif /* !WHAL_CFG_NO_TIMEOUT */ +/* whal_Reg64_* */ + +#ifdef WHAL_HAVE_REG64 + +static void Test_Reg64_WriteOnlyItsWord(void) +{ + ResetRegs64(); + whal_Reg64_Write(Reg64Base(), 8, 0x0123456789ABCDEFULL); + WHAL_ASSERT_EQ(g_regs64[1] == 0x0123456789ABCDEFULL, 1); + WHAL_ASSERT_EQ(g_regs64[0] == SENTINEL64, 1); + WHAL_ASSERT_EQ(g_regs64[2] == SENTINEL64, 1); +} + +static void Test_Reg64_ReadOnlyItsWord(void) +{ + ResetRegs64(); + g_regs64[1] = 0xFEDCBA9876543210ULL; + WHAL_ASSERT_EQ(whal_Reg64_Read(Reg64Base(), 8) == 0xFEDCBA9876543210ULL, + 1); +} + +static void Test_Reg64_UpdateOnlyItsField(void) +{ + ResetRegs64(); + /* Both halves of the field start set, so the update must clear them */ + g_regs64[1] = 0xFFFFFFFFFFFF00F0ULL; + whal_Reg64_Update(Reg64Base(), 8, 0x0000FF00000000F0ULL, + 0x0000AB0000000050ULL); + WHAL_ASSERT_EQ(g_regs64[1] == 0xFFFFABFFFFFF0050ULL, 1); + WHAL_ASSERT_EQ(g_regs64[0] == SENTINEL64, 1); + WHAL_ASSERT_EQ(g_regs64[2] == SENTINEL64, 1); +} + +static void Test_Reg64_GetField(void) +{ + uint64_t val = 0; + + ResetRegs64(); + g_regs64[1] = 0xFFFFFFFFFFFFFFFFULL; + whal_Reg64_Get(Reg64Base(), 8, 0x00003C0000000000ULL, 42, &val); + WHAL_ASSERT_EQ(val == 0xF, 1); + whal_Reg64_Get(Reg64Base(), 8, 0x0000003C00000000ULL, 34, &val); + WHAL_ASSERT_EQ(val == 0xF, 1); +} + +static void Test_Reg64_ReadPoll(void) +{ + ResetRegs64(); + /* Bits outside the mask are set and must be ignored */ + g_regs64[1] = REG64_BIT | 0xFFFFFFFFULL; + WHAL_ASSERT_EQ(whal_Reg64_ReadPoll(Reg64Base(), 8, REG64_BIT, REG64_BIT, + Bounded()), + WHAL_SUCCESS); +} + +static void Test_Reg64_ReadPollClear(void) +{ + ResetRegs64(); + g_regs64[1] = ~REG64_BIT; + WHAL_ASSERT_EQ(whal_Reg64_ReadPoll(Reg64Base(), 8, REG64_BIT, 0, + Bounded()), + WHAL_SUCCESS); +} + +#ifndef WHAL_CFG_NO_TIMEOUT + +static void Test_Reg64_ReadPollRetry(void) +{ + ResetRegs64(); + /* Bit 40 sets at tick 3; the low word is already set */ + g_regs64[1] = 0xFFFFFFFFULL; + WHAL_ASSERT_EQ(whal_Reg64_ReadPoll(Reg64Base(), 8, REG64_BIT, REG64_BIT, + RegTimeout(3, SetBit64)), + WHAL_SUCCESS); + WHAL_ASSERT_EQ(g_regTick > 3, 1); +} + +static void Test_Reg64_ReadPollTimeout(void) +{ + ResetRegs64(); + WHAL_ASSERT_EQ(whal_Reg64_ReadPoll(Reg64Base(), 8, REG64_BIT, REG64_BIT, + RegTimeout(0, NULL)), + WHAL_ETIMEOUT); +} + +static void Test_Reg64_ReadPollClearTimeout(void) +{ + ResetRegs64(); + g_regs64[1] = REG64_BIT; + WHAL_ASSERT_EQ(whal_Reg64_ReadPoll(Reg64Base(), 8, REG64_BIT, 0, + RegTimeout(0, NULL)), + WHAL_ETIMEOUT); +} + +#endif /* !WHAL_CFG_NO_TIMEOUT */ + +#endif /* WHAL_HAVE_REG64 */ + +/* Legacy whal_Reg_* (WHAL_CFG_REG_LEGACY) */ + +#ifdef WHAL_CFG_REG_LEGACY + +static size_t LegacyBase(void) +{ + return (size_t)(uintptr_t)g_regs; +} + +static void Test_RegLegacy_WriteOnlyItsWord(void) +{ + ResetRegs(); + WHAL_ASSERT_EQ(whal_Reg_Write(LegacyBase(), 4, 0x12345678), + WHAL_SUCCESS); + WHAL_ASSERT_EQ(g_regs[1], 0x12345678); + WHAL_ASSERT_EQ(g_regs[0], SENTINEL); + WHAL_ASSERT_EQ(g_regs[2], SENTINEL); + /* The largest 32-bit value is accepted */ + WHAL_ASSERT_EQ(whal_Reg_Write(LegacyBase(), 4, 0xFFFFFFFFUL), + WHAL_SUCCESS); + WHAL_ASSERT_EQ(g_regs[1] == 0xFFFFFFFFUL, 1); + WHAL_ASSERT_EQ(g_regs[2], SENTINEL); +} + +static void Test_RegLegacy_ReadOnlyItsWord(void) +{ + ResetRegs(); + g_regs[1] = 0x8000BEEF; + WHAL_ASSERT_EQ(whal_Reg_Read(LegacyBase(), 4) == 0x8000BEEFUL, 1); +} + +static void Test_RegLegacy_UpdateOnlyItsField(void) +{ + ResetRegs(); + g_regs[1] = 0xFFFF00F0; + WHAL_ASSERT_EQ(whal_Reg_Update(LegacyBase(), 4, 0x000000F0, 0x00000050), + WHAL_SUCCESS); + WHAL_ASSERT_EQ(g_regs[1], 0xFFFF0050); + WHAL_ASSERT_EQ(g_regs[0], SENTINEL); + WHAL_ASSERT_EQ(g_regs[2], SENTINEL); +} + +static void Test_RegLegacy_GetField(void) +{ + size_t val = 0; + + ResetRegs(); + g_regs[1] = 0xFFFFFFFF; + WHAL_ASSERT_EQ(whal_Reg_Get(LegacyBase(), 4, 0x00003C00, 10, &val), + WHAL_SUCCESS); + WHAL_ASSERT_EQ(val, 0xF); + WHAL_ASSERT_EQ(whal_Reg_Get(LegacyBase(), 4, 0x80000000UL, 31, &val), + WHAL_SUCCESS); + WHAL_ASSERT_EQ(val, 1); +} + +static void Test_RegLegacy_ReadPoll(void) +{ + ResetRegs(); + g_regs[1] = 0x7F; + WHAL_ASSERT_EQ(whal_Reg_ReadPoll(LegacyBase(), 4, 0x80, 0, Bounded()), + WHAL_SUCCESS); + g_regs[1] = 0xFF; + WHAL_ASSERT_EQ(whal_Reg_ReadPoll(LegacyBase(), 4, 0x80, 0x80, Bounded()), + WHAL_SUCCESS); +} + +#ifndef WHAL_CFG_NO_TIMEOUT +static void Test_RegLegacy_ReadPollTimeout(void) +{ + ResetRegs(); + WHAL_ASSERT_EQ(whal_Reg_ReadPoll(LegacyBase(), 4, 0x80, 0x80, + RegTimeout(0, NULL)), + WHAL_ETIMEOUT); +} +#endif + +#if SIZE_MAX > 0xFFFFFFFFu +/* Low 32 bits are valid, so a missing check would write or match */ +#define LEGACY_WIDE (((size_t)1 << 32) | 0x80) + +static void Test_RegLegacy_WideRejected(void) +{ + size_t val = 123; + + ResetRegs(); + g_regs[1] = 0x11111111; + WHAL_ASSERT_EQ(whal_Reg_Write(LegacyBase(), 4, LEGACY_WIDE), WHAL_EINVAL); + WHAL_ASSERT_EQ(whal_Reg_Update(LegacyBase(), 4, LEGACY_WIDE, 0x80), + WHAL_EINVAL); + WHAL_ASSERT_EQ(whal_Reg_Update(LegacyBase(), 4, 0xFF, LEGACY_WIDE), + WHAL_EINVAL); + WHAL_ASSERT_EQ(g_regs[1], 0x11111111); + WHAL_ASSERT_EQ(g_regs[0], SENTINEL); + WHAL_ASSERT_EQ(g_regs[2], SENTINEL); + + WHAL_ASSERT_EQ(whal_Reg_Get(LegacyBase(), 4, LEGACY_WIDE, 0, &val), + WHAL_EINVAL); + WHAL_ASSERT_EQ(val == 0, 1); + + g_regs[1] = 0x80; + WHAL_ASSERT_EQ(whal_Reg_ReadPoll(LegacyBase(), 4, LEGACY_WIDE, 0x80, + Bounded()), + WHAL_EINVAL); + WHAL_ASSERT_EQ(whal_Reg_ReadPoll(LegacyBase(), 4, 0x80, LEGACY_WIDE, + Bounded()), + WHAL_EINVAL); +} +#endif /* SIZE_MAX > 0xFFFFFFFFu */ + +#endif /* WHAL_CFG_REG_LEGACY */ + void whal_Test_Reg(void) { WHAL_TEST_SUITE_START("reg"); - WHAL_TEST(Test_Reg_WriteOnlyItsWord); - WHAL_TEST(Test_Reg_ReadOnlyItsWord); - WHAL_TEST(Test_Reg_UpdateOnlyItsField); - WHAL_TEST(Test_Reg_GetField); - WHAL_TEST(Test_Reg_HighBitsDropped); - WHAL_TEST(Test_Reg_ReadPoll); - WHAL_TEST(Test_Reg_ReadPollClear); + WHAL_TEST(Test_Reg32_WriteOnlyItsWord); + WHAL_TEST(Test_Reg32_ReadOnlyItsWord); + WHAL_TEST(Test_Reg32_UpdateOnlyItsField); + WHAL_TEST(Test_Reg32_GetField); + WHAL_TEST(Test_Reg32_ReadPoll); + WHAL_TEST(Test_Reg32_ReadPollClear); +#ifndef WHAL_CFG_NO_TIMEOUT + WHAL_TEST(Test_Reg32_ReadPollRetry); + WHAL_TEST(Test_Reg32_ReadPollTimeout); + WHAL_TEST(Test_Reg32_ReadPollClearTimeout); +#endif + +#ifdef WHAL_HAVE_REG64 + WHAL_TEST(Test_Reg64_WriteOnlyItsWord); + WHAL_TEST(Test_Reg64_ReadOnlyItsWord); + WHAL_TEST(Test_Reg64_UpdateOnlyItsField); + WHAL_TEST(Test_Reg64_GetField); + WHAL_TEST(Test_Reg64_ReadPoll); + WHAL_TEST(Test_Reg64_ReadPollClear); #ifndef WHAL_CFG_NO_TIMEOUT - WHAL_TEST(Test_Reg_ReadPollRetry); - WHAL_TEST(Test_Reg_ReadPollTimeout); - WHAL_TEST(Test_Reg_ReadPollClearTimeout); + WHAL_TEST(Test_Reg64_ReadPollRetry); + WHAL_TEST(Test_Reg64_ReadPollTimeout); + WHAL_TEST(Test_Reg64_ReadPollClearTimeout); +#endif +#endif + +#ifdef WHAL_CFG_REG_LEGACY + WHAL_TEST(Test_RegLegacy_WriteOnlyItsWord); + WHAL_TEST(Test_RegLegacy_ReadOnlyItsWord); + WHAL_TEST(Test_RegLegacy_UpdateOnlyItsField); + WHAL_TEST(Test_RegLegacy_GetField); + WHAL_TEST(Test_RegLegacy_ReadPoll); +#ifndef WHAL_CFG_NO_TIMEOUT + WHAL_TEST(Test_RegLegacy_ReadPollTimeout); +#endif +#if SIZE_MAX > 0xFFFFFFFFu + WHAL_TEST(Test_RegLegacy_WideRejected); +#endif #endif WHAL_TEST_SUITE_END(); } diff --git a/wolfHAL/reg.h b/wolfHAL/reg.h index f978c58b..414f97cb 100644 --- a/wolfHAL/reg.h +++ b/wolfHAL/reg.h @@ -30,65 +30,203 @@ /* * @file reg.h - * @brief Helpers for accessing and manipulating memory-mapped registers. + * @brief Memory-mapped register access with an explicit width. * - * Every access is 32 bits wide, also where size_t is 64 bits. Value and - * mask bits above bit 31 are dropped. + * whal_Reg32_* access 32-bit registers, whal_Reg64_* 64-bit registers. + * The older whal_Reg_* API needs WHAL_CFG_REG_LEGACY. */ +/* 64-bit registers: only where a 64-bit access is a single access */ +#if UINTPTR_MAX > 0xFFFFFFFFu +#define WHAL_HAVE_REG64 +#endif + /* - * @brief Update a masked field within a memory-mapped register. + * @brief Write a 32-bit register. * - * The function applies a read-modify-write using @p mask to only touch the - * desired bit field. + * @param base Base address of the register block. + * @param offset Byte offset from @p base to the register. + * @param value Value to write. + */ +static inline void whal_Reg32_Write(uintptr_t base, uint32_t offset, + uint32_t value) +{ + *(volatile uint32_t *)(base + offset) = value; +} + +/* + * @brief Read a 32-bit register. * * @param base Base address of the register block. * @param offset Byte offset from @p base to the register. - * @param mask Bit mask selecting the field to update. - * @param value Value already positioned within @p mask; it is masked but - * not shifted. * - * @note No return value. Callers are responsible for passing valid inputs. + * @return The register value. */ -static inline void whal_Reg_Update(size_t base, size_t offset, size_t mask, - size_t value) +static inline uint32_t whal_Reg32_Read(uintptr_t base, uint32_t offset) { - volatile uint32_t *reg = (volatile uint32_t *)(base + offset); - *reg = (uint32_t)((*reg & ~mask) | (value & mask)); + return *(volatile uint32_t *)(base + offset); } /* - * @brief Read a masked field from a memory-mapped register. + * @brief Read-modify-write the bits in @p mask of a 32-bit register. * * @param base Base address of the register block. * @param offset Byte offset from @p base to the register. - * @param msk Bit mask selecting the field to extract. - * @param pos Bit position of the field's LSB. - * @param value Output storage for the decoded field. + * @param mask Bits to change. + * @param value New bits, already in position; bits outside @p mask are + * ignored. + */ +static inline void whal_Reg32_Update(uintptr_t base, uint32_t offset, + uint32_t mask, uint32_t value) +{ + volatile uint32_t *reg = (volatile uint32_t *)(base + offset); + *reg = (*reg & ~mask) | (value & mask); +} + +/* + * @brief Read a field of a 32-bit register. * - * @note No return value. Callers are responsible for passing valid inputs. + * @param base Base address of the register block. + * @param offset Byte offset from @p base to the register. + * @param mask Bits of the field. + * @param pos Bit position of the field's LSB, below 32. + * @param value Output for the field, shifted down to bit 0. */ -static inline void whal_Reg_Get(size_t base, size_t offset, size_t msk, - size_t pos, size_t *value) +static inline void whal_Reg32_Get(uintptr_t base, uint32_t offset, + uint32_t mask, uint32_t pos, + uint32_t *value) { - size_t val = *(volatile uint32_t *)(base + offset); - *value = whal_GetBits(msk, pos, val); + *value = whal_GetBits(mask, pos, whal_Reg32_Read(base, offset)); } /* - * @brief Write a 32-bit value to a memory-mapped register. + * @brief Poll a 32-bit register until (reg & mask) == value, or timeout. + * + * @param base Base address of the register block. + * @param offset Byte offset from @p base to the register. + * @param mask Bits to compare. + * @param value Expected bits. Must fit in @p mask, or the poll never + * matches. + * @param timeout Timeout instance (NULL for unbounded wait). + * + * @retval WHAL_SUCCESS The masked bits matched @p value. + * @retval WHAL_ETIMEOUT The timeout expired first. + */ +whal_Error whal_Reg32_ReadPoll(uintptr_t base, uint32_t offset, + uint32_t mask, uint32_t value, + whal_Timeout *timeout); + +#ifdef WHAL_HAVE_REG64 + +/* + * @brief Write a 64-bit register. * * @param base Base address of the register block. * @param offset Byte offset from @p base to the register. * @param value Value to write. */ -static inline void whal_Reg_Write(size_t base, size_t offset, size_t value) +static inline void whal_Reg64_Write(uintptr_t base, uint32_t offset, + uint64_t value) +{ + *(volatile uint64_t *)(base + offset) = value; +} + +/* + * @brief Read a 64-bit register. + * + * @param base Base address of the register block. + * @param offset Byte offset from @p base to the register. + * + * @return The register value. + */ +static inline uint64_t whal_Reg64_Read(uintptr_t base, uint32_t offset) +{ + return *(volatile uint64_t *)(base + offset); +} + +/* + * @brief Read-modify-write the bits in @p mask of a 64-bit register. + * + * @param base Base address of the register block. + * @param offset Byte offset from @p base to the register. + * @param mask Bits to change. + * @param value New bits, already in position; bits outside @p mask are + * ignored. + */ +static inline void whal_Reg64_Update(uintptr_t base, uint32_t offset, + uint64_t mask, uint64_t value) +{ + volatile uint64_t *reg = (volatile uint64_t *)(base + offset); + *reg = (*reg & ~mask) | (value & mask); +} + +/* + * @brief Read a field of a 64-bit register. + * + * @param base Base address of the register block. + * @param offset Byte offset from @p base to the register. + * @param mask Bits of the field. + * @param pos Bit position of the field's LSB, below 64. + * @param value Output for the field, shifted down to bit 0. + */ +static inline void whal_Reg64_Get(uintptr_t base, uint32_t offset, + uint64_t mask, uint32_t pos, + uint64_t *value) +{ + *value = whal_GetBits(mask, pos, whal_Reg64_Read(base, offset)); +} + +/* + * @brief Poll a 64-bit register until (reg & mask) == value, or timeout. + * + * @param base Base address of the register block. + * @param offset Byte offset from @p base to the register. + * @param mask Bits to compare. + * @param value Expected bits. Must fit in @p mask, or the poll never + * matches. + * @param timeout Timeout instance (NULL for unbounded wait). + * + * @retval WHAL_SUCCESS The masked bits matched @p value. + * @retval WHAL_ETIMEOUT The timeout expired first. + */ +whal_Error whal_Reg64_ReadPoll(uintptr_t base, uint32_t offset, + uint64_t mask, uint64_t value, + whal_Timeout *timeout); + +#endif /* WHAL_HAVE_REG64 */ + +#ifdef WHAL_CFG_REG_LEGACY + +/* Legacy whal_Reg_* API: size_t arguments, 32-bit accesses. Where size_t + * is wider, values and masks above 32 bits return WHAL_EINVAL. */ +#if SIZE_MAX > 0xFFFFFFFFu +#define WHAL_REG_FITS32(x) ((x) <= 0xFFFFFFFFu) +#else +#define WHAL_REG_FITS32(x) (1) +#endif + +/* + * @brief Legacy: write a 32-bit register. + * + * @param base Base address of the register block. + * @param offset Byte offset from @p base to the register. + * @param value Value to write; must fit in 32 bits. + * + * @retval WHAL_SUCCESS Written. + * @retval WHAL_EINVAL @p value does not fit; nothing written. + */ +static inline whal_Error whal_Reg_Write(size_t base, size_t offset, + size_t value) { - *(volatile uint32_t *)(base + offset) = (uint32_t)value; + if (!WHAL_REG_FITS32(value)) { + return WHAL_EINVAL; + } + whal_Reg32_Write(base + offset, 0, value & 0xFFFFFFFFu); + return WHAL_SUCCESS; } /* - * @brief Read a 32-bit value from a memory-mapped register. + * @brief Legacy: read a 32-bit register. * * @param base Base address of the register block. * @param offset Byte offset from @p base to the register. @@ -97,24 +235,74 @@ static inline void whal_Reg_Write(size_t base, size_t offset, size_t value) */ static inline size_t whal_Reg_Read(size_t base, size_t offset) { - return *(volatile uint32_t *)(base + offset); + return whal_Reg32_Read(base + offset, 0); +} + +/* + * @brief Legacy: read-modify-write the bits in @p mask of a 32-bit register. + * + * @param base Base address of the register block. + * @param offset Byte offset from @p base to the register. + * @param mask Bits to change; must fit in 32 bits. + * @param value New bits, already in position; must fit in 32 bits. + * + * @retval WHAL_SUCCESS Updated. + * @retval WHAL_EINVAL @p mask or @p value does not fit; nothing written. + */ +static inline whal_Error whal_Reg_Update(size_t base, size_t offset, + size_t mask, size_t value) +{ + if (!WHAL_REG_FITS32(mask) || !WHAL_REG_FITS32(value)) { + return WHAL_EINVAL; + } + whal_Reg32_Update(base + offset, 0, mask & 0xFFFFFFFFu, + value & 0xFFFFFFFFu); + return WHAL_SUCCESS; } /* - * @brief Poll a register until (reg & mask) == value, or timeout. + * @brief Legacy: read a field of a 32-bit register. * - * @param base Register block base address. - * @param offset Register offset. - * @param mask Bit mask to extract the field. - * @param value Expected value of the masked field. Must fit in @p mask - * and in 32 bits, or the poll never matches. + * @param base Base address of the register block. + * @param offset Byte offset from @p base to the register. + * @param msk Bits of the field; must fit in 32 bits. + * @param pos Bit position of the field's LSB. + * @param value Output for the field; 0 on error. + * + * @retval WHAL_SUCCESS Read. + * @retval WHAL_EINVAL @p msk does not fit. + */ +static inline whal_Error whal_Reg_Get(size_t base, size_t offset, size_t msk, + size_t pos, size_t *value) +{ + size_t reg; + + if (!WHAL_REG_FITS32(msk)) { + *value = 0; + return WHAL_EINVAL; + } + reg = whal_Reg32_Read(base + offset, 0); + *value = whal_GetBits(msk, pos, reg); + return WHAL_SUCCESS; +} + +/* + * @brief Legacy: poll a 32-bit register until (reg & mask) == value. + * + * @param base Base address of the register block. + * @param offset Byte offset from @p base to the register. + * @param mask Bits to compare; must fit in 32 bits. + * @param value Expected bits; must fit in 32 bits and in @p mask. * @param timeout Timeout instance (NULL for unbounded wait). * - * @retval WHAL_SUCCESS The masked field matched @p value. + * @retval WHAL_SUCCESS The masked bits matched @p value. * @retval WHAL_ETIMEOUT The timeout expired first. + * @retval WHAL_EINVAL @p mask or @p value does not fit. */ whal_Error whal_Reg_ReadPoll(size_t base, size_t offset, size_t mask, size_t value, whal_Timeout *timeout); +#endif /* WHAL_CFG_REG_LEGACY */ + #endif /* WHAL_REG_H */ From c41e0c33ac6cfbd98b932fb6e19cd3b24d80e97a Mon Sep 17 00:00:00 2001 From: night1rider Date: Fri, 6 Nov 2026 09:33:24 -0700 Subject: [PATCH 3/4] [reg, drivers, test, docs] Drop the legacy whal_Reg_* API Per review, keep only whal_Reg32_* and whal_Reg64_*. All drivers, board files and tests now call whal_Reg32_*. Device base fields and base locals are uintptr_t. Variables read with whal_Reg32_Get are uint32_t. --- .../skills/generate-driver-template/SKILL.md | 12 +- .claude/skills/port-stm32-platform/SKILL.md | 2 +- boards/pic32cz_curiosity_ultra/board.mk | 2 - boards/stm32c031_nucleo/board.mk | 2 - boards/stm32f091rc_nucleo/board.mk | 2 - boards/stm32f302r8_nucleo/board.mk | 2 - boards/stm32f411_blackpill/board.mk | 2 - boards/stm32h563zi_nucleo/board.mk | 2 - boards/stm32l152re_nucleo/board.mk | 2 - boards/stm32n657a0_nucleo/board.mk | 2 - boards/stm32u5a5zj_nucleo/board.mk | 2 - boards/stm32wb05kz_nucleo/board.mk | 2 - boards/stm32wb55xx_nucleo/board.mk | 2 - boards/stm32wba55cg_nucleo/board.mk | 2 - boards/stm32wba55cg_nucleo/wolfHAL_board.c | 4 +- docs/getting_started.md | 6 +- docs/writing_a_driver.md | 23 +- src/crypto/stm32n6_cryp.c | 322 +++---- src/crypto/stm32wb_aes.c | 774 ++++++++--------- src/crypto/stm32wb_pka.c | 120 +-- src/crypto/stm32wba_aes.c | 816 +++++++++--------- src/crypto/stm32wba_hash.c | 358 ++++---- src/dma/stm32wb_dma.c | 78 +- src/dma/stm32wba_gpdma.c | 78 +- src/eth/stm32h5_eth.c | 188 ++-- src/eth/stm32n6_eth.c | 204 ++--- src/flash/pic32cz_flash.c | 92 +- src/flash/stm32c0_flash.c | 72 +- src/flash/stm32f0_flash.c | 76 +- src/flash/stm32f4_flash.c | 74 +- src/flash/stm32h5_flash.c | 68 +- src/flash/stm32l1_flash.c | 116 +-- src/flash/stm32u5_flash.c | 68 +- src/flash/stm32wb0_flash.c | 60 +- src/flash/stm32wb_flash.c | 72 +- src/flash/stm32wba_flash.c | 62 +- src/gpio/pic32cz_gpio.c | 56 +- src/gpio/stm32wb0_gpio.c | 36 +- src/gpio/stm32wb_gpio.c | 36 +- src/i2c/stm32l1_i2c.c | 120 +-- src/i2c/stm32wb_i2c.c | 96 +-- src/irq/cortex_m4_nvic.c | 12 +- src/pwm/stm32wb_lptim_pwm.c | 50 +- src/reg.c | 13 - src/rng/stm32h5_rng.c | 32 +- src/rng/stm32wb0_rng.c | 18 +- src/rng/stm32wb_rng.c | 16 +- src/rng/stm32wba_rng.c | 28 +- src/spi/stm32f4_spi.c | 72 +- src/spi/stm32h5_spi.c | 94 +- src/spi/stm32wb_spi.c | 82 +- src/timer/systick.c | 34 +- src/uart/pic32cz_uart.c | 144 ++-- src/uart/stm32f0_uart.c | 66 +- src/uart/stm32f4_uart.c | 72 +- src/uart/stm32wb_uart.c | 76 +- src/uart/stm32wb_uart_dma.c | 44 +- src/uart/stm32wba_uart_dma.c | 46 +- src/watchdog/stm32f0_wwdg.c | 14 +- src/watchdog/stm32wb_iwdg.c | 20 +- src/watchdog/stm32wb_wwdg.c | 20 +- tests/clock/test_pic32cz_clock.c | 26 +- tests/clock/test_stm32wb_clock.c | 10 +- tests/core/Makefile | 18 +- tests/core/test_reg.c | 126 --- tests/crypto/test_stm32wba_hmac_sha256.c | 20 +- tests/dma/test_stm32wb_dma.c | 46 +- tests/eth/test_stm32n6_eth.c | 28 +- tests/flash/test_flash.c | 6 +- tests/flash/test_stm32wb_flash.c | 6 +- tests/gpio/test_pic32cz_gpio.c | 42 +- tests/gpio/test_stm32wb0_gpio.c | 30 +- tests/gpio/test_stm32wb_gpio.c | 46 +- tests/i2c/test_stm32wb_i2c.c | 12 +- tests/timer/test_stm32wb_timer.c | 18 +- wolfHAL/block/block.h | 2 +- wolfHAL/clock/pic32cz_clock.h | 140 +-- wolfHAL/clock/stm32c0_rcc.h | 46 +- wolfHAL/clock/stm32f0_rcc.h | 86 +- wolfHAL/clock/stm32f3_rcc.h | 96 +-- wolfHAL/clock/stm32f4_rcc.h | 94 +- wolfHAL/clock/stm32h5_rcc.h | 128 +-- wolfHAL/clock/stm32l1_rcc.h | 92 +- wolfHAL/clock/stm32n6_rcc.h | 122 +-- wolfHAL/clock/stm32u5_rcc.h | 166 ++-- wolfHAL/clock/stm32wb0_rcc.h | 94 +- wolfHAL/clock/stm32wb_rcc.h | 106 +-- wolfHAL/clock/stm32wba_rcc.h | 136 +-- wolfHAL/crypto/crypto.h | 2 +- wolfHAL/dma/dma.h | 3 +- wolfHAL/dma/stm32wb_dma.h | 2 +- wolfHAL/eth/eth.h | 2 +- wolfHAL/flash/flash.h | 2 +- wolfHAL/gpio/gpio.h | 3 +- wolfHAL/i2c/i2c.h | 2 +- wolfHAL/ipc/ipc.h | 2 +- wolfHAL/irq/irq.h | 3 +- wolfHAL/power/pic32cz_supc.h | 12 +- wolfHAL/power/stm32l1_pwr.h | 16 +- wolfHAL/pwm/pwm.h | 2 +- wolfHAL/reg.h | 111 --- wolfHAL/rng/rng.h | 2 +- wolfHAL/spi/spi.h | 2 +- wolfHAL/timer/timer.h | 3 +- wolfHAL/uart/uart.h | 2 +- wolfHAL/watchdog/watchdog.h | 2 +- 106 files changed, 3345 insertions(+), 3636 deletions(-) diff --git a/.claude/skills/generate-driver-template/SKILL.md b/.claude/skills/generate-driver-template/SKILL.md index 2df55236..b47a29a3 100644 --- a/.claude/skills/generate-driver-template/SKILL.md +++ b/.claude/skills/generate-driver-template/SKILL.md @@ -245,7 +245,7 @@ constness to the generic struct's `cfg` field. ```c whal_Error whal___() { - size_t base = whal___Dev.base; + uintptr_t base = whal___Dev.base; whal___Cfg *cfg = (whal___Cfg *)whal___Dev.cfg; (void); @@ -267,12 +267,12 @@ the pointer, the default branch validates the pointer and reads base/cfg from it whal_Error whal___() { #ifdef WHAL_CFG___SINGLE_INSTANCE - size_t base = whal___Dev.base; + uintptr_t base = whal___Dev.base; whal___Cfg *cfg = (whal___Cfg *)whal___Dev.cfg; (void); #else - size_t base; + uintptr_t base; whal___Cfg *cfg; if (! || !->cfg) @@ -296,7 +296,7 @@ Notes for the bodies: trailing `/* validate the remaining args */` line — there is nothing else to check. - Keep `(void)base;` / `(void)cfg;` so the stub compiles with `-Werror` before the bodies are filled in. Remove them as soon as `base`/`cfg` get used. -- Add a `whal_Timeout`-based wait (`WHAL_TIMEOUT_*` or `whal_Reg_ReadPoll`) wherever the real +- Add a `whal_Timeout`-based wait (`WHAL_TIMEOUT_*` or `whal_Reg32_ReadPoll`) wherever the real implementation will poll hardware — never a bare `while`. Leave a TODO noting it. --- @@ -379,9 +379,9 @@ takes **`void`** (so the header compiles before any structs/enums are defined), static inline whal_Error whal___Enable(void) { /* TODO: implement — write WHAL___BASE registers via - * whal_Reg_Update / whal_Reg_Get. Poll any ready bit before returning. + * whal_Reg32_Update / whal_Reg32_Get. Poll any ready bit before returning. * Clock bring-up runs before the system timer, so a bare do/while on the - * ready bit is acceptable there; elsewhere prefer whal_Reg_ReadPoll with a + * ready bit is acceptable there; elsewhere prefer whal_Reg32_ReadPoll with a * whal_Timeout. */ return WHAL_SUCCESS; } diff --git a/.claude/skills/port-stm32-platform/SKILL.md b/.claude/skills/port-stm32-platform/SKILL.md index e0dda075..5a09cea0 100644 --- a/.claude/skills/port-stm32-platform/SKILL.md +++ b/.claude/skills/port-stm32-platform/SKILL.md @@ -332,7 +332,7 @@ Add the new board to `.github/workflows/boards.yml` by appending it to the `boar - Missing symbol for an aliased driver → the alias header is missing a `#define` for that function/type, or the stub `.c` isn't present. - `'whal_Stm32__Dev' undeclared` in a single-instance leaf driver → the alias header for the new platform is missing the `#define whal_Stm32__Dev whal_Stm32__Dev` line, OR the wolfHAL_board.h didn't provide `WHAL_CFG_STM32__DEV` (the leaf `.c` defines the singleton from that name). - Duplicate symbol → the Makefile is picking up both `_*.c` and the original `_*.c`; restrict the wildcard to the new prefix only. - - Implicit declaration warnings for `whal_Reg_*` / `whal_SetBits` in a stub include → you probably wrote `#include ` with angle brackets in the stub instead of `#include "_.c"` with quotes. The stub must use quoted include so the preprocessor finds the sibling `.c` in the same directory. + - Implicit declaration warnings for `whal_Reg32_*` / `whal_SetBits` in a stub include → you probably wrote `#include ` with angle brackets in the stub instead of `#include "_.c"` with quotes. The stub must use quoted include so the preprocessor finds the sibling `.c` in the same directory. 2. Flash the binary (user runs this) and run the test suite. Each suite prints `PASS`, `FAIL`, or `SKIP`. 3. If UART output is garbled or missing bytes and the chip uses DMA, enable `CR1.FIFOEN` in the UART init before chasing further — DMA→USART without FIFO has caused byte drops on WBA. diff --git a/boards/pic32cz_curiosity_ultra/board.mk b/boards/pic32cz_curiosity_ultra/board.mk index 3865566b..929481ee 100644 --- a/boards/pic32cz_curiosity_ultra/board.mk +++ b/boards/pic32cz_curiosity_ultra/board.mk @@ -28,8 +28,6 @@ GCC = $(GCC_PATH)arm-none-eabi-gcc LD = $(GCC_PATH)arm-none-eabi-ld OBJCOPY = $(GCC_PATH)arm-none-eabi-objcopy -# Drivers here use the legacy whal_Reg_* API -CFLAGS += -DWHAL_CFG_REG_LEGACY CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -ffreestanding -nostdlib -mcpu=cortex-m7 \ -DPLATFORM_PIC32CZ -MMD -MP \ diff --git a/boards/stm32c031_nucleo/board.mk b/boards/stm32c031_nucleo/board.mk index d93e758e..48df459b 100644 --- a/boards/stm32c031_nucleo/board.mk +++ b/boards/stm32c031_nucleo/board.mk @@ -28,8 +28,6 @@ GCC = $(GCC_PATH)arm-none-eabi-gcc LD = $(GCC_PATH)arm-none-eabi-gcc OBJCOPY = $(GCC_PATH)arm-none-eabi-objcopy -# Drivers here use the legacy whal_Reg_* API -CFLAGS += -DWHAL_CFG_REG_LEGACY CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -ffreestanding -nostdlib -mcpu=cortex-m0plus -mthumb \ -DPLATFORM_STM32C0 -MMD -MP \ diff --git a/boards/stm32f091rc_nucleo/board.mk b/boards/stm32f091rc_nucleo/board.mk index f54d84fa..294ab717 100644 --- a/boards/stm32f091rc_nucleo/board.mk +++ b/boards/stm32f091rc_nucleo/board.mk @@ -28,8 +28,6 @@ GCC = $(GCC_PATH)arm-none-eabi-gcc LD = $(GCC_PATH)arm-none-eabi-gcc OBJCOPY = $(GCC_PATH)arm-none-eabi-objcopy -# Drivers here use the legacy whal_Reg_* API -CFLAGS += -DWHAL_CFG_REG_LEGACY CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -ffreestanding -nostdlib -mcpu=cortex-m0 -mthumb \ -DPLATFORM_STM32F0 -MMD -MP \ diff --git a/boards/stm32f302r8_nucleo/board.mk b/boards/stm32f302r8_nucleo/board.mk index f3995a6f..ebbccd11 100644 --- a/boards/stm32f302r8_nucleo/board.mk +++ b/boards/stm32f302r8_nucleo/board.mk @@ -28,8 +28,6 @@ GCC = $(GCC_PATH)arm-none-eabi-gcc LD = $(GCC_PATH)arm-none-eabi-gcc OBJCOPY = $(GCC_PATH)arm-none-eabi-objcopy -# Drivers here use the legacy whal_Reg_* API -CFLAGS += -DWHAL_CFG_REG_LEGACY CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -ffreestanding -nostdlib \ -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 \ diff --git a/boards/stm32f411_blackpill/board.mk b/boards/stm32f411_blackpill/board.mk index 5d7aecb2..a3e6fe26 100644 --- a/boards/stm32f411_blackpill/board.mk +++ b/boards/stm32f411_blackpill/board.mk @@ -28,8 +28,6 @@ GCC = $(GCC_PATH)arm-none-eabi-gcc LD = $(GCC_PATH)arm-none-eabi-ld OBJCOPY = $(GCC_PATH)arm-none-eabi-objcopy -# Drivers here use the legacy whal_Reg_* API -CFLAGS += -DWHAL_CFG_REG_LEGACY CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -ffreestanding -nostdlib -mcpu=cortex-m4 -mfloat-abi=hard \ -mfpu=fpv4-sp-d16 -mthumb \ diff --git a/boards/stm32h563zi_nucleo/board.mk b/boards/stm32h563zi_nucleo/board.mk index 3f0b78ff..9564bfdc 100644 --- a/boards/stm32h563zi_nucleo/board.mk +++ b/boards/stm32h563zi_nucleo/board.mk @@ -28,8 +28,6 @@ GCC = $(GCC_PATH)arm-none-eabi-gcc LD = $(GCC_PATH)arm-none-eabi-ld OBJCOPY = $(GCC_PATH)arm-none-eabi-objcopy -# Drivers here use the legacy whal_Reg_* API -CFLAGS += -DWHAL_CFG_REG_LEGACY CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -ffreestanding -nostdlib -mcpu=cortex-m33 \ -DPLATFORM_STM32H5 -MMD -MP \ diff --git a/boards/stm32l152re_nucleo/board.mk b/boards/stm32l152re_nucleo/board.mk index 9b345c03..205c17f6 100644 --- a/boards/stm32l152re_nucleo/board.mk +++ b/boards/stm32l152re_nucleo/board.mk @@ -28,8 +28,6 @@ GCC = $(GCC_PATH)arm-none-eabi-gcc LD = $(GCC_PATH)arm-none-eabi-gcc OBJCOPY = $(GCC_PATH)arm-none-eabi-objcopy -# Drivers here use the legacy whal_Reg_* API -CFLAGS += -DWHAL_CFG_REG_LEGACY CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -ffreestanding -nostdlib \ -mcpu=cortex-m3 -mthumb \ diff --git a/boards/stm32n657a0_nucleo/board.mk b/boards/stm32n657a0_nucleo/board.mk index b7bd60a9..4484f405 100644 --- a/boards/stm32n657a0_nucleo/board.mk +++ b/boards/stm32n657a0_nucleo/board.mk @@ -28,8 +28,6 @@ GCC = $(GCC_PATH)arm-none-eabi-gcc LD = $(GCC_PATH)arm-none-eabi-ld OBJCOPY = $(GCC_PATH)arm-none-eabi-objcopy -# Drivers here use the legacy whal_Reg_* API -CFLAGS += -DWHAL_CFG_REG_LEGACY CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -ffreestanding -nostdlib -mcpu=cortex-m55 -mthumb \ -DPLATFORM_STM32N6 -MMD -MP \ diff --git a/boards/stm32u5a5zj_nucleo/board.mk b/boards/stm32u5a5zj_nucleo/board.mk index b3e00662..4aea426f 100644 --- a/boards/stm32u5a5zj_nucleo/board.mk +++ b/boards/stm32u5a5zj_nucleo/board.mk @@ -28,8 +28,6 @@ GCC = $(GCC_PATH)arm-none-eabi-gcc LD = $(GCC_PATH)arm-none-eabi-ld OBJCOPY = $(GCC_PATH)arm-none-eabi-objcopy -# Drivers here use the legacy whal_Reg_* API -CFLAGS += -DWHAL_CFG_REG_LEGACY CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -ffreestanding -nostdlib -mcpu=cortex-m33 -mthumb \ -DPLATFORM_STM32U5 -MMD -MP \ diff --git a/boards/stm32wb05kz_nucleo/board.mk b/boards/stm32wb05kz_nucleo/board.mk index 930b8bd9..0a54348e 100644 --- a/boards/stm32wb05kz_nucleo/board.mk +++ b/boards/stm32wb05kz_nucleo/board.mk @@ -28,8 +28,6 @@ GCC = $(GCC_PATH)arm-none-eabi-gcc LD = $(GCC_PATH)arm-none-eabi-gcc OBJCOPY = $(GCC_PATH)arm-none-eabi-objcopy -# Drivers here use the legacy whal_Reg_* API -CFLAGS += -DWHAL_CFG_REG_LEGACY CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -ffreestanding -nostdlib -mcpu=cortex-m0plus -mthumb \ -DPLATFORM_STM32WB0 -MMD -MP \ diff --git a/boards/stm32wb55xx_nucleo/board.mk b/boards/stm32wb55xx_nucleo/board.mk index a96a0303..c65dc0a9 100644 --- a/boards/stm32wb55xx_nucleo/board.mk +++ b/boards/stm32wb55xx_nucleo/board.mk @@ -28,8 +28,6 @@ GCC = $(GCC_PATH)arm-none-eabi-gcc LD = $(GCC_PATH)arm-none-eabi-ld OBJCOPY = $(GCC_PATH)arm-none-eabi-objcopy -# Drivers here use the legacy whal_Reg_* API -CFLAGS += -DWHAL_CFG_REG_LEGACY CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -ffreestanding -nostdlib -mcpu=cortex-m4 \ -DPLATFORM_STM32WB -MMD -MP \ diff --git a/boards/stm32wba55cg_nucleo/board.mk b/boards/stm32wba55cg_nucleo/board.mk index 9d07d4eb..91158415 100644 --- a/boards/stm32wba55cg_nucleo/board.mk +++ b/boards/stm32wba55cg_nucleo/board.mk @@ -28,8 +28,6 @@ GCC = $(GCC_PATH)arm-none-eabi-gcc LD = $(GCC_PATH)arm-none-eabi-ld OBJCOPY = $(GCC_PATH)arm-none-eabi-objcopy -# Drivers here use the legacy whal_Reg_* API -CFLAGS += -DWHAL_CFG_REG_LEGACY CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -ffreestanding -nostdlib -mcpu=cortex-m33 -mthumb \ -DPLATFORM_STM32WBA -MMD -MP \ diff --git a/boards/stm32wba55cg_nucleo/wolfHAL_board.c b/boards/stm32wba55cg_nucleo/wolfHAL_board.c index b58ffac6..126a4a7f 100644 --- a/boards/stm32wba55cg_nucleo/wolfHAL_board.c +++ b/boards/stm32wba55cg_nucleo/wolfHAL_board.c @@ -212,10 +212,10 @@ void Board_WaitMs(size_t ms) static whal_Error Board_SetVosRange1(void) { /* Set VOS to Range 1 */ - whal_Reg_Update(PWR_BASE, PWR_VOSR_REG, PWR_VOSR_VOS_Msk, PWR_VOSR_VOS_Msk); + whal_Reg32_Update(PWR_BASE, PWR_VOSR_REG, PWR_VOSR_VOS_Msk, PWR_VOSR_VOS_Msk); /* Wait for VOSRDY */ - while (!(whal_Reg_Read(PWR_BASE, PWR_VOSR_REG) & PWR_VOSR_VOSRDY_Msk)) + while (!(whal_Reg32_Read(PWR_BASE, PWR_VOSR_REG) & PWR_VOSR_VOSRDY_Msk)) ; return WHAL_SUCCESS; diff --git a/docs/getting_started.md b/docs/getting_started.md index 56a10e31..c4df2186 100644 --- a/docs/getting_started.md +++ b/docs/getting_started.md @@ -53,7 +53,7 @@ Most device types share the same three fields in their struct - `.cfg` — driver-specific configuration settings (pins, baud rate, etc.). ```c struct whal_Uart { - const size_t base; /* register block address */ + const uintptr_t base; /* register block address */ const whal_UartDriver *driver; /* driver vtable */ void *cfg; /* driver-specific config */ }; @@ -95,7 +95,7 @@ from the device handle the caller passes in: ```c whal_Error whal_Stm32wb_Uart_Send(whal_Uart *dev, ...) { - size_t base = dev->base; + uintptr_t base = dev->base; whal_Stm32wb_Uart_Cfg *cfg = (whal_Stm32wb_Uart_Cfg *)dev->cfg; /* ... */ } @@ -114,7 +114,7 @@ const whal_Rng whal_Stm32wb_Rng_Dev = WHAL_CFG_STM32WB_RNG_DEV; whal_Error whal_Stm32wb_Rng_Generate(whal_Rng *dev, ...) { - size_t base = whal_Stm32wb_Rng_Dev.base; + uintptr_t base = whal_Stm32wb_Rng_Dev.base; (void)dev; /* ... */ } diff --git a/docs/writing_a_driver.md b/docs/writing_a_driver.md index 926c31ca..9fbabad6 100644 --- a/docs/writing_a_driver.md +++ b/docs/writing_a_driver.md @@ -156,7 +156,7 @@ whal_Error whal_Myplatform_Uart_Init(whal_Uart *uartDev) { const whal_Myplatform_Uart_Cfg *cfg = (const whal_Myplatform_Uart_Cfg *)whal_Myplatform_Uart_Dev.cfg; - size_t base = whal_Myplatform_Uart_Dev.base; + uintptr_t base = whal_Myplatform_Uart_Dev.base; (void)uartDev; /* ... */ } @@ -177,7 +177,7 @@ whal_Error whal_Myplatform_Uart_Init(whal_Uart *uartDev) { const whal_Myplatform_Uart_Cfg *cfg = (const whal_Myplatform_Uart_Cfg *)uartDev->cfg; - size_t base = uartDev->base; + uintptr_t base = uartDev->base; /* ... */ } ``` @@ -204,7 +204,7 @@ const whal_Uart whal_Myplatform_Uart_Dev = WHAL_CFG_MYPLATFORM_UART_DEV; whal_Error whal_Myplatform_Uart_Init(whal_Uart *uartDev) { const whal_Myplatform_Uart_Cfg *cfg; - size_t base; + uintptr_t base; #ifdef WHAL_CFG_MYPLATFORM_UART_SINGLE_INSTANCE cfg = (const whal_Myplatform_Uart_Cfg *)whal_Myplatform_Uart_Dev.cfg; base = whal_Myplatform_Uart_Dev.base; @@ -261,19 +261,6 @@ whal_Reg32_Get(base, UART_FR_REG, UART_FR_CNT_Msk, UART_FR_CNT_Pos, The base is a `uintptr_t` and the offset a `uint32_t`. -#### Legacy whal_Reg_* API - -The older `whal_Reg_Write`, `whal_Reg_Read`, `whal_Reg_Update`, -`whal_Reg_Get` and `whal_Reg_ReadPoll` take `size_t` arguments. They are -only available when `WHAL_CFG_REG_LEGACY` is defined, and do 32-bit -accesses through `whal_Reg32_*`. Where `size_t` is wider than 32 bits, a -value or mask above bit 31 returns `WHAL_EINVAL` and nothing is written. -`Write`, `Update` and `Get` return `whal_Error`. - -The boards in `boards/` define `WHAL_CFG_REG_LEGACY` because the existing -drivers still use this API. New drivers should use `whal_Reg32_*` / -`whal_Reg64_*`. - ### Timeouts Most drivers poll hardware status registers in busy-wait loops (e.g., waiting @@ -1153,7 +1140,7 @@ in the dispatch path. ```c struct whal_Crypto { - const size_t base; + const uintptr_t base; const whal_CryptoDriver *driver; const void *cfg; }; @@ -1468,7 +1455,7 @@ whal_Error whal_Myplatform_AesGcm_Oneshot(whal_AesGcm *dev, const void *in, void *out, size_t sz, void *tag, size_t tagSz) { - size_t base = dev->crypto->base; + uintptr_t base = dev->crypto->base; whal_Myplatform_Aes_Cfg *cfg = (whal_Myplatform_Aes_Cfg *)dev->crypto->cfg; /* Load key, IV, process AAD, encrypt/decrypt, compute tag */ diff --git a/src/crypto/stm32n6_cryp.c b/src/crypto/stm32n6_cryp.c index 9156d629..685d9b71 100644 --- a/src/crypto/stm32n6_cryp.c +++ b/src/crypto/stm32n6_cryp.c @@ -123,42 +123,42 @@ const whal_AesCcm whal_Stm32n6_CrypCcm_Dev = WHAL_CFG_STM32N6_CRYP_CCM_DEV; static whal_Stm32n6_AesGcm_State g_aesGcmState; static whal_Stm32n6_AesCcm_State g_aesCcmState; -static whal_Error WaitKeyValid(size_t base, whal_Timeout *timeout) +static whal_Error WaitKeyValid(uintptr_t base, whal_Timeout *timeout) { - return whal_Reg_ReadPoll(base, CRYP_SR_REG, CRYP_SR_KEYVALID_Msk, - CRYP_SR_KEYVALID_Msk, timeout); + return whal_Reg32_ReadPoll(base, CRYP_SR_REG, CRYP_SR_KEYVALID_Msk, + CRYP_SR_KEYVALID_Msk, timeout); } -static whal_Error WaitBusyClear(size_t base, whal_Timeout *timeout) +static whal_Error WaitBusyClear(uintptr_t base, whal_Timeout *timeout) { - return whal_Reg_ReadPoll(base, CRYP_SR_REG, CRYP_SR_BUSY_Msk, 0, timeout); + return whal_Reg32_ReadPoll(base, CRYP_SR_REG, CRYP_SR_BUSY_Msk, 0, timeout); } -static whal_Error WaitCrypEnClear(size_t base, whal_Timeout *timeout) +static whal_Error WaitCrypEnClear(uintptr_t base, whal_Timeout *timeout) { - return whal_Reg_ReadPoll(base, CRYP_CR_REG, CRYP_CR_CRYPEN_Msk, 0, timeout); + return whal_Reg32_ReadPoll(base, CRYP_CR_REG, CRYP_CR_CRYPEN_Msk, 0, timeout); } -static whal_Error WaitOutputReady(size_t base, whal_Timeout *timeout) +static whal_Error WaitOutputReady(uintptr_t base, whal_Timeout *timeout) { - return whal_Reg_ReadPoll(base, CRYP_SR_REG, CRYP_SR_OFNE_Msk, - CRYP_SR_OFNE_Msk, timeout); + return whal_Reg32_ReadPoll(base, CRYP_SR_REG, CRYP_SR_OFNE_Msk, + CRYP_SR_OFNE_Msk, timeout); } -static void DisableAndFlush(size_t base) +static void DisableAndFlush(uintptr_t base) { - whal_Reg_Update(base, CRYP_CR_REG, CRYP_CR_CRYPEN_Msk, 0); - whal_Reg_Update(base, CRYP_CR_REG, CRYP_CR_FFLUSH_Msk, CRYP_CR_FFLUSH_Msk); + whal_Reg32_Update(base, CRYP_CR_REG, CRYP_CR_CRYPEN_Msk, 0); + whal_Reg32_Update(base, CRYP_CR_REG, CRYP_CR_FFLUSH_Msk, CRYP_CR_FFLUSH_Msk); } -static void Enable(size_t base) +static void Enable(uintptr_t base) { - whal_Reg_Update(base, CRYP_CR_REG, CRYP_CR_CRYPEN_Msk, CRYP_CR_CRYPEN_Msk); + whal_Reg32_Update(base, CRYP_CR_REG, CRYP_CR_CRYPEN_Msk, CRYP_CR_CRYPEN_Msk); } -static void Disable(size_t base) +static void Disable(uintptr_t base) { - whal_Reg_Update(base, CRYP_CR_REG, CRYP_CR_CRYPEN_Msk, 0); + whal_Reg32_Update(base, CRYP_CR_REG, CRYP_CR_CRYPEN_Msk, 0); } /* @@ -166,56 +166,56 @@ static void Disable(size_t base) * hardware key scheduler: high-order 32-bit words first, descending into the * low 32 bits (K3RR last). The key is read big-endian from the input buffer. */ -static void WriteKey(size_t base, const uint8_t *key, size_t keySz) +static void WriteKey(uintptr_t base, const uint8_t *key, size_t keySz) { const uint8_t *k = key; if (keySz == 32) { - whal_Reg_Write(base, CRYP_K0LR_REG, whal_LoadBe32(k)); - whal_Reg_Write(base, CRYP_K0RR_REG, whal_LoadBe32(k + 4)); - whal_Reg_Write(base, CRYP_K1LR_REG, whal_LoadBe32(k + 8)); - whal_Reg_Write(base, CRYP_K1RR_REG, whal_LoadBe32(k + 12)); + whal_Reg32_Write(base, CRYP_K0LR_REG, whal_LoadBe32(k)); + whal_Reg32_Write(base, CRYP_K0RR_REG, whal_LoadBe32(k + 4)); + whal_Reg32_Write(base, CRYP_K1LR_REG, whal_LoadBe32(k + 8)); + whal_Reg32_Write(base, CRYP_K1RR_REG, whal_LoadBe32(k + 12)); k += 16; } else if (keySz == 24) { - whal_Reg_Write(base, CRYP_K1LR_REG, whal_LoadBe32(k)); - whal_Reg_Write(base, CRYP_K1RR_REG, whal_LoadBe32(k + 4)); + whal_Reg32_Write(base, CRYP_K1LR_REG, whal_LoadBe32(k)); + whal_Reg32_Write(base, CRYP_K1RR_REG, whal_LoadBe32(k + 4)); k += 8; } - whal_Reg_Write(base, CRYP_K2LR_REG, whal_LoadBe32(k)); - whal_Reg_Write(base, CRYP_K2RR_REG, whal_LoadBe32(k + 4)); - whal_Reg_Write(base, CRYP_K3LR_REG, whal_LoadBe32(k + 8)); - whal_Reg_Write(base, CRYP_K3RR_REG, whal_LoadBe32(k + 12)); + whal_Reg32_Write(base, CRYP_K2LR_REG, whal_LoadBe32(k)); + whal_Reg32_Write(base, CRYP_K2RR_REG, whal_LoadBe32(k + 4)); + whal_Reg32_Write(base, CRYP_K3LR_REG, whal_LoadBe32(k + 8)); + whal_Reg32_Write(base, CRYP_K3RR_REG, whal_LoadBe32(k + 12)); } -static void WriteIv16(size_t base, const uint8_t *iv) +static void WriteIv16(uintptr_t base, const uint8_t *iv) { - whal_Reg_Write(base, CRYP_IV0LR_REG, whal_LoadBe32(iv)); - whal_Reg_Write(base, CRYP_IV0RR_REG, whal_LoadBe32(iv + 4)); - whal_Reg_Write(base, CRYP_IV1LR_REG, whal_LoadBe32(iv + 8)); - whal_Reg_Write(base, CRYP_IV1RR_REG, whal_LoadBe32(iv + 12)); + whal_Reg32_Write(base, CRYP_IV0LR_REG, whal_LoadBe32(iv)); + whal_Reg32_Write(base, CRYP_IV0RR_REG, whal_LoadBe32(iv + 4)); + whal_Reg32_Write(base, CRYP_IV1LR_REG, whal_LoadBe32(iv + 8)); + whal_Reg32_Write(base, CRYP_IV1RR_REG, whal_LoadBe32(iv + 12)); } /* Reset CRYP to clear its FIFOs, key, IV and configuration. */ -static void ResetCryp(size_t base) +static void ResetCryp(uintptr_t base) { - whal_Reg_Update(base, CRYP_CR_REG, CRYP_CR_IPRST_Msk, CRYP_CR_IPRST_Msk); - whal_Reg_Update(base, CRYP_CR_REG, CRYP_CR_IPRST_Msk, 0); + whal_Reg32_Update(base, CRYP_CR_REG, CRYP_CR_IPRST_Msk, CRYP_CR_IPRST_Msk); + whal_Reg32_Update(base, CRYP_CR_REG, CRYP_CR_IPRST_Msk, 0); } -static void WriteBlock(size_t base, const uint8_t *in) +static void WriteBlock(uintptr_t base, const uint8_t *in) { - whal_Reg_Write(base, CRYP_DINR_REG, whal_LoadBe32(in)); - whal_Reg_Write(base, CRYP_DINR_REG, whal_LoadBe32(in + 4)); - whal_Reg_Write(base, CRYP_DINR_REG, whal_LoadBe32(in + 8)); - whal_Reg_Write(base, CRYP_DINR_REG, whal_LoadBe32(in + 12)); + whal_Reg32_Write(base, CRYP_DINR_REG, whal_LoadBe32(in)); + whal_Reg32_Write(base, CRYP_DINR_REG, whal_LoadBe32(in + 4)); + whal_Reg32_Write(base, CRYP_DINR_REG, whal_LoadBe32(in + 8)); + whal_Reg32_Write(base, CRYP_DINR_REG, whal_LoadBe32(in + 12)); } -static void ReadBlock(size_t base, uint8_t *out) +static void ReadBlock(uintptr_t base, uint8_t *out) { - whal_StoreBe32(out, whal_Reg_Read(base, CRYP_DOUTR_REG)); - whal_StoreBe32(out + 4, whal_Reg_Read(base, CRYP_DOUTR_REG)); - whal_StoreBe32(out + 8, whal_Reg_Read(base, CRYP_DOUTR_REG)); - whal_StoreBe32(out + 12, whal_Reg_Read(base, CRYP_DOUTR_REG)); + whal_StoreBe32(out, whal_Reg32_Read(base, CRYP_DOUTR_REG)); + whal_StoreBe32(out + 4, whal_Reg32_Read(base, CRYP_DOUTR_REG)); + whal_StoreBe32(out + 8, whal_Reg32_Read(base, CRYP_DOUTR_REG)); + whal_StoreBe32(out + 12, whal_Reg32_Read(base, CRYP_DOUTR_REG)); } /* @@ -223,7 +223,7 @@ static void ReadBlock(size_t base, uint8_t *out) * the requested ALGOMODE/ALGODIR/KEYSIZE/KMOD/PHASE/NPBLB. CRYPEN/FFLUSH/IPRST * are left untouched. */ -static void ConfigureMode(size_t base, uint32_t algoMode, uint32_t algoDir, +static void ConfigureMode(uintptr_t base, uint32_t algoMode, uint32_t algoDir, uint32_t keySize, uint32_t phase, uint32_t npblb, uint32_t kmod) { @@ -241,7 +241,7 @@ static void ConfigureMode(size_t base, uint32_t algoMode, uint32_t algoDir, whal_SetBits(CRYP_CR_NPBLB_Msk, CRYP_CR_NPBLB_Pos, npblb) | whal_SetBits(CRYP_CR_KMOD_Msk, CRYP_CR_KMOD_Pos, kmod); - whal_Reg_Update(base, CRYP_CR_REG, mask, value); + whal_Reg32_Update(base, CRYP_CR_REG, mask, value); } static whal_Error KeySizeBits(size_t keySz, uint32_t *out) @@ -263,7 +263,7 @@ static whal_Error KeySizeBits(size_t keySz, uint32_t *out) * an ECB or CBC decryption: the hardware computes the last round key, then * auto-clears CRYPEN. Caller must hold the timeout and have keys staged. */ -static whal_Error PrepareDecryptionKey(size_t base, const uint8_t *key, +static whal_Error PrepareDecryptionKey(uintptr_t base, const uint8_t *key, size_t keySz, uint32_t keySizeBits, whal_Timeout *timeout) { @@ -284,7 +284,7 @@ static whal_Error Process_BlockCipher(const uint8_t *in, uint8_t *out, size_t sz { const whal_Stm32n6_Cryp_Cfg *cfg = (const whal_Stm32n6_Cryp_Cfg *)whal_Stm32n6_Cryp_Dev.cfg; - size_t base = whal_Stm32n6_Cryp_Dev.base; + uintptr_t base = whal_Stm32n6_Cryp_Dev.base; whal_Error err; size_t i; @@ -311,7 +311,7 @@ static whal_Error Process_BlockCipher(const uint8_t *in, uint8_t *out, size_t sz static whal_Error Stop_BlockCipher(void) { - size_t base = whal_Stm32n6_Cryp_Dev.base; + uintptr_t base = whal_Stm32n6_Cryp_Dev.base; ResetCryp(base); return WHAL_SUCCESS; @@ -390,7 +390,7 @@ whal_Error whal_Stm32n6_CrypAesEcb_Oneshot(whal_AesEcb *dev, { const whal_Stm32n6_Cryp_Cfg *cfg = (const whal_Stm32n6_Cryp_Cfg *)whal_Stm32n6_Cryp_Dev.cfg; - size_t base = whal_Stm32n6_Cryp_Dev.base; + uintptr_t base = whal_Stm32n6_Cryp_Dev.base; uint32_t keySizeBits; whal_Error err; (void)dev; @@ -433,7 +433,7 @@ whal_Error whal_Stm32n6_CrypAesEcb_Start(whal_AesEcb *dev, { const whal_Stm32n6_Cryp_Cfg *cfg = (const whal_Stm32n6_Cryp_Cfg *)whal_Stm32n6_Cryp_Dev.cfg; - size_t base = whal_Stm32n6_Cryp_Dev.base; + uintptr_t base = whal_Stm32n6_Cryp_Dev.base; uint32_t keySizeBits; whal_Error err; (void)dev; @@ -504,7 +504,7 @@ whal_Error whal_Stm32n6_CrypAesCbc_Oneshot(whal_AesCbc *dev, { const whal_Stm32n6_Cryp_Cfg *cfg = (const whal_Stm32n6_Cryp_Cfg *)whal_Stm32n6_Cryp_Dev.cfg; - size_t base = whal_Stm32n6_Cryp_Dev.base; + uintptr_t base = whal_Stm32n6_Cryp_Dev.base; uint32_t keySizeBits; whal_Error err; (void)dev; @@ -550,7 +550,7 @@ whal_Error whal_Stm32n6_CrypAesCbc_Start(whal_AesCbc *dev, { const whal_Stm32n6_Cryp_Cfg *cfg = (const whal_Stm32n6_Cryp_Cfg *)whal_Stm32n6_Cryp_Dev.cfg; - size_t base = whal_Stm32n6_Cryp_Dev.base; + uintptr_t base = whal_Stm32n6_Cryp_Dev.base; uint32_t keySizeBits; whal_Error err; (void)dev; @@ -623,7 +623,7 @@ whal_Error whal_Stm32n6_CrypAesCtr_Oneshot(whal_AesCtr *dev, { const whal_Stm32n6_Cryp_Cfg *cfg = (const whal_Stm32n6_Cryp_Cfg *)whal_Stm32n6_Cryp_Dev.cfg; - size_t base = whal_Stm32n6_Cryp_Dev.base; + uintptr_t base = whal_Stm32n6_Cryp_Dev.base; uint32_t keySizeBits; uint32_t algoDir; whal_Error err; @@ -661,7 +661,7 @@ whal_Error whal_Stm32n6_CrypAesCtr_Start(whal_AesCtr *dev, { const whal_Stm32n6_Cryp_Cfg *cfg = (const whal_Stm32n6_Cryp_Cfg *)whal_Stm32n6_Cryp_Dev.cfg; - size_t base = whal_Stm32n6_Cryp_Dev.base; + uintptr_t base = whal_Stm32n6_Cryp_Dev.base; uint32_t keySizeBits; uint32_t algoDir; whal_Error err; @@ -728,16 +728,16 @@ static whal_Error GcmInit(const uint8_t *key, size_t keySz, { const whal_Stm32n6_Cryp_Cfg *cfg = (const whal_Stm32n6_Cryp_Cfg *)whal_Stm32n6_Cryp_Dev.cfg; - size_t base = whal_Stm32n6_Cryp_Dev.base; + uintptr_t base = whal_Stm32n6_Cryp_Dev.base; whal_Error err; DisableAndFlush(base); ConfigureMode(base, CRYP_ALGOMODE_AES_GCM, algoDir, keySizeBits, CRYP_GCM_CCMPH_INIT, 0, 0); - whal_Reg_Write(base, CRYP_IV0LR_REG, whal_LoadBe32(iv12)); - whal_Reg_Write(base, CRYP_IV0RR_REG, whal_LoadBe32(iv12 + 4)); - whal_Reg_Write(base, CRYP_IV1LR_REG, whal_LoadBe32(iv12 + 8)); - whal_Reg_Write(base, CRYP_IV1RR_REG, 0x00000002UL); + whal_Reg32_Write(base, CRYP_IV0LR_REG, whal_LoadBe32(iv12)); + whal_Reg32_Write(base, CRYP_IV0RR_REG, whal_LoadBe32(iv12 + 4)); + whal_Reg32_Write(base, CRYP_IV1LR_REG, whal_LoadBe32(iv12 + 8)); + whal_Reg32_Write(base, CRYP_IV1RR_REG, 0x00000002UL); WriteKey(base, key, keySz); err = WaitKeyValid(base, cfg->timeout); if (err) @@ -754,23 +754,23 @@ static whal_Error GcmHeaderPhase(const uint8_t *aad, size_t aadSz) { const whal_Stm32n6_Cryp_Cfg *cfg = (const whal_Stm32n6_Cryp_Cfg *)whal_Stm32n6_Cryp_Dev.cfg; - size_t base = whal_Stm32n6_Cryp_Dev.base; + uintptr_t base = whal_Stm32n6_Cryp_Dev.base; whal_Error err; size_t i; if (aadSz == 0) return WHAL_SUCCESS; - whal_Reg_Update(base, CRYP_CR_REG, CRYP_CR_GCM_CCMPH_Msk, - whal_SetBits(CRYP_CR_GCM_CCMPH_Msk, - CRYP_CR_GCM_CCMPH_Pos, - CRYP_GCM_CCMPH_HEADER)); + whal_Reg32_Update(base, CRYP_CR_REG, CRYP_CR_GCM_CCMPH_Msk, + whal_SetBits(CRYP_CR_GCM_CCMPH_Msk, + CRYP_CR_GCM_CCMPH_Pos, + CRYP_GCM_CCMPH_HEADER)); Enable(base); for (i = 0; i < aadSz; i += 16) { size_t remain = aadSz - i; - err = whal_Reg_ReadPoll(base, CRYP_SR_REG, CRYP_SR_IFNF_Msk, - CRYP_SR_IFNF_Msk, cfg->timeout); + err = whal_Reg32_ReadPoll(base, CRYP_SR_REG, CRYP_SR_IFNF_Msk, + CRYP_SR_IFNF_Msk, cfg->timeout); if (err) return err; if (remain >= 16) { @@ -804,7 +804,7 @@ whal_Error whal_Stm32n6_CrypAesGcm_Oneshot(whal_AesGcm *dev, { const whal_Stm32n6_Cryp_Cfg *cfg = (const whal_Stm32n6_Cryp_Cfg *)whal_Stm32n6_Cryp_Dev.cfg; - size_t base = whal_Stm32n6_Cryp_Dev.base; + uintptr_t base = whal_Stm32n6_Cryp_Dev.base; uint32_t keySizeBits; uint32_t algoDir; uint8_t tagBuf[16]; @@ -846,10 +846,10 @@ whal_Error whal_Stm32n6_CrypAesGcm_Oneshot(whal_AesGcm *dev, /* Payload phase */ if (sz > 0) { Disable(base); - whal_Reg_Update(base, CRYP_CR_REG, CRYP_CR_GCM_CCMPH_Msk, - whal_SetBits(CRYP_CR_GCM_CCMPH_Msk, - CRYP_CR_GCM_CCMPH_Pos, - CRYP_GCM_CCMPH_PAYLOAD)); + whal_Reg32_Update(base, CRYP_CR_REG, CRYP_CR_GCM_CCMPH_Msk, + whal_SetBits(CRYP_CR_GCM_CCMPH_Msk, + CRYP_CR_GCM_CCMPH_Pos, + CRYP_GCM_CCMPH_PAYLOAD)); Enable(base); for (i = 0; i < sz; i += 16) { @@ -864,10 +864,10 @@ whal_Error whal_Stm32n6_CrypAesGcm_Oneshot(whal_AesGcm *dev, WriteBlock(base, inPtr); } else { if (dir == WHAL_CRYPTO_ENCRYPT) { - whal_Reg_Update(base, CRYP_CR_REG, CRYP_CR_NPBLB_Msk, - whal_SetBits(CRYP_CR_NPBLB_Msk, - CRYP_CR_NPBLB_Pos, - 16 - remain)); + whal_Reg32_Update(base, CRYP_CR_REG, CRYP_CR_NPBLB_Msk, + whal_SetBits(CRYP_CR_NPBLB_Msk, + CRYP_CR_NPBLB_Pos, + 16 - remain)); } for (j = 0; j < remain; j++) blockIn[j] = inPtr[j]; @@ -890,19 +890,19 @@ whal_Error whal_Stm32n6_CrypAesGcm_Oneshot(whal_AesGcm *dev, /* Final phase */ Disable(base); - whal_Reg_Update(base, CRYP_CR_REG, - CRYP_CR_GCM_CCMPH_Msk | CRYP_CR_ALGODIR_Msk, - whal_SetBits(CRYP_CR_GCM_CCMPH_Msk, - CRYP_CR_GCM_CCMPH_Pos, - CRYP_GCM_CCMPH_FINAL)); + whal_Reg32_Update(base, CRYP_CR_REG, + CRYP_CR_GCM_CCMPH_Msk | CRYP_CR_ALGODIR_Msk, + whal_SetBits(CRYP_CR_GCM_CCMPH_Msk, + CRYP_CR_GCM_CCMPH_Pos, + CRYP_GCM_CCMPH_FINAL)); Enable(base); aadBits = (uint64_t)aadSz * 8; payloadBits = (uint64_t)sz * 8; - whal_Reg_Write(base, CRYP_DINR_REG, (uint32_t)(aadBits >> 32)); - whal_Reg_Write(base, CRYP_DINR_REG, (uint32_t)aadBits); - whal_Reg_Write(base, CRYP_DINR_REG, (uint32_t)(payloadBits >> 32)); - whal_Reg_Write(base, CRYP_DINR_REG, (uint32_t)payloadBits); + whal_Reg32_Write(base, CRYP_DINR_REG, (uint32_t)(aadBits >> 32)); + whal_Reg32_Write(base, CRYP_DINR_REG, (uint32_t)aadBits); + whal_Reg32_Write(base, CRYP_DINR_REG, (uint32_t)(payloadBits >> 32)); + whal_Reg32_Write(base, CRYP_DINR_REG, (uint32_t)payloadBits); err = WaitOutputReady(base, cfg->timeout); if (err) @@ -923,7 +923,7 @@ whal_Error whal_Stm32n6_CrypAesGcm_Start(whal_AesGcm *dev, const void *iv, size_t ivSz, const void *aad, size_t aadSz) { - size_t base = whal_Stm32n6_Cryp_Dev.base; + uintptr_t base = whal_Stm32n6_Cryp_Dev.base; uint32_t keySizeBits; uint32_t algoDir; whal_Error err; @@ -956,10 +956,10 @@ whal_Error whal_Stm32n6_CrypAesGcm_Start(whal_AesGcm *dev, /* Transition to payload phase */ Disable(base); - whal_Reg_Update(base, CRYP_CR_REG, CRYP_CR_GCM_CCMPH_Msk, - whal_SetBits(CRYP_CR_GCM_CCMPH_Msk, - CRYP_CR_GCM_CCMPH_Pos, - CRYP_GCM_CCMPH_PAYLOAD)); + whal_Reg32_Update(base, CRYP_CR_REG, CRYP_CR_GCM_CCMPH_Msk, + whal_SetBits(CRYP_CR_GCM_CCMPH_Msk, + CRYP_CR_GCM_CCMPH_Pos, + CRYP_GCM_CCMPH_PAYLOAD)); Enable(base); g_aesGcmState.aadSz = aadSz; @@ -979,7 +979,7 @@ whal_Error whal_Stm32n6_CrypAesGcm_Process(whal_AesGcm *dev, { const whal_Stm32n6_Cryp_Cfg *cfg = (const whal_Stm32n6_Cryp_Cfg *)whal_Stm32n6_Cryp_Dev.cfg; - size_t base = whal_Stm32n6_Cryp_Dev.base; + uintptr_t base = whal_Stm32n6_Cryp_Dev.base; uint32_t algoDir; size_t i; whal_Error err; @@ -1000,7 +1000,7 @@ whal_Error whal_Stm32n6_CrypAesGcm_Process(whal_AesGcm *dev, } algoDir = whal_GetBits(CRYP_CR_ALGODIR_Msk, CRYP_CR_ALGODIR_Pos, - whal_Reg_Read(base, CRYP_CR_REG)); + whal_Reg32_Read(base, CRYP_CR_REG)); for (i = 0; i < sz; i += 16) { const uint8_t *inPtr = (const uint8_t *)in + i; @@ -1013,10 +1013,10 @@ whal_Error whal_Stm32n6_CrypAesGcm_Process(whal_AesGcm *dev, WriteBlock(base, inPtr); } else { if (algoDir == CRYP_ALGODIR_ENCRYPT) { - whal_Reg_Update(base, CRYP_CR_REG, CRYP_CR_NPBLB_Msk, - whal_SetBits(CRYP_CR_NPBLB_Msk, - CRYP_CR_NPBLB_Pos, - 16 - remain)); + whal_Reg32_Update(base, CRYP_CR_REG, CRYP_CR_NPBLB_Msk, + whal_SetBits(CRYP_CR_NPBLB_Msk, + CRYP_CR_NPBLB_Pos, + 16 - remain)); } for (j = 0; j < remain; j++) block[j] = inPtr[j]; @@ -1050,7 +1050,7 @@ whal_Error whal_Stm32n6_CrypAesGcm_Finalize(whal_AesGcm *dev, { const whal_Stm32n6_Cryp_Cfg *cfg = (const whal_Stm32n6_Cryp_Cfg *)whal_Stm32n6_Cryp_Dev.cfg; - size_t base = whal_Stm32n6_Cryp_Dev.base; + uintptr_t base = whal_Stm32n6_Cryp_Dev.base; uint8_t tagBuf[16]; uint64_t aadBits; uint64_t payloadBits; @@ -1065,19 +1065,19 @@ whal_Error whal_Stm32n6_CrypAesGcm_Finalize(whal_AesGcm *dev, /* Final phase */ Disable(base); - whal_Reg_Update(base, CRYP_CR_REG, - CRYP_CR_GCM_CCMPH_Msk | CRYP_CR_ALGODIR_Msk, - whal_SetBits(CRYP_CR_GCM_CCMPH_Msk, - CRYP_CR_GCM_CCMPH_Pos, - CRYP_GCM_CCMPH_FINAL)); + whal_Reg32_Update(base, CRYP_CR_REG, + CRYP_CR_GCM_CCMPH_Msk | CRYP_CR_ALGODIR_Msk, + whal_SetBits(CRYP_CR_GCM_CCMPH_Msk, + CRYP_CR_GCM_CCMPH_Pos, + CRYP_GCM_CCMPH_FINAL)); Enable(base); aadBits = (uint64_t)g_aesGcmState.aadSz * 8; payloadBits = g_aesGcmState.dataSz * 8; - whal_Reg_Write(base, CRYP_DINR_REG, (uint32_t)(aadBits >> 32)); - whal_Reg_Write(base, CRYP_DINR_REG, (uint32_t)aadBits); - whal_Reg_Write(base, CRYP_DINR_REG, (uint32_t)(payloadBits >> 32)); - whal_Reg_Write(base, CRYP_DINR_REG, (uint32_t)payloadBits); + whal_Reg32_Write(base, CRYP_DINR_REG, (uint32_t)(aadBits >> 32)); + whal_Reg32_Write(base, CRYP_DINR_REG, (uint32_t)aadBits); + whal_Reg32_Write(base, CRYP_DINR_REG, (uint32_t)(payloadBits >> 32)); + whal_Reg32_Write(base, CRYP_DINR_REG, (uint32_t)payloadBits); err = WaitOutputReady(base, cfg->timeout); if (err) { @@ -1111,7 +1111,7 @@ whal_Error whal_Stm32n6_CrypAesGmac_Oneshot(whal_AesGmac *dev, { const whal_Stm32n6_Cryp_Cfg *cfg = (const whal_Stm32n6_Cryp_Cfg *)whal_Stm32n6_Cryp_Dev.cfg; - size_t base = whal_Stm32n6_Cryp_Dev.base; + uintptr_t base = whal_Stm32n6_Cryp_Dev.base; uint32_t keySizeBits; uint8_t tagBuf[16]; uint64_t aadBits; @@ -1146,18 +1146,18 @@ whal_Error whal_Stm32n6_CrypAesGmac_Oneshot(whal_AesGmac *dev, /* Final phase */ Disable(base); - whal_Reg_Update(base, CRYP_CR_REG, - CRYP_CR_GCM_CCMPH_Msk | CRYP_CR_ALGODIR_Msk, - whal_SetBits(CRYP_CR_GCM_CCMPH_Msk, - CRYP_CR_GCM_CCMPH_Pos, - CRYP_GCM_CCMPH_FINAL)); + whal_Reg32_Update(base, CRYP_CR_REG, + CRYP_CR_GCM_CCMPH_Msk | CRYP_CR_ALGODIR_Msk, + whal_SetBits(CRYP_CR_GCM_CCMPH_Msk, + CRYP_CR_GCM_CCMPH_Pos, + CRYP_GCM_CCMPH_FINAL)); Enable(base); aadBits = (uint64_t)aadSz * 8; - whal_Reg_Write(base, CRYP_DINR_REG, (uint32_t)(aadBits >> 32)); - whal_Reg_Write(base, CRYP_DINR_REG, (uint32_t)aadBits); - whal_Reg_Write(base, CRYP_DINR_REG, 0); - whal_Reg_Write(base, CRYP_DINR_REG, 0); + whal_Reg32_Write(base, CRYP_DINR_REG, (uint32_t)(aadBits >> 32)); + whal_Reg32_Write(base, CRYP_DINR_REG, (uint32_t)aadBits); + whal_Reg32_Write(base, CRYP_DINR_REG, 0); + whal_Reg32_Write(base, CRYP_DINR_REG, 0); err = WaitOutputReady(base, cfg->timeout); if (err) @@ -1212,7 +1212,7 @@ whal_Error whal_Stm32n6_CrypAesCcm_Oneshot(whal_AesCcm *dev, { const whal_Stm32n6_Cryp_Cfg *cfg = (const whal_Stm32n6_Cryp_Cfg *)whal_Stm32n6_Cryp_Dev.cfg; - size_t base = whal_Stm32n6_Cryp_Dev.base; + uintptr_t base = whal_Stm32n6_Cryp_Dev.base; uint32_t keySizeBits; uint32_t algoDir; uint8_t b0[16]; @@ -1289,10 +1289,10 @@ whal_Error whal_Stm32n6_CrypAesCcm_Oneshot(whal_AesCcm *dev, size_t hdrOff; size_t aadOff = 0; - whal_Reg_Update(base, CRYP_CR_REG, CRYP_CR_GCM_CCMPH_Msk, - whal_SetBits(CRYP_CR_GCM_CCMPH_Msk, - CRYP_CR_GCM_CCMPH_Pos, - CRYP_GCM_CCMPH_HEADER)); + whal_Reg32_Update(base, CRYP_CR_REG, CRYP_CR_GCM_CCMPH_Msk, + whal_SetBits(CRYP_CR_GCM_CCMPH_Msk, + CRYP_CR_GCM_CCMPH_Pos, + CRYP_GCM_CCMPH_HEADER)); Enable(base); /* SP 800-38C A.2.2: 2-byte length below 0xFF00, else 0xFFFE + 4 bytes */ @@ -1318,8 +1318,8 @@ whal_Error whal_Stm32n6_CrypAesCcm_Oneshot(whal_AesCcm *dev, size_t j; for (j = 0; j < 16 && aadOff < aadSz; j++) blk[j] = aadPtr[aadOff++]; - err = whal_Reg_ReadPoll(base, CRYP_SR_REG, CRYP_SR_IFNF_Msk, - CRYP_SR_IFNF_Msk, cfg->timeout); + err = whal_Reg32_ReadPoll(base, CRYP_SR_REG, CRYP_SR_IFNF_Msk, + CRYP_SR_IFNF_Msk, cfg->timeout); if (err) goto cleanup; WriteBlock(base, blk); @@ -1333,10 +1333,10 @@ whal_Error whal_Stm32n6_CrypAesCcm_Oneshot(whal_AesCcm *dev, /* Payload phase */ if (sz > 0) { Disable(base); - whal_Reg_Update(base, CRYP_CR_REG, CRYP_CR_GCM_CCMPH_Msk, - whal_SetBits(CRYP_CR_GCM_CCMPH_Msk, - CRYP_CR_GCM_CCMPH_Pos, - CRYP_GCM_CCMPH_PAYLOAD)); + whal_Reg32_Update(base, CRYP_CR_REG, CRYP_CR_GCM_CCMPH_Msk, + whal_SetBits(CRYP_CR_GCM_CCMPH_Msk, + CRYP_CR_GCM_CCMPH_Pos, + CRYP_GCM_CCMPH_PAYLOAD)); Enable(base); for (i = 0; i < sz; i += 16) { @@ -1351,10 +1351,10 @@ whal_Error whal_Stm32n6_CrypAesCcm_Oneshot(whal_AesCcm *dev, WriteBlock(base, inPtr); } else { if (dir == WHAL_CRYPTO_DECRYPT) { - whal_Reg_Update(base, CRYP_CR_REG, CRYP_CR_NPBLB_Msk, - whal_SetBits(CRYP_CR_NPBLB_Msk, - CRYP_CR_NPBLB_Pos, - 16 - remain)); + whal_Reg32_Update(base, CRYP_CR_REG, CRYP_CR_NPBLB_Msk, + whal_SetBits(CRYP_CR_NPBLB_Msk, + CRYP_CR_NPBLB_Pos, + 16 - remain)); } for (j = 0; j < remain; j++) blockIn[j] = inPtr[j]; @@ -1377,11 +1377,11 @@ whal_Error whal_Stm32n6_CrypAesCcm_Oneshot(whal_AesCcm *dev, /* Final phase */ Disable(base); - whal_Reg_Update(base, CRYP_CR_REG, - CRYP_CR_GCM_CCMPH_Msk | CRYP_CR_ALGODIR_Msk, - whal_SetBits(CRYP_CR_GCM_CCMPH_Msk, - CRYP_CR_GCM_CCMPH_Pos, - CRYP_GCM_CCMPH_FINAL)); + whal_Reg32_Update(base, CRYP_CR_REG, + CRYP_CR_GCM_CCMPH_Msk | CRYP_CR_ALGODIR_Msk, + whal_SetBits(CRYP_CR_GCM_CCMPH_Msk, + CRYP_CR_GCM_CCMPH_Pos, + CRYP_GCM_CCMPH_FINAL)); Enable(base); WriteBlock(base, ctr0); @@ -1408,7 +1408,7 @@ whal_Error whal_Stm32n6_CrypAesCcm_Start(whal_AesCcm *dev, { const whal_Stm32n6_Cryp_Cfg *cfg = (const whal_Stm32n6_Cryp_Cfg *)whal_Stm32n6_Cryp_Dev.cfg; - size_t base = whal_Stm32n6_Cryp_Dev.base; + uintptr_t base = whal_Stm32n6_Cryp_Dev.base; uint32_t keySizeBits; uint32_t algoDir; uint8_t b0[16]; @@ -1474,10 +1474,10 @@ whal_Error whal_Stm32n6_CrypAesCcm_Start(whal_AesCcm *dev, size_t hdrOff; size_t aadOff = 0; - whal_Reg_Update(base, CRYP_CR_REG, CRYP_CR_GCM_CCMPH_Msk, - whal_SetBits(CRYP_CR_GCM_CCMPH_Msk, - CRYP_CR_GCM_CCMPH_Pos, - CRYP_GCM_CCMPH_HEADER)); + whal_Reg32_Update(base, CRYP_CR_REG, CRYP_CR_GCM_CCMPH_Msk, + whal_SetBits(CRYP_CR_GCM_CCMPH_Msk, + CRYP_CR_GCM_CCMPH_Pos, + CRYP_GCM_CCMPH_HEADER)); Enable(base); /* SP 800-38C A.2.2: 2-byte length below 0xFF00, else 0xFFFE + 4 bytes */ @@ -1503,8 +1503,8 @@ whal_Error whal_Stm32n6_CrypAesCcm_Start(whal_AesCcm *dev, size_t j; for (j = 0; j < 16 && aadOff < aadSz; j++) blk[j] = aadPtr[aadOff++]; - err = whal_Reg_ReadPoll(base, CRYP_SR_REG, CRYP_SR_IFNF_Msk, - CRYP_SR_IFNF_Msk, cfg->timeout); + err = whal_Reg32_ReadPoll(base, CRYP_SR_REG, CRYP_SR_IFNF_Msk, + CRYP_SR_IFNF_Msk, cfg->timeout); if (err) goto cleanup; WriteBlock(base, blk); @@ -1517,10 +1517,10 @@ whal_Error whal_Stm32n6_CrypAesCcm_Start(whal_AesCcm *dev, /* Transition to payload phase */ Disable(base); - whal_Reg_Update(base, CRYP_CR_REG, CRYP_CR_GCM_CCMPH_Msk, - whal_SetBits(CRYP_CR_GCM_CCMPH_Msk, - CRYP_CR_GCM_CCMPH_Pos, - CRYP_GCM_CCMPH_PAYLOAD)); + whal_Reg32_Update(base, CRYP_CR_REG, CRYP_CR_GCM_CCMPH_Msk, + whal_SetBits(CRYP_CR_GCM_CCMPH_Msk, + CRYP_CR_GCM_CCMPH_Pos, + CRYP_GCM_CCMPH_PAYLOAD)); Enable(base); g_aesCcmState.aadSz = aadSz; @@ -1542,7 +1542,7 @@ whal_Error whal_Stm32n6_CrypAesCcm_Process(whal_AesCcm *dev, { const whal_Stm32n6_Cryp_Cfg *cfg = (const whal_Stm32n6_Cryp_Cfg *)whal_Stm32n6_Cryp_Dev.cfg; - size_t base = whal_Stm32n6_Cryp_Dev.base; + uintptr_t base = whal_Stm32n6_Cryp_Dev.base; uint32_t algoDir; size_t i; whal_Error err; @@ -1565,7 +1565,7 @@ whal_Error whal_Stm32n6_CrypAesCcm_Process(whal_AesCcm *dev, } algoDir = whal_GetBits(CRYP_CR_ALGODIR_Msk, CRYP_CR_ALGODIR_Pos, - whal_Reg_Read(base, CRYP_CR_REG)); + whal_Reg32_Read(base, CRYP_CR_REG)); for (i = 0; i < sz; i += 16) { const uint8_t *inPtr = (const uint8_t *)in + i; @@ -1579,10 +1579,10 @@ whal_Error whal_Stm32n6_CrypAesCcm_Process(whal_AesCcm *dev, WriteBlock(base, inPtr); } else { if (algoDir == CRYP_ALGODIR_DECRYPT) { - whal_Reg_Update(base, CRYP_CR_REG, CRYP_CR_NPBLB_Msk, - whal_SetBits(CRYP_CR_NPBLB_Msk, - CRYP_CR_NPBLB_Pos, - 16 - remain)); + whal_Reg32_Update(base, CRYP_CR_REG, CRYP_CR_NPBLB_Msk, + whal_SetBits(CRYP_CR_NPBLB_Msk, + CRYP_CR_NPBLB_Pos, + 16 - remain)); } for (j = 0; j < remain; j++) block[j] = inPtr[j]; @@ -1616,7 +1616,7 @@ whal_Error whal_Stm32n6_CrypAesCcm_Finalize(whal_AesCcm *dev, { const whal_Stm32n6_Cryp_Cfg *cfg = (const whal_Stm32n6_Cryp_Cfg *)whal_Stm32n6_Cryp_Dev.cfg; - size_t base = whal_Stm32n6_Cryp_Dev.base; + uintptr_t base = whal_Stm32n6_Cryp_Dev.base; uint8_t tagBuf[16]; size_t i; whal_Error err; @@ -1632,11 +1632,11 @@ whal_Error whal_Stm32n6_CrypAesCcm_Finalize(whal_AesCcm *dev, /* Final phase */ Disable(base); - whal_Reg_Update(base, CRYP_CR_REG, - CRYP_CR_GCM_CCMPH_Msk | CRYP_CR_ALGODIR_Msk, - whal_SetBits(CRYP_CR_GCM_CCMPH_Msk, - CRYP_CR_GCM_CCMPH_Pos, - CRYP_GCM_CCMPH_FINAL)); + whal_Reg32_Update(base, CRYP_CR_REG, + CRYP_CR_GCM_CCMPH_Msk | CRYP_CR_ALGODIR_Msk, + whal_SetBits(CRYP_CR_GCM_CCMPH_Msk, + CRYP_CR_GCM_CCMPH_Pos, + CRYP_GCM_CCMPH_FINAL)); Enable(base); WriteBlock(base, g_aesCcmState.ccmCtr0); diff --git a/src/crypto/stm32wb_aes.c b/src/crypto/stm32wb_aes.c index 31023118..8dce7c6d 100644 --- a/src/crypto/stm32wb_aes.c +++ b/src/crypto/stm32wb_aes.c @@ -126,83 +126,83 @@ const whal_AesCcm whal_Stm32wb_AesCcm_Dev = WHAL_CFG_STM32WB_AES_CCM_DEV; #define AES_GCMPH_PAYLOAD 0x2 #define AES_GCMPH_FINAL 0x3 -static void WriteKey(size_t base, const uint8_t *key, size_t keySz) +static void WriteKey(uintptr_t base, const uint8_t *key, size_t keySz) { const uint8_t *k = key; if (keySz == 32) { - whal_Reg_Write(base, AES_KEYR7_REG, whal_LoadBe32(k)); - whal_Reg_Write(base, AES_KEYR6_REG, whal_LoadBe32(k + 4)); - whal_Reg_Write(base, AES_KEYR5_REG, whal_LoadBe32(k + 8)); - whal_Reg_Write(base, AES_KEYR4_REG, whal_LoadBe32(k + 12)); + whal_Reg32_Write(base, AES_KEYR7_REG, whal_LoadBe32(k)); + whal_Reg32_Write(base, AES_KEYR6_REG, whal_LoadBe32(k + 4)); + whal_Reg32_Write(base, AES_KEYR5_REG, whal_LoadBe32(k + 8)); + whal_Reg32_Write(base, AES_KEYR4_REG, whal_LoadBe32(k + 12)); k += 16; } - whal_Reg_Write(base, AES_KEYR3_REG, whal_LoadBe32(k)); - whal_Reg_Write(base, AES_KEYR2_REG, whal_LoadBe32(k + 4)); - whal_Reg_Write(base, AES_KEYR1_REG, whal_LoadBe32(k + 8)); - whal_Reg_Write(base, AES_KEYR0_REG, whal_LoadBe32(k + 12)); + whal_Reg32_Write(base, AES_KEYR3_REG, whal_LoadBe32(k)); + whal_Reg32_Write(base, AES_KEYR2_REG, whal_LoadBe32(k + 4)); + whal_Reg32_Write(base, AES_KEYR1_REG, whal_LoadBe32(k + 8)); + whal_Reg32_Write(base, AES_KEYR0_REG, whal_LoadBe32(k + 12)); } -static void WriteIv(size_t base, const uint8_t *iv) +static void WriteIv(uintptr_t base, const uint8_t *iv) { - whal_Reg_Write(base, AES_IVR3_REG, whal_LoadBe32(iv)); - whal_Reg_Write(base, AES_IVR2_REG, whal_LoadBe32(iv + 4)); - whal_Reg_Write(base, AES_IVR1_REG, whal_LoadBe32(iv + 8)); - whal_Reg_Write(base, AES_IVR0_REG, whal_LoadBe32(iv + 12)); + whal_Reg32_Write(base, AES_IVR3_REG, whal_LoadBe32(iv)); + whal_Reg32_Write(base, AES_IVR2_REG, whal_LoadBe32(iv + 4)); + whal_Reg32_Write(base, AES_IVR1_REG, whal_LoadBe32(iv + 8)); + whal_Reg32_Write(base, AES_IVR0_REG, whal_LoadBe32(iv + 12)); } /* Wipe key and IV/counter material from the peripheral registers. Callers must * clear EN first (key registers are only writable while disabled). */ -static void ZeroKeyIv(size_t base) +static void ZeroKeyIv(uintptr_t base) { - whal_Reg_Write(base, AES_KEYR7_REG, 0); - whal_Reg_Write(base, AES_KEYR6_REG, 0); - whal_Reg_Write(base, AES_KEYR5_REG, 0); - whal_Reg_Write(base, AES_KEYR4_REG, 0); - whal_Reg_Write(base, AES_KEYR3_REG, 0); - whal_Reg_Write(base, AES_KEYR2_REG, 0); - whal_Reg_Write(base, AES_KEYR1_REG, 0); - whal_Reg_Write(base, AES_KEYR0_REG, 0); - whal_Reg_Write(base, AES_IVR3_REG, 0); - whal_Reg_Write(base, AES_IVR2_REG, 0); - whal_Reg_Write(base, AES_IVR1_REG, 0); - whal_Reg_Write(base, AES_IVR0_REG, 0); + whal_Reg32_Write(base, AES_KEYR7_REG, 0); + whal_Reg32_Write(base, AES_KEYR6_REG, 0); + whal_Reg32_Write(base, AES_KEYR5_REG, 0); + whal_Reg32_Write(base, AES_KEYR4_REG, 0); + whal_Reg32_Write(base, AES_KEYR3_REG, 0); + whal_Reg32_Write(base, AES_KEYR2_REG, 0); + whal_Reg32_Write(base, AES_KEYR1_REG, 0); + whal_Reg32_Write(base, AES_KEYR0_REG, 0); + whal_Reg32_Write(base, AES_IVR3_REG, 0); + whal_Reg32_Write(base, AES_IVR2_REG, 0); + whal_Reg32_Write(base, AES_IVR1_REG, 0); + whal_Reg32_Write(base, AES_IVR0_REG, 0); } -static void WriteBlock(size_t base, const uint8_t *in) +static void WriteBlock(uintptr_t base, const uint8_t *in) { - whal_Reg_Write(base, AES_DINR_REG, whal_LoadBe32(in)); - whal_Reg_Write(base, AES_DINR_REG, whal_LoadBe32(in + 4)); - whal_Reg_Write(base, AES_DINR_REG, whal_LoadBe32(in + 8)); - whal_Reg_Write(base, AES_DINR_REG, whal_LoadBe32(in + 12)); + whal_Reg32_Write(base, AES_DINR_REG, whal_LoadBe32(in)); + whal_Reg32_Write(base, AES_DINR_REG, whal_LoadBe32(in + 4)); + whal_Reg32_Write(base, AES_DINR_REG, whal_LoadBe32(in + 8)); + whal_Reg32_Write(base, AES_DINR_REG, whal_LoadBe32(in + 12)); } -static void ReadBlock(size_t base, uint8_t *out) +static void ReadBlock(uintptr_t base, uint8_t *out) { - whal_StoreBe32(out, whal_Reg_Read(base, AES_DOUTR_REG)); - whal_StoreBe32(out + 4, whal_Reg_Read(base, AES_DOUTR_REG)); - whal_StoreBe32(out + 8, whal_Reg_Read(base, AES_DOUTR_REG)); - whal_StoreBe32(out + 12, whal_Reg_Read(base, AES_DOUTR_REG)); + whal_StoreBe32(out, whal_Reg32_Read(base, AES_DOUTR_REG)); + whal_StoreBe32(out + 4, whal_Reg32_Read(base, AES_DOUTR_REG)); + whal_StoreBe32(out + 8, whal_Reg32_Read(base, AES_DOUTR_REG)); + whal_StoreBe32(out + 12, whal_Reg32_Read(base, AES_DOUTR_REG)); } /* Discard any output block left in DOUTR. */ -static void DrainOutput(size_t base) +static void DrainOutput(uintptr_t base) { - (void)whal_Reg_Read(base, AES_DOUTR_REG); - (void)whal_Reg_Read(base, AES_DOUTR_REG); - (void)whal_Reg_Read(base, AES_DOUTR_REG); - (void)whal_Reg_Read(base, AES_DOUTR_REG); + (void)whal_Reg32_Read(base, AES_DOUTR_REG); + (void)whal_Reg32_Read(base, AES_DOUTR_REG); + (void)whal_Reg32_Read(base, AES_DOUTR_REG); + (void)whal_Reg32_Read(base, AES_DOUTR_REG); } -static whal_Error WaitForCCF(size_t base, whal_Timeout *timeout) +static whal_Error WaitForCCF(uintptr_t base, whal_Timeout *timeout) { whal_Error err; - err = whal_Reg_ReadPoll(base, AES_SR_REG, AES_SR_CCF_Msk, - AES_SR_CCF_Msk, timeout); + err = whal_Reg32_ReadPoll(base, AES_SR_REG, AES_SR_CCF_Msk, + AES_SR_CCF_Msk, timeout); if (err) { DrainOutput(base); return err; } - whal_Reg_Update(base, AES_CR_REG, AES_CR_CCFC_Msk, AES_CR_CCFC_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_CCFC_Msk, AES_CR_CCFC_Msk); return WHAL_SUCCESS; } @@ -212,7 +212,7 @@ static whal_Error ProcessBlockCipher(whal_Crypto *cryptoDev, { const whal_Stm32wb_Aes_Cfg *cfg = (const whal_Stm32wb_Aes_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->base; + uintptr_t base = cryptoDev->base; whal_Error err; size_t i; @@ -220,7 +220,7 @@ static whal_Error ProcessBlockCipher(whal_Crypto *cryptoDev, return WHAL_SUCCESS; if (!in || !out || (sz & 0xF) != 0) { - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); ZeroKeyIv(base); return WHAL_EINVAL; } @@ -229,7 +229,7 @@ static whal_Error ProcessBlockCipher(whal_Crypto *cryptoDev, WriteBlock(base, in + i); err = WaitForCCF(base, cfg->timeout); if (err) { - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); ZeroKeyIv(base); return err; } @@ -241,7 +241,7 @@ static whal_Error ProcessBlockCipher(whal_Crypto *cryptoDev, static void DisableAes(whal_Crypto *cryptoDev) { - whal_Reg_Update(cryptoDev->base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(cryptoDev->base, AES_CR_REG, AES_CR_EN_Msk, 0); } static whal_Error StopBlockCipher(whal_Crypto *cryptoDev) @@ -323,7 +323,7 @@ whal_Error whal_Stm32wb_AesEcb_Oneshot(whal_AesEcb *dev, whal_Crypto_Dir dir, const void *in, void *out, size_t sz) { whal_Crypto *crypto = whal_Stm32wb_AesEcb_Dev.crypto; - size_t base = crypto->base; + uintptr_t base = crypto->base; size_t mode; size_t keySizeBit; whal_Error err; @@ -340,22 +340,22 @@ whal_Error whal_Stm32wb_AesEcb_Oneshot(whal_AesEcb *dev, whal_Crypto_Dir dir, mode = (dir == WHAL_CRYPTO_ENCRYPT) ? AES_MODE_ENCRYPT : AES_MODE_KEYDERIV_DECRYPT; - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | - AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, mode) | - whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, - AES_CHMOD_ECB) | - whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, - AES_DATATYPE_NONE) | - whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, - keySizeBit)); + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | + AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, mode) | + whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, + AES_CHMOD_ECB) | + whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, + AES_DATATYPE_NONE) | + whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, + keySizeBit)); WriteKey(base, key, keySz); - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); err = ProcessBlockCipher(crypto, in, out, sz); DisableAes(crypto); @@ -367,7 +367,7 @@ whal_Error whal_Stm32wb_AesEcb_Start(whal_AesEcb *dev, whal_Crypto_Dir dir, const void *key, size_t keySz) { whal_Crypto *crypto = whal_Stm32wb_AesEcb_Dev.crypto; - size_t base = crypto->base; + uintptr_t base = crypto->base; size_t mode; size_t keySizeBit; @@ -383,23 +383,23 @@ whal_Error whal_Stm32wb_AesEcb_Start(whal_AesEcb *dev, whal_Crypto_Dir dir, mode = (dir == WHAL_CRYPTO_ENCRYPT) ? AES_MODE_ENCRYPT : AES_MODE_KEYDERIV_DECRYPT; - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); ZeroKeyIv(base); - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | - AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, mode) | - whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, - AES_CHMOD_ECB) | - whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, - AES_DATATYPE_NONE) | - whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, - keySizeBit)); + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | + AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, mode) | + whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, + AES_CHMOD_ECB) | + whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, + AES_DATATYPE_NONE) | + whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, + keySizeBit)); WriteKey(base, key, keySz); - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); return WHAL_SUCCESS; } @@ -433,7 +433,7 @@ whal_Error whal_Stm32wb_AesCbc_Oneshot(whal_AesCbc *dev, whal_Crypto_Dir dir, const void *in, void *out, size_t sz) { whal_Crypto *crypto = whal_Stm32wb_AesCbc_Dev.crypto; - size_t base = crypto->base; + uintptr_t base = crypto->base; size_t mode; size_t keySizeBit; whal_Error err; @@ -450,23 +450,23 @@ whal_Error whal_Stm32wb_AesCbc_Oneshot(whal_AesCbc *dev, whal_Crypto_Dir dir, mode = (dir == WHAL_CRYPTO_ENCRYPT) ? AES_MODE_ENCRYPT : AES_MODE_KEYDERIV_DECRYPT; - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | - AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, mode) | - whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, - AES_CHMOD_CBC) | - whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, - AES_DATATYPE_NONE) | - whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, - keySizeBit)); + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | + AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, mode) | + whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, + AES_CHMOD_CBC) | + whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, + AES_DATATYPE_NONE) | + whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, + keySizeBit)); WriteKey(base, key, keySz); WriteIv(base, iv); - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); err = ProcessBlockCipher(crypto, in, out, sz); DisableAes(crypto); @@ -479,7 +479,7 @@ whal_Error whal_Stm32wb_AesCbc_Start(whal_AesCbc *dev, whal_Crypto_Dir dir, const void *iv) { whal_Crypto *crypto = whal_Stm32wb_AesCbc_Dev.crypto; - size_t base = crypto->base; + uintptr_t base = crypto->base; size_t mode; size_t keySizeBit; @@ -495,24 +495,24 @@ whal_Error whal_Stm32wb_AesCbc_Start(whal_AesCbc *dev, whal_Crypto_Dir dir, mode = (dir == WHAL_CRYPTO_ENCRYPT) ? AES_MODE_ENCRYPT : AES_MODE_KEYDERIV_DECRYPT; - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); ZeroKeyIv(base); - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | - AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, mode) | - whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, - AES_CHMOD_CBC) | - whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, - AES_DATATYPE_NONE) | - whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, - keySizeBit)); + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | + AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, mode) | + whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, + AES_CHMOD_CBC) | + whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, + AES_DATATYPE_NONE) | + whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, + keySizeBit)); WriteKey(base, key, keySz); WriteIv(base, iv); - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); return WHAL_SUCCESS; } @@ -546,7 +546,7 @@ whal_Error whal_Stm32wb_AesCtr_Oneshot(whal_AesCtr *dev, whal_Crypto_Dir dir, const void *in, void *out, size_t sz) { whal_Crypto *crypto = whal_Stm32wb_AesCtr_Dev.crypto; - size_t base = crypto->base; + uintptr_t base = crypto->base; size_t keySizeBit; whal_Error err; @@ -560,24 +560,24 @@ whal_Error whal_Stm32wb_AesCtr_Oneshot(whal_AesCtr *dev, whal_Crypto_Dir dir, keySizeBit = (keySz == 32) ? 1 : 0; - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | - AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - AES_MODE_ENCRYPT) | - whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, - AES_CHMOD_CTR) | - whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, - AES_DATATYPE_NONE) | - whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, - keySizeBit)); + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | + AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_ENCRYPT) | + whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, + AES_CHMOD_CTR) | + whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, + AES_DATATYPE_NONE) | + whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, + keySizeBit)); WriteKey(base, key, keySz); WriteIv(base, iv); - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); err = ProcessBlockCipher(crypto, in, out, sz); DisableAes(crypto); @@ -590,7 +590,7 @@ whal_Error whal_Stm32wb_AesCtr_Start(whal_AesCtr *dev, whal_Crypto_Dir dir, const void *iv) { whal_Crypto *crypto = whal_Stm32wb_AesCtr_Dev.crypto; - size_t base = crypto->base; + uintptr_t base = crypto->base; size_t keySizeBit; (void)dev; @@ -603,25 +603,25 @@ whal_Error whal_Stm32wb_AesCtr_Start(whal_AesCtr *dev, whal_Crypto_Dir dir, keySizeBit = (keySz == 32) ? 1 : 0; - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); ZeroKeyIv(base); - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | - AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - AES_MODE_ENCRYPT) | - whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, - AES_CHMOD_CTR) | - whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, - AES_DATATYPE_NONE) | - whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, - keySizeBit)); + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | + AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_ENCRYPT) | + whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, + AES_CHMOD_CTR) | + whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, + AES_DATATYPE_NONE) | + whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, + keySizeBit)); WriteKey(base, key, keySz); WriteIv(base, iv); - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); return WHAL_SUCCESS; } @@ -659,7 +659,7 @@ whal_Error whal_Stm32wb_AesGcm_Oneshot(whal_AesGcm *dev, whal_Crypto_Dir dir, whal_Crypto *crypto = whal_Stm32wb_AesGcm_Dev.crypto; const whal_Stm32wb_Aes_Cfg *cfg = (const whal_Stm32wb_Aes_Cfg *)crypto->cfg; - size_t base = crypto->base; + uintptr_t base = crypto->base; const uint8_t *ivBytes = (const uint8_t *)iv; const uint8_t *aadBytes = (const uint8_t *)aad; size_t keySizeBit; @@ -693,31 +693,31 @@ whal_Error whal_Stm32wb_AesGcm_Oneshot(whal_AesGcm *dev, whal_Crypto_Dir dir, keySizeBit = (keySz == 32) ? 1 : 0; /* Init phase */ - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); - - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | - AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk | - AES_CR_GCMPH_Msk | AES_CR_NPBLB_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - AES_MODE_ENCRYPT) | - whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, - AES_CHMOD_GCM) | - whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, - AES_DATATYPE_NONE) | - whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, - keySizeBit) | - whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, - AES_GCMPH_INIT)); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | + AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk | + AES_CR_GCMPH_Msk | AES_CR_NPBLB_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_ENCRYPT) | + whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, + AES_CHMOD_GCM) | + whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, + AES_DATATYPE_NONE) | + whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, + keySizeBit) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_INIT)); WriteKey(base, key, keySz); - whal_Reg_Write(base, AES_IVR3_REG, whal_LoadBe32(ivBytes)); - whal_Reg_Write(base, AES_IVR2_REG, whal_LoadBe32(ivBytes + 4)); - whal_Reg_Write(base, AES_IVR1_REG, whal_LoadBe32(ivBytes + 8)); - whal_Reg_Write(base, AES_IVR0_REG, 0x00000002); + whal_Reg32_Write(base, AES_IVR3_REG, whal_LoadBe32(ivBytes)); + whal_Reg32_Write(base, AES_IVR2_REG, whal_LoadBe32(ivBytes + 4)); + whal_Reg32_Write(base, AES_IVR1_REG, whal_LoadBe32(ivBytes + 8)); + whal_Reg32_Write(base, AES_IVR0_REG, 0x00000002); - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); err = WaitForCCF(base, cfg->timeout); if (err) @@ -725,14 +725,14 @@ whal_Error whal_Stm32wb_AesGcm_Oneshot(whal_AesGcm *dev, whal_Crypto_Dir dir, /* Header phase (AAD) */ if (aadSz > 0) { - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - AES_MODE_ENCRYPT) | - whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, - AES_GCMPH_HEADER)); + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_ENCRYPT) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_HEADER)); - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); for (i = 0; i < aadSz; i += 16) { const uint8_t *blkAad = aadBytes + i; @@ -759,15 +759,15 @@ whal_Error whal_Stm32wb_AesGcm_Oneshot(whal_AesGcm *dev, whal_Crypto_Dir dir, mode = (dir == WHAL_CRYPTO_ENCRYPT) ? AES_MODE_ENCRYPT : AES_MODE_DECRYPT; - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - mode) | - whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, - AES_GCMPH_PAYLOAD)); + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + mode) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_PAYLOAD)); if (aadSz == 0) - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); for (i = 0; i < sz; i += 16) { const uint8_t *inBlk = (const uint8_t *)in + i; @@ -780,10 +780,10 @@ whal_Error whal_Stm32wb_AesGcm_Oneshot(whal_AesGcm *dev, whal_Crypto_Dir dir, WriteBlock(base, inBlk); } else { if (mode == AES_MODE_ENCRYPT) { - whal_Reg_Update(base, AES_CR_REG, AES_CR_NPBLB_Msk, - whal_SetBits(AES_CR_NPBLB_Msk, - AES_CR_NPBLB_Pos, - 16 - remain)); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_NPBLB_Msk, + whal_SetBits(AES_CR_NPBLB_Msk, + AES_CR_NPBLB_Pos, + 16 - remain)); } for (j = 0; j < remain; j++) block[j] = inBlk[j]; @@ -805,22 +805,22 @@ whal_Error whal_Stm32wb_AesGcm_Oneshot(whal_AesGcm *dev, whal_Crypto_Dir dir, } /* Final phase (tag) */ - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - AES_MODE_ENCRYPT) | - whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, - AES_GCMPH_FINAL)); + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_ENCRYPT) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_FINAL)); if (aadSz == 0 && sz == 0) - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); aadBits = (uint64_t)aadSz * 8; payloadBits = (uint64_t)sz * 8; - whal_Reg_Write(base, AES_DINR_REG, (uint32_t)(aadBits >> 32)); - whal_Reg_Write(base, AES_DINR_REG, (uint32_t)aadBits); - whal_Reg_Write(base, AES_DINR_REG, (uint32_t)(payloadBits >> 32)); - whal_Reg_Write(base, AES_DINR_REG, (uint32_t)payloadBits); + whal_Reg32_Write(base, AES_DINR_REG, (uint32_t)(aadBits >> 32)); + whal_Reg32_Write(base, AES_DINR_REG, (uint32_t)aadBits); + whal_Reg32_Write(base, AES_DINR_REG, (uint32_t)(payloadBits >> 32)); + whal_Reg32_Write(base, AES_DINR_REG, (uint32_t)payloadBits); err = WaitForCCF(base, cfg->timeout); if (err) @@ -832,7 +832,7 @@ whal_Error whal_Stm32wb_AesGcm_Oneshot(whal_AesGcm *dev, whal_Crypto_Dir dir, ((uint8_t *)tag)[i] = tagBuf[i]; cleanup: - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); ZeroKeyIv(base); return err; } @@ -845,7 +845,7 @@ whal_Error whal_Stm32wb_AesGcm_Start(whal_AesGcm *dev, whal_Crypto_Dir dir, whal_Crypto *crypto = whal_Stm32wb_AesGcm_Dev.crypto; const whal_Stm32wb_Aes_Cfg *cfg = (const whal_Stm32wb_Aes_Cfg *)crypto->cfg; - size_t base = crypto->base; + uintptr_t base = crypto->base; const uint8_t *ivBytes = (const uint8_t *)iv; const uint8_t *aadBytes = (const uint8_t *)aad; size_t keySizeBit; @@ -870,31 +870,31 @@ whal_Error whal_Stm32wb_AesGcm_Start(whal_AesGcm *dev, whal_Crypto_Dir dir, keySizeBit = (keySz == 32) ? 1 : 0; /* Init phase */ - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); - - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | - AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk | - AES_CR_GCMPH_Msk | AES_CR_NPBLB_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - AES_MODE_ENCRYPT) | - whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, - AES_CHMOD_GCM) | - whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, - AES_DATATYPE_NONE) | - whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, - keySizeBit) | - whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, - AES_GCMPH_INIT)); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | + AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk | + AES_CR_GCMPH_Msk | AES_CR_NPBLB_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_ENCRYPT) | + whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, + AES_CHMOD_GCM) | + whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, + AES_DATATYPE_NONE) | + whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, + keySizeBit) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_INIT)); WriteKey(base, key, keySz); - whal_Reg_Write(base, AES_IVR3_REG, whal_LoadBe32(ivBytes)); - whal_Reg_Write(base, AES_IVR2_REG, whal_LoadBe32(ivBytes + 4)); - whal_Reg_Write(base, AES_IVR1_REG, whal_LoadBe32(ivBytes + 8)); - whal_Reg_Write(base, AES_IVR0_REG, 0x00000002); + whal_Reg32_Write(base, AES_IVR3_REG, whal_LoadBe32(ivBytes)); + whal_Reg32_Write(base, AES_IVR2_REG, whal_LoadBe32(ivBytes + 4)); + whal_Reg32_Write(base, AES_IVR1_REG, whal_LoadBe32(ivBytes + 8)); + whal_Reg32_Write(base, AES_IVR0_REG, 0x00000002); - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); err = WaitForCCF(base, cfg->timeout); if (err) @@ -902,14 +902,14 @@ whal_Error whal_Stm32wb_AesGcm_Start(whal_AesGcm *dev, whal_Crypto_Dir dir, /* Header phase (AAD) */ if (aadSz > 0) { - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - AES_MODE_ENCRYPT) | - whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, - AES_GCMPH_HEADER)); + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_ENCRYPT) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_HEADER)); - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); for (i = 0; i < aadSz; i += 16) { const uint8_t *blkAad = aadBytes + i; @@ -935,14 +935,14 @@ whal_Error whal_Stm32wb_AesGcm_Start(whal_AesGcm *dev, whal_Crypto_Dir dir, mode = (dir == WHAL_CRYPTO_ENCRYPT) ? AES_MODE_ENCRYPT : AES_MODE_DECRYPT; - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, mode) | - whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, - AES_GCMPH_PAYLOAD)); + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, mode) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_PAYLOAD)); if (aadSz == 0) - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); { whal_Stm32wb_AesGcm_State *st = @@ -955,7 +955,7 @@ whal_Error whal_Stm32wb_AesGcm_Start(whal_AesGcm *dev, whal_Crypto_Dir dir, return WHAL_SUCCESS; cleanup: - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); ZeroKeyIv(base); return err; } @@ -966,7 +966,7 @@ whal_Error whal_Stm32wb_AesGcm_Process(whal_AesGcm *dev, whal_Crypto *crypto = whal_Stm32wb_AesGcm_Dev.crypto; const whal_Stm32wb_Aes_Cfg *cfg = (const whal_Stm32wb_Aes_Cfg *)crypto->cfg; - size_t base = crypto->base; + uintptr_t base = crypto->base; whal_Stm32wb_AesGcm_State *st = (whal_Stm32wb_AesGcm_State *)whal_Stm32wb_AesGcm_Dev.state; size_t mode; @@ -979,20 +979,20 @@ whal_Error whal_Stm32wb_AesGcm_Process(whal_AesGcm *dev, return WHAL_SUCCESS; if (!in || !out) { - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); ZeroKeyIv(base); return WHAL_EINVAL; } /* Only the last Process call may end in a partial block */ if (st->partial) { - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); ZeroKeyIv(base); return WHAL_EINVAL; } mode = whal_GetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - whal_Reg_Read(base, AES_CR_REG)); + whal_Reg32_Read(base, AES_CR_REG)); for (i = 0; i < sz; i += 16) { const uint8_t *inBlk = (const uint8_t *)in + i; @@ -1005,10 +1005,10 @@ whal_Error whal_Stm32wb_AesGcm_Process(whal_AesGcm *dev, WriteBlock(base, inBlk); } else { if (mode == AES_MODE_ENCRYPT) { - whal_Reg_Update(base, AES_CR_REG, AES_CR_NPBLB_Msk, - whal_SetBits(AES_CR_NPBLB_Msk, - AES_CR_NPBLB_Pos, - 16 - remain)); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_NPBLB_Msk, + whal_SetBits(AES_CR_NPBLB_Msk, + AES_CR_NPBLB_Pos, + 16 - remain)); } for (j = 0; j < remain; j++) block[j] = inBlk[j]; @@ -1017,7 +1017,7 @@ whal_Error whal_Stm32wb_AesGcm_Process(whal_AesGcm *dev, err = WaitForCCF(base, cfg->timeout); if (err) { - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); ZeroKeyIv(base); return err; } @@ -1044,7 +1044,7 @@ whal_Error whal_Stm32wb_AesGcm_Finalize(whal_AesGcm *dev, whal_Crypto *crypto = whal_Stm32wb_AesGcm_Dev.crypto; const whal_Stm32wb_Aes_Cfg *cfg = (const whal_Stm32wb_Aes_Cfg *)crypto->cfg; - size_t base = crypto->base; + uintptr_t base = crypto->base; whal_Stm32wb_AesGcm_State *st = (whal_Stm32wb_AesGcm_State *)whal_Stm32wb_AesGcm_Dev.state; uint8_t tagBuf[16]; @@ -1056,32 +1056,32 @@ whal_Error whal_Stm32wb_AesGcm_Finalize(whal_AesGcm *dev, (void)dev; if (!tag || tagSz == 0 || tagSz > 16) { - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); ZeroKeyIv(base); return WHAL_EINVAL; } /* Final phase (tag) */ - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - AES_MODE_ENCRYPT) | - whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, - AES_GCMPH_FINAL)); + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_ENCRYPT) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_FINAL)); if (st->aadSz == 0 && st->dataSz == 0) - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); aadBits = (uint64_t)st->aadSz * 8; payloadBits = st->dataSz * 8; - whal_Reg_Write(base, AES_DINR_REG, (uint32_t)(aadBits >> 32)); - whal_Reg_Write(base, AES_DINR_REG, (uint32_t)aadBits); - whal_Reg_Write(base, AES_DINR_REG, (uint32_t)(payloadBits >> 32)); - whal_Reg_Write(base, AES_DINR_REG, (uint32_t)payloadBits); + whal_Reg32_Write(base, AES_DINR_REG, (uint32_t)(aadBits >> 32)); + whal_Reg32_Write(base, AES_DINR_REG, (uint32_t)aadBits); + whal_Reg32_Write(base, AES_DINR_REG, (uint32_t)(payloadBits >> 32)); + whal_Reg32_Write(base, AES_DINR_REG, (uint32_t)payloadBits); err = WaitForCCF(base, cfg->timeout); if (err) { - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); ZeroKeyIv(base); return err; } @@ -1091,7 +1091,7 @@ whal_Error whal_Stm32wb_AesGcm_Finalize(whal_AesGcm *dev, for (i = 0; i < tagSz; i++) ((uint8_t *)tag)[i] = tagBuf[i]; - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); ZeroKeyIv(base); return WHAL_SUCCESS; } @@ -1115,7 +1115,7 @@ whal_Error whal_Stm32wb_AesGmac_Oneshot(whal_AesGmac *dev, whal_Crypto *crypto = whal_Stm32wb_AesGmac_Dev.crypto; const whal_Stm32wb_Aes_Cfg *cfg = (const whal_Stm32wb_Aes_Cfg *)crypto->cfg; - size_t base = crypto->base; + uintptr_t base = crypto->base; const uint8_t *ivBytes = (const uint8_t *)iv; const uint8_t *aadBytes = (const uint8_t *)aad; size_t keySizeBit; @@ -1144,31 +1144,31 @@ whal_Error whal_Stm32wb_AesGmac_Oneshot(whal_AesGmac *dev, keySizeBit = (keySz == 32) ? 1 : 0; /* Init phase */ - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); - - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | - AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk | - AES_CR_GCMPH_Msk | AES_CR_NPBLB_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - AES_MODE_ENCRYPT) | - whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, - AES_CHMOD_GCM) | - whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, - AES_DATATYPE_NONE) | - whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, - keySizeBit) | - whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, - AES_GCMPH_INIT)); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | + AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk | + AES_CR_GCMPH_Msk | AES_CR_NPBLB_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_ENCRYPT) | + whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, + AES_CHMOD_GCM) | + whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, + AES_DATATYPE_NONE) | + whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, + keySizeBit) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_INIT)); WriteKey(base, key, keySz); - whal_Reg_Write(base, AES_IVR3_REG, whal_LoadBe32(ivBytes)); - whal_Reg_Write(base, AES_IVR2_REG, whal_LoadBe32(ivBytes + 4)); - whal_Reg_Write(base, AES_IVR1_REG, whal_LoadBe32(ivBytes + 8)); - whal_Reg_Write(base, AES_IVR0_REG, 0x00000002); + whal_Reg32_Write(base, AES_IVR3_REG, whal_LoadBe32(ivBytes)); + whal_Reg32_Write(base, AES_IVR2_REG, whal_LoadBe32(ivBytes + 4)); + whal_Reg32_Write(base, AES_IVR1_REG, whal_LoadBe32(ivBytes + 8)); + whal_Reg32_Write(base, AES_IVR0_REG, 0x00000002); - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); err = WaitForCCF(base, cfg->timeout); if (err) @@ -1176,14 +1176,14 @@ whal_Error whal_Stm32wb_AesGmac_Oneshot(whal_AesGmac *dev, /* Header phase (AAD) */ if (aadSz > 0) { - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - AES_MODE_ENCRYPT) | - whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, - AES_GCMPH_HEADER)); + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_ENCRYPT) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_HEADER)); - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); for (i = 0; i < aadSz; i += 16) { const uint8_t *blkAad = aadBytes + i; @@ -1206,21 +1206,21 @@ whal_Error whal_Stm32wb_AesGmac_Oneshot(whal_AesGmac *dev, } /* Final phase (tag) -- no payload for GMAC */ - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - AES_MODE_ENCRYPT) | - whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, - AES_GCMPH_FINAL)); + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_ENCRYPT) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_FINAL)); if (aadSz == 0) - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); aadBits = (uint64_t)aadSz * 8; - whal_Reg_Write(base, AES_DINR_REG, (uint32_t)(aadBits >> 32)); - whal_Reg_Write(base, AES_DINR_REG, (uint32_t)aadBits); - whal_Reg_Write(base, AES_DINR_REG, 0); - whal_Reg_Write(base, AES_DINR_REG, 0); + whal_Reg32_Write(base, AES_DINR_REG, (uint32_t)(aadBits >> 32)); + whal_Reg32_Write(base, AES_DINR_REG, (uint32_t)aadBits); + whal_Reg32_Write(base, AES_DINR_REG, 0); + whal_Reg32_Write(base, AES_DINR_REG, 0); err = WaitForCCF(base, cfg->timeout); if (err) @@ -1232,7 +1232,7 @@ whal_Error whal_Stm32wb_AesGmac_Oneshot(whal_AesGmac *dev, ((uint8_t *)tag)[i] = tagBuf[i]; cleanup: - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); ZeroKeyIv(base); return err; } @@ -1254,7 +1254,7 @@ whal_Error whal_Stm32wb_AesCcm_Oneshot(whal_AesCcm *dev, whal_Crypto_Dir dir, whal_Crypto *crypto = whal_Stm32wb_AesCcm_Dev.crypto; const whal_Stm32wb_Aes_Cfg *cfg = (const whal_Stm32wb_Aes_Cfg *)crypto->cfg; - size_t base = crypto->base; + uintptr_t base = crypto->base; const uint8_t *nonceBytes = (const uint8_t *)nonce; const uint8_t *aadBytes = (const uint8_t *)aad; size_t keySizeBit; @@ -1312,27 +1312,27 @@ whal_Error whal_Stm32wb_AesCcm_Oneshot(whal_AesCcm *dev, whal_Crypto_Dir dir, } /* Init phase */ - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); - - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | - AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk | - AES_CR_GCMPH_Msk | AES_CR_NPBLB_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - AES_MODE_ENCRYPT) | - whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, 0) | - AES_CR_CHMOD2_Msk | - whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, - AES_DATATYPE_NONE) | - whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, - keySizeBit) | - whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, - AES_GCMPH_INIT)); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | + AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk | + AES_CR_GCMPH_Msk | AES_CR_NPBLB_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_ENCRYPT) | + whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, 0) | + AES_CR_CHMOD2_Msk | + whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, + AES_DATATYPE_NONE) | + whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, + keySizeBit) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_INIT)); WriteKey(base, key, keySz); WriteIv(base, b0); - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); err = WaitForCCF(base, cfg->timeout); if (err) @@ -1340,14 +1340,14 @@ whal_Error whal_Stm32wb_AesCcm_Oneshot(whal_AesCcm *dev, whal_Crypto_Dir dir, /* Header phase (AAD) */ if (aadSz > 0) { - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - AES_MODE_ENCRYPT) | - whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, - AES_GCMPH_HEADER)); + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_ENCRYPT) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_HEADER)); - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); { uint8_t hdrBuf[16] = {0}; @@ -1398,15 +1398,15 @@ whal_Error whal_Stm32wb_AesCcm_Oneshot(whal_AesCcm *dev, whal_Crypto_Dir dir, mode = (dir == WHAL_CRYPTO_ENCRYPT) ? AES_MODE_ENCRYPT : AES_MODE_DECRYPT; - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - mode) | - whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, - AES_GCMPH_PAYLOAD)); + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + mode) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_PAYLOAD)); if (aadSz == 0) - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); for (i = 0; i < sz; i += 16) { const uint8_t *inBlk = (const uint8_t *)in + i; @@ -1419,10 +1419,10 @@ whal_Error whal_Stm32wb_AesCcm_Oneshot(whal_AesCcm *dev, whal_Crypto_Dir dir, WriteBlock(base, inBlk); } else { if (mode == AES_MODE_DECRYPT) { - whal_Reg_Update(base, AES_CR_REG, AES_CR_NPBLB_Msk, - whal_SetBits(AES_CR_NPBLB_Msk, - AES_CR_NPBLB_Pos, - 16 - remain)); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_NPBLB_Msk, + whal_SetBits(AES_CR_NPBLB_Msk, + AES_CR_NPBLB_Pos, + 16 - remain)); } for (j = 0; j < remain; j++) block[j] = inBlk[j]; @@ -1444,20 +1444,20 @@ whal_Error whal_Stm32wb_AesCcm_Oneshot(whal_AesCcm *dev, whal_Crypto_Dir dir, } /* Final phase (tag) */ - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - AES_MODE_ENCRYPT) | - whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, - AES_GCMPH_FINAL)); + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_ENCRYPT) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_FINAL)); if (aadSz == 0 && sz == 0) - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); - whal_Reg_Write(base, AES_DINR_REG, 0); - whal_Reg_Write(base, AES_DINR_REG, 0); - whal_Reg_Write(base, AES_DINR_REG, 0); - whal_Reg_Write(base, AES_DINR_REG, 0); + whal_Reg32_Write(base, AES_DINR_REG, 0); + whal_Reg32_Write(base, AES_DINR_REG, 0); + whal_Reg32_Write(base, AES_DINR_REG, 0); + whal_Reg32_Write(base, AES_DINR_REG, 0); err = WaitForCCF(base, cfg->timeout); if (err) @@ -1469,7 +1469,7 @@ whal_Error whal_Stm32wb_AesCcm_Oneshot(whal_AesCcm *dev, whal_Crypto_Dir dir, ((uint8_t *)tag)[i] = tagBuf[i]; cleanup: - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); ZeroKeyIv(base); return err; } @@ -1483,7 +1483,7 @@ whal_Error whal_Stm32wb_AesCcm_Start(whal_AesCcm *dev, whal_Crypto_Dir dir, whal_Crypto *crypto = whal_Stm32wb_AesCcm_Dev.crypto; const whal_Stm32wb_Aes_Cfg *cfg = (const whal_Stm32wb_Aes_Cfg *)crypto->cfg; - size_t base = crypto->base; + uintptr_t base = crypto->base; const uint8_t *nonceBytes = (const uint8_t *)nonce; const uint8_t *aadBytes = (const uint8_t *)aad; size_t keySizeBit; @@ -1537,27 +1537,27 @@ whal_Error whal_Stm32wb_AesCcm_Start(whal_AesCcm *dev, whal_Crypto_Dir dir, } /* Init phase */ - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); - - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | - AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk | - AES_CR_GCMPH_Msk | AES_CR_NPBLB_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - AES_MODE_ENCRYPT) | - whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, 0) | - AES_CR_CHMOD2_Msk | - whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, - AES_DATATYPE_NONE) | - whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, - keySizeBit) | - whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, - AES_GCMPH_INIT)); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | + AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk | + AES_CR_GCMPH_Msk | AES_CR_NPBLB_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_ENCRYPT) | + whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, 0) | + AES_CR_CHMOD2_Msk | + whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, + AES_DATATYPE_NONE) | + whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, + keySizeBit) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_INIT)); WriteKey(base, key, keySz); WriteIv(base, b0); - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); err = WaitForCCF(base, cfg->timeout); if (err) @@ -1565,14 +1565,14 @@ whal_Error whal_Stm32wb_AesCcm_Start(whal_AesCcm *dev, whal_Crypto_Dir dir, /* Header phase (AAD) */ if (aadSz > 0) { - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - AES_MODE_ENCRYPT) | - whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, - AES_GCMPH_HEADER)); + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_ENCRYPT) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_HEADER)); - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); { uint8_t hdrBuf[16] = {0}; @@ -1622,14 +1622,14 @@ whal_Error whal_Stm32wb_AesCcm_Start(whal_AesCcm *dev, whal_Crypto_Dir dir, mode = (dir == WHAL_CRYPTO_ENCRYPT) ? AES_MODE_ENCRYPT : AES_MODE_DECRYPT; - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, mode) | - whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, - AES_GCMPH_PAYLOAD)); + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, mode) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_PAYLOAD)); if (aadSz == 0) - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); { whal_Stm32wb_AesCcm_State *st = @@ -1644,7 +1644,7 @@ whal_Error whal_Stm32wb_AesCcm_Start(whal_AesCcm *dev, whal_Crypto_Dir dir, return WHAL_SUCCESS; cleanup: - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); ZeroKeyIv(base); return err; } @@ -1655,7 +1655,7 @@ whal_Error whal_Stm32wb_AesCcm_Process(whal_AesCcm *dev, whal_Crypto *crypto = whal_Stm32wb_AesCcm_Dev.crypto; const whal_Stm32wb_Aes_Cfg *cfg = (const whal_Stm32wb_Aes_Cfg *)crypto->cfg; - size_t base = crypto->base; + uintptr_t base = crypto->base; whal_Stm32wb_AesCcm_State *st = (whal_Stm32wb_AesCcm_State *)whal_Stm32wb_AesCcm_Dev.state; size_t mode; @@ -1668,7 +1668,7 @@ whal_Error whal_Stm32wb_AesCcm_Process(whal_AesCcm *dev, return WHAL_SUCCESS; if (!in || !out) { - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); ZeroKeyIv(base); return WHAL_EINVAL; } @@ -1676,13 +1676,13 @@ whal_Error whal_Stm32wb_AesCcm_Process(whal_AesCcm *dev, /* Only the last Process call may end in a partial block, and the * total may not exceed the payload length declared at Start */ if (st->partial || sz > st->msgSz - st->dataSz) { - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); ZeroKeyIv(base); return WHAL_EINVAL; } mode = whal_GetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - whal_Reg_Read(base, AES_CR_REG)); + whal_Reg32_Read(base, AES_CR_REG)); for (i = 0; i < sz; i += 16) { const uint8_t *inBlk = (const uint8_t *)in + i; @@ -1695,10 +1695,10 @@ whal_Error whal_Stm32wb_AesCcm_Process(whal_AesCcm *dev, WriteBlock(base, inBlk); } else { if (mode == AES_MODE_DECRYPT) { - whal_Reg_Update(base, AES_CR_REG, AES_CR_NPBLB_Msk, - whal_SetBits(AES_CR_NPBLB_Msk, - AES_CR_NPBLB_Pos, - 16 - remain)); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_NPBLB_Msk, + whal_SetBits(AES_CR_NPBLB_Msk, + AES_CR_NPBLB_Pos, + 16 - remain)); } for (j = 0; j < remain; j++) block[j] = inBlk[j]; @@ -1707,7 +1707,7 @@ whal_Error whal_Stm32wb_AesCcm_Process(whal_AesCcm *dev, err = WaitForCCF(base, cfg->timeout); if (err) { - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); ZeroKeyIv(base); return err; } @@ -1734,7 +1734,7 @@ whal_Error whal_Stm32wb_AesCcm_Finalize(whal_AesCcm *dev, whal_Crypto *crypto = whal_Stm32wb_AesCcm_Dev.crypto; const whal_Stm32wb_Aes_Cfg *cfg = (const whal_Stm32wb_Aes_Cfg *)crypto->cfg; - size_t base = crypto->base; + uintptr_t base = crypto->base; whal_Stm32wb_AesCcm_State *st = (whal_Stm32wb_AesCcm_State *)whal_Stm32wb_AesCcm_Dev.state; uint8_t tagBuf[16]; @@ -1746,30 +1746,30 @@ whal_Error whal_Stm32wb_AesCcm_Finalize(whal_AesCcm *dev, /* Tag length and payload length must match what Start encoded in B0 */ if (!tag || tagSz < 4 || tagSz > 16 || (tagSz & 1) != 0 || tagSz != st->tagSz || st->dataSz != st->msgSz) { - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); ZeroKeyIv(base); return WHAL_EINVAL; } /* Final phase (tag) */ - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - AES_MODE_ENCRYPT) | - whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, - AES_GCMPH_FINAL)); + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_ENCRYPT) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_FINAL)); if (st->aadSz == 0 && st->dataSz == 0) - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); - whal_Reg_Write(base, AES_DINR_REG, 0); - whal_Reg_Write(base, AES_DINR_REG, 0); - whal_Reg_Write(base, AES_DINR_REG, 0); - whal_Reg_Write(base, AES_DINR_REG, 0); + whal_Reg32_Write(base, AES_DINR_REG, 0); + whal_Reg32_Write(base, AES_DINR_REG, 0); + whal_Reg32_Write(base, AES_DINR_REG, 0); + whal_Reg32_Write(base, AES_DINR_REG, 0); err = WaitForCCF(base, cfg->timeout); if (err) { - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); ZeroKeyIv(base); return err; } @@ -1779,7 +1779,7 @@ whal_Error whal_Stm32wb_AesCcm_Finalize(whal_AesCcm *dev, for (i = 0; i < tagSz; i++) ((uint8_t *)tag)[i] = tagBuf[i]; - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); ZeroKeyIv(base); return WHAL_SUCCESS; } diff --git a/src/crypto/stm32wb_pka.c b/src/crypto/stm32wb_pka.c index be09346a..9fe82868 100644 --- a/src/crypto/stm32wb_pka.c +++ b/src/crypto/stm32wb_pka.c @@ -166,7 +166,7 @@ const whal_Crypto whal_Stm32wb_Pka_Dev = WHAL_CFG_STM32WB_PKA_DEV; /* Write a big-endian integer into the PKA RAM at offset as a little-endian * 32-bit word array, with the mandatory trailing zero word. */ -static void WriteOperand(size_t base, size_t offset, +static void WriteOperand(uintptr_t base, size_t offset, const uint8_t *data, size_t dataSz) { size_t numWords = (dataSz + 3) / 4; @@ -179,20 +179,20 @@ static void WriteOperand(size_t base, size_t offset, if (bytePos < dataSz) word |= (uint32_t)data[dataSz - 1 - bytePos] << (b * 8); } - whal_Reg_Write(base, offset + i * 4, word); + whal_Reg32_Write(base, offset + i * 4, word); } - whal_Reg_Write(base, offset + numWords * 4, 0); + whal_Reg32_Write(base, offset + numWords * 4, 0); } /* Read a little-endian word array from PKA RAM into a big-endian byte array. */ -static void ReadOperand(size_t base, size_t offset, +static void ReadOperand(uintptr_t base, size_t offset, uint8_t *data, size_t dataSz) { size_t numWords = (dataSz + 3) / 4; size_t i, b; for (i = 0; i < numWords; i++) { - uint32_t word = whal_Reg_Read(base, offset + i * 4); + uint32_t word = whal_Reg32_Read(base, offset + i * 4); for (b = 0; b < 4; b++) { size_t bytePos = i * 4 + b; if (bytePos < dataSz) @@ -205,24 +205,24 @@ static void ReadOperand(size_t base, size_t offset, * numWords data words plus the one trailing word. Called after every op, * whatever its result, so the PKA RAM never carries stale operand or result * bytes into the next operation. */ -static void ZeroOperand(size_t base, size_t offset, size_t dataSz) +static void ZeroOperand(uintptr_t base, size_t offset, size_t dataSz) { size_t numWords = (dataSz + 3) / 4; size_t i; for (i = 0; i <= numWords; i++) - whal_Reg_Write(base, offset + i * 4, 0); + whal_Reg32_Write(base, offset + i * 4, 0); } -static void ZeroRam(size_t base) +static void ZeroRam(uintptr_t base) { size_t off; for (off = 0; off < PKA_RAM_SIZE; off += 4) - whal_Reg_Write(base, PKA_RAM_REG + off, 0); + whal_Reg32_Write(base, PKA_RAM_REG + off, 0); } -static whal_Error WaitForProcEnd(size_t base, whal_Timeout *timeout) +static whal_Error WaitForProcEnd(uintptr_t base, whal_Timeout *timeout) { const uint32_t errFlags = PKA_SR_ADDRERRF_Msk | PKA_SR_RAMERRF_Msk; const uint32_t doneFlags = errFlags | PKA_SR_PROCENDF_Msk; @@ -233,16 +233,16 @@ static whal_Error WaitForProcEnd(size_t base, whal_Timeout *timeout) WHAL_TIMEOUT_START(timeout); while (1) { - uint32_t sr = whal_Reg_Read(base, PKA_SR_REG); + uint32_t sr = whal_Reg32_Read(base, PKA_SR_REG); if (sr & doneFlags) { - whal_Reg_Write(base, PKA_CLRFR_REG, clrFlags); + whal_Reg32_Write(base, PKA_CLRFR_REG, clrFlags); return (sr & errFlags) ? WHAL_EHARDWARE : WHAL_SUCCESS; } if (WHAL_TIMEOUT_EXPIRED(timeout)) { /* Abort the operation so the PKA RAM is writable again */ - whal_Reg_Update(base, PKA_CR_REG, PKA_CR_EN_Msk, 0); - whal_Reg_Write(base, PKA_CLRFR_REG, clrFlags); - whal_Reg_Update(base, PKA_CR_REG, PKA_CR_EN_Msk, PKA_CR_EN_Msk); + whal_Reg32_Update(base, PKA_CR_REG, PKA_CR_EN_Msk, 0); + whal_Reg32_Write(base, PKA_CLRFR_REG, clrFlags); + whal_Reg32_Update(base, PKA_CR_REG, PKA_CR_EN_Msk, PKA_CR_EN_Msk); return WHAL_ETIMEOUT; } } @@ -252,18 +252,18 @@ static whal_Error WaitForProcEnd(size_t base, whal_Timeout *timeout) whal_Error whal_Stm32wb_Pka_Init(whal_Crypto *dev) { - size_t base = whal_Stm32wb_Pka_Dev.base; + uintptr_t base = whal_Stm32wb_Pka_Dev.base; (void)dev; - whal_Reg_Update(base, PKA_CR_REG, PKA_CR_EN_Msk, PKA_CR_EN_Msk); + whal_Reg32_Update(base, PKA_CR_REG, PKA_CR_EN_Msk, PKA_CR_EN_Msk); return WHAL_SUCCESS; } whal_Error whal_Stm32wb_Pka_Deinit(whal_Crypto *dev) { - size_t base = whal_Stm32wb_Pka_Dev.base; + uintptr_t base = whal_Stm32wb_Pka_Dev.base; (void)dev; ZeroRam(base); - whal_Reg_Update(base, PKA_CR_REG, PKA_CR_EN_Msk, 0); + whal_Reg32_Update(base, PKA_CR_REG, PKA_CR_EN_Msk, 0); return WHAL_SUCCESS; } @@ -279,7 +279,7 @@ whal_Error whal_Stm32wb_Pka_ModExp(const uint8_t *A, size_t ASz, const uint8_t *N, size_t NSz, uint8_t *result, size_t resultSz) { - size_t base = whal_Stm32wb_Pka_Dev.base; + uintptr_t base = whal_Stm32wb_Pka_Dev.base; const whal_Stm32wb_Pka_Cfg *cfg = (const whal_Stm32wb_Pka_Cfg *)whal_Stm32wb_Pka_Dev.cfg; whal_Error err; @@ -291,22 +291,22 @@ whal_Error whal_Stm32wb_Pka_ModExp(const uint8_t *A, size_t ASz, ASz != NSz || eSz != NSz || resultSz != NSz) return WHAL_ENOTSUP; - whal_Reg_Write(base, PKA_MODEXP_EXP_LEN, (uint32_t)(eSz * 8)); - whal_Reg_Write(base, PKA_MODEXP_OP_LEN, (uint32_t)(NSz * 8)); + whal_Reg32_Write(base, PKA_MODEXP_EXP_LEN, (uint32_t)(eSz * 8)); + whal_Reg32_Write(base, PKA_MODEXP_OP_LEN, (uint32_t)(NSz * 8)); WriteOperand(base, PKA_MODEXP_A, A, ASz); WriteOperand(base, PKA_MODEXP_E, e, eSz); WriteOperand(base, PKA_MODEXP_N, N, NSz); - whal_Reg_Update(base, PKA_CR_REG, PKA_CR_MODE_Msk, - (uint32_t)PKA_MODE_MODEXP_NORMAL << PKA_CR_MODE_Pos); - whal_Reg_Update(base, PKA_CR_REG, PKA_CR_START_Msk, PKA_CR_START_Msk); + whal_Reg32_Update(base, PKA_CR_REG, PKA_CR_MODE_Msk, + (uint32_t)PKA_MODE_MODEXP_NORMAL << PKA_CR_MODE_Pos); + whal_Reg32_Update(base, PKA_CR_REG, PKA_CR_START_Msk, PKA_CR_START_Msk); err = WaitForProcEnd(base, cfg->timeout); if (err == WHAL_SUCCESS) ReadOperand(base, PKA_MODEXP_RESULT, result, resultSz); - whal_Reg_Write(base, PKA_MODEXP_EXP_LEN, 0); - whal_Reg_Write(base, PKA_MODEXP_OP_LEN, 0); + whal_Reg32_Write(base, PKA_MODEXP_EXP_LEN, 0); + whal_Reg32_Write(base, PKA_MODEXP_OP_LEN, 0); ZeroOperand(base, PKA_MODEXP_A, ASz); ZeroOperand(base, PKA_MODEXP_E, eSz); ZeroOperand(base, PKA_MODEXP_N, NSz); @@ -318,7 +318,7 @@ whal_Error whal_Stm32wb_Pka_ModInv(const uint8_t *A, size_t ASz, const uint8_t *N, size_t NSz, uint8_t *result, size_t resultSz) { - size_t base = whal_Stm32wb_Pka_Dev.base; + uintptr_t base = whal_Stm32wb_Pka_Dev.base; const whal_Stm32wb_Pka_Cfg *cfg = (const whal_Stm32wb_Pka_Cfg *)whal_Stm32wb_Pka_Dev.cfg; whal_Error err; @@ -329,19 +329,19 @@ whal_Error whal_Stm32wb_Pka_ModInv(const uint8_t *A, size_t ASz, if (NSz * 8 > 3136 || ASz != NSz || resultSz != NSz) return WHAL_ENOTSUP; - whal_Reg_Write(base, PKA_MODINV_OP_LEN, (uint32_t)(NSz * 8)); + whal_Reg32_Write(base, PKA_MODINV_OP_LEN, (uint32_t)(NSz * 8)); WriteOperand(base, PKA_MODINV_A, A, ASz); WriteOperand(base, PKA_MODINV_N, N, NSz); - whal_Reg_Update(base, PKA_CR_REG, PKA_CR_MODE_Msk, - (uint32_t)PKA_MODE_MODINV << PKA_CR_MODE_Pos); - whal_Reg_Update(base, PKA_CR_REG, PKA_CR_START_Msk, PKA_CR_START_Msk); + whal_Reg32_Update(base, PKA_CR_REG, PKA_CR_MODE_Msk, + (uint32_t)PKA_MODE_MODINV << PKA_CR_MODE_Pos); + whal_Reg32_Update(base, PKA_CR_REG, PKA_CR_START_Msk, PKA_CR_START_Msk); err = WaitForProcEnd(base, cfg->timeout); if (err == WHAL_SUCCESS) ReadOperand(base, PKA_MODINV_RESULT, result, resultSz); - whal_Reg_Write(base, PKA_MODINV_OP_LEN, 0); + whal_Reg32_Write(base, PKA_MODINV_OP_LEN, 0); ZeroOperand(base, PKA_MODINV_A, ASz); ZeroOperand(base, PKA_MODINV_N, NSz); ZeroOperand(base, PKA_MODINV_RESULT, resultSz); @@ -352,7 +352,7 @@ whal_Error whal_Stm32wb_Pka_ModReduce(const uint8_t *A, size_t ASz, const uint8_t *N, size_t NSz, uint8_t *result, size_t resultSz) { - size_t base = whal_Stm32wb_Pka_Dev.base; + uintptr_t base = whal_Stm32wb_Pka_Dev.base; const whal_Stm32wb_Pka_Cfg *cfg = (const whal_Stm32wb_Pka_Cfg *)whal_Stm32wb_Pka_Dev.cfg; whal_Error err; @@ -363,21 +363,21 @@ whal_Error whal_Stm32wb_Pka_ModReduce(const uint8_t *A, size_t ASz, if (NSz * 8 > 3136 || ASz != NSz || resultSz != NSz) return WHAL_ENOTSUP; - whal_Reg_Write(base, PKA_MOD_REDUCE_OP_LEN, (uint32_t)(ASz * 8)); - whal_Reg_Write(base, PKA_MOD_REDUCE_MOD_LEN, (uint32_t)(NSz * 8)); + whal_Reg32_Write(base, PKA_MOD_REDUCE_OP_LEN, (uint32_t)(ASz * 8)); + whal_Reg32_Write(base, PKA_MOD_REDUCE_MOD_LEN, (uint32_t)(NSz * 8)); WriteOperand(base, PKA_MOD_REDUCE_A, A, ASz); WriteOperand(base, PKA_MOD_REDUCE_N, N, NSz); - whal_Reg_Update(base, PKA_CR_REG, PKA_CR_MODE_Msk, - (uint32_t)PKA_MODE_MOD_REDUCE << PKA_CR_MODE_Pos); - whal_Reg_Update(base, PKA_CR_REG, PKA_CR_START_Msk, PKA_CR_START_Msk); + whal_Reg32_Update(base, PKA_CR_REG, PKA_CR_MODE_Msk, + (uint32_t)PKA_MODE_MOD_REDUCE << PKA_CR_MODE_Pos); + whal_Reg32_Update(base, PKA_CR_REG, PKA_CR_START_Msk, PKA_CR_START_Msk); err = WaitForProcEnd(base, cfg->timeout); if (err == WHAL_SUCCESS) ReadOperand(base, PKA_MOD_REDUCE_RESULT, result, resultSz); - whal_Reg_Write(base, PKA_MOD_REDUCE_OP_LEN, 0); - whal_Reg_Write(base, PKA_MOD_REDUCE_MOD_LEN, 0); + whal_Reg32_Write(base, PKA_MOD_REDUCE_OP_LEN, 0); + whal_Reg32_Write(base, PKA_MOD_REDUCE_MOD_LEN, 0); ZeroOperand(base, PKA_MOD_REDUCE_A, ASz); ZeroOperand(base, PKA_MOD_REDUCE_N, NSz); ZeroOperand(base, PKA_MOD_REDUCE_RESULT, resultSz); @@ -388,7 +388,7 @@ whal_Error whal_Stm32wb_Pka_IntMul(const uint8_t *A, size_t ASz, const uint8_t *B, size_t BSz, uint8_t *result, size_t resultSz) { - size_t base = whal_Stm32wb_Pka_Dev.base; + uintptr_t base = whal_Stm32wb_Pka_Dev.base; const whal_Stm32wb_Pka_Cfg *cfg = (const whal_Stm32wb_Pka_Cfg *)whal_Stm32wb_Pka_Dev.cfg; whal_Error err; @@ -399,19 +399,19 @@ whal_Error whal_Stm32wb_Pka_IntMul(const uint8_t *A, size_t ASz, if (ASz * 8 > 3136 || ASz != BSz || resultSz != 2 * ASz) return WHAL_ENOTSUP; - whal_Reg_Write(base, PKA_INT_MUL_OP_LEN, (uint32_t)(ASz * 8)); + whal_Reg32_Write(base, PKA_INT_MUL_OP_LEN, (uint32_t)(ASz * 8)); WriteOperand(base, PKA_INT_MUL_A, A, ASz); WriteOperand(base, PKA_INT_MUL_B, B, BSz); - whal_Reg_Update(base, PKA_CR_REG, PKA_CR_MODE_Msk, - (uint32_t)PKA_MODE_INT_MUL << PKA_CR_MODE_Pos); - whal_Reg_Update(base, PKA_CR_REG, PKA_CR_START_Msk, PKA_CR_START_Msk); + whal_Reg32_Update(base, PKA_CR_REG, PKA_CR_MODE_Msk, + (uint32_t)PKA_MODE_INT_MUL << PKA_CR_MODE_Pos); + whal_Reg32_Update(base, PKA_CR_REG, PKA_CR_START_Msk, PKA_CR_START_Msk); err = WaitForProcEnd(base, cfg->timeout); if (err == WHAL_SUCCESS) ReadOperand(base, PKA_INT_MUL_RESULT, result, resultSz); - whal_Reg_Write(base, PKA_INT_MUL_OP_LEN, 0); + whal_Reg32_Write(base, PKA_INT_MUL_OP_LEN, 0); ZeroOperand(base, PKA_INT_MUL_A, ASz); ZeroOperand(base, PKA_INT_MUL_B, BSz); ZeroOperand(base, PKA_INT_MUL_RESULT, resultSz); @@ -422,7 +422,7 @@ whal_Error whal_Stm32wb_Pka_IntSub(const uint8_t *A, size_t ASz, const uint8_t *B, size_t BSz, uint8_t *result, size_t resultSz) { - size_t base = whal_Stm32wb_Pka_Dev.base; + uintptr_t base = whal_Stm32wb_Pka_Dev.base; const whal_Stm32wb_Pka_Cfg *cfg = (const whal_Stm32wb_Pka_Cfg *)whal_Stm32wb_Pka_Dev.cfg; whal_Error err; @@ -433,19 +433,19 @@ whal_Error whal_Stm32wb_Pka_IntSub(const uint8_t *A, size_t ASz, if (ASz * 8 > 3136 || ASz != BSz || resultSz != ASz) return WHAL_ENOTSUP; - whal_Reg_Write(base, PKA_INT_SUB_OP_LEN, (uint32_t)(ASz * 8)); + whal_Reg32_Write(base, PKA_INT_SUB_OP_LEN, (uint32_t)(ASz * 8)); WriteOperand(base, PKA_INT_SUB_A, A, ASz); WriteOperand(base, PKA_INT_SUB_B, B, BSz); - whal_Reg_Update(base, PKA_CR_REG, PKA_CR_MODE_Msk, - (uint32_t)PKA_MODE_INT_SUB << PKA_CR_MODE_Pos); - whal_Reg_Update(base, PKA_CR_REG, PKA_CR_START_Msk, PKA_CR_START_Msk); + whal_Reg32_Update(base, PKA_CR_REG, PKA_CR_MODE_Msk, + (uint32_t)PKA_MODE_INT_SUB << PKA_CR_MODE_Pos); + whal_Reg32_Update(base, PKA_CR_REG, PKA_CR_START_Msk, PKA_CR_START_Msk); err = WaitForProcEnd(base, cfg->timeout); if (err == WHAL_SUCCESS) ReadOperand(base, PKA_INT_SUB_RESULT, result, resultSz); - whal_Reg_Write(base, PKA_INT_SUB_OP_LEN, 0); + whal_Reg32_Write(base, PKA_INT_SUB_OP_LEN, 0); ZeroOperand(base, PKA_INT_SUB_A, ASz); ZeroOperand(base, PKA_INT_SUB_B, BSz); ZeroOperand(base, PKA_INT_SUB_RESULT, resultSz); @@ -460,7 +460,7 @@ whal_Error whal_Stm32wb_Pka_RsaCrtExp(const uint8_t *A, size_t ASz, const uint8_t *q, size_t qSz, uint8_t *result, size_t resultSz) { - size_t base = whal_Stm32wb_Pka_Dev.base; + uintptr_t base = whal_Stm32wb_Pka_Dev.base; const whal_Stm32wb_Pka_Cfg *cfg = (const whal_Stm32wb_Pka_Cfg *)whal_Stm32wb_Pka_Dev.cfg; whal_Error err; @@ -475,8 +475,8 @@ whal_Error whal_Stm32wb_Pka_RsaCrtExp(const uint8_t *A, size_t ASz, ASz != pSz + qSz || resultSz != pSz + qSz) return WHAL_ENOTSUP; - whal_Reg_Write(base, PKA_RSA_CRT_OP_LEN, - (uint32_t)((pSz + qSz) * 8)); + whal_Reg32_Write(base, PKA_RSA_CRT_OP_LEN, + (uint32_t)((pSz + qSz) * 8)); WriteOperand(base, PKA_RSA_CRT_DP, dP, dPSz); WriteOperand(base, PKA_RSA_CRT_DQ, dQ, dQSz); WriteOperand(base, PKA_RSA_CRT_QINV, qInv, qInvSz); @@ -484,15 +484,15 @@ whal_Error whal_Stm32wb_Pka_RsaCrtExp(const uint8_t *A, size_t ASz, WriteOperand(base, PKA_RSA_CRT_Q, q, qSz); WriteOperand(base, PKA_RSA_CRT_A, A, ASz); - whal_Reg_Update(base, PKA_CR_REG, PKA_CR_MODE_Msk, - (uint32_t)PKA_MODE_RSA_CRT_EXP << PKA_CR_MODE_Pos); - whal_Reg_Update(base, PKA_CR_REG, PKA_CR_START_Msk, PKA_CR_START_Msk); + whal_Reg32_Update(base, PKA_CR_REG, PKA_CR_MODE_Msk, + (uint32_t)PKA_MODE_RSA_CRT_EXP << PKA_CR_MODE_Pos); + whal_Reg32_Update(base, PKA_CR_REG, PKA_CR_START_Msk, PKA_CR_START_Msk); err = WaitForProcEnd(base, cfg->timeout); if (err == WHAL_SUCCESS) ReadOperand(base, PKA_RSA_CRT_RESULT, result, resultSz); - whal_Reg_Write(base, PKA_RSA_CRT_OP_LEN, 0); + whal_Reg32_Write(base, PKA_RSA_CRT_OP_LEN, 0); ZeroOperand(base, PKA_RSA_CRT_DP, dPSz); ZeroOperand(base, PKA_RSA_CRT_DQ, dQSz); ZeroOperand(base, PKA_RSA_CRT_QINV, qInvSz); diff --git a/src/crypto/stm32wba_aes.c b/src/crypto/stm32wba_aes.c index 486f7824..7d2dac09 100644 --- a/src/crypto/stm32wba_aes.c +++ b/src/crypto/stm32wba_aes.c @@ -135,96 +135,96 @@ const whal_AesCcm whal_Stm32wba_AesCcm_Dev = WHAL_CFG_STM32WBA_AES_CCM_DEV; #define AES_GCMPH_PAYLOAD 0x2 #define AES_GCMPH_FINAL 0x3 -static void WriteKey(size_t base, const uint8_t *key, size_t keySz) +static void WriteKey(uintptr_t base, const uint8_t *key, size_t keySz) { const uint8_t *k = key; if (keySz == 32) { - whal_Reg_Write(base, AES_KEYR7_REG, whal_LoadBe32(k)); - whal_Reg_Write(base, AES_KEYR6_REG, whal_LoadBe32(k + 4)); - whal_Reg_Write(base, AES_KEYR5_REG, whal_LoadBe32(k + 8)); - whal_Reg_Write(base, AES_KEYR4_REG, whal_LoadBe32(k + 12)); + whal_Reg32_Write(base, AES_KEYR7_REG, whal_LoadBe32(k)); + whal_Reg32_Write(base, AES_KEYR6_REG, whal_LoadBe32(k + 4)); + whal_Reg32_Write(base, AES_KEYR5_REG, whal_LoadBe32(k + 8)); + whal_Reg32_Write(base, AES_KEYR4_REG, whal_LoadBe32(k + 12)); k += 16; } - whal_Reg_Write(base, AES_KEYR3_REG, whal_LoadBe32(k)); - whal_Reg_Write(base, AES_KEYR2_REG, whal_LoadBe32(k + 4)); - whal_Reg_Write(base, AES_KEYR1_REG, whal_LoadBe32(k + 8)); - whal_Reg_Write(base, AES_KEYR0_REG, whal_LoadBe32(k + 12)); + whal_Reg32_Write(base, AES_KEYR3_REG, whal_LoadBe32(k)); + whal_Reg32_Write(base, AES_KEYR2_REG, whal_LoadBe32(k + 4)); + whal_Reg32_Write(base, AES_KEYR1_REG, whal_LoadBe32(k + 8)); + whal_Reg32_Write(base, AES_KEYR0_REG, whal_LoadBe32(k + 12)); } -static void WriteIv(size_t base, const uint8_t *iv) +static void WriteIv(uintptr_t base, const uint8_t *iv) { - whal_Reg_Write(base, AES_IVR3_REG, whal_LoadBe32(iv)); - whal_Reg_Write(base, AES_IVR2_REG, whal_LoadBe32(iv + 4)); - whal_Reg_Write(base, AES_IVR1_REG, whal_LoadBe32(iv + 8)); - whal_Reg_Write(base, AES_IVR0_REG, whal_LoadBe32(iv + 12)); + whal_Reg32_Write(base, AES_IVR3_REG, whal_LoadBe32(iv)); + whal_Reg32_Write(base, AES_IVR2_REG, whal_LoadBe32(iv + 4)); + whal_Reg32_Write(base, AES_IVR1_REG, whal_LoadBe32(iv + 8)); + whal_Reg32_Write(base, AES_IVR0_REG, whal_LoadBe32(iv + 12)); } /* Wipe key and IV/counter material from the peripheral registers. Callers must * clear EN first (key registers are only writable while disabled). */ -static void ZeroKeyIv(size_t base) +static void ZeroKeyIv(uintptr_t base) { /* KEYSIZE must cover all eight key registers or the write sequence raises KEIF */ - whal_Reg_Update(base, AES_CR_REG, AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Msk); - whal_Reg_Write(base, AES_KEYR7_REG, 0); - whal_Reg_Write(base, AES_KEYR6_REG, 0); - whal_Reg_Write(base, AES_KEYR5_REG, 0); - whal_Reg_Write(base, AES_KEYR4_REG, 0); - whal_Reg_Write(base, AES_KEYR3_REG, 0); - whal_Reg_Write(base, AES_KEYR2_REG, 0); - whal_Reg_Write(base, AES_KEYR1_REG, 0); - whal_Reg_Write(base, AES_KEYR0_REG, 0); - whal_Reg_Write(base, AES_IVR3_REG, 0); - whal_Reg_Write(base, AES_IVR2_REG, 0); - whal_Reg_Write(base, AES_IVR1_REG, 0); - whal_Reg_Write(base, AES_IVR0_REG, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Msk); + whal_Reg32_Write(base, AES_KEYR7_REG, 0); + whal_Reg32_Write(base, AES_KEYR6_REG, 0); + whal_Reg32_Write(base, AES_KEYR5_REG, 0); + whal_Reg32_Write(base, AES_KEYR4_REG, 0); + whal_Reg32_Write(base, AES_KEYR3_REG, 0); + whal_Reg32_Write(base, AES_KEYR2_REG, 0); + whal_Reg32_Write(base, AES_KEYR1_REG, 0); + whal_Reg32_Write(base, AES_KEYR0_REG, 0); + whal_Reg32_Write(base, AES_IVR3_REG, 0); + whal_Reg32_Write(base, AES_IVR2_REG, 0); + whal_Reg32_Write(base, AES_IVR1_REG, 0); + whal_Reg32_Write(base, AES_IVR0_REG, 0); } -static void WriteBlock(size_t base, const uint8_t *in) +static void WriteBlock(uintptr_t base, const uint8_t *in) { - whal_Reg_Write(base, AES_DINR_REG, whal_LoadBe32(in)); - whal_Reg_Write(base, AES_DINR_REG, whal_LoadBe32(in + 4)); - whal_Reg_Write(base, AES_DINR_REG, whal_LoadBe32(in + 8)); - whal_Reg_Write(base, AES_DINR_REG, whal_LoadBe32(in + 12)); + whal_Reg32_Write(base, AES_DINR_REG, whal_LoadBe32(in)); + whal_Reg32_Write(base, AES_DINR_REG, whal_LoadBe32(in + 4)); + whal_Reg32_Write(base, AES_DINR_REG, whal_LoadBe32(in + 8)); + whal_Reg32_Write(base, AES_DINR_REG, whal_LoadBe32(in + 12)); } -static void ReadBlock(size_t base, uint8_t *out) +static void ReadBlock(uintptr_t base, uint8_t *out) { - whal_StoreBe32(out, whal_Reg_Read(base, AES_DOUTR_REG)); - whal_StoreBe32(out + 4, whal_Reg_Read(base, AES_DOUTR_REG)); - whal_StoreBe32(out + 8, whal_Reg_Read(base, AES_DOUTR_REG)); - whal_StoreBe32(out + 12, whal_Reg_Read(base, AES_DOUTR_REG)); + whal_StoreBe32(out, whal_Reg32_Read(base, AES_DOUTR_REG)); + whal_StoreBe32(out + 4, whal_Reg32_Read(base, AES_DOUTR_REG)); + whal_StoreBe32(out + 8, whal_Reg32_Read(base, AES_DOUTR_REG)); + whal_StoreBe32(out + 12, whal_Reg32_Read(base, AES_DOUTR_REG)); } /* Discard any output block left in DOUTR. */ -static void DrainOutput(size_t base) +static void DrainOutput(uintptr_t base) { - (void)whal_Reg_Read(base, AES_DOUTR_REG); - (void)whal_Reg_Read(base, AES_DOUTR_REG); - (void)whal_Reg_Read(base, AES_DOUTR_REG); - (void)whal_Reg_Read(base, AES_DOUTR_REG); + (void)whal_Reg32_Read(base, AES_DOUTR_REG); + (void)whal_Reg32_Read(base, AES_DOUTR_REG); + (void)whal_Reg32_Read(base, AES_DOUTR_REG); + (void)whal_Reg32_Read(base, AES_DOUTR_REG); } -static whal_Error WaitForCCF(size_t base, whal_Timeout *timeout) +static whal_Error WaitForCCF(uintptr_t base, whal_Timeout *timeout) { whal_Error err; - err = whal_Reg_ReadPoll(base, AES_ISR_REG, AES_ISR_CCF_Msk, - AES_ISR_CCF_Msk, timeout); + err = whal_Reg32_ReadPoll(base, AES_ISR_REG, AES_ISR_CCF_Msk, + AES_ISR_CCF_Msk, timeout); if (err) { DrainOutput(base); return err; } - whal_Reg_Write(base, AES_ICR_REG, AES_ICR_CCF_Msk); + whal_Reg32_Write(base, AES_ICR_REG, AES_ICR_CCF_Msk); return WHAL_SUCCESS; } /* Write the key and wait for KEYVALID. KEYSIZE must already be programmed. */ -static inline whal_Error LoadKey(size_t base, const uint8_t *key, size_t keySz, +static inline whal_Error LoadKey(uintptr_t base, const uint8_t *key, size_t keySz, whal_Timeout *timeout) { - whal_Reg_Write(base, AES_ICR_REG, AES_ICR_KEIF_Msk); + whal_Reg32_Write(base, AES_ICR_REG, AES_ICR_KEIF_Msk); WriteKey(base, key, keySz); - return whal_Reg_ReadPoll(base, AES_SR_REG, AES_SR_KEYVALID_Msk, - AES_SR_KEYVALID_Msk, timeout); + return whal_Reg32_ReadPoll(base, AES_SR_REG, AES_SR_KEYVALID_Msk, + AES_SR_KEYVALID_Msk, timeout); } static whal_Error ProcessBlockCipher(whal_Crypto *cryptoDev, @@ -233,7 +233,7 @@ static whal_Error ProcessBlockCipher(whal_Crypto *cryptoDev, { const whal_Stm32wba_Aes_Cfg *cfg = (const whal_Stm32wba_Aes_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->base; + uintptr_t base = cryptoDev->base; whal_Error err; size_t i; @@ -241,7 +241,7 @@ static whal_Error ProcessBlockCipher(whal_Crypto *cryptoDev, return WHAL_SUCCESS; if (!in || !out || (sz & 0xF) != 0) { - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); ZeroKeyIv(base); return WHAL_EINVAL; } @@ -250,7 +250,7 @@ static whal_Error ProcessBlockCipher(whal_Crypto *cryptoDev, WriteBlock(base, in + i); err = WaitForCCF(base, cfg->timeout); if (err) { - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); ZeroKeyIv(base); return err; } @@ -262,7 +262,7 @@ static whal_Error ProcessBlockCipher(whal_Crypto *cryptoDev, static void DisableAes(whal_Crypto *cryptoDev) { - whal_Reg_Update(cryptoDev->base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(cryptoDev->base, AES_CR_REG, AES_CR_EN_Msk, 0); } static whal_Error StopBlockCipher(whal_Crypto *cryptoDev) @@ -346,7 +346,7 @@ whal_Error whal_Stm32wba_AesEcb_Oneshot(whal_AesEcb *dev, whal_Crypto_Dir dir, whal_Crypto *crypto = whal_Stm32wba_AesEcb_Dev.crypto; const whal_Stm32wba_Aes_Cfg *cfg = (const whal_Stm32wba_Aes_Cfg *)crypto->cfg; - size_t base = crypto->base; + uintptr_t base = crypto->base; size_t mode; size_t keySizeBit; whal_Error err; @@ -363,34 +363,34 @@ whal_Error whal_Stm32wba_AesEcb_Oneshot(whal_AesEcb *dev, whal_Crypto_Dir dir, mode = (dir == WHAL_CRYPTO_ENCRYPT) ? AES_MODE_ENCRYPT : AES_MODE_KEYPREP; - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | - AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, mode) | - whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, - AES_CHMOD_ECB) | - whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, - AES_DATATYPE_NONE) | - whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, - keySizeBit)); + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | + AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, mode) | + whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, + AES_CHMOD_ECB) | + whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, + AES_DATATYPE_NONE) | + whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, + keySizeBit)); err = LoadKey(base, key, keySz, cfg->timeout); if (err) goto cleanup; if (dir == WHAL_CRYPTO_DECRYPT) { /* Decryption round key preparation; AES disables itself when done */ - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); err = WaitForCCF(base, cfg->timeout); if (err) goto cleanup; - whal_Reg_Update(base, AES_CR_REG, AES_CR_MODE_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - AES_MODE_DECRYPT)); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_MODE_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_DECRYPT)); } - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); err = ProcessBlockCipher(crypto, in, out, sz); cleanup: @@ -405,7 +405,7 @@ whal_Error whal_Stm32wba_AesEcb_Start(whal_AesEcb *dev, whal_Crypto_Dir dir, whal_Crypto *crypto = whal_Stm32wba_AesEcb_Dev.crypto; const whal_Stm32wba_Aes_Cfg *cfg = (const whal_Stm32wba_Aes_Cfg *)crypto->cfg; - size_t base = crypto->base; + uintptr_t base = crypto->base; size_t mode; size_t keySizeBit; whal_Error err; @@ -422,34 +422,34 @@ whal_Error whal_Stm32wba_AesEcb_Start(whal_AesEcb *dev, whal_Crypto_Dir dir, mode = (dir == WHAL_CRYPTO_ENCRYPT) ? AES_MODE_ENCRYPT : AES_MODE_KEYPREP; - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | - AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, mode) | - whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, - AES_CHMOD_ECB) | - whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, - AES_DATATYPE_NONE) | - whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, - keySizeBit)); + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | + AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, mode) | + whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, + AES_CHMOD_ECB) | + whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, + AES_DATATYPE_NONE) | + whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, + keySizeBit)); err = LoadKey(base, key, keySz, cfg->timeout); if (err) goto cleanup; if (dir == WHAL_CRYPTO_DECRYPT) { /* Decryption round key preparation; AES disables itself when done */ - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); err = WaitForCCF(base, cfg->timeout); if (err) goto cleanup; - whal_Reg_Update(base, AES_CR_REG, AES_CR_MODE_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - AES_MODE_DECRYPT)); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_MODE_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_DECRYPT)); } - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); return WHAL_SUCCESS; @@ -490,7 +490,7 @@ whal_Error whal_Stm32wba_AesCbc_Oneshot(whal_AesCbc *dev, whal_Crypto_Dir dir, whal_Crypto *crypto = whal_Stm32wba_AesCbc_Dev.crypto; const whal_Stm32wba_Aes_Cfg *cfg = (const whal_Stm32wba_Aes_Cfg *)crypto->cfg; - size_t base = crypto->base; + uintptr_t base = crypto->base; size_t mode; size_t keySizeBit; whal_Error err; @@ -507,35 +507,35 @@ whal_Error whal_Stm32wba_AesCbc_Oneshot(whal_AesCbc *dev, whal_Crypto_Dir dir, mode = (dir == WHAL_CRYPTO_ENCRYPT) ? AES_MODE_ENCRYPT : AES_MODE_KEYPREP; - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | - AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, mode) | - whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, - AES_CHMOD_CBC) | - whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, - AES_DATATYPE_NONE) | - whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, - keySizeBit)); + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | + AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, mode) | + whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, + AES_CHMOD_CBC) | + whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, + AES_DATATYPE_NONE) | + whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, + keySizeBit)); err = LoadKey(base, key, keySz, cfg->timeout); if (err) goto cleanup; if (dir == WHAL_CRYPTO_DECRYPT) { /* Decryption round key preparation; AES disables itself when done */ - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); err = WaitForCCF(base, cfg->timeout); if (err) goto cleanup; - whal_Reg_Update(base, AES_CR_REG, AES_CR_MODE_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - AES_MODE_DECRYPT)); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_MODE_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_DECRYPT)); } WriteIv(base, iv); - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); err = ProcessBlockCipher(crypto, in, out, sz); cleanup: @@ -551,7 +551,7 @@ whal_Error whal_Stm32wba_AesCbc_Start(whal_AesCbc *dev, whal_Crypto_Dir dir, whal_Crypto *crypto = whal_Stm32wba_AesCbc_Dev.crypto; const whal_Stm32wba_Aes_Cfg *cfg = (const whal_Stm32wba_Aes_Cfg *)crypto->cfg; - size_t base = crypto->base; + uintptr_t base = crypto->base; size_t mode; size_t keySizeBit; whal_Error err; @@ -568,35 +568,35 @@ whal_Error whal_Stm32wba_AesCbc_Start(whal_AesCbc *dev, whal_Crypto_Dir dir, mode = (dir == WHAL_CRYPTO_ENCRYPT) ? AES_MODE_ENCRYPT : AES_MODE_KEYPREP; - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | - AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, mode) | - whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, - AES_CHMOD_CBC) | - whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, - AES_DATATYPE_NONE) | - whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, - keySizeBit)); + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | + AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, mode) | + whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, + AES_CHMOD_CBC) | + whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, + AES_DATATYPE_NONE) | + whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, + keySizeBit)); err = LoadKey(base, key, keySz, cfg->timeout); if (err) goto cleanup; if (dir == WHAL_CRYPTO_DECRYPT) { /* Decryption round key preparation; AES disables itself when done */ - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); err = WaitForCCF(base, cfg->timeout); if (err) goto cleanup; - whal_Reg_Update(base, AES_CR_REG, AES_CR_MODE_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - AES_MODE_DECRYPT)); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_MODE_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_DECRYPT)); } WriteIv(base, iv); - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); return WHAL_SUCCESS; @@ -637,7 +637,7 @@ whal_Error whal_Stm32wba_AesCtr_Oneshot(whal_AesCtr *dev, whal_Crypto_Dir dir, whal_Crypto *crypto = whal_Stm32wba_AesCtr_Dev.crypto; const whal_Stm32wba_Aes_Cfg *cfg = (const whal_Stm32wba_Aes_Cfg *)crypto->cfg; - size_t base = crypto->base; + uintptr_t base = crypto->base; size_t keySizeBit; whal_Error err; @@ -651,26 +651,26 @@ whal_Error whal_Stm32wba_AesCtr_Oneshot(whal_AesCtr *dev, whal_Crypto_Dir dir, keySizeBit = (keySz == 32) ? 1 : 0; - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | - AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - AES_MODE_ENCRYPT) | - whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, - AES_CHMOD_CTR) | - whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, - AES_DATATYPE_NONE) | - whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, - keySizeBit)); + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | + AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_ENCRYPT) | + whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, + AES_CHMOD_CTR) | + whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, + AES_DATATYPE_NONE) | + whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, + keySizeBit)); err = LoadKey(base, key, keySz, cfg->timeout); if (err) goto cleanup; WriteIv(base, iv); - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); err = ProcessBlockCipher(crypto, in, out, sz); cleanup: @@ -686,7 +686,7 @@ whal_Error whal_Stm32wba_AesCtr_Start(whal_AesCtr *dev, whal_Crypto_Dir dir, whal_Crypto *crypto = whal_Stm32wba_AesCtr_Dev.crypto; const whal_Stm32wba_Aes_Cfg *cfg = (const whal_Stm32wba_Aes_Cfg *)crypto->cfg; - size_t base = crypto->base; + uintptr_t base = crypto->base; size_t keySizeBit; whal_Error err; @@ -700,26 +700,26 @@ whal_Error whal_Stm32wba_AesCtr_Start(whal_AesCtr *dev, whal_Crypto_Dir dir, keySizeBit = (keySz == 32) ? 1 : 0; - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | - AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - AES_MODE_ENCRYPT) | - whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, - AES_CHMOD_CTR) | - whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, - AES_DATATYPE_NONE) | - whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, - keySizeBit)); + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | + AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_ENCRYPT) | + whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, + AES_CHMOD_CTR) | + whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, + AES_DATATYPE_NONE) | + whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, + keySizeBit)); err = LoadKey(base, key, keySz, cfg->timeout); if (err) goto cleanup; WriteIv(base, iv); - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); return WHAL_SUCCESS; @@ -762,7 +762,7 @@ whal_Error whal_Stm32wba_AesGcm_Oneshot(whal_AesGcm *dev, whal_Crypto_Dir dir, whal_Crypto *crypto = whal_Stm32wba_AesGcm_Dev.crypto; const whal_Stm32wba_Aes_Cfg *cfg = (const whal_Stm32wba_Aes_Cfg *)crypto->cfg; - size_t base = crypto->base; + uintptr_t base = crypto->base; const uint8_t *ivBytes = (const uint8_t *)iv; const uint8_t *aadBytes = (const uint8_t *)aad; size_t keySizeBit; @@ -796,33 +796,33 @@ whal_Error whal_Stm32wba_AesGcm_Oneshot(whal_AesGcm *dev, whal_Crypto_Dir dir, keySizeBit = (keySz == 32) ? 1 : 0; /* Init phase */ - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); - - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | - AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk | - AES_CR_GCMPH_Msk | AES_CR_NPBLB_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - AES_MODE_ENCRYPT) | - whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, - AES_CHMOD_GCM) | - whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, - AES_DATATYPE_NONE) | - whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, - keySizeBit) | - whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, - AES_GCMPH_INIT)); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | + AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk | + AES_CR_GCMPH_Msk | AES_CR_NPBLB_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_ENCRYPT) | + whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, + AES_CHMOD_GCM) | + whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, + AES_DATATYPE_NONE) | + whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, + keySizeBit) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_INIT)); err = LoadKey(base, key, keySz, cfg->timeout); if (err) goto cleanup; - whal_Reg_Write(base, AES_IVR3_REG, whal_LoadBe32(ivBytes)); - whal_Reg_Write(base, AES_IVR2_REG, whal_LoadBe32(ivBytes + 4)); - whal_Reg_Write(base, AES_IVR1_REG, whal_LoadBe32(ivBytes + 8)); - whal_Reg_Write(base, AES_IVR0_REG, 0x00000002); + whal_Reg32_Write(base, AES_IVR3_REG, whal_LoadBe32(ivBytes)); + whal_Reg32_Write(base, AES_IVR2_REG, whal_LoadBe32(ivBytes + 4)); + whal_Reg32_Write(base, AES_IVR1_REG, whal_LoadBe32(ivBytes + 8)); + whal_Reg32_Write(base, AES_IVR0_REG, 0x00000002); - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); err = WaitForCCF(base, cfg->timeout); if (err) @@ -830,14 +830,14 @@ whal_Error whal_Stm32wba_AesGcm_Oneshot(whal_AesGcm *dev, whal_Crypto_Dir dir, /* Header phase (AAD) */ if (aadSz > 0) { - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - AES_MODE_ENCRYPT) | - whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, - AES_GCMPH_HEADER)); + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_ENCRYPT) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_HEADER)); - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); for (i = 0; i < aadSz; i += 16) { const uint8_t *blkAad = aadBytes + i; @@ -864,15 +864,15 @@ whal_Error whal_Stm32wba_AesGcm_Oneshot(whal_AesGcm *dev, whal_Crypto_Dir dir, mode = (dir == WHAL_CRYPTO_ENCRYPT) ? AES_MODE_ENCRYPT : AES_MODE_DECRYPT; - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - mode) | - whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, - AES_GCMPH_PAYLOAD)); + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + mode) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_PAYLOAD)); if (aadSz == 0) - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); for (i = 0; i < sz; i += 16) { const uint8_t *inBlk = (const uint8_t *)in + i; @@ -885,10 +885,10 @@ whal_Error whal_Stm32wba_AesGcm_Oneshot(whal_AesGcm *dev, whal_Crypto_Dir dir, WriteBlock(base, inBlk); } else { if (mode == AES_MODE_ENCRYPT) { - whal_Reg_Update(base, AES_CR_REG, AES_CR_NPBLB_Msk, - whal_SetBits(AES_CR_NPBLB_Msk, - AES_CR_NPBLB_Pos, - 16 - remain)); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_NPBLB_Msk, + whal_SetBits(AES_CR_NPBLB_Msk, + AES_CR_NPBLB_Pos, + 16 - remain)); } for (j = 0; j < remain; j++) block[j] = inBlk[j]; @@ -910,22 +910,22 @@ whal_Error whal_Stm32wba_AesGcm_Oneshot(whal_AesGcm *dev, whal_Crypto_Dir dir, } /* Final phase (tag) */ - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - AES_MODE_ENCRYPT) | - whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, - AES_GCMPH_FINAL)); + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_ENCRYPT) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_FINAL)); if (aadSz == 0 && sz == 0) - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); aadBits = (uint64_t)aadSz * 8; payloadBits = (uint64_t)sz * 8; - whal_Reg_Write(base, AES_DINR_REG, (uint32_t)(aadBits >> 32)); - whal_Reg_Write(base, AES_DINR_REG, (uint32_t)aadBits); - whal_Reg_Write(base, AES_DINR_REG, (uint32_t)(payloadBits >> 32)); - whal_Reg_Write(base, AES_DINR_REG, (uint32_t)payloadBits); + whal_Reg32_Write(base, AES_DINR_REG, (uint32_t)(aadBits >> 32)); + whal_Reg32_Write(base, AES_DINR_REG, (uint32_t)aadBits); + whal_Reg32_Write(base, AES_DINR_REG, (uint32_t)(payloadBits >> 32)); + whal_Reg32_Write(base, AES_DINR_REG, (uint32_t)payloadBits); err = WaitForCCF(base, cfg->timeout); if (err) @@ -937,7 +937,7 @@ whal_Error whal_Stm32wba_AesGcm_Oneshot(whal_AesGcm *dev, whal_Crypto_Dir dir, ((uint8_t *)tag)[i] = tagBuf[i]; cleanup: - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); ZeroKeyIv(base); return err; } @@ -950,7 +950,7 @@ whal_Error whal_Stm32wba_AesGcm_Start(whal_AesGcm *dev, whal_Crypto_Dir dir, whal_Crypto *crypto = whal_Stm32wba_AesGcm_Dev.crypto; const whal_Stm32wba_Aes_Cfg *cfg = (const whal_Stm32wba_Aes_Cfg *)crypto->cfg; - size_t base = crypto->base; + uintptr_t base = crypto->base; const uint8_t *ivBytes = (const uint8_t *)iv; const uint8_t *aadBytes = (const uint8_t *)aad; size_t keySizeBit; @@ -975,33 +975,33 @@ whal_Error whal_Stm32wba_AesGcm_Start(whal_AesGcm *dev, whal_Crypto_Dir dir, keySizeBit = (keySz == 32) ? 1 : 0; /* Init phase */ - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); - - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | - AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk | - AES_CR_GCMPH_Msk | AES_CR_NPBLB_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - AES_MODE_ENCRYPT) | - whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, - AES_CHMOD_GCM) | - whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, - AES_DATATYPE_NONE) | - whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, - keySizeBit) | - whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, - AES_GCMPH_INIT)); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | + AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk | + AES_CR_GCMPH_Msk | AES_CR_NPBLB_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_ENCRYPT) | + whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, + AES_CHMOD_GCM) | + whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, + AES_DATATYPE_NONE) | + whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, + keySizeBit) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_INIT)); err = LoadKey(base, key, keySz, cfg->timeout); if (err) goto cleanup; - whal_Reg_Write(base, AES_IVR3_REG, whal_LoadBe32(ivBytes)); - whal_Reg_Write(base, AES_IVR2_REG, whal_LoadBe32(ivBytes + 4)); - whal_Reg_Write(base, AES_IVR1_REG, whal_LoadBe32(ivBytes + 8)); - whal_Reg_Write(base, AES_IVR0_REG, 0x00000002); + whal_Reg32_Write(base, AES_IVR3_REG, whal_LoadBe32(ivBytes)); + whal_Reg32_Write(base, AES_IVR2_REG, whal_LoadBe32(ivBytes + 4)); + whal_Reg32_Write(base, AES_IVR1_REG, whal_LoadBe32(ivBytes + 8)); + whal_Reg32_Write(base, AES_IVR0_REG, 0x00000002); - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); err = WaitForCCF(base, cfg->timeout); if (err) @@ -1009,14 +1009,14 @@ whal_Error whal_Stm32wba_AesGcm_Start(whal_AesGcm *dev, whal_Crypto_Dir dir, /* Header phase (AAD) */ if (aadSz > 0) { - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - AES_MODE_ENCRYPT) | - whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, - AES_GCMPH_HEADER)); + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_ENCRYPT) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_HEADER)); - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); for (i = 0; i < aadSz; i += 16) { const uint8_t *blkAad = aadBytes + i; @@ -1042,14 +1042,14 @@ whal_Error whal_Stm32wba_AesGcm_Start(whal_AesGcm *dev, whal_Crypto_Dir dir, mode = (dir == WHAL_CRYPTO_ENCRYPT) ? AES_MODE_ENCRYPT : AES_MODE_DECRYPT; - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, mode) | - whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, - AES_GCMPH_PAYLOAD)); + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, mode) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_PAYLOAD)); if (aadSz == 0) - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); { whal_Stm32wba_AesGcm_State *st = @@ -1062,7 +1062,7 @@ whal_Error whal_Stm32wba_AesGcm_Start(whal_AesGcm *dev, whal_Crypto_Dir dir, return WHAL_SUCCESS; cleanup: - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); ZeroKeyIv(base); return err; } @@ -1073,7 +1073,7 @@ whal_Error whal_Stm32wba_AesGcm_Process(whal_AesGcm *dev, whal_Crypto *crypto = whal_Stm32wba_AesGcm_Dev.crypto; const whal_Stm32wba_Aes_Cfg *cfg = (const whal_Stm32wba_Aes_Cfg *)crypto->cfg; - size_t base = crypto->base; + uintptr_t base = crypto->base; whal_Stm32wba_AesGcm_State *st = (whal_Stm32wba_AesGcm_State *)whal_Stm32wba_AesGcm_Dev.state; size_t mode; @@ -1086,20 +1086,20 @@ whal_Error whal_Stm32wba_AesGcm_Process(whal_AesGcm *dev, return WHAL_SUCCESS; if (!in || !out) { - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); ZeroKeyIv(base); return WHAL_EINVAL; } /* Only the last Process call may end in a partial block */ if (st->partial) { - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); ZeroKeyIv(base); return WHAL_EINVAL; } mode = whal_GetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - whal_Reg_Read(base, AES_CR_REG)); + whal_Reg32_Read(base, AES_CR_REG)); for (i = 0; i < sz; i += 16) { const uint8_t *inBlk = (const uint8_t *)in + i; @@ -1112,10 +1112,10 @@ whal_Error whal_Stm32wba_AesGcm_Process(whal_AesGcm *dev, WriteBlock(base, inBlk); } else { if (mode == AES_MODE_ENCRYPT) { - whal_Reg_Update(base, AES_CR_REG, AES_CR_NPBLB_Msk, - whal_SetBits(AES_CR_NPBLB_Msk, - AES_CR_NPBLB_Pos, - 16 - remain)); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_NPBLB_Msk, + whal_SetBits(AES_CR_NPBLB_Msk, + AES_CR_NPBLB_Pos, + 16 - remain)); } for (j = 0; j < remain; j++) block[j] = inBlk[j]; @@ -1124,7 +1124,7 @@ whal_Error whal_Stm32wba_AesGcm_Process(whal_AesGcm *dev, err = WaitForCCF(base, cfg->timeout); if (err) { - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); ZeroKeyIv(base); return err; } @@ -1151,7 +1151,7 @@ whal_Error whal_Stm32wba_AesGcm_Finalize(whal_AesGcm *dev, whal_Crypto *crypto = whal_Stm32wba_AesGcm_Dev.crypto; const whal_Stm32wba_Aes_Cfg *cfg = (const whal_Stm32wba_Aes_Cfg *)crypto->cfg; - size_t base = crypto->base; + uintptr_t base = crypto->base; whal_Stm32wba_AesGcm_State *st = (whal_Stm32wba_AesGcm_State *)whal_Stm32wba_AesGcm_Dev.state; uint8_t tagBuf[16]; @@ -1163,32 +1163,32 @@ whal_Error whal_Stm32wba_AesGcm_Finalize(whal_AesGcm *dev, (void)dev; if (!tag || tagSz == 0 || tagSz > 16) { - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); ZeroKeyIv(base); return WHAL_EINVAL; } /* Final phase (tag) */ - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - AES_MODE_ENCRYPT) | - whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, - AES_GCMPH_FINAL)); + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_ENCRYPT) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_FINAL)); if (st->aadSz == 0 && st->dataSz == 0) - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); aadBits = (uint64_t)st->aadSz * 8; payloadBits = st->dataSz * 8; - whal_Reg_Write(base, AES_DINR_REG, (uint32_t)(aadBits >> 32)); - whal_Reg_Write(base, AES_DINR_REG, (uint32_t)aadBits); - whal_Reg_Write(base, AES_DINR_REG, (uint32_t)(payloadBits >> 32)); - whal_Reg_Write(base, AES_DINR_REG, (uint32_t)payloadBits); + whal_Reg32_Write(base, AES_DINR_REG, (uint32_t)(aadBits >> 32)); + whal_Reg32_Write(base, AES_DINR_REG, (uint32_t)aadBits); + whal_Reg32_Write(base, AES_DINR_REG, (uint32_t)(payloadBits >> 32)); + whal_Reg32_Write(base, AES_DINR_REG, (uint32_t)payloadBits); err = WaitForCCF(base, cfg->timeout); if (err) { - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); ZeroKeyIv(base); return err; } @@ -1198,7 +1198,7 @@ whal_Error whal_Stm32wba_AesGcm_Finalize(whal_AesGcm *dev, for (i = 0; i < tagSz; i++) ((uint8_t *)tag)[i] = tagBuf[i]; - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); ZeroKeyIv(base); return WHAL_SUCCESS; } @@ -1222,7 +1222,7 @@ whal_Error whal_Stm32wba_AesGmac_Oneshot(whal_AesGmac *dev, whal_Crypto *crypto = whal_Stm32wba_AesGmac_Dev.crypto; const whal_Stm32wba_Aes_Cfg *cfg = (const whal_Stm32wba_Aes_Cfg *)crypto->cfg; - size_t base = crypto->base; + uintptr_t base = crypto->base; const uint8_t *ivBytes = (const uint8_t *)iv; const uint8_t *aadBytes = (const uint8_t *)aad; size_t keySizeBit; @@ -1251,33 +1251,33 @@ whal_Error whal_Stm32wba_AesGmac_Oneshot(whal_AesGmac *dev, keySizeBit = (keySz == 32) ? 1 : 0; /* Init phase */ - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); - - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | - AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk | - AES_CR_GCMPH_Msk | AES_CR_NPBLB_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - AES_MODE_ENCRYPT) | - whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, - AES_CHMOD_GCM) | - whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, - AES_DATATYPE_NONE) | - whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, - keySizeBit) | - whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, - AES_GCMPH_INIT)); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | + AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk | + AES_CR_GCMPH_Msk | AES_CR_NPBLB_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_ENCRYPT) | + whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, + AES_CHMOD_GCM) | + whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, + AES_DATATYPE_NONE) | + whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, + keySizeBit) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_INIT)); err = LoadKey(base, key, keySz, cfg->timeout); if (err) goto cleanup; - whal_Reg_Write(base, AES_IVR3_REG, whal_LoadBe32(ivBytes)); - whal_Reg_Write(base, AES_IVR2_REG, whal_LoadBe32(ivBytes + 4)); - whal_Reg_Write(base, AES_IVR1_REG, whal_LoadBe32(ivBytes + 8)); - whal_Reg_Write(base, AES_IVR0_REG, 0x00000002); + whal_Reg32_Write(base, AES_IVR3_REG, whal_LoadBe32(ivBytes)); + whal_Reg32_Write(base, AES_IVR2_REG, whal_LoadBe32(ivBytes + 4)); + whal_Reg32_Write(base, AES_IVR1_REG, whal_LoadBe32(ivBytes + 8)); + whal_Reg32_Write(base, AES_IVR0_REG, 0x00000002); - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); err = WaitForCCF(base, cfg->timeout); if (err) @@ -1285,14 +1285,14 @@ whal_Error whal_Stm32wba_AesGmac_Oneshot(whal_AesGmac *dev, /* Header phase (AAD) */ if (aadSz > 0) { - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - AES_MODE_ENCRYPT) | - whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, - AES_GCMPH_HEADER)); + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_ENCRYPT) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_HEADER)); - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); for (i = 0; i < aadSz; i += 16) { const uint8_t *blkAad = aadBytes + i; @@ -1315,21 +1315,21 @@ whal_Error whal_Stm32wba_AesGmac_Oneshot(whal_AesGmac *dev, } /* Final phase (tag) -- no payload for GMAC */ - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - AES_MODE_ENCRYPT) | - whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, - AES_GCMPH_FINAL)); + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_ENCRYPT) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_FINAL)); if (aadSz == 0) - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); aadBits = (uint64_t)aadSz * 8; - whal_Reg_Write(base, AES_DINR_REG, (uint32_t)(aadBits >> 32)); - whal_Reg_Write(base, AES_DINR_REG, (uint32_t)aadBits); - whal_Reg_Write(base, AES_DINR_REG, 0); - whal_Reg_Write(base, AES_DINR_REG, 0); + whal_Reg32_Write(base, AES_DINR_REG, (uint32_t)(aadBits >> 32)); + whal_Reg32_Write(base, AES_DINR_REG, (uint32_t)aadBits); + whal_Reg32_Write(base, AES_DINR_REG, 0); + whal_Reg32_Write(base, AES_DINR_REG, 0); err = WaitForCCF(base, cfg->timeout); if (err) @@ -1341,7 +1341,7 @@ whal_Error whal_Stm32wba_AesGmac_Oneshot(whal_AesGmac *dev, ((uint8_t *)tag)[i] = tagBuf[i]; cleanup: - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); ZeroKeyIv(base); return err; } @@ -1363,7 +1363,7 @@ whal_Error whal_Stm32wba_AesCcm_Oneshot(whal_AesCcm *dev, whal_Crypto_Dir dir, whal_Crypto *crypto = whal_Stm32wba_AesCcm_Dev.crypto; const whal_Stm32wba_Aes_Cfg *cfg = (const whal_Stm32wba_Aes_Cfg *)crypto->cfg; - size_t base = crypto->base; + uintptr_t base = crypto->base; const uint8_t *nonceBytes = (const uint8_t *)nonce; const uint8_t *aadBytes = (const uint8_t *)aad; size_t keySizeBit; @@ -1421,29 +1421,29 @@ whal_Error whal_Stm32wba_AesCcm_Oneshot(whal_AesCcm *dev, whal_Crypto_Dir dir, } /* Init phase */ - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); - - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | - AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk | - AES_CR_GCMPH_Msk | AES_CR_NPBLB_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - AES_MODE_ENCRYPT) | - whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, 0) | - AES_CR_CHMOD2_Msk | - whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, - AES_DATATYPE_NONE) | - whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, - keySizeBit) | - whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, - AES_GCMPH_INIT)); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | + AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk | + AES_CR_GCMPH_Msk | AES_CR_NPBLB_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_ENCRYPT) | + whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, 0) | + AES_CR_CHMOD2_Msk | + whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, + AES_DATATYPE_NONE) | + whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, + keySizeBit) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_INIT)); err = LoadKey(base, key, keySz, cfg->timeout); if (err) goto cleanup; WriteIv(base, b0); - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); err = WaitForCCF(base, cfg->timeout); if (err) @@ -1451,14 +1451,14 @@ whal_Error whal_Stm32wba_AesCcm_Oneshot(whal_AesCcm *dev, whal_Crypto_Dir dir, /* Header phase (AAD) */ if (aadSz > 0) { - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - AES_MODE_ENCRYPT) | - whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, - AES_GCMPH_HEADER)); + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_ENCRYPT) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_HEADER)); - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); { uint8_t hdrBuf[16] = {0}; @@ -1509,15 +1509,15 @@ whal_Error whal_Stm32wba_AesCcm_Oneshot(whal_AesCcm *dev, whal_Crypto_Dir dir, mode = (dir == WHAL_CRYPTO_ENCRYPT) ? AES_MODE_ENCRYPT : AES_MODE_DECRYPT; - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - mode) | - whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, - AES_GCMPH_PAYLOAD)); + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + mode) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_PAYLOAD)); if (aadSz == 0) - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); for (i = 0; i < sz; i += 16) { const uint8_t *inBlk = (const uint8_t *)in + i; @@ -1530,10 +1530,10 @@ whal_Error whal_Stm32wba_AesCcm_Oneshot(whal_AesCcm *dev, whal_Crypto_Dir dir, WriteBlock(base, inBlk); } else { if (mode == AES_MODE_DECRYPT) { - whal_Reg_Update(base, AES_CR_REG, AES_CR_NPBLB_Msk, - whal_SetBits(AES_CR_NPBLB_Msk, - AES_CR_NPBLB_Pos, - 16 - remain)); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_NPBLB_Msk, + whal_SetBits(AES_CR_NPBLB_Msk, + AES_CR_NPBLB_Pos, + 16 - remain)); } for (j = 0; j < remain; j++) block[j] = inBlk[j]; @@ -1555,20 +1555,20 @@ whal_Error whal_Stm32wba_AesCcm_Oneshot(whal_AesCcm *dev, whal_Crypto_Dir dir, } /* Final phase (tag) */ - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - AES_MODE_ENCRYPT) | - whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, - AES_GCMPH_FINAL)); + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_ENCRYPT) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_FINAL)); if (aadSz == 0 && sz == 0) - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); - whal_Reg_Write(base, AES_DINR_REG, 0); - whal_Reg_Write(base, AES_DINR_REG, 0); - whal_Reg_Write(base, AES_DINR_REG, 0); - whal_Reg_Write(base, AES_DINR_REG, 0); + whal_Reg32_Write(base, AES_DINR_REG, 0); + whal_Reg32_Write(base, AES_DINR_REG, 0); + whal_Reg32_Write(base, AES_DINR_REG, 0); + whal_Reg32_Write(base, AES_DINR_REG, 0); err = WaitForCCF(base, cfg->timeout); if (err) @@ -1580,7 +1580,7 @@ whal_Error whal_Stm32wba_AesCcm_Oneshot(whal_AesCcm *dev, whal_Crypto_Dir dir, ((uint8_t *)tag)[i] = tagBuf[i]; cleanup: - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); ZeroKeyIv(base); return err; } @@ -1594,7 +1594,7 @@ whal_Error whal_Stm32wba_AesCcm_Start(whal_AesCcm *dev, whal_Crypto_Dir dir, whal_Crypto *crypto = whal_Stm32wba_AesCcm_Dev.crypto; const whal_Stm32wba_Aes_Cfg *cfg = (const whal_Stm32wba_Aes_Cfg *)crypto->cfg; - size_t base = crypto->base; + uintptr_t base = crypto->base; const uint8_t *nonceBytes = (const uint8_t *)nonce; const uint8_t *aadBytes = (const uint8_t *)aad; size_t keySizeBit; @@ -1648,29 +1648,29 @@ whal_Error whal_Stm32wba_AesCcm_Start(whal_AesCcm *dev, whal_Crypto_Dir dir, } /* Init phase */ - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); - - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | - AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk | - AES_CR_GCMPH_Msk | AES_CR_NPBLB_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - AES_MODE_ENCRYPT) | - whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, 0) | - AES_CR_CHMOD2_Msk | - whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, - AES_DATATYPE_NONE) | - whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, - keySizeBit) | - whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, - AES_GCMPH_INIT)); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | + AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk | + AES_CR_GCMPH_Msk | AES_CR_NPBLB_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_ENCRYPT) | + whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, 0) | + AES_CR_CHMOD2_Msk | + whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, + AES_DATATYPE_NONE) | + whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, + keySizeBit) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_INIT)); err = LoadKey(base, key, keySz, cfg->timeout); if (err) goto cleanup; WriteIv(base, b0); - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); err = WaitForCCF(base, cfg->timeout); if (err) @@ -1678,14 +1678,14 @@ whal_Error whal_Stm32wba_AesCcm_Start(whal_AesCcm *dev, whal_Crypto_Dir dir, /* Header phase (AAD) */ if (aadSz > 0) { - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - AES_MODE_ENCRYPT) | - whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, - AES_GCMPH_HEADER)); + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_ENCRYPT) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_HEADER)); - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); { uint8_t hdrBuf[16] = {0}; @@ -1735,14 +1735,14 @@ whal_Error whal_Stm32wba_AesCcm_Start(whal_AesCcm *dev, whal_Crypto_Dir dir, mode = (dir == WHAL_CRYPTO_ENCRYPT) ? AES_MODE_ENCRYPT : AES_MODE_DECRYPT; - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, mode) | - whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, - AES_GCMPH_PAYLOAD)); + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, mode) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_PAYLOAD)); if (aadSz == 0) - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); { whal_Stm32wba_AesCcm_State *st = @@ -1757,7 +1757,7 @@ whal_Error whal_Stm32wba_AesCcm_Start(whal_AesCcm *dev, whal_Crypto_Dir dir, return WHAL_SUCCESS; cleanup: - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); ZeroKeyIv(base); return err; } @@ -1768,7 +1768,7 @@ whal_Error whal_Stm32wba_AesCcm_Process(whal_AesCcm *dev, whal_Crypto *crypto = whal_Stm32wba_AesCcm_Dev.crypto; const whal_Stm32wba_Aes_Cfg *cfg = (const whal_Stm32wba_Aes_Cfg *)crypto->cfg; - size_t base = crypto->base; + uintptr_t base = crypto->base; whal_Stm32wba_AesCcm_State *st = (whal_Stm32wba_AesCcm_State *)whal_Stm32wba_AesCcm_Dev.state; size_t mode; @@ -1781,7 +1781,7 @@ whal_Error whal_Stm32wba_AesCcm_Process(whal_AesCcm *dev, return WHAL_SUCCESS; if (!in || !out) { - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); ZeroKeyIv(base); return WHAL_EINVAL; } @@ -1789,13 +1789,13 @@ whal_Error whal_Stm32wba_AesCcm_Process(whal_AesCcm *dev, /* Only the last Process call may end in a partial block, and the * total may not exceed the payload length declared at Start */ if (st->partial || sz > st->msgSz - st->dataSz) { - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); ZeroKeyIv(base); return WHAL_EINVAL; } mode = whal_GetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - whal_Reg_Read(base, AES_CR_REG)); + whal_Reg32_Read(base, AES_CR_REG)); for (i = 0; i < sz; i += 16) { const uint8_t *inBlk = (const uint8_t *)in + i; @@ -1808,10 +1808,10 @@ whal_Error whal_Stm32wba_AesCcm_Process(whal_AesCcm *dev, WriteBlock(base, inBlk); } else { if (mode == AES_MODE_DECRYPT) { - whal_Reg_Update(base, AES_CR_REG, AES_CR_NPBLB_Msk, - whal_SetBits(AES_CR_NPBLB_Msk, - AES_CR_NPBLB_Pos, - 16 - remain)); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_NPBLB_Msk, + whal_SetBits(AES_CR_NPBLB_Msk, + AES_CR_NPBLB_Pos, + 16 - remain)); } for (j = 0; j < remain; j++) block[j] = inBlk[j]; @@ -1820,7 +1820,7 @@ whal_Error whal_Stm32wba_AesCcm_Process(whal_AesCcm *dev, err = WaitForCCF(base, cfg->timeout); if (err) { - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); ZeroKeyIv(base); return err; } @@ -1847,7 +1847,7 @@ whal_Error whal_Stm32wba_AesCcm_Finalize(whal_AesCcm *dev, whal_Crypto *crypto = whal_Stm32wba_AesCcm_Dev.crypto; const whal_Stm32wba_Aes_Cfg *cfg = (const whal_Stm32wba_Aes_Cfg *)crypto->cfg; - size_t base = crypto->base; + uintptr_t base = crypto->base; whal_Stm32wba_AesCcm_State *st = (whal_Stm32wba_AesCcm_State *)whal_Stm32wba_AesCcm_Dev.state; uint8_t tagBuf[16]; @@ -1859,30 +1859,30 @@ whal_Error whal_Stm32wba_AesCcm_Finalize(whal_AesCcm *dev, /* Tag length and payload length must match what Start encoded in B0 */ if (!tag || tagSz < 4 || tagSz > 16 || (tagSz & 1) != 0 || tagSz != st->tagSz || st->dataSz != st->msgSz) { - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); ZeroKeyIv(base); return WHAL_EINVAL; } /* Final phase (tag) */ - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, - AES_MODE_ENCRYPT) | - whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, - AES_GCMPH_FINAL)); + whal_Reg32_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_ENCRYPT) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_FINAL)); if (st->aadSz == 0 && st->dataSz == 0) - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); - whal_Reg_Write(base, AES_DINR_REG, 0); - whal_Reg_Write(base, AES_DINR_REG, 0); - whal_Reg_Write(base, AES_DINR_REG, 0); - whal_Reg_Write(base, AES_DINR_REG, 0); + whal_Reg32_Write(base, AES_DINR_REG, 0); + whal_Reg32_Write(base, AES_DINR_REG, 0); + whal_Reg32_Write(base, AES_DINR_REG, 0); + whal_Reg32_Write(base, AES_DINR_REG, 0); err = WaitForCCF(base, cfg->timeout); if (err) { - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); ZeroKeyIv(base); return err; } @@ -1892,7 +1892,7 @@ whal_Error whal_Stm32wba_AesCcm_Finalize(whal_AesCcm *dev, for (i = 0; i < tagSz; i++) ((uint8_t *)tag)[i] = tagBuf[i]; - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg32_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); ZeroKeyIv(base); return WHAL_SUCCESS; } diff --git a/src/crypto/stm32wba_hash.c b/src/crypto/stm32wba_hash.c index 7436adf3..9972477e 100644 --- a/src/crypto/stm32wba_hash.c +++ b/src/crypto/stm32wba_hash.c @@ -105,16 +105,16 @@ static uint32_t AlgoBits(size_t algo) return whal_SetBits(HASH_CR_ALGO_Msk, HASH_CR_ALGO_Pos, algo); } -static whal_Error WaitForReady(size_t base, whal_Timeout *timeout) +static whal_Error WaitForReady(uintptr_t base, whal_Timeout *timeout) { - return whal_Reg_ReadPoll(base, HASH_SR_REG, HASH_SR_BUSY_Msk, 0, timeout); + return whal_Reg32_ReadPoll(base, HASH_SR_REG, HASH_SR_BUSY_Msk, 0, timeout); } /* Reset the hash core and clear DINIS so the context swap registers read 0. */ -static void ResetHash(size_t base) +static void ResetHash(uintptr_t base) { - whal_Reg_Update(base, HASH_CR_REG, HASH_CR_INIT_Msk, HASH_CR_INIT_Msk); - whal_Reg_Update(base, HASH_SR_REG, HASH_SR_DINIS_Msk, 0); + whal_Reg32_Update(base, HASH_CR_REG, HASH_CR_INIT_Msk, HASH_CR_INIT_Msk); + whal_Reg32_Update(base, HASH_SR_REG, HASH_SR_DINIS_Msk, 0); } /* Reset the stream staging buffer; called from each Start. */ @@ -127,7 +127,7 @@ static void StreamReset(void) /* Accumulate Process input. Tops up the staging buffer to a full word if * it had leftovers, pushes full 32-bit DIN writes, and stashes the * trailing 0-3 bytes back into the staging buffer for the next call. */ -static void StreamWrite(size_t base, const uint8_t *in, size_t inSz) +static void StreamWrite(uintptr_t base, const uint8_t *in, size_t inSz) { if (inSz > 0) g_streamHasData = 1; @@ -138,13 +138,13 @@ static void StreamWrite(size_t base, const uint8_t *in, size_t inSz) inSz--; } if (g_streamBufBytes == 4) { - whal_Reg_Write(base, HASH_DIN_REG, whal_LoadBe32(g_streamBuf)); + whal_Reg32_Write(base, HASH_DIN_REG, whal_LoadBe32(g_streamBuf)); g_streamBufBytes = 0; } } while (inSz >= 4) { - whal_Reg_Write(base, HASH_DIN_REG, whal_LoadBe32(in)); + whal_Reg32_Write(base, HASH_DIN_REG, whal_LoadBe32(in)); in += 4; inSz -= 4; } @@ -157,38 +157,38 @@ static void StreamWrite(size_t base, const uint8_t *in, size_t inSz) /* Push inSz bytes immediately before issuing DCAL: full words first, then * if any trailing bytes remain, set NBLW and push one partial word. */ -static void WriteTail(size_t base, const uint8_t *in, size_t inSz) +static void WriteTail(uintptr_t base, const uint8_t *in, size_t inSz) { while (inSz >= 4) { - whal_Reg_Write(base, HASH_DIN_REG, whal_LoadBe32(in)); + whal_Reg32_Write(base, HASH_DIN_REG, whal_LoadBe32(in)); in += 4; inSz -= 4; } if (inSz > 0) { - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, - whal_SetBits(HASH_STR_NBLW_Msk, HASH_STR_NBLW_Pos, - inSz * 8)); - whal_Reg_Write(base, HASH_DIN_REG, whal_LoadBe32Partial(in, inSz)); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, + whal_SetBits(HASH_STR_NBLW_Msk, HASH_STR_NBLW_Pos, + inSz * 8)); + whal_Reg32_Write(base, HASH_DIN_REG, whal_LoadBe32Partial(in, inSz)); } } /* Drain any buffered 0-3 trailing bytes as the final partial word right * before DCAL; sets NBLW correctly via WriteTail. */ -static void StreamDrain(size_t base) +static void StreamDrain(uintptr_t base) { WriteTail(base, g_streamBuf, g_streamBufBytes); g_streamBufBytes = 0; } -static void ReadDigest(size_t base, uint8_t *digest, size_t digestSz) +static void ReadDigest(uintptr_t base, uint8_t *digest, size_t digestSz) { size_t words = digestSz / 4; size_t i; for (i = 0; i < words; i++) whal_StoreBe32(digest + i * 4, - whal_Reg_Read(base, HASH_HR_BASE_REG + i * 4)); + whal_Reg32_Read(base, HASH_HR_BASE_REG + i * 4)); } @@ -272,7 +272,7 @@ whal_Error whal_Stm32wba_Sha1_Oneshot(whal_Sha1 *dev, { const whal_Stm32wba_Hash_Cfg *cfg = (const whal_Stm32wba_Hash_Cfg *)whal_Stm32wba_Hash_Dev.cfg; - size_t base = whal_Stm32wba_Hash_Dev.base; + uintptr_t base = whal_Stm32wba_Hash_Dev.base; whal_Error err; (void)dev; @@ -280,18 +280,18 @@ whal_Error whal_Stm32wba_Sha1_Oneshot(whal_Sha1 *dev, (inSz > 0 && !in)) return WHAL_EINVAL; - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); - whal_Reg_Update(base, HASH_CR_REG, - HASH_CR_ALGO_Msk | HASH_CR_DATATYPE_Msk | - HASH_CR_MODE_Msk | HASH_CR_LKEY_Msk | HASH_CR_INIT_Msk, - AlgoBits(HASH_ALGO_SHA1) | HASH_CR_INIT_Msk); + whal_Reg32_Update(base, HASH_CR_REG, + HASH_CR_ALGO_Msk | HASH_CR_DATATYPE_Msk | + HASH_CR_MODE_Msk | HASH_CR_LKEY_Msk | HASH_CR_INIT_Msk, + AlgoBits(HASH_ALGO_SHA1) | HASH_CR_INIT_Msk); if (inSz > 0) WriteTail(base, (const uint8_t *)in, inSz); - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, - HASH_STR_DCAL_Msk); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); err = WaitForReady(base, cfg->timeout); if (err) @@ -303,15 +303,15 @@ whal_Error whal_Stm32wba_Sha1_Oneshot(whal_Sha1 *dev, whal_Error whal_Stm32wba_Sha1_Start(whal_Sha1 *dev) { - size_t base = whal_Stm32wba_Hash_Dev.base; + uintptr_t base = whal_Stm32wba_Hash_Dev.base; (void)dev; - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); - whal_Reg_Update(base, HASH_CR_REG, - HASH_CR_ALGO_Msk | HASH_CR_DATATYPE_Msk | - HASH_CR_MODE_Msk | HASH_CR_LKEY_Msk | HASH_CR_INIT_Msk, - AlgoBits(HASH_ALGO_SHA1) | HASH_CR_INIT_Msk); + whal_Reg32_Update(base, HASH_CR_REG, + HASH_CR_ALGO_Msk | HASH_CR_DATATYPE_Msk | + HASH_CR_MODE_Msk | HASH_CR_LKEY_Msk | HASH_CR_INIT_Msk, + AlgoBits(HASH_ALGO_SHA1) | HASH_CR_INIT_Msk); StreamReset(); return WHAL_SUCCESS; @@ -334,7 +334,7 @@ whal_Error whal_Stm32wba_Sha1_Finalize(whal_Sha1 *dev, { const whal_Stm32wba_Hash_Cfg *cfg = (const whal_Stm32wba_Hash_Cfg *)whal_Stm32wba_Hash_Dev.cfg; - size_t base = whal_Stm32wba_Hash_Dev.base; + uintptr_t base = whal_Stm32wba_Hash_Dev.base; whal_Error err; (void)dev; @@ -343,8 +343,8 @@ whal_Error whal_Stm32wba_Sha1_Finalize(whal_Sha1 *dev, StreamDrain(base); - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, - HASH_STR_DCAL_Msk); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); err = WaitForReady(base, cfg->timeout); if (err) @@ -370,7 +370,7 @@ whal_Error whal_Stm32wba_Sha224_Oneshot(whal_Sha224 *dev, { const whal_Stm32wba_Hash_Cfg *cfg = (const whal_Stm32wba_Hash_Cfg *)whal_Stm32wba_Hash_Dev.cfg; - size_t base = whal_Stm32wba_Hash_Dev.base; + uintptr_t base = whal_Stm32wba_Hash_Dev.base; whal_Error err; (void)dev; @@ -378,18 +378,18 @@ whal_Error whal_Stm32wba_Sha224_Oneshot(whal_Sha224 *dev, (inSz > 0 && !in)) return WHAL_EINVAL; - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); - whal_Reg_Update(base, HASH_CR_REG, - HASH_CR_ALGO_Msk | HASH_CR_DATATYPE_Msk | - HASH_CR_MODE_Msk | HASH_CR_LKEY_Msk | HASH_CR_INIT_Msk, - AlgoBits(HASH_ALGO_SHA224) | HASH_CR_INIT_Msk); + whal_Reg32_Update(base, HASH_CR_REG, + HASH_CR_ALGO_Msk | HASH_CR_DATATYPE_Msk | + HASH_CR_MODE_Msk | HASH_CR_LKEY_Msk | HASH_CR_INIT_Msk, + AlgoBits(HASH_ALGO_SHA224) | HASH_CR_INIT_Msk); if (inSz > 0) WriteTail(base, (const uint8_t *)in, inSz); - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, - HASH_STR_DCAL_Msk); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); err = WaitForReady(base, cfg->timeout); if (err) @@ -401,15 +401,15 @@ whal_Error whal_Stm32wba_Sha224_Oneshot(whal_Sha224 *dev, whal_Error whal_Stm32wba_Sha224_Start(whal_Sha224 *dev) { - size_t base = whal_Stm32wba_Hash_Dev.base; + uintptr_t base = whal_Stm32wba_Hash_Dev.base; (void)dev; - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); - whal_Reg_Update(base, HASH_CR_REG, - HASH_CR_ALGO_Msk | HASH_CR_DATATYPE_Msk | - HASH_CR_MODE_Msk | HASH_CR_LKEY_Msk | HASH_CR_INIT_Msk, - AlgoBits(HASH_ALGO_SHA224) | HASH_CR_INIT_Msk); + whal_Reg32_Update(base, HASH_CR_REG, + HASH_CR_ALGO_Msk | HASH_CR_DATATYPE_Msk | + HASH_CR_MODE_Msk | HASH_CR_LKEY_Msk | HASH_CR_INIT_Msk, + AlgoBits(HASH_ALGO_SHA224) | HASH_CR_INIT_Msk); StreamReset(); return WHAL_SUCCESS; @@ -432,7 +432,7 @@ whal_Error whal_Stm32wba_Sha224_Finalize(whal_Sha224 *dev, { const whal_Stm32wba_Hash_Cfg *cfg = (const whal_Stm32wba_Hash_Cfg *)whal_Stm32wba_Hash_Dev.cfg; - size_t base = whal_Stm32wba_Hash_Dev.base; + uintptr_t base = whal_Stm32wba_Hash_Dev.base; whal_Error err; (void)dev; @@ -441,8 +441,8 @@ whal_Error whal_Stm32wba_Sha224_Finalize(whal_Sha224 *dev, StreamDrain(base); - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, - HASH_STR_DCAL_Msk); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); err = WaitForReady(base, cfg->timeout); if (err) @@ -468,7 +468,7 @@ whal_Error whal_Stm32wba_Sha256_Oneshot(whal_Sha256 *dev, { const whal_Stm32wba_Hash_Cfg *cfg = (const whal_Stm32wba_Hash_Cfg *)whal_Stm32wba_Hash_Dev.cfg; - size_t base = whal_Stm32wba_Hash_Dev.base; + uintptr_t base = whal_Stm32wba_Hash_Dev.base; whal_Error err; (void)dev; @@ -476,18 +476,18 @@ whal_Error whal_Stm32wba_Sha256_Oneshot(whal_Sha256 *dev, (inSz > 0 && !in)) return WHAL_EINVAL; - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); - whal_Reg_Update(base, HASH_CR_REG, - HASH_CR_ALGO_Msk | HASH_CR_DATATYPE_Msk | - HASH_CR_MODE_Msk | HASH_CR_LKEY_Msk | HASH_CR_INIT_Msk, - AlgoBits(HASH_ALGO_SHA256) | HASH_CR_INIT_Msk); + whal_Reg32_Update(base, HASH_CR_REG, + HASH_CR_ALGO_Msk | HASH_CR_DATATYPE_Msk | + HASH_CR_MODE_Msk | HASH_CR_LKEY_Msk | HASH_CR_INIT_Msk, + AlgoBits(HASH_ALGO_SHA256) | HASH_CR_INIT_Msk); if (inSz > 0) WriteTail(base, (const uint8_t *)in, inSz); - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, - HASH_STR_DCAL_Msk); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); err = WaitForReady(base, cfg->timeout); if (err) @@ -499,15 +499,15 @@ whal_Error whal_Stm32wba_Sha256_Oneshot(whal_Sha256 *dev, whal_Error whal_Stm32wba_Sha256_Start(whal_Sha256 *dev) { - size_t base = whal_Stm32wba_Hash_Dev.base; + uintptr_t base = whal_Stm32wba_Hash_Dev.base; (void)dev; - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); - whal_Reg_Update(base, HASH_CR_REG, - HASH_CR_ALGO_Msk | HASH_CR_DATATYPE_Msk | - HASH_CR_MODE_Msk | HASH_CR_LKEY_Msk | HASH_CR_INIT_Msk, - AlgoBits(HASH_ALGO_SHA256) | HASH_CR_INIT_Msk); + whal_Reg32_Update(base, HASH_CR_REG, + HASH_CR_ALGO_Msk | HASH_CR_DATATYPE_Msk | + HASH_CR_MODE_Msk | HASH_CR_LKEY_Msk | HASH_CR_INIT_Msk, + AlgoBits(HASH_ALGO_SHA256) | HASH_CR_INIT_Msk); StreamReset(); return WHAL_SUCCESS; @@ -530,7 +530,7 @@ whal_Error whal_Stm32wba_Sha256_Finalize(whal_Sha256 *dev, { const whal_Stm32wba_Hash_Cfg *cfg = (const whal_Stm32wba_Hash_Cfg *)whal_Stm32wba_Hash_Dev.cfg; - size_t base = whal_Stm32wba_Hash_Dev.base; + uintptr_t base = whal_Stm32wba_Hash_Dev.base; whal_Error err; (void)dev; @@ -539,8 +539,8 @@ whal_Error whal_Stm32wba_Sha256_Finalize(whal_Sha256 *dev, StreamDrain(base); - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, - HASH_STR_DCAL_Msk); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); err = WaitForReady(base, cfg->timeout); if (err) @@ -567,7 +567,7 @@ whal_Error whal_Stm32wba_HmacSha1_Oneshot(whal_HmacSha1 *dev, { const whal_Stm32wba_Hash_Cfg *cfg = (const whal_Stm32wba_Hash_Cfg *)whal_Stm32wba_Hash_Dev.cfg; - size_t base = whal_Stm32wba_Hash_Dev.base; + uintptr_t base = whal_Stm32wba_Hash_Dev.base; size_t lkey; whal_Error err; (void)dev; @@ -582,22 +582,22 @@ whal_Error whal_Stm32wba_HmacSha1_Oneshot(whal_HmacSha1 *dev, lkey = (keySz > 64) ? 1 : 0; - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); - whal_Reg_Update(base, HASH_CR_REG, - HASH_CR_ALGO_Msk | HASH_CR_DATATYPE_Msk | - HASH_CR_MODE_Msk | HASH_CR_LKEY_Msk | HASH_CR_INIT_Msk, - AlgoBits(HASH_ALGO_SHA1) | - whal_SetBits(HASH_CR_MODE_Msk, HASH_CR_MODE_Pos, - HASH_MODE_HMAC) | - whal_SetBits(HASH_CR_LKEY_Msk, HASH_CR_LKEY_Pos, lkey) | - HASH_CR_INIT_Msk); + whal_Reg32_Update(base, HASH_CR_REG, + HASH_CR_ALGO_Msk | HASH_CR_DATATYPE_Msk | + HASH_CR_MODE_Msk | HASH_CR_LKEY_Msk | HASH_CR_INIT_Msk, + AlgoBits(HASH_ALGO_SHA1) | + whal_SetBits(HASH_CR_MODE_Msk, HASH_CR_MODE_Pos, + HASH_MODE_HMAC) | + whal_SetBits(HASH_CR_LKEY_Msk, HASH_CR_LKEY_Pos, lkey) | + HASH_CR_INIT_Msk); /* Inner key */ WriteTail(base, (const uint8_t *)key, keySz); - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, - HASH_STR_DCAL_Msk); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); err = WaitForReady(base, cfg->timeout); if (err) { @@ -606,12 +606,12 @@ whal_Error whal_Stm32wba_HmacSha1_Oneshot(whal_HmacSha1 *dev, } /* Message */ - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); if (inSz > 0) WriteTail(base, (const uint8_t *)in, inSz); - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, - HASH_STR_DCAL_Msk); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); err = WaitForReady(base, cfg->timeout); if (err) { @@ -620,11 +620,11 @@ whal_Error whal_Stm32wba_HmacSha1_Oneshot(whal_HmacSha1 *dev, } /* Outer key */ - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); WriteTail(base, (const uint8_t *)key, keySz); - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, - HASH_STR_DCAL_Msk); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); err = WaitForReady(base, cfg->timeout); if (err) { @@ -641,7 +641,7 @@ whal_Error whal_Stm32wba_HmacSha1_Start(whal_HmacSha1 *dev, { const whal_Stm32wba_Hash_Cfg *cfg = (const whal_Stm32wba_Hash_Cfg *)whal_Stm32wba_Hash_Dev.cfg; - size_t base = whal_Stm32wba_Hash_Dev.base; + uintptr_t base = whal_Stm32wba_Hash_Dev.base; size_t lkey; whal_Error err; (void)dev; @@ -651,22 +651,22 @@ whal_Error whal_Stm32wba_HmacSha1_Start(whal_HmacSha1 *dev, lkey = (keySz > 64) ? 1 : 0; - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); - whal_Reg_Update(base, HASH_CR_REG, - HASH_CR_ALGO_Msk | HASH_CR_DATATYPE_Msk | - HASH_CR_MODE_Msk | HASH_CR_LKEY_Msk | HASH_CR_INIT_Msk, - AlgoBits(HASH_ALGO_SHA1) | - whal_SetBits(HASH_CR_MODE_Msk, HASH_CR_MODE_Pos, - HASH_MODE_HMAC) | - whal_SetBits(HASH_CR_LKEY_Msk, HASH_CR_LKEY_Pos, lkey) | - HASH_CR_INIT_Msk); + whal_Reg32_Update(base, HASH_CR_REG, + HASH_CR_ALGO_Msk | HASH_CR_DATATYPE_Msk | + HASH_CR_MODE_Msk | HASH_CR_LKEY_Msk | HASH_CR_INIT_Msk, + AlgoBits(HASH_ALGO_SHA1) | + whal_SetBits(HASH_CR_MODE_Msk, HASH_CR_MODE_Pos, + HASH_MODE_HMAC) | + whal_SetBits(HASH_CR_LKEY_Msk, HASH_CR_LKEY_Pos, lkey) | + HASH_CR_INIT_Msk); /* Inner key */ WriteTail(base, (const uint8_t *)key, keySz); - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, - HASH_STR_DCAL_Msk); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); err = WaitForReady(base, cfg->timeout); if (err) { @@ -699,7 +699,7 @@ whal_Error whal_Stm32wba_HmacSha1_Finalize(whal_HmacSha1 *dev, { const whal_Stm32wba_Hash_Cfg *cfg = (const whal_Stm32wba_Hash_Cfg *)whal_Stm32wba_Hash_Dev.cfg; - size_t base = whal_Stm32wba_Hash_Dev.base; + uintptr_t base = whal_Stm32wba_Hash_Dev.base; whal_Error err; (void)dev; @@ -712,11 +712,11 @@ whal_Error whal_Stm32wba_HmacSha1_Finalize(whal_HmacSha1 *dev, } /* Drain any buffered tail bytes, then DCAL to close message phase. */ - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); StreamDrain(base); - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, - HASH_STR_DCAL_Msk); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); err = WaitForReady(base, cfg->timeout); if (err) { @@ -725,11 +725,11 @@ whal_Error whal_Stm32wba_HmacSha1_Finalize(whal_HmacSha1 *dev, } /* Outer key */ - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); WriteTail(base, (const uint8_t *)g_hmacSha1State.key, g_hmacSha1State.keySz); - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, - HASH_STR_DCAL_Msk); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); err = WaitForReady(base, cfg->timeout); if (err) { @@ -758,7 +758,7 @@ whal_Error whal_Stm32wba_HmacSha224_Oneshot(whal_HmacSha224 *dev, { const whal_Stm32wba_Hash_Cfg *cfg = (const whal_Stm32wba_Hash_Cfg *)whal_Stm32wba_Hash_Dev.cfg; - size_t base = whal_Stm32wba_Hash_Dev.base; + uintptr_t base = whal_Stm32wba_Hash_Dev.base; size_t lkey; whal_Error err; (void)dev; @@ -773,22 +773,22 @@ whal_Error whal_Stm32wba_HmacSha224_Oneshot(whal_HmacSha224 *dev, lkey = (keySz > 64) ? 1 : 0; - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); - whal_Reg_Update(base, HASH_CR_REG, - HASH_CR_ALGO_Msk | HASH_CR_DATATYPE_Msk | - HASH_CR_MODE_Msk | HASH_CR_LKEY_Msk | HASH_CR_INIT_Msk, - AlgoBits(HASH_ALGO_SHA224) | - whal_SetBits(HASH_CR_MODE_Msk, HASH_CR_MODE_Pos, - HASH_MODE_HMAC) | - whal_SetBits(HASH_CR_LKEY_Msk, HASH_CR_LKEY_Pos, lkey) | - HASH_CR_INIT_Msk); + whal_Reg32_Update(base, HASH_CR_REG, + HASH_CR_ALGO_Msk | HASH_CR_DATATYPE_Msk | + HASH_CR_MODE_Msk | HASH_CR_LKEY_Msk | HASH_CR_INIT_Msk, + AlgoBits(HASH_ALGO_SHA224) | + whal_SetBits(HASH_CR_MODE_Msk, HASH_CR_MODE_Pos, + HASH_MODE_HMAC) | + whal_SetBits(HASH_CR_LKEY_Msk, HASH_CR_LKEY_Pos, lkey) | + HASH_CR_INIT_Msk); /* Inner key */ WriteTail(base, (const uint8_t *)key, keySz); - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, - HASH_STR_DCAL_Msk); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); err = WaitForReady(base, cfg->timeout); if (err) { @@ -797,12 +797,12 @@ whal_Error whal_Stm32wba_HmacSha224_Oneshot(whal_HmacSha224 *dev, } /* Message */ - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); if (inSz > 0) WriteTail(base, (const uint8_t *)in, inSz); - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, - HASH_STR_DCAL_Msk); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); err = WaitForReady(base, cfg->timeout); if (err) { @@ -811,11 +811,11 @@ whal_Error whal_Stm32wba_HmacSha224_Oneshot(whal_HmacSha224 *dev, } /* Outer key */ - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); WriteTail(base, (const uint8_t *)key, keySz); - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, - HASH_STR_DCAL_Msk); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); err = WaitForReady(base, cfg->timeout); if (err) { @@ -832,7 +832,7 @@ whal_Error whal_Stm32wba_HmacSha224_Start(whal_HmacSha224 *dev, { const whal_Stm32wba_Hash_Cfg *cfg = (const whal_Stm32wba_Hash_Cfg *)whal_Stm32wba_Hash_Dev.cfg; - size_t base = whal_Stm32wba_Hash_Dev.base; + uintptr_t base = whal_Stm32wba_Hash_Dev.base; size_t lkey; whal_Error err; (void)dev; @@ -842,22 +842,22 @@ whal_Error whal_Stm32wba_HmacSha224_Start(whal_HmacSha224 *dev, lkey = (keySz > 64) ? 1 : 0; - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); - whal_Reg_Update(base, HASH_CR_REG, - HASH_CR_ALGO_Msk | HASH_CR_DATATYPE_Msk | - HASH_CR_MODE_Msk | HASH_CR_LKEY_Msk | HASH_CR_INIT_Msk, - AlgoBits(HASH_ALGO_SHA224) | - whal_SetBits(HASH_CR_MODE_Msk, HASH_CR_MODE_Pos, - HASH_MODE_HMAC) | - whal_SetBits(HASH_CR_LKEY_Msk, HASH_CR_LKEY_Pos, lkey) | - HASH_CR_INIT_Msk); + whal_Reg32_Update(base, HASH_CR_REG, + HASH_CR_ALGO_Msk | HASH_CR_DATATYPE_Msk | + HASH_CR_MODE_Msk | HASH_CR_LKEY_Msk | HASH_CR_INIT_Msk, + AlgoBits(HASH_ALGO_SHA224) | + whal_SetBits(HASH_CR_MODE_Msk, HASH_CR_MODE_Pos, + HASH_MODE_HMAC) | + whal_SetBits(HASH_CR_LKEY_Msk, HASH_CR_LKEY_Pos, lkey) | + HASH_CR_INIT_Msk); /* Inner key */ WriteTail(base, (const uint8_t *)key, keySz); - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, - HASH_STR_DCAL_Msk); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); err = WaitForReady(base, cfg->timeout); if (err) { @@ -890,7 +890,7 @@ whal_Error whal_Stm32wba_HmacSha224_Finalize(whal_HmacSha224 *dev, { const whal_Stm32wba_Hash_Cfg *cfg = (const whal_Stm32wba_Hash_Cfg *)whal_Stm32wba_Hash_Dev.cfg; - size_t base = whal_Stm32wba_Hash_Dev.base; + uintptr_t base = whal_Stm32wba_Hash_Dev.base; whal_Error err; (void)dev; @@ -903,11 +903,11 @@ whal_Error whal_Stm32wba_HmacSha224_Finalize(whal_HmacSha224 *dev, } /* Drain any buffered tail bytes, then DCAL to close message phase. */ - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); StreamDrain(base); - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, - HASH_STR_DCAL_Msk); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); err = WaitForReady(base, cfg->timeout); if (err) { @@ -916,11 +916,11 @@ whal_Error whal_Stm32wba_HmacSha224_Finalize(whal_HmacSha224 *dev, } /* Outer key */ - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); WriteTail(base, (const uint8_t *)g_hmacSha224State.key, g_hmacSha224State.keySz); - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, - HASH_STR_DCAL_Msk); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); err = WaitForReady(base, cfg->timeout); if (err) { @@ -949,7 +949,7 @@ whal_Error whal_Stm32wba_HmacSha256_Oneshot(whal_HmacSha256 *dev, { const whal_Stm32wba_Hash_Cfg *cfg = (const whal_Stm32wba_Hash_Cfg *)whal_Stm32wba_Hash_Dev.cfg; - size_t base = whal_Stm32wba_Hash_Dev.base; + uintptr_t base = whal_Stm32wba_Hash_Dev.base; size_t lkey; whal_Error err; (void)dev; @@ -964,22 +964,22 @@ whal_Error whal_Stm32wba_HmacSha256_Oneshot(whal_HmacSha256 *dev, lkey = (keySz > 64) ? 1 : 0; - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); - whal_Reg_Update(base, HASH_CR_REG, - HASH_CR_ALGO_Msk | HASH_CR_DATATYPE_Msk | - HASH_CR_MODE_Msk | HASH_CR_LKEY_Msk | HASH_CR_INIT_Msk, - AlgoBits(HASH_ALGO_SHA256) | - whal_SetBits(HASH_CR_MODE_Msk, HASH_CR_MODE_Pos, - HASH_MODE_HMAC) | - whal_SetBits(HASH_CR_LKEY_Msk, HASH_CR_LKEY_Pos, lkey) | - HASH_CR_INIT_Msk); + whal_Reg32_Update(base, HASH_CR_REG, + HASH_CR_ALGO_Msk | HASH_CR_DATATYPE_Msk | + HASH_CR_MODE_Msk | HASH_CR_LKEY_Msk | HASH_CR_INIT_Msk, + AlgoBits(HASH_ALGO_SHA256) | + whal_SetBits(HASH_CR_MODE_Msk, HASH_CR_MODE_Pos, + HASH_MODE_HMAC) | + whal_SetBits(HASH_CR_LKEY_Msk, HASH_CR_LKEY_Pos, lkey) | + HASH_CR_INIT_Msk); /* Inner key */ WriteTail(base, (const uint8_t *)key, keySz); - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, - HASH_STR_DCAL_Msk); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); err = WaitForReady(base, cfg->timeout); if (err) { @@ -988,12 +988,12 @@ whal_Error whal_Stm32wba_HmacSha256_Oneshot(whal_HmacSha256 *dev, } /* Message */ - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); if (inSz > 0) WriteTail(base, (const uint8_t *)in, inSz); - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, - HASH_STR_DCAL_Msk); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); err = WaitForReady(base, cfg->timeout); if (err) { @@ -1002,11 +1002,11 @@ whal_Error whal_Stm32wba_HmacSha256_Oneshot(whal_HmacSha256 *dev, } /* Outer key */ - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); WriteTail(base, (const uint8_t *)key, keySz); - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, - HASH_STR_DCAL_Msk); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); err = WaitForReady(base, cfg->timeout); if (err) { @@ -1023,7 +1023,7 @@ whal_Error whal_Stm32wba_HmacSha256_Start(whal_HmacSha256 *dev, { const whal_Stm32wba_Hash_Cfg *cfg = (const whal_Stm32wba_Hash_Cfg *)whal_Stm32wba_Hash_Dev.cfg; - size_t base = whal_Stm32wba_Hash_Dev.base; + uintptr_t base = whal_Stm32wba_Hash_Dev.base; size_t lkey; whal_Error err; (void)dev; @@ -1033,22 +1033,22 @@ whal_Error whal_Stm32wba_HmacSha256_Start(whal_HmacSha256 *dev, lkey = (keySz > 64) ? 1 : 0; - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); - whal_Reg_Update(base, HASH_CR_REG, - HASH_CR_ALGO_Msk | HASH_CR_DATATYPE_Msk | - HASH_CR_MODE_Msk | HASH_CR_LKEY_Msk | HASH_CR_INIT_Msk, - AlgoBits(HASH_ALGO_SHA256) | - whal_SetBits(HASH_CR_MODE_Msk, HASH_CR_MODE_Pos, - HASH_MODE_HMAC) | - whal_SetBits(HASH_CR_LKEY_Msk, HASH_CR_LKEY_Pos, lkey) | - HASH_CR_INIT_Msk); + whal_Reg32_Update(base, HASH_CR_REG, + HASH_CR_ALGO_Msk | HASH_CR_DATATYPE_Msk | + HASH_CR_MODE_Msk | HASH_CR_LKEY_Msk | HASH_CR_INIT_Msk, + AlgoBits(HASH_ALGO_SHA256) | + whal_SetBits(HASH_CR_MODE_Msk, HASH_CR_MODE_Pos, + HASH_MODE_HMAC) | + whal_SetBits(HASH_CR_LKEY_Msk, HASH_CR_LKEY_Pos, lkey) | + HASH_CR_INIT_Msk); /* Inner key */ WriteTail(base, (const uint8_t *)key, keySz); - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, - HASH_STR_DCAL_Msk); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); err = WaitForReady(base, cfg->timeout); if (err) { @@ -1081,7 +1081,7 @@ whal_Error whal_Stm32wba_HmacSha256_Finalize(whal_HmacSha256 *dev, { const whal_Stm32wba_Hash_Cfg *cfg = (const whal_Stm32wba_Hash_Cfg *)whal_Stm32wba_Hash_Dev.cfg; - size_t base = whal_Stm32wba_Hash_Dev.base; + uintptr_t base = whal_Stm32wba_Hash_Dev.base; whal_Error err; (void)dev; @@ -1094,11 +1094,11 @@ whal_Error whal_Stm32wba_HmacSha256_Finalize(whal_HmacSha256 *dev, } /* Drain any buffered tail bytes, then DCAL to close message phase. */ - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); StreamDrain(base); - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, - HASH_STR_DCAL_Msk); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); err = WaitForReady(base, cfg->timeout); if (err) { @@ -1107,11 +1107,11 @@ whal_Error whal_Stm32wba_HmacSha256_Finalize(whal_HmacSha256 *dev, } /* Outer key */ - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); WriteTail(base, (const uint8_t *)g_hmacSha256State.key, g_hmacSha256State.keySz); - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, - HASH_STR_DCAL_Msk); + whal_Reg32_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); err = WaitForReady(base, cfg->timeout); if (err) { diff --git a/src/dma/stm32wb_dma.c b/src/dma/stm32wb_dma.c index ecc7c056..81e867f6 100644 --- a/src/dma/stm32wb_dma.c +++ b/src/dma/stm32wb_dma.c @@ -129,11 +129,11 @@ whal_Error whal_Stm32wb_Dma_Init(whal_Dma *dmaDev) #ifdef WHAL_CFG_STM32WB_DMA_SINGLE_INSTANCE whal_Stm32wb_Dma_Cfg *cfg = (whal_Stm32wb_Dma_Cfg *)whal_Stm32wb_Dma_Dev.cfg; - size_t base = whal_Stm32wb_Dma_Dev.base; + uintptr_t base = whal_Stm32wb_Dma_Dev.base; (void)dmaDev; #else whal_Stm32wb_Dma_Cfg *cfg; - size_t base; + uintptr_t base; if (!dmaDev || !dmaDev->cfg) { return WHAL_EINVAL; @@ -149,7 +149,7 @@ whal_Error whal_Stm32wb_Dma_Init(whal_Dma *dmaDev) for (size_t i = 1; i <= cfg->numChannels; ++i) { clearAll |= DMA_IFCR_CALL(i); } - whal_Reg_Write(base, DMA_IFCR_REG, clearAll); + whal_Reg32_Write(base, DMA_IFCR_REG, clearAll); } return WHAL_SUCCESS; @@ -160,11 +160,11 @@ whal_Error whal_Stm32wb_Dma_Deinit(whal_Dma *dmaDev) #ifdef WHAL_CFG_STM32WB_DMA_SINGLE_INSTANCE whal_Stm32wb_Dma_Cfg *cfg = (whal_Stm32wb_Dma_Cfg *)whal_Stm32wb_Dma_Dev.cfg; - size_t base = whal_Stm32wb_Dma_Dev.base; + uintptr_t base = whal_Stm32wb_Dma_Dev.base; (void)dmaDev; #else whal_Stm32wb_Dma_Cfg *cfg; - size_t base; + uintptr_t base; if (!dmaDev || !dmaDev->cfg) { return WHAL_EINVAL; @@ -176,9 +176,9 @@ whal_Error whal_Stm32wb_Dma_Deinit(whal_Dma *dmaDev) /* Disable all channels and clear all interrupt flags */ for (size_t i = 1; i <= cfg->numChannels; ++i) { - whal_Reg_Update(base, DMA_CCR_REG(i), - DMA_CCR_EN_Msk, - whal_SetBits(DMA_CCR_EN_Msk, DMA_CCR_EN_Pos, 0)); + whal_Reg32_Update(base, DMA_CCR_REG(i), + DMA_CCR_EN_Msk, + whal_SetBits(DMA_CCR_EN_Msk, DMA_CCR_EN_Pos, 0)); } { @@ -186,7 +186,7 @@ whal_Error whal_Stm32wb_Dma_Deinit(whal_Dma *dmaDev) for (size_t i = 1; i <= cfg->numChannels; ++i) { clearAll |= DMA_IFCR_CALL(i); } - whal_Reg_Write(base, DMA_IFCR_REG, clearAll); + whal_Reg32_Write(base, DMA_IFCR_REG, clearAll); } return WHAL_SUCCESS; @@ -207,7 +207,7 @@ whal_Error whal_Stm32wb_Dma_Configure(whal_Dma *dmaDev, size_t ch, #ifdef WHAL_CFG_STM32WB_DMA_SINGLE_INSTANCE whal_Stm32wb_Dma_Cfg *cfg = (whal_Stm32wb_Dma_Cfg *)whal_Stm32wb_Dma_Dev.cfg; - size_t base = whal_Stm32wb_Dma_Dev.base; + uintptr_t base = whal_Stm32wb_Dma_Dev.base; (void)dmaDev; if (!chCfg) { @@ -215,7 +215,7 @@ whal_Error whal_Stm32wb_Dma_Configure(whal_Dma *dmaDev, size_t ch, } #else whal_Stm32wb_Dma_Cfg *cfg; - size_t base; + uintptr_t base; if (!dmaDev || !dmaDev->cfg || !chCfg) { return WHAL_EINVAL; @@ -306,19 +306,19 @@ whal_Error whal_Stm32wb_Dma_Configure(whal_Dma *dmaDev, size_t ch, ccr |= whal_SetBits(DMA_CCR_TEIE_Msk, DMA_CCR_TEIE_Pos, 1); /* Write channel registers. EN must be 0 before writing CCR fields. */ - whal_Reg_Write(base, DMA_CCR_REG(hw_ch), 0); - whal_Reg_Write(base, DMA_CNDTR_REG(hw_ch), dmaChCfg->length); - whal_Reg_Write(base, DMA_CPAR_REG(hw_ch), periphAddr); - whal_Reg_Write(base, DMA_CMAR_REG(hw_ch), memAddr); - whal_Reg_Write(base, DMA_CCR_REG(hw_ch), ccr); + whal_Reg32_Write(base, DMA_CCR_REG(hw_ch), 0); + whal_Reg32_Write(base, DMA_CNDTR_REG(hw_ch), dmaChCfg->length); + whal_Reg32_Write(base, DMA_CPAR_REG(hw_ch), periphAddr); + whal_Reg32_Write(base, DMA_CMAR_REG(hw_ch), memAddr); + whal_Reg32_Write(base, DMA_CCR_REG(hw_ch), ccr); /* Configure DMAMUX request mapping */ size_t muxCh = cfg->dmamuxChOffset + ch; - whal_Reg_Update(cfg->dmamuxBase, DMAMUX_CxCR_REG(muxCh), - DMAMUX_CxCR_DMAREQ_ID_Msk, - whal_SetBits(DMAMUX_CxCR_DMAREQ_ID_Msk, - DMAMUX_CxCR_DMAREQ_ID_Pos, - dmaChCfg->dmamuxReqId)); + whal_Reg32_Update(cfg->dmamuxBase, DMAMUX_CxCR_REG(muxCh), + DMAMUX_CxCR_DMAREQ_ID_Msk, + whal_SetBits(DMAMUX_CxCR_DMAREQ_ID_Msk, + DMAMUX_CxCR_DMAREQ_ID_Pos, + dmaChCfg->dmamuxReqId)); return WHAL_SUCCESS; } @@ -329,11 +329,11 @@ whal_Error whal_Stm32wb_Dma_Start(whal_Dma *dmaDev, size_t ch) #ifdef WHAL_CFG_STM32WB_DMA_SINGLE_INSTANCE whal_Stm32wb_Dma_Cfg *cfg = (whal_Stm32wb_Dma_Cfg *)whal_Stm32wb_Dma_Dev.cfg; - size_t base = whal_Stm32wb_Dma_Dev.base; + uintptr_t base = whal_Stm32wb_Dma_Dev.base; (void)dmaDev; #else whal_Stm32wb_Dma_Cfg *cfg; - size_t base; + uintptr_t base; if (!dmaDev || !dmaDev->cfg) { return WHAL_EINVAL; @@ -350,12 +350,12 @@ whal_Error whal_Stm32wb_Dma_Start(whal_Dma *dmaDev, size_t ch) hw_ch = ch + 1; /* Clear stale interrupt flags before enabling (TRM requires this) */ - whal_Reg_Write(base, DMA_IFCR_REG, DMA_IFCR_CALL(hw_ch)); + whal_Reg32_Write(base, DMA_IFCR_REG, DMA_IFCR_CALL(hw_ch)); /* Enable the channel */ - whal_Reg_Update(base, DMA_CCR_REG(hw_ch), - DMA_CCR_EN_Msk, - whal_SetBits(DMA_CCR_EN_Msk, DMA_CCR_EN_Pos, 1)); + whal_Reg32_Update(base, DMA_CCR_REG(hw_ch), + DMA_CCR_EN_Msk, + whal_SetBits(DMA_CCR_EN_Msk, DMA_CCR_EN_Pos, 1)); return WHAL_SUCCESS; } @@ -366,11 +366,11 @@ whal_Error whal_Stm32wb_Dma_Stop(whal_Dma *dmaDev, size_t ch) #ifdef WHAL_CFG_STM32WB_DMA_SINGLE_INSTANCE whal_Stm32wb_Dma_Cfg *cfg = (whal_Stm32wb_Dma_Cfg *)whal_Stm32wb_Dma_Dev.cfg; - size_t base = whal_Stm32wb_Dma_Dev.base; + uintptr_t base = whal_Stm32wb_Dma_Dev.base; (void)dmaDev; #else whal_Stm32wb_Dma_Cfg *cfg; - size_t base; + uintptr_t base; if (!dmaDev || !dmaDev->cfg) { return WHAL_EINVAL; @@ -387,12 +387,12 @@ whal_Error whal_Stm32wb_Dma_Stop(whal_Dma *dmaDev, size_t ch) hw_ch = ch + 1; /* Disable the channel */ - whal_Reg_Update(base, DMA_CCR_REG(hw_ch), - DMA_CCR_EN_Msk, - whal_SetBits(DMA_CCR_EN_Msk, DMA_CCR_EN_Pos, 0)); + whal_Reg32_Update(base, DMA_CCR_REG(hw_ch), + DMA_CCR_EN_Msk, + whal_SetBits(DMA_CCR_EN_Msk, DMA_CCR_EN_Pos, 0)); /* Clear channel interrupt flags */ - whal_Reg_Write(base, DMA_IFCR_REG, DMA_IFCR_CALL(hw_ch)); + whal_Reg32_Write(base, DMA_IFCR_REG, DMA_IFCR_CALL(hw_ch)); return WHAL_SUCCESS; } @@ -403,10 +403,10 @@ void whal_Stm32wb_Dma_IRQHandler(whal_Dma *dmaDev, size_t ch, size_t hw_ch; size_t isr; #ifdef WHAL_CFG_STM32WB_DMA_SINGLE_INSTANCE - size_t base = whal_Stm32wb_Dma_Dev.base; + uintptr_t base = whal_Stm32wb_Dma_Dev.base; (void)dmaDev; #else - size_t base; + uintptr_t base; if (!dmaDev) return; @@ -416,18 +416,18 @@ void whal_Stm32wb_Dma_IRQHandler(whal_Dma *dmaDev, size_t ch, hw_ch = ch + 1; - isr = whal_Reg_Read(base, DMA_ISR_REG); + isr = whal_Reg32_Read(base, DMA_ISR_REG); if (isr & (1UL << DMA_ISR_TEIF_Pos(hw_ch))) { - whal_Reg_Write(base, DMA_IFCR_REG, - DMA_IFCR_CTEIF(hw_ch) | DMA_IFCR_CTCIF(hw_ch)); + whal_Reg32_Write(base, DMA_IFCR_REG, + DMA_IFCR_CTEIF(hw_ch) | DMA_IFCR_CTCIF(hw_ch)); if (cb) cb(ctx, WHAL_EHARDWARE); return; } if (isr & (1UL << DMA_ISR_TCIF_Pos(hw_ch))) { - whal_Reg_Write(base, DMA_IFCR_REG, DMA_IFCR_CTCIF(hw_ch)); + whal_Reg32_Write(base, DMA_IFCR_REG, DMA_IFCR_CTCIF(hw_ch)); if (cb) cb(ctx, WHAL_SUCCESS); } diff --git a/src/dma/stm32wba_gpdma.c b/src/dma/stm32wba_gpdma.c index 9ff38e12..2c5add8e 100644 --- a/src/dma/stm32wba_gpdma.c +++ b/src/dma/stm32wba_gpdma.c @@ -141,21 +141,21 @@ const whal_Dma whal_Stm32wba_Gpdma_Dev = WHAL_CFG_STM32WBA_GPDMA_DEV; #endif /* Abort an enabled channel: suspend, wait for idle, then reset */ -static whal_Error Gpdma_AbortChannel(size_t base, size_t ch, +static whal_Error Gpdma_AbortChannel(uintptr_t base, size_t ch, whal_Timeout *timeout) { size_t cr; whal_Error err; - cr = whal_Reg_Read(base, GPDMA_CxCR(ch)); + cr = whal_Reg32_Read(base, GPDMA_CxCR(ch)); if (cr & GPDMA_CxCR_EN_Msk) { - whal_Reg_Write(base, GPDMA_CxCR(ch), - (cr & ~GPDMA_CxCR_EN_Msk) | GPDMA_CxCR_SUSP_Msk); - err = whal_Reg_ReadPoll(base, GPDMA_CxSR(ch), GPDMA_CxSR_IDLEF_Msk, + whal_Reg32_Write(base, GPDMA_CxCR(ch), + (cr & ~GPDMA_CxCR_EN_Msk) | GPDMA_CxCR_SUSP_Msk); + err = whal_Reg32_ReadPoll(base, GPDMA_CxSR(ch), GPDMA_CxSR_IDLEF_Msk, GPDMA_CxSR_IDLEF_Msk, timeout); if (err) return err; - whal_Reg_Write(base, GPDMA_CxCR(ch), GPDMA_CxCR_RESET_Msk); + whal_Reg32_Write(base, GPDMA_CxCR(ch), GPDMA_CxCR_RESET_Msk); } return WHAL_SUCCESS; @@ -180,11 +180,11 @@ whal_Error whal_Stm32wba_Gpdma_Deinit(whal_Dma *dmaDev) #ifdef WHAL_CFG_STM32WBA_GPDMA_SINGLE_INSTANCE const whal_Stm32wba_Gpdma_Cfg *cfg = (const whal_Stm32wba_Gpdma_Cfg *)whal_Stm32wba_Gpdma_Dev.cfg; - size_t base = whal_Stm32wba_Gpdma_Dev.base; + uintptr_t base = whal_Stm32wba_Gpdma_Dev.base; (void)dmaDev; #else const whal_Stm32wba_Gpdma_Cfg *cfg; - size_t base; + uintptr_t base; if (!dmaDev || !dmaDev->cfg) return WHAL_EINVAL; @@ -201,8 +201,8 @@ whal_Error whal_Stm32wba_Gpdma_Deinit(whal_Dma *dmaDev) err = abortErr; continue; } - whal_Reg_Write(base, GPDMA_CxCR(ch), - GPDMA_CxCR_RESET_Msk); + whal_Reg32_Write(base, GPDMA_CxCR(ch), + GPDMA_CxCR_RESET_Msk); } return err; @@ -217,14 +217,14 @@ whal_Error whal_Stm32wba_Gpdma_Configure(whal_Dma *dmaDev, size_t ch, #ifdef WHAL_CFG_STM32WBA_GPDMA_SINGLE_INSTANCE const whal_Stm32wba_Gpdma_Cfg *cfg = (const whal_Stm32wba_Gpdma_Cfg *)whal_Stm32wba_Gpdma_Dev.cfg; - size_t base = whal_Stm32wba_Gpdma_Dev.base; + uintptr_t base = whal_Stm32wba_Gpdma_Dev.base; (void)dmaDev; if (!chCfg) return WHAL_EINVAL; #else const whal_Stm32wba_Gpdma_Cfg *cfg; - size_t base; + uintptr_t base; if (!dmaDev || !dmaDev->cfg || !chCfg) return WHAL_EINVAL; @@ -246,14 +246,14 @@ whal_Error whal_Stm32wba_Gpdma_Configure(whal_Dma *dmaDev, size_t ch, return WHAL_EINVAL; /* Reset the channel and wait for idle */ - whal_Reg_Write(base, GPDMA_CxCR(ch), GPDMA_CxCR_RESET_Msk); - err = whal_Reg_ReadPoll(base, GPDMA_CxSR(ch), GPDMA_CxSR_IDLEF_Msk, + whal_Reg32_Write(base, GPDMA_CxCR(ch), GPDMA_CxCR_RESET_Msk); + err = whal_Reg32_ReadPoll(base, GPDMA_CxSR(ch), GPDMA_CxSR_IDLEF_Msk, GPDMA_CxSR_IDLEF_Msk, cfg->timeout); if (err) return err; /* Clear any pending flags */ - whal_Reg_Write(base, GPDMA_CxFCR(ch), GPDMA_CxFCR_ALL); + whal_Reg32_Write(base, GPDMA_CxFCR(ch), GPDMA_CxFCR_ALL); /* Build CxTR1: source and destination widths and increment modes. * Route the memory side to port 1 and the peripheral side to port 0 @@ -269,7 +269,7 @@ whal_Error whal_Stm32wba_Gpdma_Configure(whal_Dma *dmaDev, size_t ch, else if (ccfg->dir == WHAL_STM32WBA_GPDMA_DIR_PERIPH_TO_MEM) tr1 |= GPDMA_CxTR1_DAP_Msk; - whal_Reg_Write(base, GPDMA_CxTR1(ch), tr1); + whal_Reg32_Write(base, GPDMA_CxTR1(ch), tr1); /* Build CxTR2: request selection and direction */ tr2 = 0; @@ -281,22 +281,22 @@ whal_Error whal_Stm32wba_Gpdma_Configure(whal_Dma *dmaDev, size_t ch, if (ccfg->dir == WHAL_STM32WBA_GPDMA_DIR_MEM_TO_PERIPH) tr2 |= GPDMA_CxTR2_DREQ_Msk; } - whal_Reg_Write(base, GPDMA_CxTR2(ch), tr2); + whal_Reg32_Write(base, GPDMA_CxTR2(ch), tr2); /* Byte count and addresses */ - whal_Reg_Write(base, GPDMA_CxBR1(ch), ccfg->nbytes); - whal_Reg_Write(base, GPDMA_CxSAR(ch), ccfg->srcAddr); - whal_Reg_Write(base, GPDMA_CxDAR(ch), ccfg->dstAddr); + whal_Reg32_Write(base, GPDMA_CxBR1(ch), ccfg->nbytes); + whal_Reg32_Write(base, GPDMA_CxSAR(ch), ccfg->srcAddr); + whal_Reg32_Write(base, GPDMA_CxDAR(ch), ccfg->dstAddr); /* No linked-list */ - whal_Reg_Write(base, GPDMA_CxLLR(ch), 0); + whal_Reg32_Write(base, GPDMA_CxLLR(ch), 0); /* Enable transfer complete and error interrupts. Run the channel at * high priority so it isn't starved by concurrent CPU/AHB traffic. */ - whal_Reg_Write(base, GPDMA_CxCR(ch), - GPDMA_CxCR_TCIE_Msk | GPDMA_CxCR_DTEIE_Msk | - GPDMA_CxCR_ULEIE_Msk | GPDMA_CxCR_USEIE_Msk | - whal_SetBits(GPDMA_CxCR_PRIO_Msk, GPDMA_CxCR_PRIO_Pos, 3)); + whal_Reg32_Write(base, GPDMA_CxCR(ch), + GPDMA_CxCR_TCIE_Msk | GPDMA_CxCR_DTEIE_Msk | + GPDMA_CxCR_ULEIE_Msk | GPDMA_CxCR_USEIE_Msk | + whal_SetBits(GPDMA_CxCR_PRIO_Msk, GPDMA_CxCR_PRIO_Pos, 3)); return WHAL_SUCCESS; } @@ -306,11 +306,11 @@ whal_Error whal_Stm32wba_Gpdma_Start(whal_Dma *dmaDev, size_t ch) #ifdef WHAL_CFG_STM32WBA_GPDMA_SINGLE_INSTANCE const whal_Stm32wba_Gpdma_Cfg *cfg = (const whal_Stm32wba_Gpdma_Cfg *)whal_Stm32wba_Gpdma_Dev.cfg; - size_t base = whal_Stm32wba_Gpdma_Dev.base; + uintptr_t base = whal_Stm32wba_Gpdma_Dev.base; (void)dmaDev; #else const whal_Stm32wba_Gpdma_Cfg *cfg; - size_t base; + uintptr_t base; if (!dmaDev || !dmaDev->cfg) return WHAL_EINVAL; @@ -323,11 +323,11 @@ whal_Error whal_Stm32wba_Gpdma_Start(whal_Dma *dmaDev, size_t ch) return WHAL_EINVAL; /* Clear any stale flags from the previous transfer before enabling */ - whal_Reg_Write(base, GPDMA_CxFCR(ch), GPDMA_CxFCR_ALL); + whal_Reg32_Write(base, GPDMA_CxFCR(ch), GPDMA_CxFCR_ALL); /* Set EN bit without disturbing the already-configured interrupt enables */ - whal_Reg_Update(base, GPDMA_CxCR(ch), GPDMA_CxCR_EN_Msk, - GPDMA_CxCR_EN_Msk); + whal_Reg32_Update(base, GPDMA_CxCR(ch), GPDMA_CxCR_EN_Msk, + GPDMA_CxCR_EN_Msk); return WHAL_SUCCESS; } @@ -338,11 +338,11 @@ whal_Error whal_Stm32wba_Gpdma_Stop(whal_Dma *dmaDev, size_t ch) #ifdef WHAL_CFG_STM32WBA_GPDMA_SINGLE_INSTANCE const whal_Stm32wba_Gpdma_Cfg *cfg = (const whal_Stm32wba_Gpdma_Cfg *)whal_Stm32wba_Gpdma_Dev.cfg; - size_t base = whal_Stm32wba_Gpdma_Dev.base; + uintptr_t base = whal_Stm32wba_Gpdma_Dev.base; (void)dmaDev; #else const whal_Stm32wba_Gpdma_Cfg *cfg; - size_t base; + uintptr_t base; if (!dmaDev || !dmaDev->cfg) return WHAL_EINVAL; @@ -359,7 +359,7 @@ whal_Error whal_Stm32wba_Gpdma_Stop(whal_Dma *dmaDev, size_t ch) if (err) return err; - whal_Reg_Write(base, GPDMA_CxFCR(ch), GPDMA_CxFCR_ALL); + whal_Reg32_Write(base, GPDMA_CxFCR(ch), GPDMA_CxFCR_ALL); return WHAL_SUCCESS; } @@ -369,33 +369,33 @@ void whal_Stm32wba_Gpdma_IRQHandler(whal_Dma *dmaDev, size_t ch, { size_t sr; #ifdef WHAL_CFG_STM32WBA_GPDMA_SINGLE_INSTANCE - size_t base = whal_Stm32wba_Gpdma_Dev.base; + uintptr_t base = whal_Stm32wba_Gpdma_Dev.base; (void)dmaDev; #else - size_t base; + uintptr_t base; if (!dmaDev) return; base = dmaDev->base; #endif - sr = whal_Reg_Read(base, GPDMA_CxSR(ch)); + sr = whal_Reg32_Read(base, GPDMA_CxSR(ch)); if (sr & GPDMA_CxSR_ALL_ERR) { - whal_Reg_Write(base, GPDMA_CxFCR(ch), GPDMA_CxSR_ALL_ERR); + whal_Reg32_Write(base, GPDMA_CxFCR(ch), GPDMA_CxSR_ALL_ERR); if (cb) cb(ctx, WHAL_EHARDWARE); return; } if (sr & GPDMA_CxSR_TCF_Msk) { - whal_Reg_Write(base, GPDMA_CxFCR(ch), GPDMA_CxSR_TCF_Msk); + whal_Reg32_Write(base, GPDMA_CxFCR(ch), GPDMA_CxSR_TCF_Msk); if (cb) cb(ctx, WHAL_SUCCESS); } if (sr & GPDMA_CxSR_HTF_Msk) { - whal_Reg_Write(base, GPDMA_CxFCR(ch), GPDMA_CxSR_HTF_Msk); + whal_Reg32_Write(base, GPDMA_CxFCR(ch), GPDMA_CxSR_HTF_Msk); } } diff --git a/src/eth/stm32h5_eth.c b/src/eth/stm32h5_eth.c index 44e21686..976639fb 100644 --- a/src/eth/stm32h5_eth.c +++ b/src/eth/stm32h5_eth.c @@ -171,17 +171,17 @@ static struct { #define whal_Stm32h5_Eth_MdioWrite whal_Eth_MdioWrite #endif /* WHAL_CFG_STM32H5_ETH_DIRECT_API_MAPPING */ -static whal_Error MdioPoll(size_t base, whal_Timeout *timeout) +static whal_Error MdioPoll(uintptr_t base, whal_Timeout *timeout) { - return whal_Reg_ReadPoll(base, ETH_MACMDIOAR_REG, - ETH_MACMDIOAR_MB_Msk, 0, timeout); + return whal_Reg32_ReadPoll(base, ETH_MACMDIOAR_REG, + ETH_MACMDIOAR_MB_Msk, 0, timeout); } whal_Error whal_Stm32h5_Eth_Init(whal_Eth *ethDev) { const whal_Stm32h5_Eth_Cfg *cfg = (const whal_Stm32h5_Eth_Cfg *)whal_Stm32h5_Eth_Dev.cfg; - size_t base = whal_Stm32h5_Eth_Dev.base; + uintptr_t base = whal_Stm32h5_Eth_Dev.base; whal_Error err; (void)ethDev; @@ -194,31 +194,31 @@ whal_Error whal_Stm32h5_Eth_Init(whal_Eth *ethDev) return WHAL_EINVAL; /* DMA software reset */ - whal_Reg_Update(base, ETH_DMAMR_REG, ETH_DMAMR_SWR_Msk, - ETH_DMAMR_SWR_Msk); - err = whal_Reg_ReadPoll(base, ETH_DMAMR_REG, ETH_DMAMR_SWR_Msk, 0, - cfg->timeout); + whal_Reg32_Update(base, ETH_DMAMR_REG, ETH_DMAMR_SWR_Msk, + ETH_DMAMR_SWR_Msk); + err = whal_Reg32_ReadPoll(base, ETH_DMAMR_REG, ETH_DMAMR_SWR_Msk, 0, + cfg->timeout); if (err) return err; /* DMA bus mode: fixed burst, address-aligned */ - whal_Reg_Write(base, ETH_DMASBMR_REG, - ETH_DMASBMR_FB_Msk | ETH_DMASBMR_AAL_Msk); + whal_Reg32_Write(base, ETH_DMASBMR_REG, + ETH_DMASBMR_FB_Msk | ETH_DMASBMR_AAL_Msk); /* DMA channel: contiguous descriptors (DSL=0) */ - whal_Reg_Write(base, ETH_DMACCR_REG, 0); + whal_Reg32_Write(base, ETH_DMACCR_REG, 0); /* DMA TX: burst length, not started yet */ - whal_Reg_Write(base, ETH_DMACTXCR_REG, - whal_SetBits(ETH_DMACTXCR_TXPBL_Msk, - ETH_DMACTXCR_TXPBL_Pos, ETH_PBL)); + whal_Reg32_Write(base, ETH_DMACTXCR_REG, + whal_SetBits(ETH_DMACTXCR_TXPBL_Msk, + ETH_DMACTXCR_TXPBL_Pos, ETH_PBL)); /* DMA RX: burst length, buffer size, not started yet */ - whal_Reg_Write(base, ETH_DMACRXCR_REG, - whal_SetBits(ETH_DMACRXCR_RXPBL_Msk, - ETH_DMACRXCR_RXPBL_Pos, ETH_PBL) | - whal_SetBits(ETH_DMACRXCR_RBSZ_Msk, - ETH_DMACRXCR_RBSZ_Pos, cfg->rxBufSize)); + whal_Reg32_Write(base, ETH_DMACRXCR_REG, + whal_SetBits(ETH_DMACRXCR_RXPBL_Msk, + ETH_DMACRXCR_RXPBL_Pos, ETH_PBL) | + whal_SetBits(ETH_DMACRXCR_RBSZ_Msk, + ETH_DMACRXCR_RBSZ_Pos, cfg->rxBufSize)); /* Set up TX descriptor ring */ for (size_t i = 0; i < cfg->txDescCount; i++) { @@ -237,29 +237,29 @@ whal_Error whal_Stm32h5_Eth_Init(whal_Eth *ethDev) } /* Program descriptor ring addresses and lengths */ - whal_Reg_Write(base, ETH_DMACTXDLAR_REG, (uintptr_t)cfg->txDescs); - whal_Reg_Write(base, ETH_DMACRXDLAR_REG, (uintptr_t)cfg->rxDescs); - whal_Reg_Write(base, ETH_DMACTXRLR_REG, cfg->txDescCount - 1); - whal_Reg_Write(base, ETH_DMACRXRLR_REG, cfg->rxDescCount - 1); + whal_Reg32_Write(base, ETH_DMACTXDLAR_REG, (uintptr_t)cfg->txDescs); + whal_Reg32_Write(base, ETH_DMACRXDLAR_REG, (uintptr_t)cfg->rxDescs); + whal_Reg32_Write(base, ETH_DMACTXRLR_REG, cfg->txDescCount - 1); + whal_Reg32_Write(base, ETH_DMACRXRLR_REG, cfg->rxDescCount - 1); /* MTL: store-and-forward for TX and RX, enable TX queue */ - whal_Reg_Update(base, ETH_MTLTXQOMR_REG, - ETH_MTLTXQOMR_TSF_Msk | ETH_MTLTXQOMR_TXQEN_Msk, - ETH_MTLTXQOMR_TSF_Msk | - whal_SetBits(ETH_MTLTXQOMR_TXQEN_Msk, - ETH_MTLTXQOMR_TXQEN_Pos, 2)); - whal_Reg_Update(base, ETH_MTLRXQOMR_REG, - ETH_MTLRXQOMR_RSF_Msk, ETH_MTLRXQOMR_RSF_Msk); + whal_Reg32_Update(base, ETH_MTLTXQOMR_REG, + ETH_MTLTXQOMR_TSF_Msk | ETH_MTLTXQOMR_TXQEN_Msk, + ETH_MTLTXQOMR_TSF_Msk | + whal_SetBits(ETH_MTLTXQOMR_TXQEN_Msk, + ETH_MTLTXQOMR_TXQEN_Pos, 2)); + whal_Reg32_Update(base, ETH_MTLRXQOMR_REG, + ETH_MTLRXQOMR_RSF_Msk, ETH_MTLRXQOMR_RSF_Msk); /* MAC address */ - whal_Reg_Write(base, ETH_MACA0LR_REG, - ((uint32_t)whal_Stm32h5_Eth_Dev.macAddr[3] << 24) | - ((uint32_t)whal_Stm32h5_Eth_Dev.macAddr[2] << 16) | - ((uint32_t)whal_Stm32h5_Eth_Dev.macAddr[1] << 8) | - ((uint32_t)whal_Stm32h5_Eth_Dev.macAddr[0])); - whal_Reg_Write(base, ETH_MACA0HR_REG, - ((uint32_t)whal_Stm32h5_Eth_Dev.macAddr[5] << 8) | - ((uint32_t)whal_Stm32h5_Eth_Dev.macAddr[4])); + whal_Reg32_Write(base, ETH_MACA0LR_REG, + ((uint32_t)whal_Stm32h5_Eth_Dev.macAddr[3] << 24) | + ((uint32_t)whal_Stm32h5_Eth_Dev.macAddr[2] << 16) | + ((uint32_t)whal_Stm32h5_Eth_Dev.macAddr[1] << 8) | + ((uint32_t)whal_Stm32h5_Eth_Dev.macAddr[0])); + whal_Reg32_Write(base, ETH_MACA0HR_REG, + ((uint32_t)whal_Stm32h5_Eth_Dev.macAddr[5] << 8) | + ((uint32_t)whal_Stm32h5_Eth_Dev.macAddr[4])); /* Reset ring tracking state */ eth_state.txHead = 0; @@ -274,8 +274,8 @@ whal_Error whal_Stm32h5_Eth_Init(whal_Eth *ethDev) whal_Error whal_Stm32h5_Eth_Deinit(whal_Eth *ethDev) { (void)ethDev; - whal_Reg_Update(whal_Stm32h5_Eth_Dev.base, ETH_DMAMR_REG, - ETH_DMAMR_SWR_Msk, ETH_DMAMR_SWR_Msk); + whal_Reg32_Update(whal_Stm32h5_Eth_Dev.base, ETH_DMAMR_REG, + ETH_DMAMR_SWR_Msk, ETH_DMAMR_SWR_Msk); return WHAL_SUCCESS; } @@ -285,7 +285,7 @@ whal_Error whal_Stm32h5_Eth_Start(whal_Eth *ethDev, uint8_t speed, { const whal_Stm32h5_Eth_Cfg *cfg = (const whal_Stm32h5_Eth_Cfg *)whal_Stm32h5_Eth_Dev.cfg; - size_t base = whal_Stm32h5_Eth_Dev.base; + uintptr_t base = whal_Stm32h5_Eth_Dev.base; (void)ethDev; if ((speed != WHAL_ETH_SPEED_10 && speed != WHAL_ETH_SPEED_100) || @@ -293,45 +293,45 @@ whal_Error whal_Stm32h5_Eth_Start(whal_Eth *ethDev, uint8_t speed, return WHAL_EINVAL; /* Configure MAC speed and duplex to match PHY */ - whal_Reg_Update(base, ETH_MACCR_REG, - ETH_MACCR_FES_Msk | ETH_MACCR_DM_Msk, - ((speed == 100) ? ETH_MACCR_FES_Msk : 0) | - (duplex ? ETH_MACCR_DM_Msk : 0)); + whal_Reg32_Update(base, ETH_MACCR_REG, + ETH_MACCR_FES_Msk | ETH_MACCR_DM_Msk, + ((speed == 100) ? ETH_MACCR_FES_Msk : 0) | + (duplex ? ETH_MACCR_DM_Msk : 0)); /* Enable MAC TX and RX */ - whal_Reg_Update(base, ETH_MACCR_REG, - ETH_MACCR_TE_Msk | ETH_MACCR_RE_Msk, - ETH_MACCR_TE_Msk | ETH_MACCR_RE_Msk); + whal_Reg32_Update(base, ETH_MACCR_REG, + ETH_MACCR_TE_Msk | ETH_MACCR_RE_Msk, + ETH_MACCR_TE_Msk | ETH_MACCR_RE_Msk); /* Start DMA TX */ - whal_Reg_Update(base, ETH_DMACTXCR_REG, - ETH_DMACTXCR_ST_Msk, ETH_DMACTXCR_ST_Msk); + whal_Reg32_Update(base, ETH_DMACTXCR_REG, + ETH_DMACTXCR_ST_Msk, ETH_DMACTXCR_ST_Msk); /* Start DMA RX */ - whal_Reg_Update(base, ETH_DMACRXCR_REG, - ETH_DMACRXCR_SR_Msk, ETH_DMACRXCR_SR_Msk); + whal_Reg32_Update(base, ETH_DMACRXCR_REG, + ETH_DMACRXCR_SR_Msk, ETH_DMACRXCR_SR_Msk); /* Kick RX DMA by writing tail pointer past last descriptor */ - whal_Reg_Write(base, ETH_DMACRXDTPR_REG, - (uintptr_t)&cfg->rxDescs[cfg->rxDescCount]); + whal_Reg32_Write(base, ETH_DMACRXDTPR_REG, + (uintptr_t)&cfg->rxDescs[cfg->rxDescCount]); return WHAL_SUCCESS; } whal_Error whal_Stm32h5_Eth_Stop(whal_Eth *ethDev) { - size_t base = whal_Stm32h5_Eth_Dev.base; + uintptr_t base = whal_Stm32h5_Eth_Dev.base; (void)ethDev; /* Stop DMA TX */ - whal_Reg_Update(base, ETH_DMACTXCR_REG, ETH_DMACTXCR_ST_Msk, 0); + whal_Reg32_Update(base, ETH_DMACTXCR_REG, ETH_DMACTXCR_ST_Msk, 0); /* Stop DMA RX */ - whal_Reg_Update(base, ETH_DMACRXCR_REG, ETH_DMACRXCR_SR_Msk, 0); + whal_Reg32_Update(base, ETH_DMACRXCR_REG, ETH_DMACRXCR_SR_Msk, 0); /* Disable MAC TX and RX */ - whal_Reg_Update(base, ETH_MACCR_REG, - ETH_MACCR_TE_Msk | ETH_MACCR_RE_Msk, 0); + whal_Reg32_Update(base, ETH_MACCR_REG, + ETH_MACCR_TE_Msk | ETH_MACCR_RE_Msk, 0); return WHAL_SUCCESS; } @@ -343,7 +343,7 @@ whal_Error whal_Stm32h5_Eth_Send(whal_Eth *ethDev, const void *frame, const whal_Stm32h5_Eth_Cfg *cfg = (const whal_Stm32h5_Eth_Cfg *)whal_Stm32h5_Eth_Dev.cfg; whal_Stm32h5_Eth_TxDesc *desc; - size_t base = whal_Stm32h5_Eth_Dev.base; + uintptr_t base = whal_Stm32h5_Eth_Dev.base; size_t idx; (void)ethDev; @@ -374,8 +374,8 @@ whal_Error whal_Stm32h5_Eth_Send(whal_Eth *ethDev, const void *frame, __asm__ volatile ("dsb sy" ::: "memory"); /* Kick DMA — tail pointer past the end of the ring */ - whal_Reg_Write(base, ETH_DMACTXDTPR_REG, - (uintptr_t)&cfg->txDescs[cfg->txDescCount]); + whal_Reg32_Write(base, ETH_DMACTXDTPR_REG, + (uintptr_t)&cfg->txDescs[cfg->txDescCount]); return WHAL_SUCCESS; } @@ -387,7 +387,7 @@ whal_Error whal_Stm32h5_Eth_Recv(whal_Eth *ethDev, void *frame, const whal_Stm32h5_Eth_Cfg *cfg = (const whal_Stm32h5_Eth_Cfg *)whal_Stm32h5_Eth_Dev.cfg; whal_Stm32h5_Eth_RxDesc *desc; - size_t base = whal_Stm32h5_Eth_Dev.base; + uintptr_t base = whal_Stm32h5_Eth_Dev.base; size_t idx; uint32_t rdes3; size_t pktLen; @@ -414,8 +414,8 @@ whal_Error whal_Stm32h5_Eth_Recv(whal_Eth *ethDev, void *frame, desc->des[3] = RDES3_OWN | RDES3_IOC | RDES3_BUF1V; eth_state.rxHead = (idx + 1) % cfg->rxDescCount; __asm__ volatile ("dsb sy" ::: "memory"); - whal_Reg_Write(base, ETH_DMACRXDTPR_REG, - (uintptr_t)&cfg->rxDescs[cfg->rxDescCount]); + whal_Reg32_Write(base, ETH_DMACRXDTPR_REG, + (uintptr_t)&cfg->rxDescs[cfg->rxDescCount]); return WHAL_EHARDWARE; } @@ -445,8 +445,8 @@ whal_Error whal_Stm32h5_Eth_Recv(whal_Eth *ethDev, void *frame, __asm__ volatile ("dsb sy" ::: "memory"); /* Update RX tail pointer — always past end of ring */ - whal_Reg_Write(base, ETH_DMACRXDTPR_REG, - (uintptr_t)&cfg->rxDescs[cfg->rxDescCount]); + whal_Reg32_Write(base, ETH_DMACRXDTPR_REG, + (uintptr_t)&cfg->rxDescs[cfg->rxDescCount]); return WHAL_SUCCESS; } @@ -456,7 +456,7 @@ whal_Error whal_Stm32h5_Eth_MdioRead(whal_Eth *ethDev, uint8_t phyAddr, { const whal_Stm32h5_Eth_Cfg *cfg = (const whal_Stm32h5_Eth_Cfg *)whal_Stm32h5_Eth_Dev.cfg; - size_t base = whal_Stm32h5_Eth_Dev.base; + uintptr_t base = whal_Stm32h5_Eth_Dev.base; whal_Error err; (void)ethDev; @@ -467,22 +467,22 @@ whal_Error whal_Stm32h5_Eth_MdioRead(whal_Eth *ethDev, uint8_t phyAddr, if (err) return err; - whal_Reg_Write(base, ETH_MACMDIOAR_REG, - whal_SetBits(ETH_MACMDIOAR_PA_Msk, ETH_MACMDIOAR_PA_Pos, - phyAddr) | - whal_SetBits(ETH_MACMDIOAR_RDA_Msk, ETH_MACMDIOAR_RDA_Pos, - reg) | - whal_SetBits(ETH_MACMDIOAR_CR_Msk, ETH_MACMDIOAR_CR_Pos, - cfg->mdioCr) | - whal_SetBits(ETH_MACMDIOAR_GOC_Msk, ETH_MACMDIOAR_GOC_Pos, - ETH_MDIO_GOC_READ) | - ETH_MACMDIOAR_MB_Msk); + whal_Reg32_Write(base, ETH_MACMDIOAR_REG, + whal_SetBits(ETH_MACMDIOAR_PA_Msk, ETH_MACMDIOAR_PA_Pos, + phyAddr) | + whal_SetBits(ETH_MACMDIOAR_RDA_Msk, ETH_MACMDIOAR_RDA_Pos, + reg) | + whal_SetBits(ETH_MACMDIOAR_CR_Msk, ETH_MACMDIOAR_CR_Pos, + cfg->mdioCr) | + whal_SetBits(ETH_MACMDIOAR_GOC_Msk, ETH_MACMDIOAR_GOC_Pos, + ETH_MDIO_GOC_READ) | + ETH_MACMDIOAR_MB_Msk); err = MdioPoll(base, cfg->timeout); if (err) return err; - *val = (uint16_t)(whal_Reg_Read(base, ETH_MACMDIODR_REG) & + *val = (uint16_t)(whal_Reg32_Read(base, ETH_MACMDIODR_REG) & ETH_MACMDIODR_MD_Msk); return WHAL_SUCCESS; @@ -493,7 +493,7 @@ whal_Error whal_Stm32h5_Eth_MdioWrite(whal_Eth *ethDev, uint8_t phyAddr, { const whal_Stm32h5_Eth_Cfg *cfg = (const whal_Stm32h5_Eth_Cfg *)whal_Stm32h5_Eth_Dev.cfg; - size_t base = whal_Stm32h5_Eth_Dev.base; + uintptr_t base = whal_Stm32h5_Eth_Dev.base; whal_Error err; (void)ethDev; @@ -501,18 +501,18 @@ whal_Error whal_Stm32h5_Eth_MdioWrite(whal_Eth *ethDev, uint8_t phyAddr, if (err) return err; - whal_Reg_Write(base, ETH_MACMDIODR_REG, val); + whal_Reg32_Write(base, ETH_MACMDIODR_REG, val); - whal_Reg_Write(base, ETH_MACMDIOAR_REG, - whal_SetBits(ETH_MACMDIOAR_PA_Msk, ETH_MACMDIOAR_PA_Pos, - phyAddr) | - whal_SetBits(ETH_MACMDIOAR_RDA_Msk, ETH_MACMDIOAR_RDA_Pos, - reg) | - whal_SetBits(ETH_MACMDIOAR_CR_Msk, ETH_MACMDIOAR_CR_Pos, - cfg->mdioCr) | - whal_SetBits(ETH_MACMDIOAR_GOC_Msk, ETH_MACMDIOAR_GOC_Pos, - ETH_MDIO_GOC_WRITE) | - ETH_MACMDIOAR_MB_Msk); + whal_Reg32_Write(base, ETH_MACMDIOAR_REG, + whal_SetBits(ETH_MACMDIOAR_PA_Msk, ETH_MACMDIOAR_PA_Pos, + phyAddr) | + whal_SetBits(ETH_MACMDIOAR_RDA_Msk, ETH_MACMDIOAR_RDA_Pos, + reg) | + whal_SetBits(ETH_MACMDIOAR_CR_Msk, ETH_MACMDIOAR_CR_Pos, + cfg->mdioCr) | + whal_SetBits(ETH_MACMDIOAR_GOC_Msk, ETH_MACMDIOAR_GOC_Pos, + ETH_MDIO_GOC_WRITE) | + ETH_MACMDIOAR_MB_Msk); err = MdioPoll(base, cfg->timeout); if (err) @@ -528,9 +528,9 @@ whal_Error whal_Stm32h5_Eth_Ext_EnableLoopback(whal_Eth *ethDev, uint8_t enable) { (void)ethDev; - whal_Reg_Update(whal_Stm32h5_Eth_Dev.base, ETH_MACCR_REG, ETH_MACCR_LM_Msk, - whal_SetBits(ETH_MACCR_LM_Msk, ETH_MACCR_LM_Pos, - enable ? 1 : 0)); + whal_Reg32_Update(whal_Stm32h5_Eth_Dev.base, ETH_MACCR_REG, ETH_MACCR_LM_Msk, + whal_SetBits(ETH_MACCR_LM_Msk, ETH_MACCR_LM_Pos, + enable ? 1 : 0)); return WHAL_SUCCESS; } diff --git a/src/eth/stm32n6_eth.c b/src/eth/stm32n6_eth.c index 80303c69..62f4ab66 100644 --- a/src/eth/stm32n6_eth.c +++ b/src/eth/stm32n6_eth.c @@ -183,17 +183,17 @@ static struct { #define whal_Stm32n6_Eth_MdioWrite whal_Eth_MdioWrite #endif /* WHAL_CFG_STM32N6_ETH_DIRECT_API_MAPPING */ -static whal_Error MdioPoll(size_t base, whal_Timeout *timeout) +static whal_Error MdioPoll(uintptr_t base, whal_Timeout *timeout) { - return whal_Reg_ReadPoll(base, ETH_MACMDIOAR_REG, - ETH_MACMDIOAR_MB_Msk, 0, timeout); + return whal_Reg32_ReadPoll(base, ETH_MACMDIOAR_REG, + ETH_MACMDIOAR_MB_Msk, 0, timeout); } whal_Error whal_Stm32n6_Eth_Init(whal_Eth *ethDev) { const whal_Stm32n6_Eth_Cfg *cfg = (const whal_Stm32n6_Eth_Cfg *)whal_Stm32n6_Eth_Dev.cfg; - size_t base = whal_Stm32n6_Eth_Dev.base; + uintptr_t base = whal_Stm32n6_Eth_Dev.base; whal_Error err; (void)ethDev; @@ -205,36 +205,36 @@ whal_Error whal_Stm32n6_Eth_Init(whal_Eth *ethDev) return WHAL_EINVAL; /* DMA software reset */ - whal_Reg_Update(base, ETH_DMAMR_REG, ETH_DMAMR_SWR_Msk, - ETH_DMAMR_SWR_Msk); - err = whal_Reg_ReadPoll(base, ETH_DMAMR_REG, ETH_DMAMR_SWR_Msk, 0, - cfg->timeout); + whal_Reg32_Update(base, ETH_DMAMR_REG, ETH_DMAMR_SWR_Msk, + ETH_DMAMR_SWR_Msk); + err = whal_Reg32_ReadPoll(base, ETH_DMAMR_REG, ETH_DMAMR_SWR_Msk, 0, + cfg->timeout); if (err) return err; /* DMA bus mode: fixed burst, address-aligned */ - whal_Reg_Write(base, ETH_DMASBMR_REG, - ETH_DMASBMR_FB_Msk | ETH_DMASBMR_AAL_Msk); + whal_Reg32_Write(base, ETH_DMASBMR_REG, + ETH_DMASBMR_FB_Msk | ETH_DMASBMR_AAL_Msk); /* AXI coherency registers: use default non-cacheable settings */ - whal_Reg_Write(base, ETH_DMAA4TXACR_REG, 0); - whal_Reg_Write(base, ETH_DMAA4RXACR_REG, 0); - whal_Reg_Write(base, ETH_DMAA4DACR_REG, 0); + whal_Reg32_Write(base, ETH_DMAA4TXACR_REG, 0); + whal_Reg32_Write(base, ETH_DMAA4RXACR_REG, 0); + whal_Reg32_Write(base, ETH_DMAA4DACR_REG, 0); /* DMA channel 0: contiguous descriptors (DSL=0) */ - whal_Reg_Write(base, ETH_DMAC0CR_REG, 0); + whal_Reg32_Write(base, ETH_DMAC0CR_REG, 0); /* DMA TX: burst length, not started yet */ - whal_Reg_Write(base, ETH_DMAC0TXCR_REG, - whal_SetBits(ETH_DMAC0TXCR_TXPBL_Msk, - ETH_DMAC0TXCR_TXPBL_Pos, ETH_PBL)); + whal_Reg32_Write(base, ETH_DMAC0TXCR_REG, + whal_SetBits(ETH_DMAC0TXCR_TXPBL_Msk, + ETH_DMAC0TXCR_TXPBL_Pos, ETH_PBL)); /* DMA RX: burst length, buffer size, not started yet */ - whal_Reg_Write(base, ETH_DMAC0RXCR_REG, - whal_SetBits(ETH_DMAC0RXCR_RXPBL_Msk, - ETH_DMAC0RXCR_RXPBL_Pos, ETH_PBL) | - whal_SetBits(ETH_DMAC0RXCR_RBSZ_Msk, - ETH_DMAC0RXCR_RBSZ_Pos, cfg->rxBufSize)); + whal_Reg32_Write(base, ETH_DMAC0RXCR_REG, + whal_SetBits(ETH_DMAC0RXCR_RXPBL_Msk, + ETH_DMAC0RXCR_RXPBL_Pos, ETH_PBL) | + whal_SetBits(ETH_DMAC0RXCR_RBSZ_Msk, + ETH_DMAC0RXCR_RBSZ_Pos, cfg->rxBufSize)); /* Set up TX descriptor ring */ for (size_t i = 0; i < cfg->txDescCount; i++) { @@ -253,37 +253,37 @@ whal_Error whal_Stm32n6_Eth_Init(whal_Eth *ethDev) } /* Program descriptor ring addresses and lengths */ - whal_Reg_Write(base, ETH_DMAC0TXDLAR_REG, (uintptr_t)cfg->txDescs); - whal_Reg_Write(base, ETH_DMAC0RXDLAR_REG, (uintptr_t)cfg->rxDescs); - whal_Reg_Write(base, ETH_DMAC0TXRLR_REG, cfg->txDescCount - 1); - whal_Reg_Write(base, ETH_DMAC0RXRLR_REG, cfg->rxDescCount - 1); + whal_Reg32_Write(base, ETH_DMAC0TXDLAR_REG, (uintptr_t)cfg->txDescs); + whal_Reg32_Write(base, ETH_DMAC0RXDLAR_REG, (uintptr_t)cfg->rxDescs); + whal_Reg32_Write(base, ETH_DMAC0TXRLR_REG, cfg->txDescCount - 1); + whal_Reg32_Write(base, ETH_DMAC0RXRLR_REG, cfg->rxDescCount - 1); /* MTL: store-and-forward for TX and RX, enable TX queue */ - whal_Reg_Update(base, ETH_MTLTXQOMR_REG, - ETH_MTLTXQOMR_TSF_Msk | ETH_MTLTXQOMR_TXQEN_Msk, - ETH_MTLTXQOMR_TSF_Msk | - whal_SetBits(ETH_MTLTXQOMR_TXQEN_Msk, - ETH_MTLTXQOMR_TXQEN_Pos, 2)); - whal_Reg_Update(base, ETH_MTLRXQOMR_REG, - ETH_MTLRXQOMR_RSF_Msk, ETH_MTLRXQOMR_RSF_Msk); + whal_Reg32_Update(base, ETH_MTLTXQOMR_REG, + ETH_MTLTXQOMR_TSF_Msk | ETH_MTLTXQOMR_TXQEN_Msk, + ETH_MTLTXQOMR_TSF_Msk | + whal_SetBits(ETH_MTLTXQOMR_TXQEN_Msk, + ETH_MTLTXQOMR_TXQEN_Pos, 2)); + whal_Reg32_Update(base, ETH_MTLRXQOMR_REG, + ETH_MTLRXQOMR_RSF_Msk, ETH_MTLRXQOMR_RSF_Msk); /* Enable MAC Rx queue 0 for generic traffic. Reset value disables * all Rx queues, so without this the MAC drops every received * packet before it ever reaches the MTL FIFO / DMA. */ - whal_Reg_Update(base, ETH_MACRXQC0R_REG, ETH_MACRXQC0R_RXQ0EN_Msk, - whal_SetBits(ETH_MACRXQC0R_RXQ0EN_Msk, - ETH_MACRXQC0R_RXQ0EN_Pos, - ETH_MACRXQC0R_RXQ0EN_GEN)); + whal_Reg32_Update(base, ETH_MACRXQC0R_REG, ETH_MACRXQC0R_RXQ0EN_Msk, + whal_SetBits(ETH_MACRXQC0R_RXQ0EN_Msk, + ETH_MACRXQC0R_RXQ0EN_Pos, + ETH_MACRXQC0R_RXQ0EN_GEN)); /* MAC address */ - whal_Reg_Write(base, ETH_MACA0LR_REG, - ((uint32_t)whal_Stm32n6_Eth_Dev.macAddr[3] << 24) | - ((uint32_t)whal_Stm32n6_Eth_Dev.macAddr[2] << 16) | - ((uint32_t)whal_Stm32n6_Eth_Dev.macAddr[1] << 8) | - ((uint32_t)whal_Stm32n6_Eth_Dev.macAddr[0])); - whal_Reg_Write(base, ETH_MACA0HR_REG, - ((uint32_t)whal_Stm32n6_Eth_Dev.macAddr[5] << 8) | - ((uint32_t)whal_Stm32n6_Eth_Dev.macAddr[4])); + whal_Reg32_Write(base, ETH_MACA0LR_REG, + ((uint32_t)whal_Stm32n6_Eth_Dev.macAddr[3] << 24) | + ((uint32_t)whal_Stm32n6_Eth_Dev.macAddr[2] << 16) | + ((uint32_t)whal_Stm32n6_Eth_Dev.macAddr[1] << 8) | + ((uint32_t)whal_Stm32n6_Eth_Dev.macAddr[0])); + whal_Reg32_Write(base, ETH_MACA0HR_REG, + ((uint32_t)whal_Stm32n6_Eth_Dev.macAddr[5] << 8) | + ((uint32_t)whal_Stm32n6_Eth_Dev.macAddr[4])); /* Reset ring tracking state */ eth_state.txHead = 0; @@ -300,8 +300,8 @@ whal_Error whal_Stm32n6_Eth_Deinit(whal_Eth *ethDev) { (void)ethDev; - whal_Reg_Update(whal_Stm32n6_Eth_Dev.base, ETH_DMAMR_REG, - ETH_DMAMR_SWR_Msk, ETH_DMAMR_SWR_Msk); + whal_Reg32_Update(whal_Stm32n6_Eth_Dev.base, ETH_DMAMR_REG, + ETH_DMAMR_SWR_Msk, ETH_DMAMR_SWR_Msk); return WHAL_SUCCESS; } @@ -311,7 +311,7 @@ whal_Error whal_Stm32n6_Eth_Start(whal_Eth *ethDev, uint8_t speed, { const whal_Stm32n6_Eth_Cfg *cfg = (const whal_Stm32n6_Eth_Cfg *)whal_Stm32n6_Eth_Dev.cfg; - size_t base = whal_Stm32n6_Eth_Dev.base; + uintptr_t base = whal_Stm32n6_Eth_Dev.base; (void)ethDev; if ((speed != WHAL_ETH_SPEED_10 && speed != WHAL_ETH_SPEED_100) || @@ -321,46 +321,46 @@ whal_Error whal_Stm32n6_Eth_Start(whal_Eth *ethDev, uint8_t speed, /* Configure MAC speed and duplex to match PHY. PS=1 selects the * MII/RMII data path; required because the EQOS MAC defaults to GMII * (PS=0) and this driver only supports 10/100 Mbps. */ - whal_Reg_Update(base, ETH_MACCR_REG, - ETH_MACCR_PS_Msk | ETH_MACCR_FES_Msk | ETH_MACCR_DM_Msk, - ETH_MACCR_PS_Msk | - ((speed == 100) ? ETH_MACCR_FES_Msk : 0) | - (duplex ? ETH_MACCR_DM_Msk : 0)); + whal_Reg32_Update(base, ETH_MACCR_REG, + ETH_MACCR_PS_Msk | ETH_MACCR_FES_Msk | ETH_MACCR_DM_Msk, + ETH_MACCR_PS_Msk | + ((speed == 100) ? ETH_MACCR_FES_Msk : 0) | + (duplex ? ETH_MACCR_DM_Msk : 0)); /* Enable MAC TX and RX */ - whal_Reg_Update(base, ETH_MACCR_REG, - ETH_MACCR_TE_Msk | ETH_MACCR_RE_Msk, - ETH_MACCR_TE_Msk | ETH_MACCR_RE_Msk); + whal_Reg32_Update(base, ETH_MACCR_REG, + ETH_MACCR_TE_Msk | ETH_MACCR_RE_Msk, + ETH_MACCR_TE_Msk | ETH_MACCR_RE_Msk); /* Start DMA TX */ - whal_Reg_Update(base, ETH_DMAC0TXCR_REG, - ETH_DMAC0TXCR_ST_Msk, ETH_DMAC0TXCR_ST_Msk); + whal_Reg32_Update(base, ETH_DMAC0TXCR_REG, + ETH_DMAC0TXCR_ST_Msk, ETH_DMAC0TXCR_ST_Msk); /* Start DMA RX */ - whal_Reg_Update(base, ETH_DMAC0RXCR_REG, - ETH_DMAC0RXCR_SR_Msk, ETH_DMAC0RXCR_SR_Msk); + whal_Reg32_Update(base, ETH_DMAC0RXCR_REG, + ETH_DMAC0RXCR_SR_Msk, ETH_DMAC0RXCR_SR_Msk); /* Kick RX DMA by writing tail pointer past last descriptor */ - whal_Reg_Write(base, ETH_DMAC0RXDTPR_REG, - (uintptr_t)&cfg->rxDescs[cfg->rxDescCount]); + whal_Reg32_Write(base, ETH_DMAC0RXDTPR_REG, + (uintptr_t)&cfg->rxDescs[cfg->rxDescCount]); return WHAL_SUCCESS; } whal_Error whal_Stm32n6_Eth_Stop(whal_Eth *ethDev) { - size_t base = whal_Stm32n6_Eth_Dev.base; + uintptr_t base = whal_Stm32n6_Eth_Dev.base; (void)ethDev; /* Stop DMA TX */ - whal_Reg_Update(base, ETH_DMAC0TXCR_REG, ETH_DMAC0TXCR_ST_Msk, 0); + whal_Reg32_Update(base, ETH_DMAC0TXCR_REG, ETH_DMAC0TXCR_ST_Msk, 0); /* Stop DMA RX */ - whal_Reg_Update(base, ETH_DMAC0RXCR_REG, ETH_DMAC0RXCR_SR_Msk, 0); + whal_Reg32_Update(base, ETH_DMAC0RXCR_REG, ETH_DMAC0RXCR_SR_Msk, 0); /* Disable MAC TX and RX */ - whal_Reg_Update(base, ETH_MACCR_REG, - ETH_MACCR_TE_Msk | ETH_MACCR_RE_Msk, 0); + whal_Reg32_Update(base, ETH_MACCR_REG, + ETH_MACCR_TE_Msk | ETH_MACCR_RE_Msk, 0); return WHAL_SUCCESS; } @@ -371,7 +371,7 @@ whal_Error whal_Stm32n6_Eth_Send(whal_Eth *ethDev, const void *frame, const uint8_t *frameBuf = (const uint8_t *)frame; const whal_Stm32n6_Eth_Cfg *cfg = (const whal_Stm32n6_Eth_Cfg *)whal_Stm32n6_Eth_Dev.cfg; - size_t base = whal_Stm32n6_Eth_Dev.base; + uintptr_t base = whal_Stm32n6_Eth_Dev.base; whal_Stm32n6_Eth_TxDesc *desc; size_t idx; (void)ethDev; @@ -408,8 +408,8 @@ whal_Error whal_Stm32n6_Eth_Send(whal_Eth *ethDev, const void *frame, __asm__ volatile ("dsb sy" ::: "memory"); /* Kick DMA */ - whal_Reg_Write(base, ETH_DMAC0TXDTPR_REG, - (uintptr_t)&cfg->txDescs[cfg->txDescCount]); + whal_Reg32_Write(base, ETH_DMAC0TXDTPR_REG, + (uintptr_t)&cfg->txDescs[cfg->txDescCount]); return WHAL_SUCCESS; } @@ -420,7 +420,7 @@ whal_Error whal_Stm32n6_Eth_Recv(whal_Eth *ethDev, void *frame, uint8_t *frameBuf = (uint8_t *)frame; const whal_Stm32n6_Eth_Cfg *cfg = (const whal_Stm32n6_Eth_Cfg *)whal_Stm32n6_Eth_Dev.cfg; - size_t base = whal_Stm32n6_Eth_Dev.base; + uintptr_t base = whal_Stm32n6_Eth_Dev.base; whal_Stm32n6_Eth_RxDesc *desc; size_t idx; uint32_t rdes3; @@ -448,8 +448,8 @@ whal_Error whal_Stm32n6_Eth_Recv(whal_Eth *ethDev, void *frame, desc->des[3] = RDES3_OWN | RDES3_IOC | RDES3_BUF1V; eth_state.rxHead = (idx + 1) % cfg->rxDescCount; __asm__ volatile ("dsb sy" ::: "memory"); - whal_Reg_Write(base, ETH_DMAC0RXDTPR_REG, - (uintptr_t)&cfg->rxDescs[cfg->rxDescCount]); + whal_Reg32_Write(base, ETH_DMAC0RXDTPR_REG, + (uintptr_t)&cfg->rxDescs[cfg->rxDescCount]); return WHAL_EHARDWARE; } @@ -479,8 +479,8 @@ whal_Error whal_Stm32n6_Eth_Recv(whal_Eth *ethDev, void *frame, __asm__ volatile ("dsb sy" ::: "memory"); /* Update RX tail pointer */ - whal_Reg_Write(base, ETH_DMAC0RXDTPR_REG, - (uintptr_t)&cfg->rxDescs[cfg->rxDescCount]); + whal_Reg32_Write(base, ETH_DMAC0RXDTPR_REG, + (uintptr_t)&cfg->rxDescs[cfg->rxDescCount]); return WHAL_SUCCESS; } @@ -490,7 +490,7 @@ whal_Error whal_Stm32n6_Eth_MdioRead(whal_Eth *ethDev, uint8_t phyAddr, { const whal_Stm32n6_Eth_Cfg *cfg = (const whal_Stm32n6_Eth_Cfg *)whal_Stm32n6_Eth_Dev.cfg; - size_t base = whal_Stm32n6_Eth_Dev.base; + uintptr_t base = whal_Stm32n6_Eth_Dev.base; whal_Error err; (void)ethDev; @@ -501,22 +501,22 @@ whal_Error whal_Stm32n6_Eth_MdioRead(whal_Eth *ethDev, uint8_t phyAddr, if (err) return err; - whal_Reg_Write(base, ETH_MACMDIOAR_REG, - whal_SetBits(ETH_MACMDIOAR_PA_Msk, ETH_MACMDIOAR_PA_Pos, - phyAddr) | - whal_SetBits(ETH_MACMDIOAR_RDA_Msk, ETH_MACMDIOAR_RDA_Pos, - reg) | - whal_SetBits(ETH_MACMDIOAR_CR_Msk, ETH_MACMDIOAR_CR_Pos, - cfg->mdioCr) | - whal_SetBits(ETH_MACMDIOAR_GOC_Msk, ETH_MACMDIOAR_GOC_Pos, - ETH_MDIO_GOC_READ) | - ETH_MACMDIOAR_MB_Msk); + whal_Reg32_Write(base, ETH_MACMDIOAR_REG, + whal_SetBits(ETH_MACMDIOAR_PA_Msk, ETH_MACMDIOAR_PA_Pos, + phyAddr) | + whal_SetBits(ETH_MACMDIOAR_RDA_Msk, ETH_MACMDIOAR_RDA_Pos, + reg) | + whal_SetBits(ETH_MACMDIOAR_CR_Msk, ETH_MACMDIOAR_CR_Pos, + cfg->mdioCr) | + whal_SetBits(ETH_MACMDIOAR_GOC_Msk, ETH_MACMDIOAR_GOC_Pos, + ETH_MDIO_GOC_READ) | + ETH_MACMDIOAR_MB_Msk); err = MdioPoll(base, cfg->timeout); if (err) return err; - *val = (uint16_t)(whal_Reg_Read(base, ETH_MACMDIODR_REG) & + *val = (uint16_t)(whal_Reg32_Read(base, ETH_MACMDIODR_REG) & ETH_MACMDIODR_MD_Msk); return WHAL_SUCCESS; @@ -527,7 +527,7 @@ whal_Error whal_Stm32n6_Eth_MdioWrite(whal_Eth *ethDev, uint8_t phyAddr, { const whal_Stm32n6_Eth_Cfg *cfg = (const whal_Stm32n6_Eth_Cfg *)whal_Stm32n6_Eth_Dev.cfg; - size_t base = whal_Stm32n6_Eth_Dev.base; + uintptr_t base = whal_Stm32n6_Eth_Dev.base; whal_Error err; (void)ethDev; @@ -535,18 +535,18 @@ whal_Error whal_Stm32n6_Eth_MdioWrite(whal_Eth *ethDev, uint8_t phyAddr, if (err) return err; - whal_Reg_Write(base, ETH_MACMDIODR_REG, val); + whal_Reg32_Write(base, ETH_MACMDIODR_REG, val); - whal_Reg_Write(base, ETH_MACMDIOAR_REG, - whal_SetBits(ETH_MACMDIOAR_PA_Msk, ETH_MACMDIOAR_PA_Pos, - phyAddr) | - whal_SetBits(ETH_MACMDIOAR_RDA_Msk, ETH_MACMDIOAR_RDA_Pos, - reg) | - whal_SetBits(ETH_MACMDIOAR_CR_Msk, ETH_MACMDIOAR_CR_Pos, - cfg->mdioCr) | - whal_SetBits(ETH_MACMDIOAR_GOC_Msk, ETH_MACMDIOAR_GOC_Pos, - ETH_MDIO_GOC_WRITE) | - ETH_MACMDIOAR_MB_Msk); + whal_Reg32_Write(base, ETH_MACMDIOAR_REG, + whal_SetBits(ETH_MACMDIOAR_PA_Msk, ETH_MACMDIOAR_PA_Pos, + phyAddr) | + whal_SetBits(ETH_MACMDIOAR_RDA_Msk, ETH_MACMDIOAR_RDA_Pos, + reg) | + whal_SetBits(ETH_MACMDIOAR_CR_Msk, ETH_MACMDIOAR_CR_Pos, + cfg->mdioCr) | + whal_SetBits(ETH_MACMDIOAR_GOC_Msk, ETH_MACMDIOAR_GOC_Pos, + ETH_MDIO_GOC_WRITE) | + ETH_MACMDIOAR_MB_Msk); err = MdioPoll(base, cfg->timeout); if (err) @@ -563,9 +563,9 @@ whal_Error whal_Stm32n6_Eth_Ext_EnableLoopback(whal_Eth *ethDev, { (void)ethDev; - whal_Reg_Update(whal_Stm32n6_Eth_Dev.base, ETH_MACCR_REG, ETH_MACCR_LM_Msk, - whal_SetBits(ETH_MACCR_LM_Msk, ETH_MACCR_LM_Pos, - enable ? 1 : 0)); + whal_Reg32_Update(whal_Stm32n6_Eth_Dev.base, ETH_MACCR_REG, ETH_MACCR_LM_Msk, + whal_SetBits(ETH_MACCR_LM_Msk, ETH_MACCR_LM_Pos, + enable ? 1 : 0)); return WHAL_SUCCESS; } diff --git a/src/flash/pic32cz_flash.c b/src/flash/pic32cz_flash.c index 12665be5..28d3b38b 100644 --- a/src/flash/pic32cz_flash.c +++ b/src/flash/pic32cz_flash.c @@ -129,34 +129,34 @@ const whal_Flash whal_Pic32cz_Flash_Dev = WHAL_CFG_PIC32CZ_FLASH_DEV; #define whal_Pic32cz_Flash_Erase whal_Flash_Erase #endif /* WHAL_CFG_PIC32CZ_FLASH_DIRECT_API_MAPPING */ -static whal_Error whal_Pic32cz_Flash_MutexLock(size_t base, +static whal_Error whal_Pic32cz_Flash_MutexLock(uintptr_t base, whal_Timeout *timeout) { WHAL_TIMEOUT_START(timeout); - while (whal_Reg_Read(base, FCW_MUTEX_REG) & FCW_MUTEX_LOCK_Msk) { + while (whal_Reg32_Read(base, FCW_MUTEX_REG) & FCW_MUTEX_LOCK_Msk) { if (WHAL_TIMEOUT_EXPIRED(timeout)) return WHAL_ETIMEOUT; } - whal_Reg_Update(base, FCW_MUTEX_REG, FCW_MUTEX_LOCK_Msk | FCW_MUTEX_OWNER_Msk, - whal_SetBits(FCW_MUTEX_LOCK_Msk, FCW_MUTEX_LOCK_Pos, 1) | - whal_SetBits(FCW_MUTEX_OWNER_Msk, FCW_MUTEX_OWNER_Pos, 1)); + whal_Reg32_Update(base, FCW_MUTEX_REG, FCW_MUTEX_LOCK_Msk | FCW_MUTEX_OWNER_Msk, + whal_SetBits(FCW_MUTEX_LOCK_Msk, FCW_MUTEX_LOCK_Pos, 1) | + whal_SetBits(FCW_MUTEX_OWNER_Msk, FCW_MUTEX_OWNER_Pos, 1)); return WHAL_SUCCESS; } -static void whal_Pic32cz_Flash_MutexUnlock(size_t base) +static void whal_Pic32cz_Flash_MutexUnlock(uintptr_t base) { - whal_Reg_Update(base, FCW_MUTEX_REG, FCW_MUTEX_LOCK_Msk | FCW_MUTEX_OWNER_Msk, - whal_SetBits(FCW_MUTEX_LOCK_Msk, FCW_MUTEX_LOCK_Pos, 0) | - whal_SetBits(FCW_MUTEX_OWNER_Msk, FCW_MUTEX_OWNER_Pos, 1)); + whal_Reg32_Update(base, FCW_MUTEX_REG, FCW_MUTEX_LOCK_Msk | FCW_MUTEX_OWNER_Msk, + whal_SetBits(FCW_MUTEX_LOCK_Msk, FCW_MUTEX_LOCK_Pos, 0) | + whal_SetBits(FCW_MUTEX_OWNER_Msk, FCW_MUTEX_OWNER_Pos, 1)); } -static whal_Error whal_Pic32cz_Flash_WaitBusy(size_t base, +static whal_Error whal_Pic32cz_Flash_WaitBusy(uintptr_t base, whal_Timeout *timeout) { WHAL_TIMEOUT_START(timeout); - while (whal_Reg_Read(base, FCW_STATUS_REG) & FCW_STATUS_BUSY_Msk) { + while (whal_Reg32_Read(base, FCW_STATUS_REG) & FCW_STATUS_BUSY_Msk) { if (WHAL_TIMEOUT_EXPIRED(timeout)) return WHAL_ETIMEOUT; } @@ -168,19 +168,19 @@ static whal_Error whal_Pic32cz_Flash_WaitBusy(size_t base, * Execute an FCW command: unlock, trigger, wait, and check for errors. * Caller must set up FCW_ADDR and FCW_DATA registers before calling. */ -static whal_Error whal_Pic32cz_Flash_ExecCmd(size_t base, size_t cmd, +static whal_Error whal_Pic32cz_Flash_ExecCmd(uintptr_t base, size_t cmd, whal_Timeout *timeout) { whal_Error err; - size_t errFlags; + uint32_t errFlags; /* Write unlock key */ - whal_Reg_Update(base, FCW_KEY_REG, 0xFFFFFFFF, FCW_UNLOCK_WRKEY); + whal_Reg32_Update(base, FCW_KEY_REG, 0xFFFFFFFF, FCW_UNLOCK_WRKEY); /* Trigger operation with pre-program enabled */ - whal_Reg_Update(base, FCW_CTRLA_REG, - FCW_CTRLA_NVMOP_Msk | FCW_CTRLA_PREPG_Msk, - whal_SetBits(FCW_CTRLA_NVMOP_Msk, FCW_CTRLA_NVMOP_Pos, cmd) | FCW_CTRLA_PREPG_Msk); + whal_Reg32_Update(base, FCW_CTRLA_REG, + FCW_CTRLA_NVMOP_Msk | FCW_CTRLA_PREPG_Msk, + whal_SetBits(FCW_CTRLA_NVMOP_Msk, FCW_CTRLA_NVMOP_Pos, cmd) | FCW_CTRLA_PREPG_Msk); /* Wait for completion */ err = whal_Pic32cz_Flash_WaitBusy(base, timeout); @@ -188,16 +188,16 @@ static whal_Error whal_Pic32cz_Flash_ExecCmd(size_t base, size_t cmd, return err; /* Check for errors */ - whal_Reg_Get(base, FCW_INTFLAG_REG, FCW_INTFLAG_ALL_ERR, 0, &errFlags); + whal_Reg32_Get(base, FCW_INTFLAG_REG, FCW_INTFLAG_ALL_ERR, 0, &errFlags); /* Clear DONE flag */ - whal_Reg_Update(base, FCW_INTFLAG_REG, FCW_INTFLAG_DONE_Msk, - FCW_INTFLAG_DONE_Msk); + whal_Reg32_Update(base, FCW_INTFLAG_REG, FCW_INTFLAG_DONE_Msk, + FCW_INTFLAG_DONE_Msk); if (errFlags) { /* Clear error flags */ - whal_Reg_Update(base, FCW_INTFLAG_REG, FCW_INTFLAG_ALL_ERR, - FCW_INTFLAG_ALL_ERR); + whal_Reg32_Update(base, FCW_INTFLAG_REG, FCW_INTFLAG_ALL_ERR, + FCW_INTFLAG_ALL_ERR); return WHAL_EHARDWARE; } @@ -206,34 +206,34 @@ static whal_Error whal_Pic32cz_Flash_ExecCmd(size_t base, size_t cmd, whal_Error whal_Pic32cz_Flash_Init(whal_Flash *flashDev) { - size_t base = whal_Pic32cz_Flash_Dev.base; + uintptr_t base = whal_Pic32cz_Flash_Dev.base; (void)flashDev; whal_Pic32cz_Flash_MutexUnlock(base); - whal_Reg_Update(base, FCW_KEY_REG, 0xFFFFFFFF, 0); - whal_Reg_Update(base, FCW_ADDR_REG, 0xFFFFFFFF, 0); - whal_Reg_Update(base, FCW_SRCADDR_REG, 0xFFFFFFFF, 0); + whal_Reg32_Update(base, FCW_KEY_REG, 0xFFFFFFFF, 0); + whal_Reg32_Update(base, FCW_ADDR_REG, 0xFFFFFFFF, 0); + whal_Reg32_Update(base, FCW_SRCADDR_REG, 0xFFFFFFFF, 0); /* Clear all pending interrupt flags */ - whal_Reg_Update(base, FCW_INTFLAG_REG, FCW_INTFLAG_ALL, - FCW_INTFLAG_ALL); + whal_Reg32_Update(base, FCW_INTFLAG_REG, FCW_INTFLAG_ALL, + FCW_INTFLAG_ALL); return WHAL_SUCCESS; } whal_Error whal_Pic32cz_Flash_Deinit(whal_Flash *flashDev) { - size_t base = whal_Pic32cz_Flash_Dev.base; + uintptr_t base = whal_Pic32cz_Flash_Dev.base; (void)flashDev; whal_Pic32cz_Flash_MutexUnlock(base); - whal_Reg_Update(base, FCW_KEY_REG, 0xFFFFFFFF, 0); - whal_Reg_Update(base, FCW_ADDR_REG, 0xFFFFFFFF, 0); - whal_Reg_Update(base, FCW_SRCADDR_REG, 0xFFFFFFFF, 0); + whal_Reg32_Update(base, FCW_KEY_REG, 0xFFFFFFFF, 0); + whal_Reg32_Update(base, FCW_ADDR_REG, 0xFFFFFFFF, 0); + whal_Reg32_Update(base, FCW_SRCADDR_REG, 0xFFFFFFFF, 0); /* Clear all pending interrupt flags */ - whal_Reg_Update(base, FCW_INTFLAG_REG, FCW_INTFLAG_ALL, - FCW_INTFLAG_ALL); + whal_Reg32_Update(base, FCW_INTFLAG_REG, FCW_INTFLAG_ALL, + FCW_INTFLAG_ALL); return WHAL_SUCCESS; } @@ -266,7 +266,7 @@ whal_Error whal_Pic32cz_Flash_Read(whal_Flash *flashDev, size_t addr, void *data { const whal_Pic32cz_Flash_Cfg *cfg = (const whal_Pic32cz_Flash_Cfg *)whal_Pic32cz_Flash_Dev.cfg; - size_t base = whal_Pic32cz_Flash_Dev.base; + uintptr_t base = whal_Pic32cz_Flash_Dev.base; uint8_t *dataBuf = (uint8_t *)data; uint8_t *flashAddr = (uint8_t *)addr; whal_Error err; @@ -300,7 +300,7 @@ whal_Error whal_Pic32cz_Flash_Write(whal_Flash *flashDev, size_t addr, const voi { const whal_Pic32cz_Flash_Cfg *cfg = (const whal_Pic32cz_Flash_Cfg *)whal_Pic32cz_Flash_Dev.cfg; - size_t base = whal_Pic32cz_Flash_Dev.base; + uintptr_t base = whal_Pic32cz_Flash_Dev.base; const uint8_t *dataBuf = (const uint8_t *)data; whal_Error err; size_t offset = 0; @@ -337,10 +337,10 @@ whal_Error whal_Pic32cz_Flash_Write(whal_Flash *flashDev, size_t addr, const voi /* Quad double word write (32 bytes) */ size_t j; for (j = 0; j < 8; j++) { - whal_Reg_Update(base, FCW_DATA_REG(j), 0xFFFFFFFF, - whal_LoadLe32(dataBuf + offset + j * 4)); + whal_Reg32_Update(base, FCW_DATA_REG(j), 0xFFFFFFFF, + whal_LoadLe32(dataBuf + offset + j * 4)); } - whal_Reg_Update(base, FCW_ADDR_REG, 0xFFFFFFFF, curAddr); + whal_Reg32_Update(base, FCW_ADDR_REG, 0xFFFFFFFF, curAddr); err = whal_Pic32cz_Flash_ExecCmd(base, FCW_CTRLA_NVMOP_QUAD_DWORD, @@ -352,11 +352,11 @@ whal_Error whal_Pic32cz_Flash_Write(whal_Flash *flashDev, size_t addr, const voi offset += FCW_QDWORD_SIZE; } else { /* Single double word write (8 bytes) */ - whal_Reg_Update(base, FCW_DATA_REG(0), 0xFFFFFFFF, - whal_LoadLe32(dataBuf + offset)); - whal_Reg_Update(base, FCW_DATA_REG(1), 0xFFFFFFFF, - whal_LoadLe32(dataBuf + offset + 4)); - whal_Reg_Update(base, FCW_ADDR_REG, 0xFFFFFFFF, curAddr); + whal_Reg32_Update(base, FCW_DATA_REG(0), 0xFFFFFFFF, + whal_LoadLe32(dataBuf + offset)); + whal_Reg32_Update(base, FCW_DATA_REG(1), 0xFFFFFFFF, + whal_LoadLe32(dataBuf + offset + 4)); + whal_Reg32_Update(base, FCW_ADDR_REG, 0xFFFFFFFF, curAddr); err = whal_Pic32cz_Flash_ExecCmd(base, FCW_CTRLA_NVMOP_SINGLE_DWORD, @@ -379,7 +379,7 @@ whal_Error whal_Pic32cz_Flash_Erase(whal_Flash *flashDev, size_t addr, size_t da { const whal_Pic32cz_Flash_Cfg *cfg = (const whal_Pic32cz_Flash_Cfg *)whal_Pic32cz_Flash_Dev.cfg; - size_t base = whal_Pic32cz_Flash_Dev.base; + uintptr_t base = whal_Pic32cz_Flash_Dev.base; whal_Error err; size_t pageAddr; size_t endAddr; @@ -408,7 +408,7 @@ whal_Error whal_Pic32cz_Flash_Erase(whal_Flash *flashDev, size_t addr, size_t da return err; } - whal_Reg_Update(base, FCW_ADDR_REG, 0xFFFFFFFF, pageAddr); + whal_Reg32_Update(base, FCW_ADDR_REG, 0xFFFFFFFF, pageAddr); err = whal_Pic32cz_Flash_ExecCmd(base, FCW_CTRLA_NVMOP_PAGE_ERASE, cfg->timeout); diff --git a/src/flash/stm32c0_flash.c b/src/flash/stm32c0_flash.c index a83db467..8189d345 100644 --- a/src/flash/stm32c0_flash.c +++ b/src/flash/stm32c0_flash.c @@ -137,21 +137,21 @@ whal_Error whal_Stm32c0_Flash_Deinit(whal_Flash *flashDev) whal_Error whal_Stm32c0_Flash_Lock(whal_Flash *flashDev, size_t addr, size_t len) { - size_t base = whal_Stm32c0_Flash_Dev.base; + uintptr_t base = whal_Stm32c0_Flash_Dev.base; (void)flashDev; (void)addr; (void)len; /* Setting LOCK bit prevents further flash modifications until next unlock */ - whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_LOCK_Msk, - whal_SetBits(FLASH_CR_LOCK_Msk, FLASH_CR_LOCK_Pos, 1)); + whal_Reg32_Update(base, FLASH_CR_REG, FLASH_CR_LOCK_Msk, + whal_SetBits(FLASH_CR_LOCK_Msk, FLASH_CR_LOCK_Pos, 1)); return WHAL_SUCCESS; } whal_Error whal_Stm32c0_Flash_Unlock(whal_Flash *flashDev, size_t addr, size_t len) { - size_t base = whal_Stm32c0_Flash_Dev.base; + uintptr_t base = whal_Stm32c0_Flash_Dev.base; (void)flashDev; (void)addr; (void)len; @@ -160,12 +160,12 @@ whal_Error whal_Stm32c0_Flash_Unlock(whal_Flash *flashDev, size_t addr, size_t l * Unlock sequence: write KEY1 then KEY2 to KEYR register. * Incorrect sequence or order will trigger a bus error. */ - if (whal_Reg_Read(base, FLASH_CR_REG) & FLASH_CR_LOCK_Msk) { - whal_Reg_Update(base, FLASH_KEYR_REG, FLASH_KEYR_KEY_Msk, 0x45670123); - whal_Reg_Update(base, FLASH_KEYR_REG, FLASH_KEYR_KEY_Msk, 0xCDEF89AB); + if (whal_Reg32_Read(base, FLASH_CR_REG) & FLASH_CR_LOCK_Msk) { + whal_Reg32_Update(base, FLASH_KEYR_REG, FLASH_KEYR_KEY_Msk, 0x45670123); + whal_Reg32_Update(base, FLASH_KEYR_REG, FLASH_KEYR_KEY_Msk, 0xCDEF89AB); } - if (whal_Reg_Read(base, FLASH_CR_REG) & FLASH_CR_LOCK_Msk) + if (whal_Reg32_Read(base, FLASH_CR_REG) & FLASH_CR_LOCK_Msk) return WHAL_EHARDWARE; return WHAL_SUCCESS; @@ -208,8 +208,8 @@ static whal_Error whal_Stm32c0_Flash_WriteOrErase(whal_Flash *flashDev, size_t a { const whal_Stm32c0_Flash_Cfg *cfg = (const whal_Stm32c0_Flash_Cfg *)whal_Stm32c0_Flash_Dev.cfg; - size_t base = whal_Stm32c0_Flash_Dev.base; - size_t bsy; + uintptr_t base = whal_Stm32c0_Flash_Dev.base; + uint32_t bsy; (void)flashDev; if (addr < cfg->startAddr || dataSz > cfg->size || @@ -224,23 +224,23 @@ static whal_Error whal_Stm32c0_Flash_WriteOrErase(whal_Flash *flashDev, size_t a return WHAL_SUCCESS; /* Check if flash is busy */ - whal_Reg_Get(base, FLASH_SR_REG, FLASH_SR_BSY_Msk, FLASH_SR_BSY_Pos, &bsy); + whal_Reg32_Get(base, FLASH_SR_REG, FLASH_SR_BSY_Msk, FLASH_SR_BSY_Pos, &bsy); - if (bsy || (whal_Reg_Read(base, FLASH_SR_REG) & FLASH_SR_CFGBSY_Msk)) { + if (bsy || (whal_Reg32_Read(base, FLASH_SR_REG) & FLASH_SR_CFGBSY_Msk)) { return WHAL_ENOTREADY; } /* Drop PG/PER left set by an earlier operation that timed out */ - whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_PG_Msk | FLASH_CR_PER_Msk, 0); + whal_Reg32_Update(base, FLASH_CR_REG, FLASH_CR_PG_Msk | FLASH_CR_PER_Msk, 0); /* Clear all error flags by writing 1 to each */ - whal_Reg_Update(base, FLASH_SR_REG, FLASH_SR_ALL_ERR, 0xffffffff); + whal_Reg32_Update(base, FLASH_SR_REG, FLASH_SR_ALL_ERR, 0xffffffff); whal_Error err = WHAL_SUCCESS; if (write) { /* Enable flash programming mode */ - whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_PG_Msk, 1); + whal_Reg32_Update(base, FLASH_CR_REG, FLASH_CR_PG_Msk, 1); /* Program data in 64-bit (8 byte) double-word chunks */ for (size_t i = 0; i < dataSz; i += 8) { @@ -251,14 +251,14 @@ static whal_Error whal_Stm32c0_Flash_WriteOrErase(whal_Flash *flashDev, size_t a flashAddr[1] = whal_LoadLe32(data + i + 4); /* Wait for programming to complete */ - err = whal_Reg_ReadPoll(base, FLASH_SR_REG, - FLASH_SR_CFGBSY_Msk, 0, cfg->timeout); + err = whal_Reg32_ReadPoll(base, FLASH_SR_REG, + FLASH_SR_CFGBSY_Msk, 0, cfg->timeout); if (err) goto cleanup; /* Check for errors */ - if (whal_Reg_Read(base, FLASH_SR_REG) & FLASH_SR_ALL_ERR) { - whal_Reg_Update(base, FLASH_SR_REG, FLASH_SR_ALL_ERR, FLASH_SR_ALL_ERR); + if (whal_Reg32_Read(base, FLASH_SR_REG) & FLASH_SR_ALL_ERR) { + whal_Reg32_Update(base, FLASH_SR_REG, FLASH_SR_ALL_ERR, FLASH_SR_ALL_ERR); err = WHAL_EHARDWARE; goto cleanup; } @@ -271,43 +271,43 @@ static whal_Error whal_Stm32c0_Flash_WriteOrErase(whal_Flash *flashDev, size_t a endPage = ((addr - cfg->startAddr) + dataSz - 1) >> 11; /* Enable page erase mode */ - whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_PER_Msk, - whal_SetBits(FLASH_CR_PER_Msk, FLASH_CR_PER_Pos, 1)); + whal_Reg32_Update(base, FLASH_CR_REG, FLASH_CR_PER_Msk, + whal_SetBits(FLASH_CR_PER_Msk, FLASH_CR_PER_Pos, 1)); /* Erase each page in the range */ for (size_t page = startPage; page <= endPage; ++page) { /* Select page number */ - whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_PNB_Msk, - whal_SetBits(FLASH_CR_PNB_Msk, FLASH_CR_PNB_Pos, page)); + whal_Reg32_Update(base, FLASH_CR_REG, FLASH_CR_PNB_Msk, + whal_SetBits(FLASH_CR_PNB_Msk, FLASH_CR_PNB_Pos, page)); /* Start erase operation */ - whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_STRT_Msk, - whal_SetBits(FLASH_CR_STRT_Msk, FLASH_CR_STRT_Pos, 1)); + whal_Reg32_Update(base, FLASH_CR_REG, FLASH_CR_STRT_Msk, + whal_SetBits(FLASH_CR_STRT_Msk, FLASH_CR_STRT_Pos, 1)); /* Wait for erase to complete */ - err = whal_Reg_ReadPoll(base, FLASH_SR_REG, - FLASH_SR_CFGBSY_Msk, 0, cfg->timeout); + err = whal_Reg32_ReadPoll(base, FLASH_SR_REG, + FLASH_SR_CFGBSY_Msk, 0, cfg->timeout); if (err) goto cleanup; /* Check for errors */ - if (whal_Reg_Read(base, FLASH_SR_REG) & FLASH_SR_ALL_ERR) { - whal_Reg_Update(base, FLASH_SR_REG, FLASH_SR_ALL_ERR, FLASH_SR_ALL_ERR); + if (whal_Reg32_Read(base, FLASH_SR_REG) & FLASH_SR_ALL_ERR) { + whal_Reg32_Update(base, FLASH_SR_REG, FLASH_SR_ALL_ERR, FLASH_SR_ALL_ERR); err = WHAL_EHARDWARE; goto cleanup; } } /* Disable page erase mode */ - whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_PER_Msk, - whal_SetBits(FLASH_CR_PER_Msk, FLASH_CR_PER_Pos, 0)); + whal_Reg32_Update(base, FLASH_CR_REG, FLASH_CR_PER_Msk, + whal_SetBits(FLASH_CR_PER_Msk, FLASH_CR_PER_Pos, 0)); } cleanup: /* FLASH_CR must not be written while CFGBSY is set */ - if (!(whal_Reg_Read(base, FLASH_SR_REG) & FLASH_SR_CFGBSY_Msk)) - whal_Reg_Update(base, FLASH_CR_REG, - FLASH_CR_PG_Msk | FLASH_CR_PER_Msk, 0); + if (!(whal_Reg32_Read(base, FLASH_SR_REG) & FLASH_SR_CFGBSY_Msk)) + whal_Reg32_Update(base, FLASH_CR_REG, + FLASH_CR_PG_Msk | FLASH_CR_PER_Msk, 0); return err; } @@ -326,10 +326,10 @@ whal_Error whal_Stm32c0_Flash_Erase(whal_Flash *flashDev, size_t addr, whal_Error whal_Stm32c0_Flash_Ext_SetLatency(whal_Flash *flashDev, enum whal_Stm32c0_Flash_Latency latency) { - size_t base = whal_Stm32c0_Flash_Dev.base; + uintptr_t base = whal_Stm32c0_Flash_Dev.base; (void)flashDev; - whal_Reg_Update(base, FLASH_ACR_REG, FLASH_ACR_LATENCY_Msk, latency); + whal_Reg32_Update(base, FLASH_ACR_REG, FLASH_ACR_LATENCY_Msk, latency); return WHAL_SUCCESS; } diff --git a/src/flash/stm32f0_flash.c b/src/flash/stm32f0_flash.c index 46e0f055..c6658b52 100644 --- a/src/flash/stm32f0_flash.c +++ b/src/flash/stm32f0_flash.c @@ -85,32 +85,32 @@ whal_Error whal_Stm32f0_Flash_Deinit(whal_Flash *flashDev) whal_Error whal_Stm32f0_Flash_Lock(whal_Flash *flashDev, size_t addr, size_t len) { - size_t base = whal_Stm32f0_Flash_Dev.base; + uintptr_t base = whal_Stm32f0_Flash_Dev.base; (void)flashDev; (void)addr; (void)len; - whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_LOCK_Msk, - whal_SetBits(FLASH_CR_LOCK_Msk, FLASH_CR_LOCK_Pos, 1)); + whal_Reg32_Update(base, FLASH_CR_REG, FLASH_CR_LOCK_Msk, + whal_SetBits(FLASH_CR_LOCK_Msk, FLASH_CR_LOCK_Pos, 1)); return WHAL_SUCCESS; } whal_Error whal_Stm32f0_Flash_Unlock(whal_Flash *flashDev, size_t addr, size_t len) { - size_t base = whal_Stm32f0_Flash_Dev.base; + uintptr_t base = whal_Stm32f0_Flash_Dev.base; (void)flashDev; (void)addr; (void)len; - if (whal_Reg_Read(base, FLASH_CR_REG) & FLASH_CR_LOCK_Msk) { - whal_Reg_Update(base, FLASH_KEYR_REG, - FLASH_KEYR_KEY_Msk, 0x45670123); - whal_Reg_Update(base, FLASH_KEYR_REG, - FLASH_KEYR_KEY_Msk, 0xCDEF89AB); + if (whal_Reg32_Read(base, FLASH_CR_REG) & FLASH_CR_LOCK_Msk) { + whal_Reg32_Update(base, FLASH_KEYR_REG, + FLASH_KEYR_KEY_Msk, 0x45670123); + whal_Reg32_Update(base, FLASH_KEYR_REG, + FLASH_KEYR_KEY_Msk, 0xCDEF89AB); } - if (whal_Reg_Read(base, FLASH_CR_REG) & FLASH_CR_LOCK_Msk) + if (whal_Reg32_Read(base, FLASH_CR_REG) & FLASH_CR_LOCK_Msk) return WHAL_EHARDWARE; return WHAL_SUCCESS; @@ -148,8 +148,8 @@ static whal_Error whal_Stm32f0_Flash_WriteOrErase(whal_Flash *flashDev, { const whal_Stm32f0_Flash_Cfg *cfg = (const whal_Stm32f0_Flash_Cfg *)whal_Stm32f0_Flash_Dev.cfg; - size_t base = whal_Stm32f0_Flash_Dev.base; - size_t bsy; + uintptr_t base = whal_Stm32f0_Flash_Dev.base; + uint32_t bsy; (void)flashDev; if (addr < cfg->startAddr || dataSz > cfg->size || @@ -166,20 +166,20 @@ static whal_Error whal_Stm32f0_Flash_WriteOrErase(whal_Flash *flashDev, if (!write && cfg->pageSz == 0) return WHAL_EINVAL; - whal_Reg_Get(base, FLASH_SR_REG, - FLASH_SR_BSY_Msk, FLASH_SR_BSY_Pos, &bsy); + whal_Reg32_Get(base, FLASH_SR_REG, + FLASH_SR_BSY_Msk, FLASH_SR_BSY_Pos, &bsy); if (bsy) return WHAL_ENOTREADY; /* Clear error flags */ - whal_Reg_Update(base, FLASH_SR_REG, FLASH_SR_ALL_ERR, 0xffffffff); + whal_Reg32_Update(base, FLASH_SR_REG, FLASH_SR_ALL_ERR, 0xffffffff); whal_Error err = WHAL_SUCCESS; if (write) { /* Enable programming */ - whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_PG_Msk, - whal_SetBits(FLASH_CR_PG_Msk, FLASH_CR_PG_Pos, 1)); + whal_Reg32_Update(base, FLASH_CR_REG, FLASH_CR_PG_Msk, + whal_SetBits(FLASH_CR_PG_Msk, FLASH_CR_PG_Pos, 1)); /* Program in 16-bit half-words */ for (size_t i = 0; i < dataSz; i += 2) { @@ -188,14 +188,14 @@ static whal_Error whal_Stm32f0_Flash_WriteOrErase(whal_Flash *flashDev, *flashAddr = hw; - err = whal_Reg_ReadPoll(base, FLASH_SR_REG, - FLASH_SR_BSY_Msk, 0, cfg->timeout); + err = whal_Reg32_ReadPoll(base, FLASH_SR_REG, + FLASH_SR_BSY_Msk, 0, cfg->timeout); if (err) goto cleanup; /* Check for errors */ - if (whal_Reg_Read(base, FLASH_SR_REG) & FLASH_SR_ALL_ERR) { - whal_Reg_Update(base, FLASH_SR_REG, FLASH_SR_ALL_ERR, FLASH_SR_ALL_ERR); + if (whal_Reg32_Read(base, FLASH_SR_REG) & FLASH_SR_ALL_ERR) { + whal_Reg32_Update(base, FLASH_SR_REG, FLASH_SR_ALL_ERR, FLASH_SR_ALL_ERR); err = WHAL_EHARDWARE; goto cleanup; } @@ -207,38 +207,38 @@ static whal_Error whal_Stm32f0_Flash_WriteOrErase(whal_Flash *flashDev, for (size_t page = startPage; page <= endPage; ++page) { /* Enable page erase */ - whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_PER_Msk, - whal_SetBits(FLASH_CR_PER_Msk, FLASH_CR_PER_Pos, 1)); + whal_Reg32_Update(base, FLASH_CR_REG, FLASH_CR_PER_Msk, + whal_SetBits(FLASH_CR_PER_Msk, FLASH_CR_PER_Pos, 1)); /* Write page start address to AR */ - whal_Reg_Write(base, FLASH_AR_REG, - cfg->startAddr + page * cfg->pageSz); + whal_Reg32_Write(base, FLASH_AR_REG, + cfg->startAddr + page * cfg->pageSz); /* Start erase */ - whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_STRT_Msk, - whal_SetBits(FLASH_CR_STRT_Msk, FLASH_CR_STRT_Pos, 1)); + whal_Reg32_Update(base, FLASH_CR_REG, FLASH_CR_STRT_Msk, + whal_SetBits(FLASH_CR_STRT_Msk, FLASH_CR_STRT_Pos, 1)); - err = whal_Reg_ReadPoll(base, FLASH_SR_REG, - FLASH_SR_BSY_Msk, 0, cfg->timeout); + err = whal_Reg32_ReadPoll(base, FLASH_SR_REG, + FLASH_SR_BSY_Msk, 0, cfg->timeout); if (err) goto cleanup; /* Check for errors */ - if (whal_Reg_Read(base, FLASH_SR_REG) & FLASH_SR_ALL_ERR) { - whal_Reg_Update(base, FLASH_SR_REG, FLASH_SR_ALL_ERR, FLASH_SR_ALL_ERR); + if (whal_Reg32_Read(base, FLASH_SR_REG) & FLASH_SR_ALL_ERR) { + whal_Reg32_Update(base, FLASH_SR_REG, FLASH_SR_ALL_ERR, FLASH_SR_ALL_ERR); err = WHAL_EHARDWARE; goto cleanup; } } /* Disable page erase */ - whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_PER_Msk, - whal_SetBits(FLASH_CR_PER_Msk, FLASH_CR_PER_Pos, 0)); + whal_Reg32_Update(base, FLASH_CR_REG, FLASH_CR_PER_Msk, + whal_SetBits(FLASH_CR_PER_Msk, FLASH_CR_PER_Pos, 0)); } cleanup: - whal_Reg_Update(base, FLASH_CR_REG, - FLASH_CR_PG_Msk | FLASH_CR_PER_Msk, 0); + whal_Reg32_Update(base, FLASH_CR_REG, + FLASH_CR_PG_Msk | FLASH_CR_PER_Msk, 0); return err; } @@ -259,11 +259,11 @@ whal_Error whal_Stm32f0_Flash_Erase(whal_Flash *flashDev, size_t addr, whal_Error whal_Stm32f0_Flash_Ext_SetLatency(whal_Flash *flashDev, enum whal_Stm32f0_Flash_Latency latency) { - size_t base = whal_Stm32f0_Flash_Dev.base; + uintptr_t base = whal_Stm32f0_Flash_Dev.base; (void)flashDev; - whal_Reg_Update(base, FLASH_ACR_REG, - FLASH_ACR_LATENCY_Msk, latency); + whal_Reg32_Update(base, FLASH_ACR_REG, + FLASH_ACR_LATENCY_Msk, latency); return WHAL_SUCCESS; } diff --git a/src/flash/stm32f4_flash.c b/src/flash/stm32f4_flash.c index e27071fe..7f1250ee 100644 --- a/src/flash/stm32f4_flash.c +++ b/src/flash/stm32f4_flash.c @@ -129,30 +129,30 @@ whal_Error whal_Stm32f4_Flash_Deinit(whal_Flash *flashDev) whal_Error whal_Stm32f4_Flash_Lock(whal_Flash *flashDev, size_t addr, size_t len) { - size_t base = whal_Stm32f4_Flash_Dev.base; + uintptr_t base = whal_Stm32f4_Flash_Dev.base; (void)flashDev; (void)addr; (void)len; - whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_LOCK_Msk, - whal_SetBits(FLASH_CR_LOCK_Msk, FLASH_CR_LOCK_Pos, 1)); + whal_Reg32_Update(base, FLASH_CR_REG, FLASH_CR_LOCK_Msk, + whal_SetBits(FLASH_CR_LOCK_Msk, FLASH_CR_LOCK_Pos, 1)); return WHAL_SUCCESS; } whal_Error whal_Stm32f4_Flash_Unlock(whal_Flash *flashDev, size_t addr, size_t len) { - size_t base = whal_Stm32f4_Flash_Dev.base; + uintptr_t base = whal_Stm32f4_Flash_Dev.base; (void)flashDev; (void)addr; (void)len; - if (whal_Reg_Read(base, FLASH_CR_REG) & FLASH_CR_LOCK_Msk) { - whal_Reg_Write(base, FLASH_KEYR_REG, FLASH_KEY1); - whal_Reg_Write(base, FLASH_KEYR_REG, FLASH_KEY2); + if (whal_Reg32_Read(base, FLASH_CR_REG) & FLASH_CR_LOCK_Msk) { + whal_Reg32_Write(base, FLASH_KEYR_REG, FLASH_KEY1); + whal_Reg32_Write(base, FLASH_KEYR_REG, FLASH_KEY2); } - if (whal_Reg_Read(base, FLASH_CR_REG) & FLASH_CR_LOCK_Msk) + if (whal_Reg32_Read(base, FLASH_CR_REG) & FLASH_CR_LOCK_Msk) return WHAL_EHARDWARE; return WHAL_SUCCESS; @@ -185,7 +185,7 @@ whal_Error whal_Stm32f4_Flash_Write(whal_Flash *flashDev, size_t addr, { const whal_Stm32f4_Flash_Cfg *cfg = (const whal_Stm32f4_Flash_Cfg *)whal_Stm32f4_Flash_Dev.cfg; - size_t base = whal_Stm32f4_Flash_Dev.base; + uintptr_t base = whal_Stm32f4_Flash_Dev.base; const uint8_t *dataBuf = (const uint8_t *)data; whal_Error err = WHAL_SUCCESS; (void)flashDev; @@ -202,19 +202,19 @@ whal_Error whal_Stm32f4_Flash_Write(whal_Flash *flashDev, size_t addr, return WHAL_EINVAL; /* Wait for any ongoing operation */ - err = whal_Reg_ReadPoll(base, FLASH_SR_REG, FLASH_SR_BSY_Msk, + err = whal_Reg32_ReadPoll(base, FLASH_SR_REG, FLASH_SR_BSY_Msk, 0, cfg->timeout); if (err) return err; /* Clear all error flags */ - whal_Reg_Update(base, FLASH_SR_REG, FLASH_SR_ALL_ERR, FLASH_SR_ALL_ERR); + whal_Reg32_Update(base, FLASH_SR_REG, FLASH_SR_ALL_ERR, FLASH_SR_ALL_ERR); /* Set programming mode with word-size parallelism */ - whal_Reg_Update(base, FLASH_CR_REG, - FLASH_CR_PG_Msk | FLASH_CR_PSIZE_Msk, - whal_SetBits(FLASH_CR_PG_Msk, FLASH_CR_PG_Pos, 1) | - whal_SetBits(FLASH_CR_PSIZE_Msk, FLASH_CR_PSIZE_Pos, FLASH_PSIZE_WORD)); + whal_Reg32_Update(base, FLASH_CR_REG, + FLASH_CR_PG_Msk | FLASH_CR_PSIZE_Msk, + whal_SetBits(FLASH_CR_PG_Msk, FLASH_CR_PG_Pos, 1) | + whal_SetBits(FLASH_CR_PSIZE_Msk, FLASH_CR_PSIZE_Pos, FLASH_PSIZE_WORD)); /* Program data in 32-bit word chunks */ for (size_t i = 0; i < dataSz; i += 4) { @@ -223,14 +223,14 @@ whal_Error whal_Stm32f4_Flash_Write(whal_Flash *flashDev, size_t addr, *flashAddr = whal_LoadLe32(dataBuf + i); /* Wait for programming to complete */ - err = whal_Reg_ReadPoll(base, FLASH_SR_REG, FLASH_SR_BSY_Msk, + err = whal_Reg32_ReadPoll(base, FLASH_SR_REG, FLASH_SR_BSY_Msk, 0, cfg->timeout); if (err) goto cleanup; /* Check for errors */ - if (whal_Reg_Read(base, FLASH_SR_REG) & FLASH_SR_ALL_ERR) { - whal_Reg_Update(base, FLASH_SR_REG, FLASH_SR_ALL_ERR, FLASH_SR_ALL_ERR); + if (whal_Reg32_Read(base, FLASH_SR_REG) & FLASH_SR_ALL_ERR) { + whal_Reg32_Update(base, FLASH_SR_REG, FLASH_SR_ALL_ERR, FLASH_SR_ALL_ERR); err = WHAL_EHARDWARE; goto cleanup; } @@ -238,7 +238,7 @@ whal_Error whal_Stm32f4_Flash_Write(whal_Flash *flashDev, size_t addr, cleanup: /* Disable programming mode */ - whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_PG_Msk, 0); + whal_Reg32_Update(base, FLASH_CR_REG, FLASH_CR_PG_Msk, 0); return err; } @@ -254,7 +254,7 @@ whal_Error whal_Stm32f4_Flash_Erase(whal_Flash *flashDev, size_t addr, { const whal_Stm32f4_Flash_Cfg *cfg = (const whal_Stm32f4_Flash_Cfg *)whal_Stm32f4_Flash_Dev.cfg; - size_t base = whal_Stm32f4_Flash_Dev.base; + uintptr_t base = whal_Stm32f4_Flash_Dev.base; whal_Error err = WHAL_SUCCESS; (void)flashDev; @@ -266,13 +266,13 @@ whal_Error whal_Stm32f4_Flash_Erase(whal_Flash *flashDev, size_t addr, return WHAL_EINVAL; /* Wait for any ongoing operation */ - err = whal_Reg_ReadPoll(base, FLASH_SR_REG, FLASH_SR_BSY_Msk, + err = whal_Reg32_ReadPoll(base, FLASH_SR_REG, FLASH_SR_BSY_Msk, 0, cfg->timeout); if (err) return err; /* Clear all error flags */ - whal_Reg_Update(base, FLASH_SR_REG, FLASH_SR_ALL_ERR, FLASH_SR_ALL_ERR); + whal_Reg32_Update(base, FLASH_SR_REG, FLASH_SR_ALL_ERR, FLASH_SR_ALL_ERR); /* Find and erase sectors that overlap with the address range */ for (size_t s = 0; s < cfg->sectorCount; s++) { @@ -284,26 +284,26 @@ whal_Error whal_Stm32f4_Flash_Erase(whal_Flash *flashDev, size_t addr, continue; /* Set sector erase with word parallelism */ - whal_Reg_Update(base, FLASH_CR_REG, - FLASH_CR_SER_Msk | FLASH_CR_SNB_Msk | FLASH_CR_PSIZE_Msk, - whal_SetBits(FLASH_CR_SER_Msk, FLASH_CR_SER_Pos, 1) | - whal_SetBits(FLASH_CR_SNB_Msk, FLASH_CR_SNB_Pos, - SectorNumber(s)) | - whal_SetBits(FLASH_CR_PSIZE_Msk, FLASH_CR_PSIZE_Pos, FLASH_PSIZE_WORD)); + whal_Reg32_Update(base, FLASH_CR_REG, + FLASH_CR_SER_Msk | FLASH_CR_SNB_Msk | FLASH_CR_PSIZE_Msk, + whal_SetBits(FLASH_CR_SER_Msk, FLASH_CR_SER_Pos, 1) | + whal_SetBits(FLASH_CR_SNB_Msk, FLASH_CR_SNB_Pos, + SectorNumber(s)) | + whal_SetBits(FLASH_CR_PSIZE_Msk, FLASH_CR_PSIZE_Pos, FLASH_PSIZE_WORD)); /* Start erase */ - whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_STRT_Msk, - whal_SetBits(FLASH_CR_STRT_Msk, FLASH_CR_STRT_Pos, 1)); + whal_Reg32_Update(base, FLASH_CR_REG, FLASH_CR_STRT_Msk, + whal_SetBits(FLASH_CR_STRT_Msk, FLASH_CR_STRT_Pos, 1)); /* Wait for erase to complete */ - err = whal_Reg_ReadPoll(base, FLASH_SR_REG, FLASH_SR_BSY_Msk, + err = whal_Reg32_ReadPoll(base, FLASH_SR_REG, FLASH_SR_BSY_Msk, 0, cfg->timeout); if (err) goto cleanup; /* Check for errors */ - if (whal_Reg_Read(base, FLASH_SR_REG) & FLASH_SR_ALL_ERR) { - whal_Reg_Update(base, FLASH_SR_REG, FLASH_SR_ALL_ERR, FLASH_SR_ALL_ERR); + if (whal_Reg32_Read(base, FLASH_SR_REG) & FLASH_SR_ALL_ERR) { + whal_Reg32_Update(base, FLASH_SR_REG, FLASH_SR_ALL_ERR, FLASH_SR_ALL_ERR); err = WHAL_EHARDWARE; goto cleanup; } @@ -311,7 +311,7 @@ whal_Error whal_Stm32f4_Flash_Erase(whal_Flash *flashDev, size_t addr, cleanup: /* Clear sector erase mode */ - whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_SER_Msk, 0); + whal_Reg32_Update(base, FLASH_CR_REG, FLASH_CR_SER_Msk, 0); return err; } @@ -319,11 +319,11 @@ whal_Error whal_Stm32f4_Flash_Erase(whal_Flash *flashDev, size_t addr, whal_Error whal_Stm32f4_Flash_Ext_SetLatency(whal_Flash *flashDev, enum whal_Stm32f4_Flash_Latency latency) { - size_t base = whal_Stm32f4_Flash_Dev.base; + uintptr_t base = whal_Stm32f4_Flash_Dev.base; (void)flashDev; - whal_Reg_Update(base, FLASH_ACR_REG, FLASH_ACR_LATENCY_Msk, - whal_SetBits(FLASH_ACR_LATENCY_Msk, FLASH_ACR_LATENCY_Pos, latency)); + whal_Reg32_Update(base, FLASH_ACR_REG, FLASH_ACR_LATENCY_Msk, + whal_SetBits(FLASH_ACR_LATENCY_Msk, FLASH_ACR_LATENCY_Pos, latency)); return WHAL_SUCCESS; } diff --git a/src/flash/stm32h5_flash.c b/src/flash/stm32h5_flash.c index 839c581b..b5119172 100644 --- a/src/flash/stm32h5_flash.c +++ b/src/flash/stm32h5_flash.c @@ -154,13 +154,13 @@ whal_Error whal_Stm32h5_Flash_Deinit(whal_Flash *flashDev) whal_Error whal_Stm32h5_Flash_Lock(whal_Flash *flashDev, size_t addr, size_t len) { - size_t base = whal_Stm32h5_Flash_Dev.base; + uintptr_t base = whal_Stm32h5_Flash_Dev.base; (void)flashDev; (void)addr; (void)len; - whal_Reg_Update(base, FLASH_NSCR_REG, FLASH_NSCR_LOCK_Msk, - whal_SetBits(FLASH_NSCR_LOCK_Msk, FLASH_NSCR_LOCK_Pos, 1)); + whal_Reg32_Update(base, FLASH_NSCR_REG, FLASH_NSCR_LOCK_Msk, + whal_SetBits(FLASH_NSCR_LOCK_Msk, FLASH_NSCR_LOCK_Pos, 1)); return WHAL_SUCCESS; } @@ -168,17 +168,17 @@ whal_Error whal_Stm32h5_Flash_Lock(whal_Flash *flashDev, size_t addr, whal_Error whal_Stm32h5_Flash_Unlock(whal_Flash *flashDev, size_t addr, size_t len) { - size_t base = whal_Stm32h5_Flash_Dev.base; + uintptr_t base = whal_Stm32h5_Flash_Dev.base; (void)flashDev; (void)addr; (void)len; - if (whal_Reg_Read(base, FLASH_NSCR_REG) & FLASH_NSCR_LOCK_Msk) { - whal_Reg_Write(base, FLASH_NSKEYR_REG, FLASH_KEY1); - whal_Reg_Write(base, FLASH_NSKEYR_REG, FLASH_KEY2); + if (whal_Reg32_Read(base, FLASH_NSCR_REG) & FLASH_NSCR_LOCK_Msk) { + whal_Reg32_Write(base, FLASH_NSKEYR_REG, FLASH_KEY1); + whal_Reg32_Write(base, FLASH_NSKEYR_REG, FLASH_KEY2); } - if (whal_Reg_Read(base, FLASH_NSCR_REG) & FLASH_NSCR_LOCK_Msk) + if (whal_Reg32_Read(base, FLASH_NSCR_REG) & FLASH_NSCR_LOCK_Msk) return WHAL_EHARDWARE; return WHAL_SUCCESS; @@ -206,18 +206,18 @@ whal_Error whal_Stm32h5_Flash_Read(whal_Flash *flashDev, size_t addr, return WHAL_SUCCESS; } -static whal_Error WaitNotBusy(size_t base, whal_Timeout *timeout) +static whal_Error WaitNotBusy(uintptr_t base, whal_Timeout *timeout) { - return whal_Reg_ReadPoll(base, FLASH_NSSR_REG, FLASH_NSSR_BSY_Msk, - 0, timeout); + return whal_Reg32_ReadPoll(base, FLASH_NSSR_REG, FLASH_NSSR_BSY_Msk, + 0, timeout); } -static whal_Error CheckErrors(size_t base) +static whal_Error CheckErrors(uintptr_t base) { - size_t sr = whal_Reg_Read(base, FLASH_NSSR_REG); + size_t sr = whal_Reg32_Read(base, FLASH_NSSR_REG); if (sr & FLASH_NSSR_ALL_ERR) { /* Clear all error flags */ - whal_Reg_Write(base, FLASH_NSCCR_REG, FLASH_NSCCR_CLR_ALL); + whal_Reg32_Write(base, FLASH_NSCCR_REG, FLASH_NSCCR_CLR_ALL); return WHAL_EHARDWARE; } return WHAL_SUCCESS; @@ -228,7 +228,7 @@ whal_Error whal_Stm32h5_Flash_Write(whal_Flash *flashDev, size_t addr, { const whal_Stm32h5_Flash_Cfg *cfg = (const whal_Stm32h5_Flash_Cfg *)whal_Stm32h5_Flash_Dev.cfg; - size_t base = whal_Stm32h5_Flash_Dev.base; + uintptr_t base = whal_Stm32h5_Flash_Dev.base; const uint8_t *dataBuf = (const uint8_t *)data; whal_Error err; (void)flashDev; @@ -250,11 +250,11 @@ whal_Error whal_Stm32h5_Flash_Write(whal_Flash *flashDev, size_t addr, return err; /* Clear all error and status flags */ - whal_Reg_Write(base, FLASH_NSCCR_REG, FLASH_NSCCR_CLR_ALL); + whal_Reg32_Write(base, FLASH_NSCCR_REG, FLASH_NSCCR_CLR_ALL); /* Enable programming */ - whal_Reg_Update(base, FLASH_NSCR_REG, FLASH_NSCR_PG_Msk, - whal_SetBits(FLASH_NSCR_PG_Msk, FLASH_NSCR_PG_Pos, 1)); + whal_Reg32_Update(base, FLASH_NSCR_REG, FLASH_NSCR_PG_Msk, + whal_SetBits(FLASH_NSCR_PG_Msk, FLASH_NSCR_PG_Pos, 1)); /* Program data in 128-bit (16 byte) flash-word chunks */ for (size_t i = 0; i < dataSz; i += 16) { @@ -276,7 +276,7 @@ whal_Error whal_Stm32h5_Flash_Write(whal_Flash *flashDev, size_t addr, cleanup: /* Disable programming */ - whal_Reg_Update(base, FLASH_NSCR_REG, FLASH_NSCR_PG_Msk, 0); + whal_Reg32_Update(base, FLASH_NSCR_REG, FLASH_NSCR_PG_Msk, 0); return err; } @@ -286,7 +286,7 @@ whal_Error whal_Stm32h5_Flash_Erase(whal_Flash *flashDev, size_t addr, { const whal_Stm32h5_Flash_Cfg *cfg = (const whal_Stm32h5_Flash_Cfg *)whal_Stm32h5_Flash_Dev.cfg; - size_t base = whal_Stm32h5_Flash_Dev.base; + uintptr_t base = whal_Stm32h5_Flash_Dev.base; whal_Error err; size_t offset; size_t startSector, endSector; @@ -306,7 +306,7 @@ whal_Error whal_Stm32h5_Flash_Erase(whal_Flash *flashDev, size_t addr, return err; /* Clear all error and status flags */ - whal_Reg_Write(base, FLASH_NSCCR_REG, FLASH_NSCCR_CLR_ALL); + whal_Reg32_Write(base, FLASH_NSCCR_REG, FLASH_NSCCR_CLR_ALL); /* Every STM32H5 is dual-bank with the flash split evenly between banks */ sectorsPerBank = (cfg->size / 2) >> FLASH_SECTOR_SHIFT; @@ -319,15 +319,15 @@ whal_Error whal_Stm32h5_Flash_Erase(whal_Flash *flashDev, size_t addr, size_t sectorInBank = sector - (bank * sectorsPerBank); /* Configure and start sector erase in one write */ - whal_Reg_Update(base, FLASH_NSCR_REG, - FLASH_NSCR_SER_Msk | FLASH_NSCR_SNB_Msk | - FLASH_NSCR_BKSEL_Msk | FLASH_NSCR_STRT_Msk, - whal_SetBits(FLASH_NSCR_SER_Msk, FLASH_NSCR_SER_Pos, 1) | - whal_SetBits(FLASH_NSCR_SNB_Msk, FLASH_NSCR_SNB_Pos, - sectorInBank) | - whal_SetBits(FLASH_NSCR_BKSEL_Msk, FLASH_NSCR_BKSEL_Pos, - bank) | - whal_SetBits(FLASH_NSCR_STRT_Msk, FLASH_NSCR_STRT_Pos, 1)); + whal_Reg32_Update(base, FLASH_NSCR_REG, + FLASH_NSCR_SER_Msk | FLASH_NSCR_SNB_Msk | + FLASH_NSCR_BKSEL_Msk | FLASH_NSCR_STRT_Msk, + whal_SetBits(FLASH_NSCR_SER_Msk, FLASH_NSCR_SER_Pos, 1) | + whal_SetBits(FLASH_NSCR_SNB_Msk, FLASH_NSCR_SNB_Pos, + sectorInBank) | + whal_SetBits(FLASH_NSCR_BKSEL_Msk, FLASH_NSCR_BKSEL_Pos, + bank) | + whal_SetBits(FLASH_NSCR_STRT_Msk, FLASH_NSCR_STRT_Pos, 1)); err = WaitNotBusy(base, cfg->timeout); if (err) @@ -340,7 +340,7 @@ whal_Error whal_Stm32h5_Flash_Erase(whal_Flash *flashDev, size_t addr, cleanup: /* Clear sector erase mode */ - whal_Reg_Update(base, FLASH_NSCR_REG, FLASH_NSCR_SER_Msk, 0); + whal_Reg32_Update(base, FLASH_NSCR_REG, FLASH_NSCR_SER_Msk, 0); return err; } @@ -350,11 +350,11 @@ whal_Error whal_Stm32h5_Flash_Erase(whal_Flash *flashDev, size_t addr, whal_Error whal_Stm32h5_Flash_Ext_SetLatency(whal_Flash *flashDev, uint8_t latency) { - size_t base = whal_Stm32h5_Flash_Dev.base; + uintptr_t base = whal_Stm32h5_Flash_Dev.base; (void)flashDev; - whal_Reg_Update(base, FLASH_ACR_REG, - FLASH_ACR_LATENCY_WRHIGHFREQ_Msk, latency); + whal_Reg32_Update(base, FLASH_ACR_REG, + FLASH_ACR_LATENCY_WRHIGHFREQ_Msk, latency); return WHAL_SUCCESS; } diff --git a/src/flash/stm32l1_flash.c b/src/flash/stm32l1_flash.c index 9889adf8..bbba4546 100644 --- a/src/flash/stm32l1_flash.c +++ b/src/flash/stm32l1_flash.c @@ -101,32 +101,32 @@ const whal_Flash whal_Stm32l1_Flash_Dev = WHAL_CFG_STM32L1_FLASH_DEV; * Unlock FLASH_PECR by writing the PEKEY sequence to FLASH_PEKEYR. * This clears PELOCK if the keys are correct. */ -static void UnlockPecr(size_t base) +static void UnlockPecr(uintptr_t base) { - size_t pelock; - whal_Reg_Get(base, FLASH_PECR_REG, FLASH_PECR_PELOCK_Msk, - FLASH_PECR_PELOCK_Pos, &pelock); + uint32_t pelock; + whal_Reg32_Get(base, FLASH_PECR_REG, FLASH_PECR_PELOCK_Msk, + FLASH_PECR_PELOCK_Pos, &pelock); if (!pelock) return; - whal_Reg_Write(base, FLASH_PEKEYR_REG, PEKEY1); - whal_Reg_Write(base, FLASH_PEKEYR_REG, PEKEY2); + whal_Reg32_Write(base, FLASH_PEKEYR_REG, PEKEY1); + whal_Reg32_Write(base, FLASH_PEKEYR_REG, PEKEY2); } /* * Unlock program memory by writing the PRGKEY sequence to FLASH_PRGKEYR. * PECR must be unlocked first. */ -static void UnlockProgram(size_t base) +static void UnlockProgram(uintptr_t base) { - size_t prglock; - whal_Reg_Get(base, FLASH_PECR_REG, FLASH_PECR_PRGLOCK_Msk, - FLASH_PECR_PRGLOCK_Pos, &prglock); + uint32_t prglock; + whal_Reg32_Get(base, FLASH_PECR_REG, FLASH_PECR_PRGLOCK_Msk, + FLASH_PECR_PRGLOCK_Pos, &prglock); if (!prglock) return; - whal_Reg_Write(base, FLASH_PRGKEYR_REG, PRGKEY1); - whal_Reg_Write(base, FLASH_PRGKEYR_REG, PRGKEY2); + whal_Reg32_Write(base, FLASH_PRGKEYR_REG, PRGKEY1); + whal_Reg32_Write(base, FLASH_PRGKEYR_REG, PRGKEY2); } whal_Error whal_Stm32l1_Flash_Init(whal_Flash *flashDev) @@ -143,34 +143,34 @@ whal_Error whal_Stm32l1_Flash_Deinit(whal_Flash *flashDev) whal_Error whal_Stm32l1_Flash_Lock(whal_Flash *flashDev, size_t addr, size_t len) { - size_t base = whal_Stm32l1_Flash_Dev.base; + uintptr_t base = whal_Stm32l1_Flash_Dev.base; (void)flashDev; (void)addr; (void)len; /* Set PELOCK to lock everything */ - whal_Reg_Update(base, FLASH_PECR_REG, - FLASH_PECR_PELOCK_Msk, - whal_SetBits(FLASH_PECR_PELOCK_Msk, - FLASH_PECR_PELOCK_Pos, 1)); + whal_Reg32_Update(base, FLASH_PECR_REG, + FLASH_PECR_PELOCK_Msk, + whal_SetBits(FLASH_PECR_PELOCK_Msk, + FLASH_PECR_PELOCK_Pos, 1)); return WHAL_SUCCESS; } whal_Error whal_Stm32l1_Flash_Unlock(whal_Flash *flashDev, size_t addr, size_t len) { - size_t base = whal_Stm32l1_Flash_Dev.base; + uintptr_t base = whal_Stm32l1_Flash_Dev.base; (void)flashDev; (void)addr; (void)len; /* Unlock PECR then program memory */ UnlockPecr(base); - if (whal_Reg_Read(base, FLASH_PECR_REG) & FLASH_PECR_PELOCK_Msk) + if (whal_Reg32_Read(base, FLASH_PECR_REG) & FLASH_PECR_PELOCK_Msk) return WHAL_EHARDWARE; UnlockProgram(base); - if (whal_Reg_Read(base, FLASH_PECR_REG) & FLASH_PECR_PRGLOCK_Msk) + if (whal_Reg32_Read(base, FLASH_PECR_REG) & FLASH_PECR_PRGLOCK_Msk) return WHAL_EHARDWARE; return WHAL_SUCCESS; @@ -207,7 +207,7 @@ whal_Error whal_Stm32l1_Flash_Write(whal_Flash *flashDev, size_t addr, { const whal_Stm32l1_Flash_Cfg *cfg = (const whal_Stm32l1_Flash_Cfg *)whal_Stm32l1_Flash_Dev.cfg; - size_t base = whal_Stm32l1_Flash_Dev.base; + uintptr_t base = whal_Stm32l1_Flash_Dev.base; const uint8_t *buf = (const uint8_t *)data; whal_Error err = WHAL_SUCCESS; (void)flashDev; @@ -227,7 +227,7 @@ whal_Error whal_Stm32l1_Flash_Write(whal_Flash *flashDev, size_t addr, return WHAL_EINVAL; /* Clear error flags */ - whal_Reg_Write(base, FLASH_SR_REG, FLASH_SR_ALL_ERR); + whal_Reg32_Write(base, FLASH_SR_REG, FLASH_SR_ALL_ERR); /* * Fast Word Write: PECR and program memory must already be unlocked. @@ -243,12 +243,12 @@ whal_Error whal_Stm32l1_Flash_Write(whal_Flash *flashDev, size_t addr, *flashAddr = word; - err = whal_Reg_ReadPoll(base, FLASH_SR_REG, FLASH_SR_BSY_Msk, 0, - cfg->timeout); + err = whal_Reg32_ReadPoll(base, FLASH_SR_REG, FLASH_SR_BSY_Msk, 0, + cfg->timeout); if (err) return err; - if (whal_Reg_Read(base, FLASH_SR_REG) & FLASH_SR_ALL_ERR) + if (whal_Reg32_Read(base, FLASH_SR_REG) & FLASH_SR_ALL_ERR) return WHAL_EHARDWARE; } @@ -260,7 +260,7 @@ whal_Error whal_Stm32l1_Flash_Erase(whal_Flash *flashDev, size_t addr, { const whal_Stm32l1_Flash_Cfg *cfg = (const whal_Stm32l1_Flash_Cfg *)whal_Stm32l1_Flash_Dev.cfg; - size_t base = whal_Stm32l1_Flash_Dev.base; + uintptr_t base = whal_Stm32l1_Flash_Dev.base; whal_Error err = WHAL_SUCCESS; (void)flashDev; @@ -271,42 +271,42 @@ whal_Error whal_Stm32l1_Flash_Erase(whal_Flash *flashDev, size_t addr, addr - cfg->startAddr > cfg->size - dataSz) return WHAL_EINVAL; - err = whal_Reg_ReadPoll(base, FLASH_SR_REG, FLASH_SR_BSY_Msk, 0, - cfg->timeout); + err = whal_Reg32_ReadPoll(base, FLASH_SR_REG, FLASH_SR_BSY_Msk, 0, + cfg->timeout); if (err) return err; - whal_Reg_Write(base, FLASH_SR_REG, FLASH_SR_ALL_ERR); + whal_Reg32_Write(base, FLASH_SR_REG, FLASH_SR_ALL_ERR); size_t startPage = (addr - cfg->startAddr) >> PAGE_SHIFT; size_t endPage = ((addr - cfg->startAddr) + dataSz - 1) >> PAGE_SHIFT; - whal_Reg_Update(base, FLASH_PECR_REG, FLASH_PECR_ERASE_Msk, - whal_SetBits(FLASH_PECR_ERASE_Msk, - FLASH_PECR_ERASE_Pos, 1)); - whal_Reg_Update(base, FLASH_PECR_REG, FLASH_PECR_PROG_Msk, - whal_SetBits(FLASH_PECR_PROG_Msk, - FLASH_PECR_PROG_Pos, 1)); + whal_Reg32_Update(base, FLASH_PECR_REG, FLASH_PECR_ERASE_Msk, + whal_SetBits(FLASH_PECR_ERASE_Msk, + FLASH_PECR_ERASE_Pos, 1)); + whal_Reg32_Update(base, FLASH_PECR_REG, FLASH_PECR_PROG_Msk, + whal_SetBits(FLASH_PECR_PROG_Msk, + FLASH_PECR_PROG_Pos, 1)); for (size_t page = startPage; page <= endPage; ++page) { volatile uint32_t *pageAddr = (volatile uint32_t *)(cfg->startAddr + (page << PAGE_SHIFT)); *pageAddr = 0x00000000; - err = whal_Reg_ReadPoll(base, FLASH_SR_REG, FLASH_SR_BSY_Msk, 0, - cfg->timeout); + err = whal_Reg32_ReadPoll(base, FLASH_SR_REG, FLASH_SR_BSY_Msk, 0, + cfg->timeout); if (err) goto cleanup; - if (whal_Reg_Read(base, FLASH_SR_REG) & FLASH_SR_ALL_ERR) { + if (whal_Reg32_Read(base, FLASH_SR_REG) & FLASH_SR_ALL_ERR) { err = WHAL_EHARDWARE; goto cleanup; } } cleanup: - whal_Reg_Update(base, FLASH_PECR_REG, - FLASH_PECR_ERASE_Msk | FLASH_PECR_PROG_Msk, 0); + whal_Reg32_Update(base, FLASH_PECR_REG, + FLASH_PECR_ERASE_Msk | FLASH_PECR_PROG_Msk, 0); return err; } @@ -317,27 +317,27 @@ whal_Error whal_Stm32l1_Flash_Ext_SetLatency(whal_Stm32l1_Flash_Latency latency) (const whal_Stm32l1_Flash_Cfg *)whal_Stm32l1_Flash_Dev.cfg; whal_Error err; - whal_Reg_Update(FLASH_BASE_ADDR, FLASH_ACR_REG, FLASH_ACR_ACC64_Msk, - whal_SetBits(FLASH_ACR_ACC64_Msk, - FLASH_ACR_ACC64_Pos, 1)); - err = whal_Reg_ReadPoll(FLASH_BASE_ADDR, FLASH_ACR_REG, - FLASH_ACR_ACC64_Msk, FLASH_ACR_ACC64_Msk, - cfg->timeout); + whal_Reg32_Update(FLASH_BASE_ADDR, FLASH_ACR_REG, FLASH_ACR_ACC64_Msk, + whal_SetBits(FLASH_ACR_ACC64_Msk, + FLASH_ACR_ACC64_Pos, 1)); + err = whal_Reg32_ReadPoll(FLASH_BASE_ADDR, FLASH_ACR_REG, + FLASH_ACR_ACC64_Msk, FLASH_ACR_ACC64_Msk, + cfg->timeout); if (err) return err; - whal_Reg_Update(FLASH_BASE_ADDR, FLASH_ACR_REG, FLASH_ACR_PRFTEN_Msk, - whal_SetBits(FLASH_ACR_PRFTEN_Msk, - FLASH_ACR_PRFTEN_Pos, 1)); - - whal_Reg_Update(FLASH_BASE_ADDR, FLASH_ACR_REG, FLASH_ACR_LATENCY_Msk, - whal_SetBits(FLASH_ACR_LATENCY_Msk, - FLASH_ACR_LATENCY_Pos, latency)); - return whal_Reg_ReadPoll(FLASH_BASE_ADDR, FLASH_ACR_REG, - FLASH_ACR_LATENCY_Msk, - whal_SetBits(FLASH_ACR_LATENCY_Msk, - FLASH_ACR_LATENCY_Pos, latency), - cfg->timeout); + whal_Reg32_Update(FLASH_BASE_ADDR, FLASH_ACR_REG, FLASH_ACR_PRFTEN_Msk, + whal_SetBits(FLASH_ACR_PRFTEN_Msk, + FLASH_ACR_PRFTEN_Pos, 1)); + + whal_Reg32_Update(FLASH_BASE_ADDR, FLASH_ACR_REG, FLASH_ACR_LATENCY_Msk, + whal_SetBits(FLASH_ACR_LATENCY_Msk, + FLASH_ACR_LATENCY_Pos, latency)); + return whal_Reg32_ReadPoll(FLASH_BASE_ADDR, FLASH_ACR_REG, + FLASH_ACR_LATENCY_Msk, + whal_SetBits(FLASH_ACR_LATENCY_Msk, + FLASH_ACR_LATENCY_Pos, latency), + cfg->timeout); } #ifndef WHAL_CFG_STM32L1_FLASH_DIRECT_API_MAPPING diff --git a/src/flash/stm32u5_flash.c b/src/flash/stm32u5_flash.c index 04ab7072..c923a3d7 100644 --- a/src/flash/stm32u5_flash.c +++ b/src/flash/stm32u5_flash.c @@ -124,30 +124,30 @@ whal_Error whal_Stm32u5_Flash_Deinit(whal_Flash *flashDev) whal_Error whal_Stm32u5_Flash_Lock(whal_Flash *flashDev, size_t addr, size_t len) { - size_t base = whal_Stm32u5_Flash_Dev.base; + uintptr_t base = whal_Stm32u5_Flash_Dev.base; (void)flashDev; (void)addr; (void)len; - whal_Reg_Update(base, FLASH_NSCR_REG, FLASH_NSCR_LOCK_Msk, - whal_SetBits(FLASH_NSCR_LOCK_Msk, FLASH_NSCR_LOCK_Pos, 1)); + whal_Reg32_Update(base, FLASH_NSCR_REG, FLASH_NSCR_LOCK_Msk, + whal_SetBits(FLASH_NSCR_LOCK_Msk, FLASH_NSCR_LOCK_Pos, 1)); return WHAL_SUCCESS; } whal_Error whal_Stm32u5_Flash_Unlock(whal_Flash *flashDev, size_t addr, size_t len) { - size_t base = whal_Stm32u5_Flash_Dev.base; + uintptr_t base = whal_Stm32u5_Flash_Dev.base; (void)flashDev; (void)addr; (void)len; - if (whal_Reg_Read(base, FLASH_NSCR_REG) & FLASH_NSCR_LOCK_Msk) { - whal_Reg_Write(base, FLASH_NSKEYR_REG, FLASH_KEY1); - whal_Reg_Write(base, FLASH_NSKEYR_REG, FLASH_KEY2); + if (whal_Reg32_Read(base, FLASH_NSCR_REG) & FLASH_NSCR_LOCK_Msk) { + whal_Reg32_Write(base, FLASH_NSKEYR_REG, FLASH_KEY1); + whal_Reg32_Write(base, FLASH_NSKEYR_REG, FLASH_KEY2); } - if (whal_Reg_Read(base, FLASH_NSCR_REG) & FLASH_NSCR_LOCK_Msk) + if (whal_Reg32_Read(base, FLASH_NSCR_REG) & FLASH_NSCR_LOCK_Msk) return WHAL_EHARDWARE; return WHAL_SUCCESS; @@ -175,18 +175,18 @@ whal_Error whal_Stm32u5_Flash_Read(whal_Flash *flashDev, size_t addr, return WHAL_SUCCESS; } -static whal_Error WaitNotBusy(size_t base, whal_Timeout *timeout) +static whal_Error WaitNotBusy(uintptr_t base, whal_Timeout *timeout) { - return whal_Reg_ReadPoll(base, FLASH_NSSR_REG, - FLASH_NSSR_BSY_Msk | FLASH_NSSR_WDW_Msk, - 0, timeout); + return whal_Reg32_ReadPoll(base, FLASH_NSSR_REG, + FLASH_NSSR_BSY_Msk | FLASH_NSSR_WDW_Msk, + 0, timeout); } -static whal_Error CheckAndClearErrors(size_t base) +static whal_Error CheckAndClearErrors(uintptr_t base) { - size_t sr = whal_Reg_Read(base, FLASH_NSSR_REG); + size_t sr = whal_Reg32_Read(base, FLASH_NSSR_REG); if (sr & FLASH_NSSR_ALL_ERR) { - whal_Reg_Write(base, FLASH_NSSR_REG, sr & FLASH_NSSR_ALL_ERR); + whal_Reg32_Write(base, FLASH_NSSR_REG, sr & FLASH_NSSR_ALL_ERR); return WHAL_EHARDWARE; } return WHAL_SUCCESS; @@ -197,7 +197,7 @@ whal_Error whal_Stm32u5_Flash_Write(whal_Flash *flashDev, size_t addr, { const whal_Stm32u5_Flash_Cfg *cfg = (const whal_Stm32u5_Flash_Cfg *)whal_Stm32u5_Flash_Dev.cfg; - size_t base = whal_Stm32u5_Flash_Dev.base; + uintptr_t base = whal_Stm32u5_Flash_Dev.base; const uint8_t *dataBuf = (const uint8_t *)data; whal_Error err; (void)flashDev; @@ -218,12 +218,12 @@ whal_Error whal_Stm32u5_Flash_Write(whal_Flash *flashDev, size_t addr, return err; /* Clear error flags */ - whal_Reg_Write(base, FLASH_NSSR_REG, - whal_Reg_Read(base, FLASH_NSSR_REG) & FLASH_NSSR_ALL_ERR); + whal_Reg32_Write(base, FLASH_NSSR_REG, + whal_Reg32_Read(base, FLASH_NSSR_REG) & FLASH_NSSR_ALL_ERR); /* Enable programming */ - whal_Reg_Update(base, FLASH_NSCR_REG, FLASH_NSCR_PG_Msk, - whal_SetBits(FLASH_NSCR_PG_Msk, FLASH_NSCR_PG_Pos, 1)); + whal_Reg32_Update(base, FLASH_NSCR_REG, FLASH_NSCR_PG_Msk, + whal_SetBits(FLASH_NSCR_PG_Msk, FLASH_NSCR_PG_Pos, 1)); /* Program in 128-bit (16 byte) flash-word chunks. The destination must * be volatile — the flash controller's write FIFO requires exactly 4 @@ -247,7 +247,7 @@ whal_Error whal_Stm32u5_Flash_Write(whal_Flash *flashDev, size_t addr, } cleanup: - whal_Reg_Update(base, FLASH_NSCR_REG, FLASH_NSCR_PG_Msk, 0); + whal_Reg32_Update(base, FLASH_NSCR_REG, FLASH_NSCR_PG_Msk, 0); return err; } @@ -255,7 +255,7 @@ whal_Error whal_Stm32u5_Flash_Erase(whal_Flash *flashDev, size_t addr, size_t da { const whal_Stm32u5_Flash_Cfg *cfg = (const whal_Stm32u5_Flash_Cfg *)whal_Stm32u5_Flash_Dev.cfg; - size_t base = whal_Stm32u5_Flash_Dev.base; + uintptr_t base = whal_Stm32u5_Flash_Dev.base; size_t bankSize = cfg->bankSize ? cfg->bankSize : WHAL_STM32U5_FLASH_BANK_SIZE; whal_Error err; size_t offset, startGlobal, endGlobal; @@ -273,8 +273,8 @@ whal_Error whal_Stm32u5_Flash_Erase(whal_Flash *flashDev, size_t addr, size_t da return err; /* Clear error flags */ - whal_Reg_Write(base, FLASH_NSSR_REG, - whal_Reg_Read(base, FLASH_NSSR_REG) & FLASH_NSSR_ALL_ERR); + whal_Reg32_Write(base, FLASH_NSSR_REG, + whal_Reg32_Read(base, FLASH_NSSR_REG) & FLASH_NSSR_ALL_ERR); offset = addr - cfg->startAddr; startGlobal = offset / WHAL_STM32U5_FLASH_PAGE_SIZE; @@ -286,14 +286,14 @@ whal_Error whal_Stm32u5_Flash_Erase(whal_Flash *flashDev, size_t addr, size_t da size_t page = global % pagesPerBank; /* Configure page erase: PER=1, BKER=bank, PNB=page, STRT=1 */ - whal_Reg_Update(base, FLASH_NSCR_REG, - FLASH_NSCR_PER_Msk | FLASH_NSCR_BKER_Msk | + whal_Reg32_Update(base, FLASH_NSCR_REG, + FLASH_NSCR_PER_Msk | FLASH_NSCR_BKER_Msk | FLASH_NSCR_PNB_Msk, - whal_SetBits(FLASH_NSCR_PER_Msk, FLASH_NSCR_PER_Pos, 1) | - whal_SetBits(FLASH_NSCR_BKER_Msk, FLASH_NSCR_BKER_Pos, bank) | - whal_SetBits(FLASH_NSCR_PNB_Msk, FLASH_NSCR_PNB_Pos, page)); - whal_Reg_Update(base, FLASH_NSCR_REG, FLASH_NSCR_STRT_Msk, - whal_SetBits(FLASH_NSCR_STRT_Msk, FLASH_NSCR_STRT_Pos, 1)); + whal_SetBits(FLASH_NSCR_PER_Msk, FLASH_NSCR_PER_Pos, 1) | + whal_SetBits(FLASH_NSCR_BKER_Msk, FLASH_NSCR_BKER_Pos, bank) | + whal_SetBits(FLASH_NSCR_PNB_Msk, FLASH_NSCR_PNB_Pos, page)); + whal_Reg32_Update(base, FLASH_NSCR_REG, FLASH_NSCR_STRT_Msk, + whal_SetBits(FLASH_NSCR_STRT_Msk, FLASH_NSCR_STRT_Pos, 1)); err = WaitNotBusy(base, cfg->timeout); if (err) @@ -305,16 +305,16 @@ whal_Error whal_Stm32u5_Flash_Erase(whal_Flash *flashDev, size_t addr, size_t da } cleanup: - whal_Reg_Update(base, FLASH_NSCR_REG, FLASH_NSCR_PER_Msk, 0); + whal_Reg32_Update(base, FLASH_NSCR_REG, FLASH_NSCR_PER_Msk, 0); return err; } whal_Error whal_Stm32u5_Flash_Ext_SetLatency(whal_Flash *flashDev, uint8_t latency) { - size_t base = whal_Stm32u5_Flash_Dev.base; + uintptr_t base = whal_Stm32u5_Flash_Dev.base; (void)flashDev; - whal_Reg_Update(base, FLASH_ACR_REG, FLASH_ACR_LATENCY_Msk, latency); + whal_Reg32_Update(base, FLASH_ACR_REG, FLASH_ACR_LATENCY_Msk, latency); return WHAL_SUCCESS; } diff --git a/src/flash/stm32wb0_flash.c b/src/flash/stm32wb0_flash.c index 04b28184..12e998fe 100644 --- a/src/flash/stm32wb0_flash.c +++ b/src/flash/stm32wb0_flash.c @@ -101,51 +101,51 @@ const whal_Flash whal_Stm32wb0_Flash_Dev = WHAL_CFG_STM32WB0_FLASH_DEV; * CMDDONE, clear it, then sweep CMDERR/ILLCMD into an error code. All * polling loops are bounded by the configured whal_Timeout. */ -static whal_Error whal_Stm32wb0_Flash_RunCommand(size_t base, uint32_t cmd, +static whal_Error whal_Stm32wb0_Flash_RunCommand(uintptr_t base, uint32_t cmd, whal_Timeout *timeout) { whal_Error err; size_t irq; /* Clear any stale start/done/error flags before launching. */ - whal_Reg_Write(base, FLASH_IRQSTAT_REG, - FLASH_IRQ_CMDSTART_Msk | FLASH_IRQ_CMDDONE_Msk | + whal_Reg32_Write(base, FLASH_IRQSTAT_REG, + FLASH_IRQ_CMDSTART_Msk | FLASH_IRQ_CMDDONE_Msk | FLASH_IRQ_ALL_ERR_Msk); - whal_Reg_Write(base, FLASH_COMMAND_REG, cmd); + whal_Reg32_Write(base, FLASH_COMMAND_REG, cmd); /* Wait for CMDSTART (controller has accepted the opcode). */ WHAL_TIMEOUT_START(timeout); while (1) { if (WHAL_TIMEOUT_EXPIRED(timeout)) return WHAL_ETIMEOUT; - irq = whal_Reg_Read(base, FLASH_IRQRAW_REG); + irq = whal_Reg32_Read(base, FLASH_IRQRAW_REG); if (irq & FLASH_IRQ_ALL_ERR_Msk) { - whal_Reg_Write(base, FLASH_IRQSTAT_REG, FLASH_IRQ_ALL_ERR_Msk); + whal_Reg32_Write(base, FLASH_IRQSTAT_REG, FLASH_IRQ_ALL_ERR_Msk); return WHAL_EHARDWARE; } if (irq & FLASH_IRQ_CMDSTART_Msk) break; } - whal_Reg_Write(base, FLASH_IRQSTAT_REG, FLASH_IRQ_CMDSTART_Msk); + whal_Reg32_Write(base, FLASH_IRQSTAT_REG, FLASH_IRQ_CMDSTART_Msk); /* Wait for CMDDONE. */ WHAL_TIMEOUT_START(timeout); while (1) { if (WHAL_TIMEOUT_EXPIRED(timeout)) return WHAL_ETIMEOUT; - irq = whal_Reg_Read(base, FLASH_IRQRAW_REG); + irq = whal_Reg32_Read(base, FLASH_IRQRAW_REG); if (irq & FLASH_IRQ_ALL_ERR_Msk) { - whal_Reg_Write(base, FLASH_IRQSTAT_REG, FLASH_IRQ_ALL_ERR_Msk); + whal_Reg32_Write(base, FLASH_IRQSTAT_REG, FLASH_IRQ_ALL_ERR_Msk); err = WHAL_EHARDWARE; /* Still clear CMDDONE if present so we don't leave it set. */ - whal_Reg_Write(base, FLASH_IRQSTAT_REG, FLASH_IRQ_CMDDONE_Msk); + whal_Reg32_Write(base, FLASH_IRQSTAT_REG, FLASH_IRQ_CMDDONE_Msk); return err; } if (irq & FLASH_IRQ_CMDDONE_Msk) break; } - whal_Reg_Write(base, FLASH_IRQSTAT_REG, FLASH_IRQ_CMDDONE_Msk); + whal_Reg32_Write(base, FLASH_IRQSTAT_REG, FLASH_IRQ_CMDDONE_Msk); return WHAL_SUCCESS; } @@ -183,30 +183,30 @@ whal_Error whal_Stm32wb0_Flash_Deinit(whal_Flash *flashDev) whal_Error whal_Stm32wb0_Flash_Lock(whal_Flash *flashDev, size_t addr, size_t len) { - size_t base = whal_Stm32wb0_Flash_Dev.base; + uintptr_t base = whal_Stm32wb0_Flash_Dev.base; (void)flashDev; (void)addr; (void)len; /* A segment from page 0 with the largest SIZE ends at the last page */ - whal_Reg_Write(base, FLASH_PAGEPROT0_REG, - whal_SetBits(FLASH_PAGEPROT_SEG0_OFFSET_Msk, - FLASH_PAGEPROT_SEG0_OFFSET_Pos, 0) | - whal_SetBits(FLASH_PAGEPROT_SEG0_SIZE_Msk, - FLASH_PAGEPROT_SEG0_SIZE_Pos, 0x7F)); + whal_Reg32_Write(base, FLASH_PAGEPROT0_REG, + whal_SetBits(FLASH_PAGEPROT_SEG0_OFFSET_Msk, + FLASH_PAGEPROT_SEG0_OFFSET_Pos, 0) | + whal_SetBits(FLASH_PAGEPROT_SEG0_SIZE_Msk, + FLASH_PAGEPROT_SEG0_SIZE_Pos, 0x7F)); return WHAL_SUCCESS; } whal_Error whal_Stm32wb0_Flash_Unlock(whal_Flash *flashDev, size_t addr, size_t len) { - size_t base = whal_Stm32wb0_Flash_Dev.base; + uintptr_t base = whal_Stm32wb0_Flash_Dev.base; (void)flashDev; (void)addr; (void)len; - whal_Reg_Write(base, FLASH_PAGEPROT0_REG, 0); - whal_Reg_Write(base, FLASH_PAGEPROT1_REG, 0); + whal_Reg32_Write(base, FLASH_PAGEPROT0_REG, 0); + whal_Reg32_Write(base, FLASH_PAGEPROT1_REG, 0); return WHAL_SUCCESS; } @@ -238,7 +238,7 @@ whal_Error whal_Stm32wb0_Flash_Write(whal_Flash *flashDev, size_t addr, { const whal_Stm32wb0_Flash_Cfg *cfg = (const whal_Stm32wb0_Flash_Cfg *)whal_Stm32wb0_Flash_Dev.cfg; - size_t base = whal_Stm32wb0_Flash_Dev.base; + uintptr_t base = whal_Stm32wb0_Flash_Dev.base; const uint8_t *dataBuf = (const uint8_t *)data; whal_Error err; (void)flashDev; @@ -263,9 +263,9 @@ whal_Error whal_Stm32wb0_Flash_Write(whal_Flash *flashDev, size_t addr, ((uint32_t)dataBuf[i + 2] << 16) | ((uint32_t)dataBuf[i + 3] << 24); - whal_Reg_Write(base, FLASH_ADDRESS_REG, - whal_Stm32wb0_Flash_AddrToHw(cfg, addr + i)); - whal_Reg_Write(base, FLASH_DATA0_REG, word); + whal_Reg32_Write(base, FLASH_ADDRESS_REG, + whal_Stm32wb0_Flash_AddrToHw(cfg, addr + i)); + whal_Reg32_Write(base, FLASH_DATA0_REG, word); err = whal_Stm32wb0_Flash_RunCommand(base, FLASH_COMMAND_WRITE, cfg->timeout); @@ -280,7 +280,7 @@ whal_Error whal_Stm32wb0_Flash_Erase(whal_Flash *flashDev, size_t addr, { const whal_Stm32wb0_Flash_Cfg *cfg = (const whal_Stm32wb0_Flash_Cfg *)whal_Stm32wb0_Flash_Dev.cfg; - size_t base = whal_Stm32wb0_Flash_Dev.base; + uintptr_t base = whal_Stm32wb0_Flash_Dev.base; whal_Error err; (void)flashDev; @@ -298,7 +298,7 @@ whal_Error whal_Stm32wb0_Flash_Erase(whal_Flash *flashDev, size_t addr, for (size_t p = firstPage; p <= lastPage; ++p) { /* For ERASE, ADDRESS[15:9] = page number, lower bits zero. */ uint32_t hwAddr = (uint32_t)(p * FLASH_PAGE_SIZE / FLASH_WORD_SIZE); - whal_Reg_Write(base, FLASH_ADDRESS_REG, hwAddr); + whal_Reg32_Write(base, FLASH_ADDRESS_REG, hwAddr); err = whal_Stm32wb0_Flash_RunCommand(base, FLASH_COMMAND_ERASE, cfg->timeout); @@ -311,12 +311,12 @@ whal_Error whal_Stm32wb0_Flash_Erase(whal_Flash *flashDev, size_t addr, whal_Error whal_Stm32wb0_Flash_Ext_SetLatency(whal_Flash *flashDev, enum whal_Stm32wb0_Flash_Latency latency) { - size_t base = whal_Stm32wb0_Flash_Dev.base; + uintptr_t base = whal_Stm32wb0_Flash_Dev.base; (void)flashDev; - whal_Reg_Update(base, FLASH_CONFIG_REG, FLASH_CONFIG_WAIT_STATES_Msk, - whal_SetBits(FLASH_CONFIG_WAIT_STATES_Msk, - FLASH_CONFIG_WAIT_STATES_Pos, latency)); + whal_Reg32_Update(base, FLASH_CONFIG_REG, FLASH_CONFIG_WAIT_STATES_Msk, + whal_SetBits(FLASH_CONFIG_WAIT_STATES_Msk, + FLASH_CONFIG_WAIT_STATES_Pos, latency)); return WHAL_SUCCESS; } diff --git a/src/flash/stm32wb_flash.c b/src/flash/stm32wb_flash.c index 56de0c1a..d2759e0f 100644 --- a/src/flash/stm32wb_flash.c +++ b/src/flash/stm32wb_flash.c @@ -138,21 +138,21 @@ whal_Error whal_Stm32wb_Flash_Deinit(whal_Flash *flashDev) whal_Error whal_Stm32wb_Flash_Lock(whal_Flash *flashDev, size_t addr, size_t len) { - size_t base = whal_Stm32wb_Flash_Dev.base; + uintptr_t base = whal_Stm32wb_Flash_Dev.base; (void)flashDev; (void)addr; (void)len; /* Setting LOCK bit prevents further flash modifications until next unlock */ - whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_LOCK_Msk, - whal_SetBits(FLASH_CR_LOCK_Msk, FLASH_CR_LOCK_Pos, 1)); + whal_Reg32_Update(base, FLASH_CR_REG, FLASH_CR_LOCK_Msk, + whal_SetBits(FLASH_CR_LOCK_Msk, FLASH_CR_LOCK_Pos, 1)); return WHAL_SUCCESS; } whal_Error whal_Stm32wb_Flash_Unlock(whal_Flash *flashDev, size_t addr, size_t len) { - size_t base = whal_Stm32wb_Flash_Dev.base; + uintptr_t base = whal_Stm32wb_Flash_Dev.base; (void)flashDev; (void)addr; (void)len; @@ -161,12 +161,12 @@ whal_Error whal_Stm32wb_Flash_Unlock(whal_Flash *flashDev, size_t addr, size_t l * Unlock sequence: write KEY1 then KEY2 to KEYR register. * Incorrect sequence or order will trigger a bus error. */ - if (whal_Reg_Read(base, FLASH_CR_REG) & FLASH_CR_LOCK_Msk) { - whal_Reg_Update(base, FLASH_KEYR_REG, FLASH_KEYR_KEY_Msk, 0x45670123); - whal_Reg_Update(base, FLASH_KEYR_REG, FLASH_KEYR_KEY_Msk, 0xCDEF89AB); + if (whal_Reg32_Read(base, FLASH_CR_REG) & FLASH_CR_LOCK_Msk) { + whal_Reg32_Update(base, FLASH_KEYR_REG, FLASH_KEYR_KEY_Msk, 0x45670123); + whal_Reg32_Update(base, FLASH_KEYR_REG, FLASH_KEYR_KEY_Msk, 0xCDEF89AB); } - if (whal_Reg_Read(base, FLASH_CR_REG) & FLASH_CR_LOCK_Msk) + if (whal_Reg32_Read(base, FLASH_CR_REG) & FLASH_CR_LOCK_Msk) return WHAL_EHARDWARE; return WHAL_SUCCESS; @@ -209,9 +209,9 @@ static whal_Error whal_Stm32wb_Flash_WriteOrErase(whal_Flash *flashDev, size_t a { const whal_Stm32wb_Flash_Cfg *cfg = (const whal_Stm32wb_Flash_Cfg *)whal_Stm32wb_Flash_Dev.cfg; - size_t base = whal_Stm32wb_Flash_Dev.base; - size_t bsy; - size_t pesd; + uintptr_t base = whal_Stm32wb_Flash_Dev.base; + uint32_t bsy; + uint32_t pesd; (void)flashDev; if (dataSz == 0) @@ -226,25 +226,25 @@ static whal_Error whal_Stm32wb_Flash_WriteOrErase(whal_Flash *flashDev, size_t a return WHAL_EINVAL; /* Check if flash is busy or suspended */ - whal_Reg_Get(base, FLASH_SR_REG, FLASH_SR_BSY_Msk, FLASH_SR_BSY_Pos, &bsy); - whal_Reg_Get(base, FLASH_SR_REG, FLASH_SR_PESD_Msk, FLASH_SR_PESD_Pos, &pesd); + whal_Reg32_Get(base, FLASH_SR_REG, FLASH_SR_BSY_Msk, FLASH_SR_BSY_Pos, &bsy); + whal_Reg32_Get(base, FLASH_SR_REG, FLASH_SR_PESD_Msk, FLASH_SR_PESD_Pos, &pesd); if (bsy || pesd || - (whal_Reg_Read(base, FLASH_SR_REG) & FLASH_SR_CFGBSY_Msk)) { + (whal_Reg32_Read(base, FLASH_SR_REG) & FLASH_SR_CFGBSY_Msk)) { return WHAL_ENOTREADY; } /* Drop PG/PER left set by an earlier operation that timed out */ - whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_PG_Msk | FLASH_CR_PER_Msk, 0); + whal_Reg32_Update(base, FLASH_CR_REG, FLASH_CR_PG_Msk | FLASH_CR_PER_Msk, 0); /* Clear all error flags by writing 1 to each */ - whal_Reg_Update(base, FLASH_SR_REG, FLASH_SR_ALL_ERR, 0xffffffff); + whal_Reg32_Update(base, FLASH_SR_REG, FLASH_SR_ALL_ERR, 0xffffffff); whal_Error err = WHAL_SUCCESS; if (write) { /* Enable flash programming mode */ - whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_PG_Msk, 1); + whal_Reg32_Update(base, FLASH_CR_REG, FLASH_CR_PG_Msk, 1); /* Program data in 64-bit (8 byte) double-word chunks */ for (size_t i = 0; i < dataSz; i += 8) { @@ -255,14 +255,14 @@ static whal_Error whal_Stm32wb_Flash_WriteOrErase(whal_Flash *flashDev, size_t a flashAddr[1] = whal_LoadLe32(data + i + 4); /* Wait for programming to complete */ - err = whal_Reg_ReadPoll(base, FLASH_SR_REG, - FLASH_SR_CFGBSY_Msk, 0, cfg->timeout); + err = whal_Reg32_ReadPoll(base, FLASH_SR_REG, + FLASH_SR_CFGBSY_Msk, 0, cfg->timeout); if (err) goto cleanup; /* Check for errors */ - if (whal_Reg_Read(base, FLASH_SR_REG) & FLASH_SR_ALL_ERR) { - whal_Reg_Update(base, FLASH_SR_REG, FLASH_SR_ALL_ERR, FLASH_SR_ALL_ERR); + if (whal_Reg32_Read(base, FLASH_SR_REG) & FLASH_SR_ALL_ERR) { + whal_Reg32_Update(base, FLASH_SR_REG, FLASH_SR_ALL_ERR, FLASH_SR_ALL_ERR); err = WHAL_EHARDWARE; goto cleanup; } @@ -275,28 +275,28 @@ static whal_Error whal_Stm32wb_Flash_WriteOrErase(whal_Flash *flashDev, size_t a endPage = ((addr - cfg->startAddr) + dataSz - 1) >> 12; /* Enable page erase mode */ - whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_PER_Msk, - whal_SetBits(FLASH_CR_PER_Msk, FLASH_CR_PER_Pos, 1)); + whal_Reg32_Update(base, FLASH_CR_REG, FLASH_CR_PER_Msk, + whal_SetBits(FLASH_CR_PER_Msk, FLASH_CR_PER_Pos, 1)); /* Erase each page in the range */ for (size_t page = startPage; page <= endPage; ++page) { /* Select page number */ - whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_PNB_Msk, - whal_SetBits(FLASH_CR_PNB_Msk, FLASH_CR_PNB_Pos, page)); + whal_Reg32_Update(base, FLASH_CR_REG, FLASH_CR_PNB_Msk, + whal_SetBits(FLASH_CR_PNB_Msk, FLASH_CR_PNB_Pos, page)); /* Start erase operation */ - whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_STRT_Msk, - whal_SetBits(FLASH_CR_STRT_Msk, FLASH_CR_STRT_Pos, 1)); + whal_Reg32_Update(base, FLASH_CR_REG, FLASH_CR_STRT_Msk, + whal_SetBits(FLASH_CR_STRT_Msk, FLASH_CR_STRT_Pos, 1)); /* Wait for erase to complete */ - err = whal_Reg_ReadPoll(base, FLASH_SR_REG, - FLASH_SR_CFGBSY_Msk, 0, cfg->timeout); + err = whal_Reg32_ReadPoll(base, FLASH_SR_REG, + FLASH_SR_CFGBSY_Msk, 0, cfg->timeout); if (err) goto cleanup; /* Check for errors */ - if (whal_Reg_Read(base, FLASH_SR_REG) & FLASH_SR_ALL_ERR) { - whal_Reg_Update(base, FLASH_SR_REG, FLASH_SR_ALL_ERR, FLASH_SR_ALL_ERR); + if (whal_Reg32_Read(base, FLASH_SR_REG) & FLASH_SR_ALL_ERR) { + whal_Reg32_Update(base, FLASH_SR_REG, FLASH_SR_ALL_ERR, FLASH_SR_ALL_ERR); err = WHAL_EHARDWARE; goto cleanup; } @@ -305,9 +305,9 @@ static whal_Error whal_Stm32wb_Flash_WriteOrErase(whal_Flash *flashDev, size_t a cleanup: /* FLASH_CR must not be written while CFGBSY is set */ - if (!(whal_Reg_Read(base, FLASH_SR_REG) & FLASH_SR_CFGBSY_Msk)) - whal_Reg_Update(base, FLASH_CR_REG, - FLASH_CR_PG_Msk | FLASH_CR_PER_Msk, 0); + if (!(whal_Reg32_Read(base, FLASH_SR_REG) & FLASH_SR_CFGBSY_Msk)) + whal_Reg32_Update(base, FLASH_CR_REG, + FLASH_CR_PG_Msk | FLASH_CR_PER_Msk, 0); return err; } @@ -326,10 +326,10 @@ whal_Error whal_Stm32wb_Flash_Erase(whal_Flash *flashDev, size_t addr, whal_Error whal_Stm32wb_Flash_Ext_SetLatency(whal_Flash *flashDev, enum whal_Stm32wb_Flash_Latency latency) { - size_t base = whal_Stm32wb_Flash_Dev.base; + uintptr_t base = whal_Stm32wb_Flash_Dev.base; (void)flashDev; - whal_Reg_Update(base, FLASH_ACR_REG, FLASH_ACR_LATENCY_Msk, latency); + whal_Reg32_Update(base, FLASH_ACR_REG, FLASH_ACR_LATENCY_Msk, latency); return WHAL_SUCCESS; } diff --git a/src/flash/stm32wba_flash.c b/src/flash/stm32wba_flash.c index 222be318..776f3b85 100644 --- a/src/flash/stm32wba_flash.c +++ b/src/flash/stm32wba_flash.c @@ -121,31 +121,31 @@ whal_Error whal_Stm32wba_Flash_Deinit(whal_Flash *flashDev) whal_Error whal_Stm32wba_Flash_Lock(whal_Flash *flashDev, size_t addr, size_t len) { - size_t base = whal_Stm32wba_Flash_Dev.base; + uintptr_t base = whal_Stm32wba_Flash_Dev.base; (void)flashDev; (void)addr; (void)len; - whal_Reg_Update(base, FLASH_NSCR1_REG, FLASH_NSCR1_LOCK_Msk, - whal_SetBits(FLASH_NSCR1_LOCK_Msk, FLASH_NSCR1_LOCK_Pos, 1)); + whal_Reg32_Update(base, FLASH_NSCR1_REG, FLASH_NSCR1_LOCK_Msk, + whal_SetBits(FLASH_NSCR1_LOCK_Msk, FLASH_NSCR1_LOCK_Pos, 1)); return WHAL_SUCCESS; } whal_Error whal_Stm32wba_Flash_Unlock(whal_Flash *flashDev, size_t addr, size_t len) { - size_t base = whal_Stm32wba_Flash_Dev.base; + uintptr_t base = whal_Stm32wba_Flash_Dev.base; (void)flashDev; (void)addr; (void)len; /* Only write the unlock sequence if LOCK bit is set */ - if (whal_Reg_Read(base, FLASH_NSCR1_REG) & FLASH_NSCR1_LOCK_Msk) { - whal_Reg_Write(base, FLASH_NSKEYR_REG, FLASH_KEY1); - whal_Reg_Write(base, FLASH_NSKEYR_REG, FLASH_KEY2); + if (whal_Reg32_Read(base, FLASH_NSCR1_REG) & FLASH_NSCR1_LOCK_Msk) { + whal_Reg32_Write(base, FLASH_NSKEYR_REG, FLASH_KEY1); + whal_Reg32_Write(base, FLASH_NSKEYR_REG, FLASH_KEY2); } - if (whal_Reg_Read(base, FLASH_NSCR1_REG) & FLASH_NSCR1_LOCK_Msk) + if (whal_Reg32_Read(base, FLASH_NSCR1_REG) & FLASH_NSCR1_LOCK_Msk) return WHAL_EHARDWARE; return WHAL_SUCCESS; @@ -172,23 +172,23 @@ whal_Error whal_Stm32wba_Flash_Read(whal_Flash *flashDev, size_t addr, void *dat return WHAL_SUCCESS; } -static whal_Error WaitNotBusy(size_t base, whal_Timeout *timeout) +static whal_Error WaitNotBusy(uintptr_t base, whal_Timeout *timeout) { whal_Error err; /* WDW must be checked clear before BSY */ - err = whal_Reg_ReadPoll(base, FLASH_NSSR_REG, FLASH_NSSR_WDW_Msk, 0, timeout); + err = whal_Reg32_ReadPoll(base, FLASH_NSSR_REG, FLASH_NSSR_WDW_Msk, 0, timeout); if (err) return err; - return whal_Reg_ReadPoll(base, FLASH_NSSR_REG, FLASH_NSSR_BSY_Msk, 0, timeout); + return whal_Reg32_ReadPoll(base, FLASH_NSSR_REG, FLASH_NSSR_BSY_Msk, 0, timeout); } -static whal_Error CheckAndClearErrors(size_t base) +static whal_Error CheckAndClearErrors(uintptr_t base) { - size_t sr = whal_Reg_Read(base, FLASH_NSSR_REG); + size_t sr = whal_Reg32_Read(base, FLASH_NSSR_REG); if (sr & FLASH_NSSR_ALL_ERR) { /* Clear error flags by writing 1 to them */ - whal_Reg_Write(base, FLASH_NSSR_REG, sr & FLASH_NSSR_ALL_ERR); + whal_Reg32_Write(base, FLASH_NSSR_REG, sr & FLASH_NSSR_ALL_ERR); return WHAL_EHARDWARE; } return WHAL_SUCCESS; @@ -199,7 +199,7 @@ whal_Error whal_Stm32wba_Flash_Write(whal_Flash *flashDev, size_t addr, { const whal_Stm32wba_Flash_Cfg *cfg = (const whal_Stm32wba_Flash_Cfg *)whal_Stm32wba_Flash_Dev.cfg; - size_t base = whal_Stm32wba_Flash_Dev.base; + uintptr_t base = whal_Stm32wba_Flash_Dev.base; const uint8_t *dataBuf = (const uint8_t *)data; whal_Error err; (void)flashDev; @@ -220,12 +220,12 @@ whal_Error whal_Stm32wba_Flash_Write(whal_Flash *flashDev, size_t addr, return err; /* Clear error flags */ - whal_Reg_Write(base, FLASH_NSSR_REG, - whal_Reg_Read(base, FLASH_NSSR_REG) & FLASH_NSSR_ALL_ERR); + whal_Reg32_Write(base, FLASH_NSSR_REG, + whal_Reg32_Read(base, FLASH_NSSR_REG) & FLASH_NSSR_ALL_ERR); /* Enable programming */ - whal_Reg_Update(base, FLASH_NSCR1_REG, FLASH_NSCR1_PG_Msk, - whal_SetBits(FLASH_NSCR1_PG_Msk, FLASH_NSCR1_PG_Pos, 1)); + whal_Reg32_Update(base, FLASH_NSCR1_REG, FLASH_NSCR1_PG_Msk, + whal_SetBits(FLASH_NSCR1_PG_Msk, FLASH_NSCR1_PG_Pos, 1)); /* Program in 128-bit (16 byte) flash-word chunks */ for (size_t i = 0; i < dataSz; i += 16) { @@ -246,7 +246,7 @@ whal_Error whal_Stm32wba_Flash_Write(whal_Flash *flashDev, size_t addr, } cleanup: - whal_Reg_Update(base, FLASH_NSCR1_REG, FLASH_NSCR1_PG_Msk, 0); + whal_Reg32_Update(base, FLASH_NSCR1_REG, FLASH_NSCR1_PG_Msk, 0); return err; } @@ -254,7 +254,7 @@ whal_Error whal_Stm32wba_Flash_Erase(whal_Flash *flashDev, size_t addr, size_t d { const whal_Stm32wba_Flash_Cfg *cfg = (const whal_Stm32wba_Flash_Cfg *)whal_Stm32wba_Flash_Dev.cfg; - size_t base = whal_Stm32wba_Flash_Dev.base; + uintptr_t base = whal_Stm32wba_Flash_Dev.base; whal_Error err; size_t offset, startPage, endPage; (void)flashDev; @@ -271,8 +271,8 @@ whal_Error whal_Stm32wba_Flash_Erase(whal_Flash *flashDev, size_t addr, size_t d return err; /* Clear error flags */ - whal_Reg_Write(base, FLASH_NSSR_REG, - whal_Reg_Read(base, FLASH_NSSR_REG) & FLASH_NSSR_ALL_ERR); + whal_Reg32_Write(base, FLASH_NSSR_REG, + whal_Reg32_Read(base, FLASH_NSSR_REG) & FLASH_NSSR_ALL_ERR); offset = addr - cfg->startAddr; startPage = offset >> FLASH_SECTOR_SHIFT; @@ -280,11 +280,11 @@ whal_Error whal_Stm32wba_Flash_Erase(whal_Flash *flashDev, size_t addr, size_t d for (size_t page = startPage; page <= endPage; page++) { /* Configure page erase: PER=1, PNB=page, STRT=1 */ - whal_Reg_Update(base, FLASH_NSCR1_REG, - FLASH_NSCR1_PER_Msk | FLASH_NSCR1_PNB_Msk | FLASH_NSCR1_STRT_Msk, - whal_SetBits(FLASH_NSCR1_PER_Msk, FLASH_NSCR1_PER_Pos, 1) | - whal_SetBits(FLASH_NSCR1_PNB_Msk, FLASH_NSCR1_PNB_Pos, page) | - whal_SetBits(FLASH_NSCR1_STRT_Msk, FLASH_NSCR1_STRT_Pos, 1)); + whal_Reg32_Update(base, FLASH_NSCR1_REG, + FLASH_NSCR1_PER_Msk | FLASH_NSCR1_PNB_Msk | FLASH_NSCR1_STRT_Msk, + whal_SetBits(FLASH_NSCR1_PER_Msk, FLASH_NSCR1_PER_Pos, 1) | + whal_SetBits(FLASH_NSCR1_PNB_Msk, FLASH_NSCR1_PNB_Pos, page) | + whal_SetBits(FLASH_NSCR1_STRT_Msk, FLASH_NSCR1_STRT_Pos, 1)); err = WaitNotBusy(base, cfg->timeout); if (err) @@ -296,16 +296,16 @@ whal_Error whal_Stm32wba_Flash_Erase(whal_Flash *flashDev, size_t addr, size_t d } cleanup: - whal_Reg_Update(base, FLASH_NSCR1_REG, FLASH_NSCR1_PER_Msk, 0); + whal_Reg32_Update(base, FLASH_NSCR1_REG, FLASH_NSCR1_PER_Msk, 0); return err; } whal_Error whal_Stm32wba_Flash_Ext_SetLatency(whal_Flash *flashDev, uint8_t latency) { - size_t base = whal_Stm32wba_Flash_Dev.base; + uintptr_t base = whal_Stm32wba_Flash_Dev.base; (void)flashDev; - whal_Reg_Update(base, FLASH_ACR_REG, FLASH_ACR_LATENCY_Msk, latency); + whal_Reg32_Update(base, FLASH_ACR_REG, FLASH_ACR_LATENCY_Msk, latency); return WHAL_SUCCESS; } diff --git a/src/gpio/pic32cz_gpio.c b/src/gpio/pic32cz_gpio.c index ae12a343..046b93bd 100644 --- a/src/gpio/pic32cz_gpio.c +++ b/src/gpio/pic32cz_gpio.c @@ -91,7 +91,7 @@ whal_Error whal_Pic32cz_Gpio_Init(whal_Gpio *gpioDev) { const whal_Pic32cz_Gpio_Cfg *cfg = (const whal_Pic32cz_Gpio_Cfg *)whal_Pic32cz_Gpio_Dev.cfg; - size_t base = whal_Pic32cz_Gpio_Dev.base; + uintptr_t base = whal_Pic32cz_Gpio_Dev.base; (void)gpioDev; for (size_t i = 0; i < cfg->pinCfgCount; ++i) { @@ -109,15 +109,15 @@ whal_Error whal_Pic32cz_Gpio_Init(whal_Gpio *gpioDev) size_t pmuxenMask = PINCFGx_PMUXEN_Msk(pinCfg->pin); size_t pmuxenPos = PINCFGx_PMUXEN_Pos(pinCfg->pin); - whal_Reg_Update(base, - PMUXx_REG(pinCfg->port, pinCfg->pin), - pmuxMask, - whal_SetBits(pmuxMask, pmuxPos, pinCfg->pmux)); + whal_Reg32_Update(base, + PMUXx_REG(pinCfg->port, pinCfg->pin), + pmuxMask, + whal_SetBits(pmuxMask, pmuxPos, pinCfg->pmux)); - whal_Reg_Update(base, - PINCFGx_REG(pinCfg->port, pinCfg->pin), - pmuxenMask, - whal_SetBits(pmuxenMask, pmuxenPos, 1)); + whal_Reg32_Update(base, + PINCFGx_REG(pinCfg->port, pinCfg->pin), + pmuxenMask, + whal_SetBits(pmuxenMask, pmuxenPos, 1)); continue; } @@ -130,14 +130,14 @@ whal_Error whal_Pic32cz_Gpio_Init(whal_Gpio *gpioDev) */ /* Set pin direction */ - whal_Reg_Update(base, DIR_REG(pinCfg->port), - pinMask, - whal_SetBits(pinMask, pinCfg->pin, pinCfg->dir)); + whal_Reg32_Update(base, DIR_REG(pinCfg->port), + pinMask, + whal_SetBits(pinMask, pinCfg->pin, pinCfg->dir)); /* Set initial output value */ - whal_Reg_Update(base, OUT_REG(pinCfg->port), - pinMask, - whal_SetBits(pinMask, pinCfg->pin, pinCfg->out)); + whal_Reg32_Update(base, OUT_REG(pinCfg->port), + pinMask, + whal_SetBits(pinMask, pinCfg->pin, pinCfg->out)); /* Configure input buffer and pull resistor */ { @@ -146,11 +146,11 @@ whal_Error whal_Pic32cz_Gpio_Init(whal_Gpio *gpioDev) size_t pullenMask = PINCFGx_PULLEN_Msk(pinCfg->pin); size_t pullenPos = PINCFGx_PULLEN_Pos(pinCfg->pin); - whal_Reg_Update(base, - PINCFGx_REG(pinCfg->port, pinCfg->pin), - inenMask | pullenMask, - whal_SetBits(inenMask, inenPos, pinCfg->inEn) | - whal_SetBits(pullenMask, pullenPos, pinCfg->pullEn)); + whal_Reg32_Update(base, + PINCFGx_REG(pinCfg->port, pinCfg->pin), + inenMask | pullenMask, + whal_SetBits(inenMask, inenPos, pinCfg->inEn) | + whal_SetBits(pullenMask, pullenPos, pinCfg->pullEn)); } } @@ -167,10 +167,11 @@ whal_Error whal_Pic32cz_Gpio_Get(whal_Gpio *gpioDev, size_t pin, size_t *value) { const whal_Pic32cz_Gpio_Cfg *cfg = (const whal_Pic32cz_Gpio_Cfg *)whal_Pic32cz_Gpio_Dev.cfg; - size_t base = whal_Pic32cz_Gpio_Dev.base; + uintptr_t base = whal_Pic32cz_Gpio_Dev.base; whal_Pic32cz_Gpio_PinCfg *pinCfg; - size_t pinMask; - size_t reg; + uint32_t pinMask; + uint32_t reg; + uint32_t bit; (void)gpioDev; if (!value || pin >= cfg->pinCfgCount) @@ -191,7 +192,8 @@ whal_Error whal_Pic32cz_Gpio_Get(whal_Gpio *gpioDev, size_t pin, size_t *value) reg = IN_REG(pinCfg->port); } - whal_Reg_Get(base, reg, pinMask, pinCfg->pin, value); + whal_Reg32_Get(base, reg, pinMask, pinCfg->pin, &bit); + *value = bit; return WHAL_SUCCESS; } @@ -200,9 +202,9 @@ whal_Error whal_Pic32cz_Gpio_Set(whal_Gpio *gpioDev, size_t pin, size_t value) { const whal_Pic32cz_Gpio_Cfg *cfg = (const whal_Pic32cz_Gpio_Cfg *)whal_Pic32cz_Gpio_Dev.cfg; - size_t base = whal_Pic32cz_Gpio_Dev.base; + uintptr_t base = whal_Pic32cz_Gpio_Dev.base; whal_Pic32cz_Gpio_PinCfg *pinCfg; - size_t pinMask; + uint32_t pinMask; (void)gpioDev; if (pin >= cfg->pinCfgCount) @@ -211,7 +213,7 @@ whal_Error whal_Pic32cz_Gpio_Set(whal_Gpio *gpioDev, size_t pin, size_t value) pinCfg = &cfg->pinCfg[pin]; pinMask = (1UL << (pinCfg->pin)); - whal_Reg_Write(base, value ? OUTSET_REG(pinCfg->port) : + whal_Reg32_Write(base, value ? OUTSET_REG(pinCfg->port) : OUTCLR_REG(pinCfg->port), pinMask); return WHAL_SUCCESS; diff --git a/src/gpio/stm32wb0_gpio.c b/src/gpio/stm32wb0_gpio.c index bfd71a7e..7c3c82d4 100644 --- a/src/gpio/stm32wb0_gpio.c +++ b/src/gpio/stm32wb0_gpio.c @@ -57,7 +57,7 @@ const whal_Gpio whal_Stm32wb0_Gpio_Dev = WHAL_CFG_STM32WB0_GPIO_DEV; static inline whal_Error whal_Stm32wb0_Gpio_InitPin(whal_Stm32wb0_Gpio_PinCfg cfg) { uint8_t pin = WHAL_STM32WB0_GPIO_GET_PIN(cfg); - size_t portBase; + uintptr_t portBase; uint8_t pos2; size_t mask2, mask1; @@ -70,22 +70,22 @@ static inline whal_Error whal_Stm32wb0_Gpio_InitPin(whal_Stm32wb0_Gpio_PinCfg cf mask2 = WHAL_BITMASK(2) << pos2; mask1 = 1UL << pin; - whal_Reg_Update(portBase, GPIO_MODE_REG, mask2, - WHAL_STM32WB0_GPIO_GET_MODE(cfg) << pos2); - whal_Reg_Update(portBase, GPIO_SPEED_REG, mask2, - WHAL_STM32WB0_GPIO_GET_SPEED(cfg) << pos2); - whal_Reg_Update(portBase, GPIO_PULL_REG, mask2, - WHAL_STM32WB0_GPIO_GET_PULL(cfg) << pos2); - whal_Reg_Update(portBase, GPIO_OUTTYPE_REG, mask1, - WHAL_STM32WB0_GPIO_GET_OUTTYPE(cfg) << pin); + whal_Reg32_Update(portBase, GPIO_MODE_REG, mask2, + WHAL_STM32WB0_GPIO_GET_MODE(cfg) << pos2); + whal_Reg32_Update(portBase, GPIO_SPEED_REG, mask2, + WHAL_STM32WB0_GPIO_GET_SPEED(cfg) << pos2); + whal_Reg32_Update(portBase, GPIO_PULL_REG, mask2, + WHAL_STM32WB0_GPIO_GET_PULL(cfg) << pos2); + whal_Reg32_Update(portBase, GPIO_OUTTYPE_REG, mask1, + WHAL_STM32WB0_GPIO_GET_OUTTYPE(cfg) << pin); if (WHAL_STM32WB0_GPIO_GET_MODE(cfg) == WHAL_STM32WB0_GPIO_MODE_ALTFN) { uint8_t afPos = (pin & 7) << 2; - whal_Reg_Update(portBase, - (pin < 8) ? GPIO_ALTFNL_REG : GPIO_ALTFNH_REG, - WHAL_BITMASK(4) << afPos, - WHAL_STM32WB0_GPIO_GET_ALTFN(cfg) << afPos); + whal_Reg32_Update(portBase, + (pin < 8) ? GPIO_ALTFNL_REG : GPIO_ALTFNH_REG, + WHAL_BITMASK(4) << afPos, + WHAL_STM32WB0_GPIO_GET_ALTFN(cfg) << afPos); } return WHAL_SUCCESS; @@ -120,7 +120,8 @@ static whal_Error whal_Stm32wb0_Gpio_SetOrGet(whal_Gpio *gpioDev, size_t idx, (const whal_Stm32wb0_Gpio_Cfg *)whal_Stm32wb0_Gpio_Dev.cfg; whal_Stm32wb0_Gpio_PinCfg pinCfg; uint8_t port, pin; - size_t portBase, mask; + uintptr_t portBase; + uint32_t mask, bit; (void)gpioDev; if (!value || idx >= cfg->pinCount) @@ -134,10 +135,11 @@ static whal_Error whal_Stm32wb0_Gpio_SetOrGet(whal_Gpio *gpioDev, size_t idx, mask = 1UL << pin; if (set) { - whal_Reg_Write(portBase, GPIO_BSRR_REG, - *value ? mask : (mask << GPIO_BSRR_BR_Pos)); + whal_Reg32_Write(portBase, GPIO_BSRR_REG, + *value ? mask : (mask << GPIO_BSRR_BR_Pos)); } else { - whal_Reg_Get(portBase, GPIO_IDR_REG, mask, pin, value); + whal_Reg32_Get(portBase, GPIO_IDR_REG, mask, pin, &bit); + *value = bit; } return WHAL_SUCCESS; } diff --git a/src/gpio/stm32wb_gpio.c b/src/gpio/stm32wb_gpio.c index 9bd105a7..6ecfc236 100644 --- a/src/gpio/stm32wb_gpio.c +++ b/src/gpio/stm32wb_gpio.c @@ -72,7 +72,7 @@ const whal_Gpio whal_Stm32wb_Gpio_Dev = WHAL_CFG_STM32WB_GPIO_DEV; static inline whal_Error whal_Stm32wb_Gpio_InitPin(whal_Stm32wb_Gpio_PinCfg cfg) { uint8_t pin = WHAL_STM32WB_GPIO_GET_PIN(cfg); - size_t portBase; + uintptr_t portBase; uint8_t pos2; size_t mask2, mask1; @@ -85,25 +85,25 @@ static inline whal_Error whal_Stm32wb_Gpio_InitPin(whal_Stm32wb_Gpio_PinCfg cfg) mask2 = WHAL_BITMASK(2) << pos2; mask1 = 1UL << pin; - whal_Reg_Update(portBase, GPIO_MODE_REG, mask2, - WHAL_STM32WB_GPIO_GET_MODE(cfg) << pos2); + whal_Reg32_Update(portBase, GPIO_MODE_REG, mask2, + WHAL_STM32WB_GPIO_GET_MODE(cfg) << pos2); - whal_Reg_Update(portBase, GPIO_SPEED_REG, mask2, - WHAL_STM32WB_GPIO_GET_SPEED(cfg) << pos2); + whal_Reg32_Update(portBase, GPIO_SPEED_REG, mask2, + WHAL_STM32WB_GPIO_GET_SPEED(cfg) << pos2); - whal_Reg_Update(portBase, GPIO_PULL_REG, mask2, - WHAL_STM32WB_GPIO_GET_PULL(cfg) << pos2); + whal_Reg32_Update(portBase, GPIO_PULL_REG, mask2, + WHAL_STM32WB_GPIO_GET_PULL(cfg) << pos2); - whal_Reg_Update(portBase, GPIO_OUTTYPE_REG, mask1, - WHAL_STM32WB_GPIO_GET_OUTTYPE(cfg) << pin); + whal_Reg32_Update(portBase, GPIO_OUTTYPE_REG, mask1, + WHAL_STM32WB_GPIO_GET_OUTTYPE(cfg) << pin); if (WHAL_STM32WB_GPIO_GET_MODE(cfg) == WHAL_STM32WB_GPIO_MODE_ALTFN) { uint8_t afPos = (pin & 7) << 2; - whal_Reg_Update(portBase, - (pin < 8) ? GPIO_ALTFNL_REG : GPIO_ALTFNH_REG, - WHAL_BITMASK(4) << afPos, - WHAL_STM32WB_GPIO_GET_ALTFN(cfg) << afPos); + whal_Reg32_Update(portBase, + (pin < 8) ? GPIO_ALTFNL_REG : GPIO_ALTFNH_REG, + WHAL_BITMASK(4) << afPos, + WHAL_STM32WB_GPIO_GET_ALTFN(cfg) << afPos); } return WHAL_SUCCESS; @@ -147,7 +147,8 @@ static whal_Error whal_Stm32wb_Gpio_SetOrGet(whal_Gpio *gpioDev, size_t idx, (const whal_Stm32wb_Gpio_Cfg *)whal_Stm32wb_Gpio_Dev.cfg; whal_Stm32wb_Gpio_PinCfg pinCfg; uint8_t port, pin; - size_t portBase, mask; + uintptr_t portBase; + uint32_t mask, bit; (void)gpioDev; if (!value || idx >= cfg->pinCount) { @@ -162,10 +163,11 @@ static whal_Error whal_Stm32wb_Gpio_SetOrGet(whal_Gpio *gpioDev, size_t idx, mask = 1UL << pin; if (set) { - whal_Reg_Write(portBase, GPIO_BSRR_REG, - *value ? mask : (mask << GPIO_BSRR_BR_Pos)); + whal_Reg32_Write(portBase, GPIO_BSRR_REG, + *value ? mask : (mask << GPIO_BSRR_BR_Pos)); } else { - whal_Reg_Get(portBase, GPIO_IDR_REG, mask, pin, value); + whal_Reg32_Get(portBase, GPIO_IDR_REG, mask, pin, &bit); + *value = bit; } return WHAL_SUCCESS; diff --git a/src/i2c/stm32l1_i2c.c b/src/i2c/stm32l1_i2c.c index b0ac256b..59a46ab8 100644 --- a/src/i2c/stm32l1_i2c.c +++ b/src/i2c/stm32l1_i2c.c @@ -110,20 +110,20 @@ const whal_I2c whal_Stm32l1_I2c_Dev = WHAL_CFG_STM32L1_I2C_DEV; #endif -static whal_Error Stm32l1_I2c_WaitSR1(size_t base, uint32_t flag, +static whal_Error Stm32l1_I2c_WaitSR1(uintptr_t base, uint32_t flag, whal_Timeout *timeout) { WHAL_TIMEOUT_START(timeout); while (1) { - uint32_t sr1 = whal_Reg_Read(base, I2C_SR1); + uint32_t sr1 = whal_Reg32_Read(base, I2C_SR1); if (sr1 & flag) return WHAL_SUCCESS; if (sr1 & SR1_ERR_Msk) { - whal_Reg_Update(base, I2C_SR1, SR1_ERR_Msk, 0); - whal_Reg_Update(base, I2C_CR1, CR1_STOP_Msk, CR1_STOP_Msk); + whal_Reg32_Update(base, I2C_SR1, SR1_ERR_Msk, 0); + whal_Reg32_Update(base, I2C_CR1, CR1_STOP_Msk, CR1_STOP_Msk); return WHAL_EHARDWARE; } @@ -132,28 +132,28 @@ static whal_Error Stm32l1_I2c_WaitSR1(size_t base, uint32_t flag, } } -static void Stm32l1_I2c_ClearAddr(size_t base) +static void Stm32l1_I2c_ClearAddr(uintptr_t base) { - (void)whal_Reg_Read(base, I2C_SR1); - (void)whal_Reg_Read(base, I2C_SR2); + (void)whal_Reg32_Read(base, I2C_SR1); + (void)whal_Reg32_Read(base, I2C_SR2); } -static whal_Error Stm32l1_I2c_SendStart(size_t base, uint16_t addr, +static whal_Error Stm32l1_I2c_SendStart(uintptr_t base, uint16_t addr, uint8_t addrSz, uint8_t isRead, whal_Timeout *timeout) { whal_Error err; uint8_t header; - whal_Reg_Update(base, I2C_CR1, CR1_START_Msk, CR1_START_Msk); + whal_Reg32_Update(base, I2C_CR1, CR1_START_Msk, CR1_START_Msk); err = Stm32l1_I2c_WaitSR1(base, SR1_SB_Msk, timeout); if (err) return err; if (addrSz == 7) { - whal_Reg_Write(base, I2C_DR, - (uint8_t)((addr << 1) | (isRead ? 1 : 0))); + whal_Reg32_Write(base, I2C_DR, + (uint8_t)((addr << 1) | (isRead ? 1 : 0))); return Stm32l1_I2c_WaitSR1(base, SR1_ADDR_Msk, timeout); } @@ -166,13 +166,13 @@ static whal_Error Stm32l1_I2c_SendStart(size_t base, uint16_t addr, */ header = (uint8_t)(0xF0 | (((addr >> 8) & 0x03) << 1)); - whal_Reg_Write(base, I2C_DR, header); + whal_Reg32_Write(base, I2C_DR, header); err = Stm32l1_I2c_WaitSR1(base, SR1_ADD10_Msk, timeout); if (err) return err; - whal_Reg_Write(base, I2C_DR, (uint8_t)(addr & 0xFF)); + whal_Reg32_Write(base, I2C_DR, (uint8_t)(addr & 0xFF)); err = Stm32l1_I2c_WaitSR1(base, SR1_ADDR_Msk, timeout); if (err) @@ -183,18 +183,18 @@ static whal_Error Stm32l1_I2c_SendStart(size_t base, uint16_t addr, Stm32l1_I2c_ClearAddr(base); - whal_Reg_Update(base, I2C_CR1, CR1_START_Msk, CR1_START_Msk); + whal_Reg32_Update(base, I2C_CR1, CR1_START_Msk, CR1_START_Msk); err = Stm32l1_I2c_WaitSR1(base, SR1_SB_Msk, timeout); if (err) return err; - whal_Reg_Write(base, I2C_DR, (uint8_t)(header | 0x01)); + whal_Reg32_Write(base, I2C_DR, (uint8_t)(header | 0x01)); return Stm32l1_I2c_WaitSR1(base, SR1_ADDR_Msk, timeout); } -static whal_Error Stm32l1_I2c_MasterWrite(size_t base, uint8_t *buf, size_t len, +static whal_Error Stm32l1_I2c_MasterWrite(uintptr_t base, uint8_t *buf, size_t len, uint8_t stop, whal_Timeout *timeout) { whal_Error err; @@ -204,7 +204,7 @@ static whal_Error Stm32l1_I2c_MasterWrite(size_t base, uint8_t *buf, size_t len, if (err) return err; - whal_Reg_Write(base, I2C_DR, buf[i]); + whal_Reg32_Write(base, I2C_DR, buf[i]); } err = Stm32l1_I2c_WaitSR1(base, SR1_BTF_Msk, timeout); @@ -212,7 +212,7 @@ static whal_Error Stm32l1_I2c_MasterWrite(size_t base, uint8_t *buf, size_t len, return err; if (stop) - whal_Reg_Update(base, I2C_CR1, CR1_STOP_Msk, CR1_STOP_Msk); + whal_Reg32_Update(base, I2C_CR1, CR1_STOP_Msk, CR1_STOP_Msk); return WHAL_SUCCESS; } @@ -224,26 +224,26 @@ static whal_Error Stm32l1_I2c_MasterWrite(size_t base, uint8_t *buf, size_t len, * RM0038 Section 26.3.3, including the ACK/POS manipulation that must * happen before the ADDR flag is cleared. */ -static whal_Error Stm32l1_I2c_MasterRead(size_t base, uint8_t *buf, size_t len, +static whal_Error Stm32l1_I2c_MasterRead(uintptr_t base, uint8_t *buf, size_t len, uint8_t stop, whal_Timeout *timeout) { whal_Error err; if (len == 1) { - whal_Reg_Update(base, I2C_CR1, CR1_ACK_Msk, 0); + whal_Reg32_Update(base, I2C_CR1, CR1_ACK_Msk, 0); Stm32l1_I2c_ClearAddr(base); if (stop) - whal_Reg_Update(base, I2C_CR1, CR1_STOP_Msk, CR1_STOP_Msk); + whal_Reg32_Update(base, I2C_CR1, CR1_STOP_Msk, CR1_STOP_Msk); err = Stm32l1_I2c_WaitSR1(base, SR1_RXNE_Msk, timeout); if (err) return err; - buf[0] = (uint8_t)whal_Reg_Read(base, I2C_DR); + buf[0] = (uint8_t)whal_Reg32_Read(base, I2C_DR); } else if (len == 2) { - whal_Reg_Update(base, I2C_CR1, CR1_ACK_Msk | CR1_POS_Msk, CR1_POS_Msk); + whal_Reg32_Update(base, I2C_CR1, CR1_ACK_Msk | CR1_POS_Msk, CR1_POS_Msk); Stm32l1_I2c_ClearAddr(base); err = Stm32l1_I2c_WaitSR1(base, SR1_BTF_Msk, timeout); @@ -251,13 +251,13 @@ static whal_Error Stm32l1_I2c_MasterRead(size_t base, uint8_t *buf, size_t len, return err; if (stop) - whal_Reg_Update(base, I2C_CR1, CR1_STOP_Msk, CR1_STOP_Msk); + whal_Reg32_Update(base, I2C_CR1, CR1_STOP_Msk, CR1_STOP_Msk); - buf[0] = (uint8_t)whal_Reg_Read(base, I2C_DR); - buf[1] = (uint8_t)whal_Reg_Read(base, I2C_DR); + buf[0] = (uint8_t)whal_Reg32_Read(base, I2C_DR); + buf[1] = (uint8_t)whal_Reg32_Read(base, I2C_DR); } else { - whal_Reg_Update(base, I2C_CR1, CR1_ACK_Msk, CR1_ACK_Msk); + whal_Reg32_Update(base, I2C_CR1, CR1_ACK_Msk, CR1_ACK_Msk); Stm32l1_I2c_ClearAddr(base); for (size_t i = 0; i < len - 3; i++) { @@ -265,28 +265,28 @@ static whal_Error Stm32l1_I2c_MasterRead(size_t base, uint8_t *buf, size_t len, if (err) return err; - buf[i] = (uint8_t)whal_Reg_Read(base, I2C_DR); + buf[i] = (uint8_t)whal_Reg32_Read(base, I2C_DR); } err = Stm32l1_I2c_WaitSR1(base, SR1_BTF_Msk, timeout); if (err) return err; - whal_Reg_Update(base, I2C_CR1, CR1_ACK_Msk, 0); - buf[len - 3] = (uint8_t)whal_Reg_Read(base, I2C_DR); + whal_Reg32_Update(base, I2C_CR1, CR1_ACK_Msk, 0); + buf[len - 3] = (uint8_t)whal_Reg32_Read(base, I2C_DR); err = Stm32l1_I2c_WaitSR1(base, SR1_BTF_Msk, timeout); if (err) return err; if (stop) - whal_Reg_Update(base, I2C_CR1, CR1_STOP_Msk, CR1_STOP_Msk); + whal_Reg32_Update(base, I2C_CR1, CR1_STOP_Msk, CR1_STOP_Msk); - buf[len - 2] = (uint8_t)whal_Reg_Read(base, I2C_DR); - buf[len - 1] = (uint8_t)whal_Reg_Read(base, I2C_DR); + buf[len - 2] = (uint8_t)whal_Reg32_Read(base, I2C_DR); + buf[len - 1] = (uint8_t)whal_Reg32_Read(base, I2C_DR); } - whal_Reg_Update(base, I2C_CR1, CR1_POS_Msk, 0); + whal_Reg32_Update(base, I2C_CR1, CR1_POS_Msk, 0); return WHAL_SUCCESS; } @@ -321,10 +321,10 @@ static uint32_t Stm32l1_I2c_CalcTrise(uint32_t pclk, uint32_t freq) whal_Error whal_Stm32l1_I2c_Init(whal_I2c *i2cDev) { #ifdef WHAL_CFG_STM32L1_I2C_SINGLE_INSTANCE - size_t base = whal_Stm32l1_I2c_Dev.base; + uintptr_t base = whal_Stm32l1_I2c_Dev.base; (void)i2cDev; #else - size_t base; + uintptr_t base; if (!i2cDev || !i2cDev->cfg) return WHAL_EINVAL; @@ -332,10 +332,10 @@ whal_Error whal_Stm32l1_I2c_Init(whal_I2c *i2cDev) base = i2cDev->base; #endif - whal_Reg_Update(base, I2C_CR1, CR1_PE_Msk, 0); - whal_Reg_Update(base, I2C_CR1, CR1_SWRST_Msk, CR1_SWRST_Msk); - whal_Reg_Update(base, I2C_CR1, CR1_SWRST_Msk, 0); - whal_Reg_Update(base, I2C_CR1, CR1_PE_Msk, CR1_PE_Msk); + whal_Reg32_Update(base, I2C_CR1, CR1_PE_Msk, 0); + whal_Reg32_Update(base, I2C_CR1, CR1_SWRST_Msk, CR1_SWRST_Msk); + whal_Reg32_Update(base, I2C_CR1, CR1_SWRST_Msk, 0); + whal_Reg32_Update(base, I2C_CR1, CR1_PE_Msk, CR1_PE_Msk); return WHAL_SUCCESS; } @@ -343,10 +343,10 @@ whal_Error whal_Stm32l1_I2c_Init(whal_I2c *i2cDev) whal_Error whal_Stm32l1_I2c_Deinit(whal_I2c *i2cDev) { #ifdef WHAL_CFG_STM32L1_I2C_SINGLE_INSTANCE - size_t base = whal_Stm32l1_I2c_Dev.base; + uintptr_t base = whal_Stm32l1_I2c_Dev.base; (void)i2cDev; #else - size_t base; + uintptr_t base; if (!i2cDev || !i2cDev->cfg) return WHAL_EINVAL; @@ -354,7 +354,7 @@ whal_Error whal_Stm32l1_I2c_Deinit(whal_I2c *i2cDev) base = i2cDev->base; #endif - whal_Reg_Update(base, I2C_CR1, CR1_PE_Msk, 0); + whal_Reg32_Update(base, I2C_CR1, CR1_PE_Msk, 0); return WHAL_SUCCESS; } @@ -365,14 +365,14 @@ whal_Error whal_Stm32l1_I2c_StartCom(whal_I2c *i2cDev, whal_I2c_ComCfg *comCfg) #ifdef WHAL_CFG_STM32L1_I2C_SINGLE_INSTANCE whal_Stm32l1_I2c_Cfg *cfg = (whal_Stm32l1_I2c_Cfg *)whal_Stm32l1_I2c_Dev.cfg; - size_t base = whal_Stm32l1_I2c_Dev.base; + uintptr_t base = whal_Stm32l1_I2c_Dev.base; (void)i2cDev; if (!comCfg) return WHAL_EINVAL; #else whal_Stm32l1_I2c_Cfg *cfg; - size_t base; + uintptr_t base; if (!i2cDev || !i2cDev->cfg || !comCfg) return WHAL_EINVAL; @@ -392,23 +392,23 @@ whal_Error whal_Stm32l1_I2c_StartCom(whal_I2c *i2cDev, whal_I2c_ComCfg *comCfg) /* Let a pending STOP finish; a bus still busy after the timeout was left * by an abandoned transfer and only a software reset clears it */ - if (whal_Reg_ReadPoll(base, I2C_SR2, SR2_BUSY_Msk, 0, - cfg->timeout) != WHAL_SUCCESS) { - whal_Reg_Update(base, I2C_CR1, CR1_SWRST_Msk, CR1_SWRST_Msk); - whal_Reg_Update(base, I2C_CR1, CR1_SWRST_Msk, 0); + if (whal_Reg32_ReadPoll(base, I2C_SR2, SR2_BUSY_Msk, 0, + cfg->timeout) != WHAL_SUCCESS) { + whal_Reg32_Update(base, I2C_CR1, CR1_SWRST_Msk, CR1_SWRST_Msk); + whal_Reg32_Update(base, I2C_CR1, CR1_SWRST_Msk, 0); } - whal_Reg_Update(base, I2C_CR1, CR1_PE_Msk, 0); + whal_Reg32_Update(base, I2C_CR1, CR1_PE_Msk, 0); freqMhz = cfg->pclk / 1000000; - whal_Reg_Update(base, I2C_CR2, CR2_FREQ_Msk, - whal_SetBits(CR2_FREQ_Msk, CR2_FREQ_Pos, freqMhz)); + whal_Reg32_Update(base, I2C_CR2, CR2_FREQ_Msk, + whal_SetBits(CR2_FREQ_Msk, CR2_FREQ_Pos, freqMhz)); - whal_Reg_Write(base, I2C_CCR, Stm32l1_I2c_CalcCcr(cfg->pclk, comCfg->freq)); - whal_Reg_Write(base, I2C_TRISE, - Stm32l1_I2c_CalcTrise(cfg->pclk, comCfg->freq)); + whal_Reg32_Write(base, I2C_CCR, Stm32l1_I2c_CalcCcr(cfg->pclk, comCfg->freq)); + whal_Reg32_Write(base, I2C_TRISE, + Stm32l1_I2c_CalcTrise(cfg->pclk, comCfg->freq)); - whal_Reg_Update(base, I2C_CR1, CR1_PE_Msk, CR1_PE_Msk); + whal_Reg32_Update(base, I2C_CR1, CR1_PE_Msk, CR1_PE_Msk); cfg->_addr = comCfg->addr; cfg->_addrSz = comCfg->addrSz; @@ -443,14 +443,14 @@ whal_Error whal_Stm32l1_I2c_Transfer(whal_I2c *i2cDev, whal_I2c_Msg *msgs, #ifdef WHAL_CFG_STM32L1_I2C_SINGLE_INSTANCE whal_Stm32l1_I2c_Cfg *cfg = (whal_Stm32l1_I2c_Cfg *)whal_Stm32l1_I2c_Dev.cfg; - size_t base = whal_Stm32l1_I2c_Dev.base; + uintptr_t base = whal_Stm32l1_I2c_Dev.base; (void)i2cDev; if (!msgs || numMsgs == 0) return WHAL_EINVAL; #else whal_Stm32l1_I2c_Cfg *cfg; - size_t base; + uintptr_t base; if (!i2cDev || !i2cDev->cfg || !msgs || numMsgs == 0) return WHAL_EINVAL; @@ -495,9 +495,9 @@ whal_Error whal_Stm32l1_I2c_Transfer(whal_I2c *i2cDev, whal_I2c_Msg *msgs, return WHAL_SUCCESS; error: - whal_Reg_Update(base, I2C_CR1, CR1_ACK_Msk | CR1_POS_Msk, 0); + whal_Reg32_Update(base, I2C_CR1, CR1_ACK_Msk | CR1_POS_Msk, 0); if (err == WHAL_ETIMEOUT) - whal_Reg_Update(base, I2C_CR1, CR1_STOP_Msk, CR1_STOP_Msk); + whal_Reg32_Update(base, I2C_CR1, CR1_STOP_Msk, CR1_STOP_Msk); return err; } diff --git a/src/i2c/stm32wb_i2c.c b/src/i2c/stm32wb_i2c.c index f2a69f9d..e6f8143a 100644 --- a/src/i2c/stm32wb_i2c.c +++ b/src/i2c/stm32wb_i2c.c @@ -215,32 +215,32 @@ static uint32_t Stm32wb_I2c_CalcTimingr(uint32_t pclk, uint32_t freq) (scll << I2C_TIMINGR_SCLL_Pos); } -static whal_Error Stm32wb_I2c_CheckErrors(size_t base) +static whal_Error Stm32wb_I2c_CheckErrors(uintptr_t base) { - size_t isr = whal_Reg_Read(base, I2C_ISR_REG); + size_t isr = whal_Reg32_Read(base, I2C_ISR_REG); if (isr & I2C_ISR_NACKF_Msk) { - whal_Reg_Write(base, I2C_ICR_REG, I2C_ICR_NACKCF_Msk); + whal_Reg32_Write(base, I2C_ICR_REG, I2C_ICR_NACKCF_Msk); /* Generate STOP after NACK */ - whal_Reg_Update(base, I2C_CR2_REG, I2C_CR2_STOP_Msk, - whal_SetBits(I2C_CR2_STOP_Msk, I2C_CR2_STOP_Pos, 1)); + whal_Reg32_Update(base, I2C_CR2_REG, I2C_CR2_STOP_Msk, + whal_SetBits(I2C_CR2_STOP_Msk, I2C_CR2_STOP_Pos, 1)); return WHAL_EHARDWARE; } if (isr & I2C_ISR_BERR_Msk) { - whal_Reg_Write(base, I2C_ICR_REG, I2C_ICR_BERRCF_Msk); + whal_Reg32_Write(base, I2C_ICR_REG, I2C_ICR_BERRCF_Msk); return WHAL_EHARDWARE; } if (isr & I2C_ISR_ARLO_Msk) { - whal_Reg_Write(base, I2C_ICR_REG, I2C_ICR_ARLOCF_Msk); + whal_Reg32_Write(base, I2C_ICR_REG, I2C_ICR_ARLOCF_Msk); return WHAL_EHARDWARE; } return WHAL_SUCCESS; } -static whal_Error Stm32wb_I2c_WaitFlag(size_t base, size_t mask, size_t value, +static whal_Error Stm32wb_I2c_WaitFlag(uintptr_t base, size_t mask, size_t value, whal_Timeout *timeout) { whal_Error err; @@ -248,7 +248,7 @@ static whal_Error Stm32wb_I2c_WaitFlag(size_t base, size_t mask, size_t value, WHAL_TIMEOUT_START(timeout); while (1) { - size_t isr = whal_Reg_Read(base, I2C_ISR_REG); + size_t isr = whal_Reg32_Read(base, I2C_ISR_REG); if ((isr & mask) == value) return WHAL_SUCCESS; @@ -270,7 +270,7 @@ static whal_Error Stm32wb_I2c_WaitFlag(size_t base, size_t mask, size_t value, #define I2C_CR2_XFER_Msk (I2C_CR2_RD_WRN_Msk | I2C_CR2_NBYTES_Msk | \ I2C_CR2_START_Msk | I2C_CR2_RELOAD_Msk) -static whal_Error Stm32wb_I2c_TransferChunk(size_t base, uint8_t *buf, +static whal_Error Stm32wb_I2c_TransferChunk(uintptr_t base, uint8_t *buf, size_t nbytes, uint8_t isRead, uint8_t start, uint8_t reload, whal_Timeout *timeout) @@ -288,7 +288,7 @@ static whal_Error Stm32wb_I2c_TransferChunk(size_t base, uint8_t *buf, cr2 |= whal_SetBits(I2C_CR2_RELOAD_Msk, I2C_CR2_RELOAD_Pos, 1); /* Update only transfer control bits, preserving SADD + ADD10 from StartCom */ - whal_Reg_Update(base, I2C_CR2_REG, I2C_CR2_XFER_Msk, cr2); + whal_Reg32_Update(base, I2C_CR2_REG, I2C_CR2_XFER_Msk, cr2); for (size_t i = 0; i < nbytes; i++) { if (isRead) { @@ -298,16 +298,16 @@ static whal_Error Stm32wb_I2c_TransferChunk(size_t base, uint8_t *buf, return err; if (buf) - buf[i] = (uint8_t)whal_Reg_Read(base, I2C_RXDR_REG); + buf[i] = (uint8_t)whal_Reg32_Read(base, I2C_RXDR_REG); else - (void)whal_Reg_Read(base, I2C_RXDR_REG); + (void)whal_Reg32_Read(base, I2C_RXDR_REG); } else { err = Stm32wb_I2c_WaitFlag(base, I2C_ISR_TXIS_Msk, I2C_ISR_TXIS_Msk, timeout); if (err) return err; - whal_Reg_Write(base, I2C_TXDR_REG, buf ? buf[i] : 0xFF); + whal_Reg32_Write(base, I2C_TXDR_REG, buf ? buf[i] : 0xFF); } } @@ -345,7 +345,7 @@ static whal_Error Stm32wb_I2c_TransferChunk(size_t base, uint8_t *buf, * re-addressing. If false, use TC so the next message * can issue START for a direction change. */ -static whal_Error Stm32wb_I2c_TransferMsg(size_t base, whal_I2c_Msg *msg, +static whal_Error Stm32wb_I2c_TransferMsg(uintptr_t base, whal_I2c_Msg *msg, uint8_t reloadLast, whal_Timeout *timeout) { @@ -389,15 +389,15 @@ static whal_Error Stm32wb_I2c_TransferMsg(size_t base, whal_I2c_Msg *msg, } if (doStop) { - whal_Reg_Update(base, I2C_CR2_REG, I2C_CR2_STOP_Msk, - whal_SetBits(I2C_CR2_STOP_Msk, I2C_CR2_STOP_Pos, 1)); + whal_Reg32_Update(base, I2C_CR2_REG, I2C_CR2_STOP_Msk, + whal_SetBits(I2C_CR2_STOP_Msk, I2C_CR2_STOP_Pos, 1)); err = Stm32wb_I2c_WaitFlag(base, I2C_ISR_STOPF_Msk, I2C_ISR_STOPF_Msk, timeout); if (err) return err; - whal_Reg_Write(base, I2C_ICR_REG, I2C_ICR_STOPCF_Msk); + whal_Reg32_Write(base, I2C_ICR_REG, I2C_ICR_STOPCF_Msk); } return WHAL_SUCCESS; @@ -406,10 +406,10 @@ static whal_Error Stm32wb_I2c_TransferMsg(size_t base, whal_I2c_Msg *msg, whal_Error whal_Stm32wb_I2c_Init(whal_I2c *i2cDev) { #ifdef WHAL_CFG_STM32WB_I2C_SINGLE_INSTANCE - size_t base = whal_Stm32wb_I2c_Dev.base; + uintptr_t base = whal_Stm32wb_I2c_Dev.base; (void)i2cDev; #else - size_t base; + uintptr_t base; if (!i2cDev || !i2cDev->cfg) { return WHAL_EINVAL; @@ -419,18 +419,18 @@ whal_Error whal_Stm32wb_I2c_Init(whal_I2c *i2cDev) #endif /* Disable PE before configuring */ - whal_Reg_Update(base, I2C_CR1_REG, I2C_CR1_PE_Msk, - whal_SetBits(I2C_CR1_PE_Msk, I2C_CR1_PE_Pos, 0)); + whal_Reg32_Update(base, I2C_CR1_REG, I2C_CR1_PE_Msk, + whal_SetBits(I2C_CR1_PE_Msk, I2C_CR1_PE_Pos, 0)); /* Enable analog noise filter (ANFOFF=0), disable digital filter (DNF=0) */ - whal_Reg_Update(base, I2C_CR1_REG, - I2C_CR1_ANFOFF_Msk | I2C_CR1_DNF_Msk, - whal_SetBits(I2C_CR1_ANFOFF_Msk, I2C_CR1_ANFOFF_Pos, 0) | - whal_SetBits(I2C_CR1_DNF_Msk, I2C_CR1_DNF_Pos, 0)); + whal_Reg32_Update(base, I2C_CR1_REG, + I2C_CR1_ANFOFF_Msk | I2C_CR1_DNF_Msk, + whal_SetBits(I2C_CR1_ANFOFF_Msk, I2C_CR1_ANFOFF_Pos, 0) | + whal_SetBits(I2C_CR1_DNF_Msk, I2C_CR1_DNF_Pos, 0)); /* Enable peripheral */ - whal_Reg_Update(base, I2C_CR1_REG, I2C_CR1_PE_Msk, - whal_SetBits(I2C_CR1_PE_Msk, I2C_CR1_PE_Pos, 1)); + whal_Reg32_Update(base, I2C_CR1_REG, I2C_CR1_PE_Msk, + whal_SetBits(I2C_CR1_PE_Msk, I2C_CR1_PE_Pos, 1)); return WHAL_SUCCESS; } @@ -438,10 +438,10 @@ whal_Error whal_Stm32wb_I2c_Init(whal_I2c *i2cDev) whal_Error whal_Stm32wb_I2c_Deinit(whal_I2c *i2cDev) { #ifdef WHAL_CFG_STM32WB_I2C_SINGLE_INSTANCE - size_t base = whal_Stm32wb_I2c_Dev.base; + uintptr_t base = whal_Stm32wb_I2c_Dev.base; (void)i2cDev; #else - size_t base; + uintptr_t base; if (!i2cDev || !i2cDev->cfg) { return WHAL_EINVAL; @@ -451,8 +451,8 @@ whal_Error whal_Stm32wb_I2c_Deinit(whal_I2c *i2cDev) #endif /* Disable peripheral */ - whal_Reg_Update(base, I2C_CR1_REG, I2C_CR1_PE_Msk, - whal_SetBits(I2C_CR1_PE_Msk, I2C_CR1_PE_Pos, 0)); + whal_Reg32_Update(base, I2C_CR1_REG, I2C_CR1_PE_Msk, + whal_SetBits(I2C_CR1_PE_Msk, I2C_CR1_PE_Pos, 0)); return WHAL_SUCCESS; } @@ -463,14 +463,14 @@ whal_Error whal_Stm32wb_I2c_StartCom(whal_I2c *i2cDev, whal_I2c_ComCfg *comCfg) #ifdef WHAL_CFG_STM32WB_I2C_SINGLE_INSTANCE whal_Stm32wb_I2c_Cfg *cfg = (whal_Stm32wb_I2c_Cfg *)whal_Stm32wb_I2c_Dev.cfg; - size_t base = whal_Stm32wb_I2c_Dev.base; + uintptr_t base = whal_Stm32wb_I2c_Dev.base; (void)i2cDev; if (!comCfg) { return WHAL_EINVAL; } #else - size_t base; + uintptr_t base; whal_Stm32wb_I2c_Cfg *cfg; if (!i2cDev || !i2cDev->cfg || !comCfg) { @@ -498,16 +498,16 @@ whal_Error whal_Stm32wb_I2c_StartCom(whal_I2c *i2cDev, whal_I2c_ComCfg *comCfg) } /* Disable PE to configure timing */ - whal_Reg_Update(base, I2C_CR1_REG, I2C_CR1_PE_Msk, - whal_SetBits(I2C_CR1_PE_Msk, I2C_CR1_PE_Pos, 0)); + whal_Reg32_Update(base, I2C_CR1_REG, I2C_CR1_PE_Msk, + whal_SetBits(I2C_CR1_PE_Msk, I2C_CR1_PE_Pos, 0)); /* Compute and write timing register */ - whal_Reg_Write(base, I2C_TIMINGR_REG, - Stm32wb_I2c_CalcTimingr(cfg->pclk, comCfg->freq)); + whal_Reg32_Write(base, I2C_TIMINGR_REG, + Stm32wb_I2c_CalcTimingr(cfg->pclk, comCfg->freq)); /* Re-enable PE */ - whal_Reg_Update(base, I2C_CR1_REG, I2C_CR1_PE_Msk, - whal_SetBits(I2C_CR1_PE_Msk, I2C_CR1_PE_Pos, 1)); + whal_Reg32_Update(base, I2C_CR1_REG, I2C_CR1_PE_Msk, + whal_SetBits(I2C_CR1_PE_Msk, I2C_CR1_PE_Pos, 1)); /* Configure target address and addressing mode in CR2 */ if (comCfg->addrSz == 10) { @@ -519,8 +519,8 @@ whal_Error whal_Stm32wb_I2c_StartCom(whal_I2c *i2cDev, whal_I2c_ComCfg *comCfg) (uint32_t)comCfg->addr << 1); } - whal_Reg_Update(base, I2C_CR2_REG, - I2C_CR2_SADD_Msk | I2C_CR2_ADD10_Msk, cr2); + whal_Reg32_Update(base, I2C_CR2_REG, + I2C_CR2_SADD_Msk | I2C_CR2_ADD10_Msk, cr2); return WHAL_SUCCESS; } @@ -528,10 +528,10 @@ whal_Error whal_Stm32wb_I2c_StartCom(whal_I2c *i2cDev, whal_I2c_ComCfg *comCfg) whal_Error whal_Stm32wb_I2c_EndCom(whal_I2c *i2cDev) { #ifdef WHAL_CFG_STM32WB_I2C_SINGLE_INSTANCE - size_t base = whal_Stm32wb_I2c_Dev.base; + uintptr_t base = whal_Stm32wb_I2c_Dev.base; (void)i2cDev; #else - size_t base; + uintptr_t base; if (!i2cDev || !i2cDev->cfg) { return WHAL_EINVAL; @@ -541,8 +541,8 @@ whal_Error whal_Stm32wb_I2c_EndCom(whal_I2c *i2cDev) #endif /* Clear target address and addressing mode */ - whal_Reg_Update(base, I2C_CR2_REG, - I2C_CR2_SADD_Msk | I2C_CR2_ADD10_Msk, 0); + whal_Reg32_Update(base, I2C_CR2_REG, + I2C_CR2_SADD_Msk | I2C_CR2_ADD10_Msk, 0); return WHAL_SUCCESS; } @@ -554,14 +554,14 @@ whal_Error whal_Stm32wb_I2c_Transfer(whal_I2c *i2cDev, whal_I2c_Msg *msgs, #ifdef WHAL_CFG_STM32WB_I2C_SINGLE_INSTANCE whal_Stm32wb_I2c_Cfg *cfg = (whal_Stm32wb_I2c_Cfg *)whal_Stm32wb_I2c_Dev.cfg; - size_t base = whal_Stm32wb_I2c_Dev.base; + uintptr_t base = whal_Stm32wb_I2c_Dev.base; (void)i2cDev; if (!msgs || numMsgs == 0) { return WHAL_EINVAL; } #else - size_t base; + uintptr_t base; whal_Stm32wb_I2c_Cfg *cfg; if (!i2cDev || !i2cDev->cfg || !msgs || numMsgs == 0) { diff --git a/src/irq/cortex_m4_nvic.c b/src/irq/cortex_m4_nvic.c index 28ce145c..d621a554 100644 --- a/src/irq/cortex_m4_nvic.c +++ b/src/irq/cortex_m4_nvic.c @@ -60,7 +60,7 @@ whal_Error whal_Nvic_Deinit(whal_Irq *irqDev) whal_Error whal_Nvic_Enable(whal_Irq *irqDev, size_t irq, const void *irqCfg) { - size_t base = whal_Nvic_Dev.base; + uintptr_t base = whal_Nvic_Dev.base; (void)irqDev; /* Set priority if config provided */ @@ -68,22 +68,22 @@ whal_Error whal_Nvic_Enable(whal_Irq *irqDev, size_t irq, const whal_Nvic_Cfg *cfg = (const whal_Nvic_Cfg *)irqCfg; size_t shift = NVIC_IPR_SHIFT(irq); size_t mask = (0xFFUL << shift); - whal_Reg_Update(base, NVIC_IPR_REG(irq), mask, - (size_t)(cfg->priority << 4) << shift); + whal_Reg32_Update(base, NVIC_IPR_REG(irq), mask, + (size_t)(cfg->priority << 4) << shift); } /* Enable the interrupt */ - whal_Reg_Write(base, NVIC_ISER_REG(irq), (1UL << (irq & 0x1F))); + whal_Reg32_Write(base, NVIC_ISER_REG(irq), (1UL << (irq & 0x1F))); return WHAL_SUCCESS; } whal_Error whal_Nvic_Disable(whal_Irq *irqDev, size_t irq) { - size_t base = whal_Nvic_Dev.base; + uintptr_t base = whal_Nvic_Dev.base; (void)irqDev; - whal_Reg_Write(base, NVIC_ICER_REG(irq), (1UL << (irq & 0x1F))); + whal_Reg32_Write(base, NVIC_ICER_REG(irq), (1UL << (irq & 0x1F))); return WHAL_SUCCESS; } diff --git a/src/pwm/stm32wb_lptim_pwm.c b/src/pwm/stm32wb_lptim_pwm.c index 3fa4a465..9e3f8aaa 100644 --- a/src/pwm/stm32wb_lptim_pwm.c +++ b/src/pwm/stm32wb_lptim_pwm.c @@ -56,7 +56,7 @@ whal_Error whal_Stm32wb_Lptim_Pwm_Init(whal_Pwm *dev) { - size_t base; + uintptr_t base; whal_Stm32wb_Lptim_Pwm_Cfg *cfg; uint32_t cfgr; @@ -72,12 +72,12 @@ whal_Error whal_Stm32wb_Lptim_Pwm_Init(whal_Pwm *dev) } /* CFGR is writable only while disabled: set clock source, prescaler, and PWM waveform here. */ - whal_Reg_Write(base, LPTIM_CR_REG, 0); + whal_Reg32_Write(base, LPTIM_CR_REG, 0); cfgr = whal_SetBits(LPTIM_CFGR_PRESC_Msk, LPTIM_CFGR_PRESC_Pos, cfg->prescaler) | whal_SetBits(LPTIM_CFGR_CKSEL_Msk, LPTIM_CFGR_CKSEL_Pos, cfg->clkSel); - whal_Reg_Write(base, LPTIM_CFGR_REG, cfgr); + whal_Reg32_Write(base, LPTIM_CFGR_REG, cfgr); return WHAL_SUCCESS; } @@ -89,8 +89,8 @@ whal_Error whal_Stm32wb_Lptim_Pwm_Deinit(whal_Pwm *dev) } /* Disable the timer and clear its configuration; the board owns clock gating. */ - whal_Reg_Write(dev->base, LPTIM_CR_REG, 0); - whal_Reg_Write(dev->base, LPTIM_CFGR_REG, 0); + whal_Reg32_Write(dev->base, LPTIM_CR_REG, 0); + whal_Reg32_Write(dev->base, LPTIM_CFGR_REG, 0); return WHAL_SUCCESS; } @@ -98,7 +98,7 @@ whal_Error whal_Stm32wb_Lptim_Pwm_Deinit(whal_Pwm *dev) whal_Error whal_Stm32wb_Lptim_Pwm_Start(whal_Pwm *dev, uint8_t channel, const whal_Pwm_ChannelCfg *channelCfg) { - size_t base; + uintptr_t base; whal_Stm32wb_Lptim_Pwm_Cfg *cfg; uint32_t arr, cmp; whal_Error err; @@ -135,36 +135,36 @@ whal_Error whal_Stm32wb_Lptim_Pwm_Start(whal_Pwm *dev, uint8_t channel, cmp = arr - channelCfg->pulseCycles; /* Disable so CFGR/ARR/CMP are writable, then set this call's polarity via WAVPOL. */ - whal_Reg_Write(base, LPTIM_CR_REG, 0); - whal_Reg_Update(base, LPTIM_CFGR_REG, LPTIM_CFGR_WAVPOL_Msk, - channelCfg->polarity != WHAL_PWM_POLARITY_NORMAL ? + whal_Reg32_Write(base, LPTIM_CR_REG, 0); + whal_Reg32_Update(base, LPTIM_CFGR_REG, LPTIM_CFGR_WAVPOL_Msk, + channelCfg->polarity != WHAL_PWM_POLARITY_NORMAL ? LPTIM_CFGR_WAVPOL_Msk : 0); /* ARR/CMP are writable only once enabled; clear stale ARROK/CMPOK before writing. */ - whal_Reg_Update(base, LPTIM_CR_REG, LPTIM_CR_ENABLE_Msk, - LPTIM_CR_ENABLE_Msk); - whal_Reg_Write(base, LPTIM_ICR_REG, - LPTIM_ICR_ARROKCF_Msk | LPTIM_ICR_CMPOKCF_Msk); - - whal_Reg_Write(base, LPTIM_ARR_REG, arr); - err = whal_Reg_ReadPoll(base, LPTIM_ISR_REG, LPTIM_ISR_ARROK_Msk, - LPTIM_ISR_ARROK_Msk, cfg->timeout); + whal_Reg32_Update(base, LPTIM_CR_REG, LPTIM_CR_ENABLE_Msk, + LPTIM_CR_ENABLE_Msk); + whal_Reg32_Write(base, LPTIM_ICR_REG, + LPTIM_ICR_ARROKCF_Msk | LPTIM_ICR_CMPOKCF_Msk); + + whal_Reg32_Write(base, LPTIM_ARR_REG, arr); + err = whal_Reg32_ReadPoll(base, LPTIM_ISR_REG, LPTIM_ISR_ARROK_Msk, + LPTIM_ISR_ARROK_Msk, cfg->timeout); if (err != WHAL_SUCCESS) { - whal_Reg_Write(base, LPTIM_CR_REG, 0); + whal_Reg32_Write(base, LPTIM_CR_REG, 0); return err; } - whal_Reg_Write(base, LPTIM_CMP_REG, cmp); - err = whal_Reg_ReadPoll(base, LPTIM_ISR_REG, LPTIM_ISR_CMPOK_Msk, - LPTIM_ISR_CMPOK_Msk, cfg->timeout); + whal_Reg32_Write(base, LPTIM_CMP_REG, cmp); + err = whal_Reg32_ReadPoll(base, LPTIM_ISR_REG, LPTIM_ISR_CMPOK_Msk, + LPTIM_ISR_CMPOK_Msk, cfg->timeout); if (err != WHAL_SUCCESS) { - whal_Reg_Write(base, LPTIM_CR_REG, 0); + whal_Reg32_Write(base, LPTIM_CR_REG, 0); return err; } /* Waveform programmed; begin continuous counting. */ - whal_Reg_Update(base, LPTIM_CR_REG, LPTIM_CR_CNTSTRT_Msk, - LPTIM_CR_CNTSTRT_Msk); + whal_Reg32_Update(base, LPTIM_CR_REG, LPTIM_CR_CNTSTRT_Msk, + LPTIM_CR_CNTSTRT_Msk); return WHAL_SUCCESS; } @@ -179,7 +179,7 @@ whal_Error whal_Stm32wb_Lptim_Pwm_Stop(whal_Pwm *dev, uint8_t channel) } /* Clearing ENABLE stops the counter and parks the output; Start resumes. */ - whal_Reg_Update(dev->base, LPTIM_CR_REG, LPTIM_CR_ENABLE_Msk, 0); + whal_Reg32_Update(dev->base, LPTIM_CR_REG, LPTIM_CR_ENABLE_Msk, 0); return WHAL_SUCCESS; } diff --git a/src/reg.c b/src/reg.c index 994d502f..c104e702 100644 --- a/src/reg.c +++ b/src/reg.c @@ -54,16 +54,3 @@ whal_Error whal_Reg64_ReadPoll(uintptr_t base, uint32_t offset, return WHAL_SUCCESS; } #endif /* WHAL_HAVE_REG64 */ - -#ifdef WHAL_CFG_REG_LEGACY -whal_Error whal_Reg_ReadPoll(size_t base, size_t offset, - size_t mask, size_t value, - whal_Timeout *timeout) -{ - if (!WHAL_REG_FITS32(mask) || !WHAL_REG_FITS32(value)) { - return WHAL_EINVAL; - } - return whal_Reg32_ReadPoll(base + offset, 0, mask & 0xFFFFFFFFu, - value & 0xFFFFFFFFu, timeout); -} -#endif /* WHAL_CFG_REG_LEGACY */ diff --git a/src/rng/stm32h5_rng.c b/src/rng/stm32h5_rng.c index 73702ac2..1ead7c74 100644 --- a/src/rng/stm32h5_rng.c +++ b/src/rng/stm32h5_rng.c @@ -80,7 +80,7 @@ whal_Error whal_Stm32h5_Rng_Init(whal_Rng *rngDev) { const whal_Stm32h5_Rng_Cfg *cfg = (const whal_Stm32h5_Rng_Cfg *)whal_Stm32h5_Rng_Dev.cfg; - size_t base = whal_Stm32h5_Rng_Dev.base; + uintptr_t base = whal_Stm32h5_Rng_Dev.base; whal_Error err; (void)rngDev; @@ -91,19 +91,19 @@ whal_Error whal_Stm32h5_Rng_Init(whal_Rng *rngDev) * 3. Write NSCR value (while CONDRST=1) * 4. Write CONDRST=0 with RNGEN=1 to start */ - whal_Reg_Write(base, RNG_CR_REG, - cfg->cr | RNG_CR_CONDRST_Msk); + whal_Reg32_Write(base, RNG_CR_REG, + cfg->cr | RNG_CR_CONDRST_Msk); - whal_Reg_Write(base, RNG_HTCR_REG, RNG_HTCR_MAGIC); - whal_Reg_Write(base, RNG_HTCR_REG, cfg->htcr); - whal_Reg_Write(base, RNG_NSCR_REG, cfg->nscr); + whal_Reg32_Write(base, RNG_HTCR_REG, RNG_HTCR_MAGIC); + whal_Reg32_Write(base, RNG_HTCR_REG, cfg->htcr); + whal_Reg32_Write(base, RNG_NSCR_REG, cfg->nscr); - whal_Reg_Write(base, RNG_CR_REG, - cfg->cr | RNG_CR_RNGEN_Msk); + whal_Reg32_Write(base, RNG_CR_REG, + cfg->cr | RNG_CR_RNGEN_Msk); /* Wait for CONDRST to clear (reset complete) */ - err = whal_Reg_ReadPoll(base, RNG_CR_REG, - RNG_CR_CONDRST_Msk, 0, cfg->timeout); + err = whal_Reg32_ReadPoll(base, RNG_CR_REG, + RNG_CR_CONDRST_Msk, 0, cfg->timeout); return err; } @@ -112,8 +112,8 @@ whal_Error whal_Stm32h5_Rng_Deinit(whal_Rng *rngDev) { (void)rngDev; /* Disable the RNG peripheral */ - whal_Reg_Update(whal_Stm32h5_Rng_Dev.base, RNG_CR_REG, RNG_CR_RNGEN_Msk, - whal_SetBits(RNG_CR_RNGEN_Msk, RNG_CR_RNGEN_Pos, 0)); + whal_Reg32_Update(whal_Stm32h5_Rng_Dev.base, RNG_CR_REG, RNG_CR_RNGEN_Msk, + whal_SetBits(RNG_CR_RNGEN_Msk, RNG_CR_RNGEN_Pos, 0)); return WHAL_SUCCESS; } @@ -125,7 +125,7 @@ whal_Error whal_Stm32h5_Rng_Generate(whal_Rng *rngDev, void *rngData, whal_Error err = WHAL_SUCCESS; const whal_Stm32h5_Rng_Cfg *cfg = (const whal_Stm32h5_Rng_Cfg *)whal_Stm32h5_Rng_Dev.cfg; - size_t base = whal_Stm32h5_Rng_Dev.base; + uintptr_t base = whal_Stm32h5_Rng_Dev.base; size_t sr; size_t offset = 0; (void)rngDev; @@ -145,12 +145,12 @@ whal_Error whal_Stm32h5_Rng_Generate(whal_Rng *rngDev, void *rngData, goto exit; } - sr = whal_Reg_Read(base, RNG_SR_REG); + sr = whal_Reg32_Read(base, RNG_SR_REG); /* With auto-reset enabled SECS clears on its own; SEIS latches * the error so the value around it is never returned */ if (sr & (RNG_SR_SECS_Msk | RNG_SR_SEIS_Msk)) { - whal_Reg_Update(base, RNG_SR_REG, RNG_SR_SEIS_Msk, 0); + whal_Reg32_Update(base, RNG_SR_REG, RNG_SR_SEIS_Msk, 0); err = WHAL_EHARDWARE; goto exit; } @@ -164,7 +164,7 @@ whal_Error whal_Stm32h5_Rng_Generate(whal_Rng *rngDev, void *rngData, } /* Read 32-bit random value */ - uint32_t rnd = (uint32_t)whal_Reg_Read(base, RNG_DR_REG); + uint32_t rnd = (uint32_t)whal_Reg32_Read(base, RNG_DR_REG); /* Copy bytes into output buffer */ for (size_t i = 0; i < 4 && offset < rngDataSz; i++, offset++) diff --git a/src/rng/stm32wb0_rng.c b/src/rng/stm32wb0_rng.c index e5ddc26a..5c663a0a 100644 --- a/src/rng/stm32wb0_rng.c +++ b/src/rng/stm32wb0_rng.c @@ -62,27 +62,27 @@ const whal_Rng whal_Stm32wb0_Rng_Dev = WHAL_CFG_STM32WB0_RNG_DEV; whal_Error whal_Stm32wb0_Rng_Init(whal_Rng *rngDev) { - size_t base = whal_Stm32wb0_Rng_Dev.base; + uintptr_t base = whal_Stm32wb0_Rng_Dev.base; (void)rngDev; /* Full CR write: clears RNG_DIS to enable the oscillators and wipes * any stale state the bootROM may have left in reserved bits. * Matches ST's HAL/LL pattern. The TST_CLK / REVCLK probe is the * optional clock-error detection feature, not a required init step. */ - whal_Reg_Write(base, RNG_CR_REG, 0); + whal_Reg32_Write(base, RNG_CR_REG, 0); return WHAL_SUCCESS; } whal_Error whal_Stm32wb0_Rng_Deinit(whal_Rng *rngDev) { - size_t base = whal_Stm32wb0_Rng_Dev.base; + uintptr_t base = whal_Stm32wb0_Rng_Dev.base; (void)rngDev; /* Disable: set RNG_DIS to power down the internal free-running * oscillators. */ - whal_Reg_Update(base, RNG_CR_REG, RNG_CR_RNG_DIS_Msk, - whal_SetBits(RNG_CR_RNG_DIS_Msk, RNG_CR_RNG_DIS_Pos, 1)); + whal_Reg32_Update(base, RNG_CR_REG, RNG_CR_RNG_DIS_Msk, + whal_SetBits(RNG_CR_RNG_DIS_Msk, RNG_CR_RNG_DIS_Pos, 1)); return WHAL_SUCCESS; } @@ -90,7 +90,7 @@ whal_Error whal_Stm32wb0_Rng_Generate(whal_Rng *rngDev, void *rngData, size_t rngDataSz) { uint8_t *rngBuf = (uint8_t *)rngData; - size_t base = whal_Stm32wb0_Rng_Dev.base; + uintptr_t base = whal_Stm32wb0_Rng_Dev.base; size_t offset = 0; (void)rngDev; @@ -100,7 +100,7 @@ whal_Error whal_Stm32wb0_Rng_Generate(whal_Rng *rngDev, void *rngData, while (offset < rngDataSz) { /* 32-bit-only read, low half is the random value. */ - uint32_t word = whal_Reg_Read(base, RNG_VAL_REG); + uint32_t word = whal_Reg32_Read(base, RNG_VAL_REG); uint16_t rnd = (uint16_t)(word & RNG_VAL_Msk); for (size_t i = 0; i < 2 && offset < rngDataSz; i++, offset++) { @@ -109,8 +109,8 @@ whal_Error whal_Stm32wb0_Rng_Generate(whal_Rng *rngDev, void *rngData, } /* FAULT latches a bad bit sequence from the noise source; write 1 to clear */ - if (whal_Reg_Read(base, RNG_SR_REG) & RNG_SR_FAULT_Msk) { - whal_Reg_Write(base, RNG_SR_REG, RNG_SR_FAULT_Msk); + if (whal_Reg32_Read(base, RNG_SR_REG) & RNG_SR_FAULT_Msk) { + whal_Reg32_Write(base, RNG_SR_REG, RNG_SR_FAULT_Msk); return WHAL_EHARDWARE; } diff --git a/src/rng/stm32wb_rng.c b/src/rng/stm32wb_rng.c index c404459e..3f6526b9 100644 --- a/src/rng/stm32wb_rng.c +++ b/src/rng/stm32wb_rng.c @@ -89,7 +89,7 @@ whal_Error whal_Stm32wb_Rng_Generate(whal_Rng *rngDev, void *rngData, size_t rng whal_Error err = WHAL_SUCCESS; const whal_Stm32wb_Rng_Cfg *cfg = (const whal_Stm32wb_Rng_Cfg *)whal_Stm32wb_Rng_Dev.cfg; - size_t base = whal_Stm32wb_Rng_Dev.base; + uintptr_t base = whal_Stm32wb_Rng_Dev.base; size_t sr; size_t offset = 0; (void)rngDev; @@ -102,8 +102,8 @@ whal_Error whal_Stm32wb_Rng_Generate(whal_Rng *rngDev, void *rngData, size_t rng #endif /* Enable the RNG peripheral */ - whal_Reg_Update(base, RNG_CR_REG, RNG_CR_RNGEN_Msk, - whal_SetBits(RNG_CR_RNGEN_Msk, RNG_CR_RNGEN_Pos, 1)); + whal_Reg32_Update(base, RNG_CR_REG, RNG_CR_RNGEN_Msk, + whal_SetBits(RNG_CR_RNGEN_Msk, RNG_CR_RNGEN_Pos, 1)); while (offset < rngDataSz) { /* Wait for a random value to be ready */ @@ -114,7 +114,7 @@ whal_Error whal_Stm32wb_Rng_Generate(whal_Rng *rngDev, void *rngData, size_t rng goto exit; } - sr = whal_Reg_Read(base, RNG_SR_REG); + sr = whal_Reg32_Read(base, RNG_SR_REG); /* Check for seed or clock error */ if (sr & (RNG_SR_SECS_Msk | RNG_SR_SEIS_Msk)) { @@ -142,14 +142,14 @@ whal_Error whal_Stm32wb_Rng_Generate(whal_Rng *rngDev, void *rngData, size_t rng seed_error: /* Seed error recovery (RM0434 21.3.7): clear SEIS, then discard 12 words */ - whal_Reg_Update(base, RNG_SR_REG, RNG_SR_SEIS_Msk, 0); + whal_Reg32_Update(base, RNG_SR_REG, RNG_SR_SEIS_Msk, 0); for (size_t i = 0; i < 12; i++) - (void)whal_Reg_Read(base, RNG_DR_REG); + (void)whal_Reg32_Read(base, RNG_DR_REG); exit: /* Disable the RNG peripheral */ - whal_Reg_Update(base, RNG_CR_REG, RNG_CR_RNGEN_Msk, - whal_SetBits(RNG_CR_RNGEN_Msk, RNG_CR_RNGEN_Pos, 0)); + whal_Reg32_Update(base, RNG_CR_REG, RNG_CR_RNGEN_Msk, + whal_SetBits(RNG_CR_RNGEN_Msk, RNG_CR_RNGEN_Pos, 0)); return err; } diff --git a/src/rng/stm32wba_rng.c b/src/rng/stm32wba_rng.c index be84bfe4..49652d97 100644 --- a/src/rng/stm32wba_rng.c +++ b/src/rng/stm32wba_rng.c @@ -93,25 +93,25 @@ whal_Error whal_Stm32wba_Rng_Init(whal_Rng *rngDev) { const whal_Stm32wba_Rng_Cfg *cfg = (const whal_Stm32wba_Rng_Cfg *)whal_Stm32wba_Rng_Dev.cfg; - size_t base = whal_Stm32wba_Rng_Dev.base; + uintptr_t base = whal_Stm32wba_Rng_Dev.base; (void)rngDev; /* Apply the configuration with CONDRST=1 and RNGEN=1 */ - whal_Reg_Write(base, RNG_CR_REG, - RNG_CR_CONDRST_Msk | cfg->cr | RNG_CR_RNGEN_Msk); + whal_Reg32_Write(base, RNG_CR_REG, + RNG_CR_CONDRST_Msk | cfg->cr | RNG_CR_RNGEN_Msk); /* HTCR and NSCR only take effect while CONDRST is set */ - whal_Reg_Write(base, RNG_HTCR_REG, RNG_HTCR_MAGIC); - whal_Reg_Write(base, RNG_HTCR_REG, cfg->htcr); - whal_Reg_Write(base, RNG_NSCR_REG, cfg->nscr); + whal_Reg32_Write(base, RNG_HTCR_REG, RNG_HTCR_MAGIC); + whal_Reg32_Write(base, RNG_HTCR_REG, cfg->htcr); + whal_Reg32_Write(base, RNG_NSCR_REG, cfg->nscr); /* Clear CONDRST to start conditioning */ - whal_Reg_Write(base, RNG_CR_REG, - cfg->cr | RNG_CR_RNGEN_Msk); + whal_Reg32_Write(base, RNG_CR_REG, + cfg->cr | RNG_CR_RNGEN_Msk); /* Wait for CONDRST to self-clear */ - return whal_Reg_ReadPoll(base, RNG_CR_REG, RNG_CR_CONDRST_Msk, 0, - cfg->timeout); + return whal_Reg32_ReadPoll(base, RNG_CR_REG, RNG_CR_CONDRST_Msk, 0, + cfg->timeout); } whal_Error whal_Stm32wba_Rng_Deinit(whal_Rng *rngDev) @@ -119,7 +119,7 @@ whal_Error whal_Stm32wba_Rng_Deinit(whal_Rng *rngDev) (void)rngDev; /* Disable RNG */ - whal_Reg_Update(whal_Stm32wba_Rng_Dev.base, RNG_CR_REG, RNG_CR_RNGEN_Msk, 0); + whal_Reg32_Update(whal_Stm32wba_Rng_Dev.base, RNG_CR_REG, RNG_CR_RNGEN_Msk, 0); return WHAL_SUCCESS; } @@ -130,7 +130,7 @@ whal_Error whal_Stm32wba_Rng_Generate(whal_Rng *rngDev, void *rngData, size_t rn whal_Error err = WHAL_SUCCESS; const whal_Stm32wba_Rng_Cfg *cfg = (const whal_Stm32wba_Rng_Cfg *)whal_Stm32wba_Rng_Dev.cfg; - size_t base = whal_Stm32wba_Rng_Dev.base; + uintptr_t base = whal_Stm32wba_Rng_Dev.base; size_t sr; size_t offset = 0; (void)rngDev; @@ -149,12 +149,12 @@ whal_Error whal_Stm32wba_Rng_Generate(whal_Rng *rngDev, void *rngData, size_t rn goto exit; } - sr = whal_Reg_Read(base, RNG_SR_REG); + sr = whal_Reg32_Read(base, RNG_SR_REG); /* With auto-reset enabled SECS clears on its own; SEIS latches * the error so the value around it is never returned */ if (sr & (RNG_SR_SECS_Msk | RNG_SR_SEIS_Msk)) { - whal_Reg_Update(base, RNG_SR_REG, RNG_SR_SEIS_Msk, 0); + whal_Reg32_Update(base, RNG_SR_REG, RNG_SR_SEIS_Msk, 0); err = WHAL_EHARDWARE; goto exit; } diff --git a/src/spi/stm32f4_spi.c b/src/spi/stm32f4_spi.c index 00e4ae0b..5ce4bd9b 100644 --- a/src/spi/stm32f4_spi.c +++ b/src/spi/stm32f4_spi.c @@ -115,10 +115,10 @@ static uint32_t whal_Stm32f4_Spi_CalcBr(size_t pclk, uint32_t targetBaud) whal_Error whal_Stm32f4_Spi_Init(whal_Spi *spiDev) { #ifdef WHAL_CFG_STM32F4_SPI_SINGLE_INSTANCE - size_t base = whal_Stm32f4_Spi_Dev.base; + uintptr_t base = whal_Stm32f4_Spi_Dev.base; (void)spiDev; #else - size_t base; + uintptr_t base; if (!spiDev || !spiDev->cfg) return WHAL_EINVAL; @@ -127,11 +127,11 @@ whal_Error whal_Stm32f4_Spi_Init(whal_Spi *spiDev) #endif /* Master mode with software slave management */ - whal_Reg_Update(base, SPI_CR1_REG, - SPI_CR1_MSTR_Msk | SPI_CR1_SSM_Msk | SPI_CR1_SSI_Msk, - whal_SetBits(SPI_CR1_MSTR_Msk, SPI_CR1_MSTR_Pos, 1) | - whal_SetBits(SPI_CR1_SSM_Msk, SPI_CR1_SSM_Pos, 1) | - whal_SetBits(SPI_CR1_SSI_Msk, SPI_CR1_SSI_Pos, 1)); + whal_Reg32_Update(base, SPI_CR1_REG, + SPI_CR1_MSTR_Msk | SPI_CR1_SSM_Msk | SPI_CR1_SSI_Msk, + whal_SetBits(SPI_CR1_MSTR_Msk, SPI_CR1_MSTR_Pos, 1) | + whal_SetBits(SPI_CR1_SSM_Msk, SPI_CR1_SSM_Pos, 1) | + whal_SetBits(SPI_CR1_SSI_Msk, SPI_CR1_SSI_Pos, 1)); return WHAL_SUCCESS; } @@ -139,10 +139,10 @@ whal_Error whal_Stm32f4_Spi_Init(whal_Spi *spiDev) whal_Error whal_Stm32f4_Spi_Deinit(whal_Spi *spiDev) { #ifdef WHAL_CFG_STM32F4_SPI_SINGLE_INSTANCE - size_t base = whal_Stm32f4_Spi_Dev.base; + uintptr_t base = whal_Stm32f4_Spi_Dev.base; (void)spiDev; #else - size_t base; + uintptr_t base; if (!spiDev || !spiDev->cfg) return WHAL_EINVAL; @@ -151,8 +151,8 @@ whal_Error whal_Stm32f4_Spi_Deinit(whal_Spi *spiDev) #endif /* Disable SPI */ - whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, - whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 0)); + whal_Reg32_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, + whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 0)); return WHAL_SUCCESS; } @@ -163,13 +163,13 @@ whal_Error whal_Stm32f4_Spi_StartCom(whal_Spi *spiDev, whal_Spi_ComCfg *comCfg) #ifdef WHAL_CFG_STM32F4_SPI_SINGLE_INSTANCE whal_Stm32f4_Spi_Cfg *cfg = (whal_Stm32f4_Spi_Cfg *)whal_Stm32f4_Spi_Dev.cfg; - size_t base = whal_Stm32f4_Spi_Dev.base; + uintptr_t base = whal_Stm32f4_Spi_Dev.base; (void)spiDev; if (!comCfg) return WHAL_EINVAL; #else - size_t base; + uintptr_t base; whal_Stm32f4_Spi_Cfg *cfg; if (!spiDev || !spiDev->cfg || !comCfg) @@ -194,19 +194,19 @@ whal_Error whal_Stm32f4_Spi_StartCom(whal_Spi *spiDev, whal_Spi_ComCfg *comCfg) cpha = comCfg->mode & 1; /* Disable SPE before reconfiguring */ - whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, - whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 0)); + whal_Reg32_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, + whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 0)); /* Set mode and baud rate (DFF=0 for 8-bit) */ - whal_Reg_Update(base, SPI_CR1_REG, - SPI_CR1_CPOL_Msk | SPI_CR1_CPHA_Msk | SPI_CR1_BR_Msk | SPI_CR1_DFF_Msk, - whal_SetBits(SPI_CR1_CPOL_Msk, SPI_CR1_CPOL_Pos, cpol) | - whal_SetBits(SPI_CR1_CPHA_Msk, SPI_CR1_CPHA_Pos, cpha) | - whal_SetBits(SPI_CR1_BR_Msk, SPI_CR1_BR_Pos, br)); + whal_Reg32_Update(base, SPI_CR1_REG, + SPI_CR1_CPOL_Msk | SPI_CR1_CPHA_Msk | SPI_CR1_BR_Msk | SPI_CR1_DFF_Msk, + whal_SetBits(SPI_CR1_CPOL_Msk, SPI_CR1_CPOL_Pos, cpol) | + whal_SetBits(SPI_CR1_CPHA_Msk, SPI_CR1_CPHA_Pos, cpha) | + whal_SetBits(SPI_CR1_BR_Msk, SPI_CR1_BR_Pos, br)); /* Enable SPE */ - whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, - whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 1)); + whal_Reg32_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, + whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 1)); return WHAL_SUCCESS; } @@ -214,10 +214,10 @@ whal_Error whal_Stm32f4_Spi_StartCom(whal_Spi *spiDev, whal_Spi_ComCfg *comCfg) whal_Error whal_Stm32f4_Spi_EndCom(whal_Spi *spiDev) { #ifdef WHAL_CFG_STM32F4_SPI_SINGLE_INSTANCE - size_t base = whal_Stm32f4_Spi_Dev.base; + uintptr_t base = whal_Stm32f4_Spi_Dev.base; (void)spiDev; #else - size_t base; + uintptr_t base; if (!spiDev || !spiDev->cfg) return WHAL_EINVAL; @@ -226,8 +226,8 @@ whal_Error whal_Stm32f4_Spi_EndCom(whal_Spi *spiDev) #endif /* Disable SPE */ - whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, - whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 0)); + whal_Reg32_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, + whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 0)); return WHAL_SUCCESS; } @@ -244,13 +244,13 @@ whal_Error whal_Stm32f4_Spi_SendRecv(whal_Spi *spiDev, #ifdef WHAL_CFG_STM32F4_SPI_SINGLE_INSTANCE whal_Stm32f4_Spi_Cfg *cfg = (whal_Stm32f4_Spi_Cfg *)whal_Stm32f4_Spi_Dev.cfg; - size_t base = whal_Stm32f4_Spi_Dev.base; + uintptr_t base = whal_Stm32f4_Spi_Dev.base; (void)spiDev; if ((!tx && txLen) || (!rx && rxLen)) return WHAL_EINVAL; #else - size_t base; + uintptr_t base; whal_Stm32f4_Spi_Cfg *cfg; if (!spiDev || !spiDev->cfg || (!tx && txLen) || (!rx && rxLen)) @@ -263,9 +263,9 @@ whal_Error whal_Stm32f4_Spi_SendRecv(whal_Spi *spiDev, for (size_t i = 0; i < totalLen; i++) { /* Wait for TX buffer empty */ - err = whal_Reg_ReadPoll(base, SPI_SR_REG, - SPI_SR_TXE_Msk, SPI_SR_TXE_Msk, - cfg->timeout); + err = whal_Reg32_ReadPoll(base, SPI_SR_REG, + SPI_SR_TXE_Msk, SPI_SR_TXE_Msk, + cfg->timeout); if (err) return err; @@ -274,9 +274,9 @@ whal_Error whal_Stm32f4_Spi_SendRecv(whal_Spi *spiDev, *(volatile uint8_t *)(base + SPI_DR_REG) = txByte; /* Wait for RX byte */ - err = whal_Reg_ReadPoll(base, SPI_SR_REG, - SPI_SR_RXNE_Msk, SPI_SR_RXNE_Msk, - cfg->timeout); + err = whal_Reg32_ReadPoll(base, SPI_SR_REG, + SPI_SR_RXNE_Msk, SPI_SR_RXNE_Msk, + cfg->timeout); if (err) return err; @@ -288,8 +288,8 @@ whal_Error whal_Stm32f4_Spi_SendRecv(whal_Spi *spiDev, } /* Wait for not busy */ - return whal_Reg_ReadPoll(base, SPI_SR_REG, SPI_SR_BSY_Msk, 0, - cfg->timeout); + return whal_Reg32_ReadPoll(base, SPI_SR_REG, SPI_SR_BSY_Msk, 0, + cfg->timeout); } #ifndef WHAL_CFG_STM32F4_SPI_DIRECT_API_MAPPING diff --git a/src/spi/stm32h5_spi.c b/src/spi/stm32h5_spi.c index 17572741..3dd10a0d 100644 --- a/src/spi/stm32h5_spi.c +++ b/src/spi/stm32h5_spi.c @@ -145,10 +145,10 @@ static uint32_t Stm32h5_Spi_CalcMbr(size_t pclk, uint32_t targetBaud) whal_Error whal_Stm32h5_Spi_Init(whal_Spi *spiDev) { #ifdef WHAL_CFG_STM32H5_SPI_SINGLE_INSTANCE - size_t base = whal_Stm32h5_Spi_Dev.base; + uintptr_t base = whal_Stm32h5_Spi_Dev.base; (void)spiDev; #else - size_t base; + uintptr_t base; if (!spiDev || !spiDev->cfg) return WHAL_EINVAL; @@ -157,17 +157,17 @@ whal_Error whal_Stm32h5_Spi_Init(whal_Spi *spiDev) #endif /* Disable SPI before configuring */ - whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, - whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 0)); + whal_Reg32_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, + whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 0)); - whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_SSI_Msk, - whal_SetBits(SPI_CR1_SSI_Msk, SPI_CR1_SSI_Pos, 1)); + whal_Reg32_Update(base, SPI_CR1_REG, SPI_CR1_SSI_Msk, + whal_SetBits(SPI_CR1_SSI_Msk, SPI_CR1_SSI_Pos, 1)); /* Master mode, software slave management, SSI high */ - whal_Reg_Update(base, SPI_CFG2_REG, - SPI_CFG2_MASTER_Msk | SPI_CFG2_SSM_Msk, - whal_SetBits(SPI_CFG2_MASTER_Msk, SPI_CFG2_MASTER_Pos, 1) | - whal_SetBits(SPI_CFG2_SSM_Msk, SPI_CFG2_SSM_Pos, 1)); + whal_Reg32_Update(base, SPI_CFG2_REG, + SPI_CFG2_MASTER_Msk | SPI_CFG2_SSM_Msk, + whal_SetBits(SPI_CFG2_MASTER_Msk, SPI_CFG2_MASTER_Pos, 1) | + whal_SetBits(SPI_CFG2_SSM_Msk, SPI_CFG2_SSM_Pos, 1)); return WHAL_SUCCESS; } @@ -175,10 +175,10 @@ whal_Error whal_Stm32h5_Spi_Init(whal_Spi *spiDev) whal_Error whal_Stm32h5_Spi_Deinit(whal_Spi *spiDev) { #ifdef WHAL_CFG_STM32H5_SPI_SINGLE_INSTANCE - size_t base = whal_Stm32h5_Spi_Dev.base; + uintptr_t base = whal_Stm32h5_Spi_Dev.base; (void)spiDev; #else - size_t base; + uintptr_t base; if (!spiDev || !spiDev->cfg) return WHAL_EINVAL; @@ -186,8 +186,8 @@ whal_Error whal_Stm32h5_Spi_Deinit(whal_Spi *spiDev) base = spiDev->base; #endif - whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, - whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 0)); + whal_Reg32_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, + whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 0)); return WHAL_SUCCESS; } @@ -198,13 +198,13 @@ whal_Error whal_Stm32h5_Spi_StartCom(whal_Spi *spiDev, whal_Spi_ComCfg *comCfg) #ifdef WHAL_CFG_STM32H5_SPI_SINGLE_INSTANCE whal_Stm32h5_Spi_Cfg *cfg = (whal_Stm32h5_Spi_Cfg *)whal_Stm32h5_Spi_Dev.cfg; - size_t base = whal_Stm32h5_Spi_Dev.base; + uintptr_t base = whal_Stm32h5_Spi_Dev.base; (void)spiDev; if (!comCfg) return WHAL_EINVAL; #else - size_t base; + uintptr_t base; whal_Stm32h5_Spi_Cfg *cfg; if (!spiDev || !spiDev->cfg || !comCfg) @@ -223,8 +223,8 @@ whal_Error whal_Stm32h5_Spi_StartCom(whal_Spi *spiDev, whal_Spi_ComCfg *comCfg) #endif /* Disable SPE before reconfiguring */ - whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, - whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 0)); + whal_Reg32_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, + whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 0)); mbr = Stm32h5_Spi_CalcMbr(cfg->pclk, comCfg->freq); cpol = (comCfg->mode >> 1) & 1; @@ -233,28 +233,28 @@ whal_Error whal_Stm32h5_Spi_StartCom(whal_Spi *spiDev, whal_Spi_ComCfg *comCfg) fthlv = 0; /* 1 data frame threshold */ /* Set baud rate, data size, FIFO threshold */ - whal_Reg_Update(base, SPI_CFG1_REG, - SPI_CFG1_MBR_Msk | SPI_CFG1_DSIZE_Msk | SPI_CFG1_FTHLV_Msk, - whal_SetBits(SPI_CFG1_MBR_Msk, SPI_CFG1_MBR_Pos, mbr) | - whal_SetBits(SPI_CFG1_DSIZE_Msk, SPI_CFG1_DSIZE_Pos, dsize) | - whal_SetBits(SPI_CFG1_FTHLV_Msk, SPI_CFG1_FTHLV_Pos, fthlv)); + whal_Reg32_Update(base, SPI_CFG1_REG, + SPI_CFG1_MBR_Msk | SPI_CFG1_DSIZE_Msk | SPI_CFG1_FTHLV_Msk, + whal_SetBits(SPI_CFG1_MBR_Msk, SPI_CFG1_MBR_Pos, mbr) | + whal_SetBits(SPI_CFG1_DSIZE_Msk, SPI_CFG1_DSIZE_Pos, dsize) | + whal_SetBits(SPI_CFG1_FTHLV_Msk, SPI_CFG1_FTHLV_Pos, fthlv)); /* Set CPOL, CPHA */ - whal_Reg_Update(base, SPI_CFG2_REG, - SPI_CFG2_CPOL_Msk | SPI_CFG2_CPHA_Msk, - whal_SetBits(SPI_CFG2_CPOL_Msk, SPI_CFG2_CPOL_Pos, cpol) | - whal_SetBits(SPI_CFG2_CPHA_Msk, SPI_CFG2_CPHA_Pos, cpha)); + whal_Reg32_Update(base, SPI_CFG2_REG, + SPI_CFG2_CPOL_Msk | SPI_CFG2_CPHA_Msk, + whal_SetBits(SPI_CFG2_CPOL_Msk, SPI_CFG2_CPOL_Pos, cpol) | + whal_SetBits(SPI_CFG2_CPHA_Msk, SPI_CFG2_CPHA_Pos, cpha)); /* Endless transfer mode (TSIZE = 0) */ - whal_Reg_Update(base, SPI_CR2_REG, SPI_CR2_TSIZE_Msk, 0); + whal_Reg32_Update(base, SPI_CR2_REG, SPI_CR2_TSIZE_Msk, 0); /* Enable SPI */ - whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, - whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 1)); + whal_Reg32_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, + whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 1)); /* Start master transfer */ - whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_CSTART_Msk, - whal_SetBits(SPI_CR1_CSTART_Msk, SPI_CR1_CSTART_Pos, 1)); + whal_Reg32_Update(base, SPI_CR1_REG, SPI_CR1_CSTART_Msk, + whal_SetBits(SPI_CR1_CSTART_Msk, SPI_CR1_CSTART_Pos, 1)); return WHAL_SUCCESS; } @@ -262,10 +262,10 @@ whal_Error whal_Stm32h5_Spi_StartCom(whal_Spi *spiDev, whal_Spi_ComCfg *comCfg) whal_Error whal_Stm32h5_Spi_EndCom(whal_Spi *spiDev) { #ifdef WHAL_CFG_STM32H5_SPI_SINGLE_INSTANCE - size_t base = whal_Stm32h5_Spi_Dev.base; + uintptr_t base = whal_Stm32h5_Spi_Dev.base; (void)spiDev; #else - size_t base; + uintptr_t base; if (!spiDev || !spiDev->cfg) return WHAL_EINVAL; @@ -274,12 +274,12 @@ whal_Error whal_Stm32h5_Spi_EndCom(whal_Spi *spiDev) #endif /* Disable SPI */ - whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, - whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 0)); + whal_Reg32_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, + whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 0)); /* Clear EOT and TXTF flags */ - whal_Reg_Write(base, SPI_IFCR_REG, - SPI_IFCR_EOTC_Msk | SPI_IFCR_TXTFC_Msk); + whal_Reg32_Write(base, SPI_IFCR_REG, + SPI_IFCR_EOTC_Msk | SPI_IFCR_TXTFC_Msk); return WHAL_SUCCESS; } @@ -297,13 +297,13 @@ whal_Error whal_Stm32h5_Spi_SendRecv(whal_Spi *spiDev, #ifdef WHAL_CFG_STM32H5_SPI_SINGLE_INSTANCE whal_Stm32h5_Spi_Cfg *cfg = (whal_Stm32h5_Spi_Cfg *)whal_Stm32h5_Spi_Dev.cfg; - size_t base = whal_Stm32h5_Spi_Dev.base; + uintptr_t base = whal_Stm32h5_Spi_Dev.base; (void)spiDev; if ((!tx && txLen) || (!rx && rxLen)) return WHAL_EINVAL; #else - size_t base; + uintptr_t base; whal_Stm32h5_Spi_Cfg *cfg; if (!spiDev || !spiDev->cfg || (!tx && txLen) || (!rx && rxLen)) @@ -316,7 +316,7 @@ whal_Error whal_Stm32h5_Spi_SendRecv(whal_Spi *spiDev, * wordSz-1; frames occupy 1/2/4 buffer bytes held native-endian * (little-endian on these targets). */ wordSz = whal_GetBits(SPI_CFG1_DSIZE_Msk, SPI_CFG1_DSIZE_Pos, - whal_Reg_Read(base, SPI_CFG1_REG)) + 1; + whal_Reg32_Read(base, SPI_CFG1_REG)) + 1; frameBytes = (wordSz > 16) ? 4 : (wordSz > 8) ? 2 : 1; /* A multi-byte frame spans several buffer bytes, so each buffer must @@ -331,9 +331,9 @@ whal_Error whal_Stm32h5_Spi_SendRecv(whal_Spi *spiDev, size_t b; /* Wait for TXP (TX FIFO has space) */ - err = whal_Reg_ReadPoll(base, SPI_SR_REG, - SPI_SR_TXP_Msk, SPI_SR_TXP_Msk, - cfg->timeout); + err = whal_Reg32_ReadPoll(base, SPI_SR_REG, + SPI_SR_TXP_Msk, SPI_SR_TXP_Msk, + cfg->timeout); if (err) return err; @@ -353,9 +353,9 @@ whal_Error whal_Stm32h5_Spi_SendRecv(whal_Spi *spiDev, *(volatile uint32_t *)(base + SPI_TXDR_REG) = frame; /* Wait for RXP (RX FIFO has data) */ - err = whal_Reg_ReadPoll(base, SPI_SR_REG, - SPI_SR_RXP_Msk, SPI_SR_RXP_Msk, - cfg->timeout); + err = whal_Reg32_ReadPoll(base, SPI_SR_REG, + SPI_SR_RXP_Msk, SPI_SR_RXP_Msk, + cfg->timeout); if (err) return err; diff --git a/src/spi/stm32wb_spi.c b/src/spi/stm32wb_spi.c index 2f6e559e..3c0e481f 100644 --- a/src/spi/stm32wb_spi.c +++ b/src/spi/stm32wb_spi.c @@ -120,10 +120,10 @@ static uint32_t whal_Stm32wb_Spi_CalcBr(size_t pclk, uint32_t targetBaud) whal_Error whal_Stm32wb_Spi_Init(whal_Spi *spiDev) { #ifdef WHAL_CFG_STM32WB_SPI_SINGLE_INSTANCE - size_t base = whal_Stm32wb_Spi_Dev.base; + uintptr_t base = whal_Stm32wb_Spi_Dev.base; (void)spiDev; #else - size_t base; + uintptr_t base; if (!spiDev || !spiDev->cfg) { return WHAL_EINVAL; @@ -133,11 +133,11 @@ whal_Error whal_Stm32wb_Spi_Init(whal_Spi *spiDev) #endif /* Master mode with software slave management */ - whal_Reg_Update(base, SPI_CR1_REG, - SPI_CR1_MSTR_Msk | SPI_CR1_SSM_Msk | SPI_CR1_SSI_Msk, - whal_SetBits(SPI_CR1_MSTR_Msk, SPI_CR1_MSTR_Pos, 1) | - whal_SetBits(SPI_CR1_SSM_Msk, SPI_CR1_SSM_Pos, 1) | - whal_SetBits(SPI_CR1_SSI_Msk, SPI_CR1_SSI_Pos, 1)); + whal_Reg32_Update(base, SPI_CR1_REG, + SPI_CR1_MSTR_Msk | SPI_CR1_SSM_Msk | SPI_CR1_SSI_Msk, + whal_SetBits(SPI_CR1_MSTR_Msk, SPI_CR1_MSTR_Pos, 1) | + whal_SetBits(SPI_CR1_SSM_Msk, SPI_CR1_SSM_Pos, 1) | + whal_SetBits(SPI_CR1_SSI_Msk, SPI_CR1_SSI_Pos, 1)); return WHAL_SUCCESS; } @@ -145,10 +145,10 @@ whal_Error whal_Stm32wb_Spi_Init(whal_Spi *spiDev) whal_Error whal_Stm32wb_Spi_Deinit(whal_Spi *spiDev) { #ifdef WHAL_CFG_STM32WB_SPI_SINGLE_INSTANCE - size_t base = whal_Stm32wb_Spi_Dev.base; + uintptr_t base = whal_Stm32wb_Spi_Dev.base; (void)spiDev; #else - size_t base; + uintptr_t base; if (!spiDev || !spiDev->cfg) { return WHAL_EINVAL; @@ -158,8 +158,8 @@ whal_Error whal_Stm32wb_Spi_Deinit(whal_Spi *spiDev) #endif /* Disable SPI */ - whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, - whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 0)); + whal_Reg32_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, + whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 0)); return WHAL_SUCCESS; } @@ -170,14 +170,14 @@ whal_Error whal_Stm32wb_Spi_StartCom(whal_Spi *spiDev, whal_Spi_ComCfg *comCfg) #ifdef WHAL_CFG_STM32WB_SPI_SINGLE_INSTANCE whal_Stm32wb_Spi_Cfg *cfg = (whal_Stm32wb_Spi_Cfg *)whal_Stm32wb_Spi_Dev.cfg; - size_t base = whal_Stm32wb_Spi_Dev.base; + uintptr_t base = whal_Stm32wb_Spi_Dev.base; (void)spiDev; if (!comCfg) { return WHAL_EINVAL; } #else - size_t base; + uintptr_t base; whal_Stm32wb_Spi_Cfg *cfg; if (!spiDev || !spiDev->cfg || !comCfg) { @@ -207,25 +207,25 @@ whal_Error whal_Stm32wb_Spi_StartCom(whal_Spi *spiDev, whal_Spi_ComCfg *comCfg) frxth = (comCfg->wordSz <= 8) ? 1 : 0; /* Disable SPE before reconfiguring */ - whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, - whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 0)); + whal_Reg32_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, + whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 0)); /* Set mode and baud rate */ - whal_Reg_Update(base, SPI_CR1_REG, - SPI_CR1_CPOL_Msk | SPI_CR1_CPHA_Msk | SPI_CR1_BR_Msk, - whal_SetBits(SPI_CR1_CPOL_Msk, SPI_CR1_CPOL_Pos, cpol) | - whal_SetBits(SPI_CR1_CPHA_Msk, SPI_CR1_CPHA_Pos, cpha) | - whal_SetBits(SPI_CR1_BR_Msk, SPI_CR1_BR_Pos, br)); + whal_Reg32_Update(base, SPI_CR1_REG, + SPI_CR1_CPOL_Msk | SPI_CR1_CPHA_Msk | SPI_CR1_BR_Msk, + whal_SetBits(SPI_CR1_CPOL_Msk, SPI_CR1_CPOL_Pos, cpol) | + whal_SetBits(SPI_CR1_CPHA_Msk, SPI_CR1_CPHA_Pos, cpha) | + whal_SetBits(SPI_CR1_BR_Msk, SPI_CR1_BR_Pos, br)); /* Set data size and FIFO receive threshold */ - whal_Reg_Update(base, SPI_CR2_REG, - SPI_CR2_DS_Msk | SPI_CR2_FRXTH_Msk, - whal_SetBits(SPI_CR2_DS_Msk, SPI_CR2_DS_Pos, ds) | - whal_SetBits(SPI_CR2_FRXTH_Msk, SPI_CR2_FRXTH_Pos, frxth)); + whal_Reg32_Update(base, SPI_CR2_REG, + SPI_CR2_DS_Msk | SPI_CR2_FRXTH_Msk, + whal_SetBits(SPI_CR2_DS_Msk, SPI_CR2_DS_Pos, ds) | + whal_SetBits(SPI_CR2_FRXTH_Msk, SPI_CR2_FRXTH_Pos, frxth)); /* Enable SPE */ - whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, - whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 1)); + whal_Reg32_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, + whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 1)); return WHAL_SUCCESS; } @@ -233,10 +233,10 @@ whal_Error whal_Stm32wb_Spi_StartCom(whal_Spi *spiDev, whal_Spi_ComCfg *comCfg) whal_Error whal_Stm32wb_Spi_EndCom(whal_Spi *spiDev) { #ifdef WHAL_CFG_STM32WB_SPI_SINGLE_INSTANCE - size_t base = whal_Stm32wb_Spi_Dev.base; + uintptr_t base = whal_Stm32wb_Spi_Dev.base; (void)spiDev; #else - size_t base; + uintptr_t base; if (!spiDev || !spiDev->cfg) { return WHAL_EINVAL; @@ -246,8 +246,8 @@ whal_Error whal_Stm32wb_Spi_EndCom(whal_Spi *spiDev) #endif /* Disable SPE */ - whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, - whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 0)); + whal_Reg32_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, + whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 0)); return WHAL_SUCCESS; } @@ -265,14 +265,14 @@ whal_Error whal_Stm32wb_Spi_SendRecv(whal_Spi *spiDev, #ifdef WHAL_CFG_STM32WB_SPI_SINGLE_INSTANCE whal_Stm32wb_Spi_Cfg *cfg = (whal_Stm32wb_Spi_Cfg *)whal_Stm32wb_Spi_Dev.cfg; - size_t base = whal_Stm32wb_Spi_Dev.base; + uintptr_t base = whal_Stm32wb_Spi_Dev.base; (void)spiDev; if ((!tx && txLen) || (!rx && rxLen)) { return WHAL_EINVAL; } #else - size_t base; + uintptr_t base; whal_Stm32wb_Spi_Cfg *cfg; if (!spiDev || !spiDev->cfg || (!tx && txLen) || (!rx && rxLen)) { @@ -283,7 +283,7 @@ whal_Error whal_Stm32wb_Spi_SendRecv(whal_Spi *spiDev, cfg = (whal_Stm32wb_Spi_Cfg *)spiDev->cfg; #endif wordSz = whal_GetBits(SPI_CR2_DS_Msk, SPI_CR2_DS_Pos, - whal_Reg_Read(base, SPI_CR2_REG)) + 1; + whal_Reg32_Read(base, SPI_CR2_REG)) + 1; frameBytes = (wordSz > 8) ? 2 : 1; totalLen = txLen > rxLen ? txLen : rxLen; @@ -295,9 +295,9 @@ whal_Error whal_Stm32wb_Spi_SendRecv(whal_Spi *spiDev, for (size_t i = 0; i < totalLen; i += frameBytes) { /* Wait for TX buffer empty */ - err = whal_Reg_ReadPoll(base, SPI_SR_REG, - SPI_SR_TXE_Msk, SPI_SR_TXE_Msk, - cfg->timeout); + err = whal_Reg32_ReadPoll(base, SPI_SR_REG, + SPI_SR_TXE_Msk, SPI_SR_TXE_Msk, + cfg->timeout); if (err) return err; @@ -313,9 +313,9 @@ whal_Error whal_Stm32wb_Spi_SendRecv(whal_Spi *spiDev, } /* Wait for RX byte */ - err = whal_Reg_ReadPoll(base, SPI_SR_REG, - SPI_SR_RXNE_Msk, SPI_SR_RXNE_Msk, - cfg->timeout); + err = whal_Reg32_ReadPoll(base, SPI_SR_REG, + SPI_SR_RXNE_Msk, SPI_SR_RXNE_Msk, + cfg->timeout); if (err) return err; @@ -340,8 +340,8 @@ whal_Error whal_Stm32wb_Spi_SendRecv(whal_Spi *spiDev, } /* Wait for not busy */ - return whal_Reg_ReadPoll(base, SPI_SR_REG, SPI_SR_BSY_Msk, 0, - cfg->timeout); + return whal_Reg32_ReadPoll(base, SPI_SR_REG, SPI_SR_BSY_Msk, 0, + cfg->timeout); } #ifndef WHAL_CFG_STM32WB_SPI_DIRECT_API_MAPPING diff --git a/src/timer/systick.c b/src/timer/systick.c index 4581ee6d..b84729fc 100644 --- a/src/timer/systick.c +++ b/src/timer/systick.c @@ -59,58 +59,58 @@ whal_Error whal_SysTick_Init(whal_Timer *timerDev) { const whal_SysTick_Cfg *cfg = (const whal_SysTick_Cfg *)whal_SysTick_Dev.cfg; - size_t base = whal_SysTick_Dev.base; + uintptr_t base = whal_SysTick_Dev.base; (void)timerDev; /* RELOAD is 24 bits and holds the period minus one */ if (cfg->cyclesPerTick < 2 || cfg->cyclesPerTick > 0x1000000) return WHAL_EINVAL; - whal_Reg_Update(base, SYSTICK_CSR_REG, + whal_Reg32_Update(base, SYSTICK_CSR_REG, SYSTICK_CSR_CLKSOURCE_Msk | SYSTICK_CSR_TICKINT_Msk, whal_SetBits(SYSTICK_CSR_CLKSOURCE_Msk, SYSTICK_CSR_CLKSOURCE_Pos, cfg->clkSrc) | whal_SetBits(SYSTICK_CSR_TICKINT_Msk, SYSTICK_CSR_TICKINT_Pos, cfg->tickInt)); - whal_Reg_Update(base, SYSTICK_RVR_REG, - SYSTICK_RVR_RELOAD_Msk, - whal_SetBits(SYSTICK_RVR_RELOAD_Msk, SYSTICK_RVR_RELOAD_Pos, cfg->cyclesPerTick - 1)); + whal_Reg32_Update(base, SYSTICK_RVR_REG, + SYSTICK_RVR_RELOAD_Msk, + whal_SetBits(SYSTICK_RVR_RELOAD_Msk, SYSTICK_RVR_RELOAD_Pos, cfg->cyclesPerTick - 1)); /* Any write clears the counter so the first period starts from RELOAD */ - whal_Reg_Write(base, SYSTICK_CVR_REG, 0); + whal_Reg32_Write(base, SYSTICK_CVR_REG, 0); return WHAL_SUCCESS; } whal_Error whal_SysTick_Deinit(whal_Timer *timerDev) { - size_t base = whal_SysTick_Dev.base; + uintptr_t base = whal_SysTick_Dev.base; (void)timerDev; - whal_Reg_Update(base, SYSTICK_CSR_REG, - SYSTICK_CSR_ENABLE_Msk | SYSTICK_CSR_TICKINT_Msk, 0); - whal_Reg_Write(base, SYSTICK_CVR_REG, 0); + whal_Reg32_Update(base, SYSTICK_CSR_REG, + SYSTICK_CSR_ENABLE_Msk | SYSTICK_CSR_TICKINT_Msk, 0); + whal_Reg32_Write(base, SYSTICK_CVR_REG, 0); return WHAL_SUCCESS; } whal_Error whal_SysTick_Start(whal_Timer *timerDev) { - size_t base = whal_SysTick_Dev.base; + uintptr_t base = whal_SysTick_Dev.base; (void)timerDev; - whal_Reg_Update(base, SYSTICK_CSR_REG, SYSTICK_CSR_ENABLE_Msk, - whal_SetBits(SYSTICK_CSR_ENABLE_Msk, SYSTICK_CSR_ENABLE_Pos, 1)); + whal_Reg32_Update(base, SYSTICK_CSR_REG, SYSTICK_CSR_ENABLE_Msk, + whal_SetBits(SYSTICK_CSR_ENABLE_Msk, SYSTICK_CSR_ENABLE_Pos, 1)); return WHAL_SUCCESS; } whal_Error whal_SysTick_Stop(whal_Timer *timerDev) { - size_t base = whal_SysTick_Dev.base; + uintptr_t base = whal_SysTick_Dev.base; (void)timerDev; - whal_Reg_Update(base, SYSTICK_CSR_REG, SYSTICK_CSR_ENABLE_Msk, - whal_SetBits(SYSTICK_CSR_ENABLE_Msk, SYSTICK_CSR_ENABLE_Pos, 0)); + whal_Reg32_Update(base, SYSTICK_CSR_REG, SYSTICK_CSR_ENABLE_Msk, + whal_SetBits(SYSTICK_CSR_ENABLE_Msk, SYSTICK_CSR_ENABLE_Pos, 0)); return WHAL_SUCCESS; } @@ -118,7 +118,7 @@ whal_Error whal_SysTick_Stop(whal_Timer *timerDev) whal_Error whal_SysTick_Reset(whal_Timer *timerDev) { (void)timerDev; - whal_Reg_Write(whal_SysTick_Dev.base, SYSTICK_CVR_REG, 0); + whal_Reg32_Write(whal_SysTick_Dev.base, SYSTICK_CVR_REG, 0); return WHAL_SUCCESS; } diff --git a/src/uart/pic32cz_uart.c b/src/uart/pic32cz_uart.c index 44be8f57..826fad8e 100644 --- a/src/uart/pic32cz_uart.c +++ b/src/uart/pic32cz_uart.c @@ -209,11 +209,11 @@ whal_Error whal_Pic32cz_Uart_Init(whal_Uart *uartDev) #ifdef WHAL_CFG_PIC32CZ_UART_SINGLE_INSTANCE whal_Pic32cz_Uart_Cfg *cfg = (whal_Pic32cz_Uart_Cfg *)whal_Pic32cz_Uart_Dev.cfg; - size_t base = whal_Pic32cz_Uart_Dev.base; + uintptr_t base = whal_Pic32cz_Uart_Dev.base; (void)uartDev; #else whal_Pic32cz_Uart_Cfg *cfg; - size_t base; + uintptr_t base; if (!uartDev || !uartDev->cfg) { return WHAL_EINVAL; @@ -224,61 +224,61 @@ whal_Error whal_Pic32cz_Uart_Init(whal_Uart *uartDev) #endif /* Configure CTRLA: internal clock, async mode, LSB first, 16x sampling */ - whal_Reg_Update(base, USART_CTRLA_REG, - USART_CTRLA_MODE_Msk | - USART_CTRLA_SAMPR_Msk | - USART_CTRLA_TXPO_Msk | - USART_CTRLA_RXPO_Msk | - USART_CTRLA_FORM_Msk | - USART_CTRLA_CMODE_Msk | - USART_CTRLA_DORD_Msk, - whal_SetBits(USART_CTRLA_MODE_Msk, USART_CTRLA_MODE_Pos, USART_CTRLA_MODE_USART_INT_CLK) | - whal_SetBits(USART_CTRLA_SAMPR_Msk, USART_CTRLA_SAMPR_Pos, USART_CTRLA_SAMPR_16X_ARITH) | - whal_SetBits(USART_CTRLA_TXPO_Msk, USART_CTRLA_TXPO_Pos, cfg->txPad) | - whal_SetBits(USART_CTRLA_RXPO_Msk, USART_CTRLA_RXPO_Pos, cfg->rxPad) | - whal_SetBits(USART_CTRLA_FORM_Msk, USART_CTRLA_FORM_Pos, USART_CTRLA_FORM_USART) | - whal_SetBits(USART_CTRLA_CMODE_Msk, USART_CTRLA_CMODE_Pos, 0) | /* Async mode */ - whal_SetBits(USART_CTRLA_DORD_Msk, USART_CTRLA_DORD_Pos, 1)); /* LSB first */ + whal_Reg32_Update(base, USART_CTRLA_REG, + USART_CTRLA_MODE_Msk | + USART_CTRLA_SAMPR_Msk | + USART_CTRLA_TXPO_Msk | + USART_CTRLA_RXPO_Msk | + USART_CTRLA_FORM_Msk | + USART_CTRLA_CMODE_Msk | + USART_CTRLA_DORD_Msk, + whal_SetBits(USART_CTRLA_MODE_Msk, USART_CTRLA_MODE_Pos, USART_CTRLA_MODE_USART_INT_CLK) | + whal_SetBits(USART_CTRLA_SAMPR_Msk, USART_CTRLA_SAMPR_Pos, USART_CTRLA_SAMPR_16X_ARITH) | + whal_SetBits(USART_CTRLA_TXPO_Msk, USART_CTRLA_TXPO_Pos, cfg->txPad) | + whal_SetBits(USART_CTRLA_RXPO_Msk, USART_CTRLA_RXPO_Pos, cfg->rxPad) | + whal_SetBits(USART_CTRLA_FORM_Msk, USART_CTRLA_FORM_Pos, USART_CTRLA_FORM_USART) | + whal_SetBits(USART_CTRLA_CMODE_Msk, USART_CTRLA_CMODE_Pos, 0) | /* Async mode */ + whal_SetBits(USART_CTRLA_DORD_Msk, USART_CTRLA_DORD_Pos, 1)); /* LSB first */ /* Configure CTRLB: 8-bit char size, 1 stop bit, no parity */ - whal_Reg_Update(base, USART_CTRLB_REG, - USART_CTRLB_CHSIZE_Msk | - USART_CTRLB_SBMODE_Msk | - USART_CTRLB_PMODE_Msk, - whal_SetBits(USART_CTRLB_CHSIZE_Msk, USART_CTRLB_CHSIZE_Pos, USART_CTRLB_CHSIZE_8BIT) | - whal_SetBits(USART_CTRLB_SBMODE_Msk, USART_CTRLB_SBMODE_Pos, 0) | - whal_SetBits(USART_CTRLB_PMODE_Msk, USART_CTRLB_PMODE_Pos, 0)); + whal_Reg32_Update(base, USART_CTRLB_REG, + USART_CTRLB_CHSIZE_Msk | + USART_CTRLB_SBMODE_Msk | + USART_CTRLB_PMODE_Msk, + whal_SetBits(USART_CTRLB_CHSIZE_Msk, USART_CTRLB_CHSIZE_Pos, USART_CTRLB_CHSIZE_8BIT) | + whal_SetBits(USART_CTRLB_SBMODE_Msk, USART_CTRLB_SBMODE_Pos, 0) | + whal_SetBits(USART_CTRLB_PMODE_Msk, USART_CTRLB_PMODE_Pos, 0)); /* Wait for CTRLB sync */ - err = whal_Reg_ReadPoll(base, USART_SYNCBUSY_REG, + err = whal_Reg32_ReadPoll(base, USART_SYNCBUSY_REG, USART_SYNCBUSY_CTRLB_Msk, 0, cfg->timeout); if (err != WHAL_SUCCESS) return err; /* Set baud rate */ - whal_Reg_Update(base, USART_BAUD_REG, - 0xFFFF, - cfg->baud); + whal_Reg32_Update(base, USART_BAUD_REG, + 0xFFFF, + cfg->baud); /* Enable transmitter and receiver */ - whal_Reg_Update(base, USART_CTRLB_REG, - USART_CTRLB_TXEN_Msk | USART_CTRLB_RXEN_Msk, - whal_SetBits(USART_CTRLB_TXEN_Msk, USART_CTRLB_TXEN_Pos, 1) | - whal_SetBits(USART_CTRLB_RXEN_Msk, USART_CTRLB_RXEN_Pos, 1)); + whal_Reg32_Update(base, USART_CTRLB_REG, + USART_CTRLB_TXEN_Msk | USART_CTRLB_RXEN_Msk, + whal_SetBits(USART_CTRLB_TXEN_Msk, USART_CTRLB_TXEN_Pos, 1) | + whal_SetBits(USART_CTRLB_RXEN_Msk, USART_CTRLB_RXEN_Pos, 1)); /* Wait for CTRLB sync */ - err = whal_Reg_ReadPoll(base, USART_SYNCBUSY_REG, + err = whal_Reg32_ReadPoll(base, USART_SYNCBUSY_REG, USART_SYNCBUSY_CTRLB_Msk, 0, cfg->timeout); if (err != WHAL_SUCCESS) return err; /* Enable SERCOM USART */ - whal_Reg_Update(base, USART_CTRLA_REG, - USART_CTRLA_ENABLE_Msk, - whal_SetBits(USART_CTRLA_ENABLE_Msk, USART_CTRLA_ENABLE_Pos, 1)); + whal_Reg32_Update(base, USART_CTRLA_REG, + USART_CTRLA_ENABLE_Msk, + whal_SetBits(USART_CTRLA_ENABLE_Msk, USART_CTRLA_ENABLE_Pos, 1)); /* Wait for enable sync */ - err = whal_Reg_ReadPoll(base, USART_SYNCBUSY_REG, + err = whal_Reg32_ReadPoll(base, USART_SYNCBUSY_REG, USART_SYNCBUSY_ENABLE_Msk, 0, cfg->timeout); if (err != WHAL_SUCCESS) return err; @@ -292,10 +292,10 @@ whal_Error whal_Pic32cz_Uart_Deinit(whal_Uart *uartDev) #ifdef WHAL_CFG_PIC32CZ_UART_SINGLE_INSTANCE whal_Pic32cz_Uart_Cfg *cfg = (whal_Pic32cz_Uart_Cfg *)whal_Pic32cz_Uart_Dev.cfg; - size_t base = whal_Pic32cz_Uart_Dev.base; + uintptr_t base = whal_Pic32cz_Uart_Dev.base; (void)uartDev; #else - size_t base; + uintptr_t base; whal_Pic32cz_Uart_Cfg *cfg; if (!uartDev || !uartDev->cfg) { @@ -307,24 +307,24 @@ whal_Error whal_Pic32cz_Uart_Deinit(whal_Uart *uartDev) #endif /* Disable SERCOM USART */ - whal_Reg_Update(base, USART_CTRLA_REG, - USART_CTRLA_ENABLE_Msk, - whal_SetBits(USART_CTRLA_ENABLE_Msk, USART_CTRLA_ENABLE_Pos, 0)); + whal_Reg32_Update(base, USART_CTRLA_REG, + USART_CTRLA_ENABLE_Msk, + whal_SetBits(USART_CTRLA_ENABLE_Msk, USART_CTRLA_ENABLE_Pos, 0)); /* Wait for disable sync */ - err = whal_Reg_ReadPoll(base, USART_SYNCBUSY_REG, + err = whal_Reg32_ReadPoll(base, USART_SYNCBUSY_REG, USART_SYNCBUSY_ENABLE_Msk, 0, cfg->timeout); if (err != WHAL_SUCCESS) return err; /* Disable transmitter and receiver */ - whal_Reg_Update(base, USART_CTRLB_REG, - USART_CTRLB_TXEN_Msk | USART_CTRLB_RXEN_Msk, - whal_SetBits(USART_CTRLB_TXEN_Msk, USART_CTRLB_TXEN_Pos, 0) | - whal_SetBits(USART_CTRLB_RXEN_Msk, USART_CTRLB_RXEN_Pos, 0)); + whal_Reg32_Update(base, USART_CTRLB_REG, + USART_CTRLB_TXEN_Msk | USART_CTRLB_RXEN_Msk, + whal_SetBits(USART_CTRLB_TXEN_Msk, USART_CTRLB_TXEN_Pos, 0) | + whal_SetBits(USART_CTRLB_RXEN_Msk, USART_CTRLB_RXEN_Pos, 0)); /* Wait for CTRLB sync */ - err = whal_Reg_ReadPoll(base, USART_SYNCBUSY_REG, + err = whal_Reg32_ReadPoll(base, USART_SYNCBUSY_REG, USART_SYNCBUSY_CTRLB_Msk, 0, cfg->timeout); if (err != WHAL_SUCCESS) return err; @@ -339,14 +339,14 @@ whal_Error whal_Pic32cz_Uart_Send(whal_Uart *uartDev, const void *data, size_t d #ifdef WHAL_CFG_PIC32CZ_UART_SINGLE_INSTANCE whal_Pic32cz_Uart_Cfg *cfg = (whal_Pic32cz_Uart_Cfg *)whal_Pic32cz_Uart_Dev.cfg; - size_t base = whal_Pic32cz_Uart_Dev.base; + uintptr_t base = whal_Pic32cz_Uart_Dev.base; (void)uartDev; if (!data) { return WHAL_EINVAL; } #else - size_t base; + uintptr_t base; whal_Pic32cz_Uart_Cfg *cfg; if (!uartDev || !uartDev->cfg || !data) { @@ -362,27 +362,27 @@ whal_Error whal_Pic32cz_Uart_Send(whal_Uart *uartDev, const void *data, size_t d for (size_t i = 0; i < dataSz; ++i) { /* Wait for data register to be empty */ - err = whal_Reg_ReadPoll(base, USART_INTFLAG_REG, - USART_INTFLAG_DRE_Msk, USART_INTFLAG_DRE_Msk, - cfg->timeout); + err = whal_Reg32_ReadPoll(base, USART_INTFLAG_REG, + USART_INTFLAG_DRE_Msk, USART_INTFLAG_DRE_Msk, + cfg->timeout); if (err) return err; /* Write data to transmit register */ - whal_Reg_Write(base, USART_DATA_REG, + whal_Reg32_Write(base, USART_DATA_REG, whal_SetBits(USART_DATA_Msk, USART_DATA_Pos, buf[i])); } /* Wait for transmission complete */ - err = whal_Reg_ReadPoll(base, USART_INTFLAG_REG, - USART_INTFLAG_TXC_Msk, USART_INTFLAG_TXC_Msk, - cfg->timeout); + err = whal_Reg32_ReadPoll(base, USART_INTFLAG_REG, + USART_INTFLAG_TXC_Msk, USART_INTFLAG_TXC_Msk, + cfg->timeout); if (err) return err; /* Clear TXC flag by writing 1 (W1C: write only this bit, 0 elsewhere) */ - whal_Reg_Write(base, USART_INTFLAG_REG, - whal_SetBits(USART_INTFLAG_TXC_Msk, USART_INTFLAG_TXC_Pos, 1)); + whal_Reg32_Write(base, USART_INTFLAG_REG, + whal_SetBits(USART_INTFLAG_TXC_Msk, USART_INTFLAG_TXC_Pos, 1)); return WHAL_SUCCESS; } @@ -393,14 +393,14 @@ whal_Error whal_Pic32cz_Uart_Recv(whal_Uart *uartDev, void *data, size_t dataSz) #ifdef WHAL_CFG_PIC32CZ_UART_SINGLE_INSTANCE whal_Pic32cz_Uart_Cfg *cfg = (whal_Pic32cz_Uart_Cfg *)whal_Pic32cz_Uart_Dev.cfg; - size_t base = whal_Pic32cz_Uart_Dev.base; + uintptr_t base = whal_Pic32cz_Uart_Dev.base; (void)uartDev; if (!data) { return WHAL_EINVAL; } #else - size_t base; + uintptr_t base; whal_Pic32cz_Uart_Cfg *cfg; if (!uartDev || !uartDev->cfg || !data) { @@ -412,30 +412,30 @@ whal_Error whal_Pic32cz_Uart_Recv(whal_Uart *uartDev, void *data, size_t dataSz) #endif for (size_t i = 0; i < dataSz; ++i) { - size_t rxData; - size_t status; + uint32_t rxData; + uint32_t status; whal_Error err; /* Wait for receive complete */ - err = whal_Reg_ReadPoll(base, USART_INTFLAG_REG, - USART_INTFLAG_RXC_Msk, USART_INTFLAG_RXC_Msk, - cfg->timeout); + err = whal_Reg32_ReadPoll(base, USART_INTFLAG_REG, + USART_INTFLAG_RXC_Msk, USART_INTFLAG_RXC_Msk, + cfg->timeout); if (err) return err; - status = (whal_Reg_Read(base, USART_INTFLAG_REG) >> + status = (whal_Reg32_Read(base, USART_INTFLAG_REG) >> USART_STATUS_WORD_Pos) & USART_STATUS_ERR_Msk; /* Read received data */ - whal_Reg_Get(base, USART_DATA_REG, - USART_DATA_Msk, USART_DATA_Pos, &rxData); + whal_Reg32_Get(base, USART_DATA_REG, + USART_DATA_Msk, USART_DATA_Pos, &rxData); buf[i] = (uint8_t)rxData; if (status) { - whal_Reg_Write(base, USART_INTFLAG_REG, - (status << USART_STATUS_WORD_Pos) | - USART_INTFLAG_ERROR_Msk); + whal_Reg32_Write(base, USART_INTFLAG_REG, + (status << USART_STATUS_WORD_Pos) | + USART_INTFLAG_ERROR_Msk); return WHAL_EHARDWARE; } } diff --git a/src/uart/stm32f0_uart.c b/src/uart/stm32f0_uart.c index 2aedef58..ce9d1a55 100644 --- a/src/uart/stm32f0_uart.c +++ b/src/uart/stm32f0_uart.c @@ -89,11 +89,11 @@ whal_Error whal_Stm32f0_Uart_Init(whal_Uart *uartDev) #ifdef WHAL_CFG_STM32F0_UART_SINGLE_INSTANCE const whal_Stm32f0_Uart_Cfg *cfg = (const whal_Stm32f0_Uart_Cfg *)whal_Stm32f0_Uart_Dev.cfg; - size_t base = whal_Stm32f0_Uart_Dev.base; + uintptr_t base = whal_Stm32f0_Uart_Dev.base; (void)uartDev; #else whal_Stm32f0_Uart_Cfg *cfg; - size_t base; + uintptr_t base; if (!uartDev || !uartDev->cfg) return WHAL_EINVAL; @@ -102,15 +102,15 @@ whal_Error whal_Stm32f0_Uart_Init(whal_Uart *uartDev) cfg = (whal_Stm32f0_Uart_Cfg *)uartDev->cfg; #endif - whal_Reg_Update(base, UART_BRR_REG, UART_BRR_Msk, - whal_SetBits(UART_BRR_Msk, UART_BRR_Pos, cfg->brr)); + whal_Reg32_Update(base, UART_BRR_REG, UART_BRR_Msk, + whal_SetBits(UART_BRR_Msk, UART_BRR_Pos, cfg->brr)); /* Enable UE, RE, TE — no FIFOEN on STM32F0 */ - whal_Reg_Update(base, UART_CR1_REG, - UART_CR1_UE_Msk | UART_CR1_RE_Msk | UART_CR1_TE_Msk, - whal_SetBits(UART_CR1_UE_Msk, UART_CR1_UE_Pos, 1) | - whal_SetBits(UART_CR1_RE_Msk, UART_CR1_RE_Pos, 1) | - whal_SetBits(UART_CR1_TE_Msk, UART_CR1_TE_Pos, 1)); + whal_Reg32_Update(base, UART_CR1_REG, + UART_CR1_UE_Msk | UART_CR1_RE_Msk | UART_CR1_TE_Msk, + whal_SetBits(UART_CR1_UE_Msk, UART_CR1_UE_Pos, 1) | + whal_SetBits(UART_CR1_RE_Msk, UART_CR1_RE_Pos, 1) | + whal_SetBits(UART_CR1_TE_Msk, UART_CR1_TE_Pos, 1)); return WHAL_SUCCESS; } @@ -118,10 +118,10 @@ whal_Error whal_Stm32f0_Uart_Init(whal_Uart *uartDev) whal_Error whal_Stm32f0_Uart_Deinit(whal_Uart *uartDev) { #ifdef WHAL_CFG_STM32F0_UART_SINGLE_INSTANCE - size_t base = whal_Stm32f0_Uart_Dev.base; + uintptr_t base = whal_Stm32f0_Uart_Dev.base; (void)uartDev; #else - size_t base; + uintptr_t base; if (!uartDev) return WHAL_EINVAL; @@ -129,14 +129,14 @@ whal_Error whal_Stm32f0_Uart_Deinit(whal_Uart *uartDev) base = uartDev->base; #endif - whal_Reg_Update(base, UART_CR1_REG, - UART_CR1_UE_Msk | UART_CR1_RE_Msk | UART_CR1_TE_Msk, - whal_SetBits(UART_CR1_UE_Msk, UART_CR1_UE_Pos, 0) | - whal_SetBits(UART_CR1_RE_Msk, UART_CR1_RE_Pos, 0) | - whal_SetBits(UART_CR1_TE_Msk, UART_CR1_TE_Pos, 0)); + whal_Reg32_Update(base, UART_CR1_REG, + UART_CR1_UE_Msk | UART_CR1_RE_Msk | UART_CR1_TE_Msk, + whal_SetBits(UART_CR1_UE_Msk, UART_CR1_UE_Pos, 0) | + whal_SetBits(UART_CR1_RE_Msk, UART_CR1_RE_Pos, 0) | + whal_SetBits(UART_CR1_TE_Msk, UART_CR1_TE_Pos, 0)); - whal_Reg_Update(base, UART_BRR_REG, UART_BRR_Msk, - whal_SetBits(UART_BRR_Msk, UART_BRR_Pos, 0)); + whal_Reg32_Update(base, UART_BRR_REG, UART_BRR_Msk, + whal_SetBits(UART_BRR_Msk, UART_BRR_Pos, 0)); return WHAL_SUCCESS; } @@ -148,13 +148,13 @@ whal_Error whal_Stm32f0_Uart_Send(whal_Uart *uartDev, const void *data, #ifdef WHAL_CFG_STM32F0_UART_SINGLE_INSTANCE const whal_Stm32f0_Uart_Cfg *cfg = (const whal_Stm32f0_Uart_Cfg *)whal_Stm32f0_Uart_Dev.cfg; - size_t base = whal_Stm32f0_Uart_Dev.base; + uintptr_t base = whal_Stm32f0_Uart_Dev.base; (void)uartDev; if (!data) return WHAL_EINVAL; #else - size_t base; + uintptr_t base; whal_Stm32f0_Uart_Cfg *cfg; if (!uartDev || !uartDev->cfg || !data) @@ -166,11 +166,11 @@ whal_Error whal_Stm32f0_Uart_Send(whal_Uart *uartDev, const void *data, for (size_t i = 0; i < dataSz; ++i) { whal_Error err; - whal_Reg_Update(base, UART_TDR_REG, UART_TDR_Msk, - whal_SetBits(UART_TDR_Msk, UART_TDR_Pos, buf[i])); + whal_Reg32_Update(base, UART_TDR_REG, UART_TDR_Msk, + whal_SetBits(UART_TDR_Msk, UART_TDR_Pos, buf[i])); - err = whal_Reg_ReadPoll(base, UART_ISR_REG, UART_ISR_TC_Msk, - UART_ISR_TC_Msk, cfg->timeout); + err = whal_Reg32_ReadPoll(base, UART_ISR_REG, UART_ISR_TC_Msk, + UART_ISR_TC_Msk, cfg->timeout); if (err) return err; } @@ -184,13 +184,13 @@ whal_Error whal_Stm32f0_Uart_Recv(whal_Uart *uartDev, void *data, size_t dataSz) #ifdef WHAL_CFG_STM32F0_UART_SINGLE_INSTANCE const whal_Stm32f0_Uart_Cfg *cfg = (const whal_Stm32f0_Uart_Cfg *)whal_Stm32f0_Uart_Dev.cfg; - size_t base = whal_Stm32f0_Uart_Dev.base; + uintptr_t base = whal_Stm32f0_Uart_Dev.base; (void)uartDev; if (!data) return WHAL_EINVAL; #else - size_t base; + uintptr_t base; whal_Stm32f0_Uart_Cfg *cfg; if (!uartDev || !uartDev->cfg || !data) @@ -201,20 +201,20 @@ whal_Error whal_Stm32f0_Uart_Recv(whal_Uart *uartDev, void *data, size_t dataSz) #endif for (size_t i = 0; i < dataSz; ++i) { - size_t d; + uint32_t d; size_t isr; - whal_Error err = whal_Reg_ReadPoll(base, UART_ISR_REG, - UART_ISR_RXNE_Msk, - UART_ISR_RXNE_Msk, cfg->timeout); + whal_Error err = whal_Reg32_ReadPoll(base, UART_ISR_REG, + UART_ISR_RXNE_Msk, + UART_ISR_RXNE_Msk, cfg->timeout); if (err) return err; - isr = whal_Reg_Read(base, UART_ISR_REG); - whal_Reg_Get(base, UART_RDR_REG, UART_RDR_Msk, UART_RDR_Pos, &d); + isr = whal_Reg32_Read(base, UART_ISR_REG); + whal_Reg32_Get(base, UART_RDR_REG, UART_RDR_Msk, UART_RDR_Pos, &d); buf[i] = d; if (isr & UART_ISR_ERR_Msk) { - whal_Reg_Write(base, UART_ICR_REG, isr & UART_ISR_ERR_Msk); + whal_Reg32_Write(base, UART_ICR_REG, isr & UART_ISR_ERR_Msk); return WHAL_EHARDWARE; } } diff --git a/src/uart/stm32f4_uart.c b/src/uart/stm32f4_uart.c index ef71e154..456ca915 100644 --- a/src/uart/stm32f4_uart.c +++ b/src/uart/stm32f4_uart.c @@ -103,11 +103,11 @@ whal_Error whal_Stm32f4_Uart_Init(whal_Uart *uartDev) #ifdef WHAL_CFG_STM32F4_UART_SINGLE_INSTANCE const whal_Stm32f4_Uart_Cfg *cfg = (const whal_Stm32f4_Uart_Cfg *)whal_Stm32f4_Uart_Dev.cfg; - size_t base = whal_Stm32f4_Uart_Dev.base; + uintptr_t base = whal_Stm32f4_Uart_Dev.base; (void)uartDev; #else whal_Stm32f4_Uart_Cfg *cfg; - size_t base; + uintptr_t base; if (!uartDev || !uartDev->cfg) return WHAL_EINVAL; @@ -119,16 +119,16 @@ whal_Error whal_Stm32f4_Uart_Init(whal_Uart *uartDev) brr = cfg->brr; /* Set baud rate */ - whal_Reg_Update(base, UART_BRR_REG, - UART_BRR_Msk, - whal_SetBits(UART_BRR_Msk, UART_BRR_Pos, brr)); + whal_Reg32_Update(base, UART_BRR_REG, + UART_BRR_Msk, + whal_SetBits(UART_BRR_Msk, UART_BRR_Pos, brr)); /* Enable USART, transmitter, and receiver */ - whal_Reg_Update(base, UART_CR1_REG, - UART_CR1_UE_Msk | UART_CR1_RE_Msk | UART_CR1_TE_Msk, - whal_SetBits(UART_CR1_UE_Msk, UART_CR1_UE_Pos, 1) | - whal_SetBits(UART_CR1_RE_Msk, UART_CR1_RE_Pos, 1) | - whal_SetBits(UART_CR1_TE_Msk, UART_CR1_TE_Pos, 1)); + whal_Reg32_Update(base, UART_CR1_REG, + UART_CR1_UE_Msk | UART_CR1_RE_Msk | UART_CR1_TE_Msk, + whal_SetBits(UART_CR1_UE_Msk, UART_CR1_UE_Pos, 1) | + whal_SetBits(UART_CR1_RE_Msk, UART_CR1_RE_Pos, 1) | + whal_SetBits(UART_CR1_TE_Msk, UART_CR1_TE_Pos, 1)); return WHAL_SUCCESS; } @@ -136,10 +136,10 @@ whal_Error whal_Stm32f4_Uart_Init(whal_Uart *uartDev) whal_Error whal_Stm32f4_Uart_Deinit(whal_Uart *uartDev) { #ifdef WHAL_CFG_STM32F4_UART_SINGLE_INSTANCE - size_t base = whal_Stm32f4_Uart_Dev.base; + uintptr_t base = whal_Stm32f4_Uart_Dev.base; (void)uartDev; #else - size_t base; + uintptr_t base; if (!uartDev) return WHAL_EINVAL; @@ -148,16 +148,16 @@ whal_Error whal_Stm32f4_Uart_Deinit(whal_Uart *uartDev) #endif /* Disable USART, transmitter, and receiver */ - whal_Reg_Update(base, UART_CR1_REG, - UART_CR1_UE_Msk | UART_CR1_RE_Msk | UART_CR1_TE_Msk, - whal_SetBits(UART_CR1_UE_Msk, UART_CR1_UE_Pos, 0) | - whal_SetBits(UART_CR1_RE_Msk, UART_CR1_RE_Pos, 0) | - whal_SetBits(UART_CR1_TE_Msk, UART_CR1_TE_Pos, 0)); + whal_Reg32_Update(base, UART_CR1_REG, + UART_CR1_UE_Msk | UART_CR1_RE_Msk | UART_CR1_TE_Msk, + whal_SetBits(UART_CR1_UE_Msk, UART_CR1_UE_Pos, 0) | + whal_SetBits(UART_CR1_RE_Msk, UART_CR1_RE_Pos, 0) | + whal_SetBits(UART_CR1_TE_Msk, UART_CR1_TE_Pos, 0)); /* Clear baud rate */ - whal_Reg_Update(base, UART_BRR_REG, - UART_BRR_Msk, - whal_SetBits(UART_BRR_Msk, UART_BRR_Pos, 0)); + whal_Reg32_Update(base, UART_BRR_REG, + UART_BRR_Msk, + whal_SetBits(UART_BRR_Msk, UART_BRR_Pos, 0)); return WHAL_SUCCESS; } @@ -168,13 +168,13 @@ whal_Error whal_Stm32f4_Uart_Send(whal_Uart *uartDev, const void *data, size_t d #ifdef WHAL_CFG_STM32F4_UART_SINGLE_INSTANCE const whal_Stm32f4_Uart_Cfg *cfg = (const whal_Stm32f4_Uart_Cfg *)whal_Stm32f4_Uart_Dev.cfg; - size_t base = whal_Stm32f4_Uart_Dev.base; + uintptr_t base = whal_Stm32f4_Uart_Dev.base; (void)uartDev; if (!data) return WHAL_EINVAL; #else - size_t base; + uintptr_t base; whal_Stm32f4_Uart_Cfg *cfg; if (!uartDev || !uartDev->cfg || !data) @@ -191,35 +191,35 @@ whal_Error whal_Stm32f4_Uart_Send(whal_Uart *uartDev, const void *data, size_t d whal_Error err; /* Wait for transmit data register empty */ - err = whal_Reg_ReadPoll(base, UART_SR_REG, UART_SR_TXE_Msk, - UART_SR_TXE_Msk, cfg->timeout); + err = whal_Reg32_ReadPoll(base, UART_SR_REG, UART_SR_TXE_Msk, + UART_SR_TXE_Msk, cfg->timeout); if (err) return err; /* Write byte to data register (must not read DR — use pure write) */ - whal_Reg_Write(base, UART_DR_REG, buf[i]); + whal_Reg32_Write(base, UART_DR_REG, buf[i]); } /* Wait for the last frame to finish shifting out */ - return whal_Reg_ReadPoll(base, UART_SR_REG, UART_SR_TC_Msk, - UART_SR_TC_Msk, cfg->timeout); + return whal_Reg32_ReadPoll(base, UART_SR_REG, UART_SR_TC_Msk, + UART_SR_TC_Msk, cfg->timeout); } whal_Error whal_Stm32f4_Uart_Recv(whal_Uart *uartDev, void *data, size_t dataSz) { uint8_t *buf = data; - size_t d; + uint32_t d; size_t sr; #ifdef WHAL_CFG_STM32F4_UART_SINGLE_INSTANCE const whal_Stm32f4_Uart_Cfg *cfg = (const whal_Stm32f4_Uart_Cfg *)whal_Stm32f4_Uart_Dev.cfg; - size_t base = whal_Stm32f4_Uart_Dev.base; + uintptr_t base = whal_Stm32f4_Uart_Dev.base; (void)uartDev; if (!data) return WHAL_EINVAL; #else - size_t base; + uintptr_t base; whal_Stm32f4_Uart_Cfg *cfg; if (!uartDev || !uartDev->cfg || !data) @@ -231,16 +231,16 @@ whal_Error whal_Stm32f4_Uart_Recv(whal_Uart *uartDev, void *data, size_t dataSz) for (size_t i = 0; i < dataSz; ++i) { /* Wait for receive data register not empty */ - whal_Error err = whal_Reg_ReadPoll(base, UART_SR_REG, - UART_SR_RXNE_Msk, - UART_SR_RXNE_Msk, cfg->timeout); + whal_Error err = whal_Reg32_ReadPoll(base, UART_SR_REG, + UART_SR_RXNE_Msk, + UART_SR_RXNE_Msk, cfg->timeout); if (err) return err; /* Reading SR then DR also clears the error flags */ - sr = whal_Reg_Read(base, UART_SR_REG); - whal_Reg_Get(base, UART_DR_REG, - UART_DR_Msk, UART_DR_Pos, &d); + sr = whal_Reg32_Read(base, UART_SR_REG); + whal_Reg32_Get(base, UART_DR_REG, + UART_DR_Msk, UART_DR_Pos, &d); buf[i] = d; diff --git a/src/uart/stm32wb_uart.c b/src/uart/stm32wb_uart.c index ca4e06d7..d05e60f4 100644 --- a/src/uart/stm32wb_uart.c +++ b/src/uart/stm32wb_uart.c @@ -106,11 +106,11 @@ whal_Error whal_Stm32wb_Uart_Init(whal_Uart *uartDev) #ifdef WHAL_CFG_STM32WB_UART_SINGLE_INSTANCE const whal_Stm32wb_Uart_Cfg *cfg = (const whal_Stm32wb_Uart_Cfg *)whal_Stm32wb_Uart_Dev.cfg; - size_t base = whal_Stm32wb_Uart_Dev.base; + uintptr_t base = whal_Stm32wb_Uart_Dev.base; (void)uartDev; #else whal_Stm32wb_Uart_Cfg *cfg; - size_t base; + uintptr_t base; if (!uartDev || !uartDev->cfg) { return WHAL_EINVAL; @@ -122,16 +122,16 @@ whal_Error whal_Stm32wb_Uart_Init(whal_Uart *uartDev) brr = cfg->brr; - whal_Reg_Update(base, UART_BRR_REG, - UART_BRR_Msk, - whal_SetBits(UART_BRR_Msk, UART_BRR_Pos, brr)); - whal_Reg_Update(base, UART_CR1_REG, - UART_CR1_UE_Msk | UART_CR1_RE_Msk | UART_CR1_TE_Msk | - UART_CR1_FIFOEN_Msk, - whal_SetBits(UART_CR1_UE_Msk, UART_CR1_UE_Pos, 1) | - whal_SetBits(UART_CR1_RE_Msk, UART_CR1_RE_Pos, 1) | - whal_SetBits(UART_CR1_TE_Msk, UART_CR1_TE_Pos, 1) | - whal_SetBits(UART_CR1_FIFOEN_Msk, UART_CR1_FIFOEN_Pos, 1)); + whal_Reg32_Update(base, UART_BRR_REG, + UART_BRR_Msk, + whal_SetBits(UART_BRR_Msk, UART_BRR_Pos, brr)); + whal_Reg32_Update(base, UART_CR1_REG, + UART_CR1_UE_Msk | UART_CR1_RE_Msk | UART_CR1_TE_Msk | + UART_CR1_FIFOEN_Msk, + whal_SetBits(UART_CR1_UE_Msk, UART_CR1_UE_Pos, 1) | + whal_SetBits(UART_CR1_RE_Msk, UART_CR1_RE_Pos, 1) | + whal_SetBits(UART_CR1_TE_Msk, UART_CR1_TE_Pos, 1) | + whal_SetBits(UART_CR1_FIFOEN_Msk, UART_CR1_FIFOEN_Pos, 1)); return WHAL_SUCCESS; } @@ -139,10 +139,10 @@ whal_Error whal_Stm32wb_Uart_Init(whal_Uart *uartDev) whal_Error whal_Stm32wb_Uart_Deinit(whal_Uart *uartDev) { #ifdef WHAL_CFG_STM32WB_UART_SINGLE_INSTANCE - size_t base = whal_Stm32wb_Uart_Dev.base; + uintptr_t base = whal_Stm32wb_Uart_Dev.base; (void)uartDev; #else - size_t base; + uintptr_t base; if (!uartDev) { return WHAL_EINVAL; @@ -151,17 +151,17 @@ whal_Error whal_Stm32wb_Uart_Deinit(whal_Uart *uartDev) base = uartDev->base; #endif - whal_Reg_Update(base, UART_CR1_REG, - UART_CR1_UE_Msk | UART_CR1_RE_Msk | UART_CR1_TE_Msk, - whal_SetBits(UART_CR1_UE_Msk, UART_CR1_UE_Pos, 0) | - whal_SetBits(UART_CR1_RE_Msk, UART_CR1_RE_Pos, 0) | - whal_SetBits(UART_CR1_TE_Msk, UART_CR1_TE_Pos, 0)); + whal_Reg32_Update(base, UART_CR1_REG, + UART_CR1_UE_Msk | UART_CR1_RE_Msk | UART_CR1_TE_Msk, + whal_SetBits(UART_CR1_UE_Msk, UART_CR1_UE_Pos, 0) | + whal_SetBits(UART_CR1_RE_Msk, UART_CR1_RE_Pos, 0) | + whal_SetBits(UART_CR1_TE_Msk, UART_CR1_TE_Pos, 0)); /* FIFOEN is only writable while UE is 0 */ - whal_Reg_Update(base, UART_CR1_REG, UART_CR1_FIFOEN_Msk, - whal_SetBits(UART_CR1_FIFOEN_Msk, UART_CR1_FIFOEN_Pos, 0)); + whal_Reg32_Update(base, UART_CR1_REG, UART_CR1_FIFOEN_Msk, + whal_SetBits(UART_CR1_FIFOEN_Msk, UART_CR1_FIFOEN_Pos, 0)); - whal_Reg_Update(base, UART_BRR_REG, + whal_Reg32_Update(base, UART_BRR_REG, UART_BRR_Msk, whal_SetBits(UART_BRR_Msk, UART_BRR_Pos, 0)); @@ -174,14 +174,14 @@ whal_Error whal_Stm32wb_Uart_Send(whal_Uart *uartDev, const void *data, size_t d #ifdef WHAL_CFG_STM32WB_UART_SINGLE_INSTANCE const whal_Stm32wb_Uart_Cfg *cfg = (const whal_Stm32wb_Uart_Cfg *)whal_Stm32wb_Uart_Dev.cfg; - size_t base = whal_Stm32wb_Uart_Dev.base; + uintptr_t base = whal_Stm32wb_Uart_Dev.base; (void)uartDev; if (!data) { return WHAL_EINVAL; } #else - size_t base; + uintptr_t base; whal_Stm32wb_Uart_Cfg *cfg; if (!uartDev || !uartDev->cfg || !data) { @@ -194,11 +194,11 @@ whal_Error whal_Stm32wb_Uart_Send(whal_Uart *uartDev, const void *data, size_t d for (size_t i = 0; i < dataSz; ++i) { whal_Error err; - whal_Reg_Update(base, UART_TDR_REG, UART_TDR_Msk, - whal_SetBits(UART_TDR_Msk, UART_TDR_Pos, buf[i])); + whal_Reg32_Update(base, UART_TDR_REG, UART_TDR_Msk, + whal_SetBits(UART_TDR_Msk, UART_TDR_Pos, buf[i])); - err = whal_Reg_ReadPoll(base, UART_ISR_REG, UART_ISR_TC_Msk, - UART_ISR_TC_Msk, cfg->timeout); + err = whal_Reg32_ReadPoll(base, UART_ISR_REG, UART_ISR_TC_Msk, + UART_ISR_TC_Msk, cfg->timeout); if (err) return err; } @@ -212,14 +212,14 @@ whal_Error whal_Stm32wb_Uart_Recv(whal_Uart *uartDev, void *data, size_t dataSz) #ifdef WHAL_CFG_STM32WB_UART_SINGLE_INSTANCE const whal_Stm32wb_Uart_Cfg *cfg = (const whal_Stm32wb_Uart_Cfg *)whal_Stm32wb_Uart_Dev.cfg; - size_t base = whal_Stm32wb_Uart_Dev.base; + uintptr_t base = whal_Stm32wb_Uart_Dev.base; (void)uartDev; if (!data) { return WHAL_EINVAL; } #else - size_t base; + uintptr_t base; whal_Stm32wb_Uart_Cfg *cfg; if (!uartDev || !uartDev->cfg || !data) { @@ -229,25 +229,25 @@ whal_Error whal_Stm32wb_Uart_Recv(whal_Uart *uartDev, void *data, size_t dataSz) base = uartDev->base; cfg = (whal_Stm32wb_Uart_Cfg *)uartDev->cfg; #endif - size_t d; + uint32_t d; size_t isr; for (size_t i = 0; i < dataSz; ++i) { - whal_Error err = whal_Reg_ReadPoll(base, UART_ISR_REG, - UART_ISR_RXFNE_Msk, - UART_ISR_RXFNE_Msk, cfg->timeout); + whal_Error err = whal_Reg32_ReadPoll(base, UART_ISR_REG, + UART_ISR_RXFNE_Msk, + UART_ISR_RXFNE_Msk, cfg->timeout); if (err) return err; - isr = whal_Reg_Read(base, UART_ISR_REG); + isr = whal_Reg32_Read(base, UART_ISR_REG); - whal_Reg_Get(base, UART_RDR_REG, - UART_RDR_Msk, UART_RDR_Pos, &d); + whal_Reg32_Get(base, UART_RDR_REG, + UART_RDR_Msk, UART_RDR_Pos, &d); buf[i] = d; if (isr & UART_ISR_ERR_Msk) { - whal_Reg_Write(base, UART_ICR_REG, isr & UART_ISR_ERR_Msk); + whal_Reg32_Write(base, UART_ICR_REG, isr & UART_ISR_ERR_Msk); return WHAL_EHARDWARE; } } diff --git a/src/uart/stm32wb_uart_dma.c b/src/uart/stm32wb_uart_dma.c index 104d778c..8d1b66ee 100644 --- a/src/uart/stm32wb_uart_dma.c +++ b/src/uart/stm32wb_uart_dma.c @@ -86,14 +86,14 @@ whal_Error whal_Stm32wb_UartDma_SendAsync(whal_Uart *uartDev, const void *data, #ifdef WHAL_CFG_STM32WB_UART_DMA_SINGLE_INSTANCE whal_Stm32wb_UartDma_Cfg *cfg = (whal_Stm32wb_UartDma_Cfg *)whal_Stm32wb_UartDma_Dev.cfg; - size_t base = whal_Stm32wb_UartDma_Dev.base; + uintptr_t base = whal_Stm32wb_UartDma_Dev.base; (void)uartDev; if (!data || dataSz > UINT16_MAX) return WHAL_EINVAL; #else whal_Stm32wb_UartDma_Cfg *cfg; - size_t base; + uintptr_t base; if (!uartDev || !uartDev->cfg || !data || dataSz > UINT16_MAX) return WHAL_EINVAL; @@ -120,12 +120,12 @@ whal_Error whal_Stm32wb_UartDma_SendAsync(whal_Uart *uartDev, const void *data, return err; } - whal_Reg_Update(base, UART_CR3_REG, UART_CR3_DMAT_Msk, - UART_CR3_DMAT_Msk); + whal_Reg32_Update(base, UART_CR3_REG, UART_CR3_DMAT_Msk, + UART_CR3_DMAT_Msk); err = whal_Dma_Start(cfg->dma, cfg->txCh); if (err) { - whal_Reg_Update(base, UART_CR3_REG, UART_CR3_DMAT_Msk, 0); + whal_Reg32_Update(base, UART_CR3_REG, UART_CR3_DMAT_Msk, 0); cfg->txResult = err; return err; } @@ -140,14 +140,14 @@ whal_Error whal_Stm32wb_UartDma_RecvAsync(whal_Uart *uartDev, void *data, #ifdef WHAL_CFG_STM32WB_UART_DMA_SINGLE_INSTANCE whal_Stm32wb_UartDma_Cfg *cfg = (whal_Stm32wb_UartDma_Cfg *)whal_Stm32wb_UartDma_Dev.cfg; - size_t base = whal_Stm32wb_UartDma_Dev.base; + uintptr_t base = whal_Stm32wb_UartDma_Dev.base; (void)uartDev; if (!data || dataSz > UINT16_MAX) return WHAL_EINVAL; #else whal_Stm32wb_UartDma_Cfg *cfg; - size_t base; + uintptr_t base; if (!uartDev || !uartDev->cfg || !data || dataSz > UINT16_MAX) return WHAL_EINVAL; @@ -175,13 +175,13 @@ whal_Error whal_Stm32wb_UartDma_RecvAsync(whal_Uart *uartDev, void *data, } /* Drop line errors latched before this transfer */ - whal_Reg_Write(base, UART_ICR_REG, UART_ISR_ERR_Msk); - whal_Reg_Update(base, UART_CR3_REG, UART_CR3_DMAR_Msk, - UART_CR3_DMAR_Msk); + whal_Reg32_Write(base, UART_ICR_REG, UART_ISR_ERR_Msk); + whal_Reg32_Update(base, UART_CR3_REG, UART_CR3_DMAR_Msk, + UART_CR3_DMAR_Msk); err = whal_Dma_Start(cfg->dma, cfg->rxCh); if (err) { - whal_Reg_Update(base, UART_CR3_REG, UART_CR3_DMAR_Msk, 0); + whal_Reg32_Update(base, UART_CR3_REG, UART_CR3_DMAR_Msk, 0); cfg->rxResult = err; return err; } @@ -193,7 +193,7 @@ whal_Error whal_Stm32wb_UartDma_Send(whal_Uart *uartDev, const void *data, size_t dataSz) { whal_Stm32wb_UartDma_Cfg *cfg; - size_t base; + uintptr_t base; whal_Error err; err = whal_Stm32wb_UartDma_SendAsync(uartDev, data, dataSz); @@ -221,12 +221,12 @@ whal_Error whal_Stm32wb_UartDma_Send(whal_Uart *uartDev, const void *data, goto cleanup; } - err = whal_Reg_ReadPoll(base, UART_ISR_REG, - UART_ISR_TC_Msk, UART_ISR_TC_Msk, cfg->base.timeout); + err = whal_Reg32_ReadPoll(base, UART_ISR_REG, + UART_ISR_TC_Msk, UART_ISR_TC_Msk, cfg->base.timeout); cleanup: whal_Dma_Stop(cfg->dma, cfg->txCh); - whal_Reg_Update(base, UART_CR3_REG, UART_CR3_DMAT_Msk, 0); + whal_Reg32_Update(base, UART_CR3_REG, UART_CR3_DMAT_Msk, 0); cfg->txResult = err; return err; @@ -236,7 +236,7 @@ whal_Error whal_Stm32wb_UartDma_Recv(whal_Uart *uartDev, void *data, size_t dataSz) { whal_Stm32wb_UartDma_Cfg *cfg; - size_t base; + uintptr_t base; whal_Error err; size_t isr; @@ -262,16 +262,16 @@ whal_Error whal_Stm32wb_UartDma_Recv(whal_Uart *uartDev, void *data, err = cfg->rxResult; if (err == WHAL_SUCCESS) { - isr = whal_Reg_Read(base, UART_ISR_REG) & UART_ISR_ERR_Msk; + isr = whal_Reg32_Read(base, UART_ISR_REG) & UART_ISR_ERR_Msk; if (isr) { - whal_Reg_Write(base, UART_ICR_REG, isr); + whal_Reg32_Write(base, UART_ICR_REG, isr); err = WHAL_EHARDWARE; } } cleanup: whal_Dma_Stop(cfg->dma, cfg->rxCh); - whal_Reg_Update(base, UART_CR3_REG, UART_CR3_DMAR_Msk, 0); + whal_Reg32_Update(base, UART_CR3_REG, UART_CR3_DMAR_Msk, 0); cfg->rxResult = err; return err; @@ -280,7 +280,7 @@ whal_Error whal_Stm32wb_UartDma_Recv(whal_Uart *uartDev, void *data, whal_Error whal_Stm32wb_UartDma_Deinit(whal_Uart *uartDev) { whal_Stm32wb_UartDma_Cfg *cfg; - size_t base; + uintptr_t base; #ifdef WHAL_CFG_STM32WB_UART_DMA_SINGLE_INSTANCE cfg = (whal_Stm32wb_UartDma_Cfg *)whal_Stm32wb_UartDma_Dev.cfg; @@ -294,8 +294,8 @@ whal_Error whal_Stm32wb_UartDma_Deinit(whal_Uart *uartDev) #endif /* Abandon any in-flight transfer so a later Init starts clean */ - whal_Reg_Update(base, UART_CR3_REG, - UART_CR3_DMAT_Msk | UART_CR3_DMAR_Msk, 0); + whal_Reg32_Update(base, UART_CR3_REG, + UART_CR3_DMAT_Msk | UART_CR3_DMAR_Msk, 0); whal_Dma_Stop(cfg->dma, cfg->txCh); whal_Dma_Stop(cfg->dma, cfg->rxCh); cfg->txResult = WHAL_SUCCESS; diff --git a/src/uart/stm32wba_uart_dma.c b/src/uart/stm32wba_uart_dma.c index ebf3da2c..936e9537 100644 --- a/src/uart/stm32wba_uart_dma.c +++ b/src/uart/stm32wba_uart_dma.c @@ -78,14 +78,14 @@ whal_Error whal_Stm32wba_UartDma_SendAsync(whal_Uart *uartDev, const void *data, #ifdef WHAL_CFG_STM32WBA_UART_DMA_SINGLE_INSTANCE whal_Stm32wba_UartDma_Cfg *cfg = (whal_Stm32wba_UartDma_Cfg *)whal_Stm32wba_UartDma_Dev.cfg; - size_t base = whal_Stm32wba_UartDma_Dev.base; + uintptr_t base = whal_Stm32wba_UartDma_Dev.base; (void)uartDev; if (!data || dataSz > 0xFFFF) return WHAL_EINVAL; #else whal_Stm32wba_UartDma_Cfg *cfg; - size_t base; + uintptr_t base; if (!uartDev || !uartDev->cfg || !data || dataSz > 0xFFFF) return WHAL_EINVAL; @@ -129,10 +129,10 @@ whal_Error whal_Stm32wba_UartDma_SendAsync(whal_Uart *uartDev, const void *data, return err; } - whal_Reg_Write(base, UART_ICR_REG, UART_ICR_TCCF_Msk); + whal_Reg32_Write(base, UART_ICR_REG, UART_ICR_TCCF_Msk); - whal_Reg_Update(base, UART_CR3_REG, UART_CR3_DMAT_Msk, - UART_CR3_DMAT_Msk); + whal_Reg32_Update(base, UART_CR3_REG, UART_CR3_DMAT_Msk, + UART_CR3_DMAT_Msk); return WHAL_SUCCESS; } @@ -144,14 +144,14 @@ whal_Error whal_Stm32wba_UartDma_RecvAsync(whal_Uart *uartDev, void *data, #ifdef WHAL_CFG_STM32WBA_UART_DMA_SINGLE_INSTANCE whal_Stm32wba_UartDma_Cfg *cfg = (whal_Stm32wba_UartDma_Cfg *)whal_Stm32wba_UartDma_Dev.cfg; - size_t base = whal_Stm32wba_UartDma_Dev.base; + uintptr_t base = whal_Stm32wba_UartDma_Dev.base; (void)uartDev; if (!data || dataSz > 0xFFFF) return WHAL_EINVAL; #else whal_Stm32wba_UartDma_Cfg *cfg; - size_t base; + uintptr_t base; if (!uartDev || !uartDev->cfg || !data || dataSz > 0xFFFF) return WHAL_EINVAL; @@ -184,13 +184,13 @@ whal_Error whal_Stm32wba_UartDma_RecvAsync(whal_Uart *uartDev, void *data, } /* Drop line errors latched before this transfer */ - whal_Reg_Write(base, UART_ICR_REG, UART_ISR_ERR_Msk); - whal_Reg_Update(base, UART_CR3_REG, UART_CR3_DMAR_Msk, - UART_CR3_DMAR_Msk); + whal_Reg32_Write(base, UART_ICR_REG, UART_ISR_ERR_Msk); + whal_Reg32_Update(base, UART_CR3_REG, UART_CR3_DMAR_Msk, + UART_CR3_DMAR_Msk); err = whal_Dma_Start(cfg->dma, cfg->rxCh); if (err) { - whal_Reg_Update(base, UART_CR3_REG, UART_CR3_DMAR_Msk, 0); + whal_Reg32_Update(base, UART_CR3_REG, UART_CR3_DMAR_Msk, 0); cfg->rxResult = err; return err; } @@ -202,7 +202,7 @@ whal_Error whal_Stm32wba_UartDma_Send(whal_Uart *uartDev, const void *data, size_t dataSz) { whal_Stm32wba_UartDma_Cfg *cfg; - size_t base; + uintptr_t base; whal_Error err; whal_Error stopErr; @@ -233,16 +233,16 @@ whal_Error whal_Stm32wba_UartDma_Send(whal_Uart *uartDev, const void *data, /* Wait for TC (transmission complete) so the last byte has shifted out * before we tear down the DMA channel */ - err = whal_Reg_ReadPoll(base, UART_ISR_REG, - UART_ISR_TC_Msk, UART_ISR_TC_Msk, - cfg->base.timeout); + err = whal_Reg32_ReadPoll(base, UART_ISR_REG, + UART_ISR_TC_Msk, UART_ISR_TC_Msk, + cfg->base.timeout); cleanup: /* A failed stop wins: the channel may still own the caller's buffer */ stopErr = whal_Dma_Stop(cfg->dma, cfg->txCh); if (stopErr) err = stopErr; - whal_Reg_Update(base, UART_CR3_REG, UART_CR3_DMAT_Msk, 0); + whal_Reg32_Update(base, UART_CR3_REG, UART_CR3_DMAT_Msk, 0); cfg->txResult = err; return err; @@ -252,7 +252,7 @@ whal_Error whal_Stm32wba_UartDma_Recv(whal_Uart *uartDev, void *data, size_t dataSz) { whal_Stm32wba_UartDma_Cfg *cfg; - size_t base; + uintptr_t base; whal_Error err; whal_Error stopErr; size_t isr; @@ -279,9 +279,9 @@ whal_Error whal_Stm32wba_UartDma_Recv(whal_Uart *uartDev, void *data, err = cfg->rxResult; if (err == WHAL_SUCCESS) { - isr = whal_Reg_Read(base, UART_ISR_REG) & UART_ISR_ERR_Msk; + isr = whal_Reg32_Read(base, UART_ISR_REG) & UART_ISR_ERR_Msk; if (isr) { - whal_Reg_Write(base, UART_ICR_REG, isr); + whal_Reg32_Write(base, UART_ICR_REG, isr); err = WHAL_EHARDWARE; } } @@ -291,7 +291,7 @@ whal_Error whal_Stm32wba_UartDma_Recv(whal_Uart *uartDev, void *data, stopErr = whal_Dma_Stop(cfg->dma, cfg->rxCh); if (stopErr) err = stopErr; - whal_Reg_Update(base, UART_CR3_REG, UART_CR3_DMAR_Msk, 0); + whal_Reg32_Update(base, UART_CR3_REG, UART_CR3_DMAR_Msk, 0); cfg->rxResult = err; return err; @@ -300,7 +300,7 @@ whal_Error whal_Stm32wba_UartDma_Recv(whal_Uart *uartDev, void *data, whal_Error whal_Stm32wba_UartDma_Deinit(whal_Uart *uartDev) { whal_Stm32wba_UartDma_Cfg *cfg; - size_t base; + uintptr_t base; whal_Error err; whal_Error stepErr; @@ -316,8 +316,8 @@ whal_Error whal_Stm32wba_UartDma_Deinit(whal_Uart *uartDev) #endif /* Abandon any in-flight transfer so a later Init starts clean */ - whal_Reg_Update(base, UART_CR3_REG, - UART_CR3_DMAT_Msk | UART_CR3_DMAR_Msk, 0); + whal_Reg32_Update(base, UART_CR3_REG, + UART_CR3_DMAT_Msk | UART_CR3_DMAR_Msk, 0); err = whal_Dma_Stop(cfg->dma, cfg->txCh); stepErr = whal_Dma_Stop(cfg->dma, cfg->rxCh); if (stepErr && !err) diff --git a/src/watchdog/stm32f0_wwdg.c b/src/watchdog/stm32f0_wwdg.c index 2ff5be04..f28f74c4 100644 --- a/src/watchdog/stm32f0_wwdg.c +++ b/src/watchdog/stm32f0_wwdg.c @@ -52,7 +52,7 @@ whal_Error whal_Stm32f0_Wwdg_Init(whal_Watchdog *wdgDev) { const whal_Stm32f0_Wwdg_Cfg *cfg = (const whal_Stm32f0_Wwdg_Cfg *)whal_Stm32f0_Wwdg_Dev.cfg; - size_t base = whal_Stm32f0_Wwdg_Dev.base; + uintptr_t base = whal_Stm32f0_Wwdg_Dev.base; (void)wdgDev; /* Counter and window must keep T6 set or the MCU resets immediately */ @@ -60,11 +60,11 @@ whal_Error whal_Stm32f0_Wwdg_Init(whal_Watchdog *wdgDev) cfg->counter < 0x40 || cfg->counter > 0x7F) return WHAL_EINVAL; - whal_Reg_Update(base, CFR_REG, CFR_W_Msk | CFR_WDGTB_Msk, - whal_SetBits(CFR_W_Msk, CFR_W_Pos, cfg->window) | - whal_SetBits(CFR_WDGTB_Msk, CFR_WDGTB_Pos, cfg->prescaler)); + whal_Reg32_Update(base, CFR_REG, CFR_W_Msk | CFR_WDGTB_Msk, + whal_SetBits(CFR_W_Msk, CFR_W_Pos, cfg->window) | + whal_SetBits(CFR_WDGTB_Msk, CFR_WDGTB_Pos, cfg->prescaler)); - whal_Reg_Write(base, CR_REG, CR_WDGA_Msk | cfg->counter); + whal_Reg32_Write(base, CR_REG, CR_WDGA_Msk | cfg->counter); return WHAL_SUCCESS; } @@ -79,10 +79,10 @@ whal_Error whal_Stm32f0_Wwdg_Refresh(whal_Watchdog *wdgDev) { const whal_Stm32f0_Wwdg_Cfg *cfg = (const whal_Stm32f0_Wwdg_Cfg *)whal_Stm32f0_Wwdg_Dev.cfg; - size_t base = whal_Stm32f0_Wwdg_Dev.base; + uintptr_t base = whal_Stm32f0_Wwdg_Dev.base; (void)wdgDev; - whal_Reg_Write(base, CR_REG, CR_WDGA_Msk | cfg->counter); + whal_Reg32_Write(base, CR_REG, CR_WDGA_Msk | cfg->counter); return WHAL_SUCCESS; } diff --git a/src/watchdog/stm32wb_iwdg.c b/src/watchdog/stm32wb_iwdg.c index 769097f1..49062e3d 100644 --- a/src/watchdog/stm32wb_iwdg.c +++ b/src/watchdog/stm32wb_iwdg.c @@ -68,7 +68,7 @@ whal_Error whal_Stm32wb_Iwdg_Init(whal_Watchdog *wdgDev) { const whal_Stm32wb_Iwdg_Cfg *cfg = (const whal_Stm32wb_Iwdg_Cfg *)whal_Stm32wb_Iwdg_Dev.cfg; - size_t base = whal_Stm32wb_Iwdg_Dev.base; + uintptr_t base = whal_Stm32wb_Iwdg_Dev.base; whal_Error err; (void)wdgDev; @@ -77,26 +77,26 @@ whal_Error whal_Stm32wb_Iwdg_Init(whal_Watchdog *wdgDev) } /* Start the IWDG */ - whal_Reg_Write(base, IWDG_KR_REG, IWDG_KEY_START); + whal_Reg32_Write(base, IWDG_KR_REG, IWDG_KEY_START); /* Enable register access */ - whal_Reg_Write(base, IWDG_KR_REG, IWDG_KEY_ACCESS); + whal_Reg32_Write(base, IWDG_KR_REG, IWDG_KEY_ACCESS); /* Set prescaler */ - whal_Reg_Write(base, IWDG_PR_REG, cfg->prescaler); + whal_Reg32_Write(base, IWDG_PR_REG, cfg->prescaler); /* Set reload value */ - whal_Reg_Write(base, IWDG_RLR_REG, cfg->reload); + whal_Reg32_Write(base, IWDG_RLR_REG, cfg->reload); /* Wait for registers to update */ - err = whal_Reg_ReadPoll(base, IWDG_SR_REG, - IWDG_SR_PVU_Msk | IWDG_SR_RVU_Msk, 0, - cfg->timeout); + err = whal_Reg32_ReadPoll(base, IWDG_SR_REG, + IWDG_SR_PVU_Msk | IWDG_SR_RVU_Msk, 0, + cfg->timeout); if (err) return err; /* Refresh counter with new reload value */ - whal_Reg_Write(base, IWDG_KR_REG, IWDG_KEY_RELOAD); + whal_Reg32_Write(base, IWDG_KR_REG, IWDG_KEY_RELOAD); return WHAL_SUCCESS; } @@ -110,7 +110,7 @@ whal_Error whal_Stm32wb_Iwdg_Deinit(whal_Watchdog *wdgDev) whal_Error whal_Stm32wb_Iwdg_Refresh(whal_Watchdog *wdgDev) { (void)wdgDev; - whal_Reg_Write(whal_Stm32wb_Iwdg_Dev.base, IWDG_KR_REG, IWDG_KEY_RELOAD); + whal_Reg32_Write(whal_Stm32wb_Iwdg_Dev.base, IWDG_KR_REG, IWDG_KEY_RELOAD); return WHAL_SUCCESS; } diff --git a/src/watchdog/stm32wb_wwdg.c b/src/watchdog/stm32wb_wwdg.c index 519c1285..aceebcbd 100644 --- a/src/watchdog/stm32wb_wwdg.c +++ b/src/watchdog/stm32wb_wwdg.c @@ -58,7 +58,7 @@ whal_Error whal_Stm32wb_Wwdg_Init(whal_Watchdog *wdgDev) { const whal_Stm32wb_Wwdg_Cfg *cfg = (const whal_Stm32wb_Wwdg_Cfg *)whal_Stm32wb_Wwdg_Dev.cfg; - size_t base = whal_Stm32wb_Wwdg_Dev.base; + uintptr_t base = whal_Stm32wb_Wwdg_Dev.base; (void)wdgDev; /* Counter and window must keep T6 set or the MCU resets immediately */ @@ -67,14 +67,14 @@ whal_Error whal_Stm32wb_Wwdg_Init(whal_Watchdog *wdgDev) return WHAL_EINVAL; /* Configure window and prescaler */ - whal_Reg_Update(base, CFR_REG, CFR_W_Msk | CFR_WDGTB_Msk, - whal_SetBits(CFR_W_Msk, CFR_W_Pos, cfg->window) | - whal_SetBits(CFR_WDGTB_Msk, CFR_WDGTB_Pos, cfg->prescaler)); + whal_Reg32_Update(base, CFR_REG, CFR_W_Msk | CFR_WDGTB_Msk, + whal_SetBits(CFR_W_Msk, CFR_W_Pos, cfg->window) | + whal_SetBits(CFR_WDGTB_Msk, CFR_WDGTB_Pos, cfg->prescaler)); /* Set counter and enable WWDG */ - whal_Reg_Update(base, CR_REG, CR_T_Msk | CR_WDGA_Msk, - whal_SetBits(CR_T_Msk, CR_T_Pos, cfg->counter) | - whal_SetBits(CR_WDGA_Msk, CR_WDGA_Pos, 1)); + whal_Reg32_Update(base, CR_REG, CR_T_Msk | CR_WDGA_Msk, + whal_SetBits(CR_T_Msk, CR_T_Pos, cfg->counter) | + whal_SetBits(CR_WDGA_Msk, CR_WDGA_Pos, 1)); return WHAL_SUCCESS; } @@ -89,11 +89,11 @@ whal_Error whal_Stm32wb_Wwdg_Refresh(whal_Watchdog *wdgDev) { const whal_Stm32wb_Wwdg_Cfg *cfg = (const whal_Stm32wb_Wwdg_Cfg *)whal_Stm32wb_Wwdg_Dev.cfg; - size_t base = whal_Stm32wb_Wwdg_Dev.base; + uintptr_t base = whal_Stm32wb_Wwdg_Dev.base; (void)wdgDev; - whal_Reg_Update(base, CR_REG, CR_T_Msk, - whal_SetBits(CR_T_Msk, CR_T_Pos, cfg->counter)); + whal_Reg32_Update(base, CR_REG, CR_T_Msk, + whal_SetBits(CR_T_Msk, CR_T_Pos, cfg->counter)); return WHAL_SUCCESS; } diff --git a/tests/clock/test_pic32cz_clock.c b/tests/clock/test_pic32cz_clock.c index 574ebfff..04ce2903 100644 --- a/tests/clock/test_pic32cz_clock.c +++ b/tests/clock/test_pic32cz_clock.c @@ -43,32 +43,32 @@ static void Test_Clock_EnableDisable(void) }; /* Save original state */ - size_t origChen = 0; - whal_Reg_Get(WHAL_PIC32CZ_CLOCK_BASE, GCLK_PCHCTRL_OFFSET(25), - GCLK_PCHCTRL_CHEN_Msk, GCLK_PCHCTRL_CHEN_Pos, &origChen); + uint32_t origChen = 0; + whal_Reg32_Get(WHAL_PIC32CZ_CLOCK_BASE, GCLK_PCHCTRL_OFFSET(25), + GCLK_PCHCTRL_CHEN_Msk, GCLK_PCHCTRL_CHEN_Pos, &origChen); - size_t origMclk = 0; - whal_Reg_Get(WHAL_PIC32CZ_CLOCK_BASE, MCLK_CLKMSK_OFFSET(1), - (1UL << 3), 3, &origMclk); + uint32_t origMclk = 0; + whal_Reg32_Get(WHAL_PIC32CZ_CLOCK_BASE, MCLK_CLKMSK_OFFSET(1), + (1UL << 3), 3, &origMclk); - size_t val = 0; + uint32_t val = 0; /* Enable and verify */ WHAL_ASSERT_EQ(whal_Pic32cz_Clock_EnablePeriphClk(&testClk), WHAL_SUCCESS); - whal_Reg_Get(WHAL_PIC32CZ_CLOCK_BASE, GCLK_PCHCTRL_OFFSET(25), - GCLK_PCHCTRL_CHEN_Msk, GCLK_PCHCTRL_CHEN_Pos, &val); + whal_Reg32_Get(WHAL_PIC32CZ_CLOCK_BASE, GCLK_PCHCTRL_OFFSET(25), + GCLK_PCHCTRL_CHEN_Msk, GCLK_PCHCTRL_CHEN_Pos, &val); WHAL_ASSERT_EQ(val, 1); - whal_Reg_Get(WHAL_PIC32CZ_CLOCK_BASE, MCLK_CLKMSK_OFFSET(1), - (1UL << 3), 3, &val); + whal_Reg32_Get(WHAL_PIC32CZ_CLOCK_BASE, MCLK_CLKMSK_OFFSET(1), + (1UL << 3), 3, &val); WHAL_ASSERT_EQ(val, 1); /* Disable and verify */ WHAL_ASSERT_EQ(whal_Pic32cz_Clock_DisablePeriphClk(&testClk), WHAL_SUCCESS); - whal_Reg_Get(WHAL_PIC32CZ_CLOCK_BASE, GCLK_PCHCTRL_OFFSET(25), - GCLK_PCHCTRL_CHEN_Msk, GCLK_PCHCTRL_CHEN_Pos, &val); + whal_Reg32_Get(WHAL_PIC32CZ_CLOCK_BASE, GCLK_PCHCTRL_OFFSET(25), + GCLK_PCHCTRL_CHEN_Msk, GCLK_PCHCTRL_CHEN_Pos, &val); WHAL_ASSERT_EQ(val, 0); /* Restore original state */ diff --git a/tests/clock/test_stm32wb_clock.c b/tests/clock/test_stm32wb_clock.c index 0054cfee..57fab608 100644 --- a/tests/clock/test_stm32wb_clock.c +++ b/tests/clock/test_stm32wb_clock.c @@ -31,20 +31,20 @@ static void Test_Clock_EnableDisable(void) whal_Stm32wb_Rcc_PeriphClk testClk = { WHAL_STM32WB55_GPIOA_GATE }; /* Save original state */ - size_t origVal = 0; - whal_Reg_Get(WHAL_STM32WB_RCC_BASE, 0x4C, (1 << 0), 0, &origVal); + uint32_t origVal = 0; + whal_Reg32_Get(WHAL_STM32WB_RCC_BASE, 0x4C, (1 << 0), 0, &origVal); /* Enable and verify */ WHAL_ASSERT_EQ(whal_Stm32wb_Rcc_EnablePeriphClk(&testClk), WHAL_SUCCESS); - size_t val = 0; - whal_Reg_Get(WHAL_STM32WB_RCC_BASE, 0x4C, (1 << 0), 0, &val); + uint32_t val = 0; + whal_Reg32_Get(WHAL_STM32WB_RCC_BASE, 0x4C, (1 << 0), 0, &val); WHAL_ASSERT_EQ(val, 1); /* Disable and verify */ WHAL_ASSERT_EQ(whal_Stm32wb_Rcc_DisablePeriphClk(&testClk), WHAL_SUCCESS); - whal_Reg_Get(WHAL_STM32WB_RCC_BASE, 0x4C, (1 << 0), 0, &val); + whal_Reg32_Get(WHAL_STM32WB_RCC_BASE, 0x4C, (1 << 0), 0, &val); WHAL_ASSERT_EQ(val, 0); /* Restore original state */ diff --git a/tests/core/Makefile b/tests/core/Makefile index 57f9ac13..937ca2c0 100644 --- a/tests/core/Makefile +++ b/tests/core/Makefile @@ -23,9 +23,6 @@ WHAL_DIR = $(CURDIR)/../.. INCLUDE = -I$(WHAL_DIR) CFLAGS += -Wall -Werror $(INCLUDE) -g3 -NOLEGACY_CFLAGS := $(CFLAGS) -# The core tests also cover the legacy whal_Reg_* API -CFLAGS += -DWHAL_CFG_REG_LEGACY TEST_SRC = main.c test_bitops.c test_dispatch.c test_endian.c test_reg.c test_timeout.c @@ -66,20 +63,9 @@ all: $(TARGET) $(TARGET): $(OBJECTS) $(CC) $(CFLAGS) -o $@ $(OBJECTS) -.PHONY: run clean legacy-off +.PHONY: run clean -# Without WHAL_CFG_REG_LEGACY, reg.c and whal_Reg32_* build and whal_Reg_* -# does not exist. -legacy-off: - $(CC) $(NOLEGACY_CFLAGS) -c -o /dev/null $(WHAL_DIR)/src/reg.c - printf '#include \nvoid f(void);\nvoid f(void) { whal_Reg32_Write(0, 0, 0); }\n' | \ - $(CC) $(NOLEGACY_CFLAGS) -x c -c -o /dev/null - - @if printf '#include \nvoid f(void);\nvoid f(void) { whal_Reg_Write(0, 0, 0); }\n' | \ - $(CC) $(NOLEGACY_CFLAGS) -x c -c -o /dev/null - 2>/dev/null; then \ - echo "legacy-off: FAIL, whal_Reg_Write exists"; exit 1; fi - @echo "legacy-off: PASS" - -run: legacy-off $(TARGET) +run: $(TARGET) ./$(TARGET) clean: diff --git a/tests/core/test_reg.c b/tests/core/test_reg.c index 7ffc478c..5ba68fb4 100644 --- a/tests/core/test_reg.c +++ b/tests/core/test_reg.c @@ -309,118 +309,6 @@ static void Test_Reg64_ReadPollClearTimeout(void) #endif /* WHAL_HAVE_REG64 */ -/* Legacy whal_Reg_* (WHAL_CFG_REG_LEGACY) */ - -#ifdef WHAL_CFG_REG_LEGACY - -static size_t LegacyBase(void) -{ - return (size_t)(uintptr_t)g_regs; -} - -static void Test_RegLegacy_WriteOnlyItsWord(void) -{ - ResetRegs(); - WHAL_ASSERT_EQ(whal_Reg_Write(LegacyBase(), 4, 0x12345678), - WHAL_SUCCESS); - WHAL_ASSERT_EQ(g_regs[1], 0x12345678); - WHAL_ASSERT_EQ(g_regs[0], SENTINEL); - WHAL_ASSERT_EQ(g_regs[2], SENTINEL); - /* The largest 32-bit value is accepted */ - WHAL_ASSERT_EQ(whal_Reg_Write(LegacyBase(), 4, 0xFFFFFFFFUL), - WHAL_SUCCESS); - WHAL_ASSERT_EQ(g_regs[1] == 0xFFFFFFFFUL, 1); - WHAL_ASSERT_EQ(g_regs[2], SENTINEL); -} - -static void Test_RegLegacy_ReadOnlyItsWord(void) -{ - ResetRegs(); - g_regs[1] = 0x8000BEEF; - WHAL_ASSERT_EQ(whal_Reg_Read(LegacyBase(), 4) == 0x8000BEEFUL, 1); -} - -static void Test_RegLegacy_UpdateOnlyItsField(void) -{ - ResetRegs(); - g_regs[1] = 0xFFFF00F0; - WHAL_ASSERT_EQ(whal_Reg_Update(LegacyBase(), 4, 0x000000F0, 0x00000050), - WHAL_SUCCESS); - WHAL_ASSERT_EQ(g_regs[1], 0xFFFF0050); - WHAL_ASSERT_EQ(g_regs[0], SENTINEL); - WHAL_ASSERT_EQ(g_regs[2], SENTINEL); -} - -static void Test_RegLegacy_GetField(void) -{ - size_t val = 0; - - ResetRegs(); - g_regs[1] = 0xFFFFFFFF; - WHAL_ASSERT_EQ(whal_Reg_Get(LegacyBase(), 4, 0x00003C00, 10, &val), - WHAL_SUCCESS); - WHAL_ASSERT_EQ(val, 0xF); - WHAL_ASSERT_EQ(whal_Reg_Get(LegacyBase(), 4, 0x80000000UL, 31, &val), - WHAL_SUCCESS); - WHAL_ASSERT_EQ(val, 1); -} - -static void Test_RegLegacy_ReadPoll(void) -{ - ResetRegs(); - g_regs[1] = 0x7F; - WHAL_ASSERT_EQ(whal_Reg_ReadPoll(LegacyBase(), 4, 0x80, 0, Bounded()), - WHAL_SUCCESS); - g_regs[1] = 0xFF; - WHAL_ASSERT_EQ(whal_Reg_ReadPoll(LegacyBase(), 4, 0x80, 0x80, Bounded()), - WHAL_SUCCESS); -} - -#ifndef WHAL_CFG_NO_TIMEOUT -static void Test_RegLegacy_ReadPollTimeout(void) -{ - ResetRegs(); - WHAL_ASSERT_EQ(whal_Reg_ReadPoll(LegacyBase(), 4, 0x80, 0x80, - RegTimeout(0, NULL)), - WHAL_ETIMEOUT); -} -#endif - -#if SIZE_MAX > 0xFFFFFFFFu -/* Low 32 bits are valid, so a missing check would write or match */ -#define LEGACY_WIDE (((size_t)1 << 32) | 0x80) - -static void Test_RegLegacy_WideRejected(void) -{ - size_t val = 123; - - ResetRegs(); - g_regs[1] = 0x11111111; - WHAL_ASSERT_EQ(whal_Reg_Write(LegacyBase(), 4, LEGACY_WIDE), WHAL_EINVAL); - WHAL_ASSERT_EQ(whal_Reg_Update(LegacyBase(), 4, LEGACY_WIDE, 0x80), - WHAL_EINVAL); - WHAL_ASSERT_EQ(whal_Reg_Update(LegacyBase(), 4, 0xFF, LEGACY_WIDE), - WHAL_EINVAL); - WHAL_ASSERT_EQ(g_regs[1], 0x11111111); - WHAL_ASSERT_EQ(g_regs[0], SENTINEL); - WHAL_ASSERT_EQ(g_regs[2], SENTINEL); - - WHAL_ASSERT_EQ(whal_Reg_Get(LegacyBase(), 4, LEGACY_WIDE, 0, &val), - WHAL_EINVAL); - WHAL_ASSERT_EQ(val == 0, 1); - - g_regs[1] = 0x80; - WHAL_ASSERT_EQ(whal_Reg_ReadPoll(LegacyBase(), 4, LEGACY_WIDE, 0x80, - Bounded()), - WHAL_EINVAL); - WHAL_ASSERT_EQ(whal_Reg_ReadPoll(LegacyBase(), 4, 0x80, LEGACY_WIDE, - Bounded()), - WHAL_EINVAL); -} -#endif /* SIZE_MAX > 0xFFFFFFFFu */ - -#endif /* WHAL_CFG_REG_LEGACY */ - void whal_Test_Reg(void) { WHAL_TEST_SUITE_START("reg"); @@ -448,20 +336,6 @@ void whal_Test_Reg(void) WHAL_TEST(Test_Reg64_ReadPollTimeout); WHAL_TEST(Test_Reg64_ReadPollClearTimeout); #endif -#endif - -#ifdef WHAL_CFG_REG_LEGACY - WHAL_TEST(Test_RegLegacy_WriteOnlyItsWord); - WHAL_TEST(Test_RegLegacy_ReadOnlyItsWord); - WHAL_TEST(Test_RegLegacy_UpdateOnlyItsField); - WHAL_TEST(Test_RegLegacy_GetField); - WHAL_TEST(Test_RegLegacy_ReadPoll); -#ifndef WHAL_CFG_NO_TIMEOUT - WHAL_TEST(Test_RegLegacy_ReadPollTimeout); -#endif -#if SIZE_MAX > 0xFFFFFFFFu - WHAL_TEST(Test_RegLegacy_WideRejected); -#endif #endif WHAL_TEST_SUITE_END(); } diff --git a/tests/crypto/test_stm32wba_hmac_sha256.c b/tests/crypto/test_stm32wba_hmac_sha256.c index 0f3e79a4..31234a57 100644 --- a/tests/crypto/test_stm32wba_hmac_sha256.c +++ b/tests/crypto/test_stm32wba_hmac_sha256.c @@ -40,12 +40,12 @@ static const uint8_t hmacKey[20] = { 0x0B, 0x0B, 0x0B, 0x0B, }; -static void ReadCsrs(size_t base, uint32_t *out, size_t first, size_t last) +static void ReadCsrs(uintptr_t base, uint32_t *out, size_t first, size_t last) { size_t i; for (i = first; i < last; i++) - out[i - first] = (uint32_t)whal_Reg_Read(base, HASH_CSR_REG(i)); + out[i - first] = (uint32_t)whal_Reg32_Read(base, HASH_CSR_REG(i)); } static int AnyNonZero(const uint32_t *words, size_t count) @@ -61,7 +61,7 @@ static int AnyNonZero(const uint32_t *words, size_t count) static void Test_Hash_InitChangesHmacContext(void) { - size_t base = whal_Stm32wba_Hash_Dev.base; + uintptr_t base = whal_Stm32wba_Hash_Dev.base; uint32_t before[HASH_CSR_COUNT]; uint32_t after[HASH_CSR_COUNT]; @@ -69,15 +69,15 @@ static void Test_Hash_InitChangesHmacContext(void) hmacKey, sizeof(hmacKey)), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_Reg_ReadPoll(base, HASH_SR_REG, HASH_SR_DINIS_Msk, - HASH_SR_DINIS_Msk, &g_whalTimeout), + WHAL_ASSERT_EQ(whal_Reg32_ReadPoll(base, HASH_SR_REG, HASH_SR_DINIS_Msk, + HASH_SR_DINIS_Msk, &g_whalTimeout), WHAL_SUCCESS); ReadCsrs(base, before, 0, HASH_CSR_COUNT); WHAL_ASSERT_EQ(AnyNonZero(before, HASH_CSR_COUNT), 1); - whal_Reg_Update(base, HASH_CR_REG, HASH_CR_INIT_Msk, HASH_CR_INIT_Msk); + whal_Reg32_Update(base, HASH_CR_REG, HASH_CR_INIT_Msk, HASH_CR_INIT_Msk); - if ((whal_Reg_Read(base, HASH_SR_REG) & HASH_SR_DINIS_Msk) == 0) + if ((whal_Reg32_Read(base, HASH_SR_REG) & HASH_SR_DINIS_Msk) == 0) WHAL_SKIP(); ReadCsrs(base, after, 0, HASH_CSR_COUNT); @@ -86,7 +86,7 @@ static void Test_Hash_InitChangesHmacContext(void) static void Test_Hash_DeinitClearsContext(void) { - size_t base = whal_Stm32wba_Hash_Dev.base; + uintptr_t base = whal_Stm32wba_Hash_Dev.base; uint32_t csr[HASH_CSR_COUNT]; size_t i; @@ -98,12 +98,12 @@ static void Test_Hash_DeinitClearsContext(void) (whal_Crypto *)&whal_Stm32wba_Hash_Dev), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_Reg_Read(base, HASH_SR_REG) & HASH_SR_DINIS_Msk, 0); + WHAL_ASSERT_EQ(whal_Reg32_Read(base, HASH_SR_REG) & HASH_SR_DINIS_Msk, 0); ReadCsrs(base, csr, 0, HASH_CSR_COUNT); WHAL_ASSERT_EQ(AnyNonZero(csr, HASH_CSR_COUNT), 0); for (i = 0; i < 8; i++) - WHAL_ASSERT_EQ(whal_Reg_Read(base, HASH_HR_REG(i)), 0); + WHAL_ASSERT_EQ(whal_Reg32_Read(base, HASH_HR_REG(i)), 0); WHAL_ASSERT_EQ(whal_Stm32wba_Hash_Init( (whal_Crypto *)&whal_Stm32wba_Hash_Dev), diff --git a/tests/dma/test_stm32wb_dma.c b/tests/dma/test_stm32wb_dma.c index cc21a562..1ee50f54 100644 --- a/tests/dma/test_stm32wb_dma.c +++ b/tests/dma/test_stm32wb_dma.c @@ -74,12 +74,12 @@ static void RecordCb(void *ctx, whal_Error err) rec->err = err; } -static size_t DmaBase(void) +static uintptr_t DmaBase(void) { return g_whalDma1.base; } -static size_t MuxBase(void) +static uintptr_t MuxBase(void) { return ((whal_Stm32wb_Dma_Cfg *)g_whalDma1.cfg)->dmamuxBase; } @@ -108,14 +108,14 @@ static void Test_Dma_PeriphToMem(void) WHAL_ASSERT_EQ(whal_Dma_Configure(&g_whalDma1, TEST_CH, &cfg), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_Reg_Read(DmaBase(), DMA_CCR), + WHAL_ASSERT_EQ(whal_Reg32_Read(DmaBase(), DMA_CCR), CCR_TCIE | CCR_TEIE | CCR_MINC | CCR_PSIZE(1) | CCR_MSIZE(1)); - WHAL_ASSERT_EQ(whal_Reg_Read(DmaBase(), DMA_CNDTR), 7); - WHAL_ASSERT_EQ(whal_Reg_Read(DmaBase(), DMA_CPAR), FAKE_PERIPH); - WHAL_ASSERT_EQ(whal_Reg_Read(DmaBase(), DMA_CMAR), + WHAL_ASSERT_EQ(whal_Reg32_Read(DmaBase(), DMA_CNDTR), 7); + WHAL_ASSERT_EQ(whal_Reg32_Read(DmaBase(), DMA_CPAR), FAKE_PERIPH); + WHAL_ASSERT_EQ(whal_Reg32_Read(DmaBase(), DMA_CMAR), (uint32_t)(size_t)g_dst); - WHAL_ASSERT_EQ(whal_Reg_Read(MuxBase(), DMAMUX_CCR) & 0x3F, 14); + WHAL_ASSERT_EQ(whal_Reg32_Read(MuxBase(), DMAMUX_CCR) & 0x3F, 14); WHAL_ASSERT_EQ(whal_Dma_Stop(&g_whalDma1, TEST_CH), WHAL_SUCCESS); } @@ -137,14 +137,14 @@ static void Test_Dma_MemToPeriph(void) WHAL_ASSERT_EQ(whal_Dma_Configure(&g_whalDma1, TEST_CH, &cfg), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_Reg_Read(DmaBase(), DMA_CCR), + WHAL_ASSERT_EQ(whal_Reg32_Read(DmaBase(), DMA_CCR), CCR_TCIE | CCR_TEIE | CCR_DIR | CCR_CIRC | CCR_MINC | CCR_PSIZE(2) | CCR_MSIZE(2)); - WHAL_ASSERT_EQ(whal_Reg_Read(DmaBase(), DMA_CNDTR), 5); - WHAL_ASSERT_EQ(whal_Reg_Read(DmaBase(), DMA_CPAR), FAKE_PERIPH); - WHAL_ASSERT_EQ(whal_Reg_Read(DmaBase(), DMA_CMAR), + WHAL_ASSERT_EQ(whal_Reg32_Read(DmaBase(), DMA_CNDTR), 5); + WHAL_ASSERT_EQ(whal_Reg32_Read(DmaBase(), DMA_CPAR), FAKE_PERIPH); + WHAL_ASSERT_EQ(whal_Reg32_Read(DmaBase(), DMA_CMAR), (uint32_t)(size_t)g_src); - WHAL_ASSERT_EQ(whal_Reg_Read(MuxBase(), DMAMUX_CCR) & 0x3F, 15); + WHAL_ASSERT_EQ(whal_Reg32_Read(MuxBase(), DMAMUX_CCR) & 0x3F, 15); WHAL_ASSERT_EQ(whal_Dma_Stop(&g_whalDma1, TEST_CH), WHAL_SUCCESS); } @@ -164,12 +164,12 @@ static void Test_Dma_MemToMemRegs(void) WHAL_ASSERT_EQ(whal_Dma_Configure(&g_whalDma1, TEST_CH, &cfg), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_Reg_Read(DmaBase(), DMA_CCR), + WHAL_ASSERT_EQ(whal_Reg32_Read(DmaBase(), DMA_CCR), CCR_TCIE | CCR_TEIE | CCR_PINC | CCR_MINC | CCR_MEM2MEM); - WHAL_ASSERT_EQ(whal_Reg_Read(DmaBase(), DMA_CNDTR), XFER_SZ); - WHAL_ASSERT_EQ(whal_Reg_Read(DmaBase(), DMA_CPAR), + WHAL_ASSERT_EQ(whal_Reg32_Read(DmaBase(), DMA_CNDTR), XFER_SZ); + WHAL_ASSERT_EQ(whal_Reg32_Read(DmaBase(), DMA_CPAR), (uint32_t)(size_t)g_src); - WHAL_ASSERT_EQ(whal_Reg_Read(DmaBase(), DMA_CMAR), + WHAL_ASSERT_EQ(whal_Reg32_Read(DmaBase(), DMA_CMAR), (uint32_t)(size_t)g_dst); WHAL_ASSERT_EQ(whal_Dma_Stop(&g_whalDma1, TEST_CH), WHAL_SUCCESS); @@ -211,14 +211,14 @@ static void RunMemToMem(whal_Stm32wb_Dma_Width width, uint16_t items) WHAL_ASSERT_EQ(whal_Dma_Configure(&g_whalDma1, TEST_CH, &cfg), WHAL_SUCCESS); WHAL_ASSERT_EQ(whal_Dma_Start(&g_whalDma1, TEST_CH), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_Reg_ReadPoll(DmaBase(), DMA_ISR, ISR_TCIF, ISR_TCIF, - &g_whalTimeout), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_Reg_Read(DmaBase(), DMA_ISR) & ISR_TEIF, 0); + WHAL_ASSERT_EQ(whal_Reg32_ReadPoll(DmaBase(), DMA_ISR, ISR_TCIF, ISR_TCIF, + &g_whalTimeout), WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Reg32_Read(DmaBase(), DMA_ISR) & ISR_TEIF, 0); whal_Stm32wb_Dma_IRQHandler(&g_whalDma1, TEST_CH, RecordCb, &rec); WHAL_ASSERT_EQ(rec.calls, 1); WHAL_ASSERT_EQ(rec.err, WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_Reg_Read(DmaBase(), DMA_ISR) & ISR_TCIF, 0); + WHAL_ASSERT_EQ(whal_Reg32_Read(DmaBase(), DMA_ISR) & ISR_TCIF, 0); WHAL_ASSERT_MEM_EQ(g_dst, g_src, XFER_SZ); @@ -251,13 +251,13 @@ static void Test_Dma_TransferError(void) WHAL_ASSERT_EQ(whal_Dma_Configure(&g_whalDma1, TEST_CH, &cfg), WHAL_SUCCESS); WHAL_ASSERT_EQ(whal_Dma_Start(&g_whalDma1, TEST_CH), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_Reg_ReadPoll(DmaBase(), DMA_ISR, ISR_TEIF, ISR_TEIF, - &g_whalTimeout), WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Reg32_ReadPoll(DmaBase(), DMA_ISR, ISR_TEIF, ISR_TEIF, + &g_whalTimeout), WHAL_SUCCESS); whal_Stm32wb_Dma_IRQHandler(&g_whalDma1, TEST_CH, RecordCb, &rec); WHAL_ASSERT_EQ(rec.calls, 1); WHAL_ASSERT_EQ(rec.err, WHAL_EHARDWARE); - WHAL_ASSERT_EQ(whal_Reg_Read(DmaBase(), DMA_ISR) & + WHAL_ASSERT_EQ(whal_Reg32_Read(DmaBase(), DMA_ISR) & (ISR_TEIF | ISR_TCIF), 0); WHAL_ASSERT_EQ(whal_Dma_Stop(&g_whalDma1, TEST_CH), WHAL_SUCCESS); diff --git a/tests/eth/test_stm32n6_eth.c b/tests/eth/test_stm32n6_eth.c index 00ceeecc..8be7d973 100644 --- a/tests/eth/test_stm32n6_eth.c +++ b/tests/eth/test_stm32n6_eth.c @@ -65,7 +65,7 @@ static void Test_Eth_Loopback(void) }; uint8_t rxFrame[1536]; size_t rxLen = sizeof(rxFrame); - size_t base = whal_Stm32n6_Eth_Dev.base; + uintptr_t base = whal_Stm32n6_Eth_Dev.base; whal_Stm32n6_Eth_Cfg *ethCfg = (whal_Stm32n6_Eth_Cfg *)whal_Stm32n6_Eth_Dev.cfg; whal_Error err; uint16_t bcr = 0; @@ -88,18 +88,18 @@ static void Test_Eth_Loopback(void) *(volatile uint32_t *)(0x44024000U + 0xC28U)); /* DMA channel state we expect to be running after Eth_Start. */ - DumpHex32("DMAC0TXCR (pre)", (uint32_t)whal_Reg_Read(base, 0x1104)); - DumpHex32("DMAC0RXCR (pre)", (uint32_t)whal_Reg_Read(base, 0x1108)); - DumpHex32("DMAC0TXDLAR", (uint32_t)whal_Reg_Read(base, 0x1114)); - DumpHex32("DMAC0RXDLAR", (uint32_t)whal_Reg_Read(base, 0x111C)); + DumpHex32("DMAC0TXCR (pre)", (uint32_t)whal_Reg32_Read(base, 0x1104)); + DumpHex32("DMAC0RXCR (pre)", (uint32_t)whal_Reg32_Read(base, 0x1108)); + DumpHex32("DMAC0TXDLAR", (uint32_t)whal_Reg32_Read(base, 0x1114)); + DumpHex32("DMAC0RXDLAR", (uint32_t)whal_Reg32_Read(base, 0x111C)); WHAL_ASSERT_EQ(whal_Stm32n6_Eth_Ext_EnableLoopback(BOARD_ETH_DEV, 1), WHAL_SUCCESS); WHAL_ASSERT_EQ(whal_Eth_Start(BOARD_ETH_DEV, WHAL_ETH_SPEED_100, WHAL_ETH_DUPLEX_FULL), WHAL_SUCCESS); - DumpHex32("MACCR after Start", (uint32_t)whal_Reg_Read(base, - DBG_MACCR_REG)); + DumpHex32("MACCR after Start", (uint32_t)whal_Reg32_Read(base, + DBG_MACCR_REG)); WHAL_ASSERT_EQ(whal_Eth_Send(BOARD_ETH_DEV, txFrame, sizeof(txFrame)), WHAL_SUCCESS); @@ -108,9 +108,9 @@ static void Test_Eth_Loopback(void) Board_WaitMs(20); DumpHex32("TDES3 after Send+20ms", ethCfg->txDescs[0].des[3]); DumpHex32("RDES3 after Send+20ms", ethCfg->rxDescs[0].des[3]); - DumpHex32("DMADSR", (uint32_t)whal_Reg_Read(base, + DumpHex32("DMADSR", (uint32_t)whal_Reg32_Read(base, DBG_DMADSR_REG)); - DumpHex32("DMAC0SR", (uint32_t)whal_Reg_Read(base, + DumpHex32("DMAC0SR", (uint32_t)whal_Reg32_Read(base, DBG_DMAC0SR_REG)); /* Poll for the looped-back frame */ @@ -120,11 +120,11 @@ static void Test_Eth_Loopback(void) } while (err == WHAL_ENOTREADY && (g_tick - start) < 100); if (err != WHAL_SUCCESS) { - DumpHex32("MACCR final", (uint32_t)whal_Reg_Read(base, DBG_MACCR_REG)); - DumpHex32("DMADSR final", (uint32_t)whal_Reg_Read(base, - DBG_DMADSR_REG)); - DumpHex32("DMAC0SR final",(uint32_t)whal_Reg_Read(base, - DBG_DMAC0SR_REG)); + DumpHex32("MACCR final", (uint32_t)whal_Reg32_Read(base, DBG_MACCR_REG)); + DumpHex32("DMADSR final", (uint32_t)whal_Reg32_Read(base, + DBG_DMADSR_REG)); + DumpHex32("DMAC0SR final",(uint32_t)whal_Reg32_Read(base, + DBG_DMAC0SR_REG)); DumpHex32("TDES3 final", ethCfg->txDescs[0].des[3]); DumpHex32("RDES3 final", ethCfg->rxDescs[0].des[3]); } diff --git a/tests/flash/test_flash.c b/tests/flash/test_flash.c index 8eae690b..21eb8a5e 100644 --- a/tests/flash/test_flash.c +++ b/tests/flash/test_flash.c @@ -131,7 +131,7 @@ static size_t ExtentBase(void) } /* On-chip flash below the end of the running image must not be erased */ -static int ExtentOverlapsImage(size_t base) +static int ExtentOverlapsImage(uintptr_t base) { size_t imageEnd = (size_t)_sidata + (size_t)(_edata - _sdata); @@ -141,7 +141,7 @@ static int ExtentOverlapsImage(size_t base) static void Test_Flash_EraseExtent(void) { const size_t sz = g_testFlashSectorSz; - const size_t base = ExtentBase(); + const uintptr_t base = ExtentBase(); if (ExtentOverlapsImage(base)) WHAL_SKIP(); @@ -178,7 +178,7 @@ static void Test_Flash_EraseExtent(void) static void Test_Flash_EraseOneBytePastSector(void) { const size_t sz = g_testFlashSectorSz; - const size_t base = ExtentBase(); + const uintptr_t base = ExtentBase(); if (ExtentOverlapsImage(base)) WHAL_SKIP(); diff --git a/tests/flash/test_stm32wb_flash.c b/tests/flash/test_stm32wb_flash.c index fe300079..03ce4faf 100644 --- a/tests/flash/test_stm32wb_flash.c +++ b/tests/flash/test_stm32wb_flash.c @@ -36,9 +36,9 @@ static void Test_Flash_LockReadback(void) /* After locking, the CR.LOCK bit should be set */ WHAL_ASSERT_EQ(whal_Flash_Lock(BOARD_FLASH_DEV, 0, 0), WHAL_SUCCESS); - size_t val = 0; - whal_Reg_Get(whal_Stm32wb_Flash_Dev.base, FLASH_CR_REG, - FLASH_CR_LOCK_Msk, FLASH_CR_LOCK_Pos, &val); + uint32_t val = 0; + whal_Reg32_Get(whal_Stm32wb_Flash_Dev.base, FLASH_CR_REG, + FLASH_CR_LOCK_Msk, FLASH_CR_LOCK_Pos, &val); WHAL_ASSERT_EQ(val, 1); } diff --git a/tests/gpio/test_pic32cz_gpio.c b/tests/gpio/test_pic32cz_gpio.c index ecab0c34..19ffbe85 100644 --- a/tests/gpio/test_pic32cz_gpio.c +++ b/tests/gpio/test_pic32cz_gpio.c @@ -49,9 +49,9 @@ static void Test_Gpio_DirRegister(void) { /* PB21 should be configured as output (bit 21 set in DIR register) */ - size_t val = 0; - whal_Reg_Get(whal_Pic32cz_Gpio_Dev.base, PORT_DIR_REG(LED_PORT), - (1UL << LED_HW_PIN), LED_HW_PIN, &val); + uint32_t val = 0; + whal_Reg32_Get(whal_Pic32cz_Gpio_Dev.base, PORT_DIR_REG(LED_PORT), + (1UL << LED_HW_PIN), LED_HW_PIN, &val); WHAL_ASSERT_EQ(val, 1); } @@ -61,20 +61,20 @@ static void Test_Gpio_PinTableRegisters(void) { const whal_Pic32cz_Gpio_Cfg *cfg = (const whal_Pic32cz_Gpio_Cfg *)whal_Pic32cz_Gpio_Dev.cfg; - size_t base = whal_Pic32cz_Gpio_Dev.base; + uintptr_t base = whal_Pic32cz_Gpio_Dev.base; for (size_t i = 0; i < cfg->pinCfgCount; i++) { const whal_Pic32cz_Gpio_PinCfg *p = &cfg->pinCfg[i]; - size_t pincfg = (whal_Reg_Read(base, - PORT_PINCFG_REG(p->port, p->pin)) >> + size_t pincfg = (whal_Reg32_Read(base, + PORT_PINCFG_REG(p->port, p->pin)) >> PORT_PINCFG_Pos(p->pin)) & 0xFF; - size_t val = 0; + uint32_t val = 0; if (p->pmuxEn) { WHAL_ASSERT_EQ(pincfg & PINCFG_PMUXEN, PINCFG_PMUXEN); - whal_Reg_Get(base, PORT_PMUX_REG(p->port, p->pin), - WHAL_BITMASK(4) << PORT_PMUX_Pos(p->pin), - PORT_PMUX_Pos(p->pin), &val); + whal_Reg32_Get(base, PORT_PMUX_REG(p->port, p->pin), + WHAL_BITMASK(4) << PORT_PMUX_Pos(p->pin), + PORT_PMUX_Pos(p->pin), &val); WHAL_ASSERT_EQ(val, p->pmux); continue; } @@ -83,8 +83,8 @@ static void Test_Gpio_PinTableRegisters(void) WHAL_ASSERT_EQ((pincfg & PINCFG_INEN) != 0, p->inEn); WHAL_ASSERT_EQ((pincfg & PINCFG_PULLEN) != 0, p->pullEn); - whal_Reg_Get(base, PORT_DIR_REG(p->port), 1UL << p->pin, p->pin, - &val); + whal_Reg32_Get(base, PORT_DIR_REG(p->port), 1UL << p->pin, p->pin, + &val); WHAL_ASSERT_EQ(val, p->dir); } } @@ -94,9 +94,9 @@ static void Test_Gpio_SetHighReg(void) WHAL_ASSERT_EQ(whal_Gpio_Set(BOARD_GPIO_DEV, BOARD_LED_PIN, 1), WHAL_SUCCESS); /* Readback OUT register bit 21 */ - size_t val = 0; - whal_Reg_Get(whal_Pic32cz_Gpio_Dev.base, PORT_OUT_REG(LED_PORT), - (1UL << LED_HW_PIN), LED_HW_PIN, &val); + uint32_t val = 0; + whal_Reg32_Get(whal_Pic32cz_Gpio_Dev.base, PORT_OUT_REG(LED_PORT), + (1UL << LED_HW_PIN), LED_HW_PIN, &val); WHAL_ASSERT_EQ(val, 1); } @@ -104,19 +104,19 @@ static void Test_Gpio_SetLowReg(void) { WHAL_ASSERT_EQ(whal_Gpio_Set(BOARD_GPIO_DEV, BOARD_LED_PIN, 0), WHAL_SUCCESS); - size_t val = 0; - whal_Reg_Get(whal_Pic32cz_Gpio_Dev.base, PORT_OUT_REG(LED_PORT), - (1UL << LED_HW_PIN), LED_HW_PIN, &val); + uint32_t val = 0; + whal_Reg32_Get(whal_Pic32cz_Gpio_Dev.base, PORT_OUT_REG(LED_PORT), + (1UL << LED_HW_PIN), LED_HW_PIN, &val); WHAL_ASSERT_EQ(val, 0); } static void Test_Gpio_SetNonzeroReg(void) { - size_t val = 0; + uint32_t val = 0; WHAL_ASSERT_EQ(whal_Gpio_Set(BOARD_GPIO_DEV, BOARD_LED_PIN, 2), WHAL_SUCCESS); - whal_Reg_Get(whal_Pic32cz_Gpio_Dev.base, PORT_OUT_REG(LED_PORT), - (1UL << LED_HW_PIN), LED_HW_PIN, &val); + whal_Reg32_Get(whal_Pic32cz_Gpio_Dev.base, PORT_OUT_REG(LED_PORT), + (1UL << LED_HW_PIN), LED_HW_PIN, &val); WHAL_ASSERT_EQ(val, 1); WHAL_ASSERT_EQ(whal_Gpio_Set(BOARD_GPIO_DEV, BOARD_LED_PIN, 0), WHAL_SUCCESS); diff --git a/tests/gpio/test_stm32wb0_gpio.c b/tests/gpio/test_stm32wb0_gpio.c index fb850c62..87a1f08a 100644 --- a/tests/gpio/test_stm32wb0_gpio.c +++ b/tests/gpio/test_stm32wb0_gpio.c @@ -41,7 +41,7 @@ static const whal_Stm32wb0_Gpio_Cfg *GpioCfg(void) return (const whal_Stm32wb0_Gpio_Cfg *)whal_Stm32wb0_Gpio_Dev.cfg; } -static size_t PortBase(whal_Stm32wb0_Gpio_PinCfg p) +static uintptr_t PortBase(whal_Stm32wb0_Gpio_PinCfg p) { return whal_Stm32wb0_Gpio_Dev.base + WHAL_STM32WB0_GPIO_GET_PORT(p) * GPIOx_STRIDE; @@ -55,31 +55,31 @@ static void Test_Gpio_PinTableRegisters(void) for (size_t i = 0; i < cfg->pinCount; i++) { whal_Stm32wb0_Gpio_PinCfg p = cfg->pinCfg[i]; - size_t base = PortBase(p); + uintptr_t base = PortBase(p); size_t pin = WHAL_STM32WB0_GPIO_GET_PIN(p); size_t pos2 = pin << 1; - size_t val = 0; + uint32_t val = 0; - whal_Reg_Get(base, GPIOx_MODE_REG, WHAL_BITMASK(2) << pos2, pos2, - &val); + whal_Reg32_Get(base, GPIOx_MODE_REG, WHAL_BITMASK(2) << pos2, pos2, + &val); WHAL_ASSERT_EQ(val, WHAL_STM32WB0_GPIO_GET_MODE(p)); - whal_Reg_Get(base, GPIOx_OTYPER_REG, 1UL << pin, pin, &val); + whal_Reg32_Get(base, GPIOx_OTYPER_REG, 1UL << pin, pin, &val); WHAL_ASSERT_EQ(val, WHAL_STM32WB0_GPIO_GET_OUTTYPE(p)); - whal_Reg_Get(base, GPIOx_OSPEEDR_REG, WHAL_BITMASK(2) << pos2, pos2, - &val); + whal_Reg32_Get(base, GPIOx_OSPEEDR_REG, WHAL_BITMASK(2) << pos2, pos2, + &val); WHAL_ASSERT_EQ(val, WHAL_STM32WB0_GPIO_GET_SPEED(p)); - whal_Reg_Get(base, GPIOx_PUPDR_REG, WHAL_BITMASK(2) << pos2, pos2, - &val); + whal_Reg32_Get(base, GPIOx_PUPDR_REG, WHAL_BITMASK(2) << pos2, pos2, + &val); WHAL_ASSERT_EQ(val, WHAL_STM32WB0_GPIO_GET_PULL(p)); if (WHAL_STM32WB0_GPIO_GET_MODE(p) == WHAL_STM32WB0_GPIO_MODE_ALTFN) { size_t afPos = (pin & 7) << 2; - whal_Reg_Get(base, (pin < 8) ? GPIOx_AFRL_REG : GPIOx_AFRH_REG, - WHAL_BITMASK(4) << afPos, afPos, &val); + whal_Reg32_Get(base, (pin < 8) ? GPIOx_AFRL_REG : GPIOx_AFRH_REG, + WHAL_BITMASK(4) << afPos, afPos, &val); WHAL_ASSERT_EQ(val, WHAL_STM32WB0_GPIO_GET_ALTFN(p)); } } @@ -89,16 +89,16 @@ static void Test_Gpio_SetLedReg(void) { whal_Stm32wb0_Gpio_PinCfg led = GpioCfg()->pinCfg[BOARD_LED_PIN]; size_t pin = WHAL_STM32WB0_GPIO_GET_PIN(led); - size_t val = 0; + uint32_t val = 0; WHAL_ASSERT_EQ(whal_Gpio_Set(BOARD_GPIO_DEV, BOARD_LED_PIN, 1), WHAL_SUCCESS); - whal_Reg_Get(PortBase(led), GPIOx_ODR_REG, 1UL << pin, pin, &val); + whal_Reg32_Get(PortBase(led), GPIOx_ODR_REG, 1UL << pin, pin, &val); WHAL_ASSERT_EQ(val, 1); WHAL_ASSERT_EQ(whal_Gpio_Set(BOARD_GPIO_DEV, BOARD_LED_PIN, 0), WHAL_SUCCESS); - whal_Reg_Get(PortBase(led), GPIOx_ODR_REG, 1UL << pin, pin, &val); + whal_Reg32_Get(PortBase(led), GPIOx_ODR_REG, 1UL << pin, pin, &val); WHAL_ASSERT_EQ(val, 0); } diff --git a/tests/gpio/test_stm32wb_gpio.c b/tests/gpio/test_stm32wb_gpio.c index aa5c2bc3..88abac28 100644 --- a/tests/gpio/test_stm32wb_gpio.c +++ b/tests/gpio/test_stm32wb_gpio.c @@ -39,7 +39,7 @@ #define GPIOx_AFRH_REG 0x24 #define GPIOx_STRIDE 0x400 -static inline size_t Board_LedPortBase(void) +static inline uintptr_t Board_LedPortBase(void) { const whal_Stm32wb_Gpio_Cfg *cfg = (const whal_Stm32wb_Gpio_Cfg *)whal_Stm32wb_Gpio_Dev.cfg; whal_Stm32wb_Gpio_PinCfg led = cfg->pinCfg[BOARD_LED_PIN]; @@ -90,9 +90,9 @@ static void Test_Gpio_ModeRegister(void) size_t pinNum = Board_LedPinNum(); size_t bitPos = pinNum << 1; size_t mask = (WHAL_BITMASK(2) << bitPos); - size_t val = 0; + uint32_t val = 0; - whal_Reg_Get(Board_LedPortBase(), GPIOx_MODE_REG, mask, bitPos, &val); + whal_Reg32_Get(Board_LedPortBase(), GPIOx_MODE_REG, mask, bitPos, &val); WHAL_ASSERT_EQ(val, WHAL_STM32WB_GPIO_MODE_OUT); } @@ -104,32 +104,32 @@ static void Test_Gpio_PinTableRegisters(void) for (size_t i = 0; i < cfg->pinCount; i++) { whal_Stm32wb_Gpio_PinCfg p = cfg->pinCfg[i]; - size_t base = whal_Stm32wb_Gpio_Dev.base + + uintptr_t base = whal_Stm32wb_Gpio_Dev.base + WHAL_STM32WB_GPIO_GET_PORT(p) * GPIOx_STRIDE; size_t pin = WHAL_STM32WB_GPIO_GET_PIN(p); size_t pos2 = pin << 1; - size_t val = 0; + uint32_t val = 0; - whal_Reg_Get(base, GPIOx_MODE_REG, WHAL_BITMASK(2) << pos2, pos2, - &val); + whal_Reg32_Get(base, GPIOx_MODE_REG, WHAL_BITMASK(2) << pos2, pos2, + &val); WHAL_ASSERT_EQ(val, WHAL_STM32WB_GPIO_GET_MODE(p)); - whal_Reg_Get(base, GPIOx_OTYPER_REG, 1UL << pin, pin, &val); + whal_Reg32_Get(base, GPIOx_OTYPER_REG, 1UL << pin, pin, &val); WHAL_ASSERT_EQ(val, WHAL_STM32WB_GPIO_GET_OUTTYPE(p)); - whal_Reg_Get(base, GPIOx_OSPEEDR_REG, WHAL_BITMASK(2) << pos2, pos2, - &val); + whal_Reg32_Get(base, GPIOx_OSPEEDR_REG, WHAL_BITMASK(2) << pos2, pos2, + &val); WHAL_ASSERT_EQ(val, WHAL_STM32WB_GPIO_GET_SPEED(p)); - whal_Reg_Get(base, GPIOx_PUPDR_REG, WHAL_BITMASK(2) << pos2, pos2, - &val); + whal_Reg32_Get(base, GPIOx_PUPDR_REG, WHAL_BITMASK(2) << pos2, pos2, + &val); WHAL_ASSERT_EQ(val, WHAL_STM32WB_GPIO_GET_PULL(p)); if (WHAL_STM32WB_GPIO_GET_MODE(p) == WHAL_STM32WB_GPIO_MODE_ALTFN) { size_t afPos = (pin & 7) << 2; - whal_Reg_Get(base, (pin < 8) ? GPIOx_AFRL_REG : GPIOx_AFRH_REG, - WHAL_BITMASK(4) << afPos, afPos, &val); + whal_Reg32_Get(base, (pin < 8) ? GPIOx_AFRL_REG : GPIOx_AFRH_REG, + WHAL_BITMASK(4) << afPos, afPos, &val); WHAL_ASSERT_EQ(val, WHAL_STM32WB_GPIO_GET_ALTFN(p)); } } @@ -140,9 +140,9 @@ static void Test_Gpio_SetHighReg(void) WHAL_ASSERT_EQ(whal_Gpio_Set(BOARD_GPIO_DEV, BOARD_LED_PIN, 1), WHAL_SUCCESS); size_t pinNum = Board_LedPinNum(); - size_t val = 0; - whal_Reg_Get(Board_LedPortBase(), GPIOx_ODR_REG, (1UL << pinNum), - pinNum, &val); + uint32_t val = 0; + whal_Reg32_Get(Board_LedPortBase(), GPIOx_ODR_REG, (1UL << pinNum), + pinNum, &val); WHAL_ASSERT_EQ(val, 1); } @@ -151,20 +151,20 @@ static void Test_Gpio_SetLowReg(void) WHAL_ASSERT_EQ(whal_Gpio_Set(BOARD_GPIO_DEV, BOARD_LED_PIN, 0), WHAL_SUCCESS); size_t pinNum = Board_LedPinNum(); - size_t val = 0; - whal_Reg_Get(Board_LedPortBase(), GPIOx_ODR_REG, (1UL << pinNum), - pinNum, &val); + uint32_t val = 0; + whal_Reg32_Get(Board_LedPortBase(), GPIOx_ODR_REG, (1UL << pinNum), + pinNum, &val); WHAL_ASSERT_EQ(val, 0); } static void Test_Gpio_SetNonzeroReg(void) { size_t pinNum = Board_LedPinNum(); - size_t val = 0; + uint32_t val = 0; WHAL_ASSERT_EQ(whal_Gpio_Set(BOARD_GPIO_DEV, BOARD_LED_PIN, 2), WHAL_SUCCESS); - whal_Reg_Get(Board_LedPortBase(), GPIOx_ODR_REG, (1UL << pinNum), - pinNum, &val); + whal_Reg32_Get(Board_LedPortBase(), GPIOx_ODR_REG, (1UL << pinNum), + pinNum, &val); WHAL_ASSERT_EQ(val, 1); WHAL_ASSERT_EQ(whal_Gpio_Set(BOARD_GPIO_DEV, BOARD_LED_PIN, 0), WHAL_SUCCESS); diff --git a/tests/i2c/test_stm32wb_i2c.c b/tests/i2c/test_stm32wb_i2c.c index cdd1c201..51c0fdfd 100644 --- a/tests/i2c/test_stm32wb_i2c.c +++ b/tests/i2c/test_stm32wb_i2c.c @@ -49,7 +49,7 @@ typedef struct { uint32_t scll; } Timing; -static size_t I2cBase(void) +static uintptr_t I2cBase(void) { return BOARD_I2C_DEV->base; } @@ -88,7 +88,7 @@ static void StartAndRead(uint32_t freq, Timing *t) }; WHAL_ASSERT_EQ(whal_I2c_StartCom(BOARD_I2C_DEV, &com), WHAL_SUCCESS); - *t = DecodeTimingr(whal_Reg_Read(I2cBase(), I2C_TIMINGR)); + *t = DecodeTimingr(whal_Reg32_Read(I2cBase(), I2C_TIMINGR)); WHAL_ASSERT_EQ(whal_I2c_EndCom(BOARD_I2C_DEV), WHAL_SUCCESS); } @@ -149,7 +149,7 @@ static void Test_Stm32wb_I2c_Address(void) /* 7-bit addresses occupy SADD[7:1] */ WHAL_ASSERT_EQ(whal_I2c_StartCom(BOARD_I2C_DEV, &com), WHAL_SUCCESS); - cr2 = whal_Reg_Read(I2cBase(), I2C_CR2); + cr2 = whal_Reg32_Read(I2cBase(), I2C_CR2); WHAL_ASSERT_EQ(cr2 & CR2_SADD_Msk, 0x50 << 1); WHAL_ASSERT_EQ(cr2 & CR2_ADD10_Msk, 0); WHAL_ASSERT_EQ(whal_I2c_EndCom(BOARD_I2C_DEV), WHAL_SUCCESS); @@ -157,7 +157,7 @@ static void Test_Stm32wb_I2c_Address(void) /* Highest 7-bit address */ com.addr = 0x7F; WHAL_ASSERT_EQ(whal_I2c_StartCom(BOARD_I2C_DEV, &com), WHAL_SUCCESS); - cr2 = whal_Reg_Read(I2cBase(), I2C_CR2); + cr2 = whal_Reg32_Read(I2cBase(), I2C_CR2); WHAL_ASSERT_EQ(cr2 & CR2_SADD_Msk, 0x7F << 1); WHAL_ASSERT_EQ(whal_I2c_EndCom(BOARD_I2C_DEV), WHAL_SUCCESS); @@ -165,13 +165,13 @@ static void Test_Stm32wb_I2c_Address(void) com.addr = 0x2A5; com.addrSz = 10; WHAL_ASSERT_EQ(whal_I2c_StartCom(BOARD_I2C_DEV, &com), WHAL_SUCCESS); - cr2 = whal_Reg_Read(I2cBase(), I2C_CR2); + cr2 = whal_Reg32_Read(I2cBase(), I2C_CR2); WHAL_ASSERT_EQ(cr2 & CR2_SADD_Msk, 0x2A5); WHAL_ASSERT_EQ(cr2 & CR2_ADD10_Msk, CR2_ADD10_Msk); /* EndCom clears the address and addressing mode */ WHAL_ASSERT_EQ(whal_I2c_EndCom(BOARD_I2C_DEV), WHAL_SUCCESS); - cr2 = whal_Reg_Read(I2cBase(), I2C_CR2); + cr2 = whal_Reg32_Read(I2cBase(), I2C_CR2); WHAL_ASSERT_EQ(cr2 & (CR2_SADD_Msk | CR2_ADD10_Msk), 0); } diff --git a/tests/timer/test_stm32wb_timer.c b/tests/timer/test_stm32wb_timer.c index 806078a6..ecd09fd0 100644 --- a/tests/timer/test_stm32wb_timer.c +++ b/tests/timer/test_stm32wb_timer.c @@ -37,7 +37,7 @@ /* Spin budget for one tick to elapse; far longer than a 1 ms tick */ #define TICK_SPIN_MAX 10000000UL -static size_t SysTickBase(void) +static uintptr_t SysTickBase(void) { return whal_SysTick_Dev.base; } @@ -62,9 +62,9 @@ static int TickAdvances(void) static void CheckConfig(void) { const whal_SysTick_Cfg *cfg = SysTickCfg(); - size_t csr = whal_Reg_Read(SysTickBase(), SYSTICK_CSR); + size_t csr = whal_Reg32_Read(SysTickBase(), SYSTICK_CSR); - WHAL_ASSERT_EQ(whal_Reg_Read(SysTickBase(), SYSTICK_RVR) & RVR_RELOAD_Msk, + WHAL_ASSERT_EQ(whal_Reg32_Read(SysTickBase(), SYSTICK_RVR) & RVR_RELOAD_Msk, cfg->cyclesPerTick - 1); WHAL_ASSERT_EQ((csr & CSR_CLKSOURCE) != 0, cfg->clkSrc == WHAL_SYSTICK_CLKSRC_SYSCLK); @@ -87,12 +87,12 @@ static void Test_SysTick_StopStart(void) size_t cvr1, cvr2; stopErr = whal_Timer_Stop(WHAL_INTERNAL_DEV); - csr = whal_Reg_Read(SysTickBase(), SYSTICK_CSR); + csr = whal_Reg32_Read(SysTickBase(), SYSTICK_CSR); /* A stopped counter holds its value */ - cvr1 = whal_Reg_Read(SysTickBase(), SYSTICK_CVR); + cvr1 = whal_Reg32_Read(SysTickBase(), SYSTICK_CVR); for (volatile size_t i = 0; i < 1000; i++) {} - cvr2 = whal_Reg_Read(SysTickBase(), SYSTICK_CVR); + cvr2 = whal_Reg32_Read(SysTickBase(), SYSTICK_CVR); /* Restart before asserting so later tests keep a time base */ WHAL_ASSERT_EQ(whal_Timer_Start(WHAL_INTERNAL_DEV), WHAL_SUCCESS); @@ -101,7 +101,7 @@ static void Test_SysTick_StopStart(void) WHAL_ASSERT_EQ(csr & CSR_ENABLE, 0); WHAL_ASSERT_EQ(cvr1, cvr2); - WHAL_ASSERT_EQ(whal_Reg_Read(SysTickBase(), SYSTICK_CSR) & CSR_ENABLE, + WHAL_ASSERT_EQ(whal_Reg32_Read(SysTickBase(), SYSTICK_CSR) & CSR_ENABLE, CSR_ENABLE); WHAL_ASSERT_EQ(TickAdvances(), 1); } @@ -113,8 +113,8 @@ static void Test_SysTick_Deinit(void) size_t cvr; deinitErr = whal_Timer_Deinit(WHAL_INTERNAL_DEV); - csr = whal_Reg_Read(SysTickBase(), SYSTICK_CSR); - cvr = whal_Reg_Read(SysTickBase(), SYSTICK_CVR); + csr = whal_Reg32_Read(SysTickBase(), SYSTICK_CSR); + cvr = whal_Reg32_Read(SysTickBase(), SYSTICK_CVR); /* Restore the tick before asserting so later tests keep a time base */ WHAL_ASSERT_EQ(whal_Timer_Init(WHAL_INTERNAL_DEV), WHAL_SUCCESS); diff --git a/wolfHAL/block/block.h b/wolfHAL/block/block.h index 1607c39a..efda534b 100644 --- a/wolfHAL/block/block.h +++ b/wolfHAL/block/block.h @@ -57,7 +57,7 @@ typedef struct { * @brief Block device instance tying configuration to a driver implementation. */ struct whal_Block { - const size_t base; + const uintptr_t base; const whal_BlockDriver *driver; void *cfg; }; diff --git a/wolfHAL/clock/pic32cz_clock.h b/wolfHAL/clock/pic32cz_clock.h index d5069dd0..fc4cefb5 100644 --- a/wolfHAL/clock/pic32cz_clock.h +++ b/wolfHAL/clock/pic32cz_clock.h @@ -223,7 +223,7 @@ typedef struct { static inline whal_Error whal_Pic32cz_Clock_EnablePll( const whal_Pic32cz_Clock_PllCfg *cfg) { - size_t status; + uint32_t status; uint8_t i; size_t pllCtrlReg, pllFbdivReg, pllRefdivReg, pllPostdivaReg; @@ -232,39 +232,39 @@ static inline whal_Error whal_Pic32cz_Clock_EnablePll( pllRefdivReg = WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxREFDIV_REG(cfg->pllInst); pllPostdivaReg = WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxPOSTDIVA_REG(cfg->pllInst); - whal_Reg_Update(WHAL_PIC32CZ_CLOCK_BASE, pllFbdivReg, - WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxFBDIV_Msk, - whal_SetBits(WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxFBDIV_Msk, - WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxFBDIV_Pos, - cfg->fbDiv)); - whal_Reg_Update(WHAL_PIC32CZ_CLOCK_BASE, pllRefdivReg, - WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxREFDIV_Msk, - whal_SetBits(WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxREFDIV_Msk, - WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxREFDIV_Pos, - cfg->refDiv)); + whal_Reg32_Update(WHAL_PIC32CZ_CLOCK_BASE, pllFbdivReg, + WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxFBDIV_Msk, + whal_SetBits(WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxFBDIV_Msk, + WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxFBDIV_Pos, + cfg->fbDiv)); + whal_Reg32_Update(WHAL_PIC32CZ_CLOCK_BASE, pllRefdivReg, + WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxREFDIV_Msk, + whal_SetBits(WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxREFDIV_Msk, + WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxREFDIV_Pos, + cfg->refDiv)); for (i = 0; i < cfg->outCfgCount; i++) { const whal_Pic32cz_Clock_PllOutCfg *out = &cfg->outCfg[i]; - whal_Reg_Update(WHAL_PIC32CZ_CLOCK_BASE, pllPostdivaReg, - out->outEnMask | out->postDivMask, - whal_SetBits(out->postDivMask, out->postDivPos, out->postDiv) | - whal_SetBits(out->outEnMask, out->outEnPos, 1)); + whal_Reg32_Update(WHAL_PIC32CZ_CLOCK_BASE, pllPostdivaReg, + out->outEnMask | out->postDivMask, + whal_SetBits(out->postDivMask, out->postDivPos, out->postDiv) | + whal_SetBits(out->outEnMask, out->outEnPos, 1)); } - whal_Reg_Update(WHAL_PIC32CZ_CLOCK_BASE, pllCtrlReg, - WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxCTRL_ENABLE_Msk | - WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxCTRL_REFSEL_Msk | - WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxCTRL_BWSEL_Msk, - WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxCTRL_ENABLE_Msk | - whal_SetBits(WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxCTRL_REFSEL_Msk, - WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxCTRL_REFSEL_Pos, cfg->refSel) | - whal_SetBits(WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxCTRL_BWSEL_Msk, - WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxCTRL_BWSEL_Pos, cfg->bwSel)); + whal_Reg32_Update(WHAL_PIC32CZ_CLOCK_BASE, pllCtrlReg, + WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxCTRL_ENABLE_Msk | + WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxCTRL_REFSEL_Msk | + WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxCTRL_BWSEL_Msk, + WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxCTRL_ENABLE_Msk | + whal_SetBits(WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxCTRL_REFSEL_Msk, + WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxCTRL_REFSEL_Pos, cfg->refSel) | + whal_SetBits(WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxCTRL_BWSEL_Msk, + WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxCTRL_BWSEL_Pos, cfg->bwSel)); do { - whal_Reg_Get(WHAL_PIC32CZ_CLOCK_BASE, WHAL_PIC32CZ_CLOCK_OSCCTRL_STATUS_REG, - WHAL_PIC32CZ_CLOCK_OSCCTRL_STATUS_PLLxLOCK_Msk(cfg->pllInst), - WHAL_PIC32CZ_CLOCK_OSCCTRL_STATUS_PLLxLOCK_Pos(cfg->pllInst), - &status); + whal_Reg32_Get(WHAL_PIC32CZ_CLOCK_BASE, WHAL_PIC32CZ_CLOCK_OSCCTRL_STATUS_REG, + WHAL_PIC32CZ_CLOCK_OSCCTRL_STATUS_PLLxLOCK_Msk(cfg->pllInst), + WHAL_PIC32CZ_CLOCK_OSCCTRL_STATUS_PLLxLOCK_Pos(cfg->pllInst), + &status); } while (!status); return WHAL_SUCCESS; } @@ -282,22 +282,22 @@ static inline whal_Error whal_Pic32cz_Clock_EnablePll( static inline whal_Error whal_Pic32cz_Clock_EnableGclkGen( const whal_Pic32cz_Clock_GenCfg *cfg) { - size_t status; - - whal_Reg_Update(WHAL_PIC32CZ_CLOCK_BASE, WHAL_PIC32CZ_CLOCK_GCLK_GENCTRLx_REG(cfg->gen), - WHAL_PIC32CZ_CLOCK_GCLK_GENCTRLx_SRC_Msk | - WHAL_PIC32CZ_CLOCK_GCLK_GENCTRLx_GENEN_Msk | - WHAL_PIC32CZ_CLOCK_GCLK_GENCTRLx_DIV_Msk, - whal_SetBits(WHAL_PIC32CZ_CLOCK_GCLK_GENCTRLx_SRC_Msk, - WHAL_PIC32CZ_CLOCK_GCLK_GENCTRLx_SRC_Pos, cfg->genSrc) | - WHAL_PIC32CZ_CLOCK_GCLK_GENCTRLx_GENEN_Msk | - whal_SetBits(WHAL_PIC32CZ_CLOCK_GCLK_GENCTRLx_DIV_Msk, - WHAL_PIC32CZ_CLOCK_GCLK_GENCTRLx_DIV_Pos, cfg->genDiv)); + uint32_t status; + + whal_Reg32_Update(WHAL_PIC32CZ_CLOCK_BASE, WHAL_PIC32CZ_CLOCK_GCLK_GENCTRLx_REG(cfg->gen), + WHAL_PIC32CZ_CLOCK_GCLK_GENCTRLx_SRC_Msk | + WHAL_PIC32CZ_CLOCK_GCLK_GENCTRLx_GENEN_Msk | + WHAL_PIC32CZ_CLOCK_GCLK_GENCTRLx_DIV_Msk, + whal_SetBits(WHAL_PIC32CZ_CLOCK_GCLK_GENCTRLx_SRC_Msk, + WHAL_PIC32CZ_CLOCK_GCLK_GENCTRLx_SRC_Pos, cfg->genSrc) | + WHAL_PIC32CZ_CLOCK_GCLK_GENCTRLx_GENEN_Msk | + whal_SetBits(WHAL_PIC32CZ_CLOCK_GCLK_GENCTRLx_DIV_Msk, + WHAL_PIC32CZ_CLOCK_GCLK_GENCTRLx_DIV_Pos, cfg->genDiv)); do { - whal_Reg_Get(WHAL_PIC32CZ_CLOCK_BASE, WHAL_PIC32CZ_CLOCK_GCLK_SYNCBUSY_REG, - WHAL_PIC32CZ_CLOCK_GCLK_SYNCBUSY_GENCTRLx_Msk(cfg->gen), - WHAL_PIC32CZ_CLOCK_GCLK_SYNCBUSY_GENCTRLx_Pos(cfg->gen), - &status); + whal_Reg32_Get(WHAL_PIC32CZ_CLOCK_BASE, WHAL_PIC32CZ_CLOCK_GCLK_SYNCBUSY_REG, + WHAL_PIC32CZ_CLOCK_GCLK_SYNCBUSY_GENCTRLx_Msk(cfg->gen), + WHAL_PIC32CZ_CLOCK_GCLK_SYNCBUSY_GENCTRLx_Pos(cfg->gen), + &status); } while (status); return WHAL_SUCCESS; } @@ -314,16 +314,16 @@ static inline whal_Error whal_Pic32cz_Clock_EnableGclkGen( static inline whal_Error whal_Pic32cz_Clock_SetMclkDiv( uint8_t div) { - size_t status; + uint32_t status; - whal_Reg_Update(WHAL_PIC32CZ_CLOCK_BASE, WHAL_PIC32CZ_CLOCK_MCLK_DIV1_REG, - WHAL_PIC32CZ_CLOCK_MCLK_DIV1_Msk, - whal_SetBits(WHAL_PIC32CZ_CLOCK_MCLK_DIV1_Msk, - WHAL_PIC32CZ_CLOCK_MCLK_DIV1_Pos, div)); + whal_Reg32_Update(WHAL_PIC32CZ_CLOCK_BASE, WHAL_PIC32CZ_CLOCK_MCLK_DIV1_REG, + WHAL_PIC32CZ_CLOCK_MCLK_DIV1_Msk, + whal_SetBits(WHAL_PIC32CZ_CLOCK_MCLK_DIV1_Msk, + WHAL_PIC32CZ_CLOCK_MCLK_DIV1_Pos, div)); do { - whal_Reg_Get(WHAL_PIC32CZ_CLOCK_BASE, WHAL_PIC32CZ_CLOCK_MCLK_INTFLAG_REG, - WHAL_PIC32CZ_CLOCK_MCLK_INTFLAG_CKRDY_Msk, - WHAL_PIC32CZ_CLOCK_MCLK_INTFLAG_CKRDY_Pos, &status); + whal_Reg32_Get(WHAL_PIC32CZ_CLOCK_BASE, WHAL_PIC32CZ_CLOCK_MCLK_INTFLAG_REG, + WHAL_PIC32CZ_CLOCK_MCLK_INTFLAG_CKRDY_Msk, + WHAL_PIC32CZ_CLOCK_MCLK_INTFLAG_CKRDY_Pos, &status); } while (!status); return WHAL_SUCCESS; } @@ -341,18 +341,18 @@ static inline whal_Error whal_Pic32cz_Clock_SetMclkDiv( static inline whal_Error whal_Pic32cz_Clock_EnablePeriphClk( const whal_Pic32cz_Clock_PeriphClk *clk) { - whal_Reg_Update(WHAL_PIC32CZ_CLOCK_BASE, - WHAL_PIC32CZ_CLOCK_GCLK_PCHCTRLx_REG(clk->gclkPeriphChannel), - WHAL_PIC32CZ_CLOCK_GCLK_PCHCTRLx_GEN_Msk | - WHAL_PIC32CZ_CLOCK_GCLK_PCHCTRLx_CHEN_Msk, - whal_SetBits(WHAL_PIC32CZ_CLOCK_GCLK_PCHCTRLx_GEN_Msk, - WHAL_PIC32CZ_CLOCK_GCLK_PCHCTRLx_GEN_Pos, - clk->gclkPeriphSrc) | - WHAL_PIC32CZ_CLOCK_GCLK_PCHCTRLx_CHEN_Msk); - whal_Reg_Update(WHAL_PIC32CZ_CLOCK_BASE, - WHAL_PIC32CZ_CLOCK_MCLK_CLKxMSK_REG(clk->mclkEnableInst), - clk->mclkEnableMask, - whal_SetBits(clk->mclkEnableMask, clk->mclkEnablePos, 1)); + whal_Reg32_Update(WHAL_PIC32CZ_CLOCK_BASE, + WHAL_PIC32CZ_CLOCK_GCLK_PCHCTRLx_REG(clk->gclkPeriphChannel), + WHAL_PIC32CZ_CLOCK_GCLK_PCHCTRLx_GEN_Msk | + WHAL_PIC32CZ_CLOCK_GCLK_PCHCTRLx_CHEN_Msk, + whal_SetBits(WHAL_PIC32CZ_CLOCK_GCLK_PCHCTRLx_GEN_Msk, + WHAL_PIC32CZ_CLOCK_GCLK_PCHCTRLx_GEN_Pos, + clk->gclkPeriphSrc) | + WHAL_PIC32CZ_CLOCK_GCLK_PCHCTRLx_CHEN_Msk); + whal_Reg32_Update(WHAL_PIC32CZ_CLOCK_BASE, + WHAL_PIC32CZ_CLOCK_MCLK_CLKxMSK_REG(clk->mclkEnableInst), + clk->mclkEnableMask, + whal_SetBits(clk->mclkEnableMask, clk->mclkEnablePos, 1)); return WHAL_SUCCESS; } @@ -366,13 +366,13 @@ static inline whal_Error whal_Pic32cz_Clock_EnablePeriphClk( static inline whal_Error whal_Pic32cz_Clock_DisablePeriphClk( const whal_Pic32cz_Clock_PeriphClk *clk) { - whal_Reg_Update(WHAL_PIC32CZ_CLOCK_BASE, - WHAL_PIC32CZ_CLOCK_MCLK_CLKxMSK_REG(clk->mclkEnableInst), - clk->mclkEnableMask, - whal_SetBits(clk->mclkEnableMask, clk->mclkEnablePos, 0)); - whal_Reg_Update(WHAL_PIC32CZ_CLOCK_BASE, - WHAL_PIC32CZ_CLOCK_GCLK_PCHCTRLx_REG(clk->gclkPeriphChannel), - WHAL_PIC32CZ_CLOCK_GCLK_PCHCTRLx_CHEN_Msk, 0); + whal_Reg32_Update(WHAL_PIC32CZ_CLOCK_BASE, + WHAL_PIC32CZ_CLOCK_MCLK_CLKxMSK_REG(clk->mclkEnableInst), + clk->mclkEnableMask, + whal_SetBits(clk->mclkEnableMask, clk->mclkEnablePos, 0)); + whal_Reg32_Update(WHAL_PIC32CZ_CLOCK_BASE, + WHAL_PIC32CZ_CLOCK_GCLK_PCHCTRLx_REG(clk->gclkPeriphChannel), + WHAL_PIC32CZ_CLOCK_GCLK_PCHCTRLx_CHEN_Msk, 0); return WHAL_SUCCESS; } diff --git a/wolfHAL/clock/stm32c0_rcc.h b/wolfHAL/clock/stm32c0_rcc.h index cd86e5d9..d8ca536e 100644 --- a/wolfHAL/clock/stm32c0_rcc.h +++ b/wolfHAL/clock/stm32c0_rcc.h @@ -103,20 +103,20 @@ typedef struct { static inline whal_Error whal_Stm32c0_Rcc_EnableHsi( whal_Stm32c0_Rcc_HsiDiv hsidiv) { - size_t rdy; + uint32_t rdy; - whal_Reg_Update(WHAL_STM32C0_RCC_BASE, WHAL_STM32C0_RCC_CR_REG, - WHAL_STM32C0_RCC_CR_HSION_Msk, - WHAL_STM32C0_RCC_CR_HSION_Msk); + whal_Reg32_Update(WHAL_STM32C0_RCC_BASE, WHAL_STM32C0_RCC_CR_REG, + WHAL_STM32C0_RCC_CR_HSION_Msk, + WHAL_STM32C0_RCC_CR_HSION_Msk); do { - whal_Reg_Get(WHAL_STM32C0_RCC_BASE, WHAL_STM32C0_RCC_CR_REG, - WHAL_STM32C0_RCC_CR_HSIRDY_Msk, - WHAL_STM32C0_RCC_CR_HSIRDY_Pos, &rdy); + whal_Reg32_Get(WHAL_STM32C0_RCC_BASE, WHAL_STM32C0_RCC_CR_REG, + WHAL_STM32C0_RCC_CR_HSIRDY_Msk, + WHAL_STM32C0_RCC_CR_HSIRDY_Pos, &rdy); } while (!rdy); - whal_Reg_Update(WHAL_STM32C0_RCC_BASE, WHAL_STM32C0_RCC_CR_REG, - WHAL_STM32C0_RCC_CR_HSIDIV_Msk, - whal_SetBits(WHAL_STM32C0_RCC_CR_HSIDIV_Msk, - WHAL_STM32C0_RCC_CR_HSIDIV_Pos, hsidiv)); + whal_Reg32_Update(WHAL_STM32C0_RCC_BASE, WHAL_STM32C0_RCC_CR_REG, + WHAL_STM32C0_RCC_CR_HSIDIV_Msk, + whal_SetBits(WHAL_STM32C0_RCC_CR_HSIDIV_Msk, + WHAL_STM32C0_RCC_CR_HSIDIV_Pos, hsidiv)); return WHAL_SUCCESS; } @@ -132,16 +132,16 @@ static inline whal_Error whal_Stm32c0_Rcc_EnableHsi( static inline whal_Error whal_Stm32c0_Rcc_SetSysClock( whal_Stm32c0_Rcc_SysClockSrc src) { - size_t sws; + uint32_t sws; - whal_Reg_Update(WHAL_STM32C0_RCC_BASE, WHAL_STM32C0_RCC_CFGR_REG, - WHAL_STM32C0_RCC_CFGR_SW_Msk, - whal_SetBits(WHAL_STM32C0_RCC_CFGR_SW_Msk, - WHAL_STM32C0_RCC_CFGR_SW_Pos, src)); + whal_Reg32_Update(WHAL_STM32C0_RCC_BASE, WHAL_STM32C0_RCC_CFGR_REG, + WHAL_STM32C0_RCC_CFGR_SW_Msk, + whal_SetBits(WHAL_STM32C0_RCC_CFGR_SW_Msk, + WHAL_STM32C0_RCC_CFGR_SW_Pos, src)); do { - whal_Reg_Get(WHAL_STM32C0_RCC_BASE, WHAL_STM32C0_RCC_CFGR_REG, - WHAL_STM32C0_RCC_CFGR_SWS_Msk, - WHAL_STM32C0_RCC_CFGR_SWS_Pos, &sws); + whal_Reg32_Get(WHAL_STM32C0_RCC_BASE, WHAL_STM32C0_RCC_CFGR_REG, + WHAL_STM32C0_RCC_CFGR_SWS_Msk, + WHAL_STM32C0_RCC_CFGR_SWS_Pos, &sws); } while (sws != (size_t)src); return WHAL_SUCCESS; } @@ -156,8 +156,8 @@ static inline whal_Error whal_Stm32c0_Rcc_SetSysClock( static inline whal_Error whal_Stm32c0_Rcc_EnablePeriphClk( const whal_Stm32c0_Rcc_PeriphClk *clk) { - whal_Reg_Update(WHAL_STM32C0_RCC_BASE, clk->regOffset, clk->enableMask, - whal_SetBits(clk->enableMask, clk->enablePos, 1)); + whal_Reg32_Update(WHAL_STM32C0_RCC_BASE, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 1)); return WHAL_SUCCESS; } @@ -171,8 +171,8 @@ static inline whal_Error whal_Stm32c0_Rcc_EnablePeriphClk( static inline whal_Error whal_Stm32c0_Rcc_DisablePeriphClk( const whal_Stm32c0_Rcc_PeriphClk *clk) { - whal_Reg_Update(WHAL_STM32C0_RCC_BASE, clk->regOffset, clk->enableMask, - whal_SetBits(clk->enableMask, clk->enablePos, 0)); + whal_Reg32_Update(WHAL_STM32C0_RCC_BASE, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 0)); return WHAL_SUCCESS; } diff --git a/wolfHAL/clock/stm32f0_rcc.h b/wolfHAL/clock/stm32f0_rcc.h index 801cc9c7..38122b98 100644 --- a/wolfHAL/clock/stm32f0_rcc.h +++ b/wolfHAL/clock/stm32f0_rcc.h @@ -135,12 +135,12 @@ typedef struct { static inline whal_Error whal_Stm32f0_Rcc_EnableOsc( const whal_Stm32f0_Rcc_OscCfg *cfg) { - size_t rdy; + uint32_t rdy; - whal_Reg_Update(WHAL_STM32F0_RCC_BASE, cfg->onReg, cfg->onMsk, cfg->onMsk); + whal_Reg32_Update(WHAL_STM32F0_RCC_BASE, cfg->onReg, cfg->onMsk, cfg->onMsk); do { - whal_Reg_Get(WHAL_STM32F0_RCC_BASE, cfg->rdyReg, cfg->rdyMsk, - cfg->rdyPos, &rdy); + whal_Reg32_Get(WHAL_STM32F0_RCC_BASE, cfg->rdyReg, cfg->rdyMsk, + cfg->rdyPos, &rdy); } while (!rdy); return WHAL_SUCCESS; } @@ -155,7 +155,7 @@ static inline whal_Error whal_Stm32f0_Rcc_EnableOsc( static inline whal_Error whal_Stm32f0_Rcc_DisableOsc( const whal_Stm32f0_Rcc_OscCfg *cfg) { - whal_Reg_Update(WHAL_STM32F0_RCC_BASE, cfg->onReg, cfg->onMsk, 0); + whal_Reg32_Update(WHAL_STM32F0_RCC_BASE, cfg->onReg, cfg->onMsk, 0); return WHAL_SUCCESS; } @@ -173,39 +173,39 @@ static inline whal_Error whal_Stm32f0_Rcc_DisableOsc( static inline whal_Error whal_Stm32f0_Rcc_EnablePll( const whal_Stm32f0_Rcc_PllCfg *cfg) { - size_t rdy; + uint32_t rdy; uint32_t pllsrc; /* Disable PLL before reconfiguring. */ - whal_Reg_Update(WHAL_STM32F0_RCC_BASE, WHAL_STM32F0_RCC_CR_REG, - WHAL_STM32F0_RCC_CR_PLLON_Msk, 0); + whal_Reg32_Update(WHAL_STM32F0_RCC_BASE, WHAL_STM32F0_RCC_CR_REG, + WHAL_STM32F0_RCC_CR_PLLON_Msk, 0); - whal_Reg_Update(WHAL_STM32F0_RCC_BASE, WHAL_STM32F0_RCC_CFGR2_REG, - WHAL_STM32F0_RCC_CFGR2_PREDIV_Msk, - whal_SetBits(WHAL_STM32F0_RCC_CFGR2_PREDIV_Msk, - WHAL_STM32F0_RCC_CFGR2_PREDIV_Pos, - cfg->prediv - 1)); - whal_Reg_Update(WHAL_STM32F0_RCC_BASE, WHAL_STM32F0_RCC_CFGR_REG, - WHAL_STM32F0_RCC_CFGR_PLLMUL_Msk, - whal_SetBits(WHAL_STM32F0_RCC_CFGR_PLLMUL_Msk, - WHAL_STM32F0_RCC_CFGR_PLLMUL_Pos, - cfg->pllmul - 2)); + whal_Reg32_Update(WHAL_STM32F0_RCC_BASE, WHAL_STM32F0_RCC_CFGR2_REG, + WHAL_STM32F0_RCC_CFGR2_PREDIV_Msk, + whal_SetBits(WHAL_STM32F0_RCC_CFGR2_PREDIV_Msk, + WHAL_STM32F0_RCC_CFGR2_PREDIV_Pos, + cfg->prediv - 1)); + whal_Reg32_Update(WHAL_STM32F0_RCC_BASE, WHAL_STM32F0_RCC_CFGR_REG, + WHAL_STM32F0_RCC_CFGR_PLLMUL_Msk, + whal_SetBits(WHAL_STM32F0_RCC_CFGR_PLLMUL_Msk, + WHAL_STM32F0_RCC_CFGR_PLLMUL_Pos, + cfg->pllmul - 2)); pllsrc = (cfg->clkSrc == WHAL_STM32F0_RCC_PLLSRC_HSE_PREDIV || cfg->clkSrc == WHAL_STM32F0_RCC_PLLSRC_HSI48_PREDIV) ? 1 : 0; - whal_Reg_Update(WHAL_STM32F0_RCC_BASE, WHAL_STM32F0_RCC_CFGR_REG, - WHAL_STM32F0_RCC_CFGR_PLLSRC_Msk, - whal_SetBits(WHAL_STM32F0_RCC_CFGR_PLLSRC_Msk, - WHAL_STM32F0_RCC_CFGR_PLLSRC_Pos, - pllsrc)); + whal_Reg32_Update(WHAL_STM32F0_RCC_BASE, WHAL_STM32F0_RCC_CFGR_REG, + WHAL_STM32F0_RCC_CFGR_PLLSRC_Msk, + whal_SetBits(WHAL_STM32F0_RCC_CFGR_PLLSRC_Msk, + WHAL_STM32F0_RCC_CFGR_PLLSRC_Pos, + pllsrc)); - whal_Reg_Update(WHAL_STM32F0_RCC_BASE, WHAL_STM32F0_RCC_CR_REG, - WHAL_STM32F0_RCC_CR_PLLON_Msk, - WHAL_STM32F0_RCC_CR_PLLON_Msk); + whal_Reg32_Update(WHAL_STM32F0_RCC_BASE, WHAL_STM32F0_RCC_CR_REG, + WHAL_STM32F0_RCC_CR_PLLON_Msk, + WHAL_STM32F0_RCC_CR_PLLON_Msk); do { - whal_Reg_Get(WHAL_STM32F0_RCC_BASE, WHAL_STM32F0_RCC_CR_REG, - WHAL_STM32F0_RCC_CR_PLLRDY_Msk, - WHAL_STM32F0_RCC_CR_PLLRDY_Pos, &rdy); + whal_Reg32_Get(WHAL_STM32F0_RCC_BASE, WHAL_STM32F0_RCC_CR_REG, + WHAL_STM32F0_RCC_CR_PLLRDY_Msk, + WHAL_STM32F0_RCC_CR_PLLRDY_Pos, &rdy); } while (!rdy); return WHAL_SUCCESS; } @@ -217,8 +217,8 @@ static inline whal_Error whal_Stm32f0_Rcc_EnablePll( */ static inline whal_Error whal_Stm32f0_Rcc_DisablePll(void) { - whal_Reg_Update(WHAL_STM32F0_RCC_BASE, WHAL_STM32F0_RCC_CR_REG, - WHAL_STM32F0_RCC_CR_PLLON_Msk, 0); + whal_Reg32_Update(WHAL_STM32F0_RCC_BASE, WHAL_STM32F0_RCC_CR_REG, + WHAL_STM32F0_RCC_CR_PLLON_Msk, 0); return WHAL_SUCCESS; } @@ -232,16 +232,16 @@ static inline whal_Error whal_Stm32f0_Rcc_DisablePll(void) static inline whal_Error whal_Stm32f0_Rcc_SetSysClock( whal_Stm32f0_Rcc_SysClockSrc src) { - size_t sws; + uint32_t sws; - whal_Reg_Update(WHAL_STM32F0_RCC_BASE, WHAL_STM32F0_RCC_CFGR_REG, - WHAL_STM32F0_RCC_CFGR_SW_Msk, - whal_SetBits(WHAL_STM32F0_RCC_CFGR_SW_Msk, - WHAL_STM32F0_RCC_CFGR_SW_Pos, src)); + whal_Reg32_Update(WHAL_STM32F0_RCC_BASE, WHAL_STM32F0_RCC_CFGR_REG, + WHAL_STM32F0_RCC_CFGR_SW_Msk, + whal_SetBits(WHAL_STM32F0_RCC_CFGR_SW_Msk, + WHAL_STM32F0_RCC_CFGR_SW_Pos, src)); do { - whal_Reg_Get(WHAL_STM32F0_RCC_BASE, WHAL_STM32F0_RCC_CFGR_REG, - WHAL_STM32F0_RCC_CFGR_SWS_Msk, - WHAL_STM32F0_RCC_CFGR_SWS_Pos, &sws); + whal_Reg32_Get(WHAL_STM32F0_RCC_BASE, WHAL_STM32F0_RCC_CFGR_REG, + WHAL_STM32F0_RCC_CFGR_SWS_Msk, + WHAL_STM32F0_RCC_CFGR_SWS_Pos, &sws); } while (sws != (size_t)src); return WHAL_SUCCESS; } @@ -256,8 +256,8 @@ static inline whal_Error whal_Stm32f0_Rcc_SetSysClock( static inline whal_Error whal_Stm32f0_Rcc_EnablePeriphClk( const whal_Stm32f0_Rcc_PeriphClk *clk) { - whal_Reg_Update(WHAL_STM32F0_RCC_BASE, clk->regOffset, clk->enableMask, - whal_SetBits(clk->enableMask, clk->enablePos, 1)); + whal_Reg32_Update(WHAL_STM32F0_RCC_BASE, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 1)); return WHAL_SUCCESS; } @@ -271,8 +271,8 @@ static inline whal_Error whal_Stm32f0_Rcc_EnablePeriphClk( static inline whal_Error whal_Stm32f0_Rcc_DisablePeriphClk( const whal_Stm32f0_Rcc_PeriphClk *clk) { - whal_Reg_Update(WHAL_STM32F0_RCC_BASE, clk->regOffset, clk->enableMask, - whal_SetBits(clk->enableMask, clk->enablePos, 0)); + whal_Reg32_Update(WHAL_STM32F0_RCC_BASE, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 0)); return WHAL_SUCCESS; } diff --git a/wolfHAL/clock/stm32f3_rcc.h b/wolfHAL/clock/stm32f3_rcc.h index 341f5fa4..bd56fa7b 100644 --- a/wolfHAL/clock/stm32f3_rcc.h +++ b/wolfHAL/clock/stm32f3_rcc.h @@ -140,12 +140,12 @@ typedef struct { static inline whal_Error whal_Stm32f3_Rcc_EnableOsc( const whal_Stm32f3_Rcc_OscCfg *cfg) { - size_t rdy; + uint32_t rdy; - whal_Reg_Update(WHAL_STM32F3_RCC_BASE, cfg->onReg, cfg->onMsk, cfg->onMsk); + whal_Reg32_Update(WHAL_STM32F3_RCC_BASE, cfg->onReg, cfg->onMsk, cfg->onMsk); do { - whal_Reg_Get(WHAL_STM32F3_RCC_BASE, cfg->rdyReg, cfg->rdyMsk, - cfg->rdyPos, &rdy); + whal_Reg32_Get(WHAL_STM32F3_RCC_BASE, cfg->rdyReg, cfg->rdyMsk, + cfg->rdyPos, &rdy); } while (!rdy); return WHAL_SUCCESS; } @@ -160,7 +160,7 @@ static inline whal_Error whal_Stm32f3_Rcc_EnableOsc( static inline whal_Error whal_Stm32f3_Rcc_DisableOsc( const whal_Stm32f3_Rcc_OscCfg *cfg) { - whal_Reg_Update(WHAL_STM32F3_RCC_BASE, cfg->onReg, cfg->onMsk, 0); + whal_Reg32_Update(WHAL_STM32F3_RCC_BASE, cfg->onReg, cfg->onMsk, 0); return WHAL_SUCCESS; } @@ -177,38 +177,38 @@ static inline whal_Error whal_Stm32f3_Rcc_DisableOsc( static inline whal_Error whal_Stm32f3_Rcc_EnablePll( const whal_Stm32f3_Rcc_PllCfg *cfg) { - size_t rdy; + uint32_t rdy; uint32_t pllsrc; /* Disable PLL before reconfiguring. */ - whal_Reg_Update(WHAL_STM32F3_RCC_BASE, WHAL_STM32F3_RCC_CR_REG, - WHAL_STM32F3_RCC_CR_PLLON_Msk, 0); + whal_Reg32_Update(WHAL_STM32F3_RCC_BASE, WHAL_STM32F3_RCC_CR_REG, + WHAL_STM32F3_RCC_CR_PLLON_Msk, 0); - whal_Reg_Update(WHAL_STM32F3_RCC_BASE, WHAL_STM32F3_RCC_CFGR2_REG, - WHAL_STM32F3_RCC_CFGR2_PREDIV_Msk, - whal_SetBits(WHAL_STM32F3_RCC_CFGR2_PREDIV_Msk, - WHAL_STM32F3_RCC_CFGR2_PREDIV_Pos, - cfg->prediv - 1)); - whal_Reg_Update(WHAL_STM32F3_RCC_BASE, WHAL_STM32F3_RCC_CFGR_REG, - WHAL_STM32F3_RCC_CFGR_PLLMUL_Msk, - whal_SetBits(WHAL_STM32F3_RCC_CFGR_PLLMUL_Msk, - WHAL_STM32F3_RCC_CFGR_PLLMUL_Pos, - cfg->pllmul - 2)); + whal_Reg32_Update(WHAL_STM32F3_RCC_BASE, WHAL_STM32F3_RCC_CFGR2_REG, + WHAL_STM32F3_RCC_CFGR2_PREDIV_Msk, + whal_SetBits(WHAL_STM32F3_RCC_CFGR2_PREDIV_Msk, + WHAL_STM32F3_RCC_CFGR2_PREDIV_Pos, + cfg->prediv - 1)); + whal_Reg32_Update(WHAL_STM32F3_RCC_BASE, WHAL_STM32F3_RCC_CFGR_REG, + WHAL_STM32F3_RCC_CFGR_PLLMUL_Msk, + whal_SetBits(WHAL_STM32F3_RCC_CFGR_PLLMUL_Msk, + WHAL_STM32F3_RCC_CFGR_PLLMUL_Pos, + cfg->pllmul - 2)); pllsrc = (cfg->clkSrc == WHAL_STM32F3_RCC_PLLSRC_HSE_PREDIV) ? 1 : 0; - whal_Reg_Update(WHAL_STM32F3_RCC_BASE, WHAL_STM32F3_RCC_CFGR_REG, - WHAL_STM32F3_RCC_CFGR_PLLSRC_Msk, - whal_SetBits(WHAL_STM32F3_RCC_CFGR_PLLSRC_Msk, - WHAL_STM32F3_RCC_CFGR_PLLSRC_Pos, - pllsrc)); + whal_Reg32_Update(WHAL_STM32F3_RCC_BASE, WHAL_STM32F3_RCC_CFGR_REG, + WHAL_STM32F3_RCC_CFGR_PLLSRC_Msk, + whal_SetBits(WHAL_STM32F3_RCC_CFGR_PLLSRC_Msk, + WHAL_STM32F3_RCC_CFGR_PLLSRC_Pos, + pllsrc)); - whal_Reg_Update(WHAL_STM32F3_RCC_BASE, WHAL_STM32F3_RCC_CR_REG, - WHAL_STM32F3_RCC_CR_PLLON_Msk, - WHAL_STM32F3_RCC_CR_PLLON_Msk); + whal_Reg32_Update(WHAL_STM32F3_RCC_BASE, WHAL_STM32F3_RCC_CR_REG, + WHAL_STM32F3_RCC_CR_PLLON_Msk, + WHAL_STM32F3_RCC_CR_PLLON_Msk); do { - whal_Reg_Get(WHAL_STM32F3_RCC_BASE, WHAL_STM32F3_RCC_CR_REG, - WHAL_STM32F3_RCC_CR_PLLRDY_Msk, - WHAL_STM32F3_RCC_CR_PLLRDY_Pos, &rdy); + whal_Reg32_Get(WHAL_STM32F3_RCC_BASE, WHAL_STM32F3_RCC_CR_REG, + WHAL_STM32F3_RCC_CR_PLLRDY_Msk, + WHAL_STM32F3_RCC_CR_PLLRDY_Pos, &rdy); } while (!rdy); return WHAL_SUCCESS; } @@ -220,8 +220,8 @@ static inline whal_Error whal_Stm32f3_Rcc_EnablePll( */ static inline whal_Error whal_Stm32f3_Rcc_DisablePll(void) { - whal_Reg_Update(WHAL_STM32F3_RCC_BASE, WHAL_STM32F3_RCC_CR_REG, - WHAL_STM32F3_RCC_CR_PLLON_Msk, 0); + whal_Reg32_Update(WHAL_STM32F3_RCC_BASE, WHAL_STM32F3_RCC_CR_REG, + WHAL_STM32F3_RCC_CR_PLLON_Msk, 0); return WHAL_SUCCESS; } @@ -235,16 +235,16 @@ static inline whal_Error whal_Stm32f3_Rcc_DisablePll(void) static inline whal_Error whal_Stm32f3_Rcc_SetSysClock( whal_Stm32f3_Rcc_SysClockSrc src) { - size_t sws; + uint32_t sws; - whal_Reg_Update(WHAL_STM32F3_RCC_BASE, WHAL_STM32F3_RCC_CFGR_REG, - WHAL_STM32F3_RCC_CFGR_SW_Msk, - whal_SetBits(WHAL_STM32F3_RCC_CFGR_SW_Msk, - WHAL_STM32F3_RCC_CFGR_SW_Pos, src)); + whal_Reg32_Update(WHAL_STM32F3_RCC_BASE, WHAL_STM32F3_RCC_CFGR_REG, + WHAL_STM32F3_RCC_CFGR_SW_Msk, + whal_SetBits(WHAL_STM32F3_RCC_CFGR_SW_Msk, + WHAL_STM32F3_RCC_CFGR_SW_Pos, src)); do { - whal_Reg_Get(WHAL_STM32F3_RCC_BASE, WHAL_STM32F3_RCC_CFGR_REG, - WHAL_STM32F3_RCC_CFGR_SWS_Msk, - WHAL_STM32F3_RCC_CFGR_SWS_Pos, &sws); + whal_Reg32_Get(WHAL_STM32F3_RCC_BASE, WHAL_STM32F3_RCC_CFGR_REG, + WHAL_STM32F3_RCC_CFGR_SWS_Msk, + WHAL_STM32F3_RCC_CFGR_SWS_Pos, &sws); } while (sws != (size_t)src); return WHAL_SUCCESS; } @@ -259,11 +259,11 @@ static inline whal_Error whal_Stm32f3_Rcc_SetSysClock( static inline whal_Error whal_Stm32f3_Rcc_SetI2c1ClkSrc( whal_Stm32f3_Rcc_I2c1ClkSrc src) { - whal_Reg_Update(WHAL_STM32F3_RCC_BASE, WHAL_STM32F3_RCC_CFGR3_REG, - WHAL_STM32F3_RCC_CFGR3_I2C1SW_Msk, - whal_SetBits(WHAL_STM32F3_RCC_CFGR3_I2C1SW_Msk, - WHAL_STM32F3_RCC_CFGR3_I2C1SW_Pos, - src)); + whal_Reg32_Update(WHAL_STM32F3_RCC_BASE, WHAL_STM32F3_RCC_CFGR3_REG, + WHAL_STM32F3_RCC_CFGR3_I2C1SW_Msk, + whal_SetBits(WHAL_STM32F3_RCC_CFGR3_I2C1SW_Msk, + WHAL_STM32F3_RCC_CFGR3_I2C1SW_Pos, + src)); return WHAL_SUCCESS; } @@ -277,8 +277,8 @@ static inline whal_Error whal_Stm32f3_Rcc_SetI2c1ClkSrc( static inline whal_Error whal_Stm32f3_Rcc_EnablePeriphClk( const whal_Stm32f3_Rcc_PeriphClk *clk) { - whal_Reg_Update(WHAL_STM32F3_RCC_BASE, clk->regOffset, clk->enableMask, - whal_SetBits(clk->enableMask, clk->enablePos, 1)); + whal_Reg32_Update(WHAL_STM32F3_RCC_BASE, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 1)); return WHAL_SUCCESS; } @@ -292,8 +292,8 @@ static inline whal_Error whal_Stm32f3_Rcc_EnablePeriphClk( static inline whal_Error whal_Stm32f3_Rcc_DisablePeriphClk( const whal_Stm32f3_Rcc_PeriphClk *clk) { - whal_Reg_Update(WHAL_STM32F3_RCC_BASE, clk->regOffset, clk->enableMask, - whal_SetBits(clk->enableMask, clk->enablePos, 0)); + whal_Reg32_Update(WHAL_STM32F3_RCC_BASE, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 0)); return WHAL_SUCCESS; } diff --git a/wolfHAL/clock/stm32f4_rcc.h b/wolfHAL/clock/stm32f4_rcc.h index 69fed4dd..c8d54923 100644 --- a/wolfHAL/clock/stm32f4_rcc.h +++ b/wolfHAL/clock/stm32f4_rcc.h @@ -153,12 +153,12 @@ typedef struct { static inline whal_Error whal_Stm32f4_Rcc_EnableOsc( const whal_Stm32f4_Rcc_OscCfg *cfg) { - size_t rdy; + uint32_t rdy; - whal_Reg_Update(WHAL_STM32F4_RCC_BASE, cfg->onReg, cfg->onMsk, cfg->onMsk); + whal_Reg32_Update(WHAL_STM32F4_RCC_BASE, cfg->onReg, cfg->onMsk, cfg->onMsk); do { - whal_Reg_Get(WHAL_STM32F4_RCC_BASE, cfg->rdyReg, cfg->rdyMsk, - cfg->rdyPos, &rdy); + whal_Reg32_Get(WHAL_STM32F4_RCC_BASE, cfg->rdyReg, cfg->rdyMsk, + cfg->rdyPos, &rdy); } while (!rdy); return WHAL_SUCCESS; } @@ -173,7 +173,7 @@ static inline whal_Error whal_Stm32f4_Rcc_EnableOsc( static inline whal_Error whal_Stm32f4_Rcc_DisableOsc( const whal_Stm32f4_Rcc_OscCfg *cfg) { - whal_Reg_Update(WHAL_STM32F4_RCC_BASE, cfg->onReg, cfg->onMsk, 0); + whal_Reg32_Update(WHAL_STM32F4_RCC_BASE, cfg->onReg, cfg->onMsk, 0); return WHAL_SUCCESS; } @@ -190,32 +190,32 @@ static inline whal_Error whal_Stm32f4_Rcc_DisableOsc( static inline whal_Error whal_Stm32f4_Rcc_EnablePll( const whal_Stm32f4_Rcc_PllCfg *cfg) { - size_t rdy; + uint32_t rdy; /* Disable PLL before reconfiguring. */ - whal_Reg_Update(WHAL_STM32F4_RCC_BASE, WHAL_STM32F4_RCC_CR_REG, - WHAL_STM32F4_RCC_CR_PLLON_Msk, 0); + whal_Reg32_Update(WHAL_STM32F4_RCC_BASE, WHAL_STM32F4_RCC_CR_REG, + WHAL_STM32F4_RCC_CR_PLLON_Msk, 0); - whal_Reg_Update(WHAL_STM32F4_RCC_BASE, WHAL_STM32F4_RCC_PLLCFGR_REG, - WHAL_STM32F4_RCC_PLLCFGR_Msk, - whal_SetBits(WHAL_STM32F4_RCC_PLLCFGR_PLLM_Msk, - WHAL_STM32F4_RCC_PLLCFGR_PLLM_Pos, cfg->m) | - whal_SetBits(WHAL_STM32F4_RCC_PLLCFGR_PLLN_Msk, - WHAL_STM32F4_RCC_PLLCFGR_PLLN_Pos, cfg->n) | - whal_SetBits(WHAL_STM32F4_RCC_PLLCFGR_PLLP_Msk, - WHAL_STM32F4_RCC_PLLCFGR_PLLP_Pos, cfg->p) | - whal_SetBits(WHAL_STM32F4_RCC_PLLCFGR_PLLSRC_Msk, - WHAL_STM32F4_RCC_PLLCFGR_PLLSRC_Pos, cfg->clkSrc) | - whal_SetBits(WHAL_STM32F4_RCC_PLLCFGR_PLLQ_Msk, - WHAL_STM32F4_RCC_PLLCFGR_PLLQ_Pos, cfg->q)); + whal_Reg32_Update(WHAL_STM32F4_RCC_BASE, WHAL_STM32F4_RCC_PLLCFGR_REG, + WHAL_STM32F4_RCC_PLLCFGR_Msk, + whal_SetBits(WHAL_STM32F4_RCC_PLLCFGR_PLLM_Msk, + WHAL_STM32F4_RCC_PLLCFGR_PLLM_Pos, cfg->m) | + whal_SetBits(WHAL_STM32F4_RCC_PLLCFGR_PLLN_Msk, + WHAL_STM32F4_RCC_PLLCFGR_PLLN_Pos, cfg->n) | + whal_SetBits(WHAL_STM32F4_RCC_PLLCFGR_PLLP_Msk, + WHAL_STM32F4_RCC_PLLCFGR_PLLP_Pos, cfg->p) | + whal_SetBits(WHAL_STM32F4_RCC_PLLCFGR_PLLSRC_Msk, + WHAL_STM32F4_RCC_PLLCFGR_PLLSRC_Pos, cfg->clkSrc) | + whal_SetBits(WHAL_STM32F4_RCC_PLLCFGR_PLLQ_Msk, + WHAL_STM32F4_RCC_PLLCFGR_PLLQ_Pos, cfg->q)); - whal_Reg_Update(WHAL_STM32F4_RCC_BASE, WHAL_STM32F4_RCC_CR_REG, - WHAL_STM32F4_RCC_CR_PLLON_Msk, - WHAL_STM32F4_RCC_CR_PLLON_Msk); + whal_Reg32_Update(WHAL_STM32F4_RCC_BASE, WHAL_STM32F4_RCC_CR_REG, + WHAL_STM32F4_RCC_CR_PLLON_Msk, + WHAL_STM32F4_RCC_CR_PLLON_Msk); do { - whal_Reg_Get(WHAL_STM32F4_RCC_BASE, WHAL_STM32F4_RCC_CR_REG, - WHAL_STM32F4_RCC_CR_PLLRDY_Msk, - WHAL_STM32F4_RCC_CR_PLLRDY_Pos, &rdy); + whal_Reg32_Get(WHAL_STM32F4_RCC_BASE, WHAL_STM32F4_RCC_CR_REG, + WHAL_STM32F4_RCC_CR_PLLRDY_Msk, + WHAL_STM32F4_RCC_CR_PLLRDY_Pos, &rdy); } while (!rdy); return WHAL_SUCCESS; } @@ -227,8 +227,8 @@ static inline whal_Error whal_Stm32f4_Rcc_EnablePll( */ static inline whal_Error whal_Stm32f4_Rcc_DisablePll(void) { - whal_Reg_Update(WHAL_STM32F4_RCC_BASE, WHAL_STM32F4_RCC_CR_REG, - WHAL_STM32F4_RCC_CR_PLLON_Msk, 0); + whal_Reg32_Update(WHAL_STM32F4_RCC_BASE, WHAL_STM32F4_RCC_CR_REG, + WHAL_STM32F4_RCC_CR_PLLON_Msk, 0); return WHAL_SUCCESS; } @@ -242,13 +242,13 @@ static inline whal_Error whal_Stm32f4_Rcc_DisablePll(void) static inline whal_Error whal_Stm32f4_Rcc_SetBusPrescalers( const whal_Stm32f4_Rcc_BusCfg *cfg) { - whal_Reg_Update(WHAL_STM32F4_RCC_BASE, WHAL_STM32F4_RCC_CFGR_REG, - WHAL_STM32F4_RCC_CFGR_PPRE1_Msk | - WHAL_STM32F4_RCC_CFGR_PPRE2_Msk, - whal_SetBits(WHAL_STM32F4_RCC_CFGR_PPRE1_Msk, - WHAL_STM32F4_RCC_CFGR_PPRE1_Pos, cfg->ppre1) | - whal_SetBits(WHAL_STM32F4_RCC_CFGR_PPRE2_Msk, - WHAL_STM32F4_RCC_CFGR_PPRE2_Pos, cfg->ppre2)); + whal_Reg32_Update(WHAL_STM32F4_RCC_BASE, WHAL_STM32F4_RCC_CFGR_REG, + WHAL_STM32F4_RCC_CFGR_PPRE1_Msk | + WHAL_STM32F4_RCC_CFGR_PPRE2_Msk, + whal_SetBits(WHAL_STM32F4_RCC_CFGR_PPRE1_Msk, + WHAL_STM32F4_RCC_CFGR_PPRE1_Pos, cfg->ppre1) | + whal_SetBits(WHAL_STM32F4_RCC_CFGR_PPRE2_Msk, + WHAL_STM32F4_RCC_CFGR_PPRE2_Pos, cfg->ppre2)); return WHAL_SUCCESS; } @@ -262,16 +262,16 @@ static inline whal_Error whal_Stm32f4_Rcc_SetBusPrescalers( static inline whal_Error whal_Stm32f4_Rcc_SetSysClock( whal_Stm32f4_Rcc_SysClockSrc src) { - size_t sws; + uint32_t sws; - whal_Reg_Update(WHAL_STM32F4_RCC_BASE, WHAL_STM32F4_RCC_CFGR_REG, - WHAL_STM32F4_RCC_CFGR_SW_Msk, - whal_SetBits(WHAL_STM32F4_RCC_CFGR_SW_Msk, - WHAL_STM32F4_RCC_CFGR_SW_Pos, src)); + whal_Reg32_Update(WHAL_STM32F4_RCC_BASE, WHAL_STM32F4_RCC_CFGR_REG, + WHAL_STM32F4_RCC_CFGR_SW_Msk, + whal_SetBits(WHAL_STM32F4_RCC_CFGR_SW_Msk, + WHAL_STM32F4_RCC_CFGR_SW_Pos, src)); do { - whal_Reg_Get(WHAL_STM32F4_RCC_BASE, WHAL_STM32F4_RCC_CFGR_REG, - WHAL_STM32F4_RCC_CFGR_SWS_Msk, - WHAL_STM32F4_RCC_CFGR_SWS_Pos, &sws); + whal_Reg32_Get(WHAL_STM32F4_RCC_BASE, WHAL_STM32F4_RCC_CFGR_REG, + WHAL_STM32F4_RCC_CFGR_SWS_Msk, + WHAL_STM32F4_RCC_CFGR_SWS_Pos, &sws); } while (sws != (size_t)src); return WHAL_SUCCESS; } @@ -286,8 +286,8 @@ static inline whal_Error whal_Stm32f4_Rcc_SetSysClock( static inline whal_Error whal_Stm32f4_Rcc_EnablePeriphClk( const whal_Stm32f4_Rcc_PeriphClk *clk) { - whal_Reg_Update(WHAL_STM32F4_RCC_BASE, clk->regOffset, clk->enableMask, - whal_SetBits(clk->enableMask, clk->enablePos, 1)); + whal_Reg32_Update(WHAL_STM32F4_RCC_BASE, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 1)); return WHAL_SUCCESS; } @@ -301,8 +301,8 @@ static inline whal_Error whal_Stm32f4_Rcc_EnablePeriphClk( static inline whal_Error whal_Stm32f4_Rcc_DisablePeriphClk( const whal_Stm32f4_Rcc_PeriphClk *clk) { - whal_Reg_Update(WHAL_STM32F4_RCC_BASE, clk->regOffset, clk->enableMask, - whal_SetBits(clk->enableMask, clk->enablePos, 0)); + whal_Reg32_Update(WHAL_STM32F4_RCC_BASE, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 0)); return WHAL_SUCCESS; } diff --git a/wolfHAL/clock/stm32h5_rcc.h b/wolfHAL/clock/stm32h5_rcc.h index cdbc9bac..d35e9d08 100644 --- a/wolfHAL/clock/stm32h5_rcc.h +++ b/wolfHAL/clock/stm32h5_rcc.h @@ -151,12 +151,12 @@ typedef struct { static inline whal_Error whal_Stm32h5_Rcc_EnableOsc( const whal_Stm32h5_Rcc_OscCfg *cfg) { - size_t rdy; + uint32_t rdy; - whal_Reg_Update(WHAL_STM32H5_RCC_BASE, cfg->onReg, cfg->onMsk, cfg->onMsk); + whal_Reg32_Update(WHAL_STM32H5_RCC_BASE, cfg->onReg, cfg->onMsk, cfg->onMsk); do { - whal_Reg_Get(WHAL_STM32H5_RCC_BASE, cfg->rdyReg, cfg->rdyMsk, - cfg->rdyPos, &rdy); + whal_Reg32_Get(WHAL_STM32H5_RCC_BASE, cfg->rdyReg, cfg->rdyMsk, + cfg->rdyPos, &rdy); } while (!rdy); return WHAL_SUCCESS; } @@ -171,7 +171,7 @@ static inline whal_Error whal_Stm32h5_Rcc_EnableOsc( static inline whal_Error whal_Stm32h5_Rcc_DisableOsc( const whal_Stm32h5_Rcc_OscCfg *cfg) { - whal_Reg_Update(WHAL_STM32H5_RCC_BASE, cfg->onReg, cfg->onMsk, 0); + whal_Reg32_Update(WHAL_STM32H5_RCC_BASE, cfg->onReg, cfg->onMsk, 0); return WHAL_SUCCESS; } @@ -188,53 +188,53 @@ static inline whal_Error whal_Stm32h5_Rcc_DisableOsc( static inline whal_Error whal_Stm32h5_Rcc_EnablePll1( const whal_Stm32h5_Rcc_PllCfg *cfg) { - size_t rdy; + uint32_t rdy; - whal_Reg_Update(WHAL_STM32H5_RCC_BASE, WHAL_STM32H5_RCC_CR_REG, - WHAL_STM32H5_RCC_CR_PLL1ON_Msk, 0); + whal_Reg32_Update(WHAL_STM32H5_RCC_BASE, WHAL_STM32H5_RCC_CR_REG, + WHAL_STM32H5_RCC_CR_PLL1ON_Msk, 0); do { - whal_Reg_Get(WHAL_STM32H5_RCC_BASE, WHAL_STM32H5_RCC_CR_REG, - WHAL_STM32H5_RCC_CR_PLL1RDY_Msk, - WHAL_STM32H5_RCC_CR_PLL1RDY_Pos, &rdy); + whal_Reg32_Get(WHAL_STM32H5_RCC_BASE, WHAL_STM32H5_RCC_CR_REG, + WHAL_STM32H5_RCC_CR_PLL1RDY_Msk, + WHAL_STM32H5_RCC_CR_PLL1RDY_Pos, &rdy); } while (rdy); - whal_Reg_Update(WHAL_STM32H5_RCC_BASE, WHAL_STM32H5_RCC_PLL1CFGR_REG, - WHAL_STM32H5_RCC_PLL1CFGR_PLL1SRC_Msk | - WHAL_STM32H5_RCC_PLL1CFGR_PLL1M_Msk | - WHAL_STM32H5_RCC_PLL1CFGR_PLL1PEN_Msk | - WHAL_STM32H5_RCC_PLL1CFGR_PLL1QEN_Msk | - WHAL_STM32H5_RCC_PLL1CFGR_PLL1REN_Msk, - whal_SetBits(WHAL_STM32H5_RCC_PLL1CFGR_PLL1SRC_Msk, - WHAL_STM32H5_RCC_PLL1CFGR_PLL1SRC_Pos, cfg->clkSrc) | - whal_SetBits(WHAL_STM32H5_RCC_PLL1CFGR_PLL1M_Msk, - WHAL_STM32H5_RCC_PLL1CFGR_PLL1M_Pos, cfg->m) | - whal_SetBits(WHAL_STM32H5_RCC_PLL1CFGR_PLL1PEN_Msk, - WHAL_STM32H5_RCC_PLL1CFGR_PLL1PEN_Pos, 1) | - whal_SetBits(WHAL_STM32H5_RCC_PLL1CFGR_PLL1QEN_Msk, - WHAL_STM32H5_RCC_PLL1CFGR_PLL1QEN_Pos, 1) | - whal_SetBits(WHAL_STM32H5_RCC_PLL1CFGR_PLL1REN_Msk, - WHAL_STM32H5_RCC_PLL1CFGR_PLL1REN_Pos, 1)); - whal_Reg_Update(WHAL_STM32H5_RCC_BASE, WHAL_STM32H5_RCC_PLL1DIVR_REG, - WHAL_STM32H5_RCC_PLL1DIVR_PLL1N_Msk | - WHAL_STM32H5_RCC_PLL1DIVR_PLL1P_Msk | - WHAL_STM32H5_RCC_PLL1DIVR_PLL1Q_Msk | - WHAL_STM32H5_RCC_PLL1DIVR_PLL1R_Msk, - whal_SetBits(WHAL_STM32H5_RCC_PLL1DIVR_PLL1N_Msk, - WHAL_STM32H5_RCC_PLL1DIVR_PLL1N_Pos, cfg->n) | - whal_SetBits(WHAL_STM32H5_RCC_PLL1DIVR_PLL1P_Msk, - WHAL_STM32H5_RCC_PLL1DIVR_PLL1P_Pos, cfg->p) | - whal_SetBits(WHAL_STM32H5_RCC_PLL1DIVR_PLL1Q_Msk, - WHAL_STM32H5_RCC_PLL1DIVR_PLL1Q_Pos, cfg->q) | - whal_SetBits(WHAL_STM32H5_RCC_PLL1DIVR_PLL1R_Msk, - WHAL_STM32H5_RCC_PLL1DIVR_PLL1R_Pos, cfg->r)); + whal_Reg32_Update(WHAL_STM32H5_RCC_BASE, WHAL_STM32H5_RCC_PLL1CFGR_REG, + WHAL_STM32H5_RCC_PLL1CFGR_PLL1SRC_Msk | + WHAL_STM32H5_RCC_PLL1CFGR_PLL1M_Msk | + WHAL_STM32H5_RCC_PLL1CFGR_PLL1PEN_Msk | + WHAL_STM32H5_RCC_PLL1CFGR_PLL1QEN_Msk | + WHAL_STM32H5_RCC_PLL1CFGR_PLL1REN_Msk, + whal_SetBits(WHAL_STM32H5_RCC_PLL1CFGR_PLL1SRC_Msk, + WHAL_STM32H5_RCC_PLL1CFGR_PLL1SRC_Pos, cfg->clkSrc) | + whal_SetBits(WHAL_STM32H5_RCC_PLL1CFGR_PLL1M_Msk, + WHAL_STM32H5_RCC_PLL1CFGR_PLL1M_Pos, cfg->m) | + whal_SetBits(WHAL_STM32H5_RCC_PLL1CFGR_PLL1PEN_Msk, + WHAL_STM32H5_RCC_PLL1CFGR_PLL1PEN_Pos, 1) | + whal_SetBits(WHAL_STM32H5_RCC_PLL1CFGR_PLL1QEN_Msk, + WHAL_STM32H5_RCC_PLL1CFGR_PLL1QEN_Pos, 1) | + whal_SetBits(WHAL_STM32H5_RCC_PLL1CFGR_PLL1REN_Msk, + WHAL_STM32H5_RCC_PLL1CFGR_PLL1REN_Pos, 1)); + whal_Reg32_Update(WHAL_STM32H5_RCC_BASE, WHAL_STM32H5_RCC_PLL1DIVR_REG, + WHAL_STM32H5_RCC_PLL1DIVR_PLL1N_Msk | + WHAL_STM32H5_RCC_PLL1DIVR_PLL1P_Msk | + WHAL_STM32H5_RCC_PLL1DIVR_PLL1Q_Msk | + WHAL_STM32H5_RCC_PLL1DIVR_PLL1R_Msk, + whal_SetBits(WHAL_STM32H5_RCC_PLL1DIVR_PLL1N_Msk, + WHAL_STM32H5_RCC_PLL1DIVR_PLL1N_Pos, cfg->n) | + whal_SetBits(WHAL_STM32H5_RCC_PLL1DIVR_PLL1P_Msk, + WHAL_STM32H5_RCC_PLL1DIVR_PLL1P_Pos, cfg->p) | + whal_SetBits(WHAL_STM32H5_RCC_PLL1DIVR_PLL1Q_Msk, + WHAL_STM32H5_RCC_PLL1DIVR_PLL1Q_Pos, cfg->q) | + whal_SetBits(WHAL_STM32H5_RCC_PLL1DIVR_PLL1R_Msk, + WHAL_STM32H5_RCC_PLL1DIVR_PLL1R_Pos, cfg->r)); - whal_Reg_Update(WHAL_STM32H5_RCC_BASE, WHAL_STM32H5_RCC_CR_REG, - WHAL_STM32H5_RCC_CR_PLL1ON_Msk, - WHAL_STM32H5_RCC_CR_PLL1ON_Msk); + whal_Reg32_Update(WHAL_STM32H5_RCC_BASE, WHAL_STM32H5_RCC_CR_REG, + WHAL_STM32H5_RCC_CR_PLL1ON_Msk, + WHAL_STM32H5_RCC_CR_PLL1ON_Msk); do { - whal_Reg_Get(WHAL_STM32H5_RCC_BASE, WHAL_STM32H5_RCC_CR_REG, - WHAL_STM32H5_RCC_CR_PLL1RDY_Msk, - WHAL_STM32H5_RCC_CR_PLL1RDY_Pos, &rdy); + whal_Reg32_Get(WHAL_STM32H5_RCC_BASE, WHAL_STM32H5_RCC_CR_REG, + WHAL_STM32H5_RCC_CR_PLL1RDY_Msk, + WHAL_STM32H5_RCC_CR_PLL1RDY_Pos, &rdy); } while (!rdy); return WHAL_SUCCESS; } @@ -247,8 +247,8 @@ static inline whal_Error whal_Stm32h5_Rcc_EnablePll1( */ static inline whal_Error whal_Stm32h5_Rcc_DisablePll1(void) { - whal_Reg_Update(WHAL_STM32H5_RCC_BASE, WHAL_STM32H5_RCC_CR_REG, - WHAL_STM32H5_RCC_CR_PLL1ON_Msk, 0); + whal_Reg32_Update(WHAL_STM32H5_RCC_BASE, WHAL_STM32H5_RCC_CR_REG, + WHAL_STM32H5_RCC_CR_PLL1ON_Msk, 0); return WHAL_SUCCESS; } @@ -262,16 +262,16 @@ static inline whal_Error whal_Stm32h5_Rcc_DisablePll1(void) static inline whal_Error whal_Stm32h5_Rcc_SetSysClock( whal_Stm32h5_Rcc_SysClockSrc src) { - size_t sws; + uint32_t sws; - whal_Reg_Update(WHAL_STM32H5_RCC_BASE, WHAL_STM32H5_RCC_CFGR1_REG, - WHAL_STM32H5_RCC_CFGR1_SW_Msk, - whal_SetBits(WHAL_STM32H5_RCC_CFGR1_SW_Msk, - WHAL_STM32H5_RCC_CFGR1_SW_Pos, src)); + whal_Reg32_Update(WHAL_STM32H5_RCC_BASE, WHAL_STM32H5_RCC_CFGR1_REG, + WHAL_STM32H5_RCC_CFGR1_SW_Msk, + whal_SetBits(WHAL_STM32H5_RCC_CFGR1_SW_Msk, + WHAL_STM32H5_RCC_CFGR1_SW_Pos, src)); do { - whal_Reg_Get(WHAL_STM32H5_RCC_BASE, WHAL_STM32H5_RCC_CFGR1_REG, - WHAL_STM32H5_RCC_CFGR1_SWS_Msk, - WHAL_STM32H5_RCC_CFGR1_SWS_Pos, &sws); + whal_Reg32_Get(WHAL_STM32H5_RCC_BASE, WHAL_STM32H5_RCC_CFGR1_REG, + WHAL_STM32H5_RCC_CFGR1_SWS_Msk, + WHAL_STM32H5_RCC_CFGR1_SWS_Pos, &sws); } while (sws != (size_t)src); return WHAL_SUCCESS; } @@ -288,10 +288,10 @@ static inline whal_Error whal_Stm32h5_Rcc_SetSysClock( static inline whal_Error whal_Stm32h5_Rcc_SetHsiDiv( uint8_t div) { - whal_Reg_Update(WHAL_STM32H5_RCC_BASE, WHAL_STM32H5_RCC_CR_REG, - WHAL_STM32H5_RCC_CR_HSIDIV_Msk, - whal_SetBits(WHAL_STM32H5_RCC_CR_HSIDIV_Msk, - WHAL_STM32H5_RCC_CR_HSIDIV_Pos, div)); + whal_Reg32_Update(WHAL_STM32H5_RCC_BASE, WHAL_STM32H5_RCC_CR_REG, + WHAL_STM32H5_RCC_CR_HSIDIV_Msk, + whal_SetBits(WHAL_STM32H5_RCC_CR_HSIDIV_Msk, + WHAL_STM32H5_RCC_CR_HSIDIV_Pos, div)); return WHAL_SUCCESS; } @@ -305,8 +305,8 @@ static inline whal_Error whal_Stm32h5_Rcc_SetHsiDiv( static inline whal_Error whal_Stm32h5_Rcc_EnablePeriphClk( const whal_Stm32h5_Rcc_PeriphClk *clk) { - whal_Reg_Update(WHAL_STM32H5_RCC_BASE, clk->regOffset, clk->enableMask, - whal_SetBits(clk->enableMask, clk->enablePos, 1)); + whal_Reg32_Update(WHAL_STM32H5_RCC_BASE, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 1)); return WHAL_SUCCESS; } @@ -320,8 +320,8 @@ static inline whal_Error whal_Stm32h5_Rcc_EnablePeriphClk( static inline whal_Error whal_Stm32h5_Rcc_DisablePeriphClk( const whal_Stm32h5_Rcc_PeriphClk *clk) { - whal_Reg_Update(WHAL_STM32H5_RCC_BASE, clk->regOffset, clk->enableMask, - whal_SetBits(clk->enableMask, clk->enablePos, 0)); + whal_Reg32_Update(WHAL_STM32H5_RCC_BASE, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 0)); return WHAL_SUCCESS; } diff --git a/wolfHAL/clock/stm32l1_rcc.h b/wolfHAL/clock/stm32l1_rcc.h index 13a06c28..e88964ad 100644 --- a/wolfHAL/clock/stm32l1_rcc.h +++ b/wolfHAL/clock/stm32l1_rcc.h @@ -148,12 +148,12 @@ typedef struct { static inline whal_Error whal_Stm32l1_Rcc_EnableOsc( const whal_Stm32l1_Rcc_OscCfg *cfg) { - size_t rdy; + uint32_t rdy; - whal_Reg_Update(WHAL_STM32L1_RCC_BASE, cfg->onReg, cfg->onMsk, cfg->onMsk); + whal_Reg32_Update(WHAL_STM32L1_RCC_BASE, cfg->onReg, cfg->onMsk, cfg->onMsk); do { - whal_Reg_Get(WHAL_STM32L1_RCC_BASE, cfg->rdyReg, cfg->rdyMsk, - cfg->rdyPos, &rdy); + whal_Reg32_Get(WHAL_STM32L1_RCC_BASE, cfg->rdyReg, cfg->rdyMsk, + cfg->rdyPos, &rdy); } while (!rdy); return WHAL_SUCCESS; } @@ -168,7 +168,7 @@ static inline whal_Error whal_Stm32l1_Rcc_EnableOsc( static inline whal_Error whal_Stm32l1_Rcc_DisableOsc( const whal_Stm32l1_Rcc_OscCfg *cfg) { - whal_Reg_Update(WHAL_STM32L1_RCC_BASE, cfg->onReg, cfg->onMsk, 0); + whal_Reg32_Update(WHAL_STM32L1_RCC_BASE, cfg->onReg, cfg->onMsk, 0); return WHAL_SUCCESS; } @@ -186,42 +186,42 @@ static inline whal_Error whal_Stm32l1_Rcc_DisableOsc( static inline whal_Error whal_Stm32l1_Rcc_EnablePll( const whal_Stm32l1_Rcc_PllCfg *cfg) { - size_t rdy; + uint32_t rdy; uint32_t pllsrc; /* Disable PLL before reconfiguring; wait until it's actually off. */ - whal_Reg_Update(WHAL_STM32L1_RCC_BASE, WHAL_STM32L1_RCC_CR_REG, - WHAL_STM32L1_RCC_CR_PLLON_Msk, 0); + whal_Reg32_Update(WHAL_STM32L1_RCC_BASE, WHAL_STM32L1_RCC_CR_REG, + WHAL_STM32L1_RCC_CR_PLLON_Msk, 0); do { - whal_Reg_Get(WHAL_STM32L1_RCC_BASE, WHAL_STM32L1_RCC_CR_REG, - WHAL_STM32L1_RCC_CR_PLLRDY_Msk, - WHAL_STM32L1_RCC_CR_PLLRDY_Pos, &rdy); + whal_Reg32_Get(WHAL_STM32L1_RCC_BASE, WHAL_STM32L1_RCC_CR_REG, + WHAL_STM32L1_RCC_CR_PLLRDY_Msk, + WHAL_STM32L1_RCC_CR_PLLRDY_Pos, &rdy); } while (rdy); pllsrc = (cfg->clkSrc == WHAL_STM32L1_RCC_PLLSRC_HSE) ? 1 : 0; - whal_Reg_Update(WHAL_STM32L1_RCC_BASE, WHAL_STM32L1_RCC_CFGR_REG, - WHAL_STM32L1_RCC_CFGR_PLLSRC_Msk, - whal_SetBits(WHAL_STM32L1_RCC_CFGR_PLLSRC_Msk, - WHAL_STM32L1_RCC_CFGR_PLLSRC_Pos, - pllsrc)); - whal_Reg_Update(WHAL_STM32L1_RCC_BASE, WHAL_STM32L1_RCC_CFGR_REG, - WHAL_STM32L1_RCC_CFGR_PLLMUL_Msk, - whal_SetBits(WHAL_STM32L1_RCC_CFGR_PLLMUL_Msk, - WHAL_STM32L1_RCC_CFGR_PLLMUL_Pos, - cfg->pllmul)); - whal_Reg_Update(WHAL_STM32L1_RCC_BASE, WHAL_STM32L1_RCC_CFGR_REG, - WHAL_STM32L1_RCC_CFGR_PLLDIV_Msk, - whal_SetBits(WHAL_STM32L1_RCC_CFGR_PLLDIV_Msk, - WHAL_STM32L1_RCC_CFGR_PLLDIV_Pos, - cfg->plldiv)); + whal_Reg32_Update(WHAL_STM32L1_RCC_BASE, WHAL_STM32L1_RCC_CFGR_REG, + WHAL_STM32L1_RCC_CFGR_PLLSRC_Msk, + whal_SetBits(WHAL_STM32L1_RCC_CFGR_PLLSRC_Msk, + WHAL_STM32L1_RCC_CFGR_PLLSRC_Pos, + pllsrc)); + whal_Reg32_Update(WHAL_STM32L1_RCC_BASE, WHAL_STM32L1_RCC_CFGR_REG, + WHAL_STM32L1_RCC_CFGR_PLLMUL_Msk, + whal_SetBits(WHAL_STM32L1_RCC_CFGR_PLLMUL_Msk, + WHAL_STM32L1_RCC_CFGR_PLLMUL_Pos, + cfg->pllmul)); + whal_Reg32_Update(WHAL_STM32L1_RCC_BASE, WHAL_STM32L1_RCC_CFGR_REG, + WHAL_STM32L1_RCC_CFGR_PLLDIV_Msk, + whal_SetBits(WHAL_STM32L1_RCC_CFGR_PLLDIV_Msk, + WHAL_STM32L1_RCC_CFGR_PLLDIV_Pos, + cfg->plldiv)); - whal_Reg_Update(WHAL_STM32L1_RCC_BASE, WHAL_STM32L1_RCC_CR_REG, - WHAL_STM32L1_RCC_CR_PLLON_Msk, - WHAL_STM32L1_RCC_CR_PLLON_Msk); + whal_Reg32_Update(WHAL_STM32L1_RCC_BASE, WHAL_STM32L1_RCC_CR_REG, + WHAL_STM32L1_RCC_CR_PLLON_Msk, + WHAL_STM32L1_RCC_CR_PLLON_Msk); do { - whal_Reg_Get(WHAL_STM32L1_RCC_BASE, WHAL_STM32L1_RCC_CR_REG, - WHAL_STM32L1_RCC_CR_PLLRDY_Msk, - WHAL_STM32L1_RCC_CR_PLLRDY_Pos, &rdy); + whal_Reg32_Get(WHAL_STM32L1_RCC_BASE, WHAL_STM32L1_RCC_CR_REG, + WHAL_STM32L1_RCC_CR_PLLRDY_Msk, + WHAL_STM32L1_RCC_CR_PLLRDY_Pos, &rdy); } while (!rdy); return WHAL_SUCCESS; } @@ -234,8 +234,8 @@ static inline whal_Error whal_Stm32l1_Rcc_EnablePll( */ static inline whal_Error whal_Stm32l1_Rcc_DisablePll(void) { - whal_Reg_Update(WHAL_STM32L1_RCC_BASE, WHAL_STM32L1_RCC_CR_REG, - WHAL_STM32L1_RCC_CR_PLLON_Msk, 0); + whal_Reg32_Update(WHAL_STM32L1_RCC_BASE, WHAL_STM32L1_RCC_CR_REG, + WHAL_STM32L1_RCC_CR_PLLON_Msk, 0); return WHAL_SUCCESS; } @@ -249,16 +249,16 @@ static inline whal_Error whal_Stm32l1_Rcc_DisablePll(void) static inline whal_Error whal_Stm32l1_Rcc_SetSysClock( whal_Stm32l1_Rcc_SysClockSrc src) { - size_t sws; + uint32_t sws; - whal_Reg_Update(WHAL_STM32L1_RCC_BASE, WHAL_STM32L1_RCC_CFGR_REG, - WHAL_STM32L1_RCC_CFGR_SW_Msk, - whal_SetBits(WHAL_STM32L1_RCC_CFGR_SW_Msk, - WHAL_STM32L1_RCC_CFGR_SW_Pos, src)); + whal_Reg32_Update(WHAL_STM32L1_RCC_BASE, WHAL_STM32L1_RCC_CFGR_REG, + WHAL_STM32L1_RCC_CFGR_SW_Msk, + whal_SetBits(WHAL_STM32L1_RCC_CFGR_SW_Msk, + WHAL_STM32L1_RCC_CFGR_SW_Pos, src)); do { - whal_Reg_Get(WHAL_STM32L1_RCC_BASE, WHAL_STM32L1_RCC_CFGR_REG, - WHAL_STM32L1_RCC_CFGR_SWS_Msk, - WHAL_STM32L1_RCC_CFGR_SWS_Pos, &sws); + whal_Reg32_Get(WHAL_STM32L1_RCC_BASE, WHAL_STM32L1_RCC_CFGR_REG, + WHAL_STM32L1_RCC_CFGR_SWS_Msk, + WHAL_STM32L1_RCC_CFGR_SWS_Pos, &sws); } while (sws != (size_t)src); return WHAL_SUCCESS; } @@ -273,8 +273,8 @@ static inline whal_Error whal_Stm32l1_Rcc_SetSysClock( static inline whal_Error whal_Stm32l1_Rcc_EnablePeriphClk( const whal_Stm32l1_Rcc_PeriphClk *clk) { - whal_Reg_Update(WHAL_STM32L1_RCC_BASE, clk->regOffset, clk->enableMask, - whal_SetBits(clk->enableMask, clk->enablePos, 1)); + whal_Reg32_Update(WHAL_STM32L1_RCC_BASE, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 1)); return WHAL_SUCCESS; } @@ -288,8 +288,8 @@ static inline whal_Error whal_Stm32l1_Rcc_EnablePeriphClk( static inline whal_Error whal_Stm32l1_Rcc_DisablePeriphClk( const whal_Stm32l1_Rcc_PeriphClk *clk) { - whal_Reg_Update(WHAL_STM32L1_RCC_BASE, clk->regOffset, clk->enableMask, - whal_SetBits(clk->enableMask, clk->enablePos, 0)); + whal_Reg32_Update(WHAL_STM32L1_RCC_BASE, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 0)); return WHAL_SUCCESS; } diff --git a/wolfHAL/clock/stm32n6_rcc.h b/wolfHAL/clock/stm32n6_rcc.h index a8ac4436..74d539c4 100644 --- a/wolfHAL/clock/stm32n6_rcc.h +++ b/wolfHAL/clock/stm32n6_rcc.h @@ -176,12 +176,12 @@ typedef struct { static inline whal_Error whal_Stm32n6_Rcc_EnableOsc( const whal_Stm32n6_Rcc_OscCfg *cfg) { - size_t rdy; + uint32_t rdy; - whal_Reg_Update(WHAL_STM32N6_RCC_BASE, cfg->onReg, cfg->onMsk, cfg->onMsk); + whal_Reg32_Update(WHAL_STM32N6_RCC_BASE, cfg->onReg, cfg->onMsk, cfg->onMsk); do { - whal_Reg_Get(WHAL_STM32N6_RCC_BASE, cfg->rdyReg, cfg->rdyMsk, - cfg->rdyPos, &rdy); + whal_Reg32_Get(WHAL_STM32N6_RCC_BASE, cfg->rdyReg, cfg->rdyMsk, + cfg->rdyPos, &rdy); } while (!rdy); return WHAL_SUCCESS; } @@ -196,7 +196,7 @@ static inline whal_Error whal_Stm32n6_Rcc_EnableOsc( static inline whal_Error whal_Stm32n6_Rcc_DisableOsc( const whal_Stm32n6_Rcc_OscCfg *cfg) { - whal_Reg_Update(WHAL_STM32N6_RCC_BASE, cfg->onReg, cfg->onMsk, 0); + whal_Reg32_Update(WHAL_STM32N6_RCC_BASE, cfg->onReg, cfg->onMsk, 0); return WHAL_SUCCESS; } @@ -213,41 +213,41 @@ static inline whal_Error whal_Stm32n6_Rcc_DisableOsc( static inline whal_Error whal_Stm32n6_Rcc_EnablePll1( const whal_Stm32n6_Rcc_Pll1Cfg *cfg) { - size_t rdy; + uint32_t rdy; /* Disable PLL1 before reconfiguring; wait until off. */ - whal_Reg_Update(WHAL_STM32N6_RCC_BASE, WHAL_STM32N6_RCC_CR_REG, - WHAL_STM32N6_RCC_CR_PLL1ON_Msk, 0); + whal_Reg32_Update(WHAL_STM32N6_RCC_BASE, WHAL_STM32N6_RCC_CR_REG, + WHAL_STM32N6_RCC_CR_PLL1ON_Msk, 0); do { - whal_Reg_Get(WHAL_STM32N6_RCC_BASE, WHAL_STM32N6_RCC_SR_REG, - WHAL_STM32N6_RCC_SR_PLL1RDY_Msk, - WHAL_STM32N6_RCC_SR_PLL1RDY_Pos, &rdy); + whal_Reg32_Get(WHAL_STM32N6_RCC_BASE, WHAL_STM32N6_RCC_SR_REG, + WHAL_STM32N6_RCC_SR_PLL1RDY_Msk, + WHAL_STM32N6_RCC_SR_PLL1RDY_Pos, &rdy); } while (rdy); - whal_Reg_Write(WHAL_STM32N6_RCC_BASE, WHAL_STM32N6_RCC_PLL1CFGR1_REG, - whal_SetBits(WHAL_STM32N6_RCC_PLL1CFGR1_PLL1SEL_Msk, - WHAL_STM32N6_RCC_PLL1CFGR1_PLL1SEL_Pos, cfg->clkSrc) | - whal_SetBits(WHAL_STM32N6_RCC_PLL1CFGR1_PLL1DIVM_Msk, - WHAL_STM32N6_RCC_PLL1CFGR1_PLL1DIVM_Pos, cfg->m) | - whal_SetBits(WHAL_STM32N6_RCC_PLL1CFGR1_PLL1DIVN_Msk, - WHAL_STM32N6_RCC_PLL1CFGR1_PLL1DIVN_Pos, cfg->n)); - whal_Reg_Update(WHAL_STM32N6_RCC_BASE, WHAL_STM32N6_RCC_PLL1CFGR3_REG, - WHAL_STM32N6_RCC_PLL1CFGR3_PLL1PDIVEN_Msk | - WHAL_STM32N6_RCC_PLL1CFGR3_PLL1PDIV1_Msk | - WHAL_STM32N6_RCC_PLL1CFGR3_PLL1PDIV2_Msk, - WHAL_STM32N6_RCC_PLL1CFGR3_PLL1PDIVEN_Msk | - whal_SetBits(WHAL_STM32N6_RCC_PLL1CFGR3_PLL1PDIV1_Msk, - WHAL_STM32N6_RCC_PLL1CFGR3_PLL1PDIV1_Pos, cfg->pdiv1) | - whal_SetBits(WHAL_STM32N6_RCC_PLL1CFGR3_PLL1PDIV2_Msk, - WHAL_STM32N6_RCC_PLL1CFGR3_PLL1PDIV2_Pos, cfg->pdiv2)); - - whal_Reg_Update(WHAL_STM32N6_RCC_BASE, WHAL_STM32N6_RCC_CR_REG, - WHAL_STM32N6_RCC_CR_PLL1ON_Msk, - WHAL_STM32N6_RCC_CR_PLL1ON_Msk); + whal_Reg32_Write(WHAL_STM32N6_RCC_BASE, WHAL_STM32N6_RCC_PLL1CFGR1_REG, + whal_SetBits(WHAL_STM32N6_RCC_PLL1CFGR1_PLL1SEL_Msk, + WHAL_STM32N6_RCC_PLL1CFGR1_PLL1SEL_Pos, cfg->clkSrc) | + whal_SetBits(WHAL_STM32N6_RCC_PLL1CFGR1_PLL1DIVM_Msk, + WHAL_STM32N6_RCC_PLL1CFGR1_PLL1DIVM_Pos, cfg->m) | + whal_SetBits(WHAL_STM32N6_RCC_PLL1CFGR1_PLL1DIVN_Msk, + WHAL_STM32N6_RCC_PLL1CFGR1_PLL1DIVN_Pos, cfg->n)); + whal_Reg32_Update(WHAL_STM32N6_RCC_BASE, WHAL_STM32N6_RCC_PLL1CFGR3_REG, + WHAL_STM32N6_RCC_PLL1CFGR3_PLL1PDIVEN_Msk | + WHAL_STM32N6_RCC_PLL1CFGR3_PLL1PDIV1_Msk | + WHAL_STM32N6_RCC_PLL1CFGR3_PLL1PDIV2_Msk, + WHAL_STM32N6_RCC_PLL1CFGR3_PLL1PDIVEN_Msk | + whal_SetBits(WHAL_STM32N6_RCC_PLL1CFGR3_PLL1PDIV1_Msk, + WHAL_STM32N6_RCC_PLL1CFGR3_PLL1PDIV1_Pos, cfg->pdiv1) | + whal_SetBits(WHAL_STM32N6_RCC_PLL1CFGR3_PLL1PDIV2_Msk, + WHAL_STM32N6_RCC_PLL1CFGR3_PLL1PDIV2_Pos, cfg->pdiv2)); + + whal_Reg32_Update(WHAL_STM32N6_RCC_BASE, WHAL_STM32N6_RCC_CR_REG, + WHAL_STM32N6_RCC_CR_PLL1ON_Msk, + WHAL_STM32N6_RCC_CR_PLL1ON_Msk); do { - whal_Reg_Get(WHAL_STM32N6_RCC_BASE, WHAL_STM32N6_RCC_SR_REG, - WHAL_STM32N6_RCC_SR_PLL1RDY_Msk, - WHAL_STM32N6_RCC_SR_PLL1RDY_Pos, &rdy); + whal_Reg32_Get(WHAL_STM32N6_RCC_BASE, WHAL_STM32N6_RCC_SR_REG, + WHAL_STM32N6_RCC_SR_PLL1RDY_Msk, + WHAL_STM32N6_RCC_SR_PLL1RDY_Pos, &rdy); } while (!rdy); return WHAL_SUCCESS; } @@ -260,8 +260,8 @@ static inline whal_Error whal_Stm32n6_Rcc_EnablePll1( */ static inline whal_Error whal_Stm32n6_Rcc_DisablePll1(void) { - whal_Reg_Update(WHAL_STM32N6_RCC_BASE, WHAL_STM32N6_RCC_CR_REG, - WHAL_STM32N6_RCC_CR_PLL1ON_Msk, 0); + whal_Reg32_Update(WHAL_STM32N6_RCC_BASE, WHAL_STM32N6_RCC_CR_REG, + WHAL_STM32N6_RCC_CR_PLL1ON_Msk, 0); return WHAL_SUCCESS; } @@ -277,16 +277,16 @@ static inline whal_Error whal_Stm32n6_Rcc_DisablePll1(void) static inline whal_Error whal_Stm32n6_Rcc_SetSysClock( whal_Stm32n6_Rcc_SysClockSrc src) { - size_t sws; + uint32_t sws; - whal_Reg_Update(WHAL_STM32N6_RCC_BASE, WHAL_STM32N6_RCC_CFGR1_REG, - WHAL_STM32N6_RCC_CFGR1_SYSSW_Msk, - whal_SetBits(WHAL_STM32N6_RCC_CFGR1_SYSSW_Msk, - WHAL_STM32N6_RCC_CFGR1_SYSSW_Pos, src)); + whal_Reg32_Update(WHAL_STM32N6_RCC_BASE, WHAL_STM32N6_RCC_CFGR1_REG, + WHAL_STM32N6_RCC_CFGR1_SYSSW_Msk, + whal_SetBits(WHAL_STM32N6_RCC_CFGR1_SYSSW_Msk, + WHAL_STM32N6_RCC_CFGR1_SYSSW_Pos, src)); do { - whal_Reg_Get(WHAL_STM32N6_RCC_BASE, WHAL_STM32N6_RCC_CFGR1_REG, - WHAL_STM32N6_RCC_CFGR1_SYSSWS_Msk, - WHAL_STM32N6_RCC_CFGR1_SYSSWS_Pos, &sws); + whal_Reg32_Get(WHAL_STM32N6_RCC_BASE, WHAL_STM32N6_RCC_CFGR1_REG, + WHAL_STM32N6_RCC_CFGR1_SYSSWS_Msk, + WHAL_STM32N6_RCC_CFGR1_SYSSWS_Pos, &sws); } while (sws != (size_t)src); return WHAL_SUCCESS; } @@ -303,16 +303,16 @@ static inline whal_Error whal_Stm32n6_Rcc_SetSysClock( static inline whal_Error whal_Stm32n6_Rcc_SetCpuClock( whal_Stm32n6_Rcc_CpuClockSrc src) { - size_t sws; + uint32_t sws; - whal_Reg_Update(WHAL_STM32N6_RCC_BASE, WHAL_STM32N6_RCC_CFGR1_REG, - WHAL_STM32N6_RCC_CFGR1_CPUSW_Msk, - whal_SetBits(WHAL_STM32N6_RCC_CFGR1_CPUSW_Msk, - WHAL_STM32N6_RCC_CFGR1_CPUSW_Pos, src)); + whal_Reg32_Update(WHAL_STM32N6_RCC_BASE, WHAL_STM32N6_RCC_CFGR1_REG, + WHAL_STM32N6_RCC_CFGR1_CPUSW_Msk, + whal_SetBits(WHAL_STM32N6_RCC_CFGR1_CPUSW_Msk, + WHAL_STM32N6_RCC_CFGR1_CPUSW_Pos, src)); do { - whal_Reg_Get(WHAL_STM32N6_RCC_BASE, WHAL_STM32N6_RCC_CFGR1_REG, - WHAL_STM32N6_RCC_CFGR1_CPUSWS_Msk, - WHAL_STM32N6_RCC_CFGR1_CPUSWS_Pos, &sws); + whal_Reg32_Get(WHAL_STM32N6_RCC_BASE, WHAL_STM32N6_RCC_CFGR1_REG, + WHAL_STM32N6_RCC_CFGR1_CPUSWS_Msk, + WHAL_STM32N6_RCC_CFGR1_CPUSWS_Pos, &sws); } while (sws != (size_t)src); return WHAL_SUCCESS; } @@ -327,11 +327,11 @@ static inline whal_Error whal_Stm32n6_Rcc_SetCpuClock( static inline whal_Error whal_Stm32n6_Rcc_SetEth1If( whal_Stm32n6_Rcc_Eth1If mode) { - whal_Reg_Update(WHAL_STM32N6_RCC_BASE, WHAL_STM32N6_RCC_CCIPR2_REG, - WHAL_STM32N6_RCC_CCIPR2_ETH1SEL_Msk, - whal_SetBits(WHAL_STM32N6_RCC_CCIPR2_ETH1SEL_Msk, - WHAL_STM32N6_RCC_CCIPR2_ETH1SEL_Pos, - mode)); + whal_Reg32_Update(WHAL_STM32N6_RCC_BASE, WHAL_STM32N6_RCC_CCIPR2_REG, + WHAL_STM32N6_RCC_CCIPR2_ETH1SEL_Msk, + whal_SetBits(WHAL_STM32N6_RCC_CCIPR2_ETH1SEL_Msk, + WHAL_STM32N6_RCC_CCIPR2_ETH1SEL_Pos, + mode)); return WHAL_SUCCESS; } @@ -345,8 +345,8 @@ static inline whal_Error whal_Stm32n6_Rcc_SetEth1If( static inline whal_Error whal_Stm32n6_Rcc_EnablePeriphClk( const whal_Stm32n6_Rcc_PeriphClk *clk) { - whal_Reg_Update(WHAL_STM32N6_RCC_BASE, clk->regOffset, clk->enableMask, - whal_SetBits(clk->enableMask, clk->enablePos, 1)); + whal_Reg32_Update(WHAL_STM32N6_RCC_BASE, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 1)); return WHAL_SUCCESS; } @@ -360,8 +360,8 @@ static inline whal_Error whal_Stm32n6_Rcc_EnablePeriphClk( static inline whal_Error whal_Stm32n6_Rcc_DisablePeriphClk( const whal_Stm32n6_Rcc_PeriphClk *clk) { - whal_Reg_Update(WHAL_STM32N6_RCC_BASE, clk->regOffset, clk->enableMask, - whal_SetBits(clk->enableMask, clk->enablePos, 0)); + whal_Reg32_Update(WHAL_STM32N6_RCC_BASE, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 0)); return WHAL_SUCCESS; } diff --git a/wolfHAL/clock/stm32u5_rcc.h b/wolfHAL/clock/stm32u5_rcc.h index 91af5024..cd4109d5 100644 --- a/wolfHAL/clock/stm32u5_rcc.h +++ b/wolfHAL/clock/stm32u5_rcc.h @@ -227,12 +227,12 @@ typedef struct { static inline whal_Error whal_Stm32u5_Rcc_EnableOsc( const whal_Stm32u5_Rcc_OscCfg *cfg) { - size_t rdy; + uint32_t rdy; - whal_Reg_Update(WHAL_STM32U5_RCC_BASE, cfg->onReg, cfg->onMsk, cfg->onMsk); + whal_Reg32_Update(WHAL_STM32U5_RCC_BASE, cfg->onReg, cfg->onMsk, cfg->onMsk); do { - whal_Reg_Get(WHAL_STM32U5_RCC_BASE, cfg->rdyReg, cfg->rdyMsk, - cfg->rdyPos, &rdy); + whal_Reg32_Get(WHAL_STM32U5_RCC_BASE, cfg->rdyReg, cfg->rdyMsk, + cfg->rdyPos, &rdy); } while (!rdy); return WHAL_SUCCESS; } @@ -243,7 +243,7 @@ static inline whal_Error whal_Stm32u5_Rcc_EnableOsc( static inline whal_Error whal_Stm32u5_Rcc_DisableOsc( const whal_Stm32u5_Rcc_OscCfg *cfg) { - whal_Reg_Update(WHAL_STM32U5_RCC_BASE, cfg->onReg, cfg->onMsk, 0); + whal_Reg32_Update(WHAL_STM32U5_RCC_BASE, cfg->onReg, cfg->onMsk, 0); return WHAL_SUCCESS; } @@ -253,46 +253,46 @@ static inline whal_Error whal_Stm32u5_Rcc_DisableOsc( static inline whal_Error whal_Stm32u5_Rcc_EnablePll1( const whal_Stm32u5_Rcc_Pll1Cfg *cfg) { - size_t rdy; + uint32_t rdy; /* Disable PLL1 before reconfiguring; wait until off. */ - whal_Reg_Update(WHAL_STM32U5_RCC_BASE, WHAL_STM32U5_RCC_CR_REG, - WHAL_STM32U5_RCC_CR_PLL1ON_Msk, 0); + whal_Reg32_Update(WHAL_STM32U5_RCC_BASE, WHAL_STM32U5_RCC_CR_REG, + WHAL_STM32U5_RCC_CR_PLL1ON_Msk, 0); do { - whal_Reg_Get(WHAL_STM32U5_RCC_BASE, WHAL_STM32U5_RCC_CR_REG, - WHAL_STM32U5_RCC_CR_PLL1RDY_Msk, - WHAL_STM32U5_RCC_CR_PLL1RDY_Pos, &rdy); + whal_Reg32_Get(WHAL_STM32U5_RCC_BASE, WHAL_STM32U5_RCC_CR_REG, + WHAL_STM32U5_RCC_CR_PLL1RDY_Msk, + WHAL_STM32U5_RCC_CR_PLL1RDY_Pos, &rdy); } while (rdy); - whal_Reg_Write(WHAL_STM32U5_RCC_BASE, WHAL_STM32U5_RCC_PLL1CFGR_REG, - whal_SetBits(WHAL_STM32U5_RCC_PLL1CFGR_SRC_Msk, - WHAL_STM32U5_RCC_PLL1CFGR_SRC_Pos, cfg->clkSrc) | - whal_SetBits(WHAL_STM32U5_RCC_PLL1CFGR_RGE_Msk, - WHAL_STM32U5_RCC_PLL1CFGR_RGE_Pos, cfg->rge) | - whal_SetBits(WHAL_STM32U5_RCC_PLL1CFGR_M_Msk, - WHAL_STM32U5_RCC_PLL1CFGR_M_Pos, cfg->m - 1) | - whal_SetBits(WHAL_STM32U5_RCC_PLL1CFGR_MBOOST_Msk, - WHAL_STM32U5_RCC_PLL1CFGR_MBOOST_Pos, - cfg->mboost) | - whal_SetBits(WHAL_STM32U5_RCC_PLL1CFGR_REN_Msk, - WHAL_STM32U5_RCC_PLL1CFGR_REN_Pos, 1)); - whal_Reg_Write(WHAL_STM32U5_RCC_BASE, WHAL_STM32U5_RCC_PLL1DIVR_REG, - whal_SetBits(WHAL_STM32U5_RCC_PLL1DIVR_N_Msk, - WHAL_STM32U5_RCC_PLL1DIVR_N_Pos, cfg->n - 1) | - whal_SetBits(WHAL_STM32U5_RCC_PLL1DIVR_P_Msk, - WHAL_STM32U5_RCC_PLL1DIVR_P_Pos, cfg->p - 1) | - whal_SetBits(WHAL_STM32U5_RCC_PLL1DIVR_Q_Msk, - WHAL_STM32U5_RCC_PLL1DIVR_Q_Pos, cfg->q - 1) | - whal_SetBits(WHAL_STM32U5_RCC_PLL1DIVR_R_Msk, - WHAL_STM32U5_RCC_PLL1DIVR_R_Pos, cfg->r - 1)); - - whal_Reg_Update(WHAL_STM32U5_RCC_BASE, WHAL_STM32U5_RCC_CR_REG, - WHAL_STM32U5_RCC_CR_PLL1ON_Msk, - WHAL_STM32U5_RCC_CR_PLL1ON_Msk); + whal_Reg32_Write(WHAL_STM32U5_RCC_BASE, WHAL_STM32U5_RCC_PLL1CFGR_REG, + whal_SetBits(WHAL_STM32U5_RCC_PLL1CFGR_SRC_Msk, + WHAL_STM32U5_RCC_PLL1CFGR_SRC_Pos, cfg->clkSrc) | + whal_SetBits(WHAL_STM32U5_RCC_PLL1CFGR_RGE_Msk, + WHAL_STM32U5_RCC_PLL1CFGR_RGE_Pos, cfg->rge) | + whal_SetBits(WHAL_STM32U5_RCC_PLL1CFGR_M_Msk, + WHAL_STM32U5_RCC_PLL1CFGR_M_Pos, cfg->m - 1) | + whal_SetBits(WHAL_STM32U5_RCC_PLL1CFGR_MBOOST_Msk, + WHAL_STM32U5_RCC_PLL1CFGR_MBOOST_Pos, + cfg->mboost) | + whal_SetBits(WHAL_STM32U5_RCC_PLL1CFGR_REN_Msk, + WHAL_STM32U5_RCC_PLL1CFGR_REN_Pos, 1)); + whal_Reg32_Write(WHAL_STM32U5_RCC_BASE, WHAL_STM32U5_RCC_PLL1DIVR_REG, + whal_SetBits(WHAL_STM32U5_RCC_PLL1DIVR_N_Msk, + WHAL_STM32U5_RCC_PLL1DIVR_N_Pos, cfg->n - 1) | + whal_SetBits(WHAL_STM32U5_RCC_PLL1DIVR_P_Msk, + WHAL_STM32U5_RCC_PLL1DIVR_P_Pos, cfg->p - 1) | + whal_SetBits(WHAL_STM32U5_RCC_PLL1DIVR_Q_Msk, + WHAL_STM32U5_RCC_PLL1DIVR_Q_Pos, cfg->q - 1) | + whal_SetBits(WHAL_STM32U5_RCC_PLL1DIVR_R_Msk, + WHAL_STM32U5_RCC_PLL1DIVR_R_Pos, cfg->r - 1)); + + whal_Reg32_Update(WHAL_STM32U5_RCC_BASE, WHAL_STM32U5_RCC_CR_REG, + WHAL_STM32U5_RCC_CR_PLL1ON_Msk, + WHAL_STM32U5_RCC_CR_PLL1ON_Msk); do { - whal_Reg_Get(WHAL_STM32U5_RCC_BASE, WHAL_STM32U5_RCC_CR_REG, - WHAL_STM32U5_RCC_CR_PLL1RDY_Msk, - WHAL_STM32U5_RCC_CR_PLL1RDY_Pos, &rdy); + whal_Reg32_Get(WHAL_STM32U5_RCC_BASE, WHAL_STM32U5_RCC_CR_REG, + WHAL_STM32U5_RCC_CR_PLL1RDY_Msk, + WHAL_STM32U5_RCC_CR_PLL1RDY_Pos, &rdy); } while (!rdy); return WHAL_SUCCESS; } @@ -302,8 +302,8 @@ static inline whal_Error whal_Stm32u5_Rcc_EnablePll1( */ static inline whal_Error whal_Stm32u5_Rcc_DisablePll1(void) { - whal_Reg_Update(WHAL_STM32U5_RCC_BASE, WHAL_STM32U5_RCC_CR_REG, - WHAL_STM32U5_RCC_CR_PLL1ON_Msk, 0); + whal_Reg32_Update(WHAL_STM32U5_RCC_BASE, WHAL_STM32U5_RCC_CR_REG, + WHAL_STM32U5_RCC_CR_PLL1ON_Msk, 0); return WHAL_SUCCESS; } @@ -312,15 +312,15 @@ static inline whal_Error whal_Stm32u5_Rcc_DisablePll1(void) */ static inline whal_Error whal_Stm32u5_Rcc_EnableLsi(void) { - size_t rdy; + uint32_t rdy; - whal_Reg_Update(WHAL_STM32U5_RCC_BASE, WHAL_STM32U5_RCC_BDCR_REG, - WHAL_STM32U5_RCC_BDCR_LSION_Msk, - WHAL_STM32U5_RCC_BDCR_LSION_Msk); + whal_Reg32_Update(WHAL_STM32U5_RCC_BASE, WHAL_STM32U5_RCC_BDCR_REG, + WHAL_STM32U5_RCC_BDCR_LSION_Msk, + WHAL_STM32U5_RCC_BDCR_LSION_Msk); do { - whal_Reg_Get(WHAL_STM32U5_RCC_BASE, WHAL_STM32U5_RCC_BDCR_REG, - WHAL_STM32U5_RCC_BDCR_LSIRDY_Msk, - WHAL_STM32U5_RCC_BDCR_LSIRDY_Pos, &rdy); + whal_Reg32_Get(WHAL_STM32U5_RCC_BASE, WHAL_STM32U5_RCC_BDCR_REG, + WHAL_STM32U5_RCC_BDCR_LSIRDY_Msk, + WHAL_STM32U5_RCC_BDCR_LSIRDY_Pos, &rdy); } while (!rdy); return WHAL_SUCCESS; } @@ -330,8 +330,8 @@ static inline whal_Error whal_Stm32u5_Rcc_EnableLsi(void) */ static inline whal_Error whal_Stm32u5_Rcc_DisableLsi(void) { - whal_Reg_Update(WHAL_STM32U5_RCC_BASE, WHAL_STM32U5_RCC_BDCR_REG, - WHAL_STM32U5_RCC_BDCR_LSION_Msk, 0); + whal_Reg32_Update(WHAL_STM32U5_RCC_BASE, WHAL_STM32U5_RCC_BDCR_REG, + WHAL_STM32U5_RCC_BDCR_LSION_Msk, 0); return WHAL_SUCCESS; } @@ -341,16 +341,16 @@ static inline whal_Error whal_Stm32u5_Rcc_DisableLsi(void) static inline whal_Error whal_Stm32u5_Rcc_SetSysClock( whal_Stm32u5_Rcc_SysClockSrc src) { - size_t sws; + uint32_t sws; - whal_Reg_Update(WHAL_STM32U5_RCC_BASE, WHAL_STM32U5_RCC_CFGR1_REG, - WHAL_STM32U5_RCC_CFGR1_SW_Msk, - whal_SetBits(WHAL_STM32U5_RCC_CFGR1_SW_Msk, - WHAL_STM32U5_RCC_CFGR1_SW_Pos, src)); + whal_Reg32_Update(WHAL_STM32U5_RCC_BASE, WHAL_STM32U5_RCC_CFGR1_REG, + WHAL_STM32U5_RCC_CFGR1_SW_Msk, + whal_SetBits(WHAL_STM32U5_RCC_CFGR1_SW_Msk, + WHAL_STM32U5_RCC_CFGR1_SW_Pos, src)); do { - whal_Reg_Get(WHAL_STM32U5_RCC_BASE, WHAL_STM32U5_RCC_CFGR1_REG, - WHAL_STM32U5_RCC_CFGR1_SWS_Msk, - WHAL_STM32U5_RCC_CFGR1_SWS_Pos, &sws); + whal_Reg32_Get(WHAL_STM32U5_RCC_BASE, WHAL_STM32U5_RCC_CFGR1_REG, + WHAL_STM32U5_RCC_CFGR1_SWS_Msk, + WHAL_STM32U5_RCC_CFGR1_SWS_Pos, &sws); } while (sws != (size_t)src); return WHAL_SUCCESS; } @@ -361,11 +361,11 @@ static inline whal_Error whal_Stm32u5_Rcc_SetSysClock( static inline whal_Error whal_Stm32u5_Rcc_SetRngClockSrc( whal_Stm32u5_Rcc_RngSrc src) { - whal_Reg_Update(WHAL_STM32U5_RCC_BASE, WHAL_STM32U5_RCC_CCIPR2_REG, - WHAL_STM32U5_RCC_CCIPR2_RNGSEL_Msk, - whal_SetBits(WHAL_STM32U5_RCC_CCIPR2_RNGSEL_Msk, - WHAL_STM32U5_RCC_CCIPR2_RNGSEL_Pos, - src)); + whal_Reg32_Update(WHAL_STM32U5_RCC_BASE, WHAL_STM32U5_RCC_CCIPR2_REG, + WHAL_STM32U5_RCC_CCIPR2_RNGSEL_Msk, + whal_SetBits(WHAL_STM32U5_RCC_CCIPR2_RNGSEL_Msk, + WHAL_STM32U5_RCC_CCIPR2_RNGSEL_Pos, + src)); return WHAL_SUCCESS; } @@ -375,8 +375,8 @@ static inline whal_Error whal_Stm32u5_Rcc_SetRngClockSrc( static inline whal_Error whal_Stm32u5_Rcc_EnablePeriphClk( const whal_Stm32u5_Rcc_PeriphClk *clk) { - whal_Reg_Update(WHAL_STM32U5_RCC_BASE, clk->regOffset, clk->enableMask, - whal_SetBits(clk->enableMask, clk->enablePos, 1)); + whal_Reg32_Update(WHAL_STM32U5_RCC_BASE, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 1)); return WHAL_SUCCESS; } @@ -386,8 +386,8 @@ static inline whal_Error whal_Stm32u5_Rcc_EnablePeriphClk( static inline whal_Error whal_Stm32u5_Rcc_DisablePeriphClk( const whal_Stm32u5_Rcc_PeriphClk *clk) { - whal_Reg_Update(WHAL_STM32U5_RCC_BASE, clk->regOffset, clk->enableMask, - whal_SetBits(clk->enableMask, clk->enablePos, 0)); + whal_Reg32_Update(WHAL_STM32U5_RCC_BASE, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 0)); return WHAL_SUCCESS; } @@ -399,16 +399,16 @@ static inline whal_Error whal_Stm32u5_Rcc_DisablePeriphClk( static inline whal_Error whal_Stm32u5_Pwr_SetVosRange( whal_Stm32u5_Pwr_VosRange range) { - size_t rdy; + uint32_t rdy; - whal_Reg_Update(WHAL_STM32U5_PWR_BASE, WHAL_STM32U5_PWR_VOSR_REG, - WHAL_STM32U5_PWR_VOSR_VOS_Msk, - whal_SetBits(WHAL_STM32U5_PWR_VOSR_VOS_Msk, - WHAL_STM32U5_PWR_VOSR_VOS_Pos, range)); + whal_Reg32_Update(WHAL_STM32U5_PWR_BASE, WHAL_STM32U5_PWR_VOSR_REG, + WHAL_STM32U5_PWR_VOSR_VOS_Msk, + whal_SetBits(WHAL_STM32U5_PWR_VOSR_VOS_Msk, + WHAL_STM32U5_PWR_VOSR_VOS_Pos, range)); do { - whal_Reg_Get(WHAL_STM32U5_PWR_BASE, WHAL_STM32U5_PWR_VOSR_REG, - WHAL_STM32U5_PWR_VOSR_VOSRDY_Msk, - WHAL_STM32U5_PWR_VOSR_VOSRDY_Pos, &rdy); + whal_Reg32_Get(WHAL_STM32U5_PWR_BASE, WHAL_STM32U5_PWR_VOSR_REG, + WHAL_STM32U5_PWR_VOSR_VOSRDY_Msk, + WHAL_STM32U5_PWR_VOSR_VOSRDY_Pos, &rdy); } while (!rdy); return WHAL_SUCCESS; } @@ -419,16 +419,16 @@ static inline whal_Error whal_Stm32u5_Pwr_SetVosRange( */ static inline whal_Error whal_Stm32u5_Pwr_EnableEpodBooster(void) { - size_t rdy; + uint32_t rdy; - whal_Reg_Update(WHAL_STM32U5_PWR_BASE, WHAL_STM32U5_PWR_VOSR_REG, - WHAL_STM32U5_PWR_VOSR_BOOSTEN_Msk, - whal_SetBits(WHAL_STM32U5_PWR_VOSR_BOOSTEN_Msk, - WHAL_STM32U5_PWR_VOSR_BOOSTEN_Pos, 1)); + whal_Reg32_Update(WHAL_STM32U5_PWR_BASE, WHAL_STM32U5_PWR_VOSR_REG, + WHAL_STM32U5_PWR_VOSR_BOOSTEN_Msk, + whal_SetBits(WHAL_STM32U5_PWR_VOSR_BOOSTEN_Msk, + WHAL_STM32U5_PWR_VOSR_BOOSTEN_Pos, 1)); do { - whal_Reg_Get(WHAL_STM32U5_PWR_BASE, WHAL_STM32U5_PWR_VOSR_REG, - WHAL_STM32U5_PWR_VOSR_BOOSTRDY_Msk, - WHAL_STM32U5_PWR_VOSR_BOOSTRDY_Pos, &rdy); + whal_Reg32_Get(WHAL_STM32U5_PWR_BASE, WHAL_STM32U5_PWR_VOSR_REG, + WHAL_STM32U5_PWR_VOSR_BOOSTRDY_Msk, + WHAL_STM32U5_PWR_VOSR_BOOSTRDY_Pos, &rdy); } while (!rdy); return WHAL_SUCCESS; } diff --git a/wolfHAL/clock/stm32wb0_rcc.h b/wolfHAL/clock/stm32wb0_rcc.h index 8b811531..0655fcae 100644 --- a/wolfHAL/clock/stm32wb0_rcc.h +++ b/wolfHAL/clock/stm32wb0_rcc.h @@ -137,12 +137,12 @@ typedef struct { */ static inline whal_Error whal_Stm32wb0_Rcc_EnableHsi(void) { - size_t rdy; + uint32_t rdy; do { - whal_Reg_Get(WHAL_STM32WB0_RCC_BASE, WHAL_STM32WB0_RCC_CR_REG, - WHAL_STM32WB0_RCC_CR_HSIRDY_Msk, - WHAL_STM32WB0_RCC_CR_HSIRDY_Pos, &rdy); + whal_Reg32_Get(WHAL_STM32WB0_RCC_BASE, WHAL_STM32WB0_RCC_CR_REG, + WHAL_STM32WB0_RCC_CR_HSIRDY_Msk, + WHAL_STM32WB0_RCC_CR_HSIRDY_Pos, &rdy); } while (!rdy); return WHAL_SUCCESS; } @@ -154,15 +154,15 @@ static inline whal_Error whal_Stm32wb0_Rcc_EnableHsi(void) */ static inline whal_Error whal_Stm32wb0_Rcc_EnableLsi(void) { - size_t rdy; + uint32_t rdy; - whal_Reg_Update(WHAL_STM32WB0_RCC_BASE, WHAL_STM32WB0_RCC_CR_REG, - WHAL_STM32WB0_RCC_CR_LSION_Msk, - WHAL_STM32WB0_RCC_CR_LSION_Msk); + whal_Reg32_Update(WHAL_STM32WB0_RCC_BASE, WHAL_STM32WB0_RCC_CR_REG, + WHAL_STM32WB0_RCC_CR_LSION_Msk, + WHAL_STM32WB0_RCC_CR_LSION_Msk); do { - whal_Reg_Get(WHAL_STM32WB0_RCC_BASE, WHAL_STM32WB0_RCC_CR_REG, - WHAL_STM32WB0_RCC_CR_LSIRDY_Msk, - WHAL_STM32WB0_RCC_CR_LSIRDY_Pos, &rdy); + whal_Reg32_Get(WHAL_STM32WB0_RCC_BASE, WHAL_STM32WB0_RCC_CR_REG, + WHAL_STM32WB0_RCC_CR_LSIRDY_Msk, + WHAL_STM32WB0_RCC_CR_LSIRDY_Pos, &rdy); } while (!rdy); return WHAL_SUCCESS; } @@ -174,8 +174,8 @@ static inline whal_Error whal_Stm32wb0_Rcc_EnableLsi(void) */ static inline whal_Error whal_Stm32wb0_Rcc_DisableLsi(void) { - whal_Reg_Update(WHAL_STM32WB0_RCC_BASE, WHAL_STM32WB0_RCC_CR_REG, - WHAL_STM32WB0_RCC_CR_LSION_Msk, 0); + whal_Reg32_Update(WHAL_STM32WB0_RCC_BASE, WHAL_STM32WB0_RCC_CR_REG, + WHAL_STM32WB0_RCC_CR_LSION_Msk, 0); return WHAL_SUCCESS; } @@ -187,15 +187,15 @@ static inline whal_Error whal_Stm32wb0_Rcc_DisableLsi(void) */ static inline whal_Error whal_Stm32wb0_Rcc_EnableHse(void) { - size_t rdy; + uint32_t rdy; - whal_Reg_Update(WHAL_STM32WB0_RCC_BASE, WHAL_STM32WB0_RCC_CR_REG, - WHAL_STM32WB0_RCC_CR_HSEON_Msk, - WHAL_STM32WB0_RCC_CR_HSEON_Msk); + whal_Reg32_Update(WHAL_STM32WB0_RCC_BASE, WHAL_STM32WB0_RCC_CR_REG, + WHAL_STM32WB0_RCC_CR_HSEON_Msk, + WHAL_STM32WB0_RCC_CR_HSEON_Msk); do { - whal_Reg_Get(WHAL_STM32WB0_RCC_BASE, WHAL_STM32WB0_RCC_CR_REG, - WHAL_STM32WB0_RCC_CR_HSERDY_Msk, - WHAL_STM32WB0_RCC_CR_HSERDY_Pos, &rdy); + whal_Reg32_Get(WHAL_STM32WB0_RCC_BASE, WHAL_STM32WB0_RCC_CR_REG, + WHAL_STM32WB0_RCC_CR_HSERDY_Msk, + WHAL_STM32WB0_RCC_CR_HSERDY_Pos, &rdy); } while (!rdy); return WHAL_SUCCESS; } @@ -208,15 +208,15 @@ static inline whal_Error whal_Stm32wb0_Rcc_EnableHse(void) */ static inline whal_Error whal_Stm32wb0_Rcc_EnableHsiPll(void) { - size_t rdy; + uint32_t rdy; - whal_Reg_Update(WHAL_STM32WB0_RCC_BASE, WHAL_STM32WB0_RCC_CR_REG, - WHAL_STM32WB0_RCC_CR_HSIPLLON_Msk, - WHAL_STM32WB0_RCC_CR_HSIPLLON_Msk); + whal_Reg32_Update(WHAL_STM32WB0_RCC_BASE, WHAL_STM32WB0_RCC_CR_REG, + WHAL_STM32WB0_RCC_CR_HSIPLLON_Msk, + WHAL_STM32WB0_RCC_CR_HSIPLLON_Msk); do { - whal_Reg_Get(WHAL_STM32WB0_RCC_BASE, WHAL_STM32WB0_RCC_CR_REG, - WHAL_STM32WB0_RCC_CR_HSIPLLRDY_Msk, - WHAL_STM32WB0_RCC_CR_HSIPLLRDY_Pos, &rdy); + whal_Reg32_Get(WHAL_STM32WB0_RCC_BASE, WHAL_STM32WB0_RCC_CR_REG, + WHAL_STM32WB0_RCC_CR_HSIPLLRDY_Msk, + WHAL_STM32WB0_RCC_CR_HSIPLLRDY_Pos, &rdy); } while (!rdy); return WHAL_SUCCESS; } @@ -236,16 +236,16 @@ static inline whal_Error whal_Stm32wb0_Rcc_EnableHsiPll(void) static inline whal_Error whal_Stm32wb0_Rcc_SetFastClkSrc( whal_Stm32wb0_Rcc_FastClkSrc src) { - size_t status; + uint32_t status; - whal_Reg_Update(WHAL_STM32WB0_RCC_BASE, WHAL_STM32WB0_RCC_CFGR_REG, - WHAL_STM32WB0_RCC_CFGR_HSESEL_Msk, - whal_SetBits(WHAL_STM32WB0_RCC_CFGR_HSESEL_Msk, - WHAL_STM32WB0_RCC_CFGR_HSESEL_Pos, src)); + whal_Reg32_Update(WHAL_STM32WB0_RCC_BASE, WHAL_STM32WB0_RCC_CFGR_REG, + WHAL_STM32WB0_RCC_CFGR_HSESEL_Msk, + whal_SetBits(WHAL_STM32WB0_RCC_CFGR_HSESEL_Msk, + WHAL_STM32WB0_RCC_CFGR_HSESEL_Pos, src)); do { - whal_Reg_Get(WHAL_STM32WB0_RCC_BASE, WHAL_STM32WB0_RCC_CFGR_REG, - WHAL_STM32WB0_RCC_CFGR_HSESEL_STATUS_Msk, - WHAL_STM32WB0_RCC_CFGR_HSESEL_STATUS_Pos, &status); + whal_Reg32_Get(WHAL_STM32WB0_RCC_BASE, WHAL_STM32WB0_RCC_CFGR_REG, + WHAL_STM32WB0_RCC_CFGR_HSESEL_STATUS_Msk, + WHAL_STM32WB0_RCC_CFGR_HSESEL_STATUS_Pos, &status); } while (status != (size_t)src); return WHAL_SUCCESS; } @@ -264,16 +264,16 @@ static inline whal_Error whal_Stm32wb0_Rcc_SetFastClkSrc( static inline whal_Error whal_Stm32wb0_Rcc_SetSysClock( whal_Stm32wb0_Rcc_SysClkDiv div) { - size_t status; + uint32_t status; - whal_Reg_Update(WHAL_STM32WB0_RCC_BASE, WHAL_STM32WB0_RCC_CFGR_REG, - WHAL_STM32WB0_RCC_CFGR_CLKSYSDIV_Msk, - whal_SetBits(WHAL_STM32WB0_RCC_CFGR_CLKSYSDIV_Msk, - WHAL_STM32WB0_RCC_CFGR_CLKSYSDIV_Pos, div)); + whal_Reg32_Update(WHAL_STM32WB0_RCC_BASE, WHAL_STM32WB0_RCC_CFGR_REG, + WHAL_STM32WB0_RCC_CFGR_CLKSYSDIV_Msk, + whal_SetBits(WHAL_STM32WB0_RCC_CFGR_CLKSYSDIV_Msk, + WHAL_STM32WB0_RCC_CFGR_CLKSYSDIV_Pos, div)); do { - whal_Reg_Get(WHAL_STM32WB0_RCC_BASE, WHAL_STM32WB0_RCC_CFGR_REG, - WHAL_STM32WB0_RCC_CFGR_CLKSYSDIV_STATUS_Msk, - WHAL_STM32WB0_RCC_CFGR_CLKSYSDIV_STATUS_Pos, &status); + whal_Reg32_Get(WHAL_STM32WB0_RCC_BASE, WHAL_STM32WB0_RCC_CFGR_REG, + WHAL_STM32WB0_RCC_CFGR_CLKSYSDIV_STATUS_Msk, + WHAL_STM32WB0_RCC_CFGR_CLKSYSDIV_STATUS_Pos, &status); } while (status != (size_t)div); return WHAL_SUCCESS; } @@ -288,8 +288,8 @@ static inline whal_Error whal_Stm32wb0_Rcc_SetSysClock( static inline whal_Error whal_Stm32wb0_Rcc_EnablePeriphClk( const whal_Stm32wb0_Rcc_PeriphClk *clk) { - whal_Reg_Update(WHAL_STM32WB0_RCC_BASE, clk->regOffset, clk->enableMask, - whal_SetBits(clk->enableMask, clk->enablePos, 1)); + whal_Reg32_Update(WHAL_STM32WB0_RCC_BASE, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 1)); return WHAL_SUCCESS; } @@ -303,8 +303,8 @@ static inline whal_Error whal_Stm32wb0_Rcc_EnablePeriphClk( static inline whal_Error whal_Stm32wb0_Rcc_DisablePeriphClk( const whal_Stm32wb0_Rcc_PeriphClk *clk) { - whal_Reg_Update(WHAL_STM32WB0_RCC_BASE, clk->regOffset, clk->enableMask, - whal_SetBits(clk->enableMask, clk->enablePos, 0)); + whal_Reg32_Update(WHAL_STM32WB0_RCC_BASE, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 0)); return WHAL_SUCCESS; } diff --git a/wolfHAL/clock/stm32wb_rcc.h b/wolfHAL/clock/stm32wb_rcc.h index cb5cf0b0..2d253407 100644 --- a/wolfHAL/clock/stm32wb_rcc.h +++ b/wolfHAL/clock/stm32wb_rcc.h @@ -175,12 +175,12 @@ typedef struct { static inline whal_Error whal_Stm32wb_Rcc_EnableOsc( const whal_Stm32wb_Rcc_OscCfg *cfg) { - size_t rdy; + uint32_t rdy; - whal_Reg_Update(WHAL_STM32WB_RCC_BASE, cfg->onReg, cfg->onMsk, cfg->onMsk); + whal_Reg32_Update(WHAL_STM32WB_RCC_BASE, cfg->onReg, cfg->onMsk, cfg->onMsk); do { - whal_Reg_Get(WHAL_STM32WB_RCC_BASE, cfg->rdyReg, cfg->rdyMsk, - cfg->rdyPos, &rdy); + whal_Reg32_Get(WHAL_STM32WB_RCC_BASE, cfg->rdyReg, cfg->rdyMsk, + cfg->rdyPos, &rdy); } while (!rdy); return WHAL_SUCCESS; } @@ -195,7 +195,7 @@ static inline whal_Error whal_Stm32wb_Rcc_EnableOsc( static inline whal_Error whal_Stm32wb_Rcc_DisableOsc( const whal_Stm32wb_Rcc_OscCfg *cfg) { - whal_Reg_Update(WHAL_STM32WB_RCC_BASE, cfg->onReg, cfg->onMsk, 0); + whal_Reg32_Update(WHAL_STM32WB_RCC_BASE, cfg->onReg, cfg->onMsk, 0); return WHAL_SUCCESS; } @@ -211,20 +211,20 @@ static inline whal_Error whal_Stm32wb_Rcc_DisableOsc( static inline whal_Error whal_Stm32wb_Rcc_EnableMsi( whal_Stm32wb_Rcc_MsiRange range) { - size_t rdy; + uint32_t rdy; - whal_Reg_Update(WHAL_STM32WB_RCC_BASE, WHAL_STM32WB_RCC_CR_REG, - WHAL_STM32WB_RCC_CR_MSION_Msk, - WHAL_STM32WB_RCC_CR_MSION_Msk); + whal_Reg32_Update(WHAL_STM32WB_RCC_BASE, WHAL_STM32WB_RCC_CR_REG, + WHAL_STM32WB_RCC_CR_MSION_Msk, + WHAL_STM32WB_RCC_CR_MSION_Msk); do { - whal_Reg_Get(WHAL_STM32WB_RCC_BASE, WHAL_STM32WB_RCC_CR_REG, - WHAL_STM32WB_RCC_CR_MSIRDY_Msk, - WHAL_STM32WB_RCC_CR_MSIRDY_Pos, &rdy); + whal_Reg32_Get(WHAL_STM32WB_RCC_BASE, WHAL_STM32WB_RCC_CR_REG, + WHAL_STM32WB_RCC_CR_MSIRDY_Msk, + WHAL_STM32WB_RCC_CR_MSIRDY_Pos, &rdy); } while (!rdy); - whal_Reg_Update(WHAL_STM32WB_RCC_BASE, WHAL_STM32WB_RCC_CR_REG, - WHAL_STM32WB_RCC_CR_MSIRANGE_Msk, - whal_SetBits(WHAL_STM32WB_RCC_CR_MSIRANGE_Msk, - WHAL_STM32WB_RCC_CR_MSIRANGE_Pos, range)); + whal_Reg32_Update(WHAL_STM32WB_RCC_BASE, WHAL_STM32WB_RCC_CR_REG, + WHAL_STM32WB_RCC_CR_MSIRANGE_Msk, + whal_SetBits(WHAL_STM32WB_RCC_CR_MSIRANGE_Msk, + WHAL_STM32WB_RCC_CR_MSIRANGE_Pos, range)); return WHAL_SUCCESS; } @@ -240,31 +240,31 @@ static inline whal_Error whal_Stm32wb_Rcc_EnableMsi( static inline whal_Error whal_Stm32wb_Rcc_EnablePll( const whal_Stm32wb_Rcc_PllCfg *cfg) { - size_t rdy; + uint32_t rdy; - whal_Reg_Update(WHAL_STM32WB_RCC_BASE, WHAL_STM32WB_RCC_PLLCFGR_REG, - WHAL_STM32WB_RCC_PLLCFGR_Msk, - whal_SetBits(WHAL_STM32WB_RCC_PLLCFGR_PLLSRC_Msk, - WHAL_STM32WB_RCC_PLLCFGR_PLLSRC_Pos, cfg->clkSrc) | - whal_SetBits(WHAL_STM32WB_RCC_PLLCFGR_PLLM_Msk, - WHAL_STM32WB_RCC_PLLCFGR_PLLM_Pos, cfg->m) | - whal_SetBits(WHAL_STM32WB_RCC_PLLCFGR_PLLN_Msk, - WHAL_STM32WB_RCC_PLLCFGR_PLLN_Pos, cfg->n) | - whal_SetBits(WHAL_STM32WB_RCC_PLLCFGR_PLLP_Msk, - WHAL_STM32WB_RCC_PLLCFGR_PLLP_Pos, cfg->p) | - whal_SetBits(WHAL_STM32WB_RCC_PLLCFGR_PLLQ_Msk, - WHAL_STM32WB_RCC_PLLCFGR_PLLQ_Pos, cfg->q) | - whal_SetBits(WHAL_STM32WB_RCC_PLLCFGR_PLLREN_Msk, - WHAL_STM32WB_RCC_PLLCFGR_PLLREN_Pos, 1) | - whal_SetBits(WHAL_STM32WB_RCC_PLLCFGR_PLLR_Msk, - WHAL_STM32WB_RCC_PLLCFGR_PLLR_Pos, cfg->r)); - whal_Reg_Update(WHAL_STM32WB_RCC_BASE, WHAL_STM32WB_RCC_CR_REG, - WHAL_STM32WB_RCC_CR_PLLON_Msk, - WHAL_STM32WB_RCC_CR_PLLON_Msk); + whal_Reg32_Update(WHAL_STM32WB_RCC_BASE, WHAL_STM32WB_RCC_PLLCFGR_REG, + WHAL_STM32WB_RCC_PLLCFGR_Msk, + whal_SetBits(WHAL_STM32WB_RCC_PLLCFGR_PLLSRC_Msk, + WHAL_STM32WB_RCC_PLLCFGR_PLLSRC_Pos, cfg->clkSrc) | + whal_SetBits(WHAL_STM32WB_RCC_PLLCFGR_PLLM_Msk, + WHAL_STM32WB_RCC_PLLCFGR_PLLM_Pos, cfg->m) | + whal_SetBits(WHAL_STM32WB_RCC_PLLCFGR_PLLN_Msk, + WHAL_STM32WB_RCC_PLLCFGR_PLLN_Pos, cfg->n) | + whal_SetBits(WHAL_STM32WB_RCC_PLLCFGR_PLLP_Msk, + WHAL_STM32WB_RCC_PLLCFGR_PLLP_Pos, cfg->p) | + whal_SetBits(WHAL_STM32WB_RCC_PLLCFGR_PLLQ_Msk, + WHAL_STM32WB_RCC_PLLCFGR_PLLQ_Pos, cfg->q) | + whal_SetBits(WHAL_STM32WB_RCC_PLLCFGR_PLLREN_Msk, + WHAL_STM32WB_RCC_PLLCFGR_PLLREN_Pos, 1) | + whal_SetBits(WHAL_STM32WB_RCC_PLLCFGR_PLLR_Msk, + WHAL_STM32WB_RCC_PLLCFGR_PLLR_Pos, cfg->r)); + whal_Reg32_Update(WHAL_STM32WB_RCC_BASE, WHAL_STM32WB_RCC_CR_REG, + WHAL_STM32WB_RCC_CR_PLLON_Msk, + WHAL_STM32WB_RCC_CR_PLLON_Msk); do { - whal_Reg_Get(WHAL_STM32WB_RCC_BASE, WHAL_STM32WB_RCC_CR_REG, - WHAL_STM32WB_RCC_CR_PLLRDY_Msk, - WHAL_STM32WB_RCC_CR_PLLRDY_Pos, &rdy); + whal_Reg32_Get(WHAL_STM32WB_RCC_BASE, WHAL_STM32WB_RCC_CR_REG, + WHAL_STM32WB_RCC_CR_PLLRDY_Msk, + WHAL_STM32WB_RCC_CR_PLLRDY_Pos, &rdy); } while (!rdy); return WHAL_SUCCESS; } @@ -276,8 +276,8 @@ static inline whal_Error whal_Stm32wb_Rcc_EnablePll( */ static inline whal_Error whal_Stm32wb_Rcc_DisablePll(void) { - whal_Reg_Update(WHAL_STM32WB_RCC_BASE, WHAL_STM32WB_RCC_CR_REG, - WHAL_STM32WB_RCC_CR_PLLON_Msk, 0); + whal_Reg32_Update(WHAL_STM32WB_RCC_BASE, WHAL_STM32WB_RCC_CR_REG, + WHAL_STM32WB_RCC_CR_PLLON_Msk, 0); return WHAL_SUCCESS; } @@ -291,16 +291,16 @@ static inline whal_Error whal_Stm32wb_Rcc_DisablePll(void) static inline whal_Error whal_Stm32wb_Rcc_SetSysClock( whal_Stm32wb_Rcc_SysClockSrc src) { - size_t sws; + uint32_t sws; - whal_Reg_Update(WHAL_STM32WB_RCC_BASE, WHAL_STM32WB_RCC_CFGR_REG, - WHAL_STM32WB_RCC_CFGR_SW_Msk, - whal_SetBits(WHAL_STM32WB_RCC_CFGR_SW_Msk, - WHAL_STM32WB_RCC_CFGR_SW_Pos, src)); + whal_Reg32_Update(WHAL_STM32WB_RCC_BASE, WHAL_STM32WB_RCC_CFGR_REG, + WHAL_STM32WB_RCC_CFGR_SW_Msk, + whal_SetBits(WHAL_STM32WB_RCC_CFGR_SW_Msk, + WHAL_STM32WB_RCC_CFGR_SW_Pos, src)); do { - whal_Reg_Get(WHAL_STM32WB_RCC_BASE, WHAL_STM32WB_RCC_CFGR_REG, - WHAL_STM32WB_RCC_CFGR_SWS_Msk, - WHAL_STM32WB_RCC_CFGR_SWS_Pos, &sws); + whal_Reg32_Get(WHAL_STM32WB_RCC_BASE, WHAL_STM32WB_RCC_CFGR_REG, + WHAL_STM32WB_RCC_CFGR_SWS_Msk, + WHAL_STM32WB_RCC_CFGR_SWS_Pos, &sws); } while (sws != (size_t)src); return WHAL_SUCCESS; } @@ -315,8 +315,8 @@ static inline whal_Error whal_Stm32wb_Rcc_SetSysClock( static inline whal_Error whal_Stm32wb_Rcc_EnablePeriphClk( const whal_Stm32wb_Rcc_PeriphClk *clk) { - whal_Reg_Update(WHAL_STM32WB_RCC_BASE, clk->regOffset, clk->enableMask, - whal_SetBits(clk->enableMask, clk->enablePos, 1)); + whal_Reg32_Update(WHAL_STM32WB_RCC_BASE, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 1)); return WHAL_SUCCESS; } @@ -330,8 +330,8 @@ static inline whal_Error whal_Stm32wb_Rcc_EnablePeriphClk( static inline whal_Error whal_Stm32wb_Rcc_DisablePeriphClk( const whal_Stm32wb_Rcc_PeriphClk *clk) { - whal_Reg_Update(WHAL_STM32WB_RCC_BASE, clk->regOffset, clk->enableMask, - whal_SetBits(clk->enableMask, clk->enablePos, 0)); + whal_Reg32_Update(WHAL_STM32WB_RCC_BASE, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 0)); return WHAL_SUCCESS; } diff --git a/wolfHAL/clock/stm32wba_rcc.h b/wolfHAL/clock/stm32wba_rcc.h index ec534fdf..eab294d5 100644 --- a/wolfHAL/clock/stm32wba_rcc.h +++ b/wolfHAL/clock/stm32wba_rcc.h @@ -178,12 +178,12 @@ typedef struct { static inline whal_Error whal_Stm32wba_Rcc_EnableOsc( const whal_Stm32wba_Rcc_OscCfg *cfg) { - size_t rdy; + uint32_t rdy; - whal_Reg_Update(WHAL_STM32WBA_RCC_BASE, cfg->onReg, cfg->onMsk, cfg->onMsk); + whal_Reg32_Update(WHAL_STM32WBA_RCC_BASE, cfg->onReg, cfg->onMsk, cfg->onMsk); do { - whal_Reg_Get(WHAL_STM32WBA_RCC_BASE, cfg->rdyReg, cfg->rdyMsk, - cfg->rdyPos, &rdy); + whal_Reg32_Get(WHAL_STM32WBA_RCC_BASE, cfg->rdyReg, cfg->rdyMsk, + cfg->rdyPos, &rdy); } while (!rdy); return WHAL_SUCCESS; } @@ -198,7 +198,7 @@ static inline whal_Error whal_Stm32wba_Rcc_EnableOsc( static inline whal_Error whal_Stm32wba_Rcc_DisableOsc( const whal_Stm32wba_Rcc_OscCfg *cfg) { - whal_Reg_Update(WHAL_STM32WBA_RCC_BASE, cfg->onReg, cfg->onMsk, 0); + whal_Reg32_Update(WHAL_STM32WBA_RCC_BASE, cfg->onReg, cfg->onMsk, 0); return WHAL_SUCCESS; } @@ -215,43 +215,43 @@ static inline whal_Error whal_Stm32wba_Rcc_DisableOsc( static inline whal_Error whal_Stm32wba_Rcc_EnablePll1( const whal_Stm32wba_Rcc_Pll1Cfg *cfg) { - size_t rdy; + uint32_t rdy; /* Disable PLL1 before reconfiguring; wait until off. */ - whal_Reg_Update(WHAL_STM32WBA_RCC_BASE, WHAL_STM32WBA_RCC_CR_REG, - WHAL_STM32WBA_RCC_CR_PLL1ON_Msk, 0); + whal_Reg32_Update(WHAL_STM32WBA_RCC_BASE, WHAL_STM32WBA_RCC_CR_REG, + WHAL_STM32WBA_RCC_CR_PLL1ON_Msk, 0); do { - whal_Reg_Get(WHAL_STM32WBA_RCC_BASE, WHAL_STM32WBA_RCC_CR_REG, - WHAL_STM32WBA_RCC_CR_PLL1RDY_Msk, - WHAL_STM32WBA_RCC_CR_PLL1RDY_Pos, &rdy); + whal_Reg32_Get(WHAL_STM32WBA_RCC_BASE, WHAL_STM32WBA_RCC_CR_REG, + WHAL_STM32WBA_RCC_CR_PLL1RDY_Msk, + WHAL_STM32WBA_RCC_CR_PLL1RDY_Pos, &rdy); } while (rdy); - whal_Reg_Write(WHAL_STM32WBA_RCC_BASE, WHAL_STM32WBA_RCC_PLL1CFGR_REG, - whal_SetBits(WHAL_STM32WBA_RCC_PLL1CFGR_SRC_Msk, - WHAL_STM32WBA_RCC_PLL1CFGR_SRC_Pos, cfg->clkSrc) | - whal_SetBits(WHAL_STM32WBA_RCC_PLL1CFGR_RGE_Msk, - WHAL_STM32WBA_RCC_PLL1CFGR_RGE_Pos, cfg->rge) | - whal_SetBits(WHAL_STM32WBA_RCC_PLL1CFGR_M_Msk, - WHAL_STM32WBA_RCC_PLL1CFGR_M_Pos, cfg->m) | - whal_SetBits(WHAL_STM32WBA_RCC_PLL1CFGR_REN_Msk, - WHAL_STM32WBA_RCC_PLL1CFGR_REN_Pos, 1)); - whal_Reg_Write(WHAL_STM32WBA_RCC_BASE, WHAL_STM32WBA_RCC_PLL1DIVR_REG, - whal_SetBits(WHAL_STM32WBA_RCC_PLL1DIVR_N_Msk, - WHAL_STM32WBA_RCC_PLL1DIVR_N_Pos, cfg->n) | - whal_SetBits(WHAL_STM32WBA_RCC_PLL1DIVR_P_Msk, - WHAL_STM32WBA_RCC_PLL1DIVR_P_Pos, cfg->p) | - whal_SetBits(WHAL_STM32WBA_RCC_PLL1DIVR_Q_Msk, - WHAL_STM32WBA_RCC_PLL1DIVR_Q_Pos, cfg->q) | - whal_SetBits(WHAL_STM32WBA_RCC_PLL1DIVR_R_Msk, - WHAL_STM32WBA_RCC_PLL1DIVR_R_Pos, cfg->r)); - - whal_Reg_Update(WHAL_STM32WBA_RCC_BASE, WHAL_STM32WBA_RCC_CR_REG, - WHAL_STM32WBA_RCC_CR_PLL1ON_Msk, - WHAL_STM32WBA_RCC_CR_PLL1ON_Msk); + whal_Reg32_Write(WHAL_STM32WBA_RCC_BASE, WHAL_STM32WBA_RCC_PLL1CFGR_REG, + whal_SetBits(WHAL_STM32WBA_RCC_PLL1CFGR_SRC_Msk, + WHAL_STM32WBA_RCC_PLL1CFGR_SRC_Pos, cfg->clkSrc) | + whal_SetBits(WHAL_STM32WBA_RCC_PLL1CFGR_RGE_Msk, + WHAL_STM32WBA_RCC_PLL1CFGR_RGE_Pos, cfg->rge) | + whal_SetBits(WHAL_STM32WBA_RCC_PLL1CFGR_M_Msk, + WHAL_STM32WBA_RCC_PLL1CFGR_M_Pos, cfg->m) | + whal_SetBits(WHAL_STM32WBA_RCC_PLL1CFGR_REN_Msk, + WHAL_STM32WBA_RCC_PLL1CFGR_REN_Pos, 1)); + whal_Reg32_Write(WHAL_STM32WBA_RCC_BASE, WHAL_STM32WBA_RCC_PLL1DIVR_REG, + whal_SetBits(WHAL_STM32WBA_RCC_PLL1DIVR_N_Msk, + WHAL_STM32WBA_RCC_PLL1DIVR_N_Pos, cfg->n) | + whal_SetBits(WHAL_STM32WBA_RCC_PLL1DIVR_P_Msk, + WHAL_STM32WBA_RCC_PLL1DIVR_P_Pos, cfg->p) | + whal_SetBits(WHAL_STM32WBA_RCC_PLL1DIVR_Q_Msk, + WHAL_STM32WBA_RCC_PLL1DIVR_Q_Pos, cfg->q) | + whal_SetBits(WHAL_STM32WBA_RCC_PLL1DIVR_R_Msk, + WHAL_STM32WBA_RCC_PLL1DIVR_R_Pos, cfg->r)); + + whal_Reg32_Update(WHAL_STM32WBA_RCC_BASE, WHAL_STM32WBA_RCC_CR_REG, + WHAL_STM32WBA_RCC_CR_PLL1ON_Msk, + WHAL_STM32WBA_RCC_CR_PLL1ON_Msk); do { - whal_Reg_Get(WHAL_STM32WBA_RCC_BASE, WHAL_STM32WBA_RCC_CR_REG, - WHAL_STM32WBA_RCC_CR_PLL1RDY_Msk, - WHAL_STM32WBA_RCC_CR_PLL1RDY_Pos, &rdy); + whal_Reg32_Get(WHAL_STM32WBA_RCC_BASE, WHAL_STM32WBA_RCC_CR_REG, + WHAL_STM32WBA_RCC_CR_PLL1RDY_Msk, + WHAL_STM32WBA_RCC_CR_PLL1RDY_Pos, &rdy); } while (!rdy); return WHAL_SUCCESS; } @@ -263,8 +263,8 @@ static inline whal_Error whal_Stm32wba_Rcc_EnablePll1( */ static inline whal_Error whal_Stm32wba_Rcc_DisablePll1(void) { - whal_Reg_Update(WHAL_STM32WBA_RCC_BASE, WHAL_STM32WBA_RCC_CR_REG, - WHAL_STM32WBA_RCC_CR_PLL1ON_Msk, 0); + whal_Reg32_Update(WHAL_STM32WBA_RCC_BASE, WHAL_STM32WBA_RCC_CR_REG, + WHAL_STM32WBA_RCC_CR_PLL1ON_Msk, 0); return WHAL_SUCCESS; } @@ -277,15 +277,15 @@ static inline whal_Error whal_Stm32wba_Rcc_DisablePll1(void) */ static inline whal_Error whal_Stm32wba_Rcc_EnableLsi(void) { - size_t rdy; + uint32_t rdy; - whal_Reg_Update(WHAL_STM32WBA_RCC_BASE, WHAL_STM32WBA_RCC_BDCR1_REG, - WHAL_STM32WBA_RCC_BDCR1_LSI1ON_Msk, - WHAL_STM32WBA_RCC_BDCR1_LSI1ON_Msk); + whal_Reg32_Update(WHAL_STM32WBA_RCC_BASE, WHAL_STM32WBA_RCC_BDCR1_REG, + WHAL_STM32WBA_RCC_BDCR1_LSI1ON_Msk, + WHAL_STM32WBA_RCC_BDCR1_LSI1ON_Msk); do { - whal_Reg_Get(WHAL_STM32WBA_RCC_BASE, WHAL_STM32WBA_RCC_BDCR1_REG, - WHAL_STM32WBA_RCC_BDCR1_LSI1RDY_Msk, - WHAL_STM32WBA_RCC_BDCR1_LSI1RDY_Pos, &rdy); + whal_Reg32_Get(WHAL_STM32WBA_RCC_BASE, WHAL_STM32WBA_RCC_BDCR1_REG, + WHAL_STM32WBA_RCC_BDCR1_LSI1RDY_Msk, + WHAL_STM32WBA_RCC_BDCR1_LSI1RDY_Pos, &rdy); } while (!rdy); return WHAL_SUCCESS; } @@ -297,8 +297,8 @@ static inline whal_Error whal_Stm32wba_Rcc_EnableLsi(void) */ static inline whal_Error whal_Stm32wba_Rcc_DisableLsi(void) { - whal_Reg_Update(WHAL_STM32WBA_RCC_BASE, WHAL_STM32WBA_RCC_BDCR1_REG, - WHAL_STM32WBA_RCC_BDCR1_LSI1ON_Msk, 0); + whal_Reg32_Update(WHAL_STM32WBA_RCC_BASE, WHAL_STM32WBA_RCC_BDCR1_REG, + WHAL_STM32WBA_RCC_BDCR1_LSI1ON_Msk, 0); return WHAL_SUCCESS; } @@ -312,16 +312,16 @@ static inline whal_Error whal_Stm32wba_Rcc_DisableLsi(void) static inline whal_Error whal_Stm32wba_Rcc_SetSysClock( whal_Stm32wba_Rcc_SysClockSrc src) { - size_t sws; + uint32_t sws; - whal_Reg_Update(WHAL_STM32WBA_RCC_BASE, WHAL_STM32WBA_RCC_CFGR1_REG, - WHAL_STM32WBA_RCC_CFGR1_SW_Msk, - whal_SetBits(WHAL_STM32WBA_RCC_CFGR1_SW_Msk, - WHAL_STM32WBA_RCC_CFGR1_SW_Pos, src)); + whal_Reg32_Update(WHAL_STM32WBA_RCC_BASE, WHAL_STM32WBA_RCC_CFGR1_REG, + WHAL_STM32WBA_RCC_CFGR1_SW_Msk, + whal_SetBits(WHAL_STM32WBA_RCC_CFGR1_SW_Msk, + WHAL_STM32WBA_RCC_CFGR1_SW_Pos, src)); do { - whal_Reg_Get(WHAL_STM32WBA_RCC_BASE, WHAL_STM32WBA_RCC_CFGR1_REG, - WHAL_STM32WBA_RCC_CFGR1_SWS_Msk, - WHAL_STM32WBA_RCC_CFGR1_SWS_Pos, &sws); + whal_Reg32_Get(WHAL_STM32WBA_RCC_BASE, WHAL_STM32WBA_RCC_CFGR1_REG, + WHAL_STM32WBA_RCC_CFGR1_SWS_Msk, + WHAL_STM32WBA_RCC_CFGR1_SWS_Pos, &sws); } while (sws != (size_t)src); return WHAL_SUCCESS; } @@ -336,11 +336,11 @@ static inline whal_Error whal_Stm32wba_Rcc_SetSysClock( static inline whal_Error whal_Stm32wba_Rcc_SetRngClockSrc( whal_Stm32wba_Rcc_RngSrc src) { - whal_Reg_Update(WHAL_STM32WBA_RCC_BASE, WHAL_STM32WBA_RCC_CCIPR2_REG, - WHAL_STM32WBA_RCC_CCIPR2_RNGSEL_Msk, - whal_SetBits(WHAL_STM32WBA_RCC_CCIPR2_RNGSEL_Msk, - WHAL_STM32WBA_RCC_CCIPR2_RNGSEL_Pos, - src)); + whal_Reg32_Update(WHAL_STM32WBA_RCC_BASE, WHAL_STM32WBA_RCC_CCIPR2_REG, + WHAL_STM32WBA_RCC_CCIPR2_RNGSEL_Msk, + whal_SetBits(WHAL_STM32WBA_RCC_CCIPR2_RNGSEL_Msk, + WHAL_STM32WBA_RCC_CCIPR2_RNGSEL_Pos, + src)); return WHAL_SUCCESS; } @@ -353,10 +353,10 @@ static inline whal_Error whal_Stm32wba_Rcc_SetRngClockSrc( */ static inline whal_Error whal_Stm32wba_Rcc_SetHpre5(uint8_t hpre5) { - whal_Reg_Update(WHAL_STM32WBA_RCC_BASE, WHAL_STM32WBA_RCC_CFGR4_REG, - WHAL_STM32WBA_RCC_CFGR4_HPRE5_Msk, - whal_SetBits(WHAL_STM32WBA_RCC_CFGR4_HPRE5_Msk, - WHAL_STM32WBA_RCC_CFGR4_HPRE5_Pos, hpre5)); + whal_Reg32_Update(WHAL_STM32WBA_RCC_BASE, WHAL_STM32WBA_RCC_CFGR4_REG, + WHAL_STM32WBA_RCC_CFGR4_HPRE5_Msk, + whal_SetBits(WHAL_STM32WBA_RCC_CFGR4_HPRE5_Msk, + WHAL_STM32WBA_RCC_CFGR4_HPRE5_Pos, hpre5)); return WHAL_SUCCESS; } @@ -370,8 +370,8 @@ static inline whal_Error whal_Stm32wba_Rcc_SetHpre5(uint8_t hpre5) static inline whal_Error whal_Stm32wba_Rcc_EnablePeriphClk( const whal_Stm32wba_Rcc_PeriphClk *clk) { - whal_Reg_Update(WHAL_STM32WBA_RCC_BASE, clk->regOffset, clk->enableMask, - whal_SetBits(clk->enableMask, clk->enablePos, 1)); + whal_Reg32_Update(WHAL_STM32WBA_RCC_BASE, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 1)); return WHAL_SUCCESS; } @@ -385,8 +385,8 @@ static inline whal_Error whal_Stm32wba_Rcc_EnablePeriphClk( static inline whal_Error whal_Stm32wba_Rcc_DisablePeriphClk( const whal_Stm32wba_Rcc_PeriphClk *clk) { - whal_Reg_Update(WHAL_STM32WBA_RCC_BASE, clk->regOffset, clk->enableMask, - whal_SetBits(clk->enableMask, clk->enablePos, 0)); + whal_Reg32_Update(WHAL_STM32WBA_RCC_BASE, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 0)); return WHAL_SUCCESS; } diff --git a/wolfHAL/crypto/crypto.h b/wolfHAL/crypto/crypto.h index a6831305..c74db78c 100644 --- a/wolfHAL/crypto/crypto.h +++ b/wolfHAL/crypto/crypto.h @@ -62,7 +62,7 @@ typedef struct { * @brief Crypto hardware device instance. */ struct whal_Crypto { - const size_t base; + const uintptr_t base; const whal_CryptoDriver *driver; const void *cfg; }; diff --git a/wolfHAL/dma/dma.h b/wolfHAL/dma/dma.h index eae97346..13ac2154 100644 --- a/wolfHAL/dma/dma.h +++ b/wolfHAL/dma/dma.h @@ -24,6 +24,7 @@ #include #include +#include /* * @file dma.h @@ -66,7 +67,7 @@ typedef struct { * @brief DMA device instance containing driver and configuration data. */ struct whal_Dma { - const size_t base; + const uintptr_t base; const whal_DmaDriver *driver; const void *cfg; }; diff --git a/wolfHAL/dma/stm32wb_dma.h b/wolfHAL/dma/stm32wb_dma.h index 8fdbcc42..fa90a06d 100644 --- a/wolfHAL/dma/stm32wb_dma.h +++ b/wolfHAL/dma/stm32wb_dma.h @@ -92,7 +92,7 @@ typedef struct { * controller. DMA1 uses DMAMUX channels starting at 0; DMA2 starts at 7. */ typedef struct { - size_t dmamuxBase; /* DMAMUX1 register base address */ + uintptr_t dmamuxBase; /* DMAMUX1 register base address */ uint8_t dmamuxChOffset; /* First DMAMUX channel index for this controller */ uint8_t numChannels; /* Number of channels (7 for DMA1, 5 for DMA2) */ } whal_Stm32wb_Dma_Cfg; diff --git a/wolfHAL/eth/eth.h b/wolfHAL/eth/eth.h index c1fd2ec6..2ddde4d5 100644 --- a/wolfHAL/eth/eth.h +++ b/wolfHAL/eth/eth.h @@ -73,7 +73,7 @@ typedef struct { * @brief Ethernet device instance with a base address, driver vtable, and platform-specific cfg. */ struct whal_Eth { - const size_t base; + const uintptr_t base; const whal_EthDriver *driver; void *cfg; uint8_t macAddr[6]; diff --git a/wolfHAL/flash/flash.h b/wolfHAL/flash/flash.h index 31837531..7d1fbbe4 100644 --- a/wolfHAL/flash/flash.h +++ b/wolfHAL/flash/flash.h @@ -57,7 +57,7 @@ typedef struct { * @brief Flash device instance tying configuration to a driver implementation. */ struct whal_Flash { - const size_t base; + const uintptr_t base; const whal_FlashDriver *driver; void *cfg; }; diff --git a/wolfHAL/gpio/gpio.h b/wolfHAL/gpio/gpio.h index 175d5d65..5292ef39 100644 --- a/wolfHAL/gpio/gpio.h +++ b/wolfHAL/gpio/gpio.h @@ -24,6 +24,7 @@ #include #include +#include /* * @file gpio.h @@ -50,7 +51,7 @@ typedef struct { * @brief GPIO device instance containing driver and configuration data. */ struct whal_Gpio { - const size_t base; + const uintptr_t base; const whal_GpioDriver *driver; const void *cfg; }; diff --git a/wolfHAL/i2c/i2c.h b/wolfHAL/i2c/i2c.h index 9086725b..7704f4b2 100644 --- a/wolfHAL/i2c/i2c.h +++ b/wolfHAL/i2c/i2c.h @@ -86,7 +86,7 @@ typedef struct { * @brief I2C device instance with a base address, driver vtable, and platform-specific cfg. */ struct whal_I2c { - const size_t base; + const uintptr_t base; const whal_I2cDriver *driver; void *cfg; }; diff --git a/wolfHAL/ipc/ipc.h b/wolfHAL/ipc/ipc.h index d48459b4..762bd033 100644 --- a/wolfHAL/ipc/ipc.h +++ b/wolfHAL/ipc/ipc.h @@ -51,7 +51,7 @@ typedef struct { * @brief IPC device instance with a base address, driver vtable, and platform-specific cfg. */ struct whal_Ipc { - const size_t base; + const uintptr_t base; const whal_IpcDriver *driver; void *cfg; }; diff --git a/wolfHAL/irq/irq.h b/wolfHAL/irq/irq.h index aba63420..a8489d44 100644 --- a/wolfHAL/irq/irq.h +++ b/wolfHAL/irq/irq.h @@ -24,6 +24,7 @@ #include #include +#include /* * @file irq.h @@ -55,7 +56,7 @@ typedef struct { * @brief Interrupt controller device instance. */ struct whal_Irq { - const size_t base; + const uintptr_t base; const whal_IrqDriver *driver; const void *cfg; }; diff --git a/wolfHAL/power/pic32cz_supc.h b/wolfHAL/power/pic32cz_supc.h index 0363f77c..ba0dbc14 100644 --- a/wolfHAL/power/pic32cz_supc.h +++ b/wolfHAL/power/pic32cz_supc.h @@ -63,9 +63,9 @@ typedef struct whal_Pic32cz_Supc_Supply { static inline whal_Error whal_Pic32cz_Supc_EnableSupply( const whal_Pic32cz_Supc_Supply *supply) { - whal_Reg_Update(WHAL_PIC32CZ_SUPC_BASE, WHAL_PIC32CZ_SUPC_VREGCTRL_REG, - supply->enableMask, - whal_SetBits(supply->enableMask, supply->enablePos, 1)); + whal_Reg32_Update(WHAL_PIC32CZ_SUPC_BASE, WHAL_PIC32CZ_SUPC_VREGCTRL_REG, + supply->enableMask, + whal_SetBits(supply->enableMask, supply->enablePos, 1)); return WHAL_SUCCESS; } @@ -79,9 +79,9 @@ static inline whal_Error whal_Pic32cz_Supc_EnableSupply( static inline whal_Error whal_Pic32cz_Supc_DisableSupply( const whal_Pic32cz_Supc_Supply *supply) { - whal_Reg_Update(WHAL_PIC32CZ_SUPC_BASE, WHAL_PIC32CZ_SUPC_VREGCTRL_REG, - supply->enableMask, - whal_SetBits(supply->enableMask, supply->enablePos, 0)); + whal_Reg32_Update(WHAL_PIC32CZ_SUPC_BASE, WHAL_PIC32CZ_SUPC_VREGCTRL_REG, + supply->enableMask, + whal_SetBits(supply->enableMask, supply->enablePos, 0)); return WHAL_SUCCESS; } diff --git a/wolfHAL/power/stm32l1_pwr.h b/wolfHAL/power/stm32l1_pwr.h index 006dcffe..bbb2f0c6 100644 --- a/wolfHAL/power/stm32l1_pwr.h +++ b/wolfHAL/power/stm32l1_pwr.h @@ -83,18 +83,18 @@ static inline whal_Error whal_Stm32l1_Pwr_SetVosRange( { whal_Error err; - err = whal_Reg_ReadPoll(WHAL_STM32L1_PWR_BASE, WHAL_STM32L1_PWR_CSR_REG, - WHAL_STM32L1_PWR_CSR_VOSF_Msk, 0, timeout); + err = whal_Reg32_ReadPoll(WHAL_STM32L1_PWR_BASE, WHAL_STM32L1_PWR_CSR_REG, + WHAL_STM32L1_PWR_CSR_VOSF_Msk, 0, timeout); if (err) return err; - whal_Reg_Update(WHAL_STM32L1_PWR_BASE, WHAL_STM32L1_PWR_CR_REG, - WHAL_STM32L1_PWR_CR_VOS_Msk, - whal_SetBits(WHAL_STM32L1_PWR_CR_VOS_Msk, - WHAL_STM32L1_PWR_CR_VOS_Pos, range)); + whal_Reg32_Update(WHAL_STM32L1_PWR_BASE, WHAL_STM32L1_PWR_CR_REG, + WHAL_STM32L1_PWR_CR_VOS_Msk, + whal_SetBits(WHAL_STM32L1_PWR_CR_VOS_Msk, + WHAL_STM32L1_PWR_CR_VOS_Pos, range)); - return whal_Reg_ReadPoll(WHAL_STM32L1_PWR_BASE, WHAL_STM32L1_PWR_CSR_REG, - WHAL_STM32L1_PWR_CSR_VOSF_Msk, 0, timeout); + return whal_Reg32_ReadPoll(WHAL_STM32L1_PWR_BASE, WHAL_STM32L1_PWR_CSR_REG, + WHAL_STM32L1_PWR_CSR_VOSF_Msk, 0, timeout); } #endif /* WHAL_STM32L1_PWR_H */ diff --git a/wolfHAL/pwm/pwm.h b/wolfHAL/pwm/pwm.h index 6c7302c8..59325953 100644 --- a/wolfHAL/pwm/pwm.h +++ b/wolfHAL/pwm/pwm.h @@ -91,7 +91,7 @@ typedef struct { * @brief PWM device instance tying a driver and configuration. */ struct whal_Pwm { - const size_t base; + const uintptr_t base; const whal_PwmDriver *driver; void *cfg; }; diff --git a/wolfHAL/reg.h b/wolfHAL/reg.h index 414f97cb..22d557a6 100644 --- a/wolfHAL/reg.h +++ b/wolfHAL/reg.h @@ -33,7 +33,6 @@ * @brief Memory-mapped register access with an explicit width. * * whal_Reg32_* access 32-bit registers, whal_Reg64_* 64-bit registers. - * The older whal_Reg_* API needs WHAL_CFG_REG_LEGACY. */ /* 64-bit registers: only where a 64-bit access is a single access */ @@ -195,114 +194,4 @@ whal_Error whal_Reg64_ReadPoll(uintptr_t base, uint32_t offset, #endif /* WHAL_HAVE_REG64 */ -#ifdef WHAL_CFG_REG_LEGACY - -/* Legacy whal_Reg_* API: size_t arguments, 32-bit accesses. Where size_t - * is wider, values and masks above 32 bits return WHAL_EINVAL. */ -#if SIZE_MAX > 0xFFFFFFFFu -#define WHAL_REG_FITS32(x) ((x) <= 0xFFFFFFFFu) -#else -#define WHAL_REG_FITS32(x) (1) -#endif - -/* - * @brief Legacy: write a 32-bit register. - * - * @param base Base address of the register block. - * @param offset Byte offset from @p base to the register. - * @param value Value to write; must fit in 32 bits. - * - * @retval WHAL_SUCCESS Written. - * @retval WHAL_EINVAL @p value does not fit; nothing written. - */ -static inline whal_Error whal_Reg_Write(size_t base, size_t offset, - size_t value) -{ - if (!WHAL_REG_FITS32(value)) { - return WHAL_EINVAL; - } - whal_Reg32_Write(base + offset, 0, value & 0xFFFFFFFFu); - return WHAL_SUCCESS; -} - -/* - * @brief Legacy: read a 32-bit register. - * - * @param base Base address of the register block. - * @param offset Byte offset from @p base to the register. - * - * @return The register value. - */ -static inline size_t whal_Reg_Read(size_t base, size_t offset) -{ - return whal_Reg32_Read(base + offset, 0); -} - -/* - * @brief Legacy: read-modify-write the bits in @p mask of a 32-bit register. - * - * @param base Base address of the register block. - * @param offset Byte offset from @p base to the register. - * @param mask Bits to change; must fit in 32 bits. - * @param value New bits, already in position; must fit in 32 bits. - * - * @retval WHAL_SUCCESS Updated. - * @retval WHAL_EINVAL @p mask or @p value does not fit; nothing written. - */ -static inline whal_Error whal_Reg_Update(size_t base, size_t offset, - size_t mask, size_t value) -{ - if (!WHAL_REG_FITS32(mask) || !WHAL_REG_FITS32(value)) { - return WHAL_EINVAL; - } - whal_Reg32_Update(base + offset, 0, mask & 0xFFFFFFFFu, - value & 0xFFFFFFFFu); - return WHAL_SUCCESS; -} - -/* - * @brief Legacy: read a field of a 32-bit register. - * - * @param base Base address of the register block. - * @param offset Byte offset from @p base to the register. - * @param msk Bits of the field; must fit in 32 bits. - * @param pos Bit position of the field's LSB. - * @param value Output for the field; 0 on error. - * - * @retval WHAL_SUCCESS Read. - * @retval WHAL_EINVAL @p msk does not fit. - */ -static inline whal_Error whal_Reg_Get(size_t base, size_t offset, size_t msk, - size_t pos, size_t *value) -{ - size_t reg; - - if (!WHAL_REG_FITS32(msk)) { - *value = 0; - return WHAL_EINVAL; - } - reg = whal_Reg32_Read(base + offset, 0); - *value = whal_GetBits(msk, pos, reg); - return WHAL_SUCCESS; -} - -/* - * @brief Legacy: poll a 32-bit register until (reg & mask) == value. - * - * @param base Base address of the register block. - * @param offset Byte offset from @p base to the register. - * @param mask Bits to compare; must fit in 32 bits. - * @param value Expected bits; must fit in 32 bits and in @p mask. - * @param timeout Timeout instance (NULL for unbounded wait). - * - * @retval WHAL_SUCCESS The masked bits matched @p value. - * @retval WHAL_ETIMEOUT The timeout expired first. - * @retval WHAL_EINVAL @p mask or @p value does not fit. - */ -whal_Error whal_Reg_ReadPoll(size_t base, size_t offset, - size_t mask, size_t value, - whal_Timeout *timeout); - -#endif /* WHAL_CFG_REG_LEGACY */ - #endif /* WHAL_REG_H */ diff --git a/wolfHAL/rng/rng.h b/wolfHAL/rng/rng.h index 292c4e35..c2d7c228 100644 --- a/wolfHAL/rng/rng.h +++ b/wolfHAL/rng/rng.h @@ -49,7 +49,7 @@ typedef struct { * @brief RNG device instance with a base address, driver vtable, and platform-specific cfg. */ struct whal_Rng { - const size_t base; + const uintptr_t base; const whal_RngDriver *driver; void *cfg; }; diff --git a/wolfHAL/spi/spi.h b/wolfHAL/spi/spi.h index d7dc7e93..2c8604c6 100644 --- a/wolfHAL/spi/spi.h +++ b/wolfHAL/spi/spi.h @@ -73,7 +73,7 @@ typedef struct { * @brief SPI device instance with a base address, driver vtable, and platform-specific cfg. */ struct whal_Spi { - const size_t base; + const uintptr_t base; const whal_SpiDriver *driver; void *cfg; }; diff --git a/wolfHAL/timer/timer.h b/wolfHAL/timer/timer.h index 56327592..2692f0c0 100644 --- a/wolfHAL/timer/timer.h +++ b/wolfHAL/timer/timer.h @@ -24,6 +24,7 @@ #include #include +#include /* * @file timer.h @@ -52,7 +53,7 @@ typedef struct { * @brief Timer device instance pairing configuration with a driver. */ struct whal_Timer{ - const size_t base; + const uintptr_t base; const whal_TimerDriver *driver; void *cfg; }; diff --git a/wolfHAL/uart/uart.h b/wolfHAL/uart/uart.h index d854c91d..3d58db3c 100644 --- a/wolfHAL/uart/uart.h +++ b/wolfHAL/uart/uart.h @@ -55,7 +55,7 @@ typedef struct { * @brief UART device instance with a base address, driver vtable, and platform-specific cfg. */ struct whal_Uart { - const size_t base; + const uintptr_t base; const whal_UartDriver *driver; void *cfg; }; diff --git a/wolfHAL/watchdog/watchdog.h b/wolfHAL/watchdog/watchdog.h index 18f7b74d..cd55b0eb 100644 --- a/wolfHAL/watchdog/watchdog.h +++ b/wolfHAL/watchdog/watchdog.h @@ -54,7 +54,7 @@ typedef struct { * @brief Watchdog device instance with a base address, driver vtable, and platform-specific cfg. */ struct whal_Watchdog { - const size_t base; + const uintptr_t base; const whal_WatchdogDriver *driver; void *cfg; }; From 7508da8dbceac4579c71a6f8c875711c8a59762d Mon Sep 17 00:00:00 2001 From: night1rider Date: Wed, 4 Nov 2026 16:27:35 -0700 Subject: [PATCH 4/4] [uart, pl011, versal2, test] Add an Arm PL011 UART driver Add a polled Arm PL011 UART driver (pl011_uart) with single-instance and direct API mapping support, baud divisor helper macros, and a platform header for AMD Versal Gen 2 with the UART0 and UART1 bases. Init always sets the baud and format from the configuration. Init and Deinit turn the UART off and wait for the last byte to go out before changing the setup. A new core host test runs the driver against an emulated register block and checks the divisor math, Init (also over a setup an earlier boot stage left), Deinit, Send, Recv errors, argument checks, timeouts, and that each access touches only its own 32-bit register. --- src/uart/pl011_uart.c | 321 ++++++++++++++++++++ tests/README.md | 5 +- tests/core/Makefile | 4 +- tests/core/main.c | 2 + tests/core/test_pl011_uart.c | 515 +++++++++++++++++++++++++++++++++ wolfHAL/platform/amd/versal2.h | 38 +++ wolfHAL/uart/pl011_uart.h | 157 ++++++++++ 7 files changed, 1039 insertions(+), 3 deletions(-) create mode 100644 src/uart/pl011_uart.c create mode 100644 tests/core/test_pl011_uart.c create mode 100644 wolfHAL/platform/amd/versal2.h create mode 100644 wolfHAL/uart/pl011_uart.h diff --git a/src/uart/pl011_uart.c b/src/uart/pl011_uart.c new file mode 100644 index 00000000..8230a7e9 --- /dev/null +++ b/src/uart/pl011_uart.c @@ -0,0 +1,321 @@ +/* pl011_uart.c + * + * Copyright (C) 2026 wolfSSL Inc. + * + * This file is part of wolfHAL. + * + * wolfHAL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfHAL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ + +#include +#ifdef WHAL_CFG_PL011_UART_SINGLE_INSTANCE +#include "wolfHAL_board.h" /* provides WHAL_CFG_PL011_UART_DEV initializer */ +#endif +#include +#include +#include +#include +#include +#include + +/* Register map: AM028 UART module. AMD names in the comments, Arm PL011 + * names in the macros. */ + +/* DATA: TX/RX FIFO. On read, bits 11:8 are the error flags of the byte. */ +#define UART_DR_REG 0x00 +#define UART_DR_DATA_Pos 0 +#define UART_DR_DATA_Msk (WHAL_BITMASK(8) << UART_DR_DATA_Pos) + +#define UART_DR_FE_Pos 8 +#define UART_DR_FE_Msk (1UL << UART_DR_FE_Pos) + +#define UART_DR_PE_Pos 9 +#define UART_DR_PE_Msk (1UL << UART_DR_PE_Pos) + +#define UART_DR_BE_Pos 10 +#define UART_DR_BE_Msk (1UL << UART_DR_BE_Pos) + +#define UART_DR_OE_Pos 11 +#define UART_DR_OE_Msk (1UL << UART_DR_OE_Pos) + +#define UART_DR_ERR_Msk (UART_DR_FE_Msk | UART_DR_PE_Msk | \ + UART_DR_BE_Msk | UART_DR_OE_Msk) + +/* ERR_STAT_CLR (RSR / ECR): any write clears the error flags. */ +#define UART_ECR_REG 0x04 + +/* FLAG */ +#define UART_FR_REG 0x18 +#define UART_FR_BUSY_Pos 3 +#define UART_FR_BUSY_Msk (1UL << UART_FR_BUSY_Pos) + +#define UART_FR_RXFE_Pos 4 +#define UART_FR_RXFE_Msk (1UL << UART_FR_RXFE_Pos) + +#define UART_FR_TXFF_Pos 5 +#define UART_FR_TXFF_Msk (1UL << UART_FR_TXFF_Pos) + +#define UART_FR_TXFE_Pos 7 +#define UART_FR_TXFE_Msk (1UL << UART_FR_TXFE_Pos) + +/* BAUD_INTEGER: 16-bit DIVINT */ +#define UART_IBRD_REG 0x24 +#define UART_IBRD_Msk WHAL_BITMASK(16) + +/* BAUD_FRACT: 6-bit DIVFRAC */ +#define UART_FBRD_REG 0x28 +#define UART_FBRD_Msk WHAL_BITMASK(6) + +/* LINE_CTRL: bits 7:0 are used, the rest is reserved. */ +#define UART_LCRH_REG 0x2C +#define UART_LCRH_Msk WHAL_BITMASK(8) + +/* CTRL */ +#define UART_CR_REG 0x30 +#define UART_CR_UARTEN_Pos 0 +#define UART_CR_UARTEN_Msk (1UL << UART_CR_UARTEN_Pos) + +#define UART_CR_TXE_Pos 8 +#define UART_CR_TXE_Msk (1UL << UART_CR_TXE_Pos) + +#define UART_CR_RXE_Pos 9 +#define UART_CR_RXE_Msk (1UL << UART_CR_RXE_Pos) + +#ifdef WHAL_CFG_PL011_UART_DIRECT_API_MAPPING +#define whal_Pl011_Uart_Init whal_Uart_Init +#define whal_Pl011_Uart_Deinit whal_Uart_Deinit +#define whal_Pl011_Uart_Send whal_Uart_Send +#define whal_Pl011_Uart_Recv whal_Uart_Recv +#define whal_Pl011_Uart_SendAsync whal_Uart_SendAsync +#define whal_Pl011_Uart_RecvAsync whal_Uart_RecvAsync +#endif /* WHAL_CFG_PL011_UART_DIRECT_API_MAPPING */ + +#ifdef WHAL_CFG_PL011_UART_SINGLE_INSTANCE +const whal_Uart whal_Pl011_Uart_Dev = WHAL_CFG_PL011_UART_DEV; +#endif + +whal_Error whal_Pl011_Uart_Init(whal_Uart *uartDev) +{ + whal_Error err; +#ifdef WHAL_CFG_PL011_UART_SINGLE_INSTANCE + const whal_Pl011_Uart_Cfg *cfg = + (const whal_Pl011_Uart_Cfg *)whal_Pl011_Uart_Dev.cfg; + uintptr_t base = whal_Pl011_Uart_Dev.base; + (void)uartDev; +#else + whal_Pl011_Uart_Cfg *cfg; + uintptr_t base; + + if (!uartDev || !uartDev->cfg) { + return WHAL_EINVAL; + } + + base = uartDev->base; + cfg = (whal_Pl011_Uart_Cfg *)uartDev->cfg; +#endif + + /* DIVINT is 16 bits and must not be 0; DIVFRAC is 6 bits + * (AM026 ch. 63 p670). */ + if (cfg->ibrd == 0 || cfg->ibrd > UART_IBRD_Msk || + cfg->fbrd > UART_FBRD_Msk) { + return WHAL_EINVAL; + } + + /* Turn the UART off and let the last byte go out before changing the + * setup (AM026 ch. 63 p669). */ + whal_Reg32_Write(base, UART_CR_REG, 0); + err = whal_Reg32_ReadPoll(base, UART_FR_REG, UART_FR_BUSY_Msk, 0, + cfg->timeout); + if (err) { + return err; + } + + whal_Reg32_Write(base, UART_IBRD_REG, cfg->ibrd); + whal_Reg32_Write(base, UART_FBRD_REG, cfg->fbrd); + /* IBRD and FBRD only take effect on a LCR_H write, so LCR_H goes + * last (Arm PL011 TRM, UARTLCR_H). */ + whal_Reg32_Write(base, UART_LCRH_REG, cfg->lcrH & UART_LCRH_Msk); + whal_Reg32_Write(base, UART_CR_REG, + UART_CR_UARTEN_Msk | UART_CR_TXE_Msk | UART_CR_RXE_Msk); + + return WHAL_SUCCESS; +} + +whal_Error whal_Pl011_Uart_Deinit(whal_Uart *uartDev) +{ + whal_Error err; +#ifdef WHAL_CFG_PL011_UART_SINGLE_INSTANCE + const whal_Pl011_Uart_Cfg *cfg = + (const whal_Pl011_Uart_Cfg *)whal_Pl011_Uart_Dev.cfg; + uintptr_t base = whal_Pl011_Uart_Dev.base; + (void)uartDev; +#else + whal_Pl011_Uart_Cfg *cfg; + uintptr_t base; + + if (!uartDev || !uartDev->cfg) { + return WHAL_EINVAL; + } + + base = uartDev->base; + cfg = (whal_Pl011_Uart_Cfg *)uartDev->cfg; +#endif + + /* Turn the UART off and let the last byte go out before clearing the + * divisors and the FIFOs (AM026 ch. 63 p669, Clear FIFO). */ + whal_Reg32_Write(base, UART_CR_REG, 0); + err = whal_Reg32_ReadPoll(base, UART_FR_REG, UART_FR_BUSY_Msk, 0, + cfg->timeout); + if (err) { + return err; + } + + whal_Reg32_Write(base, UART_IBRD_REG, 0); + whal_Reg32_Write(base, UART_FBRD_REG, 0); + /* The LCR_H write makes the cleared divisors take effect; FEN = 0 + * flushes the FIFOs. */ + whal_Reg32_Write(base, UART_LCRH_REG, 0); + + return WHAL_SUCCESS; +} + +whal_Error whal_Pl011_Uart_Send(whal_Uart *uartDev, const void *data, size_t dataSz) +{ + const uint8_t *buf = data; + whal_Error err; +#ifdef WHAL_CFG_PL011_UART_SINGLE_INSTANCE + const whal_Pl011_Uart_Cfg *cfg = + (const whal_Pl011_Uart_Cfg *)whal_Pl011_Uart_Dev.cfg; + uintptr_t base = whal_Pl011_Uart_Dev.base; + (void)uartDev; + + if (!data) { + return WHAL_EINVAL; + } +#else + uintptr_t base; + whal_Pl011_Uart_Cfg *cfg; + + if (!uartDev || !uartDev->cfg || !data) { + return WHAL_EINVAL; + } + + base = uartDev->base; + cfg = (whal_Pl011_Uart_Cfg *)uartDev->cfg; +#endif + + for (size_t i = 0; i < dataSz; ++i) { + /* Wait for room in the TX FIFO. */ + err = whal_Reg32_ReadPoll(base, UART_FR_REG, UART_FR_TXFF_Msk, 0, + cfg->timeout); + if (err) { + return err; + } + whal_Reg32_Write(base, UART_DR_REG, buf[i]); + } + + /* Wait until the FIFO is empty and the last stop bit is out + * (AM026 ch. 63 p668, BUSY). */ + err = whal_Reg32_ReadPoll(base, UART_FR_REG, UART_FR_TXFE_Msk, + UART_FR_TXFE_Msk, cfg->timeout); + if (err) { + return err; + } + err = whal_Reg32_ReadPoll(base, UART_FR_REG, UART_FR_BUSY_Msk, 0, + cfg->timeout); + if (err) { + return err; + } + + return WHAL_SUCCESS; +} + +whal_Error whal_Pl011_Uart_Recv(whal_Uart *uartDev, void *data, size_t dataSz) +{ + uint8_t *buf = data; + uint32_t dr; + whal_Error err; +#ifdef WHAL_CFG_PL011_UART_SINGLE_INSTANCE + const whal_Pl011_Uart_Cfg *cfg = + (const whal_Pl011_Uart_Cfg *)whal_Pl011_Uart_Dev.cfg; + uintptr_t base = whal_Pl011_Uart_Dev.base; + (void)uartDev; + + if (!data) { + return WHAL_EINVAL; + } +#else + uintptr_t base; + whal_Pl011_Uart_Cfg *cfg; + + if (!uartDev || !uartDev->cfg || !data) { + return WHAL_EINVAL; + } + + base = uartDev->base; + cfg = (whal_Pl011_Uart_Cfg *)uartDev->cfg; +#endif + + for (size_t i = 0; i < dataSz; ++i) { + /* Wait for a byte in the RX FIFO. */ + err = whal_Reg32_ReadPoll(base, UART_FR_REG, UART_FR_RXFE_Msk, 0, + cfg->timeout); + if (err) { + return err; + } + + /* One read: it takes the byte and its error flags off the FIFO. */ + dr = whal_Reg32_Read(base, UART_DR_REG); + if (dr & UART_DR_ERR_Msk) { + /* Clear the error flags; the value written does not matter + * (AM028 UART ERR_STAT_CLR). */ + whal_Reg32_Write(base, UART_ECR_REG, 0); + return WHAL_EHARDWARE; + } + + buf[i] = (uint8_t)(dr & UART_DR_DATA_Msk); + } + + return WHAL_SUCCESS; +} + +whal_Error whal_Pl011_Uart_SendAsync(whal_Uart *uartDev, const void *data, size_t dataSz) +{ + (void)dataSz; + if (!uartDev || !data) { + return WHAL_EINVAL; + } + return WHAL_ENOTSUP; +} + +whal_Error whal_Pl011_Uart_RecvAsync(whal_Uart *uartDev, void *data, size_t dataSz) +{ + (void)dataSz; + if (!uartDev || !data) { + return WHAL_EINVAL; + } + return WHAL_ENOTSUP; +} + +#ifndef WHAL_CFG_PL011_UART_DIRECT_API_MAPPING +const whal_UartDriver whal_Pl011_Uart_Driver = { + .Init = whal_Pl011_Uart_Init, + .Deinit = whal_Pl011_Uart_Deinit, + .Send = whal_Pl011_Uart_Send, + .Recv = whal_Pl011_Uart_Recv, + .SendAsync = whal_Pl011_Uart_SendAsync, + .RecvAsync = whal_Pl011_Uart_RecvAsync, +}; +#endif /* !WHAL_CFG_PL011_UART_DIRECT_API_MAPPING */ diff --git a/tests/README.md b/tests/README.md index 8cd7c016..e6f210fb 100644 --- a/tests/README.md +++ b/tests/README.md @@ -67,8 +67,9 @@ use `g_peripheralSensor[]`). ## Core Tests -Host-side unit tests (bitops, dispatch, endian, reg, timeout) live in `core/` -and build with the native compiler: +Host-side unit tests (bitops, dispatch, endian, reg, timeout, and the PL011 +UART driver against an emulated register block) live in `core/` and build +with the native compiler: ``` cd core && make && make run diff --git a/tests/core/Makefile b/tests/core/Makefile index 937ca2c0..b44fec0f 100644 --- a/tests/core/Makefile +++ b/tests/core/Makefile @@ -24,11 +24,13 @@ WHAL_DIR = $(CURDIR)/../.. INCLUDE = -I$(WHAL_DIR) CFLAGS += -Wall -Werror $(INCLUDE) -g3 -TEST_SRC = main.c test_bitops.c test_dispatch.c test_endian.c test_reg.c test_timeout.c +TEST_SRC = main.c test_bitops.c test_dispatch.c test_endian.c test_reg.c test_timeout.c \ + test_pl011_uart.c WHAL_SRC = $(WHAL_DIR)/src/reg.c \ $(WHAL_DIR)/src/gpio/gpio.c \ $(WHAL_DIR)/src/uart/uart.c \ + $(WHAL_DIR)/src/uart/pl011_uart.c \ $(WHAL_DIR)/src/flash/flash.c \ $(WHAL_DIR)/src/timer/timer.c \ $(WHAL_DIR)/src/spi/spi.c \ diff --git a/tests/core/main.c b/tests/core/main.c index 00db0c9a..a91287de 100644 --- a/tests/core/main.c +++ b/tests/core/main.c @@ -37,6 +37,7 @@ void whal_Test_Bitops(void); void whal_Test_Dispatch(void); void whal_Test_Endian(void); void whal_Test_Reg(void); +void whal_Test_Pl011_Uart(void); #ifndef WHAL_CFG_NO_TIMEOUT void whal_Test_Timeout(void); #endif @@ -51,6 +52,7 @@ int main(void) whal_Test_Dispatch(); whal_Test_Endian(); whal_Test_Reg(); + whal_Test_Pl011_Uart(); #ifndef WHAL_CFG_NO_TIMEOUT whal_Test_Timeout(); #endif diff --git a/tests/core/test_pl011_uart.c b/tests/core/test_pl011_uart.c new file mode 100644 index 00000000..008c764c --- /dev/null +++ b/tests/core/test_pl011_uart.c @@ -0,0 +1,515 @@ +/* test_pl011_uart.c + * + * Copyright (C) 2026 wolfSSL Inc. + * + * This file is part of wolfHAL. + * + * wolfHAL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfHAL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ + +#include +#include +#include +#include +#include +#include "../test.h" + +/* Runs the driver on registers in memory. There are no FIFOs, so each test + * sets the FR bits it needs. */ + +/* Register word index (offset / 4) */ +#define DR (0x00 / 4) +#define ECR (0x04 / 4) +#define FR (0x18 / 4) +#define IBRD (0x24 / 4) +#define FBRD (0x28 / 4) +#define LCRH (0x2C / 4) +#define CR (0x30 / 4) +#define NREGS (0x48 / 4) + +#define FR_BUSY (1UL << 3) +#define FR_RXFE (1UL << 4) +#define FR_TXFF (1UL << 5) +#define FR_TXFE (1UL << 7) + +#define CR_UARTEN (1UL << 0) +#define CR_TXE (1UL << 8) +#define CR_RXE (1UL << 9) +#define CR_CTSEN (1UL << 15) + +#define SENTINEL 0xA5A5A5A5UL + +static uint32_t g_regs[NREGS]; + +#ifndef WHAL_CFG_NO_TIMEOUT +/* Fake tick that moves on every call, so a stuck poll runs out. */ +#ifdef WHAL_CFG_64BIT_TICK +static uint64_t g_fakeTick; + +static uint64_t FakeTick(void) +{ + return g_fakeTick++; +} +#else +static uint32_t g_fakeTick; + +static uint32_t FakeTick(void) +{ + return g_fakeTick++; +} +#endif + +static whal_Timeout g_timeout = { + .timeoutTicks = 5, + .GetTick = FakeTick, +}; + +static whal_Timeout *timeout(void) +{ + return &g_timeout; +} +#else +static whal_Timeout *timeout(void) +{ + return NULL; +} +#endif + +static whal_Pl011_Uart_Cfg g_cfg; + +/* Reset the register block and the config to 100 MHz, 115200 8N1. */ +static void Reset(void) +{ + size_t i; + + for (i = 0; i < NREGS; i++) { + g_regs[i] = SENTINEL; + } + /* Idle: TX FIFO empty, RX FIFO empty, not busy */ + g_regs[FR] = FR_TXFE | FR_RXFE; + g_regs[CR] = 0; + + memset(&g_cfg, 0, sizeof(g_cfg)); + g_cfg.ibrd = WHAL_PL011_UART_IBRD(100000000, 115200); + g_cfg.fbrd = WHAL_PL011_UART_FBRD(100000000, 115200); + g_cfg.lcrH = WHAL_PL011_UART_LCRH_8N1_FIFO; + g_cfg.timeout = timeout(); +} + +#define MAKE_DEV(name) \ + whal_Uart name = { \ + .base = (size_t)g_regs, \ + .driver = WHAL_VERSAL2_UART_DRIVER, \ + .cfg = &g_cfg, \ + } + +static void Test_Pl011_Platform(void) +{ + WHAL_ASSERT_EQ(WHAL_VERSAL2_UART0_BASE, 0xF1920000); + WHAL_ASSERT_EQ(WHAL_VERSAL2_UART1_BASE, 0xF1930000); +} + +static void Test_Pl011_Divisors(void) +{ + /* 100 MHz: 3472.2 / 64 -> 54 + 16/64 */ + WHAL_ASSERT_EQ(WHAL_PL011_UART_IBRD(100000000, 115200), 54); + WHAL_ASSERT_EQ(WHAL_PL011_UART_FBRD(100000000, 115200), 16); + /* 125 MHz: 4340.3 -> 67 + 52/64 */ + WHAL_ASSERT_EQ(WHAL_PL011_UART_IBRD(125000000, 115200), 67); + WHAL_ASSERT_EQ(WHAL_PL011_UART_FBRD(125000000, 115200), 52); + /* 150 MHz: 5208.3 -> 81 + 24/64 */ + WHAL_ASSERT_EQ(WHAL_PL011_UART_IBRD(150000000, 115200), 81); + WHAL_ASSERT_EQ(WHAL_PL011_UART_FBRD(150000000, 115200), 24); + /* AM026 ch. 63 p670 example: 4 MHz, 230400 -> DIVINT 1, DIVFRAC 5 */ + WHAL_ASSERT_EQ(WHAL_PL011_UART_IBRD(4000000, 230400), 1); + WHAL_ASSERT_EQ(WHAL_PL011_UART_FBRD(4000000, 230400), 5); +} + +static void Test_Pl011_DivisorCarry(void) +{ + /* 319 * 4 / 10 = 127.6. The fraction rounds up to 64, so it carries: + * 2 + 0/64, not 1 + 64/64 or a cut-off 1 + 63/64. */ + WHAL_ASSERT_EQ(WHAL_PL011_UART_DIV64(319, 10), 128); + WHAL_ASSERT_EQ(WHAL_PL011_UART_IBRD(319, 10), 2); + WHAL_ASSERT_EQ(WHAL_PL011_UART_FBRD(319, 10), 0); + /* 127.4 rounds down */ + WHAL_ASSERT_EQ(WHAL_PL011_UART_DIV64(3185, 100), 127); +} + +static void Test_Pl011_LcrhDefault(void) +{ + WHAL_ASSERT_EQ(WHAL_PL011_UART_LCRH_8N1_FIFO, 0x70); +} + +static void Test_Pl011_Init(void) +{ + whal_Error err; + + Reset(); + MAKE_DEV(dev); + g_regs[CR] = CR_UARTEN | CR_CTSEN; + + err = whal_Uart_Init(&dev); + WHAL_ASSERT_EQ(err, WHAL_SUCCESS); + WHAL_ASSERT_EQ(g_regs[IBRD], 54); + WHAL_ASSERT_EQ(g_regs[FBRD], 16); + WHAL_ASSERT_EQ(g_regs[LCRH], 0x70); + /* Full CR write: flow control and other bits cleared */ + WHAL_ASSERT_EQ(g_regs[CR], CR_UARTEN | CR_TXE | CR_RXE); + /* Registers the driver does not own are left alone */ + WHAL_ASSERT_EQ(g_regs[DR], SENTINEL); + WHAL_ASSERT_EQ(g_regs[ECR], SENTINEL); +} + +static void Test_Pl011_InitLcrhMasked(void) +{ + whal_Error err; + + Reset(); + MAKE_DEV(dev); + g_cfg.lcrH = 0xFFFFFF00UL | WHAL_PL011_UART_LCRH_8N1_FIFO | + WHAL_PL011_UART_LCRH_PEN; + + err = whal_Uart_Init(&dev); + WHAL_ASSERT_EQ(err, WHAL_SUCCESS); + WHAL_ASSERT_EQ(g_regs[LCRH], 0x72); +} + +static void Test_Pl011_InitReprograms(void) +{ + whal_Error err; + + /* An earlier boot stage left the UART on with another setup: Init + * sets it up again from the configuration. */ + Reset(); + MAKE_DEV(dev); + g_regs[CR] = CR_UARTEN | CR_CTSEN | CR_TXE; + g_regs[IBRD] = 7; + g_regs[FBRD] = 3; + g_regs[LCRH] = 0x60; + + err = whal_Uart_Init(&dev); + WHAL_ASSERT_EQ(err, WHAL_SUCCESS); + WHAL_ASSERT_EQ(g_regs[IBRD], 54); + WHAL_ASSERT_EQ(g_regs[FBRD], 16); + WHAL_ASSERT_EQ(g_regs[LCRH], 0x70); + WHAL_ASSERT_EQ(g_regs[CR], CR_UARTEN | CR_TXE | CR_RXE); +} + +static void Test_Pl011_InitInvalidDivisors(void) +{ + whal_Error err; + + Reset(); + MAKE_DEV(dev); + g_regs[CR] = CR_UARTEN; + + g_cfg.ibrd = 0; + err = whal_Uart_Init(&dev); + WHAL_ASSERT_EQ(err, WHAL_EINVAL); + + g_cfg.ibrd = 0x10000; + err = whal_Uart_Init(&dev); + WHAL_ASSERT_EQ(err, WHAL_EINVAL); + + g_cfg.ibrd = 0xFFFF; + g_cfg.fbrd = 64; + err = whal_Uart_Init(&dev); + WHAL_ASSERT_EQ(err, WHAL_EINVAL); + + /* Nothing was touched */ + WHAL_ASSERT_EQ(g_regs[CR], CR_UARTEN); + WHAL_ASSERT_EQ(g_regs[IBRD], SENTINEL); + WHAL_ASSERT_EQ(g_regs[FBRD], SENTINEL); + WHAL_ASSERT_EQ(g_regs[LCRH], SENTINEL); + + /* The top of both ranges is fine */ + g_cfg.fbrd = 63; + err = whal_Uart_Init(&dev); + WHAL_ASSERT_EQ(err, WHAL_SUCCESS); + WHAL_ASSERT_EQ(g_regs[IBRD], 0xFFFF); + WHAL_ASSERT_EQ(g_regs[FBRD], 63); +} + +static void Test_Pl011_Deinit(void) +{ + whal_Error err; + + Reset(); + MAKE_DEV(dev); + err = whal_Uart_Init(&dev); + WHAL_ASSERT_EQ(err, WHAL_SUCCESS); + + err = whal_Uart_Deinit(&dev); + WHAL_ASSERT_EQ(err, WHAL_SUCCESS); + WHAL_ASSERT_EQ(g_regs[CR], 0); + WHAL_ASSERT_EQ(g_regs[IBRD], 0); + WHAL_ASSERT_EQ(g_regs[FBRD], 0); + WHAL_ASSERT_EQ(g_regs[LCRH], 0); +} + +static void Test_Pl011_Send(void) +{ + whal_Error err; + const uint8_t a = 'A'; + const uint8_t ab[2] = { 'A', 'B' }; + const uint8_t nl = '\n'; + + Reset(); + MAKE_DEV(dev); + g_regs[FR] = FR_TXFE; + + err = whal_Uart_Send(&dev, &a, 1); + WHAL_ASSERT_EQ(err, WHAL_SUCCESS); + WHAL_ASSERT_EQ(g_regs[DR], 'A'); + + /* The array keeps only the last byte written */ + err = whal_Uart_Send(&dev, ab, sizeof(ab)); + WHAL_ASSERT_EQ(err, WHAL_SUCCESS); + WHAL_ASSERT_EQ(g_regs[DR], 'B'); + + /* No '\n' -> "\r\n" in the driver */ + err = whal_Uart_Send(&dev, &nl, 1); + WHAL_ASSERT_EQ(err, WHAL_SUCCESS); + WHAL_ASSERT_EQ(g_regs[DR], '\n'); + + /* A 32-bit write: ECR next to DR is not touched */ + WHAL_ASSERT_EQ(g_regs[ECR], SENTINEL); + + /* Zero bytes is fine */ + g_regs[DR] = 0; + err = whal_Uart_Send(&dev, &a, 0); + WHAL_ASSERT_EQ(err, WHAL_SUCCESS); + WHAL_ASSERT_EQ(g_regs[DR], 0); +} + +static void Test_Pl011_Recv(void) +{ + whal_Error err; + uint8_t buf[2] = { 0, 0 }; + + Reset(); + MAKE_DEV(dev); + g_regs[FR] = FR_TXFE; + g_regs[DR] = 0x5A; + + err = whal_Uart_Recv(&dev, buf, 1); + WHAL_ASSERT_EQ(err, WHAL_SUCCESS); + WHAL_ASSERT_EQ(buf[0], 0x5A); + + g_regs[DR] = 0x33; + err = whal_Uart_Recv(&dev, buf, 2); + WHAL_ASSERT_EQ(err, WHAL_SUCCESS); + WHAL_ASSERT_EQ(buf[0], 0x33); + WHAL_ASSERT_EQ(buf[1], 0x33); + WHAL_ASSERT_EQ(g_regs[ECR], SENTINEL); +} + +static void Test_Pl011_RecvError(void) +{ + whal_Error err; + uint8_t buf[1]; + size_t bit; + + Reset(); + MAKE_DEV(dev); + g_regs[FR] = FR_TXFE; + + /* FE, PE, BE, OE are DR bits 8..11 */ + for (bit = 8; bit <= 11; bit++) { + buf[0] = 0; + g_regs[DR] = (1UL << bit) | 0x5A; + g_regs[ECR] = SENTINEL; + + err = whal_Uart_Recv(&dev, buf, 1); + WHAL_ASSERT_EQ(err, WHAL_EHARDWARE); + /* Bad byte dropped, error flags cleared through ECR */ + WHAL_ASSERT_EQ(buf[0], 0); + WHAL_ASSERT_EQ(g_regs[ECR], 0); + } +} + +static void Test_Pl011_NullArgs(void) +{ + whal_Error err; + uint8_t b = 0; + whal_Uart noCfg = { + .base = (size_t)g_regs, + .driver = &whal_Pl011_Uart_Driver, + .cfg = NULL, + }; + + Reset(); + MAKE_DEV(dev); + + err = whal_Pl011_Uart_Init(NULL); + WHAL_ASSERT_EQ(err, WHAL_EINVAL); + err = whal_Pl011_Uart_Init(&noCfg); + WHAL_ASSERT_EQ(err, WHAL_EINVAL); + err = whal_Pl011_Uart_Deinit(NULL); + WHAL_ASSERT_EQ(err, WHAL_EINVAL); + err = whal_Pl011_Uart_Deinit(&noCfg); + WHAL_ASSERT_EQ(err, WHAL_EINVAL); + err = whal_Pl011_Uart_Send(NULL, &b, 1); + WHAL_ASSERT_EQ(err, WHAL_EINVAL); + err = whal_Pl011_Uart_Send(&noCfg, &b, 1); + WHAL_ASSERT_EQ(err, WHAL_EINVAL); + err = whal_Pl011_Uart_Send(&dev, NULL, 1); + WHAL_ASSERT_EQ(err, WHAL_EINVAL); + err = whal_Pl011_Uart_Recv(NULL, &b, 1); + WHAL_ASSERT_EQ(err, WHAL_EINVAL); + err = whal_Pl011_Uart_Recv(&noCfg, &b, 1); + WHAL_ASSERT_EQ(err, WHAL_EINVAL); + err = whal_Pl011_Uart_Recv(&dev, NULL, 1); + WHAL_ASSERT_EQ(err, WHAL_EINVAL); + + /* No register was touched */ + WHAL_ASSERT_EQ(g_regs[CR], 0); + WHAL_ASSERT_EQ(g_regs[DR], SENTINEL); +} + +static void Test_Pl011_Async(void) +{ + whal_Error err; + uint8_t b = 0; + + Reset(); + MAKE_DEV(dev); + + err = whal_Uart_SendAsync(&dev, &b, 1); + WHAL_ASSERT_EQ(err, WHAL_ENOTSUP); + err = whal_Uart_RecvAsync(&dev, &b, 1); + WHAL_ASSERT_EQ(err, WHAL_ENOTSUP); + err = whal_Pl011_Uart_Driver.SendAsync(NULL, &b, 1); + WHAL_ASSERT_EQ(err, WHAL_EINVAL); + err = whal_Pl011_Uart_Driver.RecvAsync(&dev, NULL, 1); + WHAL_ASSERT_EQ(err, WHAL_EINVAL); +} + +#ifndef WHAL_CFG_NO_TIMEOUT +static void Test_Pl011_InitBusyTimeout(void) +{ + whal_Error err; + + Reset(); + MAKE_DEV(dev); + g_regs[CR] = CR_UARTEN; + g_regs[FR] = FR_BUSY; + + err = whal_Uart_Init(&dev); + WHAL_ASSERT_EQ(err, WHAL_ETIMEOUT); + /* Disabled first, divisors not written while busy */ + WHAL_ASSERT_EQ(g_regs[CR], 0); + WHAL_ASSERT_EQ(g_regs[IBRD], SENTINEL); + WHAL_ASSERT_EQ(g_regs[FBRD], SENTINEL); + WHAL_ASSERT_EQ(g_regs[LCRH], SENTINEL); +} + +static void Test_Pl011_DeinitBusyTimeout(void) +{ + whal_Error err; + + Reset(); + MAKE_DEV(dev); + err = whal_Uart_Init(&dev); + WHAL_ASSERT_EQ(err, WHAL_SUCCESS); + g_regs[FR] = FR_TXFE | FR_BUSY; + + err = whal_Uart_Deinit(&dev); + WHAL_ASSERT_EQ(err, WHAL_ETIMEOUT); + /* Disabled first, setup not cleared while the last byte goes out */ + WHAL_ASSERT_EQ(g_regs[CR], 0); + WHAL_ASSERT_EQ(g_regs[IBRD], g_cfg.ibrd); + WHAL_ASSERT_EQ(g_regs[FBRD], g_cfg.fbrd); + WHAL_ASSERT_EQ(g_regs[LCRH], g_cfg.lcrH); +} + +static void Test_Pl011_SendTxffTimeout(void) +{ + whal_Error err; + const uint8_t a = 'A'; + + Reset(); + MAKE_DEV(dev); + g_regs[DR] = 0; + g_regs[FR] = FR_TXFF; + + err = whal_Uart_Send(&dev, &a, 1); + WHAL_ASSERT_EQ(err, WHAL_ETIMEOUT); + /* FIFO full: the byte was not written */ + WHAL_ASSERT_EQ(g_regs[DR], 0); +} + +static void Test_Pl011_SendDrainTimeout(void) +{ + whal_Error err; + const uint8_t a = 'A'; + + /* TXFE never sets */ + Reset(); + MAKE_DEV(dev); + g_regs[FR] = 0; + err = whal_Uart_Send(&dev, &a, 1); + WHAL_ASSERT_EQ(err, WHAL_ETIMEOUT); + WHAL_ASSERT_EQ(g_regs[DR], 'A'); + + /* BUSY never clears */ + g_regs[FR] = FR_TXFE | FR_BUSY; + err = whal_Uart_Send(&dev, &a, 1); + WHAL_ASSERT_EQ(err, WHAL_ETIMEOUT); +} + +static void Test_Pl011_RecvTimeout(void) +{ + whal_Error err; + uint8_t buf[1] = { 0 }; + + Reset(); + MAKE_DEV(dev); + g_regs[FR] = FR_RXFE; + g_regs[DR] = 0x5A; + + err = whal_Uart_Recv(&dev, buf, 1); + WHAL_ASSERT_EQ(err, WHAL_ETIMEOUT); + WHAL_ASSERT_EQ(buf[0], 0); +} +#endif /* !WHAL_CFG_NO_TIMEOUT */ + +void whal_Test_Pl011_Uart(void) +{ + WHAL_TEST_SUITE_START("pl011_uart"); + WHAL_TEST(Test_Pl011_Platform); + WHAL_TEST(Test_Pl011_Divisors); + WHAL_TEST(Test_Pl011_DivisorCarry); + WHAL_TEST(Test_Pl011_LcrhDefault); + WHAL_TEST(Test_Pl011_Init); + WHAL_TEST(Test_Pl011_InitLcrhMasked); + WHAL_TEST(Test_Pl011_InitReprograms); + WHAL_TEST(Test_Pl011_InitInvalidDivisors); + WHAL_TEST(Test_Pl011_Deinit); + WHAL_TEST(Test_Pl011_Send); + WHAL_TEST(Test_Pl011_Recv); + WHAL_TEST(Test_Pl011_RecvError); + WHAL_TEST(Test_Pl011_NullArgs); + WHAL_TEST(Test_Pl011_Async); +#ifndef WHAL_CFG_NO_TIMEOUT + WHAL_TEST(Test_Pl011_InitBusyTimeout); + WHAL_TEST(Test_Pl011_DeinitBusyTimeout); + WHAL_TEST(Test_Pl011_SendTxffTimeout); + WHAL_TEST(Test_Pl011_SendDrainTimeout); + WHAL_TEST(Test_Pl011_RecvTimeout); +#endif + WHAL_TEST_SUITE_END(); +} diff --git a/wolfHAL/platform/amd/versal2.h b/wolfHAL/platform/amd/versal2.h new file mode 100644 index 00000000..45829288 --- /dev/null +++ b/wolfHAL/platform/amd/versal2.h @@ -0,0 +1,38 @@ +/* versal2.h + * + * Copyright (C) 2026 wolfSSL Inc. + * + * This file is part of wolfHAL. + * + * wolfHAL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfHAL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ + +#ifndef WHAL_VERSAL2_H +#define WHAL_VERSAL2_H + +#include + +/* + * @file versal2.h + * @brief Convenience initializers for AMD Versal Gen 2 (AI Edge Series + * Gen 2 / Prime Series Gen 2) device instances. + */ + +/* LPD UARTs, Arm PL011 (AM026 ch. 63; bases from AM028 UART module). */ +#define WHAL_VERSAL2_UART0_BASE 0xF1920000 +#define WHAL_VERSAL2_UART1_BASE 0xF1930000 +#define WHAL_VERSAL2_UART_DRIVER &whal_Pl011_Uart_Driver + +#endif /* WHAL_VERSAL2_H */ diff --git a/wolfHAL/uart/pl011_uart.h b/wolfHAL/uart/pl011_uart.h new file mode 100644 index 00000000..4ea2781a --- /dev/null +++ b/wolfHAL/uart/pl011_uart.h @@ -0,0 +1,157 @@ +/* pl011_uart.h + * + * Copyright (C) 2026 wolfSSL Inc. + * + * This file is part of wolfHAL. + * + * wolfHAL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfHAL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ + +#ifndef WHAL_PL011_UART_H +#define WHAL_PL011_UART_H + +#include +#include +#include +#include +/* + * @file pl011_uart.h + * @brief Arm PL011 UART driver — polled variant. + * + * Used on AMD Versal Gen 2 (AM026 ch. 63, register map in AM028 UART + * module). + */ + +/* + * @brief Baud divisor times 64, rounded: round(clk * 4 / baud). + * + * Divisor = clk / (16 * baud), 6-bit fraction (AM026 ch. 63 p670). A + * fraction that rounds up to 64 carries into the whole part. + */ +#define WHAL_PL011_UART_DIV64(clk, baud) \ + ((((uint64_t)(clk) * 8) / (baud) + 1) / 2) + +/* + * @brief Integer baud divisor (IBRD / BAUD_INTEGER) value. + */ +#define WHAL_PL011_UART_IBRD(clk, baud) \ + ((uint32_t)(WHAL_PL011_UART_DIV64(clk, baud) >> 6)) + +/* + * @brief Fractional baud divisor (FBRD / BAUD_FRACT) value. + */ +#define WHAL_PL011_UART_FBRD(clk, baud) \ + ((uint32_t)(WHAL_PL011_UART_DIV64(clk, baud) & 0x3F)) + +/* + * @brief LCR_H (LINE_CTRL) bits (AM028 UART LINE_CTRL). + */ +#define WHAL_PL011_UART_LCRH_PEN (1UL << 1) /* parity on */ +#define WHAL_PL011_UART_LCRH_EPS (1UL << 2) /* even parity */ +#define WHAL_PL011_UART_LCRH_STP2 (1UL << 3) /* two stop bits */ +#define WHAL_PL011_UART_LCRH_FEN (1UL << 4) /* FIFOs on */ +#define WHAL_PL011_UART_LCRH_WLEN_8 (3UL << 5) /* 8 data bits */ + +/* + * @brief Default LCR_H value: 8 data bits, no parity, 1 stop bit, FIFOs on. + */ +#define WHAL_PL011_UART_LCRH_8N1_FIFO \ + (WHAL_PL011_UART_LCRH_WLEN_8 | WHAL_PL011_UART_LCRH_FEN) + +/* Polled UART */ + +/* + * @brief Polled UART configuration. + * + * ibrd and fbrd are computed by the board, e.g. with + * WHAL_PL011_UART_IBRD(clk, baud) and WHAL_PL011_UART_FBRD(clk, baud). + */ +typedef struct whal_Pl011_Uart_Cfg { + uint32_t ibrd; + uint32_t fbrd; + uint32_t lcrH; + whal_Timeout *timeout; +} whal_Pl011_Uart_Cfg; + +/* + * @brief Single-instance device struct. Defined in the driver TU + * from the WHAL_CFG_PL011_UART_DEV initializer in wolfHAL_board.h. + */ +#ifdef WHAL_CFG_PL011_UART_SINGLE_INSTANCE +extern const whal_Uart whal_Pl011_Uart_Dev; +#endif + +#ifndef WHAL_CFG_PL011_UART_DIRECT_API_MAPPING +/* + * @brief Polled UART driver. Implements Init, Deinit, Send, Recv. + */ +extern const whal_UartDriver whal_Pl011_Uart_Driver; + +/* + * @brief Initialize the PL011 UART. + * + * @param uartDev UART device instance. + * + * @retval WHAL_SUCCESS Initialization completed. + * @retval WHAL_EINVAL Invalid arguments, or ibrd / fbrd out of range. + * @retval WHAL_ETIMEOUT The UART stayed busy. + */ +whal_Error whal_Pl011_Uart_Init(whal_Uart *uartDev); + +/* + * @brief Deinitialize the PL011 UART. + * + * @param uartDev UART device instance. + * + * Waits for the last byte to go out before clearing the setup. + * + * @retval WHAL_SUCCESS Deinit completed. + * @retval WHAL_EINVAL Invalid arguments. + * @retval WHAL_ETIMEOUT The UART stayed busy. + */ +whal_Error whal_Pl011_Uart_Deinit(whal_Uart *uartDev); + +/* + * @brief Transmit a buffer over UART (blocking, polled). + * + * Bytes are sent as they are; no '\n' to "\r\n" change is made. + * + * @param uartDev UART device instance. + * @param data Buffer to transmit. + * @param dataSz Number of bytes to transmit. + * + * @retval WHAL_SUCCESS All bytes transmitted. + * @retval WHAL_EINVAL Invalid arguments. + * @retval WHAL_ETIMEOUT The TX FIFO did not drain in time. + */ +whal_Error whal_Pl011_Uart_Send(whal_Uart *uartDev, const void *data, size_t dataSz); + +/* + * @brief Receive a buffer over UART (blocking, polled). + * + * @param uartDev UART device instance. + * @param data Receive buffer. + * @param dataSz Number of bytes to receive. + * + * @retval WHAL_SUCCESS All bytes received. + * @retval WHAL_EINVAL Invalid arguments. + * @retval WHAL_ETIMEOUT No byte came in time. + * @retval WHAL_EHARDWARE An overrun, break, parity or framing error was + * detected. The bad byte is dropped. + */ +whal_Error whal_Pl011_Uart_Recv(whal_Uart *uartDev, void *data, size_t dataSz); +#endif /* !WHAL_CFG_PL011_UART_DIRECT_API_MAPPING */ + +#endif /* WHAL_PL011_UART_H */