diff --git a/src/cmd/compile/internal/amd64/ssa.go b/src/cmd/compile/internal/amd64/ssa.go index 1b8f8d4751b5a0..806d8a1ce1c8fd 100644 --- a/src/cmd/compile/internal/amd64/ssa.go +++ b/src/cmd/compile/internal/amd64/ssa.go @@ -2165,7 +2165,7 @@ func simdVgpvImm8(s *ssagen.State, v *ssa.Value) *obj.Prog { } func simdVgpvImm(s *ssagen.State, v *ssa.Value) *obj.Prog { // within simdgen, the choice of intrinsic shape and the output - // intruction format are linked. In the case of VgpImm, there is + // instruction format are linked. In the case of VgpImm, there is // a difference in the intrinsic, but no difference in the // instruction, it is just like VgpvImm8. // @@ -2276,7 +2276,7 @@ func simdVgpImm8(s *ssagen.State, v *ssa.Value) *obj.Prog { func simdVgpImm(s *ssagen.State, v *ssa.Value) *obj.Prog { // within simdgen, the choice of intrinsic shape and the output - // intruction format are linked. In the case of VgpImm, there is + // instruction format are linked. In the case of VgpImm, there is // a difference in the intrinsic, but no difference in the // instruction, it is just like VgpImm8. return simdVgpImm8(s, v) diff --git a/src/cmd/compile/internal/arm64/simdssa_sve.go b/src/cmd/compile/internal/arm64/simdssa_sve.go index 5f184b09c94965..a2b9ff30e2a30f 100644 --- a/src/cmd/compile/internal/arm64/simdssa_sve.go +++ b/src/cmd/compile/internal/arm64/simdssa_sve.go @@ -13,82 +13,217 @@ import ( func ssaGenSIMDSVEValue(s *ssagen.State, v *ssa.Value) bool { var p *obj.Prog switch v.Op { + case ssaop.OpARM64ZABSB, + ssaop.OpARM64ZNEGB: + p = simdZkv(s, v, arm64.ARNG_B) + + case ssaop.OpARM64ZFABSD, + ssaop.OpARM64ZABSD, + ssaop.OpARM64ZFRINTPD, + ssaop.OpARM64ZFRINTMD, + ssaop.OpARM64ZFNEGD, + ssaop.OpARM64ZNEGD, + ssaop.OpARM64ZFRINTND, + ssaop.OpARM64ZFSQRTD, + ssaop.OpARM64ZFRINTZD: + p = simdZkv(s, v, arm64.ARNG_D) + + case ssaop.OpARM64ZABSH, + ssaop.OpARM64ZNEGH: + p = simdZkv(s, v, arm64.ARNG_H) + + case ssaop.OpARM64ZFABSS, + ssaop.OpARM64ZABSS, + ssaop.OpARM64ZFRINTPS, + ssaop.OpARM64ZFRINTMS, + ssaop.OpARM64ZFNEGS, + ssaop.OpARM64ZNEGS, + ssaop.OpARM64ZFRINTNS, + ssaop.OpARM64ZFSQRTS, + ssaop.OpARM64ZFRINTZS: + p = simdZkv(s, v, arm64.ARNG_S) + case ssaop.OpARM64ZADDB, ssaop.OpARM64ZSQADDB, - ssaop.OpARM64ZUQADDB: + ssaop.OpARM64ZUQADDB, + ssaop.OpARM64ZSUBB, + ssaop.OpARM64ZSQSUBB, + ssaop.OpARM64ZUQSUBB: p = simdZ21(s, v, arm64.ARNG_B) case ssaop.OpARM64ZFADDD, ssaop.OpARM64ZADDD, ssaop.OpARM64ZSQADDD, - ssaop.OpARM64ZUQADDD: + ssaop.OpARM64ZUQADDD, + ssaop.OpARM64ZANDD, + ssaop.OpARM64ZORRD, + ssaop.OpARM64ZFSUBD, + ssaop.OpARM64ZSUBD, + ssaop.OpARM64ZSQSUBD, + ssaop.OpARM64ZUQSUBD, + ssaop.OpARM64ZEORD: p = simdZ21(s, v, arm64.ARNG_D) case ssaop.OpARM64ZADDH, ssaop.OpARM64ZSQADDH, - ssaop.OpARM64ZUQADDH: + ssaop.OpARM64ZUQADDH, + ssaop.OpARM64ZSUBH, + ssaop.OpARM64ZSQSUBH, + ssaop.OpARM64ZUQSUBH: p = simdZ21(s, v, arm64.ARNG_H) case ssaop.OpARM64ZFADDS, ssaop.OpARM64ZADDS, ssaop.OpARM64ZSQADDS, - ssaop.OpARM64ZUQADDS: + ssaop.OpARM64ZUQADDS, + ssaop.OpARM64ZFSUBS, + ssaop.OpARM64ZSUBS, + ssaop.OpARM64ZSQSUBS, + ssaop.OpARM64ZUQSUBS: p = simdZ21(s, v, arm64.ARNG_S) - case ssaop.OpARM64ZCMPGTB: + case ssaop.OpARM64ZCMPEQB, + ssaop.OpARM64ZCMPGTB, + ssaop.OpARM64ZCMPHIB, + ssaop.OpARM64ZCMPGEB, + ssaop.OpARM64ZCMPHSB, + ssaop.OpARM64ZCMPNEB: p = simdZ2kk(s, v, arm64.ARNG_B) - case ssaop.OpARM64ZCMPGTD: + case ssaop.OpARM64ZFCMEQD, + ssaop.OpARM64ZCMPEQD, + ssaop.OpARM64ZFCMGTD, + ssaop.OpARM64ZCMPGTD, + ssaop.OpARM64ZCMPHID, + ssaop.OpARM64ZFCMGED, + ssaop.OpARM64ZCMPGED, + ssaop.OpARM64ZCMPHSD, + ssaop.OpARM64ZFCMNED, + ssaop.OpARM64ZCMPNED: p = simdZ2kk(s, v, arm64.ARNG_D) - case ssaop.OpARM64ZCMPGTH: + case ssaop.OpARM64ZCMPEQH, + ssaop.OpARM64ZCMPGTH, + ssaop.OpARM64ZCMPHIH, + ssaop.OpARM64ZCMPGEH, + ssaop.OpARM64ZCMPHSH, + ssaop.OpARM64ZCMPNEH: p = simdZ2kk(s, v, arm64.ARNG_H) - case ssaop.OpARM64ZCMPGTS: + case ssaop.OpARM64ZFCMEQS, + ssaop.OpARM64ZCMPEQS, + ssaop.OpARM64ZFCMGTS, + ssaop.OpARM64ZCMPGTS, + ssaop.OpARM64ZCMPHIS, + ssaop.OpARM64ZFCMGES, + ssaop.OpARM64ZCMPGES, + ssaop.OpARM64ZCMPHSS, + ssaop.OpARM64ZFCMNES, + ssaop.OpARM64ZCMPNES: p = simdZ2kk(s, v, arm64.ARNG_S) case ssaop.OpARM64ZADDMergingB, ssaop.OpARM64ZSQADDMergingB, - ssaop.OpARM64ZUQADDMergingB: + ssaop.OpARM64ZUQADDMergingB, + ssaop.OpARM64ZANDMergingB, + ssaop.OpARM64ZORRMergingB, + ssaop.OpARM64ZSUBMergingB, + ssaop.OpARM64ZSQSUBMergingB, + ssaop.OpARM64ZUQSUBMergingB, + ssaop.OpARM64ZEORMergingB: p = simdZ2kvPred(s, v, arm64.ARNG_B) case ssaop.OpARM64ZFADDMergingD, ssaop.OpARM64ZADDMergingD, ssaop.OpARM64ZSQADDMergingD, - ssaop.OpARM64ZUQADDMergingD: + ssaop.OpARM64ZUQADDMergingD, + ssaop.OpARM64ZANDMergingD, + ssaop.OpARM64ZORRMergingD, + ssaop.OpARM64ZFSUBMergingD, + ssaop.OpARM64ZSUBMergingD, + ssaop.OpARM64ZSQSUBMergingD, + ssaop.OpARM64ZUQSUBMergingD, + ssaop.OpARM64ZEORMergingD: p = simdZ2kvPred(s, v, arm64.ARNG_D) case ssaop.OpARM64ZADDMergingH, ssaop.OpARM64ZSQADDMergingH, - ssaop.OpARM64ZUQADDMergingH: + ssaop.OpARM64ZUQADDMergingH, + ssaop.OpARM64ZANDMergingH, + ssaop.OpARM64ZORRMergingH, + ssaop.OpARM64ZSUBMergingH, + ssaop.OpARM64ZSQSUBMergingH, + ssaop.OpARM64ZUQSUBMergingH, + ssaop.OpARM64ZEORMergingH: p = simdZ2kvPred(s, v, arm64.ARNG_H) case ssaop.OpARM64ZFADDMergingS, ssaop.OpARM64ZADDMergingS, ssaop.OpARM64ZSQADDMergingS, - ssaop.OpARM64ZUQADDMergingS: + ssaop.OpARM64ZUQADDMergingS, + ssaop.OpARM64ZANDMergingS, + ssaop.OpARM64ZORRMergingS, + ssaop.OpARM64ZFSUBMergingS, + ssaop.OpARM64ZSUBMergingS, + ssaop.OpARM64ZSQSUBMergingS, + ssaop.OpARM64ZUQSUBMergingS, + ssaop.OpARM64ZEORMergingS: p = simdZ2kvPred(s, v, arm64.ARNG_S) + case ssaop.OpARM64ZABSMergingB, + ssaop.OpARM64ZNEGMergingB: + p = simdZ2kvPredResultInArg0(s, v, arm64.ARNG_B) + + case ssaop.OpARM64ZFABSMergingD, + ssaop.OpARM64ZABSMergingD, + ssaop.OpARM64ZFNEGMergingD, + ssaop.OpARM64ZNEGMergingD, + ssaop.OpARM64ZFSQRTMergingD: + p = simdZ2kvPredResultInArg0(s, v, arm64.ARNG_D) + + case ssaop.OpARM64ZABSMergingH, + ssaop.OpARM64ZNEGMergingH: + p = simdZ2kvPredResultInArg0(s, v, arm64.ARNG_H) + + case ssaop.OpARM64ZFABSMergingS, + ssaop.OpARM64ZABSMergingS, + ssaop.OpARM64ZFNEGMergingS, + ssaop.OpARM64ZNEGMergingS, + ssaop.OpARM64ZFSQRTMergingS: + p = simdZ2kvPredResultInArg0(s, v, arm64.ARNG_S) + case ssaop.OpARM64ZADDMergingPrefixedB, ssaop.OpARM64ZSQADDMergingPrefixedB, - ssaop.OpARM64ZUQADDMergingPrefixedB: + ssaop.OpARM64ZUQADDMergingPrefixedB, + ssaop.OpARM64ZANDMergingPrefixedB, + ssaop.OpARM64ZORRMergingPrefixedB, + ssaop.OpARM64ZEORMergingPrefixedB: p = simdZ3kvPredResultInArg0(s, v, arm64.ARNG_B) case ssaop.OpARM64ZFADDMergingPrefixedD, ssaop.OpARM64ZADDMergingPrefixedD, ssaop.OpARM64ZSQADDMergingPrefixedD, - ssaop.OpARM64ZUQADDMergingPrefixedD: + ssaop.OpARM64ZUQADDMergingPrefixedD, + ssaop.OpARM64ZANDMergingPrefixedD, + ssaop.OpARM64ZORRMergingPrefixedD, + ssaop.OpARM64ZEORMergingPrefixedD: p = simdZ3kvPredResultInArg0(s, v, arm64.ARNG_D) case ssaop.OpARM64ZADDMergingPrefixedH, ssaop.OpARM64ZSQADDMergingPrefixedH, - ssaop.OpARM64ZUQADDMergingPrefixedH: + ssaop.OpARM64ZUQADDMergingPrefixedH, + ssaop.OpARM64ZANDMergingPrefixedH, + ssaop.OpARM64ZORRMergingPrefixedH, + ssaop.OpARM64ZEORMergingPrefixedH: p = simdZ3kvPredResultInArg0(s, v, arm64.ARNG_H) case ssaop.OpARM64ZFADDMergingPrefixedS, ssaop.OpARM64ZADDMergingPrefixedS, ssaop.OpARM64ZSQADDMergingPrefixedS, - ssaop.OpARM64ZUQADDMergingPrefixedS: + ssaop.OpARM64ZUQADDMergingPrefixedS, + ssaop.OpARM64ZANDMergingPrefixedS, + ssaop.OpARM64ZORRMergingPrefixedS, + ssaop.OpARM64ZEORMergingPrefixedS: p = simdZ3kvPredResultInArg0(s, v, arm64.ARNG_S) default: diff --git a/src/cmd/compile/internal/arm64/ssa.go b/src/cmd/compile/internal/arm64/ssa.go index 70fc8f60d7d3f2..9e32e0479115aa 100644 --- a/src/cmd/compile/internal/arm64/ssa.go +++ b/src/cmd/compile/internal/arm64/ssa.go @@ -2163,6 +2163,12 @@ func simdZ2kvPred(s *ssagen.State, v *ssa.Value, arng int16) *obj.Prog { switch d { case x: case y: + // Only reachable for a commutative operation: a non-commutative one is + // marked resultInArg0, which pins the destination to arg0. Swapping the + // sources of one would compute y-x where x-y was asked for. + if v.Op.ResultInArg0() { + v.Fatalf("destination is arg1 of resultInArg0 op %v", v.Op) + } x, y = y, x default: mp := s.Prog(arm64.AZMOVPRFX) @@ -2181,6 +2187,35 @@ func simdZ2kvPred(s *ssagen.State, v *ssa.Value, arng int16) *obj.Prog { return p } +// simdZkv emits a predicated-only SVE unary operation standing in for an +// unpredicated one, e.g. ZABS Z0.B, P0.M, Z1.B. SSA provides arg0=x and +// arg1=the governing predicate, which the lowering rule synthesized as +// all-true. With every lane active, merging predication leaves nothing of the +// destination behind, so the operation is unpredicated in effect. +func simdZkv(s *ssagen.State, v *ssa.Value, arng int16) *obj.Prog { + return sveUnaryPred(s, v, arng, v.Args[0].Reg(), v.Args[1].Reg(), arm64.PRED_M) +} + +// simdZ2kvPredResultInArg0 emits the merging form of a predicated SVE unary +// operation, e.g. ZABS Z1.B, P0.M, Z0.B. SSA provides arg0=the value the +// inactive lanes keep, arg1=x, arg2=mask, and resultInArg0 puts that value in +// the destination. The instruction is constructive -- it names its destination +// apart from its source -- so merging into that destination needs no MOVPRFX. +func simdZ2kvPredResultInArg0(s *ssagen.State, v *ssa.Value, arng int16) *obj.Prog { + return sveUnaryPred(s, v, arng, v.Args[1].Reg(), v.Args[2].Reg(), arm64.PRED_M) +} + +// sveUnaryPred emits a predicated SVE unary operation: OP Zn.T, Pg/, Zd.T. +func sveUnaryPred(s *ssagen.State, v *ssa.Value, arng int16, zn, pg int16, qual int16) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = zregArng(zn, arng) // Zn + p.AddRestSourceReg(pregMask(pg, qual)) // Pg/M or Pg/Z + p.To.Type = obj.TYPE_REG + p.To.Reg = zregArng(v.Reg(), arng) // Zd + return p +} + // simdZ3kvPredResultInArg0 emits an SVE merging-predicated binary operation // whose inactive lanes come from a value that is neither of its sources, e.g. // x.Add(y).IfElse(mask, z). SSA provides arg0=z, arg1=x, arg2=y, arg3=mask, and diff --git a/src/cmd/compile/internal/ir/expr.go b/src/cmd/compile/internal/ir/expr.go index 155a3a77bdaaad..55ae5b92ed5516 100644 --- a/src/cmd/compile/internal/ir/expr.go +++ b/src/cmd/compile/internal/ir/expr.go @@ -1212,28 +1212,15 @@ func promotedWrapperSym(wrapper, wrappee *types.Type, msym *types.Sym, offset in recvMode = "n" } - rsym := wrapper.Sym() - if wrapper.IsPtr() { - if rsym != nil { - base.Fatalf("declared pointer receiver type: %v", wrapper) - } - rsym = wrapper.Elem().Sym() - } - rpkg := Pkgs.Go - if rsym != nil { - rpkg = rsym.Pkg - } + wrappeeMethod := ReceiverMethodSym(wrappee, msym) var b bytes.Buffer - fmt.Fprintf(&b, ".embed.%-S.", wrappee) - if !types.IsExported(msym.Name) { - b.WriteString(msym.Pkg.Prefix) - b.WriteString(".") - } - b.WriteString(msym.Name) - fmt.Fprintf(&b, ".%d%s.%d", derefs, recvMode, offset) + fmt.Fprintf(&b, ".embed.%d%s.%d.", derefs, recvMode, offset) + b.WriteString(wrappeeMethod.Pkg.Prefix) + b.WriteString(".") + b.WriteString(wrappeeMethod.Name) - sym := rpkg.LookupBytes(b.Bytes()) + sym := wrappeeMethod.Pkg.LookupBytes(b.Bytes()) sym.SetFunc(true) return sym } diff --git a/src/cmd/compile/internal/ssa/_gen/ARM64Ops.go b/src/cmd/compile/internal/ssa/_gen/ARM64Ops.go index e0033283c13b45..f53e48bf160b06 100644 --- a/src/cmd/compile/internal/ssa/_gen/ARM64Ops.go +++ b/src/cmd/compile/internal/ssa/_gen/ARM64Ops.go @@ -203,6 +203,7 @@ func init() { fp31 = regInfo{inputs: []regMask{fp, fp, fp}, outputs: []regMask{fp}} fp2flags = regInfo{inputs: []regMask{fp, fp}} fp1flags = regInfo{inputs: []regMask{fp}} + fp1predfp = regInfo{inputs: []regMask{fp, pred}, outputs: []regMask{fp}} fp2predpred = regInfo{inputs: []regMask{fp, fp, pred}, outputs: []regMask{pred}} fp2predfp = regInfo{inputs: []regMask{fp, fp, pred}, outputs: []regMask{fp}} fp3predfp = regInfo{inputs: []regMask{fp, fp, fp, pred}, outputs: []regMask{fp}} @@ -902,7 +903,7 @@ func init() { pkg: "cmd/internal/obj/arm64", genfile: "../../arm64/ssa.go", genSIMDfile: "../../arm64/simdssa.go ../../arm64/simdssa_sve.go", - ops: append(append(ops, simdARM64Ops(fp11, fp21, fp31, fpgp, fpgpfp, fp21)...), simdARM64SVEOps(fp11, fp21, fp2predpred, fp2predfp, fp2predfp, fp3predfp)...), + ops: append(append(ops, simdARM64Ops(fp11, fp21, fp31, fpgp, fpgpfp, fp21)...), simdARM64SVEOps(fp11, fp21, fp1predfp, fp2predpred, fp2predfp, fp2predfp, fp3predfp)...), blocks: blocks, regnames: regNamesARM64, ParamIntRegNames: "R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15", diff --git a/src/cmd/compile/internal/ssa/_gen/MIPS64.rules b/src/cmd/compile/internal/ssa/_gen/MIPS64.rules index f830065f96d470..01850ea07f44e4 100644 --- a/src/cmd/compile/internal/ssa/_gen/MIPS64.rules +++ b/src/cmd/compile/internal/ssa/_gen/MIPS64.rules @@ -59,65 +59,84 @@ // shifts // hardware instruction uses only the low 6 bits of the shift // we compare to 64 to ensure Go semantics for large shifts -(Lsh64x64 x y) => (AND (NEGV (SGTU (MOVVconst [64]) y)) (SLLV x y)) -(Lsh64x32 x y) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt32to64 y))) (SLLV x (ZeroExt32to64 y))) -(Lsh64x16 x y) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt16to64 y))) (SLLV x (ZeroExt16to64 y))) -(Lsh64x8 x y) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt8to64 y))) (SLLV x (ZeroExt8to64 y))) - -(Lsh32x64 x y) => (AND (NEGV (SGTU (MOVVconst [64]) y)) (SLLV x y)) -(Lsh32x32 x y) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt32to64 y))) (SLLV x (ZeroExt32to64 y))) -(Lsh32x16 x y) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt16to64 y))) (SLLV x (ZeroExt16to64 y))) -(Lsh32x8 x y) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt8to64 y))) (SLLV x (ZeroExt8to64 y))) - -(Lsh16x64 x y) => (AND (NEGV (SGTU (MOVVconst [64]) y)) (SLLV x y)) -(Lsh16x32 x y) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt32to64 y))) (SLLV x (ZeroExt32to64 y))) -(Lsh16x16 x y) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt16to64 y))) (SLLV x (ZeroExt16to64 y))) -(Lsh16x8 x y) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt8to64 y))) (SLLV x (ZeroExt8to64 y))) - -(Lsh8x64 x y) => (AND (NEGV (SGTU (MOVVconst [64]) y)) (SLLV x y)) -(Lsh8x32 x y) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt32to64 y))) (SLLV x (ZeroExt32to64 y))) -(Lsh8x16 x y) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt16to64 y))) (SLLV x (ZeroExt16to64 y))) -(Lsh8x8 x y) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt8to64 y))) (SLLV x (ZeroExt8to64 y))) - -(Rsh64Ux64 x y) => (AND (NEGV (SGTU (MOVVconst [64]) y)) (SRLV x y)) -(Rsh64Ux32 x y) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt32to64 y))) (SRLV x (ZeroExt32to64 y))) -(Rsh64Ux16 x y) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt16to64 y))) (SRLV x (ZeroExt16to64 y))) -(Rsh64Ux8 x y) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt8to64 y))) (SRLV x (ZeroExt8to64 y))) - -(Rsh32Ux64 x y) => (AND (NEGV (SGTU (MOVVconst [64]) y)) (SRLV (ZeroExt32to64 x) y)) -(Rsh32Ux32 x y) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt32to64 y))) (SRLV (ZeroExt32to64 x) (ZeroExt32to64 y))) -(Rsh32Ux16 x y) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt16to64 y))) (SRLV (ZeroExt32to64 x) (ZeroExt16to64 y))) -(Rsh32Ux8 x y) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt8to64 y))) (SRLV (ZeroExt32to64 x) (ZeroExt8to64 y))) - -(Rsh16Ux64 x y) => (AND (NEGV (SGTU (MOVVconst [64]) y)) (SRLV (ZeroExt16to64 x) y)) -(Rsh16Ux32 x y) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt32to64 y))) (SRLV (ZeroExt16to64 x) (ZeroExt32to64 y))) -(Rsh16Ux16 x y) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt16to64 y))) (SRLV (ZeroExt16to64 x) (ZeroExt16to64 y))) -(Rsh16Ux8 x y) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt8to64 y))) (SRLV (ZeroExt16to64 x) (ZeroExt8to64 y))) - -(Rsh8Ux64 x y) => (AND (NEGV (SGTU (MOVVconst [64]) y)) (SRLV (ZeroExt8to64 x) y)) -(Rsh8Ux32 x y) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt32to64 y))) (SRLV (ZeroExt8to64 x) (ZeroExt32to64 y))) -(Rsh8Ux16 x y) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt16to64 y))) (SRLV (ZeroExt8to64 x) (ZeroExt16to64 y))) -(Rsh8Ux8 x y) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt8to64 y))) (SRLV (ZeroExt8to64 x) (ZeroExt8to64 y))) - -(Rsh64x64 x y) => (SRAV x (OR (NEGV (SGTU y (MOVVconst [63]))) y)) -(Rsh64x32 x y) => (SRAV x (OR (NEGV (SGTU (ZeroExt32to64 y) (MOVVconst [63]))) (ZeroExt32to64 y))) -(Rsh64x16 x y) => (SRAV x (OR (NEGV (SGTU (ZeroExt16to64 y) (MOVVconst [63]))) (ZeroExt16to64 y))) -(Rsh64x8 x y) => (SRAV x (OR (NEGV (SGTU (ZeroExt8to64 y) (MOVVconst [63]))) (ZeroExt8to64 y))) - -(Rsh32x64 x y) => (SRAV (SignExt32to64 x) (OR (NEGV (SGTU y (MOVVconst [63]))) y)) -(Rsh32x32 x y) => (SRAV (SignExt32to64 x) (OR (NEGV (SGTU (ZeroExt32to64 y) (MOVVconst [63]))) (ZeroExt32to64 y))) -(Rsh32x16 x y) => (SRAV (SignExt32to64 x) (OR (NEGV (SGTU (ZeroExt16to64 y) (MOVVconst [63]))) (ZeroExt16to64 y))) -(Rsh32x8 x y) => (SRAV (SignExt32to64 x) (OR (NEGV (SGTU (ZeroExt8to64 y) (MOVVconst [63]))) (ZeroExt8to64 y))) - -(Rsh16x64 x y) => (SRAV (SignExt16to64 x) (OR (NEGV (SGTU y (MOVVconst [63]))) y)) -(Rsh16x32 x y) => (SRAV (SignExt16to64 x) (OR (NEGV (SGTU (ZeroExt32to64 y) (MOVVconst [63]))) (ZeroExt32to64 y))) -(Rsh16x16 x y) => (SRAV (SignExt16to64 x) (OR (NEGV (SGTU (ZeroExt16to64 y) (MOVVconst [63]))) (ZeroExt16to64 y))) -(Rsh16x8 x y) => (SRAV (SignExt16to64 x) (OR (NEGV (SGTU (ZeroExt8to64 y) (MOVVconst [63]))) (ZeroExt8to64 y))) - -(Rsh8x64 x y) => (SRAV (SignExt8to64 x) (OR (NEGV (SGTU y (MOVVconst [63]))) y)) -(Rsh8x32 x y) => (SRAV (SignExt8to64 x) (OR (NEGV (SGTU (ZeroExt32to64 y) (MOVVconst [63]))) (ZeroExt32to64 y))) -(Rsh8x16 x y) => (SRAV (SignExt8to64 x) (OR (NEGV (SGTU (ZeroExt16to64 y) (MOVVconst [63]))) (ZeroExt16to64 y))) -(Rsh8x8 x y) => (SRAV (SignExt8to64 x) (OR (NEGV (SGTU (ZeroExt8to64 y) (MOVVconst [63]))) (ZeroExt8to64 y))) + +// left shift +(Lsh64x(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SLLV x y) +(Lsh32x(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SLLV x y) +(Lsh16x(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SLLV x y) +(Lsh8x(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SLLV x y) + +(Lsh64x64 x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV (SGTU (MOVVconst [64]) y)) (SLLV x y)) +(Lsh64x32 x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt32to64 y))) (SLLV x (ZeroExt32to64 y))) +(Lsh64x16 x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt16to64 y))) (SLLV x (ZeroExt16to64 y))) +(Lsh64x8 x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt8to64 y))) (SLLV x (ZeroExt8to64 y))) + +(Lsh32x64 x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV (SGTU (MOVVconst [64]) y)) (SLLV x y)) +(Lsh32x32 x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt32to64 y))) (SLLV x (ZeroExt32to64 y))) +(Lsh32x16 x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt16to64 y))) (SLLV x (ZeroExt16to64 y))) +(Lsh32x8 x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt8to64 y))) (SLLV x (ZeroExt8to64 y))) + +(Lsh16x64 x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV (SGTU (MOVVconst [64]) y)) (SLLV x y)) +(Lsh16x32 x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt32to64 y))) (SLLV x (ZeroExt32to64 y))) +(Lsh16x16 x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt16to64 y))) (SLLV x (ZeroExt16to64 y))) +(Lsh16x8 x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt8to64 y))) (SLLV x (ZeroExt8to64 y))) + +(Lsh8x64 x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV (SGTU (MOVVconst [64]) y)) (SLLV x y)) +(Lsh8x32 x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt32to64 y))) (SLLV x (ZeroExt32to64 y))) +(Lsh8x16 x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt16to64 y))) (SLLV x (ZeroExt16to64 y))) +(Lsh8x8 x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt8to64 y))) (SLLV x (ZeroExt8to64 y))) + +// unsigned right shift +(Rsh64Ux(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SRLV x y) +(Rsh32Ux(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SRLV (ZeroExt32to64 x) y) +(Rsh16Ux(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SRLV (ZeroExt16to64 x) y) +(Rsh8Ux(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SRLV (ZeroExt8to64 x) y) + +(Rsh64Ux64 x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV (SGTU (MOVVconst [64]) y)) (SRLV x y)) +(Rsh64Ux32 x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt32to64 y))) (SRLV x (ZeroExt32to64 y))) +(Rsh64Ux16 x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt16to64 y))) (SRLV x (ZeroExt16to64 y))) +(Rsh64Ux8 x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt8to64 y))) (SRLV x (ZeroExt8to64 y))) + +(Rsh32Ux64 x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV (SGTU (MOVVconst [64]) y)) (SRLV (ZeroExt32to64 x) y)) +(Rsh32Ux32 x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt32to64 y))) (SRLV (ZeroExt32to64 x) (ZeroExt32to64 y))) +(Rsh32Ux16 x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt16to64 y))) (SRLV (ZeroExt32to64 x) (ZeroExt16to64 y))) +(Rsh32Ux8 x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt8to64 y))) (SRLV (ZeroExt32to64 x) (ZeroExt8to64 y))) + +(Rsh16Ux64 x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV (SGTU (MOVVconst [64]) y)) (SRLV (ZeroExt16to64 x) y)) +(Rsh16Ux32 x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt32to64 y))) (SRLV (ZeroExt16to64 x) (ZeroExt32to64 y))) +(Rsh16Ux16 x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt16to64 y))) (SRLV (ZeroExt16to64 x) (ZeroExt16to64 y))) +(Rsh16Ux8 x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt8to64 y))) (SRLV (ZeroExt16to64 x) (ZeroExt8to64 y))) + +(Rsh8Ux64 x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV (SGTU (MOVVconst [64]) y)) (SRLV (ZeroExt8to64 x) y)) +(Rsh8Ux32 x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt32to64 y))) (SRLV (ZeroExt8to64 x) (ZeroExt32to64 y))) +(Rsh8Ux16 x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt16to64 y))) (SRLV (ZeroExt8to64 x) (ZeroExt16to64 y))) +(Rsh8Ux8 x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt8to64 y))) (SRLV (ZeroExt8to64 x) (ZeroExt8to64 y))) + +// signed right shift +(Rsh64x(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SRAV x y) +(Rsh32x(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SRAV (SignExt32to64 x) y) +(Rsh16x(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SRAV (SignExt16to64 x) y) +(Rsh8x(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SRAV (SignExt8to64 x) y) + +(Rsh64x64 x y) && !ssa.ShiftIsBounded(v) => (SRAV x (OR (NEGV (SGTU y (MOVVconst [63]))) y)) +(Rsh64x32 x y) && !ssa.ShiftIsBounded(v) => (SRAV x (OR (NEGV (SGTU (ZeroExt32to64 y) (MOVVconst [63]))) (ZeroExt32to64 y))) +(Rsh64x16 x y) && !ssa.ShiftIsBounded(v) => (SRAV x (OR (NEGV (SGTU (ZeroExt16to64 y) (MOVVconst [63]))) (ZeroExt16to64 y))) +(Rsh64x8 x y) && !ssa.ShiftIsBounded(v) => (SRAV x (OR (NEGV (SGTU (ZeroExt8to64 y) (MOVVconst [63]))) (ZeroExt8to64 y))) + +(Rsh32x64 x y) && !ssa.ShiftIsBounded(v) => (SRAV (SignExt32to64 x) (OR (NEGV (SGTU y (MOVVconst [63]))) y)) +(Rsh32x32 x y) && !ssa.ShiftIsBounded(v) => (SRAV (SignExt32to64 x) (OR (NEGV (SGTU (ZeroExt32to64 y) (MOVVconst [63]))) (ZeroExt32to64 y))) +(Rsh32x16 x y) && !ssa.ShiftIsBounded(v) => (SRAV (SignExt32to64 x) (OR (NEGV (SGTU (ZeroExt16to64 y) (MOVVconst [63]))) (ZeroExt16to64 y))) +(Rsh32x8 x y) && !ssa.ShiftIsBounded(v) => (SRAV (SignExt32to64 x) (OR (NEGV (SGTU (ZeroExt8to64 y) (MOVVconst [63]))) (ZeroExt8to64 y))) + +(Rsh16x64 x y) && !ssa.ShiftIsBounded(v) => (SRAV (SignExt16to64 x) (OR (NEGV (SGTU y (MOVVconst [63]))) y)) +(Rsh16x32 x y) && !ssa.ShiftIsBounded(v) => (SRAV (SignExt16to64 x) (OR (NEGV (SGTU (ZeroExt32to64 y) (MOVVconst [63]))) (ZeroExt32to64 y))) +(Rsh16x16 x y) && !ssa.ShiftIsBounded(v) => (SRAV (SignExt16to64 x) (OR (NEGV (SGTU (ZeroExt16to64 y) (MOVVconst [63]))) (ZeroExt16to64 y))) +(Rsh16x8 x y) && !ssa.ShiftIsBounded(v) => (SRAV (SignExt16to64 x) (OR (NEGV (SGTU (ZeroExt8to64 y) (MOVVconst [63]))) (ZeroExt8to64 y))) + +(Rsh8x64 x y) && !ssa.ShiftIsBounded(v) => (SRAV (SignExt8to64 x) (OR (NEGV (SGTU y (MOVVconst [63]))) y)) +(Rsh8x32 x y) && !ssa.ShiftIsBounded(v) => (SRAV (SignExt8to64 x) (OR (NEGV (SGTU (ZeroExt32to64 y) (MOVVconst [63]))) (ZeroExt32to64 y))) +(Rsh8x16 x y) && !ssa.ShiftIsBounded(v) => (SRAV (SignExt8to64 x) (OR (NEGV (SGTU (ZeroExt16to64 y) (MOVVconst [63]))) (ZeroExt16to64 y))) +(Rsh8x8 x y) && !ssa.ShiftIsBounded(v) => (SRAV (SignExt8to64 x) (OR (NEGV (SGTU (ZeroExt8to64 y) (MOVVconst [63]))) (ZeroExt8to64 y))) // rotates (RotateLeft8 x (MOVVconst [c])) => (Or8 (Lsh8x64 x (MOVVconst [c&7])) (Rsh8Ux64 x (MOVVconst [-c&7]))) diff --git a/src/cmd/compile/internal/ssa/_gen/simdARM64SVE.rules b/src/cmd/compile/internal/ssa/_gen/simdARM64SVE.rules index d38949935e387a..ea1571e7d523d4 100644 --- a/src/cmd/compile/internal/ssa/_gen/simdARM64SVE.rules +++ b/src/cmd/compile/internal/ssa/_gen/simdARM64SVE.rules @@ -18,49 +18,213 @@ (AddSaturatedUint16s ...) => (ZUQADDH ...) // pureVreg (AddSaturatedUint32s ...) => (ZUQADDS ...) // pureVreg (AddSaturatedUint64s ...) => (ZUQADDD ...) // pureVreg +(AndInt8s ...) => (ZANDD ...) // pureVreg +(AndInt16s ...) => (ZANDD ...) // pureVreg +(AndInt32s ...) => (ZANDD ...) // pureVreg +(AndInt64s ...) => (ZANDD ...) // pureVreg +(AndUint8s ...) => (ZANDD ...) // pureVreg +(AndUint16s ...) => (ZANDD ...) // pureVreg +(AndUint32s ...) => (ZANDD ...) // pureVreg +(AndUint64s ...) => (ZANDD ...) // pureVreg +(OrInt8s ...) => (ZORRD ...) // pureVreg +(OrInt16s ...) => (ZORRD ...) // pureVreg +(OrInt32s ...) => (ZORRD ...) // pureVreg +(OrInt64s ...) => (ZORRD ...) // pureVreg +(OrUint8s ...) => (ZORRD ...) // pureVreg +(OrUint16s ...) => (ZORRD ...) // pureVreg +(OrUint32s ...) => (ZORRD ...) // pureVreg +(OrUint64s ...) => (ZORRD ...) // pureVreg +(SubFloat32s ...) => (ZFSUBS ...) // pureVreg +(SubFloat64s ...) => (ZFSUBD ...) // pureVreg +(SubInt8s ...) => (ZSUBB ...) // pureVreg +(SubInt16s ...) => (ZSUBH ...) // pureVreg +(SubInt32s ...) => (ZSUBS ...) // pureVreg +(SubInt64s ...) => (ZSUBD ...) // pureVreg +(SubUint8s ...) => (ZSUBB ...) // pureVreg +(SubUint16s ...) => (ZSUBH ...) // pureVreg +(SubUint32s ...) => (ZSUBS ...) // pureVreg +(SubUint64s ...) => (ZSUBD ...) // pureVreg +(SubSaturatedInt8s ...) => (ZSQSUBB ...) // pureVreg +(SubSaturatedInt16s ...) => (ZSQSUBH ...) // pureVreg +(SubSaturatedInt32s ...) => (ZSQSUBS ...) // pureVreg +(SubSaturatedInt64s ...) => (ZSQSUBD ...) // pureVreg +(SubSaturatedUint8s ...) => (ZUQSUBB ...) // pureVreg +(SubSaturatedUint16s ...) => (ZUQSUBH ...) // pureVreg +(SubSaturatedUint32s ...) => (ZUQSUBS ...) // pureVreg +(SubSaturatedUint64s ...) => (ZUQSUBD ...) // pureVreg +(XorInt8s ...) => (ZEORD ...) // pureVreg +(XorInt16s ...) => (ZEORD ...) // pureVreg +(XorInt32s ...) => (ZEORD ...) // pureVreg +(XorInt64s ...) => (ZEORD ...) // pureVreg +(XorUint8s ...) => (ZEORD ...) // pureVreg +(XorUint16s ...) => (ZEORD ...) // pureVreg +(XorUint32s ...) => (ZEORD ...) // pureVreg +(XorUint64s ...) => (ZEORD ...) // pureVreg +(AbsFloat32s x) => (ZFABSS x (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) +(AbsFloat64s x) => (ZFABSD x (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) +(AbsInt16s x) => (ZABSH x (Select0 (PWHILELTH (MOVDconst [0]) (MOVDconst [16])))) +(AbsInt32s x) => (ZABSS x (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) +(AbsInt64s x) => (ZABSD x (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) +(AbsInt8s x) => (ZABSB x (Select0 (PWHILELTB (MOVDconst [0]) (MOVDconst [32])))) +(CeilFloat32s x) => (ZFRINTPS x (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) +(CeilFloat64s x) => (ZFRINTPD x (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) +(EqualFloat32s x y) => (ZFCMEQS x y (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) +(EqualFloat64s x y) => (ZFCMEQD x y (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) +(EqualInt16s x y) => (ZCMPEQH x y (Select0 (PWHILELTH (MOVDconst [0]) (MOVDconst [16])))) +(EqualInt32s x y) => (ZCMPEQS x y (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) +(EqualInt64s x y) => (ZCMPEQD x y (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) +(EqualInt8s x y) => (ZCMPEQB x y (Select0 (PWHILELTB (MOVDconst [0]) (MOVDconst [32])))) +(EqualUint16s x y) => (ZCMPEQH x y (Select0 (PWHILELTH (MOVDconst [0]) (MOVDconst [16])))) +(EqualUint32s x y) => (ZCMPEQS x y (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) +(EqualUint64s x y) => (ZCMPEQD x y (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) +(EqualUint8s x y) => (ZCMPEQB x y (Select0 (PWHILELTB (MOVDconst [0]) (MOVDconst [32])))) +(FloorFloat32s x) => (ZFRINTMS x (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) +(FloorFloat64s x) => (ZFRINTMD x (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) +(GreaterEqualFloat32s x y) => (ZFCMGES x y (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) +(GreaterEqualFloat64s x y) => (ZFCMGED x y (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) +(GreaterEqualInt16s x y) => (ZCMPGEH x y (Select0 (PWHILELTH (MOVDconst [0]) (MOVDconst [16])))) +(GreaterEqualInt32s x y) => (ZCMPGES x y (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) +(GreaterEqualInt64s x y) => (ZCMPGED x y (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) +(GreaterEqualInt8s x y) => (ZCMPGEB x y (Select0 (PWHILELTB (MOVDconst [0]) (MOVDconst [32])))) +(GreaterEqualUint16s x y) => (ZCMPHSH x y (Select0 (PWHILELTH (MOVDconst [0]) (MOVDconst [16])))) +(GreaterEqualUint32s x y) => (ZCMPHSS x y (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) +(GreaterEqualUint64s x y) => (ZCMPHSD x y (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) +(GreaterEqualUint8s x y) => (ZCMPHSB x y (Select0 (PWHILELTB (MOVDconst [0]) (MOVDconst [32])))) +(GreaterFloat32s x y) => (ZFCMGTS x y (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) +(GreaterFloat64s x y) => (ZFCMGTD x y (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) (GreaterInt16s x y) => (ZCMPGTH x y (Select0 (PWHILELTH (MOVDconst [0]) (MOVDconst [16])))) (GreaterInt32s x y) => (ZCMPGTS x y (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) (GreaterInt64s x y) => (ZCMPGTD x y (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) (GreaterInt8s x y) => (ZCMPGTB x y (Select0 (PWHILELTB (MOVDconst [0]) (MOVDconst [32])))) +(GreaterUint16s x y) => (ZCMPHIH x y (Select0 (PWHILELTH (MOVDconst [0]) (MOVDconst [16])))) +(GreaterUint32s x y) => (ZCMPHIS x y (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) +(GreaterUint64s x y) => (ZCMPHID x y (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) +(GreaterUint8s x y) => (ZCMPHIB x y (Select0 (PWHILELTB (MOVDconst [0]) (MOVDconst [32])))) +(NegFloat32s x) => (ZFNEGS x (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) +(NegFloat64s x) => (ZFNEGD x (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) +(NegInt16s x) => (ZNEGH x (Select0 (PWHILELTH (MOVDconst [0]) (MOVDconst [16])))) +(NegInt32s x) => (ZNEGS x (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) +(NegInt64s x) => (ZNEGD x (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) +(NegInt8s x) => (ZNEGB x (Select0 (PWHILELTB (MOVDconst [0]) (MOVDconst [32])))) +(NotEqualFloat32s x y) => (ZFCMNES x y (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) +(NotEqualFloat64s x y) => (ZFCMNED x y (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) +(NotEqualInt16s x y) => (ZCMPNEH x y (Select0 (PWHILELTH (MOVDconst [0]) (MOVDconst [16])))) +(NotEqualInt32s x y) => (ZCMPNES x y (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) +(NotEqualInt64s x y) => (ZCMPNED x y (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) +(NotEqualInt8s x y) => (ZCMPNEB x y (Select0 (PWHILELTB (MOVDconst [0]) (MOVDconst [32])))) +(NotEqualUint16s x y) => (ZCMPNEH x y (Select0 (PWHILELTH (MOVDconst [0]) (MOVDconst [16])))) +(NotEqualUint32s x y) => (ZCMPNES x y (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) +(NotEqualUint64s x y) => (ZCMPNED x y (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) +(NotEqualUint8s x y) => (ZCMPNEB x y (Select0 (PWHILELTB (MOVDconst [0]) (MOVDconst [32])))) +(RoundFloat32s x) => (ZFRINTNS x (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) +(RoundFloat64s x) => (ZFRINTND x (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) +(SqrtFloat32s x) => (ZFSQRTS x (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) +(SqrtFloat64s x) => (ZFSQRTD x (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) +(TruncFloat32s x) => (ZFRINTZS x (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) +(TruncFloat64s x) => (ZFRINTZD x (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) +(ZSELB (ZABSB x (Select0 (PWHILELTB (MOVDconst [0]) (MOVDconst [32])))) z mask) => (ZABSMergingB z x mask) (ZSELB (ZADDB x y) x mask) => (ZADDMergingB x y mask) (ZSELB (ZADDB x y) y mask) => (ZADDMergingB y x mask) (ZSELB (ZADDB x y) z mask) => (ZADDMergingPrefixedB z x y mask) +(ZSELB (ZANDD x y) x mask) => (ZANDMergingB x y mask) +(ZSELB (ZANDD x y) y mask) => (ZANDMergingB y x mask) +(ZSELB (ZANDD x y) z mask) => (ZANDMergingPrefixedB z x y mask) +(ZSELB (ZEORD x y) x mask) => (ZEORMergingB x y mask) +(ZSELB (ZEORD x y) y mask) => (ZEORMergingB y x mask) +(ZSELB (ZEORD x y) z mask) => (ZEORMergingPrefixedB z x y mask) +(ZSELB (ZNEGB x (Select0 (PWHILELTB (MOVDconst [0]) (MOVDconst [32])))) z mask) => (ZNEGMergingB z x mask) +(ZSELB (ZORRD x y) x mask) => (ZORRMergingB x y mask) +(ZSELB (ZORRD x y) y mask) => (ZORRMergingB y x mask) +(ZSELB (ZORRD x y) z mask) => (ZORRMergingPrefixedB z x y mask) (ZSELB (ZSQADDB x y) x mask) => (ZSQADDMergingB x y mask) (ZSELB (ZSQADDB x y) y mask) => (ZSQADDMergingB y x mask) (ZSELB (ZSQADDB x y) z mask) => (ZSQADDMergingPrefixedB z x y mask) +(ZSELB (ZSQSUBB x y) x mask) => (ZSQSUBMergingB x y mask) +(ZSELB (ZSUBB x y) x mask) => (ZSUBMergingB x y mask) (ZSELB (ZUQADDB x y) x mask) => (ZUQADDMergingB x y mask) (ZSELB (ZUQADDB x y) y mask) => (ZUQADDMergingB y x mask) (ZSELB (ZUQADDB x y) z mask) => (ZUQADDMergingPrefixedB z x y mask) +(ZSELB (ZUQSUBB x y) x mask) => (ZUQSUBMergingB x y mask) +(ZSELD (ZABSD x (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) z mask) => (ZABSMergingD z x mask) (ZSELD (ZADDD x y) x mask) => (ZADDMergingD x y mask) (ZSELD (ZADDD x y) y mask) => (ZADDMergingD y x mask) (ZSELD (ZADDD x y) z mask) => (ZADDMergingPrefixedD z x y mask) +(ZSELD (ZANDD x y) x mask) => (ZANDMergingD x y mask) +(ZSELD (ZANDD x y) y mask) => (ZANDMergingD y x mask) +(ZSELD (ZANDD x y) z mask) => (ZANDMergingPrefixedD z x y mask) +(ZSELD (ZEORD x y) x mask) => (ZEORMergingD x y mask) +(ZSELD (ZEORD x y) y mask) => (ZEORMergingD y x mask) +(ZSELD (ZEORD x y) z mask) => (ZEORMergingPrefixedD z x y mask) +(ZSELD (ZFABSD x (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) z mask) => (ZFABSMergingD z x mask) (ZSELD (ZFADDD x y) x mask) => (ZFADDMergingD x y mask) (ZSELD (ZFADDD x y) y mask) => (ZFADDMergingD y x mask) (ZSELD (ZFADDD x y) z mask) => (ZFADDMergingPrefixedD z x y mask) +(ZSELD (ZFNEGD x (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) z mask) => (ZFNEGMergingD z x mask) +(ZSELD (ZFSQRTD x (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) z mask) => (ZFSQRTMergingD z x mask) +(ZSELD (ZFSUBD x y) x mask) => (ZFSUBMergingD x y mask) +(ZSELD (ZNEGD x (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) z mask) => (ZNEGMergingD z x mask) +(ZSELD (ZORRD x y) x mask) => (ZORRMergingD x y mask) +(ZSELD (ZORRD x y) y mask) => (ZORRMergingD y x mask) +(ZSELD (ZORRD x y) z mask) => (ZORRMergingPrefixedD z x y mask) (ZSELD (ZSQADDD x y) x mask) => (ZSQADDMergingD x y mask) (ZSELD (ZSQADDD x y) y mask) => (ZSQADDMergingD y x mask) (ZSELD (ZSQADDD x y) z mask) => (ZSQADDMergingPrefixedD z x y mask) +(ZSELD (ZSQSUBD x y) x mask) => (ZSQSUBMergingD x y mask) +(ZSELD (ZSUBD x y) x mask) => (ZSUBMergingD x y mask) (ZSELD (ZUQADDD x y) x mask) => (ZUQADDMergingD x y mask) (ZSELD (ZUQADDD x y) y mask) => (ZUQADDMergingD y x mask) (ZSELD (ZUQADDD x y) z mask) => (ZUQADDMergingPrefixedD z x y mask) +(ZSELD (ZUQSUBD x y) x mask) => (ZUQSUBMergingD x y mask) +(ZSELH (ZABSH x (Select0 (PWHILELTH (MOVDconst [0]) (MOVDconst [16])))) z mask) => (ZABSMergingH z x mask) (ZSELH (ZADDH x y) x mask) => (ZADDMergingH x y mask) (ZSELH (ZADDH x y) y mask) => (ZADDMergingH y x mask) (ZSELH (ZADDH x y) z mask) => (ZADDMergingPrefixedH z x y mask) +(ZSELH (ZANDD x y) x mask) => (ZANDMergingH x y mask) +(ZSELH (ZANDD x y) y mask) => (ZANDMergingH y x mask) +(ZSELH (ZANDD x y) z mask) => (ZANDMergingPrefixedH z x y mask) +(ZSELH (ZEORD x y) x mask) => (ZEORMergingH x y mask) +(ZSELH (ZEORD x y) y mask) => (ZEORMergingH y x mask) +(ZSELH (ZEORD x y) z mask) => (ZEORMergingPrefixedH z x y mask) +(ZSELH (ZNEGH x (Select0 (PWHILELTH (MOVDconst [0]) (MOVDconst [16])))) z mask) => (ZNEGMergingH z x mask) +(ZSELH (ZORRD x y) x mask) => (ZORRMergingH x y mask) +(ZSELH (ZORRD x y) y mask) => (ZORRMergingH y x mask) +(ZSELH (ZORRD x y) z mask) => (ZORRMergingPrefixedH z x y mask) (ZSELH (ZSQADDH x y) x mask) => (ZSQADDMergingH x y mask) (ZSELH (ZSQADDH x y) y mask) => (ZSQADDMergingH y x mask) (ZSELH (ZSQADDH x y) z mask) => (ZSQADDMergingPrefixedH z x y mask) +(ZSELH (ZSQSUBH x y) x mask) => (ZSQSUBMergingH x y mask) +(ZSELH (ZSUBH x y) x mask) => (ZSUBMergingH x y mask) (ZSELH (ZUQADDH x y) x mask) => (ZUQADDMergingH x y mask) (ZSELH (ZUQADDH x y) y mask) => (ZUQADDMergingH y x mask) (ZSELH (ZUQADDH x y) z mask) => (ZUQADDMergingPrefixedH z x y mask) +(ZSELH (ZUQSUBH x y) x mask) => (ZUQSUBMergingH x y mask) +(ZSELS (ZABSS x (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) z mask) => (ZABSMergingS z x mask) (ZSELS (ZADDS x y) x mask) => (ZADDMergingS x y mask) (ZSELS (ZADDS x y) y mask) => (ZADDMergingS y x mask) (ZSELS (ZADDS x y) z mask) => (ZADDMergingPrefixedS z x y mask) +(ZSELS (ZANDD x y) x mask) => (ZANDMergingS x y mask) +(ZSELS (ZANDD x y) y mask) => (ZANDMergingS y x mask) +(ZSELS (ZANDD x y) z mask) => (ZANDMergingPrefixedS z x y mask) +(ZSELS (ZEORD x y) x mask) => (ZEORMergingS x y mask) +(ZSELS (ZEORD x y) y mask) => (ZEORMergingS y x mask) +(ZSELS (ZEORD x y) z mask) => (ZEORMergingPrefixedS z x y mask) +(ZSELS (ZFABSS x (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) z mask) => (ZFABSMergingS z x mask) (ZSELS (ZFADDS x y) x mask) => (ZFADDMergingS x y mask) (ZSELS (ZFADDS x y) y mask) => (ZFADDMergingS y x mask) (ZSELS (ZFADDS x y) z mask) => (ZFADDMergingPrefixedS z x y mask) +(ZSELS (ZFNEGS x (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) z mask) => (ZFNEGMergingS z x mask) +(ZSELS (ZFSQRTS x (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) z mask) => (ZFSQRTMergingS z x mask) +(ZSELS (ZFSUBS x y) x mask) => (ZFSUBMergingS x y mask) +(ZSELS (ZNEGS x (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) z mask) => (ZNEGMergingS z x mask) +(ZSELS (ZORRD x y) x mask) => (ZORRMergingS x y mask) +(ZSELS (ZORRD x y) y mask) => (ZORRMergingS y x mask) +(ZSELS (ZORRD x y) z mask) => (ZORRMergingPrefixedS z x y mask) (ZSELS (ZSQADDS x y) x mask) => (ZSQADDMergingS x y mask) (ZSELS (ZSQADDS x y) y mask) => (ZSQADDMergingS y x mask) (ZSELS (ZSQADDS x y) z mask) => (ZSQADDMergingPrefixedS z x y mask) +(ZSELS (ZSQSUBS x y) x mask) => (ZSQSUBMergingS x y mask) +(ZSELS (ZSUBS x y) x mask) => (ZSUBMergingS x y mask) (ZSELS (ZUQADDS x y) x mask) => (ZUQADDMergingS x y mask) (ZSELS (ZUQADDS x y) y mask) => (ZUQADDMergingS y x mask) (ZSELS (ZUQADDS x y) z mask) => (ZUQADDMergingPrefixedS z x y mask) +(ZSELS (ZUQSUBS x y) x mask) => (ZUQSUBMergingS x y mask) diff --git a/src/cmd/compile/internal/ssa/_gen/simdARM64SVEops.go b/src/cmd/compile/internal/ssa/_gen/simdARM64SVEops.go index fd3453977bda51..1f33449b23ceec 100644 --- a/src/cmd/compile/internal/ssa/_gen/simdARM64SVEops.go +++ b/src/cmd/compile/internal/ssa/_gen/simdARM64SVEops.go @@ -2,8 +2,16 @@ package main -func simdARM64SVEOps(z11, z21, z2kk, z2kv, z2kvPred, z3kvPred regInfo) []opData { +func simdARM64SVEOps(z11, z21, zkv, z2kk, z2kv, z2kvPred, z3kvPred regInfo) []opData { return []opData{ + {name: "ZABSB", argLength: 2, reg: zkv, asm: "ZABS", typ: "Vec256"}, + {name: "ZABSD", argLength: 2, reg: zkv, asm: "ZABS", typ: "Vec256"}, + {name: "ZABSH", argLength: 2, reg: zkv, asm: "ZABS", typ: "Vec256"}, + {name: "ZABSMergingB", argLength: 3, reg: z2kvPred, asm: "ZABS", typ: "Vec256", resultInArg0: true}, + {name: "ZABSMergingD", argLength: 3, reg: z2kvPred, asm: "ZABS", typ: "Vec256", resultInArg0: true}, + {name: "ZABSMergingH", argLength: 3, reg: z2kvPred, asm: "ZABS", typ: "Vec256", resultInArg0: true}, + {name: "ZABSMergingS", argLength: 3, reg: z2kvPred, asm: "ZABS", typ: "Vec256", resultInArg0: true}, + {name: "ZABSS", argLength: 2, reg: zkv, asm: "ZABS", typ: "Vec256"}, {name: "ZADDB", argLength: 2, reg: z21, asm: "ZADD", commutative: true, typ: "Vec256"}, {name: "ZADDD", argLength: 2, reg: z21, asm: "ZADD", commutative: true, typ: "Vec256"}, {name: "ZADDH", argLength: 2, reg: z21, asm: "ZADD", commutative: true, typ: "Vec256"}, @@ -16,16 +24,103 @@ func simdARM64SVEOps(z11, z21, z2kk, z2kv, z2kvPred, z3kvPred regInfo) []opData {name: "ZADDMergingPrefixedS", argLength: 4, reg: z3kvPred, asm: "ZADD", typ: "Vec256", resultInArg0: true}, {name: "ZADDMergingS", argLength: 3, reg: z2kvPred, asm: "ZADD", commutative: true, typ: "Vec256"}, {name: "ZADDS", argLength: 2, reg: z21, asm: "ZADD", commutative: true, typ: "Vec256"}, + {name: "ZANDD", argLength: 2, reg: z21, asm: "ZAND", commutative: true, typ: "Vec256"}, + {name: "ZANDMergingB", argLength: 3, reg: z2kvPred, asm: "ZAND", commutative: true, typ: "Vec256"}, + {name: "ZANDMergingD", argLength: 3, reg: z2kvPred, asm: "ZAND", commutative: true, typ: "Vec256"}, + {name: "ZANDMergingH", argLength: 3, reg: z2kvPred, asm: "ZAND", commutative: true, typ: "Vec256"}, + {name: "ZANDMergingPrefixedB", argLength: 4, reg: z3kvPred, asm: "ZAND", typ: "Vec256", resultInArg0: true}, + {name: "ZANDMergingPrefixedD", argLength: 4, reg: z3kvPred, asm: "ZAND", typ: "Vec256", resultInArg0: true}, + {name: "ZANDMergingPrefixedH", argLength: 4, reg: z3kvPred, asm: "ZAND", typ: "Vec256", resultInArg0: true}, + {name: "ZANDMergingPrefixedS", argLength: 4, reg: z3kvPred, asm: "ZAND", typ: "Vec256", resultInArg0: true}, + {name: "ZANDMergingS", argLength: 3, reg: z2kvPred, asm: "ZAND", commutative: true, typ: "Vec256"}, + {name: "ZCMPEQB", argLength: 3, reg: z2kk, asm: "ZCMPEQ", commutative: true, typ: "Mask"}, + {name: "ZCMPEQD", argLength: 3, reg: z2kk, asm: "ZCMPEQ", commutative: true, typ: "Mask"}, + {name: "ZCMPEQH", argLength: 3, reg: z2kk, asm: "ZCMPEQ", commutative: true, typ: "Mask"}, + {name: "ZCMPEQS", argLength: 3, reg: z2kk, asm: "ZCMPEQ", commutative: true, typ: "Mask"}, + {name: "ZCMPGEB", argLength: 3, reg: z2kk, asm: "ZCMPGE", typ: "Mask"}, + {name: "ZCMPGED", argLength: 3, reg: z2kk, asm: "ZCMPGE", typ: "Mask"}, + {name: "ZCMPGEH", argLength: 3, reg: z2kk, asm: "ZCMPGE", typ: "Mask"}, + {name: "ZCMPGES", argLength: 3, reg: z2kk, asm: "ZCMPGE", typ: "Mask"}, {name: "ZCMPGTB", argLength: 3, reg: z2kk, asm: "ZCMPGT", typ: "Mask"}, {name: "ZCMPGTD", argLength: 3, reg: z2kk, asm: "ZCMPGT", typ: "Mask"}, {name: "ZCMPGTH", argLength: 3, reg: z2kk, asm: "ZCMPGT", typ: "Mask"}, {name: "ZCMPGTS", argLength: 3, reg: z2kk, asm: "ZCMPGT", typ: "Mask"}, + {name: "ZCMPHIB", argLength: 3, reg: z2kk, asm: "ZCMPHI", typ: "Mask"}, + {name: "ZCMPHID", argLength: 3, reg: z2kk, asm: "ZCMPHI", typ: "Mask"}, + {name: "ZCMPHIH", argLength: 3, reg: z2kk, asm: "ZCMPHI", typ: "Mask"}, + {name: "ZCMPHIS", argLength: 3, reg: z2kk, asm: "ZCMPHI", typ: "Mask"}, + {name: "ZCMPHSB", argLength: 3, reg: z2kk, asm: "ZCMPHS", typ: "Mask"}, + {name: "ZCMPHSD", argLength: 3, reg: z2kk, asm: "ZCMPHS", typ: "Mask"}, + {name: "ZCMPHSH", argLength: 3, reg: z2kk, asm: "ZCMPHS", typ: "Mask"}, + {name: "ZCMPHSS", argLength: 3, reg: z2kk, asm: "ZCMPHS", typ: "Mask"}, + {name: "ZCMPNEB", argLength: 3, reg: z2kk, asm: "ZCMPNE", commutative: true, typ: "Mask"}, + {name: "ZCMPNED", argLength: 3, reg: z2kk, asm: "ZCMPNE", commutative: true, typ: "Mask"}, + {name: "ZCMPNEH", argLength: 3, reg: z2kk, asm: "ZCMPNE", commutative: true, typ: "Mask"}, + {name: "ZCMPNES", argLength: 3, reg: z2kk, asm: "ZCMPNE", commutative: true, typ: "Mask"}, + {name: "ZEORD", argLength: 2, reg: z21, asm: "ZEOR", commutative: true, typ: "Vec256"}, + {name: "ZEORMergingB", argLength: 3, reg: z2kvPred, asm: "ZEOR", commutative: true, typ: "Vec256"}, + {name: "ZEORMergingD", argLength: 3, reg: z2kvPred, asm: "ZEOR", commutative: true, typ: "Vec256"}, + {name: "ZEORMergingH", argLength: 3, reg: z2kvPred, asm: "ZEOR", commutative: true, typ: "Vec256"}, + {name: "ZEORMergingPrefixedB", argLength: 4, reg: z3kvPred, asm: "ZEOR", typ: "Vec256", resultInArg0: true}, + {name: "ZEORMergingPrefixedD", argLength: 4, reg: z3kvPred, asm: "ZEOR", typ: "Vec256", resultInArg0: true}, + {name: "ZEORMergingPrefixedH", argLength: 4, reg: z3kvPred, asm: "ZEOR", typ: "Vec256", resultInArg0: true}, + {name: "ZEORMergingPrefixedS", argLength: 4, reg: z3kvPred, asm: "ZEOR", typ: "Vec256", resultInArg0: true}, + {name: "ZEORMergingS", argLength: 3, reg: z2kvPred, asm: "ZEOR", commutative: true, typ: "Vec256"}, + {name: "ZFABSD", argLength: 2, reg: zkv, asm: "ZFABS", typ: "Vec256"}, + {name: "ZFABSMergingD", argLength: 3, reg: z2kvPred, asm: "ZFABS", typ: "Vec256", resultInArg0: true}, + {name: "ZFABSMergingS", argLength: 3, reg: z2kvPred, asm: "ZFABS", typ: "Vec256", resultInArg0: true}, + {name: "ZFABSS", argLength: 2, reg: zkv, asm: "ZFABS", typ: "Vec256"}, {name: "ZFADDD", argLength: 2, reg: z21, asm: "ZFADD", commutative: true, typ: "Vec256"}, {name: "ZFADDMergingD", argLength: 3, reg: z2kvPred, asm: "ZFADD", commutative: true, typ: "Vec256"}, {name: "ZFADDMergingPrefixedD", argLength: 4, reg: z3kvPred, asm: "ZFADD", typ: "Vec256", resultInArg0: true}, {name: "ZFADDMergingPrefixedS", argLength: 4, reg: z3kvPred, asm: "ZFADD", typ: "Vec256", resultInArg0: true}, {name: "ZFADDMergingS", argLength: 3, reg: z2kvPred, asm: "ZFADD", commutative: true, typ: "Vec256"}, {name: "ZFADDS", argLength: 2, reg: z21, asm: "ZFADD", commutative: true, typ: "Vec256"}, + {name: "ZFCMEQD", argLength: 3, reg: z2kk, asm: "ZFCMEQ", commutative: true, typ: "Mask"}, + {name: "ZFCMEQS", argLength: 3, reg: z2kk, asm: "ZFCMEQ", commutative: true, typ: "Mask"}, + {name: "ZFCMGED", argLength: 3, reg: z2kk, asm: "ZFCMGE", typ: "Mask"}, + {name: "ZFCMGES", argLength: 3, reg: z2kk, asm: "ZFCMGE", typ: "Mask"}, + {name: "ZFCMGTD", argLength: 3, reg: z2kk, asm: "ZFCMGT", typ: "Mask"}, + {name: "ZFCMGTS", argLength: 3, reg: z2kk, asm: "ZFCMGT", typ: "Mask"}, + {name: "ZFCMNED", argLength: 3, reg: z2kk, asm: "ZFCMNE", commutative: true, typ: "Mask"}, + {name: "ZFCMNES", argLength: 3, reg: z2kk, asm: "ZFCMNE", commutative: true, typ: "Mask"}, + {name: "ZFNEGD", argLength: 2, reg: zkv, asm: "ZFNEG", typ: "Vec256"}, + {name: "ZFNEGMergingD", argLength: 3, reg: z2kvPred, asm: "ZFNEG", typ: "Vec256", resultInArg0: true}, + {name: "ZFNEGMergingS", argLength: 3, reg: z2kvPred, asm: "ZFNEG", typ: "Vec256", resultInArg0: true}, + {name: "ZFNEGS", argLength: 2, reg: zkv, asm: "ZFNEG", typ: "Vec256"}, + {name: "ZFRINTMD", argLength: 2, reg: zkv, asm: "ZFRINTM", typ: "Vec256"}, + {name: "ZFRINTMS", argLength: 2, reg: zkv, asm: "ZFRINTM", typ: "Vec256"}, + {name: "ZFRINTND", argLength: 2, reg: zkv, asm: "ZFRINTN", typ: "Vec256"}, + {name: "ZFRINTNS", argLength: 2, reg: zkv, asm: "ZFRINTN", typ: "Vec256"}, + {name: "ZFRINTPD", argLength: 2, reg: zkv, asm: "ZFRINTP", typ: "Vec256"}, + {name: "ZFRINTPS", argLength: 2, reg: zkv, asm: "ZFRINTP", typ: "Vec256"}, + {name: "ZFRINTZD", argLength: 2, reg: zkv, asm: "ZFRINTZ", typ: "Vec256"}, + {name: "ZFRINTZS", argLength: 2, reg: zkv, asm: "ZFRINTZ", typ: "Vec256"}, + {name: "ZFSQRTD", argLength: 2, reg: zkv, asm: "ZFSQRT", typ: "Vec256"}, + {name: "ZFSQRTMergingD", argLength: 3, reg: z2kvPred, asm: "ZFSQRT", typ: "Vec256", resultInArg0: true}, + {name: "ZFSQRTMergingS", argLength: 3, reg: z2kvPred, asm: "ZFSQRT", typ: "Vec256", resultInArg0: true}, + {name: "ZFSQRTS", argLength: 2, reg: zkv, asm: "ZFSQRT", typ: "Vec256"}, + {name: "ZFSUBD", argLength: 2, reg: z21, asm: "ZFSUB", typ: "Vec256"}, + {name: "ZFSUBMergingD", argLength: 3, reg: z2kvPred, asm: "ZFSUB", typ: "Vec256", resultInArg0: true}, + {name: "ZFSUBMergingS", argLength: 3, reg: z2kvPred, asm: "ZFSUB", typ: "Vec256", resultInArg0: true}, + {name: "ZFSUBS", argLength: 2, reg: z21, asm: "ZFSUB", typ: "Vec256"}, + {name: "ZNEGB", argLength: 2, reg: zkv, asm: "ZNEG", typ: "Vec256"}, + {name: "ZNEGD", argLength: 2, reg: zkv, asm: "ZNEG", typ: "Vec256"}, + {name: "ZNEGH", argLength: 2, reg: zkv, asm: "ZNEG", typ: "Vec256"}, + {name: "ZNEGMergingB", argLength: 3, reg: z2kvPred, asm: "ZNEG", typ: "Vec256", resultInArg0: true}, + {name: "ZNEGMergingD", argLength: 3, reg: z2kvPred, asm: "ZNEG", typ: "Vec256", resultInArg0: true}, + {name: "ZNEGMergingH", argLength: 3, reg: z2kvPred, asm: "ZNEG", typ: "Vec256", resultInArg0: true}, + {name: "ZNEGMergingS", argLength: 3, reg: z2kvPred, asm: "ZNEG", typ: "Vec256", resultInArg0: true}, + {name: "ZNEGS", argLength: 2, reg: zkv, asm: "ZNEG", typ: "Vec256"}, + {name: "ZORRD", argLength: 2, reg: z21, asm: "ZORR", commutative: true, typ: "Vec256"}, + {name: "ZORRMergingB", argLength: 3, reg: z2kvPred, asm: "ZORR", commutative: true, typ: "Vec256"}, + {name: "ZORRMergingD", argLength: 3, reg: z2kvPred, asm: "ZORR", commutative: true, typ: "Vec256"}, + {name: "ZORRMergingH", argLength: 3, reg: z2kvPred, asm: "ZORR", commutative: true, typ: "Vec256"}, + {name: "ZORRMergingPrefixedB", argLength: 4, reg: z3kvPred, asm: "ZORR", typ: "Vec256", resultInArg0: true}, + {name: "ZORRMergingPrefixedD", argLength: 4, reg: z3kvPred, asm: "ZORR", typ: "Vec256", resultInArg0: true}, + {name: "ZORRMergingPrefixedH", argLength: 4, reg: z3kvPred, asm: "ZORR", typ: "Vec256", resultInArg0: true}, + {name: "ZORRMergingPrefixedS", argLength: 4, reg: z3kvPred, asm: "ZORR", typ: "Vec256", resultInArg0: true}, + {name: "ZORRMergingS", argLength: 3, reg: z2kvPred, asm: "ZORR", commutative: true, typ: "Vec256"}, {name: "ZSQADDB", argLength: 2, reg: z21, asm: "ZSQADD", commutative: true, typ: "Vec256"}, {name: "ZSQADDD", argLength: 2, reg: z21, asm: "ZSQADD", commutative: true, typ: "Vec256"}, {name: "ZSQADDH", argLength: 2, reg: z21, asm: "ZSQADD", commutative: true, typ: "Vec256"}, @@ -38,6 +133,22 @@ func simdARM64SVEOps(z11, z21, z2kk, z2kv, z2kvPred, z3kvPred regInfo) []opData {name: "ZSQADDMergingPrefixedS", argLength: 4, reg: z3kvPred, asm: "ZSQADD", typ: "Vec256", resultInArg0: true}, {name: "ZSQADDMergingS", argLength: 3, reg: z2kvPred, asm: "ZSQADD", commutative: true, typ: "Vec256"}, {name: "ZSQADDS", argLength: 2, reg: z21, asm: "ZSQADD", commutative: true, typ: "Vec256"}, + {name: "ZSQSUBB", argLength: 2, reg: z21, asm: "ZSQSUB", typ: "Vec256"}, + {name: "ZSQSUBD", argLength: 2, reg: z21, asm: "ZSQSUB", typ: "Vec256"}, + {name: "ZSQSUBH", argLength: 2, reg: z21, asm: "ZSQSUB", typ: "Vec256"}, + {name: "ZSQSUBMergingB", argLength: 3, reg: z2kvPred, asm: "ZSQSUB", typ: "Vec256", resultInArg0: true}, + {name: "ZSQSUBMergingD", argLength: 3, reg: z2kvPred, asm: "ZSQSUB", typ: "Vec256", resultInArg0: true}, + {name: "ZSQSUBMergingH", argLength: 3, reg: z2kvPred, asm: "ZSQSUB", typ: "Vec256", resultInArg0: true}, + {name: "ZSQSUBMergingS", argLength: 3, reg: z2kvPred, asm: "ZSQSUB", typ: "Vec256", resultInArg0: true}, + {name: "ZSQSUBS", argLength: 2, reg: z21, asm: "ZSQSUB", typ: "Vec256"}, + {name: "ZSUBB", argLength: 2, reg: z21, asm: "ZSUB", typ: "Vec256"}, + {name: "ZSUBD", argLength: 2, reg: z21, asm: "ZSUB", typ: "Vec256"}, + {name: "ZSUBH", argLength: 2, reg: z21, asm: "ZSUB", typ: "Vec256"}, + {name: "ZSUBMergingB", argLength: 3, reg: z2kvPred, asm: "ZSUB", typ: "Vec256", resultInArg0: true}, + {name: "ZSUBMergingD", argLength: 3, reg: z2kvPred, asm: "ZSUB", typ: "Vec256", resultInArg0: true}, + {name: "ZSUBMergingH", argLength: 3, reg: z2kvPred, asm: "ZSUB", typ: "Vec256", resultInArg0: true}, + {name: "ZSUBMergingS", argLength: 3, reg: z2kvPred, asm: "ZSUB", typ: "Vec256", resultInArg0: true}, + {name: "ZSUBS", argLength: 2, reg: z21, asm: "ZSUB", typ: "Vec256"}, {name: "ZUQADDB", argLength: 2, reg: z21, asm: "ZUQADD", commutative: true, typ: "Vec256"}, {name: "ZUQADDD", argLength: 2, reg: z21, asm: "ZUQADD", commutative: true, typ: "Vec256"}, {name: "ZUQADDH", argLength: 2, reg: z21, asm: "ZUQADD", commutative: true, typ: "Vec256"}, @@ -50,5 +161,13 @@ func simdARM64SVEOps(z11, z21, z2kk, z2kv, z2kvPred, z3kvPred regInfo) []opData {name: "ZUQADDMergingPrefixedS", argLength: 4, reg: z3kvPred, asm: "ZUQADD", typ: "Vec256", resultInArg0: true}, {name: "ZUQADDMergingS", argLength: 3, reg: z2kvPred, asm: "ZUQADD", commutative: true, typ: "Vec256"}, {name: "ZUQADDS", argLength: 2, reg: z21, asm: "ZUQADD", commutative: true, typ: "Vec256"}, + {name: "ZUQSUBB", argLength: 2, reg: z21, asm: "ZUQSUB", typ: "Vec256"}, + {name: "ZUQSUBD", argLength: 2, reg: z21, asm: "ZUQSUB", typ: "Vec256"}, + {name: "ZUQSUBH", argLength: 2, reg: z21, asm: "ZUQSUB", typ: "Vec256"}, + {name: "ZUQSUBMergingB", argLength: 3, reg: z2kvPred, asm: "ZUQSUB", typ: "Vec256", resultInArg0: true}, + {name: "ZUQSUBMergingD", argLength: 3, reg: z2kvPred, asm: "ZUQSUB", typ: "Vec256", resultInArg0: true}, + {name: "ZUQSUBMergingH", argLength: 3, reg: z2kvPred, asm: "ZUQSUB", typ: "Vec256", resultInArg0: true}, + {name: "ZUQSUBMergingS", argLength: 3, reg: z2kvPred, asm: "ZUQSUB", typ: "Vec256", resultInArg0: true}, + {name: "ZUQSUBS", argLength: 2, reg: z21, asm: "ZUQSUB", typ: "Vec256"}, } } diff --git a/src/cmd/compile/internal/ssa/_gen/simdgenericOps.go b/src/cmd/compile/internal/ssa/_gen/simdgenericOps.go index 4052d5f02e3fdc..0a1253a0aa5573 100644 --- a/src/cmd/compile/internal/ssa/_gen/simdgenericOps.go +++ b/src/cmd/compile/internal/ssa/_gen/simdgenericOps.go @@ -17,17 +17,23 @@ func simdGenericOps() []opData { {name: "AESEncryptOneRoundUint8x32", argLength: 2}, // ARCH:amd64 {name: "AESEncryptOneRoundUint8x64", argLength: 2}, // ARCH:amd64 {name: "AESInvMixColumnsUint32x4", argLength: 1}, // ARCH:amd64 + {name: "AbsFloat32s", argLength: 1}, // ARCH:sve {name: "AbsFloat32x4", argLength: 1}, // ARCH:arm64,wasm + {name: "AbsFloat64s", argLength: 1}, // ARCH:sve {name: "AbsFloat64x2", argLength: 1}, // ARCH:arm64,wasm + {name: "AbsInt8s", argLength: 1}, // ARCH:sve {name: "AbsInt8x16", argLength: 1}, // ARCH:amd64,arm64,wasm {name: "AbsInt8x32", argLength: 1}, // ARCH:amd64 {name: "AbsInt8x64", argLength: 1}, // ARCH:amd64 + {name: "AbsInt16s", argLength: 1}, // ARCH:sve {name: "AbsInt16x8", argLength: 1}, // ARCH:amd64,arm64,wasm {name: "AbsInt16x16", argLength: 1}, // ARCH:amd64 {name: "AbsInt16x32", argLength: 1}, // ARCH:amd64 + {name: "AbsInt32s", argLength: 1}, // ARCH:sve {name: "AbsInt32x4", argLength: 1}, // ARCH:amd64,arm64,wasm {name: "AbsInt32x8", argLength: 1}, // ARCH:amd64 {name: "AbsInt32x16", argLength: 1}, // ARCH:amd64 + {name: "AbsInt64s", argLength: 1}, // ARCH:sve {name: "AbsInt64x2", argLength: 1}, // ARCH:amd64,arm64,wasm {name: "AbsInt64x4", argLength: 1}, // ARCH:amd64 {name: "AbsInt64x8", argLength: 1}, // ARCH:amd64 @@ -99,15 +105,19 @@ func simdGenericOps() []opData { {name: "AddUint64x2", argLength: 2, commutative: true}, // ARCH:amd64,arm64 {name: "AddUint64x4", argLength: 2, commutative: true}, // ARCH:amd64 {name: "AddUint64x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AndInt8s", argLength: 2, commutative: true}, // ARCH:sve {name: "AndInt8x16", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm {name: "AndInt8x32", argLength: 2, commutative: true}, // ARCH:amd64 {name: "AndInt8x64", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AndInt16s", argLength: 2, commutative: true}, // ARCH:sve {name: "AndInt16x8", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm {name: "AndInt16x16", argLength: 2, commutative: true}, // ARCH:amd64 {name: "AndInt16x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AndInt32s", argLength: 2, commutative: true}, // ARCH:sve {name: "AndInt32x4", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm {name: "AndInt32x8", argLength: 2, commutative: true}, // ARCH:amd64 {name: "AndInt32x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AndInt64s", argLength: 2, commutative: true}, // ARCH:sve {name: "AndInt64x2", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm {name: "AndInt64x4", argLength: 2, commutative: true}, // ARCH:amd64 {name: "AndInt64x8", argLength: 2, commutative: true}, // ARCH:amd64 @@ -135,15 +145,19 @@ func simdGenericOps() []opData { {name: "AndNotUint64x2", argLength: 2}, // ARCH:amd64,arm64,wasm {name: "AndNotUint64x4", argLength: 2}, // ARCH:amd64 {name: "AndNotUint64x8", argLength: 2}, // ARCH:amd64 + {name: "AndUint8s", argLength: 2, commutative: true}, // ARCH:sve {name: "AndUint8x16", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm {name: "AndUint8x32", argLength: 2, commutative: true}, // ARCH:amd64 {name: "AndUint8x64", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AndUint16s", argLength: 2, commutative: true}, // ARCH:sve {name: "AndUint16x8", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm {name: "AndUint16x16", argLength: 2, commutative: true}, // ARCH:amd64 {name: "AndUint16x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AndUint32s", argLength: 2, commutative: true}, // ARCH:sve {name: "AndUint32x4", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm {name: "AndUint32x8", argLength: 2, commutative: true}, // ARCH:amd64 {name: "AndUint32x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "AndUint64s", argLength: 2, commutative: true}, // ARCH:sve {name: "AndUint64x2", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm {name: "AndUint64x4", argLength: 2, commutative: true}, // ARCH:amd64 {name: "AndUint64x8", argLength: 2, commutative: true}, // ARCH:amd64 @@ -171,8 +185,10 @@ func simdGenericOps() []opData { {name: "BroadcastInt16x8", argLength: 1}, // ARCH:wasm {name: "BroadcastInt32x4", argLength: 1}, // ARCH:wasm {name: "BroadcastInt64x2", argLength: 1}, // ARCH:wasm + {name: "CeilFloat32s", argLength: 1}, // ARCH:sve {name: "CeilFloat32x4", argLength: 1}, // ARCH:amd64,arm64,wasm {name: "CeilFloat32x8", argLength: 1}, // ARCH:amd64 + {name: "CeilFloat64s", argLength: 1}, // ARCH:sve {name: "CeilFloat64x2", argLength: 1}, // ARCH:amd64,arm64,wasm {name: "CeilFloat64x4", argLength: 1}, // ARCH:amd64 {name: "CompressFloat32x4", argLength: 2}, // ARCH:amd64 @@ -351,33 +367,43 @@ func simdGenericOps() []opData { {name: "DotProductPairsSaturatedUint8x16", argLength: 2}, // ARCH:amd64 {name: "DotProductPairsSaturatedUint8x32", argLength: 2}, // ARCH:amd64 {name: "DotProductPairsSaturatedUint8x64", argLength: 2}, // ARCH:amd64 + {name: "EqualFloat32s", argLength: 2, commutative: true}, // ARCH:sve {name: "EqualFloat32x4", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm {name: "EqualFloat32x8", argLength: 2, commutative: true}, // ARCH:amd64 {name: "EqualFloat32x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "EqualFloat64s", argLength: 2, commutative: true}, // ARCH:sve {name: "EqualFloat64x2", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm {name: "EqualFloat64x4", argLength: 2, commutative: true}, // ARCH:amd64 {name: "EqualFloat64x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "EqualInt8s", argLength: 2, commutative: true}, // ARCH:sve {name: "EqualInt8x16", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm {name: "EqualInt8x32", argLength: 2, commutative: true}, // ARCH:amd64 {name: "EqualInt8x64", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "EqualInt16s", argLength: 2, commutative: true}, // ARCH:sve {name: "EqualInt16x8", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm {name: "EqualInt16x16", argLength: 2, commutative: true}, // ARCH:amd64 {name: "EqualInt16x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "EqualInt32s", argLength: 2, commutative: true}, // ARCH:sve {name: "EqualInt32x4", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm {name: "EqualInt32x8", argLength: 2, commutative: true}, // ARCH:amd64 {name: "EqualInt32x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "EqualInt64s", argLength: 2, commutative: true}, // ARCH:sve {name: "EqualInt64x2", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm {name: "EqualInt64x4", argLength: 2, commutative: true}, // ARCH:amd64 {name: "EqualInt64x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "EqualUint8s", argLength: 2, commutative: true}, // ARCH:sve {name: "EqualUint8x16", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm {name: "EqualUint8x32", argLength: 2, commutative: true}, // ARCH:amd64 {name: "EqualUint8x64", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "EqualUint16s", argLength: 2, commutative: true}, // ARCH:sve {name: "EqualUint16x8", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm {name: "EqualUint16x16", argLength: 2, commutative: true}, // ARCH:amd64 {name: "EqualUint16x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "EqualUint32s", argLength: 2, commutative: true}, // ARCH:sve {name: "EqualUint32x4", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm {name: "EqualUint32x8", argLength: 2, commutative: true}, // ARCH:amd64 {name: "EqualUint32x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "EqualUint64s", argLength: 2, commutative: true}, // ARCH:sve {name: "EqualUint64x2", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm {name: "EqualUint64x4", argLength: 2, commutative: true}, // ARCH:amd64 {name: "EqualUint64x8", argLength: 2, commutative: true}, // ARCH:amd64 @@ -453,8 +479,10 @@ func simdGenericOps() []opData { {name: "ExtendToUint64Uint16x8", argLength: 1}, // ARCH:amd64 {name: "ExtendToUint64Uint32x4", argLength: 1}, // ARCH:amd64 {name: "ExtendToUint64Uint32x8", argLength: 1}, // ARCH:amd64 + {name: "FloorFloat32s", argLength: 1}, // ARCH:sve {name: "FloorFloat32x4", argLength: 1}, // ARCH:amd64,arm64,wasm {name: "FloorFloat32x8", argLength: 1}, // ARCH:amd64 + {name: "FloorFloat64s", argLength: 1}, // ARCH:sve {name: "FloorFloat64x2", argLength: 1}, // ARCH:amd64,arm64,wasm {name: "FloorFloat64x4", argLength: 1}, // ARCH:amd64 {name: "GaloisFieldMulUint8x16", argLength: 2}, // ARCH:amd64 @@ -500,31 +528,43 @@ func simdGenericOps() []opData { {name: "GetLoUint32x16", argLength: 1}, // ARCH:amd64 {name: "GetLoUint64x4", argLength: 1}, // ARCH:amd64 {name: "GetLoUint64x8", argLength: 1}, // ARCH:amd64 + {name: "GreaterEqualFloat32s", argLength: 2}, // ARCH:sve {name: "GreaterEqualFloat32x4", argLength: 2}, // ARCH:amd64,arm64,wasm {name: "GreaterEqualFloat32x8", argLength: 2}, // ARCH:amd64 {name: "GreaterEqualFloat32x16", argLength: 2}, // ARCH:amd64 + {name: "GreaterEqualFloat64s", argLength: 2}, // ARCH:sve {name: "GreaterEqualFloat64x2", argLength: 2}, // ARCH:amd64,arm64,wasm {name: "GreaterEqualFloat64x4", argLength: 2}, // ARCH:amd64 {name: "GreaterEqualFloat64x8", argLength: 2}, // ARCH:amd64 + {name: "GreaterEqualInt8s", argLength: 2}, // ARCH:sve {name: "GreaterEqualInt8x16", argLength: 2}, // ARCH:arm64,wasm {name: "GreaterEqualInt8x64", argLength: 2}, // ARCH:amd64 + {name: "GreaterEqualInt16s", argLength: 2}, // ARCH:sve {name: "GreaterEqualInt16x8", argLength: 2}, // ARCH:arm64,wasm {name: "GreaterEqualInt16x32", argLength: 2}, // ARCH:amd64 + {name: "GreaterEqualInt32s", argLength: 2}, // ARCH:sve {name: "GreaterEqualInt32x4", argLength: 2}, // ARCH:arm64,wasm {name: "GreaterEqualInt32x16", argLength: 2}, // ARCH:amd64 + {name: "GreaterEqualInt64s", argLength: 2}, // ARCH:sve {name: "GreaterEqualInt64x2", argLength: 2}, // ARCH:arm64,wasm {name: "GreaterEqualInt64x8", argLength: 2}, // ARCH:amd64 + {name: "GreaterEqualUint8s", argLength: 2}, // ARCH:sve {name: "GreaterEqualUint8x16", argLength: 2}, // ARCH:arm64,wasm {name: "GreaterEqualUint8x64", argLength: 2}, // ARCH:amd64 + {name: "GreaterEqualUint16s", argLength: 2}, // ARCH:sve {name: "GreaterEqualUint16x8", argLength: 2}, // ARCH:arm64,wasm {name: "GreaterEqualUint16x32", argLength: 2}, // ARCH:amd64 + {name: "GreaterEqualUint32s", argLength: 2}, // ARCH:sve {name: "GreaterEqualUint32x4", argLength: 2}, // ARCH:arm64,wasm {name: "GreaterEqualUint32x16", argLength: 2}, // ARCH:amd64 + {name: "GreaterEqualUint64s", argLength: 2}, // ARCH:sve {name: "GreaterEqualUint64x2", argLength: 2}, // ARCH:arm64 {name: "GreaterEqualUint64x8", argLength: 2}, // ARCH:amd64 + {name: "GreaterFloat32s", argLength: 2}, // ARCH:sve {name: "GreaterFloat32x4", argLength: 2}, // ARCH:amd64,arm64,wasm {name: "GreaterFloat32x8", argLength: 2}, // ARCH:amd64 {name: "GreaterFloat32x16", argLength: 2}, // ARCH:amd64 + {name: "GreaterFloat64s", argLength: 2}, // ARCH:sve {name: "GreaterFloat64x2", argLength: 2}, // ARCH:amd64,arm64,wasm {name: "GreaterFloat64x4", argLength: 2}, // ARCH:amd64 {name: "GreaterFloat64x8", argLength: 2}, // ARCH:amd64 @@ -544,12 +584,16 @@ func simdGenericOps() []opData { {name: "GreaterInt64x2", argLength: 2}, // ARCH:amd64,arm64,wasm {name: "GreaterInt64x4", argLength: 2}, // ARCH:amd64 {name: "GreaterInt64x8", argLength: 2}, // ARCH:amd64 + {name: "GreaterUint8s", argLength: 2}, // ARCH:sve {name: "GreaterUint8x16", argLength: 2}, // ARCH:arm64,wasm {name: "GreaterUint8x64", argLength: 2}, // ARCH:amd64 + {name: "GreaterUint16s", argLength: 2}, // ARCH:sve {name: "GreaterUint16x8", argLength: 2}, // ARCH:arm64,wasm {name: "GreaterUint16x32", argLength: 2}, // ARCH:amd64 + {name: "GreaterUint32s", argLength: 2}, // ARCH:sve {name: "GreaterUint32x4", argLength: 2}, // ARCH:arm64,wasm {name: "GreaterUint32x16", argLength: 2}, // ARCH:amd64 + {name: "GreaterUint64s", argLength: 2}, // ARCH:sve {name: "GreaterUint64x2", argLength: 2}, // ARCH:arm64 {name: "GreaterUint64x8", argLength: 2}, // ARCH:amd64 {name: "InterleaveEvenInt8x16", argLength: 2}, // ARCH:arm64 @@ -820,32 +864,48 @@ func simdGenericOps() []opData { {name: "MulWidenLoUint8x16", argLength: 2, commutative: true}, // ARCH:arm64,wasm {name: "MulWidenLoUint16x8", argLength: 2, commutative: true}, // ARCH:arm64,wasm {name: "MulWidenLoUint32x4", argLength: 2, commutative: true}, // ARCH:arm64,wasm + {name: "NegFloat32s", argLength: 1}, // ARCH:sve {name: "NegFloat32x4", argLength: 1}, // ARCH:arm64,wasm + {name: "NegFloat64s", argLength: 1}, // ARCH:sve {name: "NegFloat64x2", argLength: 1}, // ARCH:arm64,wasm + {name: "NegInt8s", argLength: 1}, // ARCH:sve {name: "NegInt8x16", argLength: 1}, // ARCH:arm64,wasm + {name: "NegInt16s", argLength: 1}, // ARCH:sve {name: "NegInt16x8", argLength: 1}, // ARCH:arm64,wasm + {name: "NegInt32s", argLength: 1}, // ARCH:sve {name: "NegInt32x4", argLength: 1}, // ARCH:arm64,wasm + {name: "NegInt64s", argLength: 1}, // ARCH:sve {name: "NegInt64x2", argLength: 1}, // ARCH:arm64,wasm + {name: "NotEqualFloat32s", argLength: 2, commutative: true}, // ARCH:sve {name: "NotEqualFloat32x4", argLength: 2, commutative: true}, // ARCH:amd64,wasm {name: "NotEqualFloat32x8", argLength: 2, commutative: true}, // ARCH:amd64 {name: "NotEqualFloat32x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "NotEqualFloat64s", argLength: 2, commutative: true}, // ARCH:sve {name: "NotEqualFloat64x2", argLength: 2, commutative: true}, // ARCH:amd64,wasm {name: "NotEqualFloat64x4", argLength: 2, commutative: true}, // ARCH:amd64 {name: "NotEqualFloat64x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "NotEqualInt8s", argLength: 2, commutative: true}, // ARCH:sve {name: "NotEqualInt8x16", argLength: 2, commutative: true}, // ARCH:wasm {name: "NotEqualInt8x64", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "NotEqualInt16s", argLength: 2, commutative: true}, // ARCH:sve {name: "NotEqualInt16x8", argLength: 2, commutative: true}, // ARCH:wasm {name: "NotEqualInt16x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "NotEqualInt32s", argLength: 2, commutative: true}, // ARCH:sve {name: "NotEqualInt32x4", argLength: 2, commutative: true}, // ARCH:wasm {name: "NotEqualInt32x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "NotEqualInt64s", argLength: 2, commutative: true}, // ARCH:sve {name: "NotEqualInt64x2", argLength: 2, commutative: true}, // ARCH:wasm {name: "NotEqualInt64x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "NotEqualUint8s", argLength: 2, commutative: true}, // ARCH:sve {name: "NotEqualUint8x16", argLength: 2, commutative: true}, // ARCH:wasm {name: "NotEqualUint8x64", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "NotEqualUint16s", argLength: 2, commutative: true}, // ARCH:sve {name: "NotEqualUint16x8", argLength: 2, commutative: true}, // ARCH:wasm {name: "NotEqualUint16x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "NotEqualUint32s", argLength: 2, commutative: true}, // ARCH:sve {name: "NotEqualUint32x4", argLength: 2, commutative: true}, // ARCH:wasm {name: "NotEqualUint32x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "NotEqualUint64s", argLength: 2, commutative: true}, // ARCH:sve {name: "NotEqualUint64x2", argLength: 2, commutative: true}, // ARCH:wasm {name: "NotEqualUint64x8", argLength: 2, commutative: true}, // ARCH:amd64 {name: "NotInt8x16", argLength: 1}, // ARCH:arm64,wasm @@ -880,15 +940,19 @@ func simdGenericOps() []opData { {name: "OnesCountUint64x2", argLength: 1}, // ARCH:amd64 {name: "OnesCountUint64x4", argLength: 1}, // ARCH:amd64 {name: "OnesCountUint64x8", argLength: 1}, // ARCH:amd64 + {name: "OrInt8s", argLength: 2, commutative: true}, // ARCH:sve {name: "OrInt8x16", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm {name: "OrInt8x32", argLength: 2, commutative: true}, // ARCH:amd64 {name: "OrInt8x64", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "OrInt16s", argLength: 2, commutative: true}, // ARCH:sve {name: "OrInt16x8", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm {name: "OrInt16x16", argLength: 2, commutative: true}, // ARCH:amd64 {name: "OrInt16x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "OrInt32s", argLength: 2, commutative: true}, // ARCH:sve {name: "OrInt32x4", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm {name: "OrInt32x8", argLength: 2, commutative: true}, // ARCH:amd64 {name: "OrInt32x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "OrInt64s", argLength: 2, commutative: true}, // ARCH:sve {name: "OrInt64x2", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm {name: "OrInt64x4", argLength: 2, commutative: true}, // ARCH:amd64 {name: "OrInt64x8", argLength: 2, commutative: true}, // ARCH:amd64 @@ -900,15 +964,19 @@ func simdGenericOps() []opData { {name: "OrNotUint16x8", argLength: 2}, // ARCH:arm64 {name: "OrNotUint32x4", argLength: 2}, // ARCH:arm64 {name: "OrNotUint64x2", argLength: 2}, // ARCH:arm64 + {name: "OrUint8s", argLength: 2, commutative: true}, // ARCH:sve {name: "OrUint8x16", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm {name: "OrUint8x32", argLength: 2, commutative: true}, // ARCH:amd64 {name: "OrUint8x64", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "OrUint16s", argLength: 2, commutative: true}, // ARCH:sve {name: "OrUint16x8", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm {name: "OrUint16x16", argLength: 2, commutative: true}, // ARCH:amd64 {name: "OrUint16x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "OrUint32s", argLength: 2, commutative: true}, // ARCH:sve {name: "OrUint32x4", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm {name: "OrUint32x8", argLength: 2, commutative: true}, // ARCH:amd64 {name: "OrUint32x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "OrUint64s", argLength: 2, commutative: true}, // ARCH:sve {name: "OrUint64x2", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm {name: "OrUint64x4", argLength: 2, commutative: true}, // ARCH:amd64 {name: "OrUint64x8", argLength: 2, commutative: true}, // ARCH:amd64 @@ -994,8 +1062,10 @@ func simdGenericOps() []opData { {name: "RotateRightUint64x2", argLength: 2}, // ARCH:amd64 {name: "RotateRightUint64x4", argLength: 2}, // ARCH:amd64 {name: "RotateRightUint64x8", argLength: 2}, // ARCH:amd64 + {name: "RoundFloat32s", argLength: 1}, // ARCH:sve {name: "RoundFloat32x4", argLength: 1}, // ARCH:amd64,arm64,wasm {name: "RoundFloat32x8", argLength: 1}, // ARCH:amd64 + {name: "RoundFloat64s", argLength: 1}, // ARCH:sve {name: "RoundFloat64x2", argLength: 1}, // ARCH:amd64,arm64,wasm {name: "RoundFloat64x4", argLength: 1}, // ARCH:amd64 {name: "SHA1Message1Uint32x4", argLength: 2}, // ARCH:amd64 @@ -1217,63 +1287,85 @@ func simdGenericOps() []opData { {name: "ShiftUint16x8", argLength: 2}, // ARCH:arm64 {name: "ShiftUint32x4", argLength: 2}, // ARCH:arm64 {name: "ShiftUint64x2", argLength: 2}, // ARCH:arm64 + {name: "SqrtFloat32s", argLength: 1}, // ARCH:sve {name: "SqrtFloat32x4", argLength: 1}, // ARCH:amd64,arm64,wasm {name: "SqrtFloat32x8", argLength: 1}, // ARCH:amd64 {name: "SqrtFloat32x16", argLength: 1}, // ARCH:amd64 + {name: "SqrtFloat64s", argLength: 1}, // ARCH:sve {name: "SqrtFloat64x2", argLength: 1}, // ARCH:amd64,arm64,wasm {name: "SqrtFloat64x4", argLength: 1}, // ARCH:amd64 {name: "SqrtFloat64x8", argLength: 1}, // ARCH:amd64 + {name: "SubFloat32s", argLength: 2}, // ARCH:sve {name: "SubFloat32x4", argLength: 2}, // ARCH:amd64,arm64,wasm {name: "SubFloat32x8", argLength: 2}, // ARCH:amd64 {name: "SubFloat32x16", argLength: 2}, // ARCH:amd64 + {name: "SubFloat64s", argLength: 2}, // ARCH:sve {name: "SubFloat64x2", argLength: 2}, // ARCH:amd64,arm64,wasm {name: "SubFloat64x4", argLength: 2}, // ARCH:amd64 {name: "SubFloat64x8", argLength: 2}, // ARCH:amd64 + {name: "SubInt8s", argLength: 2}, // ARCH:sve {name: "SubInt8x16", argLength: 2}, // ARCH:amd64,arm64,wasm {name: "SubInt8x32", argLength: 2}, // ARCH:amd64 {name: "SubInt8x64", argLength: 2}, // ARCH:amd64 + {name: "SubInt16s", argLength: 2}, // ARCH:sve {name: "SubInt16x8", argLength: 2}, // ARCH:amd64,arm64,wasm {name: "SubInt16x16", argLength: 2}, // ARCH:amd64 {name: "SubInt16x32", argLength: 2}, // ARCH:amd64 + {name: "SubInt32s", argLength: 2}, // ARCH:sve {name: "SubInt32x4", argLength: 2}, // ARCH:amd64,arm64,wasm {name: "SubInt32x8", argLength: 2}, // ARCH:amd64 {name: "SubInt32x16", argLength: 2}, // ARCH:amd64 + {name: "SubInt64s", argLength: 2}, // ARCH:sve {name: "SubInt64x2", argLength: 2}, // ARCH:amd64,arm64,wasm {name: "SubInt64x4", argLength: 2}, // ARCH:amd64 {name: "SubInt64x8", argLength: 2}, // ARCH:amd64 + {name: "SubSaturatedInt8s", argLength: 2}, // ARCH:sve {name: "SubSaturatedInt8x16", argLength: 2}, // ARCH:amd64,arm64,wasm {name: "SubSaturatedInt8x32", argLength: 2}, // ARCH:amd64 {name: "SubSaturatedInt8x64", argLength: 2}, // ARCH:amd64 + {name: "SubSaturatedInt16s", argLength: 2}, // ARCH:sve {name: "SubSaturatedInt16x8", argLength: 2}, // ARCH:amd64,arm64,wasm {name: "SubSaturatedInt16x16", argLength: 2}, // ARCH:amd64 {name: "SubSaturatedInt16x32", argLength: 2}, // ARCH:amd64 + {name: "SubSaturatedInt32s", argLength: 2}, // ARCH:sve {name: "SubSaturatedInt32x4", argLength: 2}, // ARCH:arm64 + {name: "SubSaturatedInt64s", argLength: 2}, // ARCH:sve {name: "SubSaturatedInt64x2", argLength: 2}, // ARCH:arm64 + {name: "SubSaturatedUint8s", argLength: 2}, // ARCH:sve {name: "SubSaturatedUint8x16", argLength: 2}, // ARCH:amd64,arm64,wasm {name: "SubSaturatedUint8x32", argLength: 2}, // ARCH:amd64 {name: "SubSaturatedUint8x64", argLength: 2}, // ARCH:amd64 + {name: "SubSaturatedUint16s", argLength: 2}, // ARCH:sve {name: "SubSaturatedUint16x8", argLength: 2}, // ARCH:amd64,arm64,wasm {name: "SubSaturatedUint16x16", argLength: 2}, // ARCH:amd64 {name: "SubSaturatedUint16x32", argLength: 2}, // ARCH:amd64 + {name: "SubSaturatedUint32s", argLength: 2}, // ARCH:sve {name: "SubSaturatedUint32x4", argLength: 2}, // ARCH:arm64 + {name: "SubSaturatedUint64s", argLength: 2}, // ARCH:sve {name: "SubSaturatedUint64x2", argLength: 2}, // ARCH:arm64 + {name: "SubUint8s", argLength: 2}, // ARCH:sve {name: "SubUint8x16", argLength: 2}, // ARCH:amd64,arm64 {name: "SubUint8x32", argLength: 2}, // ARCH:amd64 {name: "SubUint8x64", argLength: 2}, // ARCH:amd64 + {name: "SubUint16s", argLength: 2}, // ARCH:sve {name: "SubUint16x8", argLength: 2}, // ARCH:amd64,arm64 {name: "SubUint16x16", argLength: 2}, // ARCH:amd64 {name: "SubUint16x32", argLength: 2}, // ARCH:amd64 + {name: "SubUint32s", argLength: 2}, // ARCH:sve {name: "SubUint32x4", argLength: 2}, // ARCH:amd64,arm64 {name: "SubUint32x8", argLength: 2}, // ARCH:amd64 {name: "SubUint32x16", argLength: 2}, // ARCH:amd64 + {name: "SubUint64s", argLength: 2}, // ARCH:sve {name: "SubUint64x2", argLength: 2}, // ARCH:amd64,arm64 {name: "SubUint64x4", argLength: 2}, // ARCH:amd64 {name: "SubUint64x8", argLength: 2}, // ARCH:amd64 {name: "SumOf8AbsDiffUint8x16", argLength: 2}, // ARCH:amd64 {name: "SumOf8AbsDiffUint8x32", argLength: 2}, // ARCH:amd64 {name: "SumOf8AbsDiffUint8x64", argLength: 2}, // ARCH:amd64 + {name: "TruncFloat32s", argLength: 1}, // ARCH:sve {name: "TruncFloat32x4", argLength: 1}, // ARCH:amd64,arm64,wasm {name: "TruncFloat32x8", argLength: 1}, // ARCH:amd64 + {name: "TruncFloat64s", argLength: 1}, // ARCH:sve {name: "TruncFloat64x2", argLength: 1}, // ARCH:amd64,arm64,wasm {name: "TruncFloat64x4", argLength: 1}, // ARCH:amd64 {name: "TruncToInt8Int16x8", argLength: 1}, // ARCH:amd64,arm64 @@ -1312,27 +1404,35 @@ func simdGenericOps() []opData { {name: "TruncToUint32Uint64x2", argLength: 1}, // ARCH:amd64,arm64 {name: "TruncToUint32Uint64x4", argLength: 1}, // ARCH:amd64 {name: "TruncToUint32Uint64x8", argLength: 1}, // ARCH:amd64 + {name: "XorInt8s", argLength: 2, commutative: true}, // ARCH:sve {name: "XorInt8x16", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm {name: "XorInt8x32", argLength: 2, commutative: true}, // ARCH:amd64 {name: "XorInt8x64", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "XorInt16s", argLength: 2, commutative: true}, // ARCH:sve {name: "XorInt16x8", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm {name: "XorInt16x16", argLength: 2, commutative: true}, // ARCH:amd64 {name: "XorInt16x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "XorInt32s", argLength: 2, commutative: true}, // ARCH:sve {name: "XorInt32x4", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm {name: "XorInt32x8", argLength: 2, commutative: true}, // ARCH:amd64 {name: "XorInt32x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "XorInt64s", argLength: 2, commutative: true}, // ARCH:sve {name: "XorInt64x2", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm {name: "XorInt64x4", argLength: 2, commutative: true}, // ARCH:amd64 {name: "XorInt64x8", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "XorUint8s", argLength: 2, commutative: true}, // ARCH:sve {name: "XorUint8x16", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm {name: "XorUint8x32", argLength: 2, commutative: true}, // ARCH:amd64 {name: "XorUint8x64", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "XorUint16s", argLength: 2, commutative: true}, // ARCH:sve {name: "XorUint16x8", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm {name: "XorUint16x16", argLength: 2, commutative: true}, // ARCH:amd64 {name: "XorUint16x32", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "XorUint32s", argLength: 2, commutative: true}, // ARCH:sve {name: "XorUint32x4", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm {name: "XorUint32x8", argLength: 2, commutative: true}, // ARCH:amd64 {name: "XorUint32x16", argLength: 2, commutative: true}, // ARCH:amd64 + {name: "XorUint64s", argLength: 2, commutative: true}, // ARCH:sve {name: "XorUint64x2", argLength: 2, commutative: true}, // ARCH:amd64,arm64,wasm {name: "XorUint64x4", argLength: 2, commutative: true}, // ARCH:amd64 {name: "XorUint64x8", argLength: 2, commutative: true}, // ARCH:amd64 diff --git a/src/cmd/compile/internal/ssa/ssaop/opGen.go b/src/cmd/compile/internal/ssa/ssaop/opGen.go index a1b687e63b8487..7336d86acbf7ad 100644 --- a/src/cmd/compile/internal/ssa/ssaop/opGen.go +++ b/src/cmd/compile/internal/ssa/ssaop/opGen.go @@ -5040,6 +5040,14 @@ const ( OpARM64VUSHR4S OpARM64VUSHR8H OpARM64VUSHR16B + OpARM64ZABSB + OpARM64ZABSD + OpARM64ZABSH + OpARM64ZABSMergingB + OpARM64ZABSMergingD + OpARM64ZABSMergingH + OpARM64ZABSMergingS + OpARM64ZABSS OpARM64ZADDB OpARM64ZADDD OpARM64ZADDH @@ -5052,16 +5060,103 @@ const ( OpARM64ZADDMergingPrefixedS OpARM64ZADDMergingS OpARM64ZADDS + OpARM64ZANDD + OpARM64ZANDMergingB + OpARM64ZANDMergingD + OpARM64ZANDMergingH + OpARM64ZANDMergingPrefixedB + OpARM64ZANDMergingPrefixedD + OpARM64ZANDMergingPrefixedH + OpARM64ZANDMergingPrefixedS + OpARM64ZANDMergingS + OpARM64ZCMPEQB + OpARM64ZCMPEQD + OpARM64ZCMPEQH + OpARM64ZCMPEQS + OpARM64ZCMPGEB + OpARM64ZCMPGED + OpARM64ZCMPGEH + OpARM64ZCMPGES OpARM64ZCMPGTB OpARM64ZCMPGTD OpARM64ZCMPGTH OpARM64ZCMPGTS + OpARM64ZCMPHIB + OpARM64ZCMPHID + OpARM64ZCMPHIH + OpARM64ZCMPHIS + OpARM64ZCMPHSB + OpARM64ZCMPHSD + OpARM64ZCMPHSH + OpARM64ZCMPHSS + OpARM64ZCMPNEB + OpARM64ZCMPNED + OpARM64ZCMPNEH + OpARM64ZCMPNES + OpARM64ZEORD + OpARM64ZEORMergingB + OpARM64ZEORMergingD + OpARM64ZEORMergingH + OpARM64ZEORMergingPrefixedB + OpARM64ZEORMergingPrefixedD + OpARM64ZEORMergingPrefixedH + OpARM64ZEORMergingPrefixedS + OpARM64ZEORMergingS + OpARM64ZFABSD + OpARM64ZFABSMergingD + OpARM64ZFABSMergingS + OpARM64ZFABSS OpARM64ZFADDD OpARM64ZFADDMergingD OpARM64ZFADDMergingPrefixedD OpARM64ZFADDMergingPrefixedS OpARM64ZFADDMergingS OpARM64ZFADDS + OpARM64ZFCMEQD + OpARM64ZFCMEQS + OpARM64ZFCMGED + OpARM64ZFCMGES + OpARM64ZFCMGTD + OpARM64ZFCMGTS + OpARM64ZFCMNED + OpARM64ZFCMNES + OpARM64ZFNEGD + OpARM64ZFNEGMergingD + OpARM64ZFNEGMergingS + OpARM64ZFNEGS + OpARM64ZFRINTMD + OpARM64ZFRINTMS + OpARM64ZFRINTND + OpARM64ZFRINTNS + OpARM64ZFRINTPD + OpARM64ZFRINTPS + OpARM64ZFRINTZD + OpARM64ZFRINTZS + OpARM64ZFSQRTD + OpARM64ZFSQRTMergingD + OpARM64ZFSQRTMergingS + OpARM64ZFSQRTS + OpARM64ZFSUBD + OpARM64ZFSUBMergingD + OpARM64ZFSUBMergingS + OpARM64ZFSUBS + OpARM64ZNEGB + OpARM64ZNEGD + OpARM64ZNEGH + OpARM64ZNEGMergingB + OpARM64ZNEGMergingD + OpARM64ZNEGMergingH + OpARM64ZNEGMergingS + OpARM64ZNEGS + OpARM64ZORRD + OpARM64ZORRMergingB + OpARM64ZORRMergingD + OpARM64ZORRMergingH + OpARM64ZORRMergingPrefixedB + OpARM64ZORRMergingPrefixedD + OpARM64ZORRMergingPrefixedH + OpARM64ZORRMergingPrefixedS + OpARM64ZORRMergingS OpARM64ZSQADDB OpARM64ZSQADDD OpARM64ZSQADDH @@ -5074,6 +5169,22 @@ const ( OpARM64ZSQADDMergingPrefixedS OpARM64ZSQADDMergingS OpARM64ZSQADDS + OpARM64ZSQSUBB + OpARM64ZSQSUBD + OpARM64ZSQSUBH + OpARM64ZSQSUBMergingB + OpARM64ZSQSUBMergingD + OpARM64ZSQSUBMergingH + OpARM64ZSQSUBMergingS + OpARM64ZSQSUBS + OpARM64ZSUBB + OpARM64ZSUBD + OpARM64ZSUBH + OpARM64ZSUBMergingB + OpARM64ZSUBMergingD + OpARM64ZSUBMergingH + OpARM64ZSUBMergingS + OpARM64ZSUBS OpARM64ZUQADDB OpARM64ZUQADDD OpARM64ZUQADDH @@ -5086,6 +5197,14 @@ const ( OpARM64ZUQADDMergingPrefixedS OpARM64ZUQADDMergingS OpARM64ZUQADDS + OpARM64ZUQSUBB + OpARM64ZUQSUBD + OpARM64ZUQSUBH + OpARM64ZUQSUBMergingB + OpARM64ZUQSUBMergingD + OpARM64ZUQSUBMergingH + OpARM64ZUQSUBMergingS + OpARM64ZUQSUBS OpLOONG64NEGV OpLOONG64NEGF @@ -7018,17 +7137,23 @@ const ( OpAESEncryptOneRoundUint8x64 OpAESInvMixColumnsUint32x4 OpAESRoundKeyGenAssistUint32x4 + OpAbsFloat32s OpAbsFloat32x4 + OpAbsFloat64s OpAbsFloat64x2 + OpAbsInt16s OpAbsInt16x16 OpAbsInt16x32 OpAbsInt16x8 + OpAbsInt32s OpAbsInt32x16 OpAbsInt32x4 OpAbsInt32x8 + OpAbsInt64s OpAbsInt64x2 OpAbsInt64x4 OpAbsInt64x8 + OpAbsInt8s OpAbsInt8x16 OpAbsInt8x32 OpAbsInt8x64 @@ -7100,15 +7225,19 @@ const ( OpAddUint8x16 OpAddUint8x32 OpAddUint8x64 + OpAndInt16s OpAndInt16x16 OpAndInt16x32 OpAndInt16x8 + OpAndInt32s OpAndInt32x16 OpAndInt32x4 OpAndInt32x8 + OpAndInt64s OpAndInt64x2 OpAndInt64x4 OpAndInt64x8 + OpAndInt8s OpAndInt8x16 OpAndInt8x32 OpAndInt8x64 @@ -7136,15 +7265,19 @@ const ( OpAndNotUint8x16 OpAndNotUint8x32 OpAndNotUint8x64 + OpAndUint16s OpAndUint16x16 OpAndUint16x32 OpAndUint16x8 + OpAndUint32s OpAndUint32x16 OpAndUint32x4 OpAndUint32x8 + OpAndUint64s OpAndUint64x2 OpAndUint64x4 OpAndUint64x8 + OpAndUint8s OpAndUint8x16 OpAndUint8x32 OpAndUint8x64 @@ -7172,8 +7305,10 @@ const ( OpBroadcastInt32x4 OpBroadcastInt64x2 OpBroadcastInt8x16 + OpCeilFloat32s OpCeilFloat32x4 OpCeilFloat32x8 + OpCeilFloat64s OpCeilFloat64x2 OpCeilFloat64x4 OpCeilScaledFloat32x16 @@ -7377,33 +7512,43 @@ const ( OpDotProductPairsSaturatedUint8x16 OpDotProductPairsSaturatedUint8x32 OpDotProductPairsSaturatedUint8x64 + OpEqualFloat32s OpEqualFloat32x16 OpEqualFloat32x4 OpEqualFloat32x8 + OpEqualFloat64s OpEqualFloat64x2 OpEqualFloat64x4 OpEqualFloat64x8 + OpEqualInt16s OpEqualInt16x16 OpEqualInt16x32 OpEqualInt16x8 + OpEqualInt32s OpEqualInt32x16 OpEqualInt32x4 OpEqualInt32x8 + OpEqualInt64s OpEqualInt64x2 OpEqualInt64x4 OpEqualInt64x8 + OpEqualInt8s OpEqualInt8x16 OpEqualInt8x32 OpEqualInt8x64 + OpEqualUint16s OpEqualUint16x16 OpEqualUint16x32 OpEqualUint16x8 + OpEqualUint32s OpEqualUint32x16 OpEqualUint32x4 OpEqualUint32x8 + OpEqualUint64s OpEqualUint64x2 OpEqualUint64x4 OpEqualUint64x8 + OpEqualUint8s OpEqualUint8x16 OpEqualUint8x32 OpEqualUint8x64 @@ -7479,8 +7624,10 @@ const ( OpExtendToUint64Uint16x8 OpExtendToUint64Uint32x4 OpExtendToUint64Uint32x8 + OpFloorFloat32s OpFloorFloat32x4 OpFloorFloat32x8 + OpFloorFloat64s OpFloorFloat64x2 OpFloorFloat64x4 OpFloorScaledFloat32x16 @@ -7554,31 +7701,43 @@ const ( OpGetLoUint64x8 OpGetLoUint8x32 OpGetLoUint8x64 + OpGreaterEqualFloat32s OpGreaterEqualFloat32x16 OpGreaterEqualFloat32x4 OpGreaterEqualFloat32x8 + OpGreaterEqualFloat64s OpGreaterEqualFloat64x2 OpGreaterEqualFloat64x4 OpGreaterEqualFloat64x8 + OpGreaterEqualInt16s OpGreaterEqualInt16x32 OpGreaterEqualInt16x8 + OpGreaterEqualInt32s OpGreaterEqualInt32x16 OpGreaterEqualInt32x4 + OpGreaterEqualInt64s OpGreaterEqualInt64x2 OpGreaterEqualInt64x8 + OpGreaterEqualInt8s OpGreaterEqualInt8x16 OpGreaterEqualInt8x64 + OpGreaterEqualUint16s OpGreaterEqualUint16x32 OpGreaterEqualUint16x8 + OpGreaterEqualUint32s OpGreaterEqualUint32x16 OpGreaterEqualUint32x4 + OpGreaterEqualUint64s OpGreaterEqualUint64x2 OpGreaterEqualUint64x8 + OpGreaterEqualUint8s OpGreaterEqualUint8x16 OpGreaterEqualUint8x64 + OpGreaterFloat32s OpGreaterFloat32x16 OpGreaterFloat32x4 OpGreaterFloat32x8 + OpGreaterFloat64s OpGreaterFloat64x2 OpGreaterFloat64x4 OpGreaterFloat64x8 @@ -7598,12 +7757,16 @@ const ( OpGreaterInt8x16 OpGreaterInt8x32 OpGreaterInt8x64 + OpGreaterUint16s OpGreaterUint16x32 OpGreaterUint16x8 + OpGreaterUint32s OpGreaterUint32x16 OpGreaterUint32x4 + OpGreaterUint64s OpGreaterUint64x2 OpGreaterUint64x8 + OpGreaterUint8s OpGreaterUint8x16 OpGreaterUint8x64 OpInterleaveEvenInt16x8 @@ -7874,32 +8037,48 @@ const ( OpMulWidenLoUint16x8 OpMulWidenLoUint32x4 OpMulWidenLoUint8x16 + OpNegFloat32s OpNegFloat32x4 + OpNegFloat64s OpNegFloat64x2 + OpNegInt16s OpNegInt16x8 + OpNegInt32s OpNegInt32x4 + OpNegInt64s OpNegInt64x2 + OpNegInt8s OpNegInt8x16 + OpNotEqualFloat32s OpNotEqualFloat32x16 OpNotEqualFloat32x4 OpNotEqualFloat32x8 + OpNotEqualFloat64s OpNotEqualFloat64x2 OpNotEqualFloat64x4 OpNotEqualFloat64x8 + OpNotEqualInt16s OpNotEqualInt16x32 OpNotEqualInt16x8 + OpNotEqualInt32s OpNotEqualInt32x16 OpNotEqualInt32x4 + OpNotEqualInt64s OpNotEqualInt64x2 OpNotEqualInt64x8 + OpNotEqualInt8s OpNotEqualInt8x16 OpNotEqualInt8x64 + OpNotEqualUint16s OpNotEqualUint16x32 OpNotEqualUint16x8 + OpNotEqualUint32s OpNotEqualUint32x16 OpNotEqualUint32x4 + OpNotEqualUint64s OpNotEqualUint64x2 OpNotEqualUint64x8 + OpNotEqualUint8s OpNotEqualUint8x16 OpNotEqualUint8x64 OpNotInt16x8 @@ -7934,15 +8113,19 @@ const ( OpOnesCountUint8x16 OpOnesCountUint8x32 OpOnesCountUint8x64 + OpOrInt16s OpOrInt16x16 OpOrInt16x32 OpOrInt16x8 + OpOrInt32s OpOrInt32x16 OpOrInt32x4 OpOrInt32x8 + OpOrInt64s OpOrInt64x2 OpOrInt64x4 OpOrInt64x8 + OpOrInt8s OpOrInt8x16 OpOrInt8x32 OpOrInt8x64 @@ -7954,15 +8137,19 @@ const ( OpOrNotUint32x4 OpOrNotUint64x2 OpOrNotUint8x16 + OpOrUint16s OpOrUint16x16 OpOrUint16x32 OpOrUint16x8 + OpOrUint32s OpOrUint32x16 OpOrUint32x4 OpOrUint32x8 + OpOrUint64s OpOrUint64x2 OpOrUint64x4 OpOrUint64x8 + OpOrUint8s OpOrUint8x16 OpOrUint8x32 OpOrUint8x64 @@ -8048,8 +8235,10 @@ const ( OpRotateRightUint64x2 OpRotateRightUint64x4 OpRotateRightUint64x8 + OpRoundFloat32s OpRoundFloat32x4 OpRoundFloat32x8 + OpRoundFloat64s OpRoundFloat64x2 OpRoundFloat64x4 OpRoundScaledFloat32x16 @@ -8330,63 +8519,85 @@ const ( OpShiftUint32x4 OpShiftUint64x2 OpShiftUint8x16 + OpSqrtFloat32s OpSqrtFloat32x16 OpSqrtFloat32x4 OpSqrtFloat32x8 + OpSqrtFloat64s OpSqrtFloat64x2 OpSqrtFloat64x4 OpSqrtFloat64x8 + OpSubFloat32s OpSubFloat32x16 OpSubFloat32x4 OpSubFloat32x8 + OpSubFloat64s OpSubFloat64x2 OpSubFloat64x4 OpSubFloat64x8 + OpSubInt16s OpSubInt16x16 OpSubInt16x32 OpSubInt16x8 + OpSubInt32s OpSubInt32x16 OpSubInt32x4 OpSubInt32x8 + OpSubInt64s OpSubInt64x2 OpSubInt64x4 OpSubInt64x8 + OpSubInt8s OpSubInt8x16 OpSubInt8x32 OpSubInt8x64 + OpSubSaturatedInt16s OpSubSaturatedInt16x16 OpSubSaturatedInt16x32 OpSubSaturatedInt16x8 + OpSubSaturatedInt32s OpSubSaturatedInt32x4 + OpSubSaturatedInt64s OpSubSaturatedInt64x2 + OpSubSaturatedInt8s OpSubSaturatedInt8x16 OpSubSaturatedInt8x32 OpSubSaturatedInt8x64 + OpSubSaturatedUint16s OpSubSaturatedUint16x16 OpSubSaturatedUint16x32 OpSubSaturatedUint16x8 + OpSubSaturatedUint32s OpSubSaturatedUint32x4 + OpSubSaturatedUint64s OpSubSaturatedUint64x2 + OpSubSaturatedUint8s OpSubSaturatedUint8x16 OpSubSaturatedUint8x32 OpSubSaturatedUint8x64 + OpSubUint16s OpSubUint16x16 OpSubUint16x32 OpSubUint16x8 + OpSubUint32s OpSubUint32x16 OpSubUint32x4 OpSubUint32x8 + OpSubUint64s OpSubUint64x2 OpSubUint64x4 OpSubUint64x8 + OpSubUint8s OpSubUint8x16 OpSubUint8x32 OpSubUint8x64 OpSumOf8AbsDiffUint8x16 OpSumOf8AbsDiffUint8x32 OpSumOf8AbsDiffUint8x64 + OpTruncFloat32s OpTruncFloat32x4 OpTruncFloat32x8 + OpTruncFloat64s OpTruncFloat64x2 OpTruncFloat64x4 OpTruncScaledFloat32x16 @@ -8437,27 +8648,35 @@ const ( OpTruncToUint8Uint64x2 OpTruncToUint8Uint64x4 OpTruncToUint8Uint64x8 + OpXorInt16s OpXorInt16x16 OpXorInt16x32 OpXorInt16x8 + OpXorInt32s OpXorInt32x16 OpXorInt32x4 OpXorInt32x8 + OpXorInt64s OpXorInt64x2 OpXorInt64x4 OpXorInt64x8 + OpXorInt8s OpXorInt8x16 OpXorInt8x32 OpXorInt8x64 + OpXorUint16s OpXorUint16x16 OpXorUint16x32 OpXorUint16x8 + OpXorUint32s OpXorUint32x16 OpXorUint32x4 OpXorUint32x8 + OpXorUint64s OpXorUint64x2 OpXorUint64x4 OpXorUint64x8 + OpXorUint8s OpXorUint8x16 OpXorUint8x32 OpXorUint8x64 @@ -85678,6 +85897,126 @@ var OpcodeTable = [...]OpInfo{ }, }, }, + { + Name: "ZABSB", + ArgLen: 2, + asm: arm64.AZABS, + Reg: RegInfo{ + Inputs: []InputInfo{ + {1, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZABSD", + ArgLen: 2, + asm: arm64.AZABS, + Reg: RegInfo{ + Inputs: []InputInfo{ + {1, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZABSH", + ArgLen: 2, + asm: arm64.AZABS, + Reg: RegInfo{ + Inputs: []InputInfo{ + {1, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZABSMergingB", + ArgLen: 3, + ResultInArg0: true, + asm: arm64.AZABS, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZABSMergingD", + ArgLen: 3, + ResultInArg0: true, + asm: arm64.AZABS, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZABSMergingH", + ArgLen: 3, + ResultInArg0: true, + asm: arm64.AZABS, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZABSMergingS", + ArgLen: 3, + ResultInArg0: true, + asm: arm64.AZABS, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZABSS", + ArgLen: 2, + asm: arm64.AZABS, + Reg: RegInfo{ + Inputs: []InputInfo{ + {1, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, { Name: "ZADDB", ArgLen: 2, @@ -85870,6 +86209,277 @@ var OpcodeTable = [...]OpInfo{ }, }, }, + { + Name: "ZANDD", + ArgLen: 2, + Commutative: true, + asm: arm64.AZAND, + Reg: RegInfo{ + Inputs: []InputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZANDMergingB", + ArgLen: 3, + Commutative: true, + asm: arm64.AZAND, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZANDMergingD", + ArgLen: 3, + Commutative: true, + asm: arm64.AZAND, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZANDMergingH", + ArgLen: 3, + Commutative: true, + asm: arm64.AZAND, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZANDMergingPrefixedB", + ArgLen: 4, + ResultInArg0: true, + asm: arm64.AZAND, + Reg: RegInfo{ + Inputs: []InputInfo{ + {3, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZANDMergingPrefixedD", + ArgLen: 4, + ResultInArg0: true, + asm: arm64.AZAND, + Reg: RegInfo{ + Inputs: []InputInfo{ + {3, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZANDMergingPrefixedH", + ArgLen: 4, + ResultInArg0: true, + asm: arm64.AZAND, + Reg: RegInfo{ + Inputs: []InputInfo{ + {3, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZANDMergingPrefixedS", + ArgLen: 4, + ResultInArg0: true, + asm: arm64.AZAND, + Reg: RegInfo{ + Inputs: []InputInfo{ + {3, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZANDMergingS", + ArgLen: 3, + Commutative: true, + asm: arm64.AZAND, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZCMPEQB", + ArgLen: 3, + Commutative: true, + asm: arm64.AZCMPEQ, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + }, + }, + }, + { + Name: "ZCMPEQD", + ArgLen: 3, + Commutative: true, + asm: arm64.AZCMPEQ, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + }, + }, + }, + { + Name: "ZCMPEQH", + ArgLen: 3, + Commutative: true, + asm: arm64.AZCMPEQ, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + }, + }, + }, + { + Name: "ZCMPEQS", + ArgLen: 3, + Commutative: true, + asm: arm64.AZCMPEQ, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + }, + }, + }, + { + Name: "ZCMPGEB", + ArgLen: 3, + asm: arm64.AZCMPGE, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + }, + }, + }, + { + Name: "ZCMPGED", + ArgLen: 3, + asm: arm64.AZCMPGE, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + }, + }, + }, + { + Name: "ZCMPGEH", + ArgLen: 3, + asm: arm64.AZCMPGE, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + }, + }, + }, + { + Name: "ZCMPGES", + ArgLen: 3, + asm: arm64.AZCMPGE, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + }, + }, + }, { Name: "ZCMPGTB", ArgLen: 3, @@ -85931,25 +86541,24 @@ var OpcodeTable = [...]OpInfo{ }, }, { - Name: "ZFADDD", - ArgLen: 2, - Commutative: true, - asm: arm64.AZFADD, + Name: "ZCMPHIB", + ArgLen: 3, + asm: arm64.AZCMPHI, Reg: RegInfo{ Inputs: []InputInfo{ - {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, Outputs: []OutputInfo{ - {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 }, }, }, { - Name: "ZFADDMergingD", - ArgLen: 3, - Commutative: true, - asm: arm64.AZFADD, + Name: "ZCMPHID", + ArgLen: 3, + asm: arm64.AZCMPHI, Reg: RegInfo{ Inputs: []InputInfo{ {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 @@ -85957,49 +86566,105 @@ var OpcodeTable = [...]OpInfo{ {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, Outputs: []OutputInfo{ - {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 }, }, }, { - Name: "ZFADDMergingPrefixedD", - ArgLen: 4, - ResultInArg0: true, - asm: arm64.AZFADD, + Name: "ZCMPHIH", + ArgLen: 3, + asm: arm64.AZCMPHI, Reg: RegInfo{ Inputs: []InputInfo{ - {3, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, Outputs: []OutputInfo{ - {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 }, }, }, { - Name: "ZFADDMergingPrefixedS", - ArgLen: 4, - ResultInArg0: true, - asm: arm64.AZFADD, + Name: "ZCMPHIS", + ArgLen: 3, + asm: arm64.AZCMPHI, Reg: RegInfo{ Inputs: []InputInfo{ - {3, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, Outputs: []OutputInfo{ - {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 }, }, }, { - Name: "ZFADDMergingS", + Name: "ZCMPHSB", + ArgLen: 3, + asm: arm64.AZCMPHS, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + }, + }, + }, + { + Name: "ZCMPHSD", + ArgLen: 3, + asm: arm64.AZCMPHS, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + }, + }, + }, + { + Name: "ZCMPHSH", + ArgLen: 3, + asm: arm64.AZCMPHS, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + }, + }, + }, + { + Name: "ZCMPHSS", + ArgLen: 3, + asm: arm64.AZCMPHS, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + }, + }, + }, + { + Name: "ZCMPNEB", ArgLen: 3, Commutative: true, - asm: arm64.AZFADD, + asm: arm64.AZCMPNE, Reg: RegInfo{ Inputs: []InputInfo{ {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 @@ -86007,60 +86672,63 @@ var OpcodeTable = [...]OpInfo{ {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, Outputs: []OutputInfo{ - {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 }, }, }, { - Name: "ZFADDS", - ArgLen: 2, + Name: "ZCMPNED", + ArgLen: 3, Commutative: true, - asm: arm64.AZFADD, + asm: arm64.AZCMPNE, Reg: RegInfo{ Inputs: []InputInfo{ - {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, Outputs: []OutputInfo{ - {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 }, }, }, { - Name: "ZSQADDB", - ArgLen: 2, + Name: "ZCMPNEH", + ArgLen: 3, Commutative: true, - asm: arm64.AZSQADD, + asm: arm64.AZCMPNE, Reg: RegInfo{ Inputs: []InputInfo{ - {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, Outputs: []OutputInfo{ - {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 }, }, }, { - Name: "ZSQADDD", - ArgLen: 2, + Name: "ZCMPNES", + ArgLen: 3, Commutative: true, - asm: arm64.AZSQADD, + asm: arm64.AZCMPNE, Reg: RegInfo{ Inputs: []InputInfo{ - {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, Outputs: []OutputInfo{ - {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 }, }, }, { - Name: "ZSQADDH", + Name: "ZEORD", ArgLen: 2, Commutative: true, - asm: arm64.AZSQADD, + asm: arm64.AZEOR, Reg: RegInfo{ Inputs: []InputInfo{ {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 @@ -86072,10 +86740,10 @@ var OpcodeTable = [...]OpInfo{ }, }, { - Name: "ZSQADDMergingB", + Name: "ZEORMergingB", ArgLen: 3, Commutative: true, - asm: arm64.AZSQADD, + asm: arm64.AZEOR, Reg: RegInfo{ Inputs: []InputInfo{ {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 @@ -86088,10 +86756,10 @@ var OpcodeTable = [...]OpInfo{ }, }, { - Name: "ZSQADDMergingD", + Name: "ZEORMergingD", ArgLen: 3, Commutative: true, - asm: arm64.AZSQADD, + asm: arm64.AZEOR, Reg: RegInfo{ Inputs: []InputInfo{ {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 @@ -86104,10 +86772,10 @@ var OpcodeTable = [...]OpInfo{ }, }, { - Name: "ZSQADDMergingH", + Name: "ZEORMergingH", ArgLen: 3, Commutative: true, - asm: arm64.AZSQADD, + asm: arm64.AZEOR, Reg: RegInfo{ Inputs: []InputInfo{ {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 @@ -86120,10 +86788,10 @@ var OpcodeTable = [...]OpInfo{ }, }, { - Name: "ZSQADDMergingPrefixedB", + Name: "ZEORMergingPrefixedB", ArgLen: 4, ResultInArg0: true, - asm: arm64.AZSQADD, + asm: arm64.AZEOR, Reg: RegInfo{ Inputs: []InputInfo{ {3, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 @@ -86137,10 +86805,10 @@ var OpcodeTable = [...]OpInfo{ }, }, { - Name: "ZSQADDMergingPrefixedD", + Name: "ZEORMergingPrefixedD", ArgLen: 4, ResultInArg0: true, - asm: arm64.AZSQADD, + asm: arm64.AZEOR, Reg: RegInfo{ Inputs: []InputInfo{ {3, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 @@ -86154,10 +86822,10 @@ var OpcodeTable = [...]OpInfo{ }, }, { - Name: "ZSQADDMergingPrefixedH", + Name: "ZEORMergingPrefixedH", ArgLen: 4, ResultInArg0: true, - asm: arm64.AZSQADD, + asm: arm64.AZEOR, Reg: RegInfo{ Inputs: []InputInfo{ {3, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 @@ -86171,10 +86839,10 @@ var OpcodeTable = [...]OpInfo{ }, }, { - Name: "ZSQADDMergingPrefixedS", + Name: "ZEORMergingPrefixedS", ArgLen: 4, ResultInArg0: true, - asm: arm64.AZSQADD, + asm: arm64.AZEOR, Reg: RegInfo{ Inputs: []InputInfo{ {3, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 @@ -86188,10 +86856,10 @@ var OpcodeTable = [...]OpInfo{ }, }, { - Name: "ZSQADDMergingS", + Name: "ZEORMergingS", ArgLen: 3, Commutative: true, - asm: arm64.AZSQADD, + asm: arm64.AZEOR, Reg: RegInfo{ Inputs: []InputInfo{ {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 @@ -86204,10 +86872,1266 @@ var OpcodeTable = [...]OpInfo{ }, }, { - Name: "ZSQADDS", - ArgLen: 2, - Commutative: true, - asm: arm64.AZSQADD, + Name: "ZFABSD", + ArgLen: 2, + asm: arm64.AZFABS, + Reg: RegInfo{ + Inputs: []InputInfo{ + {1, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZFABSMergingD", + ArgLen: 3, + ResultInArg0: true, + asm: arm64.AZFABS, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZFABSMergingS", + ArgLen: 3, + ResultInArg0: true, + asm: arm64.AZFABS, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZFABSS", + ArgLen: 2, + asm: arm64.AZFABS, + Reg: RegInfo{ + Inputs: []InputInfo{ + {1, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZFADDD", + ArgLen: 2, + Commutative: true, + asm: arm64.AZFADD, + Reg: RegInfo{ + Inputs: []InputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZFADDMergingD", + ArgLen: 3, + Commutative: true, + asm: arm64.AZFADD, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZFADDMergingPrefixedD", + ArgLen: 4, + ResultInArg0: true, + asm: arm64.AZFADD, + Reg: RegInfo{ + Inputs: []InputInfo{ + {3, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZFADDMergingPrefixedS", + ArgLen: 4, + ResultInArg0: true, + asm: arm64.AZFADD, + Reg: RegInfo{ + Inputs: []InputInfo{ + {3, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZFADDMergingS", + ArgLen: 3, + Commutative: true, + asm: arm64.AZFADD, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZFADDS", + ArgLen: 2, + Commutative: true, + asm: arm64.AZFADD, + Reg: RegInfo{ + Inputs: []InputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZFCMEQD", + ArgLen: 3, + Commutative: true, + asm: arm64.AZFCMEQ, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + }, + }, + }, + { + Name: "ZFCMEQS", + ArgLen: 3, + Commutative: true, + asm: arm64.AZFCMEQ, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + }, + }, + }, + { + Name: "ZFCMGED", + ArgLen: 3, + asm: arm64.AZFCMGE, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + }, + }, + }, + { + Name: "ZFCMGES", + ArgLen: 3, + asm: arm64.AZFCMGE, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + }, + }, + }, + { + Name: "ZFCMGTD", + ArgLen: 3, + asm: arm64.AZFCMGT, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + }, + }, + }, + { + Name: "ZFCMGTS", + ArgLen: 3, + asm: arm64.AZFCMGT, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + }, + }, + }, + { + Name: "ZFCMNED", + ArgLen: 3, + Commutative: true, + asm: arm64.AZFCMNE, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + }, + }, + }, + { + Name: "ZFCMNES", + ArgLen: 3, + Commutative: true, + asm: arm64.AZFCMNE, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + }, + }, + }, + { + Name: "ZFNEGD", + ArgLen: 2, + asm: arm64.AZFNEG, + Reg: RegInfo{ + Inputs: []InputInfo{ + {1, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZFNEGMergingD", + ArgLen: 3, + ResultInArg0: true, + asm: arm64.AZFNEG, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZFNEGMergingS", + ArgLen: 3, + ResultInArg0: true, + asm: arm64.AZFNEG, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZFNEGS", + ArgLen: 2, + asm: arm64.AZFNEG, + Reg: RegInfo{ + Inputs: []InputInfo{ + {1, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZFRINTMD", + ArgLen: 2, + asm: arm64.AZFRINTM, + Reg: RegInfo{ + Inputs: []InputInfo{ + {1, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZFRINTMS", + ArgLen: 2, + asm: arm64.AZFRINTM, + Reg: RegInfo{ + Inputs: []InputInfo{ + {1, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZFRINTND", + ArgLen: 2, + asm: arm64.AZFRINTN, + Reg: RegInfo{ + Inputs: []InputInfo{ + {1, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZFRINTNS", + ArgLen: 2, + asm: arm64.AZFRINTN, + Reg: RegInfo{ + Inputs: []InputInfo{ + {1, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZFRINTPD", + ArgLen: 2, + asm: arm64.AZFRINTP, + Reg: RegInfo{ + Inputs: []InputInfo{ + {1, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZFRINTPS", + ArgLen: 2, + asm: arm64.AZFRINTP, + Reg: RegInfo{ + Inputs: []InputInfo{ + {1, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZFRINTZD", + ArgLen: 2, + asm: arm64.AZFRINTZ, + Reg: RegInfo{ + Inputs: []InputInfo{ + {1, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZFRINTZS", + ArgLen: 2, + asm: arm64.AZFRINTZ, + Reg: RegInfo{ + Inputs: []InputInfo{ + {1, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZFSQRTD", + ArgLen: 2, + asm: arm64.AZFSQRT, + Reg: RegInfo{ + Inputs: []InputInfo{ + {1, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZFSQRTMergingD", + ArgLen: 3, + ResultInArg0: true, + asm: arm64.AZFSQRT, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZFSQRTMergingS", + ArgLen: 3, + ResultInArg0: true, + asm: arm64.AZFSQRT, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZFSQRTS", + ArgLen: 2, + asm: arm64.AZFSQRT, + Reg: RegInfo{ + Inputs: []InputInfo{ + {1, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZFSUBD", + ArgLen: 2, + asm: arm64.AZFSUB, + Reg: RegInfo{ + Inputs: []InputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZFSUBMergingD", + ArgLen: 3, + ResultInArg0: true, + asm: arm64.AZFSUB, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZFSUBMergingS", + ArgLen: 3, + ResultInArg0: true, + asm: arm64.AZFSUB, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZFSUBS", + ArgLen: 2, + asm: arm64.AZFSUB, + Reg: RegInfo{ + Inputs: []InputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZNEGB", + ArgLen: 2, + asm: arm64.AZNEG, + Reg: RegInfo{ + Inputs: []InputInfo{ + {1, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZNEGD", + ArgLen: 2, + asm: arm64.AZNEG, + Reg: RegInfo{ + Inputs: []InputInfo{ + {1, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZNEGH", + ArgLen: 2, + asm: arm64.AZNEG, + Reg: RegInfo{ + Inputs: []InputInfo{ + {1, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZNEGMergingB", + ArgLen: 3, + ResultInArg0: true, + asm: arm64.AZNEG, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZNEGMergingD", + ArgLen: 3, + ResultInArg0: true, + asm: arm64.AZNEG, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZNEGMergingH", + ArgLen: 3, + ResultInArg0: true, + asm: arm64.AZNEG, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZNEGMergingS", + ArgLen: 3, + ResultInArg0: true, + asm: arm64.AZNEG, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZNEGS", + ArgLen: 2, + asm: arm64.AZNEG, + Reg: RegInfo{ + Inputs: []InputInfo{ + {1, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZORRD", + ArgLen: 2, + Commutative: true, + asm: arm64.AZORR, + Reg: RegInfo{ + Inputs: []InputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZORRMergingB", + ArgLen: 3, + Commutative: true, + asm: arm64.AZORR, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZORRMergingD", + ArgLen: 3, + Commutative: true, + asm: arm64.AZORR, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZORRMergingH", + ArgLen: 3, + Commutative: true, + asm: arm64.AZORR, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZORRMergingPrefixedB", + ArgLen: 4, + ResultInArg0: true, + asm: arm64.AZORR, + Reg: RegInfo{ + Inputs: []InputInfo{ + {3, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZORRMergingPrefixedD", + ArgLen: 4, + ResultInArg0: true, + asm: arm64.AZORR, + Reg: RegInfo{ + Inputs: []InputInfo{ + {3, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZORRMergingPrefixedH", + ArgLen: 4, + ResultInArg0: true, + asm: arm64.AZORR, + Reg: RegInfo{ + Inputs: []InputInfo{ + {3, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZORRMergingPrefixedS", + ArgLen: 4, + ResultInArg0: true, + asm: arm64.AZORR, + Reg: RegInfo{ + Inputs: []InputInfo{ + {3, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZORRMergingS", + ArgLen: 3, + Commutative: true, + asm: arm64.AZORR, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZSQADDB", + ArgLen: 2, + Commutative: true, + asm: arm64.AZSQADD, + Reg: RegInfo{ + Inputs: []InputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZSQADDD", + ArgLen: 2, + Commutative: true, + asm: arm64.AZSQADD, + Reg: RegInfo{ + Inputs: []InputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZSQADDH", + ArgLen: 2, + Commutative: true, + asm: arm64.AZSQADD, + Reg: RegInfo{ + Inputs: []InputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZSQADDMergingB", + ArgLen: 3, + Commutative: true, + asm: arm64.AZSQADD, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZSQADDMergingD", + ArgLen: 3, + Commutative: true, + asm: arm64.AZSQADD, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZSQADDMergingH", + ArgLen: 3, + Commutative: true, + asm: arm64.AZSQADD, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZSQADDMergingPrefixedB", + ArgLen: 4, + ResultInArg0: true, + asm: arm64.AZSQADD, + Reg: RegInfo{ + Inputs: []InputInfo{ + {3, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZSQADDMergingPrefixedD", + ArgLen: 4, + ResultInArg0: true, + asm: arm64.AZSQADD, + Reg: RegInfo{ + Inputs: []InputInfo{ + {3, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZSQADDMergingPrefixedH", + ArgLen: 4, + ResultInArg0: true, + asm: arm64.AZSQADD, + Reg: RegInfo{ + Inputs: []InputInfo{ + {3, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZSQADDMergingPrefixedS", + ArgLen: 4, + ResultInArg0: true, + asm: arm64.AZSQADD, + Reg: RegInfo{ + Inputs: []InputInfo{ + {3, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZSQADDMergingS", + ArgLen: 3, + Commutative: true, + asm: arm64.AZSQADD, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZSQADDS", + ArgLen: 2, + Commutative: true, + asm: arm64.AZSQADD, + Reg: RegInfo{ + Inputs: []InputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZSQSUBB", + ArgLen: 2, + asm: arm64.AZSQSUB, + Reg: RegInfo{ + Inputs: []InputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZSQSUBD", + ArgLen: 2, + asm: arm64.AZSQSUB, + Reg: RegInfo{ + Inputs: []InputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZSQSUBH", + ArgLen: 2, + asm: arm64.AZSQSUB, + Reg: RegInfo{ + Inputs: []InputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZSQSUBMergingB", + ArgLen: 3, + ResultInArg0: true, + asm: arm64.AZSQSUB, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZSQSUBMergingD", + ArgLen: 3, + ResultInArg0: true, + asm: arm64.AZSQSUB, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZSQSUBMergingH", + ArgLen: 3, + ResultInArg0: true, + asm: arm64.AZSQSUB, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZSQSUBMergingS", + ArgLen: 3, + ResultInArg0: true, + asm: arm64.AZSQSUB, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZSQSUBS", + ArgLen: 2, + asm: arm64.AZSQSUB, + Reg: RegInfo{ + Inputs: []InputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZSUBB", + ArgLen: 2, + asm: arm64.AZSUB, + Reg: RegInfo{ + Inputs: []InputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZSUBD", + ArgLen: 2, + asm: arm64.AZSUB, + Reg: RegInfo{ + Inputs: []InputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZSUBH", + ArgLen: 2, + asm: arm64.AZSUB, + Reg: RegInfo{ + Inputs: []InputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZSUBMergingB", + ArgLen: 3, + ResultInArg0: true, + asm: arm64.AZSUB, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZSUBMergingD", + ArgLen: 3, + ResultInArg0: true, + asm: arm64.AZSUB, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZSUBMergingH", + ArgLen: 3, + ResultInArg0: true, + asm: arm64.AZSUB, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZSUBMergingS", + ArgLen: 3, + ResultInArg0: true, + asm: arm64.AZSUB, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZSUBS", + ArgLen: 2, + asm: arm64.AZSUB, Reg: RegInfo{ Inputs: []InputInfo{ {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 @@ -86410,6 +88334,126 @@ var OpcodeTable = [...]OpInfo{ }, }, }, + { + Name: "ZUQSUBB", + ArgLen: 2, + asm: arm64.AZUQSUB, + Reg: RegInfo{ + Inputs: []InputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZUQSUBD", + ArgLen: 2, + asm: arm64.AZUQSUB, + Reg: RegInfo{ + Inputs: []InputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZUQSUBH", + ArgLen: 2, + asm: arm64.AZUQSUB, + Reg: RegInfo{ + Inputs: []InputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZUQSUBMergingB", + ArgLen: 3, + ResultInArg0: true, + asm: arm64.AZUQSUB, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZUQSUBMergingD", + ArgLen: 3, + ResultInArg0: true, + asm: arm64.AZUQSUB, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZUQSUBMergingH", + ArgLen: 3, + ResultInArg0: true, + asm: arm64.AZUQSUB, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZUQSUBMergingS", + ArgLen: 3, + ResultInArg0: true, + asm: arm64.AZUQSUB, + Reg: RegInfo{ + Inputs: []InputInfo{ + {2, RegMask{V1: 9223372036854775808, V2: 32767}}, // P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + Name: "ZUQSUBS", + ArgLen: 2, + asm: arm64.AZUQSUB, + Reg: RegInfo{ + Inputs: []InputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + Outputs: []OutputInfo{ + {0, RegMask{V1: 9223372034707292160, V2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, { Name: "NEGV", @@ -109960,16 +112004,31 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 1, Generic: true, }, + { + Name: "AbsFloat32s", + ArgLen: 1, + Generic: true, + }, { Name: "AbsFloat32x4", ArgLen: 1, Generic: true, }, + { + Name: "AbsFloat64s", + ArgLen: 1, + Generic: true, + }, { Name: "AbsFloat64x2", ArgLen: 1, Generic: true, }, + { + Name: "AbsInt16s", + ArgLen: 1, + Generic: true, + }, { Name: "AbsInt16x16", ArgLen: 1, @@ -109985,6 +112044,11 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 1, Generic: true, }, + { + Name: "AbsInt32s", + ArgLen: 1, + Generic: true, + }, { Name: "AbsInt32x16", ArgLen: 1, @@ -110000,6 +112064,11 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 1, Generic: true, }, + { + Name: "AbsInt64s", + ArgLen: 1, + Generic: true, + }, { Name: "AbsInt64x2", ArgLen: 1, @@ -110015,6 +112084,11 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 1, Generic: true, }, + { + Name: "AbsInt8s", + ArgLen: 1, + Generic: true, + }, { Name: "AbsInt8x16", ArgLen: 1, @@ -110434,6 +112508,12 @@ var OpcodeTable = [...]OpInfo{ Commutative: true, Generic: true, }, + { + Name: "AndInt16s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "AndInt16x16", ArgLen: 2, @@ -110452,6 +112532,12 @@ var OpcodeTable = [...]OpInfo{ Commutative: true, Generic: true, }, + { + Name: "AndInt32s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "AndInt32x16", ArgLen: 2, @@ -110470,6 +112556,12 @@ var OpcodeTable = [...]OpInfo{ Commutative: true, Generic: true, }, + { + Name: "AndInt64s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "AndInt64x2", ArgLen: 2, @@ -110488,6 +112580,12 @@ var OpcodeTable = [...]OpInfo{ Commutative: true, Generic: true, }, + { + Name: "AndInt8s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "AndInt8x16", ArgLen: 2, @@ -110626,6 +112724,12 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 2, Generic: true, }, + { + Name: "AndUint16s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "AndUint16x16", ArgLen: 2, @@ -110644,6 +112748,12 @@ var OpcodeTable = [...]OpInfo{ Commutative: true, Generic: true, }, + { + Name: "AndUint32s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "AndUint32x16", ArgLen: 2, @@ -110662,6 +112772,12 @@ var OpcodeTable = [...]OpInfo{ Commutative: true, Generic: true, }, + { + Name: "AndUint64s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "AndUint64x2", ArgLen: 2, @@ -110680,6 +112796,12 @@ var OpcodeTable = [...]OpInfo{ Commutative: true, Generic: true, }, + { + Name: "AndUint8s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "AndUint8x16", ArgLen: 2, @@ -110828,6 +112950,11 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 1, Generic: true, }, + { + Name: "CeilFloat32s", + ArgLen: 1, + Generic: true, + }, { Name: "CeilFloat32x4", ArgLen: 1, @@ -110838,6 +112965,11 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 1, Generic: true, }, + { + Name: "CeilFloat64s", + ArgLen: 1, + Generic: true, + }, { Name: "CeilFloat64x2", ArgLen: 1, @@ -111878,6 +114010,12 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 2, Generic: true, }, + { + Name: "EqualFloat32s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "EqualFloat32x16", ArgLen: 2, @@ -111896,6 +114034,12 @@ var OpcodeTable = [...]OpInfo{ Commutative: true, Generic: true, }, + { + Name: "EqualFloat64s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "EqualFloat64x2", ArgLen: 2, @@ -111914,6 +114058,12 @@ var OpcodeTable = [...]OpInfo{ Commutative: true, Generic: true, }, + { + Name: "EqualInt16s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "EqualInt16x16", ArgLen: 2, @@ -111932,6 +114082,12 @@ var OpcodeTable = [...]OpInfo{ Commutative: true, Generic: true, }, + { + Name: "EqualInt32s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "EqualInt32x16", ArgLen: 2, @@ -111950,6 +114106,12 @@ var OpcodeTable = [...]OpInfo{ Commutative: true, Generic: true, }, + { + Name: "EqualInt64s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "EqualInt64x2", ArgLen: 2, @@ -111968,6 +114130,12 @@ var OpcodeTable = [...]OpInfo{ Commutative: true, Generic: true, }, + { + Name: "EqualInt8s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "EqualInt8x16", ArgLen: 2, @@ -111986,6 +114154,12 @@ var OpcodeTable = [...]OpInfo{ Commutative: true, Generic: true, }, + { + Name: "EqualUint16s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "EqualUint16x16", ArgLen: 2, @@ -112004,6 +114178,12 @@ var OpcodeTable = [...]OpInfo{ Commutative: true, Generic: true, }, + { + Name: "EqualUint32s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "EqualUint32x16", ArgLen: 2, @@ -112022,6 +114202,12 @@ var OpcodeTable = [...]OpInfo{ Commutative: true, Generic: true, }, + { + Name: "EqualUint64s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "EqualUint64x2", ArgLen: 2, @@ -112040,6 +114226,12 @@ var OpcodeTable = [...]OpInfo{ Commutative: true, Generic: true, }, + { + Name: "EqualUint8s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "EqualUint8x16", ArgLen: 2, @@ -112418,6 +114610,11 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 1, Generic: true, }, + { + Name: "FloorFloat32s", + ArgLen: 1, + Generic: true, + }, { Name: "FloorFloat32x4", ArgLen: 1, @@ -112428,6 +114625,11 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 1, Generic: true, }, + { + Name: "FloorFloat64s", + ArgLen: 1, + Generic: true, + }, { Name: "FloorFloat64x2", ArgLen: 1, @@ -112821,6 +115023,11 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 1, Generic: true, }, + { + Name: "GreaterEqualFloat32s", + ArgLen: 2, + Generic: true, + }, { Name: "GreaterEqualFloat32x16", ArgLen: 2, @@ -112836,6 +115043,11 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 2, Generic: true, }, + { + Name: "GreaterEqualFloat64s", + ArgLen: 2, + Generic: true, + }, { Name: "GreaterEqualFloat64x2", ArgLen: 2, @@ -112851,6 +115063,11 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 2, Generic: true, }, + { + Name: "GreaterEqualInt16s", + ArgLen: 2, + Generic: true, + }, { Name: "GreaterEqualInt16x32", ArgLen: 2, @@ -112861,6 +115078,11 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 2, Generic: true, }, + { + Name: "GreaterEqualInt32s", + ArgLen: 2, + Generic: true, + }, { Name: "GreaterEqualInt32x16", ArgLen: 2, @@ -112871,6 +115093,11 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 2, Generic: true, }, + { + Name: "GreaterEqualInt64s", + ArgLen: 2, + Generic: true, + }, { Name: "GreaterEqualInt64x2", ArgLen: 2, @@ -112881,6 +115108,11 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 2, Generic: true, }, + { + Name: "GreaterEqualInt8s", + ArgLen: 2, + Generic: true, + }, { Name: "GreaterEqualInt8x16", ArgLen: 2, @@ -112891,6 +115123,11 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 2, Generic: true, }, + { + Name: "GreaterEqualUint16s", + ArgLen: 2, + Generic: true, + }, { Name: "GreaterEqualUint16x32", ArgLen: 2, @@ -112901,6 +115138,11 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 2, Generic: true, }, + { + Name: "GreaterEqualUint32s", + ArgLen: 2, + Generic: true, + }, { Name: "GreaterEqualUint32x16", ArgLen: 2, @@ -112911,6 +115153,11 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 2, Generic: true, }, + { + Name: "GreaterEqualUint64s", + ArgLen: 2, + Generic: true, + }, { Name: "GreaterEqualUint64x2", ArgLen: 2, @@ -112921,6 +115168,11 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 2, Generic: true, }, + { + Name: "GreaterEqualUint8s", + ArgLen: 2, + Generic: true, + }, { Name: "GreaterEqualUint8x16", ArgLen: 2, @@ -112931,6 +115183,11 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 2, Generic: true, }, + { + Name: "GreaterFloat32s", + ArgLen: 2, + Generic: true, + }, { Name: "GreaterFloat32x16", ArgLen: 2, @@ -112946,6 +115203,11 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 2, Generic: true, }, + { + Name: "GreaterFloat64s", + ArgLen: 2, + Generic: true, + }, { Name: "GreaterFloat64x2", ArgLen: 2, @@ -113041,6 +115303,11 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 2, Generic: true, }, + { + Name: "GreaterUint16s", + ArgLen: 2, + Generic: true, + }, { Name: "GreaterUint16x32", ArgLen: 2, @@ -113051,6 +115318,11 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 2, Generic: true, }, + { + Name: "GreaterUint32s", + ArgLen: 2, + Generic: true, + }, { Name: "GreaterUint32x16", ArgLen: 2, @@ -113061,6 +115333,11 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 2, Generic: true, }, + { + Name: "GreaterUint64s", + ArgLen: 2, + Generic: true, + }, { Name: "GreaterUint64x2", ArgLen: 2, @@ -113071,6 +115348,11 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 2, Generic: true, }, + { + Name: "GreaterUint8s", + ArgLen: 2, + Generic: true, + }, { Name: "GreaterUint8x16", ArgLen: 2, @@ -114529,36 +116811,72 @@ var OpcodeTable = [...]OpInfo{ Commutative: true, Generic: true, }, + { + Name: "NegFloat32s", + ArgLen: 1, + Generic: true, + }, { Name: "NegFloat32x4", ArgLen: 1, Generic: true, }, + { + Name: "NegFloat64s", + ArgLen: 1, + Generic: true, + }, { Name: "NegFloat64x2", ArgLen: 1, Generic: true, }, + { + Name: "NegInt16s", + ArgLen: 1, + Generic: true, + }, { Name: "NegInt16x8", ArgLen: 1, Generic: true, }, + { + Name: "NegInt32s", + ArgLen: 1, + Generic: true, + }, { Name: "NegInt32x4", ArgLen: 1, Generic: true, }, + { + Name: "NegInt64s", + ArgLen: 1, + Generic: true, + }, { Name: "NegInt64x2", ArgLen: 1, Generic: true, }, + { + Name: "NegInt8s", + ArgLen: 1, + Generic: true, + }, { Name: "NegInt8x16", ArgLen: 1, Generic: true, }, + { + Name: "NotEqualFloat32s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "NotEqualFloat32x16", ArgLen: 2, @@ -114577,6 +116895,12 @@ var OpcodeTable = [...]OpInfo{ Commutative: true, Generic: true, }, + { + Name: "NotEqualFloat64s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "NotEqualFloat64x2", ArgLen: 2, @@ -114595,6 +116919,12 @@ var OpcodeTable = [...]OpInfo{ Commutative: true, Generic: true, }, + { + Name: "NotEqualInt16s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "NotEqualInt16x32", ArgLen: 2, @@ -114607,6 +116937,12 @@ var OpcodeTable = [...]OpInfo{ Commutative: true, Generic: true, }, + { + Name: "NotEqualInt32s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "NotEqualInt32x16", ArgLen: 2, @@ -114619,6 +116955,12 @@ var OpcodeTable = [...]OpInfo{ Commutative: true, Generic: true, }, + { + Name: "NotEqualInt64s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "NotEqualInt64x2", ArgLen: 2, @@ -114631,6 +116973,12 @@ var OpcodeTable = [...]OpInfo{ Commutative: true, Generic: true, }, + { + Name: "NotEqualInt8s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "NotEqualInt8x16", ArgLen: 2, @@ -114643,6 +116991,12 @@ var OpcodeTable = [...]OpInfo{ Commutative: true, Generic: true, }, + { + Name: "NotEqualUint16s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "NotEqualUint16x32", ArgLen: 2, @@ -114655,6 +117009,12 @@ var OpcodeTable = [...]OpInfo{ Commutative: true, Generic: true, }, + { + Name: "NotEqualUint32s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "NotEqualUint32x16", ArgLen: 2, @@ -114667,6 +117027,12 @@ var OpcodeTable = [...]OpInfo{ Commutative: true, Generic: true, }, + { + Name: "NotEqualUint64s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "NotEqualUint64x2", ArgLen: 2, @@ -114679,6 +117045,12 @@ var OpcodeTable = [...]OpInfo{ Commutative: true, Generic: true, }, + { + Name: "NotEqualUint8s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "NotEqualUint8x16", ArgLen: 2, @@ -114851,6 +117223,12 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 1, Generic: true, }, + { + Name: "OrInt16s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "OrInt16x16", ArgLen: 2, @@ -114869,6 +117247,12 @@ var OpcodeTable = [...]OpInfo{ Commutative: true, Generic: true, }, + { + Name: "OrInt32s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "OrInt32x16", ArgLen: 2, @@ -114887,6 +117271,12 @@ var OpcodeTable = [...]OpInfo{ Commutative: true, Generic: true, }, + { + Name: "OrInt64s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "OrInt64x2", ArgLen: 2, @@ -114905,6 +117295,12 @@ var OpcodeTable = [...]OpInfo{ Commutative: true, Generic: true, }, + { + Name: "OrInt8s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "OrInt8x16", ArgLen: 2, @@ -114963,6 +117359,12 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 2, Generic: true, }, + { + Name: "OrUint16s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "OrUint16x16", ArgLen: 2, @@ -114981,6 +117383,12 @@ var OpcodeTable = [...]OpInfo{ Commutative: true, Generic: true, }, + { + Name: "OrUint32s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "OrUint32x16", ArgLen: 2, @@ -114999,6 +117407,12 @@ var OpcodeTable = [...]OpInfo{ Commutative: true, Generic: true, }, + { + Name: "OrUint64s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "OrUint64x2", ArgLen: 2, @@ -115017,6 +117431,12 @@ var OpcodeTable = [...]OpInfo{ Commutative: true, Generic: true, }, + { + Name: "OrUint8s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "OrUint8x16", ArgLen: 2, @@ -115445,6 +117865,11 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 2, Generic: true, }, + { + Name: "RoundFloat32s", + ArgLen: 1, + Generic: true, + }, { Name: "RoundFloat32x4", ArgLen: 1, @@ -115455,6 +117880,11 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 1, Generic: true, }, + { + Name: "RoundFloat64s", + ArgLen: 1, + Generic: true, + }, { Name: "RoundFloat64x2", ArgLen: 1, @@ -116914,6 +119344,11 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 2, Generic: true, }, + { + Name: "SqrtFloat32s", + ArgLen: 1, + Generic: true, + }, { Name: "SqrtFloat32x16", ArgLen: 1, @@ -116929,6 +119364,11 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 1, Generic: true, }, + { + Name: "SqrtFloat64s", + ArgLen: 1, + Generic: true, + }, { Name: "SqrtFloat64x2", ArgLen: 1, @@ -116944,6 +119384,11 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 1, Generic: true, }, + { + Name: "SubFloat32s", + ArgLen: 2, + Generic: true, + }, { Name: "SubFloat32x16", ArgLen: 2, @@ -116959,6 +119404,11 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 2, Generic: true, }, + { + Name: "SubFloat64s", + ArgLen: 2, + Generic: true, + }, { Name: "SubFloat64x2", ArgLen: 2, @@ -116974,6 +119424,11 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 2, Generic: true, }, + { + Name: "SubInt16s", + ArgLen: 2, + Generic: true, + }, { Name: "SubInt16x16", ArgLen: 2, @@ -116989,6 +119444,11 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 2, Generic: true, }, + { + Name: "SubInt32s", + ArgLen: 2, + Generic: true, + }, { Name: "SubInt32x16", ArgLen: 2, @@ -117004,6 +119464,11 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 2, Generic: true, }, + { + Name: "SubInt64s", + ArgLen: 2, + Generic: true, + }, { Name: "SubInt64x2", ArgLen: 2, @@ -117019,6 +119484,11 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 2, Generic: true, }, + { + Name: "SubInt8s", + ArgLen: 2, + Generic: true, + }, { Name: "SubInt8x16", ArgLen: 2, @@ -117034,6 +119504,11 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 2, Generic: true, }, + { + Name: "SubSaturatedInt16s", + ArgLen: 2, + Generic: true, + }, { Name: "SubSaturatedInt16x16", ArgLen: 2, @@ -117049,16 +119524,31 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 2, Generic: true, }, + { + Name: "SubSaturatedInt32s", + ArgLen: 2, + Generic: true, + }, { Name: "SubSaturatedInt32x4", ArgLen: 2, Generic: true, }, + { + Name: "SubSaturatedInt64s", + ArgLen: 2, + Generic: true, + }, { Name: "SubSaturatedInt64x2", ArgLen: 2, Generic: true, }, + { + Name: "SubSaturatedInt8s", + ArgLen: 2, + Generic: true, + }, { Name: "SubSaturatedInt8x16", ArgLen: 2, @@ -117074,6 +119564,11 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 2, Generic: true, }, + { + Name: "SubSaturatedUint16s", + ArgLen: 2, + Generic: true, + }, { Name: "SubSaturatedUint16x16", ArgLen: 2, @@ -117089,16 +119584,31 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 2, Generic: true, }, + { + Name: "SubSaturatedUint32s", + ArgLen: 2, + Generic: true, + }, { Name: "SubSaturatedUint32x4", ArgLen: 2, Generic: true, }, + { + Name: "SubSaturatedUint64s", + ArgLen: 2, + Generic: true, + }, { Name: "SubSaturatedUint64x2", ArgLen: 2, Generic: true, }, + { + Name: "SubSaturatedUint8s", + ArgLen: 2, + Generic: true, + }, { Name: "SubSaturatedUint8x16", ArgLen: 2, @@ -117114,6 +119624,11 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 2, Generic: true, }, + { + Name: "SubUint16s", + ArgLen: 2, + Generic: true, + }, { Name: "SubUint16x16", ArgLen: 2, @@ -117129,6 +119644,11 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 2, Generic: true, }, + { + Name: "SubUint32s", + ArgLen: 2, + Generic: true, + }, { Name: "SubUint32x16", ArgLen: 2, @@ -117144,6 +119664,11 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 2, Generic: true, }, + { + Name: "SubUint64s", + ArgLen: 2, + Generic: true, + }, { Name: "SubUint64x2", ArgLen: 2, @@ -117159,6 +119684,11 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 2, Generic: true, }, + { + Name: "SubUint8s", + ArgLen: 2, + Generic: true, + }, { Name: "SubUint8x16", ArgLen: 2, @@ -117189,6 +119719,11 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 2, Generic: true, }, + { + Name: "TruncFloat32s", + ArgLen: 1, + Generic: true, + }, { Name: "TruncFloat32x4", ArgLen: 1, @@ -117199,6 +119734,11 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 1, Generic: true, }, + { + Name: "TruncFloat64s", + ArgLen: 1, + Generic: true, + }, { Name: "TruncFloat64x2", ArgLen: 1, @@ -117461,6 +120001,12 @@ var OpcodeTable = [...]OpInfo{ ArgLen: 1, Generic: true, }, + { + Name: "XorInt16s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "XorInt16x16", ArgLen: 2, @@ -117479,6 +120025,12 @@ var OpcodeTable = [...]OpInfo{ Commutative: true, Generic: true, }, + { + Name: "XorInt32s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "XorInt32x16", ArgLen: 2, @@ -117497,6 +120049,12 @@ var OpcodeTable = [...]OpInfo{ Commutative: true, Generic: true, }, + { + Name: "XorInt64s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "XorInt64x2", ArgLen: 2, @@ -117515,6 +120073,12 @@ var OpcodeTable = [...]OpInfo{ Commutative: true, Generic: true, }, + { + Name: "XorInt8s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "XorInt8x16", ArgLen: 2, @@ -117533,6 +120097,12 @@ var OpcodeTable = [...]OpInfo{ Commutative: true, Generic: true, }, + { + Name: "XorUint16s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "XorUint16x16", ArgLen: 2, @@ -117551,6 +120121,12 @@ var OpcodeTable = [...]OpInfo{ Commutative: true, Generic: true, }, + { + Name: "XorUint32s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "XorUint32x16", ArgLen: 2, @@ -117569,6 +120145,12 @@ var OpcodeTable = [...]OpInfo{ Commutative: true, Generic: true, }, + { + Name: "XorUint64s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "XorUint64x2", ArgLen: 2, @@ -117587,6 +120169,12 @@ var OpcodeTable = [...]OpInfo{ Commutative: true, Generic: true, }, + { + Name: "XorUint8s", + ArgLen: 2, + Commutative: true, + Generic: true, + }, { Name: "XorUint8x16", ArgLen: 2, diff --git a/src/cmd/compile/internal/ssagen/simdARM64SVEintrinsics.go b/src/cmd/compile/internal/ssagen/simdARM64SVEintrinsics.go index a5a6cc571b9def..d742bda5e3961a 100644 --- a/src/cmd/compile/internal/ssagen/simdARM64SVEintrinsics.go +++ b/src/cmd/compile/internal/ssagen/simdARM64SVEintrinsics.go @@ -11,6 +11,12 @@ import ( func simdARM64SVEIntrinsics(addF func(pkg, fn string, b intrinsicBuilder, archFamilies ...sys.ArchFamily)) { + addF(simdPackage, "Float32s.Abs", opLen1(ssaop.OpAbsFloat32s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Float64s.Abs", opLen1(ssaop.OpAbsFloat64s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Int8s.Abs", opLen1(ssaop.OpAbsInt8s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Int16s.Abs", opLen1(ssaop.OpAbsInt16s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Int32s.Abs", opLen1(ssaop.OpAbsInt32s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Int64s.Abs", opLen1(ssaop.OpAbsInt64s, types.TypeVec256), sys.ARM64) addF(simdPackage, "Float32s.Add", opLen2(ssaop.OpAddFloat32s, types.TypeVec256), sys.ARM64) addF(simdPackage, "Float64s.Add", opLen2(ssaop.OpAddFloat64s, types.TypeVec256), sys.ARM64) addF(simdPackage, "Int8s.Add", opLen2(ssaop.OpAddInt8s, types.TypeVec256), sys.ARM64) @@ -29,10 +35,104 @@ func simdARM64SVEIntrinsics(addF func(pkg, fn string, b intrinsicBuilder, archFa addF(simdPackage, "Uint16s.AddSaturated", opLen2(ssaop.OpAddSaturatedUint16s, types.TypeVec256), sys.ARM64) addF(simdPackage, "Uint32s.AddSaturated", opLen2(ssaop.OpAddSaturatedUint32s, types.TypeVec256), sys.ARM64) addF(simdPackage, "Uint64s.AddSaturated", opLen2(ssaop.OpAddSaturatedUint64s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Int8s.And", opLen2(ssaop.OpAndInt8s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Int16s.And", opLen2(ssaop.OpAndInt16s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Int32s.And", opLen2(ssaop.OpAndInt32s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Int64s.And", opLen2(ssaop.OpAndInt64s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Uint8s.And", opLen2(ssaop.OpAndUint8s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Uint16s.And", opLen2(ssaop.OpAndUint16s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Uint32s.And", opLen2(ssaop.OpAndUint32s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Uint64s.And", opLen2(ssaop.OpAndUint64s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Float32s.Ceil", opLen1(ssaop.OpCeilFloat32s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Float64s.Ceil", opLen1(ssaop.OpCeilFloat64s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Float32s.Equal", opLen2(ssaop.OpEqualFloat32s, types.TypeMask), sys.ARM64) + addF(simdPackage, "Float64s.Equal", opLen2(ssaop.OpEqualFloat64s, types.TypeMask), sys.ARM64) + addF(simdPackage, "Int8s.Equal", opLen2(ssaop.OpEqualInt8s, types.TypeMask), sys.ARM64) + addF(simdPackage, "Int16s.Equal", opLen2(ssaop.OpEqualInt16s, types.TypeMask), sys.ARM64) + addF(simdPackage, "Int32s.Equal", opLen2(ssaop.OpEqualInt32s, types.TypeMask), sys.ARM64) + addF(simdPackage, "Int64s.Equal", opLen2(ssaop.OpEqualInt64s, types.TypeMask), sys.ARM64) + addF(simdPackage, "Uint8s.Equal", opLen2(ssaop.OpEqualUint8s, types.TypeMask), sys.ARM64) + addF(simdPackage, "Uint16s.Equal", opLen2(ssaop.OpEqualUint16s, types.TypeMask), sys.ARM64) + addF(simdPackage, "Uint32s.Equal", opLen2(ssaop.OpEqualUint32s, types.TypeMask), sys.ARM64) + addF(simdPackage, "Uint64s.Equal", opLen2(ssaop.OpEqualUint64s, types.TypeMask), sys.ARM64) + addF(simdPackage, "Float32s.Floor", opLen1(ssaop.OpFloorFloat32s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Float64s.Floor", opLen1(ssaop.OpFloorFloat64s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Float32s.Greater", opLen2(ssaop.OpGreaterFloat32s, types.TypeMask), sys.ARM64) + addF(simdPackage, "Float64s.Greater", opLen2(ssaop.OpGreaterFloat64s, types.TypeMask), sys.ARM64) addF(simdPackage, "Int8s.Greater", opLen2(ssaop.OpGreaterInt8s, types.TypeMask), sys.ARM64) addF(simdPackage, "Int16s.Greater", opLen2(ssaop.OpGreaterInt16s, types.TypeMask), sys.ARM64) addF(simdPackage, "Int32s.Greater", opLen2(ssaop.OpGreaterInt32s, types.TypeMask), sys.ARM64) addF(simdPackage, "Int64s.Greater", opLen2(ssaop.OpGreaterInt64s, types.TypeMask), sys.ARM64) + addF(simdPackage, "Uint8s.Greater", opLen2(ssaop.OpGreaterUint8s, types.TypeMask), sys.ARM64) + addF(simdPackage, "Uint16s.Greater", opLen2(ssaop.OpGreaterUint16s, types.TypeMask), sys.ARM64) + addF(simdPackage, "Uint32s.Greater", opLen2(ssaop.OpGreaterUint32s, types.TypeMask), sys.ARM64) + addF(simdPackage, "Uint64s.Greater", opLen2(ssaop.OpGreaterUint64s, types.TypeMask), sys.ARM64) + addF(simdPackage, "Float32s.GreaterEqual", opLen2(ssaop.OpGreaterEqualFloat32s, types.TypeMask), sys.ARM64) + addF(simdPackage, "Float64s.GreaterEqual", opLen2(ssaop.OpGreaterEqualFloat64s, types.TypeMask), sys.ARM64) + addF(simdPackage, "Int8s.GreaterEqual", opLen2(ssaop.OpGreaterEqualInt8s, types.TypeMask), sys.ARM64) + addF(simdPackage, "Int16s.GreaterEqual", opLen2(ssaop.OpGreaterEqualInt16s, types.TypeMask), sys.ARM64) + addF(simdPackage, "Int32s.GreaterEqual", opLen2(ssaop.OpGreaterEqualInt32s, types.TypeMask), sys.ARM64) + addF(simdPackage, "Int64s.GreaterEqual", opLen2(ssaop.OpGreaterEqualInt64s, types.TypeMask), sys.ARM64) + addF(simdPackage, "Uint8s.GreaterEqual", opLen2(ssaop.OpGreaterEqualUint8s, types.TypeMask), sys.ARM64) + addF(simdPackage, "Uint16s.GreaterEqual", opLen2(ssaop.OpGreaterEqualUint16s, types.TypeMask), sys.ARM64) + addF(simdPackage, "Uint32s.GreaterEqual", opLen2(ssaop.OpGreaterEqualUint32s, types.TypeMask), sys.ARM64) + addF(simdPackage, "Uint64s.GreaterEqual", opLen2(ssaop.OpGreaterEqualUint64s, types.TypeMask), sys.ARM64) + addF(simdPackage, "Float32s.Neg", opLen1(ssaop.OpNegFloat32s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Float64s.Neg", opLen1(ssaop.OpNegFloat64s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Int8s.Neg", opLen1(ssaop.OpNegInt8s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Int16s.Neg", opLen1(ssaop.OpNegInt16s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Int32s.Neg", opLen1(ssaop.OpNegInt32s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Int64s.Neg", opLen1(ssaop.OpNegInt64s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Float32s.NotEqual", opLen2(ssaop.OpNotEqualFloat32s, types.TypeMask), sys.ARM64) + addF(simdPackage, "Float64s.NotEqual", opLen2(ssaop.OpNotEqualFloat64s, types.TypeMask), sys.ARM64) + addF(simdPackage, "Int8s.NotEqual", opLen2(ssaop.OpNotEqualInt8s, types.TypeMask), sys.ARM64) + addF(simdPackage, "Int16s.NotEqual", opLen2(ssaop.OpNotEqualInt16s, types.TypeMask), sys.ARM64) + addF(simdPackage, "Int32s.NotEqual", opLen2(ssaop.OpNotEqualInt32s, types.TypeMask), sys.ARM64) + addF(simdPackage, "Int64s.NotEqual", opLen2(ssaop.OpNotEqualInt64s, types.TypeMask), sys.ARM64) + addF(simdPackage, "Uint8s.NotEqual", opLen2(ssaop.OpNotEqualUint8s, types.TypeMask), sys.ARM64) + addF(simdPackage, "Uint16s.NotEqual", opLen2(ssaop.OpNotEqualUint16s, types.TypeMask), sys.ARM64) + addF(simdPackage, "Uint32s.NotEqual", opLen2(ssaop.OpNotEqualUint32s, types.TypeMask), sys.ARM64) + addF(simdPackage, "Uint64s.NotEqual", opLen2(ssaop.OpNotEqualUint64s, types.TypeMask), sys.ARM64) + addF(simdPackage, "Int8s.Or", opLen2(ssaop.OpOrInt8s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Int16s.Or", opLen2(ssaop.OpOrInt16s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Int32s.Or", opLen2(ssaop.OpOrInt32s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Int64s.Or", opLen2(ssaop.OpOrInt64s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Uint8s.Or", opLen2(ssaop.OpOrUint8s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Uint16s.Or", opLen2(ssaop.OpOrUint16s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Uint32s.Or", opLen2(ssaop.OpOrUint32s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Uint64s.Or", opLen2(ssaop.OpOrUint64s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Float32s.Round", opLen1(ssaop.OpRoundFloat32s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Float64s.Round", opLen1(ssaop.OpRoundFloat64s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Float32s.Sqrt", opLen1(ssaop.OpSqrtFloat32s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Float64s.Sqrt", opLen1(ssaop.OpSqrtFloat64s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Float32s.Sub", opLen2(ssaop.OpSubFloat32s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Float64s.Sub", opLen2(ssaop.OpSubFloat64s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Int8s.Sub", opLen2(ssaop.OpSubInt8s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Int16s.Sub", opLen2(ssaop.OpSubInt16s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Int32s.Sub", opLen2(ssaop.OpSubInt32s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Int64s.Sub", opLen2(ssaop.OpSubInt64s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Uint8s.Sub", opLen2(ssaop.OpSubUint8s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Uint16s.Sub", opLen2(ssaop.OpSubUint16s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Uint32s.Sub", opLen2(ssaop.OpSubUint32s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Uint64s.Sub", opLen2(ssaop.OpSubUint64s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Int8s.SubSaturated", opLen2(ssaop.OpSubSaturatedInt8s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Int16s.SubSaturated", opLen2(ssaop.OpSubSaturatedInt16s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Int32s.SubSaturated", opLen2(ssaop.OpSubSaturatedInt32s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Int64s.SubSaturated", opLen2(ssaop.OpSubSaturatedInt64s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Uint8s.SubSaturated", opLen2(ssaop.OpSubSaturatedUint8s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Uint16s.SubSaturated", opLen2(ssaop.OpSubSaturatedUint16s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Uint32s.SubSaturated", opLen2(ssaop.OpSubSaturatedUint32s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Uint64s.SubSaturated", opLen2(ssaop.OpSubSaturatedUint64s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Float32s.Trunc", opLen1(ssaop.OpTruncFloat32s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Float64s.Trunc", opLen1(ssaop.OpTruncFloat64s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Int8s.Xor", opLen2(ssaop.OpXorInt8s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Int16s.Xor", opLen2(ssaop.OpXorInt16s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Int32s.Xor", opLen2(ssaop.OpXorInt32s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Int64s.Xor", opLen2(ssaop.OpXorInt64s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Uint8s.Xor", opLen2(ssaop.OpXorUint8s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Uint16s.Xor", opLen2(ssaop.OpXorUint16s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Uint32s.Xor", opLen2(ssaop.OpXorUint32s, types.TypeVec256), sys.ARM64) + addF(simdPackage, "Uint64s.Xor", opLen2(ssaop.OpXorUint64s, types.TypeVec256), sys.ARM64) addF(simdPackage, "Float32s.AsFloat64s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) addF(simdPackage, "Float32s.AsInt8s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) addF(simdPackage, "Float32s.AsInt16s", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.ARM64) diff --git a/src/cmd/compile/internal/ssarewrite/rewritearm64/rewriteARM64.go b/src/cmd/compile/internal/ssarewrite/rewritearm64/rewriteARM64.go index b9f150810ce6d7..3f7aa57bc22fb2 100644 --- a/src/cmd/compile/internal/ssarewrite/rewritearm64/rewriteARM64.go +++ b/src/cmd/compile/internal/ssarewrite/rewritearm64/rewriteARM64.go @@ -530,21 +530,33 @@ func RewriteValue(v *ssa.Value) bool { case ssaop.OpAbs: v.Op = ssaop.OpARM64FABSD return true + case ssaop.OpAbsFloat32s: + return rewriteValue_OpAbsFloat32s(v) case ssaop.OpAbsFloat32x4: v.Op = ssaop.OpARM64VFABS4S return true + case ssaop.OpAbsFloat64s: + return rewriteValue_OpAbsFloat64s(v) case ssaop.OpAbsFloat64x2: v.Op = ssaop.OpARM64VFABS2D return true + case ssaop.OpAbsInt16s: + return rewriteValue_OpAbsInt16s(v) case ssaop.OpAbsInt16x8: v.Op = ssaop.OpARM64VABS8H return true + case ssaop.OpAbsInt32s: + return rewriteValue_OpAbsInt32s(v) case ssaop.OpAbsInt32x4: v.Op = ssaop.OpARM64VABS4S return true + case ssaop.OpAbsInt64s: + return rewriteValue_OpAbsInt64s(v) case ssaop.OpAbsInt64x2: v.Op = ssaop.OpARM64VABS2D return true + case ssaop.OpAbsInt8s: + return rewriteValue_OpAbsInt8s(v) case ssaop.OpAbsInt8x16: v.Op = ssaop.OpARM64VABS16B return true @@ -694,15 +706,27 @@ func RewriteValue(v *ssa.Value) bool { case ssaop.OpAndB: v.Op = ssaop.OpARM64AND return true + case ssaop.OpAndInt16s: + v.Op = ssaop.OpARM64ZANDD + return true case ssaop.OpAndInt16x8: v.Op = ssaop.OpARM64VAND16B return true + case ssaop.OpAndInt32s: + v.Op = ssaop.OpARM64ZANDD + return true case ssaop.OpAndInt32x4: v.Op = ssaop.OpARM64VAND16B return true + case ssaop.OpAndInt64s: + v.Op = ssaop.OpARM64ZANDD + return true case ssaop.OpAndInt64x2: v.Op = ssaop.OpARM64VAND16B return true + case ssaop.OpAndInt8s: + v.Op = ssaop.OpARM64ZANDD + return true case ssaop.OpAndInt8x16: v.Op = ssaop.OpARM64VAND16B return true @@ -730,15 +754,27 @@ func RewriteValue(v *ssa.Value) bool { case ssaop.OpAndNotUint8x16: v.Op = ssaop.OpARM64VBIC16B return true + case ssaop.OpAndUint16s: + v.Op = ssaop.OpARM64ZANDD + return true case ssaop.OpAndUint16x8: v.Op = ssaop.OpARM64VAND16B return true + case ssaop.OpAndUint32s: + v.Op = ssaop.OpARM64ZANDD + return true case ssaop.OpAndUint32x4: v.Op = ssaop.OpARM64VAND16B return true + case ssaop.OpAndUint64s: + v.Op = ssaop.OpARM64ZANDD + return true case ssaop.OpAndUint64x2: v.Op = ssaop.OpARM64VAND16B return true + case ssaop.OpAndUint8s: + v.Op = ssaop.OpARM64ZANDD + return true case ssaop.OpAndUint8x16: v.Op = ssaop.OpARM64VAND16B return true @@ -894,9 +930,13 @@ func RewriteValue(v *ssa.Value) bool { case ssaop.OpCeil: v.Op = ssaop.OpARM64FRINTPD return true + case ssaop.OpCeilFloat32s: + return rewriteValue_OpCeilFloat32s(v) case ssaop.OpCeilFloat32x4: v.Op = ssaop.OpARM64VFRINTP4S return true + case ssaop.OpCeilFloat64s: + return rewriteValue_OpCeilFloat64s(v) case ssaop.OpCeilFloat64x2: v.Op = ssaop.OpARM64VFRINTP2D return true @@ -1163,33 +1203,53 @@ func RewriteValue(v *ssa.Value) bool { return rewriteValue_OpEqB(v) case ssaop.OpEqPtr: return rewriteValue_OpEqPtr(v) + case ssaop.OpEqualFloat32s: + return rewriteValue_OpEqualFloat32s(v) case ssaop.OpEqualFloat32x4: v.Op = ssaop.OpARM64VFCMEQ4S return true + case ssaop.OpEqualFloat64s: + return rewriteValue_OpEqualFloat64s(v) case ssaop.OpEqualFloat64x2: v.Op = ssaop.OpARM64VFCMEQ2D return true + case ssaop.OpEqualInt16s: + return rewriteValue_OpEqualInt16s(v) case ssaop.OpEqualInt16x8: v.Op = ssaop.OpARM64VCMEQ8H return true + case ssaop.OpEqualInt32s: + return rewriteValue_OpEqualInt32s(v) case ssaop.OpEqualInt32x4: v.Op = ssaop.OpARM64VCMEQ4S return true + case ssaop.OpEqualInt64s: + return rewriteValue_OpEqualInt64s(v) case ssaop.OpEqualInt64x2: v.Op = ssaop.OpARM64VCMEQ2D return true + case ssaop.OpEqualInt8s: + return rewriteValue_OpEqualInt8s(v) case ssaop.OpEqualInt8x16: v.Op = ssaop.OpARM64VCMEQ16B return true + case ssaop.OpEqualUint16s: + return rewriteValue_OpEqualUint16s(v) case ssaop.OpEqualUint16x8: v.Op = ssaop.OpARM64VCMEQ8H return true + case ssaop.OpEqualUint32s: + return rewriteValue_OpEqualUint32s(v) case ssaop.OpEqualUint32x4: v.Op = ssaop.OpARM64VCMEQ4S return true + case ssaop.OpEqualUint64s: + return rewriteValue_OpEqualUint64s(v) case ssaop.OpEqualUint64x2: v.Op = ssaop.OpARM64VCMEQ2D return true + case ssaop.OpEqualUint8s: + return rewriteValue_OpEqualUint8s(v) case ssaop.OpEqualUint8x16: v.Op = ssaop.OpARM64VCMEQ16B return true @@ -1216,9 +1276,13 @@ func RewriteValue(v *ssa.Value) bool { case ssaop.OpFloor: v.Op = ssaop.OpARM64FRINTMD return true + case ssaop.OpFloorFloat32s: + return rewriteValue_OpFloorFloat32s(v) case ssaop.OpFloorFloat32x4: v.Op = ssaop.OpARM64VFRINTM4S return true + case ssaop.OpFloorFloat64s: + return rewriteValue_OpFloorFloat64s(v) case ssaop.OpFloorFloat64x2: v.Op = ssaop.OpARM64VFRINTM2D return true @@ -1261,39 +1325,63 @@ func RewriteValue(v *ssa.Value) bool { case ssaop.OpGetElemUint8x16: v.Op = ssaop.OpARM64VMOVBextr return true + case ssaop.OpGreaterEqualFloat32s: + return rewriteValue_OpGreaterEqualFloat32s(v) case ssaop.OpGreaterEqualFloat32x4: v.Op = ssaop.OpARM64VFCMGE4S return true + case ssaop.OpGreaterEqualFloat64s: + return rewriteValue_OpGreaterEqualFloat64s(v) case ssaop.OpGreaterEqualFloat64x2: v.Op = ssaop.OpARM64VFCMGE2D return true + case ssaop.OpGreaterEqualInt16s: + return rewriteValue_OpGreaterEqualInt16s(v) case ssaop.OpGreaterEqualInt16x8: v.Op = ssaop.OpARM64VCMGE8H return true + case ssaop.OpGreaterEqualInt32s: + return rewriteValue_OpGreaterEqualInt32s(v) case ssaop.OpGreaterEqualInt32x4: v.Op = ssaop.OpARM64VCMGE4S return true + case ssaop.OpGreaterEqualInt64s: + return rewriteValue_OpGreaterEqualInt64s(v) case ssaop.OpGreaterEqualInt64x2: v.Op = ssaop.OpARM64VCMGE2D return true + case ssaop.OpGreaterEqualInt8s: + return rewriteValue_OpGreaterEqualInt8s(v) case ssaop.OpGreaterEqualInt8x16: v.Op = ssaop.OpARM64VCMGE16B return true + case ssaop.OpGreaterEqualUint16s: + return rewriteValue_OpGreaterEqualUint16s(v) case ssaop.OpGreaterEqualUint16x8: v.Op = ssaop.OpARM64VCMHS8H return true + case ssaop.OpGreaterEqualUint32s: + return rewriteValue_OpGreaterEqualUint32s(v) case ssaop.OpGreaterEqualUint32x4: v.Op = ssaop.OpARM64VCMHS4S return true + case ssaop.OpGreaterEqualUint64s: + return rewriteValue_OpGreaterEqualUint64s(v) case ssaop.OpGreaterEqualUint64x2: v.Op = ssaop.OpARM64VCMHS2D return true + case ssaop.OpGreaterEqualUint8s: + return rewriteValue_OpGreaterEqualUint8s(v) case ssaop.OpGreaterEqualUint8x16: v.Op = ssaop.OpARM64VCMHS16B return true + case ssaop.OpGreaterFloat32s: + return rewriteValue_OpGreaterFloat32s(v) case ssaop.OpGreaterFloat32x4: v.Op = ssaop.OpARM64VFCMGT4S return true + case ssaop.OpGreaterFloat64s: + return rewriteValue_OpGreaterFloat64s(v) case ssaop.OpGreaterFloat64x2: v.Op = ssaop.OpARM64VFCMGT2D return true @@ -1317,15 +1405,23 @@ func RewriteValue(v *ssa.Value) bool { case ssaop.OpGreaterInt8x16: v.Op = ssaop.OpARM64VCMGT16B return true + case ssaop.OpGreaterUint16s: + return rewriteValue_OpGreaterUint16s(v) case ssaop.OpGreaterUint16x8: v.Op = ssaop.OpARM64VCMHI8H return true + case ssaop.OpGreaterUint32s: + return rewriteValue_OpGreaterUint32s(v) case ssaop.OpGreaterUint32x4: v.Op = ssaop.OpARM64VCMHI4S return true + case ssaop.OpGreaterUint64s: + return rewriteValue_OpGreaterUint64s(v) case ssaop.OpGreaterUint64x2: v.Op = ssaop.OpARM64VCMHI2D return true + case ssaop.OpGreaterUint8s: + return rewriteValue_OpGreaterUint8s(v) case ssaop.OpGreaterUint8x16: v.Op = ssaop.OpARM64VCMHI16B return true @@ -1781,21 +1877,33 @@ func RewriteValue(v *ssa.Value) bool { case ssaop.OpNeg8: v.Op = ssaop.OpARM64NEG return true + case ssaop.OpNegFloat32s: + return rewriteValue_OpNegFloat32s(v) case ssaop.OpNegFloat32x4: v.Op = ssaop.OpARM64VFNEG4S return true + case ssaop.OpNegFloat64s: + return rewriteValue_OpNegFloat64s(v) case ssaop.OpNegFloat64x2: v.Op = ssaop.OpARM64VFNEG2D return true + case ssaop.OpNegInt16s: + return rewriteValue_OpNegInt16s(v) case ssaop.OpNegInt16x8: v.Op = ssaop.OpARM64VNEG8H return true + case ssaop.OpNegInt32s: + return rewriteValue_OpNegInt32s(v) case ssaop.OpNegInt32x4: v.Op = ssaop.OpARM64VNEG4S return true + case ssaop.OpNegInt64s: + return rewriteValue_OpNegInt64s(v) case ssaop.OpNegInt64x2: v.Op = ssaop.OpARM64VNEG2D return true + case ssaop.OpNegInt8s: + return rewriteValue_OpNegInt8s(v) case ssaop.OpNegInt8x16: v.Op = ssaop.OpARM64VNEG16B return true @@ -1821,6 +1929,26 @@ func RewriteValue(v *ssa.Value) bool { return true case ssaop.OpNot: return rewriteValue_OpNot(v) + case ssaop.OpNotEqualFloat32s: + return rewriteValue_OpNotEqualFloat32s(v) + case ssaop.OpNotEqualFloat64s: + return rewriteValue_OpNotEqualFloat64s(v) + case ssaop.OpNotEqualInt16s: + return rewriteValue_OpNotEqualInt16s(v) + case ssaop.OpNotEqualInt32s: + return rewriteValue_OpNotEqualInt32s(v) + case ssaop.OpNotEqualInt64s: + return rewriteValue_OpNotEqualInt64s(v) + case ssaop.OpNotEqualInt8s: + return rewriteValue_OpNotEqualInt8s(v) + case ssaop.OpNotEqualUint16s: + return rewriteValue_OpNotEqualUint16s(v) + case ssaop.OpNotEqualUint32s: + return rewriteValue_OpNotEqualUint32s(v) + case ssaop.OpNotEqualUint64s: + return rewriteValue_OpNotEqualUint64s(v) + case ssaop.OpNotEqualUint8s: + return rewriteValue_OpNotEqualUint8s(v) case ssaop.OpNotInt16x8: v.Op = ssaop.OpARM64VNOT16B return true @@ -1868,15 +1996,27 @@ func RewriteValue(v *ssa.Value) bool { case ssaop.OpOrB: v.Op = ssaop.OpARM64OR return true + case ssaop.OpOrInt16s: + v.Op = ssaop.OpARM64ZORRD + return true case ssaop.OpOrInt16x8: v.Op = ssaop.OpARM64VORR16B return true + case ssaop.OpOrInt32s: + v.Op = ssaop.OpARM64ZORRD + return true case ssaop.OpOrInt32x4: v.Op = ssaop.OpARM64VORR16B return true + case ssaop.OpOrInt64s: + v.Op = ssaop.OpARM64ZORRD + return true case ssaop.OpOrInt64x2: v.Op = ssaop.OpARM64VORR16B return true + case ssaop.OpOrInt8s: + v.Op = ssaop.OpARM64ZORRD + return true case ssaop.OpOrInt8x16: v.Op = ssaop.OpARM64VORR16B return true @@ -1904,15 +2044,27 @@ func RewriteValue(v *ssa.Value) bool { case ssaop.OpOrNotUint8x16: v.Op = ssaop.OpARM64VORN16B return true + case ssaop.OpOrUint16s: + v.Op = ssaop.OpARM64ZORRD + return true case ssaop.OpOrUint16x8: v.Op = ssaop.OpARM64VORR16B return true + case ssaop.OpOrUint32s: + v.Op = ssaop.OpARM64ZORRD + return true case ssaop.OpOrUint32x4: v.Op = ssaop.OpARM64VORR16B return true + case ssaop.OpOrUint64s: + v.Op = ssaop.OpARM64ZORRD + return true case ssaop.OpOrUint64x2: v.Op = ssaop.OpARM64VORR16B return true + case ssaop.OpOrUint8s: + v.Op = ssaop.OpARM64ZORRD + return true case ssaop.OpOrUint8x16: v.Op = ssaop.OpARM64VORR16B return true @@ -1948,9 +2100,13 @@ func RewriteValue(v *ssa.Value) bool { case ssaop.OpRound64F: v.Op = ssaop.OpARM64LoweredRound64F return true + case ssaop.OpRoundFloat32s: + return rewriteValue_OpRoundFloat32s(v) case ssaop.OpRoundFloat32x4: v.Op = ssaop.OpARM64VFRINTN4S return true + case ssaop.OpRoundFloat64s: + return rewriteValue_OpRoundFloat64s(v) case ssaop.OpRoundFloat64x2: v.Op = ssaop.OpARM64VFRINTN2D return true @@ -2192,9 +2348,13 @@ func RewriteValue(v *ssa.Value) bool { case ssaop.OpSqrt32: v.Op = ssaop.OpARM64FSQRTS return true + case ssaop.OpSqrtFloat32s: + return rewriteValue_OpSqrtFloat32s(v) case ssaop.OpSqrtFloat32x4: v.Op = ssaop.OpARM64VFSQRT4S return true + case ssaop.OpSqrtFloat64s: + return rewriteValue_OpSqrtFloat64s(v) case ssaop.OpSqrtFloat64x2: v.Op = ssaop.OpARM64VFSQRT2D return true @@ -2223,60 +2383,114 @@ func RewriteValue(v *ssa.Value) bool { case ssaop.OpSub8: v.Op = ssaop.OpARM64SUB return true + case ssaop.OpSubFloat32s: + v.Op = ssaop.OpARM64ZFSUBS + return true case ssaop.OpSubFloat32x4: v.Op = ssaop.OpARM64VFSUB4S return true + case ssaop.OpSubFloat64s: + v.Op = ssaop.OpARM64ZFSUBD + return true case ssaop.OpSubFloat64x2: v.Op = ssaop.OpARM64VFSUB2D return true + case ssaop.OpSubInt16s: + v.Op = ssaop.OpARM64ZSUBH + return true case ssaop.OpSubInt16x8: v.Op = ssaop.OpARM64VSUB8H return true + case ssaop.OpSubInt32s: + v.Op = ssaop.OpARM64ZSUBS + return true case ssaop.OpSubInt32x4: v.Op = ssaop.OpARM64VSUB4S return true + case ssaop.OpSubInt64s: + v.Op = ssaop.OpARM64ZSUBD + return true case ssaop.OpSubInt64x2: v.Op = ssaop.OpARM64VSUB2D return true + case ssaop.OpSubInt8s: + v.Op = ssaop.OpARM64ZSUBB + return true case ssaop.OpSubInt8x16: v.Op = ssaop.OpARM64VSUB16B return true case ssaop.OpSubPtr: v.Op = ssaop.OpARM64SUB return true + case ssaop.OpSubSaturatedInt16s: + v.Op = ssaop.OpARM64ZSQSUBH + return true case ssaop.OpSubSaturatedInt16x8: v.Op = ssaop.OpARM64VSQSUB8H return true + case ssaop.OpSubSaturatedInt32s: + v.Op = ssaop.OpARM64ZSQSUBS + return true case ssaop.OpSubSaturatedInt32x4: v.Op = ssaop.OpARM64VSQSUB4S return true + case ssaop.OpSubSaturatedInt64s: + v.Op = ssaop.OpARM64ZSQSUBD + return true case ssaop.OpSubSaturatedInt64x2: v.Op = ssaop.OpARM64VSQSUB2D return true + case ssaop.OpSubSaturatedInt8s: + v.Op = ssaop.OpARM64ZSQSUBB + return true case ssaop.OpSubSaturatedInt8x16: v.Op = ssaop.OpARM64VSQSUB16B return true + case ssaop.OpSubSaturatedUint16s: + v.Op = ssaop.OpARM64ZUQSUBH + return true case ssaop.OpSubSaturatedUint16x8: v.Op = ssaop.OpARM64VUQSUB8H return true + case ssaop.OpSubSaturatedUint32s: + v.Op = ssaop.OpARM64ZUQSUBS + return true case ssaop.OpSubSaturatedUint32x4: v.Op = ssaop.OpARM64VUQSUB4S return true + case ssaop.OpSubSaturatedUint64s: + v.Op = ssaop.OpARM64ZUQSUBD + return true case ssaop.OpSubSaturatedUint64x2: v.Op = ssaop.OpARM64VUQSUB2D return true + case ssaop.OpSubSaturatedUint8s: + v.Op = ssaop.OpARM64ZUQSUBB + return true case ssaop.OpSubSaturatedUint8x16: v.Op = ssaop.OpARM64VUQSUB16B return true + case ssaop.OpSubUint16s: + v.Op = ssaop.OpARM64ZSUBH + return true case ssaop.OpSubUint16x8: v.Op = ssaop.OpARM64VSUB8H return true + case ssaop.OpSubUint32s: + v.Op = ssaop.OpARM64ZSUBS + return true case ssaop.OpSubUint32x4: v.Op = ssaop.OpARM64VSUB4S return true + case ssaop.OpSubUint64s: + v.Op = ssaop.OpARM64ZSUBD + return true case ssaop.OpSubUint64x2: v.Op = ssaop.OpARM64VSUB2D return true + case ssaop.OpSubUint8s: + v.Op = ssaop.OpARM64ZSUBB + return true case ssaop.OpSubUint8x16: v.Op = ssaop.OpARM64VSUB16B return true @@ -2307,9 +2521,13 @@ func RewriteValue(v *ssa.Value) bool { case ssaop.OpTrunc64to8: v.Op = ssaop.OpCopy return true + case ssaop.OpTruncFloat32s: + return rewriteValue_OpTruncFloat32s(v) case ssaop.OpTruncFloat32x4: v.Op = ssaop.OpARM64VFRINTZ4S return true + case ssaop.OpTruncFloat64s: + return rewriteValue_OpTruncFloat64s(v) case ssaop.OpTruncFloat64x2: v.Op = ssaop.OpARM64VFRINTZ2D return true @@ -2346,27 +2564,51 @@ func RewriteValue(v *ssa.Value) bool { case ssaop.OpXor8: v.Op = ssaop.OpARM64XOR return true + case ssaop.OpXorInt16s: + v.Op = ssaop.OpARM64ZEORD + return true case ssaop.OpXorInt16x8: v.Op = ssaop.OpARM64VEOR16B return true + case ssaop.OpXorInt32s: + v.Op = ssaop.OpARM64ZEORD + return true case ssaop.OpXorInt32x4: v.Op = ssaop.OpARM64VEOR16B return true + case ssaop.OpXorInt64s: + v.Op = ssaop.OpARM64ZEORD + return true case ssaop.OpXorInt64x2: v.Op = ssaop.OpARM64VEOR16B return true + case ssaop.OpXorInt8s: + v.Op = ssaop.OpARM64ZEORD + return true case ssaop.OpXorInt8x16: v.Op = ssaop.OpARM64VEOR16B return true + case ssaop.OpXorUint16s: + v.Op = ssaop.OpARM64ZEORD + return true case ssaop.OpXorUint16x8: v.Op = ssaop.OpARM64VEOR16B return true + case ssaop.OpXorUint32s: + v.Op = ssaop.OpARM64ZEORD + return true case ssaop.OpXorUint32x4: v.Op = ssaop.OpARM64VEOR16B return true + case ssaop.OpXorUint64s: + v.Op = ssaop.OpARM64ZEORD + return true case ssaop.OpXorUint64x2: v.Op = ssaop.OpARM64VEOR16B return true + case ssaop.OpXorUint8s: + v.Op = ssaop.OpARM64ZEORD + return true case ssaop.OpXorUint8x16: v.Op = ssaop.OpARM64VEOR16B return true @@ -19844,6 +20086,37 @@ func rewriteValue_OpARM64ZSELB(v *ssa.Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] + // match: (ZSELB (ZABSB x (Select0 (PWHILELTB (MOVDconst [0]) (MOVDconst [32])))) z mask) + // result: (ZABSMergingB z x mask) + for { + if v_0.Op != ssaop.OpARM64ZABSB { + break + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != ssaop.OpSelect0 || v_0_1.Type != types.TypeMask { + break + } + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != ssaop.OpARM64PWHILELTB { + break + } + _ = v_0_1_0.Args[1] + v_0_1_0_0 := v_0_1_0.Args[0] + if v_0_1_0_0.Op != ssaop.OpARM64MOVDconst || ssa.AuxIntToInt64(v_0_1_0_0.AuxInt) != 0 { + break + } + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != ssaop.OpARM64MOVDconst || ssa.AuxIntToInt64(v_0_1_0_1.AuxInt) != 32 { + break + } + z := v_1 + mask := v_2 + v.Reset(ssaop.OpARM64ZABSMergingB) + v.AddArg3(z, x, mask) + return true + } // match: (ZSELB (ZADDB x y) x mask) // result: (ZADDMergingB x y mask) for { @@ -19902,10 +20175,10 @@ func rewriteValue_OpARM64ZSELB(v *ssa.Value) bool { v.AddArg4(z, x, y, mask) return true } - // match: (ZSELB (ZSQADDB x y) x mask) - // result: (ZSQADDMergingB x y mask) + // match: (ZSELB (ZANDD x y) x mask) + // result: (ZANDMergingB x y mask) for { - if v_0.Op != ssaop.OpARM64ZSQADDB { + if v_0.Op != ssaop.OpARM64ZANDD { break } _ = v_0.Args[1] @@ -19918,16 +20191,16 @@ func rewriteValue_OpARM64ZSELB(v *ssa.Value) bool { continue } mask := v_2 - v.Reset(ssaop.OpARM64ZSQADDMergingB) + v.Reset(ssaop.OpARM64ZANDMergingB) v.AddArg3(x, y, mask) return true } break } - // match: (ZSELB (ZSQADDB x y) y mask) - // result: (ZSQADDMergingB y x mask) + // match: (ZSELB (ZANDD x y) y mask) + // result: (ZANDMergingB y x mask) for { - if v_0.Op != ssaop.OpARM64ZSQADDB { + if v_0.Op != ssaop.OpARM64ZANDD { break } _ = v_0.Args[1] @@ -19940,30 +20213,30 @@ func rewriteValue_OpARM64ZSELB(v *ssa.Value) bool { continue } mask := v_2 - v.Reset(ssaop.OpARM64ZSQADDMergingB) + v.Reset(ssaop.OpARM64ZANDMergingB) v.AddArg3(y, x, mask) return true } break } - // match: (ZSELB (ZSQADDB x y) z mask) - // result: (ZSQADDMergingPrefixedB z x y mask) + // match: (ZSELB (ZANDD x y) z mask) + // result: (ZANDMergingPrefixedB z x y mask) for { - if v_0.Op != ssaop.OpARM64ZSQADDB { + if v_0.Op != ssaop.OpARM64ZANDD { break } y := v_0.Args[1] x := v_0.Args[0] z := v_1 mask := v_2 - v.Reset(ssaop.OpARM64ZSQADDMergingPrefixedB) + v.Reset(ssaop.OpARM64ZANDMergingPrefixedB) v.AddArg4(z, x, y, mask) return true } - // match: (ZSELB (ZUQADDB x y) x mask) - // result: (ZUQADDMergingB x y mask) + // match: (ZSELB (ZEORD x y) x mask) + // result: (ZEORMergingB x y mask) for { - if v_0.Op != ssaop.OpARM64ZUQADDB { + if v_0.Op != ssaop.OpARM64ZEORD { break } _ = v_0.Args[1] @@ -19976,16 +20249,16 @@ func rewriteValue_OpARM64ZSELB(v *ssa.Value) bool { continue } mask := v_2 - v.Reset(ssaop.OpARM64ZUQADDMergingB) + v.Reset(ssaop.OpARM64ZEORMergingB) v.AddArg3(x, y, mask) return true } break } - // match: (ZSELB (ZUQADDB x y) y mask) - // result: (ZUQADDMergingB y x mask) + // match: (ZSELB (ZEORD x y) y mask) + // result: (ZEORMergingB y x mask) for { - if v_0.Op != ssaop.OpARM64ZUQADDB { + if v_0.Op != ssaop.OpARM64ZEORD { break } _ = v_0.Args[1] @@ -19998,36 +20271,61 @@ func rewriteValue_OpARM64ZSELB(v *ssa.Value) bool { continue } mask := v_2 - v.Reset(ssaop.OpARM64ZUQADDMergingB) + v.Reset(ssaop.OpARM64ZEORMergingB) v.AddArg3(y, x, mask) return true } break } - // match: (ZSELB (ZUQADDB x y) z mask) - // result: (ZUQADDMergingPrefixedB z x y mask) + // match: (ZSELB (ZEORD x y) z mask) + // result: (ZEORMergingPrefixedB z x y mask) for { - if v_0.Op != ssaop.OpARM64ZUQADDB { + if v_0.Op != ssaop.OpARM64ZEORD { break } y := v_0.Args[1] x := v_0.Args[0] z := v_1 mask := v_2 - v.Reset(ssaop.OpARM64ZUQADDMergingPrefixedB) + v.Reset(ssaop.OpARM64ZEORMergingPrefixedB) v.AddArg4(z, x, y, mask) return true } - return false -} -func rewriteValue_OpARM64ZSELD(v *ssa.Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (ZSELD (ZADDD x y) x mask) - // result: (ZADDMergingD x y mask) + // match: (ZSELB (ZNEGB x (Select0 (PWHILELTB (MOVDconst [0]) (MOVDconst [32])))) z mask) + // result: (ZNEGMergingB z x mask) for { - if v_0.Op != ssaop.OpARM64ZADDD { + if v_0.Op != ssaop.OpARM64ZNEGB { + break + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != ssaop.OpSelect0 || v_0_1.Type != types.TypeMask { + break + } + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != ssaop.OpARM64PWHILELTB { + break + } + _ = v_0_1_0.Args[1] + v_0_1_0_0 := v_0_1_0.Args[0] + if v_0_1_0_0.Op != ssaop.OpARM64MOVDconst || ssa.AuxIntToInt64(v_0_1_0_0.AuxInt) != 0 { + break + } + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != ssaop.OpARM64MOVDconst || ssa.AuxIntToInt64(v_0_1_0_1.AuxInt) != 32 { + break + } + z := v_1 + mask := v_2 + v.Reset(ssaop.OpARM64ZNEGMergingB) + v.AddArg3(z, x, mask) + return true + } + // match: (ZSELB (ZORRD x y) x mask) + // result: (ZORRMergingB x y mask) + for { + if v_0.Op != ssaop.OpARM64ZORRD { break } _ = v_0.Args[1] @@ -20040,16 +20338,16 @@ func rewriteValue_OpARM64ZSELD(v *ssa.Value) bool { continue } mask := v_2 - v.Reset(ssaop.OpARM64ZADDMergingD) + v.Reset(ssaop.OpARM64ZORRMergingB) v.AddArg3(x, y, mask) return true } break } - // match: (ZSELD (ZADDD x y) y mask) - // result: (ZADDMergingD y x mask) + // match: (ZSELB (ZORRD x y) y mask) + // result: (ZORRMergingB y x mask) for { - if v_0.Op != ssaop.OpARM64ZADDD { + if v_0.Op != ssaop.OpARM64ZORRD { break } _ = v_0.Args[1] @@ -20062,30 +20360,30 @@ func rewriteValue_OpARM64ZSELD(v *ssa.Value) bool { continue } mask := v_2 - v.Reset(ssaop.OpARM64ZADDMergingD) + v.Reset(ssaop.OpARM64ZORRMergingB) v.AddArg3(y, x, mask) return true } break } - // match: (ZSELD (ZADDD x y) z mask) - // result: (ZADDMergingPrefixedD z x y mask) + // match: (ZSELB (ZORRD x y) z mask) + // result: (ZORRMergingPrefixedB z x y mask) for { - if v_0.Op != ssaop.OpARM64ZADDD { + if v_0.Op != ssaop.OpARM64ZORRD { break } y := v_0.Args[1] x := v_0.Args[0] z := v_1 mask := v_2 - v.Reset(ssaop.OpARM64ZADDMergingPrefixedD) + v.Reset(ssaop.OpARM64ZORRMergingPrefixedB) v.AddArg4(z, x, y, mask) return true } - // match: (ZSELD (ZFADDD x y) x mask) - // result: (ZFADDMergingD x y mask) + // match: (ZSELB (ZSQADDB x y) x mask) + // result: (ZSQADDMergingB x y mask) for { - if v_0.Op != ssaop.OpARM64ZFADDD { + if v_0.Op != ssaop.OpARM64ZSQADDB { break } _ = v_0.Args[1] @@ -20098,16 +20396,16 @@ func rewriteValue_OpARM64ZSELD(v *ssa.Value) bool { continue } mask := v_2 - v.Reset(ssaop.OpARM64ZFADDMergingD) + v.Reset(ssaop.OpARM64ZSQADDMergingB) v.AddArg3(x, y, mask) return true } break } - // match: (ZSELD (ZFADDD x y) y mask) - // result: (ZFADDMergingD y x mask) + // match: (ZSELB (ZSQADDB x y) y mask) + // result: (ZSQADDMergingB y x mask) for { - if v_0.Op != ssaop.OpARM64ZFADDD { + if v_0.Op != ssaop.OpARM64ZSQADDB { break } _ = v_0.Args[1] @@ -20120,30 +20418,62 @@ func rewriteValue_OpARM64ZSELD(v *ssa.Value) bool { continue } mask := v_2 - v.Reset(ssaop.OpARM64ZFADDMergingD) + v.Reset(ssaop.OpARM64ZSQADDMergingB) v.AddArg3(y, x, mask) return true } break } - // match: (ZSELD (ZFADDD x y) z mask) - // result: (ZFADDMergingPrefixedD z x y mask) + // match: (ZSELB (ZSQADDB x y) z mask) + // result: (ZSQADDMergingPrefixedB z x y mask) for { - if v_0.Op != ssaop.OpARM64ZFADDD { + if v_0.Op != ssaop.OpARM64ZSQADDB { break } y := v_0.Args[1] x := v_0.Args[0] z := v_1 mask := v_2 - v.Reset(ssaop.OpARM64ZFADDMergingPrefixedD) + v.Reset(ssaop.OpARM64ZSQADDMergingPrefixedB) v.AddArg4(z, x, y, mask) return true } - // match: (ZSELD (ZSQADDD x y) x mask) - // result: (ZSQADDMergingD x y mask) + // match: (ZSELB (ZSQSUBB x y) x mask) + // result: (ZSQSUBMergingB x y mask) for { - if v_0.Op != ssaop.OpARM64ZSQADDD { + if v_0.Op != ssaop.OpARM64ZSQSUBB { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + if x != v_1 { + break + } + mask := v_2 + v.Reset(ssaop.OpARM64ZSQSUBMergingB) + v.AddArg3(x, y, mask) + return true + } + // match: (ZSELB (ZSUBB x y) x mask) + // result: (ZSUBMergingB x y mask) + for { + if v_0.Op != ssaop.OpARM64ZSUBB { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + if x != v_1 { + break + } + mask := v_2 + v.Reset(ssaop.OpARM64ZSUBMergingB) + v.AddArg3(x, y, mask) + return true + } + // match: (ZSELB (ZUQADDB x y) x mask) + // result: (ZUQADDMergingB x y mask) + for { + if v_0.Op != ssaop.OpARM64ZUQADDB { break } _ = v_0.Args[1] @@ -20156,16 +20486,16 @@ func rewriteValue_OpARM64ZSELD(v *ssa.Value) bool { continue } mask := v_2 - v.Reset(ssaop.OpARM64ZSQADDMergingD) + v.Reset(ssaop.OpARM64ZUQADDMergingB) v.AddArg3(x, y, mask) return true } break } - // match: (ZSELD (ZSQADDD x y) y mask) - // result: (ZSQADDMergingD y x mask) + // match: (ZSELB (ZUQADDB x y) y mask) + // result: (ZUQADDMergingB y x mask) for { - if v_0.Op != ssaop.OpARM64ZSQADDD { + if v_0.Op != ssaop.OpARM64ZUQADDB { break } _ = v_0.Args[1] @@ -20178,30 +20508,83 @@ func rewriteValue_OpARM64ZSELD(v *ssa.Value) bool { continue } mask := v_2 - v.Reset(ssaop.OpARM64ZSQADDMergingD) + v.Reset(ssaop.OpARM64ZUQADDMergingB) v.AddArg3(y, x, mask) return true } break } - // match: (ZSELD (ZSQADDD x y) z mask) - // result: (ZSQADDMergingPrefixedD z x y mask) + // match: (ZSELB (ZUQADDB x y) z mask) + // result: (ZUQADDMergingPrefixedB z x y mask) for { - if v_0.Op != ssaop.OpARM64ZSQADDD { + if v_0.Op != ssaop.OpARM64ZUQADDB { break } y := v_0.Args[1] x := v_0.Args[0] z := v_1 mask := v_2 - v.Reset(ssaop.OpARM64ZSQADDMergingPrefixedD) + v.Reset(ssaop.OpARM64ZUQADDMergingPrefixedB) v.AddArg4(z, x, y, mask) return true } - // match: (ZSELD (ZUQADDD x y) x mask) - // result: (ZUQADDMergingD x y mask) + // match: (ZSELB (ZUQSUBB x y) x mask) + // result: (ZUQSUBMergingB x y mask) for { - if v_0.Op != ssaop.OpARM64ZUQADDD { + if v_0.Op != ssaop.OpARM64ZUQSUBB { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + if x != v_1 { + break + } + mask := v_2 + v.Reset(ssaop.OpARM64ZUQSUBMergingB) + v.AddArg3(x, y, mask) + return true + } + return false +} +func rewriteValue_OpARM64ZSELD(v *ssa.Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (ZSELD (ZABSD x (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) z mask) + // result: (ZABSMergingD z x mask) + for { + if v_0.Op != ssaop.OpARM64ZABSD { + break + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != ssaop.OpSelect0 || v_0_1.Type != types.TypeMask { + break + } + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != ssaop.OpARM64PWHILELTD { + break + } + _ = v_0_1_0.Args[1] + v_0_1_0_0 := v_0_1_0.Args[0] + if v_0_1_0_0.Op != ssaop.OpARM64MOVDconst || ssa.AuxIntToInt64(v_0_1_0_0.AuxInt) != 0 { + break + } + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != ssaop.OpARM64MOVDconst || ssa.AuxIntToInt64(v_0_1_0_1.AuxInt) != 4 { + break + } + z := v_1 + mask := v_2 + v.Reset(ssaop.OpARM64ZABSMergingD) + v.AddArg3(z, x, mask) + return true + } + // match: (ZSELD (ZADDD x y) x mask) + // result: (ZADDMergingD x y mask) + for { + if v_0.Op != ssaop.OpARM64ZADDD { break } _ = v_0.Args[1] @@ -20214,16 +20597,16 @@ func rewriteValue_OpARM64ZSELD(v *ssa.Value) bool { continue } mask := v_2 - v.Reset(ssaop.OpARM64ZUQADDMergingD) + v.Reset(ssaop.OpARM64ZADDMergingD) v.AddArg3(x, y, mask) return true } break } - // match: (ZSELD (ZUQADDD x y) y mask) - // result: (ZUQADDMergingD y x mask) + // match: (ZSELD (ZADDD x y) y mask) + // result: (ZADDMergingD y x mask) for { - if v_0.Op != ssaop.OpARM64ZUQADDD { + if v_0.Op != ssaop.OpARM64ZADDD { break } _ = v_0.Args[1] @@ -20236,36 +20619,30 @@ func rewriteValue_OpARM64ZSELD(v *ssa.Value) bool { continue } mask := v_2 - v.Reset(ssaop.OpARM64ZUQADDMergingD) + v.Reset(ssaop.OpARM64ZADDMergingD) v.AddArg3(y, x, mask) return true } break } - // match: (ZSELD (ZUQADDD x y) z mask) - // result: (ZUQADDMergingPrefixedD z x y mask) + // match: (ZSELD (ZADDD x y) z mask) + // result: (ZADDMergingPrefixedD z x y mask) for { - if v_0.Op != ssaop.OpARM64ZUQADDD { + if v_0.Op != ssaop.OpARM64ZADDD { break } y := v_0.Args[1] x := v_0.Args[0] z := v_1 mask := v_2 - v.Reset(ssaop.OpARM64ZUQADDMergingPrefixedD) + v.Reset(ssaop.OpARM64ZADDMergingPrefixedD) v.AddArg4(z, x, y, mask) return true } - return false -} -func rewriteValue_OpARM64ZSELH(v *ssa.Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (ZSELH (ZADDH x y) x mask) - // result: (ZADDMergingH x y mask) + // match: (ZSELD (ZANDD x y) x mask) + // result: (ZANDMergingD x y mask) for { - if v_0.Op != ssaop.OpARM64ZADDH { + if v_0.Op != ssaop.OpARM64ZANDD { break } _ = v_0.Args[1] @@ -20278,16 +20655,16 @@ func rewriteValue_OpARM64ZSELH(v *ssa.Value) bool { continue } mask := v_2 - v.Reset(ssaop.OpARM64ZADDMergingH) + v.Reset(ssaop.OpARM64ZANDMergingD) v.AddArg3(x, y, mask) return true } break } - // match: (ZSELH (ZADDH x y) y mask) - // result: (ZADDMergingH y x mask) + // match: (ZSELD (ZANDD x y) y mask) + // result: (ZANDMergingD y x mask) for { - if v_0.Op != ssaop.OpARM64ZADDH { + if v_0.Op != ssaop.OpARM64ZANDD { break } _ = v_0.Args[1] @@ -20300,30 +20677,30 @@ func rewriteValue_OpARM64ZSELH(v *ssa.Value) bool { continue } mask := v_2 - v.Reset(ssaop.OpARM64ZADDMergingH) + v.Reset(ssaop.OpARM64ZANDMergingD) v.AddArg3(y, x, mask) return true } break } - // match: (ZSELH (ZADDH x y) z mask) - // result: (ZADDMergingPrefixedH z x y mask) + // match: (ZSELD (ZANDD x y) z mask) + // result: (ZANDMergingPrefixedD z x y mask) for { - if v_0.Op != ssaop.OpARM64ZADDH { + if v_0.Op != ssaop.OpARM64ZANDD { break } y := v_0.Args[1] x := v_0.Args[0] z := v_1 mask := v_2 - v.Reset(ssaop.OpARM64ZADDMergingPrefixedH) + v.Reset(ssaop.OpARM64ZANDMergingPrefixedD) v.AddArg4(z, x, y, mask) return true } - // match: (ZSELH (ZSQADDH x y) x mask) - // result: (ZSQADDMergingH x y mask) + // match: (ZSELD (ZEORD x y) x mask) + // result: (ZEORMergingD x y mask) for { - if v_0.Op != ssaop.OpARM64ZSQADDH { + if v_0.Op != ssaop.OpARM64ZEORD { break } _ = v_0.Args[1] @@ -20336,16 +20713,16 @@ func rewriteValue_OpARM64ZSELH(v *ssa.Value) bool { continue } mask := v_2 - v.Reset(ssaop.OpARM64ZSQADDMergingH) + v.Reset(ssaop.OpARM64ZEORMergingD) v.AddArg3(x, y, mask) return true } break } - // match: (ZSELH (ZSQADDH x y) y mask) - // result: (ZSQADDMergingH y x mask) + // match: (ZSELD (ZEORD x y) y mask) + // result: (ZEORMergingD y x mask) for { - if v_0.Op != ssaop.OpARM64ZSQADDH { + if v_0.Op != ssaop.OpARM64ZEORD { break } _ = v_0.Args[1] @@ -20358,30 +20735,61 @@ func rewriteValue_OpARM64ZSELH(v *ssa.Value) bool { continue } mask := v_2 - v.Reset(ssaop.OpARM64ZSQADDMergingH) + v.Reset(ssaop.OpARM64ZEORMergingD) v.AddArg3(y, x, mask) return true } break } - // match: (ZSELH (ZSQADDH x y) z mask) - // result: (ZSQADDMergingPrefixedH z x y mask) + // match: (ZSELD (ZEORD x y) z mask) + // result: (ZEORMergingPrefixedD z x y mask) for { - if v_0.Op != ssaop.OpARM64ZSQADDH { + if v_0.Op != ssaop.OpARM64ZEORD { break } y := v_0.Args[1] x := v_0.Args[0] z := v_1 mask := v_2 - v.Reset(ssaop.OpARM64ZSQADDMergingPrefixedH) + v.Reset(ssaop.OpARM64ZEORMergingPrefixedD) v.AddArg4(z, x, y, mask) return true } - // match: (ZSELH (ZUQADDH x y) x mask) - // result: (ZUQADDMergingH x y mask) + // match: (ZSELD (ZFABSD x (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) z mask) + // result: (ZFABSMergingD z x mask) for { - if v_0.Op != ssaop.OpARM64ZUQADDH { + if v_0.Op != ssaop.OpARM64ZFABSD { + break + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != ssaop.OpSelect0 || v_0_1.Type != types.TypeMask { + break + } + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != ssaop.OpARM64PWHILELTD { + break + } + _ = v_0_1_0.Args[1] + v_0_1_0_0 := v_0_1_0.Args[0] + if v_0_1_0_0.Op != ssaop.OpARM64MOVDconst || ssa.AuxIntToInt64(v_0_1_0_0.AuxInt) != 0 { + break + } + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != ssaop.OpARM64MOVDconst || ssa.AuxIntToInt64(v_0_1_0_1.AuxInt) != 4 { + break + } + z := v_1 + mask := v_2 + v.Reset(ssaop.OpARM64ZFABSMergingD) + v.AddArg3(z, x, mask) + return true + } + // match: (ZSELD (ZFADDD x y) x mask) + // result: (ZFADDMergingD x y mask) + for { + if v_0.Op != ssaop.OpARM64ZFADDD { break } _ = v_0.Args[1] @@ -20394,16 +20802,16 @@ func rewriteValue_OpARM64ZSELH(v *ssa.Value) bool { continue } mask := v_2 - v.Reset(ssaop.OpARM64ZUQADDMergingH) + v.Reset(ssaop.OpARM64ZFADDMergingD) v.AddArg3(x, y, mask) return true } break } - // match: (ZSELH (ZUQADDH x y) y mask) - // result: (ZUQADDMergingH y x mask) + // match: (ZSELD (ZFADDD x y) y mask) + // result: (ZFADDMergingD y x mask) for { - if v_0.Op != ssaop.OpARM64ZUQADDH { + if v_0.Op != ssaop.OpARM64ZFADDD { break } _ = v_0.Args[1] @@ -20416,94 +20824,139 @@ func rewriteValue_OpARM64ZSELH(v *ssa.Value) bool { continue } mask := v_2 - v.Reset(ssaop.OpARM64ZUQADDMergingH) + v.Reset(ssaop.OpARM64ZFADDMergingD) v.AddArg3(y, x, mask) return true } break } - // match: (ZSELH (ZUQADDH x y) z mask) - // result: (ZUQADDMergingPrefixedH z x y mask) + // match: (ZSELD (ZFADDD x y) z mask) + // result: (ZFADDMergingPrefixedD z x y mask) for { - if v_0.Op != ssaop.OpARM64ZUQADDH { + if v_0.Op != ssaop.OpARM64ZFADDD { break } y := v_0.Args[1] x := v_0.Args[0] z := v_1 mask := v_2 - v.Reset(ssaop.OpARM64ZUQADDMergingPrefixedH) + v.Reset(ssaop.OpARM64ZFADDMergingPrefixedD) v.AddArg4(z, x, y, mask) return true } - return false -} -func rewriteValue_OpARM64ZSELS(v *ssa.Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (ZSELS (ZADDS x y) x mask) - // result: (ZADDMergingS x y mask) + // match: (ZSELD (ZFNEGD x (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) z mask) + // result: (ZFNEGMergingD z x mask) for { - if v_0.Op != ssaop.OpARM64ZADDS { + if v_0.Op != ssaop.OpARM64ZFNEGD { break } _ = v_0.Args[1] - v_0_0 := v_0.Args[0] + x := v_0.Args[0] v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - x := v_0_0 - y := v_0_1 - if x != v_1 { - continue - } - mask := v_2 - v.Reset(ssaop.OpARM64ZADDMergingS) - v.AddArg3(x, y, mask) - return true + if v_0_1.Op != ssaop.OpSelect0 || v_0_1.Type != types.TypeMask { + break } - break + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != ssaop.OpARM64PWHILELTD { + break + } + _ = v_0_1_0.Args[1] + v_0_1_0_0 := v_0_1_0.Args[0] + if v_0_1_0_0.Op != ssaop.OpARM64MOVDconst || ssa.AuxIntToInt64(v_0_1_0_0.AuxInt) != 0 { + break + } + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != ssaop.OpARM64MOVDconst || ssa.AuxIntToInt64(v_0_1_0_1.AuxInt) != 4 { + break + } + z := v_1 + mask := v_2 + v.Reset(ssaop.OpARM64ZFNEGMergingD) + v.AddArg3(z, x, mask) + return true } - // match: (ZSELS (ZADDS x y) y mask) - // result: (ZADDMergingS y x mask) + // match: (ZSELD (ZFSQRTD x (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) z mask) + // result: (ZFSQRTMergingD z x mask) for { - if v_0.Op != ssaop.OpARM64ZADDS { + if v_0.Op != ssaop.OpARM64ZFSQRTD { break } _ = v_0.Args[1] - v_0_0 := v_0.Args[0] + x := v_0.Args[0] v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - x := v_0_0 - y := v_0_1 - if y != v_1 { - continue - } - mask := v_2 - v.Reset(ssaop.OpARM64ZADDMergingS) - v.AddArg3(y, x, mask) - return true + if v_0_1.Op != ssaop.OpSelect0 || v_0_1.Type != types.TypeMask { + break } - break + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != ssaop.OpARM64PWHILELTD { + break + } + _ = v_0_1_0.Args[1] + v_0_1_0_0 := v_0_1_0.Args[0] + if v_0_1_0_0.Op != ssaop.OpARM64MOVDconst || ssa.AuxIntToInt64(v_0_1_0_0.AuxInt) != 0 { + break + } + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != ssaop.OpARM64MOVDconst || ssa.AuxIntToInt64(v_0_1_0_1.AuxInt) != 4 { + break + } + z := v_1 + mask := v_2 + v.Reset(ssaop.OpARM64ZFSQRTMergingD) + v.AddArg3(z, x, mask) + return true } - // match: (ZSELS (ZADDS x y) z mask) - // result: (ZADDMergingPrefixedS z x y mask) + // match: (ZSELD (ZFSUBD x y) x mask) + // result: (ZFSUBMergingD x y mask) for { - if v_0.Op != ssaop.OpARM64ZADDS { + if v_0.Op != ssaop.OpARM64ZFSUBD { break } y := v_0.Args[1] x := v_0.Args[0] + if x != v_1 { + break + } + mask := v_2 + v.Reset(ssaop.OpARM64ZFSUBMergingD) + v.AddArg3(x, y, mask) + return true + } + // match: (ZSELD (ZNEGD x (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) z mask) + // result: (ZNEGMergingD z x mask) + for { + if v_0.Op != ssaop.OpARM64ZNEGD { + break + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != ssaop.OpSelect0 || v_0_1.Type != types.TypeMask { + break + } + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != ssaop.OpARM64PWHILELTD { + break + } + _ = v_0_1_0.Args[1] + v_0_1_0_0 := v_0_1_0.Args[0] + if v_0_1_0_0.Op != ssaop.OpARM64MOVDconst || ssa.AuxIntToInt64(v_0_1_0_0.AuxInt) != 0 { + break + } + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != ssaop.OpARM64MOVDconst || ssa.AuxIntToInt64(v_0_1_0_1.AuxInt) != 4 { + break + } z := v_1 mask := v_2 - v.Reset(ssaop.OpARM64ZADDMergingPrefixedS) - v.AddArg4(z, x, y, mask) + v.Reset(ssaop.OpARM64ZNEGMergingD) + v.AddArg3(z, x, mask) return true } - // match: (ZSELS (ZFADDS x y) x mask) - // result: (ZFADDMergingS x y mask) + // match: (ZSELD (ZORRD x y) x mask) + // result: (ZORRMergingD x y mask) for { - if v_0.Op != ssaop.OpARM64ZFADDS { + if v_0.Op != ssaop.OpARM64ZORRD { break } _ = v_0.Args[1] @@ -20516,16 +20969,16 @@ func rewriteValue_OpARM64ZSELS(v *ssa.Value) bool { continue } mask := v_2 - v.Reset(ssaop.OpARM64ZFADDMergingS) + v.Reset(ssaop.OpARM64ZORRMergingD) v.AddArg3(x, y, mask) return true } break } - // match: (ZSELS (ZFADDS x y) y mask) - // result: (ZFADDMergingS y x mask) + // match: (ZSELD (ZORRD x y) y mask) + // result: (ZORRMergingD y x mask) for { - if v_0.Op != ssaop.OpARM64ZFADDS { + if v_0.Op != ssaop.OpARM64ZORRD { break } _ = v_0.Args[1] @@ -20538,30 +20991,30 @@ func rewriteValue_OpARM64ZSELS(v *ssa.Value) bool { continue } mask := v_2 - v.Reset(ssaop.OpARM64ZFADDMergingS) + v.Reset(ssaop.OpARM64ZORRMergingD) v.AddArg3(y, x, mask) return true } break } - // match: (ZSELS (ZFADDS x y) z mask) - // result: (ZFADDMergingPrefixedS z x y mask) + // match: (ZSELD (ZORRD x y) z mask) + // result: (ZORRMergingPrefixedD z x y mask) for { - if v_0.Op != ssaop.OpARM64ZFADDS { + if v_0.Op != ssaop.OpARM64ZORRD { break } y := v_0.Args[1] x := v_0.Args[0] z := v_1 mask := v_2 - v.Reset(ssaop.OpARM64ZFADDMergingPrefixedS) + v.Reset(ssaop.OpARM64ZORRMergingPrefixedD) v.AddArg4(z, x, y, mask) return true } - // match: (ZSELS (ZSQADDS x y) x mask) - // result: (ZSQADDMergingS x y mask) + // match: (ZSELD (ZSQADDD x y) x mask) + // result: (ZSQADDMergingD x y mask) for { - if v_0.Op != ssaop.OpARM64ZSQADDS { + if v_0.Op != ssaop.OpARM64ZSQADDD { break } _ = v_0.Args[1] @@ -20574,16 +21027,16 @@ func rewriteValue_OpARM64ZSELS(v *ssa.Value) bool { continue } mask := v_2 - v.Reset(ssaop.OpARM64ZSQADDMergingS) + v.Reset(ssaop.OpARM64ZSQADDMergingD) v.AddArg3(x, y, mask) return true } break } - // match: (ZSELS (ZSQADDS x y) y mask) - // result: (ZSQADDMergingS y x mask) + // match: (ZSELD (ZSQADDD x y) y mask) + // result: (ZSQADDMergingD y x mask) for { - if v_0.Op != ssaop.OpARM64ZSQADDS { + if v_0.Op != ssaop.OpARM64ZSQADDD { break } _ = v_0.Args[1] @@ -20596,30 +21049,62 @@ func rewriteValue_OpARM64ZSELS(v *ssa.Value) bool { continue } mask := v_2 - v.Reset(ssaop.OpARM64ZSQADDMergingS) + v.Reset(ssaop.OpARM64ZSQADDMergingD) v.AddArg3(y, x, mask) return true } break } - // match: (ZSELS (ZSQADDS x y) z mask) - // result: (ZSQADDMergingPrefixedS z x y mask) + // match: (ZSELD (ZSQADDD x y) z mask) + // result: (ZSQADDMergingPrefixedD z x y mask) for { - if v_0.Op != ssaop.OpARM64ZSQADDS { + if v_0.Op != ssaop.OpARM64ZSQADDD { break } y := v_0.Args[1] x := v_0.Args[0] z := v_1 mask := v_2 - v.Reset(ssaop.OpARM64ZSQADDMergingPrefixedS) + v.Reset(ssaop.OpARM64ZSQADDMergingPrefixedD) v.AddArg4(z, x, y, mask) return true } - // match: (ZSELS (ZUQADDS x y) x mask) - // result: (ZUQADDMergingS x y mask) + // match: (ZSELD (ZSQSUBD x y) x mask) + // result: (ZSQSUBMergingD x y mask) for { - if v_0.Op != ssaop.OpARM64ZUQADDS { + if v_0.Op != ssaop.OpARM64ZSQSUBD { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + if x != v_1 { + break + } + mask := v_2 + v.Reset(ssaop.OpARM64ZSQSUBMergingD) + v.AddArg3(x, y, mask) + return true + } + // match: (ZSELD (ZSUBD x y) x mask) + // result: (ZSUBMergingD x y mask) + for { + if v_0.Op != ssaop.OpARM64ZSUBD { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + if x != v_1 { + break + } + mask := v_2 + v.Reset(ssaop.OpARM64ZSUBMergingD) + v.AddArg3(x, y, mask) + return true + } + // match: (ZSELD (ZUQADDD x y) x mask) + // result: (ZUQADDMergingD x y mask) + for { + if v_0.Op != ssaop.OpARM64ZUQADDD { break } _ = v_0.Args[1] @@ -20632,16 +21117,16 @@ func rewriteValue_OpARM64ZSELS(v *ssa.Value) bool { continue } mask := v_2 - v.Reset(ssaop.OpARM64ZUQADDMergingS) + v.Reset(ssaop.OpARM64ZUQADDMergingD) v.AddArg3(x, y, mask) return true } break } - // match: (ZSELS (ZUQADDS x y) y mask) - // result: (ZUQADDMergingS y x mask) + // match: (ZSELD (ZUQADDD x y) y mask) + // result: (ZUQADDMergingD y x mask) for { - if v_0.Op != ssaop.OpARM64ZUQADDS { + if v_0.Op != ssaop.OpARM64ZUQADDD { break } _ = v_0.Args[1] @@ -20654,645 +21139,2564 @@ func rewriteValue_OpARM64ZSELS(v *ssa.Value) bool { continue } mask := v_2 - v.Reset(ssaop.OpARM64ZUQADDMergingS) + v.Reset(ssaop.OpARM64ZUQADDMergingD) v.AddArg3(y, x, mask) return true } break } - // match: (ZSELS (ZUQADDS x y) z mask) - // result: (ZUQADDMergingPrefixedS z x y mask) + // match: (ZSELD (ZUQADDD x y) z mask) + // result: (ZUQADDMergingPrefixedD z x y mask) for { - if v_0.Op != ssaop.OpARM64ZUQADDS { + if v_0.Op != ssaop.OpARM64ZUQADDD { break } y := v_0.Args[1] x := v_0.Args[0] z := v_1 mask := v_2 - v.Reset(ssaop.OpARM64ZUQADDMergingPrefixedS) + v.Reset(ssaop.OpARM64ZUQADDMergingPrefixedD) v.AddArg4(z, x, y, mask) return true } + // match: (ZSELD (ZUQSUBD x y) x mask) + // result: (ZUQSUBMergingD x y mask) + for { + if v_0.Op != ssaop.OpARM64ZUQSUBD { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + if x != v_1 { + break + } + mask := v_2 + v.Reset(ssaop.OpARM64ZUQSUBMergingD) + v.AddArg3(x, y, mask) + return true + } return false } -func rewriteValue_OpAddr(v *ssa.Value) bool { +func rewriteValue_OpARM64ZSELH(v *ssa.Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] v_0 := v.Args[0] - // match: (Addr {sym} base) - // result: (MOVDaddr {sym} base) + // match: (ZSELH (ZABSH x (Select0 (PWHILELTH (MOVDconst [0]) (MOVDconst [16])))) z mask) + // result: (ZABSMergingH z x mask) for { - sym := ssa.AuxToSym(v.Aux) - base := v_0 + if v_0.Op != ssaop.OpARM64ZABSH { + break + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != ssaop.OpSelect0 || v_0_1.Type != types.TypeMask { + break + } + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != ssaop.OpARM64PWHILELTH { + break + } + _ = v_0_1_0.Args[1] + v_0_1_0_0 := v_0_1_0.Args[0] + if v_0_1_0_0.Op != ssaop.OpARM64MOVDconst || ssa.AuxIntToInt64(v_0_1_0_0.AuxInt) != 0 { + break + } + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != ssaop.OpARM64MOVDconst || ssa.AuxIntToInt64(v_0_1_0_1.AuxInt) != 16 { + break + } + z := v_1 + mask := v_2 + v.Reset(ssaop.OpARM64ZABSMergingH) + v.AddArg3(z, x, mask) + return true + } + // match: (ZSELH (ZADDH x y) x mask) + // result: (ZADDMergingH x y mask) + for { + if v_0.Op != ssaop.OpARM64ZADDH { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + x := v_0_0 + y := v_0_1 + if x != v_1 { + continue + } + mask := v_2 + v.Reset(ssaop.OpARM64ZADDMergingH) + v.AddArg3(x, y, mask) + return true + } + break + } + // match: (ZSELH (ZADDH x y) y mask) + // result: (ZADDMergingH y x mask) + for { + if v_0.Op != ssaop.OpARM64ZADDH { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + x := v_0_0 + y := v_0_1 + if y != v_1 { + continue + } + mask := v_2 + v.Reset(ssaop.OpARM64ZADDMergingH) + v.AddArg3(y, x, mask) + return true + } + break + } + // match: (ZSELH (ZADDH x y) z mask) + // result: (ZADDMergingPrefixedH z x y mask) + for { + if v_0.Op != ssaop.OpARM64ZADDH { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + z := v_1 + mask := v_2 + v.Reset(ssaop.OpARM64ZADDMergingPrefixedH) + v.AddArg4(z, x, y, mask) + return true + } + // match: (ZSELH (ZANDD x y) x mask) + // result: (ZANDMergingH x y mask) + for { + if v_0.Op != ssaop.OpARM64ZANDD { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + x := v_0_0 + y := v_0_1 + if x != v_1 { + continue + } + mask := v_2 + v.Reset(ssaop.OpARM64ZANDMergingH) + v.AddArg3(x, y, mask) + return true + } + break + } + // match: (ZSELH (ZANDD x y) y mask) + // result: (ZANDMergingH y x mask) + for { + if v_0.Op != ssaop.OpARM64ZANDD { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + x := v_0_0 + y := v_0_1 + if y != v_1 { + continue + } + mask := v_2 + v.Reset(ssaop.OpARM64ZANDMergingH) + v.AddArg3(y, x, mask) + return true + } + break + } + // match: (ZSELH (ZANDD x y) z mask) + // result: (ZANDMergingPrefixedH z x y mask) + for { + if v_0.Op != ssaop.OpARM64ZANDD { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + z := v_1 + mask := v_2 + v.Reset(ssaop.OpARM64ZANDMergingPrefixedH) + v.AddArg4(z, x, y, mask) + return true + } + // match: (ZSELH (ZEORD x y) x mask) + // result: (ZEORMergingH x y mask) + for { + if v_0.Op != ssaop.OpARM64ZEORD { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + x := v_0_0 + y := v_0_1 + if x != v_1 { + continue + } + mask := v_2 + v.Reset(ssaop.OpARM64ZEORMergingH) + v.AddArg3(x, y, mask) + return true + } + break + } + // match: (ZSELH (ZEORD x y) y mask) + // result: (ZEORMergingH y x mask) + for { + if v_0.Op != ssaop.OpARM64ZEORD { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + x := v_0_0 + y := v_0_1 + if y != v_1 { + continue + } + mask := v_2 + v.Reset(ssaop.OpARM64ZEORMergingH) + v.AddArg3(y, x, mask) + return true + } + break + } + // match: (ZSELH (ZEORD x y) z mask) + // result: (ZEORMergingPrefixedH z x y mask) + for { + if v_0.Op != ssaop.OpARM64ZEORD { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + z := v_1 + mask := v_2 + v.Reset(ssaop.OpARM64ZEORMergingPrefixedH) + v.AddArg4(z, x, y, mask) + return true + } + // match: (ZSELH (ZNEGH x (Select0 (PWHILELTH (MOVDconst [0]) (MOVDconst [16])))) z mask) + // result: (ZNEGMergingH z x mask) + for { + if v_0.Op != ssaop.OpARM64ZNEGH { + break + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != ssaop.OpSelect0 || v_0_1.Type != types.TypeMask { + break + } + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != ssaop.OpARM64PWHILELTH { + break + } + _ = v_0_1_0.Args[1] + v_0_1_0_0 := v_0_1_0.Args[0] + if v_0_1_0_0.Op != ssaop.OpARM64MOVDconst || ssa.AuxIntToInt64(v_0_1_0_0.AuxInt) != 0 { + break + } + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != ssaop.OpARM64MOVDconst || ssa.AuxIntToInt64(v_0_1_0_1.AuxInt) != 16 { + break + } + z := v_1 + mask := v_2 + v.Reset(ssaop.OpARM64ZNEGMergingH) + v.AddArg3(z, x, mask) + return true + } + // match: (ZSELH (ZORRD x y) x mask) + // result: (ZORRMergingH x y mask) + for { + if v_0.Op != ssaop.OpARM64ZORRD { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + x := v_0_0 + y := v_0_1 + if x != v_1 { + continue + } + mask := v_2 + v.Reset(ssaop.OpARM64ZORRMergingH) + v.AddArg3(x, y, mask) + return true + } + break + } + // match: (ZSELH (ZORRD x y) y mask) + // result: (ZORRMergingH y x mask) + for { + if v_0.Op != ssaop.OpARM64ZORRD { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + x := v_0_0 + y := v_0_1 + if y != v_1 { + continue + } + mask := v_2 + v.Reset(ssaop.OpARM64ZORRMergingH) + v.AddArg3(y, x, mask) + return true + } + break + } + // match: (ZSELH (ZORRD x y) z mask) + // result: (ZORRMergingPrefixedH z x y mask) + for { + if v_0.Op != ssaop.OpARM64ZORRD { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + z := v_1 + mask := v_2 + v.Reset(ssaop.OpARM64ZORRMergingPrefixedH) + v.AddArg4(z, x, y, mask) + return true + } + // match: (ZSELH (ZSQADDH x y) x mask) + // result: (ZSQADDMergingH x y mask) + for { + if v_0.Op != ssaop.OpARM64ZSQADDH { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + x := v_0_0 + y := v_0_1 + if x != v_1 { + continue + } + mask := v_2 + v.Reset(ssaop.OpARM64ZSQADDMergingH) + v.AddArg3(x, y, mask) + return true + } + break + } + // match: (ZSELH (ZSQADDH x y) y mask) + // result: (ZSQADDMergingH y x mask) + for { + if v_0.Op != ssaop.OpARM64ZSQADDH { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + x := v_0_0 + y := v_0_1 + if y != v_1 { + continue + } + mask := v_2 + v.Reset(ssaop.OpARM64ZSQADDMergingH) + v.AddArg3(y, x, mask) + return true + } + break + } + // match: (ZSELH (ZSQADDH x y) z mask) + // result: (ZSQADDMergingPrefixedH z x y mask) + for { + if v_0.Op != ssaop.OpARM64ZSQADDH { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + z := v_1 + mask := v_2 + v.Reset(ssaop.OpARM64ZSQADDMergingPrefixedH) + v.AddArg4(z, x, y, mask) + return true + } + // match: (ZSELH (ZSQSUBH x y) x mask) + // result: (ZSQSUBMergingH x y mask) + for { + if v_0.Op != ssaop.OpARM64ZSQSUBH { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + if x != v_1 { + break + } + mask := v_2 + v.Reset(ssaop.OpARM64ZSQSUBMergingH) + v.AddArg3(x, y, mask) + return true + } + // match: (ZSELH (ZSUBH x y) x mask) + // result: (ZSUBMergingH x y mask) + for { + if v_0.Op != ssaop.OpARM64ZSUBH { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + if x != v_1 { + break + } + mask := v_2 + v.Reset(ssaop.OpARM64ZSUBMergingH) + v.AddArg3(x, y, mask) + return true + } + // match: (ZSELH (ZUQADDH x y) x mask) + // result: (ZUQADDMergingH x y mask) + for { + if v_0.Op != ssaop.OpARM64ZUQADDH { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + x := v_0_0 + y := v_0_1 + if x != v_1 { + continue + } + mask := v_2 + v.Reset(ssaop.OpARM64ZUQADDMergingH) + v.AddArg3(x, y, mask) + return true + } + break + } + // match: (ZSELH (ZUQADDH x y) y mask) + // result: (ZUQADDMergingH y x mask) + for { + if v_0.Op != ssaop.OpARM64ZUQADDH { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + x := v_0_0 + y := v_0_1 + if y != v_1 { + continue + } + mask := v_2 + v.Reset(ssaop.OpARM64ZUQADDMergingH) + v.AddArg3(y, x, mask) + return true + } + break + } + // match: (ZSELH (ZUQADDH x y) z mask) + // result: (ZUQADDMergingPrefixedH z x y mask) + for { + if v_0.Op != ssaop.OpARM64ZUQADDH { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + z := v_1 + mask := v_2 + v.Reset(ssaop.OpARM64ZUQADDMergingPrefixedH) + v.AddArg4(z, x, y, mask) + return true + } + // match: (ZSELH (ZUQSUBH x y) x mask) + // result: (ZUQSUBMergingH x y mask) + for { + if v_0.Op != ssaop.OpARM64ZUQSUBH { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + if x != v_1 { + break + } + mask := v_2 + v.Reset(ssaop.OpARM64ZUQSUBMergingH) + v.AddArg3(x, y, mask) + return true + } + return false +} +func rewriteValue_OpARM64ZSELS(v *ssa.Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (ZSELS (ZABSS x (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) z mask) + // result: (ZABSMergingS z x mask) + for { + if v_0.Op != ssaop.OpARM64ZABSS { + break + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != ssaop.OpSelect0 || v_0_1.Type != types.TypeMask { + break + } + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != ssaop.OpARM64PWHILELTS { + break + } + _ = v_0_1_0.Args[1] + v_0_1_0_0 := v_0_1_0.Args[0] + if v_0_1_0_0.Op != ssaop.OpARM64MOVDconst || ssa.AuxIntToInt64(v_0_1_0_0.AuxInt) != 0 { + break + } + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != ssaop.OpARM64MOVDconst || ssa.AuxIntToInt64(v_0_1_0_1.AuxInt) != 8 { + break + } + z := v_1 + mask := v_2 + v.Reset(ssaop.OpARM64ZABSMergingS) + v.AddArg3(z, x, mask) + return true + } + // match: (ZSELS (ZADDS x y) x mask) + // result: (ZADDMergingS x y mask) + for { + if v_0.Op != ssaop.OpARM64ZADDS { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + x := v_0_0 + y := v_0_1 + if x != v_1 { + continue + } + mask := v_2 + v.Reset(ssaop.OpARM64ZADDMergingS) + v.AddArg3(x, y, mask) + return true + } + break + } + // match: (ZSELS (ZADDS x y) y mask) + // result: (ZADDMergingS y x mask) + for { + if v_0.Op != ssaop.OpARM64ZADDS { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + x := v_0_0 + y := v_0_1 + if y != v_1 { + continue + } + mask := v_2 + v.Reset(ssaop.OpARM64ZADDMergingS) + v.AddArg3(y, x, mask) + return true + } + break + } + // match: (ZSELS (ZADDS x y) z mask) + // result: (ZADDMergingPrefixedS z x y mask) + for { + if v_0.Op != ssaop.OpARM64ZADDS { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + z := v_1 + mask := v_2 + v.Reset(ssaop.OpARM64ZADDMergingPrefixedS) + v.AddArg4(z, x, y, mask) + return true + } + // match: (ZSELS (ZANDD x y) x mask) + // result: (ZANDMergingS x y mask) + for { + if v_0.Op != ssaop.OpARM64ZANDD { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + x := v_0_0 + y := v_0_1 + if x != v_1 { + continue + } + mask := v_2 + v.Reset(ssaop.OpARM64ZANDMergingS) + v.AddArg3(x, y, mask) + return true + } + break + } + // match: (ZSELS (ZANDD x y) y mask) + // result: (ZANDMergingS y x mask) + for { + if v_0.Op != ssaop.OpARM64ZANDD { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + x := v_0_0 + y := v_0_1 + if y != v_1 { + continue + } + mask := v_2 + v.Reset(ssaop.OpARM64ZANDMergingS) + v.AddArg3(y, x, mask) + return true + } + break + } + // match: (ZSELS (ZANDD x y) z mask) + // result: (ZANDMergingPrefixedS z x y mask) + for { + if v_0.Op != ssaop.OpARM64ZANDD { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + z := v_1 + mask := v_2 + v.Reset(ssaop.OpARM64ZANDMergingPrefixedS) + v.AddArg4(z, x, y, mask) + return true + } + // match: (ZSELS (ZEORD x y) x mask) + // result: (ZEORMergingS x y mask) + for { + if v_0.Op != ssaop.OpARM64ZEORD { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + x := v_0_0 + y := v_0_1 + if x != v_1 { + continue + } + mask := v_2 + v.Reset(ssaop.OpARM64ZEORMergingS) + v.AddArg3(x, y, mask) + return true + } + break + } + // match: (ZSELS (ZEORD x y) y mask) + // result: (ZEORMergingS y x mask) + for { + if v_0.Op != ssaop.OpARM64ZEORD { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + x := v_0_0 + y := v_0_1 + if y != v_1 { + continue + } + mask := v_2 + v.Reset(ssaop.OpARM64ZEORMergingS) + v.AddArg3(y, x, mask) + return true + } + break + } + // match: (ZSELS (ZEORD x y) z mask) + // result: (ZEORMergingPrefixedS z x y mask) + for { + if v_0.Op != ssaop.OpARM64ZEORD { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + z := v_1 + mask := v_2 + v.Reset(ssaop.OpARM64ZEORMergingPrefixedS) + v.AddArg4(z, x, y, mask) + return true + } + // match: (ZSELS (ZFABSS x (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) z mask) + // result: (ZFABSMergingS z x mask) + for { + if v_0.Op != ssaop.OpARM64ZFABSS { + break + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != ssaop.OpSelect0 || v_0_1.Type != types.TypeMask { + break + } + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != ssaop.OpARM64PWHILELTS { + break + } + _ = v_0_1_0.Args[1] + v_0_1_0_0 := v_0_1_0.Args[0] + if v_0_1_0_0.Op != ssaop.OpARM64MOVDconst || ssa.AuxIntToInt64(v_0_1_0_0.AuxInt) != 0 { + break + } + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != ssaop.OpARM64MOVDconst || ssa.AuxIntToInt64(v_0_1_0_1.AuxInt) != 8 { + break + } + z := v_1 + mask := v_2 + v.Reset(ssaop.OpARM64ZFABSMergingS) + v.AddArg3(z, x, mask) + return true + } + // match: (ZSELS (ZFADDS x y) x mask) + // result: (ZFADDMergingS x y mask) + for { + if v_0.Op != ssaop.OpARM64ZFADDS { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + x := v_0_0 + y := v_0_1 + if x != v_1 { + continue + } + mask := v_2 + v.Reset(ssaop.OpARM64ZFADDMergingS) + v.AddArg3(x, y, mask) + return true + } + break + } + // match: (ZSELS (ZFADDS x y) y mask) + // result: (ZFADDMergingS y x mask) + for { + if v_0.Op != ssaop.OpARM64ZFADDS { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + x := v_0_0 + y := v_0_1 + if y != v_1 { + continue + } + mask := v_2 + v.Reset(ssaop.OpARM64ZFADDMergingS) + v.AddArg3(y, x, mask) + return true + } + break + } + // match: (ZSELS (ZFADDS x y) z mask) + // result: (ZFADDMergingPrefixedS z x y mask) + for { + if v_0.Op != ssaop.OpARM64ZFADDS { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + z := v_1 + mask := v_2 + v.Reset(ssaop.OpARM64ZFADDMergingPrefixedS) + v.AddArg4(z, x, y, mask) + return true + } + // match: (ZSELS (ZFNEGS x (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) z mask) + // result: (ZFNEGMergingS z x mask) + for { + if v_0.Op != ssaop.OpARM64ZFNEGS { + break + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != ssaop.OpSelect0 || v_0_1.Type != types.TypeMask { + break + } + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != ssaop.OpARM64PWHILELTS { + break + } + _ = v_0_1_0.Args[1] + v_0_1_0_0 := v_0_1_0.Args[0] + if v_0_1_0_0.Op != ssaop.OpARM64MOVDconst || ssa.AuxIntToInt64(v_0_1_0_0.AuxInt) != 0 { + break + } + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != ssaop.OpARM64MOVDconst || ssa.AuxIntToInt64(v_0_1_0_1.AuxInt) != 8 { + break + } + z := v_1 + mask := v_2 + v.Reset(ssaop.OpARM64ZFNEGMergingS) + v.AddArg3(z, x, mask) + return true + } + // match: (ZSELS (ZFSQRTS x (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) z mask) + // result: (ZFSQRTMergingS z x mask) + for { + if v_0.Op != ssaop.OpARM64ZFSQRTS { + break + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != ssaop.OpSelect0 || v_0_1.Type != types.TypeMask { + break + } + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != ssaop.OpARM64PWHILELTS { + break + } + _ = v_0_1_0.Args[1] + v_0_1_0_0 := v_0_1_0.Args[0] + if v_0_1_0_0.Op != ssaop.OpARM64MOVDconst || ssa.AuxIntToInt64(v_0_1_0_0.AuxInt) != 0 { + break + } + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != ssaop.OpARM64MOVDconst || ssa.AuxIntToInt64(v_0_1_0_1.AuxInt) != 8 { + break + } + z := v_1 + mask := v_2 + v.Reset(ssaop.OpARM64ZFSQRTMergingS) + v.AddArg3(z, x, mask) + return true + } + // match: (ZSELS (ZFSUBS x y) x mask) + // result: (ZFSUBMergingS x y mask) + for { + if v_0.Op != ssaop.OpARM64ZFSUBS { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + if x != v_1 { + break + } + mask := v_2 + v.Reset(ssaop.OpARM64ZFSUBMergingS) + v.AddArg3(x, y, mask) + return true + } + // match: (ZSELS (ZNEGS x (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) z mask) + // result: (ZNEGMergingS z x mask) + for { + if v_0.Op != ssaop.OpARM64ZNEGS { + break + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != ssaop.OpSelect0 || v_0_1.Type != types.TypeMask { + break + } + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != ssaop.OpARM64PWHILELTS { + break + } + _ = v_0_1_0.Args[1] + v_0_1_0_0 := v_0_1_0.Args[0] + if v_0_1_0_0.Op != ssaop.OpARM64MOVDconst || ssa.AuxIntToInt64(v_0_1_0_0.AuxInt) != 0 { + break + } + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != ssaop.OpARM64MOVDconst || ssa.AuxIntToInt64(v_0_1_0_1.AuxInt) != 8 { + break + } + z := v_1 + mask := v_2 + v.Reset(ssaop.OpARM64ZNEGMergingS) + v.AddArg3(z, x, mask) + return true + } + // match: (ZSELS (ZORRD x y) x mask) + // result: (ZORRMergingS x y mask) + for { + if v_0.Op != ssaop.OpARM64ZORRD { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + x := v_0_0 + y := v_0_1 + if x != v_1 { + continue + } + mask := v_2 + v.Reset(ssaop.OpARM64ZORRMergingS) + v.AddArg3(x, y, mask) + return true + } + break + } + // match: (ZSELS (ZORRD x y) y mask) + // result: (ZORRMergingS y x mask) + for { + if v_0.Op != ssaop.OpARM64ZORRD { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + x := v_0_0 + y := v_0_1 + if y != v_1 { + continue + } + mask := v_2 + v.Reset(ssaop.OpARM64ZORRMergingS) + v.AddArg3(y, x, mask) + return true + } + break + } + // match: (ZSELS (ZORRD x y) z mask) + // result: (ZORRMergingPrefixedS z x y mask) + for { + if v_0.Op != ssaop.OpARM64ZORRD { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + z := v_1 + mask := v_2 + v.Reset(ssaop.OpARM64ZORRMergingPrefixedS) + v.AddArg4(z, x, y, mask) + return true + } + // match: (ZSELS (ZSQADDS x y) x mask) + // result: (ZSQADDMergingS x y mask) + for { + if v_0.Op != ssaop.OpARM64ZSQADDS { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + x := v_0_0 + y := v_0_1 + if x != v_1 { + continue + } + mask := v_2 + v.Reset(ssaop.OpARM64ZSQADDMergingS) + v.AddArg3(x, y, mask) + return true + } + break + } + // match: (ZSELS (ZSQADDS x y) y mask) + // result: (ZSQADDMergingS y x mask) + for { + if v_0.Op != ssaop.OpARM64ZSQADDS { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + x := v_0_0 + y := v_0_1 + if y != v_1 { + continue + } + mask := v_2 + v.Reset(ssaop.OpARM64ZSQADDMergingS) + v.AddArg3(y, x, mask) + return true + } + break + } + // match: (ZSELS (ZSQADDS x y) z mask) + // result: (ZSQADDMergingPrefixedS z x y mask) + for { + if v_0.Op != ssaop.OpARM64ZSQADDS { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + z := v_1 + mask := v_2 + v.Reset(ssaop.OpARM64ZSQADDMergingPrefixedS) + v.AddArg4(z, x, y, mask) + return true + } + // match: (ZSELS (ZSQSUBS x y) x mask) + // result: (ZSQSUBMergingS x y mask) + for { + if v_0.Op != ssaop.OpARM64ZSQSUBS { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + if x != v_1 { + break + } + mask := v_2 + v.Reset(ssaop.OpARM64ZSQSUBMergingS) + v.AddArg3(x, y, mask) + return true + } + // match: (ZSELS (ZSUBS x y) x mask) + // result: (ZSUBMergingS x y mask) + for { + if v_0.Op != ssaop.OpARM64ZSUBS { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + if x != v_1 { + break + } + mask := v_2 + v.Reset(ssaop.OpARM64ZSUBMergingS) + v.AddArg3(x, y, mask) + return true + } + // match: (ZSELS (ZUQADDS x y) x mask) + // result: (ZUQADDMergingS x y mask) + for { + if v_0.Op != ssaop.OpARM64ZUQADDS { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + x := v_0_0 + y := v_0_1 + if x != v_1 { + continue + } + mask := v_2 + v.Reset(ssaop.OpARM64ZUQADDMergingS) + v.AddArg3(x, y, mask) + return true + } + break + } + // match: (ZSELS (ZUQADDS x y) y mask) + // result: (ZUQADDMergingS y x mask) + for { + if v_0.Op != ssaop.OpARM64ZUQADDS { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + x := v_0_0 + y := v_0_1 + if y != v_1 { + continue + } + mask := v_2 + v.Reset(ssaop.OpARM64ZUQADDMergingS) + v.AddArg3(y, x, mask) + return true + } + break + } + // match: (ZSELS (ZUQADDS x y) z mask) + // result: (ZUQADDMergingPrefixedS z x y mask) + for { + if v_0.Op != ssaop.OpARM64ZUQADDS { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + z := v_1 + mask := v_2 + v.Reset(ssaop.OpARM64ZUQADDMergingPrefixedS) + v.AddArg4(z, x, y, mask) + return true + } + // match: (ZSELS (ZUQSUBS x y) x mask) + // result: (ZUQSUBMergingS x y mask) + for { + if v_0.Op != ssaop.OpARM64ZUQSUBS { + break + } + y := v_0.Args[1] + x := v_0.Args[0] + if x != v_1 { + break + } + mask := v_2 + v.Reset(ssaop.OpARM64ZUQSUBMergingS) + v.AddArg3(x, y, mask) + return true + } + return false +} +func rewriteValue_OpAbsFloat32s(v *ssa.Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (AbsFloat32s x) + // result: (ZFABSS x (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) + for { + x := v_0 + v.Reset(ssaop.OpARM64ZFABSS) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTS, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(8) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg2(x, v0) + return true + } +} +func rewriteValue_OpAbsFloat64s(v *ssa.Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (AbsFloat64s x) + // result: (ZFABSD x (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) + for { + x := v_0 + v.Reset(ssaop.OpARM64ZFABSD) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTD, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(4) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg2(x, v0) + return true + } +} +func rewriteValue_OpAbsInt16s(v *ssa.Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (AbsInt16s x) + // result: (ZABSH x (Select0 (PWHILELTH (MOVDconst [0]) (MOVDconst [16])))) + for { + x := v_0 + v.Reset(ssaop.OpARM64ZABSH) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTH, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(16) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg2(x, v0) + return true + } +} +func rewriteValue_OpAbsInt32s(v *ssa.Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (AbsInt32s x) + // result: (ZABSS x (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) + for { + x := v_0 + v.Reset(ssaop.OpARM64ZABSS) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTS, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(8) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg2(x, v0) + return true + } +} +func rewriteValue_OpAbsInt64s(v *ssa.Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (AbsInt64s x) + // result: (ZABSD x (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) + for { + x := v_0 + v.Reset(ssaop.OpARM64ZABSD) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTD, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(4) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg2(x, v0) + return true + } +} +func rewriteValue_OpAbsInt8s(v *ssa.Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (AbsInt8s x) + // result: (ZABSB x (Select0 (PWHILELTB (MOVDconst [0]) (MOVDconst [32])))) + for { + x := v_0 + v.Reset(ssaop.OpARM64ZABSB) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTB, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(32) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg2(x, v0) + return true + } +} +func rewriteValue_OpAddr(v *ssa.Value) bool { + v_0 := v.Args[0] + // match: (Addr {sym} base) + // result: (MOVDaddr {sym} base) + for { + sym := ssa.AuxToSym(v.Aux) + base := v_0 v.Reset(ssaop.OpARM64MOVDaddr) v.Aux = ssa.SymToAux(sym) v.AddArg(base) return true } } -func rewriteValue_OpAvg64u(v *ssa.Value) bool { +func rewriteValue_OpAvg64u(v *ssa.Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Avg64u x y) + // result: (ADD (SRLconst (SUB x y) [1]) y) + for { + t := v.Type + x := v_0 + y := v_1 + v.Reset(ssaop.OpARM64ADD) + v0 := b.NewValue0(v.Pos, ssaop.OpARM64SRLconst, t) + v0.AuxInt = ssa.Int64ToAuxInt(1) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64SUB, t) + v1.AddArg2(x, y) + v0.AddArg(v1) + v.AddArg2(v0, y) + return true + } +} +func rewriteValue_OpBitLen16(v *ssa.Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (BitLen16 x) + // result: (BitLen64 (ZeroExt16to64 x)) + for { + x := v_0 + v.Reset(ssaop.OpBitLen64) + v0 := b.NewValue0(v.Pos, ssaop.OpZeroExt16to64, typ.UInt64) + v0.AddArg(x) + v.AddArg(v0) + return true + } +} +func rewriteValue_OpBitLen32(v *ssa.Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (BitLen32 x) + // result: (SUB (MOVDconst [32]) (CLZW x)) + for { + x := v_0 + v.Reset(ssaop.OpARM64SUB) + v0 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v0.AuxInt = ssa.Int64ToAuxInt(32) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64CLZW, typ.Int) + v1.AddArg(x) + v.AddArg2(v0, v1) + return true + } +} +func rewriteValue_OpBitLen64(v *ssa.Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (BitLen64 x) + // result: (SUB (MOVDconst [64]) (CLZ x)) + for { + x := v_0 + v.Reset(ssaop.OpARM64SUB) + v0 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v0.AuxInt = ssa.Int64ToAuxInt(64) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64CLZ, typ.Int) + v1.AddArg(x) + v.AddArg2(v0, v1) + return true + } +} +func rewriteValue_OpBitLen8(v *ssa.Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (BitLen8 x) + // result: (BitLen64 (ZeroExt8to64 x)) + for { + x := v_0 + v.Reset(ssaop.OpBitLen64) + v0 := b.NewValue0(v.Pos, ssaop.OpZeroExt8to64, typ.UInt64) + v0.AddArg(x) + v.AddArg(v0) + return true + } +} +func rewriteValue_OpBitRev16(v *ssa.Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (BitRev16 x) + // result: (SRLconst [48] (RBIT x)) + for { + x := v_0 + v.Reset(ssaop.OpARM64SRLconst) + v.AuxInt = ssa.Int64ToAuxInt(48) + v0 := b.NewValue0(v.Pos, ssaop.OpARM64RBIT, typ.UInt64) + v0.AddArg(x) + v.AddArg(v0) + return true + } +} +func rewriteValue_OpBitRev8(v *ssa.Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (BitRev8 x) + // result: (SRLconst [56] (RBIT x)) + for { + x := v_0 + v.Reset(ssaop.OpARM64SRLconst) + v.AuxInt = ssa.Int64ToAuxInt(56) + v0 := b.NewValue0(v.Pos, ssaop.OpARM64RBIT, typ.UInt64) + v0.AddArg(x) + v.AddArg(v0) + return true + } +} +func rewriteValue_OpCeilFloat32s(v *ssa.Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (CeilFloat32s x) + // result: (ZFRINTPS x (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) + for { + x := v_0 + v.Reset(ssaop.OpARM64ZFRINTPS) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTS, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(8) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg2(x, v0) + return true + } +} +func rewriteValue_OpCeilFloat64s(v *ssa.Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (CeilFloat64s x) + // result: (ZFRINTPD x (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) + for { + x := v_0 + v.Reset(ssaop.OpARM64ZFRINTPD) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTD, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(4) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg2(x, v0) + return true + } +} +func rewriteValue_OpCondSelect(v *ssa.Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (CondSelect x y boolval) + // cond: ssa.FlagArg(boolval) != nil + // result: (CSEL [boolval.Op] x y ssa.FlagArg(boolval)) + for { + x := v_0 + y := v_1 + boolval := v_2 + if !(ssa.FlagArg(boolval) != nil) { + break + } + v.Reset(ssaop.OpARM64CSEL) + v.AuxInt = ssa.OpToAuxInt(boolval.Op) + v.AddArg3(x, y, ssa.FlagArg(boolval)) + return true + } + // match: (CondSelect x y boolval) + // cond: ssa.FlagArg(boolval) == nil + // result: (CSEL [ssaop.OpARM64NotEqual] x y (TSTWconst [1] boolval)) + for { + x := v_0 + y := v_1 + boolval := v_2 + if !(ssa.FlagArg(boolval) == nil) { + break + } + v.Reset(ssaop.OpARM64CSEL) + v.AuxInt = ssa.OpToAuxInt(ssaop.OpARM64NotEqual) + v0 := b.NewValue0(v.Pos, ssaop.OpARM64TSTWconst, types.TypeFlags) + v0.AuxInt = ssa.Int32ToAuxInt(1) + v0.AddArg(boolval) + v.AddArg3(x, y, v0) + return true + } + return false +} +func rewriteValue_OpConst16(v *ssa.Value) bool { + // match: (Const16 [val]) + // result: (MOVDconst [int64(val)]) + for { + val := ssa.AuxIntToInt16(v.AuxInt) + v.Reset(ssaop.OpARM64MOVDconst) + v.AuxInt = ssa.Int64ToAuxInt(int64(val)) + return true + } +} +func rewriteValue_OpConst32(v *ssa.Value) bool { + // match: (Const32 [val]) + // result: (MOVDconst [int64(val)]) + for { + val := ssa.AuxIntToInt32(v.AuxInt) + v.Reset(ssaop.OpARM64MOVDconst) + v.AuxInt = ssa.Int64ToAuxInt(int64(val)) + return true + } +} +func rewriteValue_OpConst32F(v *ssa.Value) bool { + // match: (Const32F [val]) + // result: (FMOVSconst [float64(val)]) + for { + val := ssa.AuxIntToFloat32(v.AuxInt) + v.Reset(ssaop.OpARM64FMOVSconst) + v.AuxInt = ssa.Float64ToAuxInt(float64(val)) + return true + } +} +func rewriteValue_OpConst64(v *ssa.Value) bool { + // match: (Const64 [val]) + // result: (MOVDconst [int64(val)]) + for { + val := ssa.AuxIntToInt64(v.AuxInt) + v.Reset(ssaop.OpARM64MOVDconst) + v.AuxInt = ssa.Int64ToAuxInt(int64(val)) + return true + } +} +func rewriteValue_OpConst64F(v *ssa.Value) bool { + // match: (Const64F [val]) + // result: (FMOVDconst [float64(val)]) + for { + val := ssa.AuxIntToFloat64(v.AuxInt) + v.Reset(ssaop.OpARM64FMOVDconst) + v.AuxInt = ssa.Float64ToAuxInt(float64(val)) + return true + } +} +func rewriteValue_OpConst8(v *ssa.Value) bool { + // match: (Const8 [val]) + // result: (MOVDconst [int64(val)]) + for { + val := ssa.AuxIntToInt8(v.AuxInt) + v.Reset(ssaop.OpARM64MOVDconst) + v.AuxInt = ssa.Int64ToAuxInt(int64(val)) + return true + } +} +func rewriteValue_OpConstBool(v *ssa.Value) bool { + // match: (ConstBool [t]) + // result: (MOVDconst [ssa.B2i(t)]) + for { + t := ssa.AuxIntToBool(v.AuxInt) + v.Reset(ssaop.OpARM64MOVDconst) + v.AuxInt = ssa.Int64ToAuxInt(ssa.B2i(t)) + return true + } +} +func rewriteValue_OpConstNil(v *ssa.Value) bool { + // match: (ConstNil) + // result: (MOVDconst [0]) + for { + v.Reset(ssaop.OpARM64MOVDconst) + v.AuxInt = ssa.Int64ToAuxInt(0) + return true + } +} +func rewriteValue_OpCount8s(v *ssa.Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Count8s r) + // result: (Select0 (PWHILELTB (MOVDconst [0]) r)) + for { + r := v_0 + v.Reset(ssaop.OpSelect0) + v.Type = types.TypeMask + v0 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTB, types.NewTuple(typ.Mask, types.TypeFlags)) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v1.AuxInt = ssa.Int64ToAuxInt(0) + v0.AddArg2(v1, r) + v.AddArg(v0) + return true + } +} +func rewriteValue_OpCtz16(v *ssa.Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Ctz16 x) + // result: (CLZW (RBITW (ORconst [0x10000] x))) + for { + t := v.Type + x := v_0 + v.Reset(ssaop.OpARM64CLZW) + v.Type = t + v0 := b.NewValue0(v.Pos, ssaop.OpARM64RBITW, typ.UInt32) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64ORconst, typ.UInt32) + v1.AuxInt = ssa.Int64ToAuxInt(0x10000) + v1.AddArg(x) + v0.AddArg(v1) + v.AddArg(v0) + return true + } +} +func rewriteValue_OpCtz32(v *ssa.Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (Ctz32 x) + // result: (CLZW (RBITW x)) + for { + t := v.Type + x := v_0 + v.Reset(ssaop.OpARM64CLZW) + v0 := b.NewValue0(v.Pos, ssaop.OpARM64RBITW, t) + v0.AddArg(x) + v.AddArg(v0) + return true + } +} +func rewriteValue_OpCtz64(v *ssa.Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (Ctz64 x) + // result: (CLZ (RBIT x)) + for { + t := v.Type + x := v_0 + v.Reset(ssaop.OpARM64CLZ) + v0 := b.NewValue0(v.Pos, ssaop.OpARM64RBIT, t) + v0.AddArg(x) + v.AddArg(v0) + return true + } +} +func rewriteValue_OpCtz8(v *ssa.Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Ctz8 x) + // result: (CLZW (RBITW (ORconst [0x100] x))) + for { + t := v.Type + x := v_0 + v.Reset(ssaop.OpARM64CLZW) + v.Type = t + v0 := b.NewValue0(v.Pos, ssaop.OpARM64RBITW, typ.UInt32) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64ORconst, typ.UInt32) + v1.AuxInt = ssa.Int64ToAuxInt(0x100) + v1.AddArg(x) + v0.AddArg(v1) + v.AddArg(v0) + return true + } +} +func rewriteValue_OpDiv16(v *ssa.Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Div16 [false] x y) + // result: (DIVW (SignExt16to32 x) (SignExt16to32 y)) + for { + if ssa.AuxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + y := v_1 + v.Reset(ssaop.OpARM64DIVW) + v0 := b.NewValue0(v.Pos, ssaop.OpSignExt16to32, typ.Int32) + v0.AddArg(x) + v1 := b.NewValue0(v.Pos, ssaop.OpSignExt16to32, typ.Int32) + v1.AddArg(y) + v.AddArg2(v0, v1) + return true + } + return false +} +func rewriteValue_OpDiv16u(v *ssa.Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Div16u x y) + // result: (UDIVW (ZeroExt16to32 x) (ZeroExt16to32 y)) + for { + x := v_0 + y := v_1 + v.Reset(ssaop.OpARM64UDIVW) + v0 := b.NewValue0(v.Pos, ssaop.OpZeroExt16to32, typ.UInt32) + v0.AddArg(x) + v1 := b.NewValue0(v.Pos, ssaop.OpZeroExt16to32, typ.UInt32) + v1.AddArg(y) + v.AddArg2(v0, v1) + return true + } +} +func rewriteValue_OpDiv32(v *ssa.Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (Div32 [false] x y) + // result: (DIVW x y) + for { + if ssa.AuxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + y := v_1 + v.Reset(ssaop.OpARM64DIVW) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValue_OpDiv64(v *ssa.Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (Div64 [false] x y) + // result: (DIV x y) + for { + if ssa.AuxIntToBool(v.AuxInt) != false { + break + } + x := v_0 + y := v_1 + v.Reset(ssaop.OpARM64DIV) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValue_OpDiv8(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Avg64u x y) - // result: (ADD (SRLconst (SUB x y) [1]) y) + typ := &b.Func.Config.Types + // match: (Div8 x y) + // result: (DIVW (SignExt8to32 x) (SignExt8to32 y)) for { - t := v.Type x := v_0 y := v_1 - v.Reset(ssaop.OpARM64ADD) - v0 := b.NewValue0(v.Pos, ssaop.OpARM64SRLconst, t) - v0.AuxInt = ssa.Int64ToAuxInt(1) - v1 := b.NewValue0(v.Pos, ssaop.OpARM64SUB, t) - v1.AddArg2(x, y) - v0.AddArg(v1) - v.AddArg2(v0, y) + v.Reset(ssaop.OpARM64DIVW) + v0 := b.NewValue0(v.Pos, ssaop.OpSignExt8to32, typ.Int32) + v0.AddArg(x) + v1 := b.NewValue0(v.Pos, ssaop.OpSignExt8to32, typ.Int32) + v1.AddArg(y) + v.AddArg2(v0, v1) return true } } -func rewriteValue_OpBitLen16(v *ssa.Value) bool { +func rewriteValue_OpDiv8u(v *ssa.Value) bool { + v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (BitLen16 x) - // result: (BitLen64 (ZeroExt16to64 x)) + // match: (Div8u x y) + // result: (UDIVW (ZeroExt8to32 x) (ZeroExt8to32 y)) for { x := v_0 - v.Reset(ssaop.OpBitLen64) - v0 := b.NewValue0(v.Pos, ssaop.OpZeroExt16to64, typ.UInt64) + y := v_1 + v.Reset(ssaop.OpARM64UDIVW) + v0 := b.NewValue0(v.Pos, ssaop.OpZeroExt8to32, typ.UInt32) v0.AddArg(x) - v.AddArg(v0) + v1 := b.NewValue0(v.Pos, ssaop.OpZeroExt8to32, typ.UInt32) + v1.AddArg(y) + v.AddArg2(v0, v1) return true } } -func rewriteValue_OpBitLen32(v *ssa.Value) bool { +func rewriteValue_OpEq16(v *ssa.Value) bool { + v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (BitLen32 x) - // result: (SUB (MOVDconst [32]) (CLZW x)) + // match: (Eq16 x y) + // result: (Equal (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) for { x := v_0 - v.Reset(ssaop.OpARM64SUB) - v0 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) - v0.AuxInt = ssa.Int64ToAuxInt(32) - v1 := b.NewValue0(v.Pos, ssaop.OpARM64CLZW, typ.Int) + y := v_1 + v.Reset(ssaop.OpARM64Equal) + v0 := b.NewValue0(v.Pos, ssaop.OpARM64CMPW, types.TypeFlags) + v1 := b.NewValue0(v.Pos, ssaop.OpZeroExt16to32, typ.UInt32) v1.AddArg(x) - v.AddArg2(v0, v1) + v2 := b.NewValue0(v.Pos, ssaop.OpZeroExt16to32, typ.UInt32) + v2.AddArg(y) + v0.AddArg2(v1, v2) + v.AddArg(v0) return true } } -func rewriteValue_OpBitLen64(v *ssa.Value) bool { +func rewriteValue_OpEq32(v *ssa.Value) bool { + v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - typ := &b.Func.Config.Types - // match: (BitLen64 x) - // result: (SUB (MOVDconst [64]) (CLZ x)) + // match: (Eq32 x y) + // result: (Equal (CMPW x y)) for { x := v_0 - v.Reset(ssaop.OpARM64SUB) - v0 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) - v0.AuxInt = ssa.Int64ToAuxInt(64) - v1 := b.NewValue0(v.Pos, ssaop.OpARM64CLZ, typ.Int) - v1.AddArg(x) - v.AddArg2(v0, v1) + y := v_1 + v.Reset(ssaop.OpARM64Equal) + v0 := b.NewValue0(v.Pos, ssaop.OpARM64CMPW, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) return true } } -func rewriteValue_OpBitLen8(v *ssa.Value) bool { +func rewriteValue_OpEq32F(v *ssa.Value) bool { + v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - typ := &b.Func.Config.Types - // match: (BitLen8 x) - // result: (BitLen64 (ZeroExt8to64 x)) + // match: (Eq32F x y) + // result: (Equal (FCMPS x y)) for { x := v_0 - v.Reset(ssaop.OpBitLen64) - v0 := b.NewValue0(v.Pos, ssaop.OpZeroExt8to64, typ.UInt64) - v0.AddArg(x) + y := v_1 + v.Reset(ssaop.OpARM64Equal) + v0 := b.NewValue0(v.Pos, ssaop.OpARM64FCMPS, types.TypeFlags) + v0.AddArg2(x, y) v.AddArg(v0) return true } } -func rewriteValue_OpBitRev16(v *ssa.Value) bool { +func rewriteValue_OpEq64(v *ssa.Value) bool { + v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - typ := &b.Func.Config.Types - // match: (BitRev16 x) - // result: (SRLconst [48] (RBIT x)) + // match: (Eq64 x y) + // result: (Equal (CMP x y)) for { x := v_0 - v.Reset(ssaop.OpARM64SRLconst) - v.AuxInt = ssa.Int64ToAuxInt(48) - v0 := b.NewValue0(v.Pos, ssaop.OpARM64RBIT, typ.UInt64) - v0.AddArg(x) + y := v_1 + v.Reset(ssaop.OpARM64Equal) + v0 := b.NewValue0(v.Pos, ssaop.OpARM64CMP, types.TypeFlags) + v0.AddArg2(x, y) v.AddArg(v0) return true } } -func rewriteValue_OpBitRev8(v *ssa.Value) bool { +func rewriteValue_OpEq64F(v *ssa.Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Eq64F x y) + // result: (Equal (FCMPD x y)) + for { + x := v_0 + y := v_1 + v.Reset(ssaop.OpARM64Equal) + v0 := b.NewValue0(v.Pos, ssaop.OpARM64FCMPD, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValue_OpEq8(v *ssa.Value) bool { + v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (BitRev8 x) - // result: (SRLconst [56] (RBIT x)) + // match: (Eq8 x y) + // result: (Equal (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) for { x := v_0 - v.Reset(ssaop.OpARM64SRLconst) - v.AuxInt = ssa.Int64ToAuxInt(56) - v0 := b.NewValue0(v.Pos, ssaop.OpARM64RBIT, typ.UInt64) - v0.AddArg(x) + y := v_1 + v.Reset(ssaop.OpARM64Equal) + v0 := b.NewValue0(v.Pos, ssaop.OpARM64CMPW, types.TypeFlags) + v1 := b.NewValue0(v.Pos, ssaop.OpZeroExt8to32, typ.UInt32) + v1.AddArg(x) + v2 := b.NewValue0(v.Pos, ssaop.OpZeroExt8to32, typ.UInt32) + v2.AddArg(y) + v0.AddArg2(v1, v2) v.AddArg(v0) return true } } -func rewriteValue_OpCondSelect(v *ssa.Value) bool { - v_2 := v.Args[2] +func rewriteValue_OpEqB(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (CondSelect x y boolval) - // cond: ssa.FlagArg(boolval) != nil - // result: (CSEL [boolval.Op] x y ssa.FlagArg(boolval)) + typ := &b.Func.Config.Types + // match: (EqB x y) + // result: (XOR (MOVDconst [1]) (XOR x y)) for { x := v_0 y := v_1 - boolval := v_2 - if !(ssa.FlagArg(boolval) != nil) { - break - } - v.Reset(ssaop.OpARM64CSEL) - v.AuxInt = ssa.OpToAuxInt(boolval.Op) - v.AddArg3(x, y, ssa.FlagArg(boolval)) + v.Reset(ssaop.OpARM64XOR) + v0 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v0.AuxInt = ssa.Int64ToAuxInt(1) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64XOR, typ.Bool) + v1.AddArg2(x, y) + v.AddArg2(v0, v1) return true } - // match: (CondSelect x y boolval) - // cond: ssa.FlagArg(boolval) == nil - // result: (CSEL [ssaop.OpARM64NotEqual] x y (TSTWconst [1] boolval)) +} +func rewriteValue_OpEqPtr(v *ssa.Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (EqPtr x y) + // result: (Equal (CMP x y)) for { x := v_0 y := v_1 - boolval := v_2 - if !(ssa.FlagArg(boolval) == nil) { - break - } - v.Reset(ssaop.OpARM64CSEL) - v.AuxInt = ssa.OpToAuxInt(ssaop.OpARM64NotEqual) - v0 := b.NewValue0(v.Pos, ssaop.OpARM64TSTWconst, types.TypeFlags) - v0.AuxInt = ssa.Int32ToAuxInt(1) - v0.AddArg(boolval) - v.AddArg3(x, y, v0) + v.Reset(ssaop.OpARM64Equal) + v0 := b.NewValue0(v.Pos, ssaop.OpARM64CMP, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) return true } - return false } -func rewriteValue_OpConst16(v *ssa.Value) bool { - // match: (Const16 [val]) - // result: (MOVDconst [int64(val)]) +func rewriteValue_OpEqualFloat32s(v *ssa.Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (EqualFloat32s x y) + // result: (ZFCMEQS x y (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) for { - val := ssa.AuxIntToInt16(v.AuxInt) - v.Reset(ssaop.OpARM64MOVDconst) - v.AuxInt = ssa.Int64ToAuxInt(int64(val)) + x := v_0 + y := v_1 + v.Reset(ssaop.OpARM64ZFCMEQS) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTS, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(8) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg3(x, y, v0) return true } } -func rewriteValue_OpConst32(v *ssa.Value) bool { - // match: (Const32 [val]) - // result: (MOVDconst [int64(val)]) +func rewriteValue_OpEqualFloat64s(v *ssa.Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (EqualFloat64s x y) + // result: (ZFCMEQD x y (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) for { - val := ssa.AuxIntToInt32(v.AuxInt) - v.Reset(ssaop.OpARM64MOVDconst) - v.AuxInt = ssa.Int64ToAuxInt(int64(val)) + x := v_0 + y := v_1 + v.Reset(ssaop.OpARM64ZFCMEQD) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTD, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(4) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg3(x, y, v0) return true } } -func rewriteValue_OpConst32F(v *ssa.Value) bool { - // match: (Const32F [val]) - // result: (FMOVSconst [float64(val)]) +func rewriteValue_OpEqualInt16s(v *ssa.Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (EqualInt16s x y) + // result: (ZCMPEQH x y (Select0 (PWHILELTH (MOVDconst [0]) (MOVDconst [16])))) for { - val := ssa.AuxIntToFloat32(v.AuxInt) - v.Reset(ssaop.OpARM64FMOVSconst) - v.AuxInt = ssa.Float64ToAuxInt(float64(val)) + x := v_0 + y := v_1 + v.Reset(ssaop.OpARM64ZCMPEQH) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTH, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(16) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg3(x, y, v0) return true } } -func rewriteValue_OpConst64(v *ssa.Value) bool { - // match: (Const64 [val]) - // result: (MOVDconst [int64(val)]) +func rewriteValue_OpEqualInt32s(v *ssa.Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (EqualInt32s x y) + // result: (ZCMPEQS x y (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) for { - val := ssa.AuxIntToInt64(v.AuxInt) - v.Reset(ssaop.OpARM64MOVDconst) - v.AuxInt = ssa.Int64ToAuxInt(int64(val)) + x := v_0 + y := v_1 + v.Reset(ssaop.OpARM64ZCMPEQS) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTS, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(8) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg3(x, y, v0) return true } } -func rewriteValue_OpConst64F(v *ssa.Value) bool { - // match: (Const64F [val]) - // result: (FMOVDconst [float64(val)]) +func rewriteValue_OpEqualInt64s(v *ssa.Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (EqualInt64s x y) + // result: (ZCMPEQD x y (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) for { - val := ssa.AuxIntToFloat64(v.AuxInt) - v.Reset(ssaop.OpARM64FMOVDconst) - v.AuxInt = ssa.Float64ToAuxInt(float64(val)) + x := v_0 + y := v_1 + v.Reset(ssaop.OpARM64ZCMPEQD) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTD, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(4) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg3(x, y, v0) return true } } -func rewriteValue_OpConst8(v *ssa.Value) bool { - // match: (Const8 [val]) - // result: (MOVDconst [int64(val)]) +func rewriteValue_OpEqualInt8s(v *ssa.Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (EqualInt8s x y) + // result: (ZCMPEQB x y (Select0 (PWHILELTB (MOVDconst [0]) (MOVDconst [32])))) for { - val := ssa.AuxIntToInt8(v.AuxInt) - v.Reset(ssaop.OpARM64MOVDconst) - v.AuxInt = ssa.Int64ToAuxInt(int64(val)) + x := v_0 + y := v_1 + v.Reset(ssaop.OpARM64ZCMPEQB) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTB, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(32) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg3(x, y, v0) return true } } -func rewriteValue_OpConstBool(v *ssa.Value) bool { - // match: (ConstBool [t]) - // result: (MOVDconst [ssa.B2i(t)]) +func rewriteValue_OpEqualUint16s(v *ssa.Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (EqualUint16s x y) + // result: (ZCMPEQH x y (Select0 (PWHILELTH (MOVDconst [0]) (MOVDconst [16])))) for { - t := ssa.AuxIntToBool(v.AuxInt) - v.Reset(ssaop.OpARM64MOVDconst) - v.AuxInt = ssa.Int64ToAuxInt(ssa.B2i(t)) + x := v_0 + y := v_1 + v.Reset(ssaop.OpARM64ZCMPEQH) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTH, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(16) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg3(x, y, v0) return true } } -func rewriteValue_OpConstNil(v *ssa.Value) bool { - // match: (ConstNil) - // result: (MOVDconst [0]) +func rewriteValue_OpEqualUint32s(v *ssa.Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (EqualUint32s x y) + // result: (ZCMPEQS x y (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) for { - v.Reset(ssaop.OpARM64MOVDconst) - v.AuxInt = ssa.Int64ToAuxInt(0) + x := v_0 + y := v_1 + v.Reset(ssaop.OpARM64ZCMPEQS) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTS, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(8) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg3(x, y, v0) return true } } -func rewriteValue_OpCount8s(v *ssa.Value) bool { +func rewriteValue_OpEqualUint64s(v *ssa.Value) bool { + v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Count8s r) - // result: (Select0 (PWHILELTB (MOVDconst [0]) r)) + // match: (EqualUint64s x y) + // result: (ZCMPEQD x y (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) for { - r := v_0 - v.Reset(ssaop.OpSelect0) - v.Type = types.TypeMask - v0 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTB, types.NewTuple(typ.Mask, types.TypeFlags)) - v1 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) - v1.AuxInt = ssa.Int64ToAuxInt(0) - v0.AddArg2(v1, r) - v.AddArg(v0) + x := v_0 + y := v_1 + v.Reset(ssaop.OpARM64ZCMPEQD) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTD, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(4) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg3(x, y, v0) return true } } -func rewriteValue_OpCtz16(v *ssa.Value) bool { +func rewriteValue_OpEqualUint8s(v *ssa.Value) bool { + v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Ctz16 x) - // result: (CLZW (RBITW (ORconst [0x10000] x))) + // match: (EqualUint8s x y) + // result: (ZCMPEQB x y (Select0 (PWHILELTB (MOVDconst [0]) (MOVDconst [32])))) for { - t := v.Type x := v_0 - v.Reset(ssaop.OpARM64CLZW) - v.Type = t - v0 := b.NewValue0(v.Pos, ssaop.OpARM64RBITW, typ.UInt32) - v1 := b.NewValue0(v.Pos, ssaop.OpARM64ORconst, typ.UInt32) - v1.AuxInt = ssa.Int64ToAuxInt(0x10000) - v1.AddArg(x) + y := v_1 + v.Reset(ssaop.OpARM64ZCMPEQB) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTB, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(32) + v1.AddArg2(v2, v3) v0.AddArg(v1) - v.AddArg(v0) + v.AddArg3(x, y, v0) return true } } -func rewriteValue_OpCtz32(v *ssa.Value) bool { +func rewriteValue_OpFMA(v *ssa.Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] v_0 := v.Args[0] - b := v.Block - // match: (Ctz32 x) - // result: (CLZW (RBITW x)) + // match: (FMA x y z) + // result: (FMADDD z x y) for { - t := v.Type x := v_0 - v.Reset(ssaop.OpARM64CLZW) - v0 := b.NewValue0(v.Pos, ssaop.OpARM64RBITW, t) - v0.AddArg(x) - v.AddArg(v0) + y := v_1 + z := v_2 + v.Reset(ssaop.OpARM64FMADDD) + v.AddArg3(z, x, y) return true } } -func rewriteValue_OpCtz64(v *ssa.Value) bool { +func rewriteValue_OpFloorFloat32s(v *ssa.Value) bool { v_0 := v.Args[0] b := v.Block - // match: (Ctz64 x) - // result: (CLZ (RBIT x)) + typ := &b.Func.Config.Types + // match: (FloorFloat32s x) + // result: (ZFRINTMS x (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) for { - t := v.Type x := v_0 - v.Reset(ssaop.OpARM64CLZ) - v0 := b.NewValue0(v.Pos, ssaop.OpARM64RBIT, t) - v0.AddArg(x) - v.AddArg(v0) + v.Reset(ssaop.OpARM64ZFRINTMS) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTS, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(8) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg2(x, v0) return true } } -func rewriteValue_OpCtz8(v *ssa.Value) bool { +func rewriteValue_OpFloorFloat64s(v *ssa.Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Ctz8 x) - // result: (CLZW (RBITW (ORconst [0x100] x))) + // match: (FloorFloat64s x) + // result: (ZFRINTMD x (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) for { - t := v.Type x := v_0 - v.Reset(ssaop.OpARM64CLZW) - v.Type = t - v0 := b.NewValue0(v.Pos, ssaop.OpARM64RBITW, typ.UInt32) - v1 := b.NewValue0(v.Pos, ssaop.OpARM64ORconst, typ.UInt32) - v1.AuxInt = ssa.Int64ToAuxInt(0x100) - v1.AddArg(x) + v.Reset(ssaop.OpARM64ZFRINTMD) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTD, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(4) + v1.AddArg2(v2, v3) v0.AddArg(v1) - v.AddArg(v0) + v.AddArg2(x, v0) return true } } -func rewriteValue_OpDiv16(v *ssa.Value) bool { +func rewriteValue_OpGreaterEqualFloat32s(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Div16 [false] x y) - // result: (DIVW (SignExt16to32 x) (SignExt16to32 y)) + // match: (GreaterEqualFloat32s x y) + // result: (ZFCMGES x y (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) for { - if ssa.AuxIntToBool(v.AuxInt) != false { - break - } x := v_0 y := v_1 - v.Reset(ssaop.OpARM64DIVW) - v0 := b.NewValue0(v.Pos, ssaop.OpSignExt16to32, typ.Int32) - v0.AddArg(x) - v1 := b.NewValue0(v.Pos, ssaop.OpSignExt16to32, typ.Int32) - v1.AddArg(y) - v.AddArg2(v0, v1) + v.Reset(ssaop.OpARM64ZFCMGES) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTS, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(8) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg3(x, y, v0) return true } - return false } -func rewriteValue_OpDiv16u(v *ssa.Value) bool { +func rewriteValue_OpGreaterEqualFloat64s(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Div16u x y) - // result: (UDIVW (ZeroExt16to32 x) (ZeroExt16to32 y)) + // match: (GreaterEqualFloat64s x y) + // result: (ZFCMGED x y (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) for { x := v_0 y := v_1 - v.Reset(ssaop.OpARM64UDIVW) - v0 := b.NewValue0(v.Pos, ssaop.OpZeroExt16to32, typ.UInt32) - v0.AddArg(x) - v1 := b.NewValue0(v.Pos, ssaop.OpZeroExt16to32, typ.UInt32) - v1.AddArg(y) - v.AddArg2(v0, v1) + v.Reset(ssaop.OpARM64ZFCMGED) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTD, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(4) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValue_OpGreaterEqualInt16s(v *ssa.Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterEqualInt16s x y) + // result: (ZCMPGEH x y (Select0 (PWHILELTH (MOVDconst [0]) (MOVDconst [16])))) + for { + x := v_0 + y := v_1 + v.Reset(ssaop.OpARM64ZCMPGEH) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTH, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(16) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg3(x, y, v0) return true } } -func rewriteValue_OpDiv32(v *ssa.Value) bool { +func rewriteValue_OpGreaterEqualInt32s(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - // match: (Div32 [false] x y) - // result: (DIVW x y) + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterEqualInt32s x y) + // result: (ZCMPGES x y (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) for { - if ssa.AuxIntToBool(v.AuxInt) != false { - break - } x := v_0 y := v_1 - v.Reset(ssaop.OpARM64DIVW) - v.AddArg2(x, y) + v.Reset(ssaop.OpARM64ZCMPGES) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTS, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(8) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg3(x, y, v0) return true } - return false } -func rewriteValue_OpDiv64(v *ssa.Value) bool { +func rewriteValue_OpGreaterEqualInt64s(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - // match: (Div64 [false] x y) - // result: (DIV x y) + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterEqualInt64s x y) + // result: (ZCMPGED x y (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) for { - if ssa.AuxIntToBool(v.AuxInt) != false { - break - } x := v_0 y := v_1 - v.Reset(ssaop.OpARM64DIV) - v.AddArg2(x, y) + v.Reset(ssaop.OpARM64ZCMPGED) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTD, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(4) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg3(x, y, v0) return true } - return false } -func rewriteValue_OpDiv8(v *ssa.Value) bool { +func rewriteValue_OpGreaterEqualInt8s(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Div8 x y) - // result: (DIVW (SignExt8to32 x) (SignExt8to32 y)) + // match: (GreaterEqualInt8s x y) + // result: (ZCMPGEB x y (Select0 (PWHILELTB (MOVDconst [0]) (MOVDconst [32])))) for { x := v_0 y := v_1 - v.Reset(ssaop.OpARM64DIVW) - v0 := b.NewValue0(v.Pos, ssaop.OpSignExt8to32, typ.Int32) - v0.AddArg(x) - v1 := b.NewValue0(v.Pos, ssaop.OpSignExt8to32, typ.Int32) - v1.AddArg(y) - v.AddArg2(v0, v1) + v.Reset(ssaop.OpARM64ZCMPGEB) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTB, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(32) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg3(x, y, v0) return true } } -func rewriteValue_OpDiv8u(v *ssa.Value) bool { +func rewriteValue_OpGreaterEqualUint16s(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Div8u x y) - // result: (UDIVW (ZeroExt8to32 x) (ZeroExt8to32 y)) + // match: (GreaterEqualUint16s x y) + // result: (ZCMPHSH x y (Select0 (PWHILELTH (MOVDconst [0]) (MOVDconst [16])))) for { x := v_0 y := v_1 - v.Reset(ssaop.OpARM64UDIVW) - v0 := b.NewValue0(v.Pos, ssaop.OpZeroExt8to32, typ.UInt32) - v0.AddArg(x) - v1 := b.NewValue0(v.Pos, ssaop.OpZeroExt8to32, typ.UInt32) - v1.AddArg(y) - v.AddArg2(v0, v1) + v.Reset(ssaop.OpARM64ZCMPHSH) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTH, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(16) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg3(x, y, v0) return true } } -func rewriteValue_OpEq16(v *ssa.Value) bool { +func rewriteValue_OpGreaterEqualUint32s(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Eq16 x y) - // result: (Equal (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) + // match: (GreaterEqualUint32s x y) + // result: (ZCMPHSS x y (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) for { x := v_0 y := v_1 - v.Reset(ssaop.OpARM64Equal) - v0 := b.NewValue0(v.Pos, ssaop.OpARM64CMPW, types.TypeFlags) - v1 := b.NewValue0(v.Pos, ssaop.OpZeroExt16to32, typ.UInt32) - v1.AddArg(x) - v2 := b.NewValue0(v.Pos, ssaop.OpZeroExt16to32, typ.UInt32) - v2.AddArg(y) - v0.AddArg2(v1, v2) - v.AddArg(v0) + v.Reset(ssaop.OpARM64ZCMPHSS) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTS, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(8) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg3(x, y, v0) return true } } -func rewriteValue_OpEq32(v *ssa.Value) bool { +func rewriteValue_OpGreaterEqualUint64s(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Eq32 x y) - // result: (Equal (CMPW x y)) + typ := &b.Func.Config.Types + // match: (GreaterEqualUint64s x y) + // result: (ZCMPHSD x y (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) for { x := v_0 y := v_1 - v.Reset(ssaop.OpARM64Equal) - v0 := b.NewValue0(v.Pos, ssaop.OpARM64CMPW, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) + v.Reset(ssaop.OpARM64ZCMPHSD) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTD, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(4) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg3(x, y, v0) return true } } -func rewriteValue_OpEq32F(v *ssa.Value) bool { +func rewriteValue_OpGreaterEqualUint8s(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Eq32F x y) - // result: (Equal (FCMPS x y)) + typ := &b.Func.Config.Types + // match: (GreaterEqualUint8s x y) + // result: (ZCMPHSB x y (Select0 (PWHILELTB (MOVDconst [0]) (MOVDconst [32])))) for { x := v_0 y := v_1 - v.Reset(ssaop.OpARM64Equal) - v0 := b.NewValue0(v.Pos, ssaop.OpARM64FCMPS, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) + v.Reset(ssaop.OpARM64ZCMPHSB) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTB, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(32) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg3(x, y, v0) return true } } -func rewriteValue_OpEq64(v *ssa.Value) bool { +func rewriteValue_OpGreaterFloat32s(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Eq64 x y) - // result: (Equal (CMP x y)) + typ := &b.Func.Config.Types + // match: (GreaterFloat32s x y) + // result: (ZFCMGTS x y (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) for { x := v_0 y := v_1 - v.Reset(ssaop.OpARM64Equal) - v0 := b.NewValue0(v.Pos, ssaop.OpARM64CMP, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) + v.Reset(ssaop.OpARM64ZFCMGTS) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTS, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(8) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg3(x, y, v0) return true } } -func rewriteValue_OpEq64F(v *ssa.Value) bool { +func rewriteValue_OpGreaterFloat64s(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Eq64F x y) - // result: (Equal (FCMPD x y)) + typ := &b.Func.Config.Types + // match: (GreaterFloat64s x y) + // result: (ZFCMGTD x y (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) for { x := v_0 y := v_1 - v.Reset(ssaop.OpARM64Equal) - v0 := b.NewValue0(v.Pos, ssaop.OpARM64FCMPD, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) + v.Reset(ssaop.OpARM64ZFCMGTD) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTD, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(4) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg3(x, y, v0) return true } } -func rewriteValue_OpEq8(v *ssa.Value) bool { +func rewriteValue_OpGreaterInt16s(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Eq8 x y) - // result: (Equal (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) + // match: (GreaterInt16s x y) + // result: (ZCMPGTH x y (Select0 (PWHILELTH (MOVDconst [0]) (MOVDconst [16])))) for { x := v_0 y := v_1 - v.Reset(ssaop.OpARM64Equal) - v0 := b.NewValue0(v.Pos, ssaop.OpARM64CMPW, types.TypeFlags) - v1 := b.NewValue0(v.Pos, ssaop.OpZeroExt8to32, typ.UInt32) - v1.AddArg(x) - v2 := b.NewValue0(v.Pos, ssaop.OpZeroExt8to32, typ.UInt32) - v2.AddArg(y) - v0.AddArg2(v1, v2) - v.AddArg(v0) + v.Reset(ssaop.OpARM64ZCMPGTH) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTH, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(16) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg3(x, y, v0) return true } } -func rewriteValue_OpEqB(v *ssa.Value) bool { +func rewriteValue_OpGreaterInt32s(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (EqB x y) - // result: (XOR (MOVDconst [1]) (XOR x y)) + // match: (GreaterInt32s x y) + // result: (ZCMPGTS x y (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) for { x := v_0 y := v_1 - v.Reset(ssaop.OpARM64XOR) - v0 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) - v0.AuxInt = ssa.Int64ToAuxInt(1) - v1 := b.NewValue0(v.Pos, ssaop.OpARM64XOR, typ.Bool) - v1.AddArg2(x, y) - v.AddArg2(v0, v1) + v.Reset(ssaop.OpARM64ZCMPGTS) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTS, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(8) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg3(x, y, v0) return true } } -func rewriteValue_OpEqPtr(v *ssa.Value) bool { +func rewriteValue_OpGreaterInt64s(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (EqPtr x y) - // result: (Equal (CMP x y)) + typ := &b.Func.Config.Types + // match: (GreaterInt64s x y) + // result: (ZCMPGTD x y (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) for { x := v_0 y := v_1 - v.Reset(ssaop.OpARM64Equal) - v0 := b.NewValue0(v.Pos, ssaop.OpARM64CMP, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) + v.Reset(ssaop.OpARM64ZCMPGTD) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTD, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(4) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg3(x, y, v0) return true } } -func rewriteValue_OpFMA(v *ssa.Value) bool { - v_2 := v.Args[2] +func rewriteValue_OpGreaterInt8s(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - // match: (FMA x y z) - // result: (FMADDD z x y) + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterInt8s x y) + // result: (ZCMPGTB x y (Select0 (PWHILELTB (MOVDconst [0]) (MOVDconst [32])))) for { x := v_0 y := v_1 - z := v_2 - v.Reset(ssaop.OpARM64FMADDD) - v.AddArg3(z, x, y) + v.Reset(ssaop.OpARM64ZCMPGTB) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTB, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(32) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg3(x, y, v0) return true } } -func rewriteValue_OpGreaterInt16s(v *ssa.Value) bool { +func rewriteValue_OpGreaterUint16s(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (GreaterInt16s x y) - // result: (ZCMPGTH x y (Select0 (PWHILELTH (MOVDconst [0]) (MOVDconst [16])))) + // match: (GreaterUint16s x y) + // result: (ZCMPHIH x y (Select0 (PWHILELTH (MOVDconst [0]) (MOVDconst [16])))) for { x := v_0 y := v_1 - v.Reset(ssaop.OpARM64ZCMPGTH) + v.Reset(ssaop.OpARM64ZCMPHIH) v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTH, types.NewTuple(typ.Mask, types.TypeFlags)) v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) @@ -21305,17 +23709,17 @@ func rewriteValue_OpGreaterInt16s(v *ssa.Value) bool { return true } } -func rewriteValue_OpGreaterInt32s(v *ssa.Value) bool { +func rewriteValue_OpGreaterUint32s(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (GreaterInt32s x y) - // result: (ZCMPGTS x y (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) + // match: (GreaterUint32s x y) + // result: (ZCMPHIS x y (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) for { x := v_0 y := v_1 - v.Reset(ssaop.OpARM64ZCMPGTS) + v.Reset(ssaop.OpARM64ZCMPHIS) v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTS, types.NewTuple(typ.Mask, types.TypeFlags)) v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) @@ -21328,17 +23732,17 @@ func rewriteValue_OpGreaterInt32s(v *ssa.Value) bool { return true } } -func rewriteValue_OpGreaterInt64s(v *ssa.Value) bool { +func rewriteValue_OpGreaterUint64s(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (GreaterInt64s x y) - // result: (ZCMPGTD x y (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) + // match: (GreaterUint64s x y) + // result: (ZCMPHID x y (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) for { x := v_0 y := v_1 - v.Reset(ssaop.OpARM64ZCMPGTD) + v.Reset(ssaop.OpARM64ZCMPHID) v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTD, types.NewTuple(typ.Mask, types.TypeFlags)) v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) @@ -21351,17 +23755,17 @@ func rewriteValue_OpGreaterInt64s(v *ssa.Value) bool { return true } } -func rewriteValue_OpGreaterInt8s(v *ssa.Value) bool { +func rewriteValue_OpGreaterUint8s(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (GreaterInt8s x y) - // result: (ZCMPGTB x y (Select0 (PWHILELTB (MOVDconst [0]) (MOVDconst [32])))) + // match: (GreaterUint8s x y) + // result: (ZCMPHIB x y (Select0 (PWHILELTB (MOVDconst [0]) (MOVDconst [32])))) for { x := v_0 y := v_1 - v.Reset(ssaop.OpARM64ZCMPGTB) + v.Reset(ssaop.OpARM64ZCMPHIB) v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTB, types.NewTuple(typ.Mask, types.TypeFlags)) v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) @@ -23198,325 +25602,681 @@ func rewriteValue_OpMove(v *ssa.Value) bool { v.AddArg3(dst, v0, v1) return true } - // match: (Move [s] dst src mem) - // cond: s > 48 && s <= 64 - // result: (FSTPQ [int32(s-32)] dst (Select0 (FLDPQ [int32(s-32)] src mem)) (Select1 (FLDPQ [int32(s-32)] src mem)) (FSTPQ dst (Select0 (FLDPQ src mem)) (Select1 (FLDPQ src mem)) mem)) + // match: (Move [s] dst src mem) + // cond: s > 48 && s <= 64 + // result: (FSTPQ [int32(s-32)] dst (Select0 (FLDPQ [int32(s-32)] src mem)) (Select1 (FLDPQ [int32(s-32)] src mem)) (FSTPQ dst (Select0 (FLDPQ src mem)) (Select1 (FLDPQ src mem)) mem)) + for { + s := ssa.AuxIntToInt64(v.AuxInt) + dst := v_0 + src := v_1 + mem := v_2 + if !(s > 48 && s <= 64) { + break + } + v.Reset(ssaop.OpARM64FSTPQ) + v.AuxInt = ssa.Int32ToAuxInt(int32(s - 32)) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, typ.Vec128) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64FLDPQ, types.NewTuple(typ.Vec128, typ.Vec128)) + v1.AuxInt = ssa.Int32ToAuxInt(int32(s - 32)) + v1.AddArg2(src, mem) + v0.AddArg(v1) + v2 := b.NewValue0(v.Pos, ssaop.OpSelect1, typ.Vec128) + v2.AddArg(v1) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64FSTPQ, types.TypeMem) + v4 := b.NewValue0(v.Pos, ssaop.OpSelect0, typ.Vec128) + v5 := b.NewValue0(v.Pos, ssaop.OpARM64FLDPQ, types.NewTuple(typ.Vec128, typ.Vec128)) + v5.AddArg2(src, mem) + v4.AddArg(v5) + v6 := b.NewValue0(v.Pos, ssaop.OpSelect1, typ.Vec128) + v6.AddArg(v5) + v3.AddArg4(dst, v4, v6, mem) + v.AddArg4(dst, v0, v2, v3) + return true + } + // match: (Move [s] dst src mem) + // cond: s > 64 && s < 192 && ssa.LogLargeCopyValue(v, s) + // result: (LoweredMove [s] dst src mem) + for { + s := ssa.AuxIntToInt64(v.AuxInt) + dst := v_0 + src := v_1 + mem := v_2 + if !(s > 64 && s < 192 && ssa.LogLargeCopyValue(v, s)) { + break + } + v.Reset(ssaop.OpARM64LoweredMove) + v.AuxInt = ssa.Int64ToAuxInt(s) + v.AddArg3(dst, src, mem) + return true + } + // match: (Move [s] dst src mem) + // cond: s >= 192 && ssa.LogLargeCopyValue(v, s) + // result: (LoweredMoveLoop [s] dst src mem) + for { + s := ssa.AuxIntToInt64(v.AuxInt) + dst := v_0 + src := v_1 + mem := v_2 + if !(s >= 192 && ssa.LogLargeCopyValue(v, s)) { + break + } + v.Reset(ssaop.OpARM64LoweredMoveLoop) + v.AuxInt = ssa.Int64ToAuxInt(s) + v.AddArg3(dst, src, mem) + return true + } + return false +} +func rewriteValue_OpMulAddFloat32x4(v *ssa.Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (MulAddFloat32x4 x y z) + // result: (VFMLA4S z x y) + for { + x := v_0 + y := v_1 + z := v_2 + v.Reset(ssaop.OpARM64VFMLA4S) + v.AddArg3(z, x, y) + return true + } +} +func rewriteValue_OpMulAddFloat64x2(v *ssa.Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (MulAddFloat64x2 x y z) + // result: (VFMLA2D z x y) + for { + x := v_0 + y := v_1 + z := v_2 + v.Reset(ssaop.OpARM64VFMLA2D) + v.AddArg3(z, x, y) + return true + } +} +func rewriteValue_OpMulAddInt16x8(v *ssa.Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (MulAddInt16x8 x y z) + // result: (VMLA8H z x y) + for { + x := v_0 + y := v_1 + z := v_2 + v.Reset(ssaop.OpARM64VMLA8H) + v.AddArg3(z, x, y) + return true + } +} +func rewriteValue_OpMulAddInt32x4(v *ssa.Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (MulAddInt32x4 x y z) + // result: (VMLA4S z x y) + for { + x := v_0 + y := v_1 + z := v_2 + v.Reset(ssaop.OpARM64VMLA4S) + v.AddArg3(z, x, y) + return true + } +} +func rewriteValue_OpMulAddInt8x16(v *ssa.Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (MulAddInt8x16 x y z) + // result: (VMLA16B z x y) + for { + x := v_0 + y := v_1 + z := v_2 + v.Reset(ssaop.OpARM64VMLA16B) + v.AddArg3(z, x, y) + return true + } +} +func rewriteValue_OpMulAddUint16x8(v *ssa.Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (MulAddUint16x8 x y z) + // result: (VMLA8H z x y) + for { + x := v_0 + y := v_1 + z := v_2 + v.Reset(ssaop.OpARM64VMLA8H) + v.AddArg3(z, x, y) + return true + } +} +func rewriteValue_OpMulAddUint32x4(v *ssa.Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (MulAddUint32x4 x y z) + // result: (VMLA4S z x y) + for { + x := v_0 + y := v_1 + z := v_2 + v.Reset(ssaop.OpARM64VMLA4S) + v.AddArg3(z, x, y) + return true + } +} +func rewriteValue_OpMulAddUint8x16(v *ssa.Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (MulAddUint8x16 x y z) + // result: (VMLA16B z x y) + for { + x := v_0 + y := v_1 + z := v_2 + v.Reset(ssaop.OpARM64VMLA16B) + v.AddArg3(z, x, y) + return true + } +} +func rewriteValue_OpNegFloat32s(v *ssa.Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NegFloat32s x) + // result: (ZFNEGS x (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) + for { + x := v_0 + v.Reset(ssaop.OpARM64ZFNEGS) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTS, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(8) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg2(x, v0) + return true + } +} +func rewriteValue_OpNegFloat64s(v *ssa.Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NegFloat64s x) + // result: (ZFNEGD x (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) + for { + x := v_0 + v.Reset(ssaop.OpARM64ZFNEGD) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTD, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(4) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg2(x, v0) + return true + } +} +func rewriteValue_OpNegInt16s(v *ssa.Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NegInt16s x) + // result: (ZNEGH x (Select0 (PWHILELTH (MOVDconst [0]) (MOVDconst [16])))) + for { + x := v_0 + v.Reset(ssaop.OpARM64ZNEGH) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTH, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(16) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg2(x, v0) + return true + } +} +func rewriteValue_OpNegInt32s(v *ssa.Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NegInt32s x) + // result: (ZNEGS x (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) for { - s := ssa.AuxIntToInt64(v.AuxInt) - dst := v_0 - src := v_1 - mem := v_2 - if !(s > 48 && s <= 64) { - break - } - v.Reset(ssaop.OpARM64FSTPQ) - v.AuxInt = ssa.Int32ToAuxInt(int32(s - 32)) - v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, typ.Vec128) - v1 := b.NewValue0(v.Pos, ssaop.OpARM64FLDPQ, types.NewTuple(typ.Vec128, typ.Vec128)) - v1.AuxInt = ssa.Int32ToAuxInt(int32(s - 32)) - v1.AddArg2(src, mem) + x := v_0 + v.Reset(ssaop.OpARM64ZNEGS) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTS, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(8) + v1.AddArg2(v2, v3) v0.AddArg(v1) - v2 := b.NewValue0(v.Pos, ssaop.OpSelect1, typ.Vec128) - v2.AddArg(v1) - v3 := b.NewValue0(v.Pos, ssaop.OpARM64FSTPQ, types.TypeMem) - v4 := b.NewValue0(v.Pos, ssaop.OpSelect0, typ.Vec128) - v5 := b.NewValue0(v.Pos, ssaop.OpARM64FLDPQ, types.NewTuple(typ.Vec128, typ.Vec128)) - v5.AddArg2(src, mem) - v4.AddArg(v5) - v6 := b.NewValue0(v.Pos, ssaop.OpSelect1, typ.Vec128) - v6.AddArg(v5) - v3.AddArg4(dst, v4, v6, mem) - v.AddArg4(dst, v0, v2, v3) + v.AddArg2(x, v0) return true } - // match: (Move [s] dst src mem) - // cond: s > 64 && s < 192 && ssa.LogLargeCopyValue(v, s) - // result: (LoweredMove [s] dst src mem) +} +func rewriteValue_OpNegInt64s(v *ssa.Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NegInt64s x) + // result: (ZNEGD x (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) for { - s := ssa.AuxIntToInt64(v.AuxInt) - dst := v_0 - src := v_1 - mem := v_2 - if !(s > 64 && s < 192 && ssa.LogLargeCopyValue(v, s)) { - break - } - v.Reset(ssaop.OpARM64LoweredMove) - v.AuxInt = ssa.Int64ToAuxInt(s) - v.AddArg3(dst, src, mem) + x := v_0 + v.Reset(ssaop.OpARM64ZNEGD) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTD, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(4) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg2(x, v0) return true } - // match: (Move [s] dst src mem) - // cond: s >= 192 && ssa.LogLargeCopyValue(v, s) - // result: (LoweredMoveLoop [s] dst src mem) +} +func rewriteValue_OpNegInt8s(v *ssa.Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NegInt8s x) + // result: (ZNEGB x (Select0 (PWHILELTB (MOVDconst [0]) (MOVDconst [32])))) for { - s := ssa.AuxIntToInt64(v.AuxInt) - dst := v_0 - src := v_1 - mem := v_2 - if !(s >= 192 && ssa.LogLargeCopyValue(v, s)) { - break - } - v.Reset(ssaop.OpARM64LoweredMoveLoop) - v.AuxInt = ssa.Int64ToAuxInt(s) - v.AddArg3(dst, src, mem) + x := v_0 + v.Reset(ssaop.OpARM64ZNEGB) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTB, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(32) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg2(x, v0) return true } - return false } -func rewriteValue_OpMulAddFloat32x4(v *ssa.Value) bool { - v_2 := v.Args[2] +func rewriteValue_OpNeq16(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - // match: (MulAddFloat32x4 x y z) - // result: (VFMLA4S z x y) + b := v.Block + typ := &b.Func.Config.Types + // match: (Neq16 x y) + // result: (NotEqual (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) for { x := v_0 y := v_1 - z := v_2 - v.Reset(ssaop.OpARM64VFMLA4S) - v.AddArg3(z, x, y) + v.Reset(ssaop.OpARM64NotEqual) + v0 := b.NewValue0(v.Pos, ssaop.OpARM64CMPW, types.TypeFlags) + v1 := b.NewValue0(v.Pos, ssaop.OpZeroExt16to32, typ.UInt32) + v1.AddArg(x) + v2 := b.NewValue0(v.Pos, ssaop.OpZeroExt16to32, typ.UInt32) + v2.AddArg(y) + v0.AddArg2(v1, v2) + v.AddArg(v0) return true } } -func rewriteValue_OpMulAddFloat64x2(v *ssa.Value) bool { - v_2 := v.Args[2] +func rewriteValue_OpNeq32(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - // match: (MulAddFloat64x2 x y z) - // result: (VFMLA2D z x y) + b := v.Block + // match: (Neq32 x y) + // result: (NotEqual (CMPW x y)) for { x := v_0 y := v_1 - z := v_2 - v.Reset(ssaop.OpARM64VFMLA2D) - v.AddArg3(z, x, y) + v.Reset(ssaop.OpARM64NotEqual) + v0 := b.NewValue0(v.Pos, ssaop.OpARM64CMPW, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) return true } } -func rewriteValue_OpMulAddInt16x8(v *ssa.Value) bool { - v_2 := v.Args[2] +func rewriteValue_OpNeq32F(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - // match: (MulAddInt16x8 x y z) - // result: (VMLA8H z x y) + b := v.Block + // match: (Neq32F x y) + // result: (NotEqual (FCMPS x y)) for { x := v_0 y := v_1 - z := v_2 - v.Reset(ssaop.OpARM64VMLA8H) - v.AddArg3(z, x, y) + v.Reset(ssaop.OpARM64NotEqual) + v0 := b.NewValue0(v.Pos, ssaop.OpARM64FCMPS, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) return true } } -func rewriteValue_OpMulAddInt32x4(v *ssa.Value) bool { - v_2 := v.Args[2] +func rewriteValue_OpNeq64(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - // match: (MulAddInt32x4 x y z) - // result: (VMLA4S z x y) + b := v.Block + // match: (Neq64 x y) + // result: (NotEqual (CMP x y)) for { x := v_0 y := v_1 - z := v_2 - v.Reset(ssaop.OpARM64VMLA4S) - v.AddArg3(z, x, y) + v.Reset(ssaop.OpARM64NotEqual) + v0 := b.NewValue0(v.Pos, ssaop.OpARM64CMP, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) return true } } -func rewriteValue_OpMulAddInt8x16(v *ssa.Value) bool { - v_2 := v.Args[2] +func rewriteValue_OpNeq64F(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - // match: (MulAddInt8x16 x y z) - // result: (VMLA16B z x y) + b := v.Block + // match: (Neq64F x y) + // result: (NotEqual (FCMPD x y)) for { x := v_0 y := v_1 - z := v_2 - v.Reset(ssaop.OpARM64VMLA16B) - v.AddArg3(z, x, y) + v.Reset(ssaop.OpARM64NotEqual) + v0 := b.NewValue0(v.Pos, ssaop.OpARM64FCMPD, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) return true } } -func rewriteValue_OpMulAddUint16x8(v *ssa.Value) bool { - v_2 := v.Args[2] +func rewriteValue_OpNeq8(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - // match: (MulAddUint16x8 x y z) - // result: (VMLA8H z x y) + b := v.Block + typ := &b.Func.Config.Types + // match: (Neq8 x y) + // result: (NotEqual (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) for { x := v_0 y := v_1 - z := v_2 - v.Reset(ssaop.OpARM64VMLA8H) - v.AddArg3(z, x, y) + v.Reset(ssaop.OpARM64NotEqual) + v0 := b.NewValue0(v.Pos, ssaop.OpARM64CMPW, types.TypeFlags) + v1 := b.NewValue0(v.Pos, ssaop.OpZeroExt8to32, typ.UInt32) + v1.AddArg(x) + v2 := b.NewValue0(v.Pos, ssaop.OpZeroExt8to32, typ.UInt32) + v2.AddArg(y) + v0.AddArg2(v1, v2) + v.AddArg(v0) return true } } -func rewriteValue_OpMulAddUint32x4(v *ssa.Value) bool { - v_2 := v.Args[2] +func rewriteValue_OpNeqPtr(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - // match: (MulAddUint32x4 x y z) - // result: (VMLA4S z x y) + b := v.Block + // match: (NeqPtr x y) + // result: (NotEqual (CMP x y)) for { x := v_0 y := v_1 - z := v_2 - v.Reset(ssaop.OpARM64VMLA4S) - v.AddArg3(z, x, y) + v.Reset(ssaop.OpARM64NotEqual) + v0 := b.NewValue0(v.Pos, ssaop.OpARM64CMP, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) return true } } -func rewriteValue_OpMulAddUint8x16(v *ssa.Value) bool { - v_2 := v.Args[2] +func rewriteValue_OpNot(v *ssa.Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (Not x) + // result: (XOR (MOVDconst [1]) x) + for { + x := v_0 + v.Reset(ssaop.OpARM64XOR) + v0 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v0.AuxInt = ssa.Int64ToAuxInt(1) + v.AddArg2(v0, x) + return true + } +} +func rewriteValue_OpNotEqualFloat32s(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - // match: (MulAddUint8x16 x y z) - // result: (VMLA16B z x y) + b := v.Block + typ := &b.Func.Config.Types + // match: (NotEqualFloat32s x y) + // result: (ZFCMNES x y (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) for { x := v_0 y := v_1 - z := v_2 - v.Reset(ssaop.OpARM64VMLA16B) - v.AddArg3(z, x, y) + v.Reset(ssaop.OpARM64ZFCMNES) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTS, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(8) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValue_OpNotEqualFloat64s(v *ssa.Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NotEqualFloat64s x y) + // result: (ZFCMNED x y (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) + for { + x := v_0 + y := v_1 + v.Reset(ssaop.OpARM64ZFCMNED) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTD, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(4) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg3(x, y, v0) return true } } -func rewriteValue_OpNeq16(v *ssa.Value) bool { +func rewriteValue_OpNotEqualInt16s(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Neq16 x y) - // result: (NotEqual (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) + // match: (NotEqualInt16s x y) + // result: (ZCMPNEH x y (Select0 (PWHILELTH (MOVDconst [0]) (MOVDconst [16])))) for { x := v_0 y := v_1 - v.Reset(ssaop.OpARM64NotEqual) - v0 := b.NewValue0(v.Pos, ssaop.OpARM64CMPW, types.TypeFlags) - v1 := b.NewValue0(v.Pos, ssaop.OpZeroExt16to32, typ.UInt32) - v1.AddArg(x) - v2 := b.NewValue0(v.Pos, ssaop.OpZeroExt16to32, typ.UInt32) - v2.AddArg(y) - v0.AddArg2(v1, v2) - v.AddArg(v0) + v.Reset(ssaop.OpARM64ZCMPNEH) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTH, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(16) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg3(x, y, v0) return true } } -func rewriteValue_OpNeq32(v *ssa.Value) bool { +func rewriteValue_OpNotEqualInt32s(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Neq32 x y) - // result: (NotEqual (CMPW x y)) + typ := &b.Func.Config.Types + // match: (NotEqualInt32s x y) + // result: (ZCMPNES x y (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) for { x := v_0 y := v_1 - v.Reset(ssaop.OpARM64NotEqual) - v0 := b.NewValue0(v.Pos, ssaop.OpARM64CMPW, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) + v.Reset(ssaop.OpARM64ZCMPNES) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTS, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(8) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg3(x, y, v0) return true } } -func rewriteValue_OpNeq32F(v *ssa.Value) bool { +func rewriteValue_OpNotEqualInt64s(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Neq32F x y) - // result: (NotEqual (FCMPS x y)) + typ := &b.Func.Config.Types + // match: (NotEqualInt64s x y) + // result: (ZCMPNED x y (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) for { x := v_0 y := v_1 - v.Reset(ssaop.OpARM64NotEqual) - v0 := b.NewValue0(v.Pos, ssaop.OpARM64FCMPS, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) + v.Reset(ssaop.OpARM64ZCMPNED) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTD, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(4) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg3(x, y, v0) return true } } -func rewriteValue_OpNeq64(v *ssa.Value) bool { +func rewriteValue_OpNotEqualInt8s(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Neq64 x y) - // result: (NotEqual (CMP x y)) + typ := &b.Func.Config.Types + // match: (NotEqualInt8s x y) + // result: (ZCMPNEB x y (Select0 (PWHILELTB (MOVDconst [0]) (MOVDconst [32])))) for { x := v_0 y := v_1 - v.Reset(ssaop.OpARM64NotEqual) - v0 := b.NewValue0(v.Pos, ssaop.OpARM64CMP, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) + v.Reset(ssaop.OpARM64ZCMPNEB) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTB, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(32) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg3(x, y, v0) return true } } -func rewriteValue_OpNeq64F(v *ssa.Value) bool { +func rewriteValue_OpNotEqualUint16s(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Neq64F x y) - // result: (NotEqual (FCMPD x y)) + typ := &b.Func.Config.Types + // match: (NotEqualUint16s x y) + // result: (ZCMPNEH x y (Select0 (PWHILELTH (MOVDconst [0]) (MOVDconst [16])))) for { x := v_0 y := v_1 - v.Reset(ssaop.OpARM64NotEqual) - v0 := b.NewValue0(v.Pos, ssaop.OpARM64FCMPD, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) + v.Reset(ssaop.OpARM64ZCMPNEH) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTH, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(16) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg3(x, y, v0) return true } } -func rewriteValue_OpNeq8(v *ssa.Value) bool { +func rewriteValue_OpNotEqualUint32s(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Neq8 x y) - // result: (NotEqual (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) + // match: (NotEqualUint32s x y) + // result: (ZCMPNES x y (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) for { x := v_0 y := v_1 - v.Reset(ssaop.OpARM64NotEqual) - v0 := b.NewValue0(v.Pos, ssaop.OpARM64CMPW, types.TypeFlags) - v1 := b.NewValue0(v.Pos, ssaop.OpZeroExt8to32, typ.UInt32) - v1.AddArg(x) - v2 := b.NewValue0(v.Pos, ssaop.OpZeroExt8to32, typ.UInt32) - v2.AddArg(y) - v0.AddArg2(v1, v2) - v.AddArg(v0) + v.Reset(ssaop.OpARM64ZCMPNES) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTS, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(8) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg3(x, y, v0) return true } } -func rewriteValue_OpNeqPtr(v *ssa.Value) bool { +func rewriteValue_OpNotEqualUint64s(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (NeqPtr x y) - // result: (NotEqual (CMP x y)) + typ := &b.Func.Config.Types + // match: (NotEqualUint64s x y) + // result: (ZCMPNED x y (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) for { x := v_0 y := v_1 - v.Reset(ssaop.OpARM64NotEqual) - v0 := b.NewValue0(v.Pos, ssaop.OpARM64CMP, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) + v.Reset(ssaop.OpARM64ZCMPNED) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTD, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(4) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg3(x, y, v0) return true } } -func rewriteValue_OpNot(v *ssa.Value) bool { +func rewriteValue_OpNotEqualUint8s(v *ssa.Value) bool { + v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types - // match: (Not x) - // result: (XOR (MOVDconst [1]) x) + // match: (NotEqualUint8s x y) + // result: (ZCMPNEB x y (Select0 (PWHILELTB (MOVDconst [0]) (MOVDconst [32])))) for { x := v_0 - v.Reset(ssaop.OpARM64XOR) - v0 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) - v0.AuxInt = ssa.Int64ToAuxInt(1) - v.AddArg2(v0, x) + y := v_1 + v.Reset(ssaop.OpARM64ZCMPNEB) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTB, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(32) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg3(x, y, v0) return true } } @@ -23783,6 +26543,48 @@ func rewriteValue_OpRotateLeft8(v *ssa.Value) bool { return true } } +func rewriteValue_OpRoundFloat32s(v *ssa.Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (RoundFloat32s x) + // result: (ZFRINTNS x (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) + for { + x := v_0 + v.Reset(ssaop.OpARM64ZFRINTNS) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTS, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(8) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg2(x, v0) + return true + } +} +func rewriteValue_OpRoundFloat64s(v *ssa.Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (RoundFloat64s x) + // result: (ZFRINTND x (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) + for { + x := v_0 + v.Reset(ssaop.OpARM64ZFRINTND) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTD, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(4) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg2(x, v0) + return true + } +} func rewriteValue_OpRsh16Ux16(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -25355,6 +28157,48 @@ func rewriteValue_OpSlicemask(v *ssa.Value) bool { return true } } +func rewriteValue_OpSqrtFloat32s(v *ssa.Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (SqrtFloat32s x) + // result: (ZFSQRTS x (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) + for { + x := v_0 + v.Reset(ssaop.OpARM64ZFSQRTS) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTS, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(8) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg2(x, v0) + return true + } +} +func rewriteValue_OpSqrtFloat64s(v *ssa.Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (SqrtFloat64s x) + // result: (ZFSQRTD x (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) + for { + x := v_0 + v.Reset(ssaop.OpARM64ZFSQRTD) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTD, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(4) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg2(x, v0) + return true + } +} func rewriteValue_OpStore(v *ssa.Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] @@ -25519,6 +28363,48 @@ func rewriteValue_OpStoreMasked8(v *ssa.Value) bool { } return false } +func rewriteValue_OpTruncFloat32s(v *ssa.Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (TruncFloat32s x) + // result: (ZFRINTZS x (Select0 (PWHILELTS (MOVDconst [0]) (MOVDconst [8])))) + for { + x := v_0 + v.Reset(ssaop.OpARM64ZFRINTZS) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTS, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(8) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg2(x, v0) + return true + } +} +func rewriteValue_OpTruncFloat64s(v *ssa.Value) bool { + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (TruncFloat64s x) + // result: (ZFRINTZD x (Select0 (PWHILELTD (MOVDconst [0]) (MOVDconst [4])))) + for { + x := v_0 + v.Reset(ssaop.OpARM64ZFRINTZD) + v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, types.TypeMask) + v1 := b.NewValue0(v.Pos, ssaop.OpARM64PWHILELTD, types.NewTuple(typ.Mask, types.TypeFlags)) + v2 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v2.AuxInt = ssa.Int64ToAuxInt(0) + v3 := b.NewValue0(v.Pos, ssaop.OpARM64MOVDconst, typ.UInt64) + v3.AuxInt = ssa.Int64ToAuxInt(4) + v1.AddArg2(v2, v3) + v0.AddArg(v1) + v.AddArg2(x, v0) + return true + } +} func rewriteValue_OpZero(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] diff --git a/src/cmd/compile/internal/ssarewrite/rewritemips64/rewriteMIPS64.go b/src/cmd/compile/internal/ssarewrite/rewritemips64/rewriteMIPS64.go index a231322badb2bd..59159a4d751558 100644 --- a/src/cmd/compile/internal/ssarewrite/rewritemips64/rewriteMIPS64.go +++ b/src/cmd/compile/internal/ssarewrite/rewritemips64/rewriteMIPS64.go @@ -2067,12 +2067,29 @@ func rewriteValue_OpLsh16x16(v *ssa.Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Lsh16x16 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SLLV x y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SLLV) + v.AddArg2(x, y) + return true + } // match: (Lsh16x16 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt16to64 y))) (SLLV x (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64AND) v0 := b.NewValue0(v.Pos, ssaop.OpMIPS64NEGV, t) v1 := b.NewValue0(v.Pos, ssaop.OpMIPS64SGTU, typ.Bool) @@ -2087,18 +2104,36 @@ func rewriteValue_OpLsh16x16(v *ssa.Value) bool { v.AddArg2(v0, v4) return true } + return false } func rewriteValue_OpLsh16x32(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Lsh16x32 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SLLV x y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SLLV) + v.AddArg2(x, y) + return true + } // match: (Lsh16x32 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt32to64 y))) (SLLV x (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64AND) v0 := b.NewValue0(v.Pos, ssaop.OpMIPS64NEGV, t) v1 := b.NewValue0(v.Pos, ssaop.OpMIPS64SGTU, typ.Bool) @@ -2113,18 +2148,36 @@ func rewriteValue_OpLsh16x32(v *ssa.Value) bool { v.AddArg2(v0, v4) return true } + return false } func rewriteValue_OpLsh16x64(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Lsh16x64 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SLLV x y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SLLV) + v.AddArg2(x, y) + return true + } // match: (Lsh16x64 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (AND (NEGV (SGTU (MOVVconst [64]) y)) (SLLV x y)) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64AND) v0 := b.NewValue0(v.Pos, ssaop.OpMIPS64NEGV, t) v1 := b.NewValue0(v.Pos, ssaop.OpMIPS64SGTU, typ.Bool) @@ -2137,18 +2190,36 @@ func rewriteValue_OpLsh16x64(v *ssa.Value) bool { v.AddArg2(v0, v3) return true } + return false } func rewriteValue_OpLsh16x8(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Lsh16x8 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SLLV x y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SLLV) + v.AddArg2(x, y) + return true + } // match: (Lsh16x8 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt8to64 y))) (SLLV x (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64AND) v0 := b.NewValue0(v.Pos, ssaop.OpMIPS64NEGV, t) v1 := b.NewValue0(v.Pos, ssaop.OpMIPS64SGTU, typ.Bool) @@ -2163,18 +2234,36 @@ func rewriteValue_OpLsh16x8(v *ssa.Value) bool { v.AddArg2(v0, v4) return true } + return false } func rewriteValue_OpLsh32x16(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Lsh32x16 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SLLV x y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SLLV) + v.AddArg2(x, y) + return true + } // match: (Lsh32x16 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt16to64 y))) (SLLV x (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64AND) v0 := b.NewValue0(v.Pos, ssaop.OpMIPS64NEGV, t) v1 := b.NewValue0(v.Pos, ssaop.OpMIPS64SGTU, typ.Bool) @@ -2189,18 +2278,36 @@ func rewriteValue_OpLsh32x16(v *ssa.Value) bool { v.AddArg2(v0, v4) return true } + return false } func rewriteValue_OpLsh32x32(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Lsh32x32 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SLLV x y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SLLV) + v.AddArg2(x, y) + return true + } // match: (Lsh32x32 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt32to64 y))) (SLLV x (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64AND) v0 := b.NewValue0(v.Pos, ssaop.OpMIPS64NEGV, t) v1 := b.NewValue0(v.Pos, ssaop.OpMIPS64SGTU, typ.Bool) @@ -2215,18 +2322,36 @@ func rewriteValue_OpLsh32x32(v *ssa.Value) bool { v.AddArg2(v0, v4) return true } + return false } func rewriteValue_OpLsh32x64(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Lsh32x64 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SLLV x y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SLLV) + v.AddArg2(x, y) + return true + } // match: (Lsh32x64 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (AND (NEGV (SGTU (MOVVconst [64]) y)) (SLLV x y)) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64AND) v0 := b.NewValue0(v.Pos, ssaop.OpMIPS64NEGV, t) v1 := b.NewValue0(v.Pos, ssaop.OpMIPS64SGTU, typ.Bool) @@ -2239,18 +2364,36 @@ func rewriteValue_OpLsh32x64(v *ssa.Value) bool { v.AddArg2(v0, v3) return true } + return false } func rewriteValue_OpLsh32x8(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Lsh32x8 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SLLV x y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SLLV) + v.AddArg2(x, y) + return true + } // match: (Lsh32x8 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt8to64 y))) (SLLV x (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64AND) v0 := b.NewValue0(v.Pos, ssaop.OpMIPS64NEGV, t) v1 := b.NewValue0(v.Pos, ssaop.OpMIPS64SGTU, typ.Bool) @@ -2265,18 +2408,36 @@ func rewriteValue_OpLsh32x8(v *ssa.Value) bool { v.AddArg2(v0, v4) return true } + return false } func rewriteValue_OpLsh64x16(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Lsh64x16 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SLLV x y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SLLV) + v.AddArg2(x, y) + return true + } // match: (Lsh64x16 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt16to64 y))) (SLLV x (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64AND) v0 := b.NewValue0(v.Pos, ssaop.OpMIPS64NEGV, t) v1 := b.NewValue0(v.Pos, ssaop.OpMIPS64SGTU, typ.Bool) @@ -2291,18 +2452,36 @@ func rewriteValue_OpLsh64x16(v *ssa.Value) bool { v.AddArg2(v0, v4) return true } + return false } func rewriteValue_OpLsh64x32(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Lsh64x32 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SLLV x y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SLLV) + v.AddArg2(x, y) + return true + } // match: (Lsh64x32 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt32to64 y))) (SLLV x (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64AND) v0 := b.NewValue0(v.Pos, ssaop.OpMIPS64NEGV, t) v1 := b.NewValue0(v.Pos, ssaop.OpMIPS64SGTU, typ.Bool) @@ -2317,18 +2496,36 @@ func rewriteValue_OpLsh64x32(v *ssa.Value) bool { v.AddArg2(v0, v4) return true } + return false } func rewriteValue_OpLsh64x64(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Lsh64x64 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SLLV x y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SLLV) + v.AddArg2(x, y) + return true + } // match: (Lsh64x64 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (AND (NEGV (SGTU (MOVVconst [64]) y)) (SLLV x y)) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64AND) v0 := b.NewValue0(v.Pos, ssaop.OpMIPS64NEGV, t) v1 := b.NewValue0(v.Pos, ssaop.OpMIPS64SGTU, typ.Bool) @@ -2341,18 +2538,36 @@ func rewriteValue_OpLsh64x64(v *ssa.Value) bool { v.AddArg2(v0, v3) return true } + return false } func rewriteValue_OpLsh64x8(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Lsh64x8 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SLLV x y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SLLV) + v.AddArg2(x, y) + return true + } // match: (Lsh64x8 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt8to64 y))) (SLLV x (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64AND) v0 := b.NewValue0(v.Pos, ssaop.OpMIPS64NEGV, t) v1 := b.NewValue0(v.Pos, ssaop.OpMIPS64SGTU, typ.Bool) @@ -2367,18 +2582,36 @@ func rewriteValue_OpLsh64x8(v *ssa.Value) bool { v.AddArg2(v0, v4) return true } + return false } func rewriteValue_OpLsh8x16(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Lsh8x16 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SLLV x y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SLLV) + v.AddArg2(x, y) + return true + } // match: (Lsh8x16 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt16to64 y))) (SLLV x (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64AND) v0 := b.NewValue0(v.Pos, ssaop.OpMIPS64NEGV, t) v1 := b.NewValue0(v.Pos, ssaop.OpMIPS64SGTU, typ.Bool) @@ -2393,18 +2626,36 @@ func rewriteValue_OpLsh8x16(v *ssa.Value) bool { v.AddArg2(v0, v4) return true } + return false } func rewriteValue_OpLsh8x32(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Lsh8x32 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SLLV x y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SLLV) + v.AddArg2(x, y) + return true + } // match: (Lsh8x32 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt32to64 y))) (SLLV x (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64AND) v0 := b.NewValue0(v.Pos, ssaop.OpMIPS64NEGV, t) v1 := b.NewValue0(v.Pos, ssaop.OpMIPS64SGTU, typ.Bool) @@ -2419,18 +2670,36 @@ func rewriteValue_OpLsh8x32(v *ssa.Value) bool { v.AddArg2(v0, v4) return true } + return false } func rewriteValue_OpLsh8x64(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Lsh8x64 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SLLV x y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SLLV) + v.AddArg2(x, y) + return true + } // match: (Lsh8x64 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (AND (NEGV (SGTU (MOVVconst [64]) y)) (SLLV x y)) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64AND) v0 := b.NewValue0(v.Pos, ssaop.OpMIPS64NEGV, t) v1 := b.NewValue0(v.Pos, ssaop.OpMIPS64SGTU, typ.Bool) @@ -2443,18 +2712,36 @@ func rewriteValue_OpLsh8x64(v *ssa.Value) bool { v.AddArg2(v0, v3) return true } + return false } func rewriteValue_OpLsh8x8(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Lsh8x8 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SLLV x y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SLLV) + v.AddArg2(x, y) + return true + } // match: (Lsh8x8 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt8to64 y))) (SLLV x (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64AND) v0 := b.NewValue0(v.Pos, ssaop.OpMIPS64NEGV, t) v1 := b.NewValue0(v.Pos, ssaop.OpMIPS64SGTU, typ.Bool) @@ -2469,6 +2756,7 @@ func rewriteValue_OpLsh8x8(v *ssa.Value) bool { v.AddArg2(v0, v4) return true } + return false } func rewriteValue_OpMIPS64ADDV(v *ssa.Value) bool { v_1 := v.Args[1] @@ -6424,12 +6712,31 @@ func rewriteValue_OpRsh16Ux16(v *ssa.Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Rsh16Ux16 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SRLV (ZeroExt16to64 x) y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SRLV) + v0 := b.NewValue0(v.Pos, ssaop.OpZeroExt16to64, typ.UInt64) + v0.AddArg(x) + v.AddArg2(v0, y) + return true + } // match: (Rsh16Ux16 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt16to64 y))) (SRLV (ZeroExt16to64 x) (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64AND) v0 := b.NewValue0(v.Pos, ssaop.OpMIPS64NEGV, t) v1 := b.NewValue0(v.Pos, ssaop.OpMIPS64SGTU, typ.Bool) @@ -6446,18 +6753,38 @@ func rewriteValue_OpRsh16Ux16(v *ssa.Value) bool { v.AddArg2(v0, v4) return true } + return false } func rewriteValue_OpRsh16Ux32(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Rsh16Ux32 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SRLV (ZeroExt16to64 x) y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SRLV) + v0 := b.NewValue0(v.Pos, ssaop.OpZeroExt16to64, typ.UInt64) + v0.AddArg(x) + v.AddArg2(v0, y) + return true + } // match: (Rsh16Ux32 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt32to64 y))) (SRLV (ZeroExt16to64 x) (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64AND) v0 := b.NewValue0(v.Pos, ssaop.OpMIPS64NEGV, t) v1 := b.NewValue0(v.Pos, ssaop.OpMIPS64SGTU, typ.Bool) @@ -6474,18 +6801,38 @@ func rewriteValue_OpRsh16Ux32(v *ssa.Value) bool { v.AddArg2(v0, v4) return true } + return false } func rewriteValue_OpRsh16Ux64(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Rsh16Ux64 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SRLV (ZeroExt16to64 x) y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SRLV) + v0 := b.NewValue0(v.Pos, ssaop.OpZeroExt16to64, typ.UInt64) + v0.AddArg(x) + v.AddArg2(v0, y) + return true + } // match: (Rsh16Ux64 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (AND (NEGV (SGTU (MOVVconst [64]) y)) (SRLV (ZeroExt16to64 x) y)) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64AND) v0 := b.NewValue0(v.Pos, ssaop.OpMIPS64NEGV, t) v1 := b.NewValue0(v.Pos, ssaop.OpMIPS64SGTU, typ.Bool) @@ -6500,18 +6847,38 @@ func rewriteValue_OpRsh16Ux64(v *ssa.Value) bool { v.AddArg2(v0, v3) return true } + return false } func rewriteValue_OpRsh16Ux8(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Rsh16Ux8 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SRLV (ZeroExt16to64 x) y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SRLV) + v0 := b.NewValue0(v.Pos, ssaop.OpZeroExt16to64, typ.UInt64) + v0.AddArg(x) + v.AddArg2(v0, y) + return true + } // match: (Rsh16Ux8 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt8to64 y))) (SRLV (ZeroExt16to64 x) (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64AND) v0 := b.NewValue0(v.Pos, ssaop.OpMIPS64NEGV, t) v1 := b.NewValue0(v.Pos, ssaop.OpMIPS64SGTU, typ.Bool) @@ -6528,18 +6895,38 @@ func rewriteValue_OpRsh16Ux8(v *ssa.Value) bool { v.AddArg2(v0, v4) return true } + return false } func rewriteValue_OpRsh16x16(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Rsh16x16 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SRAV (SignExt16to64 x) y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SRAV) + v0 := b.NewValue0(v.Pos, ssaop.OpSignExt16to64, typ.Int64) + v0.AddArg(x) + v.AddArg2(v0, y) + return true + } // match: (Rsh16x16 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (SRAV (SignExt16to64 x) (OR (NEGV (SGTU (ZeroExt16to64 y) (MOVVconst [63]))) (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64SRAV) v0 := b.NewValue0(v.Pos, ssaop.OpSignExt16to64, typ.Int64) v0.AddArg(x) @@ -6556,18 +6943,38 @@ func rewriteValue_OpRsh16x16(v *ssa.Value) bool { v.AddArg2(v0, v1) return true } + return false } func rewriteValue_OpRsh16x32(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Rsh16x32 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SRAV (SignExt16to64 x) y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SRAV) + v0 := b.NewValue0(v.Pos, ssaop.OpSignExt16to64, typ.Int64) + v0.AddArg(x) + v.AddArg2(v0, y) + return true + } // match: (Rsh16x32 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (SRAV (SignExt16to64 x) (OR (NEGV (SGTU (ZeroExt32to64 y) (MOVVconst [63]))) (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64SRAV) v0 := b.NewValue0(v.Pos, ssaop.OpSignExt16to64, typ.Int64) v0.AddArg(x) @@ -6584,18 +6991,38 @@ func rewriteValue_OpRsh16x32(v *ssa.Value) bool { v.AddArg2(v0, v1) return true } + return false } func rewriteValue_OpRsh16x64(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Rsh16x64 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SRAV (SignExt16to64 x) y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SRAV) + v0 := b.NewValue0(v.Pos, ssaop.OpSignExt16to64, typ.Int64) + v0.AddArg(x) + v.AddArg2(v0, y) + return true + } // match: (Rsh16x64 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (SRAV (SignExt16to64 x) (OR (NEGV (SGTU y (MOVVconst [63]))) y)) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64SRAV) v0 := b.NewValue0(v.Pos, ssaop.OpSignExt16to64, typ.Int64) v0.AddArg(x) @@ -6610,18 +7037,38 @@ func rewriteValue_OpRsh16x64(v *ssa.Value) bool { v.AddArg2(v0, v1) return true } + return false } func rewriteValue_OpRsh16x8(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Rsh16x8 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SRAV (SignExt16to64 x) y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SRAV) + v0 := b.NewValue0(v.Pos, ssaop.OpSignExt16to64, typ.Int64) + v0.AddArg(x) + v.AddArg2(v0, y) + return true + } // match: (Rsh16x8 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (SRAV (SignExt16to64 x) (OR (NEGV (SGTU (ZeroExt8to64 y) (MOVVconst [63]))) (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64SRAV) v0 := b.NewValue0(v.Pos, ssaop.OpSignExt16to64, typ.Int64) v0.AddArg(x) @@ -6638,18 +7085,38 @@ func rewriteValue_OpRsh16x8(v *ssa.Value) bool { v.AddArg2(v0, v1) return true } + return false } func rewriteValue_OpRsh32Ux16(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Rsh32Ux16 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SRLV (ZeroExt32to64 x) y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SRLV) + v0 := b.NewValue0(v.Pos, ssaop.OpZeroExt32to64, typ.UInt64) + v0.AddArg(x) + v.AddArg2(v0, y) + return true + } // match: (Rsh32Ux16 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt16to64 y))) (SRLV (ZeroExt32to64 x) (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64AND) v0 := b.NewValue0(v.Pos, ssaop.OpMIPS64NEGV, t) v1 := b.NewValue0(v.Pos, ssaop.OpMIPS64SGTU, typ.Bool) @@ -6666,18 +7133,38 @@ func rewriteValue_OpRsh32Ux16(v *ssa.Value) bool { v.AddArg2(v0, v4) return true } + return false } func rewriteValue_OpRsh32Ux32(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Rsh32Ux32 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SRLV (ZeroExt32to64 x) y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SRLV) + v0 := b.NewValue0(v.Pos, ssaop.OpZeroExt32to64, typ.UInt64) + v0.AddArg(x) + v.AddArg2(v0, y) + return true + } // match: (Rsh32Ux32 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt32to64 y))) (SRLV (ZeroExt32to64 x) (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64AND) v0 := b.NewValue0(v.Pos, ssaop.OpMIPS64NEGV, t) v1 := b.NewValue0(v.Pos, ssaop.OpMIPS64SGTU, typ.Bool) @@ -6694,18 +7181,38 @@ func rewriteValue_OpRsh32Ux32(v *ssa.Value) bool { v.AddArg2(v0, v4) return true } + return false } func rewriteValue_OpRsh32Ux64(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Rsh32Ux64 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SRLV (ZeroExt32to64 x) y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SRLV) + v0 := b.NewValue0(v.Pos, ssaop.OpZeroExt32to64, typ.UInt64) + v0.AddArg(x) + v.AddArg2(v0, y) + return true + } // match: (Rsh32Ux64 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (AND (NEGV (SGTU (MOVVconst [64]) y)) (SRLV (ZeroExt32to64 x) y)) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64AND) v0 := b.NewValue0(v.Pos, ssaop.OpMIPS64NEGV, t) v1 := b.NewValue0(v.Pos, ssaop.OpMIPS64SGTU, typ.Bool) @@ -6720,18 +7227,38 @@ func rewriteValue_OpRsh32Ux64(v *ssa.Value) bool { v.AddArg2(v0, v3) return true } + return false } func rewriteValue_OpRsh32Ux8(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Rsh32Ux8 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SRLV (ZeroExt32to64 x) y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SRLV) + v0 := b.NewValue0(v.Pos, ssaop.OpZeroExt32to64, typ.UInt64) + v0.AddArg(x) + v.AddArg2(v0, y) + return true + } // match: (Rsh32Ux8 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt8to64 y))) (SRLV (ZeroExt32to64 x) (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64AND) v0 := b.NewValue0(v.Pos, ssaop.OpMIPS64NEGV, t) v1 := b.NewValue0(v.Pos, ssaop.OpMIPS64SGTU, typ.Bool) @@ -6748,18 +7275,38 @@ func rewriteValue_OpRsh32Ux8(v *ssa.Value) bool { v.AddArg2(v0, v4) return true } + return false } func rewriteValue_OpRsh32x16(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Rsh32x16 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SRAV (SignExt32to64 x) y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SRAV) + v0 := b.NewValue0(v.Pos, ssaop.OpSignExt32to64, typ.Int64) + v0.AddArg(x) + v.AddArg2(v0, y) + return true + } // match: (Rsh32x16 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (SRAV (SignExt32to64 x) (OR (NEGV (SGTU (ZeroExt16to64 y) (MOVVconst [63]))) (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64SRAV) v0 := b.NewValue0(v.Pos, ssaop.OpSignExt32to64, typ.Int64) v0.AddArg(x) @@ -6776,18 +7323,38 @@ func rewriteValue_OpRsh32x16(v *ssa.Value) bool { v.AddArg2(v0, v1) return true } + return false } func rewriteValue_OpRsh32x32(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Rsh32x32 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SRAV (SignExt32to64 x) y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SRAV) + v0 := b.NewValue0(v.Pos, ssaop.OpSignExt32to64, typ.Int64) + v0.AddArg(x) + v.AddArg2(v0, y) + return true + } // match: (Rsh32x32 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (SRAV (SignExt32to64 x) (OR (NEGV (SGTU (ZeroExt32to64 y) (MOVVconst [63]))) (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64SRAV) v0 := b.NewValue0(v.Pos, ssaop.OpSignExt32to64, typ.Int64) v0.AddArg(x) @@ -6804,18 +7371,38 @@ func rewriteValue_OpRsh32x32(v *ssa.Value) bool { v.AddArg2(v0, v1) return true } + return false } func rewriteValue_OpRsh32x64(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Rsh32x64 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SRAV (SignExt32to64 x) y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SRAV) + v0 := b.NewValue0(v.Pos, ssaop.OpSignExt32to64, typ.Int64) + v0.AddArg(x) + v.AddArg2(v0, y) + return true + } // match: (Rsh32x64 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (SRAV (SignExt32to64 x) (OR (NEGV (SGTU y (MOVVconst [63]))) y)) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64SRAV) v0 := b.NewValue0(v.Pos, ssaop.OpSignExt32to64, typ.Int64) v0.AddArg(x) @@ -6830,18 +7417,38 @@ func rewriteValue_OpRsh32x64(v *ssa.Value) bool { v.AddArg2(v0, v1) return true } + return false } func rewriteValue_OpRsh32x8(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Rsh32x8 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SRAV (SignExt32to64 x) y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SRAV) + v0 := b.NewValue0(v.Pos, ssaop.OpSignExt32to64, typ.Int64) + v0.AddArg(x) + v.AddArg2(v0, y) + return true + } // match: (Rsh32x8 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (SRAV (SignExt32to64 x) (OR (NEGV (SGTU (ZeroExt8to64 y) (MOVVconst [63]))) (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64SRAV) v0 := b.NewValue0(v.Pos, ssaop.OpSignExt32to64, typ.Int64) v0.AddArg(x) @@ -6858,18 +7465,36 @@ func rewriteValue_OpRsh32x8(v *ssa.Value) bool { v.AddArg2(v0, v1) return true } + return false } func rewriteValue_OpRsh64Ux16(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Rsh64Ux16 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SRLV x y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SRLV) + v.AddArg2(x, y) + return true + } // match: (Rsh64Ux16 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt16to64 y))) (SRLV x (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64AND) v0 := b.NewValue0(v.Pos, ssaop.OpMIPS64NEGV, t) v1 := b.NewValue0(v.Pos, ssaop.OpMIPS64SGTU, typ.Bool) @@ -6884,18 +7509,36 @@ func rewriteValue_OpRsh64Ux16(v *ssa.Value) bool { v.AddArg2(v0, v4) return true } + return false } func rewriteValue_OpRsh64Ux32(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Rsh64Ux32 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SRLV x y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SRLV) + v.AddArg2(x, y) + return true + } // match: (Rsh64Ux32 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt32to64 y))) (SRLV x (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64AND) v0 := b.NewValue0(v.Pos, ssaop.OpMIPS64NEGV, t) v1 := b.NewValue0(v.Pos, ssaop.OpMIPS64SGTU, typ.Bool) @@ -6910,18 +7553,36 @@ func rewriteValue_OpRsh64Ux32(v *ssa.Value) bool { v.AddArg2(v0, v4) return true } + return false } func rewriteValue_OpRsh64Ux64(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Rsh64Ux64 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SRLV x y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SRLV) + v.AddArg2(x, y) + return true + } // match: (Rsh64Ux64 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (AND (NEGV (SGTU (MOVVconst [64]) y)) (SRLV x y)) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64AND) v0 := b.NewValue0(v.Pos, ssaop.OpMIPS64NEGV, t) v1 := b.NewValue0(v.Pos, ssaop.OpMIPS64SGTU, typ.Bool) @@ -6934,18 +7595,36 @@ func rewriteValue_OpRsh64Ux64(v *ssa.Value) bool { v.AddArg2(v0, v3) return true } + return false } func rewriteValue_OpRsh64Ux8(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Rsh64Ux8 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SRLV x y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SRLV) + v.AddArg2(x, y) + return true + } // match: (Rsh64Ux8 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt8to64 y))) (SRLV x (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64AND) v0 := b.NewValue0(v.Pos, ssaop.OpMIPS64NEGV, t) v1 := b.NewValue0(v.Pos, ssaop.OpMIPS64SGTU, typ.Bool) @@ -6960,18 +7639,36 @@ func rewriteValue_OpRsh64Ux8(v *ssa.Value) bool { v.AddArg2(v0, v4) return true } + return false } func rewriteValue_OpRsh64x16(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Rsh64x16 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SRAV x y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SRAV) + v.AddArg2(x, y) + return true + } // match: (Rsh64x16 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (SRAV x (OR (NEGV (SGTU (ZeroExt16to64 y) (MOVVconst [63]))) (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64SRAV) v0 := b.NewValue0(v.Pos, ssaop.OpMIPS64OR, t) v1 := b.NewValue0(v.Pos, ssaop.OpMIPS64NEGV, t) @@ -6986,18 +7683,36 @@ func rewriteValue_OpRsh64x16(v *ssa.Value) bool { v.AddArg2(x, v0) return true } + return false } func rewriteValue_OpRsh64x32(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Rsh64x32 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SRAV x y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SRAV) + v.AddArg2(x, y) + return true + } // match: (Rsh64x32 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (SRAV x (OR (NEGV (SGTU (ZeroExt32to64 y) (MOVVconst [63]))) (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64SRAV) v0 := b.NewValue0(v.Pos, ssaop.OpMIPS64OR, t) v1 := b.NewValue0(v.Pos, ssaop.OpMIPS64NEGV, t) @@ -7012,18 +7727,36 @@ func rewriteValue_OpRsh64x32(v *ssa.Value) bool { v.AddArg2(x, v0) return true } + return false } func rewriteValue_OpRsh64x64(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Rsh64x64 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SRAV x y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SRAV) + v.AddArg2(x, y) + return true + } // match: (Rsh64x64 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (SRAV x (OR (NEGV (SGTU y (MOVVconst [63]))) y)) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64SRAV) v0 := b.NewValue0(v.Pos, ssaop.OpMIPS64OR, t) v1 := b.NewValue0(v.Pos, ssaop.OpMIPS64NEGV, t) @@ -7036,18 +7769,36 @@ func rewriteValue_OpRsh64x64(v *ssa.Value) bool { v.AddArg2(x, v0) return true } + return false } func rewriteValue_OpRsh64x8(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Rsh64x8 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SRAV x y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SRAV) + v.AddArg2(x, y) + return true + } // match: (Rsh64x8 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (SRAV x (OR (NEGV (SGTU (ZeroExt8to64 y) (MOVVconst [63]))) (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64SRAV) v0 := b.NewValue0(v.Pos, ssaop.OpMIPS64OR, t) v1 := b.NewValue0(v.Pos, ssaop.OpMIPS64NEGV, t) @@ -7062,18 +7813,38 @@ func rewriteValue_OpRsh64x8(v *ssa.Value) bool { v.AddArg2(x, v0) return true } + return false } func rewriteValue_OpRsh8Ux16(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Rsh8Ux16 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SRLV (ZeroExt8to64 x) y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SRLV) + v0 := b.NewValue0(v.Pos, ssaop.OpZeroExt8to64, typ.UInt64) + v0.AddArg(x) + v.AddArg2(v0, y) + return true + } // match: (Rsh8Ux16 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt16to64 y))) (SRLV (ZeroExt8to64 x) (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64AND) v0 := b.NewValue0(v.Pos, ssaop.OpMIPS64NEGV, t) v1 := b.NewValue0(v.Pos, ssaop.OpMIPS64SGTU, typ.Bool) @@ -7090,18 +7861,38 @@ func rewriteValue_OpRsh8Ux16(v *ssa.Value) bool { v.AddArg2(v0, v4) return true } + return false } func rewriteValue_OpRsh8Ux32(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Rsh8Ux32 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SRLV (ZeroExt8to64 x) y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SRLV) + v0 := b.NewValue0(v.Pos, ssaop.OpZeroExt8to64, typ.UInt64) + v0.AddArg(x) + v.AddArg2(v0, y) + return true + } // match: (Rsh8Ux32 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt32to64 y))) (SRLV (ZeroExt8to64 x) (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64AND) v0 := b.NewValue0(v.Pos, ssaop.OpMIPS64NEGV, t) v1 := b.NewValue0(v.Pos, ssaop.OpMIPS64SGTU, typ.Bool) @@ -7118,18 +7909,38 @@ func rewriteValue_OpRsh8Ux32(v *ssa.Value) bool { v.AddArg2(v0, v4) return true } + return false } func rewriteValue_OpRsh8Ux64(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Rsh8Ux64 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SRLV (ZeroExt8to64 x) y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SRLV) + v0 := b.NewValue0(v.Pos, ssaop.OpZeroExt8to64, typ.UInt64) + v0.AddArg(x) + v.AddArg2(v0, y) + return true + } // match: (Rsh8Ux64 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (AND (NEGV (SGTU (MOVVconst [64]) y)) (SRLV (ZeroExt8to64 x) y)) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64AND) v0 := b.NewValue0(v.Pos, ssaop.OpMIPS64NEGV, t) v1 := b.NewValue0(v.Pos, ssaop.OpMIPS64SGTU, typ.Bool) @@ -7144,18 +7955,38 @@ func rewriteValue_OpRsh8Ux64(v *ssa.Value) bool { v.AddArg2(v0, v3) return true } + return false } func rewriteValue_OpRsh8Ux8(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Rsh8Ux8 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SRLV (ZeroExt8to64 x) y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SRLV) + v0 := b.NewValue0(v.Pos, ssaop.OpZeroExt8to64, typ.UInt64) + v0.AddArg(x) + v.AddArg2(v0, y) + return true + } // match: (Rsh8Ux8 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (AND (NEGV (SGTU (MOVVconst [64]) (ZeroExt8to64 y))) (SRLV (ZeroExt8to64 x) (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64AND) v0 := b.NewValue0(v.Pos, ssaop.OpMIPS64NEGV, t) v1 := b.NewValue0(v.Pos, ssaop.OpMIPS64SGTU, typ.Bool) @@ -7172,18 +8003,38 @@ func rewriteValue_OpRsh8Ux8(v *ssa.Value) bool { v.AddArg2(v0, v4) return true } + return false } func rewriteValue_OpRsh8x16(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Rsh8x16 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SRAV (SignExt8to64 x) y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SRAV) + v0 := b.NewValue0(v.Pos, ssaop.OpSignExt8to64, typ.Int64) + v0.AddArg(x) + v.AddArg2(v0, y) + return true + } // match: (Rsh8x16 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (SRAV (SignExt8to64 x) (OR (NEGV (SGTU (ZeroExt16to64 y) (MOVVconst [63]))) (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64SRAV) v0 := b.NewValue0(v.Pos, ssaop.OpSignExt8to64, typ.Int64) v0.AddArg(x) @@ -7200,18 +8051,38 @@ func rewriteValue_OpRsh8x16(v *ssa.Value) bool { v.AddArg2(v0, v1) return true } + return false } func rewriteValue_OpRsh8x32(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Rsh8x32 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SRAV (SignExt8to64 x) y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SRAV) + v0 := b.NewValue0(v.Pos, ssaop.OpSignExt8to64, typ.Int64) + v0.AddArg(x) + v.AddArg2(v0, y) + return true + } // match: (Rsh8x32 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (SRAV (SignExt8to64 x) (OR (NEGV (SGTU (ZeroExt32to64 y) (MOVVconst [63]))) (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64SRAV) v0 := b.NewValue0(v.Pos, ssaop.OpSignExt8to64, typ.Int64) v0.AddArg(x) @@ -7228,18 +8099,38 @@ func rewriteValue_OpRsh8x32(v *ssa.Value) bool { v.AddArg2(v0, v1) return true } + return false } func rewriteValue_OpRsh8x64(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Rsh8x64 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SRAV (SignExt8to64 x) y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SRAV) + v0 := b.NewValue0(v.Pos, ssaop.OpSignExt8to64, typ.Int64) + v0.AddArg(x) + v.AddArg2(v0, y) + return true + } // match: (Rsh8x64 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (SRAV (SignExt8to64 x) (OR (NEGV (SGTU y (MOVVconst [63]))) y)) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64SRAV) v0 := b.NewValue0(v.Pos, ssaop.OpSignExt8to64, typ.Int64) v0.AddArg(x) @@ -7254,18 +8145,38 @@ func rewriteValue_OpRsh8x64(v *ssa.Value) bool { v.AddArg2(v0, v1) return true } + return false } func rewriteValue_OpRsh8x8(v *ssa.Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types + // match: (Rsh8x8 x y) + // cond: ssa.ShiftIsBounded(v) + // result: (SRAV (SignExt8to64 x) y) + for { + x := v_0 + y := v_1 + if !(ssa.ShiftIsBounded(v)) { + break + } + v.Reset(ssaop.OpMIPS64SRAV) + v0 := b.NewValue0(v.Pos, ssaop.OpSignExt8to64, typ.Int64) + v0.AddArg(x) + v.AddArg2(v0, y) + return true + } // match: (Rsh8x8 x y) + // cond: !ssa.ShiftIsBounded(v) // result: (SRAV (SignExt8to64 x) (OR (NEGV (SGTU (ZeroExt8to64 y) (MOVVconst [63]))) (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 + if !(!ssa.ShiftIsBounded(v)) { + break + } v.Reset(ssaop.OpMIPS64SRAV) v0 := b.NewValue0(v.Pos, ssaop.OpSignExt8to64, typ.Int64) v0.AddArg(x) @@ -7282,6 +8193,7 @@ func rewriteValue_OpRsh8x8(v *ssa.Value) bool { v.AddArg2(v0, v1) return true } + return false } func rewriteValue_OpSelect0(v *ssa.Value) bool { v_0 := v.Args[0] diff --git a/src/cmd/go/testdata/script/tool_build_as_needed.txt b/src/cmd/go/testdata/script/tool_build_as_needed.txt index fc8e60fafb3520..cf1a3d746aa3e4 100644 --- a/src/cmd/go/testdata/script/tool_build_as_needed.txt +++ b/src/cmd/go/testdata/script/tool_build_as_needed.txt @@ -1,7 +1,10 @@ [!symlink] skip 'uses symlinks to construct a GOROOT' env NEWGOROOT=$WORK${/}goroot -env TOOLDIR=$GOROOT/pkg/tool/${GOOS}_${GOARCH} +# Use the installed host tools, but make testgo find them under its runtime tuple. +env TOOLDIR=$GOROOT/pkg/tool/${TESTGO_GOHOSTOS}_${TESTGO_GOHOSTARCH} +env TESTGO_GOHOSTOS=$GOOS +env TESTGO_GOHOSTARCH=$GOARCH # Use ${/} in paths we'll check for in stdout below, so they contain '\' on Windows env NEWTOOLDIR=$NEWGOROOT${/}pkg${/}tool${/}${GOOS}_${GOARCH} mkdir $NEWGOROOT $NEWGOROOT/bin $NEWTOOLDIR diff --git a/src/runtime/export_test.go b/src/runtime/export_test.go index b044dbb3e15b85..47e3e3d5fa8806 100644 --- a/src/runtime/export_test.go +++ b/src/runtime/export_test.go @@ -574,6 +574,22 @@ func NextArenaHint() (uintptr, bool) { return mheap_.arenaHints.addr, true } +const RandomizeHeapBase = randomizeHeapBase + +// ArenaHintAddrs returns the heap's remaining arena hint addresses, in +// chain order. +func ArenaHintAddrs() []uintptr { + // Preallocate: appending while holding the heap lock would allocate + // under mheap_.lock. mallocinit generates at most 64 heap hints. + out := make([]uintptr, 0, 128) + lock(&mheap_.lock) + for h := mheap_.arenaHints; h != nil; h = h.next { + out = append(out, h.addr) + } + unlock(&mheap_.lock) + return out +} + type G = g type Sudog = sudog diff --git a/src/runtime/malloc.go b/src/runtime/malloc.go index 4dc040c7098c79..b68820c9a75c78 100644 --- a/src/runtime/malloc.go +++ b/src/runtime/malloc.go @@ -354,9 +354,22 @@ const ( // See comment in mallocinit for how the randomization is performed. randomizeHeapBase = goexperiment.RandomizedHeapBase64 && goarch.PtrSize == 8 && !isSbrkPlatform && !raceenabled && !msanenabled && !asanenabled - // randHeapBasePrefixMask is used to extract the top byte of the randomized - // heap base address. - randHeapBasePrefixMask = ^uintptr(0xff << (heapAddrBits - 8)) + // randHeapAddrBits is the number of address bits usable by the randomized + // heap base. heapAddrBits is 48 on most platforms, but we only use 47 of + // those bits in order to provide a good amount of room for the heap to + // grow contiguously. On amd64, there are 48 bits, but the top bit is sign + // extended, so we throw away another bit, just to be safe. + randHeapAddrBits = heapAddrBits - 1 - goarch.IsAmd64 + + // randHeapBasePrefixMask clears the top byte of the randomized heap base + // address -- the byte hint generation replaces with randHeapBasePrefix+i. + // The prefix occupies bits [randHeapAddrBits-8, randHeapAddrBits), so the + // mask must be defined from randHeapAddrBits, not heapAddrBits: a wider + // mask would let stray randHeapBase bits overlap the prefix byte in the + // OR that hint generation performs, and wherever such a stray bit is 1, + // the corresponding bit of every generated prefix is forced to 1, + // collapsing distinct prefixes into duplicate hint addresses. + randHeapBasePrefixMask = ^uintptr(0xff << (randHeapAddrBits - 8)) ) // physPageSize is the size in bytes of the OS's physical pages. @@ -567,11 +580,6 @@ func mallocinit() { var randHeapBase uintptr var randHeapBasePrefix byte - // heapAddrBits is 48 on most platforms, but we only use 47 of those - // bits in order to provide a good amount of room for the heap to grow - // contiguously. On amd64, there are 48 bits, but the top bit is sign - // extended, so we throw away another bit, just to be safe. - randHeapAddrBits := heapAddrBits - 1 - (goarch.IsAmd64 * 1) if randomizeHeapBase { // Generate a random value, and take the bottom heapAddrBits-logHeapArenaBytes // bits, using them as the top bits for randHeapBase. diff --git a/src/runtime/malloc_test.go b/src/runtime/malloc_test.go index 1cf3d9000442bc..9aece833460377 100644 --- a/src/runtime/malloc_test.go +++ b/src/runtime/malloc_test.go @@ -886,3 +886,32 @@ func TestScanAllocIssue77573(t *testing.T) { verifyScanAlloc(t, func() { runtime.Escape(make([]*int, 3)) }, 3*goarch.PtrSize) }) } + +func TestArenaHintChainGeneration(t *testing.T) { + // Regression test for the randomized-heap-base prefix mask: + // randHeapBasePrefixMask used to clear the top byte at + // heapAddrBits-8 while hint generation placed the random prefix + // byte at randHeapAddrBits-8, so two stray randHeapBase bits were + // OR'd into the prefix's low bits, collapsing distinct prefixes + // into duplicate hint addresses on most launches. The hint chain + // must hold pairwise-distinct addresses with at most one + // non-ascending step (the prefix byte's single mod-256 wrap). + if !RandomizeHeapBase { + t.Skip("heap base randomization is disabled in this configuration") + } + addrs := ArenaHintAddrs() + seen := make(map[uintptr]bool, len(addrs)) + descents := 0 + for i, a := range addrs { + if seen[a] { + t.Errorf("duplicate arena hint address %#x", a) + } + seen[a] = true + if i > 0 && a <= addrs[i-1] { + descents++ + } + } + if descents > 1 { + t.Errorf("%d non-ascending steps in arena hint chain, want at most 1 (addrs %#x)", descents, addrs) + } +} diff --git a/src/simd/archsimd/_gen/simdgen/arch.go b/src/simd/archsimd/_gen/simdgen/arch.go index cd6d7284620252..52f506080ed64c 100644 --- a/src/simd/archsimd/_gen/simdgen/arch.go +++ b/src/simd/archsimd/_gen/simdgen/arch.go @@ -165,10 +165,15 @@ var sveArrangements = []string{"B", "H", "S", "D"} // simdARM64SVEOps function, bound to concrete regInfo values in ARM64Ops.go. var sveRegInfoKeys = []string{ "z11", // 1 Z in, 1 Z out (unary, e.g. NEG) + "zkv", // 1 Z in, 1 P (implicit-all-true governing predicate) in, 1 Z out (predicated-only unary, e.g. ZABS) "z21", // 2 Z in, 1 Z out (binary, e.g. unpredicated ADD) "z2kk", // 2 Z in, 1 P (governing predicate) in, 1 P out (predicated compare, e.g. ZCMPGT) "z2kv", // 2 Z in, 1 P (select predicate) in, 1 Z out (constructive, e.g. ZSEL) "z2kvPred", // 2 Z in, 1 P (governing predicate) in, 1 Z out (destructive, e.g. ZADD/M) + // 2 Z in, 1 P (governing predicate) in, 1 Z out, destination shared with the + // first input: a constructive predicated op whose merging form names the + // value the destination starts out holding, e.g. ZABSMerging. + "z2kvPredResultInArg0", // 3 Z in, 1 P (governing predicate) in, 1 Z out, destination shared with the // first input: a destructive predicated op behind a MOVPRFX, e.g. ZADDMergingPrefixed. "z3kvPredResultInArg0", @@ -176,6 +181,7 @@ var sveRegInfoKeys = []string{ var sveRegInfoSet = map[string]bool{ "z11": true, + "zkv": true, "z21": true, "z2kk": true, "z2kv": true, @@ -183,7 +189,7 @@ var sveRegInfoSet = map[string]bool{ "z3kvPred": true, } -const sveRegInfoParams = "z11, z21, z2kk, z2kv, z2kvPred, z3kvPred regInfo" +const sveRegInfoParams = "z11, z21, zkv, z2kk, z2kv, z2kvPred, z3kvPred regInfo" const sveGeneratedHeader = `// Code generated by 'simdgen -o godefs -goroot $GOROOT -arch sve -arm64Path $ARM64_ISA_PATH go_sve.yaml types.yaml categories.yaml'; DO NOT EDIT. ` diff --git a/src/simd/archsimd/_gen/simdgen/gen_simdMachineOps.go b/src/simd/archsimd/_gen/simdgen/gen_simdMachineOps.go index 65b85612ffb1b7..758920eef0e310 100644 --- a/src/simd/archsimd/_gen/simdgen/gen_simdMachineOps.go +++ b/src/simd/archsimd/_gen/simdgen/gen_simdMachineOps.go @@ -42,6 +42,12 @@ func simd{{.SIMDTag}}Ops({{.RegInfoParams}}) []opData { // writeSIMDMachineOps generates the machine ops and writes it to simdAMD64ops.go // within the specified directory. +// isWidthAgnostic reports whether the operation is an SVE width-agnostic +// bitwise op (see types.RawOperation.WidthAgnostic). +func isWidthAgnostic(gOp Operation) bool { + return gOp.WidthAgnostic != nil && *gOp.WidthAgnostic +} + func writeSIMDMachineOps(buffer *bytes.Buffer, ops []Operation) { t := templateOf(simdMachineOpsTmpl, "simdAMD64Ops") buffer.WriteString(generatedHeader()) @@ -91,6 +97,14 @@ func writeSIMDMachineOps(buffer *bytes.Buffer, ops []Operation) { for _, op := range ops { _, _, maskType, _, gOp, _ := op.shape() asm := machineOpName(maskType, gOp) + if isWidthAgnostic(gOp) { + // The unpredicated machine op of a width-agnostic bitwise operation + // collapses to one .D instruction, but its predicated forms merge at + // a real element granularity, so every width's def must survive this + // dedup to generate them; the shared unpredicated opData is deduped + // at the append instead. + asm = fmt.Sprintf("%s#%d", asm, *gOp.Out[0].ElemBits) + } other, ok := best[asm] if !ok { best[asm] = op @@ -109,9 +123,11 @@ func writeSIMDMachineOps(buffer *bytes.Buffer, ops []Operation) { regInfoErrs := make([]error, 0) regInfoMissing := make(map[string]bool, 0) + seenUnpred := make(map[string]bool) for _, asm := range mOpOrder { op := best[asm] shapeIn, shapeOut, maskType, _, gOp, _ := op.shape() + asm = machineOpName(maskType, gOp) // TODO: all our masked operations are now zeroing, we need to generate machine ops with merging masks, maybe copy // one here with a name suffix "Merging". The rewrite rules will need them. @@ -231,7 +247,10 @@ func writeSIMDMachineOps(buffer *bytes.Buffer, ops []Operation) { opsDataImmMerging = append(opsDataImmMerging, opData{asm, gOp.Asm, mergingLen, regInfoMerging, gOp.Commutative, outType, resultInArg0}) } } else { - opsData = append(opsData, opData{asm, gOp.Asm, len(gOp.In), regInfo, gOp.Commutative, outType, resultInArg0}) + if !seenUnpred[asm] { + seenUnpred[asm] = true + opsData = append(opsData, opData{asm, gOp.Asm, len(gOp.In), regInfo, gOp.Commutative, outType, resultInArg0}) + } // The inVariant implies machine ops only: one predicated instruction // per governing-predicate qualifier the encoding supports, reached by // peephole rather than by any API of its own. diff --git a/src/simd/archsimd/_gen/simdgen/godefs.go b/src/simd/archsimd/_gen/simdgen/godefs.go index c1c481cc60c60a..1f81b7dad823a4 100644 --- a/src/simd/archsimd/_gen/simdgen/godefs.go +++ b/src/simd/archsimd/_gen/simdgen/godefs.go @@ -293,6 +293,14 @@ func machineOpName(maskType maskShape, gOp Operation) string { if letter := sveArrangementLetter(gOp); letter != "" { // SVE: scalable vectors have no fixed width, so distinguish machine ops // by element-size arrangement letter (B/H/S/D), e.g. ZADD -> ZADDB. + // + // A width-agnostic bitwise operation is one .D instruction serving + // every element width, so its unpredicated machine op is always the D + // one, shared by all the generic ops; only its predicated forms, which + // merge at a real element granularity, stay per width. + if maskType == NoMask && gOp.WidthAgnostic != nil && *gOp.WidthAgnostic { + letter = "D" + } asm += letter } else if gOp.Arrangement != nil && *gOp.Arrangement != "" { asm = fmt.Sprintf("%s%s", asm, *gOp.Arrangement) diff --git a/src/simd/archsimd/_gen/simdgen/ops/AddSub/go_sve.yaml b/src/simd/archsimd/_gen/simdgen/ops/AddSub/go_sve.yaml index 5f5cef185cd366..4559e133738faf 100644 --- a/src/simd/archsimd/_gen/simdgen/ops/AddSub/go_sve.yaml +++ b/src/simd/archsimd/_gen/simdgen/ops/AddSub/go_sve.yaml @@ -9,6 +9,15 @@ out: - *any +# Sub — integer SUB and floating-point FSUB, unpredicated. +- go: Sub + asm: "ZSUB|ZFSUB" + in: + - *any + - *any + out: + - *any + # AddSaturated — signed saturating SQADD, unpredicated. - go: AddSaturated asm: "ZSQADD" @@ -30,3 +39,21 @@ - *uint out: - *uint + +# SubSaturated — signed saturating SQSUB, unpredicated. +- go: SubSaturated + asm: "ZSQSUB" + in: + - *int + - *int + out: + - *int + +# SubSaturated — unsigned saturating UQSUB, unpredicated. +- go: SubSaturated + asm: "ZUQSUB" + in: + - *uint + - *uint + out: + - *uint diff --git a/src/simd/archsimd/_gen/simdgen/ops/BitwiseLogic/go_sve.yaml b/src/simd/archsimd/_gen/simdgen/ops/BitwiseLogic/go_sve.yaml new file mode 100644 index 00000000000000..db866f54d5d967 --- /dev/null +++ b/src/simd/archsimd/_gen/simdgen/ops/BitwiseLogic/go_sve.yaml @@ -0,0 +1,57 @@ +!sum +# And — bitwise AND, both signednesses. The unpredicated ZAND is a single +# width-agnostic .D encoding that the loader emits at every element width; its +# predicated sibling merges per , so the merging machine ops stay per width. +- go: And + asm: "ZAND" + in: + - &int + go: $t + base: int + - *int + out: + - *int + +- go: And + asm: "ZAND" + in: + - &uint + go: $t + base: uint + - *uint + out: + - *uint + +# Or — bitwise inclusive OR, ZORR. Width-agnostic like ZAND. +- go: Or + asm: "ZORR" + in: + - *int + - *int + out: + - *int + +- go: Or + asm: "ZORR" + in: + - *uint + - *uint + out: + - *uint + +# Xor — bitwise exclusive OR, ZEOR. Width-agnostic like ZAND. +- go: Xor + asm: "ZEOR" + in: + - *int + - *int + out: + - *int + +- go: Xor + asm: "ZEOR" + in: + - *uint + - *uint + out: + - *uint diff --git a/src/simd/archsimd/_gen/simdgen/ops/Compares/go_sve.yaml b/src/simd/archsimd/_gen/simdgen/ops/Compares/go_sve.yaml index e98f02d3b8f8b9..2a6a74f91da0fb 100644 --- a/src/simd/archsimd/_gen/simdgen/ops/Compares/go_sve.yaml +++ b/src/simd/archsimd/_gen/simdgen/ops/Compares/go_sve.yaml @@ -11,3 +11,115 @@ - class: mask # governing predicate out: - class: mask + +# Greater — unsigned integer compare, ZCMPHI ("higher"). +- go: Greater + asm: "ZCMPHI" + in: + - &uint + go: $t + base: uint + - *uint + - class: mask # governing predicate + out: + - class: mask + +# Greater — floating-point compare, ZFCMGT. +- go: Greater + asm: "ZFCMGT" + in: + - &float + go: $t + base: float + - *float + - class: mask # governing predicate + out: + - class: mask + +# Equal — integer compare, ZCMPEQ (sign-agnostic, both signednesses). +- go: Equal + asm: "ZCMPEQ" + in: + - *int + - *int + - class: mask # governing predicate + out: + - class: mask + +- go: Equal + asm: "ZCMPEQ" + in: + - *uint + - *uint + - class: mask # governing predicate + out: + - class: mask + +# Equal — floating-point compare, ZFCMEQ. +- go: Equal + asm: "ZFCMEQ" + in: + - *float + - *float + - class: mask # governing predicate + out: + - class: mask + +# NotEqual — integer compare, ZCMPNE (sign-agnostic, both signednesses). +- go: NotEqual + asm: "ZCMPNE" + in: + - *int + - *int + - class: mask # governing predicate + out: + - class: mask + +- go: NotEqual + asm: "ZCMPNE" + in: + - *uint + - *uint + - class: mask # governing predicate + out: + - class: mask + +# NotEqual — floating-point compare, ZFCMNE. +- go: NotEqual + asm: "ZFCMNE" + in: + - *float + - *float + - class: mask # governing predicate + out: + - class: mask + +# GreaterEqual — signed integer compare, ZCMPGE. +- go: GreaterEqual + asm: "ZCMPGE" + in: + - *int + - *int + - class: mask # governing predicate + out: + - class: mask + +# GreaterEqual — unsigned integer compare, ZCMPHS ("higher or same"). +- go: GreaterEqual + asm: "ZCMPHS" + in: + - *uint + - *uint + - class: mask # governing predicate + out: + - class: mask + +# GreaterEqual — floating-point compare, ZFCMGE. +- go: GreaterEqual + asm: "ZFCMGE" + in: + - *float + - *float + - class: mask # governing predicate + out: + - class: mask diff --git a/src/simd/archsimd/_gen/simdgen/ops/FPonlyArith/go_sve.yaml b/src/simd/archsimd/_gen/simdgen/ops/FPonlyArith/go_sve.yaml new file mode 100644 index 00000000000000..3b9925e2245a21 --- /dev/null +++ b/src/simd/archsimd/_gen/simdgen/ops/FPonlyArith/go_sve.yaml @@ -0,0 +1,50 @@ +!sum +# Sqrt — floating-point square root, ZFSQRT. Predicated-only: the governing +# predicate is implicit-all-true and the merging qualifier becomes the +# predicated machine op. +- go: Sqrt + asm: "ZFSQRT" + in: + - &float + go: $t + base: float + - class: mask # governing predicate + out: + - *float + +# Ceil — floating-point round (ZFRINTP). Predicated-only, same shape as Sqrt. +- go: Ceil + asm: "ZFRINTP" + in: + - *float + - class: mask # governing predicate + out: + - *float + +# Floor — floating-point round (ZFRINTM). Predicated-only, same shape as Sqrt. +- go: Floor + asm: "ZFRINTM" + in: + - *float + - class: mask # governing predicate + out: + - *float + +# Trunc — floating-point round (ZFRINTZ). Predicated-only, same shape as Sqrt. +- go: Trunc + asm: "ZFRINTZ" + in: + - *float + - class: mask # governing predicate + out: + - *float + +# Round — floating-point round to nearest, ties to even (ZFRINTN). +# Predicated-only, same shape as Sqrt. +- go: Round + asm: "ZFRINTN" + in: + - *float + - class: mask # governing predicate + out: + - *float diff --git a/src/simd/archsimd/_gen/simdgen/ops/IntOnlyArith/go_sve.yaml b/src/simd/archsimd/_gen/simdgen/ops/IntOnlyArith/go_sve.yaml new file mode 100644 index 00000000000000..990d9331af2039 --- /dev/null +++ b/src/simd/archsimd/_gen/simdgen/ops/IntOnlyArith/go_sve.yaml @@ -0,0 +1,13 @@ +!sum +# Abs — signed integer absolute value. ZABS is predicated-only: it has no +# unpredicated encoding, so its governing predicate is implicit-all-true and +# its merging qualifier becomes the predicated machine op. +- go: Abs + asm: "ZABS" + in: + - &int + go: $t + base: int + - class: mask # governing predicate + out: + - *int diff --git a/src/simd/archsimd/_gen/simdgen/ops/NegAbs/go_sve.yaml b/src/simd/archsimd/_gen/simdgen/ops/NegAbs/go_sve.yaml new file mode 100644 index 00000000000000..71cf7c8ea6ee6c --- /dev/null +++ b/src/simd/archsimd/_gen/simdgen/ops/NegAbs/go_sve.yaml @@ -0,0 +1,34 @@ +!sum +# Neg — signed integer negate. ZNEG is predicated-only, like ZABS: the +# governing predicate is implicit-all-true and the merging qualifier becomes +# the predicated machine op. +- go: Neg + asm: "ZNEG" + in: + - &int + go: $t + base: int + - class: mask # governing predicate + out: + - *int + +# Neg — floating-point negate, ZFNEG. Same shape as ZNEG. +- go: Neg + asm: "ZFNEG" + in: + - &float + go: $t + base: float + - class: mask # governing predicate + out: + - *float + +# Abs — floating-point absolute value, ZFABS. Predicated-only, same shape as +# ZFNEG; the integer ZABS lives in IntOnlyArith. +- go: Abs + asm: "ZFABS" + in: + - *float + - class: mask # governing predicate + out: + - *float diff --git a/src/simd/archsimd/_gen/simdgen/sve/emit.go b/src/simd/archsimd/_gen/simdgen/sve/emit.go index 5c0fa294819583..8e4887e1a51d7b 100644 --- a/src/simd/archsimd/_gen/simdgen/sve/emit.go +++ b/src/simd/archsimd/_gen/simdgen/sve/emit.go @@ -127,7 +127,7 @@ func pickRegNames(variants []predVariant, idx int, sel func(predVariant) []strin // // An SVE predicate is a mandatory input, not an optional AVX-512-style K-mask, so // it goes in `in`; inVariant is emitted empty just to satisfy the types.yaml schema. -func (inst *Instruction) emitOne(asm string, ops []Operand) *unify.Value { +func (inst *Instruction) emitOne(asm string, ops []Operand, widthAgnostic bool) *unify.Value { var db unify.DefBuilder db.Add("asm", unify.NewValue(unify.NewStringExact(asm))) db.Add("goarch", unify.NewValue(unify.NewStringExact("arm64"))) @@ -135,6 +135,9 @@ func (inst *Instruction) emitOne(asm string, ops []Operand) *unify.Value { if doc := inst.documentation(); doc != "" { db.Add("details", unify.NewValue(unify.NewStringExact(asComment(doc, 80)))) } + if widthAgnostic { + db.Add("widthAgnostic", unify.NewValue(unify.NewStringExact("true"))) + } // One def can describe several encodings of one operation, grouped by // [groupPredicationForms] or [groupPredicatedOnly], so each operand also @@ -246,6 +249,17 @@ func (inst *Instruction) emitVariants(template []Operand) []*unify.Value { // encoding), or a single no-op pass when there is no governing predicate. preds := predicationVariants(template) + // A bitwise operation with no variable arrangement is width-agnostic: the + // encoding is written .D, but any element view of it computes the same + // bits, and its predicated sibling is a per- encoding. Emit a def per + // element width so every Go type gets the API, marked so that simdgen + // collapses the unpredicated machine op back to the single .D instruction. + widths := []int{0} + widthAgnostic := len(links) == 0 && inst.bitwise() + if widthAgnostic { + widths = []int{8, 16, 32, 64} + } + var defs []*unify.Value for _, sign := range signs { for _, size := range sizes { @@ -314,7 +328,19 @@ func (inst *Instruction) emitVariants(template []Operand) []*unify.Value { variant[i].ElemBits = elem } } - defs = append(defs, inst.emitOne(asm, variant)) + for _, w := range widths { + v := variant + if w > 0 { + v = make([]Operand, len(variant)) + copy(v, variant) + for i := range v { + if v[i].Class == "vreg" || v[i].Class == "mask" { + v[i].ElemBits = w + } + } + } + defs = append(defs, inst.emitOne(asm, v, widthAgnostic)) + } } } } diff --git a/src/simd/archsimd/_gen/simdgen/sve/instruction.go b/src/simd/archsimd/_gen/simdgen/sve/instruction.go index bfa4bf6c71f651..310bbc0fc78c54 100644 --- a/src/simd/archsimd/_gen/simdgen/sve/instruction.go +++ b/src/simd/archsimd/_gen/simdgen/sve/instruction.go @@ -227,6 +227,14 @@ func (inst *Instruction) laneIsFloat(op *Operand) bool { return isFloatBrief(inst.brief()) } +// bitwise reports whether this instruction is a bitwise operation, which the +// spec's brief description spells with a "Bitwise " prefix (mirroring the NEON +// loader's test). A bitwise vector encoding is written .D but is element-width +// agnostic: any lane view of it is valid. +func (inst *Instruction) bitwise() bool { + return strings.HasPrefix(inst.brief(), "Bitwise ") +} + // isFloatBrief reports whether a brief description names a floating-point type. // SVE spells these as "floating-point", "bfloat", or an "X-precision" (half / // single / double / 8-bit) qualifier. diff --git a/src/simd/archsimd/_gen/simdgen/types/operation.go b/src/simd/archsimd/_gen/simdgen/types/operation.go index 35476f7259570f..9bfccd3e3e5a05 100644 --- a/src/simd/archsimd/_gen/simdgen/types/operation.go +++ b/src/simd/archsimd/_gen/simdgen/types/operation.go @@ -51,6 +51,12 @@ type RawOperation struct { // If true, do not emit method declarations, generic ops, or intrinsics for masked variants // DO emit the architecture-specific opcodes and optimizations. HideMaskMethods *bool + // WidthAgnostic marks an SVE bitwise operation whose unpredicated encoding + // is written .D but computes the same bits under any element view. The + // loader emits one def per element width so every Go type gets the API; + // the unpredicated machine op collapses back to the single .D instruction + // (see machineOpName), while the per- predicated forms stay per width. + WidthAgnostic *bool } // MaxVectorBits is the maximum vector length in bits Go currently supports (256 diff --git a/src/simd/archsimd/internal/simd_test/binary_sve_arm64_test.go b/src/simd/archsimd/internal/simd_test/binary_sve_arm64_test.go index 2a70ab94ed1265..40dd55e4f67b26 100644 --- a/src/simd/archsimd/internal/simd_test/binary_sve_arm64_test.go +++ b/src/simd/archsimd/internal/simd_test/binary_sve_arm64_test.go @@ -14,6 +14,7 @@ package simd_test import ( + "math" "simd/archsimd" "testing" ) @@ -88,3 +89,235 @@ func TestAddSVE(t *testing.T) { testFloat32sBinary(t, archsimd.Float32s.Add, addSlice[float32]) testFloat64sBinary(t, archsimd.Float64s.Add, addSlice[float64]) } + +func TestSubSVE(t *testing.T) { + if !archsimd.ARM64.SVE() { + t.Skip("no SVE") + } + testInt8sBinary(t, archsimd.Int8s.Sub, subSlice[int8]) + testInt16sBinary(t, archsimd.Int16s.Sub, subSlice[int16]) + testInt32sBinary(t, archsimd.Int32s.Sub, subSlice[int32]) + testInt64sBinary(t, archsimd.Int64s.Sub, subSlice[int64]) + testUint8sBinary(t, archsimd.Uint8s.Sub, subSlice[uint8]) + testFloat32sBinary(t, archsimd.Float32s.Sub, subSlice[float32]) + testFloat64sBinary(t, archsimd.Float64s.Sub, subSlice[float64]) +} + +// testSVEUnary drives a scalable unary op, the one-input counterpart of +// testSVEBinary. +func testSVEUnary[T number, V any](t *testing.T, pool []T, elemBytes, active int, + load func([]T) V, f func(V) V, store func(V, []T), want func([]T) []T) { + t.Helper() + count := sveMaxBytes / elemBytes + forSlice(t, pool, count, func(x []T) bool { + t.Helper() + g := make([]T, count) + store(f(load(x)), g) + w := want(x) + return checkSlicesLogInput(t, g[:active], w[:active], 0.0, func() { + t.Helper() + t.Logf("x=%v", x) + }) + }) +} + +func TestAbsSVE(t *testing.T) { + if !archsimd.ARM64.SVE() { + t.Skip("no SVE") + } + absSlice := func(x []int8) []int8 { + r := make([]int8, len(x)) + for i, v := range x { + if v < 0 { + v = -v // -128 stays -128, as ABS does + } + r[i] = v + } + return r + } + var z archsimd.Int8s + testSVEUnary(t, int8s, 1, z.Len(), archsimd.LoadInt8s, archsimd.Int8s.Abs, archsimd.Int8s.Store, absSlice) + absFloat32 := func(x []float32) []float32 { + r := make([]float32, len(x)) + for i, v := range x { + r[i] = float32(math.Abs(float64(v))) + } + return r + } + var zf archsimd.Float32s + testSVEUnary(t, float32s, 4, zf.Len(), archsimd.LoadFloat32s, archsimd.Float32s.Abs, archsimd.Float32s.Store, absFloat32) +} + +func TestNegSVE(t *testing.T) { + if !archsimd.ARM64.SVE() { + t.Skip("no SVE") + } + negInt8 := func(x []int8) []int8 { + r := make([]int8, len(x)) + for i, v := range x { + r[i] = -v + } + return r + } + negFloat64 := func(x []float64) []float64 { + r := make([]float64, len(x)) + for i, v := range x { + r[i] = -v + } + return r + } + var zi archsimd.Int8s + testSVEUnary(t, int8s, 1, zi.Len(), archsimd.LoadInt8s, archsimd.Int8s.Neg, archsimd.Int8s.Store, negInt8) + var zf archsimd.Float64s + testSVEUnary(t, float64s, 8, zf.Len(), archsimd.LoadFloat64s, archsimd.Float64s.Neg, archsimd.Float64s.Store, negFloat64) +} + +func TestSqrtSVE(t *testing.T) { + if !archsimd.ARM64.SVE() { + t.Skip("no SVE") + } + var in, got [4]float64 + for i := range in { + in[i] = float64(i + 1) + } + v := archsimd.LoadFloat64s(in[:]) + v.Sqrt().Store(got[:]) + var z archsimd.Float64s + for i := 0; i < z.Len(); i++ { + if want := math.Sqrt(in[i]); got[i] != want { + t.Errorf("lane %d: Sqrt(%v) = %v, want %v", i, in[i], got[i], want) + } + } +} + +func TestCeilSVE(t *testing.T) { + if !archsimd.ARM64.SVE() { + t.Skip("no SVE") + } + var in, got [4]float64 + for i := range in { + in[i] = float64(i) - 1.5 + } + v := archsimd.LoadFloat64s(in[:]) + v.Ceil().Store(got[:]) + var z archsimd.Float64s + for i := 0; i < z.Len(); i++ { + if want := math.Ceil(in[i]); got[i] != want { + t.Errorf("lane %d: Ceil(%v) = %v, want %v", i, in[i], got[i], want) + } + } +} + +func TestFloorSVE(t *testing.T) { + if !archsimd.ARM64.SVE() { + t.Skip("no SVE") + } + var in, got [4]float64 + for i := range in { + in[i] = float64(i) - 1.5 + } + v := archsimd.LoadFloat64s(in[:]) + v.Floor().Store(got[:]) + var z archsimd.Float64s + for i := 0; i < z.Len(); i++ { + if want := math.Floor(in[i]); got[i] != want { + t.Errorf("lane %d: Floor(%v) = %v, want %v", i, in[i], got[i], want) + } + } +} + +func TestTruncSVE(t *testing.T) { + if !archsimd.ARM64.SVE() { + t.Skip("no SVE") + } + var in, got [4]float64 + for i := range in { + in[i] = float64(i) - 1.5 + } + v := archsimd.LoadFloat64s(in[:]) + v.Trunc().Store(got[:]) + var z archsimd.Float64s + for i := 0; i < z.Len(); i++ { + if want := math.Trunc(in[i]); got[i] != want { + t.Errorf("lane %d: Trunc(%v) = %v, want %v", i, in[i], got[i], want) + } + } +} + +func TestRoundSVE(t *testing.T) { + if !archsimd.ARM64.SVE() { + t.Skip("no SVE") + } + var in, got [4]float64 + for i := range in { + in[i] = float64(i) - 1.5 + } + v := archsimd.LoadFloat64s(in[:]) + v.Round().Store(got[:]) + var z archsimd.Float64s + for i := 0; i < z.Len(); i++ { + if want := math.RoundToEven(in[i]); got[i] != want { + t.Errorf("lane %d: Round(%v) = %v, want %v", i, in[i], got[i], want) + } + } +} + +func TestAndSVE(t *testing.T) { + if !archsimd.ARM64.SVE() { + t.Skip("no SVE") + } + andInt8 := func(x, y []int8) []int8 { + r := make([]int8, len(x)) + for i := range x { + r[i] = x[i] & y[i] + } + return r + } + testInt8sBinary(t, archsimd.Int8s.And, andInt8) + andUint64 := func(x, y []uint64) []uint64 { + r := make([]uint64, len(x)) + for i := range x { + r[i] = x[i] & y[i] + } + return r + } + var z archsimd.Uint64s + testSVEBinary(t, uint64s, 8, z.Len(), archsimd.LoadUint64s, archsimd.Uint64s.And, archsimd.Uint64s.Store, andUint64) +} + +func TestOrSVE(t *testing.T) { + if !archsimd.ARM64.SVE() { + t.Skip("no SVE") + } + orInt8 := func(x, y []int8) []int8 { + r := make([]int8, len(x)) + for i := range x { + r[i] = x[i] | y[i] + } + return r + } + testInt8sBinary(t, archsimd.Int8s.Or, orInt8) + orUint64 := func(x, y []uint64) []uint64 { + r := make([]uint64, len(x)) + for i := range x { + r[i] = x[i] | y[i] + } + return r + } + var z archsimd.Uint64s + testSVEBinary(t, uint64s, 8, z.Len(), archsimd.LoadUint64s, archsimd.Uint64s.Or, archsimd.Uint64s.Store, orUint64) +} + +func TestXorSVE(t *testing.T) { + if !archsimd.ARM64.SVE() { + t.Skip("no SVE") + } + xorInt8 := func(x, y []int8) []int8 { + r := make([]int8, len(x)) + for i := range x { + r[i] = x[i] ^ y[i] + } + return r + } + testInt8sBinary(t, archsimd.Int8s.Xor, xorInt8) +} diff --git a/src/simd/archsimd/internal/simd_test/compare_sve_arm64_test.go b/src/simd/archsimd/internal/simd_test/compare_sve_arm64_test.go index 05d3b5de84cf40..73c4f8561c77ba 100644 --- a/src/simd/archsimd/internal/simd_test/compare_sve_arm64_test.go +++ b/src/simd/archsimd/internal/simd_test/compare_sve_arm64_test.go @@ -59,6 +59,21 @@ func testInt64sCompare(t *testing.T, cmp func(_, _ archsimd.Int64s) archsimd.Mas testSVECompare(t, int64s, 8, z.Len(), archsimd.LoadInt64s, cmp, archsimd.Mask64s.Store, want) } +func testUint8sCompare(t *testing.T, cmp func(_, _ archsimd.Uint8s) archsimd.Mask8s, want func(_, _ uint8) bool) { + var z archsimd.Uint8s + testSVECompare(t, uint8s, 1, z.Len(), archsimd.LoadUint8s, cmp, archsimd.Mask8s.Store, want) +} + +func testFloat32sCompare(t *testing.T, cmp func(_, _ archsimd.Float32s) archsimd.Mask32s, want func(_, _ float32) bool) { + var z archsimd.Float32s + testSVECompare(t, float32s, 4, z.Len(), archsimd.LoadFloat32s, cmp, archsimd.Mask32s.Store, want) +} + +func testFloat64sCompare(t *testing.T, cmp func(_, _ archsimd.Float64s) archsimd.Mask64s, want func(_, _ float64) bool) { + var z archsimd.Float64s + testSVECompare(t, float64s, 8, z.Len(), archsimd.LoadFloat64s, cmp, archsimd.Mask64s.Store, want) +} + func TestGreaterSVE(t *testing.T) { if !archsimd.ARM64.SVE() { t.Skip("no sve") @@ -67,6 +82,9 @@ func TestGreaterSVE(t *testing.T) { testInt16sCompare(t, archsimd.Int16s.Greater, func(a, b int16) bool { return a > b }) testInt32sCompare(t, archsimd.Int32s.Greater, func(a, b int32) bool { return a > b }) testInt64sCompare(t, archsimd.Int64s.Greater, func(a, b int64) bool { return a > b }) + testUint8sCompare(t, archsimd.Uint8s.Greater, func(a, b uint8) bool { return a > b }) + testFloat32sCompare(t, archsimd.Float32s.Greater, func(a, b float32) bool { return a > b }) + testFloat64sCompare(t, archsimd.Float64s.Greater, func(a, b float64) bool { return a > b }) } // TestMaskStoreLoadPanicSVE checks that the exported mask memory APIs panic when @@ -84,3 +102,30 @@ func TestMaskStoreLoadPanicSVE(t *testing.T) { m.Store(bits) archsimd.LoadMask8s(bits) } + +func TestEqualSVE(t *testing.T) { + if !archsimd.ARM64.SVE() { + t.Skip("no sve") + } + testInt8sCompare(t, archsimd.Int8s.Equal, func(a, b int8) bool { return a == b }) + testUint8sCompare(t, archsimd.Uint8s.Equal, func(a, b uint8) bool { return a == b }) + testFloat64sCompare(t, archsimd.Float64s.Equal, func(a, b float64) bool { return a == b }) +} + +func TestNotEqualSVE(t *testing.T) { + if !archsimd.ARM64.SVE() { + t.Skip("no sve") + } + testInt8sCompare(t, archsimd.Int8s.NotEqual, func(a, b int8) bool { return a != b }) + testUint8sCompare(t, archsimd.Uint8s.NotEqual, func(a, b uint8) bool { return a != b }) + testFloat64sCompare(t, archsimd.Float64s.NotEqual, func(a, b float64) bool { return a != b }) +} + +func TestGreaterEqualSVE(t *testing.T) { + if !archsimd.ARM64.SVE() { + t.Skip("no sve") + } + testInt8sCompare(t, archsimd.Int8s.GreaterEqual, func(a, b int8) bool { return a >= b }) + testUint8sCompare(t, archsimd.Uint8s.GreaterEqual, func(a, b uint8) bool { return a >= b }) + testFloat64sCompare(t, archsimd.Float64s.GreaterEqual, func(a, b float64) bool { return a >= b }) +} diff --git a/src/simd/archsimd/internal/simd_test/simd_arm64_test.go b/src/simd/archsimd/internal/simd_test/simd_arm64_test.go index bcb2facd2c7b55..420bd7cd423741 100644 --- a/src/simd/archsimd/internal/simd_test/simd_arm64_test.go +++ b/src/simd/archsimd/internal/simd_test/simd_arm64_test.go @@ -156,6 +156,37 @@ func TestAddSaturatedSVE(t *testing.T) { } } +// TestSubSaturatedSVE checks that the generated saturating subtract saturates. +func TestSubSaturatedSVE(t *testing.T) { + if !archsimd.ARM64.SVE() { + t.Skip("no sve") + } + var sx, sy, gi [32]int8 + for i := range sx { + sx[i] = 100 // 100 - (-100) saturates to +127 + sy[i] = -100 + } + x, y := archsimd.LoadInt8s(sx[:]), archsimd.LoadInt8s(sy[:]) + x.SubSaturated(y).Store(gi[:]) + for i := 0; i < x.Len(); i++ { + if gi[i] != 127 { + t.Errorf("int8 lane %d: got %d, want 127", i, gi[i]) + } + } + var ux, uy, gu [32]uint8 + for i := range ux { + ux[i] = 10 // 10 - 20 saturates to 0 + uy[i] = 20 + } + vx, vy := archsimd.LoadUint8s(ux[:]), archsimd.LoadUint8s(uy[:]) + vx.SubSaturated(vy).Store(gu[:]) + for i := 0; i < vx.Len(); i++ { + if gu[i] != 0 { + t.Errorf("uint8 lane %d: got %d, want 0", i, gu[i]) + } + } +} + func TestStringSVE(t *testing.T) { if !archsimd.ARM64.SVE() { t.Skip("no sve") @@ -269,6 +300,63 @@ func TestIfElseSVE(t *testing.T) { return 0 }) + // SUB is not commutative, so only an "else" operand that is the destructive + // one — the minuend — folds into the merging-predicated instruction. + check("Sub.IfElse(x)", x.Sub(y).IfElse(m, x), func(i int, active bool) int8 { + if active { + return xs[i] - ys[i] + } + return xs[i] + }) + // Does not fold, and must not silently become y-x. + check("Sub.IfElse(y)", x.Sub(y).IfElse(m, y), func(i int, active bool) int8 { + if active { + return xs[i] - ys[i] + } + return ys[i] + }) + // Does not fold: there is no prefixed form for a non-commutative operation. + check("Sub.IfElse(z)", x.Sub(y).IfElse(m, z), func(i int, active bool) int8 { + if active { + return xs[i] - ys[i] + } + return zs[i] + }) + check("Sub.Masked", x.Sub(y).Masked(m), func(i int, active bool) int8 { + if active { + return xs[i] - ys[i] + } + return 0 + }) + + // Abs is predicated-only, so its unpredicated API runs under an all-true + // predicate that a select can simply replace: IfElse becomes the merging + // form and Masked the zeroing one, each a single instruction. + absLane := func(v int8) int8 { + if v < 0 { + return -v + } + return v + } + check("Abs.IfElse(z)", x.Abs().IfElse(m, z), func(i int, active bool) int8 { + if active { + return absLane(xs[i]) + } + return zs[i] + }) + check("Abs.IfElse(x)", x.Abs().IfElse(m, x), func(i int, active bool) int8 { + if active { + return absLane(xs[i]) + } + return xs[i] + }) + check("Abs.Masked", x.Abs().Masked(m), func(i int, active bool) int8 { + if active { + return absLane(xs[i]) + } + return 0 + }) + // The prefixed path with every operand still live afterwards, so the // destination can be none of them and the merging MOVPRFX has to place the // else operand itself. diff --git a/src/simd/archsimd/ops_sve.go b/src/simd/archsimd/ops_sve.go index 1a1fc5ebff0e31..1a5f75d18eabb6 100644 --- a/src/simd/archsimd/ops_sve.go +++ b/src/simd/archsimd/ops_sve.go @@ -4,6 +4,38 @@ package archsimd +/* Abs */ + +// Abs computes the absolute value of each element. +// +// Asm: ZFABS, CPU Feature: SVE +func (x Float32s) Abs() Float32s + +// Abs computes the absolute value of each element. +// +// Asm: ZFABS, CPU Feature: SVE +func (x Float64s) Abs() Float64s + +// Abs computes the absolute value of each element. +// +// Asm: ZABS, CPU Feature: SVE +func (x Int8s) Abs() Int8s + +// Abs computes the absolute value of each element. +// +// Asm: ZABS, CPU Feature: SVE +func (x Int16s) Abs() Int16s + +// Abs computes the absolute value of each element. +// +// Asm: ZABS, CPU Feature: SVE +func (x Int32s) Abs() Int32s + +// Abs computes the absolute value of each element. +// +// Asm: ZABS, CPU Feature: SVE +func (x Int64s) Abs() Int64s + /* Add */ // Add adds corresponding elements of two vectors. @@ -98,8 +130,136 @@ func (x Uint32s) AddSaturated(y Uint32s) Uint32s // Asm: ZUQADD, CPU Feature: SVE func (x Uint64s) AddSaturated(y Uint64s) Uint64s +/* And */ + +// And performs a bitwise x & y. +// +// Asm: ZAND, CPU Feature: SVE +func (x Int8s) And(y Int8s) Int8s + +// And performs a bitwise x & y. +// +// Asm: ZAND, CPU Feature: SVE +func (x Int16s) And(y Int16s) Int16s + +// And performs a bitwise x & y. +// +// Asm: ZAND, CPU Feature: SVE +func (x Int32s) And(y Int32s) Int32s + +// And performs a bitwise x & y. +// +// Asm: ZAND, CPU Feature: SVE +func (x Int64s) And(y Int64s) Int64s + +// And performs a bitwise x & y. +// +// Asm: ZAND, CPU Feature: SVE +func (x Uint8s) And(y Uint8s) Uint8s + +// And performs a bitwise x & y. +// +// Asm: ZAND, CPU Feature: SVE +func (x Uint16s) And(y Uint16s) Uint16s + +// And performs a bitwise x & y. +// +// Asm: ZAND, CPU Feature: SVE +func (x Uint32s) And(y Uint32s) Uint32s + +// And performs a bitwise x & y. +// +// Asm: ZAND, CPU Feature: SVE +func (x Uint64s) And(y Uint64s) Uint64s + +/* Ceil */ + +// Ceil rounds elements up to the nearest integer. +// +// Asm: ZFRINTP, CPU Feature: SVE +func (x Float32s) Ceil() Float32s + +// Ceil rounds elements up to the nearest integer. +// +// Asm: ZFRINTP, CPU Feature: SVE +func (x Float64s) Ceil() Float64s + +/* Equal */ + +// Equal returns a mask whose elements indicate whether x == y. +// +// Asm: ZFCMEQ, CPU Feature: SVE +func (x Float32s) Equal(y Float32s) Mask32s + +// Equal returns a mask whose elements indicate whether x == y. +// +// Asm: ZFCMEQ, CPU Feature: SVE +func (x Float64s) Equal(y Float64s) Mask64s + +// Equal returns a mask whose elements indicate whether x == y. +// +// Asm: ZCMPEQ, CPU Feature: SVE +func (x Int8s) Equal(y Int8s) Mask8s + +// Equal returns a mask whose elements indicate whether x == y. +// +// Asm: ZCMPEQ, CPU Feature: SVE +func (x Int16s) Equal(y Int16s) Mask16s + +// Equal returns a mask whose elements indicate whether x == y. +// +// Asm: ZCMPEQ, CPU Feature: SVE +func (x Int32s) Equal(y Int32s) Mask32s + +// Equal returns a mask whose elements indicate whether x == y. +// +// Asm: ZCMPEQ, CPU Feature: SVE +func (x Int64s) Equal(y Int64s) Mask64s + +// Equal returns a mask whose elements indicate whether x == y. +// +// Asm: ZCMPEQ, CPU Feature: SVE +func (x Uint8s) Equal(y Uint8s) Mask8s + +// Equal returns a mask whose elements indicate whether x == y. +// +// Asm: ZCMPEQ, CPU Feature: SVE +func (x Uint16s) Equal(y Uint16s) Mask16s + +// Equal returns a mask whose elements indicate whether x == y. +// +// Asm: ZCMPEQ, CPU Feature: SVE +func (x Uint32s) Equal(y Uint32s) Mask32s + +// Equal returns a mask whose elements indicate whether x == y. +// +// Asm: ZCMPEQ, CPU Feature: SVE +func (x Uint64s) Equal(y Uint64s) Mask64s + +/* Floor */ + +// Floor rounds elements down to the nearest integer. +// +// Asm: ZFRINTM, CPU Feature: SVE +func (x Float32s) Floor() Float32s + +// Floor rounds elements down to the nearest integer. +// +// Asm: ZFRINTM, CPU Feature: SVE +func (x Float64s) Floor() Float64s + /* Greater */ +// Greater returns a mask whose elements indicate whether x > y. +// +// Asm: ZFCMGT, CPU Feature: SVE +func (x Float32s) Greater(y Float32s) Mask32s + +// Greater returns a mask whose elements indicate whether x > y. +// +// Asm: ZFCMGT, CPU Feature: SVE +func (x Float64s) Greater(y Float64s) Mask64s + // Greater returns a mask whose elements indicate whether x > y. // // Asm: ZCMPGT, CPU Feature: SVE @@ -120,6 +280,376 @@ func (x Int32s) Greater(y Int32s) Mask32s // Asm: ZCMPGT, CPU Feature: SVE func (x Int64s) Greater(y Int64s) Mask64s +// Greater returns a mask whose elements indicate whether x > y. +// +// Asm: ZCMPHI, CPU Feature: SVE +func (x Uint8s) Greater(y Uint8s) Mask8s + +// Greater returns a mask whose elements indicate whether x > y. +// +// Asm: ZCMPHI, CPU Feature: SVE +func (x Uint16s) Greater(y Uint16s) Mask16s + +// Greater returns a mask whose elements indicate whether x > y. +// +// Asm: ZCMPHI, CPU Feature: SVE +func (x Uint32s) Greater(y Uint32s) Mask32s + +// Greater returns a mask whose elements indicate whether x > y. +// +// Asm: ZCMPHI, CPU Feature: SVE +func (x Uint64s) Greater(y Uint64s) Mask64s + +/* GreaterEqual */ + +// GreaterEqual returns a mask whose elements indicate whether x >= y. +// +// Asm: ZFCMGE, CPU Feature: SVE +func (x Float32s) GreaterEqual(y Float32s) Mask32s + +// GreaterEqual returns a mask whose elements indicate whether x >= y. +// +// Asm: ZFCMGE, CPU Feature: SVE +func (x Float64s) GreaterEqual(y Float64s) Mask64s + +// GreaterEqual returns a mask whose elements indicate whether x >= y. +// +// Asm: ZCMPGE, CPU Feature: SVE +func (x Int8s) GreaterEqual(y Int8s) Mask8s + +// GreaterEqual returns a mask whose elements indicate whether x >= y. +// +// Asm: ZCMPGE, CPU Feature: SVE +func (x Int16s) GreaterEqual(y Int16s) Mask16s + +// GreaterEqual returns a mask whose elements indicate whether x >= y. +// +// Asm: ZCMPGE, CPU Feature: SVE +func (x Int32s) GreaterEqual(y Int32s) Mask32s + +// GreaterEqual returns a mask whose elements indicate whether x >= y. +// +// Asm: ZCMPGE, CPU Feature: SVE +func (x Int64s) GreaterEqual(y Int64s) Mask64s + +// GreaterEqual returns a mask whose elements indicate whether x >= y. +// +// Asm: ZCMPHS, CPU Feature: SVE +func (x Uint8s) GreaterEqual(y Uint8s) Mask8s + +// GreaterEqual returns a mask whose elements indicate whether x >= y. +// +// Asm: ZCMPHS, CPU Feature: SVE +func (x Uint16s) GreaterEqual(y Uint16s) Mask16s + +// GreaterEqual returns a mask whose elements indicate whether x >= y. +// +// Asm: ZCMPHS, CPU Feature: SVE +func (x Uint32s) GreaterEqual(y Uint32s) Mask32s + +// GreaterEqual returns a mask whose elements indicate whether x >= y. +// +// Asm: ZCMPHS, CPU Feature: SVE +func (x Uint64s) GreaterEqual(y Uint64s) Mask64s + +/* Neg */ + +// Neg returns the elementwise negation of x. +// +// Asm: ZFNEG, CPU Feature: SVE +func (x Float32s) Neg() Float32s + +// Neg returns the elementwise negation of x. +// +// Asm: ZFNEG, CPU Feature: SVE +func (x Float64s) Neg() Float64s + +// Neg returns the elementwise negation of x. +// +// Asm: ZNEG, CPU Feature: SVE +func (x Int8s) Neg() Int8s + +// Neg returns the elementwise negation of x. +// +// Asm: ZNEG, CPU Feature: SVE +func (x Int16s) Neg() Int16s + +// Neg returns the elementwise negation of x. +// +// Asm: ZNEG, CPU Feature: SVE +func (x Int32s) Neg() Int32s + +// Neg returns the elementwise negation of x. +// +// Asm: ZNEG, CPU Feature: SVE +func (x Int64s) Neg() Int64s + +/* NotEqual */ + +// NotEqual returns a mask whose elements indicate whether x != y. +// +// Asm: ZFCMNE, CPU Feature: SVE +func (x Float32s) NotEqual(y Float32s) Mask32s + +// NotEqual returns a mask whose elements indicate whether x != y. +// +// Asm: ZFCMNE, CPU Feature: SVE +func (x Float64s) NotEqual(y Float64s) Mask64s + +// NotEqual returns a mask whose elements indicate whether x != y. +// +// Asm: ZCMPNE, CPU Feature: SVE +func (x Int8s) NotEqual(y Int8s) Mask8s + +// NotEqual returns a mask whose elements indicate whether x != y. +// +// Asm: ZCMPNE, CPU Feature: SVE +func (x Int16s) NotEqual(y Int16s) Mask16s + +// NotEqual returns a mask whose elements indicate whether x != y. +// +// Asm: ZCMPNE, CPU Feature: SVE +func (x Int32s) NotEqual(y Int32s) Mask32s + +// NotEqual returns a mask whose elements indicate whether x != y. +// +// Asm: ZCMPNE, CPU Feature: SVE +func (x Int64s) NotEqual(y Int64s) Mask64s + +// NotEqual returns a mask whose elements indicate whether x != y. +// +// Asm: ZCMPNE, CPU Feature: SVE +func (x Uint8s) NotEqual(y Uint8s) Mask8s + +// NotEqual returns a mask whose elements indicate whether x != y. +// +// Asm: ZCMPNE, CPU Feature: SVE +func (x Uint16s) NotEqual(y Uint16s) Mask16s + +// NotEqual returns a mask whose elements indicate whether x != y. +// +// Asm: ZCMPNE, CPU Feature: SVE +func (x Uint32s) NotEqual(y Uint32s) Mask32s + +// NotEqual returns a mask whose elements indicate whether x != y. +// +// Asm: ZCMPNE, CPU Feature: SVE +func (x Uint64s) NotEqual(y Uint64s) Mask64s + +/* Or */ + +// Or performs a bitwise x | y. +// +// Asm: ZORR, CPU Feature: SVE +func (x Int8s) Or(y Int8s) Int8s + +// Or performs a bitwise x | y. +// +// Asm: ZORR, CPU Feature: SVE +func (x Int16s) Or(y Int16s) Int16s + +// Or performs a bitwise x | y. +// +// Asm: ZORR, CPU Feature: SVE +func (x Int32s) Or(y Int32s) Int32s + +// Or performs a bitwise x | y. +// +// Asm: ZORR, CPU Feature: SVE +func (x Int64s) Or(y Int64s) Int64s + +// Or performs a bitwise x | y. +// +// Asm: ZORR, CPU Feature: SVE +func (x Uint8s) Or(y Uint8s) Uint8s + +// Or performs a bitwise x | y. +// +// Asm: ZORR, CPU Feature: SVE +func (x Uint16s) Or(y Uint16s) Uint16s + +// Or performs a bitwise x | y. +// +// Asm: ZORR, CPU Feature: SVE +func (x Uint32s) Or(y Uint32s) Uint32s + +// Or performs a bitwise x | y. +// +// Asm: ZORR, CPU Feature: SVE +func (x Uint64s) Or(y Uint64s) Uint64s + +/* Round */ + +// Round rounds elements to the nearest integer, rounding ties to even. +// +// Asm: ZFRINTN, CPU Feature: SVE +func (x Float32s) Round() Float32s + +// Round rounds elements to the nearest integer, rounding ties to even. +// +// Asm: ZFRINTN, CPU Feature: SVE +func (x Float64s) Round() Float64s + +/* Sqrt */ + +// Sqrt computes the square root of each element. +// +// Asm: ZFSQRT, CPU Feature: SVE +func (x Float32s) Sqrt() Float32s + +// Sqrt computes the square root of each element. +// +// Asm: ZFSQRT, CPU Feature: SVE +func (x Float64s) Sqrt() Float64s + +/* Sub */ + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: ZFSUB, CPU Feature: SVE +func (x Float32s) Sub(y Float32s) Float32s + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: ZFSUB, CPU Feature: SVE +func (x Float64s) Sub(y Float64s) Float64s + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: ZSUB, CPU Feature: SVE +func (x Int8s) Sub(y Int8s) Int8s + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: ZSUB, CPU Feature: SVE +func (x Int16s) Sub(y Int16s) Int16s + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: ZSUB, CPU Feature: SVE +func (x Int32s) Sub(y Int32s) Int32s + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: ZSUB, CPU Feature: SVE +func (x Int64s) Sub(y Int64s) Int64s + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: ZSUB, CPU Feature: SVE +func (x Uint8s) Sub(y Uint8s) Uint8s + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: ZSUB, CPU Feature: SVE +func (x Uint16s) Sub(y Uint16s) Uint16s + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: ZSUB, CPU Feature: SVE +func (x Uint32s) Sub(y Uint32s) Uint32s + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: ZSUB, CPU Feature: SVE +func (x Uint64s) Sub(y Uint64s) Uint64s + +/* SubSaturated */ + +// SubSaturated subtracts corresponding elements of two vectors with saturation. +// +// Asm: ZSQSUB, CPU Feature: SVE +func (x Int8s) SubSaturated(y Int8s) Int8s + +// SubSaturated subtracts corresponding elements of two vectors with saturation. +// +// Asm: ZSQSUB, CPU Feature: SVE +func (x Int16s) SubSaturated(y Int16s) Int16s + +// SubSaturated subtracts corresponding elements of two vectors with saturation. +// +// Asm: ZSQSUB, CPU Feature: SVE +func (x Int32s) SubSaturated(y Int32s) Int32s + +// SubSaturated subtracts corresponding elements of two vectors with saturation. +// +// Asm: ZSQSUB, CPU Feature: SVE +func (x Int64s) SubSaturated(y Int64s) Int64s + +// SubSaturated subtracts corresponding elements of two vectors with saturation. +// +// Asm: ZUQSUB, CPU Feature: SVE +func (x Uint8s) SubSaturated(y Uint8s) Uint8s + +// SubSaturated subtracts corresponding elements of two vectors with saturation. +// +// Asm: ZUQSUB, CPU Feature: SVE +func (x Uint16s) SubSaturated(y Uint16s) Uint16s + +// SubSaturated subtracts corresponding elements of two vectors with saturation. +// +// Asm: ZUQSUB, CPU Feature: SVE +func (x Uint32s) SubSaturated(y Uint32s) Uint32s + +// SubSaturated subtracts corresponding elements of two vectors with saturation. +// +// Asm: ZUQSUB, CPU Feature: SVE +func (x Uint64s) SubSaturated(y Uint64s) Uint64s + +/* Trunc */ + +// Trunc truncates elements towards zero. +// +// Asm: ZFRINTZ, CPU Feature: SVE +func (x Float32s) Trunc() Float32s + +// Trunc truncates elements towards zero. +// +// Asm: ZFRINTZ, CPU Feature: SVE +func (x Float64s) Trunc() Float64s + +/* Xor */ + +// Xor performs a bitwise x ^ y. +// +// Asm: ZEOR, CPU Feature: SVE +func (x Int8s) Xor(y Int8s) Int8s + +// Xor performs a bitwise x ^ y. +// +// Asm: ZEOR, CPU Feature: SVE +func (x Int16s) Xor(y Int16s) Int16s + +// Xor performs a bitwise x ^ y. +// +// Asm: ZEOR, CPU Feature: SVE +func (x Int32s) Xor(y Int32s) Int32s + +// Xor performs a bitwise x ^ y. +// +// Asm: ZEOR, CPU Feature: SVE +func (x Int64s) Xor(y Int64s) Int64s + +// Xor performs a bitwise x ^ y. +// +// Asm: ZEOR, CPU Feature: SVE +func (x Uint8s) Xor(y Uint8s) Uint8s + +// Xor performs a bitwise x ^ y. +// +// Asm: ZEOR, CPU Feature: SVE +func (x Uint16s) Xor(y Uint16s) Uint16s + +// Xor performs a bitwise x ^ y. +// +// Asm: ZEOR, CPU Feature: SVE +func (x Uint32s) Xor(y Uint32s) Uint32s + +// Xor performs a bitwise x ^ y. +// +// Asm: ZEOR, CPU Feature: SVE +func (x Uint64s) Xor(y Uint64s) Uint64s + // BitsToInt8 reinterprets the bits of a Uint8s vector as a Int8s vector func (x Uint8s) BitsToInt8() Int8s diff --git a/src/time/sleep_test.go b/src/time/sleep_test.go index 2dfcf61debbe49..484e703e99301e 100644 --- a/src/time/sleep_test.go +++ b/src/time/sleep_test.go @@ -10,6 +10,7 @@ import ( "internal/testenv" "math/rand" "runtime" + "slices" "strings" "sync" "sync/atomic" @@ -417,6 +418,9 @@ func testAfterStop(t *testing.T, newTimer func(Duration) *Timer) { logErrs() } +// TestAfterQueuing checks that concurrent After calls are queued by deadline: +// timers created in one order but with deadlines in another must fire in +// deadline order, and each must fire near its deadline. func TestAfterQueuing(t *testing.T) { t.Run("impl=chan", func(t *testing.T) { testAfterQueuing(t, After) @@ -427,8 +431,10 @@ func TestAfterQueuing(t *testing.T) { } func testAfterQueuing(t *testing.T, after func(Duration) <-chan Time) { - // This test flakes out on some systems, - // so we'll try it a few times before declaring it a failure. + // The arrival time check below depends on the timers running roughly on + // schedule, which a loaded machine cannot promise, so try a few times with + // increasing deltas before declaring a failure. The ordering check does not + // depend on load and would not benefit from a retry. const attempts = 5 err := errors.New("!=nil") for i := 0; i < attempts && err != nil; i++ { @@ -461,23 +467,33 @@ func testAfterQueuing1(delta Duration, after func(Duration) <-chan Time) error { t0 := Now() for _, slot := range slots { - go await(slot, result, After(Duration(slot)*delta)) + go await(slot, result, after(Duration(slot)*delta)) } - var order []int - var times []Time + results := make([]afterResult, 0, len(slots)) for range slots { - r := <-result - order = append(order, r.slot) - times = append(times, r.t) + results = append(results, <-result) } - for i := range order { - if i > 0 && order[i] < order[i-1] { - return fmt.Errorf("After calls returned out of order: %v", order) + + // Sort by the time each timer reported, which is the order the timers + // fired in. The order in which the goroutines started above manage to send + // on result is up to the scheduler, not the timers, so it says nothing + // about whether the timers were queued correctly. + slices.SortStableFunc(results, func(a, b afterResult) int { + return a.t.Compare(b.t) + }) + for i := range results { + if i > 0 && results[i].slot < results[i-1].slot { + fired := make([]int, len(results)) + for j, r := range results { + fired[j] = r.slot + } + return fmt.Errorf("After calls fired out of order: %v", fired) } } - for i, t := range times { - dt := t.Sub(t0) - target := Duration(order[i]) * delta + + for _, r := range results { + dt := r.t.Sub(t0) + target := Duration(r.slot) * delta if dt < target-delta/2 || dt > target+delta*10 { return fmt.Errorf("After(%s) arrived at %s, expected [%s,%s]", target, dt, target-delta/2, target+delta*10) } diff --git a/test/codegen/simd_arm64.go b/test/codegen/simd_arm64.go index 9fc1a2444e7ee8..98edf4cc0395af 100644 --- a/test/codegen/simd_arm64.go +++ b/test/codegen/simd_arm64.go @@ -201,6 +201,51 @@ func sveIfElseMovprfx(x, y archsimd.Int8s, m archsimd.Mask8s) archsimd.Int8s { return r } +// A non-commutative operation is more restricted. Its destructive operand is +// fixed, so only an "else" operand that is already that one folds, and there is +// no prefixed form to place any other. + +func sveIfElseFoldsSubMinuend(x, y archsimd.Int8s, m archsimd.Mask8s) archsimd.Int8s { + // arm64:`ZSUB.*P[0-9]+\.M` -`ZSEL` + return x.Sub(y).IfElse(m, x) +} + +func sveIfElseKeepsSelectSubSubtrahend(x, y archsimd.Int8s, m archsimd.Mask8s) archsimd.Int8s { + // Folding here would compute y-x. + // arm64:`ZSEL` -`ZSUB.*P[0-9]+\.M` + return x.Sub(y).IfElse(m, y) +} + +func sveIfElseKeepsSelectSubArbitrary(x, y, z archsimd.Int8s, m archsimd.Mask8s) archsimd.Int8s { + // arm64:`ZSEL` -`ZMOVPRFX` -`ZSUB.*P[0-9]+\.M` + return x.Sub(y).IfElse(m, z) +} + +// An operation that only comes predicated reaches its unpredicated API through +// an all-true predicate. A select over it replaces that predicate instead of +// adding an instruction. + +func sveAbsSynthesizesAllTrue(x archsimd.Int8s) archsimd.Int8s { + // arm64:`PWHILELT` `ZABS.*P[0-9]+\.M` + return x.Abs() +} + +func sveAbsIfElseFoldsToMerging(x, z archsimd.Int8s, m archsimd.Mask8s) archsimd.Int8s { + // ABS names its destination apart from its source, so the else operand is an + // operand of the instruction: no select, no MOVPRFX, and the all-true + // predicate is gone because the select's mask took its place. + // arm64:`ZABS.*P[0-9]+\.M` -`ZSEL` -`PWHILELT` -`ZMOVPRFX` + return x.Abs().IfElse(m, z) +} + +func sveAbsMaskedFoldsToMerging(x archsimd.Int8s, m archsimd.Mask8s) archsimd.Int8s { + // Masked folds through the same rule, with the zero vector as the else + // operand. Zeroing predication would save the ZDUP, but ABS only has a + // zeroing encoding from Armv9.6-A on. + // arm64:`ZABS.*P[0-9]+\.M` -`ZSEL` -`PWHILELT` + return x.Abs().Masked(m) +} + func sveIfElseFloat(x, y archsimd.Float64s, m archsimd.Mask64s) archsimd.Float64s { // arm64:`ZFADD.*P[0-9]+\.M` -`ZSEL` return x.Add(y).IfElse(m, x) diff --git a/test/fixedbugs/issue81286.dir/a.go b/test/fixedbugs/issue81286.dir/a.go new file mode 100644 index 00000000000000..ca70d90b595db6 --- /dev/null +++ b/test/fixedbugs/issue81286.dir/a.go @@ -0,0 +1,13 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package a + +type W struct{} + +var Last int + +func (W) M(x int) { + Last = x +} diff --git a/test/fixedbugs/issue81286.dir/b.go b/test/fixedbugs/issue81286.dir/b.go new file mode 100644 index 00000000000000..7329bbbc85506f --- /dev/null +++ b/test/fixedbugs/issue81286.dir/b.go @@ -0,0 +1,13 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package b + +type W struct{} + +var Called bool + +func (W) M() { + Called = true +} diff --git a/test/fixedbugs/issue81286.dir/main.go b/test/fixedbugs/issue81286.dir/main.go new file mode 100644 index 00000000000000..98c4dfb29b7aa2 --- /dev/null +++ b/test/fixedbugs/issue81286.dir/main.go @@ -0,0 +1,46 @@ +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package main + +import ( + "./a" + "./b" +) + +type A struct { + a.W +} + +type B struct { + b.W +} + +type I interface { + M(int) +} + +type J interface { + M() +} + +var x I +var y J + +func init() { + x = A{} + y = B{} +} + +func main() { + x.M(81286) + y.M() + + if a.Last != 81286 { + panic(a.Last) + } + if !b.Called { + panic("b.W.M was not called") + } +} diff --git a/test/fixedbugs/issue81286.go b/test/fixedbugs/issue81286.go new file mode 100644 index 00000000000000..78653fff04fe44 --- /dev/null +++ b/test/fixedbugs/issue81286.go @@ -0,0 +1,7 @@ +// rundir + +// Copyright 2026 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ignored