From 4741f007b838f0d6ccbb7fe51e650feef1617b80 Mon Sep 17 00:00:00 2001 From: Vishnu Reddy Date: Wed, 1 Jul 2026 18:02:08 +0530 Subject: [PATCH 01/10] iris: select vcodec core based on load on dual core platforms On platforms with two video codec cores, select the hardware core for a new session based on the current Macroblocks Per Frame (MBPF) and Macroblocks Per Second (MBPS) load on each core. The selected core is communicated to the firmware via the HFI_PROP_CORE_ID property at stream-on time. Signed-off-by: Vishnu Reddy --- .../platform/common/inc/msm_vidc_platform.h | 1 + driver/vidc/inc/msm_vidc_driver.h | 1 + driver/vidc/inc/msm_vidc_inst.h | 1 + driver/vidc/inc/msm_vidc_internal.h | 5 + driver/vidc/src/msm_vdec.c | 8 + driver/vidc/src/msm_venc.c | 4 + driver/vidc/src/msm_vidc_driver.c | 297 ++++++++++++++++++ 7 files changed, 317 insertions(+) diff --git a/driver/platform/common/inc/msm_vidc_platform.h b/driver/platform/common/inc/msm_vidc_platform.h index fc3c3aac4..80f79e7ff 100644 --- a/driver/platform/common/inc/msm_vidc_platform.h +++ b/driver/platform/common/inc/msm_vidc_platform.h @@ -372,6 +372,7 @@ struct msm_vidc_platform_data { const u32 *msm_vidc_ssr_type; unsigned int msm_vidc_ssr_type_size; int (*init_cb_devs)(struct msm_vidc_core *core); + u32 num_cores; }; struct msm_vidc_platform { diff --git a/driver/vidc/inc/msm_vidc_driver.h b/driver/vidc/inc/msm_vidc_driver.h index bde2b74b8..fb466c0a0 100644 --- a/driver/vidc/inc/msm_vidc_driver.h +++ b/driver/vidc/inc/msm_vidc_driver.h @@ -681,6 +681,7 @@ int msm_vidc_process_drain_done(struct msm_vidc_inst *inst); int msm_vidc_process_drain_last_flag(struct msm_vidc_inst *inst); int msm_vidc_process_psc_last_flag(struct msm_vidc_inst *inst); int msm_vidc_get_mbs_per_frame(struct msm_vidc_inst *inst); +int msm_vidc_set_core_id(struct msm_vidc_inst *inst); u32 msm_vidc_get_max_bitrate(struct msm_vidc_inst *inst); int msm_vidc_get_fps(struct msm_vidc_inst *inst); int msm_vidc_num_buffers(struct msm_vidc_inst *inst, diff --git a/driver/vidc/inc/msm_vidc_inst.h b/driver/vidc/inc/msm_vidc_inst.h index 99cf7a087..471c8ca41 100644 --- a/driver/vidc/inc/msm_vidc_inst.h +++ b/driver/vidc/inc/msm_vidc_inst.h @@ -152,6 +152,7 @@ struct msm_vidc_inst { u32 adjust_priority; bool iframe; u32 fw_min_count; + u32 core_id; }; #endif // _MSM_VIDC_INST_H_ diff --git a/driver/vidc/inc/msm_vidc_internal.h b/driver/vidc/inc/msm_vidc_internal.h index 346751c43..eaab0749a 100644 --- a/driver/vidc/inc/msm_vidc_internal.h +++ b/driver/vidc/inc/msm_vidc_internal.h @@ -501,6 +501,11 @@ enum msm_vidc_domain_type { MSM_VIDC_DECODER = BIT(1), }; +enum msm_vidc_vcodec_core_id { + MSM_VIDC_VCODEC0 = 1, + MSM_VIDC_VCODEC1, +}; + enum msm_vidc_codec_type { MSM_VIDC_H264 = BIT(0), MSM_VIDC_HEVC = BIT(1), diff --git a/driver/vidc/src/msm_vdec.c b/driver/vidc/src/msm_vdec.c index 6489d647a..c80fa07c2 100644 --- a/driver/vidc/src/msm_vdec.c +++ b/driver/vidc/src/msm_vdec.c @@ -1605,6 +1605,10 @@ int msm_vdec_streamon_input(struct msm_vidc_inst *inst) if (rc) goto error; + rc = msm_vidc_set_core_id(inst); + if (rc) + goto error; + rc = msm_vidc_set_v4l2_properties(inst); if (rc) goto error; @@ -1911,6 +1915,10 @@ int msm_vdec_streamon_output(struct msm_vidc_inst *inst) if (rc) goto error; + rc = msm_vidc_set_core_id(inst); + if (rc) + goto error; + rc = msm_vdec_set_output_properties(inst); if (rc) goto error; diff --git a/driver/vidc/src/msm_venc.c b/driver/vidc/src/msm_venc.c index 958390051..c84a30fb3 100644 --- a/driver/vidc/src/msm_venc.c +++ b/driver/vidc/src/msm_venc.c @@ -891,6 +891,10 @@ int msm_venc_streamon_input(struct msm_vidc_inst *inst) if (rc) goto error; + rc = msm_vidc_set_core_id(inst); + if (rc) + goto error; + rc = msm_vidc_check_scaling_supported(inst); if (rc) goto error; diff --git a/driver/vidc/src/msm_vidc_driver.c b/driver/vidc/src/msm_vidc_driver.c index 16eda6734..6d4d24b9c 100644 --- a/driver/vidc/src/msm_vidc_driver.c +++ b/driver/vidc/src/msm_vidc_driver.c @@ -2109,6 +2109,27 @@ int msm_vidc_get_mbs_per_frame(struct msm_vidc_inst *inst) return NUM_MBS_PER_FRAME(height, width); } +int msm_vidc_set_core_id(struct msm_vidc_inst *inst) +{ + u32 core_id = inst->core_id; + int rc; + + if (!core_id) + return 0; + + rc = venus_hfi_session_property(inst, + HFI_PROP_CORE_ID, + HFI_HOST_FLAGS_NONE, + HFI_PORT_NONE, + HFI_PAYLOAD_U32, + &core_id, + sizeof(u32)); + if (rc) + i_vpr_e(inst, "%s: set core_id failed\n", __func__); + + return rc; +} + int msm_vidc_get_fps(struct msm_vidc_inst *inst) { int fps; @@ -5844,6 +5865,276 @@ static bool msm_vidc_ignore_session_load(struct msm_vidc_inst *inst) return false; } +static int msm_vidc_check_core_mbps_dual_core(struct msm_vidc_inst *inst) +{ + struct msm_vidc_core *core = inst->core; + u32 num_cores = max(core->platform->data.num_cores, 1); + u32 max_session_cnt_per_core = core->capabilities[MAX_SESSION_COUNT].value / num_cores; + u32 max_load = core->capabilities[MAX_MBPS].value; + u32 core0_session_cnt = 0, core1_session_cnt = 0; + u64 core0_total_mbps = 0, core1_total_mbps = 0; + u64 core0_enc_mbps = 0, core1_enc_mbps = 0; + u64 core0_critical = 0, core1_critical = 0; + bool select_core0, select_core1; + struct msm_vidc_inst *instance; + u64 new_load, mbps; + + /* skip mbps check for non-realtime, thumbnail, image sessions */ + if (msm_vidc_ignore_session_load(inst)) { + i_vpr_h(inst, + "%s: skip mbps check due to NRT %d, TH %d, IMG %d, error session %d\n", + __func__, !is_realtime_session(inst), is_thumbnail_session(inst), + is_image_session(inst), is_session_error(inst)); + return 0; + } + + core_lock(core, __func__); + list_for_each_entry(instance, &core->instances, list) { + if (!is_critical_priority_session(instance)) + continue; + if (inst == instance) + continue; + + if (instance->core_id == MSM_VIDC_VCODEC0) + core0_critical += msm_vidc_get_inst_load(instance); + else if (instance->core_id == MSM_VIDC_VCODEC1) + core1_critical += msm_vidc_get_inst_load(instance); + } + core_unlock(core, __func__); + + if (core0_critical > max_load && core1_critical > max_load) { + i_vpr_e(inst, + "%s: Hardware overloaded with critical sessions. core0 %llu, core1 %llu, max %u\n", + __func__, core0_critical, core1_critical, max_load); + return -ENOMEM; + } + + core_lock(core, __func__); + list_for_each_entry(instance, &core->instances, list) { + /* ignore thumbnail, image, non realtime, error sessions */ + if (msm_vidc_ignore_session_load(instance)) + continue; + if (inst == instance) + continue; + + mbps = msm_vidc_get_inst_load(instance); + + if (instance->core_id == MSM_VIDC_VCODEC0) { + core0_total_mbps += mbps; + core0_session_cnt++; + if (is_encode_session(instance)) + core0_enc_mbps += mbps; + } else if (instance->core_id == MSM_VIDC_VCODEC1) { + core1_total_mbps += mbps; + core1_session_cnt++; + if (is_encode_session(instance)) + core1_enc_mbps += mbps; + } + } + core_unlock(core, __func__); + + if (is_encode_session(inst)) { + /* reject encoder if all encoders mbps is greater than MAX_MBPS */ + if (core0_enc_mbps > max_load && core1_enc_mbps > max_load) { + i_vpr_e(inst, + "%s: Hardware overloaded. core0 %llu, core1 %llu, max %u\n", + __func__, core0_enc_mbps, core1_enc_mbps, max_load); + return -ENOMEM; + } + + /* + * if total_mbps is greater than max_mbps then reduce all decoders + * priority by 1 to allow this encoder + */ + if (core0_total_mbps > max_load || core1_total_mbps > max_load) { + core_lock(core, __func__); + list_for_each_entry(instance, &core->instances, list) { + /* reduce realtime decode sessions priority */ + if (is_decode_session(instance) && is_realtime_session(instance)) { + instance->adjust_priority = RT_DEC_DOWN_PRORITY_OFFSET; + i_vpr_h(inst, "%s: pending adjust priority by %d\n", + __func__, instance->adjust_priority); + } + } + core_unlock(core, __func__); + } + } else if (is_decode_session(inst)) { + /* + * if total_mbps is greater than max_mbps then allow this + * decoder by reducing its piority (moving it to NRT) + */ + if (core0_total_mbps > max_load && core1_total_mbps > max_load) { + inst->adjust_priority = RT_DEC_DOWN_PRORITY_OFFSET; + i_vpr_h(inst, "%s: pending adjust priority by %d\n", + __func__, inst->adjust_priority); + } + } + + if (inst->core_id == MSM_VIDC_VCODEC0) + return core0_total_mbps <= max_load ? 0 : -ENOMEM; + else if (inst->core_id == MSM_VIDC_VCODEC1) + return core1_total_mbps <= max_load ? 0 : -ENOMEM; + + new_load = msm_vidc_get_inst_load(inst); + inst->core_id = 0; + + select_core0 = (core0_total_mbps + new_load <= max_load) && + (core0_session_cnt < max_session_cnt_per_core); + select_core1 = (core1_total_mbps + new_load <= max_load) && + (core1_session_cnt < max_session_cnt_per_core); + + if (select_core0 && select_core1) { + inst->core_id = (core0_total_mbps <= core1_total_mbps) ? + MSM_VIDC_VCODEC0 : MSM_VIDC_VCODEC1; + } else if (select_core0) { + inst->core_id = MSM_VIDC_VCODEC0; + } else if (select_core1) { + inst->core_id = MSM_VIDC_VCODEC1; + } else { + i_vpr_e(inst, + "%s: all cores overloaded. core0 %llu, core1 %llu, new_load %llu, max %u\n", + __func__, core0_total_mbps, core1_total_mbps, new_load, max_load); + return -ENOMEM; + } + + i_vpr_h(inst, + "%s: selected core_id %u (new_load=%llu, core0_total_mbps=%llu, core1_total_mbps=%llu, max=%u)\n", + __func__, inst->core_id, new_load, core0_total_mbps, core1_total_mbps, max_load); + + return 0; +} + +static int msm_vidc_check_core_mbpf_dual_core(struct msm_vidc_inst *inst) +{ + struct msm_vidc_core *core = inst->core; + u32 num_cores = max(core->platform->data.num_cores, 1); + u32 max_session_cnt_per_core = core->capabilities[MAX_SESSION_COUNT].value / num_cores; + u32 max_image_mbpf = core->capabilities[MAX_IMAGE_MBPF].value; + u32 max_rt_mbpf = core->capabilities[MAX_RT_MBPF].value; + u32 max_mbpf = core->capabilities[MAX_MBPF].value; + u32 core0_video_rt_mbpf = 0, core1_video_rt_mbpf = 0; + u32 core0_critical_mbpf = 0, core1_critical_mbpf = 0; + u32 core0_session_cnt = 0, core1_session_cnt = 0; + u32 core0_video_mbpf = 0, core1_video_mbpf = 0; + u32 core0_image_mbpf = 0, core1_image_mbpf = 0; + bool select_core0, select_core1; + struct msm_vidc_inst *instance; + u32 new_mbpf; + + core_lock(core, __func__); + list_for_each_entry(instance, &core->instances, list) { + if (!is_critical_priority_session(instance)) + continue; + if (inst == instance) + continue; + + if (instance->core_id == MSM_VIDC_VCODEC0) + core0_critical_mbpf += msm_vidc_get_mbs_per_frame(instance); + else if (instance->core_id == MSM_VIDC_VCODEC1) + core1_critical_mbpf += msm_vidc_get_mbs_per_frame(instance); + } + core_unlock(core, __func__); + + if (core0_critical_mbpf > max_mbpf && core1_critical_mbpf > max_mbpf) { + i_vpr_e(inst, + "%s: Hardware overloaded with critical sessions. core0 %u, core1 %u, max %u\n", + __func__, core0_critical_mbpf, core1_critical_mbpf, max_mbpf); + return -ENOMEM; + } + + core_lock(core, __func__); + list_for_each_entry(instance, &core->instances, list) { + /* ignore thumbnail session */ + if (is_thumbnail_session(instance)) + continue; + if (inst == instance) + continue; + + if (instance->core_id == MSM_VIDC_VCODEC0) { + if (is_image_session(instance)) + core0_image_mbpf += msm_vidc_get_mbs_per_frame(instance); + else + core0_video_mbpf += msm_vidc_get_mbs_per_frame(instance); + } else if (instance->core_id == MSM_VIDC_VCODEC1) { + if (is_image_session(instance)) + core1_image_mbpf += msm_vidc_get_mbs_per_frame(instance); + else + core1_video_mbpf += msm_vidc_get_mbs_per_frame(instance); + } + } + core_unlock(core, __func__); + + if (core0_video_mbpf > max_mbpf && core1_video_mbpf > max_mbpf) { + i_vpr_e(inst, + "%s: video overloaded. core0 %u, core1 %u, max %u\n", + __func__, core0_video_mbpf, core1_video_mbpf, max_mbpf); + return -ENOMEM; + } + + if (core0_image_mbpf > max_image_mbpf && core1_image_mbpf > max_image_mbpf) { + i_vpr_e(inst, + "%s: image overloaded. core0 %u, core1 %u, max %u\n", + __func__, core0_image_mbpf, core1_image_mbpf, max_image_mbpf); + return -ENOMEM; + } + + core_lock(core, __func__); + /* check real-time video sessions max limit */ + list_for_each_entry(instance, &core->instances, list) { + if (msm_vidc_ignore_session_load(instance)) + continue; + + if (instance->core_id == MSM_VIDC_VCODEC0) { + core0_video_rt_mbpf += msm_vidc_get_mbs_per_frame(instance); + core0_session_cnt++; + } else if (instance->core_id == MSM_VIDC_VCODEC1) { + core1_video_rt_mbpf += msm_vidc_get_mbs_per_frame(instance); + core1_session_cnt++; + } + } + core_unlock(core, __func__); + + if (core0_video_rt_mbpf > max_rt_mbpf && core1_video_rt_mbpf > max_rt_mbpf) { + i_vpr_e(inst, + "%s: real-time video overloaded. core0 %u, core1 %u, max %u\n", + __func__, core0_video_rt_mbpf, core1_video_rt_mbpf, max_rt_mbpf); + return -ENOMEM; + } + + if (inst->core_id == MSM_VIDC_VCODEC0) + return core0_video_mbpf <= max_mbpf ? 0 : -ENOMEM; + else if (inst->core_id == MSM_VIDC_VCODEC1) + return core1_video_mbpf <= max_mbpf ? 0 : -ENOMEM; + + new_mbpf = msm_vidc_get_mbs_per_frame(inst); + inst->core_id = 0; + + select_core0 = (core0_video_mbpf + new_mbpf <= max_mbpf) && + (core0_session_cnt < max_session_cnt_per_core); + select_core1 = (core1_video_mbpf + new_mbpf <= max_mbpf) && + (core1_session_cnt < max_session_cnt_per_core); + + if (select_core0 && select_core1) { + inst->core_id = (core0_video_mbpf <= core1_video_mbpf) ? + MSM_VIDC_VCODEC0 : MSM_VIDC_VCODEC1; + } else if (select_core0) { + inst->core_id = MSM_VIDC_VCODEC0; + } else if (select_core1) { + inst->core_id = MSM_VIDC_VCODEC1; + } else { + i_vpr_e(inst, + "%s: video overloaded. core0 %u, core1 %u, new_mbpf %u, max %u\n", + __func__, core0_video_mbpf, core1_video_mbpf, new_mbpf, max_mbpf); + return -ENOMEM; + } + + i_vpr_h(inst, + "%s: selected core_id %u (new_mbpf=%u, core0_video_mbpf=%u, core1_video_mbpf=%u, max=%u)\n", + __func__, inst->core_id, new_mbpf, core0_video_mbpf, core1_video_mbpf, max_mbpf); + + return 0; +} + int msm_vidc_check_core_mbps(struct msm_vidc_inst *inst) { u64 mbps = 0, total_mbps = 0, enc_mbps = 0, critical_mbps = 0; @@ -5852,6 +6143,9 @@ int msm_vidc_check_core_mbps(struct msm_vidc_inst *inst) core = inst->core; + if (core->platform->data.num_cores == 2) + return msm_vidc_check_core_mbps_dual_core(inst); + /* skip mbps check for non-realtime, thumnail, image sessions */ if (msm_vidc_ignore_session_load(inst)) { i_vpr_h(inst, @@ -5939,6 +6233,9 @@ int msm_vidc_check_core_mbpf(struct msm_vidc_inst *inst) core = inst->core; + if (core->platform->data.num_cores == 2) + return msm_vidc_check_core_mbpf_dual_core(inst); + core_lock(core, __func__); list_for_each_entry(instance, &core->instances, list) { if (is_critical_priority_session(instance)) From f62b188fafde588e7af7b4b6e120169fb1f5a5d3 Mon Sep 17 00:00:00 2001 From: Vishnu Reddy Date: Wed, 1 Jul 2026 18:02:08 +0530 Subject: [PATCH 02/10] iris: add support for glymur dual core power sequence Glymur has two video codec cores, VCODEC0 and VCODEC1. Add power-on and power-off sequences for the glymur controller and each vcodec core, along with register definitions needed to control and check per vcodec core power state. Signed-off-by: Vishnu Reddy --- driver/variant/iris36/inc/msm_vidc_iris36.h | 10 +- driver/variant/iris36/src/msm_vidc_iris36.c | 591 ++++++++++++++++++++ 2 files changed, 600 insertions(+), 1 deletion(-) diff --git a/driver/variant/iris36/inc/msm_vidc_iris36.h b/driver/variant/iris36/inc/msm_vidc_iris36.h index 8f707335b..216da8628 100644 --- a/driver/variant/iris36/inc/msm_vidc_iris36.h +++ b/driver/variant/iris36/inc/msm_vidc_iris36.h @@ -9,9 +9,12 @@ struct msm_vidc_core; struct v4l2_ctrl; -#if defined(CONFIG_MSM_VIDC_NORDAU) +#if defined(CONFIG_MSM_VIDC_NORDAU) || \ + defined(CONFIG_MSM_VIDC_GLYMUR) || \ + defined(CONFIG_MSM_VIDC_QLI) int msm_vidc_init_iris36(struct msm_vidc_core *core); int msm_vidc_adjust_bitrate_boost_iris36(void *instance, struct v4l2_ctrl *ctrl); +int msm_vidc_init_glymur_iris36(struct msm_vidc_core *core); #else static inline int msm_vidc_init_iris36(struct msm_vidc_core *core) { @@ -22,6 +25,11 @@ static inline int msm_vidc_adjust_bitrate_boost_iris36(void *instance, struct v4 { return -EINVAL; } + +static inline int msm_vidc_init_glymur_iris36(struct msm_vidc_core *core) +{ + return -EINVAL; +} #endif #endif // _MSM_VIDC_IRIS36_H_ diff --git a/driver/variant/iris36/src/msm_vidc_iris36.c b/driver/variant/iris36/src/msm_vidc_iris36.c index 5de585498..bf5896171 100644 --- a/driver/variant/iris36/src/msm_vidc_iris36.c +++ b/driver/variant/iris36/src/msm_vidc_iris36.c @@ -25,6 +25,8 @@ #define VIDEO_ARCH_LX 1 #define VCODEC_BASE_OFFS_IRIS36 0x00000000 +#define VCODEC1_BASE_OFFS_IRIS36 0x00040000 + /* * MSM_VIDC_HW_VIRT is enabled for hw virtualization only; in hw virtualization * scheme, each GVM will access only CS block registers and only CS block @@ -121,12 +123,31 @@ enum { #define AON_WRAPPER_MVP_NOC_CORE_SW_RESET (AON_BASE_OFFS + 0x18) #define AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL (AON_BASE_OFFS + 0x20) #define AON_WRAPPER_SPARE (AON_BASE_OFFS + 0x28) +#define AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL (AON_BASE_OFFS + 0x2C) +#define AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_STATUS (AON_BASE_OFFS + 0x30) /* * -------------------------------------------------------------------------- * MODULE: VCODEC_SS registers * -------------------------------------------------------------------------- */ #define VCODEC_SS_IDLE_STATUSn (VCODEC_BASE_OFFS_IRIS36 + 0x70) +#define VCODEC1_SS_IDLE_STATUSn (VCODEC1_BASE_OFFS_IRIS36 + 0x70) + +#define DMA_NOC_IDLE BIT(22) +#define VCODEC0_POWER_STATUS BIT(1) +#define VCODEC1_POWER_STATUS BIT(4) +#define NOC_LPI_STATUS_DONE BIT(0) +#define NOC_LPI_STATUS_DENY BIT(1) +#define NOC_LPI_STATUS_ACTIVE BIT(2) +#define NOC_LPI_VCODEC1_STATUS_DONE BIT(8) +#define NOC_LPI_VCODEC1_STATUS_DENY BIT(9) +#define NOC_LPI_VCODEC1_STATUS_ACTIVE BIT(10) +#define REQ_VCODEC0_POWER_DOWN_PREP BIT(0) +#define REQ_VCODEC1_POWER_DOWN_PREP BIT(2) +#define VCODEC0_BRIDGE_SW_RESET BIT(0) +#define VCODEC0_BRIDGE_HW_RESET_DISABLE BIT(1) +#define VCODEC1_BRIDGE_SW_RESET BIT(4) +#define VCODEC1_BRIDGE_HW_RESET_DISABLE BIT(5) /* * -------------------------------------------------------------------------- @@ -1444,3 +1465,573 @@ int msm_vidc_init_iris36(struct msm_vidc_core *core) return 0; } + +static int __power_on_glymur_controller(struct msm_vidc_core *core) +{ + int rc; + + rc = call_res_op(core, gdsc_on, core, "venus"); + if (rc) { + d_vpr_e("%s: enable venus gdsc failed\n", __func__); + return rc; + } + + rc = call_res_op(core, clk_enable, core, "core_iface"); + if (rc) { + d_vpr_e("%s: enable core_iface failed\n", __func__); + goto fail_core_iface; + } + + rc = call_res_op(core, clk_enable, core, "core_freerun"); + if (rc) { + d_vpr_e("%s: enable core_freerun failed\n", __func__); + goto fail_core_freerun; + } + + rc = call_res_op(core, clk_enable, core, "core"); + if (rc) { + d_vpr_e("%s: enable core failed\n", __func__); + goto fail_core; + } + + return 0; + +fail_core: + call_res_op(core, clk_disable, core, "core_freerun"); +fail_core_freerun: + call_res_op(core, clk_disable, core, "core_iface"); +fail_core_iface: + call_res_op(core, gdsc_off, core, "venus"); + + return rc; +} + +static int __power_off_glymur_controller(struct msm_vidc_core *core) +{ + u32 handshake_done, handshake_busy; + u32 value, count = 0; + int rc; + + rc = __write_register(core, CPU_CS_X2RPMh_IRIS36, 0x3); + if (rc) + return rc; + + rc = __write_register(core, WRAPPER_IRIS_CPU_NOC_LPI_CONTROL, 0x1); + if (rc) + return rc; + + rc = __read_register_with_poll_timeout(core, WRAPPER_IRIS_CPU_NOC_LPI_STATUS, + 0x1, 0x1, 200, 2000); + if (rc) + goto disable_power; + + rc = __write_register(core, WRAPPER_IRIS_CPU_NOC_LPI_CONTROL, 0x0); + if (rc) + return rc; + + do { + rc = __write_register(core, AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL, 0x1); + if (rc) + return rc; + + usleep_range(10, 20); + + rc = __read_register(core, AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_STATUS, &value); + if (rc) + return rc; + + handshake_done = value & NOC_LPI_STATUS_DONE; + handshake_busy = value & (NOC_LPI_STATUS_DENY | NOC_LPI_STATUS_ACTIVE); + + if (handshake_done || !handshake_busy) + break; + + rc = __write_register(core, AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL, 0x0); + if (rc) + return rc; + + usleep_range(10, 20); + + } while (++count < 1000); + + if (!handshake_done && handshake_busy) + d_vpr_e("%s: LPI handshake timeout\n", __func__); + + rc = __read_register_with_poll_timeout(core, AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_STATUS, + 0x1, 0x1, 200, 2000); + if (rc) + goto disable_power; + + rc = __write_register(core, AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL, 0x0); + if (rc) + return rc; + + rc = __write_register(core, WRAPPER_DEBUG_BRIDGE_LPI_CONTROL_IRIS36, 0x0); + if (rc) + return rc; + + rc = __read_register_with_poll_timeout(core, WRAPPER_DEBUG_BRIDGE_LPI_STATUS_IRIS36, + 0x0, 0x0, 200, 2000); +disable_power: + call_res_op(core, reset_control_assert, core, "core_bus"); + call_res_op(core, reset_control_assert, core, "core"); + usleep_range(400, 500); + call_res_op(core, reset_control_deassert, core, "core_bus"); + call_res_op(core, reset_control_deassert, core, "core"); + + call_res_op(core, clk_disable, core, "core"); + call_res_op(core, clk_disable, core, "core_freerun"); + call_res_op(core, clk_disable, core, "core_iface"); + + call_res_op(core, gdsc_off, core, "venus"); + + return rc; +} + +static int __power_on_glymur_vcodec0(struct msm_vidc_core *core) +{ + int rc; + + rc = call_res_op(core, gdsc_on, core, "vcodec0"); + if (rc) { + d_vpr_e("%s: enable vcodec0 gdsc failed\n", __func__); + return rc; + } + + rc = call_res_op(core, clk_enable, core, "vcodec0_iface"); + if (rc) { + d_vpr_e("%s: enable vcodec0_iface failed\n", __func__); + goto fail_vcodec0_iface; + } + + rc = call_res_op(core, clk_enable, core, "vcodec0_core_freerun"); + if (rc) { + d_vpr_e("%s: enable vcodec0_core_freerun failed\n", __func__); + goto fail_vcodec0_freerun; + } + + rc = call_res_op(core, clk_enable, core, "vcodec0_core"); + if (rc) { + d_vpr_e("%s: enable vcodec0_core failed\n", __func__); + goto fail_vcodec0_core; + } + + return 0; + +fail_vcodec0_core: + call_res_op(core, clk_disable, core, "vcodec0_core_freerun"); +fail_vcodec0_freerun: + call_res_op(core, clk_disable, core, "vcodec0_iface"); +fail_vcodec0_iface: + call_res_op(core, gdsc_off, core, "vcodec0"); + + return rc; +} + +static int __power_on_glymur_vcodec1(struct msm_vidc_core *core) +{ + int rc; + + rc = call_res_op(core, gdsc_on, core, "vcodec1"); + if (rc) { + d_vpr_e("%s: enable vcodec1 gdsc failed\n", __func__); + return rc; + } + + rc = call_res_op(core, clk_enable, core, "vcodec1_iface"); + if (rc) { + d_vpr_e("%s: enable vcodec1_iface failed\n", __func__); + goto fail_vcodec1_iface; + } + + rc = call_res_op(core, clk_enable, core, "vcodec1_core_freerun"); + if (rc) { + d_vpr_e("%s: enable vcodec1_core_freerun failed\n", __func__); + goto fail_vcodec1_freerun; + } + + rc = call_res_op(core, clk_enable, core, "vcodec1_core"); + if (rc) { + d_vpr_e("%s: enable vcodec1_core failed\n", __func__); + goto fail_vcodec1_core; + } + + return 0; + +fail_vcodec1_core: + call_res_op(core, clk_disable, core, "vcodec1_core_freerun"); +fail_vcodec1_freerun: + call_res_op(core, clk_disable, core, "vcodec1_iface"); +fail_vcodec1_iface: + call_res_op(core, gdsc_off, core, "vcodec1"); + + return rc; +} + +static int __power_off_glymur_vcodec0(struct msm_vidc_core *core) +{ + bool handshake_done, handshake_busy; + u32 value, count = 0; + int rc, i; + + rc = __read_register(core, WRAPPER_CORE_POWER_STATUS, &value); + if (rc) + return rc; + + if (!(value & VCODEC0_POWER_STATUS)) + goto disable_power; + + rc = __read_register(core, WRAPPER_CORE_CLOCK_CONFIG_IRIS36, &value); + if (rc) + return rc; + + if (value) { + rc = __write_register(core, WRAPPER_CORE_CLOCK_CONFIG_IRIS36, 0x0); + if (rc) + return rc; + } + + for (i = 0; i < core->capabilities[NUM_VPP_PIPE].value; i++) { + rc = __read_register_with_poll_timeout(core, VCODEC_SS_IDLE_STATUSn + 4 * i, + DMA_NOC_IDLE, DMA_NOC_IDLE, 2000, 20000); + if (rc) + goto disable_power; + } + + do { + rc = __write_register(core, AON_WRAPPER_MVP_NOC_LPI_CONTROL, + REQ_VCODEC0_POWER_DOWN_PREP); + if (rc) + return rc; + + usleep_range(15, 20); + + rc = __read_register(core, AON_WRAPPER_MVP_NOC_LPI_STATUS, &value); + if (rc) + return rc; + + handshake_done = value & NOC_LPI_STATUS_DONE; + handshake_busy = value & (NOC_LPI_STATUS_DENY | NOC_LPI_STATUS_ACTIVE); + + if (handshake_done || !handshake_busy) + break; + + rc = __write_register(core, AON_WRAPPER_MVP_NOC_LPI_CONTROL, 0); + if (rc) + return rc; + + usleep_range(15, 20); + + } while (++count < 1000); + + if (!handshake_done && handshake_busy) + goto disable_power; + + rc = __read_register_with_poll_timeout(core, AON_WRAPPER_MVP_NOC_LPI_STATUS, + NOC_LPI_STATUS_DONE, + NOC_LPI_STATUS_DONE, 200, 2000); + if (rc) + goto disable_power; + + rc = __write_register(core, AON_WRAPPER_MVP_NOC_LPI_CONTROL, 0x0); + if (rc) + return rc; + + rc = __write_register(core, CPU_CS_AHB_BRIDGE_SYNC_RESET, VCODEC0_BRIDGE_SW_RESET | + VCODEC0_BRIDGE_HW_RESET_DISABLE); + if (rc) + return rc; + + rc = __write_register(core, CPU_CS_AHB_BRIDGE_SYNC_RESET, VCODEC0_BRIDGE_HW_RESET_DISABLE); + if (rc) + return rc; + + rc = __write_register(core, CPU_CS_AHB_BRIDGE_SYNC_RESET, 0x0); + if (rc) + return rc; + +disable_power: + call_res_op(core, reset_control_assert, core, "vcodec0_bus"); + call_res_op(core, reset_control_assert, core, "vcodec0_core"); + usleep_range(400, 500); + call_res_op(core, reset_control_deassert, core, "vcodec0_bus"); + call_res_op(core, reset_control_deassert, core, "vcodec0_core"); + + call_res_op(core, clk_disable, core, "vcodec0_core"); + call_res_op(core, clk_disable, core, "vcodec0_core_freerun"); + call_res_op(core, clk_disable, core, "vcodec0_iface"); + call_res_op(core, gdsc_off, core, "vcodec0"); + + return 0; +} + +static int __power_off_glymur_vcodec1(struct msm_vidc_core *core) +{ + bool handshake_done, handshake_busy; + u32 value, count = 0; + int rc, i; + + rc = __read_register(core, WRAPPER_CORE_POWER_STATUS, &value); + if (rc) + return rc; + + if (!(value & VCODEC1_POWER_STATUS)) + goto disable_power; + + rc = __read_register(core, WRAPPER_CORE_CLOCK_CONFIG_IRIS36, &value); + if (rc) + return rc; + + if (value) { + rc = __write_register(core, WRAPPER_CORE_CLOCK_CONFIG_IRIS36, 0x0); + if (rc) + return rc; + } + + for (i = 0; i < core->capabilities[NUM_VPP_PIPE].value; i++) { + rc = __read_register_with_poll_timeout(core, VCODEC1_SS_IDLE_STATUSn + 4 * i, + DMA_NOC_IDLE, DMA_NOC_IDLE, 2000, 20000); + if (rc) + goto disable_power; + } + + do { + rc = __write_register(core, AON_WRAPPER_MVP_NOC_LPI_CONTROL, + REQ_VCODEC1_POWER_DOWN_PREP); + if (rc) + return rc; + + usleep_range(15, 20); + + rc = __read_register(core, AON_WRAPPER_MVP_NOC_LPI_STATUS, &value); + if (rc) + return rc; + + handshake_done = value & NOC_LPI_VCODEC1_STATUS_DONE; + handshake_busy = value & (NOC_LPI_VCODEC1_STATUS_DENY | + NOC_LPI_VCODEC1_STATUS_ACTIVE); + + if (handshake_done || !handshake_busy) + break; + + rc = __write_register(core, AON_WRAPPER_MVP_NOC_LPI_CONTROL, 0); + if (rc) + return rc; + + usleep_range(15, 20); + + } while (++count < 1000); + + if (!handshake_done && handshake_busy) + goto disable_power; + + rc = __read_register_with_poll_timeout(core, AON_WRAPPER_MVP_NOC_LPI_STATUS, + NOC_LPI_VCODEC1_STATUS_DONE, + NOC_LPI_VCODEC1_STATUS_DONE, 200, 2000); + if (rc) + goto disable_power; + + rc = __write_register(core, AON_WRAPPER_MVP_NOC_LPI_CONTROL, 0x0); + if (rc) + return rc; + + rc = __write_register(core, CPU_CS_AHB_BRIDGE_SYNC_RESET, VCODEC1_BRIDGE_SW_RESET | + VCODEC1_BRIDGE_HW_RESET_DISABLE); + if (rc) + return rc; + + rc = __write_register(core, CPU_CS_AHB_BRIDGE_SYNC_RESET, VCODEC1_BRIDGE_HW_RESET_DISABLE); + if (rc) + return rc; + + rc = __write_register(core, CPU_CS_AHB_BRIDGE_SYNC_RESET, 0x0); + if (rc) + return rc; + +disable_power: + call_res_op(core, reset_control_assert, core, "vcodec1_bus"); + call_res_op(core, reset_control_assert, core, "vcodec1_core"); + usleep_range(400, 500); + call_res_op(core, reset_control_deassert, core, "vcodec1_bus"); + call_res_op(core, reset_control_deassert, core, "vcodec1_core"); + + call_res_op(core, clk_disable, core, "vcodec1_core"); + call_res_op(core, clk_disable, core, "vcodec1_core_freerun"); + call_res_op(core, clk_disable, core, "vcodec1_iface"); + call_res_op(core, gdsc_off, core, "vcodec1"); + + return 0; +} + +static int __power_on_glymur_hardware(struct msm_vidc_core *core) +{ + int rc; + + rc = __power_on_glymur_vcodec0(core); + if (rc) { + d_vpr_e("%s: failed to power on vcodec0\n", __func__); + return rc; + } + + rc = __power_on_glymur_vcodec1(core); + if (rc) { + d_vpr_e("%s: failed to power on vcodec1\n", __func__); + goto fail_power_on_vcodec1; + } + + return 0; + +fail_power_on_vcodec1: + __power_off_glymur_vcodec0(core); + + return rc; +} + +static int __power_off_glymur_hardware(struct msm_vidc_core *core) +{ + int vcodec0_rc, vcodec1_rc; + + vcodec0_rc = __power_off_glymur_vcodec0(core); + if (vcodec0_rc) + d_vpr_e("%s: failed to power off vcodec0\n", __func__); + + vcodec1_rc = __power_off_glymur_vcodec1(core); + if (vcodec1_rc) + d_vpr_e("%s: failed to power off vcodec1\n", __func__); + + return vcodec0_rc | vcodec1_rc; +} + +static int __power_on_glymur(struct msm_vidc_core *core) +{ + int rc; + + if (is_core_sub_state(core, CORE_SUBSTATE_POWER_ENABLE)) + return 0; + + if (!core_in_valid_state(core)) { + d_vpr_e("%s: invalid core state %s\n", __func__, core_state_name(core->state)); + return -EINVAL; + } + + rc = call_res_op(core, set_bw, core, INT_MAX, INT_MAX); + if (rc) { + d_vpr_e("%s: failed to vote buses, rc %d\n", __func__, rc); + return rc; + } + + rc = __power_on_glymur_controller(core); + if (rc) { + d_vpr_e("%s: failed to power on glymur controller\n", __func__); + goto fail_power_on_controller; + } + + rc = __power_on_glymur_hardware(core); + if (rc) { + d_vpr_e("%s: failed to power on glymur hardware\n", __func__); + goto fail_power_on_hardware; + } + + rc = msm_vidc_change_core_sub_state(core, 0, CORE_SUBSTATE_POWER_ENABLE, __func__); + if (rc) + goto fail_power_on_substate; + + rc = call_res_op(core, set_clks, core, get_min_clock_index(core)); + if (rc) { + d_vpr_e("%s: failed to scale clocks\n", __func__); + goto fail_set_clks; + } + + rc = call_res_op(core, gdsc_sw_ctrl, core); + if (rc) + goto fail_set_clks; + + __set_registers(core); + __interrupt_init_iris36(core); + core->intr_status = 0; + enable_irq(core->resource->irq); + + return rc; + +fail_set_clks: + msm_vidc_change_core_sub_state(core, CORE_SUBSTATE_POWER_ENABLE, 0, __func__); +fail_power_on_substate: + __power_off_glymur_hardware(core); +fail_power_on_hardware: + __power_off_glymur_controller(core); +fail_power_on_controller: + call_res_op(core, set_bw, core, 0, 0); + + return rc; +} + +static int __power_off_glymur(struct msm_vidc_core *core) +{ + int rc; + + if (!is_core_sub_state(core, CORE_SUBSTATE_POWER_ENABLE)) + return 0; + + rc = call_res_op(core, set_clks, core, get_min_clock_index(core)); + if (rc) + d_vpr_e("%s: resetting clocks failed\n", __func__); + + rc = call_res_op(core, gdsc_sw_ctrl, core); + if (rc) + d_vpr_e("%s: gdsc sw ctrl failed\n", __func__); + + rc = __power_off_glymur_hardware(core); + if (rc) + d_vpr_e("%s: power off hardware failed\n", __func__); + + rc = __power_off_glymur_controller(core); + if (rc) + d_vpr_e("%s: power off controller failed\n", __func__); + + rc = call_res_op(core, set_bw, core, 0, 0); + if (rc) + d_vpr_e("%s: failed to unvote buses\n", __func__); + + if (!call_venus_op(core, watchdog, core, core->intr_status)) + disable_irq_nosync(core->resource->irq); + + msm_vidc_change_core_sub_state(core, CORE_SUBSTATE_POWER_ENABLE, 0, __func__); + + return rc; +} + +static struct msm_vidc_venus_ops iris36_glymur_ops = { + .boot_firmware = __boot_firmware_iris36, + .raise_interrupt = __raise_interrupt_iris36, + .clear_interrupt = __clear_interrupt_iris36, + .power_on = __power_on_glymur, + .power_off = __power_off_glymur, + .prepare_pc = __prepare_pc_iris36, + .watchdog = __watchdog_iris36, + .noc_error_info = __noc_error_info_iris36, + .hw_ctrl_gdsc = __hw_ctrl_gdsc_iris36, + .sw_ctrl_gdsc = __sw_ctrl_gdsc_iris36, + .scm_mem_protect = msm_vidc_mem_protect_video_regions_v2, + .enable_intr = __enable_intr_iris36, +}; + +static struct msm_vidc_session_ops msm_session_glymur_ops = { + .buffer_size = msm_buffer_size_iris36, + .min_count = msm_buffer_min_count_iris36, + .extra_count = msm_buffer_extra_count_iris36, + .ring_buf_count = msm_vidc_ring_buf_count_iris36, + .scale_clocks = msm_vidc_scale_clocks_iris36, + .calc_bw = msm_vidc_calc_bw_iris36, + .decide_work_route = msm_vidc_decide_work_route_iris36, + .decide_work_mode = msm_vidc_decide_work_mode_iris36, + .decide_quality_mode = msm_vidc_decide_quality_mode_iris36, + .decide_slice_max_mb = msm_vidc_encoder_decide_slice_max_mb_iris36, +}; + +int msm_vidc_init_glymur_iris36(struct msm_vidc_core *core) +{ + core->venus_ops = &iris36_glymur_ops; + core->session_ops = &msm_session_glymur_ops; + + return 0; +} From 32530445cfa45cf99a9d0d107e42775eafe9e933 Mon Sep 17 00:00:00 2001 From: Vishnu Reddy Date: Wed, 1 Jul 2026 18:02:08 +0530 Subject: [PATCH 03/10] iris: select clock corner based on peak load across vcodec cores Glymur platform has two video codec cores: vcodec0 and vcodec1. Both cores share a common clock source (video_cc_mvs0_clk_src) and the same power rails. The clock dividers between the source and the branch clocks are fixed. So when both cores are running, the source clock always runs at the highest frequency requested by either core. Since both cores share the same power rails, the power corner cannot be voted independently. Scaling one core's power corner up or down would directly affect the other, leading to under or over-voting. For these reasons, both cores should voted the clock and power rail must be based on the workload of both cores. Signed-off-by: Vishnu Reddy --- .../iris36/inc/msm_vidc_power_iris36.h | 2 + .../iris36/src/msm_vidc_power_iris36.c | 122 ++++++++++++++++++ 2 files changed, 124 insertions(+) diff --git a/driver/variant/iris36/inc/msm_vidc_power_iris36.h b/driver/variant/iris36/inc/msm_vidc_power_iris36.h index 44557d162..e1b06dc88 100644 --- a/driver/variant/iris36/inc/msm_vidc_power_iris36.h +++ b/driver/variant/iris36/inc/msm_vidc_power_iris36.h @@ -21,4 +21,6 @@ int msm_vidc_calculate_frequency_iris36(struct api_calculation_input codec_input struct api_calculation_freq_output *codec_output); int msm_vidc_calculate_bandwidth_iris36(struct api_calculation_input codec_input, struct api_calculation_bw_output *codec_output); +int msm_vidc_scale_clocks_iris36(struct msm_vidc_inst *inst); + #endif diff --git a/driver/variant/iris36/src/msm_vidc_power_iris36.c b/driver/variant/iris36/src/msm_vidc_power_iris36.c index f8f516d30..ff646de8f 100644 --- a/driver/variant/iris36/src/msm_vidc_power_iris36.c +++ b/driver/variant/iris36/src/msm_vidc_power_iris36.c @@ -1381,3 +1381,125 @@ int msm_vidc_ring_buf_count_iris36(struct msm_vidc_inst *inst, u32 data_size) } return 0; } + +static int get_clock_corner_index(struct msm_vidc_core *core, u64 freq) +{ + struct clock_info *cl; + int idx = INT_MAX; + u64 rate; + + if (!freq) + return idx; + + venus_hfi_for_each_clock(core, cl) { + /* + * keep checking from lowest to highest rate until + * table rate >= requested rate + */ + if (cl->has_scaling && (!strcmp(cl->name, "video_cc_mvs0_clk_src") || + !strcmp(cl->name, "vcodec0_core") || + !strcmp(cl->name, "vcodec1_core"))) { + for (idx = cl->freq_count - 1; idx > 0; idx--) { + rate = cl->freq[idx]; + if (rate >= freq) + break; + } + } + } + + return idx; +} + +static int msm_vidc_get_freq_corner(struct msm_vidc_inst *inst) +{ + bool increment = false, decrement = true; + u64 vcodec0_freq = 0, vcodec1_freq = 0; + struct msm_vidc_core *core; + struct msm_vidc_inst *temp; + u64 freq; + int idx; + + core = inst->core; + + mutex_lock(&core->lock); + list_for_each_entry(temp, &core->instances, list) { + /* skip for session where no input is there to process */ + if (!temp->max_input_data_size) + continue; + + /* skip inactive session clock rate */ + if (!temp->active) + continue; + + if (temp->core_id == MSM_VIDC_VCODEC1) + vcodec1_freq += temp->power.min_freq; + else + vcodec0_freq += temp->power.min_freq; + + if (msm_vidc_clock_voting) { + d_vpr_l("msm_vidc_clock_voting %d\n", msm_vidc_clock_voting); + vcodec0_freq = msm_vidc_clock_voting; + vcodec1_freq = msm_vidc_clock_voting; + decrement = false; + break; + } + + /* increment even if one session requested for it */ + if (temp->power.dcvs_flags & MSM_VIDC_DCVS_INCR) + increment = true; + /* decrement only if all sessions requested for it */ + if (!(temp->power.dcvs_flags & MSM_VIDC_DCVS_DECR)) + decrement = false; + } + mutex_unlock(&core->lock); + + freq = max(vcodec0_freq, vcodec1_freq); + idx = get_clock_corner_index(core, freq); + if (increment) { + if (idx > get_max_clock_index(core)) + idx -= 1; + } else if (decrement) { + if (idx < get_min_clock_index(core)) + idx += 1; + } + + i_vpr_p(inst, "%s: requested rate: core %llu, increment %d decrement %d\n", + __func__, freq, increment, decrement); + + core->power.clk_freq_idx = idx; + + return idx; +} + +int msm_vidc_scale_clocks_iris36(struct msm_vidc_inst *inst) +{ + struct vidc_clock_scaling_data *clock_data; + struct msm_vidc_core *core; + + core = inst->core; + clock_data = &inst->clock_data; + + if (inst->power.buffer_counter < DCVS_WINDOW || + is_image_session(inst) || + is_sub_state(inst, MSM_VIDC_DRC) || + is_sub_state(inst, MSM_VIDC_DRAIN)) { + inst->power.min_freq = + max3(get_clock_freq(core, "video_cc_mvs0_clk_src", + get_max_clock_index(core)), + get_clock_freq(core, "vcodec0_core", get_max_clock_index(core)), + get_clock_freq(core, "vcodec1_core", get_max_clock_index(core))); + inst->power.dcvs_flags = 0; + } else if (msm_vidc_clock_voting || + (msm_vidc_vpp_clock_voting && msm_vidc_apv_clock_voting && + msm_vidc_bse_clock_voting && msm_vidc_tensilica_clock_voting)) { + inst->power.min_freq = msm_vidc_clock_voting; + inst->power.dcvs_flags = 0; + } else { + clock_data->freq = msm_vidc_calc_freq_iris36(inst, inst->max_input_data_size); + clock_data->data_size = inst->max_input_data_size; + inst->power.min_freq = clock_data->freq; + msm_vidc_apply_dcvs(inst); + } + + return msm_vidc_get_freq_corner(inst); +} From 8aa3ddf4879a5d6aeee90cedd0607f2bf1bf2324 Mon Sep 17 00:00:00 2001 From: Vishnu Reddy Date: Wed, 1 Jul 2026 18:02:08 +0530 Subject: [PATCH 04/10] iris: add firmware memory region to video memory protection Glymur requires the firmware memory region IOVA to be passed to qcom_scm_mem_protect_video_var function along with other video memory regions so it can set the correct access permissions for the firmware memory during video firmware initialization. Signed-off-by: Vishnu Reddy --- driver/variant/common/src/msm_vidc_variant.c | 2 ++ driver/vidc/inc/msm_vidc_internal.h | 3 ++- driver/vidc/src/msm_vidc_probe.c | 3 ++- 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/driver/variant/common/src/msm_vidc_variant.c b/driver/variant/common/src/msm_vidc_variant.c index 026de70a0..5abe68614 100644 --- a/driver/variant/common/src/msm_vidc_variant.c +++ b/driver/variant/common/src/msm_vidc_variant.c @@ -231,6 +231,8 @@ int msm_vidc_mem_protect_video_regions_v2(struct msm_vidc_core *core) region = VIDEO_REGION_VM0_NONSECURE_NP_ID; else if (cb->region & MSM_VIDC_SECURE_NONPIXEL) region = VIDEO_REGION_VM0_SECURE_NP_ID; + else if (cb->region & MSM_VIDC_SECURE_FIRMWARE) + region = VIDEO_REGION_SECURE_FW_REGION_ID; else continue; diff --git a/driver/vidc/inc/msm_vidc_internal.h b/driver/vidc/inc/msm_vidc_internal.h index eaab0749a..154e70807 100644 --- a/driver/vidc/inc/msm_vidc_internal.h +++ b/driver/vidc/inc/msm_vidc_internal.h @@ -563,7 +563,8 @@ enum msm_vidc_buffer_region { MSM_VIDC_SECURE_NONPIXEL = BIT(4), MSM_VIDC_SECURE_BITSTREAM = BIT(5), MSM_VIDC_SECURE_PIXEL = BIT(6), - MSM_VIDC_REGION_MAX = BIT(7), + MSM_VIDC_SECURE_FIRMWARE = BIT(7), + MSM_VIDC_REGION_MAX = BIT(8), }; enum msm_vidc_device_region FOREACH_DEVICE_REGION(GENERATE_MSM_VIDC_ENUM); diff --git a/driver/vidc/src/msm_vidc_probe.c b/driver/vidc/src/msm_vidc_probe.c index 97efba1e2..e7c825082 100644 --- a/driver/vidc/src/msm_vidc_probe.c +++ b/driver/vidc/src/msm_vidc_probe.c @@ -80,7 +80,8 @@ static inline bool is_video_context_bank_device_node(struct device_node *of_node of_device_is_compatible(of_node, "qcom,vidc,cb-sec-non-pxl") || of_device_is_compatible(of_node, "qcom,vidc,cb-ns") || of_device_is_compatible(of_node, "qcom,vidc,cb-ns-bitstream") || - of_device_is_compatible(of_node, "qcom,vidc,cb-ns-pxl")); + of_device_is_compatible(of_node, "qcom,vidc,cb-ns-pxl") || + of_device_is_compatible(of_node, "qcom,vidc,cb-firmware")); } static inline bool is_video_context_bank_device(struct device *dev) From 7d32a07290f2e73b93ad1a042e5a658f897443c3 Mon Sep 17 00:00:00 2001 From: Vishnu Reddy Date: Wed, 1 Jul 2026 18:02:08 +0530 Subject: [PATCH 05/10] iris: enable probe support for qcom,glymur-iris Register the "qcom,glymur-iris" compatible string so that driver can match and initialize glymur devices during probe. Signed-off-by: Vishnu Reddy --- driver/platform/common/src/msm_vidc_platform.c | 8 ++++++++ driver/vidc/src/msm_vidc_probe.c | 4 +++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/driver/platform/common/src/msm_vidc_platform.c b/driver/platform/common/src/msm_vidc_platform.c index 52203d1c7..9e4c64b46 100644 --- a/driver/platform/common/src/msm_vidc_platform.c +++ b/driver/platform/common/src/msm_vidc_platform.c @@ -74,6 +74,8 @@ #include "msm_vidc_purwa.h" #include "msm_vidc_iris3.h" #include "msm_vidc_iris2.h" +#include "msm_vidc_glymur.h" +#include "msm_vidc_iris36.h" #endif #define CAP_TO_8BIT_QP(a) { \ @@ -208,6 +210,12 @@ static const struct msm_vidc_compat_handle compat_handle[] = { .init_platform = msm_vidc_init_platform_purwa, .init_iris = msm_vidc_init_iris3, }, + { + .compat = "qcom,glymur-iris", + .get_platform_data = msm_vidc_get_platform_data_glymur, + .init_platform = msm_vidc_init_platform_glymur, + .init_iris = msm_vidc_init_glymur_iris36, + }, #endif #if defined(CONFIG_MSM_VIDC_LEMANS) { diff --git a/driver/vidc/src/msm_vidc_probe.c b/driver/vidc/src/msm_vidc_probe.c index e7c825082..dd8bad23f 100644 --- a/driver/vidc/src/msm_vidc_probe.c +++ b/driver/vidc/src/msm_vidc_probe.c @@ -70,7 +70,8 @@ static inline bool is_video_device(struct device *dev) of_device_is_compatible(dev->of_node, "qcom,sa8775p-iris") || of_device_is_compatible(dev->of_node, "qcom,qcs8300-iris") || of_device_is_compatible(dev->of_node, "qcom,sc7280-venus") || - of_device_is_compatible(dev->of_node, "qcom,chora-vidc")); + of_device_is_compatible(dev->of_node, "qcom,chora-vidc") || + of_device_is_compatible(dev->of_node, "qcom,glymur-iris")); } static inline bool is_video_context_bank_device_node(struct device_node *of_node) @@ -179,6 +180,7 @@ static const struct of_device_id msm_vidc_dt_match[] = { {.compatible = "qcom,sa8775p-iris"}, {.compatible = "qcom,qcs8300-iris"}, {.compatible = "qcom,sc7280-venus"}, + {.compatible = "qcom,glymur-iris"}, {.compatible = "qcom,vidc,cb-ns-pxl"}, {.compatible = "qcom,vidc,cb-ns"}, {.compatible = "qcom,vidc,cb-ns-bitstream"}, From 9c5fc6dd47b9fb1f856f06c40183b82d79382974 Mon Sep 17 00:00:00 2001 From: Vishnu Reddy Date: Wed, 1 Jul 2026 18:02:08 +0530 Subject: [PATCH 06/10] iris: add vendor platform data support for glymur Add the vendor specific platform configuration required by the video driver for glymur targets, including hardware capabilities, resource definitions, format mappings, and platform initialization hooks. Signed-off-by: Vishnu Reddy --- driver/platform/glymur/inc/msm_vidc_glymur.h | 41 + driver/platform/glymur/src/msm_vidc_glymur.c | 2936 ++++++++++++++++++ 2 files changed, 2977 insertions(+) create mode 100644 driver/platform/glymur/inc/msm_vidc_glymur.h create mode 100644 driver/platform/glymur/src/msm_vidc_glymur.c diff --git a/driver/platform/glymur/inc/msm_vidc_glymur.h b/driver/platform/glymur/inc/msm_vidc_glymur.h new file mode 100644 index 000000000..eae2e69fd --- /dev/null +++ b/driver/platform/glymur/inc/msm_vidc_glymur.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _MSM_VIDC_GLYMUR_H_ +#define _MSM_VIDC_GLYMUR_H_ + +struct msm_vidc_core; + +#if defined(CONFIG_MSM_VIDC_GLYMUR) || defined(CONFIG_MSM_VIDC_QLI) +int msm_vidc_get_platform_data_glymur(struct msm_vidc_core *core); +int msm_vidc_init_platform_glymur(struct msm_vidc_core *core); +int msm_vidc_adjust_ir_period_glymur(void *instance, struct v4l2_ctrl *ctrl); +int msm_vidc_set_ir_period_glymur(void *instance, + enum msm_vidc_inst_capability_type cap_id); +#else +static inline int msm_vidc_get_platform_data_glymur(struct msm_vidc_core *core) +{ + return -EINVAL; +} + +static inline int msm_vidc_init_platform_glymur(struct msm_vidc_core *core) +{ + return -EINVAL; +} + +static inline int msm_vidc_adjust_ir_period_glymur(void *instance, struct v4l2_ctrl *ctrl) +{ + return -EINVAL; +} + +static inline int msm_vidc_set_ir_period_glymur(void *instance, + enum msm_vidc_inst_capability_type cap_id) +{ + return -EINVAL; +} + +#endif + +#endif /* _MSM_VIDC_GLYMUR_H_ */ diff --git a/driver/platform/glymur/src/msm_vidc_glymur.c b/driver/platform/glymur/src/msm_vidc_glymur.c new file mode 100644 index 000000000..55af3bc81 --- /dev/null +++ b/driver/platform/glymur/src/msm_vidc_glymur.c @@ -0,0 +1,2936 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +#include +#include + +#include +#include "msm_vidc_glymur.h" +#include "msm_vidc_inst.h" +#include "msm_vidc_platform.h" +#include "msm_vidc_debug.h" +#include "msm_vidc_internal.h" +#include "msm_vidc_platform_ext.h" +#include "msm_vidc_memory_ext.h" +#include "resources_ext.h" +#include "msm_vidc_iris36.h" +#include "hfi_property.h" +#include "hfi_command.h" +#include "venus_hfi.h" + +/* version: major[24:31], minor[16:23], revision[0:15] */ +#define DRIVER_VERSION 0x04000000 +#define DEFAULT_VIDEO_CONCEAL_COLOR_BLACK 0x8000800010 +#define MAX_LTR_FRAME_COUNT 2 +#define MAX_BASE_LAYER_PRIORITY_ID 63 +#define MAX_OP_POINT 31 +#define MAX_BITRATE 245000000 +#define DEFAULT_BITRATE 20000000 +#define MINIMUM_FPS 1 +#define MAXIMUM_FPS 480 +#define MAXIMUM_DEC_FPS 960 +#define MAX_QP 51 +#define DEFAULT_QP 20 +#define MAX_CONSTANT_QUALITY 100 +#define MIN_SLICE_BYTE_SIZE 512 +#define MAX_SLICE_BYTE_SIZE \ + ((MAX_BITRATE) >> 3) +#define MAX_SLICE_MB_SIZE \ + (((4096 + 15) >> 4) * ((2304 + 15) >> 4)) + +#define ENC MSM_VIDC_ENCODER +#define DEC MSM_VIDC_DECODER +#define H264 MSM_VIDC_H264 +#define HEVC MSM_VIDC_HEVC +#define VP9 MSM_VIDC_VP9 +#define AV1 MSM_VIDC_AV1 +#define HEIC MSM_VIDC_HEIC +#define MPEG2 MSM_VIDC_MPEG2 +#define CODECS_ALL (H264 | HEVC | VP9 | HEIC | AV1 | MPEG2) +#define MAXIMUM_OVERRIDE_VP9_FPS 200 + +static struct codec_info codec_data_glymur[] = { + { + .v4l2_codec = V4L2_PIX_FMT_H264, + .vidc_codec = MSM_VIDC_H264, + .pixfmt_name = "AVC", + }, + { + .v4l2_codec = V4L2_PIX_FMT_HEVC, + .vidc_codec = MSM_VIDC_HEVC, + .pixfmt_name = "HEVC", + }, + { + .v4l2_codec = V4L2_PIX_FMT_VP9, + .vidc_codec = MSM_VIDC_VP9, + .pixfmt_name = "VP9", + }, + { + .v4l2_codec = V4L2_PIX_FMT_AV1, + .vidc_codec = MSM_VIDC_AV1, + .pixfmt_name = "AV1", + }, + { + .v4l2_codec = V4L2_PIX_FMT_VIDC_HEIC, + .vidc_codec = MSM_VIDC_HEIC, + .pixfmt_name = "HEIC", + }, + { + .v4l2_codec = V4L2_PIX_FMT_MPEG2, + .vidc_codec = MSM_VIDC_MPEG2, + .pixfmt_name = "MPEG2", + }, +}; + +static struct color_format_info color_format_data_glymur[] = { + { + .v4l2_color_format = V4L2_PIX_FMT_NV12, + .vidc_color_format = MSM_VIDC_FMT_NV12, + .pixfmt_name = "NV12", + }, + { + .v4l2_color_format = V4L2_PIX_FMT_NV21, + .vidc_color_format = MSM_VIDC_FMT_NV21, + .pixfmt_name = "NV21", + }, + { + .v4l2_color_format = V4L2_PIX_FMT_QC08C, + .vidc_color_format = MSM_VIDC_FMT_NV12C, + .pixfmt_name = "NV12C", + }, + { + .v4l2_color_format = V4L2_PIX_FMT_QC10C, + .vidc_color_format = MSM_VIDC_FMT_TP10C, + .pixfmt_name = "TP10C", + }, + { + .v4l2_color_format = V4L2_PIX_FMT_RGBA32, + .vidc_color_format = MSM_VIDC_FMT_RGBA8888, + .pixfmt_name = "RGBA", + }, + { + .v4l2_color_format = V4L2_PIX_FMT_P010, + .vidc_color_format = MSM_VIDC_FMT_P010, + .pixfmt_name = "P010", + }, + { + .v4l2_color_format = V4L2_META_FMT_VIDC, + .vidc_color_format = MSM_VIDC_FMT_META, + .pixfmt_name = "META", + }, +}; + +static struct color_primaries_info color_primaries_data_glymur[] = { + { + .v4l2_color_primaries = V4L2_COLORSPACE_DEFAULT, + .vidc_color_primaries = MSM_VIDC_PRIMARIES_RESERVED, + }, + { + .v4l2_color_primaries = V4L2_COLORSPACE_DEFAULT, + .vidc_color_primaries = MSM_VIDC_PRIMARIES_UNSPECIFIED, + }, + { + .v4l2_color_primaries = V4L2_COLORSPACE_REC709, + .vidc_color_primaries = MSM_VIDC_PRIMARIES_BT709, + }, + { + .v4l2_color_primaries = V4L2_COLORSPACE_470_SYSTEM_M, + .vidc_color_primaries = MSM_VIDC_PRIMARIES_BT470_SYSTEM_M, + }, + { + .v4l2_color_primaries = V4L2_COLORSPACE_470_SYSTEM_BG, + .vidc_color_primaries = MSM_VIDC_PRIMARIES_BT470_SYSTEM_BG, + }, + { + .v4l2_color_primaries = V4L2_COLORSPACE_SMPTE170M, + .vidc_color_primaries = MSM_VIDC_PRIMARIES_BT601_525, + }, + { + .v4l2_color_primaries = V4L2_COLORSPACE_SMPTE240M, + .vidc_color_primaries = MSM_VIDC_PRIMARIES_SMPTE_ST240M, + }, + { + .v4l2_color_primaries = V4L2_COLORSPACE_VIDC_GENERIC_FILM, + .vidc_color_primaries = MSM_VIDC_PRIMARIES_GENERIC_FILM, + }, + { + .v4l2_color_primaries = V4L2_COLORSPACE_BT2020, + .vidc_color_primaries = MSM_VIDC_PRIMARIES_BT2020, + }, + { + .v4l2_color_primaries = V4L2_COLORSPACE_DCI_P3, + .vidc_color_primaries = MSM_VIDC_PRIMARIES_SMPTE_RP431_2, + }, + { + .v4l2_color_primaries = V4L2_COLORSPACE_VIDC_EG431, + .vidc_color_primaries = MSM_VIDC_PRIMARIES_SMPTE_EG431_1, + }, + { + .v4l2_color_primaries = V4L2_COLORSPACE_VIDC_EBU_TECH, + .vidc_color_primaries = MSM_VIDC_PRIMARIES_SMPTE_EBU_TECH, + }, +}; + +static struct transfer_char_info transfer_char_data_glymur[] = { + { + .v4l2_transfer_char = V4L2_XFER_FUNC_DEFAULT, + .vidc_transfer_char = MSM_VIDC_TRANSFER_RESERVED, + }, + { + .v4l2_transfer_char = V4L2_XFER_FUNC_DEFAULT, + .vidc_transfer_char = MSM_VIDC_TRANSFER_UNSPECIFIED, + }, + { + .v4l2_transfer_char = V4L2_XFER_FUNC_709, + .vidc_transfer_char = MSM_VIDC_TRANSFER_BT709, + }, + { + .v4l2_transfer_char = V4L2_XFER_FUNC_VIDC_BT470_SYSTEM_M, + .vidc_transfer_char = MSM_VIDC_TRANSFER_BT470_SYSTEM_M, + }, + { + .v4l2_transfer_char = V4L2_XFER_FUNC_VIDC_BT470_SYSTEM_BG, + .vidc_transfer_char = MSM_VIDC_TRANSFER_BT470_SYSTEM_BG, + }, + { + .v4l2_transfer_char = V4L2_XFER_FUNC_VIDC_BT601_525_OR_625, + .vidc_transfer_char = MSM_VIDC_TRANSFER_BT601_525_OR_625, + }, + { + .v4l2_transfer_char = V4L2_XFER_FUNC_SMPTE240M, + .vidc_transfer_char = MSM_VIDC_TRANSFER_SMPTE_ST240M, + }, + { + .v4l2_transfer_char = V4L2_XFER_FUNC_VIDC_LINEAR, + .vidc_transfer_char = MSM_VIDC_TRANSFER_LINEAR, + }, + { + .v4l2_transfer_char = V4L2_XFER_FUNC_VIDC_XVYCC, + .vidc_transfer_char = MSM_VIDC_TRANSFER_XVYCC, + }, + { + .v4l2_transfer_char = V4L2_XFER_FUNC_VIDC_BT1361, + .vidc_transfer_char = MSM_VIDC_TRANSFER_BT1361_0, + }, + { + .v4l2_transfer_char = V4L2_XFER_FUNC_SRGB, + .vidc_transfer_char = MSM_VIDC_TRANSFER_SRGB_SYCC, + }, + { + .v4l2_transfer_char = V4L2_XFER_FUNC_VIDC_BT2020, + .vidc_transfer_char = MSM_VIDC_TRANSFER_BT2020_14, + }, + { + .v4l2_transfer_char = V4L2_XFER_FUNC_SMPTE2084, + .vidc_transfer_char = MSM_VIDC_TRANSFER_SMPTE_ST2084_PQ, + }, + { + .v4l2_transfer_char = V4L2_XFER_FUNC_VIDC_ST428, + .vidc_transfer_char = MSM_VIDC_TRANSFER_SMPTE_ST428_1, + }, + { + .v4l2_transfer_char = V4L2_XFER_FUNC_VIDC_HLG, + .vidc_transfer_char = MSM_VIDC_TRANSFER_BT2100_2_HLG, + }, +}; + +static struct matrix_coeff_info matrix_coeff_data_glymur[] = { + { + .v4l2_matrix_coeff = V4L2_YCBCR_ENC_DEFAULT, + .vidc_matrix_coeff = MSM_VIDC_MATRIX_COEFF_RESERVED, + }, + { + .v4l2_matrix_coeff = V4L2_YCBCR_ENC_DEFAULT, + .vidc_matrix_coeff = MSM_VIDC_MATRIX_COEFF_UNSPECIFIED, + }, + { + .v4l2_matrix_coeff = V4L2_YCBCR_VIDC_SRGB_OR_SMPTE_ST428, + .vidc_matrix_coeff = MSM_VIDC_MATRIX_COEFF_SRGB_SMPTE_ST428_1, + }, + { + .v4l2_matrix_coeff = V4L2_YCBCR_ENC_709, + .vidc_matrix_coeff = MSM_VIDC_MATRIX_COEFF_BT709, + }, + { + .v4l2_matrix_coeff = V4L2_YCBCR_ENC_XV709, + .vidc_matrix_coeff = MSM_VIDC_MATRIX_COEFF_BT709, + }, + { + .v4l2_matrix_coeff = V4L2_YCBCR_VIDC_FCC47_73_682, + .vidc_matrix_coeff = MSM_VIDC_MATRIX_COEFF_FCC_TITLE_47, + }, + { + .v4l2_matrix_coeff = V4L2_YCBCR_ENC_XV601, + .vidc_matrix_coeff = MSM_VIDC_MATRIX_COEFF_BT470_SYS_BG_OR_BT601_625, + }, + { + .v4l2_matrix_coeff = V4L2_YCBCR_ENC_601, + .vidc_matrix_coeff = MSM_VIDC_MATRIX_COEFF_BT601_525_BT1358_525_OR_625, + }, + { + .v4l2_matrix_coeff = V4L2_YCBCR_ENC_SMPTE240M, + .vidc_matrix_coeff = MSM_VIDC_MATRIX_COEFF_SMPTE_ST240, + }, + { + .v4l2_matrix_coeff = V4L2_YCBCR_ENC_BT2020, + .vidc_matrix_coeff = MSM_VIDC_MATRIX_COEFF_BT2020_NON_CONSTANT, + }, + { + .v4l2_matrix_coeff = V4L2_YCBCR_ENC_BT2020_CONST_LUM, + .vidc_matrix_coeff = MSM_VIDC_MATRIX_COEFF_BT2020_CONSTANT, + }, +}; + +static const struct msm_platform_core_capability core_data_glymur[] = { + /* {type, value} */ + {ENC_CODECS, H264 | HEVC | HEIC}, + {DEC_CODECS, H264 | HEVC | VP9 | AV1 | HEIC | MPEG2}, + {MAX_SESSION_COUNT, 32}, + {MAX_NUM_720P_SESSIONS, 32}, + {MAX_NUM_1080P_SESSIONS, 32}, + {MAX_NUM_4K_SESSIONS, 6}, + {MAX_NUM_8K_SESSIONS, 2}, + {MAX_SECURE_SESSION_COUNT, 3}, + {MAX_RT_MBPF, 174080}, /* (8192x4352)/256 + (4096x2176)/256*/ + {MAX_MBPF, 278528}, /* ((8192x4352)/256) * 2 */ + {MAX_MBPS, 7833600}, + /* max_load + * 7680x4320@60fps or 3840x2176@240fps + * which is greater than 4096x2176@120fps, + * 8192x4320@48fps + */ + {MAX_IMAGE_MBPF, 1048576}, /* (16384x16384)/256 */ + {MAX_MBPF_HQ, 8160}, /* ((1920x1088)/256) */ + {MAX_MBPS_HQ, 489600}, /* ((1920x1088)/256)@60fps */ + {MAX_MBPF_B_FRAME, 32640}, /* 3840x2176/256 */ + {MAX_MBPS_B_FRAME, 1958400}, /* 3840x2176/256 MBs@60fps */ + {MAX_MBPS_ALL_INTRA, 2088960}, /* 4096x2176/256 MBs@60fps */ + {MAX_ENH_LAYER_COUNT, 5}, + {NUM_VPP_PIPE, 4}, + {SW_PC, 1}, + {FW_UNLOAD, 0}, + {HW_RESPONSE_TIMEOUT, HW_RESPONSE_TIMEOUT_VALUE}, /* 1000 ms */ + {SW_PC_DELAY, SW_PC_DELAY_VALUE }, /* 1500 ms (>HW_RESPONSE_TIMEOUT)*/ + {FW_UNLOAD_DELAY, FW_UNLOAD_DELAY_VALUE }, /* 3000 ms (>SW_PC_DELAY)*/ + {PAGEFAULT_NON_FATAL, 1}, + {PAGETABLE_CACHING, 0}, + {DCVS, 1}, + {DECODE_BATCH, 1}, + {DECODE_BATCH_TIMEOUT, 200}, + {STATS_TIMEOUT_MS, 2000}, + {AV_SYNC_WINDOW_SIZE, 40}, + {NON_FATAL_FAULTS, 1}, + {ENC_AUTO_FRAMERATE, 1}, + {DEVICE_CAPS, V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_META_CAPTURE | V4L2_CAP_STREAMING}, + {SUPPORTS_REQUESTS, 0}, +}; + +static struct msm_platform_inst_capability instance_cap_data_glymur[] = { + /* {cap, domain, codec, + * min, max, step_or_mask, value, + * v4l2_id, + * hfi_id, + * flags} + */ + {DRV_VERSION, DEC | ENC, CODECS_ALL, + 0, INT_MAX, 1, DRIVER_VERSION, + V4L2_CID_MPEG_VIDC_DRIVER_VERSION}, + + {FRAME_WIDTH, DEC, CODECS_ALL, 96, 8192, 1, 1920}, + + {FRAME_WIDTH, DEC, VP9, 96, 4096, 1, 1920}, + + {FRAME_WIDTH, DEC, MPEG2, 96, 1920, 1, 1920}, + + {FRAME_WIDTH, ENC, CODECS_ALL, 128, 8192, 1, 1920}, + + {FRAME_WIDTH, ENC, HEVC, 96, 8192, 1, 1920}, + + {FRAME_WIDTH, ENC, HEIC, 128, 16384, 1, 16384}, + + {LOSSLESS_FRAME_WIDTH, ENC, CODECS_ALL, 128, 4096, 1, 1920}, + + {LOSSLESS_FRAME_WIDTH, ENC, HEVC, 96, 4096, 1, 1920}, + + {SECURE_FRAME_WIDTH, DEC, CODECS_ALL, 96, 4096, 1, 1920}, + + {SECURE_FRAME_WIDTH, ENC, CODECS_ALL, 128, 4096, 1, 1920}, + + {SECURE_FRAME_WIDTH, ENC, HEVC, 96, 4096, 1, 1920}, + + {FRAME_HEIGHT, DEC, CODECS_ALL, 96, 8192, 1, 1080}, + + {FRAME_HEIGHT, DEC, VP9, 96, 4096, 1, 1080}, + + {FRAME_HEIGHT, DEC, MPEG2, 96, 1920, 1, 1080}, + + {FRAME_HEIGHT, ENC, CODECS_ALL, 128, 8192, 1, 1080}, + + {FRAME_HEIGHT, ENC, HEVC, 96, 8192, 1, 1080}, + + {FRAME_HEIGHT, ENC, HEIC, 128, 16384, 1, 16384}, + + {LOSSLESS_FRAME_HEIGHT, ENC, CODECS_ALL, 128, 4096, 1, 1080}, + + {LOSSLESS_FRAME_HEIGHT, ENC, HEVC, 96, 4096, 1, 1080}, + + {SECURE_FRAME_HEIGHT, DEC, CODECS_ALL, 96, 4096, 1, 1080}, + + {SECURE_FRAME_HEIGHT, ENC, CODECS_ALL, 128, 4096, 1, 1080}, + + {SECURE_FRAME_HEIGHT, ENC, HEVC, 96, 4096, 1, 1080}, + + {PIX_FMTS, ENC | DEC, H264 | MPEG2, + MSM_VIDC_FMT_NV12, + MSM_VIDC_FMT_NV12C, + MSM_VIDC_FMT_NV12 | MSM_VIDC_FMT_NV21 | MSM_VIDC_FMT_NV12C, + MSM_VIDC_FMT_NV12C}, + + {PIX_FMTS, ENC | DEC, HEVC | VP9 | AV1, + MSM_VIDC_FMT_NV12, + MSM_VIDC_FMT_TP10C, + MSM_VIDC_FMT_NV12 | MSM_VIDC_FMT_NV21 | MSM_VIDC_FMT_NV12C | + MSM_VIDC_FMT_P010 | MSM_VIDC_FMT_TP10C, + MSM_VIDC_FMT_NV12C}, + + {PIX_FMTS, ENC, HEIC, + MSM_VIDC_FMT_NV12, + MSM_VIDC_FMT_P010, + MSM_VIDC_FMT_NV12 | MSM_VIDC_FMT_NV21 | MSM_VIDC_FMT_P010, + MSM_VIDC_FMT_NV12}, + + {PIX_FMTS, DEC, HEIC, + MSM_VIDC_FMT_NV12, + MSM_VIDC_FMT_TP10C, + MSM_VIDC_FMT_NV12 | MSM_VIDC_FMT_NV21 | MSM_VIDC_FMT_NV12C | + MSM_VIDC_FMT_P010 | MSM_VIDC_FMT_TP10C, + MSM_VIDC_FMT_NV12C}, + + {MIN_BUFFERS_INPUT, ENC | DEC, CODECS_ALL, 0, 64, 1, 4, + V4L2_CID_MIN_BUFFERS_FOR_OUTPUT, + 0, + CAP_FLAG_VOLATILE}, + + {MIN_BUFFERS_INPUT, ENC | DEC, HEIC, 0, 64, 1, 1, + V4L2_CID_MIN_BUFFERS_FOR_OUTPUT, + 0, + CAP_FLAG_VOLATILE}, + + {MIN_BUFFERS_OUTPUT, ENC | DEC, CODECS_ALL, + 0, 64, 1, 4, + V4L2_CID_MIN_BUFFERS_FOR_CAPTURE, + HFI_PROP_BUFFER_FW_MIN_OUTPUT_COUNT, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_VOLATILE}, + + /* (8192 * 4320) / 256 */ + {MBPF, ENC, CODECS_ALL, 64, 138240, 1, 138240}, + + {MBPF, ENC, HEVC, 36, 138240, 1, 138240}, + + /* ((16384x16384)/256) */ + {MBPF, ENC, HEIC, 36, 1048576, 1, 1048576}, + + {MBPF, DEC, CODECS_ALL, 36, 138240, 1, 138240}, + + /* (4096 * 2304) / 256 */ + {MBPF, DEC, VP9, 36, 36864, 1, 36864}, + + /* ((8192x8192)/256) */ + {MBPF, DEC, HEIC, 64, 262144, 1, 262144 }, + + /* (4096 * 2304) / 256 */ + {LOSSLESS_MBPF, ENC, H264 | HEVC, 64, 36864, 1, 36864}, + + /* Batch Mode Decode */ + /* TODO: update with new values based on updated voltage corner */ + {BATCH_MBPF, DEC, H264 | HEVC | VP9 | AV1, 64, 34816, 1, 34816}, + + /* (4096 * 2304) / 256 */ + {BATCH_FPS, DEC, H264 | HEVC | VP9 | AV1, 1, 120, 1, 120}, + + {SECURE_MBPF, ENC | DEC, H264 | HEVC | VP9 | AV1, 64, 36864, 1, 36864}, + + {SECURE_MBPF, ENC, HEVC, 36, 36864, 1, 36864}, + + {FRAME_RATE, ENC, CODECS_ALL, + (MINIMUM_FPS << 16), (MAXIMUM_FPS << 16), + 1, (DEFAULT_FPS << 16), + 0, + HFI_PROP_FRAME_RATE, + CAP_FLAG_OUTPUT_PORT}, + + {FRAME_RATE, ENC, HEIC, + (MINIMUM_FPS << 16), (MAXIMUM_FPS << 16), + 1, (MINIMUM_FPS << 16), + 0, + HFI_PROP_FRAME_RATE, + CAP_FLAG_OUTPUT_PORT}, + + {FRAME_RATE, DEC, CODECS_ALL, + (MINIMUM_FPS << 16), (MAXIMUM_DEC_FPS << 16), + 1, (DEFAULT_FPS << 16), + V4L2_CID_MPEG_VIDC_FRAME_RATE, + 0, + CAP_FLAG_OUTPUT_PORT | + CAP_FLAG_INPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED}, + + {FRAME_RATE, DEC, VP9, + (MINIMUM_FPS << 16), (MAXIMUM_OVERRIDE_VP9_FPS << 16), + 1, (DEFAULT_FPS << 16), + V4L2_CID_MPEG_VIDC_FRAME_RATE, + 0, + CAP_FLAG_OUTPUT_PORT | + CAP_FLAG_INPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED}, + + {OPERATING_RATE, ENC, CODECS_ALL, + (MINIMUM_FPS << 16), INT_MAX, + 1, (DEFAULT_FPS << 16)}, + + {OPERATING_RATE, DEC, CODECS_ALL, + (MINIMUM_FPS << 16), INT_MAX, + 1, (DEFAULT_FPS << 16), + V4L2_CID_MPEG_VIDC_OPERATING_RATE, + 0, + CAP_FLAG_OUTPUT_PORT | + CAP_FLAG_INPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED}, + + {INPUT_RATE, ENC | DEC, CODECS_ALL, + (MINIMUM_FPS << 16), INT_MAX, + 1, (DEFAULT_FPS << 16)}, + + {TIMESTAMP_RATE, ENC | DEC, CODECS_ALL, + (MINIMUM_FPS << 16), INT_MAX, + 1, (DEFAULT_FPS << 16)}, + + {SCALE_FACTOR, ENC, H264 | HEVC, 1, 8, 1, 8}, + + {MB_CYCLES_VSP, ENC, CODECS_ALL, 25, 25, 1, 25}, + + {MB_CYCLES_VSP, DEC, CODECS_ALL, 25, 25, 1, 25}, + + {MB_CYCLES_VSP, DEC, VP9 | AV1, 60, 60, 1, 60}, + + {MB_CYCLES_VPP, ENC, CODECS_ALL, 675, 675, 1, 675}, + + {MB_CYCLES_VPP, DEC, CODECS_ALL, 200, 200, 1, 200}, + + {MB_CYCLES_LP, ENC, CODECS_ALL, 320, 320, 1, 320}, + + {MB_CYCLES_LP, DEC, CODECS_ALL, 200, 200, 1, 200}, + + {MB_CYCLES_FW, ENC | DEC, CODECS_ALL, 489583, 489583, 1, 489583}, + + {MB_CYCLES_FW_VPP, ENC, CODECS_ALL, 48405, 48405, 1, 48405}, + + {MB_CYCLES_FW_VPP, DEC, CODECS_ALL, 66234, 66234, 1, 66234}, + + {CLIENT_ID, ENC | DEC, CODECS_ALL, + INVALID_CLIENT_ID, INT_MAX, 1, INVALID_CLIENT_ID, + V4L2_CID_MPEG_VIDC_CLIENT_ID}, + + {SECURE_MODE, ENC | DEC, H264 | HEVC | VP9 | AV1, + 0, 1, 1, 0, + V4L2_CID_MPEG_VIDC_SECURE, + HFI_PROP_SECURE, + CAP_FLAG_NONE}, + + /* + * Client will enable V4L2_CID_MPEG_VIDC_METADATA_OUTPUT_TX_FENCE + * to get output fence_id in input metadata buffer done. + */ + {META_OUTPUT_TX_FENCE, DEC, H264 | HEVC | VP9 | AV1 | MPEG2, + MSM_VIDC_META_DISABLE, + MSM_VIDC_META_ENABLE | MSM_VIDC_META_RX_INPUT, + 0, MSM_VIDC_META_DISABLE, + V4L2_CID_MPEG_VIDC_METADATA_OUTPUT_TX_FENCE, + HFI_PROP_FENCE, + CAP_FLAG_BITMASK | CAP_FLAG_META}, + + /* + * Client to do set_ctrl with FENCE_ID to set fence_id + * and then client will do get_ctrl with FENCE_FD to get + * fence_fd corresponding to client set fence_id. + */ + {FENCE_ID, DEC, CODECS_ALL, + 0, INT_MAX, 1, 0, + V4L2_CID_MPEG_VIDC_SW_FENCE_ID, + 0, + CAP_FLAG_DYNAMIC_ALLOWED | CAP_FLAG_OUTPUT_PORT}, + + {FENCE_FD, DEC, CODECS_ALL, + INVALID_FD, INT_MAX, 1, INVALID_FD, + V4L2_CID_MPEG_VIDC_SW_FENCE_FD, + 0, + CAP_FLAG_VOLATILE}, + + {TS_REORDER, DEC, H264 | HEVC, + 0, 1, 1, 0, + V4L2_CID_MPEG_VIDC_TS_REORDER}, + + {HFLIP, ENC, CODECS_ALL, + 0, 1, 1, 0, + V4L2_CID_HFLIP, + HFI_PROP_FLIP, + CAP_FLAG_OUTPUT_PORT | + CAP_FLAG_INPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED}, + + {VFLIP, ENC, CODECS_ALL, + 0, 1, 1, 0, + V4L2_CID_VFLIP, + HFI_PROP_FLIP, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {ROTATION, ENC, CODECS_ALL, + 0, 270, 90, 0, + V4L2_CID_ROTATE, + HFI_PROP_ROTATION, + CAP_FLAG_OUTPUT_PORT}, + + {SUPER_FRAME, ENC, H264 | HEVC, + 0, 32, 1, 0, + V4L2_CID_MPEG_VIDC_SUPERFRAME, 0, + CAP_FLAG_NONE}, + + {HEADER_MODE, ENC, CODECS_ALL, + V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE, + V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME, + BIT(V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) | + BIT(V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME), + V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE, + V4L2_CID_MPEG_VIDEO_HEADER_MODE, + HFI_PROP_SEQ_HEADER_MODE, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {PREPEND_SPSPPS_TO_IDR, ENC, CODECS_ALL, + 0, 1, 1, 0, + V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR}, + + {VUI_TIMING_INFO, ENC, CODECS_ALL, + V4L2_MPEG_MSM_VIDC_DISABLE, + V4L2_MPEG_MSM_VIDC_ENABLE, + 1, V4L2_MPEG_MSM_VIDC_DISABLE, + V4L2_CID_MPEG_VIDC_VUI_TIMING_INFO, + HFI_PROP_DISABLE_VUI_TIMING_INFO, + CAP_FLAG_OUTPUT_PORT}, + + {WITHOUT_STARTCODE, ENC, CODECS_ALL, + 0, 1, 1, 0, + V4L2_CID_MPEG_VIDEO_HEVC_WITHOUT_STARTCODE, + HFI_PROP_NAL_LENGTH_FIELD, + CAP_FLAG_OUTPUT_PORT}, + + {WITHOUT_STARTCODE, DEC, AV1, + 0, 0, 1, 0, + V4L2_CID_MPEG_VIDEO_HEVC_WITHOUT_STARTCODE, + HFI_PROP_NAL_LENGTH_FIELD, + CAP_FLAG_INPUT_PORT}, + + {NAL_LENGTH_FIELD, ENC, CODECS_ALL, + V4L2_MPEG_VIDEO_HEVC_SIZE_0, + V4L2_MPEG_VIDEO_HEVC_SIZE_4, + BIT(V4L2_MPEG_VIDEO_HEVC_SIZE_0) | + BIT(V4L2_MPEG_VIDEO_HEVC_SIZE_4), + V4L2_MPEG_VIDEO_HEVC_SIZE_0, + V4L2_CID_MPEG_VIDEO_HEVC_SIZE_OF_LENGTH_FIELD, + HFI_PROP_NAL_LENGTH_FIELD, + CAP_FLAG_MENU | CAP_FLAG_OUTPUT_PORT}, + + /* TODO: Firmware introduced enumeration type for this + * with and without seq header. + */ + {REQUEST_I_FRAME, ENC, H264 | HEVC, + 0, 0, 0, 0, + V4L2_CID_MPEG_VIDEO_FORCE_KEY_FRAME, + HFI_PROP_REQUEST_SYNC_FRAME, + CAP_FLAG_INPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED}, + + /* Enc: Keeping CABAC and CAVLC as same bitrate. + * Dec: there's no use of Bitrate cap + */ + {BIT_RATE, ENC, H264 | HEVC, + 1, MAX_BITRATE, 1, DEFAULT_BITRATE, + V4L2_CID_MPEG_VIDEO_BITRATE, + HFI_PROP_TOTAL_BITRATE, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {BITRATE_MODE, ENC, H264, + V4L2_MPEG_VIDEO_BITRATE_MODE_VBR, + V4L2_MPEG_VIDEO_BITRATE_MODE_CBR, + BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) | + BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_CBR), + V4L2_MPEG_VIDEO_BITRATE_MODE_VBR, + V4L2_CID_MPEG_VIDEO_BITRATE_MODE, + HFI_PROP_RATE_CONTROL, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {BITRATE_MODE, ENC, HEVC, + V4L2_MPEG_VIDEO_BITRATE_MODE_VBR, + V4L2_MPEG_VIDEO_BITRATE_MODE_CQ, + BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) | + BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_CBR) | + BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_CQ), + V4L2_MPEG_VIDEO_BITRATE_MODE_VBR, + V4L2_CID_MPEG_VIDEO_BITRATE_MODE, + HFI_PROP_RATE_CONTROL, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {BITRATE_MODE, ENC, HEIC, + V4L2_MPEG_VIDEO_BITRATE_MODE_CQ, + V4L2_MPEG_VIDEO_BITRATE_MODE_CQ, + BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_CQ), + V4L2_MPEG_VIDEO_BITRATE_MODE_CQ, + V4L2_CID_MPEG_VIDEO_BITRATE_MODE, + HFI_PROP_RATE_CONTROL, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {CABAC_MAX_BITRATE, ENC, H264 | HEVC, 0, + 160000000, 1, 160000000}, + + {CAVLC_MAX_BITRATE, ENC, H264, 0, + 220000000, 1, 220000000}, + + {ALLINTRA_MAX_BITRATE, ENC, H264 | HEVC, 0, + 245000000, 1, 245000000}, + + {LOWLATENCY_MAX_BITRATE, ENC, H264 | HEVC, 0, + 70000000, 1, 70000000}, + + {NUM_COMV, DEC, CODECS_ALL, + 0, INT_MAX, 1, 0}, + + {LOSSLESS, ENC, HEVC, + 0, 1, 1, 0, + V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU}, + + {FRAME_SKIP_MODE, ENC, H264 | HEVC | HEIC, + V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED, + V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT, + BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED) | + BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_LEVEL_LIMIT) | + BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT), + V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED, + V4L2_CID_MPEG_VIDEO_FRAME_SKIP_MODE, + 0, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {FRAME_RC_ENABLE, ENC, H264 | HEVC | HEIC, + 0, 1, 1, 1, + V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE}, + + {CONSTANT_QUALITY, ENC, HEVC, + 1, MAX_CONSTANT_QUALITY, 1, 90, + V4L2_CID_MPEG_VIDEO_CONSTANT_QUALITY, + HFI_PROP_CONSTANT_QUALITY, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {CONSTANT_QUALITY, ENC, HEIC, + 1, MAX_CONSTANT_QUALITY, 1, 100, + V4L2_CID_MPEG_VIDEO_CONSTANT_QUALITY, + HFI_PROP_CONSTANT_QUALITY, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {GOP_SIZE, ENC, CODECS_ALL, + 0, INT_MAX, 1, 2 * DEFAULT_FPS - 1, + V4L2_CID_MPEG_VIDEO_GOP_SIZE, + HFI_PROP_MAX_GOP_FRAMES, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {GOP_SIZE, ENC, HEIC, + 0, INT_MAX, 1, 0 /* all intra */, + V4L2_CID_MPEG_VIDEO_GOP_SIZE, + HFI_PROP_MAX_GOP_FRAMES, + CAP_FLAG_OUTPUT_PORT | + CAP_FLAG_INPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED}, + + {GOP_CLOSURE, ENC, H264 | HEVC, + 0, 1, 1, 1, + V4L2_CID_MPEG_VIDEO_GOP_CLOSURE, + 0}, + + {B_FRAME, ENC, H264 | HEVC, + 0, 7, 1, 0, + V4L2_CID_MPEG_VIDEO_B_FRAMES, + HFI_PROP_MAX_B_FRAMES, + CAP_FLAG_OUTPUT_PORT}, + + {B_FRAME, ENC, HEIC, + 0, 1, 1, 0, + V4L2_CID_MPEG_VIDEO_B_FRAMES, + HFI_PROP_MAX_B_FRAMES, + CAP_FLAG_OUTPUT_PORT}, + + {BLUR_TYPES, ENC, H264 | HEVC, + MSM_VIDC_BLUR_NONE, MSM_VIDC_BLUR_EXTERNAL, + BIT(MSM_VIDC_BLUR_NONE) | BIT(MSM_VIDC_BLUR_EXTERNAL), + MSM_VIDC_BLUR_NONE, + V4L2_CID_MPEG_VIDC_BLUR_TYPES, + HFI_PROP_BLUR_TYPES, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {BLUR_RESOLUTION, ENC, H264 | HEVC, + 0, S32_MAX, 1, 0, + V4L2_CID_MPEG_VIDC_BLUR_RESOLUTION, + HFI_PROP_BLUR_RESOLUTION, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {CSC, ENC, CODECS_ALL, + 0, 1, 1, 0, + V4L2_CID_MPEG_VIDC_CSC, + HFI_PROP_CSC, + CAP_FLAG_OUTPUT_PORT}, + + {CSC_CUSTOM_MATRIX, ENC, CODECS_ALL, + 0, 1, 1, 0, + V4L2_CID_MPEG_VIDC_CSC_CUSTOM_MATRIX, + HFI_PROP_CSC_MATRIX, + CAP_FLAG_OUTPUT_PORT}, + + {LOWLATENCY_MODE, ENC, H264 | HEVC, + 0, 1, 1, 0, + V4L2_CID_MPEG_VIDC_LOWLATENCY_REQUEST, + 0, + CAP_FLAG_NONE}, + + {LOWLATENCY_MODE, DEC, H264 | HEVC | VP9 | AV1, + 0, 1, 1, 0, + V4L2_CID_MPEG_VIDC_LOWLATENCY_REQUEST, + HFI_PROP_SEQ_CHANGE_AT_SYNC_FRAME, + CAP_FLAG_INPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED}, + + {LTR_COUNT, ENC, H264 | HEVC, + 0, 2, 1, 0, + V4L2_CID_MPEG_VIDEO_LTR_COUNT, + HFI_PROP_LTR_COUNT, + CAP_FLAG_OUTPUT_PORT}, + + {USE_LTR, ENC, H264 | HEVC, + 0, + ((1 << MAX_LTR_FRAME_COUNT) - 1), + 0, 0, + V4L2_CID_MPEG_VIDEO_USE_LTR_FRAMES, + HFI_PROP_LTR_USE, + CAP_FLAG_INPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED}, + + {MARK_LTR, ENC, H264 | HEVC, + INVALID_DEFAULT_MARK_OR_USE_LTR, + (MAX_LTR_FRAME_COUNT - 1), + 1, INVALID_DEFAULT_MARK_OR_USE_LTR, + V4L2_CID_MPEG_VIDEO_FRAME_LTR_INDEX, + HFI_PROP_LTR_MARK, + CAP_FLAG_INPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED}, + + {BASELAYER_PRIORITY, ENC, H264, + 0, MAX_BASE_LAYER_PRIORITY_ID, 1, 0, + V4L2_CID_MPEG_VIDEO_BASELAYER_PRIORITY_ID, + HFI_PROP_BASELAYER_PRIORITYID, + CAP_FLAG_OUTPUT_PORT}, + + {IR_TYPE, ENC, H264 | HEVC, + V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM, + V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_CYCLIC, + BIT(V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM) | + BIT(V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_CYCLIC), + V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM, + V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE, + 0, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {IR_PERIOD, ENC, H264 | HEVC, + 0, INT_MAX, 1, 0, + V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD, + 0, + CAP_FLAG_INPUT_PORT | CAP_FLAG_OUTPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {AU_DELIMITER, ENC, H264 | HEVC, + 0, 1, 1, 0, + V4L2_CID_MPEG_VIDEO_AU_DELIMITER, + HFI_PROP_AUD, + CAP_FLAG_OUTPUT_PORT}, + + {TIME_DELTA_BASED_RC, ENC, H264 | HEVC, + 0, 1, 1, 1, + V4L2_CID_MPEG_VIDC_TIME_DELTA_BASED_RC, + HFI_PROP_TIME_DELTA_BASED_RATE_CONTROL, + CAP_FLAG_OUTPUT_PORT}, + + {TIME_DELTA_BASED_RC, ENC, HEIC, + 0, 1, 1, 0, + V4L2_CID_MPEG_VIDC_TIME_DELTA_BASED_RC, + HFI_PROP_TIME_DELTA_BASED_RATE_CONTROL, + CAP_FLAG_OUTPUT_PORT}, + + {CONTENT_ADAPTIVE_CODING, ENC, H264 | HEVC, + 0, 1, 1, 1, + V4L2_CID_MPEG_VIDC_CONTENT_ADAPTIVE_CODING, + HFI_PROP_CONTENT_ADAPTIVE_CODING, + CAP_FLAG_OUTPUT_PORT}, + + {REQUEST_PREPROCESS, ENC, H264 | HEVC, + MSM_VIDC_PREPROCESS_NONE, + MSM_VIDC_PREPROCESS_TYPE0, + BIT(MSM_VIDC_PREPROCESS_NONE) | + BIT(MSM_VIDC_PREPROCESS_TYPE0), + MSM_VIDC_PREPROCESS_NONE, + 0, HFI_PROP_REQUEST_PREPROCESS, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {BITRATE_BOOST, ENC, H264 | HEVC, + 0, MAX_BITRATE_BOOST, 25, MAX_BITRATE_BOOST, + V4L2_CID_MPEG_VIDC_QUALITY_BITRATE_BOOST, + HFI_PROP_BITRATE_BOOST, + CAP_FLAG_OUTPUT_PORT}, + + {MIN_QUALITY, ENC, H264 | HEVC, + 0, MAX_SUPPORTED_MIN_QUALITY, 70, MAX_SUPPORTED_MIN_QUALITY, + 0, + HFI_PROP_MAINTAIN_MIN_QUALITY, + CAP_FLAG_OUTPUT_PORT}, + + {VBV_DELAY, ENC, H264 | HEVC, + 200, 300, 100, 300, + V4L2_CID_MPEG_VIDEO_VBV_DELAY, + HFI_PROP_VBV_DELAY, + CAP_FLAG_OUTPUT_PORT}, + + {PEAK_BITRATE, ENC, H264 | HEVC, + /* default peak bitrate is 10% larger than avg bitrate */ + 1, MAX_BITRATE, 1, DEFAULT_BITRATE, + V4L2_CID_MPEG_VIDEO_BITRATE_PEAK, + HFI_PROP_TOTAL_PEAK_BITRATE, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {MIN_FRAME_QP, ENC, H264, + MIN_QP_8BIT, MAX_QP, 1, MIN_QP_8BIT, + V4L2_CID_MPEG_VIDEO_H264_MIN_QP, + HFI_PROP_MIN_QP_PACKED, + CAP_FLAG_OUTPUT_PORT}, + + {MIN_FRAME_QP, ENC, HEVC | HEIC, + MIN_QP_10BIT, MAX_QP, 1, MIN_QP_10BIT, + V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP, + HFI_PROP_MIN_QP_PACKED, + CAP_FLAG_OUTPUT_PORT}, + + {I_FRAME_MIN_QP, ENC, H264, + MIN_QP_8BIT, MAX_QP, 1, MIN_QP_8BIT, + V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MIN_QP}, + + {I_FRAME_MIN_QP, ENC, HEVC | HEIC, + MIN_QP_10BIT, MAX_QP, 1, MIN_QP_10BIT, + V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MIN_QP}, + + {P_FRAME_MIN_QP, ENC, H264, + MIN_QP_8BIT, MAX_QP, 1, MIN_QP_8BIT, + V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP}, + + {P_FRAME_MIN_QP, ENC, HEVC | HEIC, + MIN_QP_10BIT, MAX_QP, 1, MIN_QP_10BIT, + V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MIN_QP}, + + {B_FRAME_MIN_QP, ENC, H264, + MIN_QP_8BIT, MAX_QP, 1, MIN_QP_8BIT, + V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MIN_QP}, + + {B_FRAME_MIN_QP, ENC, HEVC | HEIC, + MIN_QP_10BIT, MAX_QP, 1, MIN_QP_10BIT, + V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MIN_QP}, + + {MAX_FRAME_QP, ENC, H264, + MIN_QP_8BIT, MAX_QP, 1, MAX_QP, + V4L2_CID_MPEG_VIDEO_H264_MAX_QP, + HFI_PROP_MAX_QP_PACKED, + CAP_FLAG_OUTPUT_PORT}, + + {MAX_FRAME_QP, ENC, HEVC | HEIC, + MIN_QP_10BIT, MAX_QP, 1, MAX_QP, + V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP, + HFI_PROP_MAX_QP_PACKED, + CAP_FLAG_OUTPUT_PORT}, + + {I_FRAME_MAX_QP, ENC, H264, + MIN_QP_8BIT, MAX_QP, 1, MAX_QP, + V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP}, + + {I_FRAME_MAX_QP, ENC, HEVC | HEIC, + MIN_QP_10BIT, MAX_QP, 1, MAX_QP, + V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MAX_QP}, + + {P_FRAME_MAX_QP, ENC, H264, + MIN_QP_8BIT, MAX_QP, 1, MAX_QP, + V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP}, + + {P_FRAME_MAX_QP, ENC, HEVC | HEIC, + MIN_QP_10BIT, MAX_QP, 1, MAX_QP, + V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MAX_QP}, + + {B_FRAME_MAX_QP, ENC, H264, + MIN_QP_8BIT, MAX_QP, 1, MAX_QP, + V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MAX_QP}, + + {B_FRAME_MAX_QP, ENC, HEVC | HEIC, + MIN_QP_10BIT, MAX_QP, 1, MAX_QP, + V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MAX_QP}, + + {I_FRAME_QP, ENC, HEVC, + MIN_QP_10BIT, MAX_QP, 1, DEFAULT_QP, + V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP, + HFI_PROP_QP_PACKED, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {I_FRAME_QP, ENC, H264, + MIN_QP_8BIT, MAX_QP, 1, DEFAULT_QP, + V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP, + HFI_PROP_QP_PACKED, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {P_FRAME_QP, ENC, HEVC, + MIN_QP_10BIT, MAX_QP, 1, DEFAULT_QP, + V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP, + HFI_PROP_QP_PACKED, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {P_FRAME_QP, ENC, H264, + MIN_QP_8BIT, MAX_QP, 1, DEFAULT_QP, + V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP, + HFI_PROP_QP_PACKED, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {B_FRAME_QP, ENC, HEVC, + MIN_QP_10BIT, MAX_QP, 1, DEFAULT_QP, + V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP, + HFI_PROP_QP_PACKED, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {B_FRAME_QP, ENC, H264, + MIN_QP_8BIT, MAX_QP, 1, DEFAULT_QP, + V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP, + HFI_PROP_QP_PACKED, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {LAYER_TYPE, ENC, HEVC, + V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_B, + V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_P, + BIT(V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_B) | + BIT(V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_P), + V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_P, + V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_TYPE, + HFI_PROP_LAYER_ENCODING_TYPE, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {LAYER_TYPE, ENC, H264, + V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_B, + V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_P, + BIT(V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_B) | + BIT(V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_P), + V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_P, + V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_TYPE, + HFI_PROP_LAYER_ENCODING_TYPE, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {LAYER_ENABLE, ENC, H264, + 0, 1, 1, 0, + V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING, + HFI_PROP_LAYER_ENCODING_TYPE, + CAP_FLAG_OUTPUT_PORT}, + + {LAYER_ENABLE, ENC, HEVC, + 0, 1, 1, 0, + 0, + 0, + CAP_FLAG_OUTPUT_PORT}, + + {ENH_LAYER_COUNT, ENC, HEVC, + 0, 5, 1, 0, + V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_LAYER, + HFI_PROP_LAYER_COUNT, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {ENH_LAYER_COUNT, ENC, H264, + 0, 5, 1, 0, + V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER, + HFI_PROP_LAYER_COUNT, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {ENH_LAYER_COUNT, DEC, AV1, + 0, MAX_OP_POINT, 1, 0, + 0, + HFI_PROP_AV1_OP_POINT, + CAP_FLAG_INPUT_PORT}, + + {L0_BR, ENC, H264, + 1, MAX_BITRATE, 1, DEFAULT_BITRATE, + V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L0_BR, + HFI_PROP_BITRATE_LAYER1, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {L0_BR, ENC, HEVC, + 1, MAX_BITRATE, 1, DEFAULT_BITRATE, + V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L0_BR, + HFI_PROP_BITRATE_LAYER1, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {L1_BR, ENC, H264, + 1, MAX_BITRATE, 1, DEFAULT_BITRATE, + V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L1_BR, + HFI_PROP_BITRATE_LAYER2, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {L1_BR, ENC, HEVC, + 1, MAX_BITRATE, 1, DEFAULT_BITRATE, + V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L1_BR, + HFI_PROP_BITRATE_LAYER2, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {L2_BR, ENC, H264, + 1, MAX_BITRATE, 1, DEFAULT_BITRATE, + V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L2_BR, + HFI_PROP_BITRATE_LAYER3, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {L2_BR, ENC, HEVC, + 1, MAX_BITRATE, 1, DEFAULT_BITRATE, + V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L2_BR, + HFI_PROP_BITRATE_LAYER3, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {L3_BR, ENC, H264, + 1, MAX_BITRATE, 1, DEFAULT_BITRATE, + V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L3_BR, + HFI_PROP_BITRATE_LAYER4, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + {L3_BR, ENC, HEVC, + 1, MAX_BITRATE, 1, DEFAULT_BITRATE, + V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L3_BR, + HFI_PROP_BITRATE_LAYER4, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {L4_BR, ENC, H264, + 1, MAX_BITRATE, 1, DEFAULT_BITRATE, + V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L4_BR, + HFI_PROP_BITRATE_LAYER5, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {L4_BR, ENC, HEVC, + 1, MAX_BITRATE, 1, DEFAULT_BITRATE, + V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L4_BR, + HFI_PROP_BITRATE_LAYER5, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {L5_BR, ENC, H264, + 1, MAX_BITRATE, 1, DEFAULT_BITRATE, + V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L5_BR, + HFI_PROP_BITRATE_LAYER6, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {L5_BR, ENC, HEVC, + 1, MAX_BITRATE, 1, DEFAULT_BITRATE, + V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L5_BR, + HFI_PROP_BITRATE_LAYER6, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {ENTROPY_MODE, ENC, H264, + V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC, + V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC, + BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC) | + BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC), + V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC, + V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE, + HFI_PROP_CABAC_SESSION, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {ENTROPY_MODE, DEC, H264 | HEVC | VP9 | AV1 | MPEG2, + V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC, + V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC, + BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC) | + BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC), + V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC, + 0, + HFI_PROP_CABAC_SESSION}, + + {PROFILE, ENC | DEC, H264, + V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, + V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH, + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH), + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, + V4L2_CID_MPEG_VIDEO_H264_PROFILE, + HFI_PROP_PROFILE, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {PROFILE, ENC | DEC, HEVC | HEIC, + V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, + V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10_STILL_PICTURE, + BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) | + BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE) | + BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10) | + BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10_STILL_PICTURE), + V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, + V4L2_CID_MPEG_VIDEO_HEVC_PROFILE, + HFI_PROP_PROFILE, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {PROFILE, DEC, VP9, + V4L2_MPEG_VIDEO_VP9_PROFILE_0, + V4L2_MPEG_VIDEO_VP9_PROFILE_2, + BIT(V4L2_MPEG_VIDEO_VP9_PROFILE_0) | + BIT(V4L2_MPEG_VIDEO_VP9_PROFILE_2), + V4L2_MPEG_VIDEO_VP9_PROFILE_0, + V4L2_CID_MPEG_VIDEO_VP9_PROFILE, + HFI_PROP_PROFILE, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {PROFILE, DEC, AV1, + V4L2_MPEG_VIDC_AV1_PROFILE_MAIN, + V4L2_MPEG_VIDC_AV1_PROFILE_MAIN, + BIT(V4L2_MPEG_VIDC_AV1_PROFILE_MAIN), + V4L2_MPEG_VIDC_AV1_PROFILE_MAIN, + V4L2_CID_MPEG_VIDC_AV1_PROFILE, + HFI_PROP_PROFILE, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {PROFILE, DEC, MPEG2, + V4L2_MPEG_VIDEO_MPEG2_PROFILE_SIMPLE, + V4L2_MPEG_VIDEO_MPEG2_PROFILE_MAIN, + BIT(V4L2_MPEG_VIDEO_MPEG2_PROFILE_SIMPLE) | + BIT(V4L2_MPEG_VIDEO_MPEG2_PROFILE_MAIN), + V4L2_MPEG_VIDEO_MPEG2_PROFILE_SIMPLE, + V4L2_CID_MPEG_VIDEO_MPEG2_PROFILE, + HFI_PROP_PROFILE, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {LEVEL, ENC, H264, + V4L2_MPEG_VIDEO_H264_LEVEL_1_0, + V4L2_MPEG_VIDEO_H264_LEVEL_6_0, + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_0), + V4L2_MPEG_VIDEO_H264_LEVEL_5_0, + V4L2_CID_MPEG_VIDEO_H264_LEVEL, + HFI_PROP_LEVEL, + CAP_FLAG_VOLATILE | CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {LEVEL, ENC, HEVC | HEIC, + V4L2_MPEG_VIDEO_HEVC_LEVEL_1, + V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2, + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2), + V4L2_MPEG_VIDEO_HEVC_LEVEL_5, + V4L2_CID_MPEG_VIDEO_HEVC_LEVEL, + HFI_PROP_LEVEL, + CAP_FLAG_VOLATILE | CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {LEVEL, DEC, H264, + V4L2_MPEG_VIDEO_H264_LEVEL_1_0, + V4L2_MPEG_VIDEO_H264_LEVEL_6_2, + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_2), + V4L2_MPEG_VIDEO_H264_LEVEL_6_1, + V4L2_CID_MPEG_VIDEO_H264_LEVEL, + HFI_PROP_LEVEL, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {LEVEL, DEC, HEVC | HEIC, + V4L2_MPEG_VIDEO_HEVC_LEVEL_1, + V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2, + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2), + V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1, + V4L2_CID_MPEG_VIDEO_HEVC_LEVEL, + HFI_PROP_LEVEL, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {LEVEL, DEC, VP9, + V4L2_MPEG_VIDEO_VP9_LEVEL_1_0, + V4L2_MPEG_VIDEO_VP9_LEVEL_6_0, + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_0) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_1) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_0) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_3_0) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_0) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_1) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_0) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_1) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_2) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_6_0), + V4L2_MPEG_VIDEO_VP9_LEVEL_6_0, + V4L2_CID_MPEG_VIDEO_VP9_LEVEL, + HFI_PROP_LEVEL, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {LEVEL, DEC, AV1, + V4L2_MPEG_VIDC_AV1_LEVEL_2_0, + V4L2_MPEG_VIDC_AV1_LEVEL_6_1, + BIT(V4L2_MPEG_VIDC_AV1_LEVEL_2_0) | + BIT(V4L2_MPEG_VIDC_AV1_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDC_AV1_LEVEL_2_2) | + BIT(V4L2_MPEG_VIDC_AV1_LEVEL_2_3) | + BIT(V4L2_MPEG_VIDC_AV1_LEVEL_3_0) | + BIT(V4L2_MPEG_VIDC_AV1_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDC_AV1_LEVEL_3_2) | + BIT(V4L2_MPEG_VIDC_AV1_LEVEL_3_3) | + BIT(V4L2_MPEG_VIDC_AV1_LEVEL_4_0) | + BIT(V4L2_MPEG_VIDC_AV1_LEVEL_4_1) | + BIT(V4L2_MPEG_VIDC_AV1_LEVEL_4_2) | + BIT(V4L2_MPEG_VIDC_AV1_LEVEL_4_3) | + BIT(V4L2_MPEG_VIDC_AV1_LEVEL_5_0) | + BIT(V4L2_MPEG_VIDC_AV1_LEVEL_5_1) | + BIT(V4L2_MPEG_VIDC_AV1_LEVEL_5_2) | + BIT(V4L2_MPEG_VIDC_AV1_LEVEL_5_3) | + BIT(V4L2_MPEG_VIDC_AV1_LEVEL_6_0) | + BIT(V4L2_MPEG_VIDC_AV1_LEVEL_6_1), + V4L2_MPEG_VIDC_AV1_LEVEL_6_1, + V4L2_CID_MPEG_VIDC_AV1_LEVEL, + HFI_PROP_LEVEL, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {LEVEL, DEC, MPEG2, + V4L2_MPEG_VIDEO_MPEG2_LEVEL_LOW, + V4L2_MPEG_VIDEO_MPEG2_LEVEL_HIGH, + BIT(V4L2_MPEG_VIDEO_MPEG2_LEVEL_LOW) | + BIT(V4L2_MPEG_VIDEO_MPEG2_LEVEL_MAIN) | + BIT(V4L2_MPEG_VIDEO_MPEG2_LEVEL_HIGH_1440) | + BIT(V4L2_MPEG_VIDEO_MPEG2_LEVEL_HIGH), + V4L2_MPEG_VIDEO_MPEG2_LEVEL_LOW, + V4L2_CID_MPEG_VIDEO_MPEG2_LEVEL, + HFI_PROP_LEVEL, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {AV1_TIER, DEC, AV1, + V4L2_MPEG_VIDC_AV1_TIER_MAIN, + V4L2_MPEG_VIDC_AV1_TIER_HIGH, + BIT(V4L2_MPEG_VIDC_AV1_TIER_MAIN) | + BIT(V4L2_MPEG_VIDC_AV1_TIER_HIGH), + V4L2_MPEG_VIDC_AV1_TIER_HIGH, + V4L2_CID_MPEG_VIDC_AV1_TIER, + HFI_PROP_TIER, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {HEVC_TIER, ENC | DEC, HEVC, + V4L2_MPEG_VIDEO_HEVC_TIER_MAIN, + V4L2_MPEG_VIDEO_HEVC_TIER_HIGH, + BIT(V4L2_MPEG_VIDEO_HEVC_TIER_MAIN) | + BIT(V4L2_MPEG_VIDEO_HEVC_TIER_HIGH), + V4L2_MPEG_VIDEO_HEVC_TIER_HIGH, + V4L2_CID_MPEG_VIDEO_HEVC_TIER, + HFI_PROP_TIER, + CAP_FLAG_VOLATILE | CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {HEVC_TIER, ENC | DEC, HEIC, + V4L2_MPEG_VIDEO_HEVC_TIER_MAIN, + V4L2_MPEG_VIDEO_HEVC_TIER_MAIN, + BIT(V4L2_MPEG_VIDEO_HEVC_TIER_MAIN), + V4L2_MPEG_VIDEO_HEVC_TIER_MAIN, + V4L2_CID_MPEG_VIDEO_HEVC_TIER, + HFI_PROP_TIER, + CAP_FLAG_VOLATILE | CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {LF_MODE, ENC, H264, + V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED, + DB_H264_DISABLE_SLICE_BOUNDARY, + BIT(V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED) | + BIT(V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED) | + BIT(DB_H264_DISABLE_SLICE_BOUNDARY), + V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED, + V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE, + HFI_PROP_DEBLOCKING_MODE, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {LF_MODE, ENC, HEVC | HEIC, + V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED, + DB_HEVC_DISABLE_SLICE_BOUNDARY, + BIT(V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED) | + BIT(V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_ENABLED) | + BIT(DB_HEVC_DISABLE_SLICE_BOUNDARY), + V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_ENABLED, + V4L2_CID_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE, + HFI_PROP_DEBLOCKING_MODE, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {LF_ALPHA, ENC, H264, + -6, 6, 1, 0, + V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA}, + + {LF_ALPHA, ENC, HEVC | HEIC, + -6, 6, 1, 0, + V4L2_CID_MPEG_VIDEO_HEVC_LF_TC_OFFSET_DIV2}, + + {LF_BETA, ENC, H264, + -6, 6, 1, 0, + V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA}, + + {LF_BETA, ENC, HEVC | HEIC, + -6, 6, 1, 0, + V4L2_CID_MPEG_VIDEO_HEVC_LF_BETA_OFFSET_DIV2}, + + {SLICE_MODE, ENC, H264 | HEVC, + V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE, + V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_BYTES, + BIT(V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE) | + BIT(V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_MB) | + BIT(V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_BYTES), + V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE, + V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE, + 0, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {SLICE_MODE, ENC, HEIC, + V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE, + V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE, + BIT(V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE), + V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE, + V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE, + 0, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {SLICE_MAX_BYTES, ENC, H264 | HEVC, + MIN_SLICE_BYTE_SIZE, MAX_SLICE_BYTE_SIZE, + 1, MIN_SLICE_BYTE_SIZE, + V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES, + HFI_PROP_MULTI_SLICE_BYTES_COUNT, + CAP_FLAG_OUTPUT_PORT}, + + {SLICE_MAX_MB, ENC, H264 | HEVC, + 1, MAX_SLICE_MB_SIZE, 1, 1, + V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB, + HFI_PROP_MULTI_SLICE_MB_COUNT, + CAP_FLAG_OUTPUT_PORT}, + + {MB_RC, ENC, H264 | HEVC, + 0, 1, 1, 1, + V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE, + 0, + CAP_FLAG_OUTPUT_PORT}, + + {TRANSFORM_8X8, ENC, H264, + 0, 1, 1, 1, + V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM, + HFI_PROP_8X8_TRANSFORM, + CAP_FLAG_OUTPUT_PORT}, + + {CHROMA_QP_INDEX_OFFSET, ENC, HEVC, + MIN_CHROMA_QP_OFFSET, MAX_CHROMA_QP_OFFSET, + 1, MAX_CHROMA_QP_OFFSET, + V4L2_CID_MPEG_VIDEO_H264_CHROMA_QP_INDEX_OFFSET, + HFI_PROP_CHROMA_QP_OFFSET, + CAP_FLAG_OUTPUT_PORT}, + + {DISPLAY_DELAY_ENABLE, DEC, H264 | HEVC | VP9 | AV1, + 0, 1, 1, 0, + V4L2_CID_MPEG_VIDEO_DEC_DISPLAY_DELAY_ENABLE, + HFI_PROP_DECODE_ORDER_OUTPUT, + CAP_FLAG_INPUT_PORT}, + + {DISPLAY_DELAY, DEC, H264 | HEVC | VP9 | AV1, + 0, 1, 1, 0, + V4L2_CID_MPEG_VIDEO_DEC_DISPLAY_DELAY, + HFI_PROP_DECODE_ORDER_OUTPUT, + CAP_FLAG_INPUT_PORT}, + + {OUTPUT_ORDER, DEC, H264 | HEVC | VP9 | AV1, + 0, 1, 1, 0, + 0, + HFI_PROP_DECODE_ORDER_OUTPUT, + CAP_FLAG_INPUT_PORT}, + + {INPUT_BUF_HOST_MAX_COUNT, ENC | DEC, CODECS_ALL, + DEFAULT_MAX_HOST_BUF_COUNT, DEFAULT_MAX_HOST_BURST_BUF_COUNT, + 1, DEFAULT_MAX_HOST_BUF_COUNT, + 0, + HFI_PROP_BUFFER_HOST_MAX_COUNT, + CAP_FLAG_INPUT_PORT}, + + {OUTPUT_BUF_HOST_MAX_COUNT, ENC | DEC, CODECS_ALL, + DEFAULT_MAX_HOST_BUF_COUNT, DEFAULT_MAX_HOST_BURST_BUF_COUNT, + 1, DEFAULT_MAX_HOST_BUF_COUNT, + 0, + HFI_PROP_BUFFER_HOST_MAX_COUNT, + CAP_FLAG_OUTPUT_PORT}, + + {CONCEAL_COLOR_8BIT, DEC, CODECS_ALL, 0x0, 0xFF00FF00FF, 1, + DEFAULT_VIDEO_CONCEAL_COLOR_BLACK, + V4L2_CID_MPEG_VIDEO_DEC_CONCEAL_COLOR, + HFI_PROP_CONCEAL_COLOR_8BIT, + CAP_FLAG_INPUT_PORT}, + + {CONCEAL_COLOR_10BIT, DEC, CODECS_ALL, 0x0, 0x3FF03FF03FF, 1, + DEFAULT_VIDEO_CONCEAL_COLOR_BLACK, + V4L2_CID_MPEG_VIDEO_DEC_CONCEAL_COLOR, + HFI_PROP_CONCEAL_COLOR_10BIT, + CAP_FLAG_INPUT_PORT}, + + {STAGE, DEC | ENC, CODECS_ALL, + MSM_VIDC_STAGE_1, + MSM_VIDC_STAGE_2, 1, + MSM_VIDC_STAGE_2, + 0, + HFI_PROP_STAGE}, + + {PIPE, DEC | ENC, CODECS_ALL, + MSM_VIDC_PIPE_1, + MSM_VIDC_PIPE_4, 1, + MSM_VIDC_PIPE_4, + 0, + HFI_PROP_PIPE}, + + {POC, DEC, H264, + 0, 2, 1, 1, + 0, + HFI_PROP_PIC_ORDER_CNT_TYPE}, + + {QUALITY_MODE, ENC, CODECS_ALL, + MSM_VIDC_MAX_QUALITY_MODE, + MSM_VIDC_POWER_SAVE_MODE, 1, + MSM_VIDC_POWER_SAVE_MODE}, + + {CODED_FRAMES, DEC, H264 | HEVC | HEIC, + CODED_FRAMES_PROGRESSIVE, CODED_FRAMES_INTERLACE, + 1, CODED_FRAMES_PROGRESSIVE, + V4L2_CID_MPEG_VIDC_INTERLACE, + HFI_PROP_CODED_FRAMES, + CAP_FLAG_VOLATILE}, + + {BIT_DEPTH, DEC | ENC, CODECS_ALL, BIT_DEPTH_8, BIT_DEPTH_10, 1, BIT_DEPTH_8, + 0, + HFI_PROP_LUMA_CHROMA_BIT_DEPTH}, + + {CODEC_CONFIG, DEC, H264 | HEVC | HEIC | AV1, 0, 1, 1, 0, + V4L2_CID_MPEG_VIDC_CODEC_CONFIG, 0, + CAP_FLAG_DYNAMIC_ALLOWED}, + + {BITSTREAM_SIZE_OVERWRITE, DEC, CODECS_ALL, 0, INT_MAX, 1, 0, + V4L2_CID_MPEG_VIDC_MIN_BITSTREAM_SIZE_OVERWRITE}, + + {THUMBNAIL_MODE, DEC, CODECS_ALL, + 0, 1, 1, 0, + V4L2_CID_MPEG_VIDC_THUMBNAIL_MODE, + HFI_PROP_THUMBNAIL_MODE, + CAP_FLAG_INPUT_PORT}, + + {DEFAULT_HEADER, DEC, CODECS_ALL, + 0, 1, 1, 0, + 0, + HFI_PROP_DEC_DEFAULT_HEADER}, + + {RAP_FRAME, DEC, CODECS_ALL, + 0, 1, 1, 1, + 0, + HFI_PROP_DEC_START_FROM_RAP_FRAME, + CAP_FLAG_INPUT_PORT}, + + {SEQ_CHANGE_AT_SYNC_FRAME, DEC, CODECS_ALL, + 0, 1, 1, 1, + 0, + HFI_PROP_SEQ_CHANGE_AT_SYNC_FRAME, + CAP_FLAG_INPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED}, + + {PRIORITY, DEC | ENC, CODECS_ALL, + 0, 4, 1, 4, + V4L2_CID_MPEG_VIDC_PRIORITY, + HFI_PROP_SESSION_PRIORITY, + CAP_FLAG_DYNAMIC_ALLOWED}, + + {FIRMWARE_PRIORITY_OFFSET, DEC | ENC, CODECS_ALL, + 1, 1, 1, 1}, + + {CRITICAL_PRIORITY, ENC, CODECS_ALL, + 0, 1, 1, 0, + V4L2_CID_MPEG_VIDC_CRITICAL_PRIORITY}, + + {RESERVE_DURATION, ENC, CODECS_ALL, + 0, INT_MAX, 1, 0, + V4L2_CID_MPEG_VIDC_RESERVE_DURATION, + HFI_CMD_RESERVE, + CAP_FLAG_DYNAMIC_ALLOWED}, + + {ENC_IP_CR, ENC, CODECS_ALL, + 0, S32_MAX, 1, 0, + V4L2_CID_MPEG_VIDC_COMPRESSION_RATIO, + 0, CAP_FLAG_DYNAMIC_ALLOWED}, + + {INPUT_EXTRA_METADATA_OFFSET, DEC, CODECS_ALL, + 0, INT_MAX, 1, 0, + V4L2_CID_MPEG_VIDC_INPUT_EXTRA_METADATA_OFFSET, + 0, CAP_FLAG_DYNAMIC_ALLOWED}, + + {DPB_LIST, DEC, CODECS_ALL, + 0, 1, 1, 0, + 0, + HFI_PROP_DPB_LIST, + CAP_FLAG_OUTPUT_PORT}, + + {FILM_GRAIN, DEC, AV1, + 0, 1, 1, 0, + V4L2_CID_MPEG_VIDC_FILM_GRAIN_PRESENT, + HFI_PROP_AV1_FILM_GRAIN_PRESENT, + CAP_FLAG_VOLATILE}, + + {SUPER_BLOCK, DEC, AV1, + 0, 1, 1, 0, + 0, + HFI_PROP_AV1_SUPER_BLOCK_ENABLED}, + + {DRAP, DEC, AV1, + 0, S32_MAX, 1, 0, + 0, + HFI_PROP_AV1_DRAP_CONFIG, + CAP_FLAG_INPUT_PORT}, + + {LAST_FLAG_EVENT_ENABLE, DEC, CODECS_ALL, + 0, 1, 1, 0, + V4L2_CID_MPEG_VIDC_LAST_FLAG_EVENT_ENABLE}, + + {META_BITSTREAM_RESOLUTION, DEC, AV1, + MSM_VIDC_META_DISABLE, + MSM_VIDC_META_ENABLE | MSM_VIDC_META_RX_INPUT | + MSM_VIDC_META_RX_OUTPUT, + 0, MSM_VIDC_META_DISABLE, + V4L2_CID_MPEG_VIDC_METADATA_BITSTREAM_RESOLUTION, + HFI_PROP_BITSTREAM_RESOLUTION, + CAP_FLAG_BITMASK | CAP_FLAG_META}, + + {META_CROP_OFFSETS, DEC, AV1, + MSM_VIDC_META_DISABLE, + MSM_VIDC_META_ENABLE | MSM_VIDC_META_RX_INPUT | + MSM_VIDC_META_RX_OUTPUT, + 0, MSM_VIDC_META_DISABLE, + V4L2_CID_MPEG_VIDC_METADATA_CROP_OFFSETS, + HFI_PROP_CROP_OFFSETS, + CAP_FLAG_BITMASK | CAP_FLAG_META}, + + {ALL_INTRA, ENC, H264 | HEVC, + 0, 1, 1, 0, + 0, + 0, + CAP_FLAG_OUTPUT_PORT}, + + {META_LTR_MARK_USE, ENC, H264 | HEVC, + MSM_VIDC_META_DISABLE, + MSM_VIDC_META_ENABLE | MSM_VIDC_META_RX_OUTPUT, + 0, MSM_VIDC_META_DISABLE, + V4L2_CID_MPEG_VIDC_METADATA_LTR_MARK_USE_DETAILS, + HFI_PROP_LTR_MARK_USE_DETAILS, + CAP_FLAG_BITMASK | CAP_FLAG_META}, + + {META_SEQ_HDR_NAL, ENC, CODECS_ALL, + MSM_VIDC_META_DISABLE, + MSM_VIDC_META_ENABLE | MSM_VIDC_META_RX_OUTPUT, + 0, MSM_VIDC_META_DISABLE, + V4L2_CID_MPEG_VIDC_METADATA_SEQ_HEADER_NAL, + HFI_PROP_METADATA_SEQ_HEADER_NAL, + CAP_FLAG_BITMASK | CAP_FLAG_META}, + + {META_DPB_MISR, DEC, CODECS_ALL, + MSM_VIDC_META_DISABLE, + MSM_VIDC_META_ENABLE | MSM_VIDC_META_RX_OUTPUT, + 0, MSM_VIDC_META_DISABLE, + V4L2_CID_MPEG_VIDC_METADATA_DPB_LUMA_CHROMA_MISR, + HFI_PROP_DPB_LUMA_CHROMA_MISR, + CAP_FLAG_BITMASK | CAP_FLAG_META}, + + {META_OPB_MISR, DEC, CODECS_ALL, + MSM_VIDC_META_DISABLE, + MSM_VIDC_META_ENABLE | MSM_VIDC_META_RX_OUTPUT, + 0, MSM_VIDC_META_DISABLE, + V4L2_CID_MPEG_VIDC_METADATA_OPB_LUMA_CHROMA_MISR, + HFI_PROP_OPB_LUMA_CHROMA_MISR, + CAP_FLAG_BITMASK | CAP_FLAG_META}, + + {META_INTERLACE, DEC, H264 | MPEG2, + MSM_VIDC_META_DISABLE, + MSM_VIDC_META_ENABLE | MSM_VIDC_META_RX_OUTPUT, + 0, MSM_VIDC_META_DISABLE, + V4L2_CID_MPEG_VIDC_METADATA_INTERLACE, + HFI_PROP_INTERLACE_INFO, + CAP_FLAG_BITMASK | CAP_FLAG_META}, + + {META_TIMESTAMP, DEC | ENC, CODECS_ALL, + MSM_VIDC_META_DISABLE, + MSM_VIDC_META_ENABLE | MSM_VIDC_META_RX_OUTPUT, + 0, MSM_VIDC_META_DISABLE, + V4L2_CID_MPEG_VIDC_METADATA_TIMESTAMP, + HFI_PROP_TIMESTAMP, + CAP_FLAG_BITMASK | CAP_FLAG_META}, + + {META_CONCEALED_MB_CNT, DEC, CODECS_ALL, + MSM_VIDC_META_DISABLE, + MSM_VIDC_META_ENABLE | MSM_VIDC_META_RX_OUTPUT, + 0, MSM_VIDC_META_DISABLE, + V4L2_CID_MPEG_VIDC_METADATA_CONCEALED_MB_COUNT, + HFI_PROP_CONEALED_MB_COUNT, + CAP_FLAG_BITMASK | CAP_FLAG_META}, + + {META_HIST_INFO, DEC, HEVC | AV1 | VP9, + MSM_VIDC_META_DISABLE, + MSM_VIDC_META_ENABLE | MSM_VIDC_META_RX_OUTPUT, + 0, MSM_VIDC_META_DISABLE, + V4L2_CID_MPEG_VIDC_METADATA_HISTOGRAM_INFO, + HFI_PROP_HISTOGRAM_INFO, + CAP_FLAG_BITMASK | CAP_FLAG_META}, + + {META_TRANSCODING_STAT_INFO, DEC, HEVC | H264, + MSM_VIDC_META_DISABLE, + MSM_VIDC_META_ENABLE | MSM_VIDC_META_RX_OUTPUT, + 0, MSM_VIDC_META_DISABLE, + V4L2_CID_MPEG_VIDC_METADATA_TRANSCODE_STAT_INFO, + HFI_PROP_TRANSCODING_STAT_INFO, + CAP_FLAG_BITMASK | CAP_FLAG_META}, + + {META_TRANSCODING_STAT_INFO, ENC, HEVC | H264, + MSM_VIDC_META_DISABLE, + MSM_VIDC_META_ENABLE | MSM_VIDC_META_TX_INPUT, + 0, MSM_VIDC_META_DISABLE, + V4L2_CID_MPEG_VIDC_METADATA_TRANSCODE_STAT_INFO, + HFI_PROP_TRANSCODING_STAT_INFO, + CAP_FLAG_BITMASK | CAP_FLAG_META}, + + {META_PICTURE_TYPE, DEC, CODECS_ALL, + MSM_VIDC_META_DISABLE, + MSM_VIDC_META_ENABLE | MSM_VIDC_META_RX_INPUT, + 0, MSM_VIDC_META_DISABLE, + V4L2_CID_MPEG_VIDC_METADATA_PICTURE_TYPE, + HFI_PROP_PICTURE_TYPE, + CAP_FLAG_BITMASK | CAP_FLAG_META}, + + {META_SEI_MASTERING_DISP, ENC, HEVC | HEIC, + MSM_VIDC_META_DISABLE, + MSM_VIDC_META_ENABLE | MSM_VIDC_META_TX_INPUT, + 0, MSM_VIDC_META_DISABLE, + V4L2_CID_MPEG_VIDC_METADATA_SEI_MDCV, + HFI_PROP_SEI_MASTERING_DISPLAY_COLOUR, + CAP_FLAG_BITMASK | CAP_FLAG_META}, + + {META_SEI_MASTERING_DISP, DEC, HEVC | HEIC | AV1, + MSM_VIDC_META_DISABLE, + MSM_VIDC_META_ENABLE | MSM_VIDC_META_RX_INPUT | + MSM_VIDC_META_RX_OUTPUT, + 0, MSM_VIDC_META_DISABLE, + V4L2_CID_MPEG_VIDC_METADATA_SEI_MDCV, + HFI_PROP_SEI_MASTERING_DISPLAY_COLOUR, + CAP_FLAG_BITMASK | CAP_FLAG_META}, + + {META_SEI_CLL, ENC, HEVC | HEIC, + MSM_VIDC_META_DISABLE, + MSM_VIDC_META_ENABLE | MSM_VIDC_META_TX_INPUT, + 0, MSM_VIDC_META_DISABLE, + V4L2_CID_MPEG_VIDC_METADATA_SEI_CLL, + HFI_PROP_SEI_CONTENT_LIGHT_LEVEL, + CAP_FLAG_BITMASK | CAP_FLAG_META}, + + {META_SEI_CLL, DEC, HEVC | HEIC | AV1, + MSM_VIDC_META_DISABLE, + MSM_VIDC_META_ENABLE | MSM_VIDC_META_RX_INPUT | + MSM_VIDC_META_RX_OUTPUT, + 0, MSM_VIDC_META_DISABLE, + V4L2_CID_MPEG_VIDC_METADATA_SEI_CLL, + HFI_PROP_SEI_CONTENT_LIGHT_LEVEL, + CAP_FLAG_BITMASK | CAP_FLAG_META}, + + {META_HDR10PLUS, ENC, HEVC | HEIC, + MSM_VIDC_META_DISABLE, + MSM_VIDC_META_ENABLE | MSM_VIDC_META_TX_INPUT, + 0, MSM_VIDC_META_DISABLE, + V4L2_CID_MPEG_VIDC_METADATA_HDR10PLUS, + HFI_PROP_SEI_HDR10PLUS_USERDATA, + CAP_FLAG_BITMASK | CAP_FLAG_META}, + + {META_HDR10PLUS, DEC, HEVC | HEIC | AV1, + MSM_VIDC_META_DISABLE, + MSM_VIDC_META_ENABLE | MSM_VIDC_META_RX_INPUT | + MSM_VIDC_META_RX_OUTPUT, + 0, MSM_VIDC_META_DISABLE, + V4L2_CID_MPEG_VIDC_METADATA_HDR10PLUS, + HFI_PROP_SEI_HDR10PLUS_USERDATA, + CAP_FLAG_BITMASK | CAP_FLAG_META}, + + {META_DOLBY_RPU, ENC, HEVC, + MSM_VIDC_META_DISABLE, + MSM_VIDC_META_ENABLE | MSM_VIDC_META_TX_INPUT, + 0, MSM_VIDC_META_DISABLE, + V4L2_CID_MPEG_VIDC_METADATA_DOLBY_RPU, + HFI_PROP_DOLBY_RPU_METADATA, + CAP_FLAG_BITMASK | CAP_FLAG_META}, + + {META_DOLBY_RPU, DEC, H264 | HEVC, + MSM_VIDC_META_DISABLE, + MSM_VIDC_META_ENABLE | MSM_VIDC_META_RX_OUTPUT, + 0, MSM_VIDC_META_DISABLE, + V4L2_CID_MPEG_VIDC_METADATA_DOLBY_RPU, + HFI_PROP_DOLBY_RPU_METADATA, + CAP_FLAG_BITMASK | CAP_FLAG_META}, + + {META_EVA_STATS, ENC, H264 | HEVC, + MSM_VIDC_META_DISABLE, + MSM_VIDC_META_ENABLE | MSM_VIDC_META_TX_INPUT, + 0, MSM_VIDC_META_DISABLE, + V4L2_CID_MPEG_VIDC_METADATA_EVA_STATS, + HFI_PROP_EVA_STAT_INFO, + CAP_FLAG_BITMASK | CAP_FLAG_META}, + + {META_BUF_TAG, ENC, CODECS_ALL, + MSM_VIDC_META_DISABLE, + MSM_VIDC_META_ENABLE | MSM_VIDC_META_TX_INPUT | + MSM_VIDC_META_RX_OUTPUT, + 0, MSM_VIDC_META_DISABLE, + V4L2_CID_MPEG_VIDC_METADATA_BUFFER_TAG, + HFI_PROP_BUFFER_TAG, + CAP_FLAG_BITMASK | CAP_FLAG_META}, + + /* + * when fence enabled, client needs output buffer_tag + * in input metadata buffer done. + */ + {META_BUF_TAG, DEC, CODECS_ALL, + MSM_VIDC_META_DISABLE, + MSM_VIDC_META_ENABLE | MSM_VIDC_META_TX_INPUT | + MSM_VIDC_META_TX_OUTPUT | MSM_VIDC_META_RX_INPUT | + MSM_VIDC_META_RX_OUTPUT, + 0, MSM_VIDC_META_DISABLE, + V4L2_CID_MPEG_VIDC_METADATA_BUFFER_TAG, + HFI_PROP_BUFFER_TAG, + CAP_FLAG_BITMASK | CAP_FLAG_META}, + + {META_DPB_TAG_LIST, DEC, CODECS_ALL, + MSM_VIDC_META_DISABLE, + MSM_VIDC_META_ENABLE | MSM_VIDC_META_RX_OUTPUT, + 0, MSM_VIDC_META_DISABLE, + V4L2_CID_MPEG_VIDC_METADATA_DPB_TAG_LIST, + HFI_PROP_DPB_TAG_LIST, + CAP_FLAG_BITMASK | CAP_FLAG_META}, + + {META_SUBFRAME_OUTPUT, ENC, HEIC | H264 | HEVC, + MSM_VIDC_META_DISABLE, + MSM_VIDC_META_ENABLE | MSM_VIDC_META_RX_OUTPUT, + 0, MSM_VIDC_META_DISABLE, + V4L2_CID_MPEG_VIDC_METADATA_SUBFRAME_OUTPUT, + HFI_PROP_SUBFRAME_OUTPUT, + CAP_FLAG_BITMASK | CAP_FLAG_META}, + + {META_SUBFRAME_OUTPUT, DEC, CODECS_ALL, + MSM_VIDC_META_DISABLE, + MSM_VIDC_META_ENABLE | MSM_VIDC_META_RX_OUTPUT, + 0, MSM_VIDC_META_DISABLE, + V4L2_CID_MPEG_VIDC_METADATA_SUBFRAME_OUTPUT, + HFI_PROP_SUBFRAME_OUTPUT, + CAP_FLAG_BITMASK | CAP_FLAG_META}, + + {META_ENC_QP_METADATA, ENC, CODECS_ALL, + MSM_VIDC_META_DISABLE, + MSM_VIDC_META_ENABLE | MSM_VIDC_META_RX_OUTPUT, + 0, MSM_VIDC_META_DISABLE, + V4L2_CID_MPEG_VIDC_METADATA_ENC_QP_METADATA, + HFI_PROP_ENC_QP_METADATA, + CAP_FLAG_BITMASK | CAP_FLAG_META}, + + {META_ROI_INFO, ENC, H264 | HEVC, + MSM_VIDC_META_DISABLE, + MSM_VIDC_META_ENABLE | MSM_VIDC_META_TX_INPUT, + 0, MSM_VIDC_META_DISABLE, + V4L2_CID_MPEG_VIDC_METADATA_ROI_INFO, + HFI_PROP_ROI_INFO, + CAP_FLAG_INPUT_PORT | CAP_FLAG_BITMASK | CAP_FLAG_META}, + + {META_SALIENCY_INFO, ENC, H264 | HEVC, + MSM_VIDC_META_DISABLE, + MSM_VIDC_META_ENABLE | MSM_VIDC_META_TX_INPUT, + 0, MSM_VIDC_META_DISABLE, + V4L2_CID_MPEG_VIDC_METADATA_SALIENCY_INFO, + HFI_PROP_ROI_AS_SALIENCY_INFO, + CAP_FLAG_INPUT_PORT | CAP_FLAG_BITMASK | CAP_FLAG_META}, + + {META_DEC_QP_METADATA, DEC, CODECS_ALL, + MSM_VIDC_META_DISABLE, + MSM_VIDC_META_ENABLE | MSM_VIDC_META_RX_OUTPUT, + 0, MSM_VIDC_META_DISABLE, + V4L2_CID_MPEG_VIDC_METADATA_QP, + HFI_PROP_DEC_QP_METADATA, + CAP_FLAG_BITMASK | CAP_FLAG_META}, + + {GRID_ENABLE, ENC, HEIC, + 0, 1, 1, 1, + 0, + HFI_PROP_HEIC_GRID_ENABLE, + CAP_FLAG_OUTPUT_PORT}, + + {GRID_SIZE, ENC, HEIC, + HEIC_GRID_WIDTH, HEIC_GRID_WIDTH * 2, + HEIC_GRID_WIDTH, HEIC_GRID_WIDTH, + V4L2_CID_MPEG_VIDC_GRID_WIDTH}, + + {COMPLEXITY, ENC, H264 | HEVC, + 0, 100, + 1, DEFAULT_COMPLEXITY, + V4L2_CID_MPEG_VIDC_COMPLEXITY}, + + /* + * value of MAX_NUM_REORDER_FRAMES is 32 packed as mentioned below + * (max_num_reorder_count << 16) | max_dec_frame_buffering_count + */ + {MAX_NUM_REORDER_FRAMES, DEC, H264 | HEVC, + 0, INT_MAX, 1, 0, + V4L2_CID_MPEG_VIDC_MAX_NUM_REORDER_FRAMES, + HFI_PROP_MAX_NUM_REORDER_FRAMES, + CAP_FLAG_VOLATILE}, + + {DELIVERY_MODE, ENC, HEVC, + 0, 1, 1, 0, + V4L2_CID_MPEG_VIDC_HEVC_ENCODE_DELIVERY_MODE, + HFI_PROP_ENABLE_SLICE_DELIVERY, + CAP_FLAG_OUTPUT_PORT}, + + {DELIVERY_MODE, ENC, H264, + 0, 1, 1, 0, + V4L2_CID_MPEG_VIDC_H264_ENCODE_DELIVERY_MODE, + HFI_PROP_ENABLE_SLICE_DELIVERY, + CAP_FLAG_OUTPUT_PORT}, +}; + +static struct msm_platform_inst_cap_dependency instance_cap_dependency_data_glymur[] = { + /* {cap, domain, codec, + * parents, + * children, + * adjust, set} + */ + + {PIX_FMTS, ENC, H264, + {META_ROI_INFO, IR_PERIOD, CSC, BIT_DEPTH}}, + + {PIX_FMTS, ENC, HEVC, + {PROFILE, MIN_FRAME_QP, MAX_FRAME_QP, I_FRAME_QP, P_FRAME_QP, + B_FRAME_QP, META_ROI_INFO, MIN_QUALITY, BLUR_TYPES, IR_PERIOD, + LTR_COUNT, CSC, BIT_DEPTH}}, + + {PIX_FMTS, ENC, HEIC, + {PROFILE, CSC, BIT_DEPTH}}, + + {PIX_FMTS, DEC, HEVC | HEIC, + {PROFILE}}, + + {BIT_DEPTH, ENC, CODECS_ALL, + {0}, + msm_vidc_adjust_bitdepth}, + + {FRAME_RATE, ENC, CODECS_ALL, + {LEVEL}, + NULL, + msm_vidc_set_q16}, + + {FRAME_RATE, DEC, CODECS_ALL, + {0}, + msm_vidc_adjust_dec_frame_rate}, + + {OPERATING_RATE, DEC, CODECS_ALL, + {0}, + msm_vidc_adjust_dec_operating_rate}, + + {SECURE_MODE, ENC | DEC, H264 | HEVC | VP9 | AV1, + {0}, + NULL, + msm_vidc_set_u32}, + + {META_OUTPUT_TX_FENCE, DEC, H264 | HEVC | AV1 | VP9, + {0}, + NULL, + NULL}, + + {HFLIP, ENC, CODECS_ALL, + {0}, + NULL, + msm_vidc_set_flip}, + + {VFLIP, ENC, CODECS_ALL, + {0}, + NULL, + msm_vidc_set_flip}, + + {ROTATION, ENC, CODECS_ALL, + {0}, + NULL, + msm_vidc_set_rotation}, + + {SUPER_FRAME, ENC, H264 | HEVC, + {INPUT_BUF_HOST_MAX_COUNT, OUTPUT_BUF_HOST_MAX_COUNT}, + NULL, + NULL}, + + {SLICE_DECODE, DEC, H264 | HEVC | AV1, + {0}, + NULL, + NULL}, + + {HEADER_MODE, ENC, CODECS_ALL, + {0}, + NULL, + msm_vidc_set_header_mode}, + + {WITHOUT_STARTCODE, ENC, CODECS_ALL, + {0}, + NULL, + msm_vidc_set_nal_length}, + + {WITHOUT_STARTCODE, DEC, AV1, + {0}, + NULL, + msm_vidc_set_u32}, + + {REQUEST_I_FRAME, ENC, H264 | HEVC, + {0}, + NULL, + msm_vidc_set_req_sync_frame}, + + {BIT_RATE, ENC, H264, + {PEAK_BITRATE, BITRATE_BOOST, L0_BR, LEVEL}, + msm_vidc_adjust_bitrate, + msm_vidc_set_bitrate}, + + {BIT_RATE, ENC, HEVC, + {PEAK_BITRATE, BITRATE_BOOST, L0_BR, LEVEL}, + msm_vidc_adjust_bitrate, + msm_vidc_set_bitrate}, + + {BITRATE_MODE, ENC, H264, + {LTR_COUNT, IR_PERIOD, TIME_DELTA_BASED_RC, I_FRAME_QP, + P_FRAME_QP, B_FRAME_QP, ENH_LAYER_COUNT, BIT_RATE, + META_ROI_INFO, MIN_QUALITY, BITRATE_BOOST, VBV_DELAY, + PEAK_BITRATE, SLICE_MODE, CONTENT_ADAPTIVE_CODING, + BLUR_TYPES, LOWLATENCY_MODE, META_TRANSCODING_STAT_INFO}, + msm_vidc_adjust_bitrate_mode, + msm_vidc_set_u32_enum}, + + {BITRATE_MODE, ENC, HEVC, + {LTR_COUNT, IR_PERIOD, TIME_DELTA_BASED_RC, I_FRAME_QP, + P_FRAME_QP, B_FRAME_QP, CONSTANT_QUALITY, ENH_LAYER_COUNT, + BIT_RATE, META_ROI_INFO, MIN_QUALITY, BITRATE_BOOST, VBV_DELAY, + PEAK_BITRATE, SLICE_MODE, CONTENT_ADAPTIVE_CODING, + BLUR_TYPES, LOWLATENCY_MODE, META_EVA_STATS, + META_TRANSCODING_STAT_INFO}, + msm_vidc_adjust_bitrate_mode, + msm_vidc_set_u32_enum}, + + {BITRATE_MODE, ENC, HEIC, + {TIME_DELTA_BASED_RC, CONSTANT_QUALITY}, + msm_vidc_adjust_bitrate_mode, + msm_vidc_set_u32_enum}, + + {CONSTANT_QUALITY, ENC, HEVC | HEIC, + {0}, + NULL, + msm_vidc_set_constant_quality}, + + {GOP_SIZE, ENC, CODECS_ALL, + {ALL_INTRA}, + msm_vidc_adjust_gop_size, + msm_vidc_set_gop_size}, + + {GOP_SIZE, ENC, HEIC, + {0}, + NULL, + msm_vidc_set_u32}, + + {B_FRAME, ENC, H264 | HEVC, + {ALL_INTRA}, + msm_vidc_adjust_b_frame, + msm_vidc_set_u32}, + + {B_FRAME, ENC, HEIC, + {0}, + NULL, + msm_vidc_set_u32}, + + {BLUR_TYPES, ENC, H264 | HEVC, + {BLUR_RESOLUTION}, + msm_vidc_adjust_blur_type, + msm_vidc_set_u32_enum}, + + {BLUR_RESOLUTION, ENC, H264 | HEVC, + {0}, + msm_vidc_adjust_blur_resolution, + msm_vidc_set_blur_resolution}, + + {CSC, ENC, CODECS_ALL, + {CSC_CUSTOM_MATRIX}, + msm_vidc_adjust_csc, + msm_vidc_set_u32}, + + {CSC_CUSTOM_MATRIX, ENC, CODECS_ALL, + {0}, + msm_vidc_adjust_csc_custom_matrix, + msm_vidc_set_csc_custom_matrix}, + + {LOWLATENCY_MODE, ENC, H264 | HEVC, + {STAGE, BIT_RATE}, + msm_vidc_adjust_enc_lowlatency_mode, + NULL}, + + {LOWLATENCY_MODE, DEC, H264 | HEVC | VP9 | AV1, + {STAGE}, + NULL, + NULL}, + + {LTR_COUNT, ENC, H264 | HEVC, + {0}, + msm_vidc_adjust_ltr_count, + msm_vidc_set_u32}, + + {USE_LTR, ENC, H264 | HEVC, + {0}, + msm_vidc_adjust_use_ltr, + msm_vidc_set_use_and_mark_ltr}, + + {MARK_LTR, ENC, H264 | HEVC, + {0}, + msm_vidc_adjust_mark_ltr, + msm_vidc_set_use_and_mark_ltr}, + + {IR_PERIOD, ENC, H264 | HEVC, + {0}, + msm_vidc_adjust_ir_period, + msm_vidc_set_ir_period}, + + {AU_DELIMITER, ENC, H264 | HEVC, + {0}, + NULL, + msm_vidc_set_u32}, + + {BASELAYER_PRIORITY, ENC, H264, + {0}, + NULL, + msm_vidc_set_u32}, + + {TIME_DELTA_BASED_RC, ENC, CODECS_ALL, + {0}, + msm_vidc_adjust_delta_based_rc, + msm_vidc_set_u32}, + + {CONTENT_ADAPTIVE_CODING, ENC, H264 | HEVC, + {REQUEST_PREPROCESS}, + msm_vidc_adjust_brs, + msm_vidc_set_vbr_related_properties}, + + {REQUEST_PREPROCESS, ENC, H264 | HEVC, + {0}, + msm_vidc_adjust_preprocess, + msm_vidc_set_preprocess}, + + {BITRATE_BOOST, ENC, H264 | HEVC, + {LEVEL}, + msm_vidc_adjust_bitrate_boost_iris36, + msm_vidc_set_vbr_related_properties}, + + {MIN_QUALITY, ENC, H264 | HEVC, + {BLUR_TYPES}, + msm_vidc_adjust_min_quality, + msm_vidc_set_u32}, + + {VBV_DELAY, ENC, H264 | HEVC, + {0}, + NULL, + msm_vidc_set_cbr_related_properties}, + + {PEAK_BITRATE, ENC, H264 | HEVC, + {0}, + msm_vidc_adjust_peak_bitrate, + msm_vidc_set_cbr_related_properties}, + + {MIN_FRAME_QP, ENC, H264, + {0}, + NULL, + msm_vidc_set_min_qp}, + + {MIN_FRAME_QP, ENC, HEVC, + {0}, + msm_vidc_adjust_hevc_min_qp, + msm_vidc_set_min_qp}, + + {MAX_FRAME_QP, ENC, H264, + {0}, + NULL, + msm_vidc_set_max_qp}, + + {MAX_FRAME_QP, ENC, HEVC, + {0}, + msm_vidc_adjust_hevc_max_qp, + msm_vidc_set_max_qp}, + + {I_FRAME_QP, ENC, HEVC, + {0}, + msm_vidc_adjust_hevc_i_frame_qp, + msm_vidc_set_frame_qp}, + + {I_FRAME_QP, ENC, H264, + {0}, + NULL, + msm_vidc_set_frame_qp}, + + {P_FRAME_QP, ENC, HEVC, + {0}, + msm_vidc_adjust_hevc_p_frame_qp, + msm_vidc_set_frame_qp}, + + {P_FRAME_QP, ENC, H264, + {0}, + NULL, + msm_vidc_set_frame_qp}, + + {B_FRAME_QP, ENC, HEVC, + {0}, + msm_vidc_adjust_hevc_b_frame_qp, + msm_vidc_set_frame_qp}, + + {B_FRAME_QP, ENC, H264, + {0}, + NULL, + msm_vidc_set_frame_qp}, + + {LAYER_TYPE, ENC, H264, + {CONTENT_ADAPTIVE_CODING, LTR_COUNT, LEVEL}}, + + {LAYER_TYPE, ENC, HEVC, + {CONTENT_ADAPTIVE_CODING, LTR_COUNT, OPEN_GOP}}, + + {LAYER_ENABLE, ENC, H264 | HEVC, + {CONTENT_ADAPTIVE_CODING, LEVEL}}, + + {ENH_LAYER_COUNT, ENC, H264, + {GOP_SIZE, B_FRAME, BIT_RATE, MIN_QUALITY, SLICE_MODE, LTR_COUNT, LEVEL}, + msm_vidc_adjust_layer_count, + msm_vidc_set_layer_count_and_type}, + + {ENH_LAYER_COUNT, ENC, HEVC, + {GOP_SIZE, B_FRAME, BIT_RATE, MIN_QUALITY, SLICE_MODE, LTR_COUNT}, + msm_vidc_adjust_layer_count, + msm_vidc_set_layer_count_and_type}, + + {ENH_LAYER_COUNT, DEC, AV1, + {0}, + NULL, + msm_vidc_set_u32}, + + {L0_BR, ENC, H264 | HEVC, + {L1_BR}, + msm_vidc_adjust_layer_bitrate, + msm_vidc_set_layer_bitrate}, + + {L1_BR, ENC, H264 | HEVC, + {L2_BR}, + msm_vidc_adjust_layer_bitrate, + msm_vidc_set_layer_bitrate}, + + {L2_BR, ENC, H264 | HEVC, + {L3_BR}, + msm_vidc_adjust_layer_bitrate, + msm_vidc_set_layer_bitrate}, + + {L3_BR, ENC, H264 | HEVC, + {L4_BR}, + msm_vidc_adjust_layer_bitrate, + msm_vidc_set_layer_bitrate}, + + {L4_BR, ENC, H264 | HEVC, + {L5_BR}, + msm_vidc_adjust_layer_bitrate, + msm_vidc_set_layer_bitrate}, + + {L5_BR, ENC, H264 | HEVC, + {0}, + msm_vidc_adjust_layer_bitrate, + msm_vidc_set_layer_bitrate}, + + {ENTROPY_MODE, ENC, H264, + {BIT_RATE}, + msm_vidc_adjust_entropy_mode, + msm_vidc_set_u32}, + + {PROFILE, ENC, H264, + {ENTROPY_MODE, TRANSFORM_8X8}, + NULL, + msm_vidc_set_u32_enum}, + + {PROFILE, DEC, H264, + {ENTROPY_MODE}, + NULL, + msm_vidc_set_u32_enum}, + + {PROFILE, ENC, HEVC | HEIC, + {META_SEI_MASTERING_DISP, META_SEI_CLL, META_HDR10PLUS}, + msm_vidc_adjust_profile, + msm_vidc_set_u32_enum}, + + {PROFILE, DEC, HEVC | HEIC, + {0}, + msm_vidc_adjust_profile, + msm_vidc_set_u32_enum}, + + {PROFILE, DEC, VP9 | AV1, + {0}, + NULL, + msm_vidc_set_u32_enum}, + + {LEVEL, DEC, CODECS_ALL, + {0}, + NULL, + msm_vidc_set_u32_enum}, + + {LEVEL, ENC, H264 | HEVC, + {0}, + msm_vidc_adjust_level_tier, + msm_vidc_set_level}, + + {LEVEL, ENC, HEIC, + {0}, + NULL, + msm_vidc_set_level}, + + {AV1_TIER, DEC, AV1, + {0}, + NULL, + msm_vidc_set_u32_enum}, + + {HEVC_TIER, ENC | DEC, HEVC | HEIC, + {0}, + NULL, + msm_vidc_set_u32_enum}, + + {LF_MODE, ENC, CODECS_ALL, + {0}, + NULL, + msm_vidc_set_deblock_mode}, + + {SLICE_MODE, ENC, H264 | HEVC, + {STAGE, DELIVERY_MODE}, + msm_vidc_adjust_slice_count, + msm_vidc_set_slice_count}, + + {SLICE_MODE, ENC, HEIC, + {0}, + msm_vidc_adjust_slice_count, + msm_vidc_set_slice_count}, + + {TRANSFORM_8X8, ENC, H264, + {0}, + msm_vidc_adjust_transform_8x8, + msm_vidc_set_u32}, + + {CHROMA_QP_INDEX_OFFSET, ENC, HEVC, + {0}, + msm_vidc_adjust_chroma_qp_index_offset, + msm_vidc_set_chroma_qp_index_offset}, + + {DISPLAY_DELAY_ENABLE, DEC, H264 | HEVC | VP9 | AV1, + {OUTPUT_ORDER}, + NULL, + NULL}, + + {DISPLAY_DELAY, DEC, H264 | HEVC | VP9 | AV1, + {OUTPUT_ORDER}, + NULL, + NULL}, + + {OUTPUT_ORDER, DEC, H264 | HEVC | AV1 | VP9, + {0}, + msm_vidc_adjust_output_order, + msm_vidc_set_u32}, + + {INPUT_BUF_HOST_MAX_COUNT, ENC | DEC, CODECS_ALL, + {0}, + msm_vidc_adjust_input_buf_host_max_count, + msm_vidc_set_u32}, + + {INPUT_BUF_HOST_MAX_COUNT, ENC, H264 | HEVC, + {0}, + msm_vidc_adjust_input_buf_host_max_count, + msm_vidc_set_u32}, + + {OUTPUT_BUF_HOST_MAX_COUNT, ENC | DEC, CODECS_ALL, + {0}, + msm_vidc_adjust_output_buf_host_max_count, + msm_vidc_set_u32}, + + {OUTPUT_BUF_HOST_MAX_COUNT, ENC, H264 | HEVC, + {0}, + msm_vidc_adjust_output_buf_host_max_count, + msm_vidc_set_u32}, + + {CONCEAL_COLOR_8BIT, DEC, CODECS_ALL, + {0}, + NULL, + msm_vidc_set_conceal_color}, + + {CONCEAL_COLOR_10BIT, DEC, CODECS_ALL, + {0}, + NULL, + msm_vidc_set_conceal_color}, + + {STAGE, ENC | DEC, CODECS_ALL, + {0}, + NULL, + msm_vidc_set_stage}, + + {STAGE, ENC, H264 | HEVC, + {0}, + NULL, + msm_vidc_set_stage}, + + {STAGE, DEC, H264 | HEVC | VP9 | AV1, + {0}, + NULL, + msm_vidc_set_stage}, + + {PIPE, DEC | ENC, CODECS_ALL, + {0}, + NULL, + msm_vidc_set_pipe}, + + {THUMBNAIL_MODE, DEC, H264 | HEVC | VP9 | AV1, + {OUTPUT_ORDER}, + NULL, + msm_vidc_set_u32}, + + {THUMBNAIL_MODE, DEC, HEIC, + {0}, + NULL, + msm_vidc_set_u32}, + + {RAP_FRAME, DEC, CODECS_ALL, + {0}, + NULL, + msm_vidc_set_u32}, + + {PRIORITY, DEC | ENC, CODECS_ALL, + {0}, + msm_vidc_adjust_session_priority, + msm_vidc_set_session_priority}, + + {FIRMWARE_PRIORITY_OFFSET, DEC | ENC, CODECS_ALL, + {0}, + NULL, + NULL}, + + {CRITICAL_PRIORITY, ENC, CODECS_ALL, + {0}, + NULL, + NULL}, + + {RESERVE_DURATION, ENC, CODECS_ALL, + {0}, + NULL, + msm_vidc_set_reserve_duration}, + + {DPB_LIST, DEC, CODECS_ALL, + {0}, + {0}, + NULL, + NULL}, + + {DRAP, DEC, AV1, + {0}, + NULL, + msm_vidc_set_u32}, + + {ALL_INTRA, ENC, H264 | HEVC, + {LTR_COUNT, IR_PERIOD, SLICE_MODE, BIT_RATE}, + msm_vidc_adjust_all_intra, + NULL}, + + {META_EVA_STATS, ENC, HEVC, + {0}, + msm_vidc_adjust_eva_stats, + NULL}, + + {META_ROI_INFO, ENC, H264 | HEVC, + {MIN_QUALITY, IR_PERIOD, BLUR_TYPES}, + msm_vidc_adjust_roi_info, + NULL}, + + {GRID_ENABLE, ENC, HEIC, + {0}, + NULL, + msm_vidc_set_u32}, + + {DELIVERY_MODE, ENC, H264 | HEVC, + {LOWLATENCY_MODE, OUTPUT_BUF_HOST_MAX_COUNT}, + msm_vidc_adjust_delivery_mode, + msm_vidc_set_u32}, + + {VUI_TIMING_INFO, ENC, CODECS_ALL, + {0}, + NULL, + msm_vidc_set_vui_timing_info}, + + {SIGNAL_COLOR_INFO, ENC, CODECS_ALL, + {0}, + NULL, + msm_vidc_set_signal_color_info}, + + {META_SEI_MASTERING_DISP, ENC, HEVC | HEIC, + {0}, + msm_vidc_adjust_sei_mastering_disp, + NULL}, + + {META_SEI_CLL, ENC, HEVC | HEIC, + {0}, + msm_vidc_adjust_sei_cll, + NULL}, + + {META_HDR10PLUS, ENC, HEVC | HEIC, + {0}, + msm_vidc_adjust_hdr10plus, + NULL}, + + {META_TRANSCODING_STAT_INFO, ENC, HEVC | H264, + {0}, + msm_vidc_adjust_transcoding_stats, + NULL}, +}; + +/* Default UBWC config for LPDDR5 */ +static struct msm_vidc_ubwc_config_data ubwc_config_glymur[] = { + UBWC_CONFIG(8, 32, 13, 0, 0, 1, 1), +}; + +static struct msm_vidc_format_capability format_data_glymur = { + .codec_info = codec_data_glymur, + .codec_info_size = ARRAY_SIZE(codec_data_glymur), + .color_format_info = color_format_data_glymur, + .color_format_info_size = ARRAY_SIZE(color_format_data_glymur), + .color_prim_info = color_primaries_data_glymur, + .color_prim_info_size = ARRAY_SIZE(color_primaries_data_glymur), + .transfer_char_info = transfer_char_data_glymur, + .transfer_char_info_size = ARRAY_SIZE(transfer_char_data_glymur), + .matrix_coeff_info = matrix_coeff_data_glymur, + .matrix_coeff_info_size = ARRAY_SIZE(matrix_coeff_data_glymur), +}; + +/* name, min_kbps, max_kbps */ +static const struct bw_table glymur_bw_table[] = { + { "cpu-cfg", 1000, 1000 }, + { "video-mem", 1000, 15000000 }, + { "venus-llcc", 1000, 15000000 }, +}; + +/* name, hw_trigger, hw_enable */ +static struct pd_table glymur_pd_table[] = { + { "venus", 0, 1 }, + { "vcodec0", 1, 1 }, + { "vcodec1", 1, 1 }, +}; + +/* name */ +static const char * const glymur_opp_pd_table[] = { + "mxc", + "mmcx", + NULL +}; + +/* name, clock id, scaling */ +static const struct clk_table glymur_clk_table[] = { + { "core_iface", GCC_VIDEO_AXI0C_CLK, 0 }, + { "core", VIDEO_CC_MVS0C_CLK, 0 }, + { "vcodec0_core", VIDEO_CC_MVS0_CLK, 1, + (u64[]) {655000000, 533333334, 444000000, 366000000, 338000000, 240000000}, 6}, + { "vcodec0_iface", GCC_VIDEO_AXI0_CLK, 0 }, + { "core_freerun", VIDEO_CC_MVS0C_FREERUN_CLK, 0 }, + { "vcodec0_core_freerun", VIDEO_CC_MVS0_FREERUN_CLK, 0 }, + { "vcodec1_iface", GCC_VIDEO_AXI1_CLK, 0 }, + { "vcodec1_core", VIDEO_CC_MVS1_CLK, 1, + (u64[]) {655000000, 533333334, 444000000, 366000000, 338000000, 240000000}, 6}, + { "vcodec1_core_freerun", VIDEO_CC_MVS1_FREERUN_CLK, 0 }, +}; + +const char * const glymur_opp_clk_table[] = { + "vcodec0_core", + "vcodec1_core", + "core", + NULL, +}; + +/* name, exclusive_release */ +static const struct clk_rst_table glymur_clk_reset_table[] = { + { "core_bus", 0 }, + { "vcodec0_bus", 0 }, + { "core", 0 }, + { "vcodec0_core", 0 }, + { "vcodec1_bus", 0 }, + { "vcodec1_core", 0 }, +}; + +/* name, llcc_id */ +static const struct subcache_table glymur_subcache_table[] = { + { "vidsc0", LLCC_VIDSC0 }, + { "vidvsp", LLCC_VIDVSP }, +}; + +/* name, start, size, secure, dma_coherant, region, dma_mask */ +const struct context_bank_table glymur_context_bank_table[] = { + {"qcom,vidc,cb-ns", 0x25800000, 0xda600000, 0, 1, + MSM_VIDC_NON_SECURE | MSM_VIDC_NON_SECURE_BITSTREAM, 0 }, + {"qcom,vidc,cb-ns-pxl", 0x00200000, 0xffc00000, 0, 1, MSM_VIDC_NON_SECURE_PIXEL, 0 }, + {"qcom,vidc,cb-sec-pxl", 0x00200000, 0xffc00000, 1, 0, MSM_VIDC_SECURE_PIXEL, 0 }, + {"qcom,vidc,cb-sec-non-pxl", 0x01000000, 0x24800000, 1, 0, MSM_VIDC_SECURE_NONPIXEL, 0 }, + {"qcom,vidc,cb-sec-bitstream", 0x00500000, 0xdfb00000, 1, 0, MSM_VIDC_SECURE_BITSTREAM, 0 }, + {"qcom,vidc,cb-firmware", 0x00000000, 0x01000000, 1, 0, MSM_VIDC_SECURE_FIRMWARE, 0 }, +}; + +/* register, value, mask */ +static const struct reg_preset_table glymur_reg_preset_table[] = { + { 0xB0088, 0x0, 0x3f }, +}; + +/* name, phys_addr, size, device_addr, device region type */ +static const struct device_region_table glymur_device_region_table[] = { + { + "aon-registers", + 0x0AAE0000, 0x1000, 0xFFAE0000, + MSM_VIDC_AON + }, + { + "qtimer_f0v1_qtmr_v1_cntpct_lo", + 0x17421000, 0x1000, 0xFFADE000, + MSM_VIDC_QTIMER + }, +}; + +/* decoder properties */ +static const u32 glymur_vdec_psc_avc[] = { + HFI_PROP_BITSTREAM_RESOLUTION, + HFI_PROP_CROP_OFFSETS, + HFI_PROP_CODED_FRAMES, + HFI_PROP_BUFFER_FW_MIN_OUTPUT_COUNT, + HFI_PROP_PIC_ORDER_CNT_TYPE, + HFI_PROP_PROFILE, + HFI_PROP_LEVEL, + HFI_PROP_SIGNAL_COLOR_INFO, + HFI_PROP_MAX_NUM_REORDER_FRAMES, +}; + +static const u32 glymur_vdec_psc_hevc[] = { + HFI_PROP_BITSTREAM_RESOLUTION, + HFI_PROP_CROP_OFFSETS, + HFI_PROP_LUMA_CHROMA_BIT_DEPTH, + HFI_PROP_BUFFER_FW_MIN_OUTPUT_COUNT, + HFI_PROP_PROFILE, + HFI_PROP_LEVEL, + HFI_PROP_TIER, + HFI_PROP_SIGNAL_COLOR_INFO, + HFI_PROP_MAX_NUM_REORDER_FRAMES, +}; + +static const u32 glymur_vdec_psc_vp9[] = { + HFI_PROP_BITSTREAM_RESOLUTION, + HFI_PROP_CROP_OFFSETS, + HFI_PROP_LUMA_CHROMA_BIT_DEPTH, + HFI_PROP_BUFFER_FW_MIN_OUTPUT_COUNT, + HFI_PROP_PROFILE, + HFI_PROP_LEVEL, +}; + +static const u32 glymur_vdec_psc_av1[] = { + HFI_PROP_BITSTREAM_RESOLUTION, + HFI_PROP_CROP_OFFSETS, + HFI_PROP_LUMA_CHROMA_BIT_DEPTH, + HFI_PROP_BUFFER_FW_MIN_OUTPUT_COUNT, + HFI_PROP_AV1_FILM_GRAIN_PRESENT, + HFI_PROP_AV1_SUPER_BLOCK_ENABLED, + HFI_PROP_PROFILE, + HFI_PROP_LEVEL, + HFI_PROP_TIER, + HFI_PROP_SIGNAL_COLOR_INFO, +}; + +static const u32 glymur_vdec_psc_mpeg2[] = { + HFI_PROP_BITSTREAM_RESOLUTION, + HFI_PROP_CROP_OFFSETS, + HFI_PROP_LUMA_CHROMA_BIT_DEPTH, + HFI_PROP_CODED_FRAMES, + HFI_PROP_BUFFER_FW_MIN_OUTPUT_COUNT, + HFI_PROP_PROFILE, + HFI_PROP_LEVEL, +}; + +static const u32 glymur_vdec_input_properties_avc[] = { + HFI_PROP_NO_OUTPUT, + HFI_PROP_SUBFRAME_INPUT, +}; + +static const u32 glymur_vdec_input_properties_hevc[] = { + HFI_PROP_NO_OUTPUT, + HFI_PROP_SUBFRAME_INPUT, +}; + +static const u32 glymur_vdec_input_properties_vp9[] = { + HFI_PROP_NO_OUTPUT, + HFI_PROP_SUBFRAME_INPUT, +}; + +static const u32 glymur_vdec_input_properties_av1[] = { + HFI_PROP_NO_OUTPUT, + HFI_PROP_SUBFRAME_INPUT, + HFI_PROP_AV1_TILE_ROWS_COLUMNS, + HFI_PROP_AV1_UNIFORM_TILE_SPACING, +}; + +static const u32 glymur_vdec_input_properties_mpeg2[] = { + HFI_PROP_NO_OUTPUT, + HFI_PROP_SUBFRAME_INPUT, +}; + +static const u32 glymur_vdec_output_properties_avc[] = { + HFI_PROP_WORST_COMPRESSION_RATIO, + HFI_PROP_WORST_COMPLEXITY_FACTOR, + HFI_PROP_PICTURE_TYPE, + HFI_PROP_DPB_LIST, + HFI_PROP_CABAC_SESSION, + HFI_PROP_FENCE, +}; + +static const u32 glymur_vdec_output_properties_hevc[] = { + HFI_PROP_WORST_COMPRESSION_RATIO, + HFI_PROP_WORST_COMPLEXITY_FACTOR, + HFI_PROP_PICTURE_TYPE, + HFI_PROP_DPB_LIST, + HFI_PROP_FENCE, +}; + +static const u32 glymur_vdec_output_properties_vp9[] = { + HFI_PROP_WORST_COMPRESSION_RATIO, + HFI_PROP_WORST_COMPLEXITY_FACTOR, + HFI_PROP_PICTURE_TYPE, + HFI_PROP_DPB_LIST, + HFI_PROP_FENCE, +}; + +static const u32 glymur_vdec_output_properties_av1[] = { + HFI_PROP_WORST_COMPRESSION_RATIO, + HFI_PROP_WORST_COMPLEXITY_FACTOR, + HFI_PROP_PICTURE_TYPE, + HFI_PROP_DPB_LIST, + HFI_PROP_FENCE, +}; + +static const u32 glymur_vdec_output_properties_mpeg2[] = { + HFI_PROP_WORST_COMPRESSION_RATIO, + HFI_PROP_WORST_COMPLEXITY_FACTOR, + HFI_PROP_PICTURE_TYPE, + HFI_PROP_DPB_LIST, + HFI_PROP_FENCE, +}; + +static const u32 glymur_msm_vidc_ssr_type[] = { + HFI_SSR_TYPE_SW_ERR_FATAL, +}; + +static const struct msm_vidc_platform_data glymur_data = { + /* resources dependent on other module */ + .bw_tbl = glymur_bw_table, + .bw_tbl_size = ARRAY_SIZE(glymur_bw_table), + .pd_tbl = glymur_pd_table, + .pd_tbl_size = ARRAY_SIZE(glymur_pd_table), + .gdsc_hw_ctrl_by_default = 1, + .opp_tbl = glymur_opp_pd_table, + .opp_tbl_size = ARRAY_SIZE(glymur_opp_pd_table), + .clk_tbl = glymur_clk_table, + .clk_tbl_size = ARRAY_SIZE(glymur_clk_table), + .opp_clk_tbl = glymur_opp_clk_table, + .clk_rst_tbl = glymur_clk_reset_table, + .clk_rst_tbl_size = ARRAY_SIZE(glymur_clk_reset_table), + .subcache_tbl = glymur_subcache_table, + .subcache_tbl_size = ARRAY_SIZE(glymur_subcache_table), + + /* populate context bank */ + .context_bank_tbl = glymur_context_bank_table, + .context_bank_tbl_size = ARRAY_SIZE(glymur_context_bank_table), + + /* platform specific resources */ + .reg_prst_tbl = glymur_reg_preset_table, + .reg_prst_tbl_size = ARRAY_SIZE(glymur_reg_preset_table), + .dev_reg_tbl = glymur_device_region_table, + .dev_reg_tbl_size = ARRAY_SIZE(glymur_device_region_table), + .clock_source_scaling_ratio = 3, + .fwname = "vpu36_p4_s7.mbn", + .num_cores = 2, + .pas_id = 9, + .supports_mmrm = 1, + + /* caps related resorces */ + .core_data = core_data_glymur, + .core_data_size = ARRAY_SIZE(core_data_glymur), + .inst_cap_data = instance_cap_data_glymur, + .inst_cap_data_size = ARRAY_SIZE(instance_cap_data_glymur), + .inst_cap_dependency_data = instance_cap_dependency_data_glymur, + .inst_cap_dependency_data_size = ARRAY_SIZE(instance_cap_dependency_data_glymur), + .csc_data.vpe_csc_custom_bias_coeff = vpe_csc_custom_bias_coeff, + .csc_data.vpe_csc_custom_matrix_coeff = vpe_csc_custom_matrix_coeff, + .csc_data.vpe_csc_custom_limit_coeff = vpe_csc_custom_limit_coeff, + .ubwc_config = ubwc_config_glymur, + .format_data = &format_data_glymur, + + /* decoder properties related*/ + .psc_avc_tbl = glymur_vdec_psc_avc, + .psc_avc_tbl_size = ARRAY_SIZE(glymur_vdec_psc_avc), + .psc_hevc_tbl = glymur_vdec_psc_hevc, + .psc_hevc_tbl_size = ARRAY_SIZE(glymur_vdec_psc_hevc), + .psc_vp9_tbl = glymur_vdec_psc_vp9, + .psc_vp9_tbl_size = ARRAY_SIZE(glymur_vdec_psc_vp9), + .psc_av1_tbl = glymur_vdec_psc_av1, + .psc_av1_tbl_size = ARRAY_SIZE(glymur_vdec_psc_av1), + .psc_mpeg2_tbl = glymur_vdec_psc_mpeg2, + .psc_mpeg2_tbl_size = ARRAY_SIZE(glymur_vdec_psc_mpeg2), + .dec_input_prop_avc = glymur_vdec_input_properties_avc, + .dec_input_prop_hevc = glymur_vdec_input_properties_hevc, + .dec_input_prop_vp9 = glymur_vdec_input_properties_vp9, + .dec_input_prop_av1 = glymur_vdec_input_properties_av1, + .dec_input_prop_mpeg2 = glymur_vdec_input_properties_mpeg2, + .dec_input_prop_size_avc = ARRAY_SIZE(glymur_vdec_input_properties_avc), + .dec_input_prop_size_hevc = ARRAY_SIZE(glymur_vdec_input_properties_hevc), + .dec_input_prop_size_vp9 = ARRAY_SIZE(glymur_vdec_input_properties_vp9), + .dec_input_prop_size_av1 = ARRAY_SIZE(glymur_vdec_input_properties_av1), + .dec_input_prop_size_mpeg2 = ARRAY_SIZE(glymur_vdec_input_properties_mpeg2), + .dec_output_prop_avc = glymur_vdec_output_properties_avc, + .dec_output_prop_hevc = glymur_vdec_output_properties_hevc, + .dec_output_prop_vp9 = glymur_vdec_output_properties_vp9, + .dec_output_prop_av1 = glymur_vdec_output_properties_av1, + .dec_output_prop_mpeg2 = glymur_vdec_output_properties_mpeg2, + .dec_output_prop_size_avc = ARRAY_SIZE(glymur_vdec_output_properties_avc), + .dec_output_prop_size_hevc = ARRAY_SIZE(glymur_vdec_output_properties_hevc), + .dec_output_prop_size_vp9 = ARRAY_SIZE(glymur_vdec_output_properties_vp9), + .dec_output_prop_size_av1 = ARRAY_SIZE(glymur_vdec_output_properties_av1), + .dec_output_prop_size_mpeg2 = ARRAY_SIZE(glymur_vdec_output_properties_mpeg2), + .msm_vidc_ssr_type = glymur_msm_vidc_ssr_type, + .msm_vidc_ssr_type_size = ARRAY_SIZE(glymur_msm_vidc_ssr_type), +}; + +static int msm_vidc_glymur_check_ddr_type(void) +{ + u32 ddr_type; + + ddr_type = of_fdt_get_ddrtype(); + if (ddr_type != DDR_TYPE_LPDDR5 && + ddr_type != DDR_TYPE_LPDDR5X) { + d_vpr_e("%s: wrong ddr type %d\n", __func__, ddr_type); + return -EINVAL; + } + + return 0; +} + +int msm_vidc_get_platform_data_glymur(struct msm_vidc_core *core) +{ + d_vpr_h("%s: initialize glymur data\n", __func__); + core->platform->data = glymur_data; + + return 0; +} + +int msm_vidc_init_platform_glymur(struct msm_vidc_core *core) +{ + int rc = 0; + + d_vpr_h("%s: initialize glymur ops\n", __func__); + core->mem_ops = get_mem_ops_ext(); + if (!core->mem_ops) { + d_vpr_e("%s: invalid memory ext ops\n", __func__); + return -EINVAL; + } + core->res_ops = get_res_ops_ext(core); + if (!core->res_ops) { + d_vpr_e("%s: invalid resource ext ops\n", __func__); + return -EINVAL; + } + rc = msm_vidc_glymur_check_ddr_type(); + if (rc) + return rc; + + return rc; +} From 117127cd9e72f9049c25af0556515bd11184fbe2 Mon Sep 17 00:00:00 2001 From: Vishnu Reddy Date: Wed, 1 Jul 2026 18:02:08 +0530 Subject: [PATCH 07/10] iris: add mainline platform data support for glymur Add the mainline specific platform configuration required by the video driver for glymur targets, including hardware capabilities, resource definitions, format mappings, and platform initialization hooks. Signed-off-by: Vishnu Reddy --- driver/platform/glymur/src/glymur.c | 2223 +++++++++++++++++++++++++++ 1 file changed, 2223 insertions(+) create mode 100644 driver/platform/glymur/src/glymur.c diff --git a/driver/platform/glymur/src/glymur.c b/driver/platform/glymur/src/glymur.c new file mode 100644 index 000000000..e9d8cc12d --- /dev/null +++ b/driver/platform/glymur/src/glymur.c @@ -0,0 +1,2223 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include + +#include "msm_vidc_internal.h" +#include "msm_vidc_inst.h" +#include "msm_vidc_control.h" +#include "msm_vidc_glymur.h" +#include "msm_vidc_platform.h" +#include "msm_vidc_debug.h" +#include "msm_vidc_iris36.h" +#include "hfi_property.h" +#include "hfi_command.h" +#include "venus_hfi.h" +#include "msm_vidc_driver.h" +#include "resources.h" + +#define DEFAULT_VIDEO_CONCEAL_COLOR_BLACK 0x8000800010 +#define MAX_BASE_LAYER_PRIORITY_ID 63 +#define MAX_OP_POINT 31 +#define MAX_BITRATE 245000000 +#define DEFAULT_BITRATE 20000000 +#define MINIMUM_FPS 1 +#define MAXIMUM_FPS 480 +#define MAX_QP 51 +#define DEFAULT_QP 20 +#define MAX_CONSTANT_QUALITY 100 +#define MIN_SLICE_BYTE_SIZE 512 +#define MAX_SLICE_BYTE_SIZE \ + ((MAX_BITRATE) >> 3) +#define MAX_SLICE_MB_SIZE \ + (((4096 + 15) >> 4) * ((2304 + 15) >> 4)) + +#define ENC MSM_VIDC_ENCODER +#define DEC MSM_VIDC_DECODER +#define H264 MSM_VIDC_H264 +#define HEVC MSM_VIDC_HEVC +#define VP9 MSM_VIDC_VP9 +#define AV1 MSM_VIDC_AV1 +#define CODECS_ALL (H264 | HEVC | VP9 | AV1) +#define MAXIMUM_OVERRIDE_VP9_FPS 180 + +#ifndef V4L2_PIX_FMT_QC08C +#define V4L2_PIX_FMT_QC08C v4l2_fourcc('Q', '0', '8', 'C') +#endif + +#ifndef V4L2_PIX_FMT_QC10C +#define V4L2_PIX_FMT_QC10C v4l2_fourcc('Q', '1', '0', 'C') +#endif + +static struct codec_info codec_data_glymur[] = { + { + .v4l2_codec = V4L2_PIX_FMT_H264, + .vidc_codec = MSM_VIDC_H264, + .pixfmt_name = "AVC", + }, + { + .v4l2_codec = V4L2_PIX_FMT_HEVC, + .vidc_codec = MSM_VIDC_HEVC, + .pixfmt_name = "HEVC", + }, + { + .v4l2_codec = V4L2_PIX_FMT_VP9, + .vidc_codec = MSM_VIDC_VP9, + .pixfmt_name = "VP9", + }, + { + .v4l2_codec = V4L2_PIX_FMT_AV1, + .vidc_codec = MSM_VIDC_AV1, + .pixfmt_name = "AV1", + }, +}; + +static struct color_format_info color_format_data_glymur[] = { + { + .v4l2_color_format = V4L2_PIX_FMT_NV12, + .vidc_color_format = MSM_VIDC_FMT_NV12, + .pixfmt_name = "NV12", + }, + { + .v4l2_color_format = V4L2_PIX_FMT_NV21, + .vidc_color_format = MSM_VIDC_FMT_NV21, + .pixfmt_name = "NV21", + }, + { + .v4l2_color_format = V4L2_PIX_FMT_QC08C, + .vidc_color_format = MSM_VIDC_FMT_NV12C, + .pixfmt_name = "NV12C", + }, + { + .v4l2_color_format = V4L2_PIX_FMT_QC10C, + .vidc_color_format = MSM_VIDC_FMT_TP10C, + .pixfmt_name = "TP10C", + }, + { + .v4l2_color_format = V4L2_PIX_FMT_RGBA32, + .vidc_color_format = MSM_VIDC_FMT_RGBA8888, + .pixfmt_name = "RGBA", + }, + { + .v4l2_color_format = V4L2_PIX_FMT_P010, + .vidc_color_format = MSM_VIDC_FMT_P010, + .pixfmt_name = "P010", + }, + { + .v4l2_color_format = V4L2_META_FMT_VIDC, + .vidc_color_format = MSM_VIDC_FMT_META, + .pixfmt_name = "META", + }, +}; + +static struct color_primaries_info color_primaries_data_glymur[] = { + { + .v4l2_color_primaries = V4L2_COLORSPACE_DEFAULT, + .vidc_color_primaries = MSM_VIDC_PRIMARIES_RESERVED, + }, + { + .v4l2_color_primaries = V4L2_COLORSPACE_DEFAULT, + .vidc_color_primaries = MSM_VIDC_PRIMARIES_UNSPECIFIED, + }, + { + .v4l2_color_primaries = V4L2_COLORSPACE_REC709, + .vidc_color_primaries = MSM_VIDC_PRIMARIES_BT709, + }, + { + .v4l2_color_primaries = V4L2_COLORSPACE_470_SYSTEM_M, + .vidc_color_primaries = MSM_VIDC_PRIMARIES_BT470_SYSTEM_M, + }, + { + .v4l2_color_primaries = V4L2_COLORSPACE_470_SYSTEM_BG, + .vidc_color_primaries = MSM_VIDC_PRIMARIES_BT470_SYSTEM_BG, + }, + { + .v4l2_color_primaries = V4L2_COLORSPACE_SMPTE170M, + .vidc_color_primaries = MSM_VIDC_PRIMARIES_BT601_525, + }, + { + .v4l2_color_primaries = V4L2_COLORSPACE_SMPTE240M, + .vidc_color_primaries = MSM_VIDC_PRIMARIES_SMPTE_ST240M, + }, + { + .v4l2_color_primaries = V4L2_COLORSPACE_BT2020, + .vidc_color_primaries = MSM_VIDC_PRIMARIES_BT2020, + }, + { + .v4l2_color_primaries = V4L2_COLORSPACE_DCI_P3, + .vidc_color_primaries = MSM_VIDC_PRIMARIES_SMPTE_RP431_2, + }, +}; + +static struct transfer_char_info transfer_char_data_glymur[] = { + { + .v4l2_transfer_char = V4L2_XFER_FUNC_DEFAULT, + .vidc_transfer_char = MSM_VIDC_TRANSFER_RESERVED, + }, + { + .v4l2_transfer_char = V4L2_XFER_FUNC_DEFAULT, + .vidc_transfer_char = MSM_VIDC_TRANSFER_UNSPECIFIED, + }, + { + .v4l2_transfer_char = V4L2_XFER_FUNC_709, + .vidc_transfer_char = MSM_VIDC_TRANSFER_BT709, + }, + { + .v4l2_transfer_char = V4L2_XFER_FUNC_SMPTE240M, + .vidc_transfer_char = MSM_VIDC_TRANSFER_SMPTE_ST240M, + }, + { + .v4l2_transfer_char = V4L2_XFER_FUNC_SRGB, + .vidc_transfer_char = MSM_VIDC_TRANSFER_SRGB_SYCC, + }, + { + .v4l2_transfer_char = V4L2_XFER_FUNC_SMPTE2084, + .vidc_transfer_char = MSM_VIDC_TRANSFER_SMPTE_ST2084_PQ, + }, +}; + +static struct matrix_coeff_info matrix_coeff_data_glymur[] = { + { + .v4l2_matrix_coeff = V4L2_YCBCR_ENC_DEFAULT, + .vidc_matrix_coeff = MSM_VIDC_MATRIX_COEFF_RESERVED, + }, + { + .v4l2_matrix_coeff = V4L2_YCBCR_ENC_DEFAULT, + .vidc_matrix_coeff = MSM_VIDC_MATRIX_COEFF_UNSPECIFIED, + }, + { + .v4l2_matrix_coeff = V4L2_YCBCR_ENC_709, + .vidc_matrix_coeff = MSM_VIDC_MATRIX_COEFF_BT709, + }, + { + .v4l2_matrix_coeff = V4L2_YCBCR_ENC_XV709, + .vidc_matrix_coeff = MSM_VIDC_MATRIX_COEFF_BT709, + }, + { + .v4l2_matrix_coeff = V4L2_YCBCR_ENC_XV601, + .vidc_matrix_coeff = MSM_VIDC_MATRIX_COEFF_BT470_SYS_BG_OR_BT601_625, + }, + { + .v4l2_matrix_coeff = V4L2_YCBCR_ENC_601, + .vidc_matrix_coeff = MSM_VIDC_MATRIX_COEFF_BT601_525_BT1358_525_OR_625, + }, + { + .v4l2_matrix_coeff = V4L2_YCBCR_ENC_SMPTE240M, + .vidc_matrix_coeff = MSM_VIDC_MATRIX_COEFF_SMPTE_ST240, + }, + { + .v4l2_matrix_coeff = V4L2_YCBCR_ENC_BT2020, + .vidc_matrix_coeff = MSM_VIDC_MATRIX_COEFF_BT2020_NON_CONSTANT, + }, + { + .v4l2_matrix_coeff = V4L2_YCBCR_ENC_BT2020_CONST_LUM, + .vidc_matrix_coeff = MSM_VIDC_MATRIX_COEFF_BT2020_CONSTANT, + }, +}; + +static const struct msm_platform_core_capability core_data_glymur[] = { + /* {type, value} */ + {ENC_CODECS, H264 | HEVC}, + {DEC_CODECS, H264 | HEVC | VP9 | AV1}, + {MAX_SESSION_COUNT, 32}, + {MAX_NUM_720P_SESSIONS, 32}, + {MAX_NUM_1080P_SESSIONS, 32}, + {MAX_NUM_4K_SESSIONS, 6}, + {MAX_NUM_8K_SESSIONS, 2}, + {MAX_RT_MBPF, 174080}, /* (8192x4352)/256 + (4096x2176)/256*/ + {MAX_MBPF, 278528}, /* ((8192x4352)/256) * 2 */ + {MAX_MBPS, 7833600}, + /* max_load + * 7680x4320@60fps or 3840x2176@240fps + * which is greater than 4096x2176@120fps, + * 8192x4320@48fps + */ + {MAX_MBPF_HQ, 8160}, /* ((1920x1088)/256) */ + {MAX_MBPS_HQ, 489600}, /* ((1920x1088)/256)@60fps */ + {MAX_MBPF_B_FRAME, 32640}, /* 3840x2176/256 */ + {MAX_MBPS_B_FRAME, 1958400}, /* 3840x2176/256 MBs@60fps */ + {MAX_MBPS_ALL_INTRA, 1044480}, /* 4096x2176/256 MBs@30fps */ + {MAX_ENH_LAYER_COUNT, 5}, + {NUM_VPP_PIPE, 4}, + {SW_PC, 1}, + {FW_UNLOAD, 0}, + {HW_RESPONSE_TIMEOUT, HW_RESPONSE_TIMEOUT_VALUE}, /* 1000 ms */ + {SW_PC_DELAY, SW_PC_DELAY_VALUE }, /* 1500 ms (>HW_RESPONSE_TIMEOUT)*/ + {FW_UNLOAD_DELAY, FW_UNLOAD_DELAY_VALUE }, /* 3000 ms (>SW_PC_DELAY)*/ + {DCVS, 0}, + {DECODE_BATCH, 0}, + {DECODE_BATCH_TIMEOUT, 200}, + {STATS_TIMEOUT_MS, 2000}, + {NON_FATAL_FAULTS, 1}, + {ENC_AUTO_FRAMERATE, 1}, + {DEVICE_CAPS, V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING}, + {SUPPORTS_REQUESTS, 0}, + {SKIP_DELAYED_UNMAP, 1}, +}; + +static struct msm_platform_inst_capability instance_cap_data_glymur[] = { + /* {cap, domain, codec, + * min, max, step_or_mask, value, + * v4l2_id, + * hfi_id, + * flags} + */ + + {FRAME_WIDTH, DEC, CODECS_ALL, 96, 8192, 1, 1920}, + + {FRAME_WIDTH, DEC, VP9, 96, 4096, 1, 1920}, + + {FRAME_WIDTH, ENC, CODECS_ALL, 128, 8192, 1, 1920}, + + {LOSSLESS_FRAME_WIDTH, ENC, CODECS_ALL, 128, 4096, 1, 1920}, + + {FRAME_HEIGHT, DEC, CODECS_ALL, 96, 8192, 1, 1080}, + + {FRAME_HEIGHT, DEC, VP9, 96, 4096, 1, 1080}, + + {FRAME_HEIGHT, ENC, CODECS_ALL, 128, 8192, 1, 1080}, + + {LOSSLESS_FRAME_HEIGHT, ENC, CODECS_ALL, 128, 4096, 1, 1080}, + + {PIX_FMTS, ENC | DEC, H264, + MSM_VIDC_FMT_NV12, + MSM_VIDC_FMT_NV12C, + MSM_VIDC_FMT_NV12 | MSM_VIDC_FMT_NV21 | MSM_VIDC_FMT_NV12C, + MSM_VIDC_FMT_NV12C}, + + {PIX_FMTS, ENC | DEC, HEVC | VP9 | AV1, + MSM_VIDC_FMT_NV12, + MSM_VIDC_FMT_TP10C, + MSM_VIDC_FMT_NV12 | MSM_VIDC_FMT_NV21 | MSM_VIDC_FMT_NV12C | + MSM_VIDC_FMT_TP10C, + MSM_VIDC_FMT_NV12C}, + + {MIN_BUFFERS_INPUT, ENC | DEC, CODECS_ALL, 0, 64, 1, 4, + V4L2_CID_MIN_BUFFERS_FOR_OUTPUT, + 0, + CAP_FLAG_VOLATILE}, + + {MIN_BUFFERS_OUTPUT, ENC | DEC, CODECS_ALL, + 0, 64, 1, 4, + V4L2_CID_MIN_BUFFERS_FOR_CAPTURE, + HFI_PROP_BUFFER_FW_MIN_OUTPUT_COUNT, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_VOLATILE}, + + /* (8192 * 4320) / 256 */ + {MBPF, ENC, CODECS_ALL, 64, 138240, 1, 138240}, + + {MBPF, ENC, HEVC, 36, 138240, 1, 138240}, + + {MBPF, DEC, CODECS_ALL, 36, 138240, 1, 138240}, + + /* (4096 * 2304) / 256 */ + {MBPF, DEC, VP9, 36, 36864, 1, 36864}, + + /* (4096 * 2304) / 256 */ + {LOSSLESS_MBPF, ENC, H264 | HEVC, 64, 36864, 1, 36864}, + + /* Batch Mode Decode */ + /* TODO: update with new values based on updated voltage corner */ + {BATCH_MBPF, DEC, H264 | HEVC | VP9 | AV1, 64, 34816, 1, 34816}, + + /* (4096 * 2304) / 256 */ + {BATCH_FPS, DEC, H264 | HEVC | VP9 | AV1, 1, 120, 1, 120}, + + {FRAME_RATE, ENC, CODECS_ALL, + (MINIMUM_FPS << 16), (MAXIMUM_FPS << 16), + 1, (DEFAULT_FPS << 16), + 0, + HFI_PROP_FRAME_RATE, + CAP_FLAG_OUTPUT_PORT}, + + {OPERATING_RATE, ENC, CODECS_ALL, + (MINIMUM_FPS << 16), INT_MAX, + 1, (DEFAULT_FPS << 16)}, + + {INPUT_RATE, ENC | DEC, CODECS_ALL, + (MINIMUM_FPS << 16), INT_MAX, + 1, (DEFAULT_FPS << 16)}, + + {TIMESTAMP_RATE, ENC | DEC, CODECS_ALL, + (MINIMUM_FPS << 16), INT_MAX, + 1, (DEFAULT_FPS << 16)}, + + {SCALE_FACTOR, ENC, H264 | HEVC, 1, 8, 1, 8}, + + {MB_CYCLES_VSP, ENC, CODECS_ALL, 25, 25, 1, 25}, + + {MB_CYCLES_VSP, DEC, CODECS_ALL, 25, 25, 1, 25}, + + {MB_CYCLES_VSP, DEC, VP9 | AV1, 60, 60, 1, 60}, + + {MB_CYCLES_VPP, ENC, CODECS_ALL, 675, 675, 1, 675}, + + {MB_CYCLES_VPP, DEC, CODECS_ALL, 200, 200, 1, 200}, + + {MB_CYCLES_LP, ENC, CODECS_ALL, 320, 320, 1, 320}, + + {MB_CYCLES_LP, DEC, CODECS_ALL, 200, 200, 1, 200}, + + {MB_CYCLES_FW, ENC | DEC, CODECS_ALL, 489583, 489583, 1, 489583}, + + {MB_CYCLES_FW_VPP, ENC, CODECS_ALL, 48405, 48405, 1, 48405}, + + {MB_CYCLES_FW_VPP, DEC, CODECS_ALL, 66234, 66234, 1, 66234}, + + {CLIENT_ID, ENC | DEC, CODECS_ALL, + INVALID_CLIENT_ID, INT_MAX, 1, INVALID_CLIENT_ID, + 0}, + + {HFLIP, ENC, CODECS_ALL, + 0, 1, 1, 0, + V4L2_CID_HFLIP, + HFI_PROP_FLIP, + CAP_FLAG_OUTPUT_PORT | + CAP_FLAG_INPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED}, + + {VFLIP, ENC, CODECS_ALL, + 0, 1, 1, 0, + V4L2_CID_VFLIP, + HFI_PROP_FLIP, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {ROTATION, ENC, CODECS_ALL, + 0, 270, 90, 0, + V4L2_CID_ROTATE, + HFI_PROP_ROTATION, + CAP_FLAG_OUTPUT_PORT}, + + {SUPER_FRAME, ENC, H264 | HEVC, + 0, 32, 1, 0, + 0, 0, + CAP_FLAG_NONE}, + + {SLICE_DECODE, DEC, CODECS_ALL, + 0, 0, 0, 0, + V4L2_CID_MPEG_VIDEO_DECODER_SLICE_INTERFACE, + 0}, + + {HEADER_MODE, ENC, CODECS_ALL, + V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE, + V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME, + BIT(V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) | + BIT(V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME), + V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME, + V4L2_CID_MPEG_VIDEO_HEADER_MODE, + HFI_PROP_SEQ_HEADER_MODE, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {PREPEND_SPSPPS_TO_IDR, ENC, CODECS_ALL, + 0, 1, 1, 0, + V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR}, + + {WITHOUT_STARTCODE, ENC, CODECS_ALL, + 0, 1, 1, 0, + V4L2_CID_MPEG_VIDEO_HEVC_WITHOUT_STARTCODE, + HFI_PROP_NAL_LENGTH_FIELD, + CAP_FLAG_OUTPUT_PORT}, + + {WITHOUT_STARTCODE, DEC, AV1, + 0, 0, 1, 0, + V4L2_CID_MPEG_VIDEO_HEVC_WITHOUT_STARTCODE, + HFI_PROP_NAL_LENGTH_FIELD, + CAP_FLAG_INPUT_PORT}, + + {NAL_LENGTH_FIELD, ENC, CODECS_ALL, + V4L2_MPEG_VIDEO_HEVC_SIZE_0, + V4L2_MPEG_VIDEO_HEVC_SIZE_4, + BIT(V4L2_MPEG_VIDEO_HEVC_SIZE_0) | + BIT(V4L2_MPEG_VIDEO_HEVC_SIZE_4), + V4L2_MPEG_VIDEO_HEVC_SIZE_0, + V4L2_CID_MPEG_VIDEO_HEVC_SIZE_OF_LENGTH_FIELD, + HFI_PROP_NAL_LENGTH_FIELD, + CAP_FLAG_MENU | CAP_FLAG_OUTPUT_PORT}, + + /* TODO: Firmware introduced enumeration type for this + * with and without seq header. + */ + {REQUEST_I_FRAME, ENC, H264 | HEVC, + 0, 0, 0, 0, + V4L2_CID_MPEG_VIDEO_FORCE_KEY_FRAME, + HFI_PROP_REQUEST_SYNC_FRAME, + CAP_FLAG_INPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED}, + + /* Enc: Keeping CABAC and CAVLC as same bitrate. + * Dec: there's no use of Bitrate cap + */ + {BIT_RATE, ENC, H264 | HEVC, + 1, MAX_BITRATE, 1, DEFAULT_BITRATE, + V4L2_CID_MPEG_VIDEO_BITRATE, + HFI_PROP_TOTAL_BITRATE, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {BITRATE_MODE, ENC, H264, + V4L2_MPEG_VIDEO_BITRATE_MODE_VBR, + V4L2_MPEG_VIDEO_BITRATE_MODE_CBR, + BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) | + BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_CBR), + V4L2_MPEG_VIDEO_BITRATE_MODE_VBR, + V4L2_CID_MPEG_VIDEO_BITRATE_MODE, + HFI_PROP_RATE_CONTROL, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {BITRATE_MODE, ENC, HEVC, + V4L2_MPEG_VIDEO_BITRATE_MODE_VBR, + V4L2_MPEG_VIDEO_BITRATE_MODE_CQ, + BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) | + BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_CBR) | + BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_CQ), + V4L2_MPEG_VIDEO_BITRATE_MODE_VBR, + V4L2_CID_MPEG_VIDEO_BITRATE_MODE, + HFI_PROP_RATE_CONTROL, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {CABAC_MAX_BITRATE, ENC, H264 | HEVC, 0, + 160000000, 1, 160000000}, + + {CAVLC_MAX_BITRATE, ENC, H264, 0, + 220000000, 1, 220000000}, + + {ALLINTRA_MAX_BITRATE, ENC, H264 | HEVC, 0, + 245000000, 1, 245000000}, + + {LOWLATENCY_MAX_BITRATE, ENC, H264 | HEVC, 0, + 70000000, 1, 70000000}, + + {NUM_COMV, DEC, CODECS_ALL, + 0, INT_MAX, 1, 0}, + + {LOSSLESS, ENC, HEVC, + 0, 1, 1, 0, + V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU}, + + {FRAME_SKIP_MODE, ENC, H264 | HEVC, + V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED, + V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT, + BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED) | + BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_LEVEL_LIMIT) | + BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT), + V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED, + V4L2_CID_MPEG_VIDEO_FRAME_SKIP_MODE, + 0, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {FRAME_RC_ENABLE, ENC, H264 | HEVC, + 0, 1, 1, 1, + V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE}, + + {CONSTANT_QUALITY, ENC, HEVC, + 1, MAX_CONSTANT_QUALITY, 1, 90, + V4L2_CID_MPEG_VIDEO_CONSTANT_QUALITY, + HFI_PROP_CONSTANT_QUALITY, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {GOP_SIZE, ENC, CODECS_ALL, + 0, INT_MAX, 1, 2 * DEFAULT_FPS - 1, + V4L2_CID_MPEG_VIDEO_GOP_SIZE, + HFI_PROP_MAX_GOP_FRAMES, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {OPEN_GOP, ENC, HEVC, + 0, 1, 1, 0, + 0, + HFI_PROP_OPEN_GOP, + CAP_FLAG_OUTPUT_PORT}, + + {GOP_CLOSURE, ENC, H264 | HEVC, + 0, 1, 1, 1, + V4L2_CID_MPEG_VIDEO_GOP_CLOSURE, + 0}, + + {B_FRAME, ENC, H264 | HEVC, + 0, 1, 1, 0, + V4L2_CID_MPEG_VIDEO_B_FRAMES, + HFI_PROP_MAX_B_FRAMES, + CAP_FLAG_OUTPUT_PORT}, + + {BLUR_TYPES, ENC, H264 | HEVC, + MSM_VIDC_BLUR_NONE, MSM_VIDC_BLUR_EXTERNAL, + BIT(MSM_VIDC_BLUR_NONE) | BIT(MSM_VIDC_BLUR_EXTERNAL), + MSM_VIDC_BLUR_NONE, + 0, + HFI_PROP_BLUR_TYPES, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {CSC, ENC, CODECS_ALL, + 0, 1, 1, 0, + 0, + HFI_PROP_CSC, + CAP_FLAG_OUTPUT_PORT}, + + {LOWLATENCY_MODE, ENC, H264 | HEVC, + 0, 1, 1, 0, + 0, + 0, + CAP_FLAG_NONE}, + + {LOWLATENCY_MODE, DEC, H264 | HEVC | VP9 | AV1, + 0, 1, 1, 0, + 0, + HFI_PROP_SEQ_CHANGE_AT_SYNC_FRAME, + CAP_FLAG_INPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED}, + + {LTR_COUNT, ENC, H264 | HEVC, + 0, MAX_LTR_FRAME_COUNT_2, 1, 0, + V4L2_CID_MPEG_VIDEO_LTR_COUNT, + HFI_PROP_LTR_COUNT, + CAP_FLAG_OUTPUT_PORT}, + + {USE_LTR, ENC, H264 | HEVC, + 0, + ((1 << MAX_LTR_FRAME_COUNT_2) - 1), + 0, 0, + V4L2_CID_MPEG_VIDEO_USE_LTR_FRAMES, + HFI_PROP_LTR_USE, + CAP_FLAG_INPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED}, + + {MARK_LTR, ENC, H264 | HEVC, + INVALID_DEFAULT_MARK_OR_USE_LTR, + (MAX_LTR_FRAME_COUNT_2 - 1), + 1, INVALID_DEFAULT_MARK_OR_USE_LTR, + V4L2_CID_MPEG_VIDEO_FRAME_LTR_INDEX, + HFI_PROP_LTR_MARK, + CAP_FLAG_INPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED}, + + {BASELAYER_PRIORITY, ENC, H264, + 0, MAX_BASE_LAYER_PRIORITY_ID, 1, 0, + V4L2_CID_MPEG_VIDEO_BASELAYER_PRIORITY_ID, + HFI_PROP_BASELAYER_PRIORITYID, + CAP_FLAG_INPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED}, + + {IR_TYPE, ENC, H264 | HEVC, + V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM, + V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_CYCLIC, + BIT(V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM) | + BIT(V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_CYCLIC), + V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM, + V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE, + 0, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {IR_PERIOD, ENC, H264 | HEVC, + 0, INT_MAX, 1, 0, + V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD, + 0, + CAP_FLAG_INPUT_PORT | CAP_FLAG_OUTPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {AU_DELIMITER, ENC, H264 | HEVC, + 0, 1, 1, 0, + V4L2_CID_MPEG_VIDEO_AU_DELIMITER, + HFI_PROP_AUD, + CAP_FLAG_OUTPUT_PORT}, + + {TIME_DELTA_BASED_RC, ENC, H264 | HEVC, + 0, 1, 1, 0, + V4L2_CID_MPEG_VIDC_TIME_DELTA_BASED_RC, + HFI_PROP_TIME_DELTA_BASED_RATE_CONTROL, + CAP_FLAG_OUTPUT_PORT}, + + {CONTENT_ADAPTIVE_CODING, ENC, H264 | HEVC, + 0, 1, 1, 1, + 0, + HFI_PROP_CONTENT_ADAPTIVE_CODING, + CAP_FLAG_OUTPUT_PORT}, + + {REQUEST_PREPROCESS, ENC, H264 | HEVC, + MSM_VIDC_PREPROCESS_NONE, + MSM_VIDC_PREPROCESS_TYPE0, + BIT(MSM_VIDC_PREPROCESS_NONE) | + BIT(MSM_VIDC_PREPROCESS_TYPE0), + MSM_VIDC_PREPROCESS_NONE, + 0, HFI_PROP_REQUEST_PREPROCESS, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {MIN_QUALITY, ENC, H264 | HEVC, + 0, MAX_SUPPORTED_MIN_QUALITY, 70, MAX_SUPPORTED_MIN_QUALITY, + 0, + HFI_PROP_MAINTAIN_MIN_QUALITY, + CAP_FLAG_OUTPUT_PORT}, + + {VBV_DELAY, ENC, H264 | HEVC, + 200, 300, 100, 300, + V4L2_CID_MPEG_VIDEO_VBV_DELAY, + HFI_PROP_VBV_DELAY, + CAP_FLAG_OUTPUT_PORT}, + + {PEAK_BITRATE, ENC, H264 | HEVC, + /* default peak bitrate is 10% larger than avg bitrate */ + 1, MAX_BITRATE, 1, DEFAULT_BITRATE, + V4L2_CID_MPEG_VIDEO_BITRATE_PEAK, + HFI_PROP_TOTAL_PEAK_BITRATE, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {MIN_FRAME_QP, ENC, H264, + MIN_QP_8BIT, MAX_QP, 1, MIN_QP_8BIT, + V4L2_CID_MPEG_VIDEO_H264_MIN_QP, + HFI_PROP_MIN_QP_PACKED, + CAP_FLAG_OUTPUT_PORT}, + + {MIN_FRAME_QP, ENC, HEVC, + MIN_QP_10BIT, MAX_QP, 1, MIN_QP_10BIT, + V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP, + HFI_PROP_MIN_QP_PACKED, + CAP_FLAG_OUTPUT_PORT}, + + {I_FRAME_MIN_QP, ENC, H264, + MIN_QP_8BIT, MAX_QP, 1, MIN_QP_8BIT, + V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MIN_QP}, + + {I_FRAME_MIN_QP, ENC, HEVC, + MIN_QP_10BIT, MAX_QP, 1, MIN_QP_10BIT, + V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MIN_QP}, + + {P_FRAME_MIN_QP, ENC, H264, + MIN_QP_8BIT, MAX_QP, 1, MIN_QP_8BIT, + V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP}, + + {P_FRAME_MIN_QP, ENC, HEVC, + MIN_QP_10BIT, MAX_QP, 1, MIN_QP_10BIT, + V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MIN_QP}, + + {B_FRAME_MIN_QP, ENC, H264, + MIN_QP_8BIT, MAX_QP, 1, MIN_QP_8BIT, + V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MIN_QP}, + + {B_FRAME_MIN_QP, ENC, HEVC, + MIN_QP_10BIT, MAX_QP, 1, MIN_QP_10BIT, + V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MIN_QP}, + + {MAX_FRAME_QP, ENC, H264, + MIN_QP_8BIT, MAX_QP, 1, MAX_QP, + V4L2_CID_MPEG_VIDEO_H264_MAX_QP, + HFI_PROP_MAX_QP_PACKED, + CAP_FLAG_OUTPUT_PORT}, + + {MAX_FRAME_QP, ENC, HEVC, + MIN_QP_10BIT, MAX_QP, 1, MAX_QP, + V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP, + HFI_PROP_MAX_QP_PACKED, + CAP_FLAG_OUTPUT_PORT}, + + {I_FRAME_MAX_QP, ENC, H264, + MIN_QP_8BIT, MAX_QP, 1, MAX_QP, + V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP}, + + {I_FRAME_MAX_QP, ENC, HEVC, + MIN_QP_10BIT, MAX_QP, 1, MAX_QP, + V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MAX_QP}, + + {P_FRAME_MAX_QP, ENC, H264, + MIN_QP_8BIT, MAX_QP, 1, MAX_QP, + V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP}, + + {P_FRAME_MAX_QP, ENC, HEVC, + MIN_QP_10BIT, MAX_QP, 1, MAX_QP, + V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MAX_QP}, + + {B_FRAME_MAX_QP, ENC, H264, + MIN_QP_8BIT, MAX_QP, 1, MAX_QP, + V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MAX_QP}, + + {B_FRAME_MAX_QP, ENC, HEVC, + MIN_QP_10BIT, MAX_QP, 1, MAX_QP, + V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MAX_QP}, + + {I_FRAME_QP, ENC, HEVC, + MIN_QP_10BIT, MAX_QP, 1, DEFAULT_QP, + V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP, + HFI_PROP_QP_PACKED, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {I_FRAME_QP, ENC, H264, + MIN_QP_8BIT, MAX_QP, 1, DEFAULT_QP, + V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP, + HFI_PROP_QP_PACKED, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {P_FRAME_QP, ENC, HEVC, + MIN_QP_10BIT, MAX_QP, 1, DEFAULT_QP, + V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP, + HFI_PROP_QP_PACKED, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {P_FRAME_QP, ENC, H264, + MIN_QP_8BIT, MAX_QP, 1, DEFAULT_QP, + V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP, + HFI_PROP_QP_PACKED, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {B_FRAME_QP, ENC, HEVC, + MIN_QP_10BIT, MAX_QP, 1, DEFAULT_QP, + V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP, + HFI_PROP_QP_PACKED, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {B_FRAME_QP, ENC, H264, + MIN_QP_8BIT, MAX_QP, 1, DEFAULT_QP, + V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP, + HFI_PROP_QP_PACKED, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {LAYER_TYPE, ENC, HEVC, + V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_B, + V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_P, + BIT(V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_B) | + BIT(V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_P), + V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_P, + V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_TYPE, + HFI_PROP_LAYER_ENCODING_TYPE, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {LAYER_TYPE, ENC, H264, + V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_B, + V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_P, + BIT(V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_B) | + BIT(V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_P), + V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_P, + V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_TYPE, + HFI_PROP_LAYER_ENCODING_TYPE, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {LAYER_ENABLE, ENC, H264, + 0, 1, 1, 0, + V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING, + HFI_PROP_LAYER_ENCODING_TYPE, + CAP_FLAG_OUTPUT_PORT}, + + {LAYER_ENABLE, ENC, HEVC, + 0, 1, 1, 0, + 0, + 0, + CAP_FLAG_OUTPUT_PORT}, + + {ENH_LAYER_COUNT, ENC, HEVC, + 0, 5, 1, 0, + V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_LAYER, + HFI_PROP_LAYER_COUNT, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {ENH_LAYER_COUNT, ENC, H264, + 0, 5, 1, 0, + V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER, + HFI_PROP_LAYER_COUNT, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {ENH_LAYER_COUNT, DEC, AV1, + 0, MAX_OP_POINT, 1, 0, + 0, + HFI_PROP_AV1_OP_POINT, + CAP_FLAG_INPUT_PORT}, + + {L0_BR, ENC, H264, + 1, MAX_BITRATE, 1, DEFAULT_BITRATE, + V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L0_BR, + HFI_PROP_BITRATE_LAYER1, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {L0_BR, ENC, HEVC, + 1, MAX_BITRATE, 1, DEFAULT_BITRATE, + V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L0_BR, + HFI_PROP_BITRATE_LAYER1, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {L1_BR, ENC, H264, + 1, MAX_BITRATE, 1, DEFAULT_BITRATE, + V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L1_BR, + HFI_PROP_BITRATE_LAYER2, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {L1_BR, ENC, HEVC, + 1, MAX_BITRATE, 1, DEFAULT_BITRATE, + V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L1_BR, + HFI_PROP_BITRATE_LAYER2, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {L2_BR, ENC, H264, + 1, MAX_BITRATE, 1, DEFAULT_BITRATE, + V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L2_BR, + HFI_PROP_BITRATE_LAYER3, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {L2_BR, ENC, HEVC, + 1, MAX_BITRATE, 1, DEFAULT_BITRATE, + V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L2_BR, + HFI_PROP_BITRATE_LAYER3, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {L3_BR, ENC, H264, + 1, MAX_BITRATE, 1, DEFAULT_BITRATE, + V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L3_BR, + HFI_PROP_BITRATE_LAYER4, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + {L3_BR, ENC, HEVC, + 1, MAX_BITRATE, 1, DEFAULT_BITRATE, + V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L3_BR, + HFI_PROP_BITRATE_LAYER4, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {L4_BR, ENC, H264, + 1, MAX_BITRATE, 1, DEFAULT_BITRATE, + V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L4_BR, + HFI_PROP_BITRATE_LAYER5, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {L4_BR, ENC, HEVC, + 1, MAX_BITRATE, 1, DEFAULT_BITRATE, + V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L4_BR, + HFI_PROP_BITRATE_LAYER5, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {L5_BR, ENC, H264, + 1, MAX_BITRATE, 1, DEFAULT_BITRATE, + V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L5_BR, + HFI_PROP_BITRATE_LAYER6, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {L5_BR, ENC, HEVC, + 1, MAX_BITRATE, 1, DEFAULT_BITRATE, + V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L5_BR, + HFI_PROP_BITRATE_LAYER6, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED}, + + {ENTROPY_MODE, ENC, H264, + V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC, + V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC, + BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC) | + BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC), + V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC, + V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE, + HFI_PROP_CABAC_SESSION, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {ENTROPY_MODE, DEC, H264 | HEVC | VP9 | AV1, + V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC, + V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC, + BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC) | + BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC), + V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC, + 0, + HFI_PROP_CABAC_SESSION}, + + {PROFILE, ENC | DEC, H264, + V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, + V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH, + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH), + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, + V4L2_CID_MPEG_VIDEO_H264_PROFILE, + HFI_PROP_PROFILE, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {PROFILE, ENC | DEC, HEVC, + V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, + V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10_STILL_PICTURE, + BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) | + BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE) | + BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10) | + BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10_STILL_PICTURE), + V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, + V4L2_CID_MPEG_VIDEO_HEVC_PROFILE, + HFI_PROP_PROFILE, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {PROFILE, DEC, VP9, + V4L2_MPEG_VIDEO_VP9_PROFILE_0, + V4L2_MPEG_VIDEO_VP9_PROFILE_2, + BIT(V4L2_MPEG_VIDEO_VP9_PROFILE_0) | + BIT(V4L2_MPEG_VIDEO_VP9_PROFILE_2), + V4L2_MPEG_VIDEO_VP9_PROFILE_0, + V4L2_CID_MPEG_VIDEO_VP9_PROFILE, + HFI_PROP_PROFILE, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {PROFILE, DEC, AV1, + V4L2_MPEG_VIDEO_AV1_PROFILE_MAIN, + V4L2_MPEG_VIDEO_AV1_PROFILE_MAIN, + BIT(V4L2_MPEG_VIDEO_AV1_PROFILE_MAIN), + V4L2_MPEG_VIDEO_AV1_PROFILE_MAIN, + V4L2_CID_MPEG_VIDEO_AV1_PROFILE, + HFI_PROP_PROFILE, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {LEVEL, ENC, H264, + V4L2_MPEG_VIDEO_H264_LEVEL_1_0, + V4L2_MPEG_VIDEO_H264_LEVEL_6_0, + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_0), + V4L2_MPEG_VIDEO_H264_LEVEL_5_0, + V4L2_CID_MPEG_VIDEO_H264_LEVEL, + HFI_PROP_LEVEL, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {LEVEL, ENC, HEVC, + V4L2_MPEG_VIDEO_HEVC_LEVEL_1, + V4L2_MPEG_VIDEO_HEVC_LEVEL_6, + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6), + V4L2_MPEG_VIDEO_HEVC_LEVEL_5, + V4L2_CID_MPEG_VIDEO_HEVC_LEVEL, + HFI_PROP_LEVEL, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {LEVEL, DEC, H264, + V4L2_MPEG_VIDEO_H264_LEVEL_1_0, + V4L2_MPEG_VIDEO_H264_LEVEL_6_1, + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_1), + V4L2_MPEG_VIDEO_H264_LEVEL_6_1, + V4L2_CID_MPEG_VIDEO_H264_LEVEL, + HFI_PROP_LEVEL, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {LEVEL, DEC, HEVC, + V4L2_MPEG_VIDEO_HEVC_LEVEL_1, + V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1, + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1), + V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1, + V4L2_CID_MPEG_VIDEO_HEVC_LEVEL, + HFI_PROP_LEVEL, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {LEVEL, DEC, VP9, + V4L2_MPEG_VIDEO_VP9_LEVEL_1_0, + V4L2_MPEG_VIDEO_VP9_LEVEL_5_1, + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_0) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_1) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_0) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_3_0) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_0) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_1) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_0) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_1), + V4L2_MPEG_VIDEO_VP9_LEVEL_5_1, + V4L2_CID_MPEG_VIDEO_VP9_LEVEL, + HFI_PROP_LEVEL, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {LEVEL, DEC, AV1, + V4L2_MPEG_VIDEO_AV1_LEVEL_2_0, + V4L2_MPEG_VIDEO_AV1_LEVEL_6_1, + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_2_0) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_2_2) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_2_3) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_3_0) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_3_2) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_3_3) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_4_0) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_4_1) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_4_2) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_4_3) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_5_0) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_5_1) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_5_2) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_5_3) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_6_0) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_6_1), + V4L2_MPEG_VIDEO_AV1_LEVEL_6_1, + V4L2_CID_MPEG_VIDEO_AV1_LEVEL, + HFI_PROP_LEVEL, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {AV1_TIER, DEC, AV1, + 0, 0, 0, 0, 0, + HFI_PROP_TIER, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {HEVC_TIER, ENC | DEC, HEVC, + V4L2_MPEG_VIDEO_HEVC_TIER_MAIN, + V4L2_MPEG_VIDEO_HEVC_TIER_HIGH, + BIT(V4L2_MPEG_VIDEO_HEVC_TIER_MAIN) | + BIT(V4L2_MPEG_VIDEO_HEVC_TIER_HIGH), + V4L2_MPEG_VIDEO_HEVC_TIER_HIGH, + V4L2_CID_MPEG_VIDEO_HEVC_TIER, + HFI_PROP_TIER, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {LF_MODE, ENC, H264, + V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED, + DB_H264_DISABLE_SLICE_BOUNDARY, + BIT(V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED) | + BIT(V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED) | + BIT(DB_H264_DISABLE_SLICE_BOUNDARY), + V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED, + V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE, + HFI_PROP_DEBLOCKING_MODE, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {LF_MODE, ENC, HEVC, + V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED, + DB_HEVC_DISABLE_SLICE_BOUNDARY, + BIT(V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED) | + BIT(V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_ENABLED) | + BIT(DB_HEVC_DISABLE_SLICE_BOUNDARY), + V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_ENABLED, + V4L2_CID_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE, + HFI_PROP_DEBLOCKING_MODE, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {LF_ALPHA, ENC, H264, + -6, 6, 1, 0, + V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA}, + + {LF_ALPHA, ENC, HEVC, + -6, 6, 1, 0, + V4L2_CID_MPEG_VIDEO_HEVC_LF_TC_OFFSET_DIV2}, + + {LF_BETA, ENC, H264, + -6, 6, 1, 0, + V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA}, + + {LF_BETA, ENC, HEVC, + -6, 6, 1, 0, + V4L2_CID_MPEG_VIDEO_HEVC_LF_BETA_OFFSET_DIV2}, + + {SLICE_MODE, ENC, H264 | HEVC, + V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE, + V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_BYTES, + BIT(V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE) | + BIT(V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_MB) | + BIT(V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_BYTES), + V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE, + V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE, + 0, + CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, + + {SLICE_MAX_BYTES, ENC, H264 | HEVC, + MIN_SLICE_BYTE_SIZE, MAX_SLICE_BYTE_SIZE, + 1, MIN_SLICE_BYTE_SIZE, + V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES, + HFI_PROP_MULTI_SLICE_BYTES_COUNT, + CAP_FLAG_OUTPUT_PORT}, + + {SLICE_MAX_MB, ENC, H264 | HEVC, + 1, MAX_SLICE_MB_SIZE, 1, 1, + V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB, + HFI_PROP_MULTI_SLICE_MB_COUNT, + CAP_FLAG_OUTPUT_PORT}, + + {MB_RC, ENC, H264 | HEVC, + 0, 1, 1, 1, + V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE, + 0, + CAP_FLAG_OUTPUT_PORT}, + + {TRANSFORM_8X8, ENC, H264, + 0, 1, 1, 1, + V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM, + HFI_PROP_8X8_TRANSFORM, + CAP_FLAG_OUTPUT_PORT}, + + {CHROMA_QP_INDEX_OFFSET, ENC, HEVC, + MIN_CHROMA_QP_OFFSET, MAX_CHROMA_QP_OFFSET, + 1, MAX_CHROMA_QP_OFFSET, + V4L2_CID_MPEG_VIDEO_H264_CHROMA_QP_INDEX_OFFSET, + HFI_PROP_CHROMA_QP_OFFSET, + CAP_FLAG_OUTPUT_PORT}, + + {DISPLAY_DELAY_ENABLE, DEC, H264 | HEVC | VP9 | AV1, + 0, 1, 1, 0, + V4L2_CID_MPEG_VIDEO_DEC_DISPLAY_DELAY_ENABLE, + HFI_PROP_DECODE_ORDER_OUTPUT, + CAP_FLAG_INPUT_PORT}, + + {DISPLAY_DELAY, DEC, H264 | HEVC | VP9 | AV1, + 0, 1, 1, 0, + V4L2_CID_MPEG_VIDEO_DEC_DISPLAY_DELAY, + HFI_PROP_DECODE_ORDER_OUTPUT, + CAP_FLAG_INPUT_PORT}, + + {OUTPUT_ORDER, DEC, H264 | HEVC | VP9 | AV1, + 0, 1, 1, 0, + 0, + HFI_PROP_DECODE_ORDER_OUTPUT, + CAP_FLAG_INPUT_PORT}, + + {INPUT_BUF_HOST_MAX_COUNT, ENC | DEC, CODECS_ALL, + DEFAULT_MAX_HOST_BUF_COUNT, DEFAULT_MAX_HOST_BURST_BUF_COUNT, + 1, DEFAULT_MAX_HOST_BUF_COUNT, + 0, + HFI_PROP_BUFFER_HOST_MAX_COUNT, + CAP_FLAG_INPUT_PORT}, + + {OUTPUT_BUF_HOST_MAX_COUNT, ENC | DEC, CODECS_ALL, + DEFAULT_MAX_HOST_BUF_COUNT, DEFAULT_MAX_HOST_BURST_BUF_COUNT, + 1, DEFAULT_MAX_HOST_BUF_COUNT, + 0, + HFI_PROP_BUFFER_HOST_MAX_COUNT, + CAP_FLAG_OUTPUT_PORT}, + + {CONCEAL_COLOR_8BIT, DEC, CODECS_ALL, 0x0, 0xFF00FF00FF, 1, + DEFAULT_VIDEO_CONCEAL_COLOR_BLACK, + V4L2_CID_MPEG_VIDEO_DEC_CONCEAL_COLOR, + HFI_PROP_CONCEAL_COLOR_8BIT, + CAP_FLAG_INPUT_PORT}, + + {CONCEAL_COLOR_10BIT, DEC, CODECS_ALL, 0x0, 0x3FF03FF03FF, 1, + DEFAULT_VIDEO_CONCEAL_COLOR_BLACK, + V4L2_CID_MPEG_VIDEO_DEC_CONCEAL_COLOR, + HFI_PROP_CONCEAL_COLOR_10BIT, + CAP_FLAG_INPUT_PORT}, + + {STAGE, DEC | ENC, CODECS_ALL, + MSM_VIDC_STAGE_1, + MSM_VIDC_STAGE_2, 1, + MSM_VIDC_STAGE_2, + 0, + HFI_PROP_STAGE}, + + {PIPE, DEC | ENC, CODECS_ALL, + MSM_VIDC_PIPE_1, + MSM_VIDC_PIPE_4, 1, + MSM_VIDC_PIPE_4, + 0, + HFI_PROP_PIPE}, + + {POC, DEC, H264, 0, 2, 1, 1, + 0, + HFI_PROP_PIC_ORDER_CNT_TYPE}, + + {QUALITY_MODE, ENC, CODECS_ALL, + MSM_VIDC_MAX_QUALITY_MODE, + MSM_VIDC_POWER_SAVE_MODE, 1, + MSM_VIDC_POWER_SAVE_MODE}, + + {CODED_FRAMES, DEC, H264 | HEVC, + CODED_FRAMES_PROGRESSIVE, CODED_FRAMES_INTERLACE, + 1, CODED_FRAMES_PROGRESSIVE, + 0, + HFI_PROP_CODED_FRAMES, + CAP_FLAG_VOLATILE}, + + {BIT_DEPTH, DEC | ENC, CODECS_ALL, BIT_DEPTH_8, BIT_DEPTH_10, 1, BIT_DEPTH_8, + 0, + HFI_PROP_LUMA_CHROMA_BIT_DEPTH}, + + {CODEC_CONFIG, DEC, H264 | HEVC | AV1, 0, 1, 1, 0, + 0, 0, + CAP_FLAG_DYNAMIC_ALLOWED}, + + {BITSTREAM_SIZE_OVERWRITE, DEC, CODECS_ALL, 0, INT_MAX, 1, 0, + 0}, + + {THUMBNAIL_MODE, DEC, CODECS_ALL, + 0, 1, 1, 0, + 0, + HFI_PROP_THUMBNAIL_MODE, + CAP_FLAG_INPUT_PORT}, + + {DEFAULT_HEADER, DEC, CODECS_ALL, + 0, 1, 1, 0, + 0, + HFI_PROP_DEC_DEFAULT_HEADER}, + + {RAP_FRAME, DEC, CODECS_ALL, + 0, 1, 1, 1, + 0, + HFI_PROP_DEC_START_FROM_RAP_FRAME, + CAP_FLAG_INPUT_PORT}, + + {SEQ_CHANGE_AT_SYNC_FRAME, DEC, CODECS_ALL, + 0, 1, 1, 1, + 0, + HFI_PROP_SEQ_CHANGE_AT_SYNC_FRAME, + CAP_FLAG_INPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED}, + + {PRIORITY, DEC | ENC, CODECS_ALL, + 0, 4, 1, 4, + 0, + HFI_PROP_SESSION_PRIORITY, + CAP_FLAG_DYNAMIC_ALLOWED}, + + {ENC_IP_CR, ENC, CODECS_ALL, + 0, S32_MAX, 1, 0, + 0, + 0, CAP_FLAG_DYNAMIC_ALLOWED}, + + {FILM_GRAIN, DEC, AV1, + 0, 1, 1, 0, + 0, + HFI_PROP_AV1_FILM_GRAIN_PRESENT, + CAP_FLAG_VOLATILE}, + + {SUPER_BLOCK, DEC, AV1, + 0, 1, 1, 0, + 0, + HFI_PROP_AV1_SUPER_BLOCK_ENABLED}, + + {DRAP, DEC, AV1, + 0, S32_MAX, 1, 0, + 0, + HFI_PROP_AV1_DRAP_CONFIG, + CAP_FLAG_INPUT_PORT}, + + {LAST_FLAG_EVENT_ENABLE, DEC, CODECS_ALL, + 0, 1, 1, 0, + 0}, + + {ALL_INTRA, ENC, H264 | HEVC, + 0, 1, 1, 0, + 0, + 0, + CAP_FLAG_OUTPUT_PORT}, + + {META_ROI_INFO, ENC, H264 | HEVC, + 0, 0, 0, 0, + 0, + 0, + CAP_FLAG_INPUT_PORT | CAP_FLAG_BITMASK | CAP_FLAG_META}, + {COMPLEXITY, ENC, H264 | HEVC, + 0, 100, + 1, DEFAULT_COMPLEXITY, + 0}, + + {DELIVERY_MODE, ENC, H264 | HEVC, + 0, 1, 1, 0, + 0, + HFI_PROP_ENABLE_SLICE_DELIVERY, + CAP_FLAG_OUTPUT_PORT}, + + {SIGNAL_COLOR_INFO, ENC, CODECS_ALL, + 0, INT_MAX, 1, 0, + 0, + HFI_PROP_SIGNAL_COLOR_INFO, + CAP_FLAG_INPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED}, +}; + +static struct msm_platform_inst_cap_dependency instance_cap_dependency_data_glymur[] = { + /* {cap, domain, codec, + * parents, + * children, + * adjust, set} + */ + + {PIX_FMTS, ENC, H264, + {META_ROI_INFO, IR_PERIOD, BIT_DEPTH}}, + + {PIX_FMTS, ENC, HEVC, + {PROFILE, MIN_FRAME_QP, MAX_FRAME_QP, I_FRAME_QP, P_FRAME_QP, + B_FRAME_QP, META_ROI_INFO, MIN_QUALITY, BLUR_TYPES, IR_PERIOD, + LTR_COUNT, BIT_DEPTH}}, + + {PIX_FMTS, DEC, HEVC, + {PROFILE}}, + + {BIT_DEPTH, ENC, CODECS_ALL, + {0}, + msm_vidc_adjust_bitdepth}, + + {FRAME_RATE, ENC, CODECS_ALL, + {0}, + NULL, + msm_vidc_set_q16}, + + {HFLIP, ENC, CODECS_ALL, + {0}, + NULL, + msm_vidc_set_flip}, + + {VFLIP, ENC, CODECS_ALL, + {0}, + NULL, + msm_vidc_set_flip}, + + {ROTATION, ENC, CODECS_ALL, + {0}, + NULL, + msm_vidc_set_rotation}, + + {SUPER_FRAME, ENC, H264 | HEVC, + {INPUT_BUF_HOST_MAX_COUNT, OUTPUT_BUF_HOST_MAX_COUNT}, + NULL, + NULL}, + + {HEADER_MODE, ENC, CODECS_ALL, + {0}, + NULL, + msm_vidc_set_header_mode}, + + {WITHOUT_STARTCODE, ENC, CODECS_ALL, + {0}, + NULL, + msm_vidc_set_nal_length}, + + {WITHOUT_STARTCODE, DEC, AV1, + {0}, + NULL, + msm_vidc_set_u32}, + + {REQUEST_I_FRAME, ENC, H264 | HEVC, + {0}, + NULL, + msm_vidc_set_req_sync_frame}, + + {BIT_RATE, ENC, H264 | HEVC, + {PEAK_BITRATE, L0_BR}, + msm_vidc_adjust_bitrate, + msm_vidc_set_bitrate}, + + {BITRATE_MODE, ENC, H264, + {LTR_COUNT, IR_PERIOD, TIME_DELTA_BASED_RC, I_FRAME_QP, + P_FRAME_QP, B_FRAME_QP, ENH_LAYER_COUNT, BIT_RATE, + META_ROI_INFO, MIN_QUALITY, VBV_DELAY, + PEAK_BITRATE, SLICE_MODE, CONTENT_ADAPTIVE_CODING, + BLUR_TYPES, LOWLATENCY_MODE}, + msm_vidc_adjust_bitrate_mode, + msm_vidc_set_u32_enum}, + + {BITRATE_MODE, ENC, HEVC, + {LTR_COUNT, IR_PERIOD, TIME_DELTA_BASED_RC, I_FRAME_QP, + P_FRAME_QP, B_FRAME_QP, CONSTANT_QUALITY, ENH_LAYER_COUNT, + BIT_RATE, META_ROI_INFO, MIN_QUALITY, VBV_DELAY, + PEAK_BITRATE, SLICE_MODE, CONTENT_ADAPTIVE_CODING, + BLUR_TYPES, LOWLATENCY_MODE, OPEN_GOP}, + msm_vidc_adjust_bitrate_mode, + msm_vidc_set_u32_enum}, + + {CONSTANT_QUALITY, ENC, HEVC, + {0}, + NULL, + msm_vidc_set_constant_quality}, + + {GOP_SIZE, ENC, CODECS_ALL, + {ALL_INTRA}, + msm_vidc_adjust_gop_size, + msm_vidc_set_gop_size}, + + {OPEN_GOP, ENC, HEVC, + {GOP_SIZE}, + msm_vidc_adjust_open_gop, + msm_vidc_set_u32}, + + {B_FRAME, ENC, H264 | HEVC, + {ALL_INTRA}, + msm_vidc_adjust_b_frame, + msm_vidc_set_u32}, + + {BLUR_TYPES, ENC, H264 | HEVC, + {0}, + msm_vidc_adjust_blur_type, + msm_vidc_set_u32_enum}, + + {LOWLATENCY_MODE, ENC, H264 | HEVC, + {STAGE, BIT_RATE}, + msm_vidc_adjust_enc_lowlatency_mode, + NULL}, + + {LOWLATENCY_MODE, DEC, H264 | HEVC | VP9 | AV1, + {STAGE}, + NULL, + NULL}, + + {LTR_COUNT, ENC, H264 | HEVC, + {0}, + msm_vidc_adjust_ltr_count, + msm_vidc_set_u32}, + + {USE_LTR, ENC, H264 | HEVC, + {0}, + msm_vidc_adjust_use_ltr, + msm_vidc_set_use_and_mark_ltr}, + + {MARK_LTR, ENC, H264 | HEVC, + {0}, + msm_vidc_adjust_mark_ltr, + msm_vidc_set_use_and_mark_ltr}, + + {IR_PERIOD, ENC, H264 | HEVC, + {0}, + msm_vidc_adjust_ir_period_glymur, + msm_vidc_set_ir_period_glymur}, + + {AU_DELIMITER, ENC, H264 | HEVC, + {0}, + NULL, + msm_vidc_set_u32}, + + {BASELAYER_PRIORITY, ENC, H264, + {0}, + NULL, + msm_vidc_set_u32}, + + {TIME_DELTA_BASED_RC, ENC, CODECS_ALL, + {0}, + msm_vidc_adjust_delta_based_rc, + msm_vidc_set_u32}, + + {CONTENT_ADAPTIVE_CODING, ENC, H264 | HEVC, + {REQUEST_PREPROCESS}, + msm_vidc_adjust_brs, + msm_vidc_set_vbr_related_properties}, + + {REQUEST_PREPROCESS, ENC, H264 | HEVC, + {0}, + msm_vidc_adjust_preprocess, + msm_vidc_set_preprocess}, + + {MIN_QUALITY, ENC, H264, + {BLUR_TYPES}, + msm_vidc_adjust_min_quality, + msm_vidc_set_u32}, + + {MIN_QUALITY, ENC, HEVC, + {BLUR_TYPES}, + msm_vidc_adjust_min_quality, + msm_vidc_set_u32}, + + {VBV_DELAY, ENC, H264 | HEVC, + {0}, + NULL, + msm_vidc_set_cbr_related_properties}, + + {PEAK_BITRATE, ENC, H264 | HEVC, + {0}, + msm_vidc_adjust_peak_bitrate, + msm_vidc_set_cbr_related_properties}, + + {MIN_FRAME_QP, ENC, H264, + {0}, + NULL, + msm_vidc_set_min_qp}, + + {MIN_FRAME_QP, ENC, HEVC, + {0}, + msm_vidc_adjust_hevc_min_qp, + msm_vidc_set_min_qp}, + + {MAX_FRAME_QP, ENC, H264, + {0}, + NULL, + msm_vidc_set_max_qp}, + + {MAX_FRAME_QP, ENC, HEVC, + {0}, + msm_vidc_adjust_hevc_max_qp, + msm_vidc_set_max_qp}, + + {I_FRAME_QP, ENC, HEVC, + {0}, + msm_vidc_adjust_hevc_i_frame_qp, + msm_vidc_set_frame_qp}, + + {I_FRAME_QP, ENC, H264, + {0}, + NULL, + msm_vidc_set_frame_qp}, + + {P_FRAME_QP, ENC, HEVC, + {0}, + msm_vidc_adjust_hevc_p_frame_qp, + msm_vidc_set_frame_qp}, + + {P_FRAME_QP, ENC, H264, + {0}, + NULL, + msm_vidc_set_frame_qp}, + + {B_FRAME_QP, ENC, HEVC, + {0}, + msm_vidc_adjust_hevc_b_frame_qp, + msm_vidc_set_frame_qp}, + + {B_FRAME_QP, ENC, H264, + {0}, + NULL, + msm_vidc_set_frame_qp}, + + {LAYER_TYPE, ENC, H264, + {CONTENT_ADAPTIVE_CODING, LTR_COUNT}}, + + {LAYER_TYPE, ENC, HEVC, + {CONTENT_ADAPTIVE_CODING, LTR_COUNT, OPEN_GOP}}, + + {LAYER_ENABLE, ENC, H264 | HEVC, + {CONTENT_ADAPTIVE_CODING}}, + + {ENH_LAYER_COUNT, ENC, H264, + {GOP_SIZE, B_FRAME, BIT_RATE, MIN_QUALITY, + SLICE_MODE, LTR_COUNT}, + msm_vidc_adjust_layer_count, + msm_vidc_set_layer_count_and_type}, + + {ENH_LAYER_COUNT, ENC, HEVC, + {GOP_SIZE, B_FRAME, BIT_RATE, MIN_QUALITY, + SLICE_MODE, LTR_COUNT, OPEN_GOP}, + msm_vidc_adjust_layer_count, + msm_vidc_set_layer_count_and_type}, + + {ENH_LAYER_COUNT, DEC, AV1, + {0}, + NULL, + msm_vidc_set_u32}, + + {L0_BR, ENC, H264 | HEVC, + {L1_BR}, + msm_vidc_adjust_layer_bitrate, + msm_vidc_set_layer_bitrate}, + + {L1_BR, ENC, H264 | HEVC, + {L2_BR}, + msm_vidc_adjust_layer_bitrate, + msm_vidc_set_layer_bitrate}, + + {L2_BR, ENC, H264 | HEVC, + {L3_BR}, + msm_vidc_adjust_layer_bitrate, + msm_vidc_set_layer_bitrate}, + + {L3_BR, ENC, H264 | HEVC, + {L4_BR}, + msm_vidc_adjust_layer_bitrate, + msm_vidc_set_layer_bitrate}, + + {L4_BR, ENC, H264 | HEVC, + {L5_BR}, + msm_vidc_adjust_layer_bitrate, + msm_vidc_set_layer_bitrate}, + + {L5_BR, ENC, H264 | HEVC, + {0}, + msm_vidc_adjust_layer_bitrate, + msm_vidc_set_layer_bitrate}, + + {ENTROPY_MODE, ENC, H264, + {BIT_RATE}, + msm_vidc_adjust_entropy_mode, + msm_vidc_set_u32}, + + {PROFILE, ENC, H264, + {ENTROPY_MODE, TRANSFORM_8X8}, + NULL, + msm_vidc_set_u32_enum}, + + {PROFILE, DEC, H264, + {ENTROPY_MODE}, + NULL, + msm_vidc_set_u32_enum}, + + {PROFILE, ENC | DEC, HEVC, + {0}, + msm_vidc_adjust_profile, + msm_vidc_set_u32_enum}, + + {PROFILE, DEC, VP9 | AV1, + {0}, + NULL, + msm_vidc_set_u32_enum}, + + {LEVEL, DEC, CODECS_ALL, + {0}, + NULL, + msm_vidc_set_u32_enum}, + + {LEVEL, ENC, CODECS_ALL, + {0}, + NULL, + msm_vidc_set_level}, + + {AV1_TIER, DEC, AV1, + {0}, + NULL, + msm_vidc_set_u32_enum}, + + {HEVC_TIER, ENC | DEC, HEVC, + {0}, + NULL, + msm_vidc_set_u32_enum}, + + {LF_MODE, ENC, CODECS_ALL, + {0}, + NULL, + msm_vidc_set_deblock_mode}, + + {SLICE_MODE, ENC, H264 | HEVC, + {STAGE, DELIVERY_MODE}, + msm_vidc_adjust_slice_count, + msm_vidc_set_slice_count}, + + {TRANSFORM_8X8, ENC, H264, + {0}, + msm_vidc_adjust_transform_8x8, + msm_vidc_set_u32}, + + {CHROMA_QP_INDEX_OFFSET, ENC, HEVC, + {0}, + msm_vidc_adjust_chroma_qp_index_offset, + msm_vidc_set_chroma_qp_index_offset}, + + {DISPLAY_DELAY_ENABLE, DEC, H264 | HEVC | VP9 | AV1, + {OUTPUT_ORDER}, + NULL, + NULL}, + + {DISPLAY_DELAY, DEC, H264 | HEVC | VP9 | AV1, + {OUTPUT_ORDER}, + NULL, + NULL}, + + {OUTPUT_ORDER, DEC, H264 | HEVC | VP9 | AV1, + {0}, + msm_vidc_adjust_output_order, + msm_vidc_set_u32}, + + {INPUT_BUF_HOST_MAX_COUNT, ENC | DEC, CODECS_ALL, + {0}, + msm_vidc_adjust_input_buf_host_max_count, + msm_vidc_set_u32}, + + {INPUT_BUF_HOST_MAX_COUNT, ENC, H264 | HEVC, + {0}, + msm_vidc_adjust_input_buf_host_max_count, + msm_vidc_set_u32}, + + {OUTPUT_BUF_HOST_MAX_COUNT, ENC | DEC, CODECS_ALL, + {0}, + msm_vidc_adjust_output_buf_host_max_count, + msm_vidc_set_u32}, + + {OUTPUT_BUF_HOST_MAX_COUNT, ENC, H264 | HEVC, + {0}, + msm_vidc_adjust_output_buf_host_max_count, + msm_vidc_set_u32}, + + {CONCEAL_COLOR_8BIT, DEC, CODECS_ALL, + {0}, + NULL, + msm_vidc_set_conceal_color}, + + {CONCEAL_COLOR_10BIT, DEC, CODECS_ALL, + {0}, + NULL, + msm_vidc_set_conceal_color}, + + {STAGE, ENC | DEC, CODECS_ALL, + {0}, + NULL, + msm_vidc_set_stage}, + + {PIPE, DEC | ENC, CODECS_ALL, + {0}, + NULL, + msm_vidc_set_pipe}, + + {THUMBNAIL_MODE, DEC, CODECS_ALL, + {OUTPUT_ORDER}, + NULL, + msm_vidc_set_u32}, + + {RAP_FRAME, DEC, CODECS_ALL, + {0}, + NULL, + msm_vidc_set_u32}, + + {PRIORITY, DEC | ENC, CODECS_ALL, + {0}, + msm_vidc_adjust_session_priority, + msm_vidc_set_session_priority}, + + {DRAP, DEC, AV1, + {0}, + NULL, + msm_vidc_set_u32}, + + {ALL_INTRA, ENC, H264 | HEVC, + {LTR_COUNT, IR_PERIOD, SLICE_MODE, BIT_RATE}, + msm_vidc_adjust_all_intra, + NULL}, + {META_ROI_INFO, ENC, H264 | HEVC, + {MIN_QUALITY, IR_PERIOD, BLUR_TYPES}, + NULL, + NULL}, +}; + +static struct msm_vidc_format_capability format_data_glymur = { + .codec_info = codec_data_glymur, + .codec_info_size = ARRAY_SIZE(codec_data_glymur), + .color_format_info = color_format_data_glymur, + .color_format_info_size = ARRAY_SIZE(color_format_data_glymur), + .color_prim_info = color_primaries_data_glymur, + .color_prim_info_size = ARRAY_SIZE(color_primaries_data_glymur), + .transfer_char_info = transfer_char_data_glymur, + .transfer_char_info_size = ARRAY_SIZE(transfer_char_data_glymur), + .matrix_coeff_info = matrix_coeff_data_glymur, + .matrix_coeff_info_size = ARRAY_SIZE(matrix_coeff_data_glymur), +}; + +/* name, min_kbps, max_kbps */ +static const struct bw_table glymur_bw_table[] = { + { "cpu-cfg", 1000, 1000 }, + { "video-mem", 1000, 15000000 }, +}; + +/* name */ +static struct pd_table glymur_pd_table[] = { + { "venus", 0, 1 }, + { "vcodec0", 1, 1 }, + { "vcodec1", 1, 1 }, +}; + +/* name */ +static const char * const glymur_opp_pd_table[] = { + "mxc", + "mmcx", + NULL +}; + +/* name, clock id, scaling */ +static const struct clk_table glymur_clk_table[] = { + { "core_iface", GCC_VIDEO_AXI0C_CLK, 0 }, + { "core", VIDEO_CC_MVS0C_CLK, 0 }, + { "vcodec0_core", VIDEO_CC_MVS0_CLK, 1, + (u64[]) {655000000, 533333334, 444000000, 366000000, 338000000, 240000000}, 6}, + { "vcodec0_iface", GCC_VIDEO_AXI0_CLK, 0 }, + { "core_freerun", VIDEO_CC_MVS0C_FREERUN_CLK, 0 }, + { "vcodec0_core_freerun", VIDEO_CC_MVS0_FREERUN_CLK, 0 }, + { "vcodec1_iface", GCC_VIDEO_AXI1_CLK, 0 }, + { "vcodec1_core", VIDEO_CC_MVS1_CLK, 1, + (u64[]) {655000000, 533333334, 444000000, 366000000, 338000000, 240000000}, 6}, + { "vcodec1_core_freerun", VIDEO_CC_MVS1_FREERUN_CLK, 0 }, +}; + +const char * const glymur_opp_clk_table[] = { + "vcodec0_core", + "vcodec1_core", + "core", + NULL, +}; + +/* name, exclusive_release */ +static const struct clk_rst_table glymur_clk_reset_table[] = { + { "core_bus", 0 }, + { "vcodec0_bus", 0 }, + { "core", 0 }, + { "vcodec0_core", 0 }, + { "vcodec1_bus", 0 }, + { "vcodec1_core", 0 }, +}; + +/* name, start, size, secure, dma_coherant, region, dma_mask */ +const struct context_bank_table glymur_context_bank_table[] = { + {"qcom,vidc,cb-ns", 0x25800000, 0xda600000, 0, 1, + MSM_VIDC_NON_SECURE | MSM_VIDC_NON_SECURE_BITSTREAM, 0 }, + {"qcom,vidc,cb-ns-pxl", 0x00200000, 0xffc00000, 0, 1, MSM_VIDC_NON_SECURE_PIXEL, 0 }, + {"qcom,vidc,cb-sec-pxl", 0x00200000, 0xffc00000, 1, 0, MSM_VIDC_SECURE_PIXEL, 0 }, + {"qcom,vidc,cb-sec-non-pxl", 0x01000000, 0x24800000, 1, 0, MSM_VIDC_SECURE_NONPIXEL, 0 }, + {"qcom,vidc,cb-sec-bitstream", 0x00500000, 0xdfb00000, 1, 0, MSM_VIDC_SECURE_BITSTREAM, 0 }, + {"qcom,vidc,cb-firmware", 0x00000000, 0x01000000, 1, 0, MSM_VIDC_SECURE_FIRMWARE, 0 }, +}; + +/* register, value, mask */ +static const struct reg_preset_table glymur_reg_preset_table[] = { + { 0xB0088, 0x0, 0x3f }, +}; + +/* decoder properties */ +static const u32 glymur_vdec_psc_avc[] = { + HFI_PROP_BITSTREAM_RESOLUTION, + HFI_PROP_CROP_OFFSETS, + HFI_PROP_CODED_FRAMES, + HFI_PROP_LUMA_CHROMA_BIT_DEPTH, + HFI_PROP_BUFFER_FW_MIN_OUTPUT_COUNT, + HFI_PROP_PIC_ORDER_CNT_TYPE, + HFI_PROP_PROFILE, + HFI_PROP_LEVEL, + HFI_PROP_SIGNAL_COLOR_INFO, +}; + +static const u32 glymur_vdec_psc_hevc[] = { + HFI_PROP_BITSTREAM_RESOLUTION, + HFI_PROP_CROP_OFFSETS, + HFI_PROP_LUMA_CHROMA_BIT_DEPTH, + HFI_PROP_BUFFER_FW_MIN_OUTPUT_COUNT, + HFI_PROP_PROFILE, + HFI_PROP_LEVEL, + HFI_PROP_TIER, + HFI_PROP_SIGNAL_COLOR_INFO, +}; + +static const u32 glymur_vdec_psc_vp9[] = { + HFI_PROP_BITSTREAM_RESOLUTION, + HFI_PROP_CROP_OFFSETS, + HFI_PROP_LUMA_CHROMA_BIT_DEPTH, + HFI_PROP_BUFFER_FW_MIN_OUTPUT_COUNT, + HFI_PROP_PROFILE, + HFI_PROP_LEVEL, +}; + +static const u32 glymur_vdec_psc_av1[] = { + HFI_PROP_BITSTREAM_RESOLUTION, + HFI_PROP_CROP_OFFSETS, + HFI_PROP_LUMA_CHROMA_BIT_DEPTH, + HFI_PROP_BUFFER_FW_MIN_OUTPUT_COUNT, + HFI_PROP_AV1_FILM_GRAIN_PRESENT, + HFI_PROP_AV1_SUPER_BLOCK_ENABLED, + HFI_PROP_PROFILE, + HFI_PROP_LEVEL, + HFI_PROP_TIER, + HFI_PROP_SIGNAL_COLOR_INFO, +}; + +static const u32 glymur_vdec_input_properties_avc[] = { + HFI_PROP_NO_OUTPUT, + HFI_PROP_SUBFRAME_INPUT, +}; + +static const u32 glymur_vdec_input_properties_hevc[] = { + HFI_PROP_NO_OUTPUT, + HFI_PROP_SUBFRAME_INPUT, +}; + +static const u32 glymur_vdec_input_properties_vp9[] = { + HFI_PROP_NO_OUTPUT, + HFI_PROP_SUBFRAME_INPUT, +}; + +static const u32 glymur_vdec_input_properties_av1[] = { + HFI_PROP_NO_OUTPUT, + HFI_PROP_SUBFRAME_INPUT, + HFI_PROP_DPB_LIST, + HFI_PROP_AV1_TILE_ROWS_COLUMNS, + HFI_PROP_AV1_UNIFORM_TILE_SPACING, +}; + +static const u32 glymur_vdec_output_properties_avc[] = { + HFI_PROP_WORST_COMPRESSION_RATIO, + HFI_PROP_WORST_COMPLEXITY_FACTOR, + HFI_PROP_PICTURE_TYPE, + HFI_PROP_DPB_LIST, + HFI_PROP_CABAC_SESSION, +}; + +static const u32 glymur_vdec_output_properties_hevc[] = { + HFI_PROP_WORST_COMPRESSION_RATIO, + HFI_PROP_WORST_COMPLEXITY_FACTOR, + HFI_PROP_PICTURE_TYPE, + HFI_PROP_DPB_LIST, +}; + +static const u32 glymur_vdec_output_properties_vp9[] = { + HFI_PROP_WORST_COMPRESSION_RATIO, + HFI_PROP_WORST_COMPLEXITY_FACTOR, + HFI_PROP_PICTURE_TYPE, + HFI_PROP_DPB_LIST, +}; + +static const u32 glymur_vdec_output_properties_av1[] = { + HFI_PROP_WORST_COMPRESSION_RATIO, + HFI_PROP_WORST_COMPLEXITY_FACTOR, + HFI_PROP_PICTURE_TYPE, + HFI_PROP_DPB_LIST, + HFI_PROP_CABAC_SESSION, +}; + +static const u32 glymur_msm_vidc_ssr_type[] = { + HFI_SSR_TYPE_SW_ERR_FATAL, +}; + +static int msm_vidc_glymur_init_cb_devs(struct msm_vidc_core *core) +{ + static const struct { + const char *cb_name; + const char *cb_node_name; + } glymur_cb_fid[] = { + { "qcom,vidc,cb-ns", "non-pixel" }, + { "qcom,vidc,cb-ns-pxl", "pixel" }, + }; + struct context_bank_info *cb; + int i, rc; + + venus_hfi_for_each_context_bank(core, cb) { + for (i = 0; i < ARRAY_SIZE(glymur_cb_fid); i++) { + if (strcmp(cb->name, glymur_cb_fid[i].cb_name)) + continue; + + rc = msm_vidc_create_child_device_and_map(core, cb, 0, + glymur_cb_fid[i].cb_node_name); + if (rc) { + d_vpr_e("%s: failed to create child device for %s rc %d\n", + __func__, cb->name, rc); + return rc; + } + break; + } + } + + return 0; +} + +static const struct msm_vidc_platform_data glymur_data = { + /* resources dependent on other module */ + .bw_tbl = glymur_bw_table, + .bw_tbl_size = ARRAY_SIZE(glymur_bw_table), + .pd_tbl = glymur_pd_table, + .pd_tbl_size = ARRAY_SIZE(glymur_pd_table), + .opp_tbl = glymur_opp_pd_table, + .opp_tbl_size = ARRAY_SIZE(glymur_opp_pd_table), + .clk_tbl = glymur_clk_table, + .clk_tbl_size = ARRAY_SIZE(glymur_clk_table), + .opp_clk_tbl = glymur_opp_clk_table, + .clk_rst_tbl = glymur_clk_reset_table, + .clk_rst_tbl_size = ARRAY_SIZE(glymur_clk_reset_table), + + /* populate context bank */ + .context_bank_tbl = glymur_context_bank_table, + .context_bank_tbl_size = ARRAY_SIZE(glymur_context_bank_table), + /* platform specific resources */ + .reg_prst_tbl = glymur_reg_preset_table, + .reg_prst_tbl_size = ARRAY_SIZE(glymur_reg_preset_table), + .clock_source_scaling_ratio = 1, + .fwname = "./qcom/vpu/vpu36_p4_s7.mbn", + .num_cores = 2, + .pas_id = 9, + .supports_mmrm = 0, + + .core_data = core_data_glymur, + .core_data_size = ARRAY_SIZE(core_data_glymur), + .inst_cap_data = instance_cap_data_glymur, + .inst_cap_data_size = ARRAY_SIZE(instance_cap_data_glymur), + .inst_cap_dependency_data = instance_cap_dependency_data_glymur, + .inst_cap_dependency_data_size = ARRAY_SIZE(instance_cap_dependency_data_glymur), + .csc_data.vpe_csc_custom_bias_coeff = vpe_csc_custom_bias_coeff, + .csc_data.vpe_csc_custom_matrix_coeff = vpe_csc_custom_matrix_coeff, + .csc_data.vpe_csc_custom_limit_coeff = vpe_csc_custom_limit_coeff, + .format_data = &format_data_glymur, + + /* decoder properties related*/ + .psc_avc_tbl = glymur_vdec_psc_avc, + .psc_avc_tbl_size = ARRAY_SIZE(glymur_vdec_psc_avc), + .psc_hevc_tbl = glymur_vdec_psc_hevc, + .psc_hevc_tbl_size = ARRAY_SIZE(glymur_vdec_psc_hevc), + .psc_vp9_tbl = glymur_vdec_psc_vp9, + .psc_vp9_tbl_size = ARRAY_SIZE(glymur_vdec_psc_vp9), + .psc_av1_tbl = glymur_vdec_psc_av1, + .psc_av1_tbl_size = ARRAY_SIZE(glymur_vdec_psc_av1), + .dec_input_prop_avc = glymur_vdec_input_properties_avc, + .dec_input_prop_hevc = glymur_vdec_input_properties_hevc, + .dec_input_prop_vp9 = glymur_vdec_input_properties_vp9, + .dec_input_prop_av1 = glymur_vdec_input_properties_av1, + .dec_input_prop_size_avc = ARRAY_SIZE(glymur_vdec_input_properties_avc), + .dec_input_prop_size_hevc = ARRAY_SIZE(glymur_vdec_input_properties_hevc), + .dec_input_prop_size_vp9 = ARRAY_SIZE(glymur_vdec_input_properties_vp9), + .dec_input_prop_size_av1 = ARRAY_SIZE(glymur_vdec_input_properties_av1), + .dec_output_prop_avc = glymur_vdec_output_properties_avc, + .dec_output_prop_hevc = glymur_vdec_output_properties_hevc, + .dec_output_prop_vp9 = glymur_vdec_output_properties_vp9, + .dec_output_prop_av1 = glymur_vdec_output_properties_av1, + .dec_output_prop_size_avc = ARRAY_SIZE(glymur_vdec_output_properties_avc), + .dec_output_prop_size_hevc = ARRAY_SIZE(glymur_vdec_output_properties_hevc), + .dec_output_prop_size_vp9 = ARRAY_SIZE(glymur_vdec_output_properties_vp9), + .dec_output_prop_size_av1 = ARRAY_SIZE(glymur_vdec_output_properties_av1), + .msm_vidc_ssr_type = glymur_msm_vidc_ssr_type, + .msm_vidc_ssr_type_size = ARRAY_SIZE(glymur_msm_vidc_ssr_type), + .init_cb_devs = msm_vidc_glymur_init_cb_devs, +}; + +static int msm_vidc_glymur_check_ddr_type(void) +{ + return 0; +} + +int msm_vidc_adjust_ir_period_glymur(void *instance, struct v4l2_ctrl *ctrl) +{ + s32 adjusted_value; + s64 all_intra = 0, roi_enable = 0, pix_fmts = MSM_VIDC_FMT_NONE; + struct msm_vidc_inst *inst = (struct msm_vidc_inst *)instance; + + adjusted_value = ctrl ? ctrl->val : inst->capabilities[IR_PERIOD].value; + + if (msm_vidc_get_parent_value(inst, IR_PERIOD, ALL_INTRA, + &all_intra, __func__) || + msm_vidc_get_parent_value(inst, IR_PERIOD, META_ROI_INFO, + &roi_enable, __func__)) + return -EINVAL; + + if (all_intra) { + adjusted_value = 0; + i_vpr_h(inst, "%s: intra refresh unsupported, all intra: %lld\n", + __func__, all_intra); + goto exit; + } + + if (roi_enable) { + i_vpr_h(inst, + "%s: intra refresh unsupported with roi metadata\n", + __func__); + adjusted_value = 0; + goto exit; + } + + if (inst->codec == MSM_VIDC_HEVC) { + if (msm_vidc_get_parent_value(inst, IR_PERIOD, + PIX_FMTS, &pix_fmts, __func__)) + return -EINVAL; + + if (is_10bit_colorformat(pix_fmts)) { + i_vpr_h(inst, + "%s: intra refresh is supported only for 8 bit\n", + __func__); + adjusted_value = 0; + goto exit; + } + } + + /* + * BITRATE_MODE dependency is NOT common across all chipsets. + * Hence, do not return error if not specified as one of the parent. + */ + if (is_parent_available(inst, IR_PERIOD, BITRATE_MODE, __func__) && + inst->hfi_rc_type != HFI_RC_CBR_CFR && + inst->hfi_rc_type != HFI_RC_CBR_VFR) + adjusted_value = 0; + +exit: + msm_vidc_update_cap_value(inst, IR_PERIOD, adjusted_value, __func__); + + return 0; +} + +int msm_vidc_set_ir_period_glymur(void *instance, + enum msm_vidc_inst_capability_type cap_id) +{ + int rc = 0; + struct msm_vidc_inst *inst = (struct msm_vidc_inst *)instance; + u32 ir_type = 0; + struct msm_vidc_core *core; + + core = inst->core; + + if (inst->capabilities[IR_TYPE].value == + V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM) { + if (inst->bufq[OUTPUT_PORT].vb2q->streaming) { + i_vpr_h(inst, "%s: dynamic random intra refresh not allowed\n", + __func__); + return 0; + } + ir_type = HFI_PROP_IR_RANDOM_PERIOD; + } else if (inst->capabilities[IR_TYPE].value == + V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_CYCLIC) { + ir_type = HFI_PROP_IR_CYCLIC_PERIOD; + } else { + i_vpr_e(inst, "%s: invalid ir_type %lld\n", + __func__, inst->capabilities[IR_TYPE].value); + return -EINVAL; + } + + rc = venus_hfi_set_ir_period(inst, ir_type, cap_id); + if (rc) { + i_vpr_e(inst, "%s: failed to set ir period %lld\n", + __func__, inst->capabilities[IR_PERIOD].value); + return rc; + } + + return rc; +} + +int msm_vidc_get_platform_data_glymur(struct msm_vidc_core *core) +{ + d_vpr_h("%s: initialize glymur data\n", __func__); + core->platform->data = glymur_data; + + return 0; +} + +int msm_vidc_init_platform_glymur(struct msm_vidc_core *core) +{ + int rc = 0; + + d_vpr_h("%s: initialize glymur ops\n", __func__); + rc = msm_vidc_glymur_check_ddr_type(); + if (rc) + return rc; + + return rc; +} From 20878b3ecafb04e322544f752870f1b0eb0383d2 Mon Sep 17 00:00:00 2001 From: Vishnu Reddy Date: Wed, 1 Jul 2026 18:02:08 +0530 Subject: [PATCH 08/10] iris: add support for glymur build configuration Add the glymur platform and iris36 variant source files and include paths to the Kbuild so the driver can be built with glymur support. Signed-off-by: Vishnu Reddy --- config/glymur_video.conf | 2 ++ config/glymur_video.h | 7 +++++++ msm_video/Kbuild | 19 +++++++++++++++++++ video/Kbuild | 30 ++++++++++++++++++++++++++++-- 4 files changed, 56 insertions(+), 2 deletions(-) create mode 100644 config/glymur_video.conf create mode 100644 config/glymur_video.h diff --git a/config/glymur_video.conf b/config/glymur_video.conf new file mode 100644 index 000000000..7a24cfd30 --- /dev/null +++ b/config/glymur_video.conf @@ -0,0 +1,2 @@ +export CONFIG_MSM_VIDC_GLYMUR=y +export CONFIG_MSM_VIDC_IRIS36=y diff --git a/config/glymur_video.h b/config/glymur_video.h new file mode 100644 index 000000000..db5223fe4 --- /dev/null +++ b/config/glymur_video.h @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#define CONFIG_MSM_VIDC_GLYMUR 1 +#define CONFIG_MSM_VIDC_IRIS36 1 diff --git a/msm_video/Kbuild b/msm_video/Kbuild index 75c9a59fe..2e3afa8b9 100644 --- a/msm_video/Kbuild +++ b/msm_video/Kbuild @@ -64,6 +64,11 @@ LINUXINCLUDE += -include $(VIDEO_ROOT)/config/nordau_video.h endif endif +ifeq ($(CONFIG_ARCH_GLYMUR), y) +include $(VIDEO_ROOT)/config/glymur_video.conf +LINUXINCLUDE += -include $(VIDEO_ROOT)/config/glymur_video.h +endif + ifeq ($(CONFIG_MSM_VIDC_HAMOA), y) LINUXINCLUDE += -I$(VIDEO_DRIVER_ABS_PATH)/platform/hamoa/inc \ -I$(VIDEO_DRIVER_ABS_PATH)/variant/iris3/inc @@ -103,6 +108,11 @@ LINUXINCLUDE += -I$(VIDEO_DRIVER_ABS_PATH)/platform/nordau/inc \ -I$(VIDEO_DRIVER_ABS_PATH)/variant/iris36/inc endif +ifeq ($(CONFIG_MSM_VIDC_GLYMUR), y) +LINUXINCLUDE += -I$(VIDEO_DRIVER_ABS_PATH)/platform/glymur/inc \ + -I$(VIDEO_DRIVER_ABS_PATH)/variant/iris36/inc +endif + LINUXINCLUDE += -I$(VIDEO_DRIVER_ABS_PATH)/platform/common/inc \ -I$(VIDEO_DRIVER_ABS_PATH)/variant/common/inc \ -I$(VIDEO_DRIVER_ABS_PATH)/vidc/inc \ @@ -193,6 +203,15 @@ msm_video-objs += $(VIDEO_DRIVER_REL_PATH)/platform/nordau/src/msm_vidc_nordau.o $(VIDEO_DRIVER_REL_PATH)/variant/iris36/src/msm_vidc_iris36.o endif +ifeq ($(CONFIG_MSM_VIDC_GLYMUR), y) +msm_video-objs += $(VIDEO_DRIVER_REL_PATH)/platform/glymur/src/msm_vidc_glymur.o \ + $(VIDEO_DRIVER_REL_PATH)/variant/iris36/src/msm_vidc_buffer_iris36.o \ + $(VIDEO_DRIVER_REL_PATH)/variant/iris36/src/msm_vidc_power_iris36.o \ + $(VIDEO_DRIVER_REL_PATH)/variant/iris36/src/msm_vidc_bus_iris36.o \ + $(VIDEO_DRIVER_REL_PATH)/variant/iris36/src/msm_vidc_clock_iris36.o \ + $(VIDEO_DRIVER_REL_PATH)/variant/iris36/src/msm_vidc_iris36.o +endif + msm_video-objs += $(VIDEO_DRIVER_REL_PATH)/platform/common/src/msm_vidc_platform.o \ $(VIDEO_DRIVER_REL_PATH)/platform/common/src/msm_vidc_ubwc.o \ $(VIDEO_DRIVER_REL_PATH)/platform/common/src/msm_vidc_platform_ext.o \ diff --git a/video/Kbuild b/video/Kbuild index 8b04225ab..65694653c 100644 --- a/video/Kbuild +++ b/video/Kbuild @@ -59,6 +59,10 @@ include $(VIDEO_ROOT)/config/nordau_video.conf LINUXINCLUDE += -include $(VIDEO_ROOT)/config/nordau_video.h endif +else ifeq ($(CONFIG_ARCH_GLYMUR), y) +include $(VIDEO_ROOT)/config/glymur_video.conf +LINUXINCLUDE += -include $(VIDEO_ROOT)/config/glymur_video.h + else ifeq ($(CONFIG_QLI_VIDC_SA8775P), y) include $(VIDEO_ROOT)/config/lemans_video.conf LINUXINCLUDE += -include $(VIDEO_ROOT)/config/lemans_video.h @@ -115,6 +119,11 @@ LINUXINCLUDE += -I$(VIDEO_DRIVER_ABS_PATH)/platform/nordau/inc \ -I$(VIDEO_DRIVER_ABS_PATH)/variant/iris36/inc endif +ifeq ($(CONFIG_MSM_VIDC_GLYMUR), y) +LINUXINCLUDE += -I$(VIDEO_DRIVER_ABS_PATH)/platform/glymur/inc \ + -I$(VIDEO_DRIVER_ABS_PATH)/variant/iris36/inc +endif + ifeq ($(CONFIG_MSM_VIDC_HAMOA), y) LINUXINCLUDE += -I$(VIDEO_DRIVER_ABS_PATH)/platform/hamoa/inc \ -I$(VIDEO_DRIVER_ABS_PATH)/variant/iris3/inc @@ -128,7 +137,9 @@ LINUXINCLUDE += -I$(VIDEO_DRIVER_ABS_PATH)/platform/lemans/inc \ -I$(VIDEO_DRIVER_ABS_PATH)/platform/kodiak/inc \ -I$(VIDEO_DRIVER_ABS_PATH)/platform/purwa/inc \ -I$(VIDEO_DRIVER_ABS_PATH)/variant/iris3/inc \ - -I$(VIDEO_DRIVER_ABS_PATH)/variant/iris2/inc + -I$(VIDEO_DRIVER_ABS_PATH)/variant/iris2/inc \ + -I$(VIDEO_DRIVER_ABS_PATH)/platform/glymur/inc \ + -I$(VIDEO_DRIVER_ABS_PATH)/variant/iris36/inc endif LINUXINCLUDE += -I$(VIDEO_DRIVER_ABS_PATH)/platform/common/inc \ @@ -211,6 +222,15 @@ iris_vpu-objs += $(VIDEO_DRIVER_REL_PATH)/platform/nordau/src/nordau.o \ $(VIDEO_DRIVER_REL_PATH)/variant/iris36/src/msm_vidc_iris36.o endif +ifeq ($(CONFIG_MSM_VIDC_GLYMUR), y) +iris_vpu-objs += $(VIDEO_DRIVER_REL_PATH)/platform/glymur/src/glymur.o \ + $(VIDEO_DRIVER_REL_PATH)/variant/iris36/src/msm_vidc_buffer_iris36.o \ + $(VIDEO_DRIVER_REL_PATH)/variant/iris36/src/msm_vidc_power_iris36.o \ + $(VIDEO_DRIVER_REL_PATH)/variant/iris36/src/msm_vidc_bus_iris36.o \ + $(VIDEO_DRIVER_REL_PATH)/variant/iris36/src/msm_vidc_clock_iris36.o \ + $(VIDEO_DRIVER_REL_PATH)/variant/iris36/src/msm_vidc_iris36.o +endif + ifeq ($(CONFIG_MSM_VIDC_HAMOA), y) iris_vpu-objs += $(VIDEO_DRIVER_REL_PATH)/platform/hamoa/src/hamoa.o \ $(VIDEO_DRIVER_REL_PATH)/variant/iris3/src/msm_vidc_buffer_iris3.o \ @@ -233,7 +253,13 @@ iris_vpu-objs += $(VIDEO_DRIVER_REL_PATH)/platform/lemans/src/lemans.o \ $(VIDEO_DRIVER_REL_PATH)/variant/iris3/src/msm_vidc_iris3.o \ $(VIDEO_DRIVER_REL_PATH)/variant/iris2/src/msm_vidc_buffer_iris2.o \ $(VIDEO_DRIVER_REL_PATH)/variant/iris2/src/msm_vidc_power_iris2.o \ - $(VIDEO_DRIVER_REL_PATH)/variant/iris2/src/msm_vidc_iris2.o + $(VIDEO_DRIVER_REL_PATH)/variant/iris2/src/msm_vidc_iris2.o \ + $(VIDEO_DRIVER_REL_PATH)/platform/glymur/src/glymur.o \ + $(VIDEO_DRIVER_REL_PATH)/variant/iris36/src/msm_vidc_buffer_iris36.o \ + $(VIDEO_DRIVER_REL_PATH)/variant/iris36/src/msm_vidc_power_iris36.o \ + $(VIDEO_DRIVER_REL_PATH)/variant/iris36/src/msm_vidc_bus_iris36.o \ + $(VIDEO_DRIVER_REL_PATH)/variant/iris36/src/msm_vidc_clock_iris36.o \ + $(VIDEO_DRIVER_REL_PATH)/variant/iris36/src/msm_vidc_iris36.o endif iris_vpu-objs += $(VIDEO_DRIVER_REL_PATH)/platform/common/src/msm_vidc_platform.o \ From c56b39bbc152f45e8547d549d6fcd5fcb432022e Mon Sep 17 00:00:00 2001 From: Vishnu Reddy Date: Sun, 19 Jul 2026 11:00:54 +0530 Subject: [PATCH 09/10] video: Kbuild: detect glymur videocc.h and gcc.h at build time The dt-bindings headers and should be present in the kernel trees to build the video driver for glymur support. If it is not available any kernel like linux-yocto based trees. Then the build will fail. Add a build-time probe in video/Kbuild that tests for the header and, when found, passes -DMSM_VIDC_HAS_GLYMUR_GCC_VIDEOCC=1 to compiler. Guard the include of that header and the clock-table entries whose initialiser values are defined exclusively by it with the same macro. Also guard the qcom,glymur-iris entry in msm_vidc_dt_match[] so that the kernel does not associate the driver with the glymur device at all on kernels where the header is absent. Signed-off-by: Vishnu Reddy --- driver/platform/glymur/src/glymur.c | 4 ++++ driver/vidc/src/msm_vidc_probe.c | 2 ++ video/Kbuild | 9 +++++++++ 3 files changed, 15 insertions(+) diff --git a/driver/platform/glymur/src/glymur.c b/driver/platform/glymur/src/glymur.c index e9d8cc12d..7064021b5 100644 --- a/driver/platform/glymur/src/glymur.c +++ b/driver/platform/glymur/src/glymur.c @@ -3,8 +3,10 @@ * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. */ +#ifdef MSM_VIDC_HAS_GLYMUR_GCC_VIDEOCC #include #include +#endif #include #include "msm_vidc_internal.h" @@ -1855,6 +1857,7 @@ static const char * const glymur_opp_pd_table[] = { /* name, clock id, scaling */ static const struct clk_table glymur_clk_table[] = { +#ifdef MSM_VIDC_HAS_GLYMUR_GCC_VIDEOCC { "core_iface", GCC_VIDEO_AXI0C_CLK, 0 }, { "core", VIDEO_CC_MVS0C_CLK, 0 }, { "vcodec0_core", VIDEO_CC_MVS0_CLK, 1, @@ -1866,6 +1869,7 @@ static const struct clk_table glymur_clk_table[] = { { "vcodec1_core", VIDEO_CC_MVS1_CLK, 1, (u64[]) {655000000, 533333334, 444000000, 366000000, 338000000, 240000000}, 6}, { "vcodec1_core_freerun", VIDEO_CC_MVS1_FREERUN_CLK, 0 }, +#endif }; const char * const glymur_opp_clk_table[] = { diff --git a/driver/vidc/src/msm_vidc_probe.c b/driver/vidc/src/msm_vidc_probe.c index dd8bad23f..56d6f9ed3 100644 --- a/driver/vidc/src/msm_vidc_probe.c +++ b/driver/vidc/src/msm_vidc_probe.c @@ -180,7 +180,9 @@ static const struct of_device_id msm_vidc_dt_match[] = { {.compatible = "qcom,sa8775p-iris"}, {.compatible = "qcom,qcs8300-iris"}, {.compatible = "qcom,sc7280-venus"}, +#ifdef MSM_VIDC_HAS_GLYMUR_GCC_VIDEOCC {.compatible = "qcom,glymur-iris"}, +#endif {.compatible = "qcom,vidc,cb-ns-pxl"}, {.compatible = "qcom,vidc,cb-ns"}, {.compatible = "qcom,vidc,cb-ns-bitstream"}, diff --git a/video/Kbuild b/video/Kbuild index 65694653c..95d135cd6 100644 --- a/video/Kbuild +++ b/video/Kbuild @@ -19,6 +19,15 @@ ifeq ($(HAS_X1P42100_VIDEOCC),yes) ccflags-y += -DMSM_VIDC_HAS_X1P42100_VIDEOCC=1 endif +GLYMUR_GCC_VIDEOCC_H := $(shell \ + test -f $(KERNEL_SRC)/include/dt-bindings/clock/qcom,glymur-videocc.h && \ + test -f $(KERNEL_SRC)/include/dt-bindings/clock/qcom,glymur-gcc.h && \ + echo yes || echo no) + +ifeq ($(GLYMUR_GCC_VIDEOCC_H),yes) + ccflags-y += -DMSM_VIDC_HAS_GLYMUR_GCC_VIDEOCC=1 +endif + MDT_LOADER_H := $(KERNEL_SRC)/include/linux/soc/qcom/mdt_loader.h HAS_MDT_PAS_LOAD := $(shell grep -qs 'qcom_mdt_pas_load' $(MDT_LOADER_H) && echo yes || echo no) From 13337e562e4a880d1cb2f05b773a8eaae5857d20 Mon Sep 17 00:00:00 2001 From: Vishnu Reddy Date: Sun, 12 Jul 2026 18:37:00 +0530 Subject: [PATCH 10/10] iris: fix green line on rotated output and support downscale The driver currently aligns input dimensions before programming them to the encoder firmware. The firmware does not require aligned input resolutions, and using aligned values can result in a green line being visible on the right side of rotated output frames. Remove the input dimension alignment and program the actual configured resolution to the firmware to avoid the artifact. Additionally, output resolution handling relies on compose dimensions. The compose rectangle can be updated through format, crop, and selection operations, but output format updates do not refresh the compose values. As a result, the final output resolution may be derived from stale compose dimensions, causing requested output resolutions to be ignored and preventing downscaling from working. Keep compose and format dimensions synchronized across format, crop, and compose operations so that output resolution changes are applied correctly and downscaling works as expected. Signed-off-by: Vishnu Reddy --- driver/vidc/src/msm_venc.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/driver/vidc/src/msm_venc.c b/driver/vidc/src/msm_venc.c index c84a30fb3..ff2b5e0da 100644 --- a/driver/vidc/src/msm_venc.c +++ b/driver/vidc/src/msm_venc.c @@ -1145,6 +1145,9 @@ int msm_venc_s_fmt_output(struct msm_vidc_inst *inst, struct v4l2_format *f) codec_align = (codec == MSM_VIDC_HEVC || codec == MSM_VIDC_HEIC) ? 32 : 16; + inst->compose.width = f->fmt.pix_mp.width; + inst->compose.height = f->fmt.pix_mp.height; + /* use rotated width height if rotation is enabled */ width = inst->compose.width; height = inst->compose.height; @@ -1261,8 +1264,8 @@ static int msm_venc_s_fmt_input(struct msm_vidc_inst *inst, struct v4l2_format * fmt = &inst->fmts[INPUT_PORT]; fmt->type = INPUT_MPLANE; - fmt->fmt.pix_mp.width = video_y_stride_pix(pix_fmt, width); - fmt->fmt.pix_mp.height = video_y_scanlines(pix_fmt, height); + fmt->fmt.pix_mp.width = width; + fmt->fmt.pix_mp.height = height; fmt->fmt.pix_mp.num_planes = 1; fmt->fmt.pix_mp.pixelformat = f->fmt.pix_mp.pixelformat; fmt->fmt.pix_mp.plane_fmt[0].bytesperline = bytesperline; @@ -1279,6 +1282,8 @@ static int msm_venc_s_fmt_input(struct msm_vidc_inst *inst, struct v4l2_format * * output port color after setting input color info. */ output_fmt = &inst->fmts[OUTPUT_PORT]; + output_fmt->fmt.pix_mp.width = fmt->fmt.pix_mp.width; + output_fmt->fmt.pix_mp.height = fmt->fmt.pix_mp.height; output_fmt->fmt.pix_mp.colorspace = fmt->fmt.pix_mp.colorspace; output_fmt->fmt.pix_mp.xfer_func = fmt->fmt.pix_mp.xfer_func; output_fmt->fmt.pix_mp.ycbcr_enc = fmt->fmt.pix_mp.ycbcr_enc; @@ -1453,6 +1458,8 @@ int msm_venc_s_selection(struct msm_vidc_inst *inst, struct v4l2_selection *s) inst->compose.height = inst->crop.height; /* update output format based on new crop dimensions */ output_fmt = &inst->fmts[OUTPUT_PORT]; + output_fmt->fmt.pix_mp.width = inst->compose.width; + output_fmt->fmt.pix_mp.height = inst->compose.height; rc = msm_venc_s_fmt_output(inst, output_fmt); if (rc) return rc; @@ -1498,6 +1505,8 @@ int msm_venc_s_selection(struct msm_vidc_inst *inst, struct v4l2_selection *s) /* update output format based on new compose dimensions */ output_fmt = &inst->fmts[OUTPUT_PORT]; + output_fmt->fmt.pix_mp.width = inst->compose.width; + output_fmt->fmt.pix_mp.height = inst->compose.height; rc = msm_venc_s_fmt_output(inst, output_fmt); if (rc) return rc;