diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 6820f1c61..77419b5b2 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -5,6 +5,9 @@ # Authors: # - Thomas Benz +variables: + IDMA_NONFREE_COMMIT: common-cells-v2 + default: interruptible: true hooks: diff --git a/Bender.lock b/Bender.lock index 018ea78a1..c6b317657 100644 --- a/Bender.lock +++ b/Bender.lock @@ -1,14 +1,14 @@ packages: apb: - revision: 77ddf073f194d44b9119949d2421be59789e69ae - version: 0.2.4 + revision: 6a2bd0fe9f0822322104ac602fac5739fb063aa0 + version: null source: Git: https://github.com/pulp-platform/apb.git dependencies: - common_cells axi: - revision: a8c53cee2520d328d390c507c88818e8ac144c8c - version: 0.39.10 + revision: 0ccc838fe06aeeb857eb83c6be9a915c4bf99566 + version: null source: Git: https://github.com/pulp-platform/axi.git dependencies: @@ -16,15 +16,15 @@ packages: - common_verification - tech_cells_generic axi_stream: - revision: 54891ff40455ca94a37641b9da4604647878cc07 - version: 0.1.1 + revision: 834639c9a39d00c063cef184164525416ef5b119 + version: null source: Git: https://github.com/pulp-platform/axi_stream.git dependencies: - common_cells common_cells: - revision: 1281545696eb3fcba50ec5b4275993476a3c710e - version: 1.40.0 + revision: 03d98106aa19952a10360d2230def85144a0008b + version: 2.0.0-beta.2 source: Git: https://github.com/pulp-platform/common_cells.git dependencies: @@ -37,8 +37,8 @@ packages: Git: https://github.com/pulp-platform/common_verification.git dependencies: [] obi: - revision: 0155fc34e900c7c884e081c0a1114a247937ff69 - version: 0.1.7 + revision: b69af4aa00630efd14b1c5cbf9bac977f23ce840 + version: null source: Git: https://github.com/pulp-platform/obi.git dependencies: diff --git a/Bender.yml b/Bender.yml index ec990ada2..5d0f9b8aa 100644 --- a/Bender.yml +++ b/Bender.yml @@ -14,12 +14,12 @@ package: - "Axel Vanoni " dependencies: - axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.9 } - axi_stream: { git: "https://github.com/pulp-platform/axi_stream.git", version: 0.1.1 } - common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.39.0 } + axi: { git: "https://github.com/pulp-platform/axi.git", rev: 0ccc838fe06aeeb857eb83c6be9a915c4bf99566 } + axi_stream: { git: "https://github.com/pulp-platform/axi_stream.git", rev: 834639c9a39d00c063cef184164525416ef5b119 } + common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 2.0.0-beta.2 } common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.5 } - apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.4 } - obi: { git: "https://github.com/pulp-platform/obi.git", version: 0.1.7 } + apb: { git: "https://github.com/pulp-platform/apb.git", rev: 6a2bd0fe9f0822322104ac602fac5739fb063aa0 } + obi: { git: "https://github.com/pulp-platform/obi.git", rev: b69af4aa00630efd14b1c5cbf9bac977f23ce840 } export_include_dirs: - src/include diff --git a/idma.mk b/idma.mk index c9c3e4df2..0c0f24afc 100644 --- a/idma.mk +++ b/idma.mk @@ -299,7 +299,7 @@ $(IDMA_FULL_TB): $(IDMA_TB_ALL) .PHONY: idma_pickle_clean IDMA_PICKLE_DIR := $(IDMA_ROOT)/target/pickle -IDMA_PICKLE_TARGETS := -t rtl -t synth -t asic -t snitch_cluster +IDMA_PICKLE_TARGETS := -t rtl -t synth -t asic -t snitch_cluster -t cc_no_deprecated IDMA_PICKLE_ARGS ?= $(IDMA_PICKLE_DIR)/%.sv: $(IDMA_BENDER_FILES) $(IDMA_FULL_TB) $(IDMA_FULL_RTL) $(IDMA_INCLUDE_ALL) diff --git a/src/backend/idma_channel_coupler.sv b/src/backend/idma_channel_coupler.sv index 1491716a2..838eec62d 100644 --- a/src/backend/idma_channel_coupler.sv +++ b/src/backend/idma_channel_coupler.sv @@ -28,8 +28,6 @@ module idma_channel_coupler #( input logic clk_i, /// Asynchronous reset, active low input logic rst_ni, - /// Testmode in - input logic testmode_i, /// R response valid input logic r_rsp_valid_i, @@ -60,7 +58,7 @@ module idma_channel_coupler #( ); /// The width of the credit counter keeping track of the transfers - localparam int unsigned CounterWidth = cf_math_pkg::idx_width(NumAxInFlight); + localparam int unsigned CounterWidth = cc_pkg::idx_width(NumAxInFlight); /// Credit counter type typedef logic [CounterWidth-1:0] cnt_t; @@ -91,14 +89,14 @@ module idma_channel_coupler #( assign first = r_rsp_valid_i & r_rsp_ready_i & r_rsp_first_i & !r_decouple_aw_i; // stream fifo to hold AWs back - stream_fifo_optimal_wrap #( + cc_stream_fifo_optimal_wrap #( .Depth ( NumAxInFlight ), - .type_t ( axi_aw_chan_t ), + .data_t ( axi_aw_chan_t ), .PrintInfo ( PrintFifoInfo ) ) i_aw_store ( .clk_i, .rst_ni, - .testmode_i, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), .usage_o ( /* NOT CONNECTED */ ), .data_i ( aw_req_i ), @@ -109,14 +107,14 @@ module idma_channel_coupler #( .ready_i ( aw_ready ) ); - stream_fifo_optimal_wrap #( + cc_stream_fifo_optimal_wrap #( .Depth ( NumAxInFlight ), - .type_t ( logic ), + .data_t ( logic ), .PrintInfo ( PrintFifoInfo ) ) i_aw_decoupled_store ( .clk_i, .rst_ni, - .testmode_i, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), .usage_o ( /* NOT CONNECTED */ ), .data_i ( aw_decouple_aw_i ), @@ -160,12 +158,11 @@ module idma_channel_coupler #( // fall through register to decouple the aw valid signal from the aw ready // now payload is required; just the decoupling of the handshaking signals - fall_through_register #( - .T ( logic [0:0] ) + cc_fall_through_register #( + .data_t ( logic [0:0] ) ) i_fall_through_register_decouple_aw_valid ( .clk_i, .rst_ni, - .testmode_i, .clr_i ( 1'b0 ), .valid_i ( aw_sent ), .ready_o ( aw_ready_decoupled ), diff --git a/src/backend/idma_dataflow_element.sv b/src/backend/idma_dataflow_element.sv index 00744710a..1d3472b97 100644 --- a/src/backend/idma_dataflow_element.sv +++ b/src/backend/idma_dataflow_element.sv @@ -21,7 +21,6 @@ module idma_dataflow_element #( )( input logic clk_i, input logic rst_ni, - input logic testmode_i, input byte_t [StrbWidth-1:0] data_i, input strb_t valid_i, @@ -34,14 +33,14 @@ module idma_dataflow_element #( // buffer is implemented as an array of FIFOs for (genvar i = 0; i < StrbWidth; i++) begin : gen_fifo_buffer - passthrough_stream_fifo #( - .type_t ( byte_t ), + cc_passthrough_stream_fifo #( + .data_t ( byte_t ), .Depth ( BufferDepth ), .PrintInfo ( PrintFifoInfo ) ) i_passthrough_stream_fifo ( .clk_i, .rst_ni, - .testmode_i, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), .data_i ( data_i [i] ), .valid_i ( valid_i [i] ), diff --git a/src/backend/idma_error_handler.sv b/src/backend/idma_error_handler.sv index 19994e35b..30a797e88 100644 --- a/src/backend/idma_error_handler.sv +++ b/src/backend/idma_error_handler.sv @@ -33,8 +33,6 @@ module idma_error_handler #( input logic clk_i, /// Asynchronous reset, active low input logic rst_ni, - /// Testmode in - input logic testmode_i, /// 1D iDMA response output idma_rsp_t rsp_o, @@ -136,14 +134,14 @@ module idma_error_handler #( // FIFO: read address // the read address FIFO is synchronized with the `i_w_last` FIFO in the backend. So at this // point now full handshaking is required. - stream_fifo_optimal_wrap #( + cc_stream_fifo_optimal_wrap #( .Depth ( MetaFifoDepth ), - .type_t ( addr_t ), + .data_t ( addr_t ), .PrintInfo ( PrintFifoInfo ) ) i_r_addr_store ( .clk_i, .rst_ni, - .testmode_i, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), .usage_o ( /* NOT CONNECTED */ ), .data_i ( r_addr_i ), @@ -157,14 +155,14 @@ module idma_error_handler #( // FIFO: w address // the read address FIFO is synchronized with the `i_w_last` FIFO in the backend. So at this // point now full handshaking is required. - stream_fifo_optimal_wrap #( + cc_stream_fifo_optimal_wrap #( .Depth ( MetaFifoDepth ), - .type_t ( addr_t ), + .data_t ( addr_t ), .PrintInfo ( PrintFifoInfo ) ) i_w_addr_store ( .clk_i, .rst_ni, - .testmode_i, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), .usage_o ( /* NOT CONNECTED */ ), .data_i ( w_addr_i ), diff --git a/src/backend/tpl/idma_backend.sv.tpl b/src/backend/tpl/idma_backend.sv.tpl index f71872333..fdf84f2a1 100644 --- a/src/backend/tpl/idma_backend.sv.tpl +++ b/src/backend/tpl/idma_backend.sv.tpl @@ -106,8 +106,6 @@ module idma_backend_${name_uniqueifier} #( input logic clk_i, /// Asynchronous reset, active low input logic rst_ni, - /// Testmode in - input logic testmode_i, /// 1D iDMA request input idma_req_t idma_req_i, @@ -508,11 +506,12 @@ _rsp_t ${mh_format['aw'][protocol]}${protocol}_write_rsp_i, end else begin : gen_no_hw_legalizer // stream fork is used to synchronize the two decoupled channels without the need for a // FIFO here. - stream_fork #( - .N_OUP ( 32'd2 ) + cc_stream_fork #( + .NumOup ( 32'd2 ) ) i_stream_fork ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( req_valid_leg ), .ready_o ( leg_ready ), .valid_o ( { r_valid, w_valid } ), @@ -582,7 +581,6 @@ _rsp_t ${mh_format['aw'][protocol]}${protocol}_write_rsp_i, ) i_idma_error_handler ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .testmode_i ( testmode_i ), .rsp_o ( idma_rsp ), .rsp_valid_o ( rsp_valid ), .rsp_ready_i ( rsp_ready ), @@ -652,14 +650,14 @@ _rsp_t ${mh_format['aw'][protocol]}${protocol}_write_rsp_i, //-------------------------------------- // Datapath decoupling //-------------------------------------- - stream_fifo_optimal_wrap #( + cc_stream_fifo_optimal_wrap #( .Depth ( NumAxInFlight ), - .type_t ( r_dp_req_t ), + .data_t ( r_dp_req_t ), .PrintInfo ( PrintFifoInfo ) ) i_r_dp_req ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .testmode_i ( testmode_i ), + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), .usage_o ( /* NOT CONNECTED */ ), .data_i ( r_req.r_dp_req ), @@ -670,14 +668,14 @@ _rsp_t ${mh_format['aw'][protocol]}${protocol}_write_rsp_i, .ready_i ( r_dp_req_out_ready ) ); - stream_fifo_optimal_wrap #( + cc_stream_fifo_optimal_wrap #( .Depth ( NumAxInFlight + ComputeFifoDepth ), - .type_t ( w_dp_req_t ), + .data_t ( w_dp_req_t ), .PrintInfo ( PrintFifoInfo ) ) i_w_dp_req ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .testmode_i ( testmode_i ), + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), .usage_o ( /* NOT CONNECTED */ ), .data_i ( w_req.w_dp_req ), @@ -698,8 +696,8 @@ _rsp_t ${mh_format['aw'][protocol]}${protocol}_write_rsp_i, end % endif - fall_through_register #( - .T (\ + cc_fall_through_register #( + .data_t (\ % if one_read_port: read_meta_channel_t\ % else: @@ -709,7 +707,6 @@ _rsp_t ${mh_format['aw'][protocol]}${protocol}_write_rsp_i, ) i_ar_fall_through_register ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .testmode_i ( testmode_i ), .clr_i ( 1'b0 ), .valid_i ( r_valid ), .ready_o ( ar_ready ), @@ -729,14 +726,14 @@ _rsp_t ${mh_format['aw'][protocol]}${protocol}_write_rsp_i, //-------------------------------------- // Last flag store //-------------------------------------- - stream_fifo_optimal_wrap #( + cc_stream_fifo_optimal_wrap #( .Depth ( MetaFifoDepth ), - .type_t ( logic [1:0] ), + .data_t ( logic [1:0] ), .PrintInfo ( PrintFifoInfo ) ) i_w_last ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .testmode_i ( testmode_i ), + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), .usage_o ( /* NOT CONNECTED */ ), .data_i ( {w_req.super_last, w_req.last} ), @@ -797,8 +794,7 @@ _rsp_t ${mh_format['aw'][protocol]}${protocol}_write_rsp_i, ) i_idma_transport_layer ( .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .testmode_i ( testmode_i )\ + .rst_ni ( rst_ni )\ % for protocol in used_read_protocols: , % if database[protocol]['passive_req'] == 'true': @@ -870,7 +866,6 @@ _rsp_t ${mh_format['aw'][protocol]}${protocol}_write_rsp_i, ) i_idma_channel_coupler ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .testmode_i ( testmode_i ), .r_rsp_valid_i ( r_chan_valid ), .r_rsp_ready_i ( r_chan_ready ), .r_rsp_first_i ( r_dp_rsp.first ), @@ -913,15 +908,15 @@ w_req.decouple_aw || (w_req.w_dp_req.dst_protocol inside {\ % if combined_aw_and_w: % if compute_eligible: // combined aw+w read-meta buffer; deepened for the compute engine tile read-ahead (cf. i_w_dp_req) - stream_fifo_optimal_wrap #( + cc_stream_fifo_optimal_wrap #( .Depth ( EnableCompute ? NumAxInFlight + ComputeFifoDepth : 32'd2 ), % else: // Atleast one write protocol uses combined aw and w -> Need to buffer read meta requests // As a write could depend on up to two reads - stream_fifo_optimal_wrap #( + cc_stream_fifo_optimal_wrap #( .Depth ( 2 ), % endif - .type_t (\ + .data_t (\ % if one_write_port: write_meta_channel_t ), % else: @@ -931,7 +926,7 @@ w_req.decouple_aw || (w_req.w_dp_req.dst_protocol inside {\ ) i_aw_fifo ( .clk_i, .rst_ni, - .testmode_i, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), .usage_o ( /* NOT CONNECTED */ ), .data_i ( \ @@ -949,8 +944,8 @@ w_req.decouple_aw || (w_req.w_dp_req.dst_protocol inside {\ % else: // Add fall-through register to allow the input to be ready if the output is not. This // does not add a cycle of delay - fall_through_register #( - .T (\ + cc_fall_through_register #( + .data_t (\ % if one_write_port: write_meta_channel_t ) % else: @@ -959,7 +954,6 @@ w_req.decouple_aw || (w_req.w_dp_req.dst_protocol inside {\ ) i_aw_fall_through_register ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .testmode_i ( testmode_i ), .clr_i ( 1'b0 ), .valid_i ( w_valid ), .ready_o ( aw_ready ), diff --git a/src/backend/tpl/idma_backend_synth.sv.tpl b/src/backend/tpl/idma_backend_synth.sv.tpl index 0df228c6b..71567de57 100644 --- a/src/backend/tpl/idma_backend_synth.sv.tpl +++ b/src/backend/tpl/idma_backend_synth.sv.tpl @@ -95,7 +95,6 @@ module idma_backend_synth_${name_uniqueifier} #( )( input logic clk_i, input logic rst_ni, - input logic test_i, input logic req_valid_i, output logic req_ready_o, @@ -349,7 +348,6 @@ ${p}_${database[p]['write_meta_channel']}_width\ ) i_idma_backend ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .testmode_i ( test_i ), .idma_req_i ( idma_req ), .req_valid_i ( req_valid_i ), .req_ready_o ( req_ready_o ), diff --git a/src/backend/tpl/idma_transport_layer.sv.tpl b/src/backend/tpl/idma_transport_layer.sv.tpl index f3f02aefc..6d2b2f3cd 100644 --- a/src/backend/tpl/idma_transport_layer.sv.tpl +++ b/src/backend/tpl/idma_transport_layer.sv.tpl @@ -78,8 +78,6 @@ module idma_transport_layer_${name_uniqueifier} #( input logic clk_i, /// Asynchronous reset, active low input logic rst_ni, - /// Testmode in - input logic testmode_i, % for protocol in used_read_protocols: /// ${database[protocol]['full_name']} read request @@ -382,7 +380,6 @@ ${rendered_read_ports[read_port]} ) i_dataflow_element ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .testmode_i ( testmode_i ), .data_i ( buffer_in_shifted ), .valid_i ( buffer_in_valid ), .ready_o ( buffer_in_ready ), @@ -456,11 +453,12 @@ ${rendered_read_ports[read_port]} //-------------------------------------- // Split write request to write response fifo and write ports - stream_fork #( - .N_OUP ( 2 ) + cc_stream_fork #( + .NumOup ( 2 ) ) i_write_stream_fork ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( w_dp_valid_i ), .ready_o ( w_dp_ready_o ), .valid_o ( { w_resp_fifo_in_valid, w_dp_req_valid } ), @@ -519,14 +517,14 @@ ${rendered_write_ports[write_port]} // Insert when data write happens // Remove when write response comes - stream_fifo_optimal_wrap #( + cc_stream_fifo_optimal_wrap #( .Depth ( NumAxInFlight ), - .type_t ( idma_pkg::protocol_e ), + .data_t ( idma_pkg::protocol_e ), .PrintInfo ( PrintFifoInfo ) ) i_write_response_fifo ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .testmode_i ( testmode_i ), + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), .usage_o ( /* NOT CONNECTED */ ), .data_i ( w_dp_req_i.dst_protocol ), @@ -538,14 +536,14 @@ ${rendered_write_ports[write_port]} ); % if not mh_format['aw'][wp] == '': - stream_fifo_optimal_wrap #( + cc_stream_fifo_optimal_wrap #( .Depth ( NumAxInFlight ), - .type_t ( idma_pkg::multihead_t ), + .data_t ( idma_pkg::multihead_t ), .PrintInfo ( PrintFifoInfo ) ) i_write_response_fifo_multihead ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .testmode_i ( testmode_i ), + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), .usage_o ( /* NOT CONNECTED */ ), .data_i ( w_dp_req_i.dst_head ), @@ -596,13 +594,12 @@ ${rendered_write_ports[write_port]} end // Fall through register for the write response to be ready - fall_through_register #( - .T ( w_dp_rsp_t ) + cc_fall_through_register #( + .data_t ( w_dp_rsp_t ) ) i_write_rsp_channel_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), .clr_i ( 1'b0 ), - .testmode_i ( testmode_i ), .valid_i ( w_dp_rsp_mux_valid ), .ready_o ( w_dp_rsp_mux_ready ), @@ -614,8 +611,8 @@ ${rendered_write_ports[write_port]} ); // Join write response fifo and write port responses - stream_join #( - .N_INP ( 2 ) + cc_stream_join #( + .NumInp ( 2 ) ) i_write_stream_join ( .inp_valid_i ( { w_resp_fifo_out_valid, w_dp_rsp_valid } ), .inp_ready_o ( { w_resp_fifo_out_ready, w_dp_rsp_ready } ), diff --git a/src/db/idma_init.yml b/src/db/idma_init.yml index d4210a43e..cc89871a6 100644 --- a/src/db/idma_init.yml +++ b/src/db/idma_init.yml @@ -42,12 +42,13 @@ typedefs: | logic req_ready; } init_rsp_t; read_bridge_template: | - spill_register #( - .T ( logic ), + cc_spill_register #( + .data_t ( logic ), .Bypass ( 1'b0 ) ) i_init_read_bridge ( .clk_i ( clk ), - .rst_ni ( rst_n ), + .rst_ni ( rst_n ), + .clr_i ( 1'b0 ), .valid_i ( init_read_req.req_valid ), .ready_o ( init_read_rsp.req_ready ), .data_i ( 1'b0 ), diff --git a/src/frontend/desc64/idma_desc64_ar_gen_prefetch.sv b/src/frontend/desc64/idma_desc64_ar_gen_prefetch.sv index fa540037c..16aef22e1 100644 --- a/src/frontend/desc64/idma_desc64_ar_gen_prefetch.sv +++ b/src/frontend/desc64/idma_desc64_ar_gen_prefetch.sv @@ -80,7 +80,7 @@ localparam logic [2:0] AxiSize = `MIN(`MIN($clog2(DataWidthBytes), localparam logic [7:0] AxiLength = DescriptorSize / DataWidthBytes - 1; localparam int unsigned SpeculationWidth = $clog2(NSpeculation + 1); -localparam int unsigned SpeculationUsageWidth = $clog2(NSpeculation); +localparam int unsigned SpeculationUsageWidth = $clog2(NSpeculation + 1); typedef struct packed { logic speculative; @@ -238,15 +238,15 @@ assign queued_address_ready_o = !take_from_next && (!base_valid_q || next_addr_v `FF(flush_q, flush_d, 1'b0) assign flush_d = flush; -stream_fifo #( - .FALL_THROUGH(1'b0), - .DEPTH (NSpeculation), - .T (addr_t) +cc_stream_fifo #( + .FallThrough(1'b0), + .Depth (NSpeculation), + .data_t (addr_t) ) i_speculation_fifo ( .clk_i, .rst_ni, + .clr_i (1'b0), .flush_i (flush_q), - .testmode_i(1'b0), .usage_o (speculation_usage_short), .data_i (staging_addr.addr), .valid_i (staging_addr_valid_speculation), @@ -256,15 +256,15 @@ stream_fifo #( .ready_i (speculation_ready) ); -stream_fifo #( - .FALL_THROUGH(1'b1), - .DEPTH (NSpeculation), - .T (addr_spec_t) +cc_stream_fifo #( + .FallThrough(1'b1), + .Depth (NSpeculation), + .data_t (addr_spec_t) ) i_pending_ars ( .clk_i, .rst_ni, + .clr_i (1'b0), .flush_i (flush), - .testmode_i(1'b0), .usage_o ( /* unconnected */ ), .data_i (next_ar), .valid_i (next_ar_valid), @@ -274,15 +274,15 @@ stream_fifo #( .ready_i (staging_addr_ready_pending) ); -stream_fifo #( - .FALL_THROUGH(1'b1), - .DEPTH (1), - .T (addr_t) +cc_stream_fifo #( + .FallThrough(1'b1), + .Depth (1), + .data_t (addr_t) ) i_legalization_fifo ( .clk_i, .rst_ni, + .clr_i (1'b0), .flush_i (1'b0), - .testmode_i(1'b0), .usage_o (legalization_usage), .data_i (staging_addr_legalization), .valid_i (staging_addr_valid_legalization), diff --git a/src/frontend/desc64/idma_desc64_top.sv b/src/frontend/desc64/idma_desc64_top.sv index 995b1382e..28698a39f 100644 --- a/src/frontend/desc64/idma_desc64_top.sv +++ b/src/frontend/desc64/idma_desc64_top.sv @@ -149,9 +149,10 @@ logic next_wb_addr_ready; `define MAX(a, b) (a) > (b) ? a : b localparam int unsigned PendingFifoDepthBits = `MAX($clog2(PendingFifoDepth), 1); +localparam int unsigned PendingFifoUsageWidth = `MAX($clog2(PendingFifoDepth + 1), 1); -logic [PendingFifoDepthBits-1:0] idma_req_used; -logic [PendingFifoDepthBits:0] idma_req_available; +logic [PendingFifoUsageWidth-1:0] idma_req_used; +logic [PendingFifoDepthBits:0] idma_req_available; logic [1:0] ws_per_writeback; // one bit extra for the 32 bit case @@ -366,15 +367,15 @@ idma_desc64_reader #( .idma_req_inflight_o (idma_req_inflight) ); -stream_fifo #( - .FALL_THROUGH (1'b1), - .DEPTH (InputFifoDepth), - .T (addr_t) +cc_stream_fifo #( + .FallThrough (1'b1), + .Depth (InputFifoDepth), + .data_t (addr_t) ) i_input_addr_fifo ( .clk_i, .rst_ni, + .clr_i (1'b0), .flush_i (1'b0), - .testmode_i(1'b0), .usage_o (/* unconnected */), .data_i (input_addr), .valid_i (input_addr_valid), @@ -384,15 +385,15 @@ stream_fifo #( .ready_i (queued_addr_ready) ); -stream_fifo #( - .FALL_THROUGH (1'b1), - .DEPTH (PendingFifoDepth + BackendDepth), - .T (addr_t) +cc_stream_fifo #( + .FallThrough (1'b1), + .Depth (PendingFifoDepth + BackendDepth), + .data_t (addr_t) ) i_pending_addr_fifo ( .clk_i, .rst_ni, + .clr_i (1'b0), .flush_i (1'b0), - .testmode_i(1'b0), .usage_o (/* unconnected */), .data_i (feedback_addr), .valid_i (feedback_addr_valid), @@ -402,15 +403,15 @@ stream_fifo #( .ready_i (next_wb_addr_ready && idma_rsp_valid_i) ); -stream_fifo #( - .FALL_THROUGH (1'b0), - .DEPTH (PendingFifoDepth), - .T (idma_req_t) +cc_stream_fifo #( + .FallThrough (1'b0), + .Depth (PendingFifoDepth), + .data_t (idma_req_t) ) i_idma_request_fifo ( .clk_i, .rst_ni, + .clr_i (1'b0), .flush_i (1'b0), - .testmode_i(1'b0), .usage_o (idma_req_used), .data_i (idma_req), .valid_i (idma_req_valid), @@ -420,15 +421,15 @@ stream_fifo #( .ready_i (idma_req_ready_i) ); -stream_fifo #( - .FALL_THROUGH (1'b0), - .DEPTH (PendingFifoDepth + MaxAWWPending + BackendDepth), - .T (logic) +cc_stream_fifo #( + .FallThrough (1'b0), + .Depth (PendingFifoDepth + MaxAWWPending + BackendDepth), + .data_t (logic) ) i_irq_fifo ( .clk_i, .rst_ni, + .clr_i (1'b0), .flush_i (1'b0), - .testmode_i(1'b0), .usage_o (/* unconnected */), .data_i (do_irq), .valid_i (do_irq_valid), @@ -438,15 +439,15 @@ stream_fifo #( .ready_i (master_rsp_i.b_valid) ); -stream_fifo #( - .FALL_THROUGH (1'b0), - .DEPTH (MaxAWWPending), - .T (addr_t) +cc_stream_fifo #( + .FallThrough (1'b0), + .Depth (MaxAWWPending), + .data_t (addr_t) ) i_aw_addrs ( .clk_i, .rst_ni, + .clr_i (1'b0), .flush_i (1'b0), - .testmode_i(1'b0), .usage_o (/* unconnected */), .data_i (next_wb_addr), .valid_i (next_wb_addr_valid && idma_rsp_valid_i), diff --git a/src/frontend/inst64/idma_inst64_events.sv b/src/frontend/inst64/idma_inst64_events.sv index e424f31c3..0a1eb05fe 100644 --- a/src/frontend/inst64/idma_inst64_events.sv +++ b/src/frontend/inst64/idma_inst64_events.sv @@ -33,8 +33,8 @@ module idma_inst64_events #( logic [$clog2(StrbWidth)+1-1:0] num_bytes_written; // need popcount common cell to get the number of bytes active in the strobe signal - popcount #( - .INPUT_WIDTH ( StrbWidth ) + cc_popcount #( + .InputWidth ( StrbWidth ) ) i_popcount ( .data_i ( axi_req_i.w.strb ), .popcount_o ( num_bytes_written ) diff --git a/src/frontend/inst64/idma_inst64_top.sv b/src/frontend/inst64/idma_inst64_top.sv index a3c166b33..802961c36 100644 --- a/src/frontend/inst64/idma_inst64_top.sv +++ b/src/frontend/inst64/idma_inst64_top.sv @@ -41,7 +41,6 @@ module idma_inst64_top #( ) ( input logic clk_i, input logic rst_ni, - input logic testmode_i, // AXI4 bus output axi_req_t [NumChannels-1:0] axi_req_o, input axi_res_t [NumChannels-1:0] axi_res_i, @@ -243,7 +242,6 @@ module idma_inst64_top #( ) i_idma_backend_rw_axi_rw_init_rw_obi ( .clk_i, .rst_ni, - .testmode_i, .idma_req_i ( idma_req [c] ), .req_valid_i ( idma_req_valid [c] ), .req_ready_o ( idma_req_ready [c] ), @@ -283,11 +281,12 @@ module idma_inst64_top #( ); // INIT setup - spill_register #( - .T ( logic [7:0] ) + cc_spill_register #( + .data_t ( logic [7:0] ) ) i_spill_register_init ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( init_read_req[c].req_valid ), .ready_o ( init_read_rsp[c].req_ready ), .data_i ( init_read_req[c].req_chan.cfg[7:0] ), @@ -307,9 +306,9 @@ module idma_inst64_top #( end `FF(obi_we_q[c], obi_we_d[c], '0, clk_i, rst_ni) - stream_mux #( - .DATA_T ( obi_a_chan_t ), - .N_INP ( 32'd2 ) + cc_stream_mux #( + .data_t ( obi_a_chan_t ), + .NumInp ( 32'd2 ) ) i_obi_rw_mux ( .inp_data_i ( {obi_write_req[c].a, obi_read_req[c].a } ), .inp_valid_i ( {obi_write_req[c].req, obi_read_req[c].req } ), @@ -320,8 +319,8 @@ module idma_inst64_top #( .oup_ready_i ( obi_res_i[c].gnt ) ); - stream_demux #( - .N_OUP ( 32'd2 ) + cc_stream_demux #( + .NumOup ( 32'd2 ) ) i_obi_rw_demux ( .inp_valid_i ( obi_res_i[c].rvalid ), .inp_ready_o ( obi_req_o[c].rready ), @@ -383,14 +382,14 @@ module idma_inst64_top #( .busy_o ( idma_nd_busy [c] ) ); - stream_fifo_optimal_wrap #( + cc_stream_fifo_optimal_wrap #( .Depth ( DMAReqFifoDepth ), - .type_t ( idma_nd_req_t ), + .data_t ( idma_nd_req_t ), .PrintInfo ( 1'b0 ) ) i_stream_fifo_optimal_wrap ( .clk_i, .rst_ni, - .testmode_i, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), .usage_o ( /* NC */ ), .data_i ( idma_fe_req ), @@ -453,11 +452,12 @@ module idma_inst64_top #( // Spill register for response channel //-------------------------------------- // the response path needs to be decoupled - spill_register #( - .T ( acc_res_t ) + cc_spill_register #( + .data_t ( acc_res_t ) ) i_spill_register ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( acc_res_valid ), .ready_o ( acc_res_ready ), .data_i ( acc_res ), @@ -467,7 +467,7 @@ module idma_inst64_top #( ); // Address Decode - addr_decode #( + cc_addr_decode #( .NoIndices ( NoIndices ), .NoRules ( NoRules ), .addr_t ( addr_t ), @@ -482,7 +482,7 @@ module idma_inst64_top #( .default_idx_i ( idma_pkg::ToSoC ) ); // address decoder for destination address - addr_decode #( + cc_addr_decode #( .NoIndices ( NoIndices ), .addr_t ( addr_t ), .NoRules ( NoRules ), diff --git a/src/frontend/reg/tpl/idma_reg.sv.tpl b/src/frontend/reg/tpl/idma_reg.sv.tpl index ec511ac44..4611b5f7c 100644 --- a/src/frontend/reg/tpl/idma_reg.sv.tpl +++ b/src/frontend/reg/tpl/idma_reg.sv.tpl @@ -36,7 +36,7 @@ module idma_${identifier} #( /// Width of the transfer id (max 32-bit) parameter int unsigned IdCounterWidth = 32'd32, /// Dependent parameter: Stream Idx - parameter int unsigned StreamWidth = cf_math_pkg::idx_width(NumStreams), + parameter int unsigned StreamWidth = cc_pkg::idx_width(NumStreams), % if _fam == 'apb': /// APB4 request type parameter type apb_req_t = logic, @@ -98,7 +98,7 @@ module idma_${identifier} #( dma_req_t [NumRegs-1:0] arb_dma_req_q; logic [NumRegs-1:0] arb_valid; logic [NumRegs-1:0] arb_ready; - logic [cf_math_pkg::idx_width(NumRegs)-1:0] arb_idx; + logic [cc_pkg::idx_width(NumRegs)-1:0] arb_idx; // per-port launch-pending latch logic [NumRegs-1:0] launch_pending_q; @@ -305,16 +305,16 @@ module idma_${identifier} #( end // arbitration - rr_arb_tree #( + cc_rr_arb_tree #( .NumIn ( NumRegs ), - .DataType ( dma_req_t ), + .data_t ( dma_req_t ), .ExtPrio ( 0 ), .AxiVldRdy ( 1 ), .LockIn ( 1 ) ) i_rr_arb_tree ( .clk_i, .rst_ni, - .flush_i ( 1'b0 ), + .clr_i ( 1'b0 ), .rr_i ( '0 ), .req_i ( arb_valid ), .gnt_o ( arb_ready ), diff --git a/src/midend/idma_mp_dist_midend.sv b/src/midend/idma_mp_dist_midend.sv index 362d93742..99b34c04e 100644 --- a/src/midend/idma_mp_dist_midend.sv +++ b/src/midend/idma_mp_dist_midend.sv @@ -96,11 +96,12 @@ module idma_mp_dist_midend #( // Fork logic [NumBEs-1:0] valid, ready; - stream_fork #( - .N_OUP (NumBEs) + cc_stream_fork #( + .NumOup (NumBEs) ) i_stream_fork ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( idma_req_valid_i ), .ready_o ( idma_req_ready_o ), .valid_o ( valid ), diff --git a/src/midend/idma_mp_split_midend.sv b/src/midend/idma_mp_split_midend.sv index 6d21612ce..e2cbb580e 100644 --- a/src/midend/idma_mp_split_midend.sv +++ b/src/midend/idma_mp_split_midend.sv @@ -105,8 +105,8 @@ module idma_mp_split_midend #( state_t state_d, state_q; idma_req_t req_d, req_q; - `FFARN(state_q, state_d, Idle, clk_i, rst_ni) - `FFARN(req_q, req_d, '0, clk_i, rst_ni) + `FF(state_q, state_d, Idle, clk_i, rst_ni) + `FF(req_q, req_d, '0, clk_i, rst_ni) always_comb begin : proc_splitting // defaults diff --git a/src/midend/idma_nd_midend.sv b/src/midend/idma_nd_midend.sv index fd3adaeec..6d02aedac 100644 --- a/src/midend/idma_nd_midend.sv +++ b/src/midend/idma_nd_midend.sv @@ -63,7 +63,7 @@ module idma_nd_midend #( ); /// How many bits are required to index the counters - localparam int unsigned StrideSelWidth = $clog2(NumDim-1) + 'd1; + localparam int unsigned StrideSelWidth = $clog2(NumDim); `ifndef SYNTHESIS // strides are added with same-width arithmetic; narrower strides would not sign-extend @@ -157,8 +157,8 @@ module idma_nd_midend #( //-------------------------------------- // The popcount is used to identify the highest stage that is done. This is then added to the // current address register. - popcount #( - .INPUT_WIDTH ( NumDim-1 ) + cc_popcount #( + .InputWidth ( NumDim-1 ) ) i_popcount ( .data_i ( stage_clear ), .popcount_o ( stride_sel_d ) diff --git a/src/midend/idma_nd_midend_synth.sv b/src/midend/idma_nd_midend_synth.sv index e6ddc92b2..48e84c59a 100644 --- a/src/midend/idma_nd_midend_synth.sv +++ b/src/midend/idma_nd_midend_synth.sv @@ -78,7 +78,6 @@ module idma_nd_midend_synth #( )( input logic clk_i, input logic rst_ni, - input logic test_i, input logic req_valid_i, output logic req_ready_o, @@ -282,7 +281,6 @@ module idma_nd_midend_synth #( ) i_idma_backend ( .clk_i, .rst_ni, - .testmode_i ( test_i ), .idma_req_i ( idma_req ), .req_valid_i ( idma_req_valid ), .req_ready_o ( idma_req_ready ), diff --git a/src/midend/idma_rt_midend.sv b/src/midend/idma_rt_midend.sv index 2d11e98bb..5a81d1f29 100644 --- a/src/midend/idma_rt_midend.sv +++ b/src/midend/idma_rt_midend.sv @@ -117,13 +117,13 @@ module idma_rt_midend #( // generate the counters timing the events and assemble the transfers for (genvar c = 0; c < NumEvents; c++) begin : gen_counters // counter instance - counter #( - .WIDTH ( EventCntWidth ), - .STICKY_OVERFLOW ( 1'b0 ) + cc_counter #( + .Width ( EventCntWidth ), + .StickyOverflow ( 1'b0 ) ) i_counter ( .clk_i, .rst_ni, - .clear_i ( 1'b0 ), + .clr_i ( 1'b0 ), .en_i ( cnt_ena [c] ), .load_i ( cnt_load [c] ), .down_i ( 1'b1 ), @@ -155,13 +155,14 @@ module idma_rt_midend #( assign cnt_ena = event_ena_i & ~(event_valid); // arbitrates the events - stream_arbiter #( - .DATA_T ( idma_nd_req_t ), - .N_INP ( NumEvents ), - .ARBITER ( "rr" ) + cc_stream_arbiter #( + .data_t ( idma_nd_req_t ), + .NumInp ( NumEvents ), + .ArbMode ( cc_pkg::ARB_RR ) ) i_stream_arbiter ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .inp_data_i ( idma_nd_req ), .inp_valid_i ( event_valid ), .inp_ready_o ( event_ready ), @@ -171,13 +172,14 @@ module idma_rt_midend #( ); // arbitrates the events - stream_arbiter #( - .DATA_T ( ext_arb_t ), - .N_INP ( 32'd2 ), - .ARBITER ( "rr" ) + cc_stream_arbiter #( + .data_t ( ext_arb_t ), + .NumInp ( 32'd2 ), + .ArbMode ( cc_pkg::ARB_RR ) ) i_stream_arbiter_bypass ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .inp_data_i ( { ext_req, int_req } ), .inp_valid_i ( { nd_req_valid_i, nd_req_valid_int } ), .inp_ready_o ( { nd_req_ready_o, nd_req_ready_int } ), @@ -198,15 +200,15 @@ module idma_rt_midend #( assign choice = out_req.src; // safe the choice in a fifo - stream_fifo #( - .FALL_THROUGH ( 1'b0 ), - .DATA_WIDTH ( 32'd1 ), - .DEPTH ( NumOutstanding ) + cc_stream_fifo #( + .FallThrough ( 1'b0 ), + .DataWidth ( 32'd1 ), + .Depth ( NumOutstanding ) ) i_stream_fifo ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i ( 1'b0 ), .usage_o ( /* NC */ ), .data_i ( choice ), .valid_i ( nd_req_valid_o & nd_req_ready_i & choice_fifo_ready ), @@ -217,8 +219,8 @@ module idma_rt_midend #( ); // arbitration of responses - stream_demux #( - .N_OUP ( 32'd2 ) + cc_stream_demux #( + .NumOup ( 32'd2 ) ) i_stream_demux ( .inp_valid_i ( burst_rsp_valid_i ), .inp_ready_o ( burst_rsp_ready_o ), diff --git a/target/sim/vsim/wave/tpl/backend.do.tpl b/target/sim/vsim/wave/tpl/backend.do.tpl index 0d6140b85..46b984f19 100644 --- a/target/sim/vsim/wave/tpl/backend.do.tpl +++ b/target/sim/vsim/wave/tpl/backend.do.tpl @@ -10,7 +10,6 @@ onerror {resume} quietly WaveActivateNextPane {} 0 add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/clk_i add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/rst_ni -add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/testmode_i add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/idma_req_i add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/req_valid_i add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/req_ready_o @@ -99,7 +98,6 @@ add wave -noupdate -group Legalizer /tb_idma_backend_${name_uniqueifier}/i_idma_ add wave -noupdate -group Legalizer /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/w_done add wave -noupdate -group {Transport Layer} /tb_idma_backend_${name_uniqueifier}/i_idma_backend/i_idma_transport_layer/clk_i add wave -noupdate -group {Transport Layer} /tb_idma_backend_${name_uniqueifier}/i_idma_backend/i_idma_transport_layer/rst_ni -add wave -noupdate -group {Transport Layer} /tb_idma_backend_${name_uniqueifier}/i_idma_backend/i_idma_transport_layer/testmode_i % for protocol in used_read_protocols: add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/i_idma_transport_layer/${protocol}_read_req_o add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/i_idma_transport_layer/${protocol}_read_rsp_i @@ -121,7 +119,6 @@ add wave -noupdate -group {Write Response FIFO} -expand /tb_idma_backend_${name_ % if one_read_port and one_write_port and ('axi' in used_read_protocols) and ('axi' in used_write_protocols): add wave -noupdate -group R-AW-Coupler /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/clk_i add wave -noupdate -group R-AW-Coupler /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/rst_ni -add wave -noupdate -group R-AW-Coupler /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/testmode_i add wave -noupdate -group R-AW-Coupler /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/r_rsp_valid_i add wave -noupdate -group R-AW-Coupler /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/r_rsp_ready_i add wave -noupdate -group R-AW-Coupler /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/r_rsp_first_i diff --git a/test/frontend/tb_idma_desc64_bench.sv b/test/frontend/tb_idma_desc64_bench.sv index 35be1e6e7..24b5a64a5 100644 --- a/test/frontend/tb_idma_desc64_bench.sv +++ b/test/frontend/tb_idma_desc64_bench.sv @@ -282,7 +282,6 @@ module tb_idma_desc64_bench ) i_idma_backend ( .clk_i ( clk ), .rst_ni ( rst_n ), - .testmode_i ( 1'b0 ), .idma_req_i ( dma_be_req ), .req_valid_i ( dma_be_req_valid ), .req_ready_o ( dma_be_req_ready ), @@ -361,7 +360,6 @@ module tb_idma_desc64_bench ) i_mux ( .clk_i (clk), .rst_ni (rst_n), - .test_i (1'b0), .slv_reqs_i ({dma_be_master_request, dma_fe_master_request}), .slv_resps_o({dma_be_master_response, dma_fe_master_response}), .mst_req_o (axi_throttle_req), diff --git a/test/future/idma_tb_per2axi.sv b/test/future/idma_tb_per2axi.sv index 6d5bb98f4..59a6602d7 100644 --- a/test/future/idma_tb_per2axi.sv +++ b/test/future/idma_tb_per2axi.sv @@ -14,7 +14,6 @@ module idma_tb_fifo_v3 #( input logic clk_i, input logic rst_ni, input logic flush_i, - input logic testmode_i, output logic full_o, output logic empty_o, output logic [ADDR_DEPTH-1:0] usage_o, @@ -112,7 +111,6 @@ module idma_tb_fifo_v2 #( input logic clk_i, input logic rst_ni, input logic flush_i, - input logic testmode_i, output logic full_o, output logic empty_o, output logic alm_full_o, @@ -139,7 +137,6 @@ module idma_tb_fifo_v2 #( .clk_i, .rst_ni, .flush_i, - .testmode_i, .full_o, .empty_o, .usage_o(usage), @@ -165,7 +162,6 @@ module idma_tb_fifo #( input logic clk_i, input logic rst_ni, input logic flush_i, - input logic testmode_i, output logic full_o, output logic empty_o, output logic threshold_o, @@ -184,7 +180,6 @@ module idma_tb_fifo #( .clk_i (clk_i), .rst_ni (rst_ni), .flush_i (flush_i), - .testmode_i (testmode_i), .full_o (full_o), .empty_o (empty_o), .alm_full_o (threshold_o), @@ -201,7 +196,6 @@ module idma_tb_axi_single_slice #( ) ( input logic clk_i, input logic rst_ni, - input logic testmode_i, input logic valid_i, output logic ready_o, input logic [DATA_WIDTH-1:0] data_i, @@ -221,7 +215,6 @@ module idma_tb_axi_single_slice #( .rst_ni (rst_ni), .flush_i (1'b0), .threshold_o(), - .testmode_i (testmode_i), .full_o (full), .empty_o (empty), .data_i (data_i), @@ -288,7 +281,6 @@ module idma_tb_axi_ar_buffer #( ) i_axi_single_slice ( .clk_i (clk_i), .rst_ni (rst_ni), - .testmode_i(test_en_i), .valid_i (slave_valid_i), .ready_o (slave_ready_o), .data_i (s_data_in), @@ -355,7 +347,6 @@ module idma_tb_axi_aw_buffer #( ) i_axi_single_slice ( .clk_i (clk_i), .rst_ni (rst_ni), - .testmode_i(test_en_i), .valid_i (slave_valid_i), .ready_o (slave_ready_o), .data_i (s_data_in), @@ -393,7 +384,6 @@ module idma_tb_axi_b_buffer #( ) i_axi_single_slice ( .clk_i (clk_i), .rst_ni (rst_ni), - .testmode_i(test_en_i), .valid_i (slave_valid_i), .ready_o (slave_ready_o), .data_i (s_data_in), @@ -437,7 +427,6 @@ module idma_tb_axi_r_buffer #( ) i_axi_single_slice ( .clk_i (clk_i), .rst_ni (rst_ni), - .testmode_i(test_en_i), .valid_i (slave_valid_i), .ready_o (slave_ready_o), .data_i (s_data_in), @@ -478,7 +467,6 @@ module idma_tb_axi_w_buffer #( ) i_axi_single_slice ( .clk_i (clk_i), .rst_ni (rst_ni), - .testmode_i(test_en_i), .valid_i (slave_valid_i), .ready_o (slave_ready_o), .data_i (s_data_in), diff --git a/test/midend/tb_idma_nd_midend.sv b/test/midend/tb_idma_nd_midend.sv index e2e762a9d..cefcc9352 100644 --- a/test/midend/tb_idma_nd_midend.sv +++ b/test/midend/tb_idma_nd_midend.sv @@ -407,7 +407,6 @@ module tb_idma_nd_midend import idma_pkg::*; #( ) i_idma_backend ( .clk_i ( clk ), .rst_ni ( rst_n ), - .testmode_i ( 1'b0 ), .idma_req_i ( burst_req ), .req_valid_i ( burst_req_valid ), .req_ready_o ( burst_req_ready ), diff --git a/test/tb_idma_backend_multihead.sv b/test/tb_idma_backend_multihead.sv index 2917ca28d..02bce8942 100644 --- a/test/tb_idma_backend_multihead.sv +++ b/test/tb_idma_backend_multihead.sv @@ -152,7 +152,7 @@ module tb_idma_backend_multihead import idma_pkg::*; #( .idma_busy_t (idma_busy_t), .axi_req_t (axi_req_t), .axi_rsp_t (axi_rsp_t), .write_meta_channel_t (write_meta_channel_t), .read_meta_channel_t (read_meta_channel_t) ) i_idma_backend ( - .clk_i (clk), .rst_ni (rst_n), .testmode_i (1'b0), + .clk_i (clk), .rst_ni (rst_n), .idma_req_i (idma_req), .req_valid_i (req_valid), .req_ready_o (req_ready), .idma_rsp_o (idma_rsp), .rsp_valid_o (rsp_valid), .rsp_ready_i (rsp_ready), .idma_eh_req_i (idma_eh_req), .eh_req_valid_i (eh_req_valid), .eh_req_ready_o (eh_req_ready), diff --git a/test/tb_idma_backend_multihead_rw.sv b/test/tb_idma_backend_multihead_rw.sv index b804907ed..47049de2a 100644 --- a/test/tb_idma_backend_multihead_rw.sv +++ b/test/tb_idma_backend_multihead_rw.sv @@ -143,7 +143,7 @@ module tb_idma_backend_multihead_rw import idma_pkg::*; #( .idma_busy_t (idma_busy_t), .axi_req_t (axi_req_t), .axi_rsp_t (axi_rsp_t), .write_meta_channel_t (write_meta_channel_t), .read_meta_channel_t (read_meta_channel_t) ) i_idma_backend ( - .clk_i (clk), .rst_ni (rst_n), .testmode_i (1'b0), + .clk_i (clk), .rst_ni (rst_n), .idma_req_i (idma_req), .req_valid_i (req_valid), .req_ready_o (req_ready), .idma_rsp_o (idma_rsp), .rsp_valid_o (rsp_valid), .rsp_ready_i (rsp_ready), .idma_eh_req_i (idma_eh_req), .eh_req_valid_i (eh_req_valid), .eh_req_ready_o (eh_req_ready), diff --git a/test/tb_idma_mxneg.sv b/test/tb_idma_mxneg.sv index 775cd6c4d..5d08f6ac3 100644 --- a/test/tb_idma_mxneg.sv +++ b/test/tb_idma_mxneg.sv @@ -46,7 +46,7 @@ module tb_idma_mxneg .idma_busy_t(idma_busy_t), .axi_req_t(axi_req_t), .axi_rsp_t(axi_rsp_t), .write_meta_channel_t(write_meta_channel_t), .read_meta_channel_t(read_meta_channel_t) ) i_idma_backend ( - .clk_i(clk), .rst_ni(rst_n), .testmode_i(1'b0), + .clk_i(clk), .rst_ni(rst_n), .idma_req_i(idma_req), .req_valid_i(req_valid), .req_ready_o(req_ready), .idma_rsp_o(idma_rsp), .rsp_valid_o(rsp_valid), .rsp_ready_i(rsp_ready), .idma_eh_req_i(idma_eh_req), .eh_req_valid_i(eh_req_valid), .eh_req_ready_o(eh_req_ready), diff --git a/test/tb_idma_mxperf.sv b/test/tb_idma_mxperf.sv index ce401c180..17c2a347f 100644 --- a/test/tb_idma_mxperf.sv +++ b/test/tb_idma_mxperf.sv @@ -44,7 +44,7 @@ module tb_idma_mxperf .idma_busy_t(idma_busy_t), .axi_req_t(axi_req_t), .axi_rsp_t(axi_rsp_t), .write_meta_channel_t(write_meta_channel_t), .read_meta_channel_t(read_meta_channel_t) ) i_idma_backend ( - .clk_i(clk), .rst_ni(rst_n), .testmode_i(1'b0), + .clk_i(clk), .rst_ni(rst_n), .idma_req_i(idma_req), .req_valid_i(req_valid), .req_ready_o(req_ready), .idma_rsp_o(idma_rsp), .rsp_valid_o(rsp_valid), .rsp_ready_i(rsp_ready), .idma_eh_req_i(idma_eh_req), .eh_req_valid_i(eh_req_valid), .eh_req_ready_o(eh_req_ready), diff --git a/test/tb_idma_mxquant.sv b/test/tb_idma_mxquant.sv index 314758e04..7bf22fa9b 100644 --- a/test/tb_idma_mxquant.sv +++ b/test/tb_idma_mxquant.sv @@ -49,7 +49,7 @@ module tb_idma_mxquant .idma_busy_t(idma_busy_t), .axi_req_t(axi_req_t), .axi_rsp_t(axi_rsp_t), .write_meta_channel_t(write_meta_channel_t), .read_meta_channel_t(read_meta_channel_t) ) i_idma_backend ( - .clk_i(clk), .rst_ni(rst_n), .testmode_i(1'b0), + .clk_i(clk), .rst_ni(rst_n), .idma_req_i(idma_req), .req_valid_i(req_valid), .req_ready_o(req_ready), .idma_rsp_o(idma_rsp), .rsp_valid_o(rsp_valid), .rsp_ready_i(rsp_ready), .idma_eh_req_i(idma_eh_req), .eh_req_valid_i(eh_req_valid), .eh_req_ready_o(eh_req_ready), diff --git a/test/tb_idma_mxrand.sv b/test/tb_idma_mxrand.sv index 6981b2d81..324ca1e8c 100644 --- a/test/tb_idma_mxrand.sv +++ b/test/tb_idma_mxrand.sv @@ -81,7 +81,7 @@ module tb_idma_mxrand .idma_busy_t(idma_busy_t), .axi_req_t(axi_req_t), .axi_rsp_t(axi_rsp_t), .write_meta_channel_t(write_meta_channel_t), .read_meta_channel_t(read_meta_channel_t) ) i_idma_backend ( - .clk_i(clk), .rst_ni(rst_n), .testmode_i(1'b0), + .clk_i(clk), .rst_ni(rst_n), .idma_req_i(idma_req), .req_valid_i(req_valid), .req_ready_o(req_ready), .idma_rsp_o(idma_rsp), .rsp_valid_o(rsp_valid), .rsp_ready_i(rsp_ready), .idma_eh_req_i(idma_eh_req), .eh_req_valid_i(eh_req_valid), .eh_req_ready_o(eh_req_ready), diff --git a/test/tb_idma_mxroundtrip.sv b/test/tb_idma_mxroundtrip.sv index fbc21a9f3..c93d20b41 100644 --- a/test/tb_idma_mxroundtrip.sv +++ b/test/tb_idma_mxroundtrip.sv @@ -51,7 +51,7 @@ module tb_idma_mxroundtrip .idma_busy_t(idma_busy_t), .axi_req_t(axi_req_t), .axi_rsp_t(axi_rsp_t), .write_meta_channel_t(write_meta_channel_t), .read_meta_channel_t(read_meta_channel_t) ) i_idma_backend ( - .clk_i(clk), .rst_ni(rst_n), .testmode_i(1'b0), + .clk_i(clk), .rst_ni(rst_n), .idma_req_i(idma_req), .req_valid_i(req_valid), .req_ready_o(req_ready), .idma_rsp_o(idma_rsp), .rsp_valid_o(rsp_valid), .rsp_ready_i(rsp_ready), .idma_eh_req_i(idma_eh_req), .eh_req_valid_i(eh_req_valid), .eh_req_ready_o(eh_req_ready), diff --git a/test/tb_idma_transpose_b2b.sv b/test/tb_idma_transpose_b2b.sv index bd1e007bd..219c20d27 100644 --- a/test/tb_idma_transpose_b2b.sv +++ b/test/tb_idma_transpose_b2b.sv @@ -116,7 +116,7 @@ module tb_idma_transpose_b2b .idma_busy_t(idma_busy_t), .axi_req_t(axi_req_t), .axi_rsp_t(axi_rsp_t), .write_meta_channel_t(write_meta_channel_t), .read_meta_channel_t(read_meta_channel_t) ) i_idma_backend ( - .clk_i(clk), .rst_ni(rst_n), .testmode_i(1'b0), + .clk_i(clk), .rst_ni(rst_n), .idma_req_i(idma_req), .req_valid_i(req_valid), .req_ready_o(req_ready), .idma_rsp_o(idma_rsp), .rsp_valid_o(rsp_valid), .rsp_ready_i(rsp_ready), .idma_eh_req_i(idma_eh_req), .eh_req_valid_i(eh_req_valid), .eh_req_ready_o(eh_req_ready), diff --git a/test/tb_idma_transpose_nd.sv b/test/tb_idma_transpose_nd.sv index 0cefd70fa..98eae8894 100644 --- a/test/tb_idma_transpose_nd.sv +++ b/test/tb_idma_transpose_nd.sv @@ -133,7 +133,7 @@ module tb_idma_transpose_nd .idma_busy_t(idma_busy_t), .axi_req_t(axi_req_t), .axi_rsp_t(axi_rsp_t), .write_meta_channel_t(write_meta_channel_t), .read_meta_channel_t(read_meta_channel_t) ) i_idma_backend ( - .clk_i(clk), .rst_ni(rst_n), .testmode_i(1'b0), + .clk_i(clk), .rst_ni(rst_n), .idma_req_i(idma_req), .req_valid_i(req_valid), .req_ready_o(req_ready), .idma_rsp_o(idma_rsp), .rsp_valid_o(rsp_valid), .rsp_ready_i(rsp_ready), .idma_eh_req_i(idma_eh_req), .eh_req_valid_i(eh_req_valid), .eh_req_ready_o(eh_req_ready), diff --git a/test/tpl/tb_idma_backend.sv.tpl b/test/tpl/tb_idma_backend.sv.tpl index 700db10a1..64b83146a 100644 --- a/test/tpl/tb_idma_backend.sv.tpl +++ b/test/tpl/tb_idma_backend.sv.tpl @@ -657,7 +657,6 @@ ${p}_${database[p]['write_meta_channel']}_width\ ) i_idma_backend ( .clk_i ( clk ), .rst_ni ( rst_n ), - .testmode_i ( 1'b0 ), .idma_req_i ( idma_req ), .req_valid_i ( req_valid ), .req_ready_o ( req_ready ), @@ -708,8 +707,8 @@ ${p}_${database[p]['write_meta_channel']}_width\ % if 'axis' in used_write_protocols and False: // Delay iDMA response 2 cycles such that all axi stream writes are finished - spill_register #( - .T ( idma_rsp_t ), + cc_spill_register #( + .data_t ( idma_rsp_t ), .Bypass ( 1'b0 ) ) i_idma_rsp_cut ( .clk_i ( clk ), @@ -722,8 +721,8 @@ ${p}_${database[p]['write_meta_channel']}_width\ .data_o ( idma_rsp_w2 ) ); - spill_register #( - .T ( idma_rsp_t ), + cc_spill_register #( + .data_t ( idma_rsp_t ), .Bypass ( 1'b0 ) ) i_idma_rsp_cut_2 ( .clk_i ( clk ),