From dc4ed2b6f99044f96a4dcd257569f0132ce09f63 Mon Sep 17 00:00:00 2001 From: Daniel Keller Date: Tue, 6 Oct 2026 12:03:10 +0200 Subject: [PATCH] backend: Drop the redundant ready term from the write busy signal Every write unit only raises w_dp_ready_o while w_dp_valid_i is set, so the OR adds no information. It did add a combinational path from the write port ready into the backend busy and compute config stall, which closes a structural loop through a downstream AXI-to-OBI converter. --- src/backend/tpl/idma_transport_layer.sv.tpl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/backend/tpl/idma_transport_layer.sv.tpl b/src/backend/tpl/idma_transport_layer.sv.tpl index df4ed5a2f..f029dad46 100644 --- a/src/backend/tpl/idma_transport_layer.sv.tpl +++ b/src/backend/tpl/idma_transport_layer.sv.tpl @@ -656,7 +656,7 @@ ${rendered_write_ports[write_port]} // Module Control //-------------------------------------- assign r_dp_busy_o = r_dp_valid_i; - assign w_dp_busy_o = w_dp_valid_i | w_dp_ready_o; + assign w_dp_busy_o = w_dp_valid_i; assign buffer_busy_o = |buffer_out_valid; endmodule