diff --git a/src/backend/tpl/idma_transport_layer.sv.tpl b/src/backend/tpl/idma_transport_layer.sv.tpl
index df4ed5a2f..f029dad46 100644
--- a/src/backend/tpl/idma_transport_layer.sv.tpl
+++ b/src/backend/tpl/idma_transport_layer.sv.tpl
@@ -656,7 +656,7 @@ ${rendered_write_ports[write_port]}
     // Module Control
     //--------------------------------------
     assign r_dp_busy_o   = r_dp_valid_i;
-    assign w_dp_busy_o   = w_dp_valid_i | w_dp_ready_o;
+    assign w_dp_busy_o   = w_dp_valid_i;
     assign buffer_busy_o = |buffer_out_valid;
 
 endmodule