diff --git a/Bender.lock b/Bender.lock
index ec62e7a..a9bcff5 100644
--- a/Bender.lock
+++ b/Bender.lock
@@ -109,7 +109,7 @@ packages:
     - obi
     - register_interface
   insitu-cache:
-    revision: a407d39c832aa514551d1d153d93b60bb5d3a6e5
+    revision: b1d6617d2fe3fc29a01a86ab4bab592e615d0d20
     version: null
     source:
       Git: https://github.com/pulp-platform/Insitu-Cache.git
diff --git a/software/tests/l1-bypass/main.c b/software/tests/l1-bypass/main.c
index 212e579..464edc2 100644
--- a/software/tests/l1-bypass/main.c
+++ b/software/tests/l1-bypass/main.c
@@ -32,7 +32,6 @@
 //   6. timing, two visits each: a cached region gets faster after its cold
 //      visit, the bypass region does not (DRAM refresh makes a third visit noisy)
 //   7. bypass switched off: the same region now gets faster on its second visit
-//      (timing currently waived, see part 7)
 // Half of each tile's banks are private: the private/bypass range is served by
 // the local tile, everything below L1D_ADDR (counters, scratch, the cached
 // timing region) is shared and coherent across tiles. The cache xbar interleaves
@@ -399,7 +398,8 @@ int main() {
     // not speed up on its second visit. Restore the count once the hash is fixed.
     const int c_ok = (10 * tc[1] < 7 * tc[0]);
     printf("7  cycles same region, bypass off: %u %u -> %s\n", tc[0], tc[1],
-           c_ok ? "PASS" : "WAIVED (known way-hash collision)");
+           c_ok ? "PASS" : "FAILED");
+    num_fails += !(c_ok);
   }
 
   if (cid == 0) {