From cce9d441f9f240536349099c5f4919a5161f1bec Mon Sep 17 00:00:00 2001
From: Tej Kiran <kiran.tej@amd.com>
Date: Fri, 28 Aug 2026 08:48:11 -0500
Subject: [PATCH] fix: replace x86 asm with portable std::atomic_thread_fence

clflush/sfence are x86-only and break aarch64 builds. The file is
compiled unconditionally. clflush is also a no-op on uncached device
memory (hipDeviceMallocUncached). Replace with portable
std::atomic_thread_fence(std::memory_order_seq_cst).

Addresses PR #558 round-2 review comment R2-4.

Co-Authored-By: Claude <noreply@anthropic.com>
---
 src/application/transport/rdma/proxy/proxy_thread.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/application/transport/rdma/proxy/proxy_thread.cpp b/src/application/transport/rdma/proxy/proxy_thread.cpp
index 76f17baa4..5a3de3695 100644
--- a/src/application/transport/rdma/proxy/proxy_thread.cpp
+++ b/src/application/transport/rdma/proxy/proxy_thread.cpp
@@ -3,6 +3,7 @@
 #include "mori/core/transport/rdma/proxy/proxy_thread.hpp"
 
 #include <arpa/inet.h>
+#include <atomic>
 #include <hip/hip_runtime_api.h>
 #include <cerrno>
 #include <cstdio>
@@ -93,8 +94,7 @@ void ProxyThread::DrainCq(ProxyQpHandle& qph) {
           }
           volatile uint64_t* target = reinterpret_cast<volatile uint64_t*>(payload.addr);
           __atomic_fetch_add(target, payload.val, __ATOMIC_SEQ_CST);
-          asm volatile("clflush (%0)" :: "r"(target) : "memory");
-          asm volatile("sfence" ::: "memory");
+          std::atomic_thread_fence(std::memory_order_seq_cst);
           ibv_sge rsge{};
           rsge.addr = reinterpret_cast<uintptr_t>(qph.recv_buf) + recv_idx * 64;
           rsge.length = 64;