From 06b61cee836c35dcb4145fcc5fd8883df4d6cf9a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Desbiens?= Date: Tue, 13 Oct 2026 09:02:19 -0400 Subject: [PATCH] Removed internal milestone labels from the Cortex-R52 port Comments, CMake messages and demo banners in the Cortex-R52 port and its module example referred to development milestones by internal labels. The labels mean nothing to a reader of the port, and three FVP demo images were named after them. Replaced each label with a description of what the code or image does, and renamed demo_m2, demo_m3 and demo_m5 to demo_coop, demo_tick and demo_vfp, with their run targets to match. The banners the demos print change accordingly; the FVP test runner matches only result lines, so no test depends on them. Default, feature and module configurations pass 6/6, 9/9 and 8/8 on the Armv8-R AEM FVP, as on dev, with zero warnings; the S32Z280 images build cleanly. Not run on S32Z280 hardware. Assisted-by: Claude Code (Opus 5.5) --- cmake/cortex_r52.cmake | 2 +- ports/cortex_r52/gnu/CMakeLists.txt | 2 +- .../fvp_baser_aemv8r/CMakeLists.txt | 80 +++++++++---------- .../example_build/fvp_baser_aemv8r/bsp_boot.c | 10 +-- .../example_build/fvp_baser_aemv8r/console.c | 2 +- .../example_build/fvp_baser_aemv8r/console.h | 2 +- .../{demo_m2.c => demo_coop.c} | 12 +-- .../example_build/fvp_baser_aemv8r/demo_mpu.c | 4 +- .../fvp_baser_aemv8r/demo_threadx.c | 4 +- .../{demo_m3.c => demo_tick.c} | 8 +- .../fvp_baser_aemv8r/demo_verify.c | 6 +- .../{demo_m5.c => demo_vfp.c} | 6 +- .../example_build/fvp_baser_aemv8r/entry.S | 26 +++--- .../fvp_baser_aemv8r/irq_dispatch.c | 2 +- .../gnu/example_build/fvp_baser_aemv8r/mpu.c | 4 +- .../gnu/example_build/fvp_baser_aemv8r/mpu.h | 6 +- .../tx_initialize_low_level.S | 4 +- .../example_build/s32z280_evb/CMakeLists.txt | 2 +- .../gnu/example_build/s32z280_evb/bsp_boot.c | 2 +- .../s32z280_evb/demo_vfp_s32z280.c | 2 +- .../gnu/example_build/s32z280_evb/mpu.c | 4 +- .../gnu/example_build/s32z280_evb/mpu.h | 6 +- .../s32z280_evb/readme_s32z280.txt | 4 +- .../s32z280_evb/tx_initialize_low_level.S | 4 +- ports/cortex_r52/gnu/readme_threadx.txt | 8 +- .../fvp_baser_aemv8r/link_module.lds | 8 +- 26 files changed, 109 insertions(+), 111 deletions(-) rename ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/{demo_m2.c => demo_coop.c} (95%) rename ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/{demo_m3.c => demo_tick.c} (97%) rename ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/{demo_m5.c => demo_vfp.c} (98%) diff --git a/cmake/cortex_r52.cmake b/cmake/cortex_r52.cmake index 183782c9a..a1416faeb 100644 --- a/cmake/cortex_r52.cmake +++ b/cmake/cortex_r52.cmake @@ -15,7 +15,7 @@ set(THREADX_TOOLCHAIN "gnu") # FPU -- GCC rejects "+nofp" for this core and offers only "+nofp.dp" (drop # double precision). There is therefore no FPU-less R52, so the soft-float # baseline selects the soft *ABI* rather than removing the FPU. The hard-float -# variant with lazy VFP context save arrives with AR1 milestone M5. +# variant adds lazy VFP context save (TX_R52_ENABLE_VFP). if(NOT DEFINED TX_R52_FLOAT_ABI) set(TX_R52_FLOAT_ABI "soft" CACHE STRING "R52 float ABI: soft | hard") endif() diff --git a/ports/cortex_r52/gnu/CMakeLists.txt b/ports/cortex_r52/gnu/CMakeLists.txt index 6444a0632..9dc9781b4 100644 --- a/ports/cortex_r52/gnu/CMakeLists.txt +++ b/ports/cortex_r52/gnu/CMakeLists.txt @@ -72,7 +72,7 @@ if(TX_R52_ENABLE_VFP) target_compile_definitions(${PROJECT_NAME} PUBLIC TX_ENABLE_VFP_SUPPORT) endif() -# Armv8-R AEM FVP example builds (boot check now, kernel demo from AR1/M2). +# Armv8-R AEM FVP example builds (boot check and kernel demos). # Off by default so the default build stays a pure static-library build. option(TX_R52_BUILD_FVP_EXAMPLE "Build the Armv8-R AEM FVP example targets" OFF) if(TX_R52_BUILD_FVP_EXAMPLE) diff --git a/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/CMakeLists.txt b/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/CMakeLists.txt index ee01eb3e5..cd3d41755 100644 --- a/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/CMakeLists.txt +++ b/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/CMakeLists.txt @@ -27,7 +27,7 @@ set(R52_CONSOLE_SOURCES ${FVP_DIR}/mpu.c ) -# AR1/M1 -- boot check. Verifies the EL2 configuration, the drop to EL1 and +# Boot check. Verifies the EL2 configuration, the drop to EL1 and # the EL2 HVC seam. Standalone by design: it does not link ThreadX, so a # failure here is unambiguously a boot problem rather than a kernel problem. add_executable(boot_check.elf EXCLUDE_FROM_ALL @@ -45,62 +45,62 @@ target_link_options(boot_check.elf PRIVATE ${R52_LINK_QUIET_RWX} ) -# AR1/M2 -- cooperative two-thread demo. Links ThreadX and exercises the +# Cooperative two-thread demo. Links ThreadX and exercises the # ported context-switch assembly with no interrupts and no timer tick. -add_executable(demo_m2.elf EXCLUDE_FROM_ALL +add_executable(demo_coop.elf EXCLUDE_FROM_ALL ${FVP_DIR}/entry.S ${R52_CONSOLE_SOURCES} ${FVP_DIR}/tx_initialize_low_level.S - ${FVP_DIR}/demo_m2.c + ${FVP_DIR}/demo_coop.c ) -target_link_libraries(demo_m2.elf PRIVATE threadx) +target_link_libraries(demo_coop.elf PRIVATE threadx) -target_include_directories(demo_m2.elf PRIVATE +target_include_directories(demo_coop.elf PRIVATE ${FVP_DIR} ${CMAKE_SOURCE_DIR}/common/inc ${CMAKE_SOURCE_DIR}/ports/${THREADX_ARCH}/${THREADX_TOOLCHAIN}/inc ) -target_link_options(demo_m2.elf PRIVATE +target_link_options(demo_coop.elf PRIVATE -T${FVP_DIR}/link.lds -nostartfiles - -Wl,-Map=demo_m2.map + -Wl,-Map=demo_coop.map ${R52_LINK_QUIET_RWX} ) -# AR1/M3 -- periodic tick and preemptive scheduling. Adds GICv3, the generic +# Periodic tick and preemptive scheduling. Adds GICv3, the generic # timer and the ThreadX IRQ path. TX_R52_USE_THREADX_IRQ routes the EL1 IRQ # vector into _tx_thread_context_save and has _tx_initialize_low_level bring up # the interrupt controller; images without it keep the fault reporter. -add_executable(demo_m3.elf EXCLUDE_FROM_ALL +add_executable(demo_tick.elf EXCLUDE_FROM_ALL ${FVP_DIR}/entry.S ${R52_CONSOLE_SOURCES} ${FVP_DIR}/gicv3.c ${FVP_DIR}/timer.c ${FVP_DIR}/irq_dispatch.c ${FVP_DIR}/tx_initialize_low_level.S - ${FVP_DIR}/demo_m3.c + ${FVP_DIR}/demo_tick.c ) -target_compile_definitions(demo_m3.elf PRIVATE TX_R52_USE_THREADX_IRQ) +target_compile_definitions(demo_tick.elf PRIVATE TX_R52_USE_THREADX_IRQ) -target_link_libraries(demo_m3.elf PRIVATE threadx) +target_link_libraries(demo_tick.elf PRIVATE threadx) -target_include_directories(demo_m3.elf PRIVATE +target_include_directories(demo_tick.elf PRIVATE ${FVP_DIR} ${CMAKE_SOURCE_DIR}/common/inc ${CMAKE_SOURCE_DIR}/ports/${THREADX_ARCH}/${THREADX_TOOLCHAIN}/inc ) -target_link_options(demo_m3.elf PRIVATE +target_link_options(demo_tick.elf PRIVATE -T${FVP_DIR}/link.lds -nostartfiles - -Wl,-Map=demo_m3.map + -Wl,-Map=demo_tick.map ${R52_LINK_QUIET_RWX} ) -# AR1/M4 -- the standard eight-thread ThreadX demo. demo_threadx.c is the +# The standard eight-thread ThreadX demo. demo_threadx.c is the # shipped sample kept byte-identical apart from its header note and one call # into the verification harness, which lives in demo_verify.c. add_executable(demo_threadx.elf EXCLUDE_FROM_ALL @@ -163,39 +163,39 @@ target_link_options(demo_clz.elf PRIVATE ${R52_LINK_QUIET_RWX} ) -# AR1/M5 -- lazy VFP context save and restore. Only meaningful when the +# Lazy VFP context save and restore. Only meaningful when the # library was built with TX_R52_ENABLE_VFP and a floating-point ABI, so the # target exists only in that configuration. if(TX_R52_ENABLE_VFP) - add_executable(demo_m5.elf EXCLUDE_FROM_ALL + add_executable(demo_vfp.elf EXCLUDE_FROM_ALL ${FVP_DIR}/entry.S ${R52_CONSOLE_SOURCES} ${FVP_DIR}/gicv3.c ${FVP_DIR}/timer.c ${FVP_DIR}/irq_dispatch.c ${FVP_DIR}/tx_initialize_low_level.S - ${FVP_DIR}/demo_m5.c + ${FVP_DIR}/demo_vfp.c ) - target_compile_definitions(demo_m5.elf PRIVATE TX_R52_USE_THREADX_IRQ) + target_compile_definitions(demo_vfp.elf PRIVATE TX_R52_USE_THREADX_IRQ) - target_link_libraries(demo_m5.elf PRIVATE threadx) + target_link_libraries(demo_vfp.elf PRIVATE threadx) - target_include_directories(demo_m5.elf PRIVATE + target_include_directories(demo_vfp.elf PRIVATE ${FVP_DIR} ${CMAKE_SOURCE_DIR}/common/inc ${CMAKE_SOURCE_DIR}/ports/${THREADX_ARCH}/${THREADX_TOOLCHAIN}/inc ) - target_link_options(demo_m5.elf PRIVATE + target_link_options(demo_vfp.elf PRIVATE -T${FVP_DIR}/link.lds -nostartfiles - -Wl,-Map=demo_m5.map + -Wl,-Map=demo_vfp.map ${R52_LINK_QUIET_RWX} ) endif() -# AR1/M5 -- PMSAv8-R protection and caches. Verifies enforcement, so it needs +# PMSAv8-R protection and caches. Verifies enforcement, so it needs # the recoverable data-abort path in entry.S (TX_R52_MPU_FAULT_TEST) and the # protection itself (TX_R52_ENABLE_MPU), independently of the global option. add_executable(demo_mpu.elf EXCLUDE_FROM_ALL @@ -233,7 +233,7 @@ target_link_options(demo_mpu.elf PRIVATE # because _tx_thread_irq_nesting_start only re-enables IRQ usefully when # tx_port.h agrees the configuration supports it, and entry.S only emits the # start/end pairing under the same macro. The image therefore exists in that -# configuration only, as demo_m5.elf does for VFP. +# configuration only, as demo_vfp.elf does for VFP. if(TX_R52_ENABLE_IRQ_NESTING) add_executable(demo_nesting.elf EXCLUDE_FROM_ALL ${FVP_DIR}/entry.S @@ -296,7 +296,7 @@ if(TX_R52_ENABLE_FIQ_NESTING) endif() # Every image built here, in the order they should be exercised. -set(R52_IMAGES boot_check.elf demo_m2.elf demo_m3.elf demo_threadx.elf demo_mpu.elf +set(R52_IMAGES boot_check.elf demo_coop.elf demo_tick.elf demo_threadx.elf demo_mpu.elf demo_clz.elf) # The linker script is passed with -T, which CMake does not treat as a @@ -306,7 +306,7 @@ foreach(image IN LISTS R52_IMAGES) set_target_properties(${image} PROPERTIES LINK_DEPENDS ${FVP_DIR}/link.lds) endforeach() if(TX_R52_ENABLE_VFP) - list(APPEND R52_IMAGES demo_m5.elf) + list(APPEND R52_IMAGES demo_vfp.elf) endif() if(TX_R52_ENABLE_IRQ_NESTING) list(APPEND R52_IMAGES demo_nesting.elf) @@ -340,7 +340,7 @@ endif() # ThreadX modules: the module manager, with a sample module linked into the # module area and loaded in place from there. # -# This is the AR2 deliverable that the S32Z280 example cannot be: the silicon +# This is what the S32Z280 example cannot be: the silicon # module demonstration is judged by a person reading a console through a debug # probe, and this one is judged by ctest. The image below is the same port # under the same three passes, reporting one result line the runner matches. @@ -597,7 +597,7 @@ if(TX_R52_BUILD_FVP_MODULE_EXAMPLE) ${CMAKE_SOURCE_DIR}/common_modules/inc ) - # TX_R52_ENABLE_MPU is not optional for these images, unlike the AR1 demos + # TX_R52_ENABLE_MPU is not optional for these images, unlike the kernel demos # where it is a switch: without protection there is no module boundary to # test, and the manager's load window over the module area is programmed by # mpu_init. TX_R52_USE_THREADX_IRQ brings up the tick, which the module @@ -627,7 +627,7 @@ if(TX_R52_BUILD_FVP_MODULE_EXAMPLE) endfunction() - # AR2. What the hardware does about a module that misbehaves. + # What the hardware does about a module that misbehaves. threadx_r52_add_module_image(fvp_module.elf ${MOD_FVP}/sample_threadx_module_manager.c) @@ -666,20 +666,20 @@ if(FVP_BASER_AEMV8R) endfunction() threadx_r52_add_fvp_run(boot_check.elf run-boot-check-r52 - "Running AR1/M1 boot check on FVP_BaseR_AEMv8R...") - threadx_r52_add_fvp_run(demo_m2.elf run-demo-m2-r52 - "Running AR1/M2 cooperative switch demo on FVP_BaseR_AEMv8R...") - threadx_r52_add_fvp_run(demo_m3.elf run-demo-m3-r52 - "Running AR1/M3 tick and preemption demo on FVP_BaseR_AEMv8R...") + "Running the boot check on FVP_BaseR_AEMv8R...") + threadx_r52_add_fvp_run(demo_coop.elf run-demo-coop-r52 + "Running the cooperative switch demo on FVP_BaseR_AEMv8R...") + threadx_r52_add_fvp_run(demo_tick.elf run-demo-tick-r52 + "Running the tick and preemption demo on FVP_BaseR_AEMv8R...") threadx_r52_add_fvp_run(demo_threadx.elf run-demo-threadx-r52 "Running the standard ThreadX demo on FVP_BaseR_AEMv8R...") threadx_r52_add_fvp_run(demo_clz.elf run-demo-clz-r52 "Running the CLZ lowest-set-bit regression on FVP_BaseR_AEMv8R...") if(TX_R52_BUILD_FVP_MODULE_EXAMPLE) threadx_r52_add_fvp_run(fvp_module.elf run-module-r52 - "Running the AR2 module isolation example on FVP_BaseR_AEMv8R...") + "Running the module isolation example on FVP_BaseR_AEMv8R...") threadx_r52_add_fvp_run(fvp_module_properties.elf run-module-properties-r52 - "Running the AR2 module property contract regression on FVP_BaseR_AEMv8R...") + "Running the module property contract regression on FVP_BaseR_AEMv8R...") endif() # Automated checks. The runner judges each image by its self-reported @@ -691,7 +691,7 @@ if(FVP_BASER_AEMV8R) set(R52_RUNNER ${FVP_DIR}/test/run_fvp_test.py) set(R52_TEST_IMAGES ${R52_IMAGES}) - # AR2. Kept out of R52_IMAGES above rather than added to it, because + # Module images. Kept out of R52_IMAGES above rather than added to it, because # that list is what the TX_R52_ENABLE_MPU and TX_R52_CONSOLE_PL011 # options are applied to and neither is optional for this image: the # module boundary IS the MPU, and the result line has to reach the diff --git a/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/bsp_boot.c b/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/bsp_boot.c index 4c60de8c4..1d0fb8ca8 100644 --- a/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/bsp_boot.c +++ b/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/bsp_boot.c @@ -25,13 +25,13 @@ /* */ /* DESCRIPTION */ /* */ -/* AR1 milestone M1 boot check. Verifies that the reset path really */ +/* Boot check. Verifies that the reset path really */ /* configured EL2 and then dropped to EL1, and that the EL2 HVC seam */ -/* used by ZoneX (AR3) is reachable from EL1 and returns correctly. */ +/* used by ZoneX is reachable from EL1 and returns correctly. */ /* */ /* This deliberately asserts the resulting exception level rather than */ /* merely printing a message: "it printed something" does not prove a */ -/* correct EL2-to-EL1 transition, and AR3 depends on that transition. */ +/* correct EL2-to-EL1 transition, which ZoneX depends on. */ /* */ /* MISRA C:2012 deviations (justified) */ /* */ @@ -101,7 +101,7 @@ void bsp_main(void) unsigned long hvc_after; unsigned int failures = 0U; - console_puts("\n=== ThreadX AR1/M1 boot check " + console_puts("\n=== ThreadX boot check " "(Cortex-R52, Armv8-R AArch32, Armv8-R AEM FVP) ===\n"); /* Check 1: we are executing at EL1, not still at EL2. */ @@ -133,7 +133,7 @@ void bsp_main(void) } /* Check 2: the EL2 HVC seam is reachable from EL1 and returns. This is - what AR3 (ZoneX Phase-0) builds on, so it is verified from AR1. */ + what ZoneX builds on, so the boot check verifies it. */ hvc_before = _hvc_call_count; issue_hvc(); diff --git a/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/console.c b/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/console.c index ab78f4929..ec5d6f073 100644 --- a/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/console.c +++ b/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/console.c @@ -98,7 +98,7 @@ void console_puts(const char *string_ptr) #ifdef TX_R52_CONSOLE_PL011 /* Initialise on first use rather than from board_init, so that images - with no ThreadX initialisation path (the M1 boot check) also get a + with no ThreadX initialisation path (the boot check) also get a working UART console. */ static unsigned int initialised = 0U; diff --git a/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/console.h b/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/console.h index a9bc5ba0a..16a090bcd 100644 --- a/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/console.h +++ b/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/console.h @@ -27,7 +27,7 @@ /* */ /* Minimal console for the Armv8-R AEM FVP. Backed by semihosting so */ /* that early bring-up needs no peripheral base addresses; the PL011 */ -/* UART implementation arrives in AR1/M3 behind this same interface. */ +/* UART console (TX_R52_CONSOLE_PL011) uses the same interface. */ /* */ /**************************************************************************/ diff --git a/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/demo_m2.c b/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/demo_coop.c similarity index 95% rename from ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/demo_m2.c rename to ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/demo_coop.c index a5f6243ce..0af5dab34 100644 --- a/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/demo_m2.c +++ b/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/demo_coop.c @@ -17,7 +17,7 @@ /* */ /* DEMONSTRATION RELEASE */ /* */ -/* demo_m2.c Cortex-R52/GNU */ +/* demo_coop.c Cortex-R52/GNU */ /* 6.5.2 */ /* AUTHOR */ /* */ @@ -25,7 +25,7 @@ /* */ /* DESCRIPTION */ /* */ -/* AR1 milestone M2: two threads switching cooperatively, with no */ +/* Two threads switching cooperatively, with no */ /* interrupts and no timer tick. This is the first real exercise of */ /* the ported assembly -- _tx_thread_stack_build builds each thread's */ /* initial frame, _tx_thread_schedule restores it, and */ @@ -39,7 +39,7 @@ /* itself. */ /* */ /* Only tx_thread_relinquish is used. tx_thread_sleep would hang */ -/* without a tick, which AR1/M3 adds. */ +/* without a tick, which demo_tick.c adds. */ /* */ /**************************************************************************/ @@ -194,8 +194,8 @@ static void thread_0_entry(ULONG thread_input) /**************************************************************************/ /* tx_application_define -- create the demo threads. */ /* */ -/* Static stacks are used rather than a byte pool so that M2 exercises */ -/* only the context-switch path, with no allocator in the way. */ +/* Static stacks are used rather than a byte pool so that the demo */ +/* exercises only the context-switch path, with no allocator in the way. */ /**************************************************************************/ void tx_application_define(void *first_unused_memory) @@ -218,7 +218,7 @@ void tx_application_define(void *first_unused_memory) void bsp_main(void) { - console_puts("\n=== ThreadX AR1/M2 cooperative switch " + console_puts("\n=== ThreadX cooperative switch " "(Cortex-R52, Armv8-R AArch32, Armv8-R AEM FVP) ===\n"); tx_kernel_enter(); diff --git a/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/demo_mpu.c b/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/demo_mpu.c index 7b1365e36..c4a432c57 100644 --- a/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/demo_mpu.c +++ b/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/demo_mpu.c @@ -25,7 +25,7 @@ /* */ /* DESCRIPTION */ /* */ -/* AR1 milestone M5: PMSAv8-R protection and caches. */ +/* PMSAv8-R protection and caches. */ /* */ /* The important check here is enforcement, not configuration. */ /* Reading SCTLR back only proves a bit was set; it says nothing about */ @@ -278,7 +278,7 @@ void tx_application_define(void *first_unused_memory) void bsp_main(void) { - console_puts("\n=== ThreadX AR1/M5 PMSAv8-R protection and caches " + console_puts("\n=== ThreadX PMSAv8-R protection and caches " "(Cortex-R52, Armv8-R AEM FVP) ===\n"); tx_kernel_enter(); diff --git a/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/demo_threadx.c b/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/demo_threadx.c index 90fe257db..d26a81736 100644 --- a/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/demo_threadx.c +++ b/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/demo_threadx.c @@ -13,7 +13,7 @@ /* Copied unmodified from samples/demo_threadx.c for the Armv8-R AEM FVP example build, then extended with a verification thread and a bsp_main entry point. Keeping the demo body byte-identical to the shipped sample - is the point of AR1 milestone M4: it shows the standard ThreadX demo runs + is the point of this image: it shows the standard ThreadX demo runs on Cortex-R52 with no demo-side changes. The additions are confined to the end of this file and one call in tx_application_define. */ @@ -190,7 +190,7 @@ CHAR *pointer = TX_NULL; /* Release the block back to the pool. */ tx_block_release(pointer); - /* AR1/M4 addition: create the verification thread. */ + /* Addition: create the verification thread. */ demo_verify_create(); } diff --git a/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/demo_m3.c b/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/demo_tick.c similarity index 97% rename from ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/demo_m3.c rename to ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/demo_tick.c index f07e06321..d474ae3d0 100644 --- a/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/demo_m3.c +++ b/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/demo_tick.c @@ -17,7 +17,7 @@ /* */ /* DEMONSTRATION RELEASE */ /* */ -/* demo_m3.c Cortex-R52/GNU */ +/* demo_tick.c Cortex-R52/GNU */ /* 6.5.2 */ /* AUTHOR */ /* */ @@ -25,8 +25,8 @@ /* */ /* DESCRIPTION */ /* */ -/* AR1 milestone M3: periodic tick and preemptive scheduling. This */ -/* exercises the parts of the port that M2 could not reach -- */ +/* Periodic tick and preemptive scheduling. This */ +/* exercises the parts of the port that demo_coop.c cannot reach -- */ /* _tx_thread_context_save, _tx_timer_interrupt and */ /* _tx_thread_context_restore -- by driving them from a real generic */ /* timer interrupt routed through GICv3. */ @@ -243,7 +243,7 @@ void tx_application_define(void *first_unused_memory) void bsp_main(void) { - console_puts("\n=== ThreadX AR1/M3 tick and preemption " + console_puts("\n=== ThreadX tick and preemption " "(Cortex-R52, Armv8-R AArch32, Armv8-R AEM FVP) ===\n"); tx_kernel_enter(); diff --git a/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/demo_verify.c b/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/demo_verify.c index f51691a86..6f7c6b273 100644 --- a/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/demo_verify.c +++ b/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/demo_verify.c @@ -25,11 +25,11 @@ /* */ /* DESCRIPTION */ /* */ -/* AR1 milestone M4: verifies that the standard eight-thread ThreadX */ +/* Verifies that the standard eight-thread ThreadX */ /* demo makes progress on Cortex-R52, then terminates the simulation */ /* so the run can be automated. */ /* */ -/* Where M3 proved the tick and a single preemption, this exercises */ +/* Where demo_tick.c tests the tick and one preemption, this exercises */ /* the demo's full object set -- queue, semaphore, mutex, event flags, */ /* byte pool and block pool -- across eight threads at five */ /* priorities. Each of the ten demo counters is required to have */ @@ -179,7 +179,7 @@ void demo_verify_create(void) void bsp_main(void) { - console_puts("\n=== ThreadX AR1/M4 standard eight-thread demo " + console_puts("\n=== ThreadX standard eight-thread demo " "(Cortex-R52, Armv8-R AArch32, Armv8-R AEM FVP) ===\n"); tx_kernel_enter(); diff --git a/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/demo_m5.c b/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/demo_vfp.c similarity index 98% rename from ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/demo_m5.c rename to ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/demo_vfp.c index c3c78e492..e6b1e9597 100644 --- a/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/demo_m5.c +++ b/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/demo_vfp.c @@ -17,7 +17,7 @@ /* */ /* DEMONSTRATION RELEASE */ /* */ -/* demo_m5.c Cortex-R52/GNU */ +/* demo_vfp.c Cortex-R52/GNU */ /* 6.5.2 */ /* AUTHOR */ /* */ @@ -25,7 +25,7 @@ /* */ /* DESCRIPTION */ /* */ -/* AR1 milestone M5: lazy floating-point context save and restore. */ +/* Lazy floating-point context save and restore. */ /* */ /* Two paths must be covered, and they use different register sets: */ /* */ @@ -278,7 +278,7 @@ void tx_application_define(void *first_unused_memory) void bsp_main(void) { - console_puts("\n=== ThreadX AR1/M5 lazy VFP context switch " + console_puts("\n=== ThreadX lazy VFP context switch " "(Cortex-R52, Armv8-R AArch32, Armv8-R AEM FVP) ===\n"); tx_kernel_enter(); diff --git a/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/entry.S b/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/entry.S index e1dff629a..aa296c3a5 100644 --- a/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/entry.S +++ b/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/entry.S @@ -30,7 +30,7 @@ /* file configures EL2 first, installs both the EL2 and EL1 vector */ /* tables, and only then drops to EL1 (Supervisor mode) to run the */ /* kernel. The HVC entry in the EL2 table is the seam that ZoneX */ -/* (roadmap AR3) grows into -- it is deliberately present from AR1 so */ +/* grows into. It is deliberately present in every image so */ /* that partitioning does not require re-architecting the boot path. */ /* */ /* Define TX_R52_BOOT_AT_EL1 to skip EL2 configuration, for targets */ @@ -137,7 +137,7 @@ el2_vectors: /* Offsets 0x04-0x10 are exceptions taken *from* Hyp mode itself. Offset 0x14 is the Hyp Trap Entry: every exception routed to EL2 from EL1/EL0 -- HVC, stage-2 faults, trapped register accesses -- funnels through it and - is decoded from HSR. That single funnel is the ZoneX (AR3) seam. */ + is decoded from HSR. That single funnel is the ZoneX seam. */ b el2_trap_reset /* 0x00 reset (unused at EL2) */ b el2_trap_undef /* 0x04 undef, from Hyp */ @@ -192,9 +192,9 @@ _start: isb /* Configure EL2: keep exceptions and interrupts routed to EL1, and - leave the stage-2 MPU disabled for AR1 (the FVP background memory + leave the stage-2 MPU disabled (the FVP background memory map already permits execution and data access in low DRAM). ZoneX - enables HCR_VM and programs stage 2 in AR3. + enables HCR_VM and programs stage 2. HCR_HCD is cleared explicitly so HVC is enabled from EL1 rather than relying on its reset value -- the ZoneX seam depends on it. */ @@ -375,7 +375,7 @@ _start_hang: /* plain B: context save adjusts lr itself to find the point of */ /* interrupt. Interrupts are still disabled on return from it. */ /* */ -/* Images that do not link ThreadX (the M1 boot check) keep the */ +/* Images that do not link ThreadX (the boot check) keep the */ /* self-identifying fault reporter instead. */ /**************************************************************************/ @@ -434,12 +434,12 @@ __tx_irq_processing_return: #endif /**************************************************************************/ -/* el2_hyp_trap_entry -- the ZoneX (AR3) seam. */ +/* el2_hyp_trap_entry -- the ZoneX seam. */ /* */ /* Reached for every exception routed to EL2 from EL1/EL0, so the cause */ -/* is decoded from HSR.EC before dispatch. AR1 handles only HVC, which */ +/* is decoded from HSR.EC before dispatch. It handles only HVC, which */ /* it counts before returning to EL1; that proves EL2 is live and */ -/* reachable without the boot path changing later. AR3 grows the */ +/* reachable without the boot path changing later. ZoneX grows the */ /* dispatch table here (stage-2 faults, trapped accesses, IRQ paravirt). */ /* */ /* EL1's registers must be preserved -- this runs on the Hyp stack. */ @@ -454,7 +454,7 @@ el2_hyp_trap_entry: cmp r1, #HSR_EC_HVC bne el2_hyp_trap_unhandled - /* HVC from EL1: AR1 placeholder for the ZoneX hypercall dispatch. */ + /* HVC from EL1: placeholder for the ZoneX hypercall dispatch. */ ldr r0, =_hvc_call_count ldr r1, [r0] @@ -469,12 +469,10 @@ el2_hyp_trap_unhandled: /**************************************************************************/ /* Unhandled exceptions. Each records a distinct code in r12 so a */ -/* halted model or a later fault dump (AR1/M5) can identify the cause. */ -/* Real handlers arrive with the interrupt work in M3. */ +/* halted model or a fault dump can identify the cause. */ /**************************************************************************/ -/* Unhandled exceptions. Real handlers arrive with the interrupt work in - AR1/M3; until then each vector identifies itself and halts. */ +/* Unhandled exceptions. Each vector identifies itself and halts. */ el2_trap_reset: FAULT_REPORT msg_el2_reset el2_trap_undef: FAULT_REPORT msg_el2_undef @@ -609,7 +607,7 @@ el1_trap_fiq: /* Both guards are needed, and the second is not obvious. * TX_ENABLE_FIQ_SUPPORT is PUBLIC on the threadx target, so it reaches every * image the moment the library is built with FIQ, including images that link - * no interrupt controller at all. demo_m2 is one: it has no gicv3.c and no + * no interrupt controller at all. demo_coop is one: it has no gicv3.c and no * irq_dispatch.c, so referencing gicv3_acknowledge_group0 and * board_fiq_service from here broke its link outright. Images without the * interrupt infrastructure keep the fault reporter on this vector, which is diff --git a/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/irq_dispatch.c b/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/irq_dispatch.c index a53cd65bf..a3230b900 100644 --- a/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/irq_dispatch.c +++ b/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/irq_dispatch.c @@ -43,7 +43,7 @@ extern void _tx_timer_interrupt(void); -/* Observability for the M3 checks. board_timer_intid records the INTID that +/* Observability for the tick checks. board_timer_intid records the INTID that actually arrived -- this is how the timer PPI was identified during bring-up (see TIMER_PPI_INTID) and it keeps reporting it, so a platform that assigns the timer elsewhere shows up as an unexpected INTID rather than a silent diff --git a/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/mpu.c b/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/mpu.c index 0f7f8a444..65fa80b13 100644 --- a/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/mpu.c +++ b/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/mpu.c @@ -76,8 +76,8 @@ extern char __data_end__; /* Deliberately minimal and readable: code is read-only and executable, */ /* everything writable is non-executable, and the peripheral half of the */ /* address map is Device. A write-protected code region is the point -- */ -/* it is what makes the MPU do something observable, and AR2 extends the */ -/* same table with per-module regions. */ +/* it is what makes the MPU do something observable, and the module */ +/* port extends the same table with per-module regions. */ /**************************************************************************/ static MPU_REGION mpu_regions[3]; diff --git a/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/mpu.h b/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/mpu.h index d52a03a6e..5992d909e 100644 --- a/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/mpu.h +++ b/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/mpu.h @@ -28,9 +28,9 @@ /* PMSAv8-R memory protection and cache enable for Cortex-R52. */ /* */ /* The region set is described by a table rather than a sequence of */ -/* register writes. That is deliberate and is a roadmap decision, not */ -/* a style preference: AR2 programs a Stage-1 region set per ThreadX */ -/* module and AR3 programs Stage-2 regions per ZoneX partition, and */ +/* register writes. That is deliberate, not a style preference: */ +/* the module port programs a Stage-1 region set per ThreadX */ +/* module and ZoneX programs Stage-2 regions per partition, and */ /* both reuse this shape. A table can be swapped at a partition */ /* switch; open-coded register writes cannot. */ /* */ diff --git a/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/tx_initialize_low_level.S b/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/tx_initialize_low_level.S index 48a2dd8c3..1cddfb425 100644 --- a/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/tx_initialize_low_level.S +++ b/ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/tx_initialize_low_level.S @@ -64,8 +64,8 @@ /* GICv3 and the generic timer tick here. That is safe this early */ /* because interrupts stay masked until _tx_thread_schedule enables */ /* them, so no tick can be delivered before the kernel is ready to */ -/* take one. Without that symbol (the M2 cooperative demo) no tick is */ -/* created, which keeps M2 free of any interrupt dependency. */ +/* take one. Without that symbol (the cooperative demo) no tick is */ +/* created, which keeps that demo free of any interrupt dependency. */ /* */ /* CALLED BY */ /* */ diff --git a/ports/cortex_r52/gnu/example_build/s32z280_evb/CMakeLists.txt b/ports/cortex_r52/gnu/example_build/s32z280_evb/CMakeLists.txt index 85dd29d65..01ab68fda 100644 --- a/ports/cortex_r52/gnu/example_build/s32z280_evb/CMakeLists.txt +++ b/ports/cortex_r52/gnu/example_build/s32z280_evb/CMakeLists.txt @@ -132,7 +132,7 @@ target_link_options(s32z280_demo.elf PRIVATE ) # Lazy VFP context save and restore. Only meaningful when the library was built -# with TX_R52_ENABLE_VFP and a floating-point ABI, so like the FVP's demo_m5.elf +# with TX_R52_ENABLE_VFP and a floating-point ABI, so like the FVP's demo_vfp.elf # the target exists only in that configuration. The FPU hardware enable lives in # entry.S under __ARM_FP; tx_thread_vfp_enable() sets only the per-thread flag. if(TX_R52_ENABLE_VFP) diff --git a/ports/cortex_r52/gnu/example_build/s32z280_evb/bsp_boot.c b/ports/cortex_r52/gnu/example_build/s32z280_evb/bsp_boot.c index 8dc04fb56..4cccee80d 100644 --- a/ports/cortex_r52/gnu/example_build/s32z280_evb/bsp_boot.c +++ b/ports/cortex_r52/gnu/example_build/s32z280_evb/bsp_boot.c @@ -32,7 +32,7 @@ /* through the daughtercard USB-UART, but its baud rate depends on */ /* clock configuration that is not yet established, and a console that */ /* prints at the wrong rate produces garbage indistinguishable from a */ -/* crash. So this milestone reports through memory instead, which */ +/* crash. So this check reports through memory instead, which */ /* cannot be mis-configured. The console arrives in the next step. */ /* */ /* Only EL1-accessible registers are read here. EL2-only ones */ diff --git a/ports/cortex_r52/gnu/example_build/s32z280_evb/demo_vfp_s32z280.c b/ports/cortex_r52/gnu/example_build/s32z280_evb/demo_vfp_s32z280.c index 192f51fa7..9b627ce1e 100644 --- a/ports/cortex_r52/gnu/example_build/s32z280_evb/demo_vfp_s32z280.c +++ b/ports/cortex_r52/gnu/example_build/s32z280_evb/demo_vfp_s32z280.c @@ -27,7 +27,7 @@ /* */ /* Lazy floating-point context save and restore on S32Z280 silicon. */ /* */ -/* This is the FVP's demo_m5.c test design, reporting over the */ +/* This is the FVP's demo_vfp.c test design, reporting over the */ /* LINFlexD console instead of semihosting. The design is kept */ /* deliberately: the model established that the two halves of the VFP */ /* context path need separate provocation, and silicon does not change */ diff --git a/ports/cortex_r52/gnu/example_build/s32z280_evb/mpu.c b/ports/cortex_r52/gnu/example_build/s32z280_evb/mpu.c index 01a3cc72b..b2d28021b 100644 --- a/ports/cortex_r52/gnu/example_build/s32z280_evb/mpu.c +++ b/ports/cortex_r52/gnu/example_build/s32z280_evb/mpu.c @@ -90,8 +90,8 @@ extern char __data_end__; /* Deliberately minimal and readable: code is read-only and executable, */ /* everything writable is non-executable, and the peripheral half of the */ /* address map is Device. A write-protected code region is the point -- */ -/* it is what makes the MPU do something observable, and AR2 extends the */ -/* same table with per-module regions. */ +/* it is what makes the MPU do something observable, and the module */ +/* port extends the same table with per-module regions. */ /**************************************************************************/ /* Table capacity. The FVP example this file came from declared this as [3], diff --git a/ports/cortex_r52/gnu/example_build/s32z280_evb/mpu.h b/ports/cortex_r52/gnu/example_build/s32z280_evb/mpu.h index 19d183cce..3a1e8b0a6 100644 --- a/ports/cortex_r52/gnu/example_build/s32z280_evb/mpu.h +++ b/ports/cortex_r52/gnu/example_build/s32z280_evb/mpu.h @@ -28,9 +28,9 @@ /* PMSAv8-R memory protection and cache enable for Cortex-R52. */ /* */ /* The region set is described by a table rather than a sequence of */ -/* register writes. That is deliberate and is a roadmap decision, not */ -/* a style preference: AR2 programs a Stage-1 region set per ThreadX */ -/* module and AR3 programs Stage-2 regions per ZoneX partition, and */ +/* register writes. That is deliberate, not a style preference: */ +/* the module port programs a Stage-1 region set per ThreadX */ +/* module and ZoneX programs Stage-2 regions per partition, and */ /* both reuse this shape. A table can be swapped at a partition */ /* switch; open-coded register writes cannot. */ /* */ diff --git a/ports/cortex_r52/gnu/example_build/s32z280_evb/readme_s32z280.txt b/ports/cortex_r52/gnu/example_build/s32z280_evb/readme_s32z280.txt index 30aef5dcc..56c4a7fa4 100644 --- a/ports/cortex_r52/gnu/example_build/s32z280_evb/readme_s32z280.txt +++ b/ports/cortex_r52/gnu/example_build/s32z280_evb/readme_s32z280.txt @@ -159,7 +159,7 @@ model and not an R52 at all. CPSR at EL2 0x000001DA mode 0x1A, Hyp CPSR at EL1 0x600001D3 mode 0x13, Supervisor - The two CPSR values are the point of the milestone: they are the EL2 to EL1 + The two CPSR values are the point of the check: they are the EL2 to EL1 drop performed by this code on silicon rather than on a model. @@ -170,7 +170,7 @@ model and not an R52 at all. 0x40170000, the tempting wrong choice as the first instance in the Reference Manual's list. What is missing is the clock configuration needed to compute a baud rate; a console at the wrong rate produces garbage - indistinguishable from a crash, which is why this milestone reports through + indistinguishable from a crash, which is why this check reports through memory instead. No timer, no GIC, no MPU programming and no ThreadX: this image does not diff --git a/ports/cortex_r52/gnu/example_build/s32z280_evb/tx_initialize_low_level.S b/ports/cortex_r52/gnu/example_build/s32z280_evb/tx_initialize_low_level.S index a93a951c5..06b42348e 100644 --- a/ports/cortex_r52/gnu/example_build/s32z280_evb/tx_initialize_low_level.S +++ b/ports/cortex_r52/gnu/example_build/s32z280_evb/tx_initialize_low_level.S @@ -67,8 +67,8 @@ /* and the generic timer tick here. That is safe this early because */ /* interrupts stay masked until _tx_thread_schedule enables them, so */ /* no tick can be delivered before the kernel is ready to take one. */ -/* Without that symbol (the M2 cooperative demo) no tick is created, */ -/* which keeps M2 free of any interrupt dependency. */ +/* Without that symbol (the cooperative demo) no tick is created, */ +/* which keeps that demo free of any interrupt dependency. */ /* */ /* CALLED BY */ /* */ diff --git a/ports/cortex_r52/gnu/readme_threadx.txt b/ports/cortex_r52/gnu/readme_threadx.txt index 73e0dbfe9..87239ea2d 100644 --- a/ports/cortex_r52/gnu/readme_threadx.txt +++ b/ports/cortex_r52/gnu/readme_threadx.txt @@ -50,19 +50,19 @@ baseline selects the soft ABI rather than removing the FPU. cmake -B build_r52 -G Ninja \ -DCMAKE_TOOLCHAIN_FILE=cmake/cortex_r52.cmake \ -DTX_R52_BUILD_FVP_EXAMPLE=ON . - ninja -C build_r52 boot_check.elf demo_m2.elf demo_m3.elf \ + ninja -C build_r52 boot_check.elf demo_coop.elf demo_tick.elf \ demo_threadx.elf demo_mpu.elf demo_clz.elf ctest --test-dir build_r52 The images target the free Armv8-R AEM FVP (FVP_BaseR_AEMv8R): boot_check.elf EL2 configuration, the drop to EL1 and the EL2 seam - demo_m2.elf cooperative context switching, no interrupts - demo_m3.elf generic timer tick, GICv3 and preemption + demo_coop.elf cooperative context switching, no interrupts + demo_tick.elf generic timer tick, GICv3 and preemption demo_threadx.elf the standard eight-thread demo plus verification demo_mpu.elf PMSAv8-R protection and cache enable demo_clz.elf the CLZ lowest-set-bit priority search - demo_m5.elf lazy VFP context save (needs TX_R52_ENABLE_VFP) + demo_vfp.elf lazy VFP context save (needs TX_R52_ENABLE_VFP) Each image reports its own result and terminates the model through the semihosting SYS_EXIT call, so no host-side timeout is needed. The test diff --git a/ports_module/cortex_r52/gnu/example_build/fvp_baser_aemv8r/link_module.lds b/ports_module/cortex_r52/gnu/example_build/fvp_baser_aemv8r/link_module.lds index 14ced186c..b25ee6841 100644 --- a/ports_module/cortex_r52/gnu/example_build/fvp_baser_aemv8r/link_module.lds +++ b/ports_module/cortex_r52/gnu/example_build/fvp_baser_aemv8r/link_module.lds @@ -21,8 +21,8 @@ * to be linked into low DRAM -- linking at 0x80000000 produces a silent fault * loop with no output. * - * This is the AR1 link.lds with three differences, and each of them is a - * requirement of the module port rather than a preference. + * This is the kernel example's link.lds with three differences, each of + * them a requirement of the module port rather than a preference. * * 1. DRAM stops below a MODULE region. A module's code and data are handed * to it as MPU regions, and PMSAv8-R has no region priority: an access @@ -30,8 +30,8 @@ * (TRM 8.1). So module memory has to be memory no kernel region covers, * and the only way to guarantee that is to end the kernel's data region * where the module area begins. __data_end__ below is ORIGIN(MODULE) for - * exactly that reason, not the "1 MB of heap past the image" the AR1 - * script uses. + * exactly that reason, not the "1 MB of heap past the image" the + * kernel example's script uses. * * 2. .txm_user_entry sits between the code region and the data region, in a * gap belonging to neither. It holds the module's gateway into the