api.md

API Reference

High-level interactive API

from dau_sim import Simulator

sim = Simulator.from_sv_file("design.sv", top="top_module")
result = sim.run(cycles=1000, inputs={"en": 1})

print(result.latest("count"))
rows = result.to_rows(signals=["count"])
sim.write_vcd("out.vcd", result)

Frontends

Function	Description
from_amaranth(elaboratable)	Lower an Amaranth Elaboratable or Component to IR
parse_sv(source, top=None)	Parse SystemVerilog source string to IR
parse_sv_file(path, top=None)	Parse SystemVerilog file to IR

Compiler

Function / Method	Description
compile_module(module, four_state=False)	Compile an IR Module to a CompiledModule
cm.run(cycles, clock_period, inputs, clocks)	Simulate and return traces
cm.write_vcd(path, traces, timescale="1ns")	Write traces to VCD file
cm.traces_to_vcd(traces, timescale="1ns")	Convert traces to VCD string

Backends

Function / Class	Description
run_cocotb(design, test_module, ...)	Run cocotb testbench against Amaranth design or IR Module
SimulationEngine(module)	Low-level engine with NBA-correct event scheduling

Composed configuration

Simulation profiles are options in the Hydra profile group and instantiate ccflow models in ModelRegistry. The packaged profile is selected with profile=profiles/ready-valid-sum. Other packages and user config directories can add profile/profiles/*.yaml entries of their own; no registration code is needed.

RunSvTask (task=tasks/sim/run-sv) runs a design and returns a RunSvResult with every signal's final value. PerfSvTask (task=tasks/analysis/perf-sv) returns a PerfSvResult whose benchmark, node-separation and comparison metrics are ResultBase models. Both are ccflow CallableModels; the dau-sim command is a front end over them.

IR types

Type	Description
Module	Top-level container with ports, signals, clock domains, blocks
Signal	Named bit-vector with shape and initial value
Port	Signal with direction (INPUT/OUTPUT/INOUT)
Shape(width, signed)	Bit-width and signedness
ClockDomain	Clock signal, edge polarity, optional reset
CombBlock / SeqBlock	Combinational / sequential logic blocks
Assign, IfElse, Switch	Statement types
Const, SignalRef, Binary, Unary, Mux, Concat, Slice	Expression types