From 447c33a6f1248b62c63ed2272245ad7e3b4905c2 Mon Sep 17 00:00:00 2001 From: Hyunbin Kim Date: Wed, 7 Oct 2026 03:02:00 +0000 Subject: [PATCH] Cranelift: add mid-end opt rules --- cranelift/codegen/src/opts/extends.isle | 10 + cranelift/codegen/src/opts/icmp.isle | 4 + cranelift/codegen/src/opts/selects.isle | 40 ++ .../filetests/filetests/egraph/extends.clif | 116 +++++ .../filetests/filetests/egraph/icmp.clif | 73 ++++ .../filetests/filetests/egraph/selects.clif | 376 +++++++++++++++++ .../filetests/filetests/runtests/extend.clif | 158 +++++++ .../filetests/filetests/runtests/icmp.clif | 67 +++ .../filetests/filetests/runtests/select.clif | 398 ++++++++++++++++++ 9 files changed, 1242 insertions(+) diff --git a/cranelift/codegen/src/opts/extends.isle b/cranelift/codegen/src/opts/extends.isle index 21598dd23b44..c1004b36cdaf 100644 --- a/cranelift/codegen/src/opts/extends.isle +++ b/cranelift/codegen/src/opts/extends.isle @@ -102,3 +102,13 @@ (uextend ty x @ (value_type (ty_int narrow))) (uextend ty y @ (value_type narrow)))) (ult rty x y)) + +;; sextend(x) OP sextend(y) --> x OP y, where OP = {==, x == y. +(rule (simplify (eq ty (rotr cty x k) (rotr cty y k))) + (subsume (eq ty x y))) + ;; (x >=s 0) & (x x x - y (rule (simplify (select ty (ne cty x y) (isub ty x y) (all_zero ty))) (isub ty x y)) + +;; (c ? x : y) OP (c ? y : x) --> x OP y, where OP = {&, |, ^}. +(rule (simplify (band ty (select ty c x y) (select ty c y x))) + (subsume (band ty x y))) +(rule (simplify (bor ty (select ty c x y) (select ty c y x))) + (subsume (bor ty x y))) +(rule (simplify (bxor ty (select ty c x y) (select ty c y x))) + (subsume (bxor ty x y))) + +;; (x == y) ? 0 : (x ^ y) --> x ^ y, and its variants +(rule (simplify (select ty (eq cty x y) (all_zero ty) (bxor ty x y))) + (bxor ty x y)) +(rule (simplify (select ty (eq cty x y) (all_zero ty) (bxor ty y x))) + (bxor ty x y)) +(rule (simplify (select ty (ne cty x y) (bxor ty x y) (all_zero ty))) + (bxor ty x y)) +(rule (simplify (select ty (ne cty x y) (bxor ty y x) (all_zero ty))) + (bxor ty x y)) + +;; (k == 0) ? x : (x shift k) --> x shift k +(rule (simplify (select ty (eq cty k (all_zero _)) x (ishl ty x k))) + (ishl ty x k)) +(rule (simplify (select ty (ne cty k (all_zero _)) (ishl ty x k) x)) + (ishl ty x k)) +(rule (simplify (select ty (eq cty k (all_zero _)) x (ushr ty x k))) + (ushr ty x k)) +(rule (simplify (select ty (ne cty k (all_zero _)) (ushr ty x k) x)) + (ushr ty x k)) +(rule (simplify (select ty (eq cty k (all_zero _)) x (sshr ty x k))) + (sshr ty x k)) +(rule (simplify (select ty (ne cty k (all_zero _)) (sshr ty x k) x)) + (sshr ty x k)) +(rule (simplify (select ty (eq cty k (all_zero _)) x (rotl ty x k))) + (rotl ty x k)) +(rule (simplify (select ty (ne cty k (all_zero _)) (rotl ty x k) x)) + (rotl ty x k)) +(rule (simplify (select ty (eq cty k (all_zero _)) x (rotr ty x k))) + (rotr ty x k)) +(rule (simplify (select ty (ne cty k (all_zero _)) (rotr ty x k) x)) + (rotr ty x k)) diff --git a/cranelift/filetests/filetests/egraph/extends.clif b/cranelift/filetests/filetests/egraph/extends.clif index dfb5e96905da..c484203cd681 100644 --- a/cranelift/filetests/filetests/egraph/extends.clif +++ b/cranelift/filetests/filetests/egraph/extends.clif @@ -305,3 +305,119 @@ block0(v0: i8, v1: i16): ; check: uextend.i32 v0 ; check: uextend.i32 v1 ; check: icmp ult v2, v3 + +function %eq_sextend_i8_i32(i8, i8) -> i8 { +block0(v0: i8, v1: i8): + v2 = sextend.i32 v0 + v3 = sextend.i32 v1 + v4 = icmp eq v2, v3 + return v4 +} +; check: v5 = icmp eq v0, v1 +; check: return v5 + +function %slt_sextend_i8_i32(i8, i8) -> i8 { +block0(v0: i8, v1: i8): + v2 = sextend.i32 v0 + v3 = sextend.i32 v1 + v4 = icmp slt v2, v3 + return v4 +} +; check: v5 = icmp slt v0, v1 +; check: return v5 + +function %eq_sextend_i16_i64(i16, i16) -> i8 { +block0(v0: i16, v1: i16): + v2 = sextend.i64 v0 + v3 = sextend.i64 v1 + v4 = icmp eq v2, v3 + return v4 +} +; check: v5 = icmp eq v0, v1 +; check: return v5 + +function %slt_sextend_i16_i64(i16, i16) -> i8 { +block0(v0: i16, v1: i16): + v2 = sextend.i64 v0 + v3 = sextend.i64 v1 + v4 = icmp slt v2, v3 + return v4 +} +; check: v5 = icmp slt v0, v1 +; check: return v5 + +function %eq_sextend_i32_i64(i32, i32) -> i8 { +block0(v0: i32, v1: i32): + v2 = sextend.i64 v0 + v3 = sextend.i64 v1 + v4 = icmp eq v2, v3 + return v4 +} +; check: v5 = icmp eq v0, v1 +; check: return v5 + +function %slt_sextend_i32_i64(i32, i32) -> i8 { +block0(v0: i32, v1: i32): + v2 = sextend.i64 v0 + v3 = sextend.i64 v1 + v4 = icmp slt v2, v3 + return v4 +} +; check: v5 = icmp slt v0, v1 +; check: return v5 + +function %eq_sextend_i64_i128(i64, i64) -> i8 { +block0(v0: i64, v1: i64): + v2 = sextend.i128 v0 + v3 = sextend.i128 v1 + v4 = icmp eq v2, v3 + return v4 +} +; check: v5 = icmp eq v0, v1 +; check: return v5 + +function %slt_sextend_i64_i128(i64, i64) -> i8 { +block0(v0: i64, v1: i64): + v2 = sextend.i128 v0 + v3 = sextend.i128 v1 + v4 = icmp slt v2, v3 + return v4 +} +; check: v5 = icmp slt v0, v1 +; check: return v5 + +function %eq_sextend_different_input_types(i8, i16) -> i8 { +block0(v0: i8, v1: i16): + v2 = sextend.i32 v0 + v3 = sextend.i32 v1 + v4 = icmp eq v2, v3 + return v4 +} +; check: v2 = sextend.i32 v0 +; check: v3 = sextend.i32 v1 +; check: v4 = icmp eq v2, v3 +; check: return v4 + +function %slt_sextend_different_input_types(i8, i16) -> i8 { +block0(v0: i8, v1: i16): + v2 = sextend.i32 v0 + v3 = sextend.i32 v1 + v4 = icmp slt v2, v3 + return v4 +} +; check: v2 = sextend.i32 v0 +; check: v3 = sextend.i32 v1 +; check: v4 = icmp slt v2, v3 +; check: return v4 + +function %eq_mixed_sign_and_zero_extend(i8, i8) -> i8 { +block0(v0: i8, v1: i8): + v2 = sextend.i32 v0 + v3 = uextend.i32 v1 + v4 = icmp eq v2, v3 + return v4 +} +; check: v2 = sextend.i32 v0 +; check: v3 = uextend.i32 v1 +; check: v4 = icmp eq v2, v3 +; check: return v4 diff --git a/cranelift/filetests/filetests/egraph/icmp.clif b/cranelift/filetests/filetests/egraph/icmp.clif index a6f50c828a0c..5afa9a73cd17 100644 --- a/cranelift/filetests/filetests/egraph/icmp.clif +++ b/cranelift/filetests/filetests/egraph/icmp.clif @@ -1286,3 +1286,76 @@ block0(v0: i32, v1: i32): ; v7 = icmp eq v0, v6 ; return v7 ; } + +function %eq_rotr_i32(i32, i32, i32) -> i8 { +block0(v0: i32, v1: i32, v2: i32): + v3 = rotr v0, v2 + v4 = rotr v1, v2 + v5 = icmp eq v3, v4 + return v5 +} + +; function %eq_rotr_i32(i32, i32, i32) -> i8 fast { +; block0(v0: i32, v1: i32, v2: i32): +; v6 = icmp eq v0, v1 +; return v6 +; } + +function %eq_rotr_i64(i64, i64, i64) -> i8 { +block0(v0: i64, v1: i64, v2: i64): + v3 = rotr v0, v2 + v4 = rotr v1, v2 + v5 = icmp eq v3, v4 + return v5 +} + +; function %eq_rotr_i64(i64, i64, i64) -> i8 fast { +; block0(v0: i64, v1: i64, v2: i64): +; v6 = icmp eq v0, v1 +; return v6 +; } + +function %eq_rotr_i32_i8_count(i32, i32, i8) -> i8 { +block0(v0: i32, v1: i32, v2: i8): + v3 = rotr v0, v2 + v4 = rotr v1, v2 + v5 = icmp eq v3, v4 + return v5 +} + +; function %eq_rotr_i32_i8_count(i32, i32, i8) -> i8 fast { +; block0(v0: i32, v1: i32, v2: i8): +; v6 = icmp eq v0, v1 +; return v6 +; } + +function %eq_rotr_different_counts(i32, i32, i32, i32) -> i8 { +block0(v0: i32, v1: i32, v2: i32, v3: i32): + v4 = rotr v0, v2 + v5 = rotr v1, v3 + v6 = icmp eq v4, v5 + return v6 +} + +; function %eq_rotr_different_counts(i32, i32, i32, i32) -> i8 fast { +; block0(v0: i32, v1: i32, v2: i32, v3: i32): +; v4 = rotr v0, v2 +; v5 = rotr v1, v3 +; v6 = icmp eq v4, v5 +; return v6 +; } + +function %eq_rotr_shared(i32, i32, i32) -> i8, i32 { +block0(v0: i32, v1: i32, v2: i32): + v3 = rotr v0, v2 + v4 = rotr v1, v2 + v5 = icmp eq v3, v4 + return v5, v3 +} + +; function %eq_rotr_shared(i32, i32, i32) -> i8, i32 fast { +; block0(v0: i32, v1: i32, v2: i32): +; v6 = icmp eq v0, v1 +; v3 = rotr v0, v2 +; return v6, v3 +; } diff --git a/cranelift/filetests/filetests/egraph/selects.clif b/cranelift/filetests/filetests/egraph/selects.clif index b715c913b614..cdaf418c88df 100644 --- a/cranelift/filetests/filetests/egraph/selects.clif +++ b/cranelift/filetests/filetests/egraph/selects.clif @@ -274,3 +274,379 @@ block0(v0: i32, v1: i32): ; v3 = isub v0, v1 ; return v3 ; } + +function %band_swapped_selects(i8, i32, i32) -> i32 { +block0(v0: i8, v1: i32, v2: i32): + v3 = select v0, v1, v2 + v4 = select v0, v2, v1 + v5 = band v3, v4 + return v5 +} + +; function %band_swapped_selects(i8, i32, i32) -> i32 fast { +; block0(v0: i8, v1: i32, v2: i32): +; v6 = band v1, v2 +; return v6 +; } + +function %bor_swapped_selects(i8, i32, i32) -> i32 { +block0(v0: i8, v1: i32, v2: i32): + v3 = select v0, v1, v2 + v4 = select v0, v2, v1 + v5 = bor v3, v4 + return v5 +} + +; function %bor_swapped_selects(i8, i32, i32) -> i32 fast { +; block0(v0: i8, v1: i32, v2: i32): +; v6 = bor v1, v2 +; return v6 +; } + +function %bxor_swapped_selects(i8, i32, i32) -> i32 { +block0(v0: i8, v1: i32, v2: i32): + v3 = select v0, v1, v2 + v4 = select v0, v2, v1 + v5 = bxor v3, v4 + return v5 +} + +; function %bxor_swapped_selects(i8, i32, i32) -> i32 fast { +; block0(v0: i8, v1: i32, v2: i32): +; v6 = bxor v1, v2 +; return v6 +; } + +function %band_swapped_selects_shared(i8, i32, i32) -> i32, i32 { +block0(v0: i8, v1: i32, v2: i32): + v3 = select v0, v1, v2 + v4 = select v0, v2, v1 + v5 = band v3, v4 + return v5, v3 +} + +; function %band_swapped_selects_shared(i8, i32, i32) -> i32, i32 fast { +; block0(v0: i8, v1: i32, v2: i32): +; v6 = band v1, v2 +; v3 = select v0, v1, v2 +; return v6, v3 +; } + +function %band_selects_different_conditions(i8, i8, i32, i32) -> i32 { +block0(v0: i8, v1: i8, v2: i32, v3: i32): + v4 = select v0, v2, v3 + v5 = select v1, v3, v2 + v6 = band v4, v5 + return v6 +} + +; function %band_selects_different_conditions(i8, i8, i32, i32) -> i32 fast { +; block0(v0: i8, v1: i8, v2: i32, v3: i32): +; v4 = select v0, v2, v3 +; v5 = select v1, v3, v2 +; v6 = band v4, v5 +; return v6 +; } + +function %select_eq_bxor_zero(i32, i32) -> i32 { +block0(v0: i32, v1: i32): + v2 = icmp eq v0, v1 + v3 = iconst.i32 0 + v4 = bxor v0, v1 + v5 = select v2, v3, v4 + return v5 +} + +; function %select_eq_bxor_zero(i32, i32) -> i32 fast { +; block0(v0: i32, v1: i32): +; v4 = bxor v0, v1 +; return v4 +; } + +function %select_eq_bxor_zero_commuted(i32, i32) -> i32 { +block0(v0: i32, v1: i32): + v2 = icmp eq v0, v1 + v3 = iconst.i32 0 + v4 = bxor v1, v0 + v5 = select v2, v3, v4 + return v5 +} + +; function %select_eq_bxor_zero_commuted(i32, i32) -> i32 fast { +; block0(v0: i32, v1: i32): +; v6 = bxor v0, v1 +; return v6 +; } + +function %select_ne_bxor_zero(i32, i32) -> i32 { +block0(v0: i32, v1: i32): + v2 = icmp ne v0, v1 + v3 = iconst.i32 0 + v4 = bxor v0, v1 + v5 = select v2, v4, v3 + return v5 +} + +; function %select_ne_bxor_zero(i32, i32) -> i32 fast { +; block0(v0: i32, v1: i32): +; v4 = bxor v0, v1 +; return v4 +; } + +function %select_ne_bxor_zero_commuted(i32, i32) -> i32 { +block0(v0: i32, v1: i32): + v2 = icmp ne v0, v1 + v3 = iconst.i32 0 + v4 = bxor v1, v0 + v5 = select v2, v4, v3 + return v5 +} + +; function %select_ne_bxor_zero_commuted(i32, i32) -> i32 fast { +; block0(v0: i32, v1: i32): +; v6 = bxor v0, v1 +; return v6 +; } + +function %select_zero_count_ishl_eq_i32(i32, i32) -> i32 { +block0(v0: i32, v1: i32): + v2 = iconst.i32 0 + v3 = icmp eq v1, v2 + v4 = ishl v0, v1 + v5 = select v3, v0, v4 + return v5 +} + +; function %select_zero_count_ishl_eq_i32(i32, i32) -> i32 fast { +; block0(v0: i32, v1: i32): +; v4 = ishl v0, v1 +; return v4 +; } + +function %select_zero_count_ishl_ne_i32(i32, i32) -> i32 { +block0(v0: i32, v1: i32): + v2 = iconst.i32 0 + v3 = icmp ne v1, v2 + v4 = ishl v0, v1 + v5 = select v3, v4, v0 + return v5 +} + +; function %select_zero_count_ishl_ne_i32(i32, i32) -> i32 fast { +; block0(v0: i32, v1: i32): +; v4 = ishl v0, v1 +; return v4 +; } + +function %select_zero_count_ushr_eq_i32(i32, i32) -> i32 { +block0(v0: i32, v1: i32): + v2 = iconst.i32 0 + v3 = icmp eq v1, v2 + v4 = ushr v0, v1 + v5 = select v3, v0, v4 + return v5 +} + +; function %select_zero_count_ushr_eq_i32(i32, i32) -> i32 fast { +; block0(v0: i32, v1: i32): +; v4 = ushr v0, v1 +; return v4 +; } + +function %select_zero_count_ushr_ne_i32(i32, i32) -> i32 { +block0(v0: i32, v1: i32): + v2 = iconst.i32 0 + v3 = icmp ne v1, v2 + v4 = ushr v0, v1 + v5 = select v3, v4, v0 + return v5 +} + +; function %select_zero_count_ushr_ne_i32(i32, i32) -> i32 fast { +; block0(v0: i32, v1: i32): +; v4 = ushr v0, v1 +; return v4 +; } + +function %select_zero_count_sshr_eq_i32(i32, i32) -> i32 { +block0(v0: i32, v1: i32): + v2 = iconst.i32 0 + v3 = icmp eq v1, v2 + v4 = sshr v0, v1 + v5 = select v3, v0, v4 + return v5 +} + +; function %select_zero_count_sshr_eq_i32(i32, i32) -> i32 fast { +; block0(v0: i32, v1: i32): +; v4 = sshr v0, v1 +; return v4 +; } + +function %select_zero_count_sshr_ne_i32(i32, i32) -> i32 { +block0(v0: i32, v1: i32): + v2 = iconst.i32 0 + v3 = icmp ne v1, v2 + v4 = sshr v0, v1 + v5 = select v3, v4, v0 + return v5 +} + +; function %select_zero_count_sshr_ne_i32(i32, i32) -> i32 fast { +; block0(v0: i32, v1: i32): +; v4 = sshr v0, v1 +; return v4 +; } + +function %select_zero_count_rotl_eq_i32(i32, i32) -> i32 { +block0(v0: i32, v1: i32): + v2 = iconst.i32 0 + v3 = icmp eq v1, v2 + v4 = rotl v0, v1 + v5 = select v3, v0, v4 + return v5 +} + +; function %select_zero_count_rotl_eq_i32(i32, i32) -> i32 fast { +; block0(v0: i32, v1: i32): +; v4 = rotl v0, v1 +; return v4 +; } + +function %select_zero_count_rotl_ne_i32(i32, i32) -> i32 { +block0(v0: i32, v1: i32): + v2 = iconst.i32 0 + v3 = icmp ne v1, v2 + v4 = rotl v0, v1 + v5 = select v3, v4, v0 + return v5 +} + +; function %select_zero_count_rotl_ne_i32(i32, i32) -> i32 fast { +; block0(v0: i32, v1: i32): +; v4 = rotl v0, v1 +; return v4 +; } + +function %select_zero_count_rotr_eq_i32(i32, i32) -> i32 { +block0(v0: i32, v1: i32): + v2 = iconst.i32 0 + v3 = icmp eq v1, v2 + v4 = rotr v0, v1 + v5 = select v3, v0, v4 + return v5 +} + +; function %select_zero_count_rotr_eq_i32(i32, i32) -> i32 fast { +; block0(v0: i32, v1: i32): +; v4 = rotr v0, v1 +; return v4 +; } + +function %select_zero_count_rotr_ne_i32(i32, i32) -> i32 { +block0(v0: i32, v1: i32): + v2 = iconst.i32 0 + v3 = icmp ne v1, v2 + v4 = rotr v0, v1 + v5 = select v3, v4, v0 + return v5 +} + +; function %select_zero_count_rotr_ne_i32(i32, i32) -> i32 fast { +; block0(v0: i32, v1: i32): +; v4 = rotr v0, v1 +; return v4 +; } + +function %select_zero_count_ishl_eq_i64(i64, i8) -> i64 { +block0(v0: i64, v1: i8): + v2 = iconst.i8 0 + v3 = icmp eq v1, v2 + v4 = ishl v0, v1 + v5 = select v3, v0, v4 + return v5 +} + +; function %select_zero_count_ishl_eq_i64(i64, i8) -> i64 fast { +; block0(v0: i64, v1: i8): +; v4 = ishl v0, v1 +; return v4 +; } + +function %select_zero_count_ushr_eq_i64(i64, i8) -> i64 { +block0(v0: i64, v1: i8): + v2 = iconst.i8 0 + v3 = icmp eq v1, v2 + v4 = ushr v0, v1 + v5 = select v3, v0, v4 + return v5 +} + +; function %select_zero_count_ushr_eq_i64(i64, i8) -> i64 fast { +; block0(v0: i64, v1: i8): +; v4 = ushr v0, v1 +; return v4 +; } + +function %select_zero_count_sshr_eq_i64(i64, i8) -> i64 { +block0(v0: i64, v1: i8): + v2 = iconst.i8 0 + v3 = icmp eq v1, v2 + v4 = sshr v0, v1 + v5 = select v3, v0, v4 + return v5 +} + +; function %select_zero_count_sshr_eq_i64(i64, i8) -> i64 fast { +; block0(v0: i64, v1: i8): +; v4 = sshr v0, v1 +; return v4 +; } + +function %select_zero_count_rotl_eq_i64(i64, i8) -> i64 { +block0(v0: i64, v1: i8): + v2 = iconst.i8 0 + v3 = icmp eq v1, v2 + v4 = rotl v0, v1 + v5 = select v3, v0, v4 + return v5 +} + +; function %select_zero_count_rotl_eq_i64(i64, i8) -> i64 fast { +; block0(v0: i64, v1: i8): +; v4 = rotl v0, v1 +; return v4 +; } + +function %select_zero_count_rotr_eq_i64(i64, i8) -> i64 { +block0(v0: i64, v1: i8): + v2 = iconst.i8 0 + v3 = icmp eq v1, v2 + v4 = rotr v0, v1 + v5 = select v3, v0, v4 + return v5 +} + +; function %select_zero_count_rotr_eq_i64(i64, i8) -> i64 fast { +; block0(v0: i64, v1: i8): +; v4 = rotr v0, v1 +; return v4 +; } + +function %select_nonzero_count_ishl(i32, i32) -> i32 { +block0(v0: i32, v1: i32): + v2 = iconst.i32 1 + v3 = icmp eq v1, v2 + v4 = ishl v0, v1 + v5 = select v3, v0, v4 + return v5 +} + +; function %select_nonzero_count_ishl(i32, i32) -> i32 fast { +; block0(v0: i32, v1: i32): +; v2 = iconst.i32 1 +; v3 = icmp eq v1, v2 ; v2 = 1 +; v4 = ishl v0, v1 +; v5 = select v3, v0, v4 +; return v5 +; } diff --git a/cranelift/filetests/filetests/runtests/extend.clif b/cranelift/filetests/filetests/runtests/extend.clif index 6a3474a333ea..229f5421e0c2 100644 --- a/cranelift/filetests/filetests/runtests/extend.clif +++ b/cranelift/filetests/filetests/runtests/extend.clif @@ -325,3 +325,161 @@ block0(v0: i8, v1: i16): ; run: %ult_uextend_different_input_types(255, 256) == 1 ; run: %ult_uextend_different_input_types(255, 254) == 0 ; run: %ult_uextend_different_input_types(128, 32768) == 1 + +function %eq_sextend_i8_i32(i8, i8) -> i8 { +block0(v0: i8, v1: i8): + v2 = sextend.i32 v0 + v3 = sextend.i32 v1 + v4 = icmp eq v2, v3 + return v4 +} +; run: %eq_sextend_i8_i32(0, 0) == 1 +; run: %eq_sextend_i8_i32(-1, -1) == 1 +; run: %eq_sextend_i8_i32(-1, 0) == 0 +; run: %eq_sextend_i8_i32(0, -1) == 0 +; run: %eq_sextend_i8_i32(-128, 127) == 0 +; run: %eq_sextend_i8_i32(127, -128) == 0 +; run: %eq_sextend_i8_i32(-128, -128) == 1 + +function %slt_sextend_i8_i32(i8, i8) -> i8 { +block0(v0: i8, v1: i8): + v2 = sextend.i32 v0 + v3 = sextend.i32 v1 + v4 = icmp slt v2, v3 + return v4 +} +; run: %slt_sextend_i8_i32(0, 0) == 0 +; run: %slt_sextend_i8_i32(-1, -1) == 0 +; run: %slt_sextend_i8_i32(-1, 0) == 1 +; run: %slt_sextend_i8_i32(0, -1) == 0 +; run: %slt_sextend_i8_i32(-128, 127) == 1 +; run: %slt_sextend_i8_i32(127, -128) == 0 +; run: %slt_sextend_i8_i32(-128, -128) == 0 + +function %eq_sextend_i16_i64(i16, i16) -> i8 { +block0(v0: i16, v1: i16): + v2 = sextend.i64 v0 + v3 = sextend.i64 v1 + v4 = icmp eq v2, v3 + return v4 +} +; run: %eq_sextend_i16_i64(0, 0) == 1 +; run: %eq_sextend_i16_i64(-1, -1) == 1 +; run: %eq_sextend_i16_i64(-1, 0) == 0 +; run: %eq_sextend_i16_i64(0, -1) == 0 +; run: %eq_sextend_i16_i64(-32768, 32767) == 0 +; run: %eq_sextend_i16_i64(32767, -32768) == 0 +; run: %eq_sextend_i16_i64(-32768, -32768) == 1 + +function %slt_sextend_i16_i64(i16, i16) -> i8 { +block0(v0: i16, v1: i16): + v2 = sextend.i64 v0 + v3 = sextend.i64 v1 + v4 = icmp slt v2, v3 + return v4 +} +; run: %slt_sextend_i16_i64(0, 0) == 0 +; run: %slt_sextend_i16_i64(-1, -1) == 0 +; run: %slt_sextend_i16_i64(-1, 0) == 1 +; run: %slt_sextend_i16_i64(0, -1) == 0 +; run: %slt_sextend_i16_i64(-32768, 32767) == 1 +; run: %slt_sextend_i16_i64(32767, -32768) == 0 +; run: %slt_sextend_i16_i64(-32768, -32768) == 0 + +function %eq_sextend_i32_i64(i32, i32) -> i8 { +block0(v0: i32, v1: i32): + v2 = sextend.i64 v0 + v3 = sextend.i64 v1 + v4 = icmp eq v2, v3 + return v4 +} +; run: %eq_sextend_i32_i64(0, 0) == 1 +; run: %eq_sextend_i32_i64(-1, -1) == 1 +; run: %eq_sextend_i32_i64(-1, 0) == 0 +; run: %eq_sextend_i32_i64(0, -1) == 0 +; run: %eq_sextend_i32_i64(-2147483648, 2147483647) == 0 +; run: %eq_sextend_i32_i64(2147483647, -2147483648) == 0 +; run: %eq_sextend_i32_i64(-2147483648, -2147483648) == 1 + +function %slt_sextend_i32_i64(i32, i32) -> i8 { +block0(v0: i32, v1: i32): + v2 = sextend.i64 v0 + v3 = sextend.i64 v1 + v4 = icmp slt v2, v3 + return v4 +} +; run: %slt_sextend_i32_i64(0, 0) == 0 +; run: %slt_sextend_i32_i64(-1, -1) == 0 +; run: %slt_sextend_i32_i64(-1, 0) == 1 +; run: %slt_sextend_i32_i64(0, -1) == 0 +; run: %slt_sextend_i32_i64(-2147483648, 2147483647) == 1 +; run: %slt_sextend_i32_i64(2147483647, -2147483648) == 0 +; run: %slt_sextend_i32_i64(-2147483648, -2147483648) == 0 + +function %eq_sextend_i64_i128(i64, i64) -> i8 { +block0(v0: i64, v1: i64): + v2 = sextend.i128 v0 + v3 = sextend.i128 v1 + v4 = icmp eq v2, v3 + return v4 +} +; run: %eq_sextend_i64_i128(0, 0) == 1 +; run: %eq_sextend_i64_i128(-1, -1) == 1 +; run: %eq_sextend_i64_i128(-1, 0) == 0 +; run: %eq_sextend_i64_i128(0, -1) == 0 +; run: %eq_sextend_i64_i128(-9223372036854775808, 9223372036854775807) == 0 +; run: %eq_sextend_i64_i128(9223372036854775807, -9223372036854775808) == 0 +; run: %eq_sextend_i64_i128(-9223372036854775808, -9223372036854775808) == 1 + +function %slt_sextend_i64_i128(i64, i64) -> i8 { +block0(v0: i64, v1: i64): + v2 = sextend.i128 v0 + v3 = sextend.i128 v1 + v4 = icmp slt v2, v3 + return v4 +} +; run: %slt_sextend_i64_i128(0, 0) == 0 +; run: %slt_sextend_i64_i128(-1, -1) == 0 +; run: %slt_sextend_i64_i128(-1, 0) == 1 +; run: %slt_sextend_i64_i128(0, -1) == 0 +; run: %slt_sextend_i64_i128(-9223372036854775808, 9223372036854775807) == 1 +; run: %slt_sextend_i64_i128(9223372036854775807, -9223372036854775808) == 0 +; run: %slt_sextend_i64_i128(-9223372036854775808, -9223372036854775808) == 0 + +function %eq_sextend_different_input_types(i8, i16) -> i8 { +block0(v0: i8, v1: i16): + v2 = sextend.i32 v0 + v3 = sextend.i32 v1 + v4 = icmp eq v2, v3 + return v4 +} +; run: %eq_sextend_different_input_types(-1, 255) == 0 +; run: %eq_sextend_different_input_types(-1, -1) == 1 +; run: %eq_sextend_different_input_types(-128, -129) == 0 +; run: %eq_sextend_different_input_types(-128, 128) == 0 +; run: %eq_sextend_different_input_types(127, -128) == 0 + +function %slt_sextend_different_input_types(i8, i16) -> i8 { +block0(v0: i8, v1: i16): + v2 = sextend.i32 v0 + v3 = sextend.i32 v1 + v4 = icmp slt v2, v3 + return v4 +} +; run: %slt_sextend_different_input_types(-1, 255) == 1 +; run: %slt_sextend_different_input_types(-1, -1) == 0 +; run: %slt_sextend_different_input_types(-128, -129) == 0 +; run: %slt_sextend_different_input_types(-128, 128) == 1 +; run: %slt_sextend_different_input_types(127, -128) == 0 + +function %eq_mixed_sign_and_zero_extend(i8, i8) -> i8 { +block0(v0: i8, v1: i8): + v2 = sextend.i32 v0 + v3 = uextend.i32 v1 + v4 = icmp eq v2, v3 + return v4 +} +; run: %eq_mixed_sign_and_zero_extend(-1, -1) == 0 +; run: %eq_mixed_sign_and_zero_extend(0, 0) == 1 +; run: %eq_mixed_sign_and_zero_extend(127, 127) == 1 +; run: %eq_mixed_sign_and_zero_extend(-128, -128) == 0 diff --git a/cranelift/filetests/filetests/runtests/icmp.clif b/cranelift/filetests/filetests/runtests/icmp.clif index e658aaa50e17..bb17931ae323 100644 --- a/cranelift/filetests/filetests/runtests/icmp.clif +++ b/cranelift/filetests/filetests/runtests/icmp.clif @@ -380,3 +380,70 @@ block0(v0: i32, v1: i32): ; run: %signed_bounds_variable_limit(-1, -1) == 0 ; run: %signed_bounds_variable_limit(0, 1) == 1 ; run: %signed_bounds_variable_limit(100, 100) == 0 + +function %eq_rotr_i32(i32, i32, i32) -> i8 { +block0(v0: i32, v1: i32, v2: i32): + v3 = rotr v0, v2 + v4 = rotr v1, v2 + v5 = icmp eq v3, v4 + return v5 +} +; run: %eq_rotr_i32(0, 0, 0) == 1 +; run: %eq_rotr_i32(1, 2, 1) == 0 +; run: %eq_rotr_i32(-1, -1, 1) == 1 +; run: %eq_rotr_i32(-2147483648, 2147483647, 31) == 0 +; run: %eq_rotr_i32(7, 7, 32) == 1 +; run: %eq_rotr_i32(7, 8, 33) == 0 +; run: %eq_rotr_i32(7, 7, -1) == 1 + +function %eq_rotr_i64(i64, i64, i64) -> i8 { +block0(v0: i64, v1: i64, v2: i64): + v3 = rotr v0, v2 + v4 = rotr v1, v2 + v5 = icmp eq v3, v4 + return v5 +} +; run: %eq_rotr_i64(0, 0, 0) == 1 +; run: %eq_rotr_i64(1, 2, 1) == 0 +; run: %eq_rotr_i64(-1, -1, 1) == 1 +; run: %eq_rotr_i64(-9223372036854775808, 9223372036854775807, 63) == 0 +; run: %eq_rotr_i64(7, 7, 64) == 1 +; run: %eq_rotr_i64(7, 8, 65) == 0 +; run: %eq_rotr_i64(7, 7, -1) == 1 + +function %eq_rotr_i32_i8_count(i32, i32, i8) -> i8 { +block0(v0: i32, v1: i32, v2: i8): + v3 = rotr v0, v2 + v4 = rotr v1, v2 + v5 = icmp eq v3, v4 + return v5 +} +; run: %eq_rotr_i32_i8_count(0, 0, 0) == 1 +; run: %eq_rotr_i32_i8_count(1, 2, 1) == 0 +; run: %eq_rotr_i32_i8_count(-1, -1, 1) == 1 +; run: %eq_rotr_i32_i8_count(-2147483648, 2147483647, 31) == 0 +; run: %eq_rotr_i32_i8_count(7, 7, 32) == 1 +; run: %eq_rotr_i32_i8_count(7, 8, 33) == 0 +; run: %eq_rotr_i32_i8_count(7, 7, -1) == 1 + +function %eq_rotr_different_counts(i32, i32, i32, i32) -> i8 { +block0(v0: i32, v1: i32, v2: i32, v3: i32): + v4 = rotr v0, v2 + v5 = rotr v1, v3 + v6 = icmp eq v4, v5 + return v6 +} +; run: %eq_rotr_different_counts(1, 2, 0, 1) == 1 +; run: %eq_rotr_different_counts(1, 1, 0, 1) == 0 +; run: %eq_rotr_different_counts(7, 7, 0, 32) == 1 + +function %eq_rotr_shared(i32, i32, i32) -> i8, i32 { +block0(v0: i32, v1: i32, v2: i32): + v3 = rotr v0, v2 + v4 = rotr v1, v2 + v5 = icmp eq v3, v4 + return v5, v3 +} +; run: %eq_rotr_shared(1, 1, 1) == [1, -2147483648] +; run: %eq_rotr_shared(1, 2, 1) == [0, -2147483648] +; run: %eq_rotr_shared(7, 7, 32) == [1, 7] diff --git a/cranelift/filetests/filetests/runtests/select.clif b/cranelift/filetests/filetests/runtests/select.clif index be35248ed51f..85ac0ac0f356 100644 --- a/cranelift/filetests/filetests/runtests/select.clif +++ b/cranelift/filetests/filetests/runtests/select.clif @@ -11,6 +11,18 @@ target pulley32be target pulley64 target pulley64be +set opt_level=speed +target aarch64 +target s390x +target x86_64 +target riscv64 +target riscv64 has_zicond +target riscv64 has_c has_zcb +target pulley32 +target pulley32be +target pulley64 +target pulley64be + function %select_eq_f32(f32, f32) -> i32 { block0(v0: f32, v1: f32): v2 = fcmp eq v0, v1 @@ -632,3 +644,389 @@ block0(v0: i32, v1: i32): ; run: %select_ne_isub_zero(7, 7) == 0 ; run: %select_ne_isub_zero(7, 3) == 4 ; run: %select_ne_isub_zero(3, 7) == -4 + +function %band_swapped_selects(i8, i32, i32) -> i32 { +block0(v0: i8, v1: i32, v2: i32): + v3 = select v0, v1, v2 + v4 = select v0, v2, v1 + v5 = band v3, v4 + return v5 +} +; run: %band_swapped_selects(0, 85, 51) == 17 +; run: %band_swapped_selects(1, 85, 51) == 17 +; run: %band_swapped_selects(2, 85, 51) == 17 +; run: %band_swapped_selects(-128, 85, 51) == 17 +; run: %band_swapped_selects(0, -1, -1) == -1 +; run: %band_swapped_selects(2, 0, 0) == 0 + +function %bor_swapped_selects(i8, i32, i32) -> i32 { +block0(v0: i8, v1: i32, v2: i32): + v3 = select v0, v1, v2 + v4 = select v0, v2, v1 + v5 = bor v3, v4 + return v5 +} +; run: %bor_swapped_selects(0, 85, 51) == 119 +; run: %bor_swapped_selects(1, 85, 51) == 119 +; run: %bor_swapped_selects(2, 85, 51) == 119 +; run: %bor_swapped_selects(-128, 85, 51) == 119 +; run: %bor_swapped_selects(0, -1, -1) == -1 +; run: %bor_swapped_selects(2, 0, 0) == 0 + +function %bxor_swapped_selects(i8, i32, i32) -> i32 { +block0(v0: i8, v1: i32, v2: i32): + v3 = select v0, v1, v2 + v4 = select v0, v2, v1 + v5 = bxor v3, v4 + return v5 +} +; run: %bxor_swapped_selects(0, 85, 51) == 102 +; run: %bxor_swapped_selects(1, 85, 51) == 102 +; run: %bxor_swapped_selects(2, 85, 51) == 102 +; run: %bxor_swapped_selects(-128, 85, 51) == 102 +; run: %bxor_swapped_selects(0, -1, -1) == 0 +; run: %bxor_swapped_selects(2, 0, 0) == 0 + +function %band_swapped_selects_shared(i8, i32, i32) -> i32, i32 { +block0(v0: i8, v1: i32, v2: i32): + v3 = select v0, v1, v2 + v4 = select v0, v2, v1 + v5 = band v3, v4 + return v5, v3 +} +; run: %band_swapped_selects_shared(0, 85, 51) == [17, 51] +; run: %band_swapped_selects_shared(2, 85, 51) == [17, 85] + +function %band_selects_different_conditions(i8, i8, i32, i32) -> i32 { +block0(v0: i8, v1: i8, v2: i32, v3: i32): + v4 = select v0, v2, v3 + v5 = select v1, v3, v2 + v6 = band v4, v5 + return v6 +} +; run: %band_selects_different_conditions(0, 1, 85, 51) == 51 +; run: %band_selects_different_conditions(1, 0, 85, 51) == 85 +; run: %band_selects_different_conditions(0, 0, 85, 51) == 17 + +function %select_eq_bxor_zero(i32, i32) -> i32 { +block0(v0: i32, v1: i32): + v2 = icmp eq v0, v1 + v3 = iconst.i32 0 + v4 = bxor v0, v1 + v5 = select v2, v3, v4 + return v5 +} +; run: %select_eq_bxor_zero(0, 0) == 0 +; run: %select_eq_bxor_zero(-1, -1) == 0 +; run: %select_eq_bxor_zero(85, 51) == 102 +; run: %select_eq_bxor_zero(-1, 0) == -1 +; run: %select_eq_bxor_zero(-2147483648, 2147483647) == -1 + +function %select_eq_bxor_zero_commuted(i32, i32) -> i32 { +block0(v0: i32, v1: i32): + v2 = icmp eq v0, v1 + v3 = iconst.i32 0 + v4 = bxor v1, v0 + v5 = select v2, v3, v4 + return v5 +} +; run: %select_eq_bxor_zero_commuted(0, 0) == 0 +; run: %select_eq_bxor_zero_commuted(-1, -1) == 0 +; run: %select_eq_bxor_zero_commuted(85, 51) == 102 +; run: %select_eq_bxor_zero_commuted(-1, 0) == -1 +; run: %select_eq_bxor_zero_commuted(-2147483648, 2147483647) == -1 + +function %select_ne_bxor_zero(i32, i32) -> i32 { +block0(v0: i32, v1: i32): + v2 = icmp ne v0, v1 + v3 = iconst.i32 0 + v4 = bxor v0, v1 + v5 = select v2, v4, v3 + return v5 +} +; run: %select_ne_bxor_zero(0, 0) == 0 +; run: %select_ne_bxor_zero(-1, -1) == 0 +; run: %select_ne_bxor_zero(85, 51) == 102 +; run: %select_ne_bxor_zero(-1, 0) == -1 +; run: %select_ne_bxor_zero(-2147483648, 2147483647) == -1 + +function %select_ne_bxor_zero_commuted(i32, i32) -> i32 { +block0(v0: i32, v1: i32): + v2 = icmp ne v0, v1 + v3 = iconst.i32 0 + v4 = bxor v1, v0 + v5 = select v2, v4, v3 + return v5 +} +; run: %select_ne_bxor_zero_commuted(0, 0) == 0 +; run: %select_ne_bxor_zero_commuted(-1, -1) == 0 +; run: %select_ne_bxor_zero_commuted(85, 51) == 102 +; run: %select_ne_bxor_zero_commuted(-1, 0) == -1 +; run: %select_ne_bxor_zero_commuted(-2147483648, 2147483647) == -1 + +function %select_zero_count_ishl_eq_i32(i32, i32) -> i32 { +block0(v0: i32, v1: i32): + v2 = iconst.i32 0 + v3 = icmp eq v1, v2 + v4 = ishl v0, v1 + v5 = select v3, v0, v4 + return v5 +} +; run: %select_zero_count_ishl_eq_i32(7, 0) == 7 +; run: %select_zero_count_ishl_eq_i32(7, 1) == 14 +; run: %select_zero_count_ishl_eq_i32(-1, 1) == -2 +; run: %select_zero_count_ishl_eq_i32(-2147483648, 1) == 0 +; run: %select_zero_count_ishl_eq_i32(-1, 31) == -2147483648 +; run: %select_zero_count_ishl_eq_i32(7, 32) == 7 +; run: %select_zero_count_ishl_eq_i32(7, 33) == 14 +; run: %select_zero_count_ishl_eq_i32(1, -1) == -2147483648 + +function %select_zero_count_ishl_ne_i32(i32, i32) -> i32 { +block0(v0: i32, v1: i32): + v2 = iconst.i32 0 + v3 = icmp ne v1, v2 + v4 = ishl v0, v1 + v5 = select v3, v4, v0 + return v5 +} +; run: %select_zero_count_ishl_ne_i32(7, 0) == 7 +; run: %select_zero_count_ishl_ne_i32(7, 1) == 14 +; run: %select_zero_count_ishl_ne_i32(-1, 1) == -2 +; run: %select_zero_count_ishl_ne_i32(-2147483648, 1) == 0 +; run: %select_zero_count_ishl_ne_i32(-1, 31) == -2147483648 +; run: %select_zero_count_ishl_ne_i32(7, 32) == 7 +; run: %select_zero_count_ishl_ne_i32(7, 33) == 14 +; run: %select_zero_count_ishl_ne_i32(1, -1) == -2147483648 + +function %select_zero_count_ushr_eq_i32(i32, i32) -> i32 { +block0(v0: i32, v1: i32): + v2 = iconst.i32 0 + v3 = icmp eq v1, v2 + v4 = ushr v0, v1 + v5 = select v3, v0, v4 + return v5 +} +; run: %select_zero_count_ushr_eq_i32(7, 0) == 7 +; run: %select_zero_count_ushr_eq_i32(7, 1) == 3 +; run: %select_zero_count_ushr_eq_i32(-1, 1) == 2147483647 +; run: %select_zero_count_ushr_eq_i32(-2147483648, 1) == 1073741824 +; run: %select_zero_count_ushr_eq_i32(-1, 31) == 1 +; run: %select_zero_count_ushr_eq_i32(7, 32) == 7 +; run: %select_zero_count_ushr_eq_i32(7, 33) == 3 +; run: %select_zero_count_ushr_eq_i32(1, -1) == 0 + +function %select_zero_count_ushr_ne_i32(i32, i32) -> i32 { +block0(v0: i32, v1: i32): + v2 = iconst.i32 0 + v3 = icmp ne v1, v2 + v4 = ushr v0, v1 + v5 = select v3, v4, v0 + return v5 +} +; run: %select_zero_count_ushr_ne_i32(7, 0) == 7 +; run: %select_zero_count_ushr_ne_i32(7, 1) == 3 +; run: %select_zero_count_ushr_ne_i32(-1, 1) == 2147483647 +; run: %select_zero_count_ushr_ne_i32(-2147483648, 1) == 1073741824 +; run: %select_zero_count_ushr_ne_i32(-1, 31) == 1 +; run: %select_zero_count_ushr_ne_i32(7, 32) == 7 +; run: %select_zero_count_ushr_ne_i32(7, 33) == 3 +; run: %select_zero_count_ushr_ne_i32(1, -1) == 0 + +function %select_zero_count_sshr_eq_i32(i32, i32) -> i32 { +block0(v0: i32, v1: i32): + v2 = iconst.i32 0 + v3 = icmp eq v1, v2 + v4 = sshr v0, v1 + v5 = select v3, v0, v4 + return v5 +} +; run: %select_zero_count_sshr_eq_i32(7, 0) == 7 +; run: %select_zero_count_sshr_eq_i32(7, 1) == 3 +; run: %select_zero_count_sshr_eq_i32(-1, 1) == -1 +; run: %select_zero_count_sshr_eq_i32(-2147483648, 1) == -1073741824 +; run: %select_zero_count_sshr_eq_i32(-1, 31) == -1 +; run: %select_zero_count_sshr_eq_i32(7, 32) == 7 +; run: %select_zero_count_sshr_eq_i32(7, 33) == 3 +; run: %select_zero_count_sshr_eq_i32(1, -1) == 0 + +function %select_zero_count_sshr_ne_i32(i32, i32) -> i32 { +block0(v0: i32, v1: i32): + v2 = iconst.i32 0 + v3 = icmp ne v1, v2 + v4 = sshr v0, v1 + v5 = select v3, v4, v0 + return v5 +} +; run: %select_zero_count_sshr_ne_i32(7, 0) == 7 +; run: %select_zero_count_sshr_ne_i32(7, 1) == 3 +; run: %select_zero_count_sshr_ne_i32(-1, 1) == -1 +; run: %select_zero_count_sshr_ne_i32(-2147483648, 1) == -1073741824 +; run: %select_zero_count_sshr_ne_i32(-1, 31) == -1 +; run: %select_zero_count_sshr_ne_i32(7, 32) == 7 +; run: %select_zero_count_sshr_ne_i32(7, 33) == 3 +; run: %select_zero_count_sshr_ne_i32(1, -1) == 0 + +function %select_zero_count_rotl_eq_i32(i32, i32) -> i32 { +block0(v0: i32, v1: i32): + v2 = iconst.i32 0 + v3 = icmp eq v1, v2 + v4 = rotl v0, v1 + v5 = select v3, v0, v4 + return v5 +} +; run: %select_zero_count_rotl_eq_i32(7, 0) == 7 +; run: %select_zero_count_rotl_eq_i32(7, 1) == 14 +; run: %select_zero_count_rotl_eq_i32(-1, 1) == -1 +; run: %select_zero_count_rotl_eq_i32(-2147483648, 1) == 1 +; run: %select_zero_count_rotl_eq_i32(-1, 31) == -1 +; run: %select_zero_count_rotl_eq_i32(7, 32) == 7 +; run: %select_zero_count_rotl_eq_i32(7, 33) == 14 +; run: %select_zero_count_rotl_eq_i32(1, -1) == -2147483648 + +function %select_zero_count_rotl_ne_i32(i32, i32) -> i32 { +block0(v0: i32, v1: i32): + v2 = iconst.i32 0 + v3 = icmp ne v1, v2 + v4 = rotl v0, v1 + v5 = select v3, v4, v0 + return v5 +} +; run: %select_zero_count_rotl_ne_i32(7, 0) == 7 +; run: %select_zero_count_rotl_ne_i32(7, 1) == 14 +; run: %select_zero_count_rotl_ne_i32(-1, 1) == -1 +; run: %select_zero_count_rotl_ne_i32(-2147483648, 1) == 1 +; run: %select_zero_count_rotl_ne_i32(-1, 31) == -1 +; run: %select_zero_count_rotl_ne_i32(7, 32) == 7 +; run: %select_zero_count_rotl_ne_i32(7, 33) == 14 +; run: %select_zero_count_rotl_ne_i32(1, -1) == -2147483648 + +function %select_zero_count_rotr_eq_i32(i32, i32) -> i32 { +block0(v0: i32, v1: i32): + v2 = iconst.i32 0 + v3 = icmp eq v1, v2 + v4 = rotr v0, v1 + v5 = select v3, v0, v4 + return v5 +} +; run: %select_zero_count_rotr_eq_i32(7, 0) == 7 +; run: %select_zero_count_rotr_eq_i32(7, 1) == -2147483645 +; run: %select_zero_count_rotr_eq_i32(-1, 1) == -1 +; run: %select_zero_count_rotr_eq_i32(-2147483648, 1) == 1073741824 +; run: %select_zero_count_rotr_eq_i32(-1, 31) == -1 +; run: %select_zero_count_rotr_eq_i32(7, 32) == 7 +; run: %select_zero_count_rotr_eq_i32(7, 33) == -2147483645 +; run: %select_zero_count_rotr_eq_i32(1, -1) == 2 + +function %select_zero_count_rotr_ne_i32(i32, i32) -> i32 { +block0(v0: i32, v1: i32): + v2 = iconst.i32 0 + v3 = icmp ne v1, v2 + v4 = rotr v0, v1 + v5 = select v3, v4, v0 + return v5 +} +; run: %select_zero_count_rotr_ne_i32(7, 0) == 7 +; run: %select_zero_count_rotr_ne_i32(7, 1) == -2147483645 +; run: %select_zero_count_rotr_ne_i32(-1, 1) == -1 +; run: %select_zero_count_rotr_ne_i32(-2147483648, 1) == 1073741824 +; run: %select_zero_count_rotr_ne_i32(-1, 31) == -1 +; run: %select_zero_count_rotr_ne_i32(7, 32) == 7 +; run: %select_zero_count_rotr_ne_i32(7, 33) == -2147483645 +; run: %select_zero_count_rotr_ne_i32(1, -1) == 2 + +function %select_zero_count_ishl_eq_i64(i64, i8) -> i64 { +block0(v0: i64, v1: i8): + v2 = iconst.i8 0 + v3 = icmp eq v1, v2 + v4 = ishl v0, v1 + v5 = select v3, v0, v4 + return v5 +} +; run: %select_zero_count_ishl_eq_i64(7, 0) == 7 +; run: %select_zero_count_ishl_eq_i64(7, 1) == 14 +; run: %select_zero_count_ishl_eq_i64(-1, 1) == -2 +; run: %select_zero_count_ishl_eq_i64(-9223372036854775808, 1) == 0 +; run: %select_zero_count_ishl_eq_i64(-1, 63) == -9223372036854775808 +; run: %select_zero_count_ishl_eq_i64(7, 64) == 7 +; run: %select_zero_count_ishl_eq_i64(7, 65) == 14 +; run: %select_zero_count_ishl_eq_i64(1, -1) == -9223372036854775808 + +function %select_zero_count_ushr_eq_i64(i64, i8) -> i64 { +block0(v0: i64, v1: i8): + v2 = iconst.i8 0 + v3 = icmp eq v1, v2 + v4 = ushr v0, v1 + v5 = select v3, v0, v4 + return v5 +} +; run: %select_zero_count_ushr_eq_i64(7, 0) == 7 +; run: %select_zero_count_ushr_eq_i64(7, 1) == 3 +; run: %select_zero_count_ushr_eq_i64(-1, 1) == 9223372036854775807 +; run: %select_zero_count_ushr_eq_i64(-9223372036854775808, 1) == 4611686018427387904 +; run: %select_zero_count_ushr_eq_i64(-1, 63) == 1 +; run: %select_zero_count_ushr_eq_i64(7, 64) == 7 +; run: %select_zero_count_ushr_eq_i64(7, 65) == 3 +; run: %select_zero_count_ushr_eq_i64(1, -1) == 0 + +function %select_zero_count_sshr_eq_i64(i64, i8) -> i64 { +block0(v0: i64, v1: i8): + v2 = iconst.i8 0 + v3 = icmp eq v1, v2 + v4 = sshr v0, v1 + v5 = select v3, v0, v4 + return v5 +} +; run: %select_zero_count_sshr_eq_i64(7, 0) == 7 +; run: %select_zero_count_sshr_eq_i64(7, 1) == 3 +; run: %select_zero_count_sshr_eq_i64(-1, 1) == -1 +; run: %select_zero_count_sshr_eq_i64(-9223372036854775808, 1) == -4611686018427387904 +; run: %select_zero_count_sshr_eq_i64(-1, 63) == -1 +; run: %select_zero_count_sshr_eq_i64(7, 64) == 7 +; run: %select_zero_count_sshr_eq_i64(7, 65) == 3 +; run: %select_zero_count_sshr_eq_i64(1, -1) == 0 + +function %select_zero_count_rotl_eq_i64(i64, i8) -> i64 { +block0(v0: i64, v1: i8): + v2 = iconst.i8 0 + v3 = icmp eq v1, v2 + v4 = rotl v0, v1 + v5 = select v3, v0, v4 + return v5 +} +; run: %select_zero_count_rotl_eq_i64(7, 0) == 7 +; run: %select_zero_count_rotl_eq_i64(7, 1) == 14 +; run: %select_zero_count_rotl_eq_i64(-1, 1) == -1 +; run: %select_zero_count_rotl_eq_i64(-9223372036854775808, 1) == 1 +; run: %select_zero_count_rotl_eq_i64(-1, 63) == -1 +; run: %select_zero_count_rotl_eq_i64(7, 64) == 7 +; run: %select_zero_count_rotl_eq_i64(7, 65) == 14 +; run: %select_zero_count_rotl_eq_i64(1, -1) == -9223372036854775808 + +function %select_zero_count_rotr_eq_i64(i64, i8) -> i64 { +block0(v0: i64, v1: i8): + v2 = iconst.i8 0 + v3 = icmp eq v1, v2 + v4 = rotr v0, v1 + v5 = select v3, v0, v4 + return v5 +} +; run: %select_zero_count_rotr_eq_i64(7, 0) == 7 +; run: %select_zero_count_rotr_eq_i64(7, 1) == -9223372036854775805 +; run: %select_zero_count_rotr_eq_i64(-1, 1) == -1 +; run: %select_zero_count_rotr_eq_i64(-9223372036854775808, 1) == 4611686018427387904 +; run: %select_zero_count_rotr_eq_i64(-1, 63) == -1 +; run: %select_zero_count_rotr_eq_i64(7, 64) == 7 +; run: %select_zero_count_rotr_eq_i64(7, 65) == -9223372036854775805 +; run: %select_zero_count_rotr_eq_i64(1, -1) == 2 + +function %select_nonzero_count_ishl(i32, i32) -> i32 { +block0(v0: i32, v1: i32): + v2 = iconst.i32 1 + v3 = icmp eq v1, v2 + v4 = ishl v0, v1 + v5 = select v3, v0, v4 + return v5 +} +; run: %select_nonzero_count_ishl(7, 0) == 7 +; run: %select_nonzero_count_ishl(7, 1) == 7 +; run: %select_nonzero_count_ishl(7, 2) == 28