Upstream update available: designs/src/coralnpu/dev/repo
- Repo: google-coral/coralnpu (branch
main)
- Pinned:
7731fd6 (2026-01-23)
- Upstream:
f5f6c88 (2026-06-22)
- Behind: 187 commits, 150 days stale
Severity: MAJOR
187 commits spanning ~5 months, including RTL/microarchitecture rework (fetch reorder buffer, pipelined speculative fetching, RVV datapath fixes, PLIC/CLINT peripherals, DMA engine, SRAM unification/DPI backing, SPI/I2C masters, new bus bridges), plus toolchain/build-system upgrades (Bazel 8.6, hermetic Verilator, Debian Trixie). This is architecture- and RTL-affecting and will very likely change synthesis results.
What changed (highlights)
- Core / RTL: fetch reorder buffer + pipelined speculative fetch; RVV correctness fixes (VFSGNJ, vslideup, LMUL reduction, matmul); Zfbfmin/Zvfbfmin/Zvfbfwma extensions; CSR/timing critical-path fixes.
- SoC integration: PLIC + CLINT (timer/msip interrupts), DMA engine, second SPI master + flash model, I2C master, AXI-burst
Axi2TLUL, width-bridge fixes, unified DPI-backed SRAMs.
- Peripherals/FPGA: clk_table, waveshare display HAL, ROM boot flow, FreeRTOS integration.
- Build/toolchain: Bazel 8.6.0, hermetic Verilator/CC/Python, multilib toolchain, Debian Trixie, VCS/UVM flow changes.
Recommendation
Review before updating; expect a full re-validation. The scope is large enough that RTL generation, memory inference, and QoR must all be re-checked. Treat as a deliberate re-port rather than a routine bump; verify FakeRAM cfgs still match the (possibly unified) SRAM instantiations.
Last refreshed: 2026-07-06 10:30:51 UTC
Upstream update available:
designs/src/coralnpu/dev/repomain)7731fd6(2026-01-23)f5f6c88(2026-06-22)Severity: MAJOR
187 commits spanning ~5 months, including RTL/microarchitecture rework (fetch reorder buffer, pipelined speculative fetching, RVV datapath fixes, PLIC/CLINT peripherals, DMA engine, SRAM unification/DPI backing, SPI/I2C masters, new bus bridges), plus toolchain/build-system upgrades (Bazel 8.6, hermetic Verilator, Debian Trixie). This is architecture- and RTL-affecting and will very likely change synthesis results.
What changed (highlights)
Axi2TLUL, width-bridge fixes, unified DPI-backed SRAMs.Recommendation
Review before updating; expect a full re-validation. The scope is large enough that RTL generation, memory inference, and QoR must all be re-checked. Treat as a deliberate re-port rather than a routine bump; verify FakeRAM cfgs still match the (possibly unified) SRAM instantiations.
Last refreshed: 2026-07-06 10:30:51 UTC