diff --git a/boards/common/simplelink_toolbox.board.cmake b/boards/common/simplelink_toolbox.board.cmake new file mode 100644 index 000000000000..d6b22d3f4fdc --- /dev/null +++ b/boards/common/simplelink_toolbox.board.cmake @@ -0,0 +1,7 @@ +# Copyright (c) 2025 Conclusive Engineering Sp. z o.o. +# +# SPDX-License-Identifier: Apache-2.0 + +board_set_flasher_ifnset(simplelink_toolbox) +board_set_debugger_ifnset(simplelink_toolbox) +board_finalize_runner_args(simplelink_toolbox) diff --git a/boards/common/ti_openocd.board.cmake b/boards/common/ti_openocd.board.cmake new file mode 100644 index 000000000000..d9f2f1845364 --- /dev/null +++ b/boards/common/ti_openocd.board.cmake @@ -0,0 +1,7 @@ +# Copyright (c) 2026 Texas Instruments Incorporated. +# +# SPDX-License-Identifier: Apache-2.0 + +# Force TI's openocd +set(OPENOCD OPENOCD-NOTFOUND) +find_program(OPENOCD openocd PATHS $ENV{TI_OPENOCD_INSTALL_DIR}/bin NO_DEFAULT_PATH) diff --git a/boards/deprecated.cmake b/boards/deprecated.cmake index 3277b7540fb4..68263d829dd5 100644 --- a/boards/deprecated.cmake +++ b/boards/deprecated.cmake @@ -13,6 +13,10 @@ # https://docs.zephyrproject.org/latest/develop/api/api_lifecycle.html#deprecated, # so these aliases are eventually removed +set(lp_em_cc35x1/_DEPRECATED + lp_em_cc35x1/cc3551e +) + set(arduino_uno_r4_minima_DEPRECATED arduino_uno_r4@minima ) diff --git a/boards/shields/adafruit_2_4_tft/Kconfig.defconfig b/boards/shields/adafruit_2_4_tft/Kconfig.defconfig new file mode 100644 index 000000000000..abbd4ef0c3f9 --- /dev/null +++ b/boards/shields/adafruit_2_4_tft/Kconfig.defconfig @@ -0,0 +1,28 @@ +# Copyright (c) 2026 Conclusive Engineering +# Copyright (c) 2026 Texas Instruments +# SPDX-License-Identifier: Apache-2.0 + +if SHIELD_ADAFRUIT_2_4_TFT + +if DISPLAY + +if LVGL + +config LV_Z_VDB_SIZE + default 64 + +config LV_Z_BITS_PER_PIXEL + default 24 + +choice LV_COLOR_DEPTH + default LV_COLOR_DEPTH_32 +endchoice + +config INPUT + default y + +endif # LVGL + +endif # DISPLAY + +endif # SHIELD_ADAFRUIT_2_4_TFT diff --git a/boards/shields/adafruit_2_4_tft/Kconfig.shield b/boards/shields/adafruit_2_4_tft/Kconfig.shield new file mode 100644 index 000000000000..e1ea83a088e4 --- /dev/null +++ b/boards/shields/adafruit_2_4_tft/Kconfig.shield @@ -0,0 +1,6 @@ +# Copyright (c) 2026 Conclusive Engineering +# Copyright (c) 2026 Texas Instruments +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_ADAFRUIT_2_4_TFT + def_bool $(shields_list_contains,adafruit_2_4_tft) diff --git a/boards/shields/adafruit_2_4_tft/adafruit_2_4_tft.overlay b/boards/shields/adafruit_2_4_tft/adafruit_2_4_tft.overlay new file mode 100644 index 000000000000..9bd4b613f8c9 --- /dev/null +++ b/boards/shields/adafruit_2_4_tft/adafruit_2_4_tft.overlay @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2026 Conclusive Engineering + * Copyright (c) 2026 Texas Instruments + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "adafruit_2_4_tft.dtsi" diff --git a/boards/shields/adafruit_2_4_tft/boards/lp_em_cc35x1_cc3551e.overlay b/boards/shields/adafruit_2_4_tft/boards/lp_em_cc35x1_cc3551e.overlay new file mode 100644 index 000000000000..ad78b9f31470 --- /dev/null +++ b/boards/shields/adafruit_2_4_tft/boards/lp_em_cc35x1_cc3551e.overlay @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2026 Conclusive Engineering + * Copyright (C) 2026 Texas Instruments + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "adafruit_2_4_tft.dtsi" + +display_spi: &spi0 { + status = "okay"; +}; + +&adafruit_2_4_tft_mipi_dbi { + spi-dev = <&display_spi>; + dc-gpios = <&gpios 31 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpios 17 GPIO_ACTIVE_LOW>; +}; diff --git a/boards/shields/adafruit_2_4_tft/doc/index.rst b/boards/shields/adafruit_2_4_tft/doc/index.rst new file mode 100644 index 000000000000..3679b035eeec --- /dev/null +++ b/boards/shields/adafruit_2_4_tft/doc/index.rst @@ -0,0 +1,81 @@ +.. _adafruit_2_4_tft_v2.1: + +Adafruit 2.8" TFT Shield v2.1 +################################# + +Overview +******** + +The Adafruit 2.4" TFT Shield with a +resolution of 320x240 pixels, is based on the ILI9341 controller. +This shield comes with a resistive (STMPE610 controller) +or capacitive (FT6206 controller) touchscreen. While the +Zephyr RTOS supports display output to these screens, +touchscreen input is supported only on Capacitive Touch version. +More information about the shield can be found at the `Adafruit 2.4" TFT +website `_. + + Adafruit 2.4" TFT (Credit: Adafruit) + +Pins Assignment of the Adafruit 2.4" TFT +======================================================== + ++-----------------------+---------------------------------------------+ +| Shield Connector Pin | Function | ++=======================+=============================================+ +| D4 | MicroSD SPI CSn | ++-----------------------+---------------------------------------------+ +| D9 | ILI9341 DC (Data/Command) | ++-----------------------+---------------------------------------------+ +| D10 | ILI9341 SPI CSn | ++-----------------------+---------------------------------------------+ +| D11 | SPI MOSI (Serial Data Input) | ++-----------------------+---------------------------------------------+ +| D12 | SPI MISO (Serial Data Out) | ++-----------------------+---------------------------------------------+ +| D13 | SPI SCK (Serial Clock Input) | ++-----------------------+---------------------------------------------+ + +TI BoosterHeader connector: ++-----------------------+--------------------------------------------+ +| BoosterHeader Pin | Function | ++=======================+===============+============================+ +| P4 | ST7789V Reset | | ++-----------------------+---------------+----------------------------+ +| P7 | SPI SCK | (Serial Clock Input) | ++-----------------------+---------------+----------------------------+ +| P14 | SPI MISO | (Serial Data Out) | ++-----------------------+---------------+----------------------------+ +| P15 | SPI MOSI | (Serial Data Input) | ++-----------------------+---------------+----------------------------+ +| P18 | SPI CS LCD | (LCD Chip Select) | ++-----------------------+---------------+----------------------------+ +| P30 | ILI9341 DC | (Data/Command) | ++-----------------------+---------------+----------------------------+ + + +.. note:: + Touch controller IRQ line is not connected by default. You will need to + solder the ``ICSP_SI1`` jumper to use it. You will also need to adjust + driver configuration and its Device Tree entry to make use of it. + +Requirements +************ + +This shield can only be used with a board which provides a configuration +for Arduino or Arduino Nano connectors and defines node aliases for SPI and +GPIO interfaces (see :ref:`shields` for more details). + +Programming +*********** + +Set ``--shield adafruit_2_4_tft`` when you invoke ``west build``. For example: + +.. zephyr-app-commands:: + :zephyr-app: samples/subsys/display/lvgl + :board: lp_em_cc35x1/cc3551e + :shield: adafruit_2_4_tft + :goals: build + +References +********** diff --git a/boards/shields/adafruit_2_4_tft/dts/adafruit_2_4_tft.dtsi b/boards/shields/adafruit_2_4_tft/dts/adafruit_2_4_tft.dtsi new file mode 100644 index 000000000000..ea79751096fa --- /dev/null +++ b/boards/shields/adafruit_2_4_tft/dts/adafruit_2_4_tft.dtsi @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2026 Conclusive Engineering + * Copyright (c) 2026 Texas Instruments + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + chosen { + zephyr,display = &adafruit_2_4_tft_ili9340; + }; + + adafruit_2_4_tft_mipi_dbi: adafruit_2_4_tft_mipi_dbi { + compatible = "zephyr,mipi-dbi-spi"; + spi-dev = <&arduino_spi>; + dc-gpios = <&arduino_header ARDUINO_HEADER_R3_D9 GPIO_ACTIVE_HIGH>; + reset-gpios = <&arduino_header ARDUINO_HEADER_R3_D8 GPIO_ACTIVE_LOW>; + write-only; + #address-cells = <1>; + #size-cells = <0>; + + adafruit_2_4_tft_ili9340: ili9340@0 { + compatible = "ilitek,ili9340"; + mipi-max-frequency = <15151515>; + reg = <0>; + width = <320>; + height = <240>; + pixel-format = ; + rotation = <90>; + frmctr1 = [00 18]; + pwctrl1 = [23 00]; + vmctrl1 = [3e 28]; + vmctrl2 = [86]; + pgamctrl = [0f 31 2b 0c 0e 08 4e f1 37 07 10 03 0e 09 00]; + ngamctrl = [00 0e 14 03 11 07 31 c1 48 08 0f 0c 31 36 0f]; + }; + }; +}; diff --git a/boards/shields/adafruit_2_4_tft/shield.yml b/boards/shields/adafruit_2_4_tft/shield.yml new file mode 100644 index 000000000000..0b232968f888 --- /dev/null +++ b/boards/shields/adafruit_2_4_tft/shield.yml @@ -0,0 +1,6 @@ +shields: + - name: adafruit_2_4_tft + full_name: Adafruit 2.4" TFT Shield + vendor: adafruit + supported_features: + - display diff --git a/boards/shields/st7789v_generic/Kconfig.defconfig b/boards/shields/st7789v_generic/Kconfig.defconfig index b28cf38f78cf..8e46c7b25943 100644 --- a/boards/shields/st7789v_generic/Kconfig.defconfig +++ b/boards/shields/st7789v_generic/Kconfig.defconfig @@ -1,13 +1,14 @@ # Copyright (c) 2019 Jan Van Winkel # SPDX-License-Identifier: Apache-2.0 -if SHIELD_ST7789V_TL019FQV01 || SHIELD_ST7789V_WAVESHARE_240X240 +if SHIELD_ST7789V_TL019FQV01 || SHIELD_ST7789V_WAVESHARE_240X240 || SHIELD_ST7789V_WAVESHARE_240X320 if DISPLAY choice ST7789V_PIXEL_FORMAT default ST7789V_RGB888 if SHIELD_ST7789V_TL019FQV01 default ST7789V_RGB565 if SHIELD_ST7789V_WAVESHARE_240X240 + default ST7789V_RGB565 if SHIELD_ST7789V_WAVESHARE_240X320 endchoice if LVGL @@ -15,16 +16,20 @@ if LVGL config LV_Z_BITS_PER_PIXEL default 24 if SHIELD_ST7789V_TL019FQV01 default 16 if SHIELD_ST7789V_WAVESHARE_240X240 + default 16 if SHIELD_ST7789V_WAVESHARE_240X320 choice LV_COLOR_DEPTH default LV_COLOR_DEPTH_16 if SHIELD_ST7789V_WAVESHARE_240X240 + default LV_COLOR_DEPTH_16 if SHIELD_ST7789V_WAVESHARE_240X320 endchoice configdefault LV_COLOR_16_SWAP default y if SHIELD_ST7789V_WAVESHARE_240X240 + default y if SHIELD_ST7789V_WAVESHARE_240X320 endif # LVGL endif # DISPLAY -endif # SHIELD_ST7789V_TL019FQV01 || SHIELD_ST7789V_WAVESHARE_240X240 +endif # SHIELD_ST7789V_TL019FQV01 || SHIELD_ST7789V_WAVESHARE_240X240 || +# SHIELD_ST7789V_WAVESHARE_240X320 diff --git a/boards/shields/st7789v_generic/Kconfig.shield b/boards/shields/st7789v_generic/Kconfig.shield index af7ee3da17f0..e9bc792cff17 100644 --- a/boards/shields/st7789v_generic/Kconfig.shield +++ b/boards/shields/st7789v_generic/Kconfig.shield @@ -6,3 +6,6 @@ config SHIELD_ST7789V_TL019FQV01 config SHIELD_ST7789V_WAVESHARE_240X240 def_bool $(shields_list_contains,st7789v_waveshare_240x240) + +config SHIELD_ST7789V_WAVESHARE_240X320 + def_bool $(shields_list_contains,st7789v_waveshare_240x320) diff --git a/boards/shields/st7789v_generic/doc/index.rst b/boards/shields/st7789v_generic/doc/index.rst index e6f92e63a7cb..53fcc97bfa99 100644 --- a/boards/shields/st7789v_generic/doc/index.rst +++ b/boards/shields/st7789v_generic/doc/index.rst @@ -16,6 +16,12 @@ Pins Assignment of the Generic ST7789V Display Shield +-----------------------+--------------------------------------------+ | Arduino Connector Pin | Function | +=======================+===============+============================+ +| D3 | TC IRQ | | ++-----------------------+---------------+----------------------------+ +| D5 | SPI CS SD | (SD Card Chip Select) | ++-----------------------+---------------+----------------------------+ +| D6 | SPI CS TC | (Touch Screen Chip Select) | ++-----------------------+---------------+----------------------------+ | D8 | ST7789V Reset | | +-----------------------+---------------+----------------------------+ | D9 | ST7789V DC | (Data/Command) | @@ -29,19 +35,46 @@ Pins Assignment of the Generic ST7789V Display Shield | D13 | SPI SCK | (Serial Clock Input) | +-----------------------+---------------+----------------------------+ +TI BoosterHeader connector: ++-----------------------+--------------------------------------------+ +| BoosterHeader Pin | Function | ++=======================+===============+============================+ +| P3 | SPI CS SD | (SD Card Chip Select) | ++-----------------------+---------------+----------------------------+ +| P4 | ST7789V Reset | | ++-----------------------+---------------+----------------------------+ +| P7 | SPI SCK | (Serial Clock Input) | ++-----------------------+---------------+----------------------------+ +| P14 | SPI MISO | (Serial Data Out) | ++-----------------------+---------------+----------------------------+ +| P15 | SPI MOSI | (Serial Data Input) | ++-----------------------+---------------+----------------------------+ +| P18 | SPI CS LCD | (LCD Chip Select) | ++-----------------------+---------------+----------------------------+ +| P30 | ST7789V DC | (Data/Command) | ++-----------------------+---------------+----------------------------+ +| P37 | SPI CS TC | (Touch Screen Chip Select) | ++-----------------------+---------------+----------------------------+ +| P38 | TC IRQ | (Touch Screen Interrupt) | ++-----------------------+---------------+----------------------------+ + + Current supported displays ========================== -+----------------------+------------------------------+ -| Display | Shield Designation | -| | | -+======================+==============================+ -| TL019FQV01 | st7789v_tl019fqv01 | -| | | -+----------------------+------------------------------+ -| Waveshare 240x240 | st7789v_waveshare_240x240 | -| 1.3inch IPS LCD | | -+----------------------+------------------------------+ ++--------------------------+------------------------------+ +| Display | Shield Designation | +| | | ++==========================+==============================+ +| TL019FQV01 | st7789v_tl019fqv01 | +| | | ++--------------------------+------------------------------+ +| Waveshare 240x240 | st7789v_waveshare_240x240 | +| 1.3inch IPS LCD | | ++--------------------------+------------------------------+ +| Waveshare 240x320 | st7789v_waveshare_240x320 | +| 2.8inch TFT TOUCH SCREEN | | ++--------------------------+------------------------------+ Requirements ************ diff --git a/boards/shields/st7789v_generic/shield.yml b/boards/shields/st7789v_generic/shield.yml index 69ff683fab93..6ebc7d43136f 100644 --- a/boards/shields/st7789v_generic/shield.yml +++ b/boards/shields/st7789v_generic/shield.yml @@ -10,3 +10,11 @@ shields: vendor: waveshare supported_features: - display + + - name: st7789v_waveshare_240x320 + full_name: Waveshare 240x320 2.8inch TFT Touch Screen + SD + vendor: waveshare + supported_features: + - display + - touch + - mmc diff --git a/boards/shields/st7789v_generic/st7789v_waveshare_240x320.overlay b/boards/shields/st7789v_generic/st7789v_waveshare_240x320.overlay new file mode 100644 index 000000000000..978b1c37787e --- /dev/null +++ b/boards/shields/st7789v_generic/st7789v_waveshare_240x320.overlay @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2026 Conclusive Engineering + * Copyright (c) 2026 Texas Instruments + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + chosen { + zephyr,display = &st7789v_st7789v_waveshare_240x320; + }; + + pointer { + compatible = "zephyr,lvgl-pointer-input"; + input = <&input_pointer>; + display = <&st7789v_st7789v_waveshare_240x320>; + invert-x; + invert-y; + }; + + mipi_dbi_st7789v_waveshare_240x320: mipi_dbi_st7789v_waveshare_240x320 { + compatible = "zephyr,mipi-dbi-spi"; + spi-dev = <&arduino_spi>; + dc-gpios = <&arduino_header ARDUINO_HEADER_R3_D9 GPIO_ACTIVE_HIGH>; + write-only; + #address-cells = <1>; + #size-cells = <0>; + + st7789v_st7789v_waveshare_240x320: st7789v@0 { + compatible = "sitronix,st7789v"; + mipi-max-frequency = <24000000>; + reg = <0>; + width = <240>; + height = <320>; + x-offset = <0>; + y-offset = <0>; + vcom = <0x28>; + gctrl = <0x35>; + vrhs = <0x0b>; + vdvs = <0x20>; + mdac = <0x00>; + gamma = <0x01>; + colmod = <0x55>; + lcm = <0x3c>; + + porch-param = [0c 0c 00 33 33]; + cmd2en-param = [5a 69 02 01]; + pwctrl1-param = [a4 a1]; + pvgam-param = [d0 01 08 0f 11 2a 36 55 44 3a 0b 06 11 20]; + nvgam-param = [d0 02 07 0a 0b 18 34 43 4a 2b 1b 1c 22 1f]; + ram-param = [00 f0]; + rgb-param = [cd 08 14]; + mipi-mode = "MIPI_DBI_MODE_SPI_4WIRE"; + }; + }; +}; + +arduino_spi: &spi0 { + status = "okay"; + + cs-gpios = <&arduino_header ARDUINO_HEADER_R3_D10 GPIO_ACTIVE_LOW>, + <&arduino_header ARDUINO_HEADER_R3_D5 GPIO_ACTIVE_LOW>, + <&arduino_header ARDUINO_HEADER_R3_D6 GPIO_ACTIVE_LOW>; + + sdhc_display: sdhc@1 { + compatible = "zephyr,sdhc-spi-slot"; + reg = <1>; + status = "okay"; + + mmc { + compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; + status = "okay"; + }; + + spi-max-frequency = <24000000>; + }; + + input_pointer: xpt2046@2 { + compatible = "xptek,xpt2046"; + spi-max-frequency = <2000000>; + reg = <0x2>; + int-gpios = <&arduino_header ARDUINO_HEADER_R3_D3 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <240>; + touchscreen-size-y = <320>; + reads = <5>; + min-x = <200>; + min-y = <200>; + max-x = <3800>; + max-y = <3800>; + }; +}; diff --git a/boards/ti/lp_em_cc2340r5/Kconfig b/boards/ti/lp_em_cc2340r5/Kconfig new file mode 100644 index 000000000000..2d268450fa61 --- /dev/null +++ b/boards/ti/lp_em_cc2340r5/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Texas Instruments Incorporated +# +# SPDX-License-Identifier: Apache-2.0 + +rsource "../lpf3_common/Kconfig" diff --git a/boards/ti/lp_em_cc2340r5/Kconfig.defconfig b/boards/ti/lp_em_cc2340r5/Kconfig.defconfig new file mode 100644 index 000000000000..8c25158e510f --- /dev/null +++ b/boards/ti/lp_em_cc2340r5/Kconfig.defconfig @@ -0,0 +1,28 @@ +# Copyright (c) 2024 Texas Instruments Incorporated +# +# SPDX-License-Identifier: Apache-2.0 + +rsource "../lpf3_common/Kconfig.defconfig" + +if BOARD_LP_EM_CC2340R5 + +if BT +config BT_LL_HEAP_SIZE + hex + default 0x1800 +endif # BT + +if PM +# Power Management requires increased idle task stack size because of +# stack usage introduced by "pm_state_set" +config IDLE_STACK_SIZE + default 320 +endif # PM + +# The SPI driver only supports DMA mode +if SPI +config SPI_CC23X0_CC27XX_DMA_DRIVEN + default y +endif # SPI + +endif # BOARD_LP_EM_CC2340R5 diff --git a/boards/ti/lp_em_cc2340r5/board.cmake b/boards/ti/lp_em_cc2340r5/board.cmake index aa471e86eab8..1a343b68f220 100644 --- a/boards/ti/lp_em_cc2340r5/board.cmake +++ b/boards/ti/lp_em_cc2340r5/board.cmake @@ -1,6 +1,10 @@ # Copyright (c) 2025 Fabian Pflug +# Copyright (c) 2026 Texas Instruments Incorporated # # SPDX-License-Identifier: Apache-2.0 board_runner_args(jlink "--device=CC2340R5" "--iface=swd") +board_runner_args(openocd --cmd-pre-init "source [find board/ti_lp_em_cc2340r5.cfg]") include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/ti_openocd.board.cmake) diff --git a/boards/ti/lp_em_cc2340r5/boosterpack_connector.dtsi b/boards/ti/lp_em_cc2340r5/boosterpack_connector.dtsi index 80c79f14abd5..d45a2111b8c2 100644 --- a/boards/ti/lp_em_cc2340r5/boosterpack_connector.dtsi +++ b/boards/ti/lp_em_cc2340r5/boosterpack_connector.dtsi @@ -11,6 +11,7 @@ #gpio-cells = <2>; gpio-map = <3 0 &gpio0 22 0>, <4 0 &gpio0 20 0>, + <5 0 &gpio0 4 0>, <7 0 &gpio0 18 0>, <8 0 &gpio0 3 0>, <9 0 &gpio0 24 0>, diff --git a/boards/ti/lp_em_cc2340r5/doc/img/lp_em_cc2340r5.jpg b/boards/ti/lp_em_cc2340r5/doc/img/lp_em_cc2340r5.jpg new file mode 100644 index 000000000000..42c55a9712ff Binary files /dev/null and b/boards/ti/lp_em_cc2340r5/doc/img/lp_em_cc2340r5.jpg differ diff --git a/boards/ti/lp_em_cc2340r5/lp_em_cc2340r5-pinctrl.dtsi b/boards/ti/lp_em_cc2340r5/lp_em_cc2340r5-pinctrl.dtsi index fc3f96bac90a..311c45dd78e0 100644 --- a/boards/ti/lp_em_cc2340r5/lp_em_cc2340r5-pinctrl.dtsi +++ b/boards/ti/lp_em_cc2340r5/lp_em_cc2340r5-pinctrl.dtsi @@ -16,32 +16,83 @@ uart0_rx_default: uart0_rx_default { pinmux = <22 DIO22_UART0_RXD>; + bias-pull-up; + input-enable; + }; + + uart0_rts_default: uart0_rts_default { + pinmux = <8 DIO8_UART0_RTS>; bias-disable; + }; + + uart0_cts_default: uart0_cts_default { + pinmux = <2 DIO2_UART0_CTS>; + bias-pull-up; input-enable; }; /* SPI0 */ spi0_sck_default: spi0_sck_default { pinmux = <18 DIO18_SPI0_SCLK>; + input-enable; + input-schmitt-enable; bias-disable; }; spi0_mosi_default: spi0_mosi_default { pinmux = <13 DIO13_SPI0_MOSI>; + input-enable; + input-schmitt-enable; bias-disable; }; spi0_miso_default: spi0_miso_default { pinmux = <12 DIO12_SPI0_MISO>; - bias-disable; input-enable; + input-schmitt-enable; + bias-disable; }; spi0_cs_default: spi0_cs_default { pinmux = <11 DIO11_SPI0_CSN>; + input-enable; + input-schmitt-enable; bias-disable; }; + spi0_sck_sleep: spi0_sck_sleep { + pinmux = <18 DIO18_GPIO18>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_mosi_sleep: spi0_mosi_sleep { + pinmux = <13 DIO13_GPIO13>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_miso_sleep: spi0_miso_sleep { + pinmux = <12 DIO12_GPIO12>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_cs_sleep: spi0_cs_sleep { + pinmux = <11 DIO11_GPIO11>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_flash_cs: spi0_flash_cs { + pinmux = <6 DIO6_GPIO6>; + bias-pull-up; + }; + /* ADC0 */ adc0_ch0: adc0_ch0 { pinmux = <7 DIO7_ADC0_AREFM>; @@ -111,6 +162,13 @@ bias-disable; }; + /* LGPT1 ch2 capture input (DIO6, T1_C2 PFUNC3) - BoosterPack pin 38 */ + pwm5_capture: lgpt1_chan2_capture { + pinmux = <6 DIO6_T1_C2>; + bias-disable; + input-enable; + }; + /* LGPT2 - PWM */ pwm6_default: lgpt2_chan0_default { pinmux = <15 DIO15_T2_C0N>; diff --git a/boards/ti/lp_em_cc2340r5/lp_em_cc2340r5.dts b/boards/ti/lp_em_cc2340r5/lp_em_cc2340r5.dts index 0618ff993ef0..e6c943798e54 100644 --- a/boards/ti/lp_em_cc2340r5/lp_em_cc2340r5.dts +++ b/boards/ti/lp_em_cc2340r5/lp_em_cc2340r5.dts @@ -15,7 +15,7 @@ #include / { - model = "LP_EM_CC2340R5"; + model = "TI CC2340R5 LaunchPad"; compatible = "ti,lp_em_cc2340r5"; chosen { @@ -24,6 +24,9 @@ zephyr,code-partition = &slot0_partition; zephyr,console = &uart0; zephyr,shell-uart = &uart0; + zephyr,bt_hci = &ti_bt_hci; + zephyr,bt-c2h-uart = &uart0; + zephyr,uart-mcumgr = &uart0; }; aliases { @@ -34,6 +37,9 @@ watchdog0 = &wdt0; pwm-led0 = &pwm_green; pwm-led1 = &pwm_red; + mcuboot-led0 = &led1; + mcuboot-button0 = &btn1; + rtc = &rtc0; }; leds { @@ -59,7 +65,7 @@ }; pwm_red: pwm_led_1 { - pwms = <&pwm5 0 1000 PWM_POLARITY_NORMAL>; + pwms = <&pwm5 2 1000 PWM_POLARITY_NORMAL>; label = "Red PWM LED"; }; }; @@ -83,6 +89,51 @@ lfxosc: lf_xosc { compatible = "ti,cc23x0-lf-xosc"; }; + + ti_bt_hci: ti_bt_hci { + compatible = "ti,bt-hci"; + status = "okay"; + }; +}; + +/delete-node/ &slot0_partition; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* 40 KiB (0xa000) for MCUboot */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x0000a000>; + }; + + /* 233472 Bytes (0x39000) per slot for application */ + slot0_partition: partition@a000 { + label = "image-0"; + reg = <0x0000a000 0x00039000>; + }; + + slot1_partition: partition@43000 { + label = "image-1"; + reg = <0x00043000 0x00039000>; + }; + + /* + * Storage partition will be used by NVS + * if enabled. + */ + storage_partition: partition@7c000 { + label = "storage"; + reg = <0x0007c000 0x00004000>; + }; + }; +}; + +&cpu0 { + clock-frequency = <48000000>; }; &gpio0 { @@ -110,7 +161,27 @@ &spi0_mosi_default &spi0_miso_default &spi0_cs_default>; - pinctrl-names = "default"; + pinctrl-1 = <&spi0_sck_sleep + &spi0_mosi_sleep + &spi0_miso_sleep + &spi0_cs_sleep>; + pinctrl-names = "default", "sleep"; + cs-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + + mx25r80: mx25r8035f@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <12000000>; + size = <0x800000>; + jedec-id = [c2 28 14]; + has-dpd; + dpd-wakeup-sequence = <30000 20 35000>; + t-enter-dpd = <10000>; + sfdp-bfp = [e5 20 f1 ff ff ff 7f 00 44 eb 08 6b 08 3b 04 bb + ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 + 10 d8 00 ff 23 72 f5 00 82 ed 04 b7 44 83 38 44 + 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff]; + }; }; &wdt0 { @@ -128,13 +199,18 @@ pinctrl-names = "default"; }; +&lgpt0 { + clk-prescale = <32>; + status = "okay"; +}; + &lgpt1 { - clk-prescale = <0>; + clk-prescale = <32>; status = "okay"; }; &lgpt2 { - clk-prescale = <0>; + clk-prescale = <32>; status = "okay"; }; @@ -157,3 +233,11 @@ clock-frequency = <100000>; pinctrl-names = "default"; }; + +&rtc0 { + status = "okay"; +}; + +&rng { + status = "okay"; +}; diff --git a/boards/ti/lp_em_cc2340r5/lp_em_cc2340r5.yaml b/boards/ti/lp_em_cc2340r5/lp_em_cc2340r5.yaml index 29cda9cc2399..94d4f234462c 100644 --- a/boards/ti/lp_em_cc2340r5/lp_em_cc2340r5.yaml +++ b/boards/ti/lp_em_cc2340r5/lp_em_cc2340r5.yaml @@ -2,7 +2,7 @@ identifier: lp_em_cc2340r5 name: TI SimpleLink CC2340R5 LaunchPad type: mcu arch: arm -ram: 80 +ram: 36 flash: 512 toolchain: - zephyr @@ -10,4 +10,21 @@ toolchain: supported: - gpio - uart + - adc + - counter + - pwm + - dma + - crypto + - spi + - watchdog + - rtc + - nvs + - pm + - entropy + - flash + - pinctrl + - serial + - timer + - i2c + - uart vendor: ti diff --git a/boards/ti/lp_em_cc2340r5/lp_em_cc2340r5_defconfig b/boards/ti/lp_em_cc2340r5/lp_em_cc2340r5_defconfig index 7f9b629c25f3..83b77b358bb3 100644 --- a/boards/ti/lp_em_cc2340r5/lp_em_cc2340r5_defconfig +++ b/boards/ti/lp_em_cc2340r5/lp_em_cc2340r5_defconfig @@ -1,4 +1,4 @@ -# Copyright (c) 2024 Texas Instruments Incorporated +# Copyright (c) 2025-2026 Texas Instruments Incorporated # Copyright (c) 2024 BayLibre, SAS # # SPDX-License-Identifier: Apache-2.0 @@ -8,3 +8,10 @@ CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y + +CONFIG_BT_HCI_ACL_FLOW_CONTROL=n + +CONFIG_PM=y + +CONFIG_MBEDTLS=y +CONFIG_MBEDTLS_PSA_CRYPTO_C=y diff --git a/boards/ti/lp_em_cc2340r53/Kconfig b/boards/ti/lp_em_cc2340r53/Kconfig new file mode 100644 index 000000000000..2d268450fa61 --- /dev/null +++ b/boards/ti/lp_em_cc2340r53/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Texas Instruments Incorporated +# +# SPDX-License-Identifier: Apache-2.0 + +rsource "../lpf3_common/Kconfig" diff --git a/boards/ti/lp_em_cc2340r53/Kconfig.defconfig b/boards/ti/lp_em_cc2340r53/Kconfig.defconfig new file mode 100644 index 000000000000..412f64de1ec5 --- /dev/null +++ b/boards/ti/lp_em_cc2340r53/Kconfig.defconfig @@ -0,0 +1,28 @@ +# Copyright (c) 2024 Texas Instruments Incorporated +# +# SPDX-License-Identifier: Apache-2.0 + +rsource "../lpf3_common/Kconfig.defconfig" + +if BOARD_LP_EM_CC2340R53 + +if BT +config BT_LL_HEAP_SIZE + hex + default 0x1880 +endif # BT + +if PM +# Power Management requires increased idle task stack size because of +# stack usage introduced by "pm_state_set" +config IDLE_STACK_SIZE + default 320 +endif # PM + +# The SPI driver only supports DMA mode +if SPI +config SPI_CC23X0_CC27XX_DMA_DRIVEN + default y +endif # SPI + +endif # BOARD_LP_EM_CC2340R53 diff --git a/boards/ti/lp_em_cc2340r53/Kconfig.lp_em_cc2340r53 b/boards/ti/lp_em_cc2340r53/Kconfig.lp_em_cc2340r53 new file mode 100644 index 000000000000..94855cb3ae59 --- /dev/null +++ b/boards/ti/lp_em_cc2340r53/Kconfig.lp_em_cc2340r53 @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Texas Instruments Incorporated +# Copyright (c) 2024 BayLibre, SAS +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LP_EM_CC2340R53 + select SOC_CC2340R53 diff --git a/boards/ti/lp_em_cc2340r53/board.cmake b/boards/ti/lp_em_cc2340r53/board.cmake new file mode 100644 index 000000000000..2202f2434008 --- /dev/null +++ b/boards/ti/lp_em_cc2340r53/board.cmake @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Texas Instruments Incorporated +# Copyright (c) 2024 BayLibre, SAS +# +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=CC2340R53") +board_runner_args(openocd --cmd-pre-init "source [find board/ti_lp_em_cc2340r53.cfg]") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/ti_openocd.board.cmake) diff --git a/boards/ti/lp_em_cc2340r53/board.yml b/boards/ti/lp_em_cc2340r53/board.yml new file mode 100644 index 000000000000..dddfa971da04 --- /dev/null +++ b/boards/ti/lp_em_cc2340r53/board.yml @@ -0,0 +1,6 @@ +board: + name: lp_em_cc2340r53 + full_name: CC2340R53 LaunchPad + vendor: ti + socs: + - name: cc2340r53 diff --git a/boards/ti/lp_em_cc2340r53/boosterpack_connector.dtsi b/boards/ti/lp_em_cc2340r53/boosterpack_connector.dtsi new file mode 100644 index 000000000000..d45a2111b8c2 --- /dev/null +++ b/boards/ti/lp_em_cc2340r53/boosterpack_connector.dtsi @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2024 Texas Instruments Incorporated + * Copyright (c) 2024 BayLibre, SAS + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + boosterpack_header: connector { + compatible = "ti,boosterpack-header"; + #gpio-cells = <2>; + gpio-map = <3 0 &gpio0 22 0>, + <4 0 &gpio0 20 0>, + <5 0 &gpio0 4 0>, + <7 0 &gpio0 18 0>, + <8 0 &gpio0 3 0>, + <9 0 &gpio0 24 0>, + <10 0 &gpio0 0 0>, + <12 0 &gpio0 9 0>, + <13 0 &gpio0 10 0>, + <14 0 &gpio0 12 0>, + <15 0 &gpio0 13 0>, + <17 0 &gpio0 19 0>, + <18 0 &gpio0 11 0>, + <23 0 &gpio0 23 0>, + <24 0 &gpio0 25 0>, + <25 0 &gpio0 1 0>, + <26 0 &gpio0 2 0>, + <27 0 &gpio0 5 0>, + <28 0 &gpio0 7 0>, + <36 0 &gpio0 8 0>, + <37 0 &gpio0 21 0>, + <38 0 &gpio0 6 0>, + <39 0 &gpio0 14 0>, + <40 0 &gpio0 15 0>; + }; +}; diff --git a/boards/ti/lp_em_cc2340r53/doc/img/lp_em_cc2340r53.jpg b/boards/ti/lp_em_cc2340r53/doc/img/lp_em_cc2340r53.jpg new file mode 100644 index 000000000000..42c55a9712ff Binary files /dev/null and b/boards/ti/lp_em_cc2340r53/doc/img/lp_em_cc2340r53.jpg differ diff --git a/boards/ti/lp_em_cc2340r53/doc/index.rst b/boards/ti/lp_em_cc2340r53/doc/index.rst new file mode 100644 index 000000000000..dae635d115af --- /dev/null +++ b/boards/ti/lp_em_cc2340r53/doc/index.rst @@ -0,0 +1,119 @@ +.. _lp_em_cc2340r53: + +TI CC2340R53 Launchpad +###################### + +Overview +******** + +The Texas Instruments CC2340R53 LaunchPad |trade| (LP_EM_CC2340R53) is a +development kit for the SimpleLink |trade| multi-Standard CC2340R53 wireless MCU. + +See the `TI CC2340R53 LaunchPad Product Page`_ for details. + +.. figure:: img/lp_em_cc2340r53.jpg + :align: center + :alt: TI CC2340R53 Launchpad + + Texas Instruments CC2340R53 LaunchPad |trade| + +Hardware +******** + +The CC2340R53 LaunchPad |trade| development kit features the CC2340R53 wireless MCU. +The board is equipped with two LEDs, two push buttons and BoosterPack connectors +for expansion. + +The CC2340R53 wireless MCU has a 48 MHz Arm |reg| Cortex |reg|-M0+ SoC and an +integrated 2.4 GHz transceiver supporting multiple protocols including Bluetooth +|reg| Low Energy and IEEE |reg| 802.15.4. + +See the `TI CC2340R53 Product Page`_ for additional details. + +Supported Features +================== + +The CC2340R53 LaunchPad board configuration supports the following hardware +features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. + +Connections and IOs +=================== + +All I/O signals are accessible from the BoosterPack connectors. Pin function +aligns with the LaunchPad standard. + ++-------+-----------+---------------------+ +| Pin | Function | Usage | ++=======+===========+=====================+ +| DIO0 | GPIO | | ++-------+-----------+---------------------+ +| DIO1 | ANALOG_IO | A4 | ++-------+-----------+---------------------+ +| DIO2 | ANALOG_IO | A3 | ++-------+-----------+---------------------+ +| DIO5 | ANALOG_IO | A5 | ++-------+-----------+---------------------+ +| DIO6 | SPI_CSN | SPI CS | ++-------+-----------+---------------------+ +| DIO7 | ANALOG_IO | A0 | ++-------+-----------+---------------------+ +| DIO8 | GPIO | | ++-------+-----------+---------------------+ +| DIO9 | GPIO | Button 2 | ++-------+-----------+---------------------+ +| DIO10 | GPIO | Button 1 | ++-------+-----------+---------------------+ +| DIO11 | SPI_CSN | SPI CS | ++-------+-----------+---------------------+ +| DIO12 | SPI_POCI | SPI POCI | ++-------+-----------+---------------------+ +| DIO13 | SPI_PICO | SPI_PICO | ++-------+-----------+---------------------+ +| DIO14 | GPIO | Red LED | ++-------+-----------+---------------------+ +| DIO15 | GPIO | Green LED | ++-------+-----------+---------------------+ +| DIO18 | SPI_CLK | SPI CLK | ++-------+-----------+---------------------+ +| DIO19 | GPIO | | ++-------+-----------+---------------------+ +| DIO20 | UART0_TX | UART TX | ++-------+-----------+---------------------+ +| DIO21 | GPIO | | ++-------+-----------+---------------------+ +| DIO22 | UART0_RX | UART RX | ++-------+-----------+---------------------+ +| DIO23 | ANALOG_IO | A8 | ++-------+-----------+---------------------+ +| DIO24 | ANALOG_IO | A7 | ++-------+-----------+---------------------+ + +Programming and Debugging +************************* + +The LP_EM_CC2340R53 requires an external debug probe such as the LP-XDS110 or +LP-XDS110ET. + +Currently there is no debug support in Zephyr for the LP_EM_CC2340R53, and the +built binaries for this target must be flashed/debugged using either Uniflash or +Code Composer Studio. + +References +********** + +CC2340R53 LaunchPad Quick Start Guide: + https://www.ti.com/lit/pdf/swru588 + +.. _TI CC2340R53 LaunchPad Product Page: + https://www.ti.com/tool/LP-EM-CC2340R5 + +.. _TI CC2340R53 Product Page: + https://www.ti.com/product/CC2340R5 diff --git a/boards/ti/lp_em_cc2340r53/lp_em_cc2340r53-pinctrl.dtsi b/boards/ti/lp_em_cc2340r53/lp_em_cc2340r53-pinctrl.dtsi new file mode 100644 index 000000000000..a9e55e9f1e45 --- /dev/null +++ b/boards/ti/lp_em_cc2340r53/lp_em_cc2340r53-pinctrl.dtsi @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2024 - 2026 Texas Instruments Incorporated + * Copyright (c) 2024 BayLibre, SAS + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + /* UART0 */ + uart0_tx_default: uart0_tx_default { + pinmux = <20 DIO20_UART0_TXD>; + bias-disable; + }; + + uart0_rx_default: uart0_rx_default { + pinmux = <22 DIO22_UART0_RXD>; + bias-pull-up; + input-enable; + }; + + uart0_rts_default: uart0_rts_default { + pinmux = <8 DIO8_UART0_RTS>; + bias-disable; + }; + + uart0_cts_default: uart0_cts_default { + pinmux = <2 DIO2_UART0_CTS>; + bias-pull-up; + input-enable; + }; + + /* SPI0 */ + spi0_sck_default: spi0_sck_default { + pinmux = <18 DIO18_SPI0_SCLK>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_mosi_default: spi0_mosi_default { + pinmux = <13 DIO13_SPI0_MOSI>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_miso_default: spi0_miso_default { + pinmux = <12 DIO12_SPI0_MISO>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_cs_default: spi0_cs_default { + pinmux = <6 DIO6_GPIO6>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_sck_sleep: spi0_sck_sleep { + pinmux = <18 DIO18_GPIO18>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_mosi_sleep: spi0_mosi_sleep { + pinmux = <13 DIO13_GPIO13>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_miso_sleep: spi0_miso_sleep { + pinmux = <12 DIO12_GPIO12>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_cs_sleep: spi0_cs_sleep { + pinmux = <6 DIO6_GPIO6>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_flash_cs: spi0_flash_cs { + pinmux = <6 DIO6_GPIO6>; + bias-pull-up; + }; + + /* ADC0 */ + adc0_ch0: adc0_ch0 { + pinmux = <7 DIO7_ADC0_AREFM>; + bias-disable; + input-enable; + }; + + adc0_ch2: adc0_ch2 { + pinmux = <5 DIO5_ADC2>; + bias-disable; + input-enable; + }; + + adc0_ch3: adc0_ch3 { + pinmux = <2 DIO2_ADC3>; + bias-disable; + input-enable; + }; + + adc0_ch4: adc0_ch4 { + pinmux = <1 DIO1_ADC4>; + bias-disable; + input-enable; + }; + + adc0_ch6: adc0_ch6 { + pinmux = <25 DIO25_ADC6>; + bias-disable; + input-enable; + }; + + adc0_ch8: adc0_ch8 { + pinmux = <23 DIO23_ADC8_LPCP_LPCM>; + bias-disable; + input-enable; + }; + + /* I2C0 */ + i2c0_scl_default: i2c0_scl_default { + pinmux = <24 DIO24_I2C0_SCL>; + bias-pull-up; + drive-open-drain; + input-enable; + }; + + i2c0_sda_default: i2c0_sda_default { + pinmux = <0 DIO0_I2C0_SDA>; + bias-pull-up; + drive-open-drain; + input-enable; + }; + + /* LGPT0 - PWM */ + pwm0_default: lgpt0_chan0_default { + pinmux = <8 DIO8_T0_C0N>; + bias-disable; + }; + + pwm1_default: lgpt0_chan1_default { + pinmux = <3 DIO3_T0_C1N>; + bias-disable; + }; + + pwm2_default: lgpt0_chan2_default { + pinmux = <4 DIO4_T0_C2N>; + bias-disable; + }; + + /* LGPT1 - PWM */ + pwm3_default: lgpt1_chan0_default { + pinmux = <16 DIO16_T1_C0N>; + bias-disable; + }; + + pwm4_default: lgpt1_chan1_default { + pinmux = <17 DIO17_T1_C1N>; + bias-disable; + }; + + pwm5_default: lgpt1_chan2_default { + pinmux = <14 DIO14_T1_C2N>; + bias-disable; + }; + + /* LGPT1 ch2 capture input (DIO6, T1_C2) */ + pwm5_capture: lgpt1_chan2_capture { + pinmux = <6 DIO6_T1_C2>; + bias-disable; + input-enable; + }; + + /* LGPT2 - PWM */ + pwm6_default: lgpt2_chan0_default { + pinmux = <15 DIO15_T2_C0N>; + bias-disable; + }; + + pwm7_default: lgpt2_chan1_default { + pinmux = <2 DIO2_T2_C1N>; + bias-disable; + }; + + pwm8_default: lgpt2_chan2_default { + pinmux = <25 DIO25_T2_C2N>; + bias-disable; + }; + + /* LGPT3 - PWM */ + pwm9_default: lgpt3_chan01_default { + pinmux = <10 DIO10_T3_C0N>; + bias-disable; + }; + + pwm10_default: lgpt3_chan1_default { + pinmux = <22 DIO22_T3_C1N>; + bias-disable; + }; + + pwm11_default: lgpt3_chan2_default { + pinmux = <23 DIO23_T3_C2N>; + bias-disable; + }; +}; diff --git a/boards/ti/lp_em_cc2340r53/lp_em_cc2340r53.dts b/boards/ti/lp_em_cc2340r53/lp_em_cc2340r53.dts new file mode 100644 index 000000000000..1ab1fb1d6700 --- /dev/null +++ b/boards/ti/lp_em_cc2340r53/lp_em_cc2340r53.dts @@ -0,0 +1,227 @@ +/* + * Copyright (c) 2024 Texas Instruments Incorporated + * Copyright (c) 2024 BayLibre, SAS + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "boosterpack_connector.dtsi" +#include "lp_em_cc2340r53-pinctrl.dtsi" +#include +#include +#include + +#define BTN_GPIO_FLAGS (GPIO_ACTIVE_LOW | GPIO_PULL_UP) + +/ { + model = "TI CC2340R53 LaunchPad"; + compatible = "ti,lp_em_cc2340r53"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,bt_hci = &ti_bt_hci; + zephyr,bt-c2h-uart = &uart0; + zephyr,code-partition = &slot0_partition; + zephyr,uart-mcumgr = &uart0; + }; + + aliases { + led0 = &led0; + led1 = &led1; + sw0 = &btn0; + sw1 = &btn1; + pwm-led0 = &pwm_green; + pwm-led1 = &pwm_red; + watchdog0 = &wdt0; + rtc = &rtc0; + mcuboot-led0 = &led1; + mcuboot-button0 = &btn1; + }; + + leds { + compatible = "gpio-leds"; + + led0: led_0 { + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; + label = "Green LED"; + }; + + led1: led_1 { + gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + label = "Red LED"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + pwm_green: pwm_led_0 { + pwms = <&pwm6 0 1000 PWM_POLARITY_NORMAL>; + label = "Green PWM LED"; + }; + + pwm_red: pwm_led_1 { + pwms = <&pwm5 2 1000 PWM_POLARITY_NORMAL>; + label = "Red PWM LED"; + }; + }; + + keys { + compatible = "gpio-keys"; + + btn0: btn_0 { + gpios = <&gpio0 10 BTN_GPIO_FLAGS>; + label = "Button 1"; + zephyr,code = ; + }; + + btn1: btn_1 { + gpios = <&gpio0 9 BTN_GPIO_FLAGS>; + label = "Button 2"; + zephyr,code = ; + }; + }; + + lfxosc: lf_xosc { + compatible = "ti,cc23x0-lf-xosc"; + }; + + ti_bt_hci: ti_bt_hci { + compatible = "ti,bt-hci"; + status = "okay"; + }; +}; + +/delete-node/ &slot0_partition; + +&flash0 { + partitions { + /* 40 KiB (0xa000) for MCUboot */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x0000a000>; + }; + + /* 233472 Bytes (0x39000) per slot for application */ + slot0_partition: partition@a000 { + label = "image-0"; + reg = <0x0000a000 0x00039000>; + }; + + slot1_partition: partition@43000 { + label = "image-1"; + reg = <0x00043000 0x00039000>; + }; + }; +}; + +&cpu0 { + clock-frequency = <48000000>; +}; + +&gpio0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_rx_default &uart0_tx_default>; + pinctrl-names = "default"; +}; + +&spi0 { + status = "okay"; + pinctrl-0 = <&spi0_sck_default + &spi0_mosi_default + &spi0_miso_default + &spi0_cs_default>; + pinctrl-1 = <&spi0_sck_sleep + &spi0_mosi_sleep + &spi0_miso_sleep + &spi0_cs_sleep>; + pinctrl-names = "default", "sleep"; + cs-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + + mx25r80: mx25r8035f@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <12000000>; + size = <0x800000>; + jedec-id = [c2 28 14]; + has-dpd; + dpd-wakeup-sequence = <30000 20 35000>; + t-enter-dpd = <10000>; + sfdp-bfp = [e5 20 f1 ff ff ff 7f 00 44 eb 08 6b 08 3b 04 bb + ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 + 10 d8 00 ff 23 72 f5 00 82 ed 04 b7 44 83 38 44 + 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff]; + }; +}; + +&i2c0 { + status = "okay"; + pinctrl-0 = <&i2c0_scl_default + &i2c0_sda_default>; + clock-frequency = <100000>; + pinctrl-names = "default"; +}; + +&aes { + status = "okay"; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_ch0 + &adc0_ch2 + &adc0_ch3 + &adc0_ch4 + &adc0_ch6 + &adc0_ch8>; + pinctrl-names = "default"; +}; + +&dma { + status = "okay"; +}; + +&lgpt1 { + clk-prescale = <0>; + status = "okay"; +}; + +&lgpt2 { + clk-prescale = <0>; + status = "okay"; +}; + +&pwm5 { + pinctrl-0 = <&pwm5_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pwm6 { + pinctrl-0 = <&pwm6_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&rtc0 { + status = "okay"; +}; + +&rng { + status = "okay"; +}; diff --git a/boards/ti/lp_em_cc2340r53/lp_em_cc2340r53.yaml b/boards/ti/lp_em_cc2340r53/lp_em_cc2340r53.yaml new file mode 100644 index 000000000000..f38fd2f8f8e3 --- /dev/null +++ b/boards/ti/lp_em_cc2340r53/lp_em_cc2340r53.yaml @@ -0,0 +1,30 @@ +identifier: lp_em_cc2340r53 +name: TI SimpleLink CC2340R53 LaunchPad +type: mcu +arch: arm +ram: 64 +flash: 512 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - adc + - counter + - pwm + - dma + - crypto + - spi + - watchdog + - rtc + - nvs + - pm + - entropy + - flash + - pinctrl + - serial + - timer + - i2c + - uart +vendor: ti diff --git a/boards/ti/lp_em_cc2340r53/lp_em_cc2340r53_defconfig b/boards/ti/lp_em_cc2340r53/lp_em_cc2340r53_defconfig new file mode 100644 index 000000000000..83b77b358bb3 --- /dev/null +++ b/boards/ti/lp_em_cc2340r53/lp_em_cc2340r53_defconfig @@ -0,0 +1,17 @@ +# Copyright (c) 2025-2026 Texas Instruments Incorporated +# Copyright (c) 2024 BayLibre, SAS +# +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_GPIO=y +CONFIG_SERIAL=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_BT_HCI_ACL_FLOW_CONTROL=n + +CONFIG_PM=y + +CONFIG_MBEDTLS=y +CONFIG_MBEDTLS_PSA_CRYPTO_C=y diff --git a/boards/ti/lp_em_cc2340r53_wcsp/Kconfig b/boards/ti/lp_em_cc2340r53_wcsp/Kconfig new file mode 100644 index 000000000000..188487967724 --- /dev/null +++ b/boards/ti/lp_em_cc2340r53_wcsp/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2026 Texas Instruments Incorporated +# +# SPDX-License-Identifier: Apache-2.0 + +rsource "../lpf3_common/Kconfig" diff --git a/boards/ti/lp_em_cc2340r53_wcsp/Kconfig.defconfig b/boards/ti/lp_em_cc2340r53_wcsp/Kconfig.defconfig new file mode 100644 index 000000000000..deeb96d709c9 --- /dev/null +++ b/boards/ti/lp_em_cc2340r53_wcsp/Kconfig.defconfig @@ -0,0 +1,28 @@ +# Copyright (c) 2026 Texas Instruments Incorporated +# +# SPDX-License-Identifier: Apache-2.0 + +rsource "../lpf3_common/Kconfig.defconfig" + +if BOARD_LP_EM_CC2340R53_WCSP + +if BT +config BT_LL_HEAP_SIZE + hex + default 0x1880 +endif # BT + +if PM +# Power Management requires increased idle task stack size because of +# stack usage introduced by "pm_state_set" +config IDLE_STACK_SIZE + default 320 +endif # PM + +# The SPI driver only supports DMA mode +if SPI +config SPI_CC23X0_CC27XX_DMA_DRIVEN + default y +endif # SPI + +endif # BOARD_LP_EM_CC2340R53_WCSP diff --git a/boards/ti/lp_em_cc2340r53_wcsp/Kconfig.lp_em_cc2340r53_wcsp b/boards/ti/lp_em_cc2340r53_wcsp/Kconfig.lp_em_cc2340r53_wcsp new file mode 100644 index 000000000000..adf596831090 --- /dev/null +++ b/boards/ti/lp_em_cc2340r53_wcsp/Kconfig.lp_em_cc2340r53_wcsp @@ -0,0 +1,7 @@ +# Copyright (c) 2026 Texas Instruments Incorporated +# Copyright (c) 2024 BayLibre, SAS +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LP_EM_CC2340R53_WCSP + select SOC_CC2340R53 diff --git a/boards/ti/lp_em_cc2340r53_wcsp/board.cmake b/boards/ti/lp_em_cc2340r53_wcsp/board.cmake new file mode 100644 index 000000000000..adc447006f24 --- /dev/null +++ b/boards/ti/lp_em_cc2340r53_wcsp/board.cmake @@ -0,0 +1,10 @@ +# Copyright (c) 2026 Texas Instruments Incorporated +# Copyright (c) 2024 BayLibre, SAS +# +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=CC2340R53") +board_runner_args(openocd --cmd-pre-init "source [find board/ti_lp_em_cc2340r53.cfg]") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/ti_openocd.board.cmake) diff --git a/boards/ti/lp_em_cc2340r53_wcsp/board.yml b/boards/ti/lp_em_cc2340r53_wcsp/board.yml new file mode 100644 index 000000000000..5444189e32aa --- /dev/null +++ b/boards/ti/lp_em_cc2340r53_wcsp/board.yml @@ -0,0 +1,6 @@ +board: + name: lp_em_cc2340r53_wcsp + full_name: CC2340R53 WCSP LaunchPad + vendor: ti + socs: + - name: cc2340r53 diff --git a/boards/ti/lp_em_cc2340r53_wcsp/boosterpack_connector.dtsi b/boards/ti/lp_em_cc2340r53_wcsp/boosterpack_connector.dtsi new file mode 100644 index 000000000000..6a0cfa4b3481 --- /dev/null +++ b/boards/ti/lp_em_cc2340r53_wcsp/boosterpack_connector.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2026 Texas Instruments Incorporated + * Copyright (c) 2024 BayLibre, SAS + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + boosterpack_header: connector { + compatible = "ti,boosterpack-header"; + #gpio-cells = <2>; + gpio-map = <3 0 &gpio0 20 0>, + <4 0 &gpio0 6 0>, + <12 0 &gpio0 24 0>, + <13 0 &gpio0 18 0>, + <15 0 &gpio0 12 0>, + <33 0 &gpio0 17 0>, + <34 0 &gpio0 16 0>, + <38 0 &gpio0 11 0>, + <39 0 &gpio0 21 0>, + <40 0 &gpio0 8 0>; + }; +}; diff --git a/boards/ti/lp_em_cc2340r53_wcsp/doc/index.rst b/boards/ti/lp_em_cc2340r53_wcsp/doc/index.rst new file mode 100644 index 000000000000..4883365c1e10 --- /dev/null +++ b/boards/ti/lp_em_cc2340r53_wcsp/doc/index.rst @@ -0,0 +1,133 @@ +.. _lp_em_cc2340r53_wcsp: + +TI CC2340R53 WCSP Launchpad +########################### + +Overview +******** + +The Texas Instruments CC2340R53 WCSP LaunchPad |trade| (LP_EM_CC2340R53_WCSP) is a +development kit featuring the CC2340R53 WCSP (Wafer-Level Chip Scale Package) +mounted on an LP_EM_CC2340R5 base board. + +See the `TI CC2340R53 LaunchPad Product Page`_ for details. + +Hardware +******** + +The CC2340R53 WCSP LaunchPad |trade| development kit features the CC2340R53 wireless MCU +in the YBG package variant. The board is equipped with two LEDs, two push buttons +and BoosterPack connectors for expansion. + +The CC2340R53 wireless MCU has a 48 MHz Arm |reg| Cortex |reg|-M0+ SoC and an +integrated 2.4 GHz transceiver supporting multiple protocols including Bluetooth +|reg| Low Energy and IEEE |reg| 802.15.4. + +See the `TI CC2340R53 Product Page`_ for additional details. + +Supported Features +================== + +The CC2340R53 WCSP LaunchPad board configuration supports the following hardware +features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| SPI | on-chip | spi | ++-----------+------------+----------------------+ +| I2C | on-chip | i2c | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| Watchdog | on-chip | watchdog | ++-----------+------------+----------------------+ +| Crypto | on-chip | crypto | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. + +Connections and IOs +=================== + +All I/O signals are accessible from the BoosterPack connectors. Pin function +aligns with the LaunchPad standard. + ++-------+-----------+---------------------+ +| Pin | Function | Usage | ++=======+===========+=====================+ +| DIO6 | UART0_TX | UART TX | ++-------+-----------+---------------------+ +| DIO8 | GPIO | Green LED / I2C SDA | ++-------+-----------+---------------------+ +| DIO11 | SPI_CSN | SPI CS | ++-------+-----------+---------------------+ +| DIO12 | SPI_PICO | SPI PICO | ++-------+-----------+---------------------+ +| DIO18 | SPI_CLK | SPI CLK / Button 1 | ++-------+-----------+---------------------+ +| DIO20 | UART0_RX | UART RX | ++-------+-----------+---------------------+ +| DIO21 | SPI_POCI | SPI POCI / Red LED | ++-------+-----------+---------------------+ +| DIO24 | GPIO | I2C SCL / Button 2 | ++-------+-----------+---------------------+ + +Shared PIN configuration +======================== + +Due to the limited pin count of the package, several peripheral functions +share pins with LEDs and buttons. By default, SPI and I2C are disabled in the +device tree to allow LEDs and buttons to function. + +SPI/I2C Pin Conflicts +--------------------- + +The following pins have multiple functions that conflict: + ++-------+-------------------------------------------+ +| Pin | Function | Jumper Required | ++=======+==================+========================+ +| DIO8 | Green LED | P2 pins 5-6 | ++-------+------------------+------------------------+ +| DIO8 | I2C SDA | P2 pins 3-5 | ++-------+------------------+------------------------+ +| DIO18 | SPI SCLK | P6 pins 3-5 | ++-------+------------------+------------------------+ +| DIO18 | Button 1 | P6 pins 5-6 | ++-------+------------------+------------------------+ +| DIO21 | Red LED | P2 pins 2-1 | ++-------+------------------+------------------------+ +| DIO21 | SPI POCI | P2 pins 2-4 | ++-------+------------------+------------------------+ +| DIO24 | Button 2 | P6 pins 2-1 | ++-------+------------------+------------------------+ +| DIO24 | I2C SCL | P6 pins 2-4 | ++-------+------------------+------------------------+ + +To enable SPI or I2C: + +1. Install the appropriate jumpers on headers P2 and P6 +2. Note that the corresponding LED or button will no longer function + +Programming and Debugging +************************* + +The LP_EM_CC2340R53_WCSP requires an external debug probe such as the LP-XDS110 or +LP-XDS110ET. + +References +********** + +CC2340R53 LaunchPad Quick Start Guide: + https://www.ti.com/lit/pdf/swru588 + +.. _TI CC2340R53 LaunchPad Product Page: + https://www.ti.com/tool/LP-EM-CC2340R5 + +.. _TI CC2340R53 Product Page: + https://www.ti.com/product/CC2340R5 diff --git a/boards/ti/lp_em_cc2340r53_wcsp/lp_em_cc2340r53_wcsp-pinctrl.dtsi b/boards/ti/lp_em_cc2340r53_wcsp/lp_em_cc2340r53_wcsp-pinctrl.dtsi new file mode 100644 index 000000000000..8bfcdd3d9ad8 --- /dev/null +++ b/boards/ti/lp_em_cc2340r53_wcsp/lp_em_cc2340r53_wcsp-pinctrl.dtsi @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2026 Texas Instruments Incorporated + * Copyright (c) 2024 BayLibre, SAS + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + /* UART0 */ + uart0_tx_default: uart0_tx_default { + pinmux = <6 DIO6_UART0_TXD>; + bias-disable; + }; + + uart0_rx_default: uart0_rx_default { + pinmux = <20 DIO20_UART0_RXD>; + bias-pull-up; + input-enable; + }; + + uart0_rts_default: uart0_rts_default { + pinmux = <8 DIO8_UART0_RTS>; + bias-disable; + }; + + uart0_cts_default: uart0_cts_default { + pinmux = <2 DIO2_UART0_CTS>; + bias-pull-up; + input-enable; + }; + + /* SPI0 */ + spi0_sck_default: spi0_sck_default { + pinmux = <18 DIO18_SPI0_SCLK>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_mosi_default: spi0_mosi_default { + pinmux = <12 DIO12_SPI0_MOSI>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_miso_default: spi0_miso_default { + pinmux = <21 DIO21_SPI0_MISO>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_cs_default: spi0_cs_default { + pinmux = <11 DIO11_GPIO11>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_sck_sleep: spi0_sck_sleep { + pinmux = <18 DIO18_GPIO18>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_mosi_sleep: spi0_mosi_sleep { + pinmux = <12 DIO12_GPIO12>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_miso_sleep: spi0_miso_sleep { + pinmux = <21 DIO21_GPIO21>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_cs_sleep: spi0_cs_sleep { + pinmux = <11 DIO11_GPIO11>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_flash_cs: spi0_flash_cs { + pinmux = <11 DIO11_GPIO11>; + bias-pull-up; + }; + + /* I2C0 */ + i2c0_scl_default: i2c0_scl_default { + pinmux = <24 DIO24_I2C0_SCL>; + bias-pull-up; + drive-open-drain; + input-enable; + }; + + i2c0_sda_default: i2c0_sda_default { + pinmux = <8 DIO8_I2C0_SDA>; + bias-pull-up; + drive-open-drain; + input-enable; + }; + + /* LGPT0 - PWM */ + pwm0_default: lgpt0_chan0_default { + pinmux = <8 DIO8_T0_C0N>; + bias-disable; + }; + + /* LGPT0 - PWM */ + pwm1_default: lgpt1_chan1_default { + pinmux = <21 DIO21_T1_C1N>; + bias-disable; + }; + + /* LGPT1 ch2 capture input (DIO16, T1_C2) */ + pwm5_capture: lgpt1_chan2_capture { + pinmux = <16 DIO16_T1_C2>; + bias-disable; + input-enable; + }; +}; diff --git a/boards/ti/lp_em_cc2340r53_wcsp/lp_em_cc2340r53_wcsp.dts b/boards/ti/lp_em_cc2340r53_wcsp/lp_em_cc2340r53_wcsp.dts new file mode 100644 index 000000000000..e5a0b65e640b --- /dev/null +++ b/boards/ti/lp_em_cc2340r53_wcsp/lp_em_cc2340r53_wcsp.dts @@ -0,0 +1,217 @@ +/* + * Copyright (c) 2026 Texas Instruments Incorporated + * Copyright (c) 2024 BayLibre, SAS + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "boosterpack_connector.dtsi" +#include "lp_em_cc2340r53_wcsp-pinctrl.dtsi" +#include +#include +#include + +#define BTN_GPIO_FLAGS (GPIO_ACTIVE_LOW | GPIO_PULL_UP) + +/ { + model = "TI CC2340R53 WCSP launchPad"; + compatible = "ti,lp_em_cc2340r53_wcsp"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,bt_hci = &ti_bt_hci; + zephyr,bt-c2h-uart = &uart0; + zephyr,code-partition = &slot0_partition; + zephyr,uart-mcumgr = &uart0; + }; + + aliases { + led0 = &led0; + led1 = &led1; + sw0 = &btn0; + sw1 = &btn1; + pwm-led0 = &pwm_green; + pwm-led1 = &pwm_red; + watchdog0 = &wdt0; + rtc = &rtc0; + mcuboot-led0 = &led1; + mcuboot-button0 = &btn1; + }; + + leds { + compatible = "gpio-leds"; + + led0: led_0 { + gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; + label = "Green LED"; + }; + + led1: led_1 { + gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; + label = "Red LED"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + pwm_green: pwm_led_0 { + pwms = <&pwm0 0 1000 PWM_POLARITY_NORMAL>; + label = "Green PWM LED"; + }; + + pwm_red: pwm_led_1 { + pwms = <&pwm1 0 1000 PWM_POLARITY_NORMAL>; + label = "Red PWM LED"; + }; + }; + + keys { + compatible = "gpio-keys"; + + btn0: btn_0 { + gpios = <&gpio0 18 BTN_GPIO_FLAGS>; + label = "Button 1"; + zephyr,code = ; + }; + + btn1: btn_1 { + gpios = <&gpio0 24 BTN_GPIO_FLAGS>; + label = "Button 2"; + zephyr,code = ; + }; + }; + + lfxosc: lf_xosc { + compatible = "ti,cc23x0-lf-xosc"; + }; + + ti_bt_hci: ti_bt_hci { + compatible = "ti,bt-hci"; + status = "okay"; + }; +}; + +/delete-node/ &slot0_partition; + +&flash0 { + partitions { + /* 40 KiB (0xa000) for MCUboot */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x0000a000>; + }; + + /* 233472 Bytes (0x39000) per slot for application */ + slot0_partition: partition@a000 { + label = "image-0"; + reg = <0x0000a000 0x00039000>; + }; + + slot1_partition: partition@43000 { + label = "image-1"; + reg = <0x00043000 0x00039000>; + }; + }; +}; + +&cpu0 { + clock-frequency = <48000000>; +}; + +&gpio0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_rx_default &uart0_tx_default>; + pinctrl-names = "default"; +}; + +&spi0 { + status = "disabled"; + pinctrl-0 = <&spi0_sck_default + &spi0_mosi_default + &spi0_miso_default + &spi0_cs_default>; + pinctrl-1 = <&spi0_sck_sleep + &spi0_mosi_sleep + &spi0_miso_sleep + &spi0_cs_sleep>; + pinctrl-names = "default", "sleep"; + cs-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; + + mx25r80: mx25r8035f@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + status = "disabled"; + spi-max-frequency = <12000000>; + size = <0x800000>; + jedec-id = [c2 28 14]; + has-dpd; + dpd-wakeup-sequence = <30000 20 35000>; + t-enter-dpd = <10000>; + sfdp-bfp = [e5 20 f1 ff ff ff 7f 00 44 eb 08 6b 08 3b 04 bb + ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 + 10 d8 00 ff 23 72 f5 00 82 ed 04 b7 44 83 38 44 + 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff]; + }; +}; + +&i2c0 { + status = "disabled"; + pinctrl-0 = <&i2c0_scl_default + &i2c0_sda_default>; + clock-frequency = <100000>; + pinctrl-names = "default"; +}; + +&aes { + status = "okay"; +}; + +&dma { + status = "okay"; +}; + +&lgpt0 { + clk-prescale = <32>; + status = "okay"; +}; + +&lgpt1 { + clk-prescale = <32>; + status = "okay"; +}; + +&pwm0 { + pinctrl-0 = <&pwm0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pwm1 { + pinctrl-0 = <&pwm1_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&rtc0 { + status = "okay"; +}; + +&rng { + status = "okay"; +}; diff --git a/boards/ti/lp_em_cc2340r53_wcsp/lp_em_cc2340r53_wcsp.yaml b/boards/ti/lp_em_cc2340r53_wcsp/lp_em_cc2340r53_wcsp.yaml new file mode 100644 index 000000000000..c81c3b773fcc --- /dev/null +++ b/boards/ti/lp_em_cc2340r53_wcsp/lp_em_cc2340r53_wcsp.yaml @@ -0,0 +1,29 @@ +identifier: lp_em_cc2340r53_wcsp +name: TI SimpleLink CC2340R53 WCSP on LP_EM_CC2340R5 +type: mcu +arch: arm +ram: 64 +flash: 512 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - counter + - pwm + - dma + - crypto + - spi + - watchdog + - rtc + - nvs + - pm + - entropy + - flash + - pinctrl + - serial + - timer + - i2c + - uart +vendor: ti diff --git a/boards/ti/lp_em_cc2340r53_wcsp/lp_em_cc2340r53_wcsp_defconfig b/boards/ti/lp_em_cc2340r53_wcsp/lp_em_cc2340r53_wcsp_defconfig new file mode 100644 index 000000000000..12f3a1dda58d --- /dev/null +++ b/boards/ti/lp_em_cc2340r53_wcsp/lp_em_cc2340r53_wcsp_defconfig @@ -0,0 +1,17 @@ +# Copyright (c) 2026 Texas Instruments Incorporated +# Copyright (c) 2024 BayLibre, SAS +# +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_GPIO=y +CONFIG_SERIAL=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_BT_HCI_ACL_FLOW_CONTROL=n + +CONFIG_PM=y + +CONFIG_MBEDTLS=y +CONFIG_MBEDTLS_PSA_CRYPTO_C=y diff --git a/boards/ti/lp_em_cc2340r5moda/Kconfig b/boards/ti/lp_em_cc2340r5moda/Kconfig new file mode 100644 index 000000000000..188487967724 --- /dev/null +++ b/boards/ti/lp_em_cc2340r5moda/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2026 Texas Instruments Incorporated +# +# SPDX-License-Identifier: Apache-2.0 + +rsource "../lpf3_common/Kconfig" diff --git a/boards/ti/lp_em_cc2340r5moda/Kconfig.defconfig b/boards/ti/lp_em_cc2340r5moda/Kconfig.defconfig new file mode 100644 index 000000000000..a9931594e3a1 --- /dev/null +++ b/boards/ti/lp_em_cc2340r5moda/Kconfig.defconfig @@ -0,0 +1,28 @@ +# Copyright (c) 2026 Texas Instruments Incorporated +# +# SPDX-License-Identifier: Apache-2.0 + +rsource "../lpf3_common/Kconfig.defconfig" + +if BOARD_LP_EM_CC2340R5MODA + +if BT +config BT_LL_HEAP_SIZE + hex + default 0x1880 +endif # BT + +if PM +# Power Management requires increased idle task stack size because of +# stack usage introduced by "pm_state_set" +config IDLE_STACK_SIZE + default 320 +endif # PM + +# The SPI driver only supports DMA mode +if SPI +config SPI_CC23X0_CC27XX_DMA_DRIVEN + default y +endif # SPI + +endif # BOARD_LP_EM_CC2340R5MODA diff --git a/boards/ti/lp_em_cc2340r5moda/Kconfig.lp_em_cc2340r5moda b/boards/ti/lp_em_cc2340r5moda/Kconfig.lp_em_cc2340r5moda new file mode 100644 index 000000000000..e18ff8531e71 --- /dev/null +++ b/boards/ti/lp_em_cc2340r5moda/Kconfig.lp_em_cc2340r5moda @@ -0,0 +1,6 @@ +# Copyright (c) 2026 Texas Instruments Incorporated +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LP_EM_CC2340R5MODA + select SOC_CC2340R53 diff --git a/boards/ti/lp_em_cc2340r5moda/board.cmake b/boards/ti/lp_em_cc2340r5moda/board.cmake new file mode 100644 index 000000000000..0538080c95b1 --- /dev/null +++ b/boards/ti/lp_em_cc2340r5moda/board.cmake @@ -0,0 +1,9 @@ +# Copyright (c) 2026 Texas Instruments Incorporated +# +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=CC2340R53") +board_runner_args(openocd --cmd-pre-init "source [find board/ti_lp_em_cc2340r53.cfg]") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/ti_openocd.board.cmake) diff --git a/boards/ti/lp_em_cc2340r5moda/board.yml b/boards/ti/lp_em_cc2340r5moda/board.yml new file mode 100644 index 000000000000..83c1fd4d42a5 --- /dev/null +++ b/boards/ti/lp_em_cc2340r5moda/board.yml @@ -0,0 +1,6 @@ +board: + name: lp_em_cc2340r5moda + full_name: CC2340R5MODA LaunchPad + vendor: ti + socs: + - name: cc2340r53 diff --git a/boards/ti/lp_em_cc2340r5moda/boosterpack_connector.dtsi b/boards/ti/lp_em_cc2340r5moda/boosterpack_connector.dtsi new file mode 100644 index 000000000000..1ac4e203ebe6 --- /dev/null +++ b/boards/ti/lp_em_cc2340r5moda/boosterpack_connector.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2026 Texas Instruments Incorporated + * Copyright (c) 2024 BayLibre, SAS + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + boosterpack_header: connector { + compatible = "ti,boosterpack-header"; + #gpio-cells = <2>; + gpio-map = <4 0 &gpio0 18 0>, + <6 0 &gpio0 12 0>, + <11 0 &gpio0 6 0>, + <12 0 &gpio0 24 0>, + <15 0 &gpio0 20 0>, + <23 0 &gpio0 11 0>, + <33 0 &gpio0 17 0>, + <34 0 &gpio0 16 0>, + <39 0 &gpio0 21 0>, + <40 0 &gpio0 8 0>; + }; +}; diff --git a/boards/ti/lp_em_cc2340r5moda/doc/index.rst b/boards/ti/lp_em_cc2340r5moda/doc/index.rst new file mode 100644 index 000000000000..4691d4fbabe6 --- /dev/null +++ b/boards/ti/lp_em_cc2340r5moda/doc/index.rst @@ -0,0 +1,131 @@ +.. _lp_em_cc2340r5moda: + +TI CC2340R5 Module LaunchPad +############################ + +Overview +******** + +The Texas Instruments CC2340R5 Module LaunchPad |trade| (LP_EM_CC2340R5MODA) is a +development kit for the SimpleLink |trade| CC2340R5 wireless module (MODA package). + +Hardware +******** + +The CC2340R5 Module LaunchPad |trade| development kit features the CC2340R5MODA +wireless module. The board is equipped with two LEDs, two push buttons and +BoosterPack connectors for expansion. Note that due to the module package, many +BoosterPack pins are not connected. + +The CC2340R5 wireless MCU has a 48 MHz Arm |reg| Cortex |reg|-M0+ SoC and an +integrated 2.4 GHz transceiver supporting multiple protocols including Bluetooth +|reg| Low Energy and IEEE |reg| 802.15.4. + +Supported Features +================== + +The CC2340R5 Module LaunchPad board configuration supports the following hardware +features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| SPI | on-chip | spi | ++-----------+------------+----------------------+ +| I2C | on-chip | i2c | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| Watchdog | on-chip | watchdog | ++-----------+------------+----------------------+ +| Crypto | on-chip | crypto | ++-----------+------------+----------------------+ + +Connections and IOs +=================== + +Pin assignments differ from the standard CC2340R5 LaunchPad due to the module +package. Many BoosterPack header pins are not connected. + ++-------+-----------+---------------------+ +| Pin | Function | Usage | ++=======+===========+=====================+ +| DIO3 | GPIO | | ++-------+-----------+---------------------+ +| DIO4 | GPIO | | ++-------+-----------+---------------------+ +| DIO6 | UART0_RX | UART TX | ++-------+-----------+---------------------+ +| DIO8 | GPIO/I2C | Green LED / I2C SDA | ++-------+-----------+---------------------+ +| DIO11 | SPI_CSN | SPI CS / Flash CS | ++-------+-----------+---------------------+ +| DIO12 | SPI_PICO | SPI PICO | ++-------+-----------+---------------------+ +| DIO18 | GPIO/SPI | Button 1 / SPI CLK | ++-------+-----------+---------------------+ +| DIO20 | UART0_TX | UART RX | ++-------+-----------+---------------------+ +| DIO21 | GPIO/SPI | Red LED / SPI POCI | ++-------+-----------+---------------------+ +| DIO24 | GPIO/I2C | Button 2 / I2C SCL | ++-------+-----------+---------------------+ + +Shared PIN configuration +======================== + +Due to the limited pin count of the module package, several peripheral functions +share pins with LEDs and buttons. By default, SPI and I2C are disabled in the +device tree to allow LEDs and buttons to function. + +SPI/I2C Pin Conflicts +--------------------- + +The following pins have multiple functions that conflict: + ++-------+-------------------------------------------+ +| Pin | Function | Jumper Required | ++=======+==================+========================+ +| DIO8 | Green LED | P2 pins 5-6 | ++-------+------------------+------------------------+ +| DIO8 | I2C SDA | P2 pins 3-5 | ++-------+------------------+------------------------+ +| DIO18 | SPI SCLK | P6 pins 3-5 | ++-------+------------------+------------------------+ +| DIO18 | Button 1 | P6 pins 5-6 | ++-------+------------------+------------------------+ +| DIO21 | Red LED | P2 pins 2-1 | ++-------+------------------+------------------------+ +| DIO21 | SPI POCI | P2 pins 2-4 | ++-------+------------------+------------------------+ +| DIO24 | Button 2 | P6 pins 2-1 | ++-------+------------------+------------------------+ +| DIO24 | I2C SCL | P6 pins 2-4 | ++-------+------------------+------------------------+ + +To enable SPI or I2C: + +1. Install the appropriate jumpers on headers P2 and P6 +2. Note that the corresponding LED or button will no longer function + +Programming and Debugging +************************* + +The LP_EM_CC2340R5MODA requires an external debug probe such as the LP-XDS110 or +LP-XDS110ET. + +References +********** + +CC2340R5 LaunchPad Quick Start Guide: + https://www.ti.com/lit/pdf/swru588 + +.. _TI CC2340R5 LaunchPad Product Page: + https://www.ti.com/tool/LP-EM-CC2340R5 + +.. _TI CC2340R5 Product Page: + https://www.ti.com/product/CC2340R5 diff --git a/boards/ti/lp_em_cc2340r5moda/lp_em_cc2340r5moda-pinctrl.dtsi b/boards/ti/lp_em_cc2340r5moda/lp_em_cc2340r5moda-pinctrl.dtsi new file mode 100644 index 000000000000..83cb30baa8ec --- /dev/null +++ b/boards/ti/lp_em_cc2340r5moda/lp_em_cc2340r5moda-pinctrl.dtsi @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2026 Texas Instruments Incorporated + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + /* UART0 */ + uart0_tx_default: uart0_tx_default { + pinmux = <6 DIO6_UART0_TXD>; + bias-disable; + }; + + uart0_rx_default: uart0_rx_default { + pinmux = <20 DIO20_UART0_RXD>; + bias-pull-up; + input-enable; + }; + + uart0_rts_default: uart0_rts_default { + pinmux = <8 DIO8_UART0_RTS>; + bias-disable; + }; + + uart0_cts_default: uart0_cts_default { + pinmux = <2 DIO2_UART0_CTS>; + bias-pull-up; + input-enable; + }; + + /* SPI0 */ + + /* SPI SCLK: Can be connected to DIO18 by connecting pins 3 and 5 on header P6 */ + spi0_sck_default: spi0_sck_default { + pinmux = <18 DIO18_SPI0_SCLK>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_mosi_default: spi0_mosi_default { + pinmux = <12 DIO12_SPI0_MOSI>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + /* SPI MISO: Can be connected to DIO21 by connecting pins 2 and 4 on header P2 */ + spi0_miso_default: spi0_miso_default { + pinmux = <21 DIO21_SPI0_MISO>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_cs_default: spi0_cs_default { + pinmux = <11 DIO11_GPIO11>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_sck_sleep: spi0_sck_sleep { + pinmux = <18 DIO18_GPIO18>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_mosi_sleep: spi0_mosi_sleep { + pinmux = <12 DIO12_GPIO12>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_miso_sleep: spi0_miso_sleep { + pinmux = <21 DIO21_GPIO21>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_cs_sleep: spi0_cs_sleep { + pinmux = <11 DIO11_GPIO11>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_flash_cs: spi0_flash_cs { + pinmux = <11 DIO11_GPIO11>; + bias-pull-up; + }; + + /* I2C0 */ + + /* I2C SCL: Can be connected to DIO24 by connecting pins 2 and 4 on header P6 */ + i2c0_scl_default: i2c0_scl_default { + pinmux = <24 DIO24_I2C0_SCL>; + bias-pull-up; + drive-open-drain; + input-enable; + }; + + /* I2C SDA: Can be connected to DIO8 by connecting pins 3 and 5 on header P2 */ + i2c0_sda_default: i2c0_sda_default { + pinmux = <8 DIO8_I2C0_SDA>; + bias-pull-up; + drive-open-drain; + input-enable; + }; + + /* LGPT0 - PWM */ + pwm0_default: lgpt0_chan0_default { + pinmux = <8 DIO8_T0_C0N>; + bias-disable; + }; + + /* LGPT0 - PWM */ + pwm1_default: lgpt1_chan1_default { + pinmux = <21 DIO21_T1_C1N>; + bias-disable; + }; + + /* LGPT1 ch2 capture input for PWM loopback test (DIO16, T1_C2) */ + pwm5_capture: lgpt1_chan2_capture { + pinmux = <16 DIO16_T1_C2>; + bias-disable; + input-enable; + }; +}; diff --git a/boards/ti/lp_em_cc2340r5moda/lp_em_cc2340r5moda.dts b/boards/ti/lp_em_cc2340r5moda/lp_em_cc2340r5moda.dts new file mode 100644 index 000000000000..af9e825faf92 --- /dev/null +++ b/boards/ti/lp_em_cc2340r5moda/lp_em_cc2340r5moda.dts @@ -0,0 +1,216 @@ +/* + * Copyright (c) 2026 Texas Instruments Incorporated + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "boosterpack_connector.dtsi" +#include "lp_em_cc2340r5moda-pinctrl.dtsi" +#include +#include +#include + +#define BTN_GPIO_FLAGS (GPIO_ACTIVE_LOW | GPIO_PULL_UP) + +/ { + model = "TI CC2340R5MODA launchpad"; + compatible = "ti,lp_em_cc2340r5moda"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,bt_hci = &ti_bt_hci; + zephyr,bt-c2h-uart = &uart0; + zephyr,code-partition = &slot0_partition; + zephyr,uart-mcumgr = &uart0; + }; + + aliases { + led0 = &led0; + led1 = &led1; + sw0 = &btn0; + sw1 = &btn1; + pwm-led0 = &pwm_green; + pwm-led1 = &pwm_red; + watchdog0 = &wdt0; + rtc = &rtc0; + mcuboot-led0 = &led1; + mcuboot-button0 = &btn1; + }; + + leds { + compatible = "gpio-leds"; + + led0: led_0 { + gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; + label = "Green LED"; + }; + + led1: led_1 { + gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; + label = "Red LED"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + pwm_green: pwm_led_0 { + pwms = <&pwm0 0 1000 PWM_POLARITY_NORMAL>; + label = "Green PWM LED"; + }; + + pwm_red: pwm_led_1 { + pwms = <&pwm1 0 1000 PWM_POLARITY_NORMAL>; + label = "Red PWM LED"; + }; + }; + + keys { + compatible = "gpio-keys"; + + btn0: btn_0 { + gpios = <&gpio0 18 BTN_GPIO_FLAGS>; + label = "Button 1"; + zephyr,code = ; + }; + + btn1: btn_1 { + gpios = <&gpio0 24 BTN_GPIO_FLAGS>; + label = "Button 2"; + zephyr,code = ; + }; + }; + + lfxosc: lf_xosc { + compatible = "ti,cc23x0-lf-xosc"; + }; + + ti_bt_hci: ti_bt_hci { + compatible = "ti,bt-hci"; + status = "okay"; + }; +}; + +/delete-node/ &slot0_partition; + +&flash0 { + partitions { + /* 40 KiB (0xa000) for MCUboot */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x0000a000>; + }; + + /* 233472 Bytes (0x39000) per slot for application */ + slot0_partition: partition@a000 { + label = "image-0"; + reg = <0x0000a000 0x00039000>; + }; + + slot1_partition: partition@43000 { + label = "image-1"; + reg = <0x00043000 0x00039000>; + }; + }; +}; + +&cpu0 { + clock-frequency = <48000000>; +}; + +&gpio0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_rx_default &uart0_tx_default>; + pinctrl-names = "default"; +}; + +&spi0 { + status = "disabled"; + pinctrl-0 = <&spi0_sck_default + &spi0_mosi_default + &spi0_miso_default + &spi0_cs_default>; + pinctrl-1 = <&spi0_sck_sleep + &spi0_mosi_sleep + &spi0_miso_sleep + &spi0_cs_sleep>; + pinctrl-names = "default", "sleep"; + cs-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; + + mx25r80: mx25r8035f@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + status = "disabled"; + spi-max-frequency = <12000000>; + size = <0x800000>; + jedec-id = [c2 28 14]; + has-dpd; + dpd-wakeup-sequence = <30000 20 35000>; + t-enter-dpd = <10000>; + sfdp-bfp = [e5 20 f1 ff ff ff 7f 00 44 eb 08 6b 08 3b 04 bb + ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 + 10 d8 00 ff 23 72 f5 00 82 ed 04 b7 44 83 38 44 + 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff]; + }; +}; + +&i2c0 { + status = "disabled"; + pinctrl-0 = <&i2c0_scl_default + &i2c0_sda_default>; + clock-frequency = <100000>; + pinctrl-names = "default"; +}; + +&aes { + status = "okay"; +}; + +&dma { + status = "okay"; +}; + +&lgpt0 { + clk-prescale = <32>; + status = "okay"; +}; + +&lgpt1 { + clk-prescale = <32>; + status = "okay"; +}; + +&pwm0 { + pinctrl-0 = <&pwm0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pwm1 { + pinctrl-0 = <&pwm1_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&rtc0 { + status = "okay"; +}; + +&rng { + status = "okay"; +}; diff --git a/boards/ti/lp_em_cc2340r5moda/lp_em_cc2340r5moda.yaml b/boards/ti/lp_em_cc2340r5moda/lp_em_cc2340r5moda.yaml new file mode 100644 index 000000000000..617fc2830e02 --- /dev/null +++ b/boards/ti/lp_em_cc2340r5moda/lp_em_cc2340r5moda.yaml @@ -0,0 +1,30 @@ +identifier: lp_em_cc2340r5moda +name: TI SimpleLink CC2340R5 Module LaunchPad +type: mcu +arch: arm +ram: 64 +flash: 512 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - adc + - gpio + - pwm + - counter + - dma + - crypto + - spi + - watchdog + - rtc + - nvs + - pm + - entropy + - flash + - pinctrl + - serial + - timer + - i2c + - uart +vendor: ti diff --git a/boards/ti/lp_em_cc2340r5moda/lp_em_cc2340r5moda_defconfig b/boards/ti/lp_em_cc2340r5moda/lp_em_cc2340r5moda_defconfig new file mode 100644 index 000000000000..f1b986d3816a --- /dev/null +++ b/boards/ti/lp_em_cc2340r5moda/lp_em_cc2340r5moda_defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2026 Texas Instruments Incorporated +# +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_GPIO=y +CONFIG_SERIAL=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_BT_HCI_ACL_FLOW_CONTROL=n + +CONFIG_PM=y + +CONFIG_MBEDTLS=y +CONFIG_MBEDTLS_PSA_CRYPTO_C=y diff --git a/boards/ti/lp_em_cc2745r10_q1/Kconfig b/boards/ti/lp_em_cc2745r10_q1/Kconfig new file mode 100644 index 000000000000..4ca8866b93a0 --- /dev/null +++ b/boards/ti/lp_em_cc2745r10_q1/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Texas Instruments Incorporated +# +# SPDX-License-Identifier: Apache-2.0 + +rsource "../lpf3_common/Kconfig" diff --git a/boards/ti/lp_em_cc2745r10_q1/Kconfig.defconfig b/boards/ti/lp_em_cc2745r10_q1/Kconfig.defconfig new file mode 100644 index 000000000000..c762270c7c64 --- /dev/null +++ b/boards/ti/lp_em_cc2745r10_q1/Kconfig.defconfig @@ -0,0 +1,28 @@ +# Copyright (c) 2025 Texas Instruments Incorporated +# +# SPDX-License-Identifier: Apache-2.0 + +rsource "../lpf3_common/Kconfig.defconfig" + +if BOARD_LP_EM_CC2745R10_Q1 + +if BT +config BT_LL_HEAP_SIZE + hex + default 0x4E00 +endif # BT + +if PM +# Power Management requires increased idle task stack size because of +# stack usage introduced by "pm_state_set" +config IDLE_STACK_SIZE + default 320 +endif # PM + +# The SPI driver only supports DMA mode +if SPI +config SPI_CC23X0_CC27XX_DMA_DRIVEN + default y +endif # SPI + +endif # BOARD_LP_EM_CC2745R10_Q1 diff --git a/boards/ti/lp_em_cc2745r10_q1/Kconfig.lp_em_cc2745r10_q1 b/boards/ti/lp_em_cc2745r10_q1/Kconfig.lp_em_cc2745r10_q1 new file mode 100644 index 000000000000..2bf5fbc170a1 --- /dev/null +++ b/boards/ti/lp_em_cc2745r10_q1/Kconfig.lp_em_cc2745r10_q1 @@ -0,0 +1,8 @@ +# Copyright (c) 2025-2026 Texas Instruments Incorporated +# Copyright (c) 2024 BayLibre, SAS +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LP_EM_CC2745R10_Q1 + select SOC_CC2745R10_Q1 if BOARD_LP_EM_CC2745R10_Q1_CC2745R10_Q1 + select SOC_CC2755R10 if BOARD_LP_EM_CC2745R10_Q1_CC2755R10 diff --git a/boards/ti/lp_em_cc2745r10_q1/board.cmake b/boards/ti/lp_em_cc2745r10_q1/board.cmake new file mode 100644 index 000000000000..eb60909996fc --- /dev/null +++ b/boards/ti/lp_em_cc2745r10_q1/board.cmake @@ -0,0 +1,10 @@ +# Copyright (c) 2025 Texas Instruments Incorporated +# Copyright (c) 2024 BayLibre, SAS +# +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=CC2745R10-Q1") +board_runner_args(openocd --cmd-pre-init "source [find board/ti_lp_em_cc2745r10.cfg]") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/ti_openocd.board.cmake) diff --git a/boards/ti/lp_em_cc2745r10_q1/board.yml b/boards/ti/lp_em_cc2745r10_q1/board.yml new file mode 100644 index 000000000000..206b70819af2 --- /dev/null +++ b/boards/ti/lp_em_cc2745r10_q1/board.yml @@ -0,0 +1,7 @@ +board: + name: lp_em_cc2745r10_q1 + full_name: CC2745R10-Q1 LaunchPad + vendor: ti + socs: + - name: cc2745r10_q1 + - name: cc2755r10 diff --git a/boards/ti/lp_em_cc2745r10_q1/boosterpack_connector.dtsi b/boards/ti/lp_em_cc2745r10_q1/boosterpack_connector.dtsi new file mode 100644 index 000000000000..5e11513ca99a --- /dev/null +++ b/boards/ti/lp_em_cc2745r10_q1/boosterpack_connector.dtsi @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2025 Texas Instruments Incorporated + * Copyright (c) 2024 BayLibre, SAS + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + boosterpack_header: connector { + compatible = "ti,boosterpack-header"; + #gpio-cells = <2>; + gpio-map = <2 0 &gpio0 21 0>, + <3 0 &gpio0 2 0>, + <4 0 &gpio0 1 0>, + <5 0 &gpio0 23 0>, + <6 0 &gpio0 22 0>, + <7 0 &gpio0 3 0>, + <8 0 &gpio0 24 0>, + <9 0 &gpio0 27 0>, + <10 0 &gpio0 28 0>, + <14 0 &gpio0 4 0>, + <15 0 &gpio0 5 0>, + <18 0 &gpio0 7 0>, + <19 0 &gpio0 12 0>, + <27 0 &gpio0 18 0>, + <28 0 &gpio0 17 0>, + <29 0 &gpio0 19 0>, + <30 0 &gpio0 20 0>, + <31 0 &gpio0 18 0>, + <32 0 &gpio0 17 0>, + <33 0 &gpio0 10 0>, + <34 0 &gpio0 9 0>, + <35 0 &gpio0 15 0>, + <36 0 &gpio0 16 0>, + <38 0 &gpio0 19 0>, + <39 0 &gpio0 11 0>, + <40 0 &gpio0 0 0>; + }; +}; diff --git a/boards/ti/lp_em_cc2745r10_q1/doc/img/lp_em_cc2745r10_q1.jpg b/boards/ti/lp_em_cc2745r10_q1/doc/img/lp_em_cc2745r10_q1.jpg new file mode 100644 index 000000000000..eb7b9795d1db Binary files /dev/null and b/boards/ti/lp_em_cc2745r10_q1/doc/img/lp_em_cc2745r10_q1.jpg differ diff --git a/boards/ti/lp_em_cc2745r10_q1/doc/index.rst b/boards/ti/lp_em_cc2745r10_q1/doc/index.rst new file mode 100644 index 000000000000..6b1fc92e682c --- /dev/null +++ b/boards/ti/lp_em_cc2745r10_q1/doc/index.rst @@ -0,0 +1,134 @@ +.. _lp_em_cc2745r10_q1: + +TI CC2745R10_Q1 Launchpad +######################### + +Overview +******** + +The Texas Instruments CC2745R10_Q1 LaunchPad |trade| (LP_EM_CC2745R10_Q1) is a +development kit for the SimpleLink |trade| multi-Standard CC2745R10_Q1 wireless MCU. + +See the `TI CC2745R10_Q1 LaunchPad Product Page`_ for details. + +.. figure:: img/lp_em_cc2745r10_q1.jpg + :align: center + :alt: TI CC2745R10_Q1 Launchpad + + Texas Instruments Cc2745r10_q1 LaunchPad |trade| + +Hardware +******** + +The CC2745R10_Q1 LaunchPad |trade| development kit features the CC2745R10_Q1 wireless MCU. +The board is equipped with two LEDs, two push buttons and BoosterPack connectors +for expansion. + +The board also supports the CC2755R10 device, and is available in two configurations: + +- The ``lp_em_cc2745r10_q1/cc2745r10_q1`` configuration should be the default one, and will + build for the CC2745R10_Q1 SoC. + +- The ``lp_em_cc2745r10_q1/cc2755r10`` configuration should be used if a CC2755R10 device + is mounted on the board instead. + +The CC2745R10_Q1 wireless MCU has a 96 MHz Arm |reg| Cortex |reg|-M33 SoC and an +integrated 2.4 GHz transceiver supporting multiple protocols including Bluetooth +|reg| Low Energy and IEEE |reg| 802.15.4. + +The CC2755R10 wireless MCU supports additional protocols such as Matter, Thread, and Zigbee + +See the `TI CC2745R10_Q1 Product Page`_ and `TI CC2755R10 Product Page`_ for additional details. + +Supported Features +================== + +The CC2745R10_Q1 LaunchPad board configuration supports the following hardware +features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| UART | on-chip | uart | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. + +Connections and IOs +=================== + +All I/O signals are accessible from the BoosterPack connectors. Pin function +aligns with the LaunchPad standard. + ++-------+-----------+-------------------------+ +| Pin | Function | Usage | ++=======+===========+=========================+ +| DIO0 | GPIO | Button 2 | ++-------+-----------+-------------------------+ +| DIO1 | UART_TX | UART TX | ++-------+-----------+-------------------------+ +| DIO2 | UART_RX | UART RX | ++-------+-----------+-------------------------+ +| DIO3 | SPI_CLK | SPI CLK | ++-------+-----------+-------------------------+ +| DIO4 | SPI_POCI | SPI POCI | ++-------+-----------+-------------------------+ +| DIO5 | SPI_PICO | SPI PICO | ++-------+-----------+-------------------------+ +| DIO7 | SPI_CSN | SPI CS | ++-------+-----------+-------------------------+ +| DIO9 | SWD_IO | SWD IO | ++-------+-----------+-------------------------+ +| DIO10 | SWD_CK | SWD CK | ++-------+-----------+-------------------------+ +| DIO11 | GPIO | | ++-------+-----------+-------------------------+ +| DIO12 | GPIO | Green LED | ++-------+-----------+-------------------------+ +| DIO16 | GPIO | RED LED | ++-------+-----------+-------------------------+ +| DIO17 | ANALOG_IO | CAN TX / A8 | ++-------+-----------+-------------------------+ +| DIO18 | ANALOG_IO | CAN RX / A7 | ++-------+-----------+-------------------------+ +| DIO19 | ANALOG_IO | I2S SDO / A6 | ++-------+-----------+-------------------------+ +| DIO20 | ANALOG_IO | I2C SDI / A5 / Button 1 | ++-------+-----------+-------------------------+ +| DIO21 | ANALOG_IO | A4 | ++-------+-----------+-------------------------+ +| DIO22 | ANALOG_IO | A3 | ++-------+-----------+-------------------------+ +| DIO23 | GPIO | | ++-------+-----------+-------------------------+ +| DIO24 | GPIO | | ++-------+-----------+-------------------------+ +| DIO27 | I2C_SCL | I2C SCL | ++-------+-----------+-------------------------+ +| DIO28 | I2C_SDA | I2C SDA | ++-------+-----------+-------------------------+ + +Programming and Debugging +************************* + +The LP_EM_CC2745R10_Q1 requires an external debug probe such as the LP-XDS110 or +LP-XDS110ET. + +Currently there is no debug support in Zephyr for the LP_EM_Cc2745r10_q1, and the +built binaries for this target must be flashed/debugged using either Uniflash or +Code Composer Studio. + +References +********** + +.. _TI CC2745R10_Q1 LaunchPad Quick Start Guide: + https://www.ti.com/lit/ug/swru635/swru635.pdf +.. _TI CC2745R10_Q1 LaunchPad Product Page: + https://www.ti.com/tool/LP-EM-CC2745R10-Q1 + +.. _TI CC2745R10_Q1 Product Page: + https://www.ti.com/product/CC2745R10-Q1 +.. _TI CC2755R10 Product Page: + https://www.ti.com/product/CC2755R10 diff --git a/boards/ti/lp_em_cc2745r10_q1/lp_em_cc2745r10_q1_cc2745r10_q1-pinctrl.dtsi b/boards/ti/lp_em_cc2745r10_q1/lp_em_cc2745r10_q1_cc2745r10_q1-pinctrl.dtsi new file mode 100644 index 000000000000..fa7c7f16f595 --- /dev/null +++ b/boards/ti/lp_em_cc2745r10_q1/lp_em_cc2745r10_q1_cc2745r10_q1-pinctrl.dtsi @@ -0,0 +1,278 @@ +/* + * Copyright (c) 2025 - 2026 Texas Instruments Incorporated + * Copyright (c) 2024 BayLibre, SAS + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + /* UART0 */ + uart0_tx_default: uart0_tx_default { + pinmux = <1 DIO1_UART0_TXD>; + bias-disable; + }; + + uart0_rx_default: uart0_rx_default { + pinmux = <2 DIO2_UART0_RXD>; + bias-pull-up; + input-enable; + }; + + /* UART1 */ + uart1_tx_default: uart1_tx_default { + pinmux = <21 DIO21_UART1_TXD>; + bias-disable; + }; + + uart1_rx_default: uart1_rx_default { + pinmux = <22 DIO22_UART1_RXD>; + bias-pull-up; + input-enable; + }; + + /* I2C0 */ + i2c0_scl_default: i2c0_scl_default { + pinmux = <27 DIO27_I2C0_SCL>; + bias-pull-up; + drive-open-drain; + input-enable; + }; + + i2c0_sda_default: i2c0_sda_default { + pinmux = <28 DIO28_I2C0_SDA>; + bias-pull-up; + drive-open-drain; + input-enable; + }; + + /* SPI0 */ + spi0_sck_default: spi0_sck_default { + pinmux = <3 DIO3_SPI0_SCLK>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_mosi_default: spi0_mosi_default { + pinmux = <5 DIO5_SPI0_PICO>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_miso_default: spi0_miso_default { + pinmux = <4 DIO4_SPI0_POCI>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_cs_default: spi0_cs_default { + pinmux = <19 DIO19_GPIO19>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_sck_sleep: spi0_sck_sleep { + pinmux = <3 DIO3_GPIO3>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_mosi_sleep: spi0_mosi_sleep { + pinmux = <5 DIO5_GPIO5>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_miso_sleep: spi0_miso_sleep { + pinmux = <4 DIO4_GPIO4>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_cs_sleep: spi0_cs_sleep { + pinmux = <19 DIO19_GPIO19>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_flash_cs: spi0_flash_cs { + pinmux = <19 DIO19_GPIO19>; + bias-pull-up; + }; + + /* SPI1 */ + spi1_sck_default: spi1_sck_default { + pinmux = <15 DIO15_SPI1_SCLK>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi1_mosi_default: spi1_mosi_default { + pinmux = <11 DIO11_SPI1_PICO>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi1_miso_default: spi1_miso_default { + pinmux = <12 DIO12_SPI1_POCI>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi1_cs_default: spi1_cs_default { + pinmux = <16 DIO16_GPIO16>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi1_sck_sleep: spi1_sck_sleep { + pinmux = <15 DIO15_GPIO15>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi1_mosi_sleep: spi1_mosi_sleep { + pinmux = <11 DIO11_GPIO11>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi1_miso_sleep: spi1_miso_sleep { + pinmux = <12 DIO12_GPIO12>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi1_cs_sleep: spi1_cs_sleep { + pinmux = <16 DIO16_GPIO16>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + /* ADC channels. */ + + adc0_ch0: adc0_ch0 { + pinmux = <28 DIO28_ADC0_AREFM>; + bias-disable; + input-enable; + }; + + adc0_ch1: adc0_ch1 { + pinmux = <27 DIO27_ADC1_AREFP>; + bias-disable; + input-enable; + }; + + adc0_ch3: adc0_ch3 { + pinmux = <22 DIO22_ADC3>; + bias-disable; + input-enable; + }; + + adc0_ch4: adc0_ch4 { + pinmux = <21 DIO21_ADC4_LPCP_LPCM>; + bias-disable; + input-enable; + }; + + adc0_ch5: adc0_ch5 { + pinmux = <20 DIO20_ADC5_LPCP_LPCM>; + bias-disable; + input-enable; + }; + + adc0_ch6: adc0_ch6 { + pinmux = <19 DIO19_ADC6_LPCP>; + bias-disable; + input-enable; + }; + + adc0_ch7: adc0_ch7 { + pinmux = <18 DIO18_ADC7>; + bias-disable; + input-enable; + }; + + adc0_ch8: adc0_ch8 { + pinmux = <17 DIO17_ADC8>; + bias-disable; + input-enable; + }; + + /* PWM - LGPT3 Channel 1 on DIO12 (T3_C1) for LED0/Green LED and test capture */ + pwm10_default: pwm10_default { + pinmux = <12 DIO12_T3_C1>; + bias-disable; + }; + + /* PWM - LGPT3 Channel 0 on DIO16 (T3_C0) for LED1/Red LED */ + pwm9_default: pwm9_default { + pinmux = <16 DIO16_T3_C0>; + bias-disable; + }; + + /* PWM - LGPT2 Channel 1 on DIO5 (T2_C1) - BP15 for idle level */ + pwm7_default: pwm7_default { + pinmux = <5 DIO5_T2_C1>; + bias-disable; + }; + + /* I2S0: DIO17=SCLK, DIO18=WS, DIO19=SD0(TX), DIO20=SD1(RX) + * Reference: <&i2s0_sclk_default &i2s0_ws_default + * &i2s0_sd0_default &i2s0_sd1_default> + * NOTE: All pins need input-enable (HW samples own outputs for sync) + */ + i2s0_sclk_default: i2s0_sclk_default { + pinmux = <17 DIO17_I2S0_SCLK>; + bias-disable; + input-enable; + }; + + i2s0_ws_default: i2s0_ws_default { + pinmux = <18 DIO18_I2S0_WS>; + bias-disable; + input-enable; + }; + + i2s0_sd0_default: i2s0_sd0_default { + pinmux = <19 DIO19_I2S0_SD0>; + bias-disable; + input-enable; + }; + + i2s0_sd1_default: i2s0_sd1_default { + pinmux = <20 DIO20_I2S0_SD1>; + bias-disable; + input-enable; + }; + + /* LGPT1 ch0 output (DIO15, T1_C0N) */ + pwm3_default: lgpt1_chan0_default { + pinmux = <15 DIO15_T1_C0N>; + bias-disable; + }; + + /* LGPT0 ch0 capture input (DIO0, T0_C0) */ + pwm0_capture: lgpt0_chan0_capture { + pinmux = <0 DIO0_T0_C0>; + bias-disable; + input-enable; + }; +}; diff --git a/boards/ti/lp_em_cc2745r10_q1/lp_em_cc2745r10_q1_cc2745r10_q1.dts b/boards/ti/lp_em_cc2745r10_q1/lp_em_cc2745r10_q1_cc2745r10_q1.dts new file mode 100644 index 000000000000..9979483bd5f4 --- /dev/null +++ b/boards/ti/lp_em_cc2745r10_q1/lp_em_cc2745r10_q1_cc2745r10_q1.dts @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2025 Texas Instruments Incorporated + * Copyright (c) 2024 BayLibre, SAS + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "boosterpack_connector.dtsi" +#include "lp_em_cc2745r10_q1_cc2745r10_q1-pinctrl.dtsi" +#include +#include +#include + +#include "lp_em_cc2745r10_q1_common.dtsi" + +/ { + model = "TI CC2745R10_Q1 LaunchPad with CC2745R10_Q1 SoC"; + + aliases { + pwm-led0 = &pwm_led0; + pwm-led1 = &pwm_led1; + }; + + pwmleds { + compatible = "pwm-leds"; + + pwm_led0: pwm_led0 { + /* Use LGPT3 output 1 (pwm10) on DIO12 where Green LED is */ + /* LGPT3 is 24-bit timer, supporting longer periods for led_blink */ + pwms = <&pwm10 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + }; + + pwm_led1: pwm_led1 { + /* Use LGPT3 output 0 (pwm9) on DIO16 where Red LED is */ + pwms = <&pwm9 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + }; + }; +}; + +/* Enable LGPT3 timer for PWM LEDs: + * - PWM9 (channel 0) on DIO16 for Red LED + * - PWM10 (channel 1) on DIO12 for Green LED + * LGPT3 is a 24-bit timer, supporting periods up to ~44 seconds at 375kHz + */ +&lgpt3 { + status = "okay"; + /* Prescaler at 96MHz: Effective clock = 96MHz / (31 + 1) = 3MHz */ + clk-prescale = <31>; +}; + +&pwm9 { + status = "okay"; + pinctrl-0 = <&pwm9_default>; + pinctrl-names = "default"; +}; + +&pwm10 { + status = "okay"; + pinctrl-0 = <&pwm10_default>; + pinctrl-names = "default"; +}; + +/* Enable LGPT2 timer for PWM7 (channel 1) on DIO5 (BP15) */ +&lgpt2 { + status = "okay"; + clk-prescale = <31>; +}; + +&pwm7 { + status = "okay"; + pinctrl-0 = <&pwm7_default>; + pinctrl-names = "default"; +}; diff --git a/boards/ti/lp_em_cc2745r10_q1/lp_em_cc2745r10_q1_cc2745r10_q1.yaml b/boards/ti/lp_em_cc2745r10_q1/lp_em_cc2745r10_q1_cc2745r10_q1.yaml new file mode 100644 index 000000000000..72b3eee88f21 --- /dev/null +++ b/boards/ti/lp_em_cc2745r10_q1/lp_em_cc2745r10_q1_cc2745r10_q1.yaml @@ -0,0 +1,31 @@ +identifier: lp_em_cc2745r10_q1/cc2745r10_q1 +name: TI SimpleLink CC2745R10_Q1 LaunchPad +type: mcu +arch: arm +ram: 162 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - dma + - crypto + - spi + - i2s + - adc + - pm + - pwm + - watchdog + - counter + - rtc + - nvs + - entropy + - flash + - pinctrl + - serial + - timer + - i2c + - uart +vendor: ti diff --git a/boards/ti/lp_em_cc2745r10_q1/lp_em_cc2745r10_q1_cc2745r10_q1_defconfig b/boards/ti/lp_em_cc2745r10_q1/lp_em_cc2745r10_q1_cc2745r10_q1_defconfig new file mode 100644 index 000000000000..575a11be59e3 --- /dev/null +++ b/boards/ti/lp_em_cc2745r10_q1/lp_em_cc2745r10_q1_cc2745r10_q1_defconfig @@ -0,0 +1,17 @@ +# Copyright (c) 2025 Texas Instruments Incorporated +# Copyright (c) 2024 BayLibre, SAS +# +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_GPIO=y +CONFIG_SERIAL=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_BT_HCI_ACL_FLOW_CONTROL=n + +CONFIG_PM=y + +CONFIG_MBEDTLS=y +CONFIG_MBEDTLS_PSA_CRYPTO_C=y diff --git a/boards/ti/lp_em_cc2745r10_q1/lp_em_cc2745r10_q1_cc2755r10-pinctrl.dtsi b/boards/ti/lp_em_cc2745r10_q1/lp_em_cc2745r10_q1_cc2755r10-pinctrl.dtsi new file mode 100644 index 000000000000..94e86de314a4 --- /dev/null +++ b/boards/ti/lp_em_cc2745r10_q1/lp_em_cc2745r10_q1_cc2755r10-pinctrl.dtsi @@ -0,0 +1,231 @@ +/* + * Copyright (c) 2025 - 2026 Texas Instruments Incorporated + * Copyright (c) 2024 BayLibre, SAS + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + /* UART0 */ + uart0_tx_default: uart0_tx_default { + pinmux = <1 DIO1_UART0_TXD>; + bias-disable; + }; + + uart0_rx_default: uart0_rx_default { + pinmux = <2 DIO2_UART0_RXD>; + bias-pull-up; + input-enable; + }; + + /* UART1 */ + uart1_tx_default: uart1_tx_default { + pinmux = <21 DIO21_UART1_TXD>; + bias-disable; + }; + + uart1_rx_default: uart1_rx_default { + pinmux = <22 DIO22_UART1_RXD>; + bias-pull-up; + input-enable; + }; + + /* I2C0 */ + i2c0_scl_default: i2c0_scl_default { + pinmux = <27 DIO27_I2C0_SCL>; + bias-pull-up; + drive-open-drain; + input-enable; + }; + + i2c0_sda_default: i2c0_sda_default { + pinmux = <28 DIO28_I2C0_SDA>; + bias-pull-up; + drive-open-drain; + input-enable; + }; + + /* SPI0 */ + spi0_sck_default: spi0_sck_default { + pinmux = <3 DIO3_SPI0_SCLK>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_mosi_default: spi0_mosi_default { + pinmux = <5 DIO5_SPI0_PICO>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_miso_default: spi0_miso_default { + pinmux = <4 DIO4_SPI0_POCI>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_cs_default: spi0_cs_default { + pinmux = <19 DIO19_GPIO19>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_sck_sleep: spi0_sck_sleep { + pinmux = <3 DIO3_GPIO3>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_mosi_sleep: spi0_mosi_sleep { + pinmux = <5 DIO5_GPIO5>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_miso_sleep: spi0_miso_sleep { + pinmux = <4 DIO4_GPIO4>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_cs_sleep: spi0_cs_sleep { + pinmux = <19 DIO19_GPIO19>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_flash_cs: spi0_flash_cs { + pinmux = <19 DIO19_GPIO19>; + bias-pull-up; + }; + + /* SPI1 */ + spi1_sck_default: spi1_sck_default { + pinmux = <15 DIO15_SPI1_SCLK>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi1_mosi_default: spi1_mosi_default { + pinmux = <11 DIO11_SPI1_PICO>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi1_miso_default: spi1_miso_default { + pinmux = <12 DIO12_SPI1_POCI>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi1_cs_default: spi1_cs_default { + pinmux = <16 DIO16_GPIO16>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi1_sck_sleep: spi1_sck_sleep { + pinmux = <15 DIO15_GPIO15>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi1_mosi_sleep: spi1_mosi_sleep { + pinmux = <11 DIO11_GPIO11>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi1_miso_sleep: spi1_miso_sleep { + pinmux = <12 DIO12_GPIO12>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi1_cs_sleep: spi1_cs_sleep { + pinmux = <16 DIO16_GPIO16>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + /* ADC channels. */ + + adc0_ch0: adc0_ch0 { + pinmux = <28 DIO28_ADC0_AREFM>; + bias-disable; + input-enable; + }; + + adc0_ch1: adc0_ch1 { + pinmux = <27 DIO27_ADC1_AREFP>; + bias-disable; + input-enable; + }; + + adc0_ch3: adc0_ch3 { + pinmux = <22 DIO22_ADC3>; + bias-disable; + input-enable; + }; + + adc0_ch4: adc0_ch4 { + pinmux = <21 DIO21_ADC4_LPCP_LPCM>; + bias-disable; + input-enable; + }; + + adc0_ch5: adc0_ch5 { + pinmux = <20 DIO20_ADC5_LPCP_LPCM>; + bias-disable; + input-enable; + }; + + adc0_ch6: adc0_ch6 { + pinmux = <19 DIO19_ADC6_LPCP>; + bias-disable; + input-enable; + }; + + adc0_ch7: adc0_ch7 { + pinmux = <18 DIO18_ADC7>; + bias-disable; + input-enable; + }; + + adc0_ch8: adc0_ch8 { + pinmux = <17 DIO17_ADC8>; + bias-disable; + input-enable; + }; + + /* LGPT1 ch0 output (DIO15, T1_C0N) */ + pwm3_default: lgpt1_chan0_default { + pinmux = <15 DIO15_T1_C0N>; + bias-disable; + }; + + /* LGPT0 ch0 capture input (DIO0, T0_C0) */ + pwm0_capture: lgpt0_chan0_capture { + pinmux = <0 DIO0_T0_C0>; + bias-disable; + input-enable; + }; +}; diff --git a/boards/ti/lp_em_cc2745r10_q1/lp_em_cc2745r10_q1_cc2755r10.dts b/boards/ti/lp_em_cc2745r10_q1/lp_em_cc2745r10_q1_cc2755r10.dts new file mode 100644 index 000000000000..cd935cad83ea --- /dev/null +++ b/boards/ti/lp_em_cc2745r10_q1/lp_em_cc2745r10_q1_cc2755r10.dts @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2025 Texas Instruments Incorporated + * Copyright (c) 2024 BayLibre, SAS + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "boosterpack_connector.dtsi" +#include "lp_em_cc2745r10_q1_cc2755r10-pinctrl.dtsi" +#include +#include + +#include "lp_em_cc2745r10_q1_common.dtsi" + +/ { + model = "TI CC2745R10_Q1 LaunchPad with CC2755R10 SoC"; +}; diff --git a/boards/ti/lp_em_cc2745r10_q1/lp_em_cc2745r10_q1_cc2755r10.yaml b/boards/ti/lp_em_cc2745r10_q1/lp_em_cc2745r10_q1_cc2755r10.yaml new file mode 100644 index 000000000000..585c817dbfa4 --- /dev/null +++ b/boards/ti/lp_em_cc2745r10_q1/lp_em_cc2745r10_q1_cc2755r10.yaml @@ -0,0 +1,31 @@ +identifier: lp_em_cc2745r10_q1/cc2755r10 +name: TI SimpleLink CC2745R10_Q1 LaunchPad +type: mcu +arch: arm +ram: 162 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - dma + - crypto + - spi + - i2s + - adc + - pm + - pwm + - watchdog + - counter + - rtc + - nvs + - entropy + - flash + - pinctrl + - serial + - timer + - i2c + - uart +vendor: ti diff --git a/boards/ti/lp_em_cc2745r10_q1/lp_em_cc2745r10_q1_cc2755r10_defconfig b/boards/ti/lp_em_cc2745r10_q1/lp_em_cc2745r10_q1_cc2755r10_defconfig new file mode 100644 index 000000000000..575a11be59e3 --- /dev/null +++ b/boards/ti/lp_em_cc2745r10_q1/lp_em_cc2745r10_q1_cc2755r10_defconfig @@ -0,0 +1,17 @@ +# Copyright (c) 2025 Texas Instruments Incorporated +# Copyright (c) 2024 BayLibre, SAS +# +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_GPIO=y +CONFIG_SERIAL=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_BT_HCI_ACL_FLOW_CONTROL=n + +CONFIG_PM=y + +CONFIG_MBEDTLS=y +CONFIG_MBEDTLS_PSA_CRYPTO_C=y diff --git a/boards/ti/lp_em_cc2745r10_q1/lp_em_cc2745r10_q1_common.dtsi b/boards/ti/lp_em_cc2745r10_q1/lp_em_cc2745r10_q1_common.dtsi new file mode 100644 index 000000000000..eb06c194bb16 --- /dev/null +++ b/boards/ti/lp_em_cc2745r10_q1/lp_em_cc2745r10_q1_common.dtsi @@ -0,0 +1,190 @@ +/* + * Copyright (c) 2026 Texas Instruments Incorporated + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define BTN_GPIO_FLAGS (GPIO_ACTIVE_LOW | GPIO_PULL_UP) + +/ { + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,bt_hci = &ti_bt_hci; + zephyr,bt-c2h-uart = &uart0; + zephyr,code-partition = &slot0_partition; + zephyr,uart-mcumgr = &uart0; + }; + + aliases { + led0 = &led0; + led1 = &led1; + sw0 = &btn0; + sw1 = &btn1; + rtc = &rtc; + }; + + leds { + compatible = "gpio-leds"; + + led0: led_0 { + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + label = "Green LED"; + }; + + led1: led_1 { + gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + label = "Red LED"; + }; + }; + + keys { + compatible = "gpio-keys"; + + btn0: btn_0 { + gpios = <&gpio0 20 BTN_GPIO_FLAGS>; + label = "Button 1"; + zephyr,code = ; + }; + + btn1: btn_1 { + gpios = <&gpio0 0 BTN_GPIO_FLAGS>; + label = "Button 2"; + zephyr,code = ; + }; + }; + + lfxosc: lf_xosc { + compatible = "ti,cc27xx-lf-xosc"; + }; + + ti_bt_hci: ti_bt_hci { + compatible = "ti,bt-hci"; + status = "okay"; + }; +}; + +/delete-node/ &slot0_partition; + +&flash0 { + partitions { + /* 40 KiB (0xa000) for MCUboot */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x0000a000>; + }; + + /* 446464 Bytes (0x6d000) per slot for application */ + slot0_partition: partition@a000 { + label = "image-0"; + reg = <0x0000a000 0x0006d000>; + }; + + slot1_partition: partition@77000 { + label = "image-1"; + reg = <0x00077000 0x0006d000>; + }; + }; +}; + +&cpu0 { + clock-frequency = <96000000>; +}; + +&gpio0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_rx_default &uart0_tx_default>; + pinctrl-names = "default"; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart1_rx_default &uart1_tx_default>; + pinctrl-names = "default"; +}; + +&i2c0 { + status = "okay"; + pinctrl-0 = <&i2c0_scl_default + &i2c0_sda_default>; + clock-frequency = <100000>; + pinctrl-names = "default"; +}; + +&spi0 { + status = "okay"; + pinctrl-0 = <&spi0_sck_default + &spi0_mosi_default + &spi0_miso_default + &spi0_cs_default>; + pinctrl-1 = <&spi0_sck_sleep + &spi0_mosi_sleep + &spi0_miso_sleep + &spi0_cs_sleep>; + pinctrl-names = "default", "sleep"; + cs-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>; + + mx25r80: mx25r8035f@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <12000000>; + size = <0x800000>; + jedec-id = [c2 28 14]; + sfdp-bfp = [e5 20 f1 ff ff ff 7f 00 44 eb 08 6b 08 3b 04 bb + ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 + 10 d8 00 ff 23 72 f5 00 82 ed 04 b7 44 83 38 44 + 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff]; + }; +}; + +&spi1 { + status = "okay"; + pinctrl-0 = <&spi1_sck_default + &spi1_mosi_default + &spi1_miso_default + &spi1_cs_default>; + pinctrl-1 = <&spi1_sck_sleep + &spi1_mosi_sleep + &spi1_miso_sleep + &spi1_cs_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&dma { + status = "okay"; +}; + +&aes { + status = "okay"; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_ch3 + &adc0_ch4 + &adc0_ch5 + &adc0_ch6 + &adc0_ch7 + &adc0_ch8>; + pinctrl-names = "default"; +}; + +&wdt0 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&rng { + status = "okay"; +}; diff --git a/boards/ti/lp_em_cc2755p10/Kconfig b/boards/ti/lp_em_cc2755p10/Kconfig new file mode 100644 index 000000000000..188487967724 --- /dev/null +++ b/boards/ti/lp_em_cc2755p10/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2026 Texas Instruments Incorporated +# +# SPDX-License-Identifier: Apache-2.0 + +rsource "../lpf3_common/Kconfig" diff --git a/boards/ti/lp_em_cc2755p10/Kconfig.defconfig b/boards/ti/lp_em_cc2755p10/Kconfig.defconfig new file mode 100644 index 000000000000..c44fd493cd75 --- /dev/null +++ b/boards/ti/lp_em_cc2755p10/Kconfig.defconfig @@ -0,0 +1,28 @@ +# Copyright (c) 2026 Texas Instruments Incorporated +# +# SPDX-License-Identifier: Apache-2.0 + +rsource "../lpf3_common/Kconfig.defconfig" + +if BOARD_LP_EM_CC2755P10 + +if BT +config BT_LL_HEAP_SIZE + hex + default 0x4E00 +endif # BT + +if PM +# Power Management requires increased idle task stack size because of +# stack usage introduced by "pm_state_set" +config IDLE_STACK_SIZE + default 320 +endif # PM + +# The SPI driver only supports DMA mode +if SPI +config SPI_CC23X0_CC27XX_DMA_DRIVEN + default y +endif # SPI + +endif # BOARD_LP_EM_CC2755P10 diff --git a/boards/ti/lp_em_cc2755p10/Kconfig.lp_em_cc2755p10 b/boards/ti/lp_em_cc2755p10/Kconfig.lp_em_cc2755p10 new file mode 100644 index 000000000000..1bec02389b18 --- /dev/null +++ b/boards/ti/lp_em_cc2755p10/Kconfig.lp_em_cc2755p10 @@ -0,0 +1,7 @@ +# Copyright (c) 2026 Texas Instruments Incorporated +# Copyright (c) 2024 BayLibre, SAS +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LP_EM_CC2755P10 + select SOC_CC2755P10 if BOARD_LP_EM_CC2755P10 diff --git a/boards/ti/lp_em_cc2755p10/board.cmake b/boards/ti/lp_em_cc2755p10/board.cmake new file mode 100644 index 000000000000..fc13d35685cd --- /dev/null +++ b/boards/ti/lp_em_cc2755p10/board.cmake @@ -0,0 +1,10 @@ +# Copyright (c) 2025 Texas Instruments Incorporated +# Copyright (c) 2024 BayLibre, SAS +# +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=CC2755P10") +board_runner_args(openocd --cmd-pre-init "source [find board/ti_lp_em_cc2755P10.cfg]") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/ti_openocd.board.cmake) diff --git a/boards/ti/lp_em_cc2755p10/board.yml b/boards/ti/lp_em_cc2755p10/board.yml new file mode 100644 index 000000000000..99e75a618447 --- /dev/null +++ b/boards/ti/lp_em_cc2755p10/board.yml @@ -0,0 +1,6 @@ +board: + name: lp_em_cc2755p10 + full_name: CC2755P10 LaunchPad + vendor: ti + socs: + - name: cc2755p10 diff --git a/boards/ti/lp_em_cc2755p10/boosterpack_connector.dtsi b/boards/ti/lp_em_cc2755p10/boosterpack_connector.dtsi new file mode 100644 index 000000000000..9c7f696e7f0d --- /dev/null +++ b/boards/ti/lp_em_cc2755p10/boosterpack_connector.dtsi @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2026 Texas Instruments Incorporated + * Copyright (c) 2024 BayLibre, SAS + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + boosterpack_header: connector { + compatible = "ti,boosterpack-header"; + #gpio-cells = <2>; + gpio-map = <2 0 &gpio0 21 0>, + <3 0 &gpio0 2 0>, + <4 0 &gpio0 1 0>, + <5 0 &gpio0 23 0>, + <6 0 &gpio0 22 0>, + <7 0 &gpio0 3 0>, + <8 0 &gpio0 24 0>, + <9 0 &gpio0 27 0>, + <10 0 &gpio0 28 0>, + <14 0 &gpio0 4 0>, + <15 0 &gpio0 5 0>, + <18 0 &gpio0 7 0>, + <19 0 &gpio0 12 0>, + <27 0 &gpio0 18 0>, + <28 0 &gpio0 17 0>, + <29 0 &gpio0 19 0>, + <30 0 &gpio0 20 0>, + <31 0 &gpio0 18 0>, + <32 0 &gpio0 17 0>, + <33 0 &gpio0 10 0>, + <34 0 &gpio0 9 0>, + <35 0 &gpio0 15 0>, + <36 0 &gpio0 16 0>, + <38 0 &gpio0 19 0>, + <39 0 &gpio0 11 0>, + <40 0 &gpio0 0 0>; + }; +}; diff --git a/boards/ti/lp_em_cc2755p10/doc/img/lp_em_cc2755p10.jpg b/boards/ti/lp_em_cc2755p10/doc/img/lp_em_cc2755p10.jpg new file mode 100644 index 000000000000..eb7b9795d1db Binary files /dev/null and b/boards/ti/lp_em_cc2755p10/doc/img/lp_em_cc2755p10.jpg differ diff --git a/boards/ti/lp_em_cc2755p10/doc/index.rst b/boards/ti/lp_em_cc2755p10/doc/index.rst new file mode 100644 index 000000000000..04820b481018 --- /dev/null +++ b/boards/ti/lp_em_cc2755p10/doc/index.rst @@ -0,0 +1,124 @@ +.. _lp_em_cc2755p10: + +TI CC2755P10 Launchpad +######################### + +Overview +******** + +The Texas Instruments CC2755P10 LaunchPad |trade| (LP_EM_CC2755P10) is a +development kit for the SimpleLink |trade| multi-Standard CC2755P10 wireless MCU. + +See the `TI CC2755P10 LaunchPad Product Page`_ for details. + +.. figure:: img/lp_em_cc2755p10.jpg + :align: center + :alt: TI CC2755P10 Launchpad + + Texas Instruments CC2755P10 LaunchPad |trade| + +Hardware +******** + +The CC2755P10 LaunchPad |trade| development kit features the CC2755P10 wireless MCU. +The board is equipped with two LEDs, two push buttons and BoosterPack connectors +for expansion. + +The CC2755P10 wireless MCU has a 96 MHz Arm |reg| Cortex |reg|-M33 SoC and an +integrated 2.4 GHz transceiver supporting multiple protocols including Bluetooth +|reg| Low Energy and IEEE |reg| 802.15.4. + +The CC2755P10 wireless MCU supports additional protocols such as Matter, Thread, and Zigbee + +See the `TI CC2755P10 Product Page`_ for additional details. + +Supported Features +================== + +The CC2755P10 LaunchPad board configuration supports the following hardware +features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| UART | on-chip | uart | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. + +Connections and IOs +=================== + +All I/O signals are accessible from the BoosterPack connectors. Pin function +aligns with the LaunchPad standard. + ++-------+-----------+-------------------------+ +| Pin | Function | Usage | ++=======+===========+=========================+ +| DIO0 | GPIO | Button 2 | ++-------+-----------+-------------------------+ +| DIO1 | UART_TX | UART TX | ++-------+-----------+-------------------------+ +| DIO2 | UART_RX | UART RX | ++-------+-----------+-------------------------+ +| DIO3 | SPI_CLK | SPI CLK | ++-------+-----------+-------------------------+ +| DIO4 | SPI_POCI | SPI POCI | ++-------+-----------+-------------------------+ +| DIO5 | SPI_PICO | SPI PICO | ++-------+-----------+-------------------------+ +| DIO7 | SPI_CSN | SPI CS | ++-------+-----------+-------------------------+ +| DIO9 | SWD_IO | SWD IO | ++-------+-----------+-------------------------+ +| DIO10 | SWD_CK | SWD CK | ++-------+-----------+-------------------------+ +| DIO11 | GPIO | | ++-------+-----------+-------------------------+ +| DIO12 | GPIO | Green LED | ++-------+-----------+-------------------------+ +| DIO16 | GPIO | RED LED | ++-------+-----------+-------------------------+ +| DIO17 | ANALOG_IO | CAN TX / A8 | ++-------+-----------+-------------------------+ +| DIO18 | ANALOG_IO | CAN RX / A7 | ++-------+-----------+-------------------------+ +| DIO19 | ANALOG_IO | I2S SDO / A6 | ++-------+-----------+-------------------------+ +| DIO20 | ANALOG_IO | I2C SDI / A5 / Button 1 | ++-------+-----------+-------------------------+ +| DIO21 | ANALOG_IO | A4 | ++-------+-----------+-------------------------+ +| DIO22 | ANALOG_IO | A3 | ++-------+-----------+-------------------------+ +| DIO23 | GPIO | | ++-------+-----------+-------------------------+ +| DIO24 | GPIO | | ++-------+-----------+-------------------------+ +| DIO27 | I2C_SCL | I2C SCL | ++-------+-----------+-------------------------+ +| DIO28 | I2C_SDA | I2C SDA | ++-------+-----------+-------------------------+ + +Programming and Debugging +************************* + +The LP_EM_CC2755P10 requires an external debug probe such as the LP-XDS110 or +LP-XDS110ET. + +Currently there is no debug support in Zephyr for the LP_EM_CC2755P10, and the +built binaries for this target must be flashed/debugged using either Uniflash or +Code Composer Studio. + +References +********** + +.. _TI CC2755P10 LaunchPad Quick Start Guide: + https://www.ti.com/lit/ug/swru635/swru635.pdf +.. _TI CC2755P10 LaunchPad Product Page: + https://www.ti.com/tool/LP-EM-CC2745R10-Q1 + +.. _TI CC2755P10 Product Page: + https://www.ti.com/product/CC2745R10-Q1 diff --git a/boards/ti/lp_em_cc2755p10/lp_em_cc2755p10-pinctrl.dtsi b/boards/ti/lp_em_cc2755p10/lp_em_cc2755p10-pinctrl.dtsi new file mode 100644 index 000000000000..399e83fb81c0 --- /dev/null +++ b/boards/ti/lp_em_cc2755p10/lp_em_cc2755p10-pinctrl.dtsi @@ -0,0 +1,258 @@ +/* + * Copyright (c) 2026 Texas Instruments Incorporated + * Copyright (c) 2024 BayLibre, SAS + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + /* UART0 */ + uart0_tx_default: uart0_tx_default { + pinmux = <1 DIO1_UART0_TXD>; + bias-disable; + }; + + uart0_rx_default: uart0_rx_default { + pinmux = <2 DIO2_UART0_RXD>; + bias-disable; + input-enable; + }; + + /* UART1 */ + uart1_tx_default: uart1_tx_default { + pinmux = <21 DIO21_UART1_TXD>; + bias-disable; + }; + + uart1_rx_default: uart1_rx_default { + pinmux = <22 DIO22_UART1_RXD>; + bias-disable; + input-enable; + }; + + /* I2C0 */ + i2c0_scl_default: i2c0_scl_default { + pinmux = <27 DIO27_I2C0_SCL>; + bias-pull-up; + drive-open-drain; + input-enable; + }; + + i2c0_sda_default: i2c0_sda_default { + pinmux = <28 DIO28_I2C0_SDA>; + bias-pull-up; + drive-open-drain; + input-enable; + }; + + /* SPI0 */ + spi0_sck_default: spi0_sck_default { + pinmux = <3 DIO3_SPI0_SCLK>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_mosi_default: spi0_mosi_default { + pinmux = <5 DIO5_SPI0_PICO>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_miso_default: spi0_miso_default { + pinmux = <4 DIO4_SPI0_POCI>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_cs_default: spi0_cs_default { + pinmux = <19 DIO19_GPIO19>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_sck_sleep: spi0_sck_sleep { + pinmux = <3 DIO3_GPIO3>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_mosi_sleep: spi0_mosi_sleep { + pinmux = <5 DIO5_GPIO5>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_miso_sleep: spi0_miso_sleep { + pinmux = <4 DIO4_GPIO4>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_cs_sleep: spi0_cs_sleep { + pinmux = <19 DIO19_GPIO19>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_flash_cs: spi0_flash_cs { + pinmux = <19 DIO19_GPIO19>; + bias-pull-up; + }; + + /* SPI1 */ + spi1_sck_default: spi1_sck_default { + pinmux = <15 DIO15_SPI1_SCLK>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi1_mosi_default: spi1_mosi_default { + pinmux = <11 DIO11_SPI1_PICO>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi1_miso_default: spi1_miso_default { + pinmux = <12 DIO12_SPI1_POCI>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi1_cs_default: spi1_cs_default { + pinmux = <16 DIO16_GPIO16>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi1_sck_sleep: spi1_sck_sleep { + pinmux = <15 DIO15_GPIO15>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi1_mosi_sleep: spi1_mosi_sleep { + pinmux = <11 DIO11_GPIO11>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi1_miso_sleep: spi1_miso_sleep { + pinmux = <12 DIO12_GPIO12>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi1_cs_sleep: spi1_cs_sleep { + pinmux = <16 DIO16_GPIO16>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + /* ADC channels. */ + + adc0_ch0: adc0_ch0 { + pinmux = <28 DIO28_ADC0_AREFM>; + bias-disable; + input-enable; + }; + + adc0_ch1: adc0_ch1 { + pinmux = <27 DIO27_ADC1_AREFP>; + bias-disable; + input-enable; + }; + + adc0_ch3: adc0_ch3 { + pinmux = <22 DIO22_ADC3>; + bias-disable; + input-enable; + }; + + adc0_ch4: adc0_ch4 { + pinmux = <21 DIO21_ADC4_LPCP_LPCM>; + bias-disable; + input-enable; + }; + + adc0_ch5: adc0_ch5 { + pinmux = <20 DIO20_ADC5_LPCP_LPCM>; + bias-disable; + input-enable; + }; + + adc0_ch6: adc0_ch6 { + pinmux = <19 DIO19_ADC6_LPCP>; + bias-disable; + input-enable; + }; + + adc0_ch7: adc0_ch7 { + pinmux = <18 DIO18_ADC7>; + bias-disable; + input-enable; + }; + + adc0_ch8: adc0_ch8 { + pinmux = <17 DIO17_ADC8>; + bias-disable; + input-enable; + }; + + /* I2S0: DIO16=MCLK, DIO17=SCLK, DIO18=WS, DIO19=SD0(TX), DIO20=SD1(RX) */ + i2s0_mclk_default: i2s0_mclk_default { + pinmux = <16 DIO16_I2S0_MCLK>; + bias-disable; + }; + + i2s0_sclk_default: i2s0_sclk_default { + pinmux = <17 DIO17_I2S0_SCLK>; + bias-disable; + }; + + i2s0_ws_default: i2s0_ws_default { + pinmux = <18 DIO18_I2S0_WS>; + bias-disable; + }; + + i2s0_sd0_default: i2s0_sd0_default { + pinmux = <19 DIO19_I2S0_SD0>; + bias-disable; + }; + + i2s0_sd1_default: i2s0_sd1_default { + pinmux = <20 DIO20_I2S0_SD1>; + bias-disable; + input-enable; + }; + + /* LGPT3 ch0 output (DIO28, T3_C0N) */ + pwm9_default: lgpt3_chan0_default { + pinmux = <28 DIO28_T3_C0N>; + bias-disable; + }; + + /* LGPT0 ch0 capture input (DIO0, T0_C0) */ + pwm0_capture: lgpt0_chan0_capture { + pinmux = <0 DIO0_T0_C0>; + bias-disable; + input-enable; + }; +}; diff --git a/boards/ti/lp_em_cc2755p10/lp_em_cc2755p10.dts b/boards/ti/lp_em_cc2755p10/lp_em_cc2755p10.dts new file mode 100644 index 000000000000..1ae7bc2e836b --- /dev/null +++ b/boards/ti/lp_em_cc2755p10/lp_em_cc2755p10.dts @@ -0,0 +1,196 @@ +/* + * Copyright (c) 2026 Texas Instruments Incorporated + * Copyright (c) 2024 BayLibre, SAS + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "boosterpack_connector.dtsi" +#include "lp_em_cc2755p10-pinctrl.dtsi" +#include +#include + +#define BTN_GPIO_FLAGS (GPIO_ACTIVE_LOW | GPIO_PULL_UP) + +/ { + model = "TI CC2755P10 LaunchPad "; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,bt_hci = &ti_bt_hci; + zephyr,bt-c2h-uart = &uart0; + zephyr,code-partition = &slot0_partition; + zephyr,uart-mcumgr = &uart0; + }; + + aliases { + led0 = &led0; + led1 = &led1; + sw0 = &btn0; + sw1 = &btn1; + }; + + leds { + compatible = "gpio-leds"; + + led0: led_0 { + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + label = "Green LED"; + }; + + led1: led_1 { + gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + label = "Red LED"; + }; + }; + + keys { + compatible = "gpio-keys"; + + btn0: btn_0 { + gpios = <&gpio0 20 BTN_GPIO_FLAGS>; + label = "Button 1"; + zephyr,code = ; + }; + + btn1: btn_1 { + gpios = <&gpio0 0 BTN_GPIO_FLAGS>; + label = "Button 2"; + zephyr,code = ; + }; + }; + + lfxosc: lf_xosc { + compatible = "ti,cc27xx-lf-xosc"; + }; + + ti_bt_hci: ti_bt_hci { + compatible = "ti,bt-hci"; + status = "okay"; + }; +}; + +/delete-node/ &slot0_partition; + +&flash0 { + partitions { + /* 40 KiB (0xa000) for MCUboot */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x0000a000>; + }; + + /* 233472 Bytes (0x39000) per slot for application */ + slot0_partition: partition@a000 { + label = "image-0"; + reg = <0x0000a000 0x0006d000>; + }; + + slot1_partition: partition@77000 { + label = "image-1"; + reg = <0x00077000 0x0006d000>; + }; + }; +}; + +&cpu0 { + clock-frequency = <96000000>; +}; + +&gpio0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_rx_default &uart0_tx_default>; + pinctrl-names = "default"; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart1_rx_default &uart1_tx_default>; + pinctrl-names = "default"; +}; + +&i2c0 { + status = "okay"; + pinctrl-0 = <&i2c0_scl_default + &i2c0_sda_default>; + clock-frequency = <100000>; + pinctrl-names = "default"; +}; + +&spi0 { + status = "okay"; + pinctrl-0 = <&spi0_sck_default + &spi0_mosi_default + &spi0_miso_default + &spi0_cs_default>; + pinctrl-1 = <&spi0_sck_sleep + &spi0_mosi_sleep + &spi0_miso_sleep + &spi0_cs_sleep>; + pinctrl-names = "default", "sleep"; + cs-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>; + + mx25r80: mx25r8035f@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <12000000>; + size = <0x800000>; + jedec-id = [c2 28 14]; + sfdp-bfp = [e5 20 f1 ff ff ff 7f 00 44 eb 08 6b 08 3b 04 bb + ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 + 10 d8 00 ff 23 72 f5 00 82 ed 04 b7 44 83 38 44 + 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff]; + }; +}; + +&spi1 { + status = "okay"; + pinctrl-0 = <&spi1_sck_default + &spi1_mosi_default + &spi1_miso_default + &spi1_cs_default>; + pinctrl-1 = <&spi1_sck_sleep + &spi1_mosi_sleep + &spi1_miso_sleep + &spi1_cs_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&aes { + status = "okay"; +}; + +&dma { + status = "okay"; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_ch3 + &adc0_ch4 + &adc0_ch5 + &adc0_ch6 + &adc0_ch7 + &adc0_ch8>; + pinctrl-names = "default"; +}; + +&wdt0 { + status = "okay"; +}; + +&rng { + status = "okay"; +}; diff --git a/boards/ti/lp_em_cc2755p10/lp_em_cc2755p10.yaml b/boards/ti/lp_em_cc2755p10/lp_em_cc2755p10.yaml new file mode 100644 index 000000000000..421914842c37 --- /dev/null +++ b/boards/ti/lp_em_cc2755p10/lp_em_cc2755p10.yaml @@ -0,0 +1,31 @@ +identifier: lp_em_cc2755p10 +name: TI SimpleLink CC2755P10 LaunchPad +type: mcu +arch: arm +ram: 162 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - dma + - crypto + - spi + - i2s + - adc + - pm + - pwm + - watchdog + - counter + - rtc + - nvs + - entropy + - flash + - pinctrl + - serial + - timer + - i2c + - uart +vendor: ti diff --git a/boards/ti/lp_em_cc2755p10/lp_em_cc2755p10_defconfig b/boards/ti/lp_em_cc2755p10/lp_em_cc2755p10_defconfig new file mode 100644 index 000000000000..12f3a1dda58d --- /dev/null +++ b/boards/ti/lp_em_cc2755p10/lp_em_cc2755p10_defconfig @@ -0,0 +1,17 @@ +# Copyright (c) 2026 Texas Instruments Incorporated +# Copyright (c) 2024 BayLibre, SAS +# +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_GPIO=y +CONFIG_SERIAL=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_BT_HCI_ACL_FLOW_CONTROL=n + +CONFIG_PM=y + +CONFIG_MBEDTLS=y +CONFIG_MBEDTLS_PSA_CRYPTO_C=y diff --git a/boards/ti/lp_em_cc2755p20/Kconfig b/boards/ti/lp_em_cc2755p20/Kconfig new file mode 100644 index 000000000000..188487967724 --- /dev/null +++ b/boards/ti/lp_em_cc2755p20/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2026 Texas Instruments Incorporated +# +# SPDX-License-Identifier: Apache-2.0 + +rsource "../lpf3_common/Kconfig" diff --git a/boards/ti/lp_em_cc2755p20/Kconfig.defconfig b/boards/ti/lp_em_cc2755p20/Kconfig.defconfig new file mode 100644 index 000000000000..6e6120b2fe2b --- /dev/null +++ b/boards/ti/lp_em_cc2755p20/Kconfig.defconfig @@ -0,0 +1,28 @@ +# Copyright (c) 2026 Texas Instruments Incorporated +# +# SPDX-License-Identifier: Apache-2.0 + +rsource "../lpf3_common/Kconfig.defconfig" + +if BOARD_LP_EM_CC2755P20 + +if BT +config BT_LL_HEAP_SIZE + hex + default 0x4E00 +endif # BT + +if PM +# Power Management requires increased idle task stack size because of +# stack usage introduced by "pm_state_set" +config IDLE_STACK_SIZE + default 320 +endif # PM + +# The SPI driver only supports DMA mode +if SPI +config SPI_CC23X0_CC27XX_DMA_DRIVEN + default y +endif # SPI + +endif # BOARD_LP_EM_CC2755P20 diff --git a/boards/ti/lp_em_cc2755p20/Kconfig.lp_em_cc2755p20 b/boards/ti/lp_em_cc2755p20/Kconfig.lp_em_cc2755p20 new file mode 100644 index 000000000000..63c999e37e50 --- /dev/null +++ b/boards/ti/lp_em_cc2755p20/Kconfig.lp_em_cc2755p20 @@ -0,0 +1,6 @@ +# Copyright (c) 2026 Texas Instruments Incorporated +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LP_EM_CC2755P20 + select SOC_CC2755P20 if BOARD_LP_EM_CC2755P20 diff --git a/boards/ti/lp_em_cc2755p20/board.cmake b/boards/ti/lp_em_cc2755p20/board.cmake new file mode 100644 index 000000000000..778efb8f7128 --- /dev/null +++ b/boards/ti/lp_em_cc2755p20/board.cmake @@ -0,0 +1,10 @@ +# Copyright (c) 2026 Texas Instruments Incorporated +# Copyright (c) 2024 BayLibre, SAS +# +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=CC2755P20") +board_runner_args(openocd --cmd-pre-init "source [find board/ti_lp_em_cc2755P20.cfg]") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/ti_openocd.board.cmake) diff --git a/boards/ti/lp_em_cc2755p20/board.yml b/boards/ti/lp_em_cc2755p20/board.yml new file mode 100644 index 000000000000..5cac89b7601f --- /dev/null +++ b/boards/ti/lp_em_cc2755p20/board.yml @@ -0,0 +1,6 @@ +board: + name: lp_em_cc2755p20 + full_name: CC2755P20 LaunchPad + vendor: ti + socs: + - name: cc2755p20 diff --git a/boards/ti/lp_em_cc2755p20/boosterpack_connector.dtsi b/boards/ti/lp_em_cc2755p20/boosterpack_connector.dtsi new file mode 100644 index 000000000000..9c7f696e7f0d --- /dev/null +++ b/boards/ti/lp_em_cc2755p20/boosterpack_connector.dtsi @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2026 Texas Instruments Incorporated + * Copyright (c) 2024 BayLibre, SAS + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + boosterpack_header: connector { + compatible = "ti,boosterpack-header"; + #gpio-cells = <2>; + gpio-map = <2 0 &gpio0 21 0>, + <3 0 &gpio0 2 0>, + <4 0 &gpio0 1 0>, + <5 0 &gpio0 23 0>, + <6 0 &gpio0 22 0>, + <7 0 &gpio0 3 0>, + <8 0 &gpio0 24 0>, + <9 0 &gpio0 27 0>, + <10 0 &gpio0 28 0>, + <14 0 &gpio0 4 0>, + <15 0 &gpio0 5 0>, + <18 0 &gpio0 7 0>, + <19 0 &gpio0 12 0>, + <27 0 &gpio0 18 0>, + <28 0 &gpio0 17 0>, + <29 0 &gpio0 19 0>, + <30 0 &gpio0 20 0>, + <31 0 &gpio0 18 0>, + <32 0 &gpio0 17 0>, + <33 0 &gpio0 10 0>, + <34 0 &gpio0 9 0>, + <35 0 &gpio0 15 0>, + <36 0 &gpio0 16 0>, + <38 0 &gpio0 19 0>, + <39 0 &gpio0 11 0>, + <40 0 &gpio0 0 0>; + }; +}; diff --git a/boards/ti/lp_em_cc2755p20/doc/index.rst b/boards/ti/lp_em_cc2755p20/doc/index.rst new file mode 100644 index 000000000000..9d98e63d634e --- /dev/null +++ b/boards/ti/lp_em_cc2755p20/doc/index.rst @@ -0,0 +1,103 @@ +.. _lp_em_cc2755p20: + +TI CC2755P20 Launchpad +######################### + +Overview +******** + +The Texas Instruments CC2755P20 LaunchPad |trade| (LP_EM_CC2755P20) is a +development kit for the SimpleLink |trade| multi-Standard CC2755P20 wireless MCU. + +Hardware +******** + +The CC2755P20 LaunchPad |trade| development kit features the CC2755P20 wireless MCU. +The board is equipped with two LEDs, two push buttons and BoosterPack connectors +for expansion. + +The CC2755P20 wireless MCU has a 96 MHz Arm |reg| Cortex |reg|-M33 SoC and an +integrated 2.4 GHz transceiver supporting multiple protocols including Bluetooth +|reg| Low Energy and IEEE |reg| 802.15.4. + +The CC2755P20 wireless MCU supports additional protocols such as Matter, Thread, and Zigbee. + +Supported Features +================== + +The CC2755P20 LaunchPad board configuration supports the following hardware +features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| UART | on-chip | uart | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. + +Connections and IOs +=================== + +All I/O signals are accessible from the BoosterPack connectors. Pin function +aligns with the LaunchPad standard. + ++-------+-----------+-------------------------+ +| Pin | Function | Usage | ++=======+===========+=========================+ +| DIO0 | GPIO | Button 2 | ++-------+-----------+-------------------------+ +| DIO1 | UART_TX | UART TX | ++-------+-----------+-------------------------+ +| DIO2 | UART_RX | UART RX | ++-------+-----------+-------------------------+ +| DIO3 | SPI_CLK | SPI CLK | ++-------+-----------+-------------------------+ +| DIO4 | SPI_POCI | SPI POCI | ++-------+-----------+-------------------------+ +| DIO5 | SPI_PICO | SPI PICO | ++-------+-----------+-------------------------+ +| DIO7 | SPI_CSN | SPI CS | ++-------+-----------+-------------------------+ +| DIO9 | SWD_IO | SWD IO | ++-------+-----------+-------------------------+ +| DIO10 | SWD_CK | SWD CK | ++-------+-----------+-------------------------+ +| DIO11 | GPIO | | ++-------+-----------+-------------------------+ +| DIO12 | GPIO | Green LED | ++-------+-----------+-------------------------+ +| DIO16 | GPIO | RED LED | ++-------+-----------+-------------------------+ +| DIO17 | ANALOG_IO | CAN TX / A8 | ++-------+-----------+-------------------------+ +| DIO18 | ANALOG_IO | CAN RX / A7 | ++-------+-----------+-------------------------+ +| DIO19 | ANALOG_IO | I2S SDO / A6 | ++-------+-----------+-------------------------+ +| DIO20 | ANALOG_IO | I2C SDI / A5 / Button 1 | ++-------+-----------+-------------------------+ +| DIO21 | ANALOG_IO | A4 | ++-------+-----------+-------------------------+ +| DIO22 | ANALOG_IO | A3 | ++-------+-----------+-------------------------+ +| DIO23 | GPIO | | ++-------+-----------+-------------------------+ +| DIO24 | GPIO | | ++-------+-----------+-------------------------+ +| DIO27 | I2C_SCL | I2C SCL | ++-------+-----------+-------------------------+ +| DIO28 | I2C_SDA | I2C SDA | ++-------+-----------+-------------------------+ + +Programming and Debugging +************************* + +The LP_EM_CC2755P20 requires an external debug probe such as the LP-XDS110 or +LP-XDS110ET. + +Currently there is no debug support in Zephyr for the LP_EM_CC2755P20, and the +built binaries for this target must be flashed/debugged using either Uniflash or +Code Composer Studio. diff --git a/boards/ti/lp_em_cc2755p20/lp_em_cc2755p20-pinctrl.dtsi b/boards/ti/lp_em_cc2755p20/lp_em_cc2755p20-pinctrl.dtsi new file mode 100644 index 000000000000..5109b29c01a5 --- /dev/null +++ b/boards/ti/lp_em_cc2755p20/lp_em_cc2755p20-pinctrl.dtsi @@ -0,0 +1,268 @@ +/* + * Copyright (c) 2026 Texas Instruments Incorporated + * Copyright (c) 2024 BayLibre, SAS + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + /* UART0 */ + uart0_tx_default: uart0_tx_default { + pinmux = <1 DIO1_UART0_TXD>; + bias-disable; + }; + + uart0_rx_default: uart0_rx_default { + pinmux = <2 DIO2_UART0_RXD>; + bias-disable; + input-enable; + }; + + /* UART1 */ + uart1_tx_default: uart1_tx_default { + pinmux = <21 DIO21_UART1_TXD>; + bias-disable; + }; + + uart1_rx_default: uart1_rx_default { + pinmux = <22 DIO22_UART1_RXD>; + bias-disable; + input-enable; + }; + + /* I2C0 */ + /* Change to DIO11 if adc0_ch1 is used */ + i2c0_scl_default: i2c0_scl_default { + pinmux = <27 DIO27_I2C0_SCL>; + bias-pull-up; + drive-open-drain; + input-enable; + }; + + /* Change to DIO12 if adc0_ch0 is used */ + i2c0_sda_default: i2c0_sda_default { + pinmux = <28 DIO28_I2C0_SDA>; + bias-pull-up; + drive-open-drain; + input-enable; + }; + + /* SPI0 */ + spi0_sck_default: spi0_sck_default { + pinmux = <3 DIO3_SPI0_SCLK>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_mosi_default: spi0_mosi_default { + pinmux = <5 DIO5_SPI0_PICO>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_miso_default: spi0_miso_default { + pinmux = <4 DIO4_SPI0_POCI>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_cs_default: spi0_cs_default { + pinmux = <19 DIO19_GPIO19>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_sck_sleep: spi0_sck_sleep { + pinmux = <3 DIO3_GPIO3>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_mosi_sleep: spi0_mosi_sleep { + pinmux = <5 DIO5_GPIO5>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_miso_sleep: spi0_miso_sleep { + pinmux = <4 DIO4_GPIO4>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_cs_sleep: spi0_cs_sleep { + pinmux = <19 DIO19_GPIO19>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi0_flash_cs: spi0_flash_cs { + pinmux = <19 DIO19_GPIO19>; + bias-pull-up; + }; + + /* SPI1 */ + spi1_sck_default: spi1_sck_default { + pinmux = <15 DIO15_SPI1_SCLK>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi1_mosi_default: spi1_mosi_default { + pinmux = <11 DIO11_SPI1_PICO>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi1_miso_default: spi1_miso_default { + pinmux = <12 DIO12_SPI1_POCI>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi1_cs_default: spi1_cs_default { + pinmux = <16 DIO16_GPIO16>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi1_sck_sleep: spi1_sck_sleep { + pinmux = <15 DIO15_GPIO15>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi1_mosi_sleep: spi1_mosi_sleep { + pinmux = <11 DIO11_GPIO11>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi1_miso_sleep: spi1_miso_sleep { + pinmux = <12 DIO12_GPIO12>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + spi1_cs_sleep: spi1_cs_sleep { + pinmux = <16 DIO16_GPIO16>; + input-enable; + input-schmitt-enable; + bias-disable; + }; + + /* ADC channels. */ + + adc0_ch0: adc0_ch0 { + pinmux = <28 DIO28_ADC0_AREFM>; + bias-disable; + input-enable; + }; + + adc0_ch1: adc0_ch1 { + pinmux = <27 DIO27_ADC1_AREFP>; + bias-disable; + input-enable; + }; + + adc0_ch3: adc0_ch3 { + pinmux = <22 DIO22_ADC3>; + bias-disable; + input-enable; + }; + + adc0_ch4: adc0_ch4 { + pinmux = <21 DIO21_ADC4_LPCP_LPCM>; + bias-disable; + input-enable; + }; + + adc0_ch5: adc0_ch5 { + pinmux = <20 DIO20_ADC5_LPCP_LPCM>; + bias-disable; + input-enable; + }; + + adc0_ch6: adc0_ch6 { + pinmux = <19 DIO19_ADC6_LPCP>; + bias-disable; + input-enable; + }; + + adc0_ch7: adc0_ch7 { + pinmux = <18 DIO18_ADC7>; + bias-disable; + input-enable; + }; + + adc0_ch8: adc0_ch8 { + pinmux = <17 DIO17_ADC8>; + bias-disable; + input-enable; + }; + + /* I2S0: DIO16=MCLK, DIO17=SCLK, DIO18=WS, DIO19=SD0(TX), DIO20=SD1(RX) */ + i2s0_mclk_default: i2s0_mclk_default { + pinmux = <16 DIO16_I2S0_MCLK>; + bias-disable; + }; + + /* I2S0: DIO17=SCLK, DIO18=WS, DIO19=SD0(TX), DIO20=SD1(RX) + * Reference: <&i2s0_sclk_default &i2s0_ws_default + * &i2s0_sd0_default &i2s0_sd1_default> + * NOTE: All pins need input-enable (HW samples own outputs for sync) + */ + i2s0_sclk_default: i2s0_sclk_default { + pinmux = <17 DIO17_I2S0_SCLK>; + bias-disable; + input-enable; + }; + + i2s0_ws_default: i2s0_ws_default { + pinmux = <18 DIO18_I2S0_WS>; + bias-disable; + input-enable; + }; + + i2s0_sd0_default: i2s0_sd0_default { + pinmux = <19 DIO19_I2S0_SD0>; + bias-disable; + input-enable; + }; + + i2s0_sd1_default: i2s0_sd1_default { + pinmux = <20 DIO20_I2S0_SD1>; + bias-disable; + input-enable; + }; + + /* LGPT3 ch0 output (DIO28, T3_C0N) */ + pwm9_default: lgpt3_chan0_default { + pinmux = <28 DIO28_T3_C0N>; + bias-disable; + }; + + /* LGPT0 ch0 capture input (DIO0, T0_C0) */ + pwm0_capture: lgpt0_chan0_capture { + pinmux = <0 DIO0_T0_C0>; + bias-disable; + input-enable; + }; +}; diff --git a/boards/ti/lp_em_cc2755p20/lp_em_cc2755p20.dts b/boards/ti/lp_em_cc2755p20/lp_em_cc2755p20.dts new file mode 100644 index 000000000000..07ebbf40e2ff --- /dev/null +++ b/boards/ti/lp_em_cc2755p20/lp_em_cc2755p20.dts @@ -0,0 +1,195 @@ +/* + * Copyright (c) 2026 Texas Instruments Incorporated + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "boosterpack_connector.dtsi" +#include "lp_em_cc2755p20-pinctrl.dtsi" +#include +#include + +#define BTN_GPIO_FLAGS (GPIO_ACTIVE_LOW | GPIO_PULL_UP) + +/ { + model = "TI CC2755P20 LaunchPad "; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,bt_hci = &ti_bt_hci; + zephyr,bt-c2h-uart = &uart0; + zephyr,code-partition = &slot0_partition; + zephyr,uart-mcumgr = &uart0; + }; + + aliases { + led0 = &led0; + led1 = &led1; + sw0 = &btn0; + sw1 = &btn1; + }; + + leds { + compatible = "gpio-leds"; + + led0: led_0 { + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + label = "Green LED"; + }; + + led1: led_1 { + gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + label = "Red LED"; + }; + }; + + keys { + compatible = "gpio-keys"; + + btn0: btn_0 { + gpios = <&gpio0 20 BTN_GPIO_FLAGS>; + label = "Button 1"; + zephyr,code = ; + }; + + btn1: btn_1 { + gpios = <&gpio0 0 BTN_GPIO_FLAGS>; + label = "Button 2"; + zephyr,code = ; + }; + }; + + lfxosc: lf_xosc { + compatible = "ti,cc27xx-lf-xosc"; + }; + + ti_bt_hci: ti_bt_hci { + compatible = "ti,bt-hci"; + status = "okay"; + }; +}; + +/delete-node/ &slot0_partition; + +&flash0 { + partitions { + /* 40 KiB (0xa000) for MCUboot */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x0000a000>; + }; + + /* 233472 Bytes (0x39000) per slot for application */ + slot0_partition: partition@a000 { + label = "image-0"; + reg = <0x0000a000 0x0006d000>; + }; + + slot1_partition: partition@77000 { + label = "image-1"; + reg = <0x00077000 0x0006d000>; + }; + }; +}; + +&cpu0 { + clock-frequency = <96000000>; +}; + +&gpio0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_rx_default &uart0_tx_default>; + pinctrl-names = "default"; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart1_rx_default &uart1_tx_default>; + pinctrl-names = "default"; +}; + +&i2c0 { + status = "okay"; + pinctrl-0 = <&i2c0_scl_default + &i2c0_sda_default>; + clock-frequency = <100000>; + pinctrl-names = "default"; +}; + +&spi0 { + status = "okay"; + pinctrl-0 = <&spi0_sck_default + &spi0_mosi_default + &spi0_miso_default + &spi0_cs_default>; + pinctrl-1 = <&spi0_sck_sleep + &spi0_mosi_sleep + &spi0_miso_sleep + &spi0_cs_sleep>; + pinctrl-names = "default", "sleep"; + cs-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>; + + mx25r80: mx25r8035f@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <12000000>; + size = <0x800000>; + jedec-id = [c2 28 14]; + sfdp-bfp = [e5 20 f1 ff ff ff 7f 00 44 eb 08 6b 08 3b 04 bb + ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 + 10 d8 00 ff 23 72 f5 00 82 ed 04 b7 44 83 38 44 + 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff]; + }; +}; + +&spi1 { + status = "okay"; + pinctrl-0 = <&spi1_sck_default + &spi1_mosi_default + &spi1_miso_default + &spi1_cs_default>; + pinctrl-1 = <&spi1_sck_sleep + &spi1_mosi_sleep + &spi1_miso_sleep + &spi1_cs_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&dma { + status = "okay"; +}; + +&aes { + status = "okay"; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_ch3 + &adc0_ch4 + &adc0_ch5 + &adc0_ch6 + &adc0_ch7 + &adc0_ch8>; + pinctrl-names = "default"; +}; + +&wdt0 { + status = "okay"; +}; + +&rng { + status = "okay"; +}; diff --git a/boards/ti/lp_em_cc2755p20/lp_em_cc2755p20.yaml b/boards/ti/lp_em_cc2755p20/lp_em_cc2755p20.yaml new file mode 100644 index 000000000000..2635e82fe072 --- /dev/null +++ b/boards/ti/lp_em_cc2755p20/lp_em_cc2755p20.yaml @@ -0,0 +1,31 @@ +identifier: lp_em_cc2755p20 +name: TI SimpleLink CC2755P20 LaunchPad +type: mcu +arch: arm +ram: 288 +flash: 2048 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - dma + - crypto + - spi + - i2s + - adc + - pm + - pwm + - watchdog + - counter + - rtc + - nvs + - entropy + - flash + - pinctrl + - serial + - timer + - i2c + - uart +vendor: ti diff --git a/boards/ti/lp_em_cc2755p20/lp_em_cc2755p20_defconfig b/boards/ti/lp_em_cc2755p20/lp_em_cc2755p20_defconfig new file mode 100644 index 000000000000..12f3a1dda58d --- /dev/null +++ b/boards/ti/lp_em_cc2755p20/lp_em_cc2755p20_defconfig @@ -0,0 +1,17 @@ +# Copyright (c) 2026 Texas Instruments Incorporated +# Copyright (c) 2024 BayLibre, SAS +# +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_GPIO=y +CONFIG_SERIAL=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_BT_HCI_ACL_FLOW_CONTROL=n + +CONFIG_PM=y + +CONFIG_MBEDTLS=y +CONFIG_MBEDTLS_PSA_CRYPTO_C=y diff --git a/boards/ti/lp_em_cc35x1/CMakeLists.txt b/boards/ti/lp_em_cc35x1/CMakeLists.txt new file mode 100644 index 000000000000..38828ef1fae5 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/CMakeLists.txt @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() +zephyr_library_sources(shared_mem.c) diff --git a/boards/ti/lp_em_cc35x1/Kconfig.lp_em_cc35x1 b/boards/ti/lp_em_cc35x1/Kconfig.lp_em_cc35x1 new file mode 100644 index 000000000000..6574430eca66 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/Kconfig.lp_em_cc35x1 @@ -0,0 +1,10 @@ +# TI CC35X1 LaunchPad board +# Copyright (c) 2025 Conclusive Engineering Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LP_EM_CC35X1 + bool + select SOC_CC3500E if BOARD_LP_EM_CC35X1_CC3500E + select SOC_CC3501E if BOARD_LP_EM_CC35X1_CC3501E + select SOC_CC3550E if BOARD_LP_EM_CC35X1_CC3550E + select SOC_CC3551E if BOARD_LP_EM_CC35X1_CC3551E diff --git a/boards/ti/lp_em_cc35x1/board.cmake b/boards/ti/lp_em_cc35x1/board.cmake new file mode 100644 index 000000000000..e32d8525a739 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/board.cmake @@ -0,0 +1,7 @@ +# Copyright (c) 2025 Conclusive Engineering Sp. z o.o. +# +# SPDX-License-Identifier: Apache-2.0 + +set(BOARD_DIR ${CMAKE_CURRENT_LIST_DIR}) + +include(${ZEPHYR_BASE}/boards/common/simplelink_toolbox.board.cmake) diff --git a/boards/ti/lp_em_cc35x1/board.yml b/boards/ti/lp_em_cc35x1/board.yml new file mode 100644 index 000000000000..1ce99b67bcf0 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/board.yml @@ -0,0 +1,9 @@ +board: + name: lp_em_cc35x1 + full_name: CC35x1 LaunchPad + vendor: ti + socs: + - name: cc3500e + - name: cc3501e + - name: cc3550e + - name: cc3551e diff --git a/boards/ti/lp_em_cc35x1/boosterpack_connector.dtsi b/boards/ti/lp_em_cc35x1/boosterpack_connector.dtsi new file mode 100644 index 000000000000..d68963facc2a --- /dev/null +++ b/boards/ti/lp_em_cc35x1/boosterpack_connector.dtsi @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2026 Conclusive Engineering Sp. z o.o. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + boosterpack_header: connector { + compatible = "ti,boosterpack-header"; + #gpio-cells = <2>; + gpio-map = <3 0 &gpios 18 0>, /* UART0_RX */ + <4 0 &gpios 17 0>, /* UART0_TX */ + <5 0 &gpios 10 0>, /* I2C1_DATA */ + <6 0 &gpios 11 0>, /* I2C1_CLK */ + <7 0 &gpios 27 0>, /* SPI0_CLK */ + <8 0 &gpios 14 0>, /* SPI1_CLK */ + <9 0 &gpios 33 0>, /* I2C0_CLK */ + <10 0 &gpios 32 0>, /* I2C0_DATA */ + <11 0 &gpios 15 0>, /* SPI1_MISO */ + <12 0 &gpios 12 0>, /* SPI1_CS */ + <13 0 &gpios 13 0>, /* SPI1_MOSI */ + <14 0 &gpios 28 0>, /* SPI0_MISO */ + <15 0 &gpios 29 0>, /* SPI0_MOSI */ + <17 0 &gpios 30 0>, /* PWM / Green LED */ + <18 0 &gpios 26 0>, /* SPI0_CS */ + <19 0 &gpios 2 0>, /* Button 1 */ + <25 0 &gpios 4 0>, /* ADC4 */ + <26 0 &gpios 3 0>, /* ADC5 */ + <30 0 &gpios 31 0>, /* I2S_DATA1 */ + <31 0 &gpios 34 0>, /* CAN_RX / Red LED */ + <32 0 &gpios 30 0>, /* CAN_TX */ + <36 0 &gpios 35 0>, /* Blue LED */ + <37 0 &gpios 16 0>, /* UART0_RTS */ + <38 0 &gpios 19 0>, /* UART0_CTS */ + <40 0 &gpios 36 0>; /* Button 2 */ + }; +}; + +boosterpack_serial: &uart0 {}; diff --git a/boards/ti/lp_em_cc35x1/config/action_params.json b/boards/ti/lp_em_cc35x1/config/action_params.json new file mode 100644 index 000000000000..238f095917b7 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/action_params.json @@ -0,0 +1,137 @@ +{ + "programming": { + "header_version": 1, + "udid": "", + "pub_key": "", + "payload_param": { + "type_version": 0, + "payload": { + "prog_req_content": { + "fuse_programming_instruction_update": false, + "flash_factory_reset": false, + "boot_sector": false, + "primary_tbl": false, + "secondary_tbl": false, + "primary_vendor_image": true, + "primary_vendor_sbl": false, + "secondary_vendor_image": false, + "secondary_vendor_sbl": false, + "primary_ti_wsoc": false, + "secondary_ti_wsoc": false, + "primary_ti_wsoc_bl2": false, + "secondary_ti_wsoc_bl2": false, + "protected_storage": false + }, + "prog_validation": { + "fuse_programming_instruction_update": false, + "flash_factory_reset": false, + "boot_sector": false, + "primary_tbl": false, + "secondary_tbl": false, + "primary_vendor_image": false, + "primary_vendor_sbl": false, + "secondary_vendor_image": false, + "secondary_vendor_sbl": false, + "primary_ti_wsoc": false, + "secondary_ti_wsoc": false, + "primary_ti_wsoc_bl2": false, + "secondary_ti_wsoc_bl2": false, + "protected_storage": false + } + } + } + }, + "query": { + "header_version": 1, + "udid": "", + "pub_key": "", + "payload_param": { + "type_version": 0, + "payload": { + "query_req_content": { + "boot_sector_query": true, + "primary_ti_bootloader_query": true, + "secondary_ti_bootloader_query": false, + "primary_vendor_image_query": false, + "primary_vendor_sbl_query": false, + "secondary_vendor_image_query": false, + "secondary_vendor_sbl_query": false, + "primary_ti_wsoc_query": false, + "secondary_ti_wsoc_query": false, + "primary_ti_wsoc_bl2_query": false, + "secondary_ti_wsoc_bl2_query": false, + "protected_storage_query": false + } + } + } + }, + "debug": { + "header_version": 1, + "udid": "", + "pub_key": "", + "payload_param": { + "type_version": 0, + "payload": { + "vendor_debug_bypass": { + "efuse_crc_validation_bypass": false, + "otfde_protection_bypass": true, + "second_container_validation_bypass": true, + "rollback_validation_bypass": false, + "security_policy_bypass": false, + "security_Failure_Behavioral_bypass": false, + "primary_rot_switching_to_secondary_bypass": false, + "crc_efuse_validation_bypass": false, + "non_crc_efuse_validation_otp_bypass": false, + "non_crc_efuse_mismatch_bypass": false, + "soc_boot_configurations_bypass": false, + "host_boot_configurations_bypass": false, + "soc_security_configuration_bypass": false, + "host_security_configuration_bypass": false, + "host_services_irq_configurations_bypass": false, + "full_open_all_vendors_debug": false, + "full_open_vendors_all_ns_debug": false, + "full_open_vendors_all_s_debug": false, + "partial_open_all_vendors_debug": false, + "partial_open_vendors_all_ns_debug": false, + "partial_open_vendors_all_s_debug": false + }, + "vendor_efuse_crc_validation_bypass": { + "m33_halt_or_run": "halt", + "clear_errors_scratchpad": false + }, + "vendors_hide_and_lock_policy_instructions": { + "host_boot_done_set_bypass": false, + "host_peripherals_lock_set_bypass": false, + "icache_configurations_lock_set_bypass": false, + "m33_memory_partitioning_lock_set_bypass": false, + "memss_mode_and_firewall_lock_set_bypass": false, + "dma_channel_owner_lock_set_bypass": false, + "core_events_lock_set_bypass": false, + "otfde_region_lock_bypass": false + } + } + } + }, + "enter_rma": { + "header_version": 1, + "udid": "", + "pub_key": "", + "payload_param": { + "type_version": 0, + "payload": { + "enter_rma_option": { + "invalidate_vendor_rot_fuses": false, + "invalidate_other_vendor_fuses": false, + "invalidate_all_vendor_components": false, + "invalidate_internal_memory": false + }, + "enter_rma_validation": { + "invalidate_vendor_rot_fuses_validate": false, + "invalidate_other_vendor_fuses_validate": false, + "invalidate_all_vendor_components_validate": false, + "invalidate_internal_memory_validate": false + } + } + } + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/gd25lf32e/flash_disc_param_ext_mem.json b/boards/ti/lp_em_cc35x1/config/flash/gd25lf32e/flash_disc_param_ext_mem.json new file mode 100644 index 000000000000..321810768be1 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/gd25lf32e/flash_disc_param_ext_mem.json @@ -0,0 +1,99 @@ +{ + "vendor_primary_sbl": true, + "ti_wsoc_primary_container": true, + "ti_wsoc_bl2_primary_container": true, + "nvs_enable": true, + "vendor_alternate_image": true, + "vendor_sbl_alternate_image": true, + "ti_bl_alternate_image": true, + "ti_wsoc_alternate_image": true, + "ti_wsoc_bl2_alternate_image": true, + "region_0": { + "mem_region_0_start_phy_address": 1069056, + "mem_region_0_end_phy_address": 4194303, + "region0_boot": false, + "region0_main_code": true, + "region0_nvs": false, + "region0_wsoc_code": false, + "region0_alternate_code": false + }, + "region_1": { + "mem_region_1_start_phy_address": 0, + "mem_region_1_end_phy_address": 1069055, + "region1_boot": true, + "region1_main_code": false, + "region1_nvs": true, + "region1_wsoc_code": true, + "region1_alternate_code": false + }, + "region_2": { + "mem_region_2_start_phy_address": 0, + "mem_region_2_end_phy_address": 0, + "region2_boot": false, + "region2_main_code": false, + "region2_nvs": false, + "region2_wsoc_code": false, + "region2_alternate_code": true + }, + "region_3": { + "mem_region_3_start_phy_address": 0, + "mem_region_3_end_phy_address": 0, + "region3_boot": false, + "region3_main_code": false, + "region3_nvs": false, + "region3_wsoc_code": false, + "region3_alternate_code": false + }, + "boot_region_conf": { + "boot_region_size": 0, + "boot_region_flash_disco_param_start_address": 0, + "boot_region_primary_ti_bl_start_phy_address": 12284, + "boot_region_primary_ti_bl_magic": 0, + "boot_region_primary_ti_bl_major": 0, + "boot_region_primary_ti_bl_minor": 0, + "boot_region_sec_ti_bl_start_phy_address": 430076, + "boot_region_sec_ti_bl_magic": 0, + "boot_region_sec_ti_bl_major": 0, + "boot_region_sec_ti_bl_minor": 0 + }, + "main_code_region_conf": { + "main_code_region_vendor_image_start_phy_address": 1073148, + "main_code_region_vendor_image_magic": 0, + "main_code_region_vendor_image_major": 0, + "main_code_region_vendor_image_minor": 0, + "main_code_region_sbl_start_phy_address": 0, + "main_code_region_sbl_magic": 0, + "main_code_region_sbl_major": 0, + "main_code_region_sbl_minor": 0 + }, + "alt_code_region_conf": { + "alt_code_region_vendor_image_start_phy_address": 4194304, + "alt_code_region_vendor_image_magic": 0, + "alt_code_region_vendor_image_major": 0, + "alt_code_region_vendor_image_minor": 0, + "alt_code_region_sbl_start_phy_address": 0, + "alt_code_region_sbl_magic": 0, + "alt_code_region_sbl_major": 0, + "alt_code_region_sbl_minor": 0 + }, + "nvs_code_region_conf": { + "nvs_start_phy_address": 892928, + "nvs_region_size": 176128, + "nvs_region_primary_wsoc_start_phy_address": 430076, + "nvs_region_primary_wsoc_magic": 0, + "nvs_region_primary_wsoc_major": 0, + "nvs_region_primary_wsoc_minor": 0, + "nvs_region_sec_wsoc_start_phy_address": 897020, + "nvs_region_sec_wsoc_magic": 0, + "nvs_region_sec_wsoc_major": 0, + "nvs_region_sec_wsoc_minor": 0, + "nvs_region_primary_wsoc_bl2_start_phy_address": 0, + "nvs_region_primary_wsoc_bl2_magic": 0, + "nvs_region_primary_wsoc_bl2_major": 0, + "nvs_region_primary_wsoc_bl2_minor": 0, + "nvs_region_sec_wsoc_bl2_start_phy_address": 0, + "nvs_region_sec_wsoc_bl2_magic": 0, + "nvs_region_sec_wsoc_bl2_major": 0, + "nvs_region_sec_wsoc_bl2_minor": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/gd25lf32e/flash_disc_param_otfde.json b/boards/ti/lp_em_cc35x1/config/flash/gd25lf32e/flash_disc_param_otfde.json new file mode 100644 index 000000000000..635e11319c5d --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/gd25lf32e/flash_disc_param_otfde.json @@ -0,0 +1,286 @@ +{ + "otfde_header": { + "name": "OTFDEWFF3", + "flash_only": true, + "ip_protection": false, + "regions_lock": false, + "regions_number": 4, + "flash_enabled": true + }, + "bl_conf": { + "host_boot_done_lock": true, + "host_peripherals_lock": true, + "icache_conf_lock": true, + "m33_mem_part_lock": true, + "memss_firewall_lock": true, + "dma_channel_owner_lock": true, + "otfde_region_lock": true, + "core_events_lock": true + }, + "otfde_general": { + "parameters": { + "mem_otfde_initial_delay": 10, + "otfde_global_watchdog_timer": 5 + }, + "events": { + "reset_evt_mask": false, + "reset_evt_suspend": false, + "sft_reset_evt_mask": false, + "sft_reset_evt_suspend": false, + "bypass_mode_evt_mask": false, + "bypass_mode_evt_suspend": false, + "debug_mode_evt_mask": false, + "debug_mode_evt_suspend": false, + "general_evt_mask": false, + "general_evt_suspend": false, + "xspi_data_path_evt_mask": false, + "xspi_data_path_evt_suspend": false, + "xspi_cnfg_path_evt_mask": false, + "xspi_cnfg_path_evt_suspend": false, + "xspi_service_interrupt_evt_mask": false, + "xspi_service_interrupt_evt_suspend": false, + "trans_device_disabled_evt_mask": false, + "trans_device_disabled_evt_suspend": false, + "trans_region_disabled_evt_mask": false, + "trans_region_disabled_evt_suspend": false, + "trans_region_params_conf_evt_mask": false, + "trans_region_params_conf_evt_suspend": false, + "trans_multiple_regions_mapped_evt_mask": false, + "trans_multiple_regions_mapped_evt_suspend": false, + "trans_address_not_32_bit_evt_mask": false, + "trans_address_not_32_bit_evt_suspend": false, + "trans_size_not_32_bit_evt_mask": false, + "trans_size_not_32_bit_evt_suspend": false, + "trans_burst_not_32_bit_evt_mask": false, + "trans_burst_not_32_bit_evt_suspend": false, + "region_read_write_def_evt_mask": false, + "region_read_write_def_evt_suspend": false, + "suspend_while_disabled_evt_mask": false, + "suspend_while_disabled_evt_suspend": false + } + }, + "regions_settings": { + "region_parameters_lock": { + "REGION_0_PARAMS_0": true, + "REGION_0_PARAMS_1": true, + "REGION_0_PARAMS_2": true, + "REGION_1_PARAMS_0": false, + "REGION_1_PARAMS_1": false, + "REGION_1_PARAMS_2": false, + "REGION_2_PARAMS_0": true, + "REGION_2_PARAMS_1": true, + "REGION_2_PARAMS_2": true, + "REGION_3_PARAMS_0": false, + "REGION_3_PARAMS_1": false, + "REGION_3_PARAMS_2": false + }, + "region_0_protection": { + "mem_region_0_enabled": true, + "mem_region_0_device_id": 0, + "mem_region_0_spi_write_enable": true, + "mem_region_0_spi_read_enable": true, + "mem_region_0_physical_offset": 261, + "mem_region_0_security_id_msb": 0, + "mem_region_0_start_address": 81920, + "mem_region_0_end_address": 82682, + "mem_region_0_security_id_lsb": 0, + "mem_otfde_region_0_write_lock_en": false, + "mem_otfde_region_0_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_1_protection": { + "mem_region_1_enabled": true, + "mem_region_1_device_id": 0, + "mem_region_1_spi_write_enable": true, + "mem_region_1_spi_read_enable": true, + "mem_region_1_physical_offset": 0, + "mem_region_1_security_id_msb": 0, + "mem_region_1_start_address": 655360, + "mem_region_1_end_address": 655620, + "mem_region_1_security_id_lsb": 0, + "mem_otfde_region_1_write_lock_en": false, + "mem_otfde_region_1_enc_dec_bypass": "Bypass" + }, + "region_2_protection": { + "mem_region_2_enabled": false, + "mem_region_2_device_id": 0, + "mem_region_2_spi_write_enable": true, + "mem_region_2_spi_read_enable": true, + "mem_region_2_physical_offset": 0, + "mem_region_2_security_id_msb": 0, + "mem_region_2_start_address": 1, + "mem_region_2_end_address": 0, + "mem_region_2_security_id_lsb": 0, + "mem_otfde_region_2_write_lock_en": false, + "mem_otfde_region_2_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_3_protection": { + "mem_region_3_enabled": false, + "mem_region_3_device_id": 1, + "mem_region_3_spi_write_enable": true, + "mem_region_3_spi_read_enable": true, + "mem_region_3_physical_offset": 0, + "mem_region_3_security_id_msb": 0, + "mem_region_3_start_address": 1, + "mem_region_3_end_address": 0, + "mem_region_3_security_id_lsb": 0, + "mem_otfde_region_3_write_lock_en": false, + "mem_otfde_region_3_enc_dec_bypass": "Bypass" + } + }, + "devices": { + "header": { + "flash_device_switch_conf": 1, + "ram_device_switch_conf": 1 + }, + "flash_switch": { + "flash_grant_sel": 0, + "flash_data_for_conf_0": 2181562505, + "flash_offset_bits_for_conf_0": 0, + "flash_stop_bit_for_conf_0": 0, + "flash_data_for_conf_1": 67248651, + "flash_offset_bits_for_conf_1": 1, + "flash_stop_bit_for_conf_1": 0, + "flash_data_for_conf_2": 139266, + "flash_offset_bits_for_conf_2": 2, + "flash_stop_bit_for_conf_2": 0, + "flash_data_for_conf_3": 1, + "flash_offset_bits_for_conf_3": 4, + "flash_stop_bit_for_conf_3": 0, + "flash_data_for_conf_4": 1076887634, + "flash_offset_bits_for_conf_4": 45, + "flash_stop_bit_for_conf_4": 0, + "flash_data_for_conf_5": 3224371282, + "flash_offset_bits_for_conf_5": 45, + "flash_stop_bit_for_conf_5": 0, + "flash_data_for_conf_6": 262149, + "flash_offset_bits_for_conf_6": 14, + "flash_stop_bit_for_conf_6": 0, + "flash_data_for_conf_7": 0, + "flash_offset_bits_for_conf_7": 44, + "flash_stop_bit_for_conf_7": 1, + "flash_data_for_conf_8": 0, + "flash_offset_bits_for_conf_8": 0, + "flash_stop_bit_for_conf_8": 1, + "flash_data_for_conf_9": 0, + "flash_offset_bits_for_conf_9": 0, + "flash_stop_bit_for_conf_9": 1, + "flash_data_for_conf_10": 0, + "flash_offset_bits_for_conf_10": 0, + "flash_stop_bit_for_conf_10": 1, + "flash_data_for_conf_11": 0, + "flash_offset_bits_for_conf_11": 0, + "flash_stop_bit_for_conf_11": 1, + "flash_data_for_conf_12": 0, + "flash_offset_bits_for_conf_12": 0, + "flash_stop_bit_for_conf_12": 1, + "flash_data_for_conf_13": 0, + "flash_offset_bits_for_conf_13": 0, + "flash_stop_bit_for_conf_13": 1, + "flash_data_for_conf_14": 0, + "flash_offset_bits_for_conf_14": 0, + "flash_stop_bit_for_conf_14": 1, + "flash_data_for_conf_15": 0, + "flash_offset_bits_for_conf_15": 0, + "flash_stop_bit_for_conf_15": 1, + "flash_data_for_conf_16": 0, + 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"ram_offset_bits_for_conf_21": 0, + "ram_stop_bit_for_conf_21": 1, + "ram_data_for_conf_22": 0, + "ram_offset_bits_for_conf_22": 0, + "ram_stop_bit_for_conf_22": 1, + "ram_data_for_conf_23": 0, + "ram_offset_bits_for_conf_23": 0, + "ram_stop_bit_for_conf_23": 1 + } + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/gd25lf32e/flash_disc_param_xspi.json b/boards/ti/lp_em_cc35x1/config/flash/gd25lf32e/flash_disc_param_xspi.json new file mode 100644 index 000000000000..8d7f8d001a98 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/gd25lf32e/flash_disc_param_xspi.json @@ -0,0 +1,485 @@ +{ + "xspi_header": { + "name": "xSPIWFF3", + "device": "CC3500", + "use_hardware": "GD25LF32E", + "use_case": "Quadro", + "dqs_support": 0, + "flash_only": 1, + "flash_separate_reset": 0, + "ram_separate_reset": true, + "clock_frequency": 80, + "qospi_clock_divider": 1, + "flash_device_character_conf": 0, + "ram_device_character_conf": 0, + "header_advanced": 0, + "phy_mode_enable": 1, + "pipeline_mode_enable": 1, + "loopback_support": "No", + "qspi_ref_clock": 80, + "spi_clock_freq": 20, + "spi_clock_divider": 1, + "flash_device_size": 4, + "flash_bytes_per_block": 16, + "flash_bytes_per_page": 256, + "flash_number_of_address_bytes": 3, + "flash_dual_opcode": 0, + "flash_jedec_manufacturer_id": 0, + "flash_jedec_device_id": 0, + "flash_name": "GD25LF32E", + "flash_page_size": 256, + "flash_sector_size": 4096, + "flash_cs_polarity": "ACTIVE_LOW", + "flash_sw_reset_type": "x1xxxx", + "ram_device_size": 4, + "ram_bytes_per_block": 16, + "ram_bytes_per_page": 256, + "ram_number_of_address_bytes": 3, + "ram_dual_opcode": 0, + "ram_jedec_manufacturer_id": 0, + "ram_jedec_device_id": 0, + "ram_name": "NO_PSRAM", + "ram_page_size": 256, + "ram_sector_size": 4096, + "ram_cs_polarity": "ACTIVE_LOW", + "ram_sw_reset_type": "x1xxxx", + "flash_write_operation_modes": "4S-4S-4S", + "flash_read_operation_modes": "4S-4S-4S", + "ram_write_operation_modes": "4S-4S-4S", + "ram_read_operation_modes": "4S-4S-4S", + "crc_enable": 0, + "enable_dtr": 0, + "enable_ahb_decoder": 0, + "enter_xip_mod_immediately": 0, + "enter_xip_mod_next_read": 0, + "ahb_address_remapping": 0, + "enable_dma": 0, + "select_decode": 0, + "legacy_ip_mode": 0, + "direct_access": 1 + }, + "xspi_pinmux": { + "xspi_clk_input": 44, + "xspi_clk_input_use_hw": 0, + "xspi_clk_input_mode": "Input", + "xspi_clk_input_pull": "None", + "xspi_clk_input_interrupt_trigger": "Low", + "xspi_clk_input_dont_conf": 0, + "xspi_clk_input_output_strength": "High", + "xspi_clk_input_initial_output_state": "High", + "xspi_clk": 24, + "xspi_clk_use_hw": "None", + "xspi_clk_mode": "Output", + "xspi_clk_pull": "None", + "xspi_clk_output_strength": "High", + "xspi_clk_initial_output_state": "High", + "xspi_clk_interrupt_trigger": "None", + "xspi_clk_dont_conf": 0, + "xspi_flash_cs": 20, + "xspi_flash_cs_use_hw": "None", + "xspi_flash_cs_mode": "Output", + "xspi_flash_cs_pull": "None", + "xspi_flash_cs_output_strength": "High", + "xspi_flash_cs_initial_output_state": "High", + "xspi_flash_cs_interrupt_trigger": "None", + "xspi_flash_cs_dont_conf": 0, + "xspi_data_0": 25, + "xspi_data_0_use_hw": "None", + "xspi_data_0_mode": "Input", + "xspi_data_0_pull": "None", + "xspi_data_0_output_strength": "High", + "xspi_data_0_initial_output_state": "High", + "xspi_data_0_interrupt_trigger": "Low", + "xspi_data_0_dont_conf": 0, + "xspi_data_1": 21, + "xspi_data_1_use_hw": "None", + "xspi_data_1_mode": "Input", + "xspi_data_1_pull": "None", + "xspi_data_1_output_strength": "High", + "xspi_data_1_initial_output_state": "High", + "xspi_data_1_interrupt_trigger": "Low", + "xspi_data_1_dont_conf": 0, + "xspi_data_2": 22, + "xspi_data_2_use_hw": "None", + "xspi_data_2_mode": "Input", + "xspi_data_2_pull": "None", + "xspi_data_2_output_strength": "High", + "xspi_data_2_initial_output_state": "High", + "xspi_data_2_interrupt_trigger": "Low", + "xspi_data_2_dont_conf": 0, + "xspi_data_3": 23, + "xspi_data_3_use_hw": "None", + "xspi_data_3_mode": "Input", + "xspi_data_3_pull": "None", + "xspi_data_3_output_strength": "High", + "xspi_data_3_initial_output_state": "High", + "xspi_data_3_interrupt_trigger": "Low", + "xspi_data_3_dont_conf": 0, + "xspi_data_4": 26, + "xspi_data_4_use_hw": "None", + "xspi_data_4_mode": "Input", + "xspi_data_4_pull": "None", + "xspi_data_4_output_strength": "High", + "xspi_data_4_initial_output_state": "High", + "xspi_data_4_interrupt_trigger": "None", + "xspi_data_4_dont_conf": 0, + "xspi_data_5": 27, + "xspi_data_5_use_hw": "None", + "xspi_data_5_mode": "Input", + "xspi_data_5_pull": "None", + "xspi_data_5_output_strength": "High", + "xspi_data_5_initial_output_state": "High", + "xspi_data_5_interrupt_trigger": "None", + "xspi_data_5_dont_conf": 0, + "xspi_data_6": 28, + "xspi_data_6_use_hw": "None", + "xspi_data_6_mode": "Input", + "xspi_data_6_pull": "None", + "xspi_data_6_output_strength": "High", + "xspi_data_6_initial_output_state": "High", + "xspi_data_6_interrupt_trigger": "None", + "xspi_data_6_dont_conf": 0, + "xspi_data_7": 29, + "xspi_data_7_use_hw": "None", + "xspi_data_7_mode": "Input", + "xspi_data_7_pull": "None", + "xspi_data_7_output_strength": "High", + "xspi_data_7_initial_output_state": "High", + "xspi_data_7_interrupt_trigger": "None", + "xspi_data_7_dont_conf": 0, + "xspi_reset_flash": 36, + "xspi_reset_flash_use_hw": "None", + "xspi_reset_flash_mode": "Output", + "xspi_reset_flash_pull": "None", + "xspi_reset_flash_output_strength": "High", + "xspi_reset_flash_initial_output_state": "High", + "xspi_reset_flash_interrupt_trigger": "None", + "xspi_reset_flash_dont_conf": 0, + "xspi_cs_ram": 3, + "xspi_cs_ram_use_hw": "None", + "xspi_cs_ram_mode": "Output", + "xspi_cs_ram_pull": "None", + "xspi_cs_ram_output_strength": "High", + "xspi_cs_ram_initial_output_state": "High", + "xspi_cs_ram_interrupt_trigger": "None", + "xspi_cs_ram_dont_conf": 0, + "xspi_dqs": 30, + "xspi_dqs_use_hw": "None", + "xspi_dqs_mode": "Input", + "xspi_dqs_pull": "None", + "xspi_dqs_output_strength": "High", + "xspi_dqs_initial_output_state": "High", + "xspi_dqs_interrupt_trigger": "None", + "xspi_dqs_dont_conf": 0, + "xspi_reset_ram": 2, + "xspi_reset_ram_use_hw": "None", + "xspi_reset_ram_mode": "Input", + "xspi_reset_ram_pull": "None", + "xspi_reset_ram_output_strength": "High", + "xspi_reset_ram_initial_output_state": "High", + "xspi_reset_ram_interrupt_trigger": "None", + "xspi_reset_ram_dont_conf": 0 + }, + "xspi_operations": { + "xspi_operations_clocks": { + "clock_phase": 0, + "clock_polarity": 0, + "spi_mode": "2'b00" + }, + "xspi_operations_chip_select": { + "csda": 2, + "csdads": 0, + "cseot": 4, + "cssot": 1 + }, + "xspi_operations_reset": { + "flash_jedec_reset": 0, + "ram_jedec_reset": 0, + "flash_treset": 20, + "ram_treset": 20 + }, + "xspi_phy_operations": { + "flash_rx_dll_bypass_bit": 0, + "flash_dll_tx_delay": 22, + "flash_dll_rx_delay": 34, + "ram_rx_dll_bypass_bit": 0, + "ram_dll_tx_delay": 22, + "ram_dll_rx_delay": 34 + }, + "xspi_read_operations": { + "flash_dummy_rd_cycles": 4, + "flash_read_opcode": 11, + "suppl_flash_read_opcode": 0, + "ram_dummy_rd_cycles": 4, + "ram_read_opcode": 11, + "suppl_ram_read_opcode": 0, + "flash_non_cont_read_enable": 0, + "flash_max_read_jobs": 256, + "ram_non_cont_read_enable": 0, + "ram_max_read_jobs": 256, + "rww_en": 0, + "device_size": 4, + "number_of_banks": 1, + "bank_size": 4, + "mode_bit_enable": 0 + }, + "xspi_write_operations": { + "flash_address_and_data": { + "flash_dummy_wr_cycles": 0 + }, + "flash_command": { + "flash_write_opcode": 2, + "suppl_flash_write_opcode": 0 + }, + "ram_address_and_data": { + "ram_dummy_wr_cycles": 0 + }, + "ram_command": { + "ram_write_opcode": 2, + "suppl_ram_write_opcode": 0 + }, + "write_to_buffer": { + "flash_write_to_buffer_support": 0, + "ram_write_to_buffer_support": 0 + }, + "non_continuous_write": { + "flash_non_cont_write_enable": 0, + "flash_max_write_jobs": 64, + "ram_non_cont_write_enable": 0, + "ram_max_write_jobs": 0 + }, + "flash_program_operation": { + "flash_min_program_size": "256 B", + "flash_program_opcode": 2, + "suppl_flash_program_opcode": 0, + "flash_maximum_program_time_limit": 1600 + }, + "flash_erase_operation": { + "flash_min_erase_size": "4 kB", + "flash_erase_opcode": 32, + "suppl_flash_erase_opcode": 0, + "flash_maximum_erase_time_limit": 4095 + }, + "flash_erase_conf": { + "flash_block_erase_opcode": 0, + "suppl_block_flash_erase_opcode": 0, + "flash_sector_erase_opcode": 0, + "suppl_sector_flash_erase_opcode": 0, + "flash_chip_erase_opcode": 0, + "suppl_chip_flash_erase_opcode": 0 + }, + "ram_program_operation": { + "ram_min_program_size": "256 B", + "ram_program_opcode": 2, + "suppl_ram_program_opcode": 0, + "ram_maximum_program_time_limit": 1600 + }, + "ram_erase_conf": { + "ram_block_erase_opcode": 0, + "suppl_block_ram_erase_opcode": 0, + "ram_sector_erase_opcode": 0, + "suppl_sector_ram_erase_opcode": 0, + "ram_chip_erase_opcode": 0, + "suppl_chip_ram_erase_opcode": 0 + }, + "flash_buffer_support": { + "flash_pre_write_sequence": 0, + "flash_post_write_sequence": 0, + "flash_write_protection_timer_en": 0, + "flash_write_buffer_timer_mode": 16, + "flash_write_buffer_timer_range": 0, + "flash_service_interrupt_criteria": 0 + }, + "ram_buffer_support": { + "ram_pre_write_sequence": 0, + "ram_post_write_sequence": 0, + "ram_write_protection_timer_en": 0, + "ram_write_buffer_timer_mode": 16, + "ram_write_buffer_timer_range": 0, + "ram_service_interrupt_criteria": 0 + }, + "flash_pre_write_conf": { + "flash_pre_write_job_done_grant_sel": 0, + "data_for_flash_pre_write_conf_0": 0, + "offset_bits_for_flash_pre_write_conf_0": 0, + "stop_bit_for_flash_pre_write_conf_0": 1, + "data_for_flash_pre_write_conf_1": 0, + "offset_bits_for_flash_pre_write_conf_1": 0 + }, + "flash_post_write_conf": { + "flash_post_write_job_done_grant_sel": 0, + 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0, + "flash_quad_enable_opcode": 56, + "suppl_flash_quad_enable_opcode": 0, + "flash_quad_disable_opcode": 255, + "suppl_flash_quad_disable_opcode": 0, + "flash_octal_enable_opcode": 0, + "suppl_flash_octal_enable_opcode": 0, + "flash_octal_disable_opcode": 0, + "suppl_flash_octal_disable_opcode": 0, + "ram_quad_enable_opcode": 56, + "suppl_ram_quad_enable_opcode": 0, + "ram_quad_disable_opcode": 255, + "suppl_ram_quad_disable_opcode": 0, + "ram_octal_enable_opcode": 0, + "suppl_ram_octal_enable_opcode": 0, + "ram_octal_disable_opcode": 0, + "suppl_ram_octal_disable_opcode": 0 + } + } + }, + "external_memory_reporting": { + "header": { + "flash_auto_polling_enable": 1, + "flash_wel_enable": 1, + "flash_write_protect_enable": 0, + "flash_alternate_polling_conf_enable": 0, + "ram_auto_polling_enable": 1, + "ram_wel_enable": 1, + "ram_write_protect_enable": 0, + "ram_alternate_polling_conf_enable": 0 + }, + "flash_auto_polling": { + "flash_polling_repetition_delay": 0, + "flash_polling_count": 4, + "flash_enable_polling_expiration": 0, + "flash_polling_polarity": 0, + "flash_polling_address_phase_enable": 0, + "flash_polling_bit_index": 0, + "flash_numbers_poll_cycles": 65535, + "flash_dummy_autopoll_cycles": 0 + }, + "ram_auto_polling": { + "ram_polling_repetition_delay": 0, + "ram_polling_count": 4, + "ram_enable_polling_expiration": 0, + "ram_polling_polarity": 0, + "ram_polling_address_phase_enable": 0, + "ram_polling_bit_index": 0, + "ram_numbers_poll_cycles": 65535, + "ram_dummy_autopoll_cycles": 0 + }, + "flash_polling_command": { + "flash_polling_opcode": 5, + "suppl_flash_polling_opcode": 0 + }, + "ram_polling_command": { + "ram_polling_opcode": 5, + "suppl_ram_polling_opcode": 0 + }, + "flash_alternate_polling": { + "flash_polling_resp_count": 1023, + "flash_polling_iterations": 1, + "flash_polling_enabled": 0, + "flash_polling_disabled": 0, + "flash_grant_sel": 0, + "flash_data_for_enable_poling_conf_0": 0, + "flash_offset_bits_for_enable_poling_conf_0": 0, + "flash_stop_bit_for_enable_poling_conf_0": 1, + "flash_data_for_enable_poling_conf_1": 0, + "flash_offset_bits_for_enable_poling_conf_1": 0, + "flash_stop_bit_for_enable_poling_conf_1": 1, + "flash_data_for_disable_poling_conf_0": 0, + "flash_offset_bits_for_disable_poling_conf_0": 0, + "flash_stop_bit_for_disable_poling_conf_0": 1, + "flash_data_for_disable_poling_conf_1": 0, + "flash_offset_bits_for_disable_poling_conf_1": 0, + "flash_stop_bit_for_disable_poling_conf_1": 1 + }, + "ram_alternate_polling": { + "ram_polling_resp_count": 1023, + "ram_polling_iterations": 1, + "ram_polling_enabled": 0, + "ram_polling_disabled": 0, + "ram_grant_sel": 0, + "ram_data_for_enable_poling_conf_0": 0, + "ram_offset_bits_for_enable_poling_conf_0": 0, + "ram_stop_bit_for_enable_poling_conf_0": 1, + "ram_data_for_enable_poling_conf_1": 0, + "ram_offset_bits_for_enable_poling_conf_1": 0, + "ram_stop_bit_for_enable_poling_conf_1": 1, + "ram_data_for_disable_poling_conf_0": 0, + "ram_offset_bits_for_disable_poling_conf_0": 0, + "ram_stop_bit_for_disable_poling_conf_0": 1, + "ram_data_for_disable_poling_conf_1": 0, + "ram_offset_bits_for_disable_poling_conf_1": 0, + "ram_stop_bit_for_disable_poling_conf_1": 1 + }, + "flash_wel_command": { + "flash_wel_opcode": 6, + "suppl_flash_wel_opcode": 0 + }, + "ram_wel_command": { + "ram_wel_opcode": 6, + "suppl_ram_wel_opcode": 0 + } + }, + "event": { + "host_nvic_irq": 0, + "core_10_mux_sel": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/gd25lf64e/flash_disc_param_ext_mem.json b/boards/ti/lp_em_cc35x1/config/flash/gd25lf64e/flash_disc_param_ext_mem.json new file mode 100644 index 000000000000..6585853ccd5e --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/gd25lf64e/flash_disc_param_ext_mem.json @@ -0,0 +1,99 @@ +{ + "vendor_primary_sbl": true, + "ti_wsoc_primary_container": true, + "ti_wsoc_bl2_primary_container": true, + "nvs_enable": true, + "vendor_alternate_image": true, + "vendor_sbl_alternate_image": true, + "ti_bl_alternate_image": true, + "ti_wsoc_alternate_image": true, + "ti_wsoc_bl2_alternate_image": true, + "region_0": { + "mem_region_0_start_phy_address": 2867200, + "mem_region_0_end_phy_address": 5627903, + "region0_boot": false, + "region0_main_code": true, + "region0_nvs": false, + "region0_wsoc_code": false, + "region0_alternate_code": false + }, + "region_1": { + "mem_region_1_start_phy_address": 0, + "mem_region_1_end_phy_address": 2867199, + "region1_boot": true, + "region1_main_code": false, + "region1_nvs": true, + "region1_wsoc_code": true, + "region1_alternate_code": false + }, + "region_2": { + "mem_region_2_start_phy_address": 5627904, + "mem_region_2_end_phy_address": 8388607, + "region2_boot": false, + "region2_main_code": false, + "region2_nvs": false, + "region2_wsoc_code": false, + "region2_alternate_code": true + }, + "region_3": { + "mem_region_3_start_phy_address": 0, + "mem_region_3_end_phy_address": 0, + "region3_boot": false, + "region3_main_code": false, + "region3_nvs": false, + "region3_wsoc_code": false, + "region3_alternate_code": false + }, + "boot_region_conf": { + "boot_region_size": 0, + "boot_region_flash_disco_param_start_address": 0, + "boot_region_primary_ti_bl_start_phy_address": 12284, + "boot_region_primary_ti_bl_magic": 0, + "boot_region_primary_ti_bl_major": 0, + "boot_region_primary_ti_bl_minor": 0, + "boot_region_sec_ti_bl_start_phy_address": 430076, + "boot_region_sec_ti_bl_magic": 0, + "boot_region_sec_ti_bl_major": 0, + "boot_region_sec_ti_bl_minor": 0 + }, + "main_code_region_conf": { + "main_code_region_vendor_image_start_phy_address": 2871292, + "main_code_region_vendor_image_magic": 0, + "main_code_region_vendor_image_major": 0, + "main_code_region_vendor_image_minor": 0, + "main_code_region_sbl_start_phy_address": 0, + "main_code_region_sbl_magic": 0, + "main_code_region_sbl_major": 0, + "main_code_region_sbl_minor": 0 + }, + "alt_code_region_conf": { + "alt_code_region_vendor_image_start_phy_address": 5631996, + "alt_code_region_vendor_image_magic": 0, + "alt_code_region_vendor_image_major": 0, + "alt_code_region_vendor_image_minor": 0, + "alt_code_region_sbl_start_phy_address": 0, + "alt_code_region_sbl_magic": 0, + "alt_code_region_sbl_major": 0, + "alt_code_region_sbl_minor": 0 + }, + "nvs_code_region_conf": { + "nvs_start_phy_address": 1777664, + "nvs_region_size": 1089536, + "nvs_region_primary_wsoc_start_phy_address": 847868, + "nvs_region_primary_wsoc_magic": 0, + "nvs_region_primary_wsoc_major": 0, + "nvs_region_primary_wsoc_minor": 0, + "nvs_region_sec_wsoc_start_phy_address": 1314812, + "nvs_region_sec_wsoc_magic": 0, + "nvs_region_sec_wsoc_major": 0, + "nvs_region_sec_wsoc_minor": 0, + "nvs_region_primary_wsoc_bl2_start_phy_address": 0, + "nvs_region_primary_wsoc_bl2_magic": 0, + "nvs_region_primary_wsoc_bl2_major": 0, + "nvs_region_primary_wsoc_bl2_minor": 0, + "nvs_region_sec_wsoc_bl2_start_phy_address": 0, + "nvs_region_sec_wsoc_bl2_magic": 0, + "nvs_region_sec_wsoc_bl2_major": 0, + "nvs_region_sec_wsoc_bl2_minor": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/gd25lf64e/flash_disc_param_otfde.json b/boards/ti/lp_em_cc35x1/config/flash/gd25lf64e/flash_disc_param_otfde.json new file mode 100644 index 000000000000..22a24d3d5430 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/gd25lf64e/flash_disc_param_otfde.json @@ -0,0 +1,286 @@ +{ + "otfde_header": { + "name": "OTFDEWFF3", + "flash_only": true, + "ip_protection": false, + "regions_lock": false, + "regions_number": 4, + "flash_enabled": true + }, + "bl_conf": { + "host_boot_done_lock": true, + "host_peripherals_lock": true, + "icache_conf_lock": true, + "m33_mem_part_lock": true, + "memss_firewall_lock": true, + "dma_channel_owner_lock": true, + "otfde_region_lock": true, + "core_events_lock": true + }, + "otfde_general": { + "parameters": { + "mem_otfde_initial_delay": 10, + "otfde_global_watchdog_timer": 5 + }, + "events": { + "reset_evt_mask": false, + "reset_evt_suspend": false, + "sft_reset_evt_mask": false, + "sft_reset_evt_suspend": false, + "bypass_mode_evt_mask": false, + "bypass_mode_evt_suspend": false, + "debug_mode_evt_mask": false, + "debug_mode_evt_suspend": false, + "general_evt_mask": false, + "general_evt_suspend": false, + "xspi_data_path_evt_mask": false, + "xspi_data_path_evt_suspend": false, + "xspi_cnfg_path_evt_mask": false, + "xspi_cnfg_path_evt_suspend": false, + "xspi_service_interrupt_evt_mask": false, + "xspi_service_interrupt_evt_suspend": false, + "trans_device_disabled_evt_mask": false, + "trans_device_disabled_evt_suspend": false, + "trans_region_disabled_evt_mask": false, + "trans_region_disabled_evt_suspend": false, + "trans_region_params_conf_evt_mask": false, + "trans_region_params_conf_evt_suspend": false, + "trans_multiple_regions_mapped_evt_mask": false, + "trans_multiple_regions_mapped_evt_suspend": false, + "trans_address_not_32_bit_evt_mask": false, + "trans_address_not_32_bit_evt_suspend": false, + "trans_size_not_32_bit_evt_mask": false, + "trans_size_not_32_bit_evt_suspend": false, + "trans_burst_not_32_bit_evt_mask": false, + "trans_burst_not_32_bit_evt_suspend": false, + "region_read_write_def_evt_mask": false, + "region_read_write_def_evt_suspend": false, + "suspend_while_disabled_evt_mask": false, + "suspend_while_disabled_evt_suspend": false + } + }, + "regions_settings": { + "region_parameters_lock": { + "REGION_0_PARAMS_0": true, + "REGION_0_PARAMS_1": true, + "REGION_0_PARAMS_2": true, + "REGION_1_PARAMS_0": false, + "REGION_1_PARAMS_1": false, + "REGION_1_PARAMS_2": false, + "REGION_2_PARAMS_0": true, + "REGION_2_PARAMS_1": true, + "REGION_2_PARAMS_2": true, + "REGION_3_PARAMS_0": false, + "REGION_3_PARAMS_1": false, + "REGION_3_PARAMS_2": false + }, + "region_0_protection": { + "mem_region_0_enabled": true, + "mem_region_0_device_id": 0, + "mem_region_0_spi_write_enable": true, + "mem_region_0_spi_read_enable": true, + "mem_region_0_physical_offset": 700, + "mem_region_0_security_id_msb": 0, + "mem_region_0_start_address": 81920, + "mem_region_0_end_address": 82593, + "mem_region_0_security_id_lsb": 0, + "mem_otfde_region_0_write_lock_en": false, + "mem_otfde_region_0_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_1_protection": { + "mem_region_1_enabled": true, + "mem_region_1_device_id": 0, + "mem_region_1_spi_write_enable": true, + "mem_region_1_spi_read_enable": true, + "mem_region_1_physical_offset": 0, + "mem_region_1_security_id_msb": 0, + "mem_region_1_start_address": 655360, + "mem_region_1_end_address": 656059, + "mem_region_1_security_id_lsb": 0, + "mem_otfde_region_1_write_lock_en": false, + "mem_otfde_region_1_enc_dec_bypass": "Bypass" + }, + "region_2_protection": { + "mem_region_2_enabled": true, + "mem_region_2_device_id": 0, + "mem_region_2_spi_write_enable": true, + "mem_region_2_spi_read_enable": true, + "mem_region_2_physical_offset": 1374, + "mem_region_2_security_id_msb": 0, + "mem_region_2_start_address": 671744, + "mem_region_2_end_address": 672417, + "mem_region_2_security_id_lsb": 0, + "mem_otfde_region_2_write_lock_en": false, + "mem_otfde_region_2_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_3_protection": { + "mem_region_3_enabled": false, + "mem_region_3_device_id": 1, + "mem_region_3_spi_write_enable": true, + "mem_region_3_spi_read_enable": true, + "mem_region_3_physical_offset": 0, + "mem_region_3_security_id_msb": 0, + "mem_region_3_start_address": 1, + "mem_region_3_end_address": 0, + "mem_region_3_security_id_lsb": 0, + "mem_otfde_region_3_write_lock_en": false, + "mem_otfde_region_3_enc_dec_bypass": "Bypass" + } + }, + "devices": { + "header": { + "flash_device_switch_conf": 1, + "ram_device_switch_conf": 1 + }, + "flash_switch": { + "flash_grant_sel": 0, + "flash_data_for_conf_0": 2181562505, + "flash_offset_bits_for_conf_0": 0, + "flash_stop_bit_for_conf_0": 0, + "flash_data_for_conf_1": 67248651, + "flash_offset_bits_for_conf_1": 1, + "flash_stop_bit_for_conf_1": 0, + "flash_data_for_conf_2": 139266, + "flash_offset_bits_for_conf_2": 2, + "flash_stop_bit_for_conf_2": 0, + "flash_data_for_conf_3": 1, + "flash_offset_bits_for_conf_3": 4, + "flash_stop_bit_for_conf_3": 0, + "flash_data_for_conf_4": 1076887634, + "flash_offset_bits_for_conf_4": 45, + "flash_stop_bit_for_conf_4": 0, + "flash_data_for_conf_5": 3224371282, + "flash_offset_bits_for_conf_5": 45, + "flash_stop_bit_for_conf_5": 0, + "flash_data_for_conf_6": 262149, + "flash_offset_bits_for_conf_6": 14, + "flash_stop_bit_for_conf_6": 0, + "flash_data_for_conf_7": 0, + "flash_offset_bits_for_conf_7": 44, + "flash_stop_bit_for_conf_7": 1, + "flash_data_for_conf_8": 0, + "flash_offset_bits_for_conf_8": 0, + "flash_stop_bit_for_conf_8": 1, + "flash_data_for_conf_9": 0, + "flash_offset_bits_for_conf_9": 0, + "flash_stop_bit_for_conf_9": 1, + "flash_data_for_conf_10": 0, + "flash_offset_bits_for_conf_10": 0, + "flash_stop_bit_for_conf_10": 1, + "flash_data_for_conf_11": 0, + "flash_offset_bits_for_conf_11": 0, + "flash_stop_bit_for_conf_11": 1, + "flash_data_for_conf_12": 0, + "flash_offset_bits_for_conf_12": 0, + "flash_stop_bit_for_conf_12": 1, + "flash_data_for_conf_13": 0, + "flash_offset_bits_for_conf_13": 0, + "flash_stop_bit_for_conf_13": 1, + "flash_data_for_conf_14": 0, + "flash_offset_bits_for_conf_14": 0, + "flash_stop_bit_for_conf_14": 1, + "flash_data_for_conf_15": 0, + "flash_offset_bits_for_conf_15": 0, + "flash_stop_bit_for_conf_15": 1, + "flash_data_for_conf_16": 0, + "flash_offset_bits_for_conf_16": 0, + "flash_stop_bit_for_conf_16": 1, + "flash_data_for_conf_17": 0, + "flash_offset_bits_for_conf_17": 0, + "flash_stop_bit_for_conf_17": 1, + "flash_data_for_conf_18": 0, + "flash_offset_bits_for_conf_18": 0, + "flash_stop_bit_for_conf_18": 1, + "flash_data_for_conf_19": 0, + "flash_offset_bits_for_conf_19": 0, + "flash_stop_bit_for_conf_19": 1, + "flash_data_for_conf_20": 0, + "flash_offset_bits_for_conf_20": 0, + "flash_stop_bit_for_conf_20": 1, + "flash_data_for_conf_21": 0, + "flash_offset_bits_for_conf_21": 0, + "flash_stop_bit_for_conf_21": 1, + "flash_data_for_conf_22": 0, + "flash_offset_bits_for_conf_22": 0, + "flash_stop_bit_for_conf_22": 1, + "flash_data_for_conf_23": 0, + "flash_offset_bits_for_conf_23": 0, + "flash_stop_bit_for_conf_23": 1 + }, + "ram_switch": { + "ram_grant_sel": 0, + "ram_data_for_conf_0": 2181562505, + "ram_offset_bits_for_conf_0": 0, + "ram_stop_bit_for_conf_0": 0, + "ram_data_for_conf_1": 67248651, + "ram_offset_bits_for_conf_1": 1, + "ram_stop_bit_for_conf_1": 0, + "ram_data_for_conf_2": 139266, + "ram_offset_bits_for_conf_2": 2, + "ram_stop_bit_for_conf_2": 0, + "ram_data_for_conf_3": 1, + "ram_offset_bits_for_conf_3": 4, + "ram_stop_bit_for_conf_3": 0, + "ram_data_for_conf_4": 1076887634, + "ram_offset_bits_for_conf_4": 45, + "ram_stop_bit_for_conf_4": 0, + "ram_data_for_conf_5": 3224371282, + "ram_offset_bits_for_conf_5": 45, + "ram_stop_bit_for_conf_5": 0, + "ram_data_for_conf_6": 262149, + "ram_offset_bits_for_conf_6": 14, + "ram_stop_bit_for_conf_6": 0, + "ram_data_for_conf_7": 0, + "ram_offset_bits_for_conf_7": 44, + "ram_stop_bit_for_conf_7": 1, + "ram_data_for_conf_8": 0, + "ram_offset_bits_for_conf_8": 0, + "ram_stop_bit_for_conf_8": 1, + "ram_data_for_conf_9": 0, + "ram_offset_bits_for_conf_9": 0, + "ram_stop_bit_for_conf_9": 1, + "ram_data_for_conf_10": 0, + "ram_offset_bits_for_conf_10": 0, + "ram_stop_bit_for_conf_10": 1, + "ram_data_for_conf_11": 0, + "ram_offset_bits_for_conf_11": 0, + "ram_stop_bit_for_conf_11": 1, + "ram_data_for_conf_12": 0, + "ram_offset_bits_for_conf_12": 0, + "ram_stop_bit_for_conf_12": 1, + "ram_data_for_conf_13": 0, + "ram_offset_bits_for_conf_13": 0, + "ram_stop_bit_for_conf_13": 1, + "ram_data_for_conf_14": 0, + "ram_offset_bits_for_conf_14": 0, + "ram_stop_bit_for_conf_14": 1, + "ram_data_for_conf_15": 0, + "ram_offset_bits_for_conf_15": 0, + "ram_stop_bit_for_conf_15": 1, + "ram_data_for_conf_16": 0, + "ram_offset_bits_for_conf_16": 0, + "ram_stop_bit_for_conf_16": 1, + "ram_data_for_conf_17": 0, + "ram_offset_bits_for_conf_17": 0, + "ram_stop_bit_for_conf_17": 1, + "ram_data_for_conf_18": 0, + "ram_offset_bits_for_conf_18": 0, + "ram_stop_bit_for_conf_18": 1, + "ram_data_for_conf_19": 0, + "ram_offset_bits_for_conf_19": 0, + "ram_stop_bit_for_conf_19": 1, + "ram_data_for_conf_20": 0, + "ram_offset_bits_for_conf_20": 0, + "ram_stop_bit_for_conf_20": 1, + "ram_data_for_conf_21": 0, + "ram_offset_bits_for_conf_21": 0, + "ram_stop_bit_for_conf_21": 1, + "ram_data_for_conf_22": 0, + "ram_offset_bits_for_conf_22": 0, + "ram_stop_bit_for_conf_22": 1, + "ram_data_for_conf_23": 0, + "ram_offset_bits_for_conf_23": 0, + "ram_stop_bit_for_conf_23": 1 + } + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/gd25lf64e/flash_disc_param_xspi.json b/boards/ti/lp_em_cc35x1/config/flash/gd25lf64e/flash_disc_param_xspi.json new file mode 100644 index 000000000000..ecd4d20bdd53 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/gd25lf64e/flash_disc_param_xspi.json @@ -0,0 +1,485 @@ +{ + "xspi_header": { + "name": "xSPIWFF3", + "device": "CC3500", + "use_hardware": "GD25LF64E", + "use_case": "Quadro", + "dqs_support": 0, + "flash_only": 1, + "flash_separate_reset": 0, + "ram_separate_reset": true, + "clock_frequency": 80, + "qospi_clock_divider": 1, + "flash_device_character_conf": 0, + "ram_device_character_conf": 0, + "header_advanced": 0, + "phy_mode_enable": 1, + "pipeline_mode_enable": 1, + "loopback_support": "No", + "qspi_ref_clock": 80, + "spi_clock_freq": 20, + "spi_clock_divider": 1, + "flash_device_size": 8, + "flash_bytes_per_block": 16, + "flash_bytes_per_page": 256, + "flash_number_of_address_bytes": 3, + "flash_dual_opcode": 0, + "flash_jedec_manufacturer_id": 0, + "flash_jedec_device_id": 0, + "flash_name": "GD25LF64E", + "flash_page_size": 256, + "flash_sector_size": 4096, + "flash_cs_polarity": "ACTIVE_LOW", + "flash_sw_reset_type": "x1xxxx", + "ram_device_size": 8, + "ram_bytes_per_block": 16, + "ram_bytes_per_page": 256, + "ram_number_of_address_bytes": 3, + "ram_dual_opcode": 0, + "ram_jedec_manufacturer_id": 0, + "ram_jedec_device_id": 0, + "ram_name": "NO_PSRAM", + "ram_page_size": 256, + "ram_sector_size": 4096, + "ram_cs_polarity": "ACTIVE_LOW", + "ram_sw_reset_type": "x1xxxx", + "flash_write_operation_modes": "4S-4S-4S", + "flash_read_operation_modes": "4S-4S-4S", + "ram_write_operation_modes": "4S-4S-4S", + "ram_read_operation_modes": "4S-4S-4S", + "crc_enable": 0, + "enable_dtr": 0, + "enable_ahb_decoder": 0, + "enter_xip_mod_immediately": 0, + "enter_xip_mod_next_read": 0, + "ahb_address_remapping": 0, + "enable_dma": 0, + "select_decode": 0, + "legacy_ip_mode": 0, + "direct_access": 1 + }, + "xspi_pinmux": { + "xspi_clk_input": 44, + "xspi_clk_input_use_hw": 0, + "xspi_clk_input_mode": "Input", + "xspi_clk_input_pull": "None", + "xspi_clk_input_interrupt_trigger": "Low", + "xspi_clk_input_dont_conf": 0, + "xspi_clk_input_output_strength": "High", + "xspi_clk_input_initial_output_state": "High", + "xspi_clk": 24, + "xspi_clk_use_hw": "None", + "xspi_clk_mode": "Output", + "xspi_clk_pull": "None", + "xspi_clk_output_strength": "High", + "xspi_clk_initial_output_state": "High", + "xspi_clk_interrupt_trigger": "None", + "xspi_clk_dont_conf": 0, + "xspi_flash_cs": 20, + "xspi_flash_cs_use_hw": "None", + "xspi_flash_cs_mode": "Output", + "xspi_flash_cs_pull": "None", + "xspi_flash_cs_output_strength": "High", + "xspi_flash_cs_initial_output_state": "High", + "xspi_flash_cs_interrupt_trigger": "None", + "xspi_flash_cs_dont_conf": 0, + "xspi_data_0": 25, + "xspi_data_0_use_hw": "None", + "xspi_data_0_mode": "Input", + "xspi_data_0_pull": "None", + "xspi_data_0_output_strength": "High", + "xspi_data_0_initial_output_state": "High", + "xspi_data_0_interrupt_trigger": "Low", + "xspi_data_0_dont_conf": 0, + "xspi_data_1": 21, + "xspi_data_1_use_hw": "None", + "xspi_data_1_mode": "Input", + "xspi_data_1_pull": "None", + "xspi_data_1_output_strength": "High", + "xspi_data_1_initial_output_state": "High", + "xspi_data_1_interrupt_trigger": "Low", + "xspi_data_1_dont_conf": 0, + "xspi_data_2": 22, + "xspi_data_2_use_hw": "None", + "xspi_data_2_mode": "Input", + "xspi_data_2_pull": "None", + "xspi_data_2_output_strength": "High", + "xspi_data_2_initial_output_state": "High", + "xspi_data_2_interrupt_trigger": "Low", + "xspi_data_2_dont_conf": 0, + "xspi_data_3": 23, + "xspi_data_3_use_hw": "None", + "xspi_data_3_mode": "Input", + "xspi_data_3_pull": "None", + "xspi_data_3_output_strength": "High", + "xspi_data_3_initial_output_state": "High", + "xspi_data_3_interrupt_trigger": "Low", + "xspi_data_3_dont_conf": 0, + "xspi_data_4": 26, + "xspi_data_4_use_hw": "None", + "xspi_data_4_mode": "Input", + "xspi_data_4_pull": "None", + "xspi_data_4_output_strength": "High", + "xspi_data_4_initial_output_state": "High", + "xspi_data_4_interrupt_trigger": "None", + "xspi_data_4_dont_conf": 0, + "xspi_data_5": 27, + "xspi_data_5_use_hw": "None", + "xspi_data_5_mode": "Input", + "xspi_data_5_pull": "None", + "xspi_data_5_output_strength": "High", + "xspi_data_5_initial_output_state": "High", + "xspi_data_5_interrupt_trigger": "None", + "xspi_data_5_dont_conf": 0, + "xspi_data_6": 28, + "xspi_data_6_use_hw": "None", + "xspi_data_6_mode": "Input", + "xspi_data_6_pull": "None", + "xspi_data_6_output_strength": "High", + "xspi_data_6_initial_output_state": "High", + "xspi_data_6_interrupt_trigger": "None", + "xspi_data_6_dont_conf": 0, + "xspi_data_7": 29, + "xspi_data_7_use_hw": "None", + "xspi_data_7_mode": "Input", + "xspi_data_7_pull": "None", + "xspi_data_7_output_strength": "High", + "xspi_data_7_initial_output_state": "High", + "xspi_data_7_interrupt_trigger": "None", + "xspi_data_7_dont_conf": 0, + "xspi_reset_flash": 36, + "xspi_reset_flash_use_hw": "None", + "xspi_reset_flash_mode": "Output", + "xspi_reset_flash_pull": "None", + "xspi_reset_flash_output_strength": "High", + "xspi_reset_flash_initial_output_state": "High", + "xspi_reset_flash_interrupt_trigger": "None", + "xspi_reset_flash_dont_conf": 0, + "xspi_cs_ram": 3, + "xspi_cs_ram_use_hw": "None", + "xspi_cs_ram_mode": "Output", + "xspi_cs_ram_pull": "None", + "xspi_cs_ram_output_strength": "High", + "xspi_cs_ram_initial_output_state": "High", + "xspi_cs_ram_interrupt_trigger": "None", + "xspi_cs_ram_dont_conf": 0, + "xspi_dqs": 30, + "xspi_dqs_use_hw": "None", + "xspi_dqs_mode": "Input", + "xspi_dqs_pull": "None", + "xspi_dqs_output_strength": "High", + "xspi_dqs_initial_output_state": "High", + "xspi_dqs_interrupt_trigger": "None", + "xspi_dqs_dont_conf": 0, + "xspi_reset_ram": 2, + "xspi_reset_ram_use_hw": "None", + "xspi_reset_ram_mode": "Input", + "xspi_reset_ram_pull": "None", + "xspi_reset_ram_output_strength": "High", + "xspi_reset_ram_initial_output_state": "High", + "xspi_reset_ram_interrupt_trigger": "None", + "xspi_reset_ram_dont_conf": 0 + }, + "xspi_operations": { + "xspi_operations_clocks": { + "clock_phase": 0, + "clock_polarity": 0, + "spi_mode": "2'b00" + }, + "xspi_operations_chip_select": { + "csda": 2, + "csdads": 0, + "cseot": 4, + "cssot": 1 + }, + "xspi_operations_reset": { + "flash_jedec_reset": 0, + "ram_jedec_reset": 0, + "flash_treset": 20, + "ram_treset": 20 + }, + "xspi_phy_operations": { + "flash_rx_dll_bypass_bit": 0, + "flash_dll_tx_delay": 22, + "flash_dll_rx_delay": 34, + "ram_rx_dll_bypass_bit": 0, + "ram_dll_tx_delay": 22, + "ram_dll_rx_delay": 34 + }, + "xspi_read_operations": { + "flash_dummy_rd_cycles": 4, + "flash_read_opcode": 11, + "suppl_flash_read_opcode": 0, + "ram_dummy_rd_cycles": 4, + "ram_read_opcode": 11, + "suppl_ram_read_opcode": 0, + "flash_non_cont_read_enable": 0, + "flash_max_read_jobs": 256, + "ram_non_cont_read_enable": 0, + "ram_max_read_jobs": 256, + "rww_en": 0, + "device_size": 8, + "number_of_banks": 1, + "bank_size": 8, + "mode_bit_enable": 0 + }, + "xspi_write_operations": { + "flash_address_and_data": { + "flash_dummy_wr_cycles": 0 + }, + "flash_command": { + "flash_write_opcode": 2, + "suppl_flash_write_opcode": 0 + }, + "ram_address_and_data": { + "ram_dummy_wr_cycles": 0 + }, + "ram_command": { + "ram_write_opcode": 2, + "suppl_ram_write_opcode": 0 + }, + "write_to_buffer": { + "flash_write_to_buffer_support": 0, + "ram_write_to_buffer_support": 0 + }, + "non_continuous_write": { + "flash_non_cont_write_enable": 0, + "flash_max_write_jobs": 64, + "ram_non_cont_write_enable": 0, + "ram_max_write_jobs": 0 + }, + "flash_program_operation": { + "flash_min_program_size": "256 B", + "flash_program_opcode": 2, + "suppl_flash_program_opcode": 0, + "flash_maximum_program_time_limit": 1600 + }, + "flash_erase_operation": { + "flash_min_erase_size": "4 kB", + "flash_erase_opcode": 32, + "suppl_flash_erase_opcode": 0, + "flash_maximum_erase_time_limit": 4095 + }, + "flash_erase_conf": { + "flash_block_erase_opcode": 0, + "suppl_block_flash_erase_opcode": 0, + "flash_sector_erase_opcode": 0, + "suppl_sector_flash_erase_opcode": 0, + "flash_chip_erase_opcode": 0, + "suppl_chip_flash_erase_opcode": 0 + }, + "ram_program_operation": { + "ram_min_program_size": "256 B", + "ram_program_opcode": 2, + "suppl_ram_program_opcode": 0, + "ram_maximum_program_time_limit": 1600 + }, + "ram_erase_conf": { + "ram_block_erase_opcode": 0, + "suppl_block_ram_erase_opcode": 0, + "ram_sector_erase_opcode": 0, + "suppl_sector_ram_erase_opcode": 0, + "ram_chip_erase_opcode": 0, + "suppl_chip_ram_erase_opcode": 0 + }, + "flash_buffer_support": { + "flash_pre_write_sequence": 0, + "flash_post_write_sequence": 0, + "flash_write_protection_timer_en": 0, + "flash_write_buffer_timer_mode": 16, + "flash_write_buffer_timer_range": 0, + "flash_service_interrupt_criteria": 0 + }, + "ram_buffer_support": { + "ram_pre_write_sequence": 0, + "ram_post_write_sequence": 0, + "ram_write_protection_timer_en": 0, + "ram_write_buffer_timer_mode": 16, + "ram_write_buffer_timer_range": 0, + "ram_service_interrupt_criteria": 0 + }, + "flash_pre_write_conf": { + "flash_pre_write_job_done_grant_sel": 0, + "data_for_flash_pre_write_conf_0": 0, + "offset_bits_for_flash_pre_write_conf_0": 0, + "stop_bit_for_flash_pre_write_conf_0": 1, + "data_for_flash_pre_write_conf_1": 0, + "offset_bits_for_flash_pre_write_conf_1": 0 + }, + "flash_post_write_conf": { + "flash_post_write_job_done_grant_sel": 0, + "data_for_flash_post_write_conf_0": 0, + "offset_bits_for_flash_post_write_conf_0": 0, + "stop_bit_for_flash_post_write_conf_0": 1, + "data_for_flash_post_write_conf_1": 0, + "offset_bits_for_flash_post_write_conf_1": 0 + }, + "ram_pre_write_conf": { + "ram_pre_write_job_done_grant_sel": 0, + "data_for_ram_pre_write_conf_0": 0, + "offset_bits_for_ram_pre_write_conf_0": 0, + "stop_bit_for_ram_pre_write_conf_0": 1, + "data_for_ram_pre_write_conf_1": 0, + "offset_bits_for_ram_pre_write_conf_1": 0 + }, + "ram_post_write_conf": { + "ram_post_write_job_done_grant_sel": 0, + "data_for_ram_post_write_conf_0": 0, + "offset_bits_for_ram_post_write_conf_0": 0, + "stop_bit_for_ram_post_write_conf_0": 1, + "data_for_ram_post_write_conf_1": 0, + "offset_bits_for_ram_post_write_conf_1": 0 + } + }, + "xspi_capture_operations": { + "read_data_capture": { + "flash_delay_transmitted_data": 0, + "flash_loopback_clock": 0, + "flash_bypass_adapted_loopback": 1, + "flash_sample_edge_sel": 0, + "ram_delay_transmitted_data": 0, + "ram_loopback_clock": 0, + "ram_bypass_adapted_loopback": 1, + "ram_sample_edge_sel": 0 + }, + "delays": { + "flash_full_half_cycle_delay": 0, + "flash_dll_bypass_mode": 1, + "flash_phase_detect_sel": 0, + "flash_dll_lock_num": 0, + "flash_dll_start_point": 0, + "flash_loopback_clock": 0, + "ram_full_half_cycle_delay": 0, + "ram_dll_bypass_mode": 1, + "ram_phase_detect_sel": 0, + "ram_dll_lock_num": 0, + "ram_dll_start_point": 0, + "ram_loopback_clock": 0 + }, + "operation_modes": { + "flash_sfdp_support": 0, + "ram_sfdp_support": 0, + "flash_pm_support": 0, + "ram_pm_support": 0, + "flash_sfdp_opcode": 0, + "suppl_flash_sfdp_opcode": 0, + "ram_sfdp_opcode": 0, + "suppl_ram_sfdp_opcode": 0, + "flash_enter_dpd_opcode": 185, + "suppl_flash_enter_dpd_opcode": 0, + "flash_exit_dpd_opcode": 171, + "suppl_flash_exit_dpd_opcode": 0, + "ram_enter_dpd_opcode": 185, + "suppl_ram_enter_dpd_opcode": 0, + "ram_exit_dpd_opcode": 171, + "suppl_ram_exit_dpd_opcode": 0, + "flash_quad_enable_opcode": 56, + "suppl_flash_quad_enable_opcode": 0, + "flash_quad_disable_opcode": 255, + "suppl_flash_quad_disable_opcode": 0, + "flash_octal_enable_opcode": 0, + "suppl_flash_octal_enable_opcode": 0, + "flash_octal_disable_opcode": 0, + "suppl_flash_octal_disable_opcode": 0, + "ram_quad_enable_opcode": 56, + "suppl_ram_quad_enable_opcode": 0, + "ram_quad_disable_opcode": 255, + "suppl_ram_quad_disable_opcode": 0, + "ram_octal_enable_opcode": 0, + "suppl_ram_octal_enable_opcode": 0, + "ram_octal_disable_opcode": 0, + "suppl_ram_octal_disable_opcode": 0 + } + } + }, + "external_memory_reporting": { + "header": { + "flash_auto_polling_enable": 1, + "flash_wel_enable": 1, + "flash_write_protect_enable": 0, + "flash_alternate_polling_conf_enable": 0, + "ram_auto_polling_enable": 1, + "ram_wel_enable": 1, + "ram_write_protect_enable": 0, + "ram_alternate_polling_conf_enable": 0 + }, + "flash_auto_polling": { + "flash_polling_repetition_delay": 0, + "flash_polling_count": 4, + "flash_enable_polling_expiration": 0, + "flash_polling_polarity": 0, + "flash_polling_address_phase_enable": 0, + "flash_polling_bit_index": 0, + "flash_numbers_poll_cycles": 65535, + "flash_dummy_autopoll_cycles": 0 + }, + "ram_auto_polling": { + "ram_polling_repetition_delay": 0, + "ram_polling_count": 4, + "ram_enable_polling_expiration": 0, + "ram_polling_polarity": 0, + "ram_polling_address_phase_enable": 0, + "ram_polling_bit_index": 0, + "ram_numbers_poll_cycles": 65535, + "ram_dummy_autopoll_cycles": 0 + }, + "flash_polling_command": { + "flash_polling_opcode": 5, + "suppl_flash_polling_opcode": 0 + }, + "ram_polling_command": { + "ram_polling_opcode": 5, + "suppl_ram_polling_opcode": 0 + }, + "flash_alternate_polling": { + "flash_polling_resp_count": 1023, + "flash_polling_iterations": 1, + "flash_polling_enabled": 0, + "flash_polling_disabled": 0, + "flash_grant_sel": 0, + "flash_data_for_enable_poling_conf_0": 0, + "flash_offset_bits_for_enable_poling_conf_0": 0, + "flash_stop_bit_for_enable_poling_conf_0": 1, + "flash_data_for_enable_poling_conf_1": 0, + "flash_offset_bits_for_enable_poling_conf_1": 0, + "flash_stop_bit_for_enable_poling_conf_1": 1, + "flash_data_for_disable_poling_conf_0": 0, + "flash_offset_bits_for_disable_poling_conf_0": 0, + "flash_stop_bit_for_disable_poling_conf_0": 1, + "flash_data_for_disable_poling_conf_1": 0, + "flash_offset_bits_for_disable_poling_conf_1": 0, + "flash_stop_bit_for_disable_poling_conf_1": 1 + }, + "ram_alternate_polling": { + "ram_polling_resp_count": 1023, + "ram_polling_iterations": 1, + "ram_polling_enabled": 0, + "ram_polling_disabled": 0, + "ram_grant_sel": 0, + "ram_data_for_enable_poling_conf_0": 0, + "ram_offset_bits_for_enable_poling_conf_0": 0, + "ram_stop_bit_for_enable_poling_conf_0": 1, + "ram_data_for_enable_poling_conf_1": 0, + "ram_offset_bits_for_enable_poling_conf_1": 0, + "ram_stop_bit_for_enable_poling_conf_1": 1, + "ram_data_for_disable_poling_conf_0": 0, + "ram_offset_bits_for_disable_poling_conf_0": 0, + "ram_stop_bit_for_disable_poling_conf_0": 1, + "ram_data_for_disable_poling_conf_1": 0, + "ram_offset_bits_for_disable_poling_conf_1": 0, + "ram_stop_bit_for_disable_poling_conf_1": 1 + }, + "flash_wel_command": { + "flash_wel_opcode": 6, + "suppl_flash_wel_opcode": 0 + }, + "ram_wel_command": { + "ram_wel_opcode": 6, + "suppl_ram_wel_opcode": 0 + } + }, + "event": { + "host_nvic_irq": 0, + "core_10_mux_sel": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/is25wj032f/external_memory_configurator.json b/boards/ti/lp_em_cc35x1/config/flash/is25wj032f/external_memory_configurator.json new file mode 100644 index 000000000000..cf15120ef862 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/is25wj032f/external_memory_configurator.json @@ -0,0 +1,27 @@ +{ + "flash_type": { + "flash_device_type": "IS25WJ032F", + "flash_device_size": 4, + "flash_page_size": 256, + "flash_sector_size": 4096 + }, + "inputs": { + "boot_sector_size": 8, + "ti_btl2_slot1_size": 400, + "vendor_app_slot1_size": 3044, + "nvs_data_max_size": 140, + "key_storage_data_max_size": 32, + "vendor_specific_max_size": 0, + "wsoc_code_slot1_size": 450, + "wsoc_bl2_cont_max_size": 0, + "psram_data": 4096 + }, + "internal": { + "ota": false, + "primary_region": 0, + "memory_mode": 0, + "dtcm": 64, + "itcm": 32 + }, + "psram_type": "NO_PSRAM" +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/is25wj032f/flash_disc_param_ext_mem.json b/boards/ti/lp_em_cc35x1/config/flash/is25wj032f/flash_disc_param_ext_mem.json new file mode 100644 index 000000000000..da33e3a6385b --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/is25wj032f/flash_disc_param_ext_mem.json @@ -0,0 +1,99 @@ +{ + "vendor_primary_sbl": true, + "ti_wsoc_primary_container": true, + "ti_wsoc_bl2_primary_container": true, + "nvs_enable": true, + "vendor_alternate_image": true, + "vendor_sbl_alternate_image": true, + "ti_bl_alternate_image": true, + "ti_wsoc_alternate_image": true, + "ti_wsoc_bl2_alternate_image": true, + "region_0": { + "mem_region_0_start_phy_address": 1073152, + "mem_region_0_end_phy_address": 4194303, + "region0_boot": false, + "region0_main_code": true, + "region0_nvs": false, + "region0_wsoc_code": false, + "region0_alternate_code": false + }, + "region_1": { + "mem_region_1_start_phy_address": 0, + "mem_region_1_end_phy_address": 1073151, + "region1_boot": true, + "region1_main_code": false, + "region1_nvs": true, + "region1_wsoc_code": true, + "region1_alternate_code": false + }, + "region_2": { + "mem_region_2_start_phy_address": 0, + "mem_region_2_end_phy_address": 0, + "region2_boot": false, + "region2_main_code": false, + "region2_nvs": false, + "region2_wsoc_code": false, + "region2_alternate_code": true + }, + "region_3": { + "mem_region_3_start_phy_address": 0, + "mem_region_3_end_phy_address": 0, + "region3_boot": false, + "region3_main_code": false, + "region3_nvs": false, + "region3_wsoc_code": false, + "region3_alternate_code": false + }, + "boot_region_conf": { + "boot_region_size": 0, + "boot_region_flash_disco_param_start_address": 0, + "boot_region_primary_ti_bl_start_phy_address": 12284, + "boot_region_primary_ti_bl_magic": 0, + "boot_region_primary_ti_bl_major": 0, + "boot_region_primary_ti_bl_minor": 0, + "boot_region_sec_ti_bl_start_phy_address": 430076, + "boot_region_sec_ti_bl_magic": 0, + "boot_region_sec_ti_bl_major": 0, + "boot_region_sec_ti_bl_minor": 0 + }, + "main_code_region_conf": { + "main_code_region_vendor_image_start_phy_address": 1077244, + "main_code_region_vendor_image_magic": 0, + "main_code_region_vendor_image_major": 0, + "main_code_region_vendor_image_minor": 0, + "main_code_region_sbl_start_phy_address": 0, + "main_code_region_sbl_magic": 0, + "main_code_region_sbl_major": 0, + "main_code_region_sbl_minor": 0 + }, + "alt_code_region_conf": { + "alt_code_region_vendor_image_start_phy_address": 4194304, + "alt_code_region_vendor_image_magic": 0, + "alt_code_region_vendor_image_major": 0, + "alt_code_region_vendor_image_minor": 0, + "alt_code_region_sbl_start_phy_address": 0, + "alt_code_region_sbl_magic": 0, + "alt_code_region_sbl_major": 0, + "alt_code_region_sbl_minor": 0 + }, + "nvs_code_region_conf": { + "nvs_start_phy_address": 892928, + "nvs_region_size": 180224, + "nvs_region_primary_wsoc_start_phy_address": 430076, + "nvs_region_primary_wsoc_magic": 0, + "nvs_region_primary_wsoc_major": 0, + "nvs_region_primary_wsoc_minor": 0, + "nvs_region_sec_wsoc_start_phy_address": 897020, + "nvs_region_sec_wsoc_magic": 0, + "nvs_region_sec_wsoc_major": 0, + "nvs_region_sec_wsoc_minor": 0, + "nvs_region_primary_wsoc_bl2_start_phy_address": 0, + "nvs_region_primary_wsoc_bl2_magic": 0, + "nvs_region_primary_wsoc_bl2_major": 0, + "nvs_region_primary_wsoc_bl2_minor": 0, + "nvs_region_sec_wsoc_bl2_start_phy_address": 0, + "nvs_region_sec_wsoc_bl2_magic": 0, + "nvs_region_sec_wsoc_bl2_major": 0, + "nvs_region_sec_wsoc_bl2_minor": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/is25wj032f/flash_disc_param_otfde.json b/boards/ti/lp_em_cc35x1/config/flash/is25wj032f/flash_disc_param_otfde.json new file mode 100644 index 000000000000..635e11319c5d --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/is25wj032f/flash_disc_param_otfde.json @@ -0,0 +1,286 @@ +{ + "otfde_header": { + "name": "OTFDEWFF3", + "flash_only": true, + "ip_protection": false, + "regions_lock": false, + "regions_number": 4, + "flash_enabled": true + }, + "bl_conf": { + "host_boot_done_lock": true, + "host_peripherals_lock": true, + "icache_conf_lock": true, + "m33_mem_part_lock": true, + "memss_firewall_lock": true, + "dma_channel_owner_lock": true, + "otfde_region_lock": true, + "core_events_lock": true + }, + "otfde_general": { + "parameters": { + "mem_otfde_initial_delay": 10, + "otfde_global_watchdog_timer": 5 + }, + "events": { + "reset_evt_mask": false, + "reset_evt_suspend": false, + "sft_reset_evt_mask": false, + "sft_reset_evt_suspend": false, + "bypass_mode_evt_mask": false, + "bypass_mode_evt_suspend": false, + "debug_mode_evt_mask": false, + "debug_mode_evt_suspend": false, + "general_evt_mask": false, + "general_evt_suspend": false, + "xspi_data_path_evt_mask": false, + "xspi_data_path_evt_suspend": false, + "xspi_cnfg_path_evt_mask": false, + "xspi_cnfg_path_evt_suspend": false, + "xspi_service_interrupt_evt_mask": false, + "xspi_service_interrupt_evt_suspend": false, + "trans_device_disabled_evt_mask": false, + "trans_device_disabled_evt_suspend": false, + "trans_region_disabled_evt_mask": false, + "trans_region_disabled_evt_suspend": false, + "trans_region_params_conf_evt_mask": false, + "trans_region_params_conf_evt_suspend": false, + "trans_multiple_regions_mapped_evt_mask": false, + "trans_multiple_regions_mapped_evt_suspend": false, + "trans_address_not_32_bit_evt_mask": false, + "trans_address_not_32_bit_evt_suspend": false, + "trans_size_not_32_bit_evt_mask": false, + "trans_size_not_32_bit_evt_suspend": false, + "trans_burst_not_32_bit_evt_mask": false, + "trans_burst_not_32_bit_evt_suspend": false, + "region_read_write_def_evt_mask": false, + "region_read_write_def_evt_suspend": false, + "suspend_while_disabled_evt_mask": false, + "suspend_while_disabled_evt_suspend": false + } + }, + "regions_settings": { + "region_parameters_lock": { + "REGION_0_PARAMS_0": true, + "REGION_0_PARAMS_1": true, + "REGION_0_PARAMS_2": true, + "REGION_1_PARAMS_0": false, + "REGION_1_PARAMS_1": false, + "REGION_1_PARAMS_2": false, + "REGION_2_PARAMS_0": true, + "REGION_2_PARAMS_1": true, + "REGION_2_PARAMS_2": true, + "REGION_3_PARAMS_0": false, + "REGION_3_PARAMS_1": false, + "REGION_3_PARAMS_2": false + }, + "region_0_protection": { + "mem_region_0_enabled": true, + "mem_region_0_device_id": 0, + "mem_region_0_spi_write_enable": true, + "mem_region_0_spi_read_enable": true, + "mem_region_0_physical_offset": 261, + "mem_region_0_security_id_msb": 0, + "mem_region_0_start_address": 81920, + "mem_region_0_end_address": 82682, + "mem_region_0_security_id_lsb": 0, + "mem_otfde_region_0_write_lock_en": false, + "mem_otfde_region_0_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_1_protection": { + "mem_region_1_enabled": true, + "mem_region_1_device_id": 0, + "mem_region_1_spi_write_enable": true, + "mem_region_1_spi_read_enable": true, + "mem_region_1_physical_offset": 0, + "mem_region_1_security_id_msb": 0, + "mem_region_1_start_address": 655360, + "mem_region_1_end_address": 655620, + "mem_region_1_security_id_lsb": 0, + "mem_otfde_region_1_write_lock_en": false, + "mem_otfde_region_1_enc_dec_bypass": "Bypass" + }, + "region_2_protection": { + "mem_region_2_enabled": false, + "mem_region_2_device_id": 0, + "mem_region_2_spi_write_enable": true, + "mem_region_2_spi_read_enable": true, + "mem_region_2_physical_offset": 0, + "mem_region_2_security_id_msb": 0, + "mem_region_2_start_address": 1, + "mem_region_2_end_address": 0, + "mem_region_2_security_id_lsb": 0, + "mem_otfde_region_2_write_lock_en": false, + "mem_otfde_region_2_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_3_protection": { + "mem_region_3_enabled": false, + "mem_region_3_device_id": 1, + "mem_region_3_spi_write_enable": true, + "mem_region_3_spi_read_enable": true, + "mem_region_3_physical_offset": 0, + "mem_region_3_security_id_msb": 0, + "mem_region_3_start_address": 1, + "mem_region_3_end_address": 0, + "mem_region_3_security_id_lsb": 0, + "mem_otfde_region_3_write_lock_en": false, + "mem_otfde_region_3_enc_dec_bypass": "Bypass" + } + }, + "devices": { + "header": { + "flash_device_switch_conf": 1, + "ram_device_switch_conf": 1 + }, + "flash_switch": { + "flash_grant_sel": 0, + "flash_data_for_conf_0": 2181562505, + "flash_offset_bits_for_conf_0": 0, + "flash_stop_bit_for_conf_0": 0, + "flash_data_for_conf_1": 67248651, + "flash_offset_bits_for_conf_1": 1, + "flash_stop_bit_for_conf_1": 0, + "flash_data_for_conf_2": 139266, + "flash_offset_bits_for_conf_2": 2, + "flash_stop_bit_for_conf_2": 0, + "flash_data_for_conf_3": 1, + "flash_offset_bits_for_conf_3": 4, + "flash_stop_bit_for_conf_3": 0, + "flash_data_for_conf_4": 1076887634, + "flash_offset_bits_for_conf_4": 45, + "flash_stop_bit_for_conf_4": 0, + "flash_data_for_conf_5": 3224371282, + "flash_offset_bits_for_conf_5": 45, + "flash_stop_bit_for_conf_5": 0, + "flash_data_for_conf_6": 262149, + "flash_offset_bits_for_conf_6": 14, + "flash_stop_bit_for_conf_6": 0, + "flash_data_for_conf_7": 0, + "flash_offset_bits_for_conf_7": 44, + "flash_stop_bit_for_conf_7": 1, + "flash_data_for_conf_8": 0, + "flash_offset_bits_for_conf_8": 0, + "flash_stop_bit_for_conf_8": 1, + "flash_data_for_conf_9": 0, + "flash_offset_bits_for_conf_9": 0, + "flash_stop_bit_for_conf_9": 1, + "flash_data_for_conf_10": 0, + "flash_offset_bits_for_conf_10": 0, + "flash_stop_bit_for_conf_10": 1, + "flash_data_for_conf_11": 0, + "flash_offset_bits_for_conf_11": 0, + "flash_stop_bit_for_conf_11": 1, + "flash_data_for_conf_12": 0, + "flash_offset_bits_for_conf_12": 0, + "flash_stop_bit_for_conf_12": 1, + "flash_data_for_conf_13": 0, + "flash_offset_bits_for_conf_13": 0, + "flash_stop_bit_for_conf_13": 1, + "flash_data_for_conf_14": 0, + "flash_offset_bits_for_conf_14": 0, + "flash_stop_bit_for_conf_14": 1, + "flash_data_for_conf_15": 0, + "flash_offset_bits_for_conf_15": 0, + "flash_stop_bit_for_conf_15": 1, + "flash_data_for_conf_16": 0, + "flash_offset_bits_for_conf_16": 0, + "flash_stop_bit_for_conf_16": 1, + "flash_data_for_conf_17": 0, + "flash_offset_bits_for_conf_17": 0, + "flash_stop_bit_for_conf_17": 1, + "flash_data_for_conf_18": 0, + "flash_offset_bits_for_conf_18": 0, + "flash_stop_bit_for_conf_18": 1, + "flash_data_for_conf_19": 0, + "flash_offset_bits_for_conf_19": 0, + "flash_stop_bit_for_conf_19": 1, + "flash_data_for_conf_20": 0, + "flash_offset_bits_for_conf_20": 0, + "flash_stop_bit_for_conf_20": 1, + "flash_data_for_conf_21": 0, + "flash_offset_bits_for_conf_21": 0, + "flash_stop_bit_for_conf_21": 1, + "flash_data_for_conf_22": 0, + "flash_offset_bits_for_conf_22": 0, + "flash_stop_bit_for_conf_22": 1, + "flash_data_for_conf_23": 0, + "flash_offset_bits_for_conf_23": 0, + "flash_stop_bit_for_conf_23": 1 + }, + "ram_switch": { + "ram_grant_sel": 0, + "ram_data_for_conf_0": 2181562505, + "ram_offset_bits_for_conf_0": 0, + "ram_stop_bit_for_conf_0": 0, + "ram_data_for_conf_1": 67248651, + "ram_offset_bits_for_conf_1": 1, + "ram_stop_bit_for_conf_1": 0, + "ram_data_for_conf_2": 139266, + "ram_offset_bits_for_conf_2": 2, + "ram_stop_bit_for_conf_2": 0, + "ram_data_for_conf_3": 1, + "ram_offset_bits_for_conf_3": 4, + "ram_stop_bit_for_conf_3": 0, + "ram_data_for_conf_4": 1076887634, + "ram_offset_bits_for_conf_4": 45, + "ram_stop_bit_for_conf_4": 0, + "ram_data_for_conf_5": 3224371282, + "ram_offset_bits_for_conf_5": 45, + "ram_stop_bit_for_conf_5": 0, + "ram_data_for_conf_6": 262149, + "ram_offset_bits_for_conf_6": 14, + "ram_stop_bit_for_conf_6": 0, + "ram_data_for_conf_7": 0, + "ram_offset_bits_for_conf_7": 44, + "ram_stop_bit_for_conf_7": 1, + "ram_data_for_conf_8": 0, + "ram_offset_bits_for_conf_8": 0, + "ram_stop_bit_for_conf_8": 1, + "ram_data_for_conf_9": 0, + "ram_offset_bits_for_conf_9": 0, + "ram_stop_bit_for_conf_9": 1, + "ram_data_for_conf_10": 0, + "ram_offset_bits_for_conf_10": 0, + "ram_stop_bit_for_conf_10": 1, + "ram_data_for_conf_11": 0, + "ram_offset_bits_for_conf_11": 0, + "ram_stop_bit_for_conf_11": 1, + "ram_data_for_conf_12": 0, + "ram_offset_bits_for_conf_12": 0, + "ram_stop_bit_for_conf_12": 1, + "ram_data_for_conf_13": 0, + "ram_offset_bits_for_conf_13": 0, + "ram_stop_bit_for_conf_13": 1, + "ram_data_for_conf_14": 0, + "ram_offset_bits_for_conf_14": 0, + "ram_stop_bit_for_conf_14": 1, + "ram_data_for_conf_15": 0, + "ram_offset_bits_for_conf_15": 0, + "ram_stop_bit_for_conf_15": 1, + "ram_data_for_conf_16": 0, + "ram_offset_bits_for_conf_16": 0, + "ram_stop_bit_for_conf_16": 1, + "ram_data_for_conf_17": 0, + "ram_offset_bits_for_conf_17": 0, + "ram_stop_bit_for_conf_17": 1, + "ram_data_for_conf_18": 0, + "ram_offset_bits_for_conf_18": 0, + "ram_stop_bit_for_conf_18": 1, + "ram_data_for_conf_19": 0, + "ram_offset_bits_for_conf_19": 0, + "ram_stop_bit_for_conf_19": 1, + "ram_data_for_conf_20": 0, + "ram_offset_bits_for_conf_20": 0, + "ram_stop_bit_for_conf_20": 1, + "ram_data_for_conf_21": 0, + "ram_offset_bits_for_conf_21": 0, + "ram_stop_bit_for_conf_21": 1, + "ram_data_for_conf_22": 0, + "ram_offset_bits_for_conf_22": 0, + "ram_stop_bit_for_conf_22": 1, + "ram_data_for_conf_23": 0, + "ram_offset_bits_for_conf_23": 0, + "ram_stop_bit_for_conf_23": 1 + } + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/is25wj032f/flash_disc_param_xspi.json b/boards/ti/lp_em_cc35x1/config/flash/is25wj032f/flash_disc_param_xspi.json new file mode 100644 index 000000000000..c96cbac6431a --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/is25wj032f/flash_disc_param_xspi.json @@ -0,0 +1,485 @@ +{ + "xspi_header": { + "name": "xSPIWFF3", + "device": "CC3500", + "use_hardware": "IS25WJ032F", + "use_case": "Quadro", + "dqs_support": 0, + "flash_only": 1, + "flash_separate_reset": 0, + "ram_separate_reset": true, + "clock_frequency": 80, + "qospi_clock_divider": 1, + "flash_device_character_conf": 0, + "ram_device_character_conf": 0, + "header_advanced": 0, + "phy_mode_enable": 1, + "pipeline_mode_enable": 1, + "loopback_support": "No", + "qspi_ref_clock": 80, + "spi_clock_freq": 20, + "spi_clock_divider": 1, + "flash_device_size": 4, + "flash_bytes_per_block": 16, + "flash_bytes_per_page": 256, + "flash_number_of_address_bytes": 3, + "flash_dual_opcode": 0, + "flash_jedec_manufacturer_id": 0, + "flash_jedec_device_id": 0, + "flash_name": "IS25WJ032F", + "flash_page_size": 256, + "flash_sector_size": 4096, + "flash_cs_polarity": "ACTIVE_LOW", + "flash_sw_reset_type": "x1xxxx", + "ram_device_size": 4, + "ram_bytes_per_block": 16, + "ram_bytes_per_page": 256, + "ram_number_of_address_bytes": 3, + "ram_dual_opcode": 0, + "ram_jedec_manufacturer_id": 0, + "ram_jedec_device_id": 0, + "ram_name": "NO_PSRAM", + "ram_page_size": 256, + "ram_sector_size": 4096, + "ram_cs_polarity": "ACTIVE_LOW", + "ram_sw_reset_type": "x1xxxx", + "flash_write_operation_modes": "4S-4S-4S", + "flash_read_operation_modes": "4S-4S-4S", + "ram_write_operation_modes": "4S-4S-4S", + "ram_read_operation_modes": "4S-4S-4S", + "crc_enable": 0, + "enable_dtr": 0, + "enable_ahb_decoder": 0, + "enter_xip_mod_immediately": 0, + "enter_xip_mod_next_read": 0, + "ahb_address_remapping": 0, + "enable_dma": 0, + "select_decode": 0, + "legacy_ip_mode": 0, + "direct_access": 1 + }, + "xspi_pinmux": { + "xspi_clk_input": 44, + "xspi_clk_input_use_hw": 0, + "xspi_clk_input_mode": "Input", + "xspi_clk_input_pull": "None", + "xspi_clk_input_interrupt_trigger": "Low", + "xspi_clk_input_dont_conf": 0, + "xspi_clk_input_output_strength": "High", + "xspi_clk_input_initial_output_state": "High", + "xspi_clk": 24, + "xspi_clk_use_hw": "None", + "xspi_clk_mode": "Output", + "xspi_clk_pull": "None", + "xspi_clk_output_strength": "High", + "xspi_clk_initial_output_state": "High", + "xspi_clk_interrupt_trigger": "None", + "xspi_clk_dont_conf": 0, + "xspi_flash_cs": 20, + "xspi_flash_cs_use_hw": "None", + "xspi_flash_cs_mode": "Output", + "xspi_flash_cs_pull": "None", + "xspi_flash_cs_output_strength": "High", + "xspi_flash_cs_initial_output_state": "High", + "xspi_flash_cs_interrupt_trigger": "None", + "xspi_flash_cs_dont_conf": 0, + "xspi_data_0": 25, + "xspi_data_0_use_hw": "None", + "xspi_data_0_mode": "Input", + "xspi_data_0_pull": "None", + "xspi_data_0_output_strength": "High", + "xspi_data_0_initial_output_state": "High", + "xspi_data_0_interrupt_trigger": "Low", + "xspi_data_0_dont_conf": 0, + "xspi_data_1": 21, + "xspi_data_1_use_hw": "None", + "xspi_data_1_mode": "Input", + "xspi_data_1_pull": "None", + "xspi_data_1_output_strength": "High", + "xspi_data_1_initial_output_state": "High", + "xspi_data_1_interrupt_trigger": "Low", + "xspi_data_1_dont_conf": 0, + "xspi_data_2": 22, + "xspi_data_2_use_hw": "None", + "xspi_data_2_mode": "Input", + "xspi_data_2_pull": "None", + "xspi_data_2_output_strength": "High", + "xspi_data_2_initial_output_state": "High", + "xspi_data_2_interrupt_trigger": "Low", + "xspi_data_2_dont_conf": 0, + "xspi_data_3": 23, + "xspi_data_3_use_hw": "None", + "xspi_data_3_mode": "Input", + "xspi_data_3_pull": "None", + "xspi_data_3_output_strength": "High", + "xspi_data_3_initial_output_state": "High", + "xspi_data_3_interrupt_trigger": "Low", + "xspi_data_3_dont_conf": 0, + "xspi_data_4": 26, + "xspi_data_4_use_hw": "None", + "xspi_data_4_mode": "Input", + "xspi_data_4_pull": "None", + "xspi_data_4_output_strength": "High", + "xspi_data_4_initial_output_state": "High", + "xspi_data_4_interrupt_trigger": "None", + "xspi_data_4_dont_conf": 0, + "xspi_data_5": 27, + "xspi_data_5_use_hw": "None", + "xspi_data_5_mode": "Input", + "xspi_data_5_pull": "None", + "xspi_data_5_output_strength": "High", + "xspi_data_5_initial_output_state": "High", + "xspi_data_5_interrupt_trigger": "None", + "xspi_data_5_dont_conf": 0, + "xspi_data_6": 28, + "xspi_data_6_use_hw": "None", + "xspi_data_6_mode": "Input", + "xspi_data_6_pull": "None", + "xspi_data_6_output_strength": "High", + "xspi_data_6_initial_output_state": "High", + "xspi_data_6_interrupt_trigger": "None", + "xspi_data_6_dont_conf": 0, + "xspi_data_7": 29, + "xspi_data_7_use_hw": "None", + "xspi_data_7_mode": "Input", + "xspi_data_7_pull": "None", + "xspi_data_7_output_strength": "High", + "xspi_data_7_initial_output_state": "High", + "xspi_data_7_interrupt_trigger": "None", + "xspi_data_7_dont_conf": 0, + "xspi_reset_flash": 36, + "xspi_reset_flash_use_hw": "None", + "xspi_reset_flash_mode": "Output", + "xspi_reset_flash_pull": "None", + "xspi_reset_flash_output_strength": "High", + "xspi_reset_flash_initial_output_state": "High", + "xspi_reset_flash_interrupt_trigger": "None", + "xspi_reset_flash_dont_conf": 0, + "xspi_cs_ram": 3, + "xspi_cs_ram_use_hw": "None", + "xspi_cs_ram_mode": "Output", + "xspi_cs_ram_pull": "None", + "xspi_cs_ram_output_strength": "High", + "xspi_cs_ram_initial_output_state": "High", + "xspi_cs_ram_interrupt_trigger": "None", + "xspi_cs_ram_dont_conf": 0, + "xspi_dqs": 30, + "xspi_dqs_use_hw": "None", + "xspi_dqs_mode": "Input", + "xspi_dqs_pull": "None", + "xspi_dqs_output_strength": "High", + "xspi_dqs_initial_output_state": "High", + "xspi_dqs_interrupt_trigger": "None", + "xspi_dqs_dont_conf": 0, + "xspi_reset_ram": 2, + "xspi_reset_ram_use_hw": "None", + "xspi_reset_ram_mode": "Input", + "xspi_reset_ram_pull": "None", + "xspi_reset_ram_output_strength": "High", + "xspi_reset_ram_initial_output_state": "High", + "xspi_reset_ram_interrupt_trigger": "None", + "xspi_reset_ram_dont_conf": 0 + }, + "xspi_operations": { + "xspi_operations_clocks": { + "clock_phase": 0, + "clock_polarity": 0, + "spi_mode": "2'b00" + }, + "xspi_operations_chip_select": { + "csda": 2, + "csdads": 0, + "cseot": 4, + "cssot": 1 + }, + "xspi_operations_reset": { + "flash_jedec_reset": 0, + "ram_jedec_reset": 0, + "flash_treset": 20, + "ram_treset": 20 + }, + "xspi_phy_operations": { + "flash_rx_dll_bypass_bit": 0, + "flash_dll_tx_delay": 22, + "flash_dll_rx_delay": 34, + "ram_rx_dll_bypass_bit": 0, + "ram_dll_tx_delay": 22, + "ram_dll_rx_delay": 34 + }, + "xspi_read_operations": { + "flash_dummy_rd_cycles": 4, + "flash_read_opcode": 11, + "suppl_flash_read_opcode": 0, + "ram_dummy_rd_cycles": 4, + "ram_read_opcode": 11, + "suppl_ram_read_opcode": 0, + "flash_non_cont_read_enable": 0, + "flash_max_read_jobs": 256, + "ram_non_cont_read_enable": 0, + "ram_max_read_jobs": 256, + "rww_en": 0, + "device_size": 4, + "number_of_banks": 1, + "bank_size": 4, + "mode_bit_enable": 0 + }, + "xspi_write_operations": { + "flash_address_and_data": { + "flash_dummy_wr_cycles": 0 + }, + "flash_command": { + "flash_write_opcode": 2, + "suppl_flash_write_opcode": 0 + }, + "ram_address_and_data": { + "ram_dummy_wr_cycles": 0 + }, + "ram_command": { + "ram_write_opcode": 2, + "suppl_ram_write_opcode": 0 + }, + "write_to_buffer": { + "flash_write_to_buffer_support": 0, + "ram_write_to_buffer_support": 0 + }, + "non_continuous_write": { + "flash_non_cont_write_enable": 0, + "flash_max_write_jobs": 64, + "ram_non_cont_write_enable": 0, + "ram_max_write_jobs": 0 + }, + "flash_program_operation": { + "flash_min_program_size": "256 B", + "flash_program_opcode": 2, + "suppl_flash_program_opcode": 0, + "flash_maximum_program_time_limit": 1600 + }, + "flash_erase_operation": { + "flash_min_erase_size": "4 kB", + "flash_erase_opcode": 32, + "suppl_flash_erase_opcode": 0, + "flash_maximum_erase_time_limit": 4095 + }, + "flash_erase_conf": { + "flash_block_erase_opcode": 0, + "suppl_block_flash_erase_opcode": 0, + "flash_sector_erase_opcode": 0, + "suppl_sector_flash_erase_opcode": 0, + "flash_chip_erase_opcode": 0, + "suppl_chip_flash_erase_opcode": 0 + }, + "ram_program_operation": { + "ram_min_program_size": "256 B", + "ram_program_opcode": 2, + "suppl_ram_program_opcode": 0, + "ram_maximum_program_time_limit": 1600 + }, + "ram_erase_conf": { + "ram_block_erase_opcode": 0, + "suppl_block_ram_erase_opcode": 0, + "ram_sector_erase_opcode": 0, + "suppl_sector_ram_erase_opcode": 0, + "ram_chip_erase_opcode": 0, + "suppl_chip_ram_erase_opcode": 0 + }, + "flash_buffer_support": { + "flash_pre_write_sequence": 0, + "flash_post_write_sequence": 0, + "flash_write_protection_timer_en": 0, + "flash_write_buffer_timer_mode": 16, + "flash_write_buffer_timer_range": 0, + "flash_service_interrupt_criteria": 0 + }, + "ram_buffer_support": { + "ram_pre_write_sequence": 0, + "ram_post_write_sequence": 0, + "ram_write_protection_timer_en": 0, + "ram_write_buffer_timer_mode": 16, + "ram_write_buffer_timer_range": 0, + "ram_service_interrupt_criteria": 0 + }, + "flash_pre_write_conf": { + "flash_pre_write_job_done_grant_sel": 0, + "data_for_flash_pre_write_conf_0": 0, + "offset_bits_for_flash_pre_write_conf_0": 0, + "stop_bit_for_flash_pre_write_conf_0": 1, + "data_for_flash_pre_write_conf_1": 0, + "offset_bits_for_flash_pre_write_conf_1": 0 + }, + "flash_post_write_conf": { + "flash_post_write_job_done_grant_sel": 0, + "data_for_flash_post_write_conf_0": 0, + "offset_bits_for_flash_post_write_conf_0": 0, + "stop_bit_for_flash_post_write_conf_0": 1, + "data_for_flash_post_write_conf_1": 0, + "offset_bits_for_flash_post_write_conf_1": 0 + }, + "ram_pre_write_conf": { + "ram_pre_write_job_done_grant_sel": 0, + "data_for_ram_pre_write_conf_0": 0, + "offset_bits_for_ram_pre_write_conf_0": 0, + "stop_bit_for_ram_pre_write_conf_0": 1, + "data_for_ram_pre_write_conf_1": 0, + "offset_bits_for_ram_pre_write_conf_1": 0 + }, + "ram_post_write_conf": { + "ram_post_write_job_done_grant_sel": 0, + "data_for_ram_post_write_conf_0": 0, + "offset_bits_for_ram_post_write_conf_0": 0, + "stop_bit_for_ram_post_write_conf_0": 1, + "data_for_ram_post_write_conf_1": 0, + "offset_bits_for_ram_post_write_conf_1": 0 + } + }, + "xspi_capture_operations": { + "read_data_capture": { + "flash_delay_transmitted_data": 0, + "flash_loopback_clock": 0, + "flash_bypass_adapted_loopback": 1, + "flash_sample_edge_sel": 0, + "ram_delay_transmitted_data": 0, + "ram_loopback_clock": 0, + "ram_bypass_adapted_loopback": 1, + "ram_sample_edge_sel": 0 + }, + "delays": { + "flash_full_half_cycle_delay": 0, + "flash_dll_bypass_mode": 1, + "flash_phase_detect_sel": 0, + "flash_dll_lock_num": 0, + "flash_dll_start_point": 0, + "flash_loopback_clock": 0, + "ram_full_half_cycle_delay": 0, + "ram_dll_bypass_mode": 1, + "ram_phase_detect_sel": 0, + "ram_dll_lock_num": 0, + "ram_dll_start_point": 0, + "ram_loopback_clock": 0 + }, + "operation_modes": { + "flash_sfdp_support": 0, + "ram_sfdp_support": 0, + "flash_pm_support": 0, + "ram_pm_support": 0, + "flash_sfdp_opcode": 0, + "suppl_flash_sfdp_opcode": 0, + "ram_sfdp_opcode": 0, + "suppl_ram_sfdp_opcode": 0, + "flash_enter_dpd_opcode": 185, + "suppl_flash_enter_dpd_opcode": 0, + "flash_exit_dpd_opcode": 171, + "suppl_flash_exit_dpd_opcode": 0, + "ram_enter_dpd_opcode": 185, + "suppl_ram_enter_dpd_opcode": 0, + "ram_exit_dpd_opcode": 171, + "suppl_ram_exit_dpd_opcode": 0, + "flash_quad_enable_opcode": 56, + "suppl_flash_quad_enable_opcode": 0, + "flash_quad_disable_opcode": 255, + "suppl_flash_quad_disable_opcode": 0, + "flash_octal_enable_opcode": 0, + "suppl_flash_octal_enable_opcode": 0, + "flash_octal_disable_opcode": 0, + "suppl_flash_octal_disable_opcode": 0, + "ram_quad_enable_opcode": 56, + "suppl_ram_quad_enable_opcode": 0, + "ram_quad_disable_opcode": 255, + "suppl_ram_quad_disable_opcode": 0, + "ram_octal_enable_opcode": 0, + "suppl_ram_octal_enable_opcode": 0, + "ram_octal_disable_opcode": 0, + "suppl_ram_octal_disable_opcode": 0 + } + } + }, + "external_memory_reporting": { + "header": { + "flash_auto_polling_enable": 1, + "flash_wel_enable": 1, + "flash_write_protect_enable": 0, + "flash_alternate_polling_conf_enable": 0, + "ram_auto_polling_enable": 1, + "ram_wel_enable": 1, + "ram_write_protect_enable": 0, + "ram_alternate_polling_conf_enable": 0 + }, + "flash_auto_polling": { + "flash_polling_repetition_delay": 0, + "flash_polling_count": 4, + "flash_enable_polling_expiration": 0, + "flash_polling_polarity": 0, + "flash_polling_address_phase_enable": 0, + "flash_polling_bit_index": 0, + "flash_numbers_poll_cycles": 65535, + "flash_dummy_autopoll_cycles": 0 + }, + "ram_auto_polling": { + "ram_polling_repetition_delay": 0, + "ram_polling_count": 4, + "ram_enable_polling_expiration": 0, + "ram_polling_polarity": 0, + "ram_polling_address_phase_enable": 0, + "ram_polling_bit_index": 0, + "ram_numbers_poll_cycles": 65535, + "ram_dummy_autopoll_cycles": 0 + }, + "flash_polling_command": { + "flash_polling_opcode": 5, + "suppl_flash_polling_opcode": 0 + }, + "ram_polling_command": { + "ram_polling_opcode": 5, + "suppl_ram_polling_opcode": 0 + }, + "flash_alternate_polling": { + "flash_polling_resp_count": 1023, + "flash_polling_iterations": 1, + "flash_polling_enabled": 0, + "flash_polling_disabled": 0, + "flash_grant_sel": 0, + "flash_data_for_enable_poling_conf_0": 0, + "flash_offset_bits_for_enable_poling_conf_0": 0, + "flash_stop_bit_for_enable_poling_conf_0": 1, + "flash_data_for_enable_poling_conf_1": 0, + "flash_offset_bits_for_enable_poling_conf_1": 0, + "flash_stop_bit_for_enable_poling_conf_1": 1, + "flash_data_for_disable_poling_conf_0": 0, + "flash_offset_bits_for_disable_poling_conf_0": 0, + "flash_stop_bit_for_disable_poling_conf_0": 1, + "flash_data_for_disable_poling_conf_1": 0, + "flash_offset_bits_for_disable_poling_conf_1": 0, + "flash_stop_bit_for_disable_poling_conf_1": 1 + }, + "ram_alternate_polling": { + "ram_polling_resp_count": 1023, + "ram_polling_iterations": 1, + "ram_polling_enabled": 0, + "ram_polling_disabled": 0, + "ram_grant_sel": 0, + "ram_data_for_enable_poling_conf_0": 0, + "ram_offset_bits_for_enable_poling_conf_0": 0, + "ram_stop_bit_for_enable_poling_conf_0": 1, + "ram_data_for_enable_poling_conf_1": 0, + "ram_offset_bits_for_enable_poling_conf_1": 0, + "ram_stop_bit_for_enable_poling_conf_1": 1, + "ram_data_for_disable_poling_conf_0": 0, + "ram_offset_bits_for_disable_poling_conf_0": 0, + "ram_stop_bit_for_disable_poling_conf_0": 1, + "ram_data_for_disable_poling_conf_1": 0, + "ram_offset_bits_for_disable_poling_conf_1": 0, + "ram_stop_bit_for_disable_poling_conf_1": 1 + }, + "flash_wel_command": { + "flash_wel_opcode": 6, + "suppl_flash_wel_opcode": 0 + }, + "ram_wel_command": { + "ram_wel_opcode": 6, + "suppl_ram_wel_opcode": 0 + } + }, + "event": { + "host_nvic_irq": 0, + "core_10_mux_sel": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/is25wj032f/ota/external_memory_configurator.json b/boards/ti/lp_em_cc35x1/config/flash/is25wj032f/ota/external_memory_configurator.json new file mode 100644 index 000000000000..01fbbd030c18 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/is25wj032f/ota/external_memory_configurator.json @@ -0,0 +1,27 @@ +{ + "flash_type": { + "flash_device_type": "IS25WJ032F", + "flash_device_size": 4, + "flash_page_size": 256, + "flash_sector_size": 4096 + }, + "inputs": { + "boot_sector_size": 8, + "ti_btl2_slot1_size": 400, + "vendor_app_slot1_size": 1092, + "nvs_data_max_size": 136, + "key_storage_data_max_size": 32, + "vendor_specific_max_size": 0, + "wsoc_code_slot1_size": 450, + "wsoc_bl2_cont_max_size": 0, + "psram_data": 4096 + }, + "internal": { + "ota": true, + "primary_region": 0, + "memory_mode": 0, + "dtcm": 64, + "itcm": 32 + }, + "psram_type": "NO_PSRAM" +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/is25wj032f/ota/flash_disc_param_ext_mem.json b/boards/ti/lp_em_cc35x1/config/flash/is25wj032f/ota/flash_disc_param_ext_mem.json new file mode 100644 index 000000000000..39e516b132c1 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/is25wj032f/ota/flash_disc_param_ext_mem.json @@ -0,0 +1,99 @@ +{ + "vendor_primary_sbl": true, + "ti_wsoc_primary_container": true, + "ti_wsoc_bl2_primary_container": true, + "nvs_enable": true, + "vendor_alternate_image": true, + "vendor_sbl_alternate_image": true, + "ti_bl_alternate_image": true, + "ti_wsoc_alternate_image": true, + "ti_wsoc_bl2_alternate_image": true, + "region_0": { + "mem_region_0_start_phy_address": 1953792, + "mem_region_0_end_phy_address": 3071999, + "region0_boot": false, + "region0_main_code": true, + "region0_nvs": false, + "region0_wsoc_code": false, + "region0_alternate_code": false + }, + "region_1": { + "mem_region_1_start_phy_address": 0, + "mem_region_1_end_phy_address": 1953791, + "region1_boot": true, + "region1_main_code": false, + "region1_nvs": true, + "region1_wsoc_code": true, + "region1_alternate_code": false + }, + "region_2": { + "mem_region_2_start_phy_address": 3072000, + "mem_region_2_end_phy_address": 4190207, + "region2_boot": false, + "region2_main_code": false, + "region2_nvs": false, + "region2_wsoc_code": false, + "region2_alternate_code": true + }, + "region_3": { + "mem_region_3_start_phy_address": 0, + "mem_region_3_end_phy_address": 0, + "region3_boot": false, + "region3_main_code": false, + "region3_nvs": false, + "region3_wsoc_code": false, + "region3_alternate_code": false + }, + "boot_region_conf": { + "boot_region_size": 0, + "boot_region_flash_disco_param_start_address": 0, + "boot_region_primary_ti_bl_start_phy_address": 12284, + "boot_region_primary_ti_bl_magic": 0, + "boot_region_primary_ti_bl_major": 0, + "boot_region_primary_ti_bl_minor": 0, + "boot_region_sec_ti_bl_start_phy_address": 430076, + "boot_region_sec_ti_bl_magic": 0, + "boot_region_sec_ti_bl_major": 0, + "boot_region_sec_ti_bl_minor": 0 + }, + "main_code_region_conf": { + "main_code_region_vendor_image_start_phy_address": 1957884, + "main_code_region_vendor_image_magic": 0, + "main_code_region_vendor_image_major": 0, + "main_code_region_vendor_image_minor": 0, + "main_code_region_sbl_start_phy_address": 0, + "main_code_region_sbl_magic": 0, + "main_code_region_sbl_major": 0, + "main_code_region_sbl_minor": 0 + }, + "alt_code_region_conf": { + "alt_code_region_vendor_image_start_phy_address": 3076092, + "alt_code_region_vendor_image_magic": 0, + "alt_code_region_vendor_image_major": 0, + "alt_code_region_vendor_image_minor": 0, + "alt_code_region_sbl_start_phy_address": 0, + "alt_code_region_sbl_magic": 0, + "alt_code_region_sbl_major": 0, + "alt_code_region_sbl_minor": 0 + }, + "nvs_code_region_conf": { + "nvs_start_phy_address": 1777664, + "nvs_region_size": 176128, + "nvs_region_primary_wsoc_start_phy_address": 847868, + "nvs_region_primary_wsoc_magic": 0, + "nvs_region_primary_wsoc_major": 0, + "nvs_region_primary_wsoc_minor": 0, + "nvs_region_sec_wsoc_start_phy_address": 1314812, + "nvs_region_sec_wsoc_magic": 0, + "nvs_region_sec_wsoc_major": 0, + "nvs_region_sec_wsoc_minor": 0, + "nvs_region_primary_wsoc_bl2_start_phy_address": 0, + "nvs_region_primary_wsoc_bl2_magic": 0, + "nvs_region_primary_wsoc_bl2_major": 0, + "nvs_region_primary_wsoc_bl2_minor": 0, + "nvs_region_sec_wsoc_bl2_start_phy_address": 0, + "nvs_region_sec_wsoc_bl2_magic": 0, + "nvs_region_sec_wsoc_bl2_major": 0, + "nvs_region_sec_wsoc_bl2_minor": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/is25wj032f/ota/flash_disc_param_otfde.json b/boards/ti/lp_em_cc35x1/config/flash/is25wj032f/ota/flash_disc_param_otfde.json new file mode 100644 index 000000000000..23355619e499 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/is25wj032f/ota/flash_disc_param_otfde.json @@ -0,0 +1,286 @@ +{ + "otfde_header": { + "name": "OTFDEWFF3", + "flash_only": true, + "ip_protection": false, + "regions_lock": false, + "regions_number": 4, + "flash_enabled": true + }, + "bl_conf": { + "host_boot_done_lock": true, + "host_peripherals_lock": true, + "icache_conf_lock": true, + "m33_mem_part_lock": true, + "memss_firewall_lock": true, + "dma_channel_owner_lock": true, + "otfde_region_lock": true, + "core_events_lock": true + }, + "otfde_general": { + "parameters": { + "mem_otfde_initial_delay": 10, + "otfde_global_watchdog_timer": 5 + }, + "events": { + "reset_evt_mask": false, + "reset_evt_suspend": false, + "sft_reset_evt_mask": false, + "sft_reset_evt_suspend": false, + "bypass_mode_evt_mask": false, + "bypass_mode_evt_suspend": false, + "debug_mode_evt_mask": false, + "debug_mode_evt_suspend": false, + "general_evt_mask": false, + "general_evt_suspend": false, + "xspi_data_path_evt_mask": false, + "xspi_data_path_evt_suspend": false, + "xspi_cnfg_path_evt_mask": false, + "xspi_cnfg_path_evt_suspend": false, + "xspi_service_interrupt_evt_mask": false, + "xspi_service_interrupt_evt_suspend": false, + "trans_device_disabled_evt_mask": false, + "trans_device_disabled_evt_suspend": false, + "trans_region_disabled_evt_mask": false, + "trans_region_disabled_evt_suspend": false, + "trans_region_params_conf_evt_mask": false, + "trans_region_params_conf_evt_suspend": false, + "trans_multiple_regions_mapped_evt_mask": false, + "trans_multiple_regions_mapped_evt_suspend": false, + "trans_address_not_32_bit_evt_mask": false, + "trans_address_not_32_bit_evt_suspend": false, + "trans_size_not_32_bit_evt_mask": false, + "trans_size_not_32_bit_evt_suspend": false, + "trans_burst_not_32_bit_evt_mask": false, + "trans_burst_not_32_bit_evt_suspend": false, + "region_read_write_def_evt_mask": false, + "region_read_write_def_evt_suspend": false, + "suspend_while_disabled_evt_mask": false, + "suspend_while_disabled_evt_suspend": false + } + }, + "regions_settings": { + "region_parameters_lock": { + "REGION_0_PARAMS_0": true, + "REGION_0_PARAMS_1": true, + "REGION_0_PARAMS_2": true, + "REGION_1_PARAMS_0": false, + "REGION_1_PARAMS_1": false, + "REGION_1_PARAMS_2": false, + "REGION_2_PARAMS_0": true, + "REGION_2_PARAMS_1": true, + "REGION_2_PARAMS_2": true, + "REGION_3_PARAMS_0": false, + "REGION_3_PARAMS_1": false, + "REGION_3_PARAMS_2": false + }, + "region_0_protection": { + "mem_region_0_enabled": true, + "mem_region_0_device_id": 0, + "mem_region_0_spi_write_enable": true, + "mem_region_0_spi_read_enable": true, + "mem_region_0_physical_offset": 477, + "mem_region_0_security_id_msb": 0, + "mem_region_0_start_address": 81920, + "mem_region_0_end_address": 82192, + "mem_region_0_security_id_lsb": 0, + "mem_otfde_region_0_write_lock_en": false, + "mem_otfde_region_0_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_1_protection": { + "mem_region_1_enabled": true, + "mem_region_1_device_id": 0, + "mem_region_1_spi_write_enable": true, + "mem_region_1_spi_read_enable": true, + "mem_region_1_physical_offset": 0, + "mem_region_1_security_id_msb": 0, + "mem_region_1_start_address": 655360, + "mem_region_1_end_address": 655836, + "mem_region_1_security_id_lsb": 0, + "mem_otfde_region_1_write_lock_en": false, + "mem_otfde_region_1_enc_dec_bypass": "Bypass" + }, + "region_2_protection": { + "mem_region_2_enabled": true, + "mem_region_2_device_id": 0, + "mem_region_2_spi_write_enable": true, + "mem_region_2_spi_read_enable": true, + "mem_region_2_physical_offset": 750, + "mem_region_2_security_id_msb": 0, + "mem_region_2_start_address": 671744, + "mem_region_2_end_address": 672016, + "mem_region_2_security_id_lsb": 0, + "mem_otfde_region_2_write_lock_en": false, + "mem_otfde_region_2_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_3_protection": { + "mem_region_3_enabled": false, + "mem_region_3_device_id": 1, + "mem_region_3_spi_write_enable": true, + "mem_region_3_spi_read_enable": true, + "mem_region_3_physical_offset": 0, + "mem_region_3_security_id_msb": 0, + "mem_region_3_start_address": 1, + "mem_region_3_end_address": 0, + "mem_region_3_security_id_lsb": 0, + "mem_otfde_region_3_write_lock_en": false, + "mem_otfde_region_3_enc_dec_bypass": "Bypass" + } + }, + "devices": { + "header": { + "flash_device_switch_conf": 1, + "ram_device_switch_conf": 1 + }, + "flash_switch": { + "flash_grant_sel": 0, + "flash_data_for_conf_0": 2181562505, + "flash_offset_bits_for_conf_0": 0, + "flash_stop_bit_for_conf_0": 0, + "flash_data_for_conf_1": 67248651, + "flash_offset_bits_for_conf_1": 1, + "flash_stop_bit_for_conf_1": 0, + "flash_data_for_conf_2": 139266, + "flash_offset_bits_for_conf_2": 2, + "flash_stop_bit_for_conf_2": 0, + "flash_data_for_conf_3": 1, + "flash_offset_bits_for_conf_3": 4, + "flash_stop_bit_for_conf_3": 0, + "flash_data_for_conf_4": 1076887634, + "flash_offset_bits_for_conf_4": 45, + "flash_stop_bit_for_conf_4": 0, + "flash_data_for_conf_5": 3224371282, + "flash_offset_bits_for_conf_5": 45, + "flash_stop_bit_for_conf_5": 0, + "flash_data_for_conf_6": 262149, + "flash_offset_bits_for_conf_6": 14, + "flash_stop_bit_for_conf_6": 0, + "flash_data_for_conf_7": 0, + "flash_offset_bits_for_conf_7": 44, + "flash_stop_bit_for_conf_7": 1, + "flash_data_for_conf_8": 0, + "flash_offset_bits_for_conf_8": 0, + "flash_stop_bit_for_conf_8": 1, + "flash_data_for_conf_9": 0, + "flash_offset_bits_for_conf_9": 0, + "flash_stop_bit_for_conf_9": 1, + "flash_data_for_conf_10": 0, + "flash_offset_bits_for_conf_10": 0, + "flash_stop_bit_for_conf_10": 1, + "flash_data_for_conf_11": 0, + "flash_offset_bits_for_conf_11": 0, + "flash_stop_bit_for_conf_11": 1, + "flash_data_for_conf_12": 0, + "flash_offset_bits_for_conf_12": 0, + "flash_stop_bit_for_conf_12": 1, + "flash_data_for_conf_13": 0, + "flash_offset_bits_for_conf_13": 0, + "flash_stop_bit_for_conf_13": 1, + "flash_data_for_conf_14": 0, + "flash_offset_bits_for_conf_14": 0, + "flash_stop_bit_for_conf_14": 1, + "flash_data_for_conf_15": 0, + "flash_offset_bits_for_conf_15": 0, + "flash_stop_bit_for_conf_15": 1, + "flash_data_for_conf_16": 0, + "flash_offset_bits_for_conf_16": 0, + "flash_stop_bit_for_conf_16": 1, + "flash_data_for_conf_17": 0, + "flash_offset_bits_for_conf_17": 0, + "flash_stop_bit_for_conf_17": 1, + "flash_data_for_conf_18": 0, + "flash_offset_bits_for_conf_18": 0, + "flash_stop_bit_for_conf_18": 1, + "flash_data_for_conf_19": 0, + "flash_offset_bits_for_conf_19": 0, + "flash_stop_bit_for_conf_19": 1, + "flash_data_for_conf_20": 0, + "flash_offset_bits_for_conf_20": 0, + "flash_stop_bit_for_conf_20": 1, + "flash_data_for_conf_21": 0, + "flash_offset_bits_for_conf_21": 0, + "flash_stop_bit_for_conf_21": 1, + "flash_data_for_conf_22": 0, + "flash_offset_bits_for_conf_22": 0, + "flash_stop_bit_for_conf_22": 1, + "flash_data_for_conf_23": 0, + "flash_offset_bits_for_conf_23": 0, + "flash_stop_bit_for_conf_23": 1 + }, + "ram_switch": { + "ram_grant_sel": 0, + "ram_data_for_conf_0": 2181562505, + "ram_offset_bits_for_conf_0": 0, + "ram_stop_bit_for_conf_0": 0, + "ram_data_for_conf_1": 67248651, + "ram_offset_bits_for_conf_1": 1, + "ram_stop_bit_for_conf_1": 0, + "ram_data_for_conf_2": 139266, + "ram_offset_bits_for_conf_2": 2, + "ram_stop_bit_for_conf_2": 0, + "ram_data_for_conf_3": 1, + "ram_offset_bits_for_conf_3": 4, + "ram_stop_bit_for_conf_3": 0, + "ram_data_for_conf_4": 1076887634, + "ram_offset_bits_for_conf_4": 45, + "ram_stop_bit_for_conf_4": 0, + "ram_data_for_conf_5": 3224371282, + "ram_offset_bits_for_conf_5": 45, + "ram_stop_bit_for_conf_5": 0, + "ram_data_for_conf_6": 262149, + "ram_offset_bits_for_conf_6": 14, + "ram_stop_bit_for_conf_6": 0, + "ram_data_for_conf_7": 0, + "ram_offset_bits_for_conf_7": 44, + "ram_stop_bit_for_conf_7": 1, + "ram_data_for_conf_8": 0, + "ram_offset_bits_for_conf_8": 0, + "ram_stop_bit_for_conf_8": 1, + "ram_data_for_conf_9": 0, + "ram_offset_bits_for_conf_9": 0, + "ram_stop_bit_for_conf_9": 1, + "ram_data_for_conf_10": 0, + "ram_offset_bits_for_conf_10": 0, + "ram_stop_bit_for_conf_10": 1, + "ram_data_for_conf_11": 0, + "ram_offset_bits_for_conf_11": 0, + "ram_stop_bit_for_conf_11": 1, + "ram_data_for_conf_12": 0, + "ram_offset_bits_for_conf_12": 0, + "ram_stop_bit_for_conf_12": 1, + "ram_data_for_conf_13": 0, + "ram_offset_bits_for_conf_13": 0, + "ram_stop_bit_for_conf_13": 1, + "ram_data_for_conf_14": 0, + "ram_offset_bits_for_conf_14": 0, + "ram_stop_bit_for_conf_14": 1, + "ram_data_for_conf_15": 0, + "ram_offset_bits_for_conf_15": 0, + "ram_stop_bit_for_conf_15": 1, + "ram_data_for_conf_16": 0, + "ram_offset_bits_for_conf_16": 0, + "ram_stop_bit_for_conf_16": 1, + "ram_data_for_conf_17": 0, + "ram_offset_bits_for_conf_17": 0, + "ram_stop_bit_for_conf_17": 1, + "ram_data_for_conf_18": 0, + "ram_offset_bits_for_conf_18": 0, + "ram_stop_bit_for_conf_18": 1, + "ram_data_for_conf_19": 0, + "ram_offset_bits_for_conf_19": 0, + "ram_stop_bit_for_conf_19": 1, + "ram_data_for_conf_20": 0, + "ram_offset_bits_for_conf_20": 0, + "ram_stop_bit_for_conf_20": 1, + "ram_data_for_conf_21": 0, + "ram_offset_bits_for_conf_21": 0, + "ram_stop_bit_for_conf_21": 1, + "ram_data_for_conf_22": 0, + "ram_offset_bits_for_conf_22": 0, + "ram_stop_bit_for_conf_22": 1, + "ram_data_for_conf_23": 0, + "ram_offset_bits_for_conf_23": 0, + "ram_stop_bit_for_conf_23": 1 + } + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/is25wj032f/ota/flash_disc_param_xspi.json b/boards/ti/lp_em_cc35x1/config/flash/is25wj032f/ota/flash_disc_param_xspi.json new file mode 100644 index 000000000000..c96cbac6431a --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/is25wj032f/ota/flash_disc_param_xspi.json @@ -0,0 +1,485 @@ +{ + "xspi_header": { + "name": "xSPIWFF3", + "device": "CC3500", + "use_hardware": "IS25WJ032F", + "use_case": "Quadro", + "dqs_support": 0, + "flash_only": 1, + "flash_separate_reset": 0, + "ram_separate_reset": true, + "clock_frequency": 80, + "qospi_clock_divider": 1, + "flash_device_character_conf": 0, + "ram_device_character_conf": 0, + "header_advanced": 0, + "phy_mode_enable": 1, + "pipeline_mode_enable": 1, + "loopback_support": "No", + "qspi_ref_clock": 80, + "spi_clock_freq": 20, + "spi_clock_divider": 1, + "flash_device_size": 4, + "flash_bytes_per_block": 16, + "flash_bytes_per_page": 256, + "flash_number_of_address_bytes": 3, + "flash_dual_opcode": 0, + "flash_jedec_manufacturer_id": 0, + "flash_jedec_device_id": 0, + "flash_name": "IS25WJ032F", + "flash_page_size": 256, + "flash_sector_size": 4096, + "flash_cs_polarity": "ACTIVE_LOW", + "flash_sw_reset_type": "x1xxxx", + "ram_device_size": 4, + "ram_bytes_per_block": 16, + "ram_bytes_per_page": 256, + "ram_number_of_address_bytes": 3, + "ram_dual_opcode": 0, + "ram_jedec_manufacturer_id": 0, + "ram_jedec_device_id": 0, + "ram_name": "NO_PSRAM", + "ram_page_size": 256, + "ram_sector_size": 4096, + "ram_cs_polarity": "ACTIVE_LOW", + "ram_sw_reset_type": "x1xxxx", + "flash_write_operation_modes": "4S-4S-4S", + "flash_read_operation_modes": "4S-4S-4S", + "ram_write_operation_modes": "4S-4S-4S", + "ram_read_operation_modes": "4S-4S-4S", + "crc_enable": 0, + "enable_dtr": 0, + "enable_ahb_decoder": 0, + "enter_xip_mod_immediately": 0, + "enter_xip_mod_next_read": 0, + "ahb_address_remapping": 0, + "enable_dma": 0, + "select_decode": 0, + "legacy_ip_mode": 0, + "direct_access": 1 + }, + "xspi_pinmux": { + "xspi_clk_input": 44, + "xspi_clk_input_use_hw": 0, + "xspi_clk_input_mode": "Input", + "xspi_clk_input_pull": "None", + "xspi_clk_input_interrupt_trigger": "Low", + "xspi_clk_input_dont_conf": 0, + "xspi_clk_input_output_strength": "High", + "xspi_clk_input_initial_output_state": "High", + "xspi_clk": 24, + "xspi_clk_use_hw": "None", + "xspi_clk_mode": "Output", + "xspi_clk_pull": "None", + "xspi_clk_output_strength": "High", + "xspi_clk_initial_output_state": "High", + "xspi_clk_interrupt_trigger": "None", + "xspi_clk_dont_conf": 0, + "xspi_flash_cs": 20, + "xspi_flash_cs_use_hw": "None", + "xspi_flash_cs_mode": "Output", + "xspi_flash_cs_pull": "None", + "xspi_flash_cs_output_strength": "High", + "xspi_flash_cs_initial_output_state": "High", + "xspi_flash_cs_interrupt_trigger": "None", + "xspi_flash_cs_dont_conf": 0, + "xspi_data_0": 25, + "xspi_data_0_use_hw": "None", + "xspi_data_0_mode": "Input", + "xspi_data_0_pull": "None", + "xspi_data_0_output_strength": "High", + "xspi_data_0_initial_output_state": "High", + "xspi_data_0_interrupt_trigger": "Low", + "xspi_data_0_dont_conf": 0, + "xspi_data_1": 21, + "xspi_data_1_use_hw": "None", + "xspi_data_1_mode": "Input", + "xspi_data_1_pull": "None", + "xspi_data_1_output_strength": "High", + "xspi_data_1_initial_output_state": "High", + "xspi_data_1_interrupt_trigger": "Low", + "xspi_data_1_dont_conf": 0, + "xspi_data_2": 22, + "xspi_data_2_use_hw": "None", + "xspi_data_2_mode": "Input", + "xspi_data_2_pull": "None", + "xspi_data_2_output_strength": "High", + "xspi_data_2_initial_output_state": "High", + "xspi_data_2_interrupt_trigger": "Low", + "xspi_data_2_dont_conf": 0, + "xspi_data_3": 23, + "xspi_data_3_use_hw": "None", + "xspi_data_3_mode": "Input", + "xspi_data_3_pull": "None", + "xspi_data_3_output_strength": "High", + "xspi_data_3_initial_output_state": "High", + "xspi_data_3_interrupt_trigger": "Low", + "xspi_data_3_dont_conf": 0, + "xspi_data_4": 26, + "xspi_data_4_use_hw": "None", + "xspi_data_4_mode": "Input", + "xspi_data_4_pull": "None", + "xspi_data_4_output_strength": "High", + "xspi_data_4_initial_output_state": "High", + "xspi_data_4_interrupt_trigger": "None", + "xspi_data_4_dont_conf": 0, + "xspi_data_5": 27, + "xspi_data_5_use_hw": "None", + "xspi_data_5_mode": "Input", + "xspi_data_5_pull": "None", + "xspi_data_5_output_strength": "High", + "xspi_data_5_initial_output_state": "High", + "xspi_data_5_interrupt_trigger": "None", + "xspi_data_5_dont_conf": 0, + "xspi_data_6": 28, + "xspi_data_6_use_hw": "None", + "xspi_data_6_mode": "Input", + "xspi_data_6_pull": "None", + "xspi_data_6_output_strength": "High", + "xspi_data_6_initial_output_state": "High", + "xspi_data_6_interrupt_trigger": "None", + "xspi_data_6_dont_conf": 0, + "xspi_data_7": 29, + "xspi_data_7_use_hw": "None", + "xspi_data_7_mode": "Input", + "xspi_data_7_pull": "None", + "xspi_data_7_output_strength": "High", + "xspi_data_7_initial_output_state": "High", + "xspi_data_7_interrupt_trigger": "None", + "xspi_data_7_dont_conf": 0, + "xspi_reset_flash": 36, + "xspi_reset_flash_use_hw": "None", + "xspi_reset_flash_mode": "Output", + "xspi_reset_flash_pull": "None", + "xspi_reset_flash_output_strength": "High", + "xspi_reset_flash_initial_output_state": "High", + "xspi_reset_flash_interrupt_trigger": "None", + "xspi_reset_flash_dont_conf": 0, + "xspi_cs_ram": 3, + "xspi_cs_ram_use_hw": "None", + "xspi_cs_ram_mode": "Output", + "xspi_cs_ram_pull": "None", + "xspi_cs_ram_output_strength": "High", + "xspi_cs_ram_initial_output_state": "High", + "xspi_cs_ram_interrupt_trigger": "None", + "xspi_cs_ram_dont_conf": 0, + "xspi_dqs": 30, + "xspi_dqs_use_hw": "None", + "xspi_dqs_mode": "Input", + "xspi_dqs_pull": "None", + "xspi_dqs_output_strength": "High", + "xspi_dqs_initial_output_state": "High", + "xspi_dqs_interrupt_trigger": "None", + "xspi_dqs_dont_conf": 0, + "xspi_reset_ram": 2, + "xspi_reset_ram_use_hw": "None", + "xspi_reset_ram_mode": "Input", + "xspi_reset_ram_pull": "None", + "xspi_reset_ram_output_strength": "High", + "xspi_reset_ram_initial_output_state": "High", + "xspi_reset_ram_interrupt_trigger": "None", + "xspi_reset_ram_dont_conf": 0 + }, + "xspi_operations": { + "xspi_operations_clocks": { + "clock_phase": 0, + "clock_polarity": 0, + "spi_mode": "2'b00" + }, + "xspi_operations_chip_select": { + "csda": 2, + "csdads": 0, + "cseot": 4, + "cssot": 1 + }, + "xspi_operations_reset": { + "flash_jedec_reset": 0, + "ram_jedec_reset": 0, + "flash_treset": 20, + "ram_treset": 20 + }, + "xspi_phy_operations": { + "flash_rx_dll_bypass_bit": 0, + "flash_dll_tx_delay": 22, + "flash_dll_rx_delay": 34, + "ram_rx_dll_bypass_bit": 0, + "ram_dll_tx_delay": 22, + "ram_dll_rx_delay": 34 + }, + "xspi_read_operations": { + "flash_dummy_rd_cycles": 4, + "flash_read_opcode": 11, + "suppl_flash_read_opcode": 0, + "ram_dummy_rd_cycles": 4, + "ram_read_opcode": 11, + "suppl_ram_read_opcode": 0, + "flash_non_cont_read_enable": 0, + "flash_max_read_jobs": 256, + "ram_non_cont_read_enable": 0, + "ram_max_read_jobs": 256, + "rww_en": 0, + "device_size": 4, + "number_of_banks": 1, + "bank_size": 4, + "mode_bit_enable": 0 + }, + "xspi_write_operations": { + "flash_address_and_data": { + "flash_dummy_wr_cycles": 0 + }, + "flash_command": { + "flash_write_opcode": 2, + "suppl_flash_write_opcode": 0 + }, + "ram_address_and_data": { + "ram_dummy_wr_cycles": 0 + }, + "ram_command": { + "ram_write_opcode": 2, + "suppl_ram_write_opcode": 0 + }, + "write_to_buffer": { + "flash_write_to_buffer_support": 0, + "ram_write_to_buffer_support": 0 + }, + "non_continuous_write": { + "flash_non_cont_write_enable": 0, + "flash_max_write_jobs": 64, + "ram_non_cont_write_enable": 0, + "ram_max_write_jobs": 0 + }, + "flash_program_operation": { + "flash_min_program_size": "256 B", + "flash_program_opcode": 2, + "suppl_flash_program_opcode": 0, + "flash_maximum_program_time_limit": 1600 + }, + "flash_erase_operation": { + "flash_min_erase_size": "4 kB", + "flash_erase_opcode": 32, + "suppl_flash_erase_opcode": 0, + "flash_maximum_erase_time_limit": 4095 + }, + "flash_erase_conf": { + "flash_block_erase_opcode": 0, + "suppl_block_flash_erase_opcode": 0, + "flash_sector_erase_opcode": 0, + "suppl_sector_flash_erase_opcode": 0, + "flash_chip_erase_opcode": 0, + "suppl_chip_flash_erase_opcode": 0 + }, + "ram_program_operation": { + "ram_min_program_size": "256 B", + "ram_program_opcode": 2, + "suppl_ram_program_opcode": 0, + "ram_maximum_program_time_limit": 1600 + }, + "ram_erase_conf": { + "ram_block_erase_opcode": 0, + "suppl_block_ram_erase_opcode": 0, + "ram_sector_erase_opcode": 0, + "suppl_sector_ram_erase_opcode": 0, + "ram_chip_erase_opcode": 0, + "suppl_chip_ram_erase_opcode": 0 + }, + "flash_buffer_support": { + "flash_pre_write_sequence": 0, + "flash_post_write_sequence": 0, + "flash_write_protection_timer_en": 0, + "flash_write_buffer_timer_mode": 16, + "flash_write_buffer_timer_range": 0, + "flash_service_interrupt_criteria": 0 + }, + "ram_buffer_support": { + "ram_pre_write_sequence": 0, + "ram_post_write_sequence": 0, + "ram_write_protection_timer_en": 0, + "ram_write_buffer_timer_mode": 16, + "ram_write_buffer_timer_range": 0, + "ram_service_interrupt_criteria": 0 + }, + "flash_pre_write_conf": { + "flash_pre_write_job_done_grant_sel": 0, + "data_for_flash_pre_write_conf_0": 0, + "offset_bits_for_flash_pre_write_conf_0": 0, + "stop_bit_for_flash_pre_write_conf_0": 1, + "data_for_flash_pre_write_conf_1": 0, + "offset_bits_for_flash_pre_write_conf_1": 0 + }, + "flash_post_write_conf": { + "flash_post_write_job_done_grant_sel": 0, + "data_for_flash_post_write_conf_0": 0, + "offset_bits_for_flash_post_write_conf_0": 0, + "stop_bit_for_flash_post_write_conf_0": 1, + "data_for_flash_post_write_conf_1": 0, + "offset_bits_for_flash_post_write_conf_1": 0 + }, + "ram_pre_write_conf": { + "ram_pre_write_job_done_grant_sel": 0, + "data_for_ram_pre_write_conf_0": 0, + "offset_bits_for_ram_pre_write_conf_0": 0, + "stop_bit_for_ram_pre_write_conf_0": 1, + "data_for_ram_pre_write_conf_1": 0, + "offset_bits_for_ram_pre_write_conf_1": 0 + }, + "ram_post_write_conf": { + "ram_post_write_job_done_grant_sel": 0, + "data_for_ram_post_write_conf_0": 0, + "offset_bits_for_ram_post_write_conf_0": 0, + "stop_bit_for_ram_post_write_conf_0": 1, + "data_for_ram_post_write_conf_1": 0, + "offset_bits_for_ram_post_write_conf_1": 0 + } + }, + "xspi_capture_operations": { + "read_data_capture": { + "flash_delay_transmitted_data": 0, + "flash_loopback_clock": 0, + "flash_bypass_adapted_loopback": 1, + "flash_sample_edge_sel": 0, + "ram_delay_transmitted_data": 0, + "ram_loopback_clock": 0, + "ram_bypass_adapted_loopback": 1, + "ram_sample_edge_sel": 0 + }, + "delays": { + "flash_full_half_cycle_delay": 0, + "flash_dll_bypass_mode": 1, + "flash_phase_detect_sel": 0, + "flash_dll_lock_num": 0, + "flash_dll_start_point": 0, + "flash_loopback_clock": 0, + "ram_full_half_cycle_delay": 0, + "ram_dll_bypass_mode": 1, + "ram_phase_detect_sel": 0, + "ram_dll_lock_num": 0, + "ram_dll_start_point": 0, + "ram_loopback_clock": 0 + }, + "operation_modes": { + "flash_sfdp_support": 0, + "ram_sfdp_support": 0, + "flash_pm_support": 0, + "ram_pm_support": 0, + "flash_sfdp_opcode": 0, + "suppl_flash_sfdp_opcode": 0, + "ram_sfdp_opcode": 0, + "suppl_ram_sfdp_opcode": 0, + "flash_enter_dpd_opcode": 185, + "suppl_flash_enter_dpd_opcode": 0, + "flash_exit_dpd_opcode": 171, + "suppl_flash_exit_dpd_opcode": 0, + "ram_enter_dpd_opcode": 185, + "suppl_ram_enter_dpd_opcode": 0, + "ram_exit_dpd_opcode": 171, + "suppl_ram_exit_dpd_opcode": 0, + "flash_quad_enable_opcode": 56, + "suppl_flash_quad_enable_opcode": 0, + "flash_quad_disable_opcode": 255, + "suppl_flash_quad_disable_opcode": 0, + "flash_octal_enable_opcode": 0, + "suppl_flash_octal_enable_opcode": 0, + "flash_octal_disable_opcode": 0, + "suppl_flash_octal_disable_opcode": 0, + "ram_quad_enable_opcode": 56, + "suppl_ram_quad_enable_opcode": 0, + "ram_quad_disable_opcode": 255, + "suppl_ram_quad_disable_opcode": 0, + "ram_octal_enable_opcode": 0, + "suppl_ram_octal_enable_opcode": 0, + "ram_octal_disable_opcode": 0, + "suppl_ram_octal_disable_opcode": 0 + } + } + }, + "external_memory_reporting": { + "header": { + "flash_auto_polling_enable": 1, + "flash_wel_enable": 1, + "flash_write_protect_enable": 0, + "flash_alternate_polling_conf_enable": 0, + "ram_auto_polling_enable": 1, + "ram_wel_enable": 1, + "ram_write_protect_enable": 0, + "ram_alternate_polling_conf_enable": 0 + }, + "flash_auto_polling": { + "flash_polling_repetition_delay": 0, + "flash_polling_count": 4, + "flash_enable_polling_expiration": 0, + "flash_polling_polarity": 0, + "flash_polling_address_phase_enable": 0, + "flash_polling_bit_index": 0, + "flash_numbers_poll_cycles": 65535, + "flash_dummy_autopoll_cycles": 0 + }, + "ram_auto_polling": { + "ram_polling_repetition_delay": 0, + "ram_polling_count": 4, + "ram_enable_polling_expiration": 0, + "ram_polling_polarity": 0, + "ram_polling_address_phase_enable": 0, + "ram_polling_bit_index": 0, + "ram_numbers_poll_cycles": 65535, + "ram_dummy_autopoll_cycles": 0 + }, + "flash_polling_command": { + "flash_polling_opcode": 5, + "suppl_flash_polling_opcode": 0 + }, + "ram_polling_command": { + "ram_polling_opcode": 5, + "suppl_ram_polling_opcode": 0 + }, + "flash_alternate_polling": { + "flash_polling_resp_count": 1023, + "flash_polling_iterations": 1, + "flash_polling_enabled": 0, + "flash_polling_disabled": 0, + "flash_grant_sel": 0, + "flash_data_for_enable_poling_conf_0": 0, + "flash_offset_bits_for_enable_poling_conf_0": 0, + "flash_stop_bit_for_enable_poling_conf_0": 1, + "flash_data_for_enable_poling_conf_1": 0, + "flash_offset_bits_for_enable_poling_conf_1": 0, + "flash_stop_bit_for_enable_poling_conf_1": 1, + "flash_data_for_disable_poling_conf_0": 0, + "flash_offset_bits_for_disable_poling_conf_0": 0, + "flash_stop_bit_for_disable_poling_conf_0": 1, + "flash_data_for_disable_poling_conf_1": 0, + "flash_offset_bits_for_disable_poling_conf_1": 0, + "flash_stop_bit_for_disable_poling_conf_1": 1 + }, + "ram_alternate_polling": { + "ram_polling_resp_count": 1023, + "ram_polling_iterations": 1, + "ram_polling_enabled": 0, + "ram_polling_disabled": 0, + "ram_grant_sel": 0, + "ram_data_for_enable_poling_conf_0": 0, + "ram_offset_bits_for_enable_poling_conf_0": 0, + "ram_stop_bit_for_enable_poling_conf_0": 1, + "ram_data_for_enable_poling_conf_1": 0, + "ram_offset_bits_for_enable_poling_conf_1": 0, + "ram_stop_bit_for_enable_poling_conf_1": 1, + "ram_data_for_disable_poling_conf_0": 0, + "ram_offset_bits_for_disable_poling_conf_0": 0, + "ram_stop_bit_for_disable_poling_conf_0": 1, + "ram_data_for_disable_poling_conf_1": 0, + "ram_offset_bits_for_disable_poling_conf_1": 0, + "ram_stop_bit_for_disable_poling_conf_1": 1 + }, + "flash_wel_command": { + "flash_wel_opcode": 6, + "suppl_flash_wel_opcode": 0 + }, + "ram_wel_command": { + "ram_wel_opcode": 6, + "suppl_ram_wel_opcode": 0 + } + }, + "event": { + "host_nvic_irq": 0, + "core_10_mux_sel": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/is25wj064f/flash_disc_param_ext_mem.json b/boards/ti/lp_em_cc35x1/config/flash/is25wj064f/flash_disc_param_ext_mem.json new file mode 100644 index 000000000000..6585853ccd5e --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/is25wj064f/flash_disc_param_ext_mem.json @@ -0,0 +1,99 @@ +{ + "vendor_primary_sbl": true, + "ti_wsoc_primary_container": true, + "ti_wsoc_bl2_primary_container": true, + "nvs_enable": true, + "vendor_alternate_image": true, + "vendor_sbl_alternate_image": true, + "ti_bl_alternate_image": true, + "ti_wsoc_alternate_image": true, + "ti_wsoc_bl2_alternate_image": true, + "region_0": { + "mem_region_0_start_phy_address": 2867200, + "mem_region_0_end_phy_address": 5627903, + "region0_boot": false, + "region0_main_code": true, + "region0_nvs": false, + "region0_wsoc_code": false, + "region0_alternate_code": false + }, + "region_1": { + "mem_region_1_start_phy_address": 0, + "mem_region_1_end_phy_address": 2867199, + "region1_boot": true, + "region1_main_code": false, + "region1_nvs": true, + "region1_wsoc_code": true, + "region1_alternate_code": false + }, + "region_2": { + "mem_region_2_start_phy_address": 5627904, + "mem_region_2_end_phy_address": 8388607, + "region2_boot": false, + "region2_main_code": false, + "region2_nvs": false, + "region2_wsoc_code": false, + "region2_alternate_code": true + }, + "region_3": { + "mem_region_3_start_phy_address": 0, + "mem_region_3_end_phy_address": 0, + "region3_boot": false, + "region3_main_code": false, + "region3_nvs": false, + "region3_wsoc_code": false, + "region3_alternate_code": false + }, + "boot_region_conf": { + "boot_region_size": 0, + "boot_region_flash_disco_param_start_address": 0, + "boot_region_primary_ti_bl_start_phy_address": 12284, + "boot_region_primary_ti_bl_magic": 0, + "boot_region_primary_ti_bl_major": 0, + "boot_region_primary_ti_bl_minor": 0, + "boot_region_sec_ti_bl_start_phy_address": 430076, + "boot_region_sec_ti_bl_magic": 0, + "boot_region_sec_ti_bl_major": 0, + "boot_region_sec_ti_bl_minor": 0 + }, + "main_code_region_conf": { + "main_code_region_vendor_image_start_phy_address": 2871292, + "main_code_region_vendor_image_magic": 0, + "main_code_region_vendor_image_major": 0, + "main_code_region_vendor_image_minor": 0, + "main_code_region_sbl_start_phy_address": 0, + "main_code_region_sbl_magic": 0, + "main_code_region_sbl_major": 0, + "main_code_region_sbl_minor": 0 + }, + "alt_code_region_conf": { + "alt_code_region_vendor_image_start_phy_address": 5631996, + "alt_code_region_vendor_image_magic": 0, + "alt_code_region_vendor_image_major": 0, + "alt_code_region_vendor_image_minor": 0, + "alt_code_region_sbl_start_phy_address": 0, + "alt_code_region_sbl_magic": 0, + "alt_code_region_sbl_major": 0, + "alt_code_region_sbl_minor": 0 + }, + "nvs_code_region_conf": { + "nvs_start_phy_address": 1777664, + "nvs_region_size": 1089536, + "nvs_region_primary_wsoc_start_phy_address": 847868, + "nvs_region_primary_wsoc_magic": 0, + "nvs_region_primary_wsoc_major": 0, + "nvs_region_primary_wsoc_minor": 0, + "nvs_region_sec_wsoc_start_phy_address": 1314812, + "nvs_region_sec_wsoc_magic": 0, + "nvs_region_sec_wsoc_major": 0, + "nvs_region_sec_wsoc_minor": 0, + "nvs_region_primary_wsoc_bl2_start_phy_address": 0, + "nvs_region_primary_wsoc_bl2_magic": 0, + "nvs_region_primary_wsoc_bl2_major": 0, + "nvs_region_primary_wsoc_bl2_minor": 0, + "nvs_region_sec_wsoc_bl2_start_phy_address": 0, + "nvs_region_sec_wsoc_bl2_magic": 0, + "nvs_region_sec_wsoc_bl2_major": 0, + "nvs_region_sec_wsoc_bl2_minor": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/is25wj064f/flash_disc_param_otfde.json b/boards/ti/lp_em_cc35x1/config/flash/is25wj064f/flash_disc_param_otfde.json new file mode 100644 index 000000000000..22a24d3d5430 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/is25wj064f/flash_disc_param_otfde.json @@ -0,0 +1,286 @@ +{ + "otfde_header": { + "name": "OTFDEWFF3", + "flash_only": true, + "ip_protection": false, + "regions_lock": false, + "regions_number": 4, + "flash_enabled": true + }, + "bl_conf": { + "host_boot_done_lock": true, + "host_peripherals_lock": true, + "icache_conf_lock": true, + "m33_mem_part_lock": true, + "memss_firewall_lock": true, + "dma_channel_owner_lock": true, + "otfde_region_lock": true, + "core_events_lock": true + }, + "otfde_general": { + "parameters": { + "mem_otfde_initial_delay": 10, + "otfde_global_watchdog_timer": 5 + }, + "events": { + "reset_evt_mask": false, + "reset_evt_suspend": false, + "sft_reset_evt_mask": false, + "sft_reset_evt_suspend": false, + "bypass_mode_evt_mask": false, + "bypass_mode_evt_suspend": false, + "debug_mode_evt_mask": false, + "debug_mode_evt_suspend": false, + "general_evt_mask": false, + "general_evt_suspend": false, + "xspi_data_path_evt_mask": false, + "xspi_data_path_evt_suspend": false, + "xspi_cnfg_path_evt_mask": false, + "xspi_cnfg_path_evt_suspend": false, + "xspi_service_interrupt_evt_mask": false, + "xspi_service_interrupt_evt_suspend": false, + "trans_device_disabled_evt_mask": false, + "trans_device_disabled_evt_suspend": false, + "trans_region_disabled_evt_mask": false, + "trans_region_disabled_evt_suspend": false, + "trans_region_params_conf_evt_mask": false, + "trans_region_params_conf_evt_suspend": false, + "trans_multiple_regions_mapped_evt_mask": false, + "trans_multiple_regions_mapped_evt_suspend": false, + "trans_address_not_32_bit_evt_mask": false, + "trans_address_not_32_bit_evt_suspend": false, + "trans_size_not_32_bit_evt_mask": false, + "trans_size_not_32_bit_evt_suspend": false, + "trans_burst_not_32_bit_evt_mask": false, + "trans_burst_not_32_bit_evt_suspend": false, + "region_read_write_def_evt_mask": false, + "region_read_write_def_evt_suspend": false, + "suspend_while_disabled_evt_mask": false, + "suspend_while_disabled_evt_suspend": false + } + }, + "regions_settings": { + "region_parameters_lock": { + "REGION_0_PARAMS_0": true, + "REGION_0_PARAMS_1": true, + "REGION_0_PARAMS_2": true, + "REGION_1_PARAMS_0": false, + "REGION_1_PARAMS_1": false, + "REGION_1_PARAMS_2": false, + "REGION_2_PARAMS_0": true, + "REGION_2_PARAMS_1": true, + "REGION_2_PARAMS_2": true, + "REGION_3_PARAMS_0": false, + "REGION_3_PARAMS_1": false, + "REGION_3_PARAMS_2": false + }, + "region_0_protection": { + "mem_region_0_enabled": true, + "mem_region_0_device_id": 0, + "mem_region_0_spi_write_enable": true, + "mem_region_0_spi_read_enable": true, + "mem_region_0_physical_offset": 700, + "mem_region_0_security_id_msb": 0, + "mem_region_0_start_address": 81920, + "mem_region_0_end_address": 82593, + "mem_region_0_security_id_lsb": 0, + "mem_otfde_region_0_write_lock_en": false, + "mem_otfde_region_0_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_1_protection": { + "mem_region_1_enabled": true, + "mem_region_1_device_id": 0, + "mem_region_1_spi_write_enable": true, + "mem_region_1_spi_read_enable": true, + "mem_region_1_physical_offset": 0, + "mem_region_1_security_id_msb": 0, + "mem_region_1_start_address": 655360, + "mem_region_1_end_address": 656059, + "mem_region_1_security_id_lsb": 0, + "mem_otfde_region_1_write_lock_en": false, + "mem_otfde_region_1_enc_dec_bypass": "Bypass" + }, + "region_2_protection": { + "mem_region_2_enabled": true, + "mem_region_2_device_id": 0, + "mem_region_2_spi_write_enable": true, + "mem_region_2_spi_read_enable": true, + "mem_region_2_physical_offset": 1374, + "mem_region_2_security_id_msb": 0, + "mem_region_2_start_address": 671744, + "mem_region_2_end_address": 672417, + "mem_region_2_security_id_lsb": 0, + "mem_otfde_region_2_write_lock_en": false, + "mem_otfde_region_2_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_3_protection": { + "mem_region_3_enabled": false, + "mem_region_3_device_id": 1, + "mem_region_3_spi_write_enable": true, + "mem_region_3_spi_read_enable": true, + "mem_region_3_physical_offset": 0, + "mem_region_3_security_id_msb": 0, + "mem_region_3_start_address": 1, + "mem_region_3_end_address": 0, + "mem_region_3_security_id_lsb": 0, + "mem_otfde_region_3_write_lock_en": false, + "mem_otfde_region_3_enc_dec_bypass": "Bypass" + } + }, + "devices": { + "header": { + "flash_device_switch_conf": 1, + "ram_device_switch_conf": 1 + }, + "flash_switch": { + "flash_grant_sel": 0, + "flash_data_for_conf_0": 2181562505, + "flash_offset_bits_for_conf_0": 0, + "flash_stop_bit_for_conf_0": 0, + "flash_data_for_conf_1": 67248651, + "flash_offset_bits_for_conf_1": 1, + "flash_stop_bit_for_conf_1": 0, + "flash_data_for_conf_2": 139266, + "flash_offset_bits_for_conf_2": 2, + "flash_stop_bit_for_conf_2": 0, + "flash_data_for_conf_3": 1, + "flash_offset_bits_for_conf_3": 4, + "flash_stop_bit_for_conf_3": 0, + "flash_data_for_conf_4": 1076887634, + "flash_offset_bits_for_conf_4": 45, + "flash_stop_bit_for_conf_4": 0, + "flash_data_for_conf_5": 3224371282, + "flash_offset_bits_for_conf_5": 45, + "flash_stop_bit_for_conf_5": 0, + "flash_data_for_conf_6": 262149, + "flash_offset_bits_for_conf_6": 14, + "flash_stop_bit_for_conf_6": 0, + "flash_data_for_conf_7": 0, + "flash_offset_bits_for_conf_7": 44, + "flash_stop_bit_for_conf_7": 1, + "flash_data_for_conf_8": 0, + "flash_offset_bits_for_conf_8": 0, + "flash_stop_bit_for_conf_8": 1, + "flash_data_for_conf_9": 0, + "flash_offset_bits_for_conf_9": 0, + "flash_stop_bit_for_conf_9": 1, + "flash_data_for_conf_10": 0, + "flash_offset_bits_for_conf_10": 0, + "flash_stop_bit_for_conf_10": 1, + "flash_data_for_conf_11": 0, + "flash_offset_bits_for_conf_11": 0, + "flash_stop_bit_for_conf_11": 1, + "flash_data_for_conf_12": 0, + "flash_offset_bits_for_conf_12": 0, + "flash_stop_bit_for_conf_12": 1, + "flash_data_for_conf_13": 0, + "flash_offset_bits_for_conf_13": 0, + "flash_stop_bit_for_conf_13": 1, + "flash_data_for_conf_14": 0, + "flash_offset_bits_for_conf_14": 0, + "flash_stop_bit_for_conf_14": 1, + "flash_data_for_conf_15": 0, + "flash_offset_bits_for_conf_15": 0, + "flash_stop_bit_for_conf_15": 1, + "flash_data_for_conf_16": 0, + "flash_offset_bits_for_conf_16": 0, + "flash_stop_bit_for_conf_16": 1, + "flash_data_for_conf_17": 0, + "flash_offset_bits_for_conf_17": 0, + "flash_stop_bit_for_conf_17": 1, + "flash_data_for_conf_18": 0, + "flash_offset_bits_for_conf_18": 0, + "flash_stop_bit_for_conf_18": 1, + "flash_data_for_conf_19": 0, + "flash_offset_bits_for_conf_19": 0, + "flash_stop_bit_for_conf_19": 1, + "flash_data_for_conf_20": 0, + "flash_offset_bits_for_conf_20": 0, + "flash_stop_bit_for_conf_20": 1, + "flash_data_for_conf_21": 0, + "flash_offset_bits_for_conf_21": 0, + "flash_stop_bit_for_conf_21": 1, + "flash_data_for_conf_22": 0, + "flash_offset_bits_for_conf_22": 0, + "flash_stop_bit_for_conf_22": 1, + "flash_data_for_conf_23": 0, + "flash_offset_bits_for_conf_23": 0, + "flash_stop_bit_for_conf_23": 1 + }, + "ram_switch": { + "ram_grant_sel": 0, + "ram_data_for_conf_0": 2181562505, + "ram_offset_bits_for_conf_0": 0, + "ram_stop_bit_for_conf_0": 0, + "ram_data_for_conf_1": 67248651, + "ram_offset_bits_for_conf_1": 1, + "ram_stop_bit_for_conf_1": 0, + "ram_data_for_conf_2": 139266, + "ram_offset_bits_for_conf_2": 2, + "ram_stop_bit_for_conf_2": 0, + "ram_data_for_conf_3": 1, + "ram_offset_bits_for_conf_3": 4, + "ram_stop_bit_for_conf_3": 0, + "ram_data_for_conf_4": 1076887634, + "ram_offset_bits_for_conf_4": 45, + "ram_stop_bit_for_conf_4": 0, + "ram_data_for_conf_5": 3224371282, + "ram_offset_bits_for_conf_5": 45, + "ram_stop_bit_for_conf_5": 0, + "ram_data_for_conf_6": 262149, + "ram_offset_bits_for_conf_6": 14, + "ram_stop_bit_for_conf_6": 0, + "ram_data_for_conf_7": 0, + "ram_offset_bits_for_conf_7": 44, + "ram_stop_bit_for_conf_7": 1, + "ram_data_for_conf_8": 0, + "ram_offset_bits_for_conf_8": 0, + "ram_stop_bit_for_conf_8": 1, + "ram_data_for_conf_9": 0, + "ram_offset_bits_for_conf_9": 0, + "ram_stop_bit_for_conf_9": 1, + "ram_data_for_conf_10": 0, + "ram_offset_bits_for_conf_10": 0, + "ram_stop_bit_for_conf_10": 1, + "ram_data_for_conf_11": 0, + "ram_offset_bits_for_conf_11": 0, + "ram_stop_bit_for_conf_11": 1, + "ram_data_for_conf_12": 0, + "ram_offset_bits_for_conf_12": 0, + "ram_stop_bit_for_conf_12": 1, + "ram_data_for_conf_13": 0, + "ram_offset_bits_for_conf_13": 0, + "ram_stop_bit_for_conf_13": 1, + "ram_data_for_conf_14": 0, + "ram_offset_bits_for_conf_14": 0, + "ram_stop_bit_for_conf_14": 1, + "ram_data_for_conf_15": 0, + "ram_offset_bits_for_conf_15": 0, + "ram_stop_bit_for_conf_15": 1, + "ram_data_for_conf_16": 0, + "ram_offset_bits_for_conf_16": 0, + "ram_stop_bit_for_conf_16": 1, + "ram_data_for_conf_17": 0, + "ram_offset_bits_for_conf_17": 0, + "ram_stop_bit_for_conf_17": 1, + "ram_data_for_conf_18": 0, + "ram_offset_bits_for_conf_18": 0, + "ram_stop_bit_for_conf_18": 1, + "ram_data_for_conf_19": 0, + "ram_offset_bits_for_conf_19": 0, + "ram_stop_bit_for_conf_19": 1, + "ram_data_for_conf_20": 0, + "ram_offset_bits_for_conf_20": 0, + "ram_stop_bit_for_conf_20": 1, + "ram_data_for_conf_21": 0, + "ram_offset_bits_for_conf_21": 0, + "ram_stop_bit_for_conf_21": 1, + "ram_data_for_conf_22": 0, + "ram_offset_bits_for_conf_22": 0, + "ram_stop_bit_for_conf_22": 1, + "ram_data_for_conf_23": 0, + "ram_offset_bits_for_conf_23": 0, + "ram_stop_bit_for_conf_23": 1 + } + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/is25wj064f/flash_disc_param_xspi.json b/boards/ti/lp_em_cc35x1/config/flash/is25wj064f/flash_disc_param_xspi.json new file mode 100644 index 000000000000..1c27fb760476 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/is25wj064f/flash_disc_param_xspi.json @@ -0,0 +1,485 @@ +{ + "xspi_header": { + "name": "xSPIWFF3", + "device": "CC3500", + "use_hardware": "IS25WJ064F", + "use_case": "Quadro", + "dqs_support": 0, + "flash_only": 1, + "flash_separate_reset": 0, + "ram_separate_reset": true, + "clock_frequency": 80, + "qospi_clock_divider": 1, + "flash_device_character_conf": 0, + "ram_device_character_conf": 0, + "header_advanced": 0, + "phy_mode_enable": 1, + "pipeline_mode_enable": 1, + "loopback_support": "No", + "qspi_ref_clock": 80, + "spi_clock_freq": 20, + "spi_clock_divider": 1, + "flash_device_size": 8, + "flash_bytes_per_block": 16, + "flash_bytes_per_page": 256, + "flash_number_of_address_bytes": 3, + "flash_dual_opcode": 0, + "flash_jedec_manufacturer_id": 0, + "flash_jedec_device_id": 0, + "flash_name": "IS25WJ064F", + "flash_page_size": 256, + "flash_sector_size": 4096, + "flash_cs_polarity": "ACTIVE_LOW", + "flash_sw_reset_type": "x1xxxx", + "ram_device_size": 8, + "ram_bytes_per_block": 16, + "ram_bytes_per_page": 256, + "ram_number_of_address_bytes": 3, + "ram_dual_opcode": 0, + "ram_jedec_manufacturer_id": 0, + "ram_jedec_device_id": 0, + "ram_name": "NO_PSRAM", + "ram_page_size": 256, + "ram_sector_size": 4096, + "ram_cs_polarity": "ACTIVE_LOW", + "ram_sw_reset_type": "x1xxxx", + "flash_write_operation_modes": "4S-4S-4S", + "flash_read_operation_modes": "4S-4S-4S", + "ram_write_operation_modes": "4S-4S-4S", + "ram_read_operation_modes": "4S-4S-4S", + "crc_enable": 0, + "enable_dtr": 0, + "enable_ahb_decoder": 0, + "enter_xip_mod_immediately": 0, + "enter_xip_mod_next_read": 0, + "ahb_address_remapping": 0, + "enable_dma": 0, + "select_decode": 0, + "legacy_ip_mode": 0, + "direct_access": 1 + }, + "xspi_pinmux": { + "xspi_clk_input": 44, + "xspi_clk_input_use_hw": 0, + "xspi_clk_input_mode": "Input", + "xspi_clk_input_pull": "None", + "xspi_clk_input_interrupt_trigger": "Low", + "xspi_clk_input_dont_conf": 0, + "xspi_clk_input_output_strength": "High", + "xspi_clk_input_initial_output_state": "High", + "xspi_clk": 24, + "xspi_clk_use_hw": "None", + "xspi_clk_mode": "Output", + "xspi_clk_pull": "None", + "xspi_clk_output_strength": "High", + "xspi_clk_initial_output_state": "High", + "xspi_clk_interrupt_trigger": "None", + "xspi_clk_dont_conf": 0, + "xspi_flash_cs": 20, + "xspi_flash_cs_use_hw": "None", + "xspi_flash_cs_mode": "Output", + "xspi_flash_cs_pull": "None", + "xspi_flash_cs_output_strength": "High", + "xspi_flash_cs_initial_output_state": "High", + "xspi_flash_cs_interrupt_trigger": "None", + "xspi_flash_cs_dont_conf": 0, + "xspi_data_0": 25, + "xspi_data_0_use_hw": "None", + "xspi_data_0_mode": "Input", + "xspi_data_0_pull": "None", + "xspi_data_0_output_strength": "High", + "xspi_data_0_initial_output_state": "High", + "xspi_data_0_interrupt_trigger": "Low", + "xspi_data_0_dont_conf": 0, + "xspi_data_1": 21, + "xspi_data_1_use_hw": "None", + "xspi_data_1_mode": "Input", + "xspi_data_1_pull": "None", + "xspi_data_1_output_strength": "High", + "xspi_data_1_initial_output_state": "High", + "xspi_data_1_interrupt_trigger": "Low", + "xspi_data_1_dont_conf": 0, + "xspi_data_2": 22, + "xspi_data_2_use_hw": "None", + "xspi_data_2_mode": "Input", + "xspi_data_2_pull": "None", + "xspi_data_2_output_strength": "High", + "xspi_data_2_initial_output_state": "High", + "xspi_data_2_interrupt_trigger": "Low", + "xspi_data_2_dont_conf": 0, + "xspi_data_3": 23, + "xspi_data_3_use_hw": "None", + "xspi_data_3_mode": "Input", + "xspi_data_3_pull": "None", + "xspi_data_3_output_strength": "High", + "xspi_data_3_initial_output_state": "High", + "xspi_data_3_interrupt_trigger": "Low", + "xspi_data_3_dont_conf": 0, + "xspi_data_4": 26, + "xspi_data_4_use_hw": "None", + "xspi_data_4_mode": "Input", + "xspi_data_4_pull": "None", + "xspi_data_4_output_strength": "High", + "xspi_data_4_initial_output_state": "High", + "xspi_data_4_interrupt_trigger": "None", + "xspi_data_4_dont_conf": 0, + "xspi_data_5": 27, + "xspi_data_5_use_hw": "None", + "xspi_data_5_mode": "Input", + "xspi_data_5_pull": "None", + "xspi_data_5_output_strength": "High", + "xspi_data_5_initial_output_state": "High", + "xspi_data_5_interrupt_trigger": "None", + "xspi_data_5_dont_conf": 0, + "xspi_data_6": 28, + "xspi_data_6_use_hw": "None", + "xspi_data_6_mode": "Input", + "xspi_data_6_pull": "None", + "xspi_data_6_output_strength": "High", + "xspi_data_6_initial_output_state": "High", + "xspi_data_6_interrupt_trigger": "None", + "xspi_data_6_dont_conf": 0, + "xspi_data_7": 29, + "xspi_data_7_use_hw": "None", + "xspi_data_7_mode": "Input", + "xspi_data_7_pull": "None", + "xspi_data_7_output_strength": "High", + "xspi_data_7_initial_output_state": "High", + "xspi_data_7_interrupt_trigger": "None", + "xspi_data_7_dont_conf": 0, + "xspi_reset_flash": 36, + "xspi_reset_flash_use_hw": "None", + "xspi_reset_flash_mode": "Output", + "xspi_reset_flash_pull": "None", + "xspi_reset_flash_output_strength": "High", + "xspi_reset_flash_initial_output_state": "High", + "xspi_reset_flash_interrupt_trigger": "None", + "xspi_reset_flash_dont_conf": 0, + "xspi_cs_ram": 3, + "xspi_cs_ram_use_hw": "None", + "xspi_cs_ram_mode": "Output", + "xspi_cs_ram_pull": "None", + "xspi_cs_ram_output_strength": "High", + "xspi_cs_ram_initial_output_state": "High", + "xspi_cs_ram_interrupt_trigger": "None", + "xspi_cs_ram_dont_conf": 0, + "xspi_dqs": 30, + "xspi_dqs_use_hw": "None", + "xspi_dqs_mode": "Input", + "xspi_dqs_pull": "None", + "xspi_dqs_output_strength": "High", + "xspi_dqs_initial_output_state": "High", + "xspi_dqs_interrupt_trigger": "None", + "xspi_dqs_dont_conf": 0, + "xspi_reset_ram": 2, + "xspi_reset_ram_use_hw": "None", + "xspi_reset_ram_mode": "Input", + "xspi_reset_ram_pull": "None", + "xspi_reset_ram_output_strength": "High", + "xspi_reset_ram_initial_output_state": "High", + "xspi_reset_ram_interrupt_trigger": "None", + "xspi_reset_ram_dont_conf": 0 + }, + "xspi_operations": { + "xspi_operations_clocks": { + "clock_phase": 0, + "clock_polarity": 0, + "spi_mode": "2'b00" + }, + "xspi_operations_chip_select": { + "csda": 2, + "csdads": 0, + "cseot": 4, + "cssot": 1 + }, + "xspi_operations_reset": { + "flash_jedec_reset": 0, + "ram_jedec_reset": 0, + "flash_treset": 20, + "ram_treset": 20 + }, + "xspi_phy_operations": { + "flash_rx_dll_bypass_bit": 0, + "flash_dll_tx_delay": 22, + "flash_dll_rx_delay": 34, + "ram_rx_dll_bypass_bit": 0, + "ram_dll_tx_delay": 22, + "ram_dll_rx_delay": 34 + }, + "xspi_read_operations": { + "flash_dummy_rd_cycles": 4, + "flash_read_opcode": 11, + "suppl_flash_read_opcode": 0, + "ram_dummy_rd_cycles": 4, + "ram_read_opcode": 11, + "suppl_ram_read_opcode": 0, + "flash_non_cont_read_enable": 0, + "flash_max_read_jobs": 256, + "ram_non_cont_read_enable": 0, + "ram_max_read_jobs": 256, + "rww_en": 0, + "device_size": 8, + "number_of_banks": 1, + "bank_size": 8, + "mode_bit_enable": 0 + }, + "xspi_write_operations": { + "flash_address_and_data": { + "flash_dummy_wr_cycles": 0 + }, + "flash_command": { + "flash_write_opcode": 2, + "suppl_flash_write_opcode": 0 + }, + "ram_address_and_data": { + "ram_dummy_wr_cycles": 0 + }, + "ram_command": { + "ram_write_opcode": 2, + "suppl_ram_write_opcode": 0 + }, + "write_to_buffer": { + "flash_write_to_buffer_support": 0, + "ram_write_to_buffer_support": 0 + }, + "non_continuous_write": { + "flash_non_cont_write_enable": 0, + "flash_max_write_jobs": 64, + "ram_non_cont_write_enable": 0, + "ram_max_write_jobs": 0 + }, + "flash_program_operation": { + "flash_min_program_size": "256 B", + "flash_program_opcode": 2, + "suppl_flash_program_opcode": 0, + "flash_maximum_program_time_limit": 1600 + }, + "flash_erase_operation": { + "flash_min_erase_size": "4 kB", + "flash_erase_opcode": 32, + "suppl_flash_erase_opcode": 0, + "flash_maximum_erase_time_limit": 4095 + }, + "flash_erase_conf": { + "flash_block_erase_opcode": 0, + "suppl_block_flash_erase_opcode": 0, + "flash_sector_erase_opcode": 0, + "suppl_sector_flash_erase_opcode": 0, + "flash_chip_erase_opcode": 0, + "suppl_chip_flash_erase_opcode": 0 + }, + "ram_program_operation": { + "ram_min_program_size": "256 B", + "ram_program_opcode": 2, + "suppl_ram_program_opcode": 0, + "ram_maximum_program_time_limit": 1600 + }, + "ram_erase_conf": { + "ram_block_erase_opcode": 0, + "suppl_block_ram_erase_opcode": 0, + "ram_sector_erase_opcode": 0, + "suppl_sector_ram_erase_opcode": 0, + "ram_chip_erase_opcode": 0, + "suppl_chip_ram_erase_opcode": 0 + }, + "flash_buffer_support": { + "flash_pre_write_sequence": 0, + "flash_post_write_sequence": 0, + "flash_write_protection_timer_en": 0, + "flash_write_buffer_timer_mode": 16, + "flash_write_buffer_timer_range": 0, + "flash_service_interrupt_criteria": 0 + }, + "ram_buffer_support": { + "ram_pre_write_sequence": 0, + "ram_post_write_sequence": 0, + "ram_write_protection_timer_en": 0, + "ram_write_buffer_timer_mode": 16, + "ram_write_buffer_timer_range": 0, + "ram_service_interrupt_criteria": 0 + }, + "flash_pre_write_conf": { + "flash_pre_write_job_done_grant_sel": 0, + "data_for_flash_pre_write_conf_0": 0, + "offset_bits_for_flash_pre_write_conf_0": 0, + "stop_bit_for_flash_pre_write_conf_0": 1, + "data_for_flash_pre_write_conf_1": 0, + "offset_bits_for_flash_pre_write_conf_1": 0 + }, + "flash_post_write_conf": { + "flash_post_write_job_done_grant_sel": 0, + "data_for_flash_post_write_conf_0": 0, + "offset_bits_for_flash_post_write_conf_0": 0, + "stop_bit_for_flash_post_write_conf_0": 1, + "data_for_flash_post_write_conf_1": 0, + "offset_bits_for_flash_post_write_conf_1": 0 + }, + "ram_pre_write_conf": { + "ram_pre_write_job_done_grant_sel": 0, + "data_for_ram_pre_write_conf_0": 0, + "offset_bits_for_ram_pre_write_conf_0": 0, + "stop_bit_for_ram_pre_write_conf_0": 1, + "data_for_ram_pre_write_conf_1": 0, + "offset_bits_for_ram_pre_write_conf_1": 0 + }, + "ram_post_write_conf": { + "ram_post_write_job_done_grant_sel": 0, + "data_for_ram_post_write_conf_0": 0, + "offset_bits_for_ram_post_write_conf_0": 0, + "stop_bit_for_ram_post_write_conf_0": 1, + "data_for_ram_post_write_conf_1": 0, + "offset_bits_for_ram_post_write_conf_1": 0 + } + }, + "xspi_capture_operations": { + "read_data_capture": { + "flash_delay_transmitted_data": 0, + "flash_loopback_clock": 0, + "flash_bypass_adapted_loopback": 1, + "flash_sample_edge_sel": 0, + "ram_delay_transmitted_data": 0, + "ram_loopback_clock": 0, + "ram_bypass_adapted_loopback": 1, + "ram_sample_edge_sel": 0 + }, + "delays": { + "flash_full_half_cycle_delay": 0, + "flash_dll_bypass_mode": 1, + "flash_phase_detect_sel": 0, + "flash_dll_lock_num": 0, + "flash_dll_start_point": 0, + "flash_loopback_clock": 0, + "ram_full_half_cycle_delay": 0, + "ram_dll_bypass_mode": 1, + "ram_phase_detect_sel": 0, + "ram_dll_lock_num": 0, + "ram_dll_start_point": 0, + "ram_loopback_clock": 0 + }, + "operation_modes": { + "flash_sfdp_support": 0, + "ram_sfdp_support": 0, + "flash_pm_support": 0, + "ram_pm_support": 0, + "flash_sfdp_opcode": 0, + "suppl_flash_sfdp_opcode": 0, + "ram_sfdp_opcode": 0, + "suppl_ram_sfdp_opcode": 0, + "flash_enter_dpd_opcode": 185, + "suppl_flash_enter_dpd_opcode": 0, + "flash_exit_dpd_opcode": 171, + "suppl_flash_exit_dpd_opcode": 0, + "ram_enter_dpd_opcode": 185, + "suppl_ram_enter_dpd_opcode": 0, + "ram_exit_dpd_opcode": 171, + "suppl_ram_exit_dpd_opcode": 0, + "flash_quad_enable_opcode": 56, + "suppl_flash_quad_enable_opcode": 0, + "flash_quad_disable_opcode": 255, + "suppl_flash_quad_disable_opcode": 0, + "flash_octal_enable_opcode": 0, + "suppl_flash_octal_enable_opcode": 0, + "flash_octal_disable_opcode": 0, + "suppl_flash_octal_disable_opcode": 0, + "ram_quad_enable_opcode": 56, + "suppl_ram_quad_enable_opcode": 0, + "ram_quad_disable_opcode": 255, + "suppl_ram_quad_disable_opcode": 0, + "ram_octal_enable_opcode": 0, + "suppl_ram_octal_enable_opcode": 0, + "ram_octal_disable_opcode": 0, + "suppl_ram_octal_disable_opcode": 0 + } + } + }, + "external_memory_reporting": { + "header": { + "flash_auto_polling_enable": 1, + "flash_wel_enable": 1, + "flash_write_protect_enable": 0, + "flash_alternate_polling_conf_enable": 0, + "ram_auto_polling_enable": 1, + "ram_wel_enable": 1, + "ram_write_protect_enable": 0, + "ram_alternate_polling_conf_enable": 0 + }, + "flash_auto_polling": { + "flash_polling_repetition_delay": 0, + "flash_polling_count": 4, + "flash_enable_polling_expiration": 0, + "flash_polling_polarity": 0, + "flash_polling_address_phase_enable": 0, + "flash_polling_bit_index": 0, + "flash_numbers_poll_cycles": 65535, + "flash_dummy_autopoll_cycles": 0 + }, + "ram_auto_polling": { + "ram_polling_repetition_delay": 0, + "ram_polling_count": 4, + "ram_enable_polling_expiration": 0, + "ram_polling_polarity": 0, + "ram_polling_address_phase_enable": 0, + "ram_polling_bit_index": 0, + "ram_numbers_poll_cycles": 65535, + "ram_dummy_autopoll_cycles": 0 + }, + "flash_polling_command": { + "flash_polling_opcode": 5, + "suppl_flash_polling_opcode": 0 + }, + "ram_polling_command": { + "ram_polling_opcode": 5, + "suppl_ram_polling_opcode": 0 + }, + "flash_alternate_polling": { + "flash_polling_resp_count": 1023, + "flash_polling_iterations": 1, + "flash_polling_enabled": 0, + "flash_polling_disabled": 0, + "flash_grant_sel": 0, + "flash_data_for_enable_poling_conf_0": 0, + "flash_offset_bits_for_enable_poling_conf_0": 0, + "flash_stop_bit_for_enable_poling_conf_0": 1, + "flash_data_for_enable_poling_conf_1": 0, + "flash_offset_bits_for_enable_poling_conf_1": 0, + "flash_stop_bit_for_enable_poling_conf_1": 1, + "flash_data_for_disable_poling_conf_0": 0, + "flash_offset_bits_for_disable_poling_conf_0": 0, + "flash_stop_bit_for_disable_poling_conf_0": 1, + "flash_data_for_disable_poling_conf_1": 0, + "flash_offset_bits_for_disable_poling_conf_1": 0, + "flash_stop_bit_for_disable_poling_conf_1": 1 + }, + "ram_alternate_polling": { + "ram_polling_resp_count": 1023, + "ram_polling_iterations": 1, + "ram_polling_enabled": 0, + "ram_polling_disabled": 0, + "ram_grant_sel": 0, + "ram_data_for_enable_poling_conf_0": 0, + "ram_offset_bits_for_enable_poling_conf_0": 0, + "ram_stop_bit_for_enable_poling_conf_0": 1, + "ram_data_for_enable_poling_conf_1": 0, + "ram_offset_bits_for_enable_poling_conf_1": 0, + "ram_stop_bit_for_enable_poling_conf_1": 1, + "ram_data_for_disable_poling_conf_0": 0, + "ram_offset_bits_for_disable_poling_conf_0": 0, + "ram_stop_bit_for_disable_poling_conf_0": 1, + "ram_data_for_disable_poling_conf_1": 0, + "ram_offset_bits_for_disable_poling_conf_1": 0, + "ram_stop_bit_for_disable_poling_conf_1": 1 + }, + "flash_wel_command": { + "flash_wel_opcode": 6, + "suppl_flash_wel_opcode": 0 + }, + "ram_wel_command": { + "ram_wel_opcode": 6, + "suppl_ram_wel_opcode": 0 + } + }, + "event": { + "host_nvic_irq": 0, + "core_10_mux_sel": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/is25wj128f/flash_disc_param_ext_mem.json b/boards/ti/lp_em_cc35x1/config/flash/is25wj128f/flash_disc_param_ext_mem.json new file mode 100644 index 000000000000..14d05d9aba5a --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/is25wj128f/flash_disc_param_ext_mem.json @@ -0,0 +1,99 @@ +{ + "vendor_primary_sbl": true, + "ti_wsoc_primary_container": true, + "ti_wsoc_bl2_primary_container": true, + "nvs_enable": true, + "vendor_alternate_image": true, + "vendor_sbl_alternate_image": true, + "ti_bl_alternate_image": true, + "ti_wsoc_alternate_image": true, + "ti_wsoc_bl2_alternate_image": true, + "region_0": { + "mem_region_0_start_phy_address": 2867200, + "mem_region_0_end_phy_address": 9822207, + "region0_boot": false, + "region0_main_code": true, + "region0_nvs": false, + "region0_wsoc_code": false, + "region0_alternate_code": false + }, + "region_1": { + "mem_region_1_start_phy_address": 0, + "mem_region_1_end_phy_address": 2867199, + "region1_boot": true, + "region1_main_code": false, + "region1_nvs": true, + "region1_wsoc_code": true, + "region1_alternate_code": false + }, + "region_2": { + "mem_region_2_start_phy_address": 9822208, + "mem_region_2_end_phy_address": 16777215, + "region2_boot": false, + "region2_main_code": false, + "region2_nvs": false, + "region2_wsoc_code": false, + "region2_alternate_code": true + }, + "region_3": { + "mem_region_3_start_phy_address": 0, + "mem_region_3_end_phy_address": 0, + "region3_boot": false, + "region3_main_code": false, + "region3_nvs": false, + "region3_wsoc_code": false, + "region3_alternate_code": false + }, + "boot_region_conf": { + "boot_region_size": 0, + "boot_region_flash_disco_param_start_address": 0, + "boot_region_primary_ti_bl_start_phy_address": 12284, + "boot_region_primary_ti_bl_magic": 0, + "boot_region_primary_ti_bl_major": 0, + "boot_region_primary_ti_bl_minor": 0, + "boot_region_sec_ti_bl_start_phy_address": 430076, + "boot_region_sec_ti_bl_magic": 0, + "boot_region_sec_ti_bl_major": 0, + "boot_region_sec_ti_bl_minor": 0 + }, + "main_code_region_conf": { + "main_code_region_vendor_image_start_phy_address": 2871292, + "main_code_region_vendor_image_magic": 0, + "main_code_region_vendor_image_major": 0, + "main_code_region_vendor_image_minor": 0, + "main_code_region_sbl_start_phy_address": 0, + "main_code_region_sbl_magic": 0, + "main_code_region_sbl_major": 0, + "main_code_region_sbl_minor": 0 + }, + "alt_code_region_conf": { + "alt_code_region_vendor_image_start_phy_address": 9826300, + "alt_code_region_vendor_image_magic": 0, + "alt_code_region_vendor_image_major": 0, + "alt_code_region_vendor_image_minor": 0, + "alt_code_region_sbl_start_phy_address": 0, + "alt_code_region_sbl_magic": 0, + "alt_code_region_sbl_major": 0, + "alt_code_region_sbl_minor": 0 + }, + "nvs_code_region_conf": { + "nvs_start_phy_address": 1777664, + "nvs_region_size": 1089536, + "nvs_region_primary_wsoc_start_phy_address": 847868, + "nvs_region_primary_wsoc_magic": 0, + "nvs_region_primary_wsoc_major": 0, + "nvs_region_primary_wsoc_minor": 0, + "nvs_region_sec_wsoc_start_phy_address": 1314812, + "nvs_region_sec_wsoc_magic": 0, + "nvs_region_sec_wsoc_major": 0, + "nvs_region_sec_wsoc_minor": 0, + "nvs_region_primary_wsoc_bl2_start_phy_address": 0, + "nvs_region_primary_wsoc_bl2_magic": 0, + "nvs_region_primary_wsoc_bl2_major": 0, + "nvs_region_primary_wsoc_bl2_minor": 0, + "nvs_region_sec_wsoc_bl2_start_phy_address": 0, + "nvs_region_sec_wsoc_bl2_magic": 0, + "nvs_region_sec_wsoc_bl2_major": 0, + "nvs_region_sec_wsoc_bl2_minor": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/is25wj128f/flash_disc_param_otfde.json b/boards/ti/lp_em_cc35x1/config/flash/is25wj128f/flash_disc_param_otfde.json new file mode 100644 index 000000000000..a39371a15d7d --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/is25wj128f/flash_disc_param_otfde.json @@ -0,0 +1,286 @@ +{ + "otfde_header": { + "name": "OTFDEWFF3", + "flash_only": true, + "ip_protection": false, + "regions_lock": false, + "regions_number": 4, + "flash_enabled": true + }, + "bl_conf": { + "host_boot_done_lock": true, + "host_peripherals_lock": true, + "icache_conf_lock": true, + "m33_mem_part_lock": true, + "memss_firewall_lock": true, + "dma_channel_owner_lock": true, + "otfde_region_lock": true, + "core_events_lock": true + }, + "otfde_general": { + "parameters": { + "mem_otfde_initial_delay": 10, + "otfde_global_watchdog_timer": 5 + }, + "events": { + "reset_evt_mask": false, + "reset_evt_suspend": false, + "sft_reset_evt_mask": false, + "sft_reset_evt_suspend": false, + "bypass_mode_evt_mask": false, + "bypass_mode_evt_suspend": false, + "debug_mode_evt_mask": false, + "debug_mode_evt_suspend": false, + "general_evt_mask": false, + "general_evt_suspend": false, + "xspi_data_path_evt_mask": false, + "xspi_data_path_evt_suspend": false, + "xspi_cnfg_path_evt_mask": false, + "xspi_cnfg_path_evt_suspend": false, + "xspi_service_interrupt_evt_mask": false, + "xspi_service_interrupt_evt_suspend": false, + "trans_device_disabled_evt_mask": false, + "trans_device_disabled_evt_suspend": false, + "trans_region_disabled_evt_mask": false, + "trans_region_disabled_evt_suspend": false, + "trans_region_params_conf_evt_mask": false, + "trans_region_params_conf_evt_suspend": false, + "trans_multiple_regions_mapped_evt_mask": false, + "trans_multiple_regions_mapped_evt_suspend": false, + "trans_address_not_32_bit_evt_mask": false, + "trans_address_not_32_bit_evt_suspend": false, + "trans_size_not_32_bit_evt_mask": false, + "trans_size_not_32_bit_evt_suspend": false, + "trans_burst_not_32_bit_evt_mask": false, + "trans_burst_not_32_bit_evt_suspend": false, + "region_read_write_def_evt_mask": false, + "region_read_write_def_evt_suspend": false, + "suspend_while_disabled_evt_mask": false, + "suspend_while_disabled_evt_suspend": false + } + }, + "regions_settings": { + "region_parameters_lock": { + "REGION_0_PARAMS_0": true, + "REGION_0_PARAMS_1": true, + "REGION_0_PARAMS_2": true, + "REGION_1_PARAMS_0": false, + "REGION_1_PARAMS_1": false, + "REGION_1_PARAMS_2": false, + "REGION_2_PARAMS_0": true, + "REGION_2_PARAMS_1": true, + "REGION_2_PARAMS_2": true, + "REGION_3_PARAMS_0": false, + "REGION_3_PARAMS_1": false, + "REGION_3_PARAMS_2": false + }, + "region_0_protection": { + "mem_region_0_enabled": true, + "mem_region_0_device_id": 0, + "mem_region_0_spi_write_enable": true, + "mem_region_0_spi_read_enable": true, + "mem_region_0_physical_offset": 700, + "mem_region_0_security_id_msb": 0, + "mem_region_0_start_address": 81920, + "mem_region_0_end_address": 83617, + "mem_region_0_security_id_lsb": 0, + "mem_otfde_region_0_write_lock_en": false, + "mem_otfde_region_0_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_1_protection": { + "mem_region_1_enabled": true, + "mem_region_1_device_id": 0, + "mem_region_1_spi_write_enable": true, + "mem_region_1_spi_read_enable": true, + "mem_region_1_physical_offset": 0, + "mem_region_1_security_id_msb": 0, + "mem_region_1_start_address": 655360, + "mem_region_1_end_address": 656059, + "mem_region_1_security_id_lsb": 0, + "mem_otfde_region_1_write_lock_en": false, + "mem_otfde_region_1_enc_dec_bypass": "Bypass" + }, + "region_2_protection": { + "mem_region_2_enabled": true, + "mem_region_2_device_id": 0, + "mem_region_2_spi_write_enable": true, + "mem_region_2_spi_read_enable": true, + "mem_region_2_physical_offset": 2398, + "mem_region_2_security_id_msb": 0, + "mem_region_2_start_address": 671744, + "mem_region_2_end_address": 673441, + "mem_region_2_security_id_lsb": 0, + "mem_otfde_region_2_write_lock_en": false, + "mem_otfde_region_2_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_3_protection": { + "mem_region_3_enabled": false, + "mem_region_3_device_id": 1, + "mem_region_3_spi_write_enable": true, + "mem_region_3_spi_read_enable": true, + "mem_region_3_physical_offset": 0, + "mem_region_3_security_id_msb": 0, + "mem_region_3_start_address": 1, + "mem_region_3_end_address": 0, + "mem_region_3_security_id_lsb": 0, + "mem_otfde_region_3_write_lock_en": false, + "mem_otfde_region_3_enc_dec_bypass": "Bypass" + } + }, + "devices": { + "header": { + "flash_device_switch_conf": 1, + "ram_device_switch_conf": 1 + }, + "flash_switch": { + "flash_grant_sel": 0, + "flash_data_for_conf_0": 2181562505, + "flash_offset_bits_for_conf_0": 0, + "flash_stop_bit_for_conf_0": 0, + "flash_data_for_conf_1": 100803083, + "flash_offset_bits_for_conf_1": 1, + "flash_stop_bit_for_conf_1": 0, + "flash_data_for_conf_2": 139266, + "flash_offset_bits_for_conf_2": 2, + "flash_stop_bit_for_conf_2": 0, + "flash_data_for_conf_3": 1, + "flash_offset_bits_for_conf_3": 4, + "flash_stop_bit_for_conf_3": 0, + "flash_data_for_conf_4": 1076887634, + "flash_offset_bits_for_conf_4": 45, + "flash_stop_bit_for_conf_4": 0, + "flash_data_for_conf_5": 3224371282, + "flash_offset_bits_for_conf_5": 45, + "flash_stop_bit_for_conf_5": 0, + "flash_data_for_conf_6": 262149, + "flash_offset_bits_for_conf_6": 14, + "flash_stop_bit_for_conf_6": 0, + "flash_data_for_conf_7": 0, + "flash_offset_bits_for_conf_7": 44, + "flash_stop_bit_for_conf_7": 1, + "flash_data_for_conf_8": 0, + "flash_offset_bits_for_conf_8": 0, + "flash_stop_bit_for_conf_8": 1, + "flash_data_for_conf_9": 0, + "flash_offset_bits_for_conf_9": 0, + "flash_stop_bit_for_conf_9": 1, + "flash_data_for_conf_10": 0, + "flash_offset_bits_for_conf_10": 0, + "flash_stop_bit_for_conf_10": 1, + "flash_data_for_conf_11": 0, + "flash_offset_bits_for_conf_11": 0, + "flash_stop_bit_for_conf_11": 1, + "flash_data_for_conf_12": 0, + "flash_offset_bits_for_conf_12": 0, + "flash_stop_bit_for_conf_12": 1, + "flash_data_for_conf_13": 0, + "flash_offset_bits_for_conf_13": 0, + "flash_stop_bit_for_conf_13": 1, + "flash_data_for_conf_14": 0, + "flash_offset_bits_for_conf_14": 0, + "flash_stop_bit_for_conf_14": 1, + "flash_data_for_conf_15": 0, + "flash_offset_bits_for_conf_15": 0, + "flash_stop_bit_for_conf_15": 1, + "flash_data_for_conf_16": 0, + "flash_offset_bits_for_conf_16": 0, + "flash_stop_bit_for_conf_16": 1, + "flash_data_for_conf_17": 0, + "flash_offset_bits_for_conf_17": 0, + "flash_stop_bit_for_conf_17": 1, + "flash_data_for_conf_18": 0, + "flash_offset_bits_for_conf_18": 0, + "flash_stop_bit_for_conf_18": 1, + "flash_data_for_conf_19": 0, + "flash_offset_bits_for_conf_19": 0, + "flash_stop_bit_for_conf_19": 1, + "flash_data_for_conf_20": 0, + "flash_offset_bits_for_conf_20": 0, + "flash_stop_bit_for_conf_20": 1, + "flash_data_for_conf_21": 0, + "flash_offset_bits_for_conf_21": 0, + "flash_stop_bit_for_conf_21": 1, + "flash_data_for_conf_22": 0, + "flash_offset_bits_for_conf_22": 0, + "flash_stop_bit_for_conf_22": 1, + "flash_data_for_conf_23": 0, + "flash_offset_bits_for_conf_23": 0, + "flash_stop_bit_for_conf_23": 1 + }, + "ram_switch": { + "ram_grant_sel": 0, + "ram_data_for_conf_0": 2181562505, + "ram_offset_bits_for_conf_0": 0, + "ram_stop_bit_for_conf_0": 0, + "ram_data_for_conf_1": 67248651, + "ram_offset_bits_for_conf_1": 1, + "ram_stop_bit_for_conf_1": 0, + "ram_data_for_conf_2": 139266, + "ram_offset_bits_for_conf_2": 2, + "ram_stop_bit_for_conf_2": 0, + "ram_data_for_conf_3": 1, + "ram_offset_bits_for_conf_3": 4, + "ram_stop_bit_for_conf_3": 0, + "ram_data_for_conf_4": 1076887634, + "ram_offset_bits_for_conf_4": 45, + "ram_stop_bit_for_conf_4": 0, + "ram_data_for_conf_5": 3224371282, + "ram_offset_bits_for_conf_5": 45, + "ram_stop_bit_for_conf_5": 0, + "ram_data_for_conf_6": 262149, + "ram_offset_bits_for_conf_6": 14, + "ram_stop_bit_for_conf_6": 0, + "ram_data_for_conf_7": 0, + "ram_offset_bits_for_conf_7": 44, + "ram_stop_bit_for_conf_7": 1, + "ram_data_for_conf_8": 0, + "ram_offset_bits_for_conf_8": 0, + "ram_stop_bit_for_conf_8": 1, + "ram_data_for_conf_9": 0, + "ram_offset_bits_for_conf_9": 0, + "ram_stop_bit_for_conf_9": 1, + "ram_data_for_conf_10": 0, + "ram_offset_bits_for_conf_10": 0, + "ram_stop_bit_for_conf_10": 1, + "ram_data_for_conf_11": 0, + "ram_offset_bits_for_conf_11": 0, + "ram_stop_bit_for_conf_11": 1, + "ram_data_for_conf_12": 0, + "ram_offset_bits_for_conf_12": 0, + "ram_stop_bit_for_conf_12": 1, + "ram_data_for_conf_13": 0, + "ram_offset_bits_for_conf_13": 0, + "ram_stop_bit_for_conf_13": 1, + "ram_data_for_conf_14": 0, + "ram_offset_bits_for_conf_14": 0, + "ram_stop_bit_for_conf_14": 1, + "ram_data_for_conf_15": 0, + "ram_offset_bits_for_conf_15": 0, + "ram_stop_bit_for_conf_15": 1, + "ram_data_for_conf_16": 0, + "ram_offset_bits_for_conf_16": 0, + "ram_stop_bit_for_conf_16": 1, + "ram_data_for_conf_17": 0, + "ram_offset_bits_for_conf_17": 0, + "ram_stop_bit_for_conf_17": 1, + "ram_data_for_conf_18": 0, + "ram_offset_bits_for_conf_18": 0, + "ram_stop_bit_for_conf_18": 1, + "ram_data_for_conf_19": 0, + "ram_offset_bits_for_conf_19": 0, + "ram_stop_bit_for_conf_19": 1, + "ram_data_for_conf_20": 0, + "ram_offset_bits_for_conf_20": 0, + "ram_stop_bit_for_conf_20": 1, + "ram_data_for_conf_21": 0, + "ram_offset_bits_for_conf_21": 0, + "ram_stop_bit_for_conf_21": 1, + "ram_data_for_conf_22": 0, + "ram_offset_bits_for_conf_22": 0, + "ram_stop_bit_for_conf_22": 1, + "ram_data_for_conf_23": 0, + "ram_offset_bits_for_conf_23": 0, + "ram_stop_bit_for_conf_23": 1 + } + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/is25wj128f/flash_disc_param_xspi.json b/boards/ti/lp_em_cc35x1/config/flash/is25wj128f/flash_disc_param_xspi.json new file mode 100644 index 000000000000..d5e12d823532 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/is25wj128f/flash_disc_param_xspi.json @@ -0,0 +1,485 @@ +{ + "xspi_header": { + "name": "xSPIWFF3", + "device": "CC3500", + "use_hardware": "IS25WJ128F", + "use_case": "Quadro", + "dqs_support": 0, + "flash_only": 1, + "flash_separate_reset": 0, + "ram_separate_reset": true, + "clock_frequency": 80, + "qospi_clock_divider": 1, + "flash_device_character_conf": 0, + "ram_device_character_conf": 0, + "header_advanced": 0, + "phy_mode_enable": 1, + "pipeline_mode_enable": 1, + "loopback_support": "No", + "qspi_ref_clock": 80, + "spi_clock_freq": 20, + "spi_clock_divider": 1, + "flash_device_size": 16, + "flash_bytes_per_block": 16, + "flash_bytes_per_page": 256, + "flash_number_of_address_bytes": 3, + "flash_dual_opcode": 0, + "flash_jedec_manufacturer_id": 0, + "flash_jedec_device_id": 0, + "flash_name": "IS25WJ128F", + "flash_page_size": 256, + "flash_sector_size": 4096, + "flash_cs_polarity": "ACTIVE_LOW", + "flash_sw_reset_type": "x1xxxx", + "ram_device_size": 8, + "ram_bytes_per_block": 16, + "ram_bytes_per_page": 256, + "ram_number_of_address_bytes": 3, + "ram_dual_opcode": 0, + "ram_jedec_manufacturer_id": 0, + "ram_jedec_device_id": 0, + "ram_name": "NO_PSRAM", + "ram_page_size": 256, + "ram_sector_size": 4096, + "ram_cs_polarity": "ACTIVE_LOW", + "ram_sw_reset_type": "x1xxxx", + "flash_write_operation_modes": "4S-4S-4S", + "flash_read_operation_modes": "4S-4S-4S", + "ram_write_operation_modes": "4S-4S-4S", + "ram_read_operation_modes": "4S-4S-4S", + "crc_enable": 0, + "enable_dtr": 0, + "enable_ahb_decoder": 0, + "enter_xip_mod_immediately": 0, + "enter_xip_mod_next_read": 0, + "ahb_address_remapping": 0, + "enable_dma": 0, + "select_decode": 0, + "legacy_ip_mode": 0, + "direct_access": 1 + }, + "xspi_pinmux": { + "xspi_clk_input": 44, + "xspi_clk_input_use_hw": 0, + "xspi_clk_input_mode": "Input", + "xspi_clk_input_pull": "None", + "xspi_clk_input_interrupt_trigger": "Low", + "xspi_clk_input_dont_conf": 0, + "xspi_clk_input_output_strength": "High", + "xspi_clk_input_initial_output_state": "High", + "xspi_clk": 24, + "xspi_clk_use_hw": "None", + "xspi_clk_mode": "Output", + "xspi_clk_pull": "None", + "xspi_clk_output_strength": "High", + "xspi_clk_initial_output_state": "High", + "xspi_clk_interrupt_trigger": "None", + "xspi_clk_dont_conf": 0, + "xspi_flash_cs": 20, + "xspi_flash_cs_use_hw": "None", + "xspi_flash_cs_mode": "Output", + "xspi_flash_cs_pull": "None", + "xspi_flash_cs_output_strength": "High", + "xspi_flash_cs_initial_output_state": "High", + "xspi_flash_cs_interrupt_trigger": "None", + "xspi_flash_cs_dont_conf": 0, + "xspi_data_0": 25, + "xspi_data_0_use_hw": "None", + "xspi_data_0_mode": "Input", + "xspi_data_0_pull": "None", + "xspi_data_0_output_strength": "High", + "xspi_data_0_initial_output_state": "High", + "xspi_data_0_interrupt_trigger": "Low", + "xspi_data_0_dont_conf": 0, + "xspi_data_1": 21, + "xspi_data_1_use_hw": "None", + "xspi_data_1_mode": "Input", + "xspi_data_1_pull": "None", + "xspi_data_1_output_strength": "High", + "xspi_data_1_initial_output_state": "High", + "xspi_data_1_interrupt_trigger": "Low", + "xspi_data_1_dont_conf": 0, + "xspi_data_2": 22, + "xspi_data_2_use_hw": "None", + "xspi_data_2_mode": "Input", + "xspi_data_2_pull": "None", + "xspi_data_2_output_strength": "High", + "xspi_data_2_initial_output_state": "High", + "xspi_data_2_interrupt_trigger": "Low", + "xspi_data_2_dont_conf": 0, + "xspi_data_3": 23, + "xspi_data_3_use_hw": "None", + "xspi_data_3_mode": "Input", + "xspi_data_3_pull": "None", + "xspi_data_3_output_strength": "High", + "xspi_data_3_initial_output_state": "High", + "xspi_data_3_interrupt_trigger": "Low", + "xspi_data_3_dont_conf": 0, + "xspi_data_4": 26, + "xspi_data_4_use_hw": "None", + "xspi_data_4_mode": "Input", + "xspi_data_4_pull": "None", + "xspi_data_4_output_strength": "High", + "xspi_data_4_initial_output_state": "High", + "xspi_data_4_interrupt_trigger": "None", + "xspi_data_4_dont_conf": 0, + "xspi_data_5": 27, + "xspi_data_5_use_hw": "None", + "xspi_data_5_mode": "Input", + "xspi_data_5_pull": "None", + "xspi_data_5_output_strength": "High", + "xspi_data_5_initial_output_state": "High", + "xspi_data_5_interrupt_trigger": "None", + "xspi_data_5_dont_conf": 0, + "xspi_data_6": 28, + "xspi_data_6_use_hw": "None", + "xspi_data_6_mode": "Input", + "xspi_data_6_pull": "None", + "xspi_data_6_output_strength": "High", + "xspi_data_6_initial_output_state": "High", + "xspi_data_6_interrupt_trigger": "None", + "xspi_data_6_dont_conf": 0, + "xspi_data_7": 29, + "xspi_data_7_use_hw": "None", + "xspi_data_7_mode": "Input", + "xspi_data_7_pull": "None", + "xspi_data_7_output_strength": "High", + "xspi_data_7_initial_output_state": "High", + "xspi_data_7_interrupt_trigger": "None", + "xspi_data_7_dont_conf": 0, + "xspi_reset_flash": 36, + "xspi_reset_flash_use_hw": "None", + "xspi_reset_flash_mode": "Output", + "xspi_reset_flash_pull": "None", + "xspi_reset_flash_output_strength": "High", + "xspi_reset_flash_initial_output_state": "High", + "xspi_reset_flash_interrupt_trigger": "None", + "xspi_reset_flash_dont_conf": 0, + "xspi_cs_ram": 3, + "xspi_cs_ram_use_hw": "None", + "xspi_cs_ram_mode": "Output", + "xspi_cs_ram_pull": "None", + "xspi_cs_ram_output_strength": "High", + "xspi_cs_ram_initial_output_state": "High", + "xspi_cs_ram_interrupt_trigger": "None", + "xspi_cs_ram_dont_conf": 0, + "xspi_dqs": 30, + "xspi_dqs_use_hw": "None", + "xspi_dqs_mode": "Input", + "xspi_dqs_pull": "None", + "xspi_dqs_output_strength": "High", + "xspi_dqs_initial_output_state": "High", + "xspi_dqs_interrupt_trigger": "None", + "xspi_dqs_dont_conf": 0, + "xspi_reset_ram": 2, + "xspi_reset_ram_use_hw": "None", + "xspi_reset_ram_mode": "Input", + "xspi_reset_ram_pull": "None", + "xspi_reset_ram_output_strength": "High", + "xspi_reset_ram_initial_output_state": "High", + "xspi_reset_ram_interrupt_trigger": "None", + "xspi_reset_ram_dont_conf": 0 + }, + "xspi_operations": { + "xspi_operations_clocks": { + "clock_phase": 0, + "clock_polarity": 0, + "spi_mode": "2'b00" + }, + "xspi_operations_chip_select": { + "csda": 2, + "csdads": 0, + "cseot": 4, + "cssot": 1 + }, + "xspi_operations_reset": { + "flash_jedec_reset": 0, + "ram_jedec_reset": 0, + "flash_treset": 20, + "ram_treset": 20 + }, + "xspi_phy_operations": { + "flash_rx_dll_bypass_bit": 0, + "flash_dll_tx_delay": 22, + "flash_dll_rx_delay": 34, + "ram_rx_dll_bypass_bit": 0, + "ram_dll_tx_delay": 22, + "ram_dll_rx_delay": 34 + }, + "xspi_read_operations": { + "flash_dummy_rd_cycles": 6, + "flash_read_opcode": 11, + "suppl_flash_read_opcode": 0, + "ram_dummy_rd_cycles": 4, + "ram_read_opcode": 11, + "suppl_ram_read_opcode": 0, + "flash_non_cont_read_enable": 0, + "flash_max_read_jobs": 256, + "ram_non_cont_read_enable": 0, + "ram_max_read_jobs": 256, + "rww_en": 0, + "device_size": 8, + "number_of_banks": 1, + "bank_size": 8, + "mode_bit_enable": 0 + }, + "xspi_write_operations": { + "flash_address_and_data": { + "flash_dummy_wr_cycles": 0 + }, + "flash_command": { + "flash_write_opcode": 2, + "suppl_flash_write_opcode": 0 + }, + "ram_address_and_data": { + "ram_dummy_wr_cycles": 0 + }, + "ram_command": { + "ram_write_opcode": 2, + "suppl_ram_write_opcode": 0 + }, + "write_to_buffer": { + "flash_write_to_buffer_support": 0, + "ram_write_to_buffer_support": 0 + }, + "non_continuous_write": { + "flash_non_cont_write_enable": 0, + "flash_max_write_jobs": 64, + "ram_non_cont_write_enable": 0, + "ram_max_write_jobs": 0 + }, + "flash_program_operation": { + "flash_min_program_size": "256 B", + "flash_program_opcode": 2, + "suppl_flash_program_opcode": 0, + "flash_maximum_program_time_limit": 1600 + }, + "flash_erase_operation": { + "flash_min_erase_size": "4 kB", + "flash_erase_opcode": 32, + "suppl_flash_erase_opcode": 0, + "flash_maximum_erase_time_limit": 4095 + }, + "flash_erase_conf": { + "flash_block_erase_opcode": 0, + "suppl_block_flash_erase_opcode": 0, + "flash_sector_erase_opcode": 0, + "suppl_sector_flash_erase_opcode": 0, + "flash_chip_erase_opcode": 0, + "suppl_chip_flash_erase_opcode": 0 + }, + "ram_program_operation": { + "ram_min_program_size": "256 B", + "ram_program_opcode": 2, + "suppl_ram_program_opcode": 0, + "ram_maximum_program_time_limit": 1600 + }, + "ram_erase_conf": { + "ram_block_erase_opcode": 0, + "suppl_block_ram_erase_opcode": 0, + "ram_sector_erase_opcode": 0, + "suppl_sector_ram_erase_opcode": 0, + "ram_chip_erase_opcode": 0, + "suppl_chip_ram_erase_opcode": 0 + }, + "flash_buffer_support": { + "flash_pre_write_sequence": 0, + "flash_post_write_sequence": 0, + "flash_write_protection_timer_en": 0, + "flash_write_buffer_timer_mode": 16, + "flash_write_buffer_timer_range": 0, + "flash_service_interrupt_criteria": 0 + }, + "ram_buffer_support": { + "ram_pre_write_sequence": 0, + "ram_post_write_sequence": 0, + "ram_write_protection_timer_en": 0, + "ram_write_buffer_timer_mode": 16, + "ram_write_buffer_timer_range": 0, + "ram_service_interrupt_criteria": 0 + }, + "flash_pre_write_conf": { + "flash_pre_write_job_done_grant_sel": 0, + "data_for_flash_pre_write_conf_0": 0, + "offset_bits_for_flash_pre_write_conf_0": 0, + "stop_bit_for_flash_pre_write_conf_0": 1, + "data_for_flash_pre_write_conf_1": 0, + "offset_bits_for_flash_pre_write_conf_1": 0 + }, + "flash_post_write_conf": { + "flash_post_write_job_done_grant_sel": 0, + "data_for_flash_post_write_conf_0": 0, + "offset_bits_for_flash_post_write_conf_0": 0, + "stop_bit_for_flash_post_write_conf_0": 1, + "data_for_flash_post_write_conf_1": 0, + "offset_bits_for_flash_post_write_conf_1": 0 + }, + "ram_pre_write_conf": { + "ram_pre_write_job_done_grant_sel": 0, + "data_for_ram_pre_write_conf_0": 0, + "offset_bits_for_ram_pre_write_conf_0": 0, + "stop_bit_for_ram_pre_write_conf_0": 1, + "data_for_ram_pre_write_conf_1": 0, + "offset_bits_for_ram_pre_write_conf_1": 0 + }, + "ram_post_write_conf": { + "ram_post_write_job_done_grant_sel": 0, + "data_for_ram_post_write_conf_0": 0, + "offset_bits_for_ram_post_write_conf_0": 0, + "stop_bit_for_ram_post_write_conf_0": 1, + "data_for_ram_post_write_conf_1": 0, + "offset_bits_for_ram_post_write_conf_1": 0 + } + }, + "xspi_capture_operations": { + "read_data_capture": { + "flash_delay_transmitted_data": 0, + "flash_loopback_clock": 0, + "flash_bypass_adapted_loopback": 1, + "flash_sample_edge_sel": 0, + "ram_delay_transmitted_data": 0, + "ram_loopback_clock": 0, + "ram_bypass_adapted_loopback": 1, + "ram_sample_edge_sel": 0 + }, + "delays": { + "flash_full_half_cycle_delay": 0, + "flash_dll_bypass_mode": 1, + "flash_phase_detect_sel": 0, + "flash_dll_lock_num": 0, + "flash_dll_start_point": 0, + "flash_loopback_clock": 0, + "ram_full_half_cycle_delay": 0, + "ram_dll_bypass_mode": 1, + "ram_phase_detect_sel": 0, + "ram_dll_lock_num": 0, + "ram_dll_start_point": 0, + "ram_loopback_clock": 0 + }, + "operation_modes": { + "flash_sfdp_support": 0, + "ram_sfdp_support": 0, + "flash_pm_support": 0, + "ram_pm_support": 0, + "flash_sfdp_opcode": 0, + "suppl_flash_sfdp_opcode": 0, + "ram_sfdp_opcode": 0, + "suppl_ram_sfdp_opcode": 0, + "flash_enter_dpd_opcode": 185, + "suppl_flash_enter_dpd_opcode": 0, + "flash_exit_dpd_opcode": 171, + "suppl_flash_exit_dpd_opcode": 0, + "ram_enter_dpd_opcode": 185, + "suppl_ram_enter_dpd_opcode": 0, + "ram_exit_dpd_opcode": 171, + "suppl_ram_exit_dpd_opcode": 0, + "flash_quad_enable_opcode": 56, + "suppl_flash_quad_enable_opcode": 0, + "flash_quad_disable_opcode": 255, + "suppl_flash_quad_disable_opcode": 0, + "flash_octal_enable_opcode": 0, + "suppl_flash_octal_enable_opcode": 0, + "flash_octal_disable_opcode": 0, + "suppl_flash_octal_disable_opcode": 0, + "ram_quad_enable_opcode": 56, + "suppl_ram_quad_enable_opcode": 0, + "ram_quad_disable_opcode": 255, + "suppl_ram_quad_disable_opcode": 0, + "ram_octal_enable_opcode": 0, + "suppl_ram_octal_enable_opcode": 0, + "ram_octal_disable_opcode": 0, + "suppl_ram_octal_disable_opcode": 0 + } + } + }, + "external_memory_reporting": { + "header": { + "flash_auto_polling_enable": 1, + "flash_wel_enable": 1, + "flash_write_protect_enable": 0, + "flash_alternate_polling_conf_enable": 0, + "ram_auto_polling_enable": 1, + "ram_wel_enable": 1, + "ram_write_protect_enable": 0, + "ram_alternate_polling_conf_enable": 0 + }, + "flash_auto_polling": { + "flash_polling_repetition_delay": 0, + "flash_polling_count": 4, + "flash_enable_polling_expiration": 0, + "flash_polling_polarity": 0, + "flash_polling_address_phase_enable": 0, + "flash_polling_bit_index": 0, + "flash_numbers_poll_cycles": 65535, + "flash_dummy_autopoll_cycles": 0 + }, + "ram_auto_polling": { + "ram_polling_repetition_delay": 0, + "ram_polling_count": 4, + "ram_enable_polling_expiration": 0, + "ram_polling_polarity": 0, + "ram_polling_address_phase_enable": 0, + "ram_polling_bit_index": 0, + "ram_numbers_poll_cycles": 65535, + "ram_dummy_autopoll_cycles": 0 + }, + "flash_polling_command": { + "flash_polling_opcode": 5, + "suppl_flash_polling_opcode": 0 + }, + "ram_polling_command": { + "ram_polling_opcode": 5, + "suppl_ram_polling_opcode": 0 + }, + "flash_alternate_polling": { + "flash_polling_resp_count": 1023, + "flash_polling_iterations": 1, + "flash_polling_enabled": 0, + "flash_polling_disabled": 0, + "flash_grant_sel": 0, + "flash_data_for_enable_poling_conf_0": 0, + "flash_offset_bits_for_enable_poling_conf_0": 0, + "flash_stop_bit_for_enable_poling_conf_0": 1, + "flash_data_for_enable_poling_conf_1": 0, + "flash_offset_bits_for_enable_poling_conf_1": 0, + "flash_stop_bit_for_enable_poling_conf_1": 1, + "flash_data_for_disable_poling_conf_0": 0, + "flash_offset_bits_for_disable_poling_conf_0": 0, + "flash_stop_bit_for_disable_poling_conf_0": 1, + "flash_data_for_disable_poling_conf_1": 0, + "flash_offset_bits_for_disable_poling_conf_1": 0, + "flash_stop_bit_for_disable_poling_conf_1": 1 + }, + "ram_alternate_polling": { + "ram_polling_resp_count": 1023, + "ram_polling_iterations": 1, + "ram_polling_enabled": 0, + "ram_polling_disabled": 0, + "ram_grant_sel": 0, + "ram_data_for_enable_poling_conf_0": 0, + "ram_offset_bits_for_enable_poling_conf_0": 0, + "ram_stop_bit_for_enable_poling_conf_0": 1, + "ram_data_for_enable_poling_conf_1": 0, + "ram_offset_bits_for_enable_poling_conf_1": 0, + "ram_stop_bit_for_enable_poling_conf_1": 1, + "ram_data_for_disable_poling_conf_0": 0, + "ram_offset_bits_for_disable_poling_conf_0": 0, + "ram_stop_bit_for_disable_poling_conf_0": 1, + "ram_data_for_disable_poling_conf_1": 0, + "ram_offset_bits_for_disable_poling_conf_1": 0, + "ram_stop_bit_for_disable_poling_conf_1": 1 + }, + "flash_wel_command": { + "flash_wel_opcode": 6, + "suppl_flash_wel_opcode": 0 + }, + "ram_wel_command": { + "ram_wel_opcode": 6, + "suppl_ram_wel_opcode": 0 + } + }, + "event": { + "host_nvic_irq": 0, + "core_10_mux_sel": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/mx25u12843g/flash_disc_param_ext_mem.json b/boards/ti/lp_em_cc35x1/config/flash/mx25u12843g/flash_disc_param_ext_mem.json new file mode 100644 index 000000000000..14d05d9aba5a --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/mx25u12843g/flash_disc_param_ext_mem.json @@ -0,0 +1,99 @@ +{ + "vendor_primary_sbl": true, + "ti_wsoc_primary_container": true, + "ti_wsoc_bl2_primary_container": true, + "nvs_enable": true, + "vendor_alternate_image": true, + "vendor_sbl_alternate_image": true, + "ti_bl_alternate_image": true, + "ti_wsoc_alternate_image": true, + "ti_wsoc_bl2_alternate_image": true, + "region_0": { + "mem_region_0_start_phy_address": 2867200, + "mem_region_0_end_phy_address": 9822207, + "region0_boot": false, + "region0_main_code": true, + "region0_nvs": false, + "region0_wsoc_code": false, + "region0_alternate_code": false + }, + "region_1": { + "mem_region_1_start_phy_address": 0, + "mem_region_1_end_phy_address": 2867199, + "region1_boot": true, + "region1_main_code": false, + "region1_nvs": true, + "region1_wsoc_code": true, + "region1_alternate_code": false + }, + "region_2": { + "mem_region_2_start_phy_address": 9822208, + "mem_region_2_end_phy_address": 16777215, + "region2_boot": false, + "region2_main_code": false, + "region2_nvs": false, + "region2_wsoc_code": false, + "region2_alternate_code": true + }, + "region_3": { + "mem_region_3_start_phy_address": 0, + "mem_region_3_end_phy_address": 0, + "region3_boot": false, + "region3_main_code": false, + "region3_nvs": false, + "region3_wsoc_code": false, + "region3_alternate_code": false + }, + "boot_region_conf": { + "boot_region_size": 0, + "boot_region_flash_disco_param_start_address": 0, + "boot_region_primary_ti_bl_start_phy_address": 12284, + "boot_region_primary_ti_bl_magic": 0, + "boot_region_primary_ti_bl_major": 0, + "boot_region_primary_ti_bl_minor": 0, + "boot_region_sec_ti_bl_start_phy_address": 430076, + "boot_region_sec_ti_bl_magic": 0, + "boot_region_sec_ti_bl_major": 0, + "boot_region_sec_ti_bl_minor": 0 + }, + "main_code_region_conf": { + "main_code_region_vendor_image_start_phy_address": 2871292, + "main_code_region_vendor_image_magic": 0, + "main_code_region_vendor_image_major": 0, + "main_code_region_vendor_image_minor": 0, + "main_code_region_sbl_start_phy_address": 0, + "main_code_region_sbl_magic": 0, + "main_code_region_sbl_major": 0, + "main_code_region_sbl_minor": 0 + }, + "alt_code_region_conf": { + "alt_code_region_vendor_image_start_phy_address": 9826300, + "alt_code_region_vendor_image_magic": 0, + "alt_code_region_vendor_image_major": 0, + "alt_code_region_vendor_image_minor": 0, + "alt_code_region_sbl_start_phy_address": 0, + "alt_code_region_sbl_magic": 0, + "alt_code_region_sbl_major": 0, + "alt_code_region_sbl_minor": 0 + }, + "nvs_code_region_conf": { + "nvs_start_phy_address": 1777664, + "nvs_region_size": 1089536, + "nvs_region_primary_wsoc_start_phy_address": 847868, + "nvs_region_primary_wsoc_magic": 0, + "nvs_region_primary_wsoc_major": 0, + "nvs_region_primary_wsoc_minor": 0, + "nvs_region_sec_wsoc_start_phy_address": 1314812, + "nvs_region_sec_wsoc_magic": 0, + "nvs_region_sec_wsoc_major": 0, + "nvs_region_sec_wsoc_minor": 0, + "nvs_region_primary_wsoc_bl2_start_phy_address": 0, + "nvs_region_primary_wsoc_bl2_magic": 0, + "nvs_region_primary_wsoc_bl2_major": 0, + "nvs_region_primary_wsoc_bl2_minor": 0, + "nvs_region_sec_wsoc_bl2_start_phy_address": 0, + "nvs_region_sec_wsoc_bl2_magic": 0, + "nvs_region_sec_wsoc_bl2_major": 0, + "nvs_region_sec_wsoc_bl2_minor": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/mx25u12843g/flash_disc_param_otfde.json b/boards/ti/lp_em_cc35x1/config/flash/mx25u12843g/flash_disc_param_otfde.json new file mode 100644 index 000000000000..4c0fe6211e50 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/mx25u12843g/flash_disc_param_otfde.json @@ -0,0 +1,286 @@ +{ + "otfde_header": { + "name": "OTFDEWFF3", + "flash_only": true, + "ip_protection": false, + "regions_lock": false, + "regions_number": 4, + "flash_enabled": true + }, + "bl_conf": { + "host_boot_done_lock": true, + "host_peripherals_lock": true, + "icache_conf_lock": true, + "m33_mem_part_lock": true, + "memss_firewall_lock": true, + "dma_channel_owner_lock": true, + "otfde_region_lock": true, + "core_events_lock": true + }, + "otfde_general": { + "parameters": { + "mem_otfde_initial_delay": 10, + "otfde_global_watchdog_timer": 5 + }, + "events": { + "reset_evt_mask": false, + "reset_evt_suspend": false, + "sft_reset_evt_mask": false, + "sft_reset_evt_suspend": false, + "bypass_mode_evt_mask": false, + "bypass_mode_evt_suspend": false, + "debug_mode_evt_mask": false, + "debug_mode_evt_suspend": false, + "general_evt_mask": false, + "general_evt_suspend": false, + "xspi_data_path_evt_mask": false, + "xspi_data_path_evt_suspend": false, + "xspi_cnfg_path_evt_mask": false, + "xspi_cnfg_path_evt_suspend": false, + "xspi_service_interrupt_evt_mask": false, + "xspi_service_interrupt_evt_suspend": false, + "trans_device_disabled_evt_mask": false, + "trans_device_disabled_evt_suspend": false, + "trans_region_disabled_evt_mask": false, + "trans_region_disabled_evt_suspend": false, + "trans_region_params_conf_evt_mask": false, + "trans_region_params_conf_evt_suspend": false, + "trans_multiple_regions_mapped_evt_mask": false, + "trans_multiple_regions_mapped_evt_suspend": false, + "trans_address_not_32_bit_evt_mask": false, + "trans_address_not_32_bit_evt_suspend": false, + "trans_size_not_32_bit_evt_mask": false, + "trans_size_not_32_bit_evt_suspend": false, + "trans_burst_not_32_bit_evt_mask": false, + "trans_burst_not_32_bit_evt_suspend": false, + "region_read_write_def_evt_mask": false, + "region_read_write_def_evt_suspend": false, + "suspend_while_disabled_evt_mask": false, + "suspend_while_disabled_evt_suspend": false + } + }, + "regions_settings": { + "region_parameters_lock": { + "REGION_0_PARAMS_0": true, + "REGION_0_PARAMS_1": true, + "REGION_0_PARAMS_2": true, + "REGION_1_PARAMS_0": false, + "REGION_1_PARAMS_1": false, + "REGION_1_PARAMS_2": false, + "REGION_2_PARAMS_0": true, + "REGION_2_PARAMS_1": true, + "REGION_2_PARAMS_2": true, + "REGION_3_PARAMS_0": false, + "REGION_3_PARAMS_1": false, + "REGION_3_PARAMS_2": false + }, + "region_0_protection": { + "mem_region_0_enabled": true, + "mem_region_0_device_id": 0, + "mem_region_0_spi_write_enable": true, + "mem_region_0_spi_read_enable": true, + "mem_region_0_physical_offset": 700, + "mem_region_0_security_id_msb": 0, + "mem_region_0_start_address": 81920, + "mem_region_0_end_address": 83617, + "mem_region_0_security_id_lsb": 0, + "mem_otfde_region_0_write_lock_en": false, + "mem_otfde_region_0_enc_dec_bypass": "Bypass" + }, + "region_1_protection": { + "mem_region_1_enabled": true, + "mem_region_1_device_id": 0, + "mem_region_1_spi_write_enable": true, + "mem_region_1_spi_read_enable": true, + "mem_region_1_physical_offset": 0, + "mem_region_1_security_id_msb": 0, + "mem_region_1_start_address": 655360, + "mem_region_1_end_address": 656059, + "mem_region_1_security_id_lsb": 0, + "mem_otfde_region_1_write_lock_en": false, + "mem_otfde_region_1_enc_dec_bypass": "Bypass" + }, + "region_2_protection": { + "mem_region_2_enabled": true, + "mem_region_2_device_id": 0, + "mem_region_2_spi_write_enable": true, + "mem_region_2_spi_read_enable": true, + "mem_region_2_physical_offset": 2398, + "mem_region_2_security_id_msb": 0, + "mem_region_2_start_address": 671744, + "mem_region_2_end_address": 673441, + "mem_region_2_security_id_lsb": 0, + "mem_otfde_region_2_write_lock_en": false, + "mem_otfde_region_2_enc_dec_bypass": "Bypass" + }, + "region_3_protection": { + "mem_region_3_enabled": false, + "mem_region_3_device_id": 1, + "mem_region_3_spi_write_enable": true, + "mem_region_3_spi_read_enable": true, + "mem_region_3_physical_offset": 0, + "mem_region_3_security_id_msb": 0, + "mem_region_3_start_address": 1, + "mem_region_3_end_address": 0, + "mem_region_3_security_id_lsb": 0, + "mem_otfde_region_3_write_lock_en": false, + "mem_otfde_region_3_enc_dec_bypass": "Bypass" + } + }, + "devices": { + "header": { + "flash_device_switch_conf": 1, + "ram_device_switch_conf": 1 + }, + "flash_switch": { + "flash_grant_sel": 0, + "flash_data_for_conf_0": 2181562505, + "flash_offset_bits_for_conf_0": 0, + "flash_stop_bit_for_conf_0": 0, + "flash_data_for_conf_1": 100803307, + "flash_offset_bits_for_conf_1": 1, + "flash_stop_bit_for_conf_1": 0, + "flash_data_for_conf_2": 139266, + "flash_offset_bits_for_conf_2": 2, + "flash_stop_bit_for_conf_2": 0, + "flash_data_for_conf_3": 1, + "flash_offset_bits_for_conf_3": 4, + "flash_stop_bit_for_conf_3": 0, + "flash_data_for_conf_4": 1076887634, + "flash_offset_bits_for_conf_4": 45, + "flash_stop_bit_for_conf_4": 0, + "flash_data_for_conf_5": 3224371282, + "flash_offset_bits_for_conf_5": 45, + "flash_stop_bit_for_conf_5": 0, + "flash_data_for_conf_6": 262149, + "flash_offset_bits_for_conf_6": 14, + "flash_stop_bit_for_conf_6": 0, + "flash_data_for_conf_7": 0, + "flash_offset_bits_for_conf_7": 44, + "flash_stop_bit_for_conf_7": 1, + "flash_data_for_conf_8": 0, + "flash_offset_bits_for_conf_8": 0, + "flash_stop_bit_for_conf_8": 1, + "flash_data_for_conf_9": 0, + "flash_offset_bits_for_conf_9": 0, + "flash_stop_bit_for_conf_9": 1, + "flash_data_for_conf_10": 0, + "flash_offset_bits_for_conf_10": 0, + "flash_stop_bit_for_conf_10": 1, + "flash_data_for_conf_11": 0, + "flash_offset_bits_for_conf_11": 0, + "flash_stop_bit_for_conf_11": 1, + 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0, + "flash_stop_bit_for_conf_21": 1, + "flash_data_for_conf_22": 0, + "flash_offset_bits_for_conf_22": 0, + "flash_stop_bit_for_conf_22": 1, + "flash_data_for_conf_23": 0, + "flash_offset_bits_for_conf_23": 0, + "flash_stop_bit_for_conf_23": 1 + }, + "ram_switch": { + "ram_grant_sel": 0, + "ram_data_for_conf_0": 2181562505, + "ram_offset_bits_for_conf_0": 0, + "ram_stop_bit_for_conf_0": 0, + "ram_data_for_conf_1": 100803307, + "ram_offset_bits_for_conf_1": 1, + "ram_stop_bit_for_conf_1": 0, + "ram_data_for_conf_2": 139266, + "ram_offset_bits_for_conf_2": 2, + "ram_stop_bit_for_conf_2": 0, + "ram_data_for_conf_3": 1, + "ram_offset_bits_for_conf_3": 4, + "ram_stop_bit_for_conf_3": 0, + "ram_data_for_conf_4": 1076887634, + "ram_offset_bits_for_conf_4": 45, + "ram_stop_bit_for_conf_4": 0, + "ram_data_for_conf_5": 3224371282, + "ram_offset_bits_for_conf_5": 45, + "ram_stop_bit_for_conf_5": 0, + "ram_data_for_conf_6": 262149, + "ram_offset_bits_for_conf_6": 14, + "ram_stop_bit_for_conf_6": 0, + "ram_data_for_conf_7": 0, + "ram_offset_bits_for_conf_7": 44, + "ram_stop_bit_for_conf_7": 1, + "ram_data_for_conf_8": 0, + "ram_offset_bits_for_conf_8": 0, + "ram_stop_bit_for_conf_8": 1, + "ram_data_for_conf_9": 0, + "ram_offset_bits_for_conf_9": 0, + "ram_stop_bit_for_conf_9": 1, + "ram_data_for_conf_10": 0, + "ram_offset_bits_for_conf_10": 0, + "ram_stop_bit_for_conf_10": 1, + "ram_data_for_conf_11": 0, + "ram_offset_bits_for_conf_11": 0, + "ram_stop_bit_for_conf_11": 1, + "ram_data_for_conf_12": 0, + "ram_offset_bits_for_conf_12": 0, + "ram_stop_bit_for_conf_12": 1, + "ram_data_for_conf_13": 0, + "ram_offset_bits_for_conf_13": 0, + "ram_stop_bit_for_conf_13": 1, + "ram_data_for_conf_14": 0, + "ram_offset_bits_for_conf_14": 0, + "ram_stop_bit_for_conf_14": 1, + "ram_data_for_conf_15": 0, + "ram_offset_bits_for_conf_15": 0, + "ram_stop_bit_for_conf_15": 1, + "ram_data_for_conf_16": 0, + "ram_offset_bits_for_conf_16": 0, + "ram_stop_bit_for_conf_16": 1, + "ram_data_for_conf_17": 0, + "ram_offset_bits_for_conf_17": 0, + "ram_stop_bit_for_conf_17": 1, + "ram_data_for_conf_18": 0, + "ram_offset_bits_for_conf_18": 0, + "ram_stop_bit_for_conf_18": 1, + "ram_data_for_conf_19": 0, + "ram_offset_bits_for_conf_19": 0, + "ram_stop_bit_for_conf_19": 1, + "ram_data_for_conf_20": 0, + "ram_offset_bits_for_conf_20": 0, + "ram_stop_bit_for_conf_20": 1, + "ram_data_for_conf_21": 0, + "ram_offset_bits_for_conf_21": 0, + "ram_stop_bit_for_conf_21": 1, + "ram_data_for_conf_22": 0, + "ram_offset_bits_for_conf_22": 0, + "ram_stop_bit_for_conf_22": 1, + "ram_data_for_conf_23": 0, + "ram_offset_bits_for_conf_23": 0, + "ram_stop_bit_for_conf_23": 1 + } + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/mx25u12843g/flash_disc_param_xspi.json b/boards/ti/lp_em_cc35x1/config/flash/mx25u12843g/flash_disc_param_xspi.json new file mode 100644 index 000000000000..3b54f8d1f2be --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/mx25u12843g/flash_disc_param_xspi.json @@ -0,0 +1,485 @@ +{ + "xspi_header": { + "name": "xSPIWFF3", + "device": "CC3500", + "use_hardware": "MX25U12843G", + "use_case": "Quadro", + "dqs_support": 0, + "flash_only": 1, + "flash_separate_reset": 0, + "ram_separate_reset": true, + "clock_frequency": 80, + "qospi_clock_divider": 1, + "flash_device_character_conf": 0, + "ram_device_character_conf": 0, + "header_advanced": 0, + "phy_mode_enable": 1, + "pipeline_mode_enable": 1, + "loopback_support": "No", + "qspi_ref_clock": 80, + "spi_clock_freq": 20, + "spi_clock_divider": 1, + "flash_device_size": 16, + "flash_bytes_per_block": 16, + "flash_bytes_per_page": 256, + "flash_number_of_address_bytes": 3, + "flash_dual_opcode": 0, + "flash_jedec_manufacturer_id": 0, + "flash_jedec_device_id": 0, + "flash_name": "MX25U12843G", + "flash_page_size": 256, + "flash_sector_size": 4096, + "flash_cs_polarity": "ACTIVE_LOW", + "flash_sw_reset_type": "x1xxxx", + "ram_device_size": 8, + "ram_bytes_per_block": 16, + "ram_bytes_per_page": 256, + "ram_number_of_address_bytes": 3, + "ram_dual_opcode": 0, + "ram_jedec_manufacturer_id": 0, + "ram_jedec_device_id": 0, + "ram_name": "NO_PSRAM", + "ram_page_size": 256, + "ram_sector_size": 4096, + "ram_cs_polarity": "ACTIVE_LOW", + "ram_sw_reset_type": "x1xxxx", + "flash_write_operation_modes": "4S-4S-4S", + "flash_read_operation_modes": "4S-4S-4S", + "ram_write_operation_modes": "4S-4S-4S", + "ram_read_operation_modes": "4S-4S-4S", + "crc_enable": 0, + "enable_dtr": 0, + "enable_ahb_decoder": 0, + "enter_xip_mod_immediately": 0, + "enter_xip_mod_next_read": 0, + "ahb_address_remapping": 0, + "enable_dma": 0, + "select_decode": 0, + "legacy_ip_mode": 0, + "direct_access": 1 + }, + "xspi_pinmux": { + "xspi_clk_input": 44, + "xspi_clk_input_use_hw": 0, + "xspi_clk_input_mode": "Input", + "xspi_clk_input_pull": "None", + "xspi_clk_input_interrupt_trigger": "Low", + "xspi_clk_input_dont_conf": 0, + "xspi_clk_input_output_strength": "High", + "xspi_clk_input_initial_output_state": "High", + "xspi_clk": 24, + "xspi_clk_use_hw": "None", + "xspi_clk_mode": "Output", + "xspi_clk_pull": "None", + "xspi_clk_output_strength": "High", + "xspi_clk_initial_output_state": "High", + "xspi_clk_interrupt_trigger": "None", + "xspi_clk_dont_conf": 0, + "xspi_flash_cs": 20, + "xspi_flash_cs_use_hw": "None", + "xspi_flash_cs_mode": "Output", + "xspi_flash_cs_pull": "None", + "xspi_flash_cs_output_strength": "High", + "xspi_flash_cs_initial_output_state": "High", + "xspi_flash_cs_interrupt_trigger": "None", + "xspi_flash_cs_dont_conf": 0, + "xspi_data_0": 25, + "xspi_data_0_use_hw": "None", + "xspi_data_0_mode": "Input", + "xspi_data_0_pull": "None", + "xspi_data_0_output_strength": "High", + "xspi_data_0_initial_output_state": "High", + "xspi_data_0_interrupt_trigger": "Low", + "xspi_data_0_dont_conf": 0, + "xspi_data_1": 21, + "xspi_data_1_use_hw": "None", + "xspi_data_1_mode": "Input", + "xspi_data_1_pull": "None", + "xspi_data_1_output_strength": "High", + "xspi_data_1_initial_output_state": "High", + "xspi_data_1_interrupt_trigger": "Low", + "xspi_data_1_dont_conf": 0, + "xspi_data_2": 22, + "xspi_data_2_use_hw": "None", + "xspi_data_2_mode": "Input", + "xspi_data_2_pull": "None", + "xspi_data_2_output_strength": "High", + "xspi_data_2_initial_output_state": "High", + "xspi_data_2_interrupt_trigger": "Low", + "xspi_data_2_dont_conf": 0, + "xspi_data_3": 23, + "xspi_data_3_use_hw": "None", + "xspi_data_3_mode": "Input", + "xspi_data_3_pull": "None", + "xspi_data_3_output_strength": "High", + "xspi_data_3_initial_output_state": "High", + "xspi_data_3_interrupt_trigger": "Low", + "xspi_data_3_dont_conf": 0, + "xspi_data_4": 26, + "xspi_data_4_use_hw": "None", + "xspi_data_4_mode": "Input", + "xspi_data_4_pull": "None", + "xspi_data_4_output_strength": "High", + "xspi_data_4_initial_output_state": "High", + "xspi_data_4_interrupt_trigger": "None", + "xspi_data_4_dont_conf": 0, + "xspi_data_5": 27, + "xspi_data_5_use_hw": "None", + "xspi_data_5_mode": "Input", + "xspi_data_5_pull": "None", + "xspi_data_5_output_strength": "High", + "xspi_data_5_initial_output_state": "High", + "xspi_data_5_interrupt_trigger": "None", + "xspi_data_5_dont_conf": 0, + "xspi_data_6": 28, + "xspi_data_6_use_hw": "None", + "xspi_data_6_mode": "Input", + "xspi_data_6_pull": "None", + "xspi_data_6_output_strength": "High", + "xspi_data_6_initial_output_state": "High", + "xspi_data_6_interrupt_trigger": "None", + "xspi_data_6_dont_conf": 0, + "xspi_data_7": 29, + "xspi_data_7_use_hw": "None", + "xspi_data_7_mode": "Input", + "xspi_data_7_pull": "None", + "xspi_data_7_output_strength": "High", + "xspi_data_7_initial_output_state": "High", + "xspi_data_7_interrupt_trigger": "None", + "xspi_data_7_dont_conf": 0, + "xspi_reset_flash": 36, + "xspi_reset_flash_use_hw": "None", + "xspi_reset_flash_mode": "Output", + "xspi_reset_flash_pull": "None", + "xspi_reset_flash_output_strength": "High", + "xspi_reset_flash_initial_output_state": "High", + "xspi_reset_flash_interrupt_trigger": "None", + "xspi_reset_flash_dont_conf": 0, + "xspi_cs_ram": 3, + "xspi_cs_ram_use_hw": "None", + "xspi_cs_ram_mode": "Output", + "xspi_cs_ram_pull": "None", + "xspi_cs_ram_output_strength": "High", + "xspi_cs_ram_initial_output_state": "High", + "xspi_cs_ram_interrupt_trigger": "None", + "xspi_cs_ram_dont_conf": 0, + "xspi_dqs": 30, + "xspi_dqs_use_hw": "None", + "xspi_dqs_mode": "Input", + "xspi_dqs_pull": "None", + "xspi_dqs_output_strength": "High", + "xspi_dqs_initial_output_state": "High", + "xspi_dqs_interrupt_trigger": "None", + "xspi_dqs_dont_conf": 0, + "xspi_reset_ram": 2, + "xspi_reset_ram_use_hw": "None", + "xspi_reset_ram_mode": "Input", + "xspi_reset_ram_pull": "None", + "xspi_reset_ram_output_strength": "High", + "xspi_reset_ram_initial_output_state": "High", + "xspi_reset_ram_interrupt_trigger": "None", + "xspi_reset_ram_dont_conf": 0 + }, + "xspi_operations": { + "xspi_operations_clocks": { + "clock_phase": 0, + "clock_polarity": 0, + "spi_mode": "2'b00" + }, + "xspi_operations_chip_select": { + "csda": 2, + "csdads": 0, + "cseot": 4, + "cssot": 1 + }, + "xspi_operations_reset": { + "flash_jedec_reset": 0, + "ram_jedec_reset": 0, + "flash_treset": 20, + "ram_treset": 20 + }, + "xspi_phy_operations": { + "flash_rx_dll_bypass_bit": 0, + "flash_dll_tx_delay": 42, + "flash_dll_rx_delay": 62, + "ram_rx_dll_bypass_bit": 0, + "ram_dll_tx_delay": 42, + "ram_dll_rx_delay": 62 + }, + "xspi_read_operations": { + "flash_dummy_rd_cycles": 4, + "flash_read_opcode": 11, + "suppl_flash_read_opcode": 0, + "ram_dummy_rd_cycles": 4, + "ram_read_opcode": 11, + "suppl_ram_read_opcode": 0, + "flash_non_cont_read_enable": 0, + "flash_max_read_jobs": 256, + "ram_non_cont_read_enable": 0, + "ram_max_read_jobs": 256, + "rww_en": 0, + "device_size": 8, + "number_of_banks": 1, + "bank_size": 8, + "mode_bit_enable": 0 + }, + "xspi_write_operations": { + "flash_address_and_data": { + "flash_dummy_wr_cycles": 0 + }, + "flash_command": { + "flash_write_opcode": 2, + "suppl_flash_write_opcode": 0 + }, + "ram_address_and_data": { + "ram_dummy_wr_cycles": 0 + }, + "ram_command": { + "ram_write_opcode": 2, + "suppl_ram_write_opcode": 0 + }, + "write_to_buffer": { + "flash_write_to_buffer_support": 0, + "ram_write_to_buffer_support": 0 + }, + "non_continuous_write": { + "flash_non_cont_write_enable": 0, + "flash_max_write_jobs": 64, + "ram_non_cont_write_enable": 0, + "ram_max_write_jobs": 0 + }, + "flash_program_operation": { + "flash_min_program_size": "256 B", + "flash_program_opcode": 2, + "suppl_flash_program_opcode": 0, + "flash_maximum_program_time_limit": 1600 + }, + "flash_erase_operation": { + "flash_min_erase_size": "4 kB", + "flash_erase_opcode": 32, + "suppl_flash_erase_opcode": 0, + "flash_maximum_erase_time_limit": 4095 + }, + "flash_erase_conf": { + "flash_block_erase_opcode": 0, + "suppl_block_flash_erase_opcode": 0, + "flash_sector_erase_opcode": 0, + "suppl_sector_flash_erase_opcode": 0, + "flash_chip_erase_opcode": 0, + "suppl_chip_flash_erase_opcode": 0 + }, + "ram_program_operation": { + "ram_min_program_size": "256 B", + "ram_program_opcode": 2, + "suppl_ram_program_opcode": 0, + "ram_maximum_program_time_limit": 1600 + }, + "ram_erase_conf": { + "ram_block_erase_opcode": 0, + "suppl_block_ram_erase_opcode": 0, + "ram_sector_erase_opcode": 0, + "suppl_sector_ram_erase_opcode": 0, + "ram_chip_erase_opcode": 0, + "suppl_chip_ram_erase_opcode": 0 + }, + "flash_buffer_support": { + "flash_pre_write_sequence": 0, + "flash_post_write_sequence": 0, + "flash_write_protection_timer_en": 0, + "flash_write_buffer_timer_mode": 16, + "flash_write_buffer_timer_range": 0, + "flash_service_interrupt_criteria": 0 + }, + "ram_buffer_support": { + "ram_pre_write_sequence": 0, + "ram_post_write_sequence": 0, + "ram_write_protection_timer_en": 0, + "ram_write_buffer_timer_mode": 16, + "ram_write_buffer_timer_range": 0, + "ram_service_interrupt_criteria": 0 + }, + "flash_pre_write_conf": { + "flash_pre_write_job_done_grant_sel": 0, + "data_for_flash_pre_write_conf_0": 0, + "offset_bits_for_flash_pre_write_conf_0": 0, + "stop_bit_for_flash_pre_write_conf_0": 1, + "data_for_flash_pre_write_conf_1": 0, + "offset_bits_for_flash_pre_write_conf_1": 0 + }, + "flash_post_write_conf": { + "flash_post_write_job_done_grant_sel": 0, + "data_for_flash_post_write_conf_0": 0, + "offset_bits_for_flash_post_write_conf_0": 0, + "stop_bit_for_flash_post_write_conf_0": 1, + "data_for_flash_post_write_conf_1": 0, + "offset_bits_for_flash_post_write_conf_1": 0 + }, + "ram_pre_write_conf": { + "ram_pre_write_job_done_grant_sel": 0, + "data_for_ram_pre_write_conf_0": 0, + "offset_bits_for_ram_pre_write_conf_0": 0, + "stop_bit_for_ram_pre_write_conf_0": 1, + "data_for_ram_pre_write_conf_1": 0, + "offset_bits_for_ram_pre_write_conf_1": 0 + }, + "ram_post_write_conf": { + "ram_post_write_job_done_grant_sel": 0, + "data_for_ram_post_write_conf_0": 0, + "offset_bits_for_ram_post_write_conf_0": 0, + "stop_bit_for_ram_post_write_conf_0": 1, + "data_for_ram_post_write_conf_1": 0, + "offset_bits_for_ram_post_write_conf_1": 0 + } + }, + "xspi_capture_operations": { + "read_data_capture": { + "flash_delay_transmitted_data": 0, + "flash_loopback_clock": 0, + "flash_bypass_adapted_loopback": 1, + "flash_sample_edge_sel": 0, + "ram_delay_transmitted_data": 0, + "ram_loopback_clock": 0, + "ram_bypass_adapted_loopback": 1, + "ram_sample_edge_sel": 0 + }, + "delays": { + "flash_full_half_cycle_delay": 0, + "flash_dll_bypass_mode": 1, + "flash_phase_detect_sel": 0, + "flash_dll_lock_num": 0, + "flash_dll_start_point": 0, + "flash_loopback_clock": 0, + "ram_full_half_cycle_delay": 0, + "ram_dll_bypass_mode": 1, + "ram_phase_detect_sel": 0, + "ram_dll_lock_num": 0, + "ram_dll_start_point": 0, + "ram_loopback_clock": 0 + }, + "operation_modes": { + "flash_sfdp_support": 0, + "ram_sfdp_support": 0, + "flash_pm_support": 0, + "ram_pm_support": 0, + "flash_sfdp_opcode": 0, + "suppl_flash_sfdp_opcode": 0, + "ram_sfdp_opcode": 0, + "suppl_ram_sfdp_opcode": 0, + "flash_enter_dpd_opcode": 185, + "suppl_flash_enter_dpd_opcode": 0, + "flash_exit_dpd_opcode": 171, + "suppl_flash_exit_dpd_opcode": 0, + "ram_enter_dpd_opcode": 185, + "suppl_ram_enter_dpd_opcode": 0, + "ram_exit_dpd_opcode": 171, + "suppl_ram_exit_dpd_opcode": 0, + "flash_quad_enable_opcode": 53, + "suppl_flash_quad_enable_opcode": 0, + "flash_quad_disable_opcode": 245, + "suppl_flash_quad_disable_opcode": 0, + "flash_octal_enable_opcode": 0, + "suppl_flash_octal_enable_opcode": 0, + "flash_octal_disable_opcode": 0, + "suppl_flash_octal_disable_opcode": 0, + "ram_quad_enable_opcode": 53, + "suppl_ram_quad_enable_opcode": 0, + "ram_quad_disable_opcode": 245, + "suppl_ram_quad_disable_opcode": 0, + "ram_octal_enable_opcode": 0, + "suppl_ram_octal_enable_opcode": 0, + "ram_octal_disable_opcode": 0, + "suppl_ram_octal_disable_opcode": 0 + } + } + }, + "external_memory_reporting": { + "header": { + "flash_auto_polling_enable": 1, + "flash_wel_enable": 1, + "flash_write_protect_enable": 0, + "flash_alternate_polling_conf_enable": 0, + "ram_auto_polling_enable": 1, + "ram_wel_enable": 1, + "ram_write_protect_enable": 0, + "ram_alternate_polling_conf_enable": 0 + }, + "flash_auto_polling": { + "flash_polling_repetition_delay": 0, + "flash_polling_count": 4, + "flash_enable_polling_expiration": 0, + "flash_polling_polarity": 0, + "flash_polling_address_phase_enable": 0, + "flash_polling_bit_index": 0, + "flash_numbers_poll_cycles": 65535, + "flash_dummy_autopoll_cycles": 0 + }, + "ram_auto_polling": { + "ram_polling_repetition_delay": 0, + "ram_polling_count": 4, + "ram_enable_polling_expiration": 0, + "ram_polling_polarity": 0, + "ram_polling_address_phase_enable": 0, + "ram_polling_bit_index": 0, + "ram_numbers_poll_cycles": 65535, + "ram_dummy_autopoll_cycles": 0 + }, + "flash_polling_command": { + "flash_polling_opcode": 5, + "suppl_flash_polling_opcode": 0 + }, + "ram_polling_command": { + "ram_polling_opcode": 5, + "suppl_ram_polling_opcode": 0 + }, + "flash_alternate_polling": { + "flash_polling_resp_count": 1023, + "flash_polling_iterations": 1, + "flash_polling_enabled": 0, + "flash_polling_disabled": 0, + "flash_grant_sel": 0, + "flash_data_for_enable_poling_conf_0": 0, + "flash_offset_bits_for_enable_poling_conf_0": 0, + "flash_stop_bit_for_enable_poling_conf_0": 1, + "flash_data_for_enable_poling_conf_1": 0, + "flash_offset_bits_for_enable_poling_conf_1": 0, + "flash_stop_bit_for_enable_poling_conf_1": 1, + "flash_data_for_disable_poling_conf_0": 0, + "flash_offset_bits_for_disable_poling_conf_0": 0, + "flash_stop_bit_for_disable_poling_conf_0": 1, + "flash_data_for_disable_poling_conf_1": 0, + "flash_offset_bits_for_disable_poling_conf_1": 0, + "flash_stop_bit_for_disable_poling_conf_1": 1 + }, + "ram_alternate_polling": { + "ram_polling_resp_count": 1023, + "ram_polling_iterations": 1, + "ram_polling_enabled": 0, + "ram_polling_disabled": 0, + "ram_grant_sel": 0, + "ram_data_for_enable_poling_conf_0": 0, + "ram_offset_bits_for_enable_poling_conf_0": 0, + "ram_stop_bit_for_enable_poling_conf_0": 1, + "ram_data_for_enable_poling_conf_1": 0, + "ram_offset_bits_for_enable_poling_conf_1": 0, + "ram_stop_bit_for_enable_poling_conf_1": 1, + "ram_data_for_disable_poling_conf_0": 0, + "ram_offset_bits_for_disable_poling_conf_0": 0, + "ram_stop_bit_for_disable_poling_conf_0": 1, + "ram_data_for_disable_poling_conf_1": 0, + "ram_offset_bits_for_disable_poling_conf_1": 0, + "ram_stop_bit_for_disable_poling_conf_1": 1 + }, + "flash_wel_command": { + "flash_wel_opcode": 6, + "suppl_flash_wel_opcode": 0 + }, + "ram_wel_command": { + "ram_wel_opcode": 6, + "suppl_ram_wel_opcode": 0 + } + }, + "event": { + "host_nvic_irq": 0, + "core_10_mux_sel": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/mx25u3235f/flash_disc_param_ext_mem.json b/boards/ti/lp_em_cc35x1/config/flash/mx25u3235f/flash_disc_param_ext_mem.json new file mode 100644 index 000000000000..321810768be1 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/mx25u3235f/flash_disc_param_ext_mem.json @@ -0,0 +1,99 @@ +{ + "vendor_primary_sbl": true, + "ti_wsoc_primary_container": true, + "ti_wsoc_bl2_primary_container": true, + "nvs_enable": true, + "vendor_alternate_image": true, + "vendor_sbl_alternate_image": true, + "ti_bl_alternate_image": true, + "ti_wsoc_alternate_image": true, + "ti_wsoc_bl2_alternate_image": true, + "region_0": { + "mem_region_0_start_phy_address": 1069056, + "mem_region_0_end_phy_address": 4194303, + "region0_boot": false, + "region0_main_code": true, + "region0_nvs": false, + "region0_wsoc_code": false, + "region0_alternate_code": false + }, + "region_1": { + "mem_region_1_start_phy_address": 0, + "mem_region_1_end_phy_address": 1069055, + "region1_boot": true, + "region1_main_code": false, + "region1_nvs": true, + "region1_wsoc_code": true, + "region1_alternate_code": false + }, + "region_2": { + "mem_region_2_start_phy_address": 0, + "mem_region_2_end_phy_address": 0, + "region2_boot": false, + "region2_main_code": false, + "region2_nvs": false, + "region2_wsoc_code": false, + "region2_alternate_code": true + }, + "region_3": { + "mem_region_3_start_phy_address": 0, + "mem_region_3_end_phy_address": 0, + "region3_boot": false, + "region3_main_code": false, + "region3_nvs": false, + "region3_wsoc_code": false, + "region3_alternate_code": false + }, + "boot_region_conf": { + "boot_region_size": 0, + "boot_region_flash_disco_param_start_address": 0, + "boot_region_primary_ti_bl_start_phy_address": 12284, + "boot_region_primary_ti_bl_magic": 0, + "boot_region_primary_ti_bl_major": 0, + "boot_region_primary_ti_bl_minor": 0, + "boot_region_sec_ti_bl_start_phy_address": 430076, + "boot_region_sec_ti_bl_magic": 0, + "boot_region_sec_ti_bl_major": 0, + "boot_region_sec_ti_bl_minor": 0 + }, + "main_code_region_conf": { + "main_code_region_vendor_image_start_phy_address": 1073148, + "main_code_region_vendor_image_magic": 0, + "main_code_region_vendor_image_major": 0, + "main_code_region_vendor_image_minor": 0, + "main_code_region_sbl_start_phy_address": 0, + "main_code_region_sbl_magic": 0, + "main_code_region_sbl_major": 0, + "main_code_region_sbl_minor": 0 + }, + "alt_code_region_conf": { + "alt_code_region_vendor_image_start_phy_address": 4194304, + "alt_code_region_vendor_image_magic": 0, + "alt_code_region_vendor_image_major": 0, + "alt_code_region_vendor_image_minor": 0, + "alt_code_region_sbl_start_phy_address": 0, + "alt_code_region_sbl_magic": 0, + "alt_code_region_sbl_major": 0, + "alt_code_region_sbl_minor": 0 + }, + "nvs_code_region_conf": { + "nvs_start_phy_address": 892928, + "nvs_region_size": 176128, + "nvs_region_primary_wsoc_start_phy_address": 430076, + "nvs_region_primary_wsoc_magic": 0, + "nvs_region_primary_wsoc_major": 0, + "nvs_region_primary_wsoc_minor": 0, + "nvs_region_sec_wsoc_start_phy_address": 897020, + "nvs_region_sec_wsoc_magic": 0, + "nvs_region_sec_wsoc_major": 0, + "nvs_region_sec_wsoc_minor": 0, + "nvs_region_primary_wsoc_bl2_start_phy_address": 0, + "nvs_region_primary_wsoc_bl2_magic": 0, + "nvs_region_primary_wsoc_bl2_major": 0, + "nvs_region_primary_wsoc_bl2_minor": 0, + "nvs_region_sec_wsoc_bl2_start_phy_address": 0, + "nvs_region_sec_wsoc_bl2_magic": 0, + "nvs_region_sec_wsoc_bl2_major": 0, + "nvs_region_sec_wsoc_bl2_minor": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/mx25u3235f/flash_disc_param_otfde.json b/boards/ti/lp_em_cc35x1/config/flash/mx25u3235f/flash_disc_param_otfde.json new file mode 100644 index 000000000000..e1106f2330ac --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/mx25u3235f/flash_disc_param_otfde.json @@ -0,0 +1,286 @@ +{ + "otfde_header": { + "name": "OTFDEWFF3", + "flash_only": true, + "ip_protection": false, + "regions_lock": false, + "regions_number": 4, + "flash_enabled": true + }, + "bl_conf": { + "host_boot_done_lock": true, + "host_peripherals_lock": true, + "icache_conf_lock": true, + "m33_mem_part_lock": true, + "memss_firewall_lock": true, + "dma_channel_owner_lock": true, + "otfde_region_lock": true, + "core_events_lock": true + }, + "otfde_general": { + "parameters": { + "mem_otfde_initial_delay": 10, + "otfde_global_watchdog_timer": 5 + }, + "events": { + "reset_evt_mask": false, + "reset_evt_suspend": false, + "sft_reset_evt_mask": false, + "sft_reset_evt_suspend": false, + "bypass_mode_evt_mask": false, + "bypass_mode_evt_suspend": false, + "debug_mode_evt_mask": false, + "debug_mode_evt_suspend": false, + "general_evt_mask": false, + "general_evt_suspend": false, + "xspi_data_path_evt_mask": false, + "xspi_data_path_evt_suspend": false, + "xspi_cnfg_path_evt_mask": false, + "xspi_cnfg_path_evt_suspend": false, + "xspi_service_interrupt_evt_mask": false, + "xspi_service_interrupt_evt_suspend": false, + "trans_device_disabled_evt_mask": false, + "trans_device_disabled_evt_suspend": false, + "trans_region_disabled_evt_mask": false, + "trans_region_disabled_evt_suspend": false, + "trans_region_params_conf_evt_mask": false, + "trans_region_params_conf_evt_suspend": false, + "trans_multiple_regions_mapped_evt_mask": false, + "trans_multiple_regions_mapped_evt_suspend": false, + "trans_address_not_32_bit_evt_mask": false, + "trans_address_not_32_bit_evt_suspend": false, + "trans_size_not_32_bit_evt_mask": false, + "trans_size_not_32_bit_evt_suspend": false, + "trans_burst_not_32_bit_evt_mask": false, + "trans_burst_not_32_bit_evt_suspend": false, + "region_read_write_def_evt_mask": false, + "region_read_write_def_evt_suspend": false, + "suspend_while_disabled_evt_mask": false, + "suspend_while_disabled_evt_suspend": false + } + }, + "regions_settings": { + "region_parameters_lock": { + "REGION_0_PARAMS_0": true, + "REGION_0_PARAMS_1": true, + "REGION_0_PARAMS_2": true, + "REGION_1_PARAMS_0": false, + "REGION_1_PARAMS_1": false, + "REGION_1_PARAMS_2": false, + "REGION_2_PARAMS_0": true, + "REGION_2_PARAMS_1": true, + "REGION_2_PARAMS_2": true, + "REGION_3_PARAMS_0": false, + "REGION_3_PARAMS_1": false, + "REGION_3_PARAMS_2": false + }, + "region_0_protection": { + "mem_region_0_enabled": true, + "mem_region_0_device_id": 0, + "mem_region_0_spi_write_enable": true, + "mem_region_0_spi_read_enable": true, + "mem_region_0_physical_offset": 261, + "mem_region_0_security_id_msb": 0, + "mem_region_0_start_address": 81920, + "mem_region_0_end_address": 82682, + "mem_region_0_security_id_lsb": 0, + "mem_otfde_region_0_write_lock_en": false, + "mem_otfde_region_0_enc_dec_bypass": "Bypass" + }, + "region_1_protection": { + "mem_region_1_enabled": true, + "mem_region_1_device_id": 0, + "mem_region_1_spi_write_enable": true, + "mem_region_1_spi_read_enable": true, + "mem_region_1_physical_offset": 0, + "mem_region_1_security_id_msb": 0, + "mem_region_1_start_address": 655360, + "mem_region_1_end_address": 655620, + "mem_region_1_security_id_lsb": 0, + "mem_otfde_region_1_write_lock_en": false, + "mem_otfde_region_1_enc_dec_bypass": "Bypass" + }, + "region_2_protection": { + "mem_region_2_enabled": false, + "mem_region_2_device_id": 0, + "mem_region_2_spi_write_enable": true, + "mem_region_2_spi_read_enable": true, + "mem_region_2_physical_offset": 0, + "mem_region_2_security_id_msb": 0, + "mem_region_2_start_address": 1, + "mem_region_2_end_address": 0, + "mem_region_2_security_id_lsb": 0, + "mem_otfde_region_2_write_lock_en": false, + "mem_otfde_region_2_enc_dec_bypass": "Bypass" + }, + "region_3_protection": { + "mem_region_3_enabled": false, + "mem_region_3_device_id": 1, + "mem_region_3_spi_write_enable": true, + "mem_region_3_spi_read_enable": true, + "mem_region_3_physical_offset": 0, + "mem_region_3_security_id_msb": 0, + "mem_region_3_start_address": 1, + "mem_region_3_end_address": 0, + "mem_region_3_security_id_lsb": 0, + "mem_otfde_region_3_write_lock_en": false, + "mem_otfde_region_3_enc_dec_bypass": "Bypass" + } + }, + "devices": { + "header": { + "flash_device_switch_conf": 1, + "ram_device_switch_conf": 1 + }, + "flash_switch": { + "flash_grant_sel": 0, + "flash_data_for_conf_0": 2181562505, + "flash_offset_bits_for_conf_0": 0, + "flash_stop_bit_for_conf_0": 0, + "flash_data_for_conf_1": 67248651, + "flash_offset_bits_for_conf_1": 1, + "flash_stop_bit_for_conf_1": 0, + "flash_data_for_conf_2": 139266, + "flash_offset_bits_for_conf_2": 2, + "flash_stop_bit_for_conf_2": 0, + "flash_data_for_conf_3": 1, + "flash_offset_bits_for_conf_3": 4, + "flash_stop_bit_for_conf_3": 0, + "flash_data_for_conf_4": 1076887634, + "flash_offset_bits_for_conf_4": 45, + "flash_stop_bit_for_conf_4": 0, + "flash_data_for_conf_5": 3224371282, + "flash_offset_bits_for_conf_5": 45, + "flash_stop_bit_for_conf_5": 0, + "flash_data_for_conf_6": 262149, + "flash_offset_bits_for_conf_6": 14, + "flash_stop_bit_for_conf_6": 0, + "flash_data_for_conf_7": 0, + "flash_offset_bits_for_conf_7": 44, + "flash_stop_bit_for_conf_7": 1, + "flash_data_for_conf_8": 0, + "flash_offset_bits_for_conf_8": 0, + "flash_stop_bit_for_conf_8": 1, + "flash_data_for_conf_9": 0, + "flash_offset_bits_for_conf_9": 0, + "flash_stop_bit_for_conf_9": 1, + "flash_data_for_conf_10": 0, + "flash_offset_bits_for_conf_10": 0, + "flash_stop_bit_for_conf_10": 1, + "flash_data_for_conf_11": 0, + "flash_offset_bits_for_conf_11": 0, + "flash_stop_bit_for_conf_11": 1, + "flash_data_for_conf_12": 0, + "flash_offset_bits_for_conf_12": 0, + "flash_stop_bit_for_conf_12": 1, + "flash_data_for_conf_13": 0, + "flash_offset_bits_for_conf_13": 0, + "flash_stop_bit_for_conf_13": 1, + "flash_data_for_conf_14": 0, + "flash_offset_bits_for_conf_14": 0, + "flash_stop_bit_for_conf_14": 1, + "flash_data_for_conf_15": 0, + "flash_offset_bits_for_conf_15": 0, + "flash_stop_bit_for_conf_15": 1, + "flash_data_for_conf_16": 0, + "flash_offset_bits_for_conf_16": 0, + "flash_stop_bit_for_conf_16": 1, + "flash_data_for_conf_17": 0, + "flash_offset_bits_for_conf_17": 0, + "flash_stop_bit_for_conf_17": 1, + "flash_data_for_conf_18": 0, + "flash_offset_bits_for_conf_18": 0, + "flash_stop_bit_for_conf_18": 1, + "flash_data_for_conf_19": 0, + "flash_offset_bits_for_conf_19": 0, + "flash_stop_bit_for_conf_19": 1, + "flash_data_for_conf_20": 0, + "flash_offset_bits_for_conf_20": 0, + "flash_stop_bit_for_conf_20": 1, + "flash_data_for_conf_21": 0, + "flash_offset_bits_for_conf_21": 0, + "flash_stop_bit_for_conf_21": 1, + "flash_data_for_conf_22": 0, + "flash_offset_bits_for_conf_22": 0, + "flash_stop_bit_for_conf_22": 1, + "flash_data_for_conf_23": 0, + "flash_offset_bits_for_conf_23": 0, + "flash_stop_bit_for_conf_23": 1 + }, + "ram_switch": { + "ram_grant_sel": 0, + "ram_data_for_conf_0": 2181562505, + "ram_offset_bits_for_conf_0": 0, + "ram_stop_bit_for_conf_0": 0, + "ram_data_for_conf_1": 67248651, + "ram_offset_bits_for_conf_1": 1, + "ram_stop_bit_for_conf_1": 0, + "ram_data_for_conf_2": 139266, + "ram_offset_bits_for_conf_2": 2, + "ram_stop_bit_for_conf_2": 0, + "ram_data_for_conf_3": 1, + "ram_offset_bits_for_conf_3": 4, + "ram_stop_bit_for_conf_3": 0, + "ram_data_for_conf_4": 1076887634, + "ram_offset_bits_for_conf_4": 45, + "ram_stop_bit_for_conf_4": 0, + "ram_data_for_conf_5": 3224371282, + "ram_offset_bits_for_conf_5": 45, + "ram_stop_bit_for_conf_5": 0, + "ram_data_for_conf_6": 262149, + "ram_offset_bits_for_conf_6": 14, + "ram_stop_bit_for_conf_6": 0, + "ram_data_for_conf_7": 0, + "ram_offset_bits_for_conf_7": 44, + "ram_stop_bit_for_conf_7": 1, + "ram_data_for_conf_8": 0, + "ram_offset_bits_for_conf_8": 0, + "ram_stop_bit_for_conf_8": 1, + "ram_data_for_conf_9": 0, + "ram_offset_bits_for_conf_9": 0, + "ram_stop_bit_for_conf_9": 1, + "ram_data_for_conf_10": 0, + "ram_offset_bits_for_conf_10": 0, + "ram_stop_bit_for_conf_10": 1, + "ram_data_for_conf_11": 0, + "ram_offset_bits_for_conf_11": 0, + "ram_stop_bit_for_conf_11": 1, + "ram_data_for_conf_12": 0, + "ram_offset_bits_for_conf_12": 0, + "ram_stop_bit_for_conf_12": 1, + "ram_data_for_conf_13": 0, + "ram_offset_bits_for_conf_13": 0, + "ram_stop_bit_for_conf_13": 1, + "ram_data_for_conf_14": 0, + "ram_offset_bits_for_conf_14": 0, + "ram_stop_bit_for_conf_14": 1, + "ram_data_for_conf_15": 0, + "ram_offset_bits_for_conf_15": 0, + "ram_stop_bit_for_conf_15": 1, + "ram_data_for_conf_16": 0, + "ram_offset_bits_for_conf_16": 0, + "ram_stop_bit_for_conf_16": 1, + "ram_data_for_conf_17": 0, + "ram_offset_bits_for_conf_17": 0, + "ram_stop_bit_for_conf_17": 1, + "ram_data_for_conf_18": 0, + "ram_offset_bits_for_conf_18": 0, + "ram_stop_bit_for_conf_18": 1, + "ram_data_for_conf_19": 0, + "ram_offset_bits_for_conf_19": 0, + "ram_stop_bit_for_conf_19": 1, + "ram_data_for_conf_20": 0, + "ram_offset_bits_for_conf_20": 0, + "ram_stop_bit_for_conf_20": 1, + "ram_data_for_conf_21": 0, + "ram_offset_bits_for_conf_21": 0, + "ram_stop_bit_for_conf_21": 1, + "ram_data_for_conf_22": 0, + "ram_offset_bits_for_conf_22": 0, + "ram_stop_bit_for_conf_22": 1, + "ram_data_for_conf_23": 0, + "ram_offset_bits_for_conf_23": 0, + "ram_stop_bit_for_conf_23": 1 + } + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/mx25u3235f/flash_disc_param_xspi.json b/boards/ti/lp_em_cc35x1/config/flash/mx25u3235f/flash_disc_param_xspi.json new file mode 100644 index 000000000000..87a7d3543805 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/mx25u3235f/flash_disc_param_xspi.json @@ -0,0 +1,485 @@ +{ + "xspi_header": { + "name": "xSPIWFF3", + "device": "CC3500", + "use_hardware": "MX25U3235F", + "use_case": "Quadro", + "dqs_support": 0, + "flash_only": 1, + "flash_separate_reset": 0, + "ram_separate_reset": true, + "clock_frequency": 80, + "qospi_clock_divider": 1, + "flash_device_character_conf": 0, + "ram_device_character_conf": 0, + "header_advanced": 0, + "phy_mode_enable": 1, + "pipeline_mode_enable": 1, + "loopback_support": "No", + "qspi_ref_clock": 80, + "spi_clock_freq": 20, + "spi_clock_divider": 1, + "flash_device_size": 4, + "flash_bytes_per_block": 16, + "flash_bytes_per_page": 256, + "flash_number_of_address_bytes": 3, + "flash_dual_opcode": 0, + "flash_jedec_manufacturer_id": 0, + "flash_jedec_device_id": 0, + "flash_name": "MX25U3235F", + "flash_page_size": 256, + "flash_sector_size": 4096, + "flash_cs_polarity": "ACTIVE_LOW", + "flash_sw_reset_type": "x1xxxx", + "ram_device_size": 4, + "ram_bytes_per_block": 16, + "ram_bytes_per_page": 256, + "ram_number_of_address_bytes": 3, + "ram_dual_opcode": 0, + "ram_jedec_manufacturer_id": 0, + "ram_jedec_device_id": 0, + "ram_name": "NO_PSRAM", + "ram_page_size": 256, + "ram_sector_size": 4096, + "ram_cs_polarity": "ACTIVE_LOW", + "ram_sw_reset_type": "x1xxxx", + "flash_write_operation_modes": "4S-4S-4S", + "flash_read_operation_modes": "4S-4S-4S", + "ram_write_operation_modes": "4S-4S-4S", + "ram_read_operation_modes": "4S-4S-4S", + "crc_enable": 0, + "enable_dtr": 0, + "enable_ahb_decoder": 0, + "enter_xip_mod_immediately": 0, + "enter_xip_mod_next_read": 0, + "ahb_address_remapping": 0, + "enable_dma": 0, + "select_decode": 0, + "legacy_ip_mode": 0, + "direct_access": 1 + }, + "xspi_pinmux": { + "xspi_clk_input": 44, + "xspi_clk_input_use_hw": 0, + "xspi_clk_input_mode": "Input", + "xspi_clk_input_pull": "None", + "xspi_clk_input_interrupt_trigger": "Low", + "xspi_clk_input_dont_conf": 0, + "xspi_clk_input_output_strength": "High", + "xspi_clk_input_initial_output_state": "High", + "xspi_clk": 24, + "xspi_clk_use_hw": "None", + "xspi_clk_mode": "Output", + "xspi_clk_pull": "None", + "xspi_clk_output_strength": "High", + "xspi_clk_initial_output_state": "High", + "xspi_clk_interrupt_trigger": "None", + "xspi_clk_dont_conf": 0, + "xspi_flash_cs": 20, + "xspi_flash_cs_use_hw": "None", + "xspi_flash_cs_mode": "Output", + "xspi_flash_cs_pull": "None", + "xspi_flash_cs_output_strength": "High", + "xspi_flash_cs_initial_output_state": "High", + "xspi_flash_cs_interrupt_trigger": "None", + "xspi_flash_cs_dont_conf": 0, + "xspi_data_0": 25, + "xspi_data_0_use_hw": "None", + "xspi_data_0_mode": "Input", + "xspi_data_0_pull": "None", + "xspi_data_0_output_strength": "High", + "xspi_data_0_initial_output_state": "High", + "xspi_data_0_interrupt_trigger": "Low", + "xspi_data_0_dont_conf": 0, + "xspi_data_1": 21, + "xspi_data_1_use_hw": "None", + "xspi_data_1_mode": "Input", + "xspi_data_1_pull": "None", + "xspi_data_1_output_strength": "High", + "xspi_data_1_initial_output_state": "High", + "xspi_data_1_interrupt_trigger": "Low", + "xspi_data_1_dont_conf": 0, + "xspi_data_2": 22, + "xspi_data_2_use_hw": "None", + "xspi_data_2_mode": "Input", + "xspi_data_2_pull": "None", + "xspi_data_2_output_strength": "High", + "xspi_data_2_initial_output_state": "High", + "xspi_data_2_interrupt_trigger": "Low", + "xspi_data_2_dont_conf": 0, + "xspi_data_3": 23, + "xspi_data_3_use_hw": "None", + "xspi_data_3_mode": "Input", + "xspi_data_3_pull": "None", + "xspi_data_3_output_strength": "High", + "xspi_data_3_initial_output_state": "High", + "xspi_data_3_interrupt_trigger": "Low", + "xspi_data_3_dont_conf": 0, + "xspi_data_4": 26, + "xspi_data_4_use_hw": "None", + "xspi_data_4_mode": "Input", + "xspi_data_4_pull": "None", + "xspi_data_4_output_strength": "High", + "xspi_data_4_initial_output_state": "High", + "xspi_data_4_interrupt_trigger": "None", + "xspi_data_4_dont_conf": 0, + "xspi_data_5": 27, + "xspi_data_5_use_hw": "None", + "xspi_data_5_mode": "Input", + "xspi_data_5_pull": "None", + "xspi_data_5_output_strength": "High", + "xspi_data_5_initial_output_state": "High", + "xspi_data_5_interrupt_trigger": "None", + "xspi_data_5_dont_conf": 0, + "xspi_data_6": 28, + "xspi_data_6_use_hw": "None", + "xspi_data_6_mode": "Input", + "xspi_data_6_pull": "None", + "xspi_data_6_output_strength": "High", + "xspi_data_6_initial_output_state": "High", + "xspi_data_6_interrupt_trigger": "None", + "xspi_data_6_dont_conf": 0, + "xspi_data_7": 29, + "xspi_data_7_use_hw": "None", + "xspi_data_7_mode": "Input", + "xspi_data_7_pull": "None", + "xspi_data_7_output_strength": "High", + "xspi_data_7_initial_output_state": "High", + "xspi_data_7_interrupt_trigger": "None", + "xspi_data_7_dont_conf": 0, + "xspi_reset_flash": 36, + "xspi_reset_flash_use_hw": "None", + "xspi_reset_flash_mode": "Output", + "xspi_reset_flash_pull": "None", + "xspi_reset_flash_output_strength": "High", + "xspi_reset_flash_initial_output_state": "High", + "xspi_reset_flash_interrupt_trigger": "None", + "xspi_reset_flash_dont_conf": 0, + "xspi_cs_ram": 3, + "xspi_cs_ram_use_hw": "None", + "xspi_cs_ram_mode": "Output", + "xspi_cs_ram_pull": "None", + "xspi_cs_ram_output_strength": "High", + "xspi_cs_ram_initial_output_state": "High", + "xspi_cs_ram_interrupt_trigger": "None", + "xspi_cs_ram_dont_conf": 0, + "xspi_dqs": 30, + "xspi_dqs_use_hw": "None", + "xspi_dqs_mode": "Input", + "xspi_dqs_pull": "None", + "xspi_dqs_output_strength": "High", + "xspi_dqs_initial_output_state": "High", + "xspi_dqs_interrupt_trigger": "None", + "xspi_dqs_dont_conf": 0, + "xspi_reset_ram": 2, + "xspi_reset_ram_use_hw": "None", + "xspi_reset_ram_mode": "Input", + "xspi_reset_ram_pull": "None", + "xspi_reset_ram_output_strength": "High", + "xspi_reset_ram_initial_output_state": "High", + "xspi_reset_ram_interrupt_trigger": "None", + "xspi_reset_ram_dont_conf": 0 + }, + "xspi_operations": { + "xspi_operations_clocks": { + "clock_phase": 0, + "clock_polarity": 0, + "spi_mode": "2'b00" + }, + "xspi_operations_chip_select": { + "csda": 2, + "csdads": 0, + "cseot": 4, + "cssot": 1 + }, + "xspi_operations_reset": { + "flash_jedec_reset": 0, + "ram_jedec_reset": 0, + "flash_treset": 20, + "ram_treset": 20 + }, + "xspi_phy_operations": { + "flash_rx_dll_bypass_bit": 0, + "flash_dll_tx_delay": 42, + "flash_dll_rx_delay": 62, + "ram_rx_dll_bypass_bit": 0, + "ram_dll_tx_delay": 42, + "ram_dll_rx_delay": 62 + }, + "xspi_read_operations": { + "flash_dummy_rd_cycles": 4, + "flash_read_opcode": 11, + "suppl_flash_read_opcode": 0, + "ram_dummy_rd_cycles": 4, + "ram_read_opcode": 11, + "suppl_ram_read_opcode": 0, + "flash_non_cont_read_enable": 0, + "flash_max_read_jobs": 256, + "ram_non_cont_read_enable": 0, + "ram_max_read_jobs": 256, + "rww_en": 0, + "device_size": 4, + "number_of_banks": 1, + "bank_size": 4, + "mode_bit_enable": 0 + }, + "xspi_write_operations": { + "flash_address_and_data": { + "flash_dummy_wr_cycles": 0 + }, + "flash_command": { + "flash_write_opcode": 2, + "suppl_flash_write_opcode": 0 + }, + "ram_address_and_data": { + "ram_dummy_wr_cycles": 0 + }, + "ram_command": { + "ram_write_opcode": 2, + "suppl_ram_write_opcode": 0 + }, + "write_to_buffer": { + "flash_write_to_buffer_support": 0, + "ram_write_to_buffer_support": 0 + }, + "non_continuous_write": { + "flash_non_cont_write_enable": 0, + "flash_max_write_jobs": 64, + "ram_non_cont_write_enable": 0, + "ram_max_write_jobs": 0 + }, + "flash_program_operation": { + "flash_min_program_size": "256 B", + "flash_program_opcode": 2, + "suppl_flash_program_opcode": 0, + "flash_maximum_program_time_limit": 1600 + }, + "flash_erase_operation": { + "flash_min_erase_size": "4 kB", + "flash_erase_opcode": 32, + "suppl_flash_erase_opcode": 0, + "flash_maximum_erase_time_limit": 4095 + }, + "flash_erase_conf": { + "flash_block_erase_opcode": 0, + "suppl_block_flash_erase_opcode": 0, + "flash_sector_erase_opcode": 0, + "suppl_sector_flash_erase_opcode": 0, + "flash_chip_erase_opcode": 0, + "suppl_chip_flash_erase_opcode": 0 + }, + "ram_program_operation": { + "ram_min_program_size": "256 B", + "ram_program_opcode": 2, + "suppl_ram_program_opcode": 0, + "ram_maximum_program_time_limit": 1600 + }, + "ram_erase_conf": { + "ram_block_erase_opcode": 0, + "suppl_block_ram_erase_opcode": 0, + "ram_sector_erase_opcode": 0, + "suppl_sector_ram_erase_opcode": 0, + "ram_chip_erase_opcode": 0, + "suppl_chip_ram_erase_opcode": 0 + }, + "flash_buffer_support": { + "flash_pre_write_sequence": 0, + "flash_post_write_sequence": 0, + "flash_write_protection_timer_en": 0, + "flash_write_buffer_timer_mode": 16, + "flash_write_buffer_timer_range": 0, + "flash_service_interrupt_criteria": 0 + }, + "ram_buffer_support": { + "ram_pre_write_sequence": 0, + "ram_post_write_sequence": 0, + "ram_write_protection_timer_en": 0, + "ram_write_buffer_timer_mode": 16, + "ram_write_buffer_timer_range": 0, + "ram_service_interrupt_criteria": 0 + }, + "flash_pre_write_conf": { + "flash_pre_write_job_done_grant_sel": 0, + "data_for_flash_pre_write_conf_0": 0, + "offset_bits_for_flash_pre_write_conf_0": 0, + "stop_bit_for_flash_pre_write_conf_0": 1, + "data_for_flash_pre_write_conf_1": 0, + "offset_bits_for_flash_pre_write_conf_1": 0 + }, + "flash_post_write_conf": { + "flash_post_write_job_done_grant_sel": 0, + "data_for_flash_post_write_conf_0": 0, + "offset_bits_for_flash_post_write_conf_0": 0, + "stop_bit_for_flash_post_write_conf_0": 1, + "data_for_flash_post_write_conf_1": 0, + "offset_bits_for_flash_post_write_conf_1": 0 + }, + "ram_pre_write_conf": { + "ram_pre_write_job_done_grant_sel": 0, + "data_for_ram_pre_write_conf_0": 0, + "offset_bits_for_ram_pre_write_conf_0": 0, + "stop_bit_for_ram_pre_write_conf_0": 1, + "data_for_ram_pre_write_conf_1": 0, + "offset_bits_for_ram_pre_write_conf_1": 0 + }, + "ram_post_write_conf": { + "ram_post_write_job_done_grant_sel": 0, + "data_for_ram_post_write_conf_0": 0, + "offset_bits_for_ram_post_write_conf_0": 0, + "stop_bit_for_ram_post_write_conf_0": 1, + "data_for_ram_post_write_conf_1": 0, + "offset_bits_for_ram_post_write_conf_1": 0 + } + }, + "xspi_capture_operations": { + "read_data_capture": { + "flash_delay_transmitted_data": 0, + "flash_loopback_clock": 0, + "flash_bypass_adapted_loopback": 1, + "flash_sample_edge_sel": 0, + "ram_delay_transmitted_data": 0, + "ram_loopback_clock": 0, + "ram_bypass_adapted_loopback": 1, + "ram_sample_edge_sel": 0 + }, + "delays": { + "flash_full_half_cycle_delay": 0, + "flash_dll_bypass_mode": 1, + "flash_phase_detect_sel": 0, + "flash_dll_lock_num": 0, + "flash_dll_start_point": 0, + "flash_loopback_clock": 0, + "ram_full_half_cycle_delay": 0, + "ram_dll_bypass_mode": 1, + "ram_phase_detect_sel": 0, + "ram_dll_lock_num": 0, + "ram_dll_start_point": 0, + "ram_loopback_clock": 0 + }, + "operation_modes": { + "flash_sfdp_support": 0, + "ram_sfdp_support": 0, + "flash_pm_support": 0, + "ram_pm_support": 0, + "flash_sfdp_opcode": 0, + "suppl_flash_sfdp_opcode": 0, + "ram_sfdp_opcode": 0, + "suppl_ram_sfdp_opcode": 0, + "flash_enter_dpd_opcode": 185, + "suppl_flash_enter_dpd_opcode": 0, + "flash_exit_dpd_opcode": 171, + "suppl_flash_exit_dpd_opcode": 0, + "ram_enter_dpd_opcode": 185, + "suppl_ram_enter_dpd_opcode": 0, + "ram_exit_dpd_opcode": 171, + "suppl_ram_exit_dpd_opcode": 0, + "flash_quad_enable_opcode": 53, + "suppl_flash_quad_enable_opcode": 0, + "flash_quad_disable_opcode": 245, + "suppl_flash_quad_disable_opcode": 0, + "flash_octal_enable_opcode": 0, + "suppl_flash_octal_enable_opcode": 0, + "flash_octal_disable_opcode": 0, + "suppl_flash_octal_disable_opcode": 0, + "ram_quad_enable_opcode": 53, + "suppl_ram_quad_enable_opcode": 0, + "ram_quad_disable_opcode": 245, + "suppl_ram_quad_disable_opcode": 0, + "ram_octal_enable_opcode": 0, + "suppl_ram_octal_enable_opcode": 0, + "ram_octal_disable_opcode": 0, + "suppl_ram_octal_disable_opcode": 0 + } + } + }, + "external_memory_reporting": { + "header": { + "flash_auto_polling_enable": 1, + "flash_wel_enable": 1, + "flash_write_protect_enable": 0, + "flash_alternate_polling_conf_enable": 0, + "ram_auto_polling_enable": 1, + "ram_wel_enable": 1, + "ram_write_protect_enable": 0, + "ram_alternate_polling_conf_enable": 0 + }, + "flash_auto_polling": { + "flash_polling_repetition_delay": 0, + "flash_polling_count": 4, + "flash_enable_polling_expiration": 0, + "flash_polling_polarity": 0, + "flash_polling_address_phase_enable": 0, + "flash_polling_bit_index": 0, + "flash_numbers_poll_cycles": 65535, + "flash_dummy_autopoll_cycles": 0 + }, + "ram_auto_polling": { + "ram_polling_repetition_delay": 0, + "ram_polling_count": 4, + "ram_enable_polling_expiration": 0, + "ram_polling_polarity": 0, + "ram_polling_address_phase_enable": 0, + "ram_polling_bit_index": 0, + "ram_numbers_poll_cycles": 65535, + "ram_dummy_autopoll_cycles": 0 + }, + "flash_polling_command": { + "flash_polling_opcode": 5, + "suppl_flash_polling_opcode": 0 + }, + "ram_polling_command": { + "ram_polling_opcode": 5, + "suppl_ram_polling_opcode": 0 + }, + "flash_alternate_polling": { + "flash_polling_resp_count": 1023, + "flash_polling_iterations": 1, + "flash_polling_enabled": 0, + "flash_polling_disabled": 0, + "flash_grant_sel": 0, + "flash_data_for_enable_poling_conf_0": 0, + "flash_offset_bits_for_enable_poling_conf_0": 0, + "flash_stop_bit_for_enable_poling_conf_0": 1, + "flash_data_for_enable_poling_conf_1": 0, + "flash_offset_bits_for_enable_poling_conf_1": 0, + "flash_stop_bit_for_enable_poling_conf_1": 1, + "flash_data_for_disable_poling_conf_0": 0, + "flash_offset_bits_for_disable_poling_conf_0": 0, + "flash_stop_bit_for_disable_poling_conf_0": 1, + "flash_data_for_disable_poling_conf_1": 0, + "flash_offset_bits_for_disable_poling_conf_1": 0, + "flash_stop_bit_for_disable_poling_conf_1": 1 + }, + "ram_alternate_polling": { + "ram_polling_resp_count": 1023, + "ram_polling_iterations": 1, + "ram_polling_enabled": 0, + "ram_polling_disabled": 0, + "ram_grant_sel": 0, + "ram_data_for_enable_poling_conf_0": 0, + "ram_offset_bits_for_enable_poling_conf_0": 0, + "ram_stop_bit_for_enable_poling_conf_0": 1, + "ram_data_for_enable_poling_conf_1": 0, + "ram_offset_bits_for_enable_poling_conf_1": 0, + "ram_stop_bit_for_enable_poling_conf_1": 1, + "ram_data_for_disable_poling_conf_0": 0, + "ram_offset_bits_for_disable_poling_conf_0": 0, + "ram_stop_bit_for_disable_poling_conf_0": 1, + "ram_data_for_disable_poling_conf_1": 0, + "ram_offset_bits_for_disable_poling_conf_1": 0, + "ram_stop_bit_for_disable_poling_conf_1": 1 + }, + "flash_wel_command": { + "flash_wel_opcode": 6, + "suppl_flash_wel_opcode": 0 + }, + "ram_wel_command": { + "ram_wel_opcode": 6, + "suppl_ram_wel_opcode": 0 + } + }, + "event": { + "host_nvic_irq": 0, + "core_10_mux_sel": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/mx25u6435f/flash_disc_param_ext_mem.json b/boards/ti/lp_em_cc35x1/config/flash/mx25u6435f/flash_disc_param_ext_mem.json new file mode 100644 index 000000000000..6585853ccd5e --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/mx25u6435f/flash_disc_param_ext_mem.json @@ -0,0 +1,99 @@ +{ + "vendor_primary_sbl": true, + "ti_wsoc_primary_container": true, + "ti_wsoc_bl2_primary_container": true, + "nvs_enable": true, + "vendor_alternate_image": true, + "vendor_sbl_alternate_image": true, + "ti_bl_alternate_image": true, + "ti_wsoc_alternate_image": true, + "ti_wsoc_bl2_alternate_image": true, + "region_0": { + "mem_region_0_start_phy_address": 2867200, + "mem_region_0_end_phy_address": 5627903, + "region0_boot": false, + "region0_main_code": true, + "region0_nvs": false, + "region0_wsoc_code": false, + "region0_alternate_code": false + }, + "region_1": { + "mem_region_1_start_phy_address": 0, + "mem_region_1_end_phy_address": 2867199, + "region1_boot": true, + "region1_main_code": false, + "region1_nvs": true, + "region1_wsoc_code": true, + "region1_alternate_code": false + }, + "region_2": { + "mem_region_2_start_phy_address": 5627904, + "mem_region_2_end_phy_address": 8388607, + "region2_boot": false, + "region2_main_code": false, + "region2_nvs": false, + "region2_wsoc_code": false, + "region2_alternate_code": true + }, + "region_3": { + "mem_region_3_start_phy_address": 0, + "mem_region_3_end_phy_address": 0, + "region3_boot": false, + "region3_main_code": false, + "region3_nvs": false, + "region3_wsoc_code": false, + "region3_alternate_code": false + }, + "boot_region_conf": { + "boot_region_size": 0, + "boot_region_flash_disco_param_start_address": 0, + "boot_region_primary_ti_bl_start_phy_address": 12284, + "boot_region_primary_ti_bl_magic": 0, + "boot_region_primary_ti_bl_major": 0, + "boot_region_primary_ti_bl_minor": 0, + "boot_region_sec_ti_bl_start_phy_address": 430076, + "boot_region_sec_ti_bl_magic": 0, + "boot_region_sec_ti_bl_major": 0, + "boot_region_sec_ti_bl_minor": 0 + }, + "main_code_region_conf": { + "main_code_region_vendor_image_start_phy_address": 2871292, + "main_code_region_vendor_image_magic": 0, + "main_code_region_vendor_image_major": 0, + "main_code_region_vendor_image_minor": 0, + "main_code_region_sbl_start_phy_address": 0, + "main_code_region_sbl_magic": 0, + "main_code_region_sbl_major": 0, + "main_code_region_sbl_minor": 0 + }, + "alt_code_region_conf": { + "alt_code_region_vendor_image_start_phy_address": 5631996, + "alt_code_region_vendor_image_magic": 0, + "alt_code_region_vendor_image_major": 0, + "alt_code_region_vendor_image_minor": 0, + "alt_code_region_sbl_start_phy_address": 0, + "alt_code_region_sbl_magic": 0, + "alt_code_region_sbl_major": 0, + "alt_code_region_sbl_minor": 0 + }, + "nvs_code_region_conf": { + "nvs_start_phy_address": 1777664, + "nvs_region_size": 1089536, + "nvs_region_primary_wsoc_start_phy_address": 847868, + "nvs_region_primary_wsoc_magic": 0, + "nvs_region_primary_wsoc_major": 0, + "nvs_region_primary_wsoc_minor": 0, + "nvs_region_sec_wsoc_start_phy_address": 1314812, + "nvs_region_sec_wsoc_magic": 0, + "nvs_region_sec_wsoc_major": 0, + "nvs_region_sec_wsoc_minor": 0, + "nvs_region_primary_wsoc_bl2_start_phy_address": 0, + "nvs_region_primary_wsoc_bl2_magic": 0, + "nvs_region_primary_wsoc_bl2_major": 0, + "nvs_region_primary_wsoc_bl2_minor": 0, + "nvs_region_sec_wsoc_bl2_start_phy_address": 0, + "nvs_region_sec_wsoc_bl2_magic": 0, + "nvs_region_sec_wsoc_bl2_major": 0, + "nvs_region_sec_wsoc_bl2_minor": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/mx25u6435f/flash_disc_param_otfde.json b/boards/ti/lp_em_cc35x1/config/flash/mx25u6435f/flash_disc_param_otfde.json new file mode 100644 index 000000000000..40d31f025e3c --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/mx25u6435f/flash_disc_param_otfde.json @@ -0,0 +1,286 @@ +{ + "otfde_header": { + "name": "OTFDEWFF3", + "flash_only": true, + "ip_protection": false, + "regions_lock": false, + "regions_number": 4, + "flash_enabled": true + }, + "bl_conf": { + "host_boot_done_lock": true, + "host_peripherals_lock": true, + "icache_conf_lock": true, + "m33_mem_part_lock": true, + "memss_firewall_lock": true, + "dma_channel_owner_lock": true, + "otfde_region_lock": true, + "core_events_lock": true + }, + "otfde_general": { + "parameters": { + "mem_otfde_initial_delay": 10, + "otfde_global_watchdog_timer": 5 + }, + "events": { + "reset_evt_mask": false, + "reset_evt_suspend": false, + "sft_reset_evt_mask": false, + "sft_reset_evt_suspend": false, + "bypass_mode_evt_mask": false, + "bypass_mode_evt_suspend": false, + "debug_mode_evt_mask": false, + "debug_mode_evt_suspend": false, + "general_evt_mask": false, + "general_evt_suspend": false, + "xspi_data_path_evt_mask": false, + "xspi_data_path_evt_suspend": false, + "xspi_cnfg_path_evt_mask": false, + "xspi_cnfg_path_evt_suspend": false, + "xspi_service_interrupt_evt_mask": false, + "xspi_service_interrupt_evt_suspend": false, + "trans_device_disabled_evt_mask": false, + "trans_device_disabled_evt_suspend": false, + "trans_region_disabled_evt_mask": false, + "trans_region_disabled_evt_suspend": false, + "trans_region_params_conf_evt_mask": false, + "trans_region_params_conf_evt_suspend": false, + "trans_multiple_regions_mapped_evt_mask": false, + "trans_multiple_regions_mapped_evt_suspend": false, + "trans_address_not_32_bit_evt_mask": false, + "trans_address_not_32_bit_evt_suspend": false, + "trans_size_not_32_bit_evt_mask": false, + "trans_size_not_32_bit_evt_suspend": false, + "trans_burst_not_32_bit_evt_mask": false, + "trans_burst_not_32_bit_evt_suspend": false, + "region_read_write_def_evt_mask": false, + "region_read_write_def_evt_suspend": false, + "suspend_while_disabled_evt_mask": false, + "suspend_while_disabled_evt_suspend": false + } + }, + "regions_settings": { + "region_parameters_lock": { + "REGION_0_PARAMS_0": true, + "REGION_0_PARAMS_1": true, + "REGION_0_PARAMS_2": true, + "REGION_1_PARAMS_0": false, + "REGION_1_PARAMS_1": false, + "REGION_1_PARAMS_2": false, + "REGION_2_PARAMS_0": true, + "REGION_2_PARAMS_1": true, + "REGION_2_PARAMS_2": true, + "REGION_3_PARAMS_0": false, + "REGION_3_PARAMS_1": false, + "REGION_3_PARAMS_2": false + }, + "region_0_protection": { + "mem_region_0_enabled": true, + "mem_region_0_device_id": 0, + "mem_region_0_spi_write_enable": true, + "mem_region_0_spi_read_enable": true, + "mem_region_0_physical_offset": 700, + "mem_region_0_security_id_msb": 0, + "mem_region_0_start_address": 81920, + "mem_region_0_end_address": 82593, + "mem_region_0_security_id_lsb": 0, + "mem_otfde_region_0_write_lock_en": false, + "mem_otfde_region_0_enc_dec_bypass": "Bypass" + }, + "region_1_protection": { + "mem_region_1_enabled": true, + "mem_region_1_device_id": 0, + "mem_region_1_spi_write_enable": true, + "mem_region_1_spi_read_enable": true, + "mem_region_1_physical_offset": 0, + "mem_region_1_security_id_msb": 0, + "mem_region_1_start_address": 655360, + "mem_region_1_end_address": 656059, + "mem_region_1_security_id_lsb": 0, + "mem_otfde_region_1_write_lock_en": false, + "mem_otfde_region_1_enc_dec_bypass": "Bypass" + }, + "region_2_protection": { + "mem_region_2_enabled": true, + "mem_region_2_device_id": 0, + "mem_region_2_spi_write_enable": true, + "mem_region_2_spi_read_enable": true, + "mem_region_2_physical_offset": 1374, + "mem_region_2_security_id_msb": 0, + "mem_region_2_start_address": 671744, + "mem_region_2_end_address": 672417, + "mem_region_2_security_id_lsb": 0, + "mem_otfde_region_2_write_lock_en": false, + "mem_otfde_region_2_enc_dec_bypass": "Bypass" + }, + "region_3_protection": { + "mem_region_3_enabled": false, + "mem_region_3_device_id": 1, + "mem_region_3_spi_write_enable": true, + "mem_region_3_spi_read_enable": true, + "mem_region_3_physical_offset": 0, + "mem_region_3_security_id_msb": 0, + "mem_region_3_start_address": 1, + "mem_region_3_end_address": 0, + "mem_region_3_security_id_lsb": 0, + "mem_otfde_region_3_write_lock_en": false, + "mem_otfde_region_3_enc_dec_bypass": "Bypass" + } + }, + "devices": { + "header": { + "flash_device_switch_conf": 1, + "ram_device_switch_conf": 1 + }, + "flash_switch": { + "flash_grant_sel": 0, + "flash_data_for_conf_0": 2181562505, + "flash_offset_bits_for_conf_0": 0, + "flash_stop_bit_for_conf_0": 0, + "flash_data_for_conf_1": 67248651, + "flash_offset_bits_for_conf_1": 1, + "flash_stop_bit_for_conf_1": 0, + "flash_data_for_conf_2": 139266, + "flash_offset_bits_for_conf_2": 2, + "flash_stop_bit_for_conf_2": 0, + "flash_data_for_conf_3": 1, + "flash_offset_bits_for_conf_3": 4, + "flash_stop_bit_for_conf_3": 0, + "flash_data_for_conf_4": 1076887634, + "flash_offset_bits_for_conf_4": 45, + "flash_stop_bit_for_conf_4": 0, + "flash_data_for_conf_5": 3224371282, + "flash_offset_bits_for_conf_5": 45, + "flash_stop_bit_for_conf_5": 0, + "flash_data_for_conf_6": 262149, + "flash_offset_bits_for_conf_6": 14, + "flash_stop_bit_for_conf_6": 0, + "flash_data_for_conf_7": 0, + "flash_offset_bits_for_conf_7": 44, + "flash_stop_bit_for_conf_7": 1, + "flash_data_for_conf_8": 0, + "flash_offset_bits_for_conf_8": 0, + "flash_stop_bit_for_conf_8": 1, + "flash_data_for_conf_9": 0, + "flash_offset_bits_for_conf_9": 0, + "flash_stop_bit_for_conf_9": 1, + "flash_data_for_conf_10": 0, + "flash_offset_bits_for_conf_10": 0, + "flash_stop_bit_for_conf_10": 1, + "flash_data_for_conf_11": 0, + "flash_offset_bits_for_conf_11": 0, + "flash_stop_bit_for_conf_11": 1, + "flash_data_for_conf_12": 0, + "flash_offset_bits_for_conf_12": 0, + "flash_stop_bit_for_conf_12": 1, + "flash_data_for_conf_13": 0, + "flash_offset_bits_for_conf_13": 0, + "flash_stop_bit_for_conf_13": 1, + "flash_data_for_conf_14": 0, + "flash_offset_bits_for_conf_14": 0, + "flash_stop_bit_for_conf_14": 1, + "flash_data_for_conf_15": 0, + "flash_offset_bits_for_conf_15": 0, + "flash_stop_bit_for_conf_15": 1, + "flash_data_for_conf_16": 0, + "flash_offset_bits_for_conf_16": 0, + "flash_stop_bit_for_conf_16": 1, + "flash_data_for_conf_17": 0, + "flash_offset_bits_for_conf_17": 0, + "flash_stop_bit_for_conf_17": 1, + "flash_data_for_conf_18": 0, + "flash_offset_bits_for_conf_18": 0, + "flash_stop_bit_for_conf_18": 1, + "flash_data_for_conf_19": 0, + "flash_offset_bits_for_conf_19": 0, + "flash_stop_bit_for_conf_19": 1, + "flash_data_for_conf_20": 0, + "flash_offset_bits_for_conf_20": 0, + "flash_stop_bit_for_conf_20": 1, + "flash_data_for_conf_21": 0, + "flash_offset_bits_for_conf_21": 0, + "flash_stop_bit_for_conf_21": 1, + "flash_data_for_conf_22": 0, + "flash_offset_bits_for_conf_22": 0, + "flash_stop_bit_for_conf_22": 1, + "flash_data_for_conf_23": 0, + "flash_offset_bits_for_conf_23": 0, + "flash_stop_bit_for_conf_23": 1 + }, + "ram_switch": { + "ram_grant_sel": 0, + "ram_data_for_conf_0": 2181562505, + "ram_offset_bits_for_conf_0": 0, + "ram_stop_bit_for_conf_0": 0, + "ram_data_for_conf_1": 67248651, + "ram_offset_bits_for_conf_1": 1, + "ram_stop_bit_for_conf_1": 0, + "ram_data_for_conf_2": 139266, + "ram_offset_bits_for_conf_2": 2, + "ram_stop_bit_for_conf_2": 0, + "ram_data_for_conf_3": 1, + "ram_offset_bits_for_conf_3": 4, + "ram_stop_bit_for_conf_3": 0, + "ram_data_for_conf_4": 1076887634, + "ram_offset_bits_for_conf_4": 45, + "ram_stop_bit_for_conf_4": 0, + "ram_data_for_conf_5": 3224371282, + "ram_offset_bits_for_conf_5": 45, + "ram_stop_bit_for_conf_5": 0, + "ram_data_for_conf_6": 262149, + "ram_offset_bits_for_conf_6": 14, + "ram_stop_bit_for_conf_6": 0, + "ram_data_for_conf_7": 0, + "ram_offset_bits_for_conf_7": 44, + "ram_stop_bit_for_conf_7": 1, + "ram_data_for_conf_8": 0, + "ram_offset_bits_for_conf_8": 0, + "ram_stop_bit_for_conf_8": 1, + "ram_data_for_conf_9": 0, + "ram_offset_bits_for_conf_9": 0, + "ram_stop_bit_for_conf_9": 1, + "ram_data_for_conf_10": 0, + "ram_offset_bits_for_conf_10": 0, + "ram_stop_bit_for_conf_10": 1, + "ram_data_for_conf_11": 0, + "ram_offset_bits_for_conf_11": 0, + "ram_stop_bit_for_conf_11": 1, + "ram_data_for_conf_12": 0, + "ram_offset_bits_for_conf_12": 0, + "ram_stop_bit_for_conf_12": 1, + "ram_data_for_conf_13": 0, + "ram_offset_bits_for_conf_13": 0, + "ram_stop_bit_for_conf_13": 1, + "ram_data_for_conf_14": 0, + "ram_offset_bits_for_conf_14": 0, + "ram_stop_bit_for_conf_14": 1, + "ram_data_for_conf_15": 0, + "ram_offset_bits_for_conf_15": 0, + "ram_stop_bit_for_conf_15": 1, + "ram_data_for_conf_16": 0, + "ram_offset_bits_for_conf_16": 0, + "ram_stop_bit_for_conf_16": 1, + "ram_data_for_conf_17": 0, + "ram_offset_bits_for_conf_17": 0, + "ram_stop_bit_for_conf_17": 1, + "ram_data_for_conf_18": 0, + "ram_offset_bits_for_conf_18": 0, + "ram_stop_bit_for_conf_18": 1, + "ram_data_for_conf_19": 0, + "ram_offset_bits_for_conf_19": 0, + "ram_stop_bit_for_conf_19": 1, + "ram_data_for_conf_20": 0, + "ram_offset_bits_for_conf_20": 0, + "ram_stop_bit_for_conf_20": 1, + "ram_data_for_conf_21": 0, + "ram_offset_bits_for_conf_21": 0, + "ram_stop_bit_for_conf_21": 1, + "ram_data_for_conf_22": 0, + "ram_offset_bits_for_conf_22": 0, + "ram_stop_bit_for_conf_22": 1, + "ram_data_for_conf_23": 0, + "ram_offset_bits_for_conf_23": 0, + "ram_stop_bit_for_conf_23": 1 + } + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/mx25u6435f/flash_disc_param_xspi.json b/boards/ti/lp_em_cc35x1/config/flash/mx25u6435f/flash_disc_param_xspi.json new file mode 100644 index 000000000000..6d30f5b1665e --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/mx25u6435f/flash_disc_param_xspi.json @@ -0,0 +1,485 @@ +{ + "xspi_header": { + "name": "xSPIWFF3", + "device": "CC3500", + "use_hardware": "MX25U6435F", + "use_case": "Quadro", + "dqs_support": 0, + "flash_only": 1, + "flash_separate_reset": 0, + "ram_separate_reset": true, + "clock_frequency": 80, + "qospi_clock_divider": 1, + "flash_device_character_conf": 0, + "ram_device_character_conf": 0, + "header_advanced": 0, + "phy_mode_enable": 1, + "pipeline_mode_enable": 1, + "loopback_support": "No", + "qspi_ref_clock": 80, + "spi_clock_freq": 20, + "spi_clock_divider": 1, + "flash_device_size": 8, + "flash_bytes_per_block": 16, + "flash_bytes_per_page": 256, + "flash_number_of_address_bytes": 3, + "flash_dual_opcode": 0, + "flash_jedec_manufacturer_id": 0, + "flash_jedec_device_id": 0, + "flash_name": "MX25U6435F", + "flash_page_size": 256, + "flash_sector_size": 4096, + "flash_cs_polarity": "ACTIVE_LOW", + "flash_sw_reset_type": "x1xxxx", + "ram_device_size": 8, + "ram_bytes_per_block": 16, + "ram_bytes_per_page": 256, + "ram_number_of_address_bytes": 3, + "ram_dual_opcode": 0, + "ram_jedec_manufacturer_id": 0, + "ram_jedec_device_id": 0, + "ram_name": "NO_PSRAM", + "ram_page_size": 256, + "ram_sector_size": 4096, + "ram_cs_polarity": "ACTIVE_LOW", + "ram_sw_reset_type": "x1xxxx", + "flash_write_operation_modes": "4S-4S-4S", + "flash_read_operation_modes": "4S-4S-4S", + "ram_write_operation_modes": "4S-4S-4S", + "ram_read_operation_modes": "4S-4S-4S", + "crc_enable": 0, + "enable_dtr": 0, + "enable_ahb_decoder": 0, + "enter_xip_mod_immediately": 0, + "enter_xip_mod_next_read": 0, + "ahb_address_remapping": 0, + "enable_dma": 0, + "select_decode": 0, + "legacy_ip_mode": 0, + "direct_access": 1 + }, + "xspi_pinmux": { + "xspi_clk_input": 44, + "xspi_clk_input_use_hw": 0, + "xspi_clk_input_mode": "Input", + "xspi_clk_input_pull": "None", + "xspi_clk_input_interrupt_trigger": "Low", + "xspi_clk_input_dont_conf": 0, + "xspi_clk_input_output_strength": "High", + "xspi_clk_input_initial_output_state": "High", + "xspi_clk": 24, + "xspi_clk_use_hw": "None", + "xspi_clk_mode": "Output", + "xspi_clk_pull": "None", + "xspi_clk_output_strength": "High", + "xspi_clk_initial_output_state": "High", + "xspi_clk_interrupt_trigger": "None", + "xspi_clk_dont_conf": 0, + "xspi_flash_cs": 20, + "xspi_flash_cs_use_hw": "None", + "xspi_flash_cs_mode": "Output", + "xspi_flash_cs_pull": "None", + "xspi_flash_cs_output_strength": "High", + "xspi_flash_cs_initial_output_state": "High", + "xspi_flash_cs_interrupt_trigger": "None", + "xspi_flash_cs_dont_conf": 0, + "xspi_data_0": 25, + "xspi_data_0_use_hw": "None", + "xspi_data_0_mode": "Input", + "xspi_data_0_pull": "None", + "xspi_data_0_output_strength": "High", + "xspi_data_0_initial_output_state": "High", + "xspi_data_0_interrupt_trigger": "Low", + "xspi_data_0_dont_conf": 0, + "xspi_data_1": 21, + "xspi_data_1_use_hw": "None", + "xspi_data_1_mode": "Input", + "xspi_data_1_pull": "None", + "xspi_data_1_output_strength": "High", + "xspi_data_1_initial_output_state": "High", + "xspi_data_1_interrupt_trigger": "Low", + "xspi_data_1_dont_conf": 0, + "xspi_data_2": 22, + "xspi_data_2_use_hw": "None", + "xspi_data_2_mode": "Input", + "xspi_data_2_pull": "None", + "xspi_data_2_output_strength": "High", + "xspi_data_2_initial_output_state": "High", + "xspi_data_2_interrupt_trigger": "Low", + "xspi_data_2_dont_conf": 0, + "xspi_data_3": 23, + "xspi_data_3_use_hw": "None", + "xspi_data_3_mode": "Input", + "xspi_data_3_pull": "None", + "xspi_data_3_output_strength": "High", + "xspi_data_3_initial_output_state": "High", + "xspi_data_3_interrupt_trigger": "Low", + "xspi_data_3_dont_conf": 0, + "xspi_data_4": 26, + "xspi_data_4_use_hw": "None", + "xspi_data_4_mode": "Input", + "xspi_data_4_pull": "None", + "xspi_data_4_output_strength": "High", + "xspi_data_4_initial_output_state": "High", + "xspi_data_4_interrupt_trigger": "None", + "xspi_data_4_dont_conf": 0, + "xspi_data_5": 27, + "xspi_data_5_use_hw": "None", + "xspi_data_5_mode": "Input", + "xspi_data_5_pull": "None", + "xspi_data_5_output_strength": "High", + "xspi_data_5_initial_output_state": "High", + "xspi_data_5_interrupt_trigger": "None", + "xspi_data_5_dont_conf": 0, + "xspi_data_6": 28, + "xspi_data_6_use_hw": "None", + "xspi_data_6_mode": "Input", + "xspi_data_6_pull": "None", + "xspi_data_6_output_strength": "High", + "xspi_data_6_initial_output_state": "High", + "xspi_data_6_interrupt_trigger": "None", + "xspi_data_6_dont_conf": 0, + "xspi_data_7": 29, + "xspi_data_7_use_hw": "None", + "xspi_data_7_mode": "Input", + "xspi_data_7_pull": "None", + "xspi_data_7_output_strength": "High", + "xspi_data_7_initial_output_state": "High", + "xspi_data_7_interrupt_trigger": "None", + "xspi_data_7_dont_conf": 0, + "xspi_reset_flash": 36, + "xspi_reset_flash_use_hw": "None", + "xspi_reset_flash_mode": "Output", + "xspi_reset_flash_pull": "None", + "xspi_reset_flash_output_strength": "High", + "xspi_reset_flash_initial_output_state": "High", + "xspi_reset_flash_interrupt_trigger": "None", + "xspi_reset_flash_dont_conf": 0, + "xspi_cs_ram": 3, + "xspi_cs_ram_use_hw": "None", + "xspi_cs_ram_mode": "Output", + "xspi_cs_ram_pull": "None", + "xspi_cs_ram_output_strength": "High", + "xspi_cs_ram_initial_output_state": "High", + "xspi_cs_ram_interrupt_trigger": "None", + "xspi_cs_ram_dont_conf": 0, + "xspi_dqs": 30, + "xspi_dqs_use_hw": "None", + "xspi_dqs_mode": "Input", + "xspi_dqs_pull": "None", + "xspi_dqs_output_strength": "High", + "xspi_dqs_initial_output_state": "High", + "xspi_dqs_interrupt_trigger": "None", + "xspi_dqs_dont_conf": 0, + "xspi_reset_ram": 2, + "xspi_reset_ram_use_hw": "None", + "xspi_reset_ram_mode": "Input", + "xspi_reset_ram_pull": "None", + "xspi_reset_ram_output_strength": "High", + "xspi_reset_ram_initial_output_state": "High", + "xspi_reset_ram_interrupt_trigger": "None", + "xspi_reset_ram_dont_conf": 0 + }, + "xspi_operations": { + "xspi_operations_clocks": { + "clock_phase": 0, + "clock_polarity": 0, + "spi_mode": "2'b00" + }, + "xspi_operations_chip_select": { + "csda": 2, + "csdads": 0, + "cseot": 4, + "cssot": 1 + }, + "xspi_operations_reset": { + "flash_jedec_reset": 0, + "ram_jedec_reset": 0, + "flash_treset": 20, + "ram_treset": 20 + }, + "xspi_phy_operations": { + "flash_rx_dll_bypass_bit": 0, + "flash_dll_tx_delay": 42, + "flash_dll_rx_delay": 62, + "ram_rx_dll_bypass_bit": 0, + "ram_dll_tx_delay": 42, + "ram_dll_rx_delay": 62 + }, + "xspi_read_operations": { + "flash_dummy_rd_cycles": 4, + "flash_read_opcode": 11, + "suppl_flash_read_opcode": 0, + "ram_dummy_rd_cycles": 4, + "ram_read_opcode": 11, + "suppl_ram_read_opcode": 0, + "flash_non_cont_read_enable": 0, + "flash_max_read_jobs": 256, + "ram_non_cont_read_enable": 0, + "ram_max_read_jobs": 256, + "rww_en": 0, + "device_size": 8, + "number_of_banks": 1, + "bank_size": 8, + "mode_bit_enable": 0 + }, + "xspi_write_operations": { + "flash_address_and_data": { + "flash_dummy_wr_cycles": 0 + }, + "flash_command": { + "flash_write_opcode": 2, + "suppl_flash_write_opcode": 0 + }, + "ram_address_and_data": { + "ram_dummy_wr_cycles": 0 + }, + "ram_command": { + "ram_write_opcode": 2, + "suppl_ram_write_opcode": 0 + }, + "write_to_buffer": { + "flash_write_to_buffer_support": 0, + "ram_write_to_buffer_support": 0 + }, + "non_continuous_write": { + "flash_non_cont_write_enable": 0, + "flash_max_write_jobs": 64, + "ram_non_cont_write_enable": 0, + "ram_max_write_jobs": 0 + }, + "flash_program_operation": { + "flash_min_program_size": "256 B", + "flash_program_opcode": 2, + "suppl_flash_program_opcode": 0, + "flash_maximum_program_time_limit": 1600 + }, + "flash_erase_operation": { + "flash_min_erase_size": "4 kB", + "flash_erase_opcode": 32, + "suppl_flash_erase_opcode": 0, + "flash_maximum_erase_time_limit": 4095 + }, + "flash_erase_conf": { + "flash_block_erase_opcode": 0, + "suppl_block_flash_erase_opcode": 0, + "flash_sector_erase_opcode": 0, + "suppl_sector_flash_erase_opcode": 0, + "flash_chip_erase_opcode": 0, + "suppl_chip_flash_erase_opcode": 0 + }, + "ram_program_operation": { + "ram_min_program_size": "256 B", + "ram_program_opcode": 2, + "suppl_ram_program_opcode": 0, + "ram_maximum_program_time_limit": 1600 + }, + "ram_erase_conf": { + "ram_block_erase_opcode": 0, + "suppl_block_ram_erase_opcode": 0, + "ram_sector_erase_opcode": 0, + "suppl_sector_ram_erase_opcode": 0, + "ram_chip_erase_opcode": 0, + "suppl_chip_ram_erase_opcode": 0 + }, + "flash_buffer_support": { + "flash_pre_write_sequence": 0, + "flash_post_write_sequence": 0, + "flash_write_protection_timer_en": 0, + "flash_write_buffer_timer_mode": 16, + "flash_write_buffer_timer_range": 0, + "flash_service_interrupt_criteria": 0 + }, + "ram_buffer_support": { + "ram_pre_write_sequence": 0, + "ram_post_write_sequence": 0, + "ram_write_protection_timer_en": 0, + "ram_write_buffer_timer_mode": 16, + "ram_write_buffer_timer_range": 0, + "ram_service_interrupt_criteria": 0 + }, + "flash_pre_write_conf": { + "flash_pre_write_job_done_grant_sel": 0, + "data_for_flash_pre_write_conf_0": 0, + "offset_bits_for_flash_pre_write_conf_0": 0, + "stop_bit_for_flash_pre_write_conf_0": 1, + "data_for_flash_pre_write_conf_1": 0, + "offset_bits_for_flash_pre_write_conf_1": 0 + }, + "flash_post_write_conf": { + "flash_post_write_job_done_grant_sel": 0, + "data_for_flash_post_write_conf_0": 0, + "offset_bits_for_flash_post_write_conf_0": 0, + "stop_bit_for_flash_post_write_conf_0": 1, + "data_for_flash_post_write_conf_1": 0, + "offset_bits_for_flash_post_write_conf_1": 0 + }, + "ram_pre_write_conf": { + "ram_pre_write_job_done_grant_sel": 0, + "data_for_ram_pre_write_conf_0": 0, + "offset_bits_for_ram_pre_write_conf_0": 0, + "stop_bit_for_ram_pre_write_conf_0": 1, + "data_for_ram_pre_write_conf_1": 0, + "offset_bits_for_ram_pre_write_conf_1": 0 + }, + "ram_post_write_conf": { + "ram_post_write_job_done_grant_sel": 0, + "data_for_ram_post_write_conf_0": 0, + "offset_bits_for_ram_post_write_conf_0": 0, + "stop_bit_for_ram_post_write_conf_0": 1, + "data_for_ram_post_write_conf_1": 0, + "offset_bits_for_ram_post_write_conf_1": 0 + } + }, + "xspi_capture_operations": { + "read_data_capture": { + "flash_delay_transmitted_data": 0, + "flash_loopback_clock": 0, + "flash_bypass_adapted_loopback": 1, + "flash_sample_edge_sel": 0, + "ram_delay_transmitted_data": 0, + "ram_loopback_clock": 0, + "ram_bypass_adapted_loopback": 1, + "ram_sample_edge_sel": 0 + }, + "delays": { + "flash_full_half_cycle_delay": 0, + "flash_dll_bypass_mode": 1, + "flash_phase_detect_sel": 0, + "flash_dll_lock_num": 0, + "flash_dll_start_point": 0, + "flash_loopback_clock": 0, + "ram_full_half_cycle_delay": 0, + "ram_dll_bypass_mode": 1, + "ram_phase_detect_sel": 0, + "ram_dll_lock_num": 0, + "ram_dll_start_point": 0, + "ram_loopback_clock": 0 + }, + "operation_modes": { + "flash_sfdp_support": 0, + "ram_sfdp_support": 0, + "flash_pm_support": 0, + "ram_pm_support": 0, + "flash_sfdp_opcode": 0, + "suppl_flash_sfdp_opcode": 0, + "ram_sfdp_opcode": 0, + "suppl_ram_sfdp_opcode": 0, + "flash_enter_dpd_opcode": 185, + "suppl_flash_enter_dpd_opcode": 0, + "flash_exit_dpd_opcode": 171, + "suppl_flash_exit_dpd_opcode": 0, + "ram_enter_dpd_opcode": 185, + "suppl_ram_enter_dpd_opcode": 0, + "ram_exit_dpd_opcode": 171, + "suppl_ram_exit_dpd_opcode": 0, + "flash_quad_enable_opcode": 53, + "suppl_flash_quad_enable_opcode": 0, + "flash_quad_disable_opcode": 245, + "suppl_flash_quad_disable_opcode": 0, + "flash_octal_enable_opcode": 0, + "suppl_flash_octal_enable_opcode": 0, + "flash_octal_disable_opcode": 0, + "suppl_flash_octal_disable_opcode": 0, + "ram_quad_enable_opcode": 53, + "suppl_ram_quad_enable_opcode": 0, + "ram_quad_disable_opcode": 245, + "suppl_ram_quad_disable_opcode": 0, + "ram_octal_enable_opcode": 0, + "suppl_ram_octal_enable_opcode": 0, + "ram_octal_disable_opcode": 0, + "suppl_ram_octal_disable_opcode": 0 + } + } + }, + "external_memory_reporting": { + "header": { + "flash_auto_polling_enable": 1, + "flash_wel_enable": 1, + "flash_write_protect_enable": 0, + "flash_alternate_polling_conf_enable": 0, + "ram_auto_polling_enable": 1, + "ram_wel_enable": 1, + "ram_write_protect_enable": 0, + "ram_alternate_polling_conf_enable": 0 + }, + "flash_auto_polling": { + "flash_polling_repetition_delay": 0, + "flash_polling_count": 4, + "flash_enable_polling_expiration": 0, + "flash_polling_polarity": 0, + "flash_polling_address_phase_enable": 0, + "flash_polling_bit_index": 0, + "flash_numbers_poll_cycles": 65535, + "flash_dummy_autopoll_cycles": 0 + }, + "ram_auto_polling": { + "ram_polling_repetition_delay": 0, + "ram_polling_count": 4, + "ram_enable_polling_expiration": 0, + "ram_polling_polarity": 0, + "ram_polling_address_phase_enable": 0, + "ram_polling_bit_index": 0, + "ram_numbers_poll_cycles": 65535, + "ram_dummy_autopoll_cycles": 0 + }, + "flash_polling_command": { + "flash_polling_opcode": 5, + "suppl_flash_polling_opcode": 0 + }, + "ram_polling_command": { + "ram_polling_opcode": 5, + "suppl_ram_polling_opcode": 0 + }, + "flash_alternate_polling": { + "flash_polling_resp_count": 1023, + "flash_polling_iterations": 1, + "flash_polling_enabled": 0, + "flash_polling_disabled": 0, + "flash_grant_sel": 0, + "flash_data_for_enable_poling_conf_0": 0, + "flash_offset_bits_for_enable_poling_conf_0": 0, + "flash_stop_bit_for_enable_poling_conf_0": 1, + "flash_data_for_enable_poling_conf_1": 0, + "flash_offset_bits_for_enable_poling_conf_1": 0, + "flash_stop_bit_for_enable_poling_conf_1": 1, + "flash_data_for_disable_poling_conf_0": 0, + "flash_offset_bits_for_disable_poling_conf_0": 0, + "flash_stop_bit_for_disable_poling_conf_0": 1, + "flash_data_for_disable_poling_conf_1": 0, + "flash_offset_bits_for_disable_poling_conf_1": 0, + "flash_stop_bit_for_disable_poling_conf_1": 1 + }, + "ram_alternate_polling": { + "ram_polling_resp_count": 1023, + "ram_polling_iterations": 1, + "ram_polling_enabled": 0, + "ram_polling_disabled": 0, + "ram_grant_sel": 0, + "ram_data_for_enable_poling_conf_0": 0, + "ram_offset_bits_for_enable_poling_conf_0": 0, + "ram_stop_bit_for_enable_poling_conf_0": 1, + "ram_data_for_enable_poling_conf_1": 0, + "ram_offset_bits_for_enable_poling_conf_1": 0, + "ram_stop_bit_for_enable_poling_conf_1": 1, + "ram_data_for_disable_poling_conf_0": 0, + "ram_offset_bits_for_disable_poling_conf_0": 0, + "ram_stop_bit_for_disable_poling_conf_0": 1, + "ram_data_for_disable_poling_conf_1": 0, + "ram_offset_bits_for_disable_poling_conf_1": 0, + "ram_stop_bit_for_disable_poling_conf_1": 1 + }, + "flash_wel_command": { + "flash_wel_opcode": 6, + "suppl_flash_wel_opcode": 0 + }, + "ram_wel_command": { + "ram_wel_opcode": 6, + "suppl_ram_wel_opcode": 0 + } + }, + "event": { + "host_nvic_irq": 0, + "core_10_mux_sel": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/py25q128la/flash_disc_param_ext_mem.json b/boards/ti/lp_em_cc35x1/config/flash/py25q128la/flash_disc_param_ext_mem.json new file mode 100644 index 000000000000..14d05d9aba5a --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/py25q128la/flash_disc_param_ext_mem.json @@ -0,0 +1,99 @@ +{ + "vendor_primary_sbl": true, + "ti_wsoc_primary_container": true, + "ti_wsoc_bl2_primary_container": true, + "nvs_enable": true, + "vendor_alternate_image": true, + "vendor_sbl_alternate_image": true, + "ti_bl_alternate_image": true, + "ti_wsoc_alternate_image": true, + "ti_wsoc_bl2_alternate_image": true, + "region_0": { + "mem_region_0_start_phy_address": 2867200, + "mem_region_0_end_phy_address": 9822207, + "region0_boot": false, + "region0_main_code": true, + "region0_nvs": false, + "region0_wsoc_code": false, + "region0_alternate_code": false + }, + "region_1": { + "mem_region_1_start_phy_address": 0, + "mem_region_1_end_phy_address": 2867199, + "region1_boot": true, + "region1_main_code": false, + "region1_nvs": true, + "region1_wsoc_code": true, + "region1_alternate_code": false + }, + "region_2": { + "mem_region_2_start_phy_address": 9822208, + "mem_region_2_end_phy_address": 16777215, + "region2_boot": false, + "region2_main_code": false, + "region2_nvs": false, + "region2_wsoc_code": false, + "region2_alternate_code": true + }, + "region_3": { + "mem_region_3_start_phy_address": 0, + "mem_region_3_end_phy_address": 0, + "region3_boot": false, + "region3_main_code": false, + "region3_nvs": false, + "region3_wsoc_code": false, + "region3_alternate_code": false + }, + "boot_region_conf": { + "boot_region_size": 0, + "boot_region_flash_disco_param_start_address": 0, + "boot_region_primary_ti_bl_start_phy_address": 12284, + "boot_region_primary_ti_bl_magic": 0, + "boot_region_primary_ti_bl_major": 0, + "boot_region_primary_ti_bl_minor": 0, + "boot_region_sec_ti_bl_start_phy_address": 430076, + "boot_region_sec_ti_bl_magic": 0, + "boot_region_sec_ti_bl_major": 0, + "boot_region_sec_ti_bl_minor": 0 + }, + "main_code_region_conf": { + "main_code_region_vendor_image_start_phy_address": 2871292, + "main_code_region_vendor_image_magic": 0, + "main_code_region_vendor_image_major": 0, + "main_code_region_vendor_image_minor": 0, + "main_code_region_sbl_start_phy_address": 0, + "main_code_region_sbl_magic": 0, + "main_code_region_sbl_major": 0, + "main_code_region_sbl_minor": 0 + }, + "alt_code_region_conf": { + "alt_code_region_vendor_image_start_phy_address": 9826300, + "alt_code_region_vendor_image_magic": 0, + "alt_code_region_vendor_image_major": 0, + "alt_code_region_vendor_image_minor": 0, + "alt_code_region_sbl_start_phy_address": 0, + "alt_code_region_sbl_magic": 0, + "alt_code_region_sbl_major": 0, + "alt_code_region_sbl_minor": 0 + }, + "nvs_code_region_conf": { + "nvs_start_phy_address": 1777664, + "nvs_region_size": 1089536, + "nvs_region_primary_wsoc_start_phy_address": 847868, + "nvs_region_primary_wsoc_magic": 0, + "nvs_region_primary_wsoc_major": 0, + "nvs_region_primary_wsoc_minor": 0, + "nvs_region_sec_wsoc_start_phy_address": 1314812, + "nvs_region_sec_wsoc_magic": 0, + "nvs_region_sec_wsoc_major": 0, + "nvs_region_sec_wsoc_minor": 0, + "nvs_region_primary_wsoc_bl2_start_phy_address": 0, + "nvs_region_primary_wsoc_bl2_magic": 0, + "nvs_region_primary_wsoc_bl2_major": 0, + "nvs_region_primary_wsoc_bl2_minor": 0, + "nvs_region_sec_wsoc_bl2_start_phy_address": 0, + "nvs_region_sec_wsoc_bl2_magic": 0, + "nvs_region_sec_wsoc_bl2_major": 0, + "nvs_region_sec_wsoc_bl2_minor": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/py25q128la/flash_disc_param_otfde.json b/boards/ti/lp_em_cc35x1/config/flash/py25q128la/flash_disc_param_otfde.json new file mode 100644 index 000000000000..b7de9063e057 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/py25q128la/flash_disc_param_otfde.json @@ -0,0 +1,286 @@ +{ + "otfde_header": { + "name": "OTFDEWFF3", + "flash_only": true, + "ip_protection": false, + "regions_lock": false, + "regions_number": 4, + "flash_enabled": true + }, + "bl_conf": { + "host_boot_done_lock": true, + "host_peripherals_lock": true, + "icache_conf_lock": true, + "m33_mem_part_lock": true, + "memss_firewall_lock": true, + "dma_channel_owner_lock": true, + "otfde_region_lock": true, + "core_events_lock": true + }, + "otfde_general": { + "parameters": { + "mem_otfde_initial_delay": 10, + "otfde_global_watchdog_timer": 5 + }, + "events": { + "reset_evt_mask": false, + "reset_evt_suspend": false, + "sft_reset_evt_mask": false, + "sft_reset_evt_suspend": false, + "bypass_mode_evt_mask": false, + "bypass_mode_evt_suspend": false, + "debug_mode_evt_mask": false, + "debug_mode_evt_suspend": false, + "general_evt_mask": false, + "general_evt_suspend": false, + "xspi_data_path_evt_mask": false, + "xspi_data_path_evt_suspend": false, + "xspi_cnfg_path_evt_mask": false, + "xspi_cnfg_path_evt_suspend": false, + "xspi_service_interrupt_evt_mask": false, + "xspi_service_interrupt_evt_suspend": false, + "trans_device_disabled_evt_mask": false, + "trans_device_disabled_evt_suspend": false, + "trans_region_disabled_evt_mask": false, + "trans_region_disabled_evt_suspend": false, + "trans_region_params_conf_evt_mask": false, + "trans_region_params_conf_evt_suspend": false, + "trans_multiple_regions_mapped_evt_mask": false, + "trans_multiple_regions_mapped_evt_suspend": false, + "trans_address_not_32_bit_evt_mask": false, + "trans_address_not_32_bit_evt_suspend": false, + "trans_size_not_32_bit_evt_mask": false, + "trans_size_not_32_bit_evt_suspend": false, + "trans_burst_not_32_bit_evt_mask": false, + "trans_burst_not_32_bit_evt_suspend": false, + "region_read_write_def_evt_mask": false, + "region_read_write_def_evt_suspend": false, + "suspend_while_disabled_evt_mask": false, + "suspend_while_disabled_evt_suspend": false + } + }, + "regions_settings": { + "region_parameters_lock": { + "REGION_0_PARAMS_0": true, + "REGION_0_PARAMS_1": true, + "REGION_0_PARAMS_2": true, + "REGION_1_PARAMS_0": false, + "REGION_1_PARAMS_1": false, + "REGION_1_PARAMS_2": false, + "REGION_2_PARAMS_0": true, + "REGION_2_PARAMS_1": true, + "REGION_2_PARAMS_2": true, + "REGION_3_PARAMS_0": false, + "REGION_3_PARAMS_1": false, + "REGION_3_PARAMS_2": false + }, + "region_0_protection": { + "mem_region_0_enabled": true, + "mem_region_0_device_id": 0, + "mem_region_0_spi_write_enable": true, + "mem_region_0_spi_read_enable": true, + "mem_region_0_physical_offset": 700, + "mem_region_0_security_id_msb": 0, + "mem_region_0_start_address": 81920, + "mem_region_0_end_address": 83617, + "mem_region_0_security_id_lsb": 0, + "mem_otfde_region_0_write_lock_en": false, + "mem_otfde_region_0_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_1_protection": { + "mem_region_1_enabled": true, + "mem_region_1_device_id": 0, + "mem_region_1_spi_write_enable": true, + "mem_region_1_spi_read_enable": true, + "mem_region_1_physical_offset": 0, + "mem_region_1_security_id_msb": 0, + "mem_region_1_start_address": 655360, + "mem_region_1_end_address": 656059, + "mem_region_1_security_id_lsb": 0, + "mem_otfde_region_1_write_lock_en": false, + "mem_otfde_region_1_enc_dec_bypass": "Bypass" + }, + "region_2_protection": { + "mem_region_2_enabled": true, + "mem_region_2_device_id": 0, + "mem_region_2_spi_write_enable": true, + "mem_region_2_spi_read_enable": true, + "mem_region_2_physical_offset": 2398, + "mem_region_2_security_id_msb": 0, + "mem_region_2_start_address": 671744, + "mem_region_2_end_address": 673441, + "mem_region_2_security_id_lsb": 0, + "mem_otfde_region_2_write_lock_en": false, + "mem_otfde_region_2_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_3_protection": { + "mem_region_3_enabled": false, + "mem_region_3_device_id": 1, + "mem_region_3_spi_write_enable": true, + "mem_region_3_spi_read_enable": true, + "mem_region_3_physical_offset": 0, + "mem_region_3_security_id_msb": 0, + "mem_region_3_start_address": 1, + "mem_region_3_end_address": 0, + "mem_region_3_security_id_lsb": 0, + "mem_otfde_region_3_write_lock_en": false, + "mem_otfde_region_3_enc_dec_bypass": "Bypass" + } + }, + "devices": { + "header": { + "flash_device_switch_conf": 1, + "ram_device_switch_conf": 1 + }, + "flash_switch": { + "flash_grant_sel": 0, + "flash_data_for_conf_0": 2181562505, + "flash_offset_bits_for_conf_0": 0, + "flash_stop_bit_for_conf_0": 0, + "flash_data_for_conf_1": 167911947, + "flash_offset_bits_for_conf_1": 1, + "flash_stop_bit_for_conf_1": 0, + "flash_data_for_conf_2": 139266, + "flash_offset_bits_for_conf_2": 2, + "flash_stop_bit_for_conf_2": 0, + "flash_data_for_conf_3": 1, + "flash_offset_bits_for_conf_3": 4, + "flash_stop_bit_for_conf_3": 0, + "flash_data_for_conf_4": 1076887634, + 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"flash_stop_bit_for_conf_13": 1, + "flash_data_for_conf_14": 0, + "flash_offset_bits_for_conf_14": 0, + "flash_stop_bit_for_conf_14": 1, + "flash_data_for_conf_15": 0, + "flash_offset_bits_for_conf_15": 0, + "flash_stop_bit_for_conf_15": 1, + "flash_data_for_conf_16": 0, + "flash_offset_bits_for_conf_16": 0, + "flash_stop_bit_for_conf_16": 1, + "flash_data_for_conf_17": 0, + "flash_offset_bits_for_conf_17": 0, + "flash_stop_bit_for_conf_17": 1, + "flash_data_for_conf_18": 0, + "flash_offset_bits_for_conf_18": 0, + "flash_stop_bit_for_conf_18": 1, + "flash_data_for_conf_19": 0, + "flash_offset_bits_for_conf_19": 0, + "flash_stop_bit_for_conf_19": 1, + "flash_data_for_conf_20": 0, + "flash_offset_bits_for_conf_20": 0, + "flash_stop_bit_for_conf_20": 1, + "flash_data_for_conf_21": 0, + "flash_offset_bits_for_conf_21": 0, + "flash_stop_bit_for_conf_21": 1, + "flash_data_for_conf_22": 0, + "flash_offset_bits_for_conf_22": 0, + "flash_stop_bit_for_conf_22": 1, + "flash_data_for_conf_23": 0, + "flash_offset_bits_for_conf_23": 0, + "flash_stop_bit_for_conf_23": 1 + }, + "ram_switch": { + "ram_grant_sel": 0, + "ram_data_for_conf_0": 2181562505, + "ram_offset_bits_for_conf_0": 0, + "ram_stop_bit_for_conf_0": 0, + "ram_data_for_conf_1": 67248651, + "ram_offset_bits_for_conf_1": 1, + "ram_stop_bit_for_conf_1": 0, + "ram_data_for_conf_2": 139266, + "ram_offset_bits_for_conf_2": 2, + "ram_stop_bit_for_conf_2": 0, + "ram_data_for_conf_3": 1, + "ram_offset_bits_for_conf_3": 4, + "ram_stop_bit_for_conf_3": 0, + "ram_data_for_conf_4": 1076887634, + "ram_offset_bits_for_conf_4": 45, + "ram_stop_bit_for_conf_4": 0, + "ram_data_for_conf_5": 3224371282, + "ram_offset_bits_for_conf_5": 45, + "ram_stop_bit_for_conf_5": 0, + "ram_data_for_conf_6": 262149, + "ram_offset_bits_for_conf_6": 14, + "ram_stop_bit_for_conf_6": 0, + "ram_data_for_conf_7": 0, + "ram_offset_bits_for_conf_7": 44, + "ram_stop_bit_for_conf_7": 1, + "ram_data_for_conf_8": 0, + "ram_offset_bits_for_conf_8": 0, + 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"ram_stop_bit_for_conf_18": 1, + "ram_data_for_conf_19": 0, + "ram_offset_bits_for_conf_19": 0, + "ram_stop_bit_for_conf_19": 1, + "ram_data_for_conf_20": 0, + "ram_offset_bits_for_conf_20": 0, + "ram_stop_bit_for_conf_20": 1, + "ram_data_for_conf_21": 0, + "ram_offset_bits_for_conf_21": 0, + "ram_stop_bit_for_conf_21": 1, + "ram_data_for_conf_22": 0, + "ram_offset_bits_for_conf_22": 0, + "ram_stop_bit_for_conf_22": 1, + "ram_data_for_conf_23": 0, + "ram_offset_bits_for_conf_23": 0, + "ram_stop_bit_for_conf_23": 1 + } + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/py25q128la/flash_disc_param_xspi.json b/boards/ti/lp_em_cc35x1/config/flash/py25q128la/flash_disc_param_xspi.json new file mode 100644 index 000000000000..229e12c5f41d --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/py25q128la/flash_disc_param_xspi.json @@ -0,0 +1,485 @@ +{ + "xspi_header": { + "name": "xSPIWFF3", + "device": "CC3500", + "use_hardware": "PY25Q128LA", + "use_case": "Quadro", + "dqs_support": 0, + "flash_only": 1, + "flash_separate_reset": 0, + "ram_separate_reset": true, + "clock_frequency": 80, + "qospi_clock_divider": 1, + "flash_device_character_conf": 0, + "ram_device_character_conf": 0, + "header_advanced": 0, + "phy_mode_enable": 1, + "pipeline_mode_enable": 1, + "loopback_support": "No", + "qspi_ref_clock": 80, + "spi_clock_freq": 20, + "spi_clock_divider": 1, + "flash_device_size": 16, + "flash_bytes_per_block": 16, + "flash_bytes_per_page": 256, + "flash_number_of_address_bytes": 3, + "flash_dual_opcode": 0, + "flash_jedec_manufacturer_id": 0, + "flash_jedec_device_id": 0, + "flash_name": "PY25Q128LA", + "flash_page_size": 256, + "flash_sector_size": 4096, + "flash_cs_polarity": "ACTIVE_LOW", + "flash_sw_reset_type": "x1xxxx", + "ram_device_size": 8, + "ram_bytes_per_block": 16, + "ram_bytes_per_page": 256, + "ram_number_of_address_bytes": 3, + "ram_dual_opcode": 0, + "ram_jedec_manufacturer_id": 0, + "ram_jedec_device_id": 0, + "ram_name": "NO_PSRAM", + "ram_page_size": 256, + "ram_sector_size": 4096, + "ram_cs_polarity": "ACTIVE_LOW", + "ram_sw_reset_type": "x1xxxx", + "flash_write_operation_modes": "4S-4S-4S", + "flash_read_operation_modes": "4S-4S-4S", + "ram_write_operation_modes": "4S-4S-4S", + "ram_read_operation_modes": "4S-4S-4S", + "crc_enable": 0, + "enable_dtr": 0, + "enable_ahb_decoder": 0, + "enter_xip_mod_immediately": 0, + "enter_xip_mod_next_read": 0, + "ahb_address_remapping": 0, + "enable_dma": 0, + "select_decode": 0, + "legacy_ip_mode": 0, + "direct_access": 1 + }, + "xspi_pinmux": { + "xspi_clk_input": 44, + "xspi_clk_input_use_hw": 0, + "xspi_clk_input_mode": "Input", + "xspi_clk_input_pull": "None", + "xspi_clk_input_interrupt_trigger": "Low", + "xspi_clk_input_dont_conf": 0, + "xspi_clk_input_output_strength": "High", + "xspi_clk_input_initial_output_state": "High", + "xspi_clk": 24, + "xspi_clk_use_hw": "None", + "xspi_clk_mode": "Output", + "xspi_clk_pull": "None", + "xspi_clk_output_strength": "High", + "xspi_clk_initial_output_state": "High", + "xspi_clk_interrupt_trigger": "None", + "xspi_clk_dont_conf": 0, + "xspi_flash_cs": 20, + "xspi_flash_cs_use_hw": "None", + "xspi_flash_cs_mode": "Output", + "xspi_flash_cs_pull": "None", + "xspi_flash_cs_output_strength": "High", + "xspi_flash_cs_initial_output_state": "High", + "xspi_flash_cs_interrupt_trigger": "None", + "xspi_flash_cs_dont_conf": 0, + "xspi_data_0": 25, + "xspi_data_0_use_hw": "None", + "xspi_data_0_mode": "Input", + "xspi_data_0_pull": "None", + "xspi_data_0_output_strength": "High", + "xspi_data_0_initial_output_state": "High", + "xspi_data_0_interrupt_trigger": "Low", + "xspi_data_0_dont_conf": 0, + "xspi_data_1": 21, + "xspi_data_1_use_hw": "None", + "xspi_data_1_mode": "Input", + "xspi_data_1_pull": "None", + "xspi_data_1_output_strength": "High", + "xspi_data_1_initial_output_state": "High", + "xspi_data_1_interrupt_trigger": "Low", + "xspi_data_1_dont_conf": 0, + "xspi_data_2": 22, + "xspi_data_2_use_hw": "None", + "xspi_data_2_mode": "Input", + "xspi_data_2_pull": "None", + "xspi_data_2_output_strength": "High", + "xspi_data_2_initial_output_state": "High", + "xspi_data_2_interrupt_trigger": "Low", + "xspi_data_2_dont_conf": 0, + "xspi_data_3": 23, + "xspi_data_3_use_hw": "None", + "xspi_data_3_mode": "Input", + "xspi_data_3_pull": "None", + "xspi_data_3_output_strength": "High", + "xspi_data_3_initial_output_state": "High", + "xspi_data_3_interrupt_trigger": "Low", + "xspi_data_3_dont_conf": 0, + "xspi_data_4": 26, + "xspi_data_4_use_hw": "None", + "xspi_data_4_mode": "Input", + "xspi_data_4_pull": "None", + "xspi_data_4_output_strength": "High", + "xspi_data_4_initial_output_state": "High", + "xspi_data_4_interrupt_trigger": "None", + "xspi_data_4_dont_conf": 0, + "xspi_data_5": 27, + "xspi_data_5_use_hw": "None", + "xspi_data_5_mode": "Input", + "xspi_data_5_pull": "None", + "xspi_data_5_output_strength": "High", + "xspi_data_5_initial_output_state": "High", + "xspi_data_5_interrupt_trigger": "None", + "xspi_data_5_dont_conf": 0, + "xspi_data_6": 28, + "xspi_data_6_use_hw": "None", + "xspi_data_6_mode": "Input", + "xspi_data_6_pull": "None", + "xspi_data_6_output_strength": "High", + "xspi_data_6_initial_output_state": "High", + "xspi_data_6_interrupt_trigger": "None", + "xspi_data_6_dont_conf": 0, + "xspi_data_7": 29, + "xspi_data_7_use_hw": "None", + "xspi_data_7_mode": "Input", + "xspi_data_7_pull": "None", + "xspi_data_7_output_strength": "High", + "xspi_data_7_initial_output_state": "High", + "xspi_data_7_interrupt_trigger": "None", + "xspi_data_7_dont_conf": 0, + "xspi_reset_flash": 36, + "xspi_reset_flash_use_hw": "None", + "xspi_reset_flash_mode": "Output", + "xspi_reset_flash_pull": "None", + "xspi_reset_flash_output_strength": "High", + "xspi_reset_flash_initial_output_state": "High", + "xspi_reset_flash_interrupt_trigger": "None", + "xspi_reset_flash_dont_conf": 0, + "xspi_cs_ram": 3, + "xspi_cs_ram_use_hw": "None", + "xspi_cs_ram_mode": "Output", + "xspi_cs_ram_pull": "None", + "xspi_cs_ram_output_strength": "High", + "xspi_cs_ram_initial_output_state": "High", + "xspi_cs_ram_interrupt_trigger": "None", + "xspi_cs_ram_dont_conf": 0, + "xspi_dqs": 30, + "xspi_dqs_use_hw": "None", + "xspi_dqs_mode": "Input", + "xspi_dqs_pull": "None", + "xspi_dqs_output_strength": "High", + "xspi_dqs_initial_output_state": "High", + "xspi_dqs_interrupt_trigger": "None", + "xspi_dqs_dont_conf": 0, + "xspi_reset_ram": 2, + "xspi_reset_ram_use_hw": "None", + "xspi_reset_ram_mode": "Input", + "xspi_reset_ram_pull": "None", + "xspi_reset_ram_output_strength": "High", + "xspi_reset_ram_initial_output_state": "High", + "xspi_reset_ram_interrupt_trigger": "None", + "xspi_reset_ram_dont_conf": 0 + }, + "xspi_operations": { + "xspi_operations_clocks": { + "clock_phase": 0, + "clock_polarity": 0, + "spi_mode": "2'b00" + }, + "xspi_operations_chip_select": { + "csda": 2, + "csdads": 0, + "cseot": 4, + "cssot": 1 + }, + "xspi_operations_reset": { + "flash_jedec_reset": 0, + "ram_jedec_reset": 0, + "flash_treset": 20, + "ram_treset": 20 + }, + "xspi_phy_operations": { + "flash_rx_dll_bypass_bit": 0, + "flash_dll_tx_delay": 22, + "flash_dll_rx_delay": 34, + "ram_rx_dll_bypass_bit": 0, + "ram_dll_tx_delay": 22, + "ram_dll_rx_delay": 34 + }, + "xspi_read_operations": { + "flash_dummy_rd_cycles": 10, + "flash_read_opcode": 11, + "suppl_flash_read_opcode": 0, + "ram_dummy_rd_cycles": 10, + "ram_read_opcode": 11, + "suppl_ram_read_opcode": 0, + "flash_non_cont_read_enable": 0, + "flash_max_read_jobs": 256, + "ram_non_cont_read_enable": 0, + "ram_max_read_jobs": 256, + "rww_en": 0, + "device_size": 8, + "number_of_banks": 1, + "bank_size": 8, + "mode_bit_enable": 0 + }, + "xspi_write_operations": { + "flash_address_and_data": { + "flash_dummy_wr_cycles": 0 + }, + "flash_command": { + "flash_write_opcode": 2, + "suppl_flash_write_opcode": 0 + }, + "ram_address_and_data": { + "ram_dummy_wr_cycles": 0 + }, + "ram_command": { + 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2, + "suppl_ram_program_opcode": 0, + "ram_maximum_program_time_limit": 1600 + }, + "ram_erase_conf": { + "ram_block_erase_opcode": 0, + "suppl_block_ram_erase_opcode": 0, + "ram_sector_erase_opcode": 0, + "suppl_sector_ram_erase_opcode": 0, + "ram_chip_erase_opcode": 0, + "suppl_chip_ram_erase_opcode": 0 + }, + "flash_buffer_support": { + "flash_pre_write_sequence": 0, + "flash_post_write_sequence": 0, + "flash_write_protection_timer_en": 0, + "flash_write_buffer_timer_mode": 16, + "flash_write_buffer_timer_range": 0, + "flash_service_interrupt_criteria": 0 + }, + "ram_buffer_support": { + "ram_pre_write_sequence": 0, + "ram_post_write_sequence": 0, + "ram_write_protection_timer_en": 0, + "ram_write_buffer_timer_mode": 16, + "ram_write_buffer_timer_range": 0, + "ram_service_interrupt_criteria": 0 + }, + "flash_pre_write_conf": { + "flash_pre_write_job_done_grant_sel": 0, + "data_for_flash_pre_write_conf_0": 0, + "offset_bits_for_flash_pre_write_conf_0": 0, + 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}, + "xspi_capture_operations": { + "read_data_capture": { + "flash_delay_transmitted_data": 0, + "flash_loopback_clock": 0, + "flash_bypass_adapted_loopback": 1, + "flash_sample_edge_sel": 0, + "ram_delay_transmitted_data": 0, + "ram_loopback_clock": 0, + "ram_bypass_adapted_loopback": 1, + "ram_sample_edge_sel": 0 + }, + "delays": { + "flash_full_half_cycle_delay": 0, + "flash_dll_bypass_mode": 1, + "flash_phase_detect_sel": 0, + "flash_dll_lock_num": 0, + "flash_dll_start_point": 0, + "flash_loopback_clock": 0, + "ram_full_half_cycle_delay": 0, + "ram_dll_bypass_mode": 1, + "ram_phase_detect_sel": 0, + "ram_dll_lock_num": 0, + "ram_dll_start_point": 0, + "ram_loopback_clock": 0 + }, + "operation_modes": { + "flash_sfdp_support": 0, + "ram_sfdp_support": 0, + "flash_pm_support": 0, + "ram_pm_support": 0, + "flash_sfdp_opcode": 0, + "suppl_flash_sfdp_opcode": 0, + "ram_sfdp_opcode": 0, + "suppl_ram_sfdp_opcode": 0, + "flash_enter_dpd_opcode": 185, + "suppl_flash_enter_dpd_opcode": 0, + "flash_exit_dpd_opcode": 171, + "suppl_flash_exit_dpd_opcode": 0, + "ram_enter_dpd_opcode": 185, + "suppl_ram_enter_dpd_opcode": 0, + "ram_exit_dpd_opcode": 171, + "suppl_ram_exit_dpd_opcode": 0, + "flash_quad_enable_opcode": 56, + "suppl_flash_quad_enable_opcode": 0, + "flash_quad_disable_opcode": 255, + "suppl_flash_quad_disable_opcode": 0, + "flash_octal_enable_opcode": 0, + "suppl_flash_octal_enable_opcode": 0, + "flash_octal_disable_opcode": 0, + "suppl_flash_octal_disable_opcode": 0, + "ram_quad_enable_opcode": 56, + "suppl_ram_quad_enable_opcode": 0, + "ram_quad_disable_opcode": 255, + "suppl_ram_quad_disable_opcode": 0, + "ram_octal_enable_opcode": 0, + "suppl_ram_octal_enable_opcode": 0, + "ram_octal_disable_opcode": 0, + "suppl_ram_octal_disable_opcode": 0 + } + } + }, + "external_memory_reporting": { + "header": { + "flash_auto_polling_enable": 1, + "flash_wel_enable": 1, + "flash_write_protect_enable": 0, + "flash_alternate_polling_conf_enable": 0, + "ram_auto_polling_enable": 1, + "ram_wel_enable": 1, + "ram_write_protect_enable": 0, + "ram_alternate_polling_conf_enable": 0 + }, + "flash_auto_polling": { + "flash_polling_repetition_delay": 0, + "flash_polling_count": 4, + "flash_enable_polling_expiration": 0, + "flash_polling_polarity": 0, + "flash_polling_address_phase_enable": 0, + "flash_polling_bit_index": 0, + "flash_numbers_poll_cycles": 65535, + "flash_dummy_autopoll_cycles": 0 + }, + "ram_auto_polling": { + "ram_polling_repetition_delay": 0, + "ram_polling_count": 4, + "ram_enable_polling_expiration": 0, + "ram_polling_polarity": 0, + "ram_polling_address_phase_enable": 0, + "ram_polling_bit_index": 0, + "ram_numbers_poll_cycles": 65535, + "ram_dummy_autopoll_cycles": 0 + }, + "flash_polling_command": { + "flash_polling_opcode": 5, + "suppl_flash_polling_opcode": 0 + }, + "ram_polling_command": { + "ram_polling_opcode": 5, + "suppl_ram_polling_opcode": 0 + }, + "flash_alternate_polling": { + "flash_polling_resp_count": 1023, + "flash_polling_iterations": 1, + "flash_polling_enabled": 0, + "flash_polling_disabled": 0, + "flash_grant_sel": 0, + "flash_data_for_enable_poling_conf_0": 0, + "flash_offset_bits_for_enable_poling_conf_0": 0, + "flash_stop_bit_for_enable_poling_conf_0": 1, + "flash_data_for_enable_poling_conf_1": 0, + "flash_offset_bits_for_enable_poling_conf_1": 0, + "flash_stop_bit_for_enable_poling_conf_1": 1, + "flash_data_for_disable_poling_conf_0": 0, + "flash_offset_bits_for_disable_poling_conf_0": 0, + "flash_stop_bit_for_disable_poling_conf_0": 1, + "flash_data_for_disable_poling_conf_1": 0, + "flash_offset_bits_for_disable_poling_conf_1": 0, + "flash_stop_bit_for_disable_poling_conf_1": 1 + }, + "ram_alternate_polling": { + "ram_polling_resp_count": 1023, + "ram_polling_iterations": 1, + "ram_polling_enabled": 0, + "ram_polling_disabled": 0, + "ram_grant_sel": 0, + "ram_data_for_enable_poling_conf_0": 0, + "ram_offset_bits_for_enable_poling_conf_0": 0, + "ram_stop_bit_for_enable_poling_conf_0": 1, + "ram_data_for_enable_poling_conf_1": 0, + "ram_offset_bits_for_enable_poling_conf_1": 0, + "ram_stop_bit_for_enable_poling_conf_1": 1, + "ram_data_for_disable_poling_conf_0": 0, + "ram_offset_bits_for_disable_poling_conf_0": 0, + "ram_stop_bit_for_disable_poling_conf_0": 1, + "ram_data_for_disable_poling_conf_1": 0, + "ram_offset_bits_for_disable_poling_conf_1": 0, + "ram_stop_bit_for_disable_poling_conf_1": 1 + }, + "flash_wel_command": { + "flash_wel_opcode": 6, + "suppl_flash_wel_opcode": 0 + }, + "ram_wel_command": { + "ram_wel_opcode": 6, + "suppl_ram_wel_opcode": 0 + } + }, + "event": { + "host_nvic_irq": 0, + "core_10_mux_sel": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/py25q256lc/flash_disc_param_ext_mem.json b/boards/ti/lp_em_cc35x1/config/flash/py25q256lc/flash_disc_param_ext_mem.json new file mode 100644 index 000000000000..22b8d198bffd --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/py25q256lc/flash_disc_param_ext_mem.json @@ -0,0 +1,99 @@ +{ + "vendor_primary_sbl": true, + "ti_wsoc_primary_container": true, + "ti_wsoc_bl2_primary_container": true, + "nvs_enable": true, + "vendor_alternate_image": true, + "vendor_sbl_alternate_image": true, + "ti_bl_alternate_image": true, + "ti_wsoc_alternate_image": true, + "ti_wsoc_bl2_alternate_image": true, + "region_0": { + "mem_region_0_start_phy_address": 16760832, + "mem_region_0_end_phy_address": 25157631, + "region0_boot": false, + "region0_main_code": true, + "region0_nvs": false, + "region0_wsoc_code": false, + "region0_alternate_code": false + }, + "region_1": { + "mem_region_1_start_phy_address": 0, + "mem_region_1_end_phy_address": 16760831, + "region1_boot": true, + "region1_main_code": false, + "region1_nvs": true, + "region1_wsoc_code": true, + "region1_alternate_code": false + }, + "region_2": { + "mem_region_2_start_phy_address": 25157632, + "mem_region_2_end_phy_address": 33554431, + "region2_boot": false, + "region2_main_code": false, + "region2_nvs": false, + "region2_wsoc_code": false, + "region2_alternate_code": true + }, + "region_3": { + "mem_region_3_start_phy_address": 0, + "mem_region_3_end_phy_address": 0, + "region3_boot": false, + "region3_main_code": false, + "region3_nvs": false, + "region3_wsoc_code": false, + "region3_alternate_code": false + }, + "boot_region_conf": { + "boot_region_size": 0, + "boot_region_flash_disco_param_start_address": 0, + "boot_region_primary_ti_bl_start_phy_address": 12284, + "boot_region_primary_ti_bl_magic": 0, + "boot_region_primary_ti_bl_major": 0, + "boot_region_primary_ti_bl_minor": 0, + "boot_region_sec_ti_bl_start_phy_address": 430076, + "boot_region_sec_ti_bl_magic": 0, + "boot_region_sec_ti_bl_major": 0, + "boot_region_sec_ti_bl_minor": 0 + }, + "main_code_region_conf": { + "main_code_region_vendor_image_start_phy_address": 16764924, + "main_code_region_vendor_image_magic": 0, + "main_code_region_vendor_image_major": 0, + "main_code_region_vendor_image_minor": 0, + "main_code_region_sbl_start_phy_address": 0, + "main_code_region_sbl_magic": 0, + "main_code_region_sbl_major": 0, + "main_code_region_sbl_minor": 0 + }, + "alt_code_region_conf": { + "alt_code_region_vendor_image_start_phy_address": 25161724, + "alt_code_region_vendor_image_magic": 0, + "alt_code_region_vendor_image_major": 0, + "alt_code_region_vendor_image_minor": 0, + "alt_code_region_sbl_start_phy_address": 0, + "alt_code_region_sbl_magic": 0, + "alt_code_region_sbl_major": 0, + "alt_code_region_sbl_minor": 0 + }, + "nvs_code_region_conf": { + "nvs_start_phy_address": 1777664, + "nvs_region_size": 14983168, + "nvs_region_primary_wsoc_start_phy_address": 847868, + "nvs_region_primary_wsoc_magic": 0, + "nvs_region_primary_wsoc_major": 0, + "nvs_region_primary_wsoc_minor": 0, + "nvs_region_sec_wsoc_start_phy_address": 1314812, + "nvs_region_sec_wsoc_magic": 0, + "nvs_region_sec_wsoc_major": 0, + "nvs_region_sec_wsoc_minor": 0, + "nvs_region_primary_wsoc_bl2_start_phy_address": 0, + "nvs_region_primary_wsoc_bl2_magic": 0, + "nvs_region_primary_wsoc_bl2_major": 0, + "nvs_region_primary_wsoc_bl2_minor": 0, + "nvs_region_sec_wsoc_bl2_start_phy_address": 0, + "nvs_region_sec_wsoc_bl2_magic": 0, + "nvs_region_sec_wsoc_bl2_major": 0, + "nvs_region_sec_wsoc_bl2_minor": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/py25q256lc/flash_disc_param_otfde.json b/boards/ti/lp_em_cc35x1/config/flash/py25q256lc/flash_disc_param_otfde.json new file mode 100644 index 000000000000..6a1724457bbe --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/py25q256lc/flash_disc_param_otfde.json @@ -0,0 +1,286 @@ +{ + "otfde_header": { + "name": "OTFDEWFF3", + "flash_only": true, + "ip_protection": false, + "regions_lock": false, + "regions_number": 4, + "flash_enabled": true + }, + "bl_conf": { + "host_boot_done_lock": true, + "host_peripherals_lock": true, + "icache_conf_lock": true, + "m33_mem_part_lock": true, + "memss_firewall_lock": true, + "dma_channel_owner_lock": true, + "otfde_region_lock": true, + "core_events_lock": true + }, + "otfde_general": { + "parameters": { + "mem_otfde_initial_delay": 10, + "otfde_global_watchdog_timer": 5 + }, + "events": { + "reset_evt_mask": false, + "reset_evt_suspend": false, + "sft_reset_evt_mask": false, + "sft_reset_evt_suspend": false, + "bypass_mode_evt_mask": false, + "bypass_mode_evt_suspend": false, + "debug_mode_evt_mask": false, + "debug_mode_evt_suspend": false, + "general_evt_mask": false, + "general_evt_suspend": false, + "xspi_data_path_evt_mask": false, + "xspi_data_path_evt_suspend": false, + "xspi_cnfg_path_evt_mask": false, + "xspi_cnfg_path_evt_suspend": false, + "xspi_service_interrupt_evt_mask": false, + "xspi_service_interrupt_evt_suspend": false, + "trans_device_disabled_evt_mask": false, + "trans_device_disabled_evt_suspend": false, + "trans_region_disabled_evt_mask": false, + "trans_region_disabled_evt_suspend": false, + "trans_region_params_conf_evt_mask": false, + "trans_region_params_conf_evt_suspend": false, + "trans_multiple_regions_mapped_evt_mask": false, + "trans_multiple_regions_mapped_evt_suspend": false, + "trans_address_not_32_bit_evt_mask": false, + "trans_address_not_32_bit_evt_suspend": false, + "trans_size_not_32_bit_evt_mask": false, + "trans_size_not_32_bit_evt_suspend": false, + "trans_burst_not_32_bit_evt_mask": false, + "trans_burst_not_32_bit_evt_suspend": false, + "region_read_write_def_evt_mask": false, + "region_read_write_def_evt_suspend": false, + "suspend_while_disabled_evt_mask": false, + "suspend_while_disabled_evt_suspend": false + } + }, + "regions_settings": { + "region_parameters_lock": { + "REGION_0_PARAMS_0": true, + "REGION_0_PARAMS_1": true, + "REGION_0_PARAMS_2": true, + "REGION_1_PARAMS_0": false, + "REGION_1_PARAMS_1": false, + "REGION_1_PARAMS_2": false, + "REGION_2_PARAMS_0": true, + "REGION_2_PARAMS_1": true, + "REGION_2_PARAMS_2": true, + "REGION_3_PARAMS_0": false, + "REGION_3_PARAMS_1": false, + "REGION_3_PARAMS_2": false + }, + "region_0_protection": { + "mem_region_0_enabled": true, + "mem_region_0_device_id": 0, + "mem_region_0_spi_write_enable": true, + "mem_region_0_spi_read_enable": true, + "mem_region_0_physical_offset": 4092, + "mem_region_0_security_id_msb": 0, + "mem_region_0_start_address": 81920, + "mem_region_0_end_address": 83969, + "mem_region_0_security_id_lsb": 0, + "mem_otfde_region_0_write_lock_en": false, + "mem_otfde_region_0_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_1_protection": { + "mem_region_1_enabled": true, + "mem_region_1_device_id": 0, + "mem_region_1_spi_write_enable": true, + "mem_region_1_spi_read_enable": true, + "mem_region_1_physical_offset": 0, + "mem_region_1_security_id_msb": 0, + "mem_region_1_start_address": 655360, + "mem_region_1_end_address": 659451, + "mem_region_1_security_id_lsb": 0, + "mem_otfde_region_1_write_lock_en": false, + "mem_otfde_region_1_enc_dec_bypass": "Bypass" + }, + "region_2_protection": { + "mem_region_2_enabled": true, + "mem_region_2_device_id": 0, + "mem_region_2_spi_write_enable": true, + "mem_region_2_spi_read_enable": true, + "mem_region_2_physical_offset": 6142, + "mem_region_2_security_id_msb": 0, + "mem_region_2_start_address": 671744, + "mem_region_2_end_address": 673793, + "mem_region_2_security_id_lsb": 0, + "mem_otfde_region_2_write_lock_en": false, + "mem_otfde_region_2_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_3_protection": { + "mem_region_3_enabled": false, + "mem_region_3_device_id": 1, + "mem_region_3_spi_write_enable": true, + "mem_region_3_spi_read_enable": true, + "mem_region_3_physical_offset": 0, + "mem_region_3_security_id_msb": 0, + "mem_region_3_start_address": 1, + "mem_region_3_end_address": 0, + "mem_region_3_security_id_lsb": 0, + "mem_otfde_region_3_write_lock_en": false, + "mem_otfde_region_3_enc_dec_bypass": "Bypass" + } + }, + "devices": { + "header": { + "flash_device_switch_conf": 1, + "ram_device_switch_conf": 1 + }, + "flash_switch": { + "flash_grant_sel": 0, + "flash_data_for_conf_0": 2181562505, + "flash_offset_bits_for_conf_0": 0, + "flash_stop_bit_for_conf_0": 0, + "flash_data_for_conf_1": 201466379, + "flash_offset_bits_for_conf_1": 1, + "flash_stop_bit_for_conf_1": 0, + "flash_data_for_conf_2": 139266, + "flash_offset_bits_for_conf_2": 2, + "flash_stop_bit_for_conf_2": 0, + "flash_data_for_conf_3": 1, + "flash_offset_bits_for_conf_3": 4, + "flash_stop_bit_for_conf_3": 0, + "flash_data_for_conf_4": 1076887634, + "flash_offset_bits_for_conf_4": 45, + "flash_stop_bit_for_conf_4": 0, + "flash_data_for_conf_5": 3224371282, + "flash_offset_bits_for_conf_5": 45, + "flash_stop_bit_for_conf_5": 0, + "flash_data_for_conf_6": 262149, + "flash_offset_bits_for_conf_6": 14, + "flash_stop_bit_for_conf_6": 0, + "flash_data_for_conf_7": 0, + "flash_offset_bits_for_conf_7": 44, + "flash_stop_bit_for_conf_7": 0, + "flash_data_for_conf_8": 32509955, + "flash_offset_bits_for_conf_8": 5, + "flash_stop_bit_for_conf_8": 1, + "flash_data_for_conf_9": 0, + "flash_offset_bits_for_conf_9": 0, + "flash_stop_bit_for_conf_9": 1, + "flash_data_for_conf_10": 0, + "flash_offset_bits_for_conf_10": 0, + "flash_stop_bit_for_conf_10": 1, + "flash_data_for_conf_11": 0, + "flash_offset_bits_for_conf_11": 0, + "flash_stop_bit_for_conf_11": 1, + "flash_data_for_conf_12": 0, + "flash_offset_bits_for_conf_12": 0, + "flash_stop_bit_for_conf_12": 1, + "flash_data_for_conf_13": 0, + "flash_offset_bits_for_conf_13": 0, + "flash_stop_bit_for_conf_13": 1, + "flash_data_for_conf_14": 0, + "flash_offset_bits_for_conf_14": 0, + "flash_stop_bit_for_conf_14": 1, + "flash_data_for_conf_15": 0, + "flash_offset_bits_for_conf_15": 0, + "flash_stop_bit_for_conf_15": 1, + "flash_data_for_conf_16": 0, + "flash_offset_bits_for_conf_16": 0, + "flash_stop_bit_for_conf_16": 1, + "flash_data_for_conf_17": 0, + "flash_offset_bits_for_conf_17": 0, + "flash_stop_bit_for_conf_17": 1, + "flash_data_for_conf_18": 0, + "flash_offset_bits_for_conf_18": 0, + "flash_stop_bit_for_conf_18": 1, + "flash_data_for_conf_19": 0, + "flash_offset_bits_for_conf_19": 0, + "flash_stop_bit_for_conf_19": 1, + "flash_data_for_conf_20": 0, + "flash_offset_bits_for_conf_20": 0, + "flash_stop_bit_for_conf_20": 1, + "flash_data_for_conf_21": 0, + "flash_offset_bits_for_conf_21": 0, + "flash_stop_bit_for_conf_21": 1, + "flash_data_for_conf_22": 0, + "flash_offset_bits_for_conf_22": 0, + "flash_stop_bit_for_conf_22": 1, + "flash_data_for_conf_23": 0, + "flash_offset_bits_for_conf_23": 0, + "flash_stop_bit_for_conf_23": 1 + }, + "ram_switch": { + "ram_grant_sel": 0, + "ram_data_for_conf_0": 2181562505, + "ram_offset_bits_for_conf_0": 0, + "ram_stop_bit_for_conf_0": 0, + "ram_data_for_conf_1": 67248651, + "ram_offset_bits_for_conf_1": 1, + "ram_stop_bit_for_conf_1": 0, + "ram_data_for_conf_2": 139266, + "ram_offset_bits_for_conf_2": 2, + "ram_stop_bit_for_conf_2": 0, + "ram_data_for_conf_3": 1, + "ram_offset_bits_for_conf_3": 4, + "ram_stop_bit_for_conf_3": 0, + "ram_data_for_conf_4": 1076887634, + "ram_offset_bits_for_conf_4": 45, + "ram_stop_bit_for_conf_4": 0, + "ram_data_for_conf_5": 3224371282, + "ram_offset_bits_for_conf_5": 45, + "ram_stop_bit_for_conf_5": 0, + "ram_data_for_conf_6": 262149, + "ram_offset_bits_for_conf_6": 14, + "ram_stop_bit_for_conf_6": 0, + "ram_data_for_conf_7": 0, + "ram_offset_bits_for_conf_7": 44, + "ram_stop_bit_for_conf_7": 0, + "ram_data_for_conf_8": 32509954, + "ram_offset_bits_for_conf_8": 5, + "ram_stop_bit_for_conf_8": 1, + "ram_data_for_conf_9": 0, + "ram_offset_bits_for_conf_9": 0, + "ram_stop_bit_for_conf_9": 1, + "ram_data_for_conf_10": 0, + "ram_offset_bits_for_conf_10": 0, + "ram_stop_bit_for_conf_10": 1, + "ram_data_for_conf_11": 0, + "ram_offset_bits_for_conf_11": 0, + "ram_stop_bit_for_conf_11": 1, + "ram_data_for_conf_12": 0, + "ram_offset_bits_for_conf_12": 0, + "ram_stop_bit_for_conf_12": 1, + "ram_data_for_conf_13": 0, + "ram_offset_bits_for_conf_13": 0, + "ram_stop_bit_for_conf_13": 1, + "ram_data_for_conf_14": 0, + "ram_offset_bits_for_conf_14": 0, + "ram_stop_bit_for_conf_14": 1, + "ram_data_for_conf_15": 0, + "ram_offset_bits_for_conf_15": 0, + "ram_stop_bit_for_conf_15": 1, + "ram_data_for_conf_16": 0, + "ram_offset_bits_for_conf_16": 0, + "ram_stop_bit_for_conf_16": 1, + "ram_data_for_conf_17": 0, + "ram_offset_bits_for_conf_17": 0, + "ram_stop_bit_for_conf_17": 1, + "ram_data_for_conf_18": 0, + "ram_offset_bits_for_conf_18": 0, + "ram_stop_bit_for_conf_18": 1, + "ram_data_for_conf_19": 0, + "ram_offset_bits_for_conf_19": 0, + "ram_stop_bit_for_conf_19": 1, + "ram_data_for_conf_20": 0, + "ram_offset_bits_for_conf_20": 0, + "ram_stop_bit_for_conf_20": 1, + "ram_data_for_conf_21": 0, + "ram_offset_bits_for_conf_21": 0, + "ram_stop_bit_for_conf_21": 1, + "ram_data_for_conf_22": 0, + "ram_offset_bits_for_conf_22": 0, + "ram_stop_bit_for_conf_22": 1, + "ram_data_for_conf_23": 0, + "ram_offset_bits_for_conf_23": 0, + "ram_stop_bit_for_conf_23": 1 + } + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/py25q256lc/flash_disc_param_xspi.json b/boards/ti/lp_em_cc35x1/config/flash/py25q256lc/flash_disc_param_xspi.json new file mode 100644 index 000000000000..c95741a7111d --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/py25q256lc/flash_disc_param_xspi.json @@ -0,0 +1,485 @@ +{ + "xspi_header": { + "name": "xSPIWFF3", + "device": "CC3500", + "use_hardware": "PY25Q256LC", + "use_case": "Quadro", + "dqs_support": 0, + "flash_only": 1, + "flash_separate_reset": 0, + "ram_separate_reset": true, + "clock_frequency": 80, + "qospi_clock_divider": 1, + "flash_device_character_conf": 0, + "ram_device_character_conf": 0, + "header_advanced": 0, + "phy_mode_enable": 1, + "pipeline_mode_enable": 1, + "loopback_support": "No", + "qspi_ref_clock": 80, + "spi_clock_freq": 20, + "spi_clock_divider": 1, + "flash_device_size": 32, + "flash_bytes_per_block": 16, + "flash_bytes_per_page": 256, + "flash_number_of_address_bytes": 4, + "flash_dual_opcode": 0, + "flash_jedec_manufacturer_id": 0, + "flash_jedec_device_id": 0, + "flash_name": "PY25Q256LC", + "flash_page_size": 256, + "flash_sector_size": 4096, + "flash_cs_polarity": "ACTIVE_LOW", + "flash_sw_reset_type": "x1xxxx", + "ram_device_size": 8, + "ram_bytes_per_block": 16, + "ram_bytes_per_page": 256, + "ram_number_of_address_bytes": 3, + "ram_dual_opcode": 0, + "ram_jedec_manufacturer_id": 0, + "ram_jedec_device_id": 0, + "ram_name": "NO_PSRAM", + "ram_page_size": 256, + "ram_sector_size": 4096, + "ram_cs_polarity": "ACTIVE_LOW", + "ram_sw_reset_type": "x1xxxx", + "flash_write_operation_modes": "4S-4S-4S", + "flash_read_operation_modes": "4S-4S-4S", + "ram_write_operation_modes": "4S-4S-4S", + "ram_read_operation_modes": "4S-4S-4S", + "crc_enable": 0, + "enable_dtr": 0, + "enable_ahb_decoder": 0, + "enter_xip_mod_immediately": 0, + "enter_xip_mod_next_read": 0, + "ahb_address_remapping": 0, + "enable_dma": 0, + "select_decode": 0, + "legacy_ip_mode": 0, + "direct_access": 1 + }, + "xspi_pinmux": { + "xspi_clk_input": 44, + "xspi_clk_input_use_hw": 0, + "xspi_clk_input_mode": "Input", + "xspi_clk_input_pull": "None", + "xspi_clk_input_interrupt_trigger": "Low", + "xspi_clk_input_dont_conf": 0, + "xspi_clk_input_output_strength": "High", + "xspi_clk_input_initial_output_state": "High", + "xspi_clk": 24, + "xspi_clk_use_hw": "None", + "xspi_clk_mode": "Output", + "xspi_clk_pull": "None", + "xspi_clk_output_strength": "High", + "xspi_clk_initial_output_state": "High", + "xspi_clk_interrupt_trigger": "None", + "xspi_clk_dont_conf": 0, + "xspi_flash_cs": 20, + "xspi_flash_cs_use_hw": "None", + "xspi_flash_cs_mode": "Output", + "xspi_flash_cs_pull": "None", + "xspi_flash_cs_output_strength": "High", + "xspi_flash_cs_initial_output_state": "High", + "xspi_flash_cs_interrupt_trigger": "None", + "xspi_flash_cs_dont_conf": 0, + "xspi_data_0": 25, + "xspi_data_0_use_hw": "None", + "xspi_data_0_mode": "Input", + "xspi_data_0_pull": "None", + "xspi_data_0_output_strength": "High", + "xspi_data_0_initial_output_state": "High", + "xspi_data_0_interrupt_trigger": "Low", + "xspi_data_0_dont_conf": 0, + "xspi_data_1": 21, + "xspi_data_1_use_hw": "None", + "xspi_data_1_mode": "Input", + "xspi_data_1_pull": "None", + "xspi_data_1_output_strength": "High", + "xspi_data_1_initial_output_state": "High", + "xspi_data_1_interrupt_trigger": "Low", + "xspi_data_1_dont_conf": 0, + "xspi_data_2": 22, + "xspi_data_2_use_hw": "None", + "xspi_data_2_mode": "Input", + "xspi_data_2_pull": "None", + "xspi_data_2_output_strength": "High", + "xspi_data_2_initial_output_state": "High", + "xspi_data_2_interrupt_trigger": "Low", + "xspi_data_2_dont_conf": 0, + "xspi_data_3": 23, + "xspi_data_3_use_hw": "None", + "xspi_data_3_mode": "Input", + "xspi_data_3_pull": "None", + "xspi_data_3_output_strength": "High", + "xspi_data_3_initial_output_state": "High", + "xspi_data_3_interrupt_trigger": "Low", + "xspi_data_3_dont_conf": 0, + "xspi_data_4": 26, + "xspi_data_4_use_hw": "None", + "xspi_data_4_mode": "Input", + "xspi_data_4_pull": "None", + "xspi_data_4_output_strength": "High", + "xspi_data_4_initial_output_state": "High", + "xspi_data_4_interrupt_trigger": "None", + "xspi_data_4_dont_conf": 0, + "xspi_data_5": 27, + "xspi_data_5_use_hw": "None", + "xspi_data_5_mode": "Input", + "xspi_data_5_pull": "None", + "xspi_data_5_output_strength": "High", + "xspi_data_5_initial_output_state": "High", + "xspi_data_5_interrupt_trigger": "None", + "xspi_data_5_dont_conf": 0, + "xspi_data_6": 28, + "xspi_data_6_use_hw": "None", + "xspi_data_6_mode": "Input", + "xspi_data_6_pull": "None", + "xspi_data_6_output_strength": "High", + "xspi_data_6_initial_output_state": "High", + "xspi_data_6_interrupt_trigger": "None", + "xspi_data_6_dont_conf": 0, + "xspi_data_7": 29, + "xspi_data_7_use_hw": "None", + "xspi_data_7_mode": "Input", + "xspi_data_7_pull": "None", + "xspi_data_7_output_strength": "High", + "xspi_data_7_initial_output_state": "High", + "xspi_data_7_interrupt_trigger": "None", + "xspi_data_7_dont_conf": 0, + "xspi_reset_flash": 36, + "xspi_reset_flash_use_hw": "None", + "xspi_reset_flash_mode": "Output", + "xspi_reset_flash_pull": "None", + "xspi_reset_flash_output_strength": "High", + "xspi_reset_flash_initial_output_state": "High", + "xspi_reset_flash_interrupt_trigger": "None", + "xspi_reset_flash_dont_conf": 0, + "xspi_cs_ram": 3, + "xspi_cs_ram_use_hw": "None", + "xspi_cs_ram_mode": "Output", + "xspi_cs_ram_pull": "None", + "xspi_cs_ram_output_strength": "High", + "xspi_cs_ram_initial_output_state": "High", + "xspi_cs_ram_interrupt_trigger": "None", + "xspi_cs_ram_dont_conf": 0, + "xspi_dqs": 30, + "xspi_dqs_use_hw": "None", + "xspi_dqs_mode": "Input", + "xspi_dqs_pull": "None", + "xspi_dqs_output_strength": "High", + "xspi_dqs_initial_output_state": "High", + "xspi_dqs_interrupt_trigger": "None", + "xspi_dqs_dont_conf": 0, + "xspi_reset_ram": 2, + "xspi_reset_ram_use_hw": "None", + "xspi_reset_ram_mode": "Input", + "xspi_reset_ram_pull": "None", + "xspi_reset_ram_output_strength": "High", + "xspi_reset_ram_initial_output_state": "High", + "xspi_reset_ram_interrupt_trigger": "None", + "xspi_reset_ram_dont_conf": 0 + }, + "xspi_operations": { + "xspi_operations_clocks": { + "clock_phase": 0, + "clock_polarity": 0, + "spi_mode": "2'b00" + }, + "xspi_operations_chip_select": { + "csda": 2, + "csdads": 0, + "cseot": 4, + "cssot": 1 + }, + "xspi_operations_reset": { + "flash_jedec_reset": 1, + "ram_jedec_reset": 0, + "flash_treset": 20, + "ram_treset": 20 + }, + "xspi_phy_operations": { + "flash_rx_dll_bypass_bit": 0, + "flash_dll_tx_delay": 22, + "flash_dll_rx_delay": 34, + "ram_rx_dll_bypass_bit": 0, + "ram_dll_tx_delay": 22, + "ram_dll_rx_delay": 34 + }, + "xspi_read_operations": { + "flash_dummy_rd_cycles": 12, + "flash_read_opcode": 11, + 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"flash_program_opcode": 2, + "suppl_flash_program_opcode": 0, + "flash_maximum_program_time_limit": 1600 + }, + "flash_erase_operation": { + "flash_min_erase_size": "4 kB", + "flash_erase_opcode": 32, + "suppl_flash_erase_opcode": 0, + "flash_maximum_erase_time_limit": 4095 + }, + "flash_erase_conf": { + "flash_block_erase_opcode": 0, + "suppl_block_flash_erase_opcode": 0, + "flash_sector_erase_opcode": 0, + "suppl_sector_flash_erase_opcode": 0, + "flash_chip_erase_opcode": 0, + "suppl_chip_flash_erase_opcode": 0 + }, + "ram_program_operation": { + "ram_min_program_size": "256 B", + "ram_program_opcode": 2, + "suppl_ram_program_opcode": 0, + "ram_maximum_program_time_limit": 1600 + }, + "ram_erase_conf": { + "ram_block_erase_opcode": 0, + "suppl_block_ram_erase_opcode": 0, + "ram_sector_erase_opcode": 0, + "suppl_sector_ram_erase_opcode": 0, + "ram_chip_erase_opcode": 0, + "suppl_chip_ram_erase_opcode": 0 + }, + "flash_buffer_support": { + "flash_pre_write_sequence": 0, + "flash_post_write_sequence": 0, + "flash_write_protection_timer_en": 0, + "flash_write_buffer_timer_mode": 16, + "flash_write_buffer_timer_range": 0, + "flash_service_interrupt_criteria": 0 + }, + "ram_buffer_support": { + "ram_pre_write_sequence": 0, + "ram_post_write_sequence": 0, + "ram_write_protection_timer_en": 0, + "ram_write_buffer_timer_mode": 16, + "ram_write_buffer_timer_range": 0, + "ram_service_interrupt_criteria": 0 + }, + "flash_pre_write_conf": { + "flash_pre_write_job_done_grant_sel": 0, + "data_for_flash_pre_write_conf_0": 0, + "offset_bits_for_flash_pre_write_conf_0": 0, + "stop_bit_for_flash_pre_write_conf_0": 1, + "data_for_flash_pre_write_conf_1": 0, + "offset_bits_for_flash_pre_write_conf_1": 0 + }, + "flash_post_write_conf": { + "flash_post_write_job_done_grant_sel": 0, + "data_for_flash_post_write_conf_0": 0, + "offset_bits_for_flash_post_write_conf_0": 0, + "stop_bit_for_flash_post_write_conf_0": 1, + "data_for_flash_post_write_conf_1": 0, + "offset_bits_for_flash_post_write_conf_1": 0 + }, + "ram_pre_write_conf": { + "ram_pre_write_job_done_grant_sel": 0, + "data_for_ram_pre_write_conf_0": 0, + "offset_bits_for_ram_pre_write_conf_0": 0, + "stop_bit_for_ram_pre_write_conf_0": 1, + "data_for_ram_pre_write_conf_1": 0, + "offset_bits_for_ram_pre_write_conf_1": 0 + }, + "ram_post_write_conf": { + "ram_post_write_job_done_grant_sel": 0, + "data_for_ram_post_write_conf_0": 0, + "offset_bits_for_ram_post_write_conf_0": 0, + "stop_bit_for_ram_post_write_conf_0": 1, + "data_for_ram_post_write_conf_1": 0, + "offset_bits_for_ram_post_write_conf_1": 0 + } + }, + "xspi_capture_operations": { + "read_data_capture": { + "flash_delay_transmitted_data": 0, + "flash_loopback_clock": 0, + "flash_bypass_adapted_loopback": 1, + "flash_sample_edge_sel": 0, + "ram_delay_transmitted_data": 0, + "ram_loopback_clock": 0, + "ram_bypass_adapted_loopback": 1, + "ram_sample_edge_sel": 0 + }, + "delays": { + "flash_full_half_cycle_delay": 0, + "flash_dll_bypass_mode": 1, + "flash_phase_detect_sel": 0, + "flash_dll_lock_num": 0, + "flash_dll_start_point": 0, + "flash_loopback_clock": 0, + "ram_full_half_cycle_delay": 0, + "ram_dll_bypass_mode": 1, + "ram_phase_detect_sel": 0, + "ram_dll_lock_num": 0, + "ram_dll_start_point": 0, + "ram_loopback_clock": 0 + }, + "operation_modes": { + "flash_sfdp_support": 0, + "ram_sfdp_support": 0, + "flash_pm_support": 0, + "ram_pm_support": 0, + "flash_sfdp_opcode": 0, + "suppl_flash_sfdp_opcode": 0, + "ram_sfdp_opcode": 0, + "suppl_ram_sfdp_opcode": 0, + "flash_enter_dpd_opcode": 185, + "suppl_flash_enter_dpd_opcode": 0, + "flash_exit_dpd_opcode": 171, + "suppl_flash_exit_dpd_opcode": 0, + "ram_enter_dpd_opcode": 185, + "suppl_ram_enter_dpd_opcode": 0, + "ram_exit_dpd_opcode": 171, + "suppl_ram_exit_dpd_opcode": 0, + "flash_quad_enable_opcode": 56, + "suppl_flash_quad_enable_opcode": 0, + "flash_quad_disable_opcode": 255, + "suppl_flash_quad_disable_opcode": 0, + "flash_octal_enable_opcode": 0, + "suppl_flash_octal_enable_opcode": 0, + "flash_octal_disable_opcode": 0, + "suppl_flash_octal_disable_opcode": 0, + "ram_quad_enable_opcode": 56, + "suppl_ram_quad_enable_opcode": 0, + "ram_quad_disable_opcode": 255, + "suppl_ram_quad_disable_opcode": 0, + "ram_octal_enable_opcode": 0, + "suppl_ram_octal_enable_opcode": 0, + "ram_octal_disable_opcode": 0, + "suppl_ram_octal_disable_opcode": 0 + } + } + }, + "external_memory_reporting": { + "header": { + "flash_auto_polling_enable": 1, + "flash_wel_enable": 1, + "flash_write_protect_enable": 0, + "flash_alternate_polling_conf_enable": 0, + "ram_auto_polling_enable": 1, + "ram_wel_enable": 1, + "ram_write_protect_enable": 0, + "ram_alternate_polling_conf_enable": 0 + }, + "flash_auto_polling": { + "flash_polling_repetition_delay": 0, + "flash_polling_count": 4, + "flash_enable_polling_expiration": 0, + "flash_polling_polarity": 0, + "flash_polling_address_phase_enable": 0, + "flash_polling_bit_index": 0, + "flash_numbers_poll_cycles": 65535, + "flash_dummy_autopoll_cycles": 0 + }, + "ram_auto_polling": { + "ram_polling_repetition_delay": 0, + "ram_polling_count": 4, + "ram_enable_polling_expiration": 0, + "ram_polling_polarity": 0, + "ram_polling_address_phase_enable": 0, + "ram_polling_bit_index": 0, + "ram_numbers_poll_cycles": 65535, + "ram_dummy_autopoll_cycles": 0 + }, + "flash_polling_command": { + "flash_polling_opcode": 5, + "suppl_flash_polling_opcode": 0 + }, + "ram_polling_command": { + "ram_polling_opcode": 5, + "suppl_ram_polling_opcode": 0 + }, + "flash_alternate_polling": { + "flash_polling_resp_count": 1023, + "flash_polling_iterations": 1, + "flash_polling_enabled": 0, + "flash_polling_disabled": 0, + "flash_grant_sel": 0, + "flash_data_for_enable_poling_conf_0": 0, + "flash_offset_bits_for_enable_poling_conf_0": 0, + "flash_stop_bit_for_enable_poling_conf_0": 1, + "flash_data_for_enable_poling_conf_1": 0, + "flash_offset_bits_for_enable_poling_conf_1": 0, + "flash_stop_bit_for_enable_poling_conf_1": 1, + "flash_data_for_disable_poling_conf_0": 0, + "flash_offset_bits_for_disable_poling_conf_0": 0, + "flash_stop_bit_for_disable_poling_conf_0": 1, + "flash_data_for_disable_poling_conf_1": 0, + "flash_offset_bits_for_disable_poling_conf_1": 0, + "flash_stop_bit_for_disable_poling_conf_1": 1 + }, + "ram_alternate_polling": { + "ram_polling_resp_count": 1023, + "ram_polling_iterations": 1, + "ram_polling_enabled": 0, + "ram_polling_disabled": 0, + "ram_grant_sel": 0, + "ram_data_for_enable_poling_conf_0": 0, + "ram_offset_bits_for_enable_poling_conf_0": 0, + "ram_stop_bit_for_enable_poling_conf_0": 1, + "ram_data_for_enable_poling_conf_1": 0, + "ram_offset_bits_for_enable_poling_conf_1": 0, + "ram_stop_bit_for_enable_poling_conf_1": 1, + "ram_data_for_disable_poling_conf_0": 0, + "ram_offset_bits_for_disable_poling_conf_0": 0, + "ram_stop_bit_for_disable_poling_conf_0": 1, + "ram_data_for_disable_poling_conf_1": 0, + "ram_offset_bits_for_disable_poling_conf_1": 0, + "ram_stop_bit_for_disable_poling_conf_1": 1 + }, + "flash_wel_command": { + "flash_wel_opcode": 6, + "suppl_flash_wel_opcode": 0 + }, + "ram_wel_command": { + "ram_wel_opcode": 6, + "suppl_ram_wel_opcode": 0 + } + }, + "event": { + "host_nvic_irq": 0, + "core_10_mux_sel": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/py25q32lb/flash_disc_param_ext_mem.json b/boards/ti/lp_em_cc35x1/config/flash/py25q32lb/flash_disc_param_ext_mem.json new file mode 100644 index 000000000000..321810768be1 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/py25q32lb/flash_disc_param_ext_mem.json @@ -0,0 +1,99 @@ +{ + "vendor_primary_sbl": true, + "ti_wsoc_primary_container": true, + "ti_wsoc_bl2_primary_container": true, + "nvs_enable": true, + "vendor_alternate_image": true, + "vendor_sbl_alternate_image": true, + "ti_bl_alternate_image": true, + "ti_wsoc_alternate_image": true, + "ti_wsoc_bl2_alternate_image": true, + "region_0": { + "mem_region_0_start_phy_address": 1069056, + "mem_region_0_end_phy_address": 4194303, + "region0_boot": false, + "region0_main_code": true, + "region0_nvs": false, + "region0_wsoc_code": false, + "region0_alternate_code": false + }, + "region_1": { + "mem_region_1_start_phy_address": 0, + "mem_region_1_end_phy_address": 1069055, + "region1_boot": true, + "region1_main_code": false, + "region1_nvs": true, + "region1_wsoc_code": true, + "region1_alternate_code": false + }, + "region_2": { + "mem_region_2_start_phy_address": 0, + "mem_region_2_end_phy_address": 0, + "region2_boot": false, + "region2_main_code": false, + "region2_nvs": false, + "region2_wsoc_code": false, + "region2_alternate_code": true + }, + "region_3": { + "mem_region_3_start_phy_address": 0, + "mem_region_3_end_phy_address": 0, + "region3_boot": false, + "region3_main_code": false, + "region3_nvs": false, + "region3_wsoc_code": false, + "region3_alternate_code": false + }, + "boot_region_conf": { + "boot_region_size": 0, + "boot_region_flash_disco_param_start_address": 0, + "boot_region_primary_ti_bl_start_phy_address": 12284, + "boot_region_primary_ti_bl_magic": 0, + "boot_region_primary_ti_bl_major": 0, + "boot_region_primary_ti_bl_minor": 0, + "boot_region_sec_ti_bl_start_phy_address": 430076, + "boot_region_sec_ti_bl_magic": 0, + "boot_region_sec_ti_bl_major": 0, + "boot_region_sec_ti_bl_minor": 0 + }, + "main_code_region_conf": { + "main_code_region_vendor_image_start_phy_address": 1073148, + "main_code_region_vendor_image_magic": 0, + "main_code_region_vendor_image_major": 0, + "main_code_region_vendor_image_minor": 0, + "main_code_region_sbl_start_phy_address": 0, + "main_code_region_sbl_magic": 0, + "main_code_region_sbl_major": 0, + "main_code_region_sbl_minor": 0 + }, + "alt_code_region_conf": { + "alt_code_region_vendor_image_start_phy_address": 4194304, + "alt_code_region_vendor_image_magic": 0, + "alt_code_region_vendor_image_major": 0, + "alt_code_region_vendor_image_minor": 0, + "alt_code_region_sbl_start_phy_address": 0, + "alt_code_region_sbl_magic": 0, + "alt_code_region_sbl_major": 0, + "alt_code_region_sbl_minor": 0 + }, + "nvs_code_region_conf": { + "nvs_start_phy_address": 892928, + "nvs_region_size": 176128, + "nvs_region_primary_wsoc_start_phy_address": 430076, + "nvs_region_primary_wsoc_magic": 0, + "nvs_region_primary_wsoc_major": 0, + "nvs_region_primary_wsoc_minor": 0, + "nvs_region_sec_wsoc_start_phy_address": 897020, + "nvs_region_sec_wsoc_magic": 0, + "nvs_region_sec_wsoc_major": 0, + "nvs_region_sec_wsoc_minor": 0, + "nvs_region_primary_wsoc_bl2_start_phy_address": 0, + "nvs_region_primary_wsoc_bl2_magic": 0, + "nvs_region_primary_wsoc_bl2_major": 0, + "nvs_region_primary_wsoc_bl2_minor": 0, + "nvs_region_sec_wsoc_bl2_start_phy_address": 0, + "nvs_region_sec_wsoc_bl2_magic": 0, + "nvs_region_sec_wsoc_bl2_major": 0, + "nvs_region_sec_wsoc_bl2_minor": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/py25q32lb/flash_disc_param_otfde.json b/boards/ti/lp_em_cc35x1/config/flash/py25q32lb/flash_disc_param_otfde.json new file mode 100644 index 000000000000..3cd58d686a45 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/py25q32lb/flash_disc_param_otfde.json @@ -0,0 +1,286 @@ +{ + "otfde_header": { + "name": "OTFDEWFF3", + "flash_only": true, + "ip_protection": false, + "regions_lock": false, + "regions_number": 4, + "flash_enabled": true + }, + "bl_conf": { + "host_boot_done_lock": true, + "host_peripherals_lock": true, + "icache_conf_lock": true, + "m33_mem_part_lock": true, + "memss_firewall_lock": true, + "dma_channel_owner_lock": true, + "otfde_region_lock": true, + "core_events_lock": true + }, + "otfde_general": { + "parameters": { + "mem_otfde_initial_delay": 10, + "otfde_global_watchdog_timer": 5 + }, + "events": { + "reset_evt_mask": false, + "reset_evt_suspend": false, + "sft_reset_evt_mask": false, + "sft_reset_evt_suspend": false, + "bypass_mode_evt_mask": false, + "bypass_mode_evt_suspend": false, + "debug_mode_evt_mask": false, + "debug_mode_evt_suspend": false, + "general_evt_mask": false, + "general_evt_suspend": false, + "xspi_data_path_evt_mask": false, + "xspi_data_path_evt_suspend": false, + "xspi_cnfg_path_evt_mask": false, + "xspi_cnfg_path_evt_suspend": false, + "xspi_service_interrupt_evt_mask": false, + "xspi_service_interrupt_evt_suspend": false, + "trans_device_disabled_evt_mask": false, + "trans_device_disabled_evt_suspend": false, + "trans_region_disabled_evt_mask": false, + "trans_region_disabled_evt_suspend": false, + "trans_region_params_conf_evt_mask": false, + "trans_region_params_conf_evt_suspend": false, + "trans_multiple_regions_mapped_evt_mask": false, + "trans_multiple_regions_mapped_evt_suspend": false, + "trans_address_not_32_bit_evt_mask": false, + "trans_address_not_32_bit_evt_suspend": false, + "trans_size_not_32_bit_evt_mask": false, + "trans_size_not_32_bit_evt_suspend": false, + "trans_burst_not_32_bit_evt_mask": false, + "trans_burst_not_32_bit_evt_suspend": false, + "region_read_write_def_evt_mask": false, + "region_read_write_def_evt_suspend": false, + "suspend_while_disabled_evt_mask": false, + "suspend_while_disabled_evt_suspend": false + } + }, + "regions_settings": { + "region_parameters_lock": { + "REGION_0_PARAMS_0": true, + "REGION_0_PARAMS_1": true, + "REGION_0_PARAMS_2": true, + "REGION_1_PARAMS_0": false, + "REGION_1_PARAMS_1": false, + "REGION_1_PARAMS_2": false, + "REGION_2_PARAMS_0": true, + "REGION_2_PARAMS_1": true, + "REGION_2_PARAMS_2": true, + "REGION_3_PARAMS_0": false, + "REGION_3_PARAMS_1": false, + "REGION_3_PARAMS_2": false + }, + "region_0_protection": { + "mem_region_0_enabled": true, + "mem_region_0_device_id": 0, + "mem_region_0_spi_write_enable": true, + "mem_region_0_spi_read_enable": true, + "mem_region_0_physical_offset": 261, + "mem_region_0_security_id_msb": 0, + "mem_region_0_start_address": 81920, + "mem_region_0_end_address": 82682, + "mem_region_0_security_id_lsb": 0, + "mem_otfde_region_0_write_lock_en": false, + "mem_otfde_region_0_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_1_protection": { + "mem_region_1_enabled": true, + "mem_region_1_device_id": 0, + "mem_region_1_spi_write_enable": true, + "mem_region_1_spi_read_enable": true, + "mem_region_1_physical_offset": 0, + "mem_region_1_security_id_msb": 0, + "mem_region_1_start_address": 655360, + "mem_region_1_end_address": 655620, + "mem_region_1_security_id_lsb": 0, + "mem_otfde_region_1_write_lock_en": false, + "mem_otfde_region_1_enc_dec_bypass": "Bypass" + }, + "region_2_protection": { + "mem_region_2_enabled": false, + "mem_region_2_device_id": 0, + "mem_region_2_spi_write_enable": true, + "mem_region_2_spi_read_enable": true, + "mem_region_2_physical_offset": 0, + "mem_region_2_security_id_msb": 0, + "mem_region_2_start_address": 1, + "mem_region_2_end_address": 0, + "mem_region_2_security_id_lsb": 0, + "mem_otfde_region_2_write_lock_en": false, + "mem_otfde_region_2_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_3_protection": { + "mem_region_3_enabled": false, + "mem_region_3_device_id": 1, + "mem_region_3_spi_write_enable": true, + "mem_region_3_spi_read_enable": true, + "mem_region_3_physical_offset": 0, + "mem_region_3_security_id_msb": 0, + "mem_region_3_start_address": 1, + "mem_region_3_end_address": 0, + "mem_region_3_security_id_lsb": 0, + "mem_otfde_region_3_write_lock_en": false, + "mem_otfde_region_3_enc_dec_bypass": "Bypass" + } + }, + "devices": { + "header": { + "flash_device_switch_conf": 1, + "ram_device_switch_conf": 1 + }, + "flash_switch": { + "flash_grant_sel": 0, + "flash_data_for_conf_0": 2181562505, + "flash_offset_bits_for_conf_0": 0, + "flash_stop_bit_for_conf_0": 0, + "flash_data_for_conf_1": 167911947, + "flash_offset_bits_for_conf_1": 1, + "flash_stop_bit_for_conf_1": 0, + "flash_data_for_conf_2": 139266, + "flash_offset_bits_for_conf_2": 2, + "flash_stop_bit_for_conf_2": 0, + "flash_data_for_conf_3": 1, + "flash_offset_bits_for_conf_3": 4, + "flash_stop_bit_for_conf_3": 0, + "flash_data_for_conf_4": 1076887634, + "flash_offset_bits_for_conf_4": 45, + "flash_stop_bit_for_conf_4": 0, + "flash_data_for_conf_5": 3224371282, + "flash_offset_bits_for_conf_5": 45, + "flash_stop_bit_for_conf_5": 0, + "flash_data_for_conf_6": 262149, + "flash_offset_bits_for_conf_6": 14, + "flash_stop_bit_for_conf_6": 0, + "flash_data_for_conf_7": 0, + "flash_offset_bits_for_conf_7": 44, + "flash_stop_bit_for_conf_7": 1, + "flash_data_for_conf_8": 0, + "flash_offset_bits_for_conf_8": 0, + "flash_stop_bit_for_conf_8": 1, + "flash_data_for_conf_9": 0, + "flash_offset_bits_for_conf_9": 0, + "flash_stop_bit_for_conf_9": 1, + "flash_data_for_conf_10": 0, + "flash_offset_bits_for_conf_10": 0, + "flash_stop_bit_for_conf_10": 1, + "flash_data_for_conf_11": 0, + "flash_offset_bits_for_conf_11": 0, + "flash_stop_bit_for_conf_11": 1, + "flash_data_for_conf_12": 0, + "flash_offset_bits_for_conf_12": 0, + "flash_stop_bit_for_conf_12": 1, + "flash_data_for_conf_13": 0, + "flash_offset_bits_for_conf_13": 0, + "flash_stop_bit_for_conf_13": 1, + "flash_data_for_conf_14": 0, + "flash_offset_bits_for_conf_14": 0, + "flash_stop_bit_for_conf_14": 1, + "flash_data_for_conf_15": 0, + "flash_offset_bits_for_conf_15": 0, + "flash_stop_bit_for_conf_15": 1, + "flash_data_for_conf_16": 0, + "flash_offset_bits_for_conf_16": 0, + "flash_stop_bit_for_conf_16": 1, + "flash_data_for_conf_17": 0, + "flash_offset_bits_for_conf_17": 0, + "flash_stop_bit_for_conf_17": 1, + "flash_data_for_conf_18": 0, + "flash_offset_bits_for_conf_18": 0, + "flash_stop_bit_for_conf_18": 1, + "flash_data_for_conf_19": 0, + "flash_offset_bits_for_conf_19": 0, + "flash_stop_bit_for_conf_19": 1, + "flash_data_for_conf_20": 0, + "flash_offset_bits_for_conf_20": 0, + "flash_stop_bit_for_conf_20": 1, + "flash_data_for_conf_21": 0, + "flash_offset_bits_for_conf_21": 0, + "flash_stop_bit_for_conf_21": 1, + "flash_data_for_conf_22": 0, + "flash_offset_bits_for_conf_22": 0, + "flash_stop_bit_for_conf_22": 1, + "flash_data_for_conf_23": 0, + "flash_offset_bits_for_conf_23": 0, + "flash_stop_bit_for_conf_23": 1 + }, + "ram_switch": { + "ram_grant_sel": 0, + "ram_data_for_conf_0": 2181562505, + "ram_offset_bits_for_conf_0": 0, + "ram_stop_bit_for_conf_0": 0, + "ram_data_for_conf_1": 67248651, + "ram_offset_bits_for_conf_1": 1, + "ram_stop_bit_for_conf_1": 0, + "ram_data_for_conf_2": 139266, + "ram_offset_bits_for_conf_2": 2, + "ram_stop_bit_for_conf_2": 0, + "ram_data_for_conf_3": 1, + "ram_offset_bits_for_conf_3": 4, + "ram_stop_bit_for_conf_3": 0, + "ram_data_for_conf_4": 1076887634, + "ram_offset_bits_for_conf_4": 45, + "ram_stop_bit_for_conf_4": 0, + "ram_data_for_conf_5": 3224371282, + "ram_offset_bits_for_conf_5": 45, + "ram_stop_bit_for_conf_5": 0, + "ram_data_for_conf_6": 262149, + "ram_offset_bits_for_conf_6": 14, + "ram_stop_bit_for_conf_6": 0, + "ram_data_for_conf_7": 0, + "ram_offset_bits_for_conf_7": 44, + "ram_stop_bit_for_conf_7": 1, + "ram_data_for_conf_8": 0, + "ram_offset_bits_for_conf_8": 0, + "ram_stop_bit_for_conf_8": 1, + "ram_data_for_conf_9": 0, + "ram_offset_bits_for_conf_9": 0, + "ram_stop_bit_for_conf_9": 1, + "ram_data_for_conf_10": 0, + "ram_offset_bits_for_conf_10": 0, + "ram_stop_bit_for_conf_10": 1, + "ram_data_for_conf_11": 0, + "ram_offset_bits_for_conf_11": 0, + "ram_stop_bit_for_conf_11": 1, + "ram_data_for_conf_12": 0, + "ram_offset_bits_for_conf_12": 0, + "ram_stop_bit_for_conf_12": 1, + "ram_data_for_conf_13": 0, + "ram_offset_bits_for_conf_13": 0, + "ram_stop_bit_for_conf_13": 1, + "ram_data_for_conf_14": 0, + "ram_offset_bits_for_conf_14": 0, + "ram_stop_bit_for_conf_14": 1, + "ram_data_for_conf_15": 0, + "ram_offset_bits_for_conf_15": 0, + "ram_stop_bit_for_conf_15": 1, + "ram_data_for_conf_16": 0, + "ram_offset_bits_for_conf_16": 0, + "ram_stop_bit_for_conf_16": 1, + "ram_data_for_conf_17": 0, + "ram_offset_bits_for_conf_17": 0, + "ram_stop_bit_for_conf_17": 1, + "ram_data_for_conf_18": 0, + "ram_offset_bits_for_conf_18": 0, + "ram_stop_bit_for_conf_18": 1, + "ram_data_for_conf_19": 0, + "ram_offset_bits_for_conf_19": 0, + "ram_stop_bit_for_conf_19": 1, + "ram_data_for_conf_20": 0, + "ram_offset_bits_for_conf_20": 0, + "ram_stop_bit_for_conf_20": 1, + "ram_data_for_conf_21": 0, + "ram_offset_bits_for_conf_21": 0, + "ram_stop_bit_for_conf_21": 1, + "ram_data_for_conf_22": 0, + "ram_offset_bits_for_conf_22": 0, + "ram_stop_bit_for_conf_22": 1, + "ram_data_for_conf_23": 0, + "ram_offset_bits_for_conf_23": 0, + "ram_stop_bit_for_conf_23": 1 + } + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/py25q32lb/flash_disc_param_xspi.json b/boards/ti/lp_em_cc35x1/config/flash/py25q32lb/flash_disc_param_xspi.json new file mode 100644 index 000000000000..4e40e5c6e041 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/py25q32lb/flash_disc_param_xspi.json @@ -0,0 +1,485 @@ +{ + "xspi_header": { + "name": "xSPIWFF3", + "device": "CC3500", + "use_hardware": "PY25Q32LB", + "use_case": "Quadro", + "dqs_support": 0, + "flash_only": 1, + "flash_separate_reset": 0, + "ram_separate_reset": true, + "clock_frequency": 80, + "qospi_clock_divider": 1, + "flash_device_character_conf": 0, + "ram_device_character_conf": 0, + "header_advanced": 0, + "phy_mode_enable": 1, + "pipeline_mode_enable": 1, + "loopback_support": "No", + "qspi_ref_clock": 80, + "spi_clock_freq": 20, + "spi_clock_divider": 1, + "flash_device_size": 4, + "flash_bytes_per_block": 16, + "flash_bytes_per_page": 256, + "flash_number_of_address_bytes": 3, + "flash_dual_opcode": 0, + "flash_jedec_manufacturer_id": 0, + "flash_jedec_device_id": 0, + "flash_name": "PY25Q32LB", + "flash_page_size": 256, + "flash_sector_size": 4096, + "flash_cs_polarity": "ACTIVE_LOW", + "flash_sw_reset_type": "x1xxxx", + "ram_device_size": 4, + "ram_bytes_per_block": 16, + "ram_bytes_per_page": 256, + "ram_number_of_address_bytes": 3, + "ram_dual_opcode": 0, + "ram_jedec_manufacturer_id": 0, + "ram_jedec_device_id": 0, + "ram_name": "NO_PSRAM", + "ram_page_size": 256, + "ram_sector_size": 4096, + "ram_cs_polarity": "ACTIVE_LOW", + "ram_sw_reset_type": "x1xxxx", + "flash_write_operation_modes": "4S-4S-4S", + "flash_read_operation_modes": "4S-4S-4S", + "ram_write_operation_modes": "4S-4S-4S", + "ram_read_operation_modes": "4S-4S-4S", + "crc_enable": 0, + "enable_dtr": 0, + "enable_ahb_decoder": 0, + "enter_xip_mod_immediately": 0, + "enter_xip_mod_next_read": 0, + "ahb_address_remapping": 0, + "enable_dma": 0, + "select_decode": 0, + "legacy_ip_mode": 0, + "direct_access": 1 + }, + "xspi_pinmux": { + "xspi_clk_input": 44, + "xspi_clk_input_use_hw": 0, + "xspi_clk_input_mode": "Input", + "xspi_clk_input_pull": "None", + "xspi_clk_input_interrupt_trigger": "Low", + "xspi_clk_input_dont_conf": 0, + "xspi_clk_input_output_strength": "High", + "xspi_clk_input_initial_output_state": "High", + "xspi_clk": 24, + "xspi_clk_use_hw": "None", + "xspi_clk_mode": "Output", + "xspi_clk_pull": "None", + "xspi_clk_output_strength": "High", + "xspi_clk_initial_output_state": "High", + "xspi_clk_interrupt_trigger": "None", + "xspi_clk_dont_conf": 0, + "xspi_flash_cs": 20, + "xspi_flash_cs_use_hw": "None", + "xspi_flash_cs_mode": "Output", + "xspi_flash_cs_pull": "None", + "xspi_flash_cs_output_strength": "High", + "xspi_flash_cs_initial_output_state": "High", + "xspi_flash_cs_interrupt_trigger": "None", + "xspi_flash_cs_dont_conf": 0, + "xspi_data_0": 25, + "xspi_data_0_use_hw": "None", + "xspi_data_0_mode": "Input", + "xspi_data_0_pull": "None", + "xspi_data_0_output_strength": "High", + "xspi_data_0_initial_output_state": "High", + "xspi_data_0_interrupt_trigger": "Low", + "xspi_data_0_dont_conf": 0, + "xspi_data_1": 21, + "xspi_data_1_use_hw": "None", + "xspi_data_1_mode": "Input", + "xspi_data_1_pull": "None", + "xspi_data_1_output_strength": "High", + "xspi_data_1_initial_output_state": "High", + "xspi_data_1_interrupt_trigger": "Low", + "xspi_data_1_dont_conf": 0, + "xspi_data_2": 22, + "xspi_data_2_use_hw": "None", + "xspi_data_2_mode": "Input", + "xspi_data_2_pull": "None", + "xspi_data_2_output_strength": "High", + "xspi_data_2_initial_output_state": "High", + "xspi_data_2_interrupt_trigger": "Low", + "xspi_data_2_dont_conf": 0, + "xspi_data_3": 23, + "xspi_data_3_use_hw": "None", + "xspi_data_3_mode": "Input", + "xspi_data_3_pull": "None", + "xspi_data_3_output_strength": "High", + "xspi_data_3_initial_output_state": "High", + "xspi_data_3_interrupt_trigger": "Low", + "xspi_data_3_dont_conf": 0, + "xspi_data_4": 26, + "xspi_data_4_use_hw": "None", + "xspi_data_4_mode": "Input", + "xspi_data_4_pull": "None", + "xspi_data_4_output_strength": "High", + "xspi_data_4_initial_output_state": "High", + "xspi_data_4_interrupt_trigger": "None", + "xspi_data_4_dont_conf": 0, + "xspi_data_5": 27, + "xspi_data_5_use_hw": "None", + "xspi_data_5_mode": "Input", + "xspi_data_5_pull": "None", + "xspi_data_5_output_strength": "High", + "xspi_data_5_initial_output_state": "High", + "xspi_data_5_interrupt_trigger": "None", + "xspi_data_5_dont_conf": 0, + "xspi_data_6": 28, + "xspi_data_6_use_hw": "None", + "xspi_data_6_mode": "Input", + "xspi_data_6_pull": "None", + "xspi_data_6_output_strength": "High", + "xspi_data_6_initial_output_state": "High", + "xspi_data_6_interrupt_trigger": "None", + "xspi_data_6_dont_conf": 0, + "xspi_data_7": 29, + "xspi_data_7_use_hw": "None", + "xspi_data_7_mode": "Input", + "xspi_data_7_pull": "None", + "xspi_data_7_output_strength": "High", + "xspi_data_7_initial_output_state": "High", + "xspi_data_7_interrupt_trigger": "None", + "xspi_data_7_dont_conf": 0, + "xspi_reset_flash": 36, + "xspi_reset_flash_use_hw": "None", + "xspi_reset_flash_mode": "Output", + "xspi_reset_flash_pull": "None", + "xspi_reset_flash_output_strength": "High", + "xspi_reset_flash_initial_output_state": "High", + "xspi_reset_flash_interrupt_trigger": "None", + "xspi_reset_flash_dont_conf": 0, + "xspi_cs_ram": 3, + "xspi_cs_ram_use_hw": "None", + "xspi_cs_ram_mode": "Output", + "xspi_cs_ram_pull": "None", + "xspi_cs_ram_output_strength": "High", + "xspi_cs_ram_initial_output_state": "High", + "xspi_cs_ram_interrupt_trigger": "None", + "xspi_cs_ram_dont_conf": 0, + "xspi_dqs": 30, + "xspi_dqs_use_hw": "None", + "xspi_dqs_mode": "Input", + "xspi_dqs_pull": "None", + "xspi_dqs_output_strength": "High", + "xspi_dqs_initial_output_state": "High", + "xspi_dqs_interrupt_trigger": "None", + "xspi_dqs_dont_conf": 0, + "xspi_reset_ram": 2, + "xspi_reset_ram_use_hw": "None", + "xspi_reset_ram_mode": "Input", + "xspi_reset_ram_pull": "None", + "xspi_reset_ram_output_strength": "High", + "xspi_reset_ram_initial_output_state": "High", + "xspi_reset_ram_interrupt_trigger": "None", + "xspi_reset_ram_dont_conf": 0 + }, + "xspi_operations": { + "xspi_operations_clocks": { + "clock_phase": 0, + "clock_polarity": 0, + "spi_mode": "2'b00" + }, + "xspi_operations_chip_select": { + "csda": 2, + "csdads": 0, + "cseot": 4, + "cssot": 1 + }, + "xspi_operations_reset": { + "flash_jedec_reset": 0, + "ram_jedec_reset": 0, + "flash_treset": 20, + "ram_treset": 20 + }, + "xspi_phy_operations": { + "flash_rx_dll_bypass_bit": 0, + "flash_dll_tx_delay": 22, + "flash_dll_rx_delay": 34, + "ram_rx_dll_bypass_bit": 0, + "ram_dll_tx_delay": 22, + "ram_dll_rx_delay": 34 + }, + "xspi_read_operations": { + "flash_dummy_rd_cycles": 10, + "flash_read_opcode": 11, + "suppl_flash_read_opcode": 0, + "ram_dummy_rd_cycles": 10, + "ram_read_opcode": 11, + "suppl_ram_read_opcode": 0, + "flash_non_cont_read_enable": 0, + "flash_max_read_jobs": 256, + "ram_non_cont_read_enable": 0, + "ram_max_read_jobs": 256, + "rww_en": 0, + "device_size": 4, + "number_of_banks": 1, + "bank_size": 4, + "mode_bit_enable": 0 + }, + "xspi_write_operations": { + "flash_address_and_data": { + "flash_dummy_wr_cycles": 0 + }, + "flash_command": { + "flash_write_opcode": 2, + "suppl_flash_write_opcode": 0 + }, + "ram_address_and_data": { + "ram_dummy_wr_cycles": 0 + }, + "ram_command": { + "ram_write_opcode": 2, + "suppl_ram_write_opcode": 0 + }, + "write_to_buffer": { + "flash_write_to_buffer_support": 0, + "ram_write_to_buffer_support": 0 + }, + "non_continuous_write": { + "flash_non_cont_write_enable": 0, + "flash_max_write_jobs": 64, + "ram_non_cont_write_enable": 0, + "ram_max_write_jobs": 0 + }, + "flash_program_operation": { + "flash_min_program_size": "256 B", + "flash_program_opcode": 2, + "suppl_flash_program_opcode": 0, + "flash_maximum_program_time_limit": 1600 + }, + "flash_erase_operation": { + "flash_min_erase_size": "4 kB", + "flash_erase_opcode": 32, + "suppl_flash_erase_opcode": 0, + "flash_maximum_erase_time_limit": 4095 + }, + "flash_erase_conf": { + "flash_block_erase_opcode": 0, + "suppl_block_flash_erase_opcode": 0, + "flash_sector_erase_opcode": 0, + "suppl_sector_flash_erase_opcode": 0, + "flash_chip_erase_opcode": 0, + "suppl_chip_flash_erase_opcode": 0 + }, + "ram_program_operation": { + "ram_min_program_size": "256 B", + "ram_program_opcode": 2, + "suppl_ram_program_opcode": 0, + "ram_maximum_program_time_limit": 1600 + }, + "ram_erase_conf": { + "ram_block_erase_opcode": 0, + "suppl_block_ram_erase_opcode": 0, + "ram_sector_erase_opcode": 0, + "suppl_sector_ram_erase_opcode": 0, + "ram_chip_erase_opcode": 0, + "suppl_chip_ram_erase_opcode": 0 + }, + "flash_buffer_support": { + "flash_pre_write_sequence": 0, + "flash_post_write_sequence": 0, + "flash_write_protection_timer_en": 0, + "flash_write_buffer_timer_mode": 16, + "flash_write_buffer_timer_range": 0, + "flash_service_interrupt_criteria": 0 + }, + "ram_buffer_support": { + "ram_pre_write_sequence": 0, + "ram_post_write_sequence": 0, + "ram_write_protection_timer_en": 0, + "ram_write_buffer_timer_mode": 16, + "ram_write_buffer_timer_range": 0, + "ram_service_interrupt_criteria": 0 + }, + "flash_pre_write_conf": { + "flash_pre_write_job_done_grant_sel": 0, + "data_for_flash_pre_write_conf_0": 0, + "offset_bits_for_flash_pre_write_conf_0": 0, + "stop_bit_for_flash_pre_write_conf_0": 1, + "data_for_flash_pre_write_conf_1": 0, + "offset_bits_for_flash_pre_write_conf_1": 0 + }, + "flash_post_write_conf": { + "flash_post_write_job_done_grant_sel": 0, + "data_for_flash_post_write_conf_0": 0, + "offset_bits_for_flash_post_write_conf_0": 0, + "stop_bit_for_flash_post_write_conf_0": 1, + "data_for_flash_post_write_conf_1": 0, + "offset_bits_for_flash_post_write_conf_1": 0 + }, + "ram_pre_write_conf": { + "ram_pre_write_job_done_grant_sel": 0, + "data_for_ram_pre_write_conf_0": 0, + "offset_bits_for_ram_pre_write_conf_0": 0, + "stop_bit_for_ram_pre_write_conf_0": 1, + "data_for_ram_pre_write_conf_1": 0, + "offset_bits_for_ram_pre_write_conf_1": 0 + }, + "ram_post_write_conf": { + "ram_post_write_job_done_grant_sel": 0, + "data_for_ram_post_write_conf_0": 0, + "offset_bits_for_ram_post_write_conf_0": 0, + "stop_bit_for_ram_post_write_conf_0": 1, + "data_for_ram_post_write_conf_1": 0, + "offset_bits_for_ram_post_write_conf_1": 0 + } + }, + "xspi_capture_operations": { + "read_data_capture": { + "flash_delay_transmitted_data": 0, + "flash_loopback_clock": 0, + "flash_bypass_adapted_loopback": 1, + "flash_sample_edge_sel": 0, + "ram_delay_transmitted_data": 0, + "ram_loopback_clock": 0, + "ram_bypass_adapted_loopback": 1, + "ram_sample_edge_sel": 0 + }, + "delays": { + "flash_full_half_cycle_delay": 0, + "flash_dll_bypass_mode": 1, + "flash_phase_detect_sel": 0, + "flash_dll_lock_num": 0, + "flash_dll_start_point": 0, + "flash_loopback_clock": 0, + "ram_full_half_cycle_delay": 0, + "ram_dll_bypass_mode": 1, + "ram_phase_detect_sel": 0, + "ram_dll_lock_num": 0, + "ram_dll_start_point": 0, + "ram_loopback_clock": 0 + }, + "operation_modes": { + "flash_sfdp_support": 0, + "ram_sfdp_support": 0, + "flash_pm_support": 0, + "ram_pm_support": 0, + "flash_sfdp_opcode": 0, + "suppl_flash_sfdp_opcode": 0, + "ram_sfdp_opcode": 0, + "suppl_ram_sfdp_opcode": 0, + "flash_enter_dpd_opcode": 185, + "suppl_flash_enter_dpd_opcode": 0, + "flash_exit_dpd_opcode": 171, + "suppl_flash_exit_dpd_opcode": 0, + "ram_enter_dpd_opcode": 185, + "suppl_ram_enter_dpd_opcode": 0, + "ram_exit_dpd_opcode": 171, + "suppl_ram_exit_dpd_opcode": 0, + "flash_quad_enable_opcode": 56, + "suppl_flash_quad_enable_opcode": 0, + "flash_quad_disable_opcode": 255, + "suppl_flash_quad_disable_opcode": 0, + "flash_octal_enable_opcode": 0, + "suppl_flash_octal_enable_opcode": 0, + "flash_octal_disable_opcode": 0, + "suppl_flash_octal_disable_opcode": 0, + "ram_quad_enable_opcode": 56, + "suppl_ram_quad_enable_opcode": 0, + "ram_quad_disable_opcode": 255, + "suppl_ram_quad_disable_opcode": 0, + "ram_octal_enable_opcode": 0, + "suppl_ram_octal_enable_opcode": 0, + "ram_octal_disable_opcode": 0, + "suppl_ram_octal_disable_opcode": 0 + } + } + }, + "external_memory_reporting": { + "header": { + "flash_auto_polling_enable": 1, + "flash_wel_enable": 1, + "flash_write_protect_enable": 0, + "flash_alternate_polling_conf_enable": 0, + "ram_auto_polling_enable": 1, + "ram_wel_enable": 1, + "ram_write_protect_enable": 0, + "ram_alternate_polling_conf_enable": 0 + }, + "flash_auto_polling": { + "flash_polling_repetition_delay": 0, + "flash_polling_count": 4, + "flash_enable_polling_expiration": 0, + "flash_polling_polarity": 0, + "flash_polling_address_phase_enable": 0, + "flash_polling_bit_index": 0, + "flash_numbers_poll_cycles": 65535, + "flash_dummy_autopoll_cycles": 0 + }, + "ram_auto_polling": { + "ram_polling_repetition_delay": 0, + "ram_polling_count": 4, + "ram_enable_polling_expiration": 0, + "ram_polling_polarity": 0, + "ram_polling_address_phase_enable": 0, + "ram_polling_bit_index": 0, + "ram_numbers_poll_cycles": 65535, + "ram_dummy_autopoll_cycles": 0 + }, + "flash_polling_command": { + "flash_polling_opcode": 5, + "suppl_flash_polling_opcode": 0 + }, + "ram_polling_command": { + "ram_polling_opcode": 5, + "suppl_ram_polling_opcode": 0 + }, + "flash_alternate_polling": { + "flash_polling_resp_count": 1023, + "flash_polling_iterations": 1, + "flash_polling_enabled": 0, + "flash_polling_disabled": 0, + "flash_grant_sel": 0, + "flash_data_for_enable_poling_conf_0": 0, + "flash_offset_bits_for_enable_poling_conf_0": 0, + "flash_stop_bit_for_enable_poling_conf_0": 1, + "flash_data_for_enable_poling_conf_1": 0, + "flash_offset_bits_for_enable_poling_conf_1": 0, + "flash_stop_bit_for_enable_poling_conf_1": 1, + "flash_data_for_disable_poling_conf_0": 0, + "flash_offset_bits_for_disable_poling_conf_0": 0, + "flash_stop_bit_for_disable_poling_conf_0": 1, + "flash_data_for_disable_poling_conf_1": 0, + "flash_offset_bits_for_disable_poling_conf_1": 0, + "flash_stop_bit_for_disable_poling_conf_1": 1 + }, + "ram_alternate_polling": { + "ram_polling_resp_count": 1023, + "ram_polling_iterations": 1, + "ram_polling_enabled": 0, + "ram_polling_disabled": 0, + "ram_grant_sel": 0, + "ram_data_for_enable_poling_conf_0": 0, + "ram_offset_bits_for_enable_poling_conf_0": 0, + "ram_stop_bit_for_enable_poling_conf_0": 1, + "ram_data_for_enable_poling_conf_1": 0, + "ram_offset_bits_for_enable_poling_conf_1": 0, + "ram_stop_bit_for_enable_poling_conf_1": 1, + "ram_data_for_disable_poling_conf_0": 0, + "ram_offset_bits_for_disable_poling_conf_0": 0, + "ram_stop_bit_for_disable_poling_conf_0": 1, + "ram_data_for_disable_poling_conf_1": 0, + "ram_offset_bits_for_disable_poling_conf_1": 0, + "ram_stop_bit_for_disable_poling_conf_1": 1 + }, + "flash_wel_command": { + "flash_wel_opcode": 6, + "suppl_flash_wel_opcode": 0 + }, + "ram_wel_command": { + "ram_wel_opcode": 6, + "suppl_ram_wel_opcode": 0 + } + }, + "event": { + "host_nvic_irq": 0, + "core_10_mux_sel": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/py25q64lb/flash_disc_param_ext_mem.json b/boards/ti/lp_em_cc35x1/config/flash/py25q64lb/flash_disc_param_ext_mem.json new file mode 100644 index 000000000000..6585853ccd5e --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/py25q64lb/flash_disc_param_ext_mem.json @@ -0,0 +1,99 @@ +{ + "vendor_primary_sbl": true, + "ti_wsoc_primary_container": true, + "ti_wsoc_bl2_primary_container": true, + "nvs_enable": true, + "vendor_alternate_image": true, + "vendor_sbl_alternate_image": true, + "ti_bl_alternate_image": true, + "ti_wsoc_alternate_image": true, + "ti_wsoc_bl2_alternate_image": true, + "region_0": { + "mem_region_0_start_phy_address": 2867200, + "mem_region_0_end_phy_address": 5627903, + "region0_boot": false, + "region0_main_code": true, + "region0_nvs": false, + "region0_wsoc_code": false, + "region0_alternate_code": false + }, + "region_1": { + "mem_region_1_start_phy_address": 0, + "mem_region_1_end_phy_address": 2867199, + "region1_boot": true, + "region1_main_code": false, + "region1_nvs": true, + "region1_wsoc_code": true, + "region1_alternate_code": false + }, + "region_2": { + "mem_region_2_start_phy_address": 5627904, + "mem_region_2_end_phy_address": 8388607, + "region2_boot": false, + "region2_main_code": false, + "region2_nvs": false, + "region2_wsoc_code": false, + "region2_alternate_code": true + }, + "region_3": { + "mem_region_3_start_phy_address": 0, + "mem_region_3_end_phy_address": 0, + "region3_boot": false, + "region3_main_code": false, + "region3_nvs": false, + "region3_wsoc_code": false, + "region3_alternate_code": false + }, + "boot_region_conf": { + "boot_region_size": 0, + "boot_region_flash_disco_param_start_address": 0, + "boot_region_primary_ti_bl_start_phy_address": 12284, + "boot_region_primary_ti_bl_magic": 0, + "boot_region_primary_ti_bl_major": 0, + "boot_region_primary_ti_bl_minor": 0, + "boot_region_sec_ti_bl_start_phy_address": 430076, + "boot_region_sec_ti_bl_magic": 0, + "boot_region_sec_ti_bl_major": 0, + "boot_region_sec_ti_bl_minor": 0 + }, + "main_code_region_conf": { + "main_code_region_vendor_image_start_phy_address": 2871292, + "main_code_region_vendor_image_magic": 0, + "main_code_region_vendor_image_major": 0, + "main_code_region_vendor_image_minor": 0, + "main_code_region_sbl_start_phy_address": 0, + "main_code_region_sbl_magic": 0, + "main_code_region_sbl_major": 0, + "main_code_region_sbl_minor": 0 + }, + "alt_code_region_conf": { + "alt_code_region_vendor_image_start_phy_address": 5631996, + "alt_code_region_vendor_image_magic": 0, + "alt_code_region_vendor_image_major": 0, + "alt_code_region_vendor_image_minor": 0, + "alt_code_region_sbl_start_phy_address": 0, + "alt_code_region_sbl_magic": 0, + "alt_code_region_sbl_major": 0, + "alt_code_region_sbl_minor": 0 + }, + "nvs_code_region_conf": { + "nvs_start_phy_address": 1777664, + "nvs_region_size": 1089536, + "nvs_region_primary_wsoc_start_phy_address": 847868, + "nvs_region_primary_wsoc_magic": 0, + "nvs_region_primary_wsoc_major": 0, + "nvs_region_primary_wsoc_minor": 0, + "nvs_region_sec_wsoc_start_phy_address": 1314812, + "nvs_region_sec_wsoc_magic": 0, + "nvs_region_sec_wsoc_major": 0, + "nvs_region_sec_wsoc_minor": 0, + "nvs_region_primary_wsoc_bl2_start_phy_address": 0, + "nvs_region_primary_wsoc_bl2_magic": 0, + "nvs_region_primary_wsoc_bl2_major": 0, + "nvs_region_primary_wsoc_bl2_minor": 0, + "nvs_region_sec_wsoc_bl2_start_phy_address": 0, + "nvs_region_sec_wsoc_bl2_magic": 0, + "nvs_region_sec_wsoc_bl2_major": 0, + "nvs_region_sec_wsoc_bl2_minor": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/py25q64lb/flash_disc_param_otfde.json b/boards/ti/lp_em_cc35x1/config/flash/py25q64lb/flash_disc_param_otfde.json new file mode 100644 index 000000000000..b361706e76c1 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/py25q64lb/flash_disc_param_otfde.json @@ -0,0 +1,286 @@ +{ + "otfde_header": { + "name": "OTFDEWFF3", + "flash_only": true, + "ip_protection": false, + "regions_lock": false, + "regions_number": 4, + "flash_enabled": true + }, + "bl_conf": { + "host_boot_done_lock": true, + "host_peripherals_lock": true, + "icache_conf_lock": true, + "m33_mem_part_lock": true, + "memss_firewall_lock": true, + "dma_channel_owner_lock": true, + "otfde_region_lock": true, + "core_events_lock": true + }, + "otfde_general": { + "parameters": { + "mem_otfde_initial_delay": 10, + "otfde_global_watchdog_timer": 5 + }, + "events": { + "reset_evt_mask": false, + "reset_evt_suspend": false, + "sft_reset_evt_mask": false, + "sft_reset_evt_suspend": false, + "bypass_mode_evt_mask": false, + "bypass_mode_evt_suspend": false, + "debug_mode_evt_mask": false, + "debug_mode_evt_suspend": false, + "general_evt_mask": false, + "general_evt_suspend": false, + "xspi_data_path_evt_mask": false, + "xspi_data_path_evt_suspend": false, + "xspi_cnfg_path_evt_mask": false, + "xspi_cnfg_path_evt_suspend": false, + "xspi_service_interrupt_evt_mask": false, + "xspi_service_interrupt_evt_suspend": false, + "trans_device_disabled_evt_mask": false, + "trans_device_disabled_evt_suspend": false, + "trans_region_disabled_evt_mask": false, + "trans_region_disabled_evt_suspend": false, + "trans_region_params_conf_evt_mask": false, + "trans_region_params_conf_evt_suspend": false, + "trans_multiple_regions_mapped_evt_mask": false, + "trans_multiple_regions_mapped_evt_suspend": false, + "trans_address_not_32_bit_evt_mask": false, + "trans_address_not_32_bit_evt_suspend": false, + "trans_size_not_32_bit_evt_mask": false, + "trans_size_not_32_bit_evt_suspend": false, + "trans_burst_not_32_bit_evt_mask": false, + "trans_burst_not_32_bit_evt_suspend": false, + "region_read_write_def_evt_mask": false, + "region_read_write_def_evt_suspend": false, + "suspend_while_disabled_evt_mask": false, + "suspend_while_disabled_evt_suspend": false + } + }, + "regions_settings": { + "region_parameters_lock": { + "REGION_0_PARAMS_0": true, + "REGION_0_PARAMS_1": true, + "REGION_0_PARAMS_2": true, + "REGION_1_PARAMS_0": false, + "REGION_1_PARAMS_1": false, + "REGION_1_PARAMS_2": false, + "REGION_2_PARAMS_0": true, + "REGION_2_PARAMS_1": true, + "REGION_2_PARAMS_2": true, + "REGION_3_PARAMS_0": false, + "REGION_3_PARAMS_1": false, + "REGION_3_PARAMS_2": false + }, + "region_0_protection": { + "mem_region_0_enabled": true, + "mem_region_0_device_id": 0, + "mem_region_0_spi_write_enable": true, + "mem_region_0_spi_read_enable": true, + "mem_region_0_physical_offset": 700, + "mem_region_0_security_id_msb": 0, + "mem_region_0_start_address": 81920, + "mem_region_0_end_address": 82593, + "mem_region_0_security_id_lsb": 0, + "mem_otfde_region_0_write_lock_en": false, + "mem_otfde_region_0_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_1_protection": { + "mem_region_1_enabled": true, + "mem_region_1_device_id": 0, + "mem_region_1_spi_write_enable": true, + "mem_region_1_spi_read_enable": true, + "mem_region_1_physical_offset": 0, + "mem_region_1_security_id_msb": 0, + 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"mem_region_3_security_id_lsb": 0, + "mem_otfde_region_3_write_lock_en": false, + "mem_otfde_region_3_enc_dec_bypass": "Bypass" + } + }, + "devices": { + "header": { + "flash_device_switch_conf": 1, + "ram_device_switch_conf": 1 + }, + "flash_switch": { + "flash_grant_sel": 0, + "flash_data_for_conf_0": 2181562505, + "flash_offset_bits_for_conf_0": 0, + "flash_stop_bit_for_conf_0": 0, + "flash_data_for_conf_1": 167911947, + "flash_offset_bits_for_conf_1": 1, + "flash_stop_bit_for_conf_1": 0, + "flash_data_for_conf_2": 139266, + "flash_offset_bits_for_conf_2": 2, + "flash_stop_bit_for_conf_2": 0, + "flash_data_for_conf_3": 1, + "flash_offset_bits_for_conf_3": 4, + "flash_stop_bit_for_conf_3": 0, + "flash_data_for_conf_4": 1076887634, + "flash_offset_bits_for_conf_4": 45, + "flash_stop_bit_for_conf_4": 0, + "flash_data_for_conf_5": 3224371282, + "flash_offset_bits_for_conf_5": 45, + "flash_stop_bit_for_conf_5": 0, + "flash_data_for_conf_6": 262149, + "flash_offset_bits_for_conf_6": 14, + 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"ram_offset_bits_for_conf_21": 0, + "ram_stop_bit_for_conf_21": 1, + "ram_data_for_conf_22": 0, + "ram_offset_bits_for_conf_22": 0, + "ram_stop_bit_for_conf_22": 1, + "ram_data_for_conf_23": 0, + "ram_offset_bits_for_conf_23": 0, + "ram_stop_bit_for_conf_23": 1 + } + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/py25q64lb/flash_disc_param_xspi.json b/boards/ti/lp_em_cc35x1/config/flash/py25q64lb/flash_disc_param_xspi.json new file mode 100644 index 000000000000..90b40802d176 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/py25q64lb/flash_disc_param_xspi.json @@ -0,0 +1,485 @@ +{ + "xspi_header": { + "name": "xSPIWFF3", + "device": "CC3500", + "use_hardware": "PY25Q64LB", + "use_case": "Quadro", + "dqs_support": 0, + "flash_only": 1, + "flash_separate_reset": 0, + "ram_separate_reset": true, + "clock_frequency": 80, + "qospi_clock_divider": 1, + "flash_device_character_conf": 0, + "ram_device_character_conf": 0, + "header_advanced": 0, + "phy_mode_enable": 1, + "pipeline_mode_enable": 1, + "loopback_support": "No", + "qspi_ref_clock": 80, + "spi_clock_freq": 20, + "spi_clock_divider": 1, + "flash_device_size": 8, + "flash_bytes_per_block": 16, + "flash_bytes_per_page": 256, + "flash_number_of_address_bytes": 3, + "flash_dual_opcode": 0, + "flash_jedec_manufacturer_id": 0, + "flash_jedec_device_id": 0, + "flash_name": "PY25Q64LB", + "flash_page_size": 256, + "flash_sector_size": 4096, + "flash_cs_polarity": "ACTIVE_LOW", + "flash_sw_reset_type": "x1xxxx", + "ram_device_size": 8, + "ram_bytes_per_block": 16, + "ram_bytes_per_page": 256, + "ram_number_of_address_bytes": 3, + "ram_dual_opcode": 0, + "ram_jedec_manufacturer_id": 0, + "ram_jedec_device_id": 0, + "ram_name": "NO_PSRAM", + "ram_page_size": 256, + "ram_sector_size": 4096, + "ram_cs_polarity": "ACTIVE_LOW", + "ram_sw_reset_type": "x1xxxx", + "flash_write_operation_modes": "4S-4S-4S", + "flash_read_operation_modes": "4S-4S-4S", + "ram_write_operation_modes": "4S-4S-4S", + "ram_read_operation_modes": "4S-4S-4S", + "crc_enable": 0, + "enable_dtr": 0, + "enable_ahb_decoder": 0, + "enter_xip_mod_immediately": 0, + "enter_xip_mod_next_read": 0, + "ahb_address_remapping": 0, + "enable_dma": 0, + "select_decode": 0, + "legacy_ip_mode": 0, + "direct_access": 1 + }, + "xspi_pinmux": { + "xspi_clk_input": 44, + "xspi_clk_input_use_hw": 0, + "xspi_clk_input_mode": "Input", + "xspi_clk_input_pull": "None", + "xspi_clk_input_interrupt_trigger": "Low", + "xspi_clk_input_dont_conf": 0, + "xspi_clk_input_output_strength": "High", + "xspi_clk_input_initial_output_state": "High", + "xspi_clk": 24, + "xspi_clk_use_hw": "None", + "xspi_clk_mode": "Output", + "xspi_clk_pull": "None", + "xspi_clk_output_strength": "High", + "xspi_clk_initial_output_state": "High", + "xspi_clk_interrupt_trigger": "None", + "xspi_clk_dont_conf": 0, + "xspi_flash_cs": 20, + "xspi_flash_cs_use_hw": "None", + "xspi_flash_cs_mode": "Output", + "xspi_flash_cs_pull": "None", + "xspi_flash_cs_output_strength": "High", + "xspi_flash_cs_initial_output_state": "High", + "xspi_flash_cs_interrupt_trigger": "None", + "xspi_flash_cs_dont_conf": 0, + "xspi_data_0": 25, + "xspi_data_0_use_hw": "None", + "xspi_data_0_mode": "Input", + "xspi_data_0_pull": "None", + "xspi_data_0_output_strength": "High", + "xspi_data_0_initial_output_state": "High", + "xspi_data_0_interrupt_trigger": "Low", + "xspi_data_0_dont_conf": 0, + "xspi_data_1": 21, + "xspi_data_1_use_hw": "None", + "xspi_data_1_mode": "Input", + "xspi_data_1_pull": "None", + "xspi_data_1_output_strength": "High", + "xspi_data_1_initial_output_state": "High", + "xspi_data_1_interrupt_trigger": "Low", + "xspi_data_1_dont_conf": 0, + "xspi_data_2": 22, + "xspi_data_2_use_hw": "None", + "xspi_data_2_mode": "Input", + "xspi_data_2_pull": "None", + "xspi_data_2_output_strength": "High", + "xspi_data_2_initial_output_state": "High", + "xspi_data_2_interrupt_trigger": "Low", + "xspi_data_2_dont_conf": 0, + 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"xspi_data_6_initial_output_state": "High", + "xspi_data_6_interrupt_trigger": "None", + "xspi_data_6_dont_conf": 0, + "xspi_data_7": 29, + "xspi_data_7_use_hw": "None", + "xspi_data_7_mode": "Input", + "xspi_data_7_pull": "None", + "xspi_data_7_output_strength": "High", + "xspi_data_7_initial_output_state": "High", + "xspi_data_7_interrupt_trigger": "None", + "xspi_data_7_dont_conf": 0, + "xspi_reset_flash": 36, + "xspi_reset_flash_use_hw": "None", + "xspi_reset_flash_mode": "Output", + "xspi_reset_flash_pull": "None", + "xspi_reset_flash_output_strength": "High", + "xspi_reset_flash_initial_output_state": "High", + "xspi_reset_flash_interrupt_trigger": "None", + "xspi_reset_flash_dont_conf": 0, + "xspi_cs_ram": 3, + "xspi_cs_ram_use_hw": "None", + "xspi_cs_ram_mode": "Output", + "xspi_cs_ram_pull": "None", + "xspi_cs_ram_output_strength": "High", + "xspi_cs_ram_initial_output_state": "High", + "xspi_cs_ram_interrupt_trigger": "None", + "xspi_cs_ram_dont_conf": 0, + "xspi_dqs": 30, + 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"ram_rx_dll_bypass_bit": 0, + "ram_dll_tx_delay": 22, + "ram_dll_rx_delay": 34 + }, + "xspi_read_operations": { + "flash_dummy_rd_cycles": 10, + "flash_read_opcode": 11, + "suppl_flash_read_opcode": 0, + "ram_dummy_rd_cycles": 10, + "ram_read_opcode": 11, + "suppl_ram_read_opcode": 0, + "flash_non_cont_read_enable": 0, + "flash_max_read_jobs": 256, + "ram_non_cont_read_enable": 0, + "ram_max_read_jobs": 256, + "rww_en": 0, + "device_size": 8, + "number_of_banks": 1, + "bank_size": 8, + "mode_bit_enable": 0 + }, + "xspi_write_operations": { + "flash_address_and_data": { + "flash_dummy_wr_cycles": 0 + }, + "flash_command": { + "flash_write_opcode": 2, + "suppl_flash_write_opcode": 0 + }, + "ram_address_and_data": { + "ram_dummy_wr_cycles": 0 + }, + "ram_command": { + "ram_write_opcode": 2, + "suppl_ram_write_opcode": 0 + }, + "write_to_buffer": { + "flash_write_to_buffer_support": 0, + "ram_write_to_buffer_support": 0 + }, + "non_continuous_write": { + "flash_non_cont_write_enable": 0, + "flash_max_write_jobs": 64, + "ram_non_cont_write_enable": 0, + "ram_max_write_jobs": 0 + }, + "flash_program_operation": { + "flash_min_program_size": "256 B", + "flash_program_opcode": 2, + "suppl_flash_program_opcode": 0, + "flash_maximum_program_time_limit": 1600 + }, + "flash_erase_operation": { + "flash_min_erase_size": "4 kB", + "flash_erase_opcode": 32, + "suppl_flash_erase_opcode": 0, + "flash_maximum_erase_time_limit": 4095 + }, + "flash_erase_conf": { + "flash_block_erase_opcode": 0, + "suppl_block_flash_erase_opcode": 0, + "flash_sector_erase_opcode": 0, + "suppl_sector_flash_erase_opcode": 0, + "flash_chip_erase_opcode": 0, + "suppl_chip_flash_erase_opcode": 0 + }, + "ram_program_operation": { + "ram_min_program_size": "256 B", + "ram_program_opcode": 2, + "suppl_ram_program_opcode": 0, + "ram_maximum_program_time_limit": 1600 + }, + "ram_erase_conf": { + "ram_block_erase_opcode": 0, + "suppl_block_ram_erase_opcode": 0, + "ram_sector_erase_opcode": 0, + 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"ram_delay_transmitted_data": 0, + "ram_loopback_clock": 0, + "ram_bypass_adapted_loopback": 1, + "ram_sample_edge_sel": 0 + }, + "delays": { + "flash_full_half_cycle_delay": 0, + "flash_dll_bypass_mode": 1, + "flash_phase_detect_sel": 0, + "flash_dll_lock_num": 0, + "flash_dll_start_point": 0, + "flash_loopback_clock": 0, + "ram_full_half_cycle_delay": 0, + "ram_dll_bypass_mode": 1, + "ram_phase_detect_sel": 0, + "ram_dll_lock_num": 0, + "ram_dll_start_point": 0, + "ram_loopback_clock": 0 + }, + "operation_modes": { + "flash_sfdp_support": 0, + "ram_sfdp_support": 0, + "flash_pm_support": 0, + "ram_pm_support": 0, + "flash_sfdp_opcode": 0, + "suppl_flash_sfdp_opcode": 0, + "ram_sfdp_opcode": 0, + "suppl_ram_sfdp_opcode": 0, + "flash_enter_dpd_opcode": 185, + "suppl_flash_enter_dpd_opcode": 0, + "flash_exit_dpd_opcode": 171, + "suppl_flash_exit_dpd_opcode": 0, + "ram_enter_dpd_opcode": 185, + "suppl_ram_enter_dpd_opcode": 0, + "ram_exit_dpd_opcode": 171, + "suppl_ram_exit_dpd_opcode": 0, + "flash_quad_enable_opcode": 56, + "suppl_flash_quad_enable_opcode": 0, + "flash_quad_disable_opcode": 255, + "suppl_flash_quad_disable_opcode": 0, + "flash_octal_enable_opcode": 0, + "suppl_flash_octal_enable_opcode": 0, + "flash_octal_disable_opcode": 0, + "suppl_flash_octal_disable_opcode": 0, + "ram_quad_enable_opcode": 56, + "suppl_ram_quad_enable_opcode": 0, + "ram_quad_disable_opcode": 255, + "suppl_ram_quad_disable_opcode": 0, + "ram_octal_enable_opcode": 0, + "suppl_ram_octal_enable_opcode": 0, + "ram_octal_disable_opcode": 0, + "suppl_ram_octal_disable_opcode": 0 + } + } + }, + "external_memory_reporting": { + "header": { + "flash_auto_polling_enable": 1, + "flash_wel_enable": 1, + "flash_write_protect_enable": 0, + "flash_alternate_polling_conf_enable": 0, + "ram_auto_polling_enable": 1, + "ram_wel_enable": 1, + "ram_write_protect_enable": 0, + "ram_alternate_polling_conf_enable": 0 + }, + "flash_auto_polling": { + "flash_polling_repetition_delay": 0, + "flash_polling_count": 4, + "flash_enable_polling_expiration": 0, + "flash_polling_polarity": 0, + "flash_polling_address_phase_enable": 0, + "flash_polling_bit_index": 0, + "flash_numbers_poll_cycles": 65535, + "flash_dummy_autopoll_cycles": 0 + }, + "ram_auto_polling": { + "ram_polling_repetition_delay": 0, + "ram_polling_count": 4, + "ram_enable_polling_expiration": 0, + "ram_polling_polarity": 0, + "ram_polling_address_phase_enable": 0, + "ram_polling_bit_index": 0, + "ram_numbers_poll_cycles": 65535, + "ram_dummy_autopoll_cycles": 0 + }, + "flash_polling_command": { + "flash_polling_opcode": 5, + "suppl_flash_polling_opcode": 0 + }, + "ram_polling_command": { + "ram_polling_opcode": 5, + "suppl_ram_polling_opcode": 0 + }, + "flash_alternate_polling": { + "flash_polling_resp_count": 1023, + "flash_polling_iterations": 1, + "flash_polling_enabled": 0, + "flash_polling_disabled": 0, + "flash_grant_sel": 0, + "flash_data_for_enable_poling_conf_0": 0, + "flash_offset_bits_for_enable_poling_conf_0": 0, + "flash_stop_bit_for_enable_poling_conf_0": 1, + "flash_data_for_enable_poling_conf_1": 0, + "flash_offset_bits_for_enable_poling_conf_1": 0, + "flash_stop_bit_for_enable_poling_conf_1": 1, + "flash_data_for_disable_poling_conf_0": 0, + "flash_offset_bits_for_disable_poling_conf_0": 0, + "flash_stop_bit_for_disable_poling_conf_0": 1, + "flash_data_for_disable_poling_conf_1": 0, + "flash_offset_bits_for_disable_poling_conf_1": 0, + "flash_stop_bit_for_disable_poling_conf_1": 1 + }, + "ram_alternate_polling": { + "ram_polling_resp_count": 1023, + "ram_polling_iterations": 1, + "ram_polling_enabled": 0, + "ram_polling_disabled": 0, + "ram_grant_sel": 0, + "ram_data_for_enable_poling_conf_0": 0, + "ram_offset_bits_for_enable_poling_conf_0": 0, + "ram_stop_bit_for_enable_poling_conf_0": 1, + "ram_data_for_enable_poling_conf_1": 0, + "ram_offset_bits_for_enable_poling_conf_1": 0, + "ram_stop_bit_for_enable_poling_conf_1": 1, + "ram_data_for_disable_poling_conf_0": 0, + "ram_offset_bits_for_disable_poling_conf_0": 0, + "ram_stop_bit_for_disable_poling_conf_0": 1, + "ram_data_for_disable_poling_conf_1": 0, + "ram_offset_bits_for_disable_poling_conf_1": 0, + "ram_stop_bit_for_disable_poling_conf_1": 1 + }, + "flash_wel_command": { + "flash_wel_opcode": 6, + "suppl_flash_wel_opcode": 0 + }, + "ram_wel_command": { + "ram_wel_opcode": 6, + "suppl_ram_wel_opcode": 0 + } + }, + "event": { + "host_nvic_irq": 0, + "core_10_mux_sel": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/w25q12pw/flash_disc_param_ext_mem.json b/boards/ti/lp_em_cc35x1/config/flash/w25q12pw/flash_disc_param_ext_mem.json new file mode 100644 index 000000000000..14d05d9aba5a --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/w25q12pw/flash_disc_param_ext_mem.json @@ -0,0 +1,99 @@ +{ + "vendor_primary_sbl": true, + "ti_wsoc_primary_container": true, + "ti_wsoc_bl2_primary_container": true, + "nvs_enable": true, + "vendor_alternate_image": true, + "vendor_sbl_alternate_image": true, + "ti_bl_alternate_image": true, + "ti_wsoc_alternate_image": true, + "ti_wsoc_bl2_alternate_image": true, + "region_0": { + "mem_region_0_start_phy_address": 2867200, + "mem_region_0_end_phy_address": 9822207, + "region0_boot": false, + "region0_main_code": true, + "region0_nvs": false, + "region0_wsoc_code": false, + "region0_alternate_code": false + }, + "region_1": { + "mem_region_1_start_phy_address": 0, + "mem_region_1_end_phy_address": 2867199, + "region1_boot": true, + "region1_main_code": false, + "region1_nvs": true, + "region1_wsoc_code": true, + "region1_alternate_code": false + }, + "region_2": { + "mem_region_2_start_phy_address": 9822208, + "mem_region_2_end_phy_address": 16777215, + "region2_boot": false, + "region2_main_code": false, + "region2_nvs": false, + "region2_wsoc_code": false, + "region2_alternate_code": true + }, + "region_3": { + "mem_region_3_start_phy_address": 0, + "mem_region_3_end_phy_address": 0, + "region3_boot": false, + "region3_main_code": false, + "region3_nvs": false, + "region3_wsoc_code": false, + "region3_alternate_code": false + }, + "boot_region_conf": { + "boot_region_size": 0, + "boot_region_flash_disco_param_start_address": 0, + "boot_region_primary_ti_bl_start_phy_address": 12284, + "boot_region_primary_ti_bl_magic": 0, + "boot_region_primary_ti_bl_major": 0, + "boot_region_primary_ti_bl_minor": 0, + "boot_region_sec_ti_bl_start_phy_address": 430076, + "boot_region_sec_ti_bl_magic": 0, + "boot_region_sec_ti_bl_major": 0, + "boot_region_sec_ti_bl_minor": 0 + }, + "main_code_region_conf": { + "main_code_region_vendor_image_start_phy_address": 2871292, + "main_code_region_vendor_image_magic": 0, + "main_code_region_vendor_image_major": 0, + "main_code_region_vendor_image_minor": 0, + "main_code_region_sbl_start_phy_address": 0, + "main_code_region_sbl_magic": 0, + "main_code_region_sbl_major": 0, + "main_code_region_sbl_minor": 0 + }, + "alt_code_region_conf": { + "alt_code_region_vendor_image_start_phy_address": 9826300, + "alt_code_region_vendor_image_magic": 0, + "alt_code_region_vendor_image_major": 0, + "alt_code_region_vendor_image_minor": 0, + "alt_code_region_sbl_start_phy_address": 0, + "alt_code_region_sbl_magic": 0, + "alt_code_region_sbl_major": 0, + "alt_code_region_sbl_minor": 0 + }, + "nvs_code_region_conf": { + "nvs_start_phy_address": 1777664, + "nvs_region_size": 1089536, + "nvs_region_primary_wsoc_start_phy_address": 847868, + "nvs_region_primary_wsoc_magic": 0, + "nvs_region_primary_wsoc_major": 0, + "nvs_region_primary_wsoc_minor": 0, + "nvs_region_sec_wsoc_start_phy_address": 1314812, + "nvs_region_sec_wsoc_magic": 0, + "nvs_region_sec_wsoc_major": 0, + "nvs_region_sec_wsoc_minor": 0, + "nvs_region_primary_wsoc_bl2_start_phy_address": 0, + "nvs_region_primary_wsoc_bl2_magic": 0, + "nvs_region_primary_wsoc_bl2_major": 0, + "nvs_region_primary_wsoc_bl2_minor": 0, + "nvs_region_sec_wsoc_bl2_start_phy_address": 0, + "nvs_region_sec_wsoc_bl2_magic": 0, + "nvs_region_sec_wsoc_bl2_major": 0, + "nvs_region_sec_wsoc_bl2_minor": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/w25q12pw/flash_disc_param_otfde.json b/boards/ti/lp_em_cc35x1/config/flash/w25q12pw/flash_disc_param_otfde.json new file mode 100644 index 000000000000..0a4af30e7551 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/w25q12pw/flash_disc_param_otfde.json @@ -0,0 +1,286 @@ +{ + "otfde_header": { + "name": "OTFDEWFF3", + "flash_only": true, + "ip_protection": false, + "regions_lock": false, + "regions_number": 4, + "flash_enabled": true + }, + "bl_conf": { + "host_boot_done_lock": true, + "host_peripherals_lock": true, + "icache_conf_lock": true, + "m33_mem_part_lock": true, + "memss_firewall_lock": true, + "dma_channel_owner_lock": true, + "otfde_region_lock": true, + "core_events_lock": true + }, + "otfde_general": { + "parameters": { + "mem_otfde_initial_delay": 10, + "otfde_global_watchdog_timer": 5 + }, + "events": { + "reset_evt_mask": false, + "reset_evt_suspend": false, + "sft_reset_evt_mask": false, + "sft_reset_evt_suspend": false, + "bypass_mode_evt_mask": false, + "bypass_mode_evt_suspend": false, + "debug_mode_evt_mask": false, + "debug_mode_evt_suspend": false, + "general_evt_mask": false, + "general_evt_suspend": false, + "xspi_data_path_evt_mask": false, + "xspi_data_path_evt_suspend": false, + "xspi_cnfg_path_evt_mask": false, + "xspi_cnfg_path_evt_suspend": false, + "xspi_service_interrupt_evt_mask": false, + "xspi_service_interrupt_evt_suspend": false, + "trans_device_disabled_evt_mask": false, + "trans_device_disabled_evt_suspend": false, + "trans_region_disabled_evt_mask": false, + "trans_region_disabled_evt_suspend": false, + "trans_region_params_conf_evt_mask": false, + "trans_region_params_conf_evt_suspend": false, + "trans_multiple_regions_mapped_evt_mask": false, + "trans_multiple_regions_mapped_evt_suspend": false, + "trans_address_not_32_bit_evt_mask": false, + "trans_address_not_32_bit_evt_suspend": false, + "trans_size_not_32_bit_evt_mask": false, + "trans_size_not_32_bit_evt_suspend": false, + "trans_burst_not_32_bit_evt_mask": false, + "trans_burst_not_32_bit_evt_suspend": false, + "region_read_write_def_evt_mask": false, + "region_read_write_def_evt_suspend": false, + "suspend_while_disabled_evt_mask": false, + "suspend_while_disabled_evt_suspend": false + } + }, + "regions_settings": { + "region_parameters_lock": { + "REGION_0_PARAMS_0": true, + "REGION_0_PARAMS_1": true, + "REGION_0_PARAMS_2": true, + "REGION_1_PARAMS_0": false, + "REGION_1_PARAMS_1": false, + "REGION_1_PARAMS_2": false, + "REGION_2_PARAMS_0": true, + "REGION_2_PARAMS_1": true, + "REGION_2_PARAMS_2": true, + "REGION_3_PARAMS_0": false, + "REGION_3_PARAMS_1": false, + "REGION_3_PARAMS_2": false + }, + "region_0_protection": { + "mem_region_0_enabled": true, + "mem_region_0_device_id": 0, + "mem_region_0_spi_write_enable": true, + "mem_region_0_spi_read_enable": true, + "mem_region_0_physical_offset": 700, + "mem_region_0_security_id_msb": 0, + "mem_region_0_start_address": 81920, + "mem_region_0_end_address": 83617, + "mem_region_0_security_id_lsb": 0, + "mem_otfde_region_0_write_lock_en": false, + "mem_otfde_region_0_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_1_protection": { + "mem_region_1_enabled": true, + "mem_region_1_device_id": 0, + "mem_region_1_spi_write_enable": true, + "mem_region_1_spi_read_enable": true, + "mem_region_1_physical_offset": 0, + "mem_region_1_security_id_msb": 0, + "mem_region_1_start_address": 655360, + "mem_region_1_end_address": 656059, + "mem_region_1_security_id_lsb": 0, + "mem_otfde_region_1_write_lock_en": false, + "mem_otfde_region_1_enc_dec_bypass": "Bypass" + }, + "region_2_protection": { + "mem_region_2_enabled": true, + "mem_region_2_device_id": 0, + "mem_region_2_spi_write_enable": true, + "mem_region_2_spi_read_enable": true, + "mem_region_2_physical_offset": 2398, + "mem_region_2_security_id_msb": 0, + "mem_region_2_start_address": 671744, + "mem_region_2_end_address": 673441, + "mem_region_2_security_id_lsb": 0, + "mem_otfde_region_2_write_lock_en": false, + "mem_otfde_region_2_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_3_protection": { + "mem_region_3_enabled": false, + "mem_region_3_device_id": 1, + "mem_region_3_spi_write_enable": true, + "mem_region_3_spi_read_enable": true, + "mem_region_3_physical_offset": 0, + "mem_region_3_security_id_msb": 0, + "mem_region_3_start_address": 1, + "mem_region_3_end_address": 0, + "mem_region_3_security_id_lsb": 0, + "mem_otfde_region_3_write_lock_en": false, + "mem_otfde_region_3_enc_dec_bypass": "Bypass" + } + }, + "devices": { + "header": { + "flash_device_switch_conf": 1, + "ram_device_switch_conf": 1 + }, + "flash_switch": { + "flash_grant_sel": 0, + "flash_data_for_conf_0": 2181562505, + "flash_offset_bits_for_conf_0": 0, + "flash_stop_bit_for_conf_0": 0, + "flash_data_for_conf_1": 100803083, + "flash_offset_bits_for_conf_1": 1, + "flash_stop_bit_for_conf_1": 0, + "flash_data_for_conf_2": 139266, + "flash_offset_bits_for_conf_2": 2, + "flash_stop_bit_for_conf_2": 0, + "flash_data_for_conf_3": 1, + "flash_offset_bits_for_conf_3": 4, + "flash_stop_bit_for_conf_3": 0, + "flash_data_for_conf_4": 1076887634, + "flash_offset_bits_for_conf_4": 45, + "flash_stop_bit_for_conf_4": 0, + "flash_data_for_conf_5": 3224371282, + "flash_offset_bits_for_conf_5": 45, + "flash_stop_bit_for_conf_5": 0, + "flash_data_for_conf_6": 262149, + "flash_offset_bits_for_conf_6": 14, + "flash_stop_bit_for_conf_6": 0, + "flash_data_for_conf_7": 0, + "flash_offset_bits_for_conf_7": 44, + "flash_stop_bit_for_conf_7": 1, + "flash_data_for_conf_8": 0, + "flash_offset_bits_for_conf_8": 0, + "flash_stop_bit_for_conf_8": 1, + "flash_data_for_conf_9": 0, + "flash_offset_bits_for_conf_9": 0, + "flash_stop_bit_for_conf_9": 1, + "flash_data_for_conf_10": 0, + "flash_offset_bits_for_conf_10": 0, + "flash_stop_bit_for_conf_10": 1, + "flash_data_for_conf_11": 0, + "flash_offset_bits_for_conf_11": 0, + "flash_stop_bit_for_conf_11": 1, + "flash_data_for_conf_12": 0, + "flash_offset_bits_for_conf_12": 0, + "flash_stop_bit_for_conf_12": 1, + "flash_data_for_conf_13": 0, + "flash_offset_bits_for_conf_13": 0, + "flash_stop_bit_for_conf_13": 1, + "flash_data_for_conf_14": 0, + "flash_offset_bits_for_conf_14": 0, + "flash_stop_bit_for_conf_14": 1, + "flash_data_for_conf_15": 0, + "flash_offset_bits_for_conf_15": 0, + "flash_stop_bit_for_conf_15": 1, + "flash_data_for_conf_16": 0, + "flash_offset_bits_for_conf_16": 0, + "flash_stop_bit_for_conf_16": 1, + "flash_data_for_conf_17": 0, + "flash_offset_bits_for_conf_17": 0, + "flash_stop_bit_for_conf_17": 1, + "flash_data_for_conf_18": 0, + "flash_offset_bits_for_conf_18": 0, + "flash_stop_bit_for_conf_18": 1, + "flash_data_for_conf_19": 0, + "flash_offset_bits_for_conf_19": 0, + "flash_stop_bit_for_conf_19": 1, + "flash_data_for_conf_20": 0, + "flash_offset_bits_for_conf_20": 0, + "flash_stop_bit_for_conf_20": 1, + "flash_data_for_conf_21": 0, + "flash_offset_bits_for_conf_21": 0, + "flash_stop_bit_for_conf_21": 1, + "flash_data_for_conf_22": 0, + "flash_offset_bits_for_conf_22": 0, + "flash_stop_bit_for_conf_22": 1, + "flash_data_for_conf_23": 0, + "flash_offset_bits_for_conf_23": 0, + "flash_stop_bit_for_conf_23": 1 + }, + "ram_switch": { + "ram_grant_sel": 0, + "ram_data_for_conf_0": 2181562505, + "ram_offset_bits_for_conf_0": 0, + "ram_stop_bit_for_conf_0": 0, + "ram_data_for_conf_1": 100803083, + "ram_offset_bits_for_conf_1": 1, + "ram_stop_bit_for_conf_1": 0, + "ram_data_for_conf_2": 139266, + "ram_offset_bits_for_conf_2": 2, + "ram_stop_bit_for_conf_2": 0, + "ram_data_for_conf_3": 1, + "ram_offset_bits_for_conf_3": 4, + "ram_stop_bit_for_conf_3": 0, + "ram_data_for_conf_4": 1076887634, + "ram_offset_bits_for_conf_4": 45, + "ram_stop_bit_for_conf_4": 0, + "ram_data_for_conf_5": 3224371282, + "ram_offset_bits_for_conf_5": 45, + "ram_stop_bit_for_conf_5": 0, + "ram_data_for_conf_6": 262149, + "ram_offset_bits_for_conf_6": 14, + "ram_stop_bit_for_conf_6": 0, + "ram_data_for_conf_7": 0, + "ram_offset_bits_for_conf_7": 44, + "ram_stop_bit_for_conf_7": 1, + "ram_data_for_conf_8": 0, + "ram_offset_bits_for_conf_8": 0, + "ram_stop_bit_for_conf_8": 1, + "ram_data_for_conf_9": 0, + "ram_offset_bits_for_conf_9": 0, + "ram_stop_bit_for_conf_9": 1, + "ram_data_for_conf_10": 0, + "ram_offset_bits_for_conf_10": 0, + "ram_stop_bit_for_conf_10": 1, + "ram_data_for_conf_11": 0, + "ram_offset_bits_for_conf_11": 0, + "ram_stop_bit_for_conf_11": 1, + "ram_data_for_conf_12": 0, + "ram_offset_bits_for_conf_12": 0, + "ram_stop_bit_for_conf_12": 1, + "ram_data_for_conf_13": 0, + "ram_offset_bits_for_conf_13": 0, + "ram_stop_bit_for_conf_13": 1, + "ram_data_for_conf_14": 0, + "ram_offset_bits_for_conf_14": 0, + "ram_stop_bit_for_conf_14": 1, + "ram_data_for_conf_15": 0, + "ram_offset_bits_for_conf_15": 0, + "ram_stop_bit_for_conf_15": 1, + "ram_data_for_conf_16": 0, + "ram_offset_bits_for_conf_16": 0, + "ram_stop_bit_for_conf_16": 1, + "ram_data_for_conf_17": 0, + "ram_offset_bits_for_conf_17": 0, + "ram_stop_bit_for_conf_17": 1, + "ram_data_for_conf_18": 0, + "ram_offset_bits_for_conf_18": 0, + "ram_stop_bit_for_conf_18": 1, + "ram_data_for_conf_19": 0, + "ram_offset_bits_for_conf_19": 0, + "ram_stop_bit_for_conf_19": 1, + "ram_data_for_conf_20": 0, + "ram_offset_bits_for_conf_20": 0, + "ram_stop_bit_for_conf_20": 1, + "ram_data_for_conf_21": 0, + "ram_offset_bits_for_conf_21": 0, + "ram_stop_bit_for_conf_21": 1, + "ram_data_for_conf_22": 0, + "ram_offset_bits_for_conf_22": 0, + "ram_stop_bit_for_conf_22": 1, + "ram_data_for_conf_23": 0, + "ram_offset_bits_for_conf_23": 0, + "ram_stop_bit_for_conf_23": 1 + } + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/w25q12pw/flash_disc_param_xspi.json b/boards/ti/lp_em_cc35x1/config/flash/w25q12pw/flash_disc_param_xspi.json new file mode 100644 index 000000000000..61763985c259 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/w25q12pw/flash_disc_param_xspi.json @@ -0,0 +1,485 @@ +{ + "xspi_header": { + "name": "xSPIWFF3", + "device": "CC3500", + "use_hardware": "W25Q12PW", + "use_case": "Quadro", + "dqs_support": 0, + "flash_only": 1, + "flash_separate_reset": 0, + "ram_separate_reset": true, + "clock_frequency": 80, + "qospi_clock_divider": 1, + "flash_device_character_conf": 0, + "ram_device_character_conf": 0, + "header_advanced": 0, + "phy_mode_enable": 1, + "pipeline_mode_enable": 1, + "loopback_support": "No", + "qspi_ref_clock": 80, + "spi_clock_freq": 20, + "spi_clock_divider": 1, + "flash_device_size": 16, + "flash_bytes_per_block": 65535, + "flash_bytes_per_page": 256, + "flash_number_of_address_bytes": 3, + "flash_dual_opcode": 0, + "flash_jedec_manufacturer_id": 0, + "flash_jedec_device_id": 0, + "flash_name": "W25Q12PW", + "flash_page_size": 256, + "flash_sector_size": 4096, + "flash_cs_polarity": "ACTIVE_LOW", + "flash_sw_reset_type": "x1xxxx", + "ram_device_size": 16, + "ram_bytes_per_block": 65535, + "ram_bytes_per_page": 256, + "ram_number_of_address_bytes": 3, + "ram_dual_opcode": 0, + "ram_jedec_manufacturer_id": 0, + "ram_jedec_device_id": 0, + "ram_name": "NO_PSRAM", + "ram_page_size": 256, + "ram_sector_size": 4096, + "ram_cs_polarity": "ACTIVE_LOW", + "ram_sw_reset_type": "x1xxxx", + "flash_write_operation_modes": "4S-4S-4S", + "flash_read_operation_modes": "4S-4S-4S", + "ram_write_operation_modes": "4S-4S-4S", + "ram_read_operation_modes": "4S-4S-4S", + "crc_enable": 0, + "enable_dtr": 0, + "enable_ahb_decoder": 0, + "enter_xip_mod_immediately": 0, + "enter_xip_mod_next_read": 0, + "ahb_address_remapping": 0, + "enable_dma": 0, + "select_decode": 0, + "legacy_ip_mode": 0, + "direct_access": 1 + }, + "xspi_pinmux": { + "xspi_clk_input": 44, + "xspi_clk_input_use_hw": 0, + "xspi_clk_input_mode": "Input", + "xspi_clk_input_pull": "None", + "xspi_clk_input_interrupt_trigger": "Low", + "xspi_clk_input_dont_conf": 0, + "xspi_clk_input_output_strength": "High", + "xspi_clk_input_initial_output_state": "High", + "xspi_clk": 24, + "xspi_clk_use_hw": "None", + "xspi_clk_mode": "Output", + "xspi_clk_pull": "None", + "xspi_clk_output_strength": "High", + "xspi_clk_initial_output_state": "High", + "xspi_clk_interrupt_trigger": "None", + "xspi_clk_dont_conf": 0, + "xspi_flash_cs": 20, + "xspi_flash_cs_use_hw": "None", + "xspi_flash_cs_mode": "Output", + "xspi_flash_cs_pull": "None", + "xspi_flash_cs_output_strength": "High", + "xspi_flash_cs_initial_output_state": "High", + "xspi_flash_cs_interrupt_trigger": "None", + "xspi_flash_cs_dont_conf": 0, + "xspi_data_0": 25, + "xspi_data_0_use_hw": "None", + "xspi_data_0_mode": "Input", + "xspi_data_0_pull": "None", + "xspi_data_0_output_strength": "High", + "xspi_data_0_initial_output_state": "High", + "xspi_data_0_interrupt_trigger": "Low", + "xspi_data_0_dont_conf": 0, + "xspi_data_1": 21, + "xspi_data_1_use_hw": "None", + "xspi_data_1_mode": "Input", + "xspi_data_1_pull": "None", + "xspi_data_1_output_strength": "High", + "xspi_data_1_initial_output_state": "High", + "xspi_data_1_interrupt_trigger": "Low", + "xspi_data_1_dont_conf": 0, + "xspi_data_2": 22, + "xspi_data_2_use_hw": "None", + "xspi_data_2_mode": "Input", + "xspi_data_2_pull": "None", + "xspi_data_2_output_strength": "High", + "xspi_data_2_initial_output_state": "High", + "xspi_data_2_interrupt_trigger": "Low", + "xspi_data_2_dont_conf": 0, + "xspi_data_3": 23, + "xspi_data_3_use_hw": "None", + "xspi_data_3_mode": "Input", + "xspi_data_3_pull": "None", + "xspi_data_3_output_strength": "High", + "xspi_data_3_initial_output_state": "High", + "xspi_data_3_interrupt_trigger": "Low", + "xspi_data_3_dont_conf": 0, + "xspi_data_4": 26, + "xspi_data_4_use_hw": "None", + "xspi_data_4_mode": "Input", + "xspi_data_4_pull": "None", + "xspi_data_4_output_strength": "High", + "xspi_data_4_initial_output_state": "High", + "xspi_data_4_interrupt_trigger": "None", + "xspi_data_4_dont_conf": 0, + "xspi_data_5": 27, + "xspi_data_5_use_hw": "None", + "xspi_data_5_mode": "Input", + "xspi_data_5_pull": "None", + "xspi_data_5_output_strength": "High", + "xspi_data_5_initial_output_state": "High", + "xspi_data_5_interrupt_trigger": "None", + "xspi_data_5_dont_conf": 0, + "xspi_data_6": 28, + "xspi_data_6_use_hw": "None", + "xspi_data_6_mode": "Input", + "xspi_data_6_pull": "None", + "xspi_data_6_output_strength": "High", + "xspi_data_6_initial_output_state": "High", + "xspi_data_6_interrupt_trigger": "None", + "xspi_data_6_dont_conf": 0, + "xspi_data_7": 29, + "xspi_data_7_use_hw": "None", + "xspi_data_7_mode": "Input", + "xspi_data_7_pull": "None", + "xspi_data_7_output_strength": "High", + "xspi_data_7_initial_output_state": "High", + "xspi_data_7_interrupt_trigger": "None", + "xspi_data_7_dont_conf": 0, + "xspi_reset_flash": 36, + "xspi_reset_flash_use_hw": "None", + "xspi_reset_flash_mode": "Output", + "xspi_reset_flash_pull": "None", + "xspi_reset_flash_output_strength": "High", + "xspi_reset_flash_initial_output_state": "High", + "xspi_reset_flash_interrupt_trigger": "None", + "xspi_reset_flash_dont_conf": 0, + "xspi_cs_ram": 3, + "xspi_cs_ram_use_hw": "None", + "xspi_cs_ram_mode": "Output", + "xspi_cs_ram_pull": "None", + "xspi_cs_ram_output_strength": "High", + "xspi_cs_ram_initial_output_state": "High", + "xspi_cs_ram_interrupt_trigger": "None", + "xspi_cs_ram_dont_conf": 0, + "xspi_dqs": 30, + "xspi_dqs_use_hw": "None", + "xspi_dqs_mode": "Input", + "xspi_dqs_pull": "None", + "xspi_dqs_output_strength": "High", + "xspi_dqs_initial_output_state": "High", + "xspi_dqs_interrupt_trigger": "None", + "xspi_dqs_dont_conf": 0, + "xspi_reset_ram": 2, + "xspi_reset_ram_use_hw": "None", + "xspi_reset_ram_mode": "Input", + "xspi_reset_ram_pull": "None", + "xspi_reset_ram_output_strength": "High", + "xspi_reset_ram_initial_output_state": "High", + "xspi_reset_ram_interrupt_trigger": "None", + "xspi_reset_ram_dont_conf": 0 + }, + "xspi_operations": { + "xspi_operations_clocks": { + "clock_phase": 0, + "clock_polarity": 0, + "spi_mode": "2'b00" + }, + "xspi_operations_chip_select": { + "csda": 2, + "csdads": 0, + "cseot": 4, + "cssot": 1 + }, + "xspi_operations_reset": { + "flash_jedec_reset": 0, + "ram_jedec_reset": 0, + "flash_treset": 20, + "ram_treset": 20 + }, + "xspi_phy_operations": { + "flash_rx_dll_bypass_bit": 0, + "flash_dll_tx_delay": 42, + "flash_dll_rx_delay": 62, + "ram_rx_dll_bypass_bit": 0, + "ram_dll_tx_delay": 42, + "ram_dll_rx_delay": 62 + }, + "xspi_read_operations": { + "flash_dummy_rd_cycles": 6, + "flash_read_opcode": 11, + "suppl_flash_read_opcode": 0, + "ram_dummy_rd_cycles": 6, + "ram_read_opcode": 11, + "suppl_ram_read_opcode": 0, + "flash_non_cont_read_enable": 0, + "flash_max_read_jobs": 256, + "ram_non_cont_read_enable": 0, + "ram_max_read_jobs": 256, + "rww_en": 0, + "device_size": 16, + "number_of_banks": 1, + "bank_size": 16, + "mode_bit_enable": 0 + }, + "xspi_write_operations": { + "flash_address_and_data": { + "flash_dummy_wr_cycles": 0 + }, + "flash_command": { + "flash_write_opcode": 2, + "suppl_flash_write_opcode": 0 + }, + "ram_address_and_data": { + "ram_dummy_wr_cycles": 0 + }, + "ram_command": { + "ram_write_opcode": 2, + "suppl_ram_write_opcode": 0 + }, + "write_to_buffer": { + "flash_write_to_buffer_support": 0, + "ram_write_to_buffer_support": 0 + }, + "non_continuous_write": { + "flash_non_cont_write_enable": 0, + "flash_max_write_jobs": 64, + "ram_non_cont_write_enable": 0, + "ram_max_write_jobs": 0 + }, + "flash_program_operation": { + "flash_min_program_size": "256 B", + "flash_program_opcode": 2, + "suppl_flash_program_opcode": 0, + "flash_maximum_program_time_limit": 1600 + }, + "flash_erase_operation": { + "flash_min_erase_size": "4 kB", + "flash_erase_opcode": 32, + "suppl_flash_erase_opcode": 0, + "flash_maximum_erase_time_limit": 4095 + }, + "flash_erase_conf": { + "flash_block_erase_opcode": 0, + "suppl_block_flash_erase_opcode": 0, + "flash_sector_erase_opcode": 0, + "suppl_sector_flash_erase_opcode": 0, + "flash_chip_erase_opcode": 0, + "suppl_chip_flash_erase_opcode": 0 + }, + "ram_program_operation": { + "ram_min_program_size": "256 B", + "ram_program_opcode": 2, + "suppl_ram_program_opcode": 0, + "ram_maximum_program_time_limit": 1600 + }, + "ram_erase_conf": { + "ram_block_erase_opcode": 0, + "suppl_block_ram_erase_opcode": 0, + "ram_sector_erase_opcode": 0, + "suppl_sector_ram_erase_opcode": 0, + "ram_chip_erase_opcode": 0, + "suppl_chip_ram_erase_opcode": 0 + }, + "flash_buffer_support": { + "flash_pre_write_sequence": 0, + "flash_post_write_sequence": 0, + "flash_write_protection_timer_en": 0, + "flash_write_buffer_timer_mode": 16, + "flash_write_buffer_timer_range": 0, + "flash_service_interrupt_criteria": 0 + }, + "ram_buffer_support": { + "ram_pre_write_sequence": 0, + "ram_post_write_sequence": 0, + "ram_write_protection_timer_en": 0, + "ram_write_buffer_timer_mode": 16, + "ram_write_buffer_timer_range": 0, + "ram_service_interrupt_criteria": 0 + }, + "flash_pre_write_conf": { + "flash_pre_write_job_done_grant_sel": 0, + "data_for_flash_pre_write_conf_0": 0, + "offset_bits_for_flash_pre_write_conf_0": 0, + "stop_bit_for_flash_pre_write_conf_0": 1, + "data_for_flash_pre_write_conf_1": 0, + "offset_bits_for_flash_pre_write_conf_1": 0 + }, + "flash_post_write_conf": { + "flash_post_write_job_done_grant_sel": 0, + "data_for_flash_post_write_conf_0": 0, + "offset_bits_for_flash_post_write_conf_0": 0, + "stop_bit_for_flash_post_write_conf_0": 1, + "data_for_flash_post_write_conf_1": 0, + "offset_bits_for_flash_post_write_conf_1": 0 + }, + "ram_pre_write_conf": { + "ram_pre_write_job_done_grant_sel": 0, + "data_for_ram_pre_write_conf_0": 0, + "offset_bits_for_ram_pre_write_conf_0": 0, + "stop_bit_for_ram_pre_write_conf_0": 1, + "data_for_ram_pre_write_conf_1": 0, + "offset_bits_for_ram_pre_write_conf_1": 0 + }, + "ram_post_write_conf": { + "ram_post_write_job_done_grant_sel": 0, + "data_for_ram_post_write_conf_0": 0, + "offset_bits_for_ram_post_write_conf_0": 0, + "stop_bit_for_ram_post_write_conf_0": 1, + "data_for_ram_post_write_conf_1": 0, + "offset_bits_for_ram_post_write_conf_1": 0 + } + }, + "xspi_capture_operations": { + "read_data_capture": { + "flash_delay_transmitted_data": 0, + "flash_loopback_clock": 0, + "flash_bypass_adapted_loopback": 1, + "flash_sample_edge_sel": 0, + "ram_delay_transmitted_data": 0, + "ram_loopback_clock": 0, + "ram_bypass_adapted_loopback": 1, + "ram_sample_edge_sel": 0 + }, + "delays": { + "flash_full_half_cycle_delay": 0, + "flash_dll_bypass_mode": 1, + "flash_phase_detect_sel": 0, + "flash_dll_lock_num": 0, + "flash_dll_start_point": 0, + "flash_loopback_clock": 0, + "ram_full_half_cycle_delay": 0, + "ram_dll_bypass_mode": 1, + "ram_phase_detect_sel": 0, + "ram_dll_lock_num": 0, + "ram_dll_start_point": 0, + "ram_loopback_clock": 0 + }, + "operation_modes": { + "flash_sfdp_support": 0, + "ram_sfdp_support": 0, + "flash_pm_support": 0, + "ram_pm_support": 0, + "flash_sfdp_opcode": 0, + "suppl_flash_sfdp_opcode": 0, + "ram_sfdp_opcode": 0, + "suppl_ram_sfdp_opcode": 0, + "flash_enter_dpd_opcode": 185, + "suppl_flash_enter_dpd_opcode": 0, + "flash_exit_dpd_opcode": 171, + "suppl_flash_exit_dpd_opcode": 0, + "ram_enter_dpd_opcode": 185, + "suppl_ram_enter_dpd_opcode": 0, + "ram_exit_dpd_opcode": 171, + "suppl_ram_exit_dpd_opcode": 0, + "flash_quad_enable_opcode": 56, + "suppl_flash_quad_enable_opcode": 0, + "flash_quad_disable_opcode": 255, + "suppl_flash_quad_disable_opcode": 0, + "flash_octal_enable_opcode": 0, + "suppl_flash_octal_enable_opcode": 0, + "flash_octal_disable_opcode": 0, + "suppl_flash_octal_disable_opcode": 0, + "ram_quad_enable_opcode": 56, + "suppl_ram_quad_enable_opcode": 0, + "ram_quad_disable_opcode": 255, + "suppl_ram_quad_disable_opcode": 0, + "ram_octal_enable_opcode": 0, + "suppl_ram_octal_enable_opcode": 0, + "ram_octal_disable_opcode": 0, + "suppl_ram_octal_disable_opcode": 0 + } + } + }, + "external_memory_reporting": { + "header": { + "flash_auto_polling_enable": 1, + "flash_wel_enable": 1, + "flash_write_protect_enable": 0, + "flash_alternate_polling_conf_enable": 0, + "ram_auto_polling_enable": 1, + "ram_wel_enable": 1, + "ram_write_protect_enable": 0, + "ram_alternate_polling_conf_enable": 0 + }, + "flash_auto_polling": { + "flash_polling_repetition_delay": 0, + "flash_polling_count": 4, + "flash_enable_polling_expiration": 0, + "flash_polling_polarity": 0, + "flash_polling_address_phase_enable": 0, + "flash_polling_bit_index": 0, + "flash_numbers_poll_cycles": 65535, + "flash_dummy_autopoll_cycles": 0 + }, + "ram_auto_polling": { + "ram_polling_repetition_delay": 0, + "ram_polling_count": 4, + "ram_enable_polling_expiration": 0, + "ram_polling_polarity": 0, + "ram_polling_address_phase_enable": 0, + "ram_polling_bit_index": 0, + "ram_numbers_poll_cycles": 65535, + "ram_dummy_autopoll_cycles": 0 + }, + "flash_polling_command": { + "flash_polling_opcode": 5, + "suppl_flash_polling_opcode": 0 + }, + "ram_polling_command": { + "ram_polling_opcode": 5, + "suppl_ram_polling_opcode": 0 + }, + "flash_alternate_polling": { + "flash_polling_resp_count": 1023, + "flash_polling_iterations": 1, + "flash_polling_enabled": 0, + "flash_polling_disabled": 0, + "flash_grant_sel": 0, + "flash_data_for_enable_poling_conf_0": 0, + "flash_offset_bits_for_enable_poling_conf_0": 0, + "flash_stop_bit_for_enable_poling_conf_0": 1, + "flash_data_for_enable_poling_conf_1": 0, + "flash_offset_bits_for_enable_poling_conf_1": 0, + "flash_stop_bit_for_enable_poling_conf_1": 1, + "flash_data_for_disable_poling_conf_0": 0, + "flash_offset_bits_for_disable_poling_conf_0": 0, + "flash_stop_bit_for_disable_poling_conf_0": 1, + "flash_data_for_disable_poling_conf_1": 0, + "flash_offset_bits_for_disable_poling_conf_1": 0, + "flash_stop_bit_for_disable_poling_conf_1": 1 + }, + "ram_alternate_polling": { + "ram_polling_resp_count": 1023, + "ram_polling_iterations": 1, + "ram_polling_enabled": 0, + "ram_polling_disabled": 0, + "ram_grant_sel": 0, + "ram_data_for_enable_poling_conf_0": 0, + "ram_offset_bits_for_enable_poling_conf_0": 0, + "ram_stop_bit_for_enable_poling_conf_0": 1, + "ram_data_for_enable_poling_conf_1": 0, + "ram_offset_bits_for_enable_poling_conf_1": 0, + "ram_stop_bit_for_enable_poling_conf_1": 1, + "ram_data_for_disable_poling_conf_0": 0, + "ram_offset_bits_for_disable_poling_conf_0": 0, + "ram_stop_bit_for_disable_poling_conf_0": 1, + "ram_data_for_disable_poling_conf_1": 0, + "ram_offset_bits_for_disable_poling_conf_1": 0, + "ram_stop_bit_for_disable_poling_conf_1": 1 + }, + "flash_wel_command": { + "flash_wel_opcode": 6, + "suppl_flash_wel_opcode": 0 + }, + "ram_wel_command": { + "ram_wel_opcode": 6, + "suppl_ram_wel_opcode": 0 + } + }, + "event": { + "host_nvic_irq": 0, + "core_10_mux_sel": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/w25q32jw/flash_disc_param_ext_mem.json b/boards/ti/lp_em_cc35x1/config/flash/w25q32jw/flash_disc_param_ext_mem.json new file mode 100644 index 000000000000..321810768be1 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/w25q32jw/flash_disc_param_ext_mem.json @@ -0,0 +1,99 @@ +{ + "vendor_primary_sbl": true, + "ti_wsoc_primary_container": true, + "ti_wsoc_bl2_primary_container": true, + "nvs_enable": true, + "vendor_alternate_image": true, + "vendor_sbl_alternate_image": true, + "ti_bl_alternate_image": true, + "ti_wsoc_alternate_image": true, + "ti_wsoc_bl2_alternate_image": true, + "region_0": { + "mem_region_0_start_phy_address": 1069056, + "mem_region_0_end_phy_address": 4194303, + "region0_boot": false, + "region0_main_code": true, + "region0_nvs": false, + "region0_wsoc_code": false, + "region0_alternate_code": false + }, + "region_1": { + "mem_region_1_start_phy_address": 0, + "mem_region_1_end_phy_address": 1069055, + "region1_boot": true, + "region1_main_code": false, + "region1_nvs": true, + "region1_wsoc_code": true, + "region1_alternate_code": false + }, + "region_2": { + "mem_region_2_start_phy_address": 0, + "mem_region_2_end_phy_address": 0, + "region2_boot": false, + "region2_main_code": false, + "region2_nvs": false, + "region2_wsoc_code": false, + "region2_alternate_code": true + }, + "region_3": { + "mem_region_3_start_phy_address": 0, + "mem_region_3_end_phy_address": 0, + "region3_boot": false, + "region3_main_code": false, + "region3_nvs": false, + "region3_wsoc_code": false, + "region3_alternate_code": false + }, + "boot_region_conf": { + "boot_region_size": 0, + "boot_region_flash_disco_param_start_address": 0, + "boot_region_primary_ti_bl_start_phy_address": 12284, + "boot_region_primary_ti_bl_magic": 0, + "boot_region_primary_ti_bl_major": 0, + "boot_region_primary_ti_bl_minor": 0, + "boot_region_sec_ti_bl_start_phy_address": 430076, + "boot_region_sec_ti_bl_magic": 0, + "boot_region_sec_ti_bl_major": 0, + "boot_region_sec_ti_bl_minor": 0 + }, + "main_code_region_conf": { + "main_code_region_vendor_image_start_phy_address": 1073148, + "main_code_region_vendor_image_magic": 0, + "main_code_region_vendor_image_major": 0, + "main_code_region_vendor_image_minor": 0, + "main_code_region_sbl_start_phy_address": 0, + "main_code_region_sbl_magic": 0, + "main_code_region_sbl_major": 0, + "main_code_region_sbl_minor": 0 + }, + "alt_code_region_conf": { + "alt_code_region_vendor_image_start_phy_address": 4194304, + "alt_code_region_vendor_image_magic": 0, + "alt_code_region_vendor_image_major": 0, + "alt_code_region_vendor_image_minor": 0, + "alt_code_region_sbl_start_phy_address": 0, + "alt_code_region_sbl_magic": 0, + "alt_code_region_sbl_major": 0, + "alt_code_region_sbl_minor": 0 + }, + "nvs_code_region_conf": { + "nvs_start_phy_address": 892928, + "nvs_region_size": 176128, + "nvs_region_primary_wsoc_start_phy_address": 430076, + "nvs_region_primary_wsoc_magic": 0, + "nvs_region_primary_wsoc_major": 0, + "nvs_region_primary_wsoc_minor": 0, + "nvs_region_sec_wsoc_start_phy_address": 897020, + "nvs_region_sec_wsoc_magic": 0, + "nvs_region_sec_wsoc_major": 0, + "nvs_region_sec_wsoc_minor": 0, + "nvs_region_primary_wsoc_bl2_start_phy_address": 0, + "nvs_region_primary_wsoc_bl2_magic": 0, + "nvs_region_primary_wsoc_bl2_major": 0, + "nvs_region_primary_wsoc_bl2_minor": 0, + "nvs_region_sec_wsoc_bl2_start_phy_address": 0, + "nvs_region_sec_wsoc_bl2_magic": 0, + "nvs_region_sec_wsoc_bl2_major": 0, + "nvs_region_sec_wsoc_bl2_minor": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/w25q32jw/flash_disc_param_otfde.json b/boards/ti/lp_em_cc35x1/config/flash/w25q32jw/flash_disc_param_otfde.json new file mode 100644 index 000000000000..efd3377fcf69 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/w25q32jw/flash_disc_param_otfde.json @@ -0,0 +1,286 @@ +{ + "otfde_header": { + "name": "OTFDEWFF3", + "flash_only": true, + "ip_protection": false, + "regions_lock": false, + "regions_number": 4, + "flash_enabled": true + }, + "bl_conf": { + "host_boot_done_lock": true, + "host_peripherals_lock": true, + "icache_conf_lock": true, + "m33_mem_part_lock": true, + "memss_firewall_lock": true, + "dma_channel_owner_lock": true, + "otfde_region_lock": true, + "core_events_lock": true + }, + "otfde_general": { + "parameters": { + "mem_otfde_initial_delay": 10, + "otfde_global_watchdog_timer": 5 + }, + "events": { + "reset_evt_mask": false, + "reset_evt_suspend": false, + "sft_reset_evt_mask": false, + "sft_reset_evt_suspend": false, + "bypass_mode_evt_mask": false, + "bypass_mode_evt_suspend": false, + "debug_mode_evt_mask": false, + "debug_mode_evt_suspend": false, + "general_evt_mask": false, + "general_evt_suspend": false, + "xspi_data_path_evt_mask": false, + "xspi_data_path_evt_suspend": false, + "xspi_cnfg_path_evt_mask": false, + "xspi_cnfg_path_evt_suspend": false, + "xspi_service_interrupt_evt_mask": false, + "xspi_service_interrupt_evt_suspend": false, + "trans_device_disabled_evt_mask": false, + "trans_device_disabled_evt_suspend": false, + "trans_region_disabled_evt_mask": false, + "trans_region_disabled_evt_suspend": false, + "trans_region_params_conf_evt_mask": false, + "trans_region_params_conf_evt_suspend": false, + "trans_multiple_regions_mapped_evt_mask": false, + "trans_multiple_regions_mapped_evt_suspend": false, + "trans_address_not_32_bit_evt_mask": false, + "trans_address_not_32_bit_evt_suspend": false, + "trans_size_not_32_bit_evt_mask": false, + "trans_size_not_32_bit_evt_suspend": false, + "trans_burst_not_32_bit_evt_mask": false, + "trans_burst_not_32_bit_evt_suspend": false, + "region_read_write_def_evt_mask": false, + "region_read_write_def_evt_suspend": false, + "suspend_while_disabled_evt_mask": false, + "suspend_while_disabled_evt_suspend": false + } + }, + "regions_settings": { + "region_parameters_lock": { + "REGION_0_PARAMS_0": true, + "REGION_0_PARAMS_1": true, + "REGION_0_PARAMS_2": true, + "REGION_1_PARAMS_0": false, + "REGION_1_PARAMS_1": false, + "REGION_1_PARAMS_2": false, + "REGION_2_PARAMS_0": true, + "REGION_2_PARAMS_1": true, + "REGION_2_PARAMS_2": true, + "REGION_3_PARAMS_0": false, + "REGION_3_PARAMS_1": false, + "REGION_3_PARAMS_2": false + }, + "region_0_protection": { + "mem_region_0_enabled": true, + "mem_region_0_device_id": 0, + "mem_region_0_spi_write_enable": true, + "mem_region_0_spi_read_enable": true, + "mem_region_0_physical_offset": 261, + "mem_region_0_security_id_msb": 0, + "mem_region_0_start_address": 81920, + "mem_region_0_end_address": 82682, + "mem_region_0_security_id_lsb": 0, + "mem_otfde_region_0_write_lock_en": false, + "mem_otfde_region_0_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_1_protection": { + "mem_region_1_enabled": true, + "mem_region_1_device_id": 0, + "mem_region_1_spi_write_enable": true, + "mem_region_1_spi_read_enable": true, + "mem_region_1_physical_offset": 0, + "mem_region_1_security_id_msb": 0, + "mem_region_1_start_address": 655360, + "mem_region_1_end_address": 655620, + "mem_region_1_security_id_lsb": 0, + "mem_otfde_region_1_write_lock_en": false, + "mem_otfde_region_1_enc_dec_bypass": "Bypass" + }, + "region_2_protection": { + "mem_region_2_enabled": false, + "mem_region_2_device_id": 0, + "mem_region_2_spi_write_enable": true, + "mem_region_2_spi_read_enable": true, + "mem_region_2_physical_offset": 0, + "mem_region_2_security_id_msb": 0, + "mem_region_2_start_address": 1, + "mem_region_2_end_address": 0, + "mem_region_2_security_id_lsb": 0, + "mem_otfde_region_2_write_lock_en": false, + "mem_otfde_region_2_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_3_protection": { + "mem_region_3_enabled": false, + "mem_region_3_device_id": 1, + "mem_region_3_spi_write_enable": true, + "mem_region_3_spi_read_enable": true, + "mem_region_3_physical_offset": 0, + "mem_region_3_security_id_msb": 0, + "mem_region_3_start_address": 1, + "mem_region_3_end_address": 0, + "mem_region_3_security_id_lsb": 0, + "mem_otfde_region_3_write_lock_en": false, + "mem_otfde_region_3_enc_dec_bypass": "Bypass" + } + }, + "devices": { + "header": { + "flash_device_switch_conf": 1, + "ram_device_switch_conf": 1 + }, + "flash_switch": { + "flash_grant_sel": 0, + "flash_data_for_conf_0": 2181562505, + "flash_offset_bits_for_conf_0": 0, + "flash_stop_bit_for_conf_0": 0, + "flash_data_for_conf_1": 134357515, + "flash_offset_bits_for_conf_1": 1, + "flash_stop_bit_for_conf_1": 0, + "flash_data_for_conf_2": 139266, + "flash_offset_bits_for_conf_2": 2, + "flash_stop_bit_for_conf_2": 0, + "flash_data_for_conf_3": 1, + "flash_offset_bits_for_conf_3": 4, + "flash_stop_bit_for_conf_3": 0, + "flash_data_for_conf_4": 1077739587, + "flash_offset_bits_for_conf_4": 45, + "flash_stop_bit_for_conf_4": 0, + "flash_data_for_conf_5": 3225223235, + "flash_offset_bits_for_conf_5": 45, + "flash_stop_bit_for_conf_5": 0, + "flash_data_for_conf_6": 262149, + "flash_offset_bits_for_conf_6": 14, + "flash_stop_bit_for_conf_6": 0, + "flash_data_for_conf_7": 0, + "flash_offset_bits_for_conf_7": 44, + "flash_stop_bit_for_conf_7": 1, + "flash_data_for_conf_8": 0, + "flash_offset_bits_for_conf_8": 0, + "flash_stop_bit_for_conf_8": 1, + "flash_data_for_conf_9": 0, + "flash_offset_bits_for_conf_9": 0, + "flash_stop_bit_for_conf_9": 1, + "flash_data_for_conf_10": 0, + "flash_offset_bits_for_conf_10": 0, + "flash_stop_bit_for_conf_10": 1, + "flash_data_for_conf_11": 0, + "flash_offset_bits_for_conf_11": 0, + "flash_stop_bit_for_conf_11": 1, + "flash_data_for_conf_12": 0, + "flash_offset_bits_for_conf_12": 0, + "flash_stop_bit_for_conf_12": 1, + "flash_data_for_conf_13": 0, + "flash_offset_bits_for_conf_13": 0, + "flash_stop_bit_for_conf_13": 1, + "flash_data_for_conf_14": 0, + "flash_offset_bits_for_conf_14": 0, + "flash_stop_bit_for_conf_14": 1, + "flash_data_for_conf_15": 0, + "flash_offset_bits_for_conf_15": 0, + "flash_stop_bit_for_conf_15": 1, + "flash_data_for_conf_16": 0, + "flash_offset_bits_for_conf_16": 0, + "flash_stop_bit_for_conf_16": 1, + "flash_data_for_conf_17": 0, + "flash_offset_bits_for_conf_17": 0, + "flash_stop_bit_for_conf_17": 1, + "flash_data_for_conf_18": 0, + "flash_offset_bits_for_conf_18": 0, + "flash_stop_bit_for_conf_18": 1, + "flash_data_for_conf_19": 0, + "flash_offset_bits_for_conf_19": 0, + "flash_stop_bit_for_conf_19": 1, + "flash_data_for_conf_20": 0, + "flash_offset_bits_for_conf_20": 0, + "flash_stop_bit_for_conf_20": 1, + "flash_data_for_conf_21": 0, + "flash_offset_bits_for_conf_21": 0, + "flash_stop_bit_for_conf_21": 1, + "flash_data_for_conf_22": 0, + "flash_offset_bits_for_conf_22": 0, + "flash_stop_bit_for_conf_22": 1, + "flash_data_for_conf_23": 0, + "flash_offset_bits_for_conf_23": 0, + "flash_stop_bit_for_conf_23": 1 + }, + "ram_switch": { + "ram_grant_sel": 0, + "ram_data_for_conf_0": 2181563529, + "ram_offset_bits_for_conf_0": 0, + "ram_stop_bit_for_conf_0": 0, + "ram_data_for_conf_1": 100803307, + "ram_offset_bits_for_conf_1": 1, + "ram_stop_bit_for_conf_1": 0, + "ram_data_for_conf_2": 139320, + "ram_offset_bits_for_conf_2": 2, + "ram_stop_bit_for_conf_2": 0, + "ram_data_for_conf_3": 3089693184, + "ram_offset_bits_for_conf_3": 56, + "ram_stop_bit_for_conf_3": 0, + "ram_data_for_conf_4": 1, + "ram_offset_bits_for_conf_4": 4, + "ram_stop_bit_for_conf_4": 0, + "ram_data_for_conf_5": 1076494399, + "ram_offset_bits_for_conf_5": 45, + "ram_stop_bit_for_conf_5": 0, + "ram_data_for_conf_6": 3223978047, + "ram_offset_bits_for_conf_6": 45, + "ram_stop_bit_for_conf_6": 0, + "ram_data_for_conf_7": 278533, + "ram_offset_bits_for_conf_7": 14, + "ram_stop_bit_for_conf_7": 0, + "ram_data_for_conf_8": 0, + "ram_offset_bits_for_conf_8": 44, + "ram_stop_bit_for_conf_8": 1, + "ram_data_for_conf_9": 0, + "ram_offset_bits_for_conf_9": 0, + "ram_stop_bit_for_conf_9": 1, + "ram_data_for_conf_10": 0, + "ram_offset_bits_for_conf_10": 0, + "ram_stop_bit_for_conf_10": 1, + "ram_data_for_conf_11": 0, + "ram_offset_bits_for_conf_11": 0, + "ram_stop_bit_for_conf_11": 1, + "ram_data_for_conf_12": 0, + "ram_offset_bits_for_conf_12": 0, + "ram_stop_bit_for_conf_12": 1, + "ram_data_for_conf_13": 0, + "ram_offset_bits_for_conf_13": 0, + "ram_stop_bit_for_conf_13": 1, + "ram_data_for_conf_14": 0, + "ram_offset_bits_for_conf_14": 0, + "ram_stop_bit_for_conf_14": 1, + "ram_data_for_conf_15": 0, + "ram_offset_bits_for_conf_15": 0, + "ram_stop_bit_for_conf_15": 1, + "ram_data_for_conf_16": 0, + "ram_offset_bits_for_conf_16": 0, + "ram_stop_bit_for_conf_16": 1, + "ram_data_for_conf_17": 0, + "ram_offset_bits_for_conf_17": 0, + "ram_stop_bit_for_conf_17": 1, + "ram_data_for_conf_18": 0, + "ram_offset_bits_for_conf_18": 0, + "ram_stop_bit_for_conf_18": 1, + "ram_data_for_conf_19": 0, + "ram_offset_bits_for_conf_19": 0, + "ram_stop_bit_for_conf_19": 1, + "ram_data_for_conf_20": 0, + "ram_offset_bits_for_conf_20": 0, + "ram_stop_bit_for_conf_20": 1, + "ram_data_for_conf_21": 0, + "ram_offset_bits_for_conf_21": 0, + "ram_stop_bit_for_conf_21": 1, + "ram_data_for_conf_22": 0, + "ram_offset_bits_for_conf_22": 0, + "ram_stop_bit_for_conf_22": 1, + "ram_data_for_conf_23": 0, + "ram_offset_bits_for_conf_23": 0, + "ram_stop_bit_for_conf_23": 1 + } + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/w25q32jw/flash_disc_param_xspi.json b/boards/ti/lp_em_cc35x1/config/flash/w25q32jw/flash_disc_param_xspi.json new file mode 100644 index 000000000000..28d58bb7fba2 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/w25q32jw/flash_disc_param_xspi.json @@ -0,0 +1,485 @@ +{ + "xspi_header": { + "name": "xSPIWFF3", + "device": "CC3500", + "use_hardware": "W25Q32JW", + "use_case": "Quadro", + "dqs_support": 0, + "flash_only": 1, + "flash_separate_reset": 0, + "ram_separate_reset": true, + "clock_frequency": 80, + "qospi_clock_divider": 1, + "flash_device_character_conf": 0, + "ram_device_character_conf": 0, + "header_advanced": 0, + "phy_mode_enable": 1, + "pipeline_mode_enable": 1, + "loopback_support": "No", + "qspi_ref_clock": 80, + "spi_clock_freq": 20, + "spi_clock_divider": 1, + "flash_device_size": 4, + "flash_bytes_per_block": 16, + "flash_bytes_per_page": 256, + "flash_number_of_address_bytes": 3, + "flash_dual_opcode": 0, + "flash_jedec_manufacturer_id": 0, + "flash_jedec_device_id": 0, + "flash_name": "W25Q32JW", + "flash_page_size": 256, + "flash_sector_size": 4096, + "flash_cs_polarity": "ACTIVE_LOW", + "flash_sw_reset_type": "x1xxxx", + "ram_device_size": 4, + "ram_bytes_per_block": 16, + "ram_bytes_per_page": 256, + "ram_number_of_address_bytes": 3, + "ram_dual_opcode": 0, + "ram_jedec_manufacturer_id": 0, + "ram_jedec_device_id": 0, + "ram_name": "NO_PSRAM", + "ram_page_size": 256, + "ram_sector_size": 4096, + "ram_cs_polarity": "ACTIVE_LOW", + "ram_sw_reset_type": "x1xxxx", + "flash_write_operation_modes": "4S-4S-4S", + "flash_read_operation_modes": "4S-4S-4S", + "ram_write_operation_modes": "4S-4S-4S", + "ram_read_operation_modes": "4S-4S-4S", + "crc_enable": 0, + "enable_dtr": 0, + "enable_ahb_decoder": 0, + "enter_xip_mod_immediately": 0, + "enter_xip_mod_next_read": 0, + "ahb_address_remapping": 0, + "enable_dma": 0, + "select_decode": 0, + "legacy_ip_mode": 0, + "direct_access": 1 + }, + "xspi_pinmux": { + "xspi_clk_input": 44, + "xspi_clk_input_use_hw": 0, + "xspi_clk_input_mode": "Input", + "xspi_clk_input_pull": "None", + "xspi_clk_input_interrupt_trigger": "Low", + "xspi_clk_input_dont_conf": 0, + "xspi_clk_input_output_strength": "High", + "xspi_clk_input_initial_output_state": "High", + "xspi_clk": 24, + "xspi_clk_use_hw": "None", + "xspi_clk_mode": "Output", + "xspi_clk_pull": "None", + "xspi_clk_output_strength": "High", + "xspi_clk_initial_output_state": "High", + "xspi_clk_interrupt_trigger": "None", + "xspi_clk_dont_conf": 0, + "xspi_flash_cs": 20, + "xspi_flash_cs_use_hw": "None", + "xspi_flash_cs_mode": "Output", + "xspi_flash_cs_pull": "None", + "xspi_flash_cs_output_strength": "High", + "xspi_flash_cs_initial_output_state": "High", + "xspi_flash_cs_interrupt_trigger": "None", + "xspi_flash_cs_dont_conf": 0, + "xspi_data_0": 25, + "xspi_data_0_use_hw": "None", + "xspi_data_0_mode": "Input", + "xspi_data_0_pull": "None", + "xspi_data_0_output_strength": "High", + "xspi_data_0_initial_output_state": "High", + "xspi_data_0_interrupt_trigger": "Low", + "xspi_data_0_dont_conf": 0, + "xspi_data_1": 21, + "xspi_data_1_use_hw": "None", + "xspi_data_1_mode": "Input", + "xspi_data_1_pull": "None", + "xspi_data_1_output_strength": "High", + "xspi_data_1_initial_output_state": "High", + "xspi_data_1_interrupt_trigger": "Low", + "xspi_data_1_dont_conf": 0, + "xspi_data_2": 22, + "xspi_data_2_use_hw": "None", + "xspi_data_2_mode": "Input", + "xspi_data_2_pull": "None", + "xspi_data_2_output_strength": "High", + "xspi_data_2_initial_output_state": "High", + "xspi_data_2_interrupt_trigger": "Low", + "xspi_data_2_dont_conf": 0, + "xspi_data_3": 23, + "xspi_data_3_use_hw": "None", + "xspi_data_3_mode": "Input", + "xspi_data_3_pull": "None", + "xspi_data_3_output_strength": "High", + "xspi_data_3_initial_output_state": "High", + "xspi_data_3_interrupt_trigger": "Low", + "xspi_data_3_dont_conf": 0, + "xspi_data_4": 26, + "xspi_data_4_use_hw": "None", + "xspi_data_4_mode": "Input", + "xspi_data_4_pull": "None", + "xspi_data_4_output_strength": "High", + "xspi_data_4_initial_output_state": "High", + "xspi_data_4_interrupt_trigger": "None", + "xspi_data_4_dont_conf": 0, + "xspi_data_5": 27, + "xspi_data_5_use_hw": "None", + "xspi_data_5_mode": "Input", + "xspi_data_5_pull": "None", + "xspi_data_5_output_strength": "High", + "xspi_data_5_initial_output_state": "High", + "xspi_data_5_interrupt_trigger": "None", + "xspi_data_5_dont_conf": 0, + "xspi_data_6": 28, + "xspi_data_6_use_hw": "None", + "xspi_data_6_mode": "Input", + "xspi_data_6_pull": "None", + "xspi_data_6_output_strength": "High", + "xspi_data_6_initial_output_state": "High", + "xspi_data_6_interrupt_trigger": "None", + "xspi_data_6_dont_conf": 0, + "xspi_data_7": 29, + "xspi_data_7_use_hw": "None", + "xspi_data_7_mode": "Input", + "xspi_data_7_pull": "None", + "xspi_data_7_output_strength": "High", + "xspi_data_7_initial_output_state": "High", + "xspi_data_7_interrupt_trigger": "None", + "xspi_data_7_dont_conf": 0, + "xspi_reset_flash": 36, + "xspi_reset_flash_use_hw": "None", + "xspi_reset_flash_mode": "Output", + "xspi_reset_flash_pull": "None", + "xspi_reset_flash_output_strength": "High", + "xspi_reset_flash_initial_output_state": "High", + "xspi_reset_flash_interrupt_trigger": "None", + "xspi_reset_flash_dont_conf": 0, + "xspi_cs_ram": 3, + "xspi_cs_ram_use_hw": "None", + "xspi_cs_ram_mode": "Output", + "xspi_cs_ram_pull": "None", + "xspi_cs_ram_output_strength": "High", + "xspi_cs_ram_initial_output_state": "High", + "xspi_cs_ram_interrupt_trigger": "None", + "xspi_cs_ram_dont_conf": 0, + "xspi_dqs": 30, + "xspi_dqs_use_hw": "None", + "xspi_dqs_mode": "Input", + "xspi_dqs_pull": "None", + "xspi_dqs_output_strength": "High", + "xspi_dqs_initial_output_state": "High", + "xspi_dqs_interrupt_trigger": "None", + "xspi_dqs_dont_conf": 0, + "xspi_reset_ram": 2, + "xspi_reset_ram_use_hw": "None", + "xspi_reset_ram_mode": "Input", + "xspi_reset_ram_pull": "None", + "xspi_reset_ram_output_strength": "High", + "xspi_reset_ram_initial_output_state": "High", + "xspi_reset_ram_interrupt_trigger": "None", + "xspi_reset_ram_dont_conf": 0 + }, + "xspi_operations": { + "xspi_operations_clocks": { + "clock_phase": 0, + "clock_polarity": 0, + "spi_mode": "2'b00" + }, + "xspi_operations_chip_select": { + "csda": 2, + "csdads": 0, + "cseot": 4, + "cssot": 1 + }, + "xspi_operations_reset": { + "flash_jedec_reset": 0, + "ram_jedec_reset": 0, + "flash_treset": 20, + "ram_treset": 20 + }, + "xspi_phy_operations": { + "flash_rx_dll_bypass_bit": 0, + "flash_dll_tx_delay": 61, + "flash_dll_rx_delay": 65, + "ram_rx_dll_bypass_bit": 0, + "ram_dll_tx_delay": 61, + "ram_dll_rx_delay": 65 + }, + "xspi_read_operations": { + "flash_dummy_rd_cycles": 8, + "flash_read_opcode": 11, + "suppl_flash_read_opcode": 0, + "ram_dummy_rd_cycles": 8, + "ram_read_opcode": 11, + "suppl_ram_read_opcode": 0, + "flash_non_cont_read_enable": 0, + "flash_max_read_jobs": 256, + "ram_non_cont_read_enable": 0, + "ram_max_read_jobs": 256, + "rww_en": 0, + "device_size": 4, + "number_of_banks": 1, + "bank_size": 4, + "mode_bit_enable": 0 + }, + "xspi_write_operations": { + "flash_address_and_data": { + "flash_dummy_wr_cycles": 0 + }, + "flash_command": { + "flash_write_opcode": 2, + "suppl_flash_write_opcode": 0 + }, + "ram_address_and_data": { + "ram_dummy_wr_cycles": 0 + }, + "ram_command": { + "ram_write_opcode": 2, + "suppl_ram_write_opcode": 0 + }, + "write_to_buffer": { + "flash_write_to_buffer_support": 0, + "ram_write_to_buffer_support": 0 + }, + "non_continuous_write": { + "flash_non_cont_write_enable": 0, + "flash_max_write_jobs": 64, + "ram_non_cont_write_enable": 0, + "ram_max_write_jobs": 0 + }, + "flash_program_operation": { + "flash_min_program_size": "256 B", + "flash_program_opcode": 2, + "suppl_flash_program_opcode": 0, + "flash_maximum_program_time_limit": 1600 + }, + "flash_erase_operation": { + "flash_min_erase_size": "4 kB", + "flash_erase_opcode": 32, + "suppl_flash_erase_opcode": 0, + "flash_maximum_erase_time_limit": 4095 + }, + "flash_erase_conf": { + "flash_block_erase_opcode": 0, + "suppl_block_flash_erase_opcode": 0, + "flash_sector_erase_opcode": 0, + "suppl_sector_flash_erase_opcode": 0, + "flash_chip_erase_opcode": 0, + "suppl_chip_flash_erase_opcode": 0 + }, + "ram_program_operation": { + "ram_min_program_size": "256 B", + "ram_program_opcode": 2, + "suppl_ram_program_opcode": 0, + "ram_maximum_program_time_limit": 1600 + }, + "ram_erase_conf": { + "ram_block_erase_opcode": 0, + "suppl_block_ram_erase_opcode": 0, + "ram_sector_erase_opcode": 0, + "suppl_sector_ram_erase_opcode": 0, + "ram_chip_erase_opcode": 0, + "suppl_chip_ram_erase_opcode": 0 + }, + "flash_buffer_support": { + "flash_pre_write_sequence": 0, + "flash_post_write_sequence": 0, + "flash_write_protection_timer_en": 0, + "flash_write_buffer_timer_mode": 16, + "flash_write_buffer_timer_range": 0, + "flash_service_interrupt_criteria": 0 + }, + "ram_buffer_support": { + "ram_pre_write_sequence": 0, + "ram_post_write_sequence": 0, + "ram_write_protection_timer_en": 0, + "ram_write_buffer_timer_mode": 16, + "ram_write_buffer_timer_range": 0, + "ram_service_interrupt_criteria": 0 + }, + "flash_pre_write_conf": { + "flash_pre_write_job_done_grant_sel": 0, + "data_for_flash_pre_write_conf_0": 0, + "offset_bits_for_flash_pre_write_conf_0": 0, + "stop_bit_for_flash_pre_write_conf_0": 1, + "data_for_flash_pre_write_conf_1": 0, + "offset_bits_for_flash_pre_write_conf_1": 0 + }, + "flash_post_write_conf": { + "flash_post_write_job_done_grant_sel": 0, + "data_for_flash_post_write_conf_0": 0, + "offset_bits_for_flash_post_write_conf_0": 0, + "stop_bit_for_flash_post_write_conf_0": 1, + "data_for_flash_post_write_conf_1": 0, + "offset_bits_for_flash_post_write_conf_1": 0 + }, + "ram_pre_write_conf": { + "ram_pre_write_job_done_grant_sel": 0, + "data_for_ram_pre_write_conf_0": 0, + "offset_bits_for_ram_pre_write_conf_0": 0, + "stop_bit_for_ram_pre_write_conf_0": 1, + "data_for_ram_pre_write_conf_1": 0, + "offset_bits_for_ram_pre_write_conf_1": 0 + }, + "ram_post_write_conf": { + "ram_post_write_job_done_grant_sel": 0, + "data_for_ram_post_write_conf_0": 0, + "offset_bits_for_ram_post_write_conf_0": 0, + "stop_bit_for_ram_post_write_conf_0": 1, + "data_for_ram_post_write_conf_1": 0, + "offset_bits_for_ram_post_write_conf_1": 0 + } + }, + "xspi_capture_operations": { + "read_data_capture": { + "flash_delay_transmitted_data": 0, + "flash_loopback_clock": 0, + "flash_bypass_adapted_loopback": 1, + "flash_sample_edge_sel": 0, + "ram_delay_transmitted_data": 0, + "ram_loopback_clock": 0, + "ram_bypass_adapted_loopback": 1, + "ram_sample_edge_sel": 0 + }, + "delays": { + "flash_full_half_cycle_delay": 0, + "flash_dll_bypass_mode": 1, + "flash_phase_detect_sel": 0, + "flash_dll_lock_num": 0, + "flash_dll_start_point": 0, + "flash_loopback_clock": 0, + "ram_full_half_cycle_delay": 0, + "ram_dll_bypass_mode": 1, + "ram_phase_detect_sel": 0, + "ram_dll_lock_num": 0, + "ram_dll_start_point": 0, + "ram_loopback_clock": 0 + }, + "operation_modes": { + "flash_sfdp_support": 0, + "ram_sfdp_support": 0, + "flash_pm_support": 0, + "ram_pm_support": 0, + "flash_sfdp_opcode": 0, + "suppl_flash_sfdp_opcode": 0, + "ram_sfdp_opcode": 0, + "suppl_ram_sfdp_opcode": 0, + "flash_enter_dpd_opcode": 185, + "suppl_flash_enter_dpd_opcode": 0, + "flash_exit_dpd_opcode": 171, + "suppl_flash_exit_dpd_opcode": 0, + "ram_enter_dpd_opcode": 185, + "suppl_ram_enter_dpd_opcode": 0, + "ram_exit_dpd_opcode": 171, + "suppl_ram_exit_dpd_opcode": 0, + "flash_quad_enable_opcode": 56, + "suppl_flash_quad_enable_opcode": 0, + "flash_quad_disable_opcode": 255, + "suppl_flash_quad_disable_opcode": 0, + "flash_octal_enable_opcode": 0, + "suppl_flash_octal_enable_opcode": 0, + "flash_octal_disable_opcode": 0, + "suppl_flash_octal_disable_opcode": 0, + "ram_quad_enable_opcode": 56, + "suppl_ram_quad_enable_opcode": 0, + "ram_quad_disable_opcode": 255, + "suppl_ram_quad_disable_opcode": 0, + "ram_octal_enable_opcode": 0, + "suppl_ram_octal_enable_opcode": 0, + "ram_octal_disable_opcode": 0, + "suppl_ram_octal_disable_opcode": 0 + } + } + }, + "external_memory_reporting": { + "header": { + "flash_auto_polling_enable": 1, + "flash_wel_enable": 1, + "flash_write_protect_enable": 0, + "flash_alternate_polling_conf_enable": 0, + "ram_auto_polling_enable": 1, + "ram_wel_enable": 1, + "ram_write_protect_enable": 0, + "ram_alternate_polling_conf_enable": 0 + }, + "flash_auto_polling": { + "flash_polling_repetition_delay": 0, + "flash_polling_count": 4, + "flash_enable_polling_expiration": 0, + "flash_polling_polarity": 0, + "flash_polling_address_phase_enable": 0, + "flash_polling_bit_index": 0, + "flash_numbers_poll_cycles": 65535, + "flash_dummy_autopoll_cycles": 0 + }, + "ram_auto_polling": { + "ram_polling_repetition_delay": 0, + "ram_polling_count": 4, + "ram_enable_polling_expiration": 0, + "ram_polling_polarity": 0, + "ram_polling_address_phase_enable": 0, + "ram_polling_bit_index": 0, + "ram_numbers_poll_cycles": 65535, + "ram_dummy_autopoll_cycles": 0 + }, + "flash_polling_command": { + "flash_polling_opcode": 5, + "suppl_flash_polling_opcode": 0 + }, + "ram_polling_command": { + "ram_polling_opcode": 5, + "suppl_ram_polling_opcode": 0 + }, + "flash_alternate_polling": { + "flash_polling_resp_count": 1023, + "flash_polling_iterations": 1, + "flash_polling_enabled": 0, + "flash_polling_disabled": 0, + "flash_grant_sel": 0, + "flash_data_for_enable_poling_conf_0": 0, + "flash_offset_bits_for_enable_poling_conf_0": 0, + "flash_stop_bit_for_enable_poling_conf_0": 1, + "flash_data_for_enable_poling_conf_1": 0, + "flash_offset_bits_for_enable_poling_conf_1": 0, + "flash_stop_bit_for_enable_poling_conf_1": 1, + "flash_data_for_disable_poling_conf_0": 0, + "flash_offset_bits_for_disable_poling_conf_0": 0, + "flash_stop_bit_for_disable_poling_conf_0": 1, + "flash_data_for_disable_poling_conf_1": 0, + "flash_offset_bits_for_disable_poling_conf_1": 0, + "flash_stop_bit_for_disable_poling_conf_1": 1 + }, + "ram_alternate_polling": { + "ram_polling_resp_count": 1023, + "ram_polling_iterations": 1, + "ram_polling_enabled": 0, + "ram_polling_disabled": 0, + "ram_grant_sel": 0, + "ram_data_for_enable_poling_conf_0": 0, + "ram_offset_bits_for_enable_poling_conf_0": 0, + "ram_stop_bit_for_enable_poling_conf_0": 1, + "ram_data_for_enable_poling_conf_1": 0, + "ram_offset_bits_for_enable_poling_conf_1": 0, + "ram_stop_bit_for_enable_poling_conf_1": 1, + "ram_data_for_disable_poling_conf_0": 0, + "ram_offset_bits_for_disable_poling_conf_0": 0, + "ram_stop_bit_for_disable_poling_conf_0": 1, + "ram_data_for_disable_poling_conf_1": 0, + "ram_offset_bits_for_disable_poling_conf_1": 0, + "ram_stop_bit_for_disable_poling_conf_1": 1 + }, + "flash_wel_command": { + "flash_wel_opcode": 6, + "suppl_flash_wel_opcode": 0 + }, + "ram_wel_command": { + "ram_wel_opcode": 6, + "suppl_ram_wel_opcode": 0 + } + }, + "event": { + "host_nvic_irq": 0, + "core_10_mux_sel": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/w25q33pw/flash_disc_param_ext_mem.json b/boards/ti/lp_em_cc35x1/config/flash/w25q33pw/flash_disc_param_ext_mem.json new file mode 100644 index 000000000000..321810768be1 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/w25q33pw/flash_disc_param_ext_mem.json @@ -0,0 +1,99 @@ +{ + "vendor_primary_sbl": true, + "ti_wsoc_primary_container": true, + "ti_wsoc_bl2_primary_container": true, + "nvs_enable": true, + "vendor_alternate_image": true, + "vendor_sbl_alternate_image": true, + "ti_bl_alternate_image": true, + "ti_wsoc_alternate_image": true, + "ti_wsoc_bl2_alternate_image": true, + "region_0": { + "mem_region_0_start_phy_address": 1069056, + "mem_region_0_end_phy_address": 4194303, + "region0_boot": false, + "region0_main_code": true, + "region0_nvs": false, + "region0_wsoc_code": false, + "region0_alternate_code": false + }, + "region_1": { + "mem_region_1_start_phy_address": 0, + "mem_region_1_end_phy_address": 1069055, + "region1_boot": true, + "region1_main_code": false, + "region1_nvs": true, + "region1_wsoc_code": true, + "region1_alternate_code": false + }, + "region_2": { + "mem_region_2_start_phy_address": 0, + "mem_region_2_end_phy_address": 0, + "region2_boot": false, + "region2_main_code": false, + "region2_nvs": false, + "region2_wsoc_code": false, + "region2_alternate_code": true + }, + "region_3": { + "mem_region_3_start_phy_address": 0, + "mem_region_3_end_phy_address": 0, + "region3_boot": false, + "region3_main_code": false, + "region3_nvs": false, + "region3_wsoc_code": false, + "region3_alternate_code": false + }, + "boot_region_conf": { + "boot_region_size": 0, + "boot_region_flash_disco_param_start_address": 0, + "boot_region_primary_ti_bl_start_phy_address": 12284, + "boot_region_primary_ti_bl_magic": 0, + "boot_region_primary_ti_bl_major": 0, + "boot_region_primary_ti_bl_minor": 0, + "boot_region_sec_ti_bl_start_phy_address": 430076, + "boot_region_sec_ti_bl_magic": 0, + "boot_region_sec_ti_bl_major": 0, + "boot_region_sec_ti_bl_minor": 0 + }, + "main_code_region_conf": { + "main_code_region_vendor_image_start_phy_address": 1073148, + "main_code_region_vendor_image_magic": 0, + "main_code_region_vendor_image_major": 0, + "main_code_region_vendor_image_minor": 0, + "main_code_region_sbl_start_phy_address": 0, + "main_code_region_sbl_magic": 0, + "main_code_region_sbl_major": 0, + "main_code_region_sbl_minor": 0 + }, + "alt_code_region_conf": { + "alt_code_region_vendor_image_start_phy_address": 4194304, + "alt_code_region_vendor_image_magic": 0, + "alt_code_region_vendor_image_major": 0, + "alt_code_region_vendor_image_minor": 0, + "alt_code_region_sbl_start_phy_address": 0, + "alt_code_region_sbl_magic": 0, + "alt_code_region_sbl_major": 0, + "alt_code_region_sbl_minor": 0 + }, + "nvs_code_region_conf": { + "nvs_start_phy_address": 892928, + "nvs_region_size": 176128, + "nvs_region_primary_wsoc_start_phy_address": 430076, + "nvs_region_primary_wsoc_magic": 0, + "nvs_region_primary_wsoc_major": 0, + "nvs_region_primary_wsoc_minor": 0, + "nvs_region_sec_wsoc_start_phy_address": 897020, + "nvs_region_sec_wsoc_magic": 0, + "nvs_region_sec_wsoc_major": 0, + "nvs_region_sec_wsoc_minor": 0, + "nvs_region_primary_wsoc_bl2_start_phy_address": 0, + "nvs_region_primary_wsoc_bl2_magic": 0, + "nvs_region_primary_wsoc_bl2_major": 0, + "nvs_region_primary_wsoc_bl2_minor": 0, + "nvs_region_sec_wsoc_bl2_start_phy_address": 0, + "nvs_region_sec_wsoc_bl2_magic": 0, + "nvs_region_sec_wsoc_bl2_major": 0, + "nvs_region_sec_wsoc_bl2_minor": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/w25q33pw/flash_disc_param_otfde.json b/boards/ti/lp_em_cc35x1/config/flash/w25q33pw/flash_disc_param_otfde.json new file mode 100644 index 000000000000..e4949eaa1add --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/w25q33pw/flash_disc_param_otfde.json @@ -0,0 +1,286 @@ +{ + "otfde_header": { + "name": "OTFDEWFF3", + "flash_only": true, + "ip_protection": false, + "regions_lock": false, + "regions_number": 4, + "flash_enabled": true + }, + "bl_conf": { + "host_boot_done_lock": true, + "host_peripherals_lock": true, + "icache_conf_lock": true, + "m33_mem_part_lock": true, + "memss_firewall_lock": true, + "dma_channel_owner_lock": true, + "otfde_region_lock": true, + "core_events_lock": true + }, + "otfde_general": { + "parameters": { + "mem_otfde_initial_delay": 10, + "otfde_global_watchdog_timer": 5 + }, + "events": { + "reset_evt_mask": false, + "reset_evt_suspend": false, + "sft_reset_evt_mask": false, + "sft_reset_evt_suspend": false, + "bypass_mode_evt_mask": false, + "bypass_mode_evt_suspend": false, + "debug_mode_evt_mask": false, + "debug_mode_evt_suspend": false, + "general_evt_mask": false, + "general_evt_suspend": false, + "xspi_data_path_evt_mask": false, + "xspi_data_path_evt_suspend": false, + "xspi_cnfg_path_evt_mask": false, + "xspi_cnfg_path_evt_suspend": false, + "xspi_service_interrupt_evt_mask": false, + "xspi_service_interrupt_evt_suspend": false, + "trans_device_disabled_evt_mask": false, + "trans_device_disabled_evt_suspend": false, + "trans_region_disabled_evt_mask": false, + "trans_region_disabled_evt_suspend": false, + "trans_region_params_conf_evt_mask": false, + "trans_region_params_conf_evt_suspend": false, + "trans_multiple_regions_mapped_evt_mask": false, + "trans_multiple_regions_mapped_evt_suspend": false, + "trans_address_not_32_bit_evt_mask": false, + "trans_address_not_32_bit_evt_suspend": false, + "trans_size_not_32_bit_evt_mask": false, + "trans_size_not_32_bit_evt_suspend": false, + "trans_burst_not_32_bit_evt_mask": false, + "trans_burst_not_32_bit_evt_suspend": false, + "region_read_write_def_evt_mask": false, + "region_read_write_def_evt_suspend": false, + "suspend_while_disabled_evt_mask": false, + "suspend_while_disabled_evt_suspend": false + } + }, + "regions_settings": { + "region_parameters_lock": { + "REGION_0_PARAMS_0": true, + "REGION_0_PARAMS_1": true, + "REGION_0_PARAMS_2": true, + "REGION_1_PARAMS_0": false, + "REGION_1_PARAMS_1": false, + "REGION_1_PARAMS_2": false, + "REGION_2_PARAMS_0": true, + "REGION_2_PARAMS_1": true, + "REGION_2_PARAMS_2": true, + "REGION_3_PARAMS_0": false, + "REGION_3_PARAMS_1": false, + "REGION_3_PARAMS_2": false + }, + "region_0_protection": { + "mem_region_0_enabled": true, + "mem_region_0_device_id": 0, + "mem_region_0_spi_write_enable": true, + "mem_region_0_spi_read_enable": true, + "mem_region_0_physical_offset": 261, + "mem_region_0_security_id_msb": 0, + "mem_region_0_start_address": 81920, + "mem_region_0_end_address": 82682, + "mem_region_0_security_id_lsb": 0, + "mem_otfde_region_0_write_lock_en": false, + "mem_otfde_region_0_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_1_protection": { + "mem_region_1_enabled": true, + "mem_region_1_device_id": 0, + "mem_region_1_spi_write_enable": true, + "mem_region_1_spi_read_enable": true, + "mem_region_1_physical_offset": 0, + "mem_region_1_security_id_msb": 0, + "mem_region_1_start_address": 655360, + "mem_region_1_end_address": 655620, + "mem_region_1_security_id_lsb": 0, + "mem_otfde_region_1_write_lock_en": false, + "mem_otfde_region_1_enc_dec_bypass": "Bypass" + }, + "region_2_protection": { + "mem_region_2_enabled": false, + "mem_region_2_device_id": 0, + "mem_region_2_spi_write_enable": true, + "mem_region_2_spi_read_enable": true, + "mem_region_2_physical_offset": 0, + "mem_region_2_security_id_msb": 0, + "mem_region_2_start_address": 1, + "mem_region_2_end_address": 0, + "mem_region_2_security_id_lsb": 0, + "mem_otfde_region_2_write_lock_en": false, + "mem_otfde_region_2_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_3_protection": { + "mem_region_3_enabled": false, + "mem_region_3_device_id": 1, + "mem_region_3_spi_write_enable": true, + "mem_region_3_spi_read_enable": true, + "mem_region_3_physical_offset": 0, + "mem_region_3_security_id_msb": 0, + "mem_region_3_start_address": 1, + "mem_region_3_end_address": 0, + "mem_region_3_security_id_lsb": 0, + "mem_otfde_region_3_write_lock_en": false, + "mem_otfde_region_3_enc_dec_bypass": "Bypass" + } + }, + "devices": { + "header": { + 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"ram_data_for_conf_23": 0, + "ram_offset_bits_for_conf_23": 0, + "ram_stop_bit_for_conf_23": 1 + } + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/w25q33pw/flash_disc_param_xspi.json b/boards/ti/lp_em_cc35x1/config/flash/w25q33pw/flash_disc_param_xspi.json new file mode 100644 index 000000000000..f4dbbdd0eba9 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/w25q33pw/flash_disc_param_xspi.json @@ -0,0 +1,485 @@ +{ + "xspi_header": { + "name": "xSPIWFF3", + "device": "CC3500", + "use_hardware": "W25Q33PW", + "use_case": "Quadro", + "dqs_support": 0, + "flash_only": 1, + "flash_separate_reset": 0, + "ram_separate_reset": true, + "clock_frequency": 80, + "qospi_clock_divider": 1, + "flash_device_character_conf": 0, + "ram_device_character_conf": 0, + "header_advanced": 0, + "phy_mode_enable": 1, + "pipeline_mode_enable": 1, + "loopback_support": "No", + "qspi_ref_clock": 80, + "spi_clock_freq": 20, + "spi_clock_divider": 1, + "flash_device_size": 4, + "flash_bytes_per_block": 16, + "flash_bytes_per_page": 256, + "flash_number_of_address_bytes": 3, + "flash_dual_opcode": 0, + "flash_jedec_manufacturer_id": 0, + "flash_jedec_device_id": 32790, + "flash_name": "W25Q33PW", + "flash_page_size": 256, + "flash_sector_size": 4096, + "flash_cs_polarity": "ACTIVE_LOW", + "flash_sw_reset_type": "x1xxxx", + "ram_device_size": 4, + "ram_bytes_per_block": 16, + "ram_bytes_per_page": 256, + "ram_number_of_address_bytes": 3, + "ram_dual_opcode": 0, + "ram_jedec_manufacturer_id": 0, + "ram_jedec_device_id": 32790, + "ram_name": "NO_PSRAM", + "ram_page_size": 256, + "ram_sector_size": 4096, + "ram_cs_polarity": "ACTIVE_LOW", + "ram_sw_reset_type": "x1xxxx", + "flash_write_operation_modes": "4S-4S-4S", + "flash_read_operation_modes": "4S-4S-4S", + "ram_write_operation_modes": "4S-4S-4S", + "ram_read_operation_modes": "4S-4S-4S", + "crc_enable": 0, + "enable_dtr": 0, + "enable_ahb_decoder": 0, + "enter_xip_mod_immediately": 0, + "enter_xip_mod_next_read": 0, + "ahb_address_remapping": 0, + "enable_dma": 0, + "select_decode": 0, + "legacy_ip_mode": 0, + "direct_access": 1 + }, + "xspi_pinmux": { + "xspi_clk_input": 44, + "xspi_clk_input_use_hw": 0, + "xspi_clk_input_mode": "Input", + "xspi_clk_input_pull": "None", + "xspi_clk_input_interrupt_trigger": "Low", + "xspi_clk_input_dont_conf": 0, + "xspi_clk_input_output_strength": "High", + "xspi_clk_input_initial_output_state": "High", + "xspi_clk": 24, + "xspi_clk_use_hw": "None", + "xspi_clk_mode": "Output", + "xspi_clk_pull": "None", + "xspi_clk_output_strength": "High", + "xspi_clk_initial_output_state": "High", + "xspi_clk_interrupt_trigger": "None", + "xspi_clk_dont_conf": 0, + "xspi_flash_cs": 20, + "xspi_flash_cs_use_hw": "None", + "xspi_flash_cs_mode": "Output", + "xspi_flash_cs_pull": "None", + "xspi_flash_cs_output_strength": "High", + "xspi_flash_cs_initial_output_state": "High", + "xspi_flash_cs_interrupt_trigger": "None", + "xspi_flash_cs_dont_conf": 0, + "xspi_data_0": 25, + "xspi_data_0_use_hw": "None", + "xspi_data_0_mode": "Input", + "xspi_data_0_pull": "None", + "xspi_data_0_output_strength": "High", + "xspi_data_0_initial_output_state": "High", + "xspi_data_0_interrupt_trigger": "Low", + "xspi_data_0_dont_conf": 0, + "xspi_data_1": 21, + "xspi_data_1_use_hw": "None", + "xspi_data_1_mode": "Input", + "xspi_data_1_pull": "None", + "xspi_data_1_output_strength": "High", + "xspi_data_1_initial_output_state": "High", + "xspi_data_1_interrupt_trigger": "Low", + "xspi_data_1_dont_conf": 0, + "xspi_data_2": 22, + "xspi_data_2_use_hw": "None", + "xspi_data_2_mode": "Input", + "xspi_data_2_pull": "None", + "xspi_data_2_output_strength": "High", + "xspi_data_2_initial_output_state": "High", + "xspi_data_2_interrupt_trigger": "Low", + "xspi_data_2_dont_conf": 0, + "xspi_data_3": 23, + "xspi_data_3_use_hw": "None", + "xspi_data_3_mode": "Input", + "xspi_data_3_pull": "None", + "xspi_data_3_output_strength": "High", + "xspi_data_3_initial_output_state": "High", + "xspi_data_3_interrupt_trigger": "Low", + "xspi_data_3_dont_conf": 0, + "xspi_data_4": 26, + "xspi_data_4_use_hw": "None", + "xspi_data_4_mode": "Input", + "xspi_data_4_pull": "None", + "xspi_data_4_output_strength": "High", + "xspi_data_4_initial_output_state": "High", + "xspi_data_4_interrupt_trigger": "None", + "xspi_data_4_dont_conf": 0, + "xspi_data_5": 27, + "xspi_data_5_use_hw": "None", + "xspi_data_5_mode": "Input", + "xspi_data_5_pull": "None", + "xspi_data_5_output_strength": "High", + "xspi_data_5_initial_output_state": "High", + "xspi_data_5_interrupt_trigger": "None", + "xspi_data_5_dont_conf": 0, + "xspi_data_6": 28, + "xspi_data_6_use_hw": "None", + "xspi_data_6_mode": "Input", + "xspi_data_6_pull": "None", + "xspi_data_6_output_strength": "High", + "xspi_data_6_initial_output_state": "High", + "xspi_data_6_interrupt_trigger": "None", + "xspi_data_6_dont_conf": 0, + "xspi_data_7": 29, + "xspi_data_7_use_hw": "None", + "xspi_data_7_mode": "Input", + "xspi_data_7_pull": "None", + "xspi_data_7_output_strength": "High", + "xspi_data_7_initial_output_state": "High", + "xspi_data_7_interrupt_trigger": "None", + "xspi_data_7_dont_conf": 0, + "xspi_reset_flash": 36, + "xspi_reset_flash_use_hw": "None", + "xspi_reset_flash_mode": "Output", + "xspi_reset_flash_pull": "None", + "xspi_reset_flash_output_strength": "High", + "xspi_reset_flash_initial_output_state": "High", + "xspi_reset_flash_interrupt_trigger": "None", + "xspi_reset_flash_dont_conf": 0, + "xspi_cs_ram": 3, + "xspi_cs_ram_use_hw": "None", + "xspi_cs_ram_mode": "Output", + "xspi_cs_ram_pull": "None", + "xspi_cs_ram_output_strength": "High", + "xspi_cs_ram_initial_output_state": "High", + "xspi_cs_ram_interrupt_trigger": "None", + "xspi_cs_ram_dont_conf": 0, + "xspi_dqs": 30, + "xspi_dqs_use_hw": "None", + "xspi_dqs_mode": "Input", + "xspi_dqs_pull": "None", + "xspi_dqs_output_strength": "High", + "xspi_dqs_initial_output_state": "High", + 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"flash_program_opcode": 2, + "suppl_flash_program_opcode": 0, + "flash_maximum_program_time_limit": 1600 + }, + "flash_erase_operation": { + "flash_min_erase_size": "4 kB", + "flash_erase_opcode": 32, + "suppl_flash_erase_opcode": 0, + "flash_maximum_erase_time_limit": 4095 + }, + "flash_erase_conf": { + "flash_block_erase_opcode": 0, + "suppl_block_flash_erase_opcode": 0, + "flash_sector_erase_opcode": 0, + "suppl_sector_flash_erase_opcode": 0, + "flash_chip_erase_opcode": 0, + "suppl_chip_flash_erase_opcode": 0 + }, + "ram_program_operation": { + "ram_min_program_size": "256 B", + "ram_program_opcode": 2, + "suppl_ram_program_opcode": 0, + "ram_maximum_program_time_limit": 1600 + }, + "ram_erase_conf": { + "ram_block_erase_opcode": 0, + "suppl_block_ram_erase_opcode": 0, + "ram_sector_erase_opcode": 0, + "suppl_sector_ram_erase_opcode": 0, + "ram_chip_erase_opcode": 0, + "suppl_chip_ram_erase_opcode": 0 + }, + "flash_buffer_support": { + "flash_pre_write_sequence": 0, + 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"offset_bits_for_flash_post_write_conf_1": 0 + }, + "ram_pre_write_conf": { + "ram_pre_write_job_done_grant_sel": 0, + "data_for_ram_pre_write_conf_0": 0, + "offset_bits_for_ram_pre_write_conf_0": 0, + "stop_bit_for_ram_pre_write_conf_0": 1, + "data_for_ram_pre_write_conf_1": 0, + "offset_bits_for_ram_pre_write_conf_1": 0 + }, + "ram_post_write_conf": { + "ram_post_write_job_done_grant_sel": 0, + "data_for_ram_post_write_conf_0": 0, + "offset_bits_for_ram_post_write_conf_0": 0, + "stop_bit_for_ram_post_write_conf_0": 1, + "data_for_ram_post_write_conf_1": 0, + "offset_bits_for_ram_post_write_conf_1": 0 + } + }, + "xspi_capture_operations": { + "read_data_capture": { + "flash_delay_transmitted_data": 0, + "flash_loopback_clock": 0, + "flash_bypass_adapted_loopback": 1, + "flash_sample_edge_sel": 0, + "ram_delay_transmitted_data": 0, + "ram_loopback_clock": 0, + "ram_bypass_adapted_loopback": 1, + "ram_sample_edge_sel": 0 + }, + "delays": { + "flash_full_half_cycle_delay": 0, + "flash_dll_bypass_mode": 1, + "flash_phase_detect_sel": 0, + "flash_dll_lock_num": 0, + "flash_dll_start_point": 0, + "flash_loopback_clock": 0, + "ram_full_half_cycle_delay": 0, + "ram_dll_bypass_mode": 1, + "ram_phase_detect_sel": 0, + "ram_dll_lock_num": 0, + "ram_dll_start_point": 0, + "ram_loopback_clock": 0 + }, + "operation_modes": { + "flash_sfdp_support": 0, + "ram_sfdp_support": 0, + "flash_pm_support": 0, + "ram_pm_support": 0, + "flash_sfdp_opcode": 0, + "suppl_flash_sfdp_opcode": 0, + "ram_sfdp_opcode": 0, + "suppl_ram_sfdp_opcode": 0, + "flash_enter_dpd_opcode": 185, + "suppl_flash_enter_dpd_opcode": 0, + "flash_exit_dpd_opcode": 171, + "suppl_flash_exit_dpd_opcode": 0, + "ram_enter_dpd_opcode": 185, + "suppl_ram_enter_dpd_opcode": 0, + "ram_exit_dpd_opcode": 171, + "suppl_ram_exit_dpd_opcode": 0, + "flash_quad_enable_opcode": 56, + "suppl_flash_quad_enable_opcode": 0, + "flash_quad_disable_opcode": 255, + "suppl_flash_quad_disable_opcode": 0, + "flash_octal_enable_opcode": 0, + "suppl_flash_octal_enable_opcode": 0, + "flash_octal_disable_opcode": 0, + "suppl_flash_octal_disable_opcode": 0, + "ram_quad_enable_opcode": 56, + "suppl_ram_quad_enable_opcode": 0, + "ram_quad_disable_opcode": 255, + "suppl_ram_quad_disable_opcode": 0, + "ram_octal_enable_opcode": 0, + "suppl_ram_octal_enable_opcode": 0, + "ram_octal_disable_opcode": 0, + "suppl_ram_octal_disable_opcode": 0 + } + } + }, + "external_memory_reporting": { + "header": { + "flash_auto_polling_enable": 1, + "flash_wel_enable": 1, + "flash_write_protect_enable": 0, + "flash_alternate_polling_conf_enable": 0, + "ram_auto_polling_enable": 1, + "ram_wel_enable": 1, + "ram_write_protect_enable": 0, + "ram_alternate_polling_conf_enable": 0 + }, + "flash_auto_polling": { + "flash_polling_repetition_delay": 0, + "flash_polling_count": 4, + "flash_enable_polling_expiration": 0, + "flash_polling_polarity": 0, + "flash_polling_address_phase_enable": 0, + "flash_polling_bit_index": 0, + "flash_numbers_poll_cycles": 65535, + "flash_dummy_autopoll_cycles": 0 + }, + "ram_auto_polling": { + "ram_polling_repetition_delay": 0, + "ram_polling_count": 4, + "ram_enable_polling_expiration": 0, + "ram_polling_polarity": 0, + "ram_polling_address_phase_enable": 0, + "ram_polling_bit_index": 0, + "ram_numbers_poll_cycles": 65535, + "ram_dummy_autopoll_cycles": 0 + }, + "flash_polling_command": { + "flash_polling_opcode": 5, + "suppl_flash_polling_opcode": 0 + }, + "ram_polling_command": { + "ram_polling_opcode": 5, + "suppl_ram_polling_opcode": 0 + }, + "flash_alternate_polling": { + "flash_polling_resp_count": 1023, + "flash_polling_iterations": 1, + "flash_polling_enabled": 0, + "flash_polling_disabled": 0, + "flash_grant_sel": 0, + "flash_data_for_enable_poling_conf_0": 0, + "flash_offset_bits_for_enable_poling_conf_0": 0, + "flash_stop_bit_for_enable_poling_conf_0": 1, + "flash_data_for_enable_poling_conf_1": 0, + "flash_offset_bits_for_enable_poling_conf_1": 0, + "flash_stop_bit_for_enable_poling_conf_1": 1, + "flash_data_for_disable_poling_conf_0": 0, + "flash_offset_bits_for_disable_poling_conf_0": 0, + "flash_stop_bit_for_disable_poling_conf_0": 1, + "flash_data_for_disable_poling_conf_1": 0, + "flash_offset_bits_for_disable_poling_conf_1": 0, + "flash_stop_bit_for_disable_poling_conf_1": 1 + }, + "ram_alternate_polling": { + "ram_polling_resp_count": 1023, + "ram_polling_iterations": 1, + "ram_polling_enabled": 0, + "ram_polling_disabled": 0, + "ram_grant_sel": 0, + "ram_data_for_enable_poling_conf_0": 0, + "ram_offset_bits_for_enable_poling_conf_0": 0, + "ram_stop_bit_for_enable_poling_conf_0": 1, + "ram_data_for_enable_poling_conf_1": 0, + "ram_offset_bits_for_enable_poling_conf_1": 0, + "ram_stop_bit_for_enable_poling_conf_1": 1, + "ram_data_for_disable_poling_conf_0": 0, + "ram_offset_bits_for_disable_poling_conf_0": 0, + "ram_stop_bit_for_disable_poling_conf_0": 1, + "ram_data_for_disable_poling_conf_1": 0, + "ram_offset_bits_for_disable_poling_conf_1": 0, + "ram_stop_bit_for_disable_poling_conf_1": 1 + }, + "flash_wel_command": { + "flash_wel_opcode": 6, + "suppl_flash_wel_opcode": 0 + }, + "ram_wel_command": { + "ram_wel_opcode": 6, + "suppl_ram_wel_opcode": 0 + } + }, + "event": { + "host_nvic_irq": 0, + "core_10_mux_sel": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/w25q64jw/flash_disc_param_ext_mem.json b/boards/ti/lp_em_cc35x1/config/flash/w25q64jw/flash_disc_param_ext_mem.json new file mode 100644 index 000000000000..6585853ccd5e --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/w25q64jw/flash_disc_param_ext_mem.json @@ -0,0 +1,99 @@ +{ + "vendor_primary_sbl": true, + "ti_wsoc_primary_container": true, + "ti_wsoc_bl2_primary_container": true, + "nvs_enable": true, + "vendor_alternate_image": true, + "vendor_sbl_alternate_image": true, + "ti_bl_alternate_image": true, + "ti_wsoc_alternate_image": true, + "ti_wsoc_bl2_alternate_image": true, + "region_0": { + "mem_region_0_start_phy_address": 2867200, + "mem_region_0_end_phy_address": 5627903, + "region0_boot": false, + "region0_main_code": true, + "region0_nvs": false, + "region0_wsoc_code": false, + "region0_alternate_code": false + }, + "region_1": { + "mem_region_1_start_phy_address": 0, + "mem_region_1_end_phy_address": 2867199, + "region1_boot": true, + "region1_main_code": false, + "region1_nvs": true, + "region1_wsoc_code": true, + "region1_alternate_code": false + }, + "region_2": { + "mem_region_2_start_phy_address": 5627904, + "mem_region_2_end_phy_address": 8388607, + "region2_boot": false, + "region2_main_code": false, + "region2_nvs": false, + "region2_wsoc_code": false, + "region2_alternate_code": true + }, + "region_3": { + "mem_region_3_start_phy_address": 0, + "mem_region_3_end_phy_address": 0, + "region3_boot": false, + "region3_main_code": false, + "region3_nvs": false, + "region3_wsoc_code": false, + "region3_alternate_code": false + }, + "boot_region_conf": { + "boot_region_size": 0, + "boot_region_flash_disco_param_start_address": 0, + "boot_region_primary_ti_bl_start_phy_address": 12284, + "boot_region_primary_ti_bl_magic": 0, + "boot_region_primary_ti_bl_major": 0, + "boot_region_primary_ti_bl_minor": 0, + "boot_region_sec_ti_bl_start_phy_address": 430076, + "boot_region_sec_ti_bl_magic": 0, + "boot_region_sec_ti_bl_major": 0, + "boot_region_sec_ti_bl_minor": 0 + }, + "main_code_region_conf": { + "main_code_region_vendor_image_start_phy_address": 2871292, + "main_code_region_vendor_image_magic": 0, + "main_code_region_vendor_image_major": 0, + "main_code_region_vendor_image_minor": 0, + "main_code_region_sbl_start_phy_address": 0, + "main_code_region_sbl_magic": 0, + "main_code_region_sbl_major": 0, + "main_code_region_sbl_minor": 0 + }, + "alt_code_region_conf": { + "alt_code_region_vendor_image_start_phy_address": 5631996, + "alt_code_region_vendor_image_magic": 0, + "alt_code_region_vendor_image_major": 0, + "alt_code_region_vendor_image_minor": 0, + "alt_code_region_sbl_start_phy_address": 0, + "alt_code_region_sbl_magic": 0, + "alt_code_region_sbl_major": 0, + "alt_code_region_sbl_minor": 0 + }, + "nvs_code_region_conf": { + "nvs_start_phy_address": 1777664, + "nvs_region_size": 1089536, + "nvs_region_primary_wsoc_start_phy_address": 847868, + "nvs_region_primary_wsoc_magic": 0, + "nvs_region_primary_wsoc_major": 0, + "nvs_region_primary_wsoc_minor": 0, + "nvs_region_sec_wsoc_start_phy_address": 1314812, + "nvs_region_sec_wsoc_magic": 0, + "nvs_region_sec_wsoc_major": 0, + "nvs_region_sec_wsoc_minor": 0, + "nvs_region_primary_wsoc_bl2_start_phy_address": 0, + "nvs_region_primary_wsoc_bl2_magic": 0, + "nvs_region_primary_wsoc_bl2_major": 0, + "nvs_region_primary_wsoc_bl2_minor": 0, + "nvs_region_sec_wsoc_bl2_start_phy_address": 0, + "nvs_region_sec_wsoc_bl2_magic": 0, + "nvs_region_sec_wsoc_bl2_major": 0, + "nvs_region_sec_wsoc_bl2_minor": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/w25q64jw/flash_disc_param_otfde.json b/boards/ti/lp_em_cc35x1/config/flash/w25q64jw/flash_disc_param_otfde.json new file mode 100644 index 000000000000..9d566e87bc6a --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/w25q64jw/flash_disc_param_otfde.json @@ -0,0 +1,286 @@ +{ + "otfde_header": { + "name": "OTFDEWFF3", + "flash_only": true, + "ip_protection": false, + "regions_lock": false, + "regions_number": 4, + "flash_enabled": true + }, + "bl_conf": { + "host_boot_done_lock": true, + "host_peripherals_lock": true, + "icache_conf_lock": true, + "m33_mem_part_lock": true, + "memss_firewall_lock": true, + "dma_channel_owner_lock": true, + "otfde_region_lock": true, + "core_events_lock": true + }, + "otfde_general": { + "parameters": { + "mem_otfde_initial_delay": 10, + "otfde_global_watchdog_timer": 5 + }, + "events": { + "reset_evt_mask": false, + "reset_evt_suspend": false, + "sft_reset_evt_mask": false, + "sft_reset_evt_suspend": false, + "bypass_mode_evt_mask": false, + "bypass_mode_evt_suspend": false, + "debug_mode_evt_mask": false, + "debug_mode_evt_suspend": false, + "general_evt_mask": false, + "general_evt_suspend": false, + "xspi_data_path_evt_mask": false, + "xspi_data_path_evt_suspend": false, + "xspi_cnfg_path_evt_mask": false, + "xspi_cnfg_path_evt_suspend": false, + "xspi_service_interrupt_evt_mask": false, + "xspi_service_interrupt_evt_suspend": false, + "trans_device_disabled_evt_mask": false, + "trans_device_disabled_evt_suspend": false, + "trans_region_disabled_evt_mask": false, + "trans_region_disabled_evt_suspend": false, + "trans_region_params_conf_evt_mask": false, + "trans_region_params_conf_evt_suspend": false, + "trans_multiple_regions_mapped_evt_mask": false, + "trans_multiple_regions_mapped_evt_suspend": false, + "trans_address_not_32_bit_evt_mask": false, + "trans_address_not_32_bit_evt_suspend": false, + "trans_size_not_32_bit_evt_mask": false, + "trans_size_not_32_bit_evt_suspend": false, + "trans_burst_not_32_bit_evt_mask": false, + "trans_burst_not_32_bit_evt_suspend": false, + "region_read_write_def_evt_mask": false, + "region_read_write_def_evt_suspend": false, + "suspend_while_disabled_evt_mask": false, + "suspend_while_disabled_evt_suspend": false + } + }, + "regions_settings": { + "region_parameters_lock": { + "REGION_0_PARAMS_0": true, + "REGION_0_PARAMS_1": true, + "REGION_0_PARAMS_2": true, + "REGION_1_PARAMS_0": false, + "REGION_1_PARAMS_1": false, + "REGION_1_PARAMS_2": false, + "REGION_2_PARAMS_0": true, + "REGION_2_PARAMS_1": true, + "REGION_2_PARAMS_2": true, + "REGION_3_PARAMS_0": false, + "REGION_3_PARAMS_1": false, + "REGION_3_PARAMS_2": false + }, + "region_0_protection": { + "mem_region_0_enabled": true, + "mem_region_0_device_id": 0, + "mem_region_0_spi_write_enable": true, + "mem_region_0_spi_read_enable": true, + "mem_region_0_physical_offset": 700, + "mem_region_0_security_id_msb": 0, + "mem_region_0_start_address": 81920, + "mem_region_0_end_address": 82593, + "mem_region_0_security_id_lsb": 0, + "mem_otfde_region_0_write_lock_en": false, + "mem_otfde_region_0_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_1_protection": { + "mem_region_1_enabled": true, + "mem_region_1_device_id": 0, + "mem_region_1_spi_write_enable": true, + "mem_region_1_spi_read_enable": true, + "mem_region_1_physical_offset": 0, + "mem_region_1_security_id_msb": 0, + "mem_region_1_start_address": 655360, + "mem_region_1_end_address": 656059, + "mem_region_1_security_id_lsb": 0, + "mem_otfde_region_1_write_lock_en": false, + "mem_otfde_region_1_enc_dec_bypass": "Bypass" + }, + "region_2_protection": { + "mem_region_2_enabled": true, + "mem_region_2_device_id": 0, + "mem_region_2_spi_write_enable": true, + "mem_region_2_spi_read_enable": true, + "mem_region_2_physical_offset": 1374, + "mem_region_2_security_id_msb": 0, + "mem_region_2_start_address": 671744, + "mem_region_2_end_address": 672417, + "mem_region_2_security_id_lsb": 0, + "mem_otfde_region_2_write_lock_en": false, + "mem_otfde_region_2_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_3_protection": { + "mem_region_3_enabled": false, + "mem_region_3_device_id": 1, + "mem_region_3_spi_write_enable": true, + "mem_region_3_spi_read_enable": true, + "mem_region_3_physical_offset": 0, + "mem_region_3_security_id_msb": 0, + "mem_region_3_start_address": 1, + "mem_region_3_end_address": 0, + "mem_region_3_security_id_lsb": 0, + "mem_otfde_region_3_write_lock_en": false, + "mem_otfde_region_3_enc_dec_bypass": "Bypass" + } + }, + "devices": { + "header": { + "flash_device_switch_conf": 1, + "ram_device_switch_conf": 1 + }, + "flash_switch": { + "flash_grant_sel": 0, + "flash_data_for_conf_0": 2181562505, + "flash_offset_bits_for_conf_0": 0, + "flash_stop_bit_for_conf_0": 0, + "flash_data_for_conf_1": 134357515, + "flash_offset_bits_for_conf_1": 1, + "flash_stop_bit_for_conf_1": 0, + "flash_data_for_conf_2": 139266, + "flash_offset_bits_for_conf_2": 2, + "flash_stop_bit_for_conf_2": 0, + "flash_data_for_conf_3": 1, + "flash_offset_bits_for_conf_3": 4, + "flash_stop_bit_for_conf_3": 0, + "flash_data_for_conf_4": 1077739587, + "flash_offset_bits_for_conf_4": 45, + "flash_stop_bit_for_conf_4": 0, + "flash_data_for_conf_5": 3225223235, + "flash_offset_bits_for_conf_5": 45, + "flash_stop_bit_for_conf_5": 0, + "flash_data_for_conf_6": 262149, + "flash_offset_bits_for_conf_6": 14, + "flash_stop_bit_for_conf_6": 0, + "flash_data_for_conf_7": 0, + "flash_offset_bits_for_conf_7": 44, + "flash_stop_bit_for_conf_7": 1, + "flash_data_for_conf_8": 0, + "flash_offset_bits_for_conf_8": 0, + "flash_stop_bit_for_conf_8": 1, + "flash_data_for_conf_9": 0, + "flash_offset_bits_for_conf_9": 0, + "flash_stop_bit_for_conf_9": 1, + "flash_data_for_conf_10": 0, + "flash_offset_bits_for_conf_10": 0, + "flash_stop_bit_for_conf_10": 1, + "flash_data_for_conf_11": 0, + "flash_offset_bits_for_conf_11": 0, + "flash_stop_bit_for_conf_11": 1, + "flash_data_for_conf_12": 0, + "flash_offset_bits_for_conf_12": 0, + "flash_stop_bit_for_conf_12": 1, + "flash_data_for_conf_13": 0, + "flash_offset_bits_for_conf_13": 0, + "flash_stop_bit_for_conf_13": 1, + "flash_data_for_conf_14": 0, + "flash_offset_bits_for_conf_14": 0, + "flash_stop_bit_for_conf_14": 1, + "flash_data_for_conf_15": 0, + "flash_offset_bits_for_conf_15": 0, + "flash_stop_bit_for_conf_15": 1, + "flash_data_for_conf_16": 0, + "flash_offset_bits_for_conf_16": 0, + "flash_stop_bit_for_conf_16": 1, + "flash_data_for_conf_17": 0, + "flash_offset_bits_for_conf_17": 0, + "flash_stop_bit_for_conf_17": 1, + "flash_data_for_conf_18": 0, + "flash_offset_bits_for_conf_18": 0, + "flash_stop_bit_for_conf_18": 1, + "flash_data_for_conf_19": 0, + "flash_offset_bits_for_conf_19": 0, + "flash_stop_bit_for_conf_19": 1, + "flash_data_for_conf_20": 0, + "flash_offset_bits_for_conf_20": 0, + "flash_stop_bit_for_conf_20": 1, + "flash_data_for_conf_21": 0, + "flash_offset_bits_for_conf_21": 0, + "flash_stop_bit_for_conf_21": 1, + "flash_data_for_conf_22": 0, + "flash_offset_bits_for_conf_22": 0, + "flash_stop_bit_for_conf_22": 1, + "flash_data_for_conf_23": 0, + "flash_offset_bits_for_conf_23": 0, + "flash_stop_bit_for_conf_23": 1 + }, + "ram_switch": { + "ram_grant_sel": 0, + "ram_data_for_conf_0": 2181563529, + "ram_offset_bits_for_conf_0": 0, + "ram_stop_bit_for_conf_0": 0, + "ram_data_for_conf_1": 100803307, + "ram_offset_bits_for_conf_1": 1, + "ram_stop_bit_for_conf_1": 0, + "ram_data_for_conf_2": 139320, + "ram_offset_bits_for_conf_2": 2, + "ram_stop_bit_for_conf_2": 0, + "ram_data_for_conf_3": 3089693184, + "ram_offset_bits_for_conf_3": 56, + "ram_stop_bit_for_conf_3": 0, + "ram_data_for_conf_4": 1, + "ram_offset_bits_for_conf_4": 4, + "ram_stop_bit_for_conf_4": 0, + "ram_data_for_conf_5": 1076494399, + "ram_offset_bits_for_conf_5": 45, + "ram_stop_bit_for_conf_5": 0, + "ram_data_for_conf_6": 3223978047, + "ram_offset_bits_for_conf_6": 45, + "ram_stop_bit_for_conf_6": 0, + "ram_data_for_conf_7": 278533, + "ram_offset_bits_for_conf_7": 14, + "ram_stop_bit_for_conf_7": 0, + "ram_data_for_conf_8": 0, + "ram_offset_bits_for_conf_8": 44, + "ram_stop_bit_for_conf_8": 1, + "ram_data_for_conf_9": 0, + "ram_offset_bits_for_conf_9": 0, + "ram_stop_bit_for_conf_9": 1, + "ram_data_for_conf_10": 0, + "ram_offset_bits_for_conf_10": 0, + "ram_stop_bit_for_conf_10": 1, + "ram_data_for_conf_11": 0, + "ram_offset_bits_for_conf_11": 0, + "ram_stop_bit_for_conf_11": 1, + "ram_data_for_conf_12": 0, + "ram_offset_bits_for_conf_12": 0, + "ram_stop_bit_for_conf_12": 1, + "ram_data_for_conf_13": 0, + "ram_offset_bits_for_conf_13": 0, + "ram_stop_bit_for_conf_13": 1, + "ram_data_for_conf_14": 0, + "ram_offset_bits_for_conf_14": 0, + "ram_stop_bit_for_conf_14": 1, + "ram_data_for_conf_15": 0, + "ram_offset_bits_for_conf_15": 0, + "ram_stop_bit_for_conf_15": 1, + "ram_data_for_conf_16": 0, + "ram_offset_bits_for_conf_16": 0, + "ram_stop_bit_for_conf_16": 1, + "ram_data_for_conf_17": 0, + "ram_offset_bits_for_conf_17": 0, + "ram_stop_bit_for_conf_17": 1, + "ram_data_for_conf_18": 0, + "ram_offset_bits_for_conf_18": 0, + "ram_stop_bit_for_conf_18": 1, + "ram_data_for_conf_19": 0, + "ram_offset_bits_for_conf_19": 0, + "ram_stop_bit_for_conf_19": 1, + "ram_data_for_conf_20": 0, + "ram_offset_bits_for_conf_20": 0, + "ram_stop_bit_for_conf_20": 1, + "ram_data_for_conf_21": 0, + "ram_offset_bits_for_conf_21": 0, + "ram_stop_bit_for_conf_21": 1, + "ram_data_for_conf_22": 0, + "ram_offset_bits_for_conf_22": 0, + "ram_stop_bit_for_conf_22": 1, + "ram_data_for_conf_23": 0, + "ram_offset_bits_for_conf_23": 0, + "ram_stop_bit_for_conf_23": 1 + } + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/w25q64jw/flash_disc_param_xspi.json b/boards/ti/lp_em_cc35x1/config/flash/w25q64jw/flash_disc_param_xspi.json new file mode 100644 index 000000000000..e2981a0f06d2 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/w25q64jw/flash_disc_param_xspi.json @@ -0,0 +1,485 @@ +{ + "xspi_header": { + "name": "xSPIWFF3", + "device": "CC3500", + "use_hardware": "W25Q64JW", + "use_case": "Quadro", + "dqs_support": 0, + "flash_only": 1, + "flash_separate_reset": 0, + "ram_separate_reset": true, + "clock_frequency": 80, + "qospi_clock_divider": 1, + "flash_device_character_conf": 0, + "ram_device_character_conf": 0, + "header_advanced": 0, + "phy_mode_enable": 1, + "pipeline_mode_enable": 1, + "loopback_support": "No", + "qspi_ref_clock": 80, + "spi_clock_freq": 20, + "spi_clock_divider": 1, + "flash_device_size": 8, + "flash_bytes_per_block": 16, + "flash_bytes_per_page": 256, + "flash_number_of_address_bytes": 3, + "flash_dual_opcode": 0, + "flash_jedec_manufacturer_id": 0, + "flash_jedec_device_id": 0, + "flash_name": "W25Q64JW", + "flash_page_size": 256, + "flash_sector_size": 4096, + "flash_cs_polarity": "ACTIVE_LOW", + "flash_sw_reset_type": "x1xxxx", + "ram_device_size": 8, + "ram_bytes_per_block": 16, + "ram_bytes_per_page": 256, + "ram_number_of_address_bytes": 3, + "ram_dual_opcode": 0, + "ram_jedec_manufacturer_id": 0, + "ram_jedec_device_id": 0, + "ram_name": "NO_PSRAM", + "ram_page_size": 256, + "ram_sector_size": 4096, + "ram_cs_polarity": "ACTIVE_LOW", + "ram_sw_reset_type": "x1xxxx", + "flash_write_operation_modes": "4S-4S-4S", + "flash_read_operation_modes": "4S-4S-4S", + "ram_write_operation_modes": "4S-4S-4S", + "ram_read_operation_modes": "4S-4S-4S", + "crc_enable": 0, + "enable_dtr": 0, + "enable_ahb_decoder": 0, + "enter_xip_mod_immediately": 0, + "enter_xip_mod_next_read": 0, + "ahb_address_remapping": 0, + "enable_dma": 0, + "select_decode": 0, + "legacy_ip_mode": 0, + "direct_access": 1 + }, + "xspi_pinmux": { + "xspi_clk_input": 44, + "xspi_clk_input_use_hw": 0, + "xspi_clk_input_mode": "Input", + "xspi_clk_input_pull": "None", + "xspi_clk_input_interrupt_trigger": "Low", + "xspi_clk_input_dont_conf": 0, + "xspi_clk_input_output_strength": "High", + "xspi_clk_input_initial_output_state": "High", + "xspi_clk": 24, + "xspi_clk_use_hw": "None", + "xspi_clk_mode": "Output", + "xspi_clk_pull": "None", + "xspi_clk_output_strength": "High", + "xspi_clk_initial_output_state": "High", + "xspi_clk_interrupt_trigger": "None", + "xspi_clk_dont_conf": 0, + "xspi_flash_cs": 20, + "xspi_flash_cs_use_hw": "None", + "xspi_flash_cs_mode": "Output", + "xspi_flash_cs_pull": "None", + "xspi_flash_cs_output_strength": "High", + "xspi_flash_cs_initial_output_state": "High", + "xspi_flash_cs_interrupt_trigger": "None", + "xspi_flash_cs_dont_conf": 0, + "xspi_data_0": 25, + "xspi_data_0_use_hw": "None", + "xspi_data_0_mode": "Input", + "xspi_data_0_pull": "None", + "xspi_data_0_output_strength": "High", + "xspi_data_0_initial_output_state": "High", + "xspi_data_0_interrupt_trigger": "Low", + "xspi_data_0_dont_conf": 0, + "xspi_data_1": 21, + "xspi_data_1_use_hw": "None", + "xspi_data_1_mode": "Input", + "xspi_data_1_pull": "None", + "xspi_data_1_output_strength": "High", + "xspi_data_1_initial_output_state": "High", + "xspi_data_1_interrupt_trigger": "Low", + "xspi_data_1_dont_conf": 0, + "xspi_data_2": 22, + "xspi_data_2_use_hw": "None", + "xspi_data_2_mode": "Input", + "xspi_data_2_pull": "None", + "xspi_data_2_output_strength": "High", + "xspi_data_2_initial_output_state": "High", + "xspi_data_2_interrupt_trigger": "Low", + "xspi_data_2_dont_conf": 0, + "xspi_data_3": 23, + "xspi_data_3_use_hw": "None", + "xspi_data_3_mode": "Input", + "xspi_data_3_pull": "None", + "xspi_data_3_output_strength": "High", + "xspi_data_3_initial_output_state": "High", + "xspi_data_3_interrupt_trigger": "Low", + "xspi_data_3_dont_conf": 0, + "xspi_data_4": 26, + "xspi_data_4_use_hw": "None", + "xspi_data_4_mode": "Input", + "xspi_data_4_pull": "None", + "xspi_data_4_output_strength": "High", + "xspi_data_4_initial_output_state": "High", + "xspi_data_4_interrupt_trigger": "None", + "xspi_data_4_dont_conf": 0, + "xspi_data_5": 27, + "xspi_data_5_use_hw": "None", + "xspi_data_5_mode": "Input", + "xspi_data_5_pull": "None", + "xspi_data_5_output_strength": "High", + "xspi_data_5_initial_output_state": "High", + "xspi_data_5_interrupt_trigger": "None", + "xspi_data_5_dont_conf": 0, + "xspi_data_6": 28, + "xspi_data_6_use_hw": "None", + "xspi_data_6_mode": "Input", + "xspi_data_6_pull": "None", + "xspi_data_6_output_strength": "High", + "xspi_data_6_initial_output_state": "High", + "xspi_data_6_interrupt_trigger": "None", + "xspi_data_6_dont_conf": 0, + "xspi_data_7": 29, + "xspi_data_7_use_hw": "None", + "xspi_data_7_mode": "Input", + "xspi_data_7_pull": "None", + "xspi_data_7_output_strength": "High", + "xspi_data_7_initial_output_state": "High", + "xspi_data_7_interrupt_trigger": "None", + "xspi_data_7_dont_conf": 0, + "xspi_reset_flash": 36, + "xspi_reset_flash_use_hw": "None", + "xspi_reset_flash_mode": "Output", + "xspi_reset_flash_pull": "None", + "xspi_reset_flash_output_strength": "High", + "xspi_reset_flash_initial_output_state": "High", + "xspi_reset_flash_interrupt_trigger": "None", + "xspi_reset_flash_dont_conf": 0, + "xspi_cs_ram": 3, + "xspi_cs_ram_use_hw": "None", + "xspi_cs_ram_mode": "Output", + "xspi_cs_ram_pull": "None", + "xspi_cs_ram_output_strength": "High", + "xspi_cs_ram_initial_output_state": "High", + "xspi_cs_ram_interrupt_trigger": "None", + "xspi_cs_ram_dont_conf": 0, + "xspi_dqs": 30, + "xspi_dqs_use_hw": "None", + "xspi_dqs_mode": "Input", + "xspi_dqs_pull": "None", + "xspi_dqs_output_strength": "High", + "xspi_dqs_initial_output_state": "High", + "xspi_dqs_interrupt_trigger": "None", + "xspi_dqs_dont_conf": 0, + "xspi_reset_ram": 2, + "xspi_reset_ram_use_hw": "None", + "xspi_reset_ram_mode": "Input", + "xspi_reset_ram_pull": "None", + "xspi_reset_ram_output_strength": "High", + "xspi_reset_ram_initial_output_state": "High", + "xspi_reset_ram_interrupt_trigger": "None", + "xspi_reset_ram_dont_conf": 0 + }, + "xspi_operations": { + "xspi_operations_clocks": { + "clock_phase": 0, + "clock_polarity": 0, + "spi_mode": "2'b00" + }, + "xspi_operations_chip_select": { + "csda": 2, + "csdads": 0, + "cseot": 4, + "cssot": 1 + }, + "xspi_operations_reset": { + "flash_jedec_reset": 0, + "ram_jedec_reset": 0, + "flash_treset": 20, + "ram_treset": 20 + }, + "xspi_phy_operations": { + "flash_rx_dll_bypass_bit": 0, + "flash_dll_tx_delay": 61, + "flash_dll_rx_delay": 65, + "ram_rx_dll_bypass_bit": 0, + "ram_dll_tx_delay": 61, + "ram_dll_rx_delay": 65 + }, + "xspi_read_operations": { + "flash_dummy_rd_cycles": 8, + "flash_read_opcode": 11, + "suppl_flash_read_opcode": 0, + "ram_dummy_rd_cycles": 8, + "ram_read_opcode": 11, + "suppl_ram_read_opcode": 0, + "flash_non_cont_read_enable": 0, + "flash_max_read_jobs": 256, + "ram_non_cont_read_enable": 0, + "ram_max_read_jobs": 256, + "rww_en": 0, + "device_size": 8, + "number_of_banks": 1, + "bank_size": 8, + "mode_bit_enable": 0 + }, + "xspi_write_operations": { + "flash_address_and_data": { + "flash_dummy_wr_cycles": 0 + }, + "flash_command": { + "flash_write_opcode": 2, + "suppl_flash_write_opcode": 0 + }, + "ram_address_and_data": { + "ram_dummy_wr_cycles": 0 + }, + "ram_command": { + "ram_write_opcode": 2, + "suppl_ram_write_opcode": 0 + }, + "write_to_buffer": { + "flash_write_to_buffer_support": 0, + "ram_write_to_buffer_support": 0 + }, + "non_continuous_write": { + "flash_non_cont_write_enable": 0, + "flash_max_write_jobs": 64, + "ram_non_cont_write_enable": 0, + "ram_max_write_jobs": 0 + }, + "flash_program_operation": { + "flash_min_program_size": "256 B", + "flash_program_opcode": 2, + "suppl_flash_program_opcode": 0, + "flash_maximum_program_time_limit": 1600 + }, + "flash_erase_operation": { + "flash_min_erase_size": "4 kB", + "flash_erase_opcode": 32, + "suppl_flash_erase_opcode": 0, + "flash_maximum_erase_time_limit": 4095 + }, + "flash_erase_conf": { + "flash_block_erase_opcode": 0, + "suppl_block_flash_erase_opcode": 0, + "flash_sector_erase_opcode": 0, + "suppl_sector_flash_erase_opcode": 0, + "flash_chip_erase_opcode": 0, + "suppl_chip_flash_erase_opcode": 0 + }, + "ram_program_operation": { + "ram_min_program_size": "256 B", + "ram_program_opcode": 2, + "suppl_ram_program_opcode": 0, + "ram_maximum_program_time_limit": 1600 + }, + "ram_erase_conf": { + "ram_block_erase_opcode": 0, + "suppl_block_ram_erase_opcode": 0, + "ram_sector_erase_opcode": 0, + "suppl_sector_ram_erase_opcode": 0, + "ram_chip_erase_opcode": 0, + "suppl_chip_ram_erase_opcode": 0 + }, + "flash_buffer_support": { + "flash_pre_write_sequence": 0, + "flash_post_write_sequence": 0, + "flash_write_protection_timer_en": 0, + "flash_write_buffer_timer_mode": 16, + "flash_write_buffer_timer_range": 0, + "flash_service_interrupt_criteria": 0 + }, + "ram_buffer_support": { + "ram_pre_write_sequence": 0, + "ram_post_write_sequence": 0, + "ram_write_protection_timer_en": 0, + "ram_write_buffer_timer_mode": 16, + "ram_write_buffer_timer_range": 0, + "ram_service_interrupt_criteria": 0 + }, + "flash_pre_write_conf": { + "flash_pre_write_job_done_grant_sel": 0, + "data_for_flash_pre_write_conf_0": 0, + "offset_bits_for_flash_pre_write_conf_0": 0, + "stop_bit_for_flash_pre_write_conf_0": 1, + "data_for_flash_pre_write_conf_1": 0, + "offset_bits_for_flash_pre_write_conf_1": 0 + }, + "flash_post_write_conf": { + "flash_post_write_job_done_grant_sel": 0, + "data_for_flash_post_write_conf_0": 0, + "offset_bits_for_flash_post_write_conf_0": 0, + "stop_bit_for_flash_post_write_conf_0": 1, + "data_for_flash_post_write_conf_1": 0, + "offset_bits_for_flash_post_write_conf_1": 0 + }, + "ram_pre_write_conf": { + "ram_pre_write_job_done_grant_sel": 0, + "data_for_ram_pre_write_conf_0": 0, + "offset_bits_for_ram_pre_write_conf_0": 0, + "stop_bit_for_ram_pre_write_conf_0": 1, + "data_for_ram_pre_write_conf_1": 0, + "offset_bits_for_ram_pre_write_conf_1": 0 + }, + "ram_post_write_conf": { + "ram_post_write_job_done_grant_sel": 0, + "data_for_ram_post_write_conf_0": 0, + "offset_bits_for_ram_post_write_conf_0": 0, + "stop_bit_for_ram_post_write_conf_0": 1, + "data_for_ram_post_write_conf_1": 0, + "offset_bits_for_ram_post_write_conf_1": 0 + } + }, + "xspi_capture_operations": { + "read_data_capture": { + "flash_delay_transmitted_data": 0, + "flash_loopback_clock": 0, + "flash_bypass_adapted_loopback": 1, + "flash_sample_edge_sel": 0, + "ram_delay_transmitted_data": 0, + "ram_loopback_clock": 0, + "ram_bypass_adapted_loopback": 1, + "ram_sample_edge_sel": 0 + }, + "delays": { + "flash_full_half_cycle_delay": 0, + "flash_dll_bypass_mode": 1, + "flash_phase_detect_sel": 0, + "flash_dll_lock_num": 0, + "flash_dll_start_point": 0, + "flash_loopback_clock": 0, + "ram_full_half_cycle_delay": 0, + "ram_dll_bypass_mode": 1, + "ram_phase_detect_sel": 0, + "ram_dll_lock_num": 0, + "ram_dll_start_point": 0, + "ram_loopback_clock": 0 + }, + "operation_modes": { + "flash_sfdp_support": 0, + "ram_sfdp_support": 0, + "flash_pm_support": 0, + "ram_pm_support": 0, + "flash_sfdp_opcode": 0, + "suppl_flash_sfdp_opcode": 0, + "ram_sfdp_opcode": 0, + "suppl_ram_sfdp_opcode": 0, + "flash_enter_dpd_opcode": 185, + "suppl_flash_enter_dpd_opcode": 0, + "flash_exit_dpd_opcode": 171, + "suppl_flash_exit_dpd_opcode": 0, + "ram_enter_dpd_opcode": 185, + "suppl_ram_enter_dpd_opcode": 0, + "ram_exit_dpd_opcode": 171, + "suppl_ram_exit_dpd_opcode": 0, + "flash_quad_enable_opcode": 56, + "suppl_flash_quad_enable_opcode": 0, + "flash_quad_disable_opcode": 255, + "suppl_flash_quad_disable_opcode": 0, + "flash_octal_enable_opcode": 0, + "suppl_flash_octal_enable_opcode": 0, + "flash_octal_disable_opcode": 0, + "suppl_flash_octal_disable_opcode": 0, + "ram_quad_enable_opcode": 56, + "suppl_ram_quad_enable_opcode": 0, + "ram_quad_disable_opcode": 255, + "suppl_ram_quad_disable_opcode": 0, + "ram_octal_enable_opcode": 0, + "suppl_ram_octal_enable_opcode": 0, + "ram_octal_disable_opcode": 0, + "suppl_ram_octal_disable_opcode": 0 + } + } + }, + "external_memory_reporting": { + "header": { + "flash_auto_polling_enable": 1, + "flash_wel_enable": 1, + "flash_write_protect_enable": 0, + "flash_alternate_polling_conf_enable": 0, + "ram_auto_polling_enable": 1, + "ram_wel_enable": 1, + "ram_write_protect_enable": 0, + "ram_alternate_polling_conf_enable": 0 + }, + "flash_auto_polling": { + "flash_polling_repetition_delay": 0, + "flash_polling_count": 4, + "flash_enable_polling_expiration": 0, + "flash_polling_polarity": 0, + "flash_polling_address_phase_enable": 0, + "flash_polling_bit_index": 0, + "flash_numbers_poll_cycles": 65535, + "flash_dummy_autopoll_cycles": 0 + }, + "ram_auto_polling": { + "ram_polling_repetition_delay": 0, + "ram_polling_count": 4, + "ram_enable_polling_expiration": 0, + "ram_polling_polarity": 0, + "ram_polling_address_phase_enable": 0, + "ram_polling_bit_index": 0, + "ram_numbers_poll_cycles": 65535, + "ram_dummy_autopoll_cycles": 0 + }, + "flash_polling_command": { + "flash_polling_opcode": 5, + "suppl_flash_polling_opcode": 0 + }, + "ram_polling_command": { + "ram_polling_opcode": 5, + "suppl_ram_polling_opcode": 0 + }, + "flash_alternate_polling": { + "flash_polling_resp_count": 1023, + "flash_polling_iterations": 1, + "flash_polling_enabled": 0, + "flash_polling_disabled": 0, + "flash_grant_sel": 0, + "flash_data_for_enable_poling_conf_0": 0, + "flash_offset_bits_for_enable_poling_conf_0": 0, + "flash_stop_bit_for_enable_poling_conf_0": 1, + "flash_data_for_enable_poling_conf_1": 0, + "flash_offset_bits_for_enable_poling_conf_1": 0, + "flash_stop_bit_for_enable_poling_conf_1": 1, + "flash_data_for_disable_poling_conf_0": 0, + "flash_offset_bits_for_disable_poling_conf_0": 0, + "flash_stop_bit_for_disable_poling_conf_0": 1, + "flash_data_for_disable_poling_conf_1": 0, + "flash_offset_bits_for_disable_poling_conf_1": 0, + "flash_stop_bit_for_disable_poling_conf_1": 1 + }, + "ram_alternate_polling": { + "ram_polling_resp_count": 1023, + "ram_polling_iterations": 1, + "ram_polling_enabled": 0, + "ram_polling_disabled": 0, + "ram_grant_sel": 0, + "ram_data_for_enable_poling_conf_0": 0, + "ram_offset_bits_for_enable_poling_conf_0": 0, + "ram_stop_bit_for_enable_poling_conf_0": 1, + "ram_data_for_enable_poling_conf_1": 0, + "ram_offset_bits_for_enable_poling_conf_1": 0, + "ram_stop_bit_for_enable_poling_conf_1": 1, + "ram_data_for_disable_poling_conf_0": 0, + "ram_offset_bits_for_disable_poling_conf_0": 0, + "ram_stop_bit_for_disable_poling_conf_0": 1, + "ram_data_for_disable_poling_conf_1": 0, + "ram_offset_bits_for_disable_poling_conf_1": 0, + "ram_stop_bit_for_disable_poling_conf_1": 1 + }, + "flash_wel_command": { + "flash_wel_opcode": 6, + "suppl_flash_wel_opcode": 0 + }, + "ram_wel_command": { + "ram_wel_opcode": 6, + "suppl_ram_wel_opcode": 0 + } + }, + "event": { + "host_nvic_irq": 0, + "core_10_mux_sel": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/w25q64pw/flash_disc_param_ext_mem.json b/boards/ti/lp_em_cc35x1/config/flash/w25q64pw/flash_disc_param_ext_mem.json new file mode 100644 index 000000000000..6585853ccd5e --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/w25q64pw/flash_disc_param_ext_mem.json @@ -0,0 +1,99 @@ +{ + "vendor_primary_sbl": true, + "ti_wsoc_primary_container": true, + "ti_wsoc_bl2_primary_container": true, + "nvs_enable": true, + "vendor_alternate_image": true, + "vendor_sbl_alternate_image": true, + "ti_bl_alternate_image": true, + "ti_wsoc_alternate_image": true, + "ti_wsoc_bl2_alternate_image": true, + "region_0": { + "mem_region_0_start_phy_address": 2867200, + "mem_region_0_end_phy_address": 5627903, + "region0_boot": false, + "region0_main_code": true, + "region0_nvs": false, + "region0_wsoc_code": false, + "region0_alternate_code": false + }, + "region_1": { + "mem_region_1_start_phy_address": 0, + "mem_region_1_end_phy_address": 2867199, + "region1_boot": true, + "region1_main_code": false, + "region1_nvs": true, + "region1_wsoc_code": true, + "region1_alternate_code": false + }, + "region_2": { + "mem_region_2_start_phy_address": 5627904, + "mem_region_2_end_phy_address": 8388607, + "region2_boot": false, + "region2_main_code": false, + "region2_nvs": false, + "region2_wsoc_code": false, + "region2_alternate_code": true + }, + "region_3": { + "mem_region_3_start_phy_address": 0, + "mem_region_3_end_phy_address": 0, + "region3_boot": false, + "region3_main_code": false, + "region3_nvs": false, + "region3_wsoc_code": false, + "region3_alternate_code": false + }, + "boot_region_conf": { + "boot_region_size": 0, + "boot_region_flash_disco_param_start_address": 0, + "boot_region_primary_ti_bl_start_phy_address": 12284, + "boot_region_primary_ti_bl_magic": 0, + "boot_region_primary_ti_bl_major": 0, + "boot_region_primary_ti_bl_minor": 0, + "boot_region_sec_ti_bl_start_phy_address": 430076, + "boot_region_sec_ti_bl_magic": 0, + "boot_region_sec_ti_bl_major": 0, + "boot_region_sec_ti_bl_minor": 0 + }, + "main_code_region_conf": { + "main_code_region_vendor_image_start_phy_address": 2871292, + "main_code_region_vendor_image_magic": 0, + "main_code_region_vendor_image_major": 0, + "main_code_region_vendor_image_minor": 0, + "main_code_region_sbl_start_phy_address": 0, + "main_code_region_sbl_magic": 0, + "main_code_region_sbl_major": 0, + "main_code_region_sbl_minor": 0 + }, + "alt_code_region_conf": { + "alt_code_region_vendor_image_start_phy_address": 5631996, + "alt_code_region_vendor_image_magic": 0, + "alt_code_region_vendor_image_major": 0, + "alt_code_region_vendor_image_minor": 0, + "alt_code_region_sbl_start_phy_address": 0, + "alt_code_region_sbl_magic": 0, + "alt_code_region_sbl_major": 0, + "alt_code_region_sbl_minor": 0 + }, + "nvs_code_region_conf": { + "nvs_start_phy_address": 1777664, + "nvs_region_size": 1089536, + "nvs_region_primary_wsoc_start_phy_address": 847868, + "nvs_region_primary_wsoc_magic": 0, + "nvs_region_primary_wsoc_major": 0, + "nvs_region_primary_wsoc_minor": 0, + "nvs_region_sec_wsoc_start_phy_address": 1314812, + "nvs_region_sec_wsoc_magic": 0, + "nvs_region_sec_wsoc_major": 0, + "nvs_region_sec_wsoc_minor": 0, + "nvs_region_primary_wsoc_bl2_start_phy_address": 0, + "nvs_region_primary_wsoc_bl2_magic": 0, + "nvs_region_primary_wsoc_bl2_major": 0, + "nvs_region_primary_wsoc_bl2_minor": 0, + "nvs_region_sec_wsoc_bl2_start_phy_address": 0, + "nvs_region_sec_wsoc_bl2_magic": 0, + "nvs_region_sec_wsoc_bl2_major": 0, + "nvs_region_sec_wsoc_bl2_minor": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/w25q64pw/flash_disc_param_otfde.json b/boards/ti/lp_em_cc35x1/config/flash/w25q64pw/flash_disc_param_otfde.json new file mode 100644 index 000000000000..b0110e0b1ae7 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/w25q64pw/flash_disc_param_otfde.json @@ -0,0 +1,286 @@ +{ + "otfde_header": { + "name": "OTFDEWFF3", + "flash_only": true, + "ip_protection": false, + "regions_lock": false, + "regions_number": 4, + "flash_enabled": true + }, + "bl_conf": { + "host_boot_done_lock": true, + "host_peripherals_lock": true, + "icache_conf_lock": true, + "m33_mem_part_lock": true, + "memss_firewall_lock": true, + "dma_channel_owner_lock": true, + "otfde_region_lock": true, + "core_events_lock": true + }, + "otfde_general": { + "parameters": { + "mem_otfde_initial_delay": 10, + "otfde_global_watchdog_timer": 5 + }, + "events": { + "reset_evt_mask": false, + "reset_evt_suspend": false, + "sft_reset_evt_mask": false, + "sft_reset_evt_suspend": false, + "bypass_mode_evt_mask": false, + "bypass_mode_evt_suspend": false, + "debug_mode_evt_mask": false, + "debug_mode_evt_suspend": false, + "general_evt_mask": false, + "general_evt_suspend": false, + "xspi_data_path_evt_mask": false, + "xspi_data_path_evt_suspend": false, + "xspi_cnfg_path_evt_mask": false, + "xspi_cnfg_path_evt_suspend": false, + "xspi_service_interrupt_evt_mask": false, + "xspi_service_interrupt_evt_suspend": false, + "trans_device_disabled_evt_mask": false, + "trans_device_disabled_evt_suspend": false, + "trans_region_disabled_evt_mask": false, + "trans_region_disabled_evt_suspend": false, + "trans_region_params_conf_evt_mask": false, + "trans_region_params_conf_evt_suspend": false, + "trans_multiple_regions_mapped_evt_mask": false, + "trans_multiple_regions_mapped_evt_suspend": false, + "trans_address_not_32_bit_evt_mask": false, + "trans_address_not_32_bit_evt_suspend": false, + "trans_size_not_32_bit_evt_mask": false, + "trans_size_not_32_bit_evt_suspend": false, + "trans_burst_not_32_bit_evt_mask": false, + "trans_burst_not_32_bit_evt_suspend": false, + "region_read_write_def_evt_mask": false, + "region_read_write_def_evt_suspend": false, + "suspend_while_disabled_evt_mask": false, + "suspend_while_disabled_evt_suspend": false + } + }, + "regions_settings": { + "region_parameters_lock": { + "REGION_0_PARAMS_0": true, + "REGION_0_PARAMS_1": true, + "REGION_0_PARAMS_2": true, + "REGION_1_PARAMS_0": false, + "REGION_1_PARAMS_1": false, + "REGION_1_PARAMS_2": false, + "REGION_2_PARAMS_0": true, + "REGION_2_PARAMS_1": true, + "REGION_2_PARAMS_2": true, + "REGION_3_PARAMS_0": false, + "REGION_3_PARAMS_1": false, + "REGION_3_PARAMS_2": false + }, + "region_0_protection": { + "mem_region_0_enabled": true, + "mem_region_0_device_id": 0, + "mem_region_0_spi_write_enable": true, + "mem_region_0_spi_read_enable": true, + "mem_region_0_physical_offset": 700, + "mem_region_0_security_id_msb": 0, + "mem_region_0_start_address": 81920, + "mem_region_0_end_address": 82593, + "mem_region_0_security_id_lsb": 0, + "mem_otfde_region_0_write_lock_en": false, + "mem_otfde_region_0_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_1_protection": { + "mem_region_1_enabled": true, + "mem_region_1_device_id": 0, + "mem_region_1_spi_write_enable": true, + "mem_region_1_spi_read_enable": true, + "mem_region_1_physical_offset": 0, + "mem_region_1_security_id_msb": 0, + "mem_region_1_start_address": 655360, + "mem_region_1_end_address": 656059, + "mem_region_1_security_id_lsb": 0, + "mem_otfde_region_1_write_lock_en": false, + "mem_otfde_region_1_enc_dec_bypass": "Bypass" + }, + "region_2_protection": { + "mem_region_2_enabled": true, + "mem_region_2_device_id": 0, + "mem_region_2_spi_write_enable": true, + "mem_region_2_spi_read_enable": true, + "mem_region_2_physical_offset": 1374, + "mem_region_2_security_id_msb": 0, + "mem_region_2_start_address": 671744, + "mem_region_2_end_address": 672417, + "mem_region_2_security_id_lsb": 0, + "mem_otfde_region_2_write_lock_en": false, + "mem_otfde_region_2_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_3_protection": { + "mem_region_3_enabled": false, + "mem_region_3_device_id": 1, + "mem_region_3_spi_write_enable": true, + "mem_region_3_spi_read_enable": true, + "mem_region_3_physical_offset": 0, + "mem_region_3_security_id_msb": 0, + "mem_region_3_start_address": 1, + "mem_region_3_end_address": 0, + "mem_region_3_security_id_lsb": 0, + "mem_otfde_region_3_write_lock_en": false, + "mem_otfde_region_3_enc_dec_bypass": "Bypass" + } + }, + "devices": { + "header": { + "flash_device_switch_conf": 1, + "ram_device_switch_conf": 1 + }, + "flash_switch": { + "flash_grant_sel": 0, + "flash_data_for_conf_0": 2181562505, + "flash_offset_bits_for_conf_0": 0, + "flash_stop_bit_for_conf_0": 0, + "flash_data_for_conf_1": 100803083, + "flash_offset_bits_for_conf_1": 1, + "flash_stop_bit_for_conf_1": 0, + "flash_data_for_conf_2": 139266, + "flash_offset_bits_for_conf_2": 2, + "flash_stop_bit_for_conf_2": 0, + "flash_data_for_conf_3": 1, + "flash_offset_bits_for_conf_3": 4, + "flash_stop_bit_for_conf_3": 0, + "flash_data_for_conf_4": 1076887634, + "flash_offset_bits_for_conf_4": 45, + "flash_stop_bit_for_conf_4": 0, + "flash_data_for_conf_5": 3224371282, + "flash_offset_bits_for_conf_5": 45, + "flash_stop_bit_for_conf_5": 0, + "flash_data_for_conf_6": 262149, + "flash_offset_bits_for_conf_6": 14, + "flash_stop_bit_for_conf_6": 0, + "flash_data_for_conf_7": 0, + "flash_offset_bits_for_conf_7": 44, + "flash_stop_bit_for_conf_7": 1, + "flash_data_for_conf_8": 0, + "flash_offset_bits_for_conf_8": 0, + "flash_stop_bit_for_conf_8": 1, + "flash_data_for_conf_9": 0, + "flash_offset_bits_for_conf_9": 0, + "flash_stop_bit_for_conf_9": 1, + "flash_data_for_conf_10": 0, + "flash_offset_bits_for_conf_10": 0, + "flash_stop_bit_for_conf_10": 1, + "flash_data_for_conf_11": 0, + "flash_offset_bits_for_conf_11": 0, + "flash_stop_bit_for_conf_11": 1, + "flash_data_for_conf_12": 0, + "flash_offset_bits_for_conf_12": 0, + "flash_stop_bit_for_conf_12": 1, + "flash_data_for_conf_13": 0, + "flash_offset_bits_for_conf_13": 0, + "flash_stop_bit_for_conf_13": 1, + "flash_data_for_conf_14": 0, + "flash_offset_bits_for_conf_14": 0, + "flash_stop_bit_for_conf_14": 1, + "flash_data_for_conf_15": 0, + "flash_offset_bits_for_conf_15": 0, + "flash_stop_bit_for_conf_15": 1, + "flash_data_for_conf_16": 0, + "flash_offset_bits_for_conf_16": 0, + "flash_stop_bit_for_conf_16": 1, + "flash_data_for_conf_17": 0, + "flash_offset_bits_for_conf_17": 0, + "flash_stop_bit_for_conf_17": 1, + "flash_data_for_conf_18": 0, + "flash_offset_bits_for_conf_18": 0, + "flash_stop_bit_for_conf_18": 1, + "flash_data_for_conf_19": 0, + "flash_offset_bits_for_conf_19": 0, + "flash_stop_bit_for_conf_19": 1, + "flash_data_for_conf_20": 0, + "flash_offset_bits_for_conf_20": 0, + "flash_stop_bit_for_conf_20": 1, + "flash_data_for_conf_21": 0, + "flash_offset_bits_for_conf_21": 0, + "flash_stop_bit_for_conf_21": 1, + "flash_data_for_conf_22": 0, + "flash_offset_bits_for_conf_22": 0, + "flash_stop_bit_for_conf_22": 1, + "flash_data_for_conf_23": 0, + "flash_offset_bits_for_conf_23": 0, + "flash_stop_bit_for_conf_23": 1 + }, + "ram_switch": { + "ram_grant_sel": 0, + "ram_data_for_conf_0": 2181563529, + "ram_offset_bits_for_conf_0": 0, + "ram_stop_bit_for_conf_0": 0, + "ram_data_for_conf_1": 100803307, + "ram_offset_bits_for_conf_1": 1, + "ram_stop_bit_for_conf_1": 0, + "ram_data_for_conf_2": 139320, + "ram_offset_bits_for_conf_2": 2, + "ram_stop_bit_for_conf_2": 0, + "ram_data_for_conf_3": 3089693184, + "ram_offset_bits_for_conf_3": 56, + "ram_stop_bit_for_conf_3": 0, + "ram_data_for_conf_4": 1, + "ram_offset_bits_for_conf_4": 4, + "ram_stop_bit_for_conf_4": 0, + "ram_data_for_conf_5": 1076494399, + "ram_offset_bits_for_conf_5": 45, + "ram_stop_bit_for_conf_5": 0, + "ram_data_for_conf_6": 3223978047, + "ram_offset_bits_for_conf_6": 45, + "ram_stop_bit_for_conf_6": 0, + "ram_data_for_conf_7": 278533, + "ram_offset_bits_for_conf_7": 14, + "ram_stop_bit_for_conf_7": 0, + "ram_data_for_conf_8": 0, + "ram_offset_bits_for_conf_8": 44, + "ram_stop_bit_for_conf_8": 1, + "ram_data_for_conf_9": 0, + "ram_offset_bits_for_conf_9": 0, + "ram_stop_bit_for_conf_9": 1, + "ram_data_for_conf_10": 0, + "ram_offset_bits_for_conf_10": 0, + "ram_stop_bit_for_conf_10": 1, + "ram_data_for_conf_11": 0, + "ram_offset_bits_for_conf_11": 0, + "ram_stop_bit_for_conf_11": 1, + "ram_data_for_conf_12": 0, + "ram_offset_bits_for_conf_12": 0, + "ram_stop_bit_for_conf_12": 1, + "ram_data_for_conf_13": 0, + "ram_offset_bits_for_conf_13": 0, + "ram_stop_bit_for_conf_13": 1, + "ram_data_for_conf_14": 0, + "ram_offset_bits_for_conf_14": 0, + "ram_stop_bit_for_conf_14": 1, + "ram_data_for_conf_15": 0, + "ram_offset_bits_for_conf_15": 0, + "ram_stop_bit_for_conf_15": 1, + "ram_data_for_conf_16": 0, + "ram_offset_bits_for_conf_16": 0, + "ram_stop_bit_for_conf_16": 1, + "ram_data_for_conf_17": 0, + "ram_offset_bits_for_conf_17": 0, + "ram_stop_bit_for_conf_17": 1, + "ram_data_for_conf_18": 0, + "ram_offset_bits_for_conf_18": 0, + "ram_stop_bit_for_conf_18": 1, + "ram_data_for_conf_19": 0, + "ram_offset_bits_for_conf_19": 0, + "ram_stop_bit_for_conf_19": 1, + "ram_data_for_conf_20": 0, + "ram_offset_bits_for_conf_20": 0, + "ram_stop_bit_for_conf_20": 1, + "ram_data_for_conf_21": 0, + "ram_offset_bits_for_conf_21": 0, + "ram_stop_bit_for_conf_21": 1, + "ram_data_for_conf_22": 0, + "ram_offset_bits_for_conf_22": 0, + "ram_stop_bit_for_conf_22": 1, + "ram_data_for_conf_23": 0, + "ram_offset_bits_for_conf_23": 0, + "ram_stop_bit_for_conf_23": 1 + } + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/w25q64pw/flash_disc_param_xspi.json b/boards/ti/lp_em_cc35x1/config/flash/w25q64pw/flash_disc_param_xspi.json new file mode 100644 index 000000000000..53c8328e751c --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/w25q64pw/flash_disc_param_xspi.json @@ -0,0 +1,485 @@ +{ + "xspi_header": { + "name": "xSPIWFF3", + "device": "CC3500", + "use_hardware": "W25Q64PW", + "use_case": "Quadro", + "dqs_support": 0, + "flash_only": 1, + "flash_separate_reset": 0, + "ram_separate_reset": true, + "clock_frequency": 80, + "qospi_clock_divider": 1, + "flash_device_character_conf": 0, + "ram_device_character_conf": 0, + "header_advanced": 0, + "phy_mode_enable": 1, + "pipeline_mode_enable": 1, + "loopback_support": "No", + "qspi_ref_clock": 80, + "spi_clock_freq": 20, + "spi_clock_divider": 1, + "flash_device_size": 8, + "flash_bytes_per_block": 16, + "flash_bytes_per_page": 256, + "flash_number_of_address_bytes": 3, + "flash_dual_opcode": 0, + "flash_jedec_manufacturer_id": 0, + "flash_jedec_device_id": 32791, + "flash_name": "W25Q64PW", + "flash_page_size": 256, + "flash_sector_size": 4096, + "flash_cs_polarity": "ACTIVE_LOW", + "flash_sw_reset_type": "x1xxxx", + "ram_device_size": 8, + "ram_bytes_per_block": 16, + "ram_bytes_per_page": 256, + "ram_number_of_address_bytes": 3, + "ram_dual_opcode": 0, + "ram_jedec_manufacturer_id": 0, + "ram_jedec_device_id": 32791, + "ram_name": "NO_PSRAM", + "ram_page_size": 256, + "ram_sector_size": 4096, + "ram_cs_polarity": "ACTIVE_LOW", + "ram_sw_reset_type": "x1xxxx", + "flash_write_operation_modes": "4S-4S-4S", + "flash_read_operation_modes": "4S-4S-4S", + "ram_write_operation_modes": "4S-4S-4S", + "ram_read_operation_modes": "4S-4S-4S", + "crc_enable": 0, + "enable_dtr": 0, + "enable_ahb_decoder": 0, + "enter_xip_mod_immediately": 0, + "enter_xip_mod_next_read": 0, + "ahb_address_remapping": 0, + "enable_dma": 0, + "select_decode": 0, + "legacy_ip_mode": 0, + "direct_access": 1 + }, + "xspi_pinmux": { + "xspi_clk_input": 44, + "xspi_clk_input_use_hw": 0, + "xspi_clk_input_mode": "Input", + "xspi_clk_input_pull": "None", + "xspi_clk_input_interrupt_trigger": "Low", + "xspi_clk_input_dont_conf": 0, + "xspi_clk_input_output_strength": "High", + "xspi_clk_input_initial_output_state": "High", + "xspi_clk": 24, + "xspi_clk_use_hw": "None", + "xspi_clk_mode": "Output", + "xspi_clk_pull": "None", + "xspi_clk_output_strength": "High", + "xspi_clk_initial_output_state": "High", + "xspi_clk_interrupt_trigger": "None", + "xspi_clk_dont_conf": 0, + "xspi_flash_cs": 20, + "xspi_flash_cs_use_hw": "None", + "xspi_flash_cs_mode": "Output", + "xspi_flash_cs_pull": "None", + "xspi_flash_cs_output_strength": "High", + "xspi_flash_cs_initial_output_state": "High", + "xspi_flash_cs_interrupt_trigger": "None", + "xspi_flash_cs_dont_conf": 0, + "xspi_data_0": 25, + "xspi_data_0_use_hw": "None", + "xspi_data_0_mode": "Input", + "xspi_data_0_pull": "None", + "xspi_data_0_output_strength": "High", + "xspi_data_0_initial_output_state": "High", + "xspi_data_0_interrupt_trigger": "Low", + "xspi_data_0_dont_conf": 0, + "xspi_data_1": 21, + "xspi_data_1_use_hw": "None", + "xspi_data_1_mode": "Input", + "xspi_data_1_pull": "None", + "xspi_data_1_output_strength": "High", + "xspi_data_1_initial_output_state": "High", + "xspi_data_1_interrupt_trigger": "Low", + "xspi_data_1_dont_conf": 0, + "xspi_data_2": 22, + "xspi_data_2_use_hw": "None", + "xspi_data_2_mode": "Input", + "xspi_data_2_pull": "None", + "xspi_data_2_output_strength": "High", + "xspi_data_2_initial_output_state": "High", + "xspi_data_2_interrupt_trigger": "Low", + "xspi_data_2_dont_conf": 0, + "xspi_data_3": 23, + "xspi_data_3_use_hw": "None", + "xspi_data_3_mode": "Input", + "xspi_data_3_pull": "None", + "xspi_data_3_output_strength": "High", + "xspi_data_3_initial_output_state": "High", + "xspi_data_3_interrupt_trigger": "Low", + "xspi_data_3_dont_conf": 0, + "xspi_data_4": 26, + "xspi_data_4_use_hw": "None", + "xspi_data_4_mode": "Input", + "xspi_data_4_pull": "None", + "xspi_data_4_output_strength": "High", + "xspi_data_4_initial_output_state": "High", + "xspi_data_4_interrupt_trigger": "None", + "xspi_data_4_dont_conf": 0, + "xspi_data_5": 27, + "xspi_data_5_use_hw": "None", + "xspi_data_5_mode": "Input", + "xspi_data_5_pull": "None", + "xspi_data_5_output_strength": "High", + "xspi_data_5_initial_output_state": "High", + "xspi_data_5_interrupt_trigger": "None", + "xspi_data_5_dont_conf": 0, + "xspi_data_6": 28, + "xspi_data_6_use_hw": "None", + "xspi_data_6_mode": "Input", + "xspi_data_6_pull": "None", + "xspi_data_6_output_strength": "High", + "xspi_data_6_initial_output_state": "High", + "xspi_data_6_interrupt_trigger": "None", + "xspi_data_6_dont_conf": 0, + "xspi_data_7": 29, + "xspi_data_7_use_hw": "None", + "xspi_data_7_mode": "Input", + "xspi_data_7_pull": "None", + "xspi_data_7_output_strength": "High", + "xspi_data_7_initial_output_state": "High", + "xspi_data_7_interrupt_trigger": "None", + "xspi_data_7_dont_conf": 0, + "xspi_reset_flash": 36, + "xspi_reset_flash_use_hw": "None", + "xspi_reset_flash_mode": "Output", + "xspi_reset_flash_pull": "None", + "xspi_reset_flash_output_strength": "High", + "xspi_reset_flash_initial_output_state": "High", + "xspi_reset_flash_interrupt_trigger": "None", + "xspi_reset_flash_dont_conf": 0, + "xspi_cs_ram": 3, + "xspi_cs_ram_use_hw": "None", + "xspi_cs_ram_mode": "Output", + "xspi_cs_ram_pull": "None", + "xspi_cs_ram_output_strength": "High", + "xspi_cs_ram_initial_output_state": "High", + "xspi_cs_ram_interrupt_trigger": "None", + "xspi_cs_ram_dont_conf": 0, + "xspi_dqs": 30, + "xspi_dqs_use_hw": "None", + "xspi_dqs_mode": "Input", + "xspi_dqs_pull": "None", + "xspi_dqs_output_strength": "High", + "xspi_dqs_initial_output_state": "High", + "xspi_dqs_interrupt_trigger": "None", + "xspi_dqs_dont_conf": 0, + "xspi_reset_ram": 2, + "xspi_reset_ram_use_hw": "None", + "xspi_reset_ram_mode": "Input", + "xspi_reset_ram_pull": "None", + "xspi_reset_ram_output_strength": "High", + "xspi_reset_ram_initial_output_state": "High", + "xspi_reset_ram_interrupt_trigger": "None", + "xspi_reset_ram_dont_conf": 0 + }, + "xspi_operations": { + "xspi_operations_clocks": { + "clock_phase": 0, + "clock_polarity": 0, + "spi_mode": "2'b00" + }, + "xspi_operations_chip_select": { + "csda": 2, + "csdads": 0, + "cseot": 4, + "cssot": 1 + }, + "xspi_operations_reset": { + "flash_jedec_reset": 0, + "ram_jedec_reset": 0, + "flash_treset": 20, + "ram_treset": 20 + }, + "xspi_phy_operations": { + "flash_rx_dll_bypass_bit": 0, + "flash_dll_tx_delay": 61, + "flash_dll_rx_delay": 65, + "ram_rx_dll_bypass_bit": 0, + "ram_dll_tx_delay": 61, + "ram_dll_rx_delay": 65 + }, + "xspi_read_operations": { + "flash_dummy_rd_cycles": 6, + "flash_read_opcode": 11, + "suppl_flash_read_opcode": 0, + "ram_dummy_rd_cycles": 8, + "ram_read_opcode": 11, + "suppl_ram_read_opcode": 0, + "flash_non_cont_read_enable": 0, + "flash_max_read_jobs": 256, + "ram_non_cont_read_enable": 0, + "ram_max_read_jobs": 256, + "rww_en": 0, + "device_size": 8, + "number_of_banks": 1, + "bank_size": 8, + "mode_bit_enable": 0 + }, + "xspi_write_operations": { + "flash_address_and_data": { + "flash_dummy_wr_cycles": 0 + }, + "flash_command": { + "flash_write_opcode": 2, + "suppl_flash_write_opcode": 0 + }, + "ram_address_and_data": { + "ram_dummy_wr_cycles": 0 + }, + "ram_command": { + "ram_write_opcode": 2, + "suppl_ram_write_opcode": 0 + }, + "write_to_buffer": { + "flash_write_to_buffer_support": 0, + "ram_write_to_buffer_support": 0 + }, + "non_continuous_write": { + "flash_non_cont_write_enable": 0, + "flash_max_write_jobs": 64, + "ram_non_cont_write_enable": 0, + "ram_max_write_jobs": 0 + }, + "flash_program_operation": { + "flash_min_program_size": "256 B", + "flash_program_opcode": 2, + "suppl_flash_program_opcode": 0, + "flash_maximum_program_time_limit": 1600 + }, + "flash_erase_operation": { + "flash_min_erase_size": "4 kB", + "flash_erase_opcode": 32, + "suppl_flash_erase_opcode": 0, + "flash_maximum_erase_time_limit": 4095 + }, + "flash_erase_conf": { + "flash_block_erase_opcode": 0, + "suppl_block_flash_erase_opcode": 0, + "flash_sector_erase_opcode": 0, + "suppl_sector_flash_erase_opcode": 0, + "flash_chip_erase_opcode": 0, + "suppl_chip_flash_erase_opcode": 0 + }, + "ram_program_operation": { + "ram_min_program_size": "256 B", + "ram_program_opcode": 2, + "suppl_ram_program_opcode": 0, + "ram_maximum_program_time_limit": 1600 + }, + "ram_erase_conf": { + "ram_block_erase_opcode": 0, + "suppl_block_ram_erase_opcode": 0, + "ram_sector_erase_opcode": 0, + "suppl_sector_ram_erase_opcode": 0, + "ram_chip_erase_opcode": 0, + "suppl_chip_ram_erase_opcode": 0 + }, + "flash_buffer_support": { + "flash_pre_write_sequence": 0, + "flash_post_write_sequence": 0, + "flash_write_protection_timer_en": 0, + "flash_write_buffer_timer_mode": 16, + "flash_write_buffer_timer_range": 0, + "flash_service_interrupt_criteria": 0 + }, + "ram_buffer_support": { + "ram_pre_write_sequence": 0, + "ram_post_write_sequence": 0, + "ram_write_protection_timer_en": 0, + "ram_write_buffer_timer_mode": 16, + "ram_write_buffer_timer_range": 0, + "ram_service_interrupt_criteria": 0 + }, + "flash_pre_write_conf": { + "flash_pre_write_job_done_grant_sel": 0, + "data_for_flash_pre_write_conf_0": 0, + "offset_bits_for_flash_pre_write_conf_0": 0, + "stop_bit_for_flash_pre_write_conf_0": 1, + "data_for_flash_pre_write_conf_1": 0, + "offset_bits_for_flash_pre_write_conf_1": 0 + }, + "flash_post_write_conf": { + "flash_post_write_job_done_grant_sel": 0, + "data_for_flash_post_write_conf_0": 0, + "offset_bits_for_flash_post_write_conf_0": 0, + "stop_bit_for_flash_post_write_conf_0": 1, + "data_for_flash_post_write_conf_1": 0, + "offset_bits_for_flash_post_write_conf_1": 0 + }, + "ram_pre_write_conf": { + "ram_pre_write_job_done_grant_sel": 0, + "data_for_ram_pre_write_conf_0": 0, + "offset_bits_for_ram_pre_write_conf_0": 0, + "stop_bit_for_ram_pre_write_conf_0": 1, + "data_for_ram_pre_write_conf_1": 0, + "offset_bits_for_ram_pre_write_conf_1": 0 + }, + "ram_post_write_conf": { + "ram_post_write_job_done_grant_sel": 0, + "data_for_ram_post_write_conf_0": 0, + "offset_bits_for_ram_post_write_conf_0": 0, + "stop_bit_for_ram_post_write_conf_0": 1, + "data_for_ram_post_write_conf_1": 0, + "offset_bits_for_ram_post_write_conf_1": 0 + } + }, + "xspi_capture_operations": { + "read_data_capture": { + "flash_delay_transmitted_data": 0, + "flash_loopback_clock": 0, + "flash_bypass_adapted_loopback": 1, + "flash_sample_edge_sel": 0, + "ram_delay_transmitted_data": 0, + "ram_loopback_clock": 0, + "ram_bypass_adapted_loopback": 1, + "ram_sample_edge_sel": 0 + }, + "delays": { + "flash_full_half_cycle_delay": 0, + "flash_dll_bypass_mode": 1, + "flash_phase_detect_sel": 0, + "flash_dll_lock_num": 0, + "flash_dll_start_point": 0, + "flash_loopback_clock": 0, + "ram_full_half_cycle_delay": 0, + "ram_dll_bypass_mode": 1, + "ram_phase_detect_sel": 0, + "ram_dll_lock_num": 0, + "ram_dll_start_point": 0, + "ram_loopback_clock": 0 + }, + "operation_modes": { + "flash_sfdp_support": 0, + "ram_sfdp_support": 0, + "flash_pm_support": 0, + "ram_pm_support": 0, + "flash_sfdp_opcode": 0, + "suppl_flash_sfdp_opcode": 0, + "ram_sfdp_opcode": 0, + "suppl_ram_sfdp_opcode": 0, + "flash_enter_dpd_opcode": 185, + "suppl_flash_enter_dpd_opcode": 0, + "flash_exit_dpd_opcode": 171, + "suppl_flash_exit_dpd_opcode": 0, + "ram_enter_dpd_opcode": 185, + "suppl_ram_enter_dpd_opcode": 0, + "ram_exit_dpd_opcode": 171, + "suppl_ram_exit_dpd_opcode": 0, + "flash_quad_enable_opcode": 56, + "suppl_flash_quad_enable_opcode": 0, + "flash_quad_disable_opcode": 255, + "suppl_flash_quad_disable_opcode": 0, + "flash_octal_enable_opcode": 0, + "suppl_flash_octal_enable_opcode": 0, + "flash_octal_disable_opcode": 0, + "suppl_flash_octal_disable_opcode": 0, + "ram_quad_enable_opcode": 56, + "suppl_ram_quad_enable_opcode": 0, + "ram_quad_disable_opcode": 255, + "suppl_ram_quad_disable_opcode": 0, + "ram_octal_enable_opcode": 0, + "suppl_ram_octal_enable_opcode": 0, + "ram_octal_disable_opcode": 0, + "suppl_ram_octal_disable_opcode": 0 + } + } + }, + "external_memory_reporting": { + "header": { + "flash_auto_polling_enable": 1, + "flash_wel_enable": 1, + "flash_write_protect_enable": 0, + "flash_alternate_polling_conf_enable": 0, + "ram_auto_polling_enable": 1, + "ram_wel_enable": 1, + "ram_write_protect_enable": 0, + "ram_alternate_polling_conf_enable": 0 + }, + "flash_auto_polling": { + "flash_polling_repetition_delay": 0, + "flash_polling_count": 4, + "flash_enable_polling_expiration": 0, + "flash_polling_polarity": 0, + "flash_polling_address_phase_enable": 0, + "flash_polling_bit_index": 0, + "flash_numbers_poll_cycles": 65535, + "flash_dummy_autopoll_cycles": 0 + }, + "ram_auto_polling": { + "ram_polling_repetition_delay": 0, + "ram_polling_count": 4, + "ram_enable_polling_expiration": 0, + "ram_polling_polarity": 0, + "ram_polling_address_phase_enable": 0, + "ram_polling_bit_index": 0, + "ram_numbers_poll_cycles": 65535, + "ram_dummy_autopoll_cycles": 0 + }, + "flash_polling_command": { + "flash_polling_opcode": 5, + "suppl_flash_polling_opcode": 0 + }, + "ram_polling_command": { + "ram_polling_opcode": 5, + "suppl_ram_polling_opcode": 0 + }, + "flash_alternate_polling": { + "flash_polling_resp_count": 1023, + "flash_polling_iterations": 1, + "flash_polling_enabled": 0, + "flash_polling_disabled": 0, + "flash_grant_sel": 0, + "flash_data_for_enable_poling_conf_0": 0, + "flash_offset_bits_for_enable_poling_conf_0": 0, + "flash_stop_bit_for_enable_poling_conf_0": 1, + "flash_data_for_enable_poling_conf_1": 0, + "flash_offset_bits_for_enable_poling_conf_1": 0, + "flash_stop_bit_for_enable_poling_conf_1": 1, + "flash_data_for_disable_poling_conf_0": 0, + "flash_offset_bits_for_disable_poling_conf_0": 0, + "flash_stop_bit_for_disable_poling_conf_0": 1, + "flash_data_for_disable_poling_conf_1": 0, + "flash_offset_bits_for_disable_poling_conf_1": 0, + "flash_stop_bit_for_disable_poling_conf_1": 1 + }, + "ram_alternate_polling": { + "ram_polling_resp_count": 1023, + "ram_polling_iterations": 1, + "ram_polling_enabled": 0, + "ram_polling_disabled": 0, + "ram_grant_sel": 0, + "ram_data_for_enable_poling_conf_0": 0, + "ram_offset_bits_for_enable_poling_conf_0": 0, + "ram_stop_bit_for_enable_poling_conf_0": 1, + "ram_data_for_enable_poling_conf_1": 0, + "ram_offset_bits_for_enable_poling_conf_1": 0, + "ram_stop_bit_for_enable_poling_conf_1": 1, + "ram_data_for_disable_poling_conf_0": 0, + "ram_offset_bits_for_disable_poling_conf_0": 0, + "ram_stop_bit_for_disable_poling_conf_0": 1, + "ram_data_for_disable_poling_conf_1": 0, + "ram_offset_bits_for_disable_poling_conf_1": 0, + "ram_stop_bit_for_disable_poling_conf_1": 1 + }, + "flash_wel_command": { + "flash_wel_opcode": 6, + "suppl_flash_wel_opcode": 0 + }, + "ram_wel_command": { + "ram_wel_opcode": 6, + "suppl_ram_wel_opcode": 0 + } + }, + "event": { + "host_nvic_irq": 0, + "core_10_mux_sel": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash_disc_param_ext_mem.json b/boards/ti/lp_em_cc35x1/config/flash_disc_param_ext_mem.json new file mode 100644 index 000000000000..321810768be1 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash_disc_param_ext_mem.json @@ -0,0 +1,99 @@ +{ + "vendor_primary_sbl": true, + "ti_wsoc_primary_container": true, + "ti_wsoc_bl2_primary_container": true, + "nvs_enable": true, + "vendor_alternate_image": true, + "vendor_sbl_alternate_image": true, + "ti_bl_alternate_image": true, + "ti_wsoc_alternate_image": true, + "ti_wsoc_bl2_alternate_image": true, + "region_0": { + "mem_region_0_start_phy_address": 1069056, + "mem_region_0_end_phy_address": 4194303, + "region0_boot": false, + "region0_main_code": true, + "region0_nvs": false, + "region0_wsoc_code": false, + "region0_alternate_code": false + }, + "region_1": { + "mem_region_1_start_phy_address": 0, + "mem_region_1_end_phy_address": 1069055, + "region1_boot": true, + "region1_main_code": false, + "region1_nvs": true, + "region1_wsoc_code": true, + "region1_alternate_code": false + }, + "region_2": { + "mem_region_2_start_phy_address": 0, + "mem_region_2_end_phy_address": 0, + "region2_boot": false, + "region2_main_code": false, + "region2_nvs": false, + "region2_wsoc_code": false, + "region2_alternate_code": true + }, + "region_3": { + "mem_region_3_start_phy_address": 0, + "mem_region_3_end_phy_address": 0, + "region3_boot": false, + "region3_main_code": false, + "region3_nvs": false, + "region3_wsoc_code": false, + "region3_alternate_code": false + }, + "boot_region_conf": { + "boot_region_size": 0, + "boot_region_flash_disco_param_start_address": 0, + "boot_region_primary_ti_bl_start_phy_address": 12284, + "boot_region_primary_ti_bl_magic": 0, + "boot_region_primary_ti_bl_major": 0, + "boot_region_primary_ti_bl_minor": 0, + "boot_region_sec_ti_bl_start_phy_address": 430076, + "boot_region_sec_ti_bl_magic": 0, + "boot_region_sec_ti_bl_major": 0, + "boot_region_sec_ti_bl_minor": 0 + }, + "main_code_region_conf": { + "main_code_region_vendor_image_start_phy_address": 1073148, + "main_code_region_vendor_image_magic": 0, + "main_code_region_vendor_image_major": 0, + "main_code_region_vendor_image_minor": 0, + "main_code_region_sbl_start_phy_address": 0, + "main_code_region_sbl_magic": 0, + "main_code_region_sbl_major": 0, + "main_code_region_sbl_minor": 0 + }, + "alt_code_region_conf": { + "alt_code_region_vendor_image_start_phy_address": 4194304, + "alt_code_region_vendor_image_magic": 0, + "alt_code_region_vendor_image_major": 0, + "alt_code_region_vendor_image_minor": 0, + "alt_code_region_sbl_start_phy_address": 0, + "alt_code_region_sbl_magic": 0, + "alt_code_region_sbl_major": 0, + "alt_code_region_sbl_minor": 0 + }, + "nvs_code_region_conf": { + "nvs_start_phy_address": 892928, + "nvs_region_size": 176128, + "nvs_region_primary_wsoc_start_phy_address": 430076, + "nvs_region_primary_wsoc_magic": 0, + "nvs_region_primary_wsoc_major": 0, + "nvs_region_primary_wsoc_minor": 0, + "nvs_region_sec_wsoc_start_phy_address": 897020, + "nvs_region_sec_wsoc_magic": 0, + "nvs_region_sec_wsoc_major": 0, + "nvs_region_sec_wsoc_minor": 0, + "nvs_region_primary_wsoc_bl2_start_phy_address": 0, + "nvs_region_primary_wsoc_bl2_magic": 0, + "nvs_region_primary_wsoc_bl2_major": 0, + "nvs_region_primary_wsoc_bl2_minor": 0, + "nvs_region_sec_wsoc_bl2_start_phy_address": 0, + "nvs_region_sec_wsoc_bl2_magic": 0, + "nvs_region_sec_wsoc_bl2_major": 0, + "nvs_region_sec_wsoc_bl2_minor": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash_disc_param_otfde.json b/boards/ti/lp_em_cc35x1/config/flash_disc_param_otfde.json new file mode 100644 index 000000000000..635e11319c5d --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash_disc_param_otfde.json @@ -0,0 +1,286 @@ +{ + "otfde_header": { + "name": "OTFDEWFF3", + "flash_only": true, + "ip_protection": false, + "regions_lock": false, + "regions_number": 4, + "flash_enabled": true + }, + "bl_conf": { + "host_boot_done_lock": true, + "host_peripherals_lock": true, + "icache_conf_lock": true, + "m33_mem_part_lock": true, + "memss_firewall_lock": true, + "dma_channel_owner_lock": true, + "otfde_region_lock": true, + "core_events_lock": true + }, + "otfde_general": { + "parameters": { + "mem_otfde_initial_delay": 10, + "otfde_global_watchdog_timer": 5 + }, + "events": { + "reset_evt_mask": false, + "reset_evt_suspend": false, + "sft_reset_evt_mask": false, + "sft_reset_evt_suspend": false, + "bypass_mode_evt_mask": false, + "bypass_mode_evt_suspend": false, + "debug_mode_evt_mask": false, + "debug_mode_evt_suspend": false, + "general_evt_mask": false, + "general_evt_suspend": false, + "xspi_data_path_evt_mask": false, + "xspi_data_path_evt_suspend": false, + "xspi_cnfg_path_evt_mask": false, + "xspi_cnfg_path_evt_suspend": false, + "xspi_service_interrupt_evt_mask": false, + "xspi_service_interrupt_evt_suspend": false, + "trans_device_disabled_evt_mask": false, + "trans_device_disabled_evt_suspend": false, + "trans_region_disabled_evt_mask": false, + "trans_region_disabled_evt_suspend": false, + "trans_region_params_conf_evt_mask": false, + "trans_region_params_conf_evt_suspend": false, + "trans_multiple_regions_mapped_evt_mask": false, + "trans_multiple_regions_mapped_evt_suspend": false, + "trans_address_not_32_bit_evt_mask": false, + "trans_address_not_32_bit_evt_suspend": false, + "trans_size_not_32_bit_evt_mask": false, + "trans_size_not_32_bit_evt_suspend": false, + "trans_burst_not_32_bit_evt_mask": false, + "trans_burst_not_32_bit_evt_suspend": false, + "region_read_write_def_evt_mask": false, + "region_read_write_def_evt_suspend": false, + "suspend_while_disabled_evt_mask": false, + "suspend_while_disabled_evt_suspend": false + } + }, + "regions_settings": { + "region_parameters_lock": { + "REGION_0_PARAMS_0": true, + "REGION_0_PARAMS_1": true, + "REGION_0_PARAMS_2": true, + "REGION_1_PARAMS_0": false, + "REGION_1_PARAMS_1": false, + "REGION_1_PARAMS_2": false, + "REGION_2_PARAMS_0": true, + "REGION_2_PARAMS_1": true, + "REGION_2_PARAMS_2": true, + "REGION_3_PARAMS_0": false, + "REGION_3_PARAMS_1": false, + "REGION_3_PARAMS_2": false + }, + "region_0_protection": { + "mem_region_0_enabled": true, + "mem_region_0_device_id": 0, + "mem_region_0_spi_write_enable": true, + "mem_region_0_spi_read_enable": true, + "mem_region_0_physical_offset": 261, + "mem_region_0_security_id_msb": 0, + "mem_region_0_start_address": 81920, + "mem_region_0_end_address": 82682, + "mem_region_0_security_id_lsb": 0, + "mem_otfde_region_0_write_lock_en": false, + "mem_otfde_region_0_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_1_protection": { + "mem_region_1_enabled": true, + "mem_region_1_device_id": 0, + "mem_region_1_spi_write_enable": true, + "mem_region_1_spi_read_enable": true, + "mem_region_1_physical_offset": 0, + "mem_region_1_security_id_msb": 0, + "mem_region_1_start_address": 655360, + "mem_region_1_end_address": 655620, + "mem_region_1_security_id_lsb": 0, + "mem_otfde_region_1_write_lock_en": false, + "mem_otfde_region_1_enc_dec_bypass": "Bypass" + }, + "region_2_protection": { + "mem_region_2_enabled": false, + "mem_region_2_device_id": 0, + "mem_region_2_spi_write_enable": true, + "mem_region_2_spi_read_enable": true, + "mem_region_2_physical_offset": 0, + "mem_region_2_security_id_msb": 0, + "mem_region_2_start_address": 1, + "mem_region_2_end_address": 0, + "mem_region_2_security_id_lsb": 0, + "mem_otfde_region_2_write_lock_en": false, + "mem_otfde_region_2_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_3_protection": { + "mem_region_3_enabled": false, + "mem_region_3_device_id": 1, + "mem_region_3_spi_write_enable": true, + "mem_region_3_spi_read_enable": true, + "mem_region_3_physical_offset": 0, + "mem_region_3_security_id_msb": 0, + "mem_region_3_start_address": 1, + "mem_region_3_end_address": 0, + "mem_region_3_security_id_lsb": 0, + "mem_otfde_region_3_write_lock_en": false, + "mem_otfde_region_3_enc_dec_bypass": "Bypass" + } + }, + "devices": { + "header": { + "flash_device_switch_conf": 1, + "ram_device_switch_conf": 1 + }, + "flash_switch": { + "flash_grant_sel": 0, + "flash_data_for_conf_0": 2181562505, + "flash_offset_bits_for_conf_0": 0, + "flash_stop_bit_for_conf_0": 0, + "flash_data_for_conf_1": 67248651, + "flash_offset_bits_for_conf_1": 1, + "flash_stop_bit_for_conf_1": 0, + "flash_data_for_conf_2": 139266, + "flash_offset_bits_for_conf_2": 2, + "flash_stop_bit_for_conf_2": 0, + "flash_data_for_conf_3": 1, + "flash_offset_bits_for_conf_3": 4, + "flash_stop_bit_for_conf_3": 0, + "flash_data_for_conf_4": 1076887634, + "flash_offset_bits_for_conf_4": 45, + "flash_stop_bit_for_conf_4": 0, + "flash_data_for_conf_5": 3224371282, + "flash_offset_bits_for_conf_5": 45, + "flash_stop_bit_for_conf_5": 0, + "flash_data_for_conf_6": 262149, + "flash_offset_bits_for_conf_6": 14, + "flash_stop_bit_for_conf_6": 0, + "flash_data_for_conf_7": 0, + "flash_offset_bits_for_conf_7": 44, + "flash_stop_bit_for_conf_7": 1, + "flash_data_for_conf_8": 0, + "flash_offset_bits_for_conf_8": 0, + "flash_stop_bit_for_conf_8": 1, + "flash_data_for_conf_9": 0, + "flash_offset_bits_for_conf_9": 0, + "flash_stop_bit_for_conf_9": 1, + "flash_data_for_conf_10": 0, + "flash_offset_bits_for_conf_10": 0, + "flash_stop_bit_for_conf_10": 1, + "flash_data_for_conf_11": 0, + "flash_offset_bits_for_conf_11": 0, + "flash_stop_bit_for_conf_11": 1, + "flash_data_for_conf_12": 0, + "flash_offset_bits_for_conf_12": 0, + "flash_stop_bit_for_conf_12": 1, + "flash_data_for_conf_13": 0, + "flash_offset_bits_for_conf_13": 0, + "flash_stop_bit_for_conf_13": 1, + "flash_data_for_conf_14": 0, + "flash_offset_bits_for_conf_14": 0, + "flash_stop_bit_for_conf_14": 1, + "flash_data_for_conf_15": 0, + "flash_offset_bits_for_conf_15": 0, + "flash_stop_bit_for_conf_15": 1, + "flash_data_for_conf_16": 0, + "flash_offset_bits_for_conf_16": 0, + "flash_stop_bit_for_conf_16": 1, + "flash_data_for_conf_17": 0, + "flash_offset_bits_for_conf_17": 0, + "flash_stop_bit_for_conf_17": 1, + "flash_data_for_conf_18": 0, + "flash_offset_bits_for_conf_18": 0, + "flash_stop_bit_for_conf_18": 1, + "flash_data_for_conf_19": 0, + "flash_offset_bits_for_conf_19": 0, + "flash_stop_bit_for_conf_19": 1, + "flash_data_for_conf_20": 0, + "flash_offset_bits_for_conf_20": 0, + "flash_stop_bit_for_conf_20": 1, + "flash_data_for_conf_21": 0, + "flash_offset_bits_for_conf_21": 0, + "flash_stop_bit_for_conf_21": 1, + "flash_data_for_conf_22": 0, + "flash_offset_bits_for_conf_22": 0, + "flash_stop_bit_for_conf_22": 1, + "flash_data_for_conf_23": 0, + "flash_offset_bits_for_conf_23": 0, + "flash_stop_bit_for_conf_23": 1 + }, + "ram_switch": { + "ram_grant_sel": 0, + "ram_data_for_conf_0": 2181562505, + "ram_offset_bits_for_conf_0": 0, + "ram_stop_bit_for_conf_0": 0, + "ram_data_for_conf_1": 67248651, + "ram_offset_bits_for_conf_1": 1, + "ram_stop_bit_for_conf_1": 0, + "ram_data_for_conf_2": 139266, + "ram_offset_bits_for_conf_2": 2, + "ram_stop_bit_for_conf_2": 0, + "ram_data_for_conf_3": 1, + "ram_offset_bits_for_conf_3": 4, + "ram_stop_bit_for_conf_3": 0, + "ram_data_for_conf_4": 1076887634, + "ram_offset_bits_for_conf_4": 45, + "ram_stop_bit_for_conf_4": 0, + "ram_data_for_conf_5": 3224371282, + "ram_offset_bits_for_conf_5": 45, + "ram_stop_bit_for_conf_5": 0, + "ram_data_for_conf_6": 262149, + "ram_offset_bits_for_conf_6": 14, + "ram_stop_bit_for_conf_6": 0, + "ram_data_for_conf_7": 0, + "ram_offset_bits_for_conf_7": 44, + "ram_stop_bit_for_conf_7": 1, + "ram_data_for_conf_8": 0, + "ram_offset_bits_for_conf_8": 0, + "ram_stop_bit_for_conf_8": 1, + "ram_data_for_conf_9": 0, + "ram_offset_bits_for_conf_9": 0, + "ram_stop_bit_for_conf_9": 1, + "ram_data_for_conf_10": 0, + "ram_offset_bits_for_conf_10": 0, + "ram_stop_bit_for_conf_10": 1, + "ram_data_for_conf_11": 0, + "ram_offset_bits_for_conf_11": 0, + "ram_stop_bit_for_conf_11": 1, + "ram_data_for_conf_12": 0, + "ram_offset_bits_for_conf_12": 0, + "ram_stop_bit_for_conf_12": 1, + "ram_data_for_conf_13": 0, + "ram_offset_bits_for_conf_13": 0, + "ram_stop_bit_for_conf_13": 1, + "ram_data_for_conf_14": 0, + "ram_offset_bits_for_conf_14": 0, + "ram_stop_bit_for_conf_14": 1, + "ram_data_for_conf_15": 0, + "ram_offset_bits_for_conf_15": 0, + "ram_stop_bit_for_conf_15": 1, + "ram_data_for_conf_16": 0, + "ram_offset_bits_for_conf_16": 0, + "ram_stop_bit_for_conf_16": 1, + "ram_data_for_conf_17": 0, + "ram_offset_bits_for_conf_17": 0, + "ram_stop_bit_for_conf_17": 1, + "ram_data_for_conf_18": 0, + "ram_offset_bits_for_conf_18": 0, + "ram_stop_bit_for_conf_18": 1, + "ram_data_for_conf_19": 0, + "ram_offset_bits_for_conf_19": 0, + "ram_stop_bit_for_conf_19": 1, + "ram_data_for_conf_20": 0, + "ram_offset_bits_for_conf_20": 0, + "ram_stop_bit_for_conf_20": 1, + "ram_data_for_conf_21": 0, + "ram_offset_bits_for_conf_21": 0, + "ram_stop_bit_for_conf_21": 1, + "ram_data_for_conf_22": 0, + "ram_offset_bits_for_conf_22": 0, + "ram_stop_bit_for_conf_22": 1, + "ram_data_for_conf_23": 0, + "ram_offset_bits_for_conf_23": 0, + "ram_stop_bit_for_conf_23": 1 + } + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash_disc_param_xspi.json b/boards/ti/lp_em_cc35x1/config/flash_disc_param_xspi.json new file mode 100644 index 000000000000..c96cbac6431a --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash_disc_param_xspi.json @@ -0,0 +1,485 @@ +{ + "xspi_header": { + "name": "xSPIWFF3", + "device": "CC3500", + "use_hardware": "IS25WJ032F", + "use_case": "Quadro", + "dqs_support": 0, + "flash_only": 1, + "flash_separate_reset": 0, + "ram_separate_reset": true, + "clock_frequency": 80, + "qospi_clock_divider": 1, + "flash_device_character_conf": 0, + "ram_device_character_conf": 0, + "header_advanced": 0, + "phy_mode_enable": 1, + "pipeline_mode_enable": 1, + "loopback_support": "No", + "qspi_ref_clock": 80, + "spi_clock_freq": 20, + "spi_clock_divider": 1, + "flash_device_size": 4, + "flash_bytes_per_block": 16, + "flash_bytes_per_page": 256, + "flash_number_of_address_bytes": 3, + "flash_dual_opcode": 0, + "flash_jedec_manufacturer_id": 0, + "flash_jedec_device_id": 0, + "flash_name": "IS25WJ032F", + "flash_page_size": 256, + "flash_sector_size": 4096, + "flash_cs_polarity": "ACTIVE_LOW", + "flash_sw_reset_type": "x1xxxx", + "ram_device_size": 4, + "ram_bytes_per_block": 16, + "ram_bytes_per_page": 256, + "ram_number_of_address_bytes": 3, + "ram_dual_opcode": 0, + "ram_jedec_manufacturer_id": 0, + "ram_jedec_device_id": 0, + "ram_name": "NO_PSRAM", + "ram_page_size": 256, + "ram_sector_size": 4096, + "ram_cs_polarity": "ACTIVE_LOW", + "ram_sw_reset_type": "x1xxxx", + "flash_write_operation_modes": "4S-4S-4S", + "flash_read_operation_modes": "4S-4S-4S", + "ram_write_operation_modes": "4S-4S-4S", + "ram_read_operation_modes": "4S-4S-4S", + "crc_enable": 0, + "enable_dtr": 0, + "enable_ahb_decoder": 0, + "enter_xip_mod_immediately": 0, + "enter_xip_mod_next_read": 0, + "ahb_address_remapping": 0, + "enable_dma": 0, + "select_decode": 0, + "legacy_ip_mode": 0, + "direct_access": 1 + }, + "xspi_pinmux": { + "xspi_clk_input": 44, + "xspi_clk_input_use_hw": 0, + "xspi_clk_input_mode": "Input", + "xspi_clk_input_pull": "None", + "xspi_clk_input_interrupt_trigger": "Low", + "xspi_clk_input_dont_conf": 0, + "xspi_clk_input_output_strength": "High", + "xspi_clk_input_initial_output_state": "High", + "xspi_clk": 24, + "xspi_clk_use_hw": "None", + "xspi_clk_mode": "Output", + "xspi_clk_pull": "None", + "xspi_clk_output_strength": "High", + "xspi_clk_initial_output_state": "High", + "xspi_clk_interrupt_trigger": "None", + "xspi_clk_dont_conf": 0, + "xspi_flash_cs": 20, + "xspi_flash_cs_use_hw": "None", + "xspi_flash_cs_mode": "Output", + "xspi_flash_cs_pull": "None", + "xspi_flash_cs_output_strength": "High", + "xspi_flash_cs_initial_output_state": "High", + "xspi_flash_cs_interrupt_trigger": "None", + "xspi_flash_cs_dont_conf": 0, + "xspi_data_0": 25, + "xspi_data_0_use_hw": "None", + "xspi_data_0_mode": "Input", + "xspi_data_0_pull": "None", + "xspi_data_0_output_strength": "High", + "xspi_data_0_initial_output_state": "High", + "xspi_data_0_interrupt_trigger": "Low", + "xspi_data_0_dont_conf": 0, + "xspi_data_1": 21, + "xspi_data_1_use_hw": "None", + "xspi_data_1_mode": "Input", + "xspi_data_1_pull": "None", + "xspi_data_1_output_strength": "High", + "xspi_data_1_initial_output_state": "High", + "xspi_data_1_interrupt_trigger": "Low", + "xspi_data_1_dont_conf": 0, + "xspi_data_2": 22, + "xspi_data_2_use_hw": "None", + "xspi_data_2_mode": "Input", + "xspi_data_2_pull": "None", + "xspi_data_2_output_strength": "High", + "xspi_data_2_initial_output_state": "High", + "xspi_data_2_interrupt_trigger": "Low", + "xspi_data_2_dont_conf": 0, + "xspi_data_3": 23, + "xspi_data_3_use_hw": "None", + "xspi_data_3_mode": "Input", + "xspi_data_3_pull": "None", + "xspi_data_3_output_strength": "High", + "xspi_data_3_initial_output_state": "High", + "xspi_data_3_interrupt_trigger": "Low", + "xspi_data_3_dont_conf": 0, + "xspi_data_4": 26, + "xspi_data_4_use_hw": "None", + "xspi_data_4_mode": "Input", + "xspi_data_4_pull": "None", + "xspi_data_4_output_strength": "High", + "xspi_data_4_initial_output_state": "High", + "xspi_data_4_interrupt_trigger": "None", + "xspi_data_4_dont_conf": 0, + "xspi_data_5": 27, + "xspi_data_5_use_hw": "None", + "xspi_data_5_mode": "Input", + "xspi_data_5_pull": "None", + "xspi_data_5_output_strength": "High", + "xspi_data_5_initial_output_state": "High", + "xspi_data_5_interrupt_trigger": "None", + "xspi_data_5_dont_conf": 0, + "xspi_data_6": 28, + "xspi_data_6_use_hw": "None", + "xspi_data_6_mode": "Input", + "xspi_data_6_pull": "None", + "xspi_data_6_output_strength": "High", + "xspi_data_6_initial_output_state": "High", + "xspi_data_6_interrupt_trigger": "None", + "xspi_data_6_dont_conf": 0, + "xspi_data_7": 29, + "xspi_data_7_use_hw": "None", + "xspi_data_7_mode": "Input", + "xspi_data_7_pull": "None", + "xspi_data_7_output_strength": "High", + "xspi_data_7_initial_output_state": "High", + "xspi_data_7_interrupt_trigger": "None", + "xspi_data_7_dont_conf": 0, + "xspi_reset_flash": 36, + "xspi_reset_flash_use_hw": "None", + "xspi_reset_flash_mode": "Output", + "xspi_reset_flash_pull": "None", + "xspi_reset_flash_output_strength": "High", + "xspi_reset_flash_initial_output_state": "High", + "xspi_reset_flash_interrupt_trigger": "None", + "xspi_reset_flash_dont_conf": 0, + "xspi_cs_ram": 3, + "xspi_cs_ram_use_hw": "None", + "xspi_cs_ram_mode": "Output", + "xspi_cs_ram_pull": "None", + "xspi_cs_ram_output_strength": "High", + "xspi_cs_ram_initial_output_state": "High", + "xspi_cs_ram_interrupt_trigger": "None", + "xspi_cs_ram_dont_conf": 0, + "xspi_dqs": 30, + "xspi_dqs_use_hw": "None", + "xspi_dqs_mode": "Input", + "xspi_dqs_pull": "None", + "xspi_dqs_output_strength": "High", + "xspi_dqs_initial_output_state": "High", + "xspi_dqs_interrupt_trigger": "None", + "xspi_dqs_dont_conf": 0, + "xspi_reset_ram": 2, + "xspi_reset_ram_use_hw": "None", + "xspi_reset_ram_mode": "Input", + "xspi_reset_ram_pull": "None", + "xspi_reset_ram_output_strength": "High", + "xspi_reset_ram_initial_output_state": "High", + "xspi_reset_ram_interrupt_trigger": "None", + "xspi_reset_ram_dont_conf": 0 + }, + "xspi_operations": { + "xspi_operations_clocks": { + "clock_phase": 0, + "clock_polarity": 0, + "spi_mode": "2'b00" + }, + "xspi_operations_chip_select": { + "csda": 2, + "csdads": 0, + "cseot": 4, + "cssot": 1 + }, + "xspi_operations_reset": { + "flash_jedec_reset": 0, + "ram_jedec_reset": 0, + "flash_treset": 20, + "ram_treset": 20 + }, + "xspi_phy_operations": { + "flash_rx_dll_bypass_bit": 0, + "flash_dll_tx_delay": 22, + "flash_dll_rx_delay": 34, + "ram_rx_dll_bypass_bit": 0, + "ram_dll_tx_delay": 22, + "ram_dll_rx_delay": 34 + }, + "xspi_read_operations": { + "flash_dummy_rd_cycles": 4, + "flash_read_opcode": 11, + "suppl_flash_read_opcode": 0, + "ram_dummy_rd_cycles": 4, + "ram_read_opcode": 11, + "suppl_ram_read_opcode": 0, + "flash_non_cont_read_enable": 0, + "flash_max_read_jobs": 256, + "ram_non_cont_read_enable": 0, + "ram_max_read_jobs": 256, + "rww_en": 0, + "device_size": 4, + "number_of_banks": 1, + "bank_size": 4, + "mode_bit_enable": 0 + }, + "xspi_write_operations": { + "flash_address_and_data": { + "flash_dummy_wr_cycles": 0 + }, + "flash_command": { + "flash_write_opcode": 2, + "suppl_flash_write_opcode": 0 + }, + "ram_address_and_data": { + "ram_dummy_wr_cycles": 0 + }, + "ram_command": { + "ram_write_opcode": 2, + "suppl_ram_write_opcode": 0 + }, + "write_to_buffer": { + "flash_write_to_buffer_support": 0, + "ram_write_to_buffer_support": 0 + }, + "non_continuous_write": { + "flash_non_cont_write_enable": 0, + "flash_max_write_jobs": 64, + "ram_non_cont_write_enable": 0, + "ram_max_write_jobs": 0 + }, + "flash_program_operation": { + "flash_min_program_size": "256 B", + "flash_program_opcode": 2, + "suppl_flash_program_opcode": 0, + "flash_maximum_program_time_limit": 1600 + }, + "flash_erase_operation": { + "flash_min_erase_size": "4 kB", + "flash_erase_opcode": 32, + "suppl_flash_erase_opcode": 0, + "flash_maximum_erase_time_limit": 4095 + }, + "flash_erase_conf": { + "flash_block_erase_opcode": 0, + "suppl_block_flash_erase_opcode": 0, + "flash_sector_erase_opcode": 0, + "suppl_sector_flash_erase_opcode": 0, + "flash_chip_erase_opcode": 0, + "suppl_chip_flash_erase_opcode": 0 + }, + "ram_program_operation": { + "ram_min_program_size": "256 B", + "ram_program_opcode": 2, + "suppl_ram_program_opcode": 0, + "ram_maximum_program_time_limit": 1600 + }, + "ram_erase_conf": { + "ram_block_erase_opcode": 0, + "suppl_block_ram_erase_opcode": 0, + "ram_sector_erase_opcode": 0, + "suppl_sector_ram_erase_opcode": 0, + "ram_chip_erase_opcode": 0, + "suppl_chip_ram_erase_opcode": 0 + }, + "flash_buffer_support": { + "flash_pre_write_sequence": 0, + "flash_post_write_sequence": 0, + "flash_write_protection_timer_en": 0, + "flash_write_buffer_timer_mode": 16, + "flash_write_buffer_timer_range": 0, + "flash_service_interrupt_criteria": 0 + }, + "ram_buffer_support": { + "ram_pre_write_sequence": 0, + "ram_post_write_sequence": 0, + "ram_write_protection_timer_en": 0, + "ram_write_buffer_timer_mode": 16, + "ram_write_buffer_timer_range": 0, + "ram_service_interrupt_criteria": 0 + }, + "flash_pre_write_conf": { + "flash_pre_write_job_done_grant_sel": 0, + "data_for_flash_pre_write_conf_0": 0, + "offset_bits_for_flash_pre_write_conf_0": 0, + "stop_bit_for_flash_pre_write_conf_0": 1, + "data_for_flash_pre_write_conf_1": 0, + "offset_bits_for_flash_pre_write_conf_1": 0 + }, + "flash_post_write_conf": { + "flash_post_write_job_done_grant_sel": 0, + "data_for_flash_post_write_conf_0": 0, + "offset_bits_for_flash_post_write_conf_0": 0, + "stop_bit_for_flash_post_write_conf_0": 1, + "data_for_flash_post_write_conf_1": 0, + "offset_bits_for_flash_post_write_conf_1": 0 + }, + "ram_pre_write_conf": { + "ram_pre_write_job_done_grant_sel": 0, + "data_for_ram_pre_write_conf_0": 0, + "offset_bits_for_ram_pre_write_conf_0": 0, + "stop_bit_for_ram_pre_write_conf_0": 1, + "data_for_ram_pre_write_conf_1": 0, + "offset_bits_for_ram_pre_write_conf_1": 0 + }, + "ram_post_write_conf": { + "ram_post_write_job_done_grant_sel": 0, + "data_for_ram_post_write_conf_0": 0, + "offset_bits_for_ram_post_write_conf_0": 0, + "stop_bit_for_ram_post_write_conf_0": 1, + "data_for_ram_post_write_conf_1": 0, + "offset_bits_for_ram_post_write_conf_1": 0 + } + }, + "xspi_capture_operations": { + "read_data_capture": { + "flash_delay_transmitted_data": 0, + "flash_loopback_clock": 0, + "flash_bypass_adapted_loopback": 1, + "flash_sample_edge_sel": 0, + "ram_delay_transmitted_data": 0, + "ram_loopback_clock": 0, + "ram_bypass_adapted_loopback": 1, + "ram_sample_edge_sel": 0 + }, + "delays": { + "flash_full_half_cycle_delay": 0, + "flash_dll_bypass_mode": 1, + "flash_phase_detect_sel": 0, + "flash_dll_lock_num": 0, + "flash_dll_start_point": 0, + "flash_loopback_clock": 0, + "ram_full_half_cycle_delay": 0, + "ram_dll_bypass_mode": 1, + "ram_phase_detect_sel": 0, + "ram_dll_lock_num": 0, + "ram_dll_start_point": 0, + "ram_loopback_clock": 0 + }, + "operation_modes": { + "flash_sfdp_support": 0, + "ram_sfdp_support": 0, + "flash_pm_support": 0, + "ram_pm_support": 0, + "flash_sfdp_opcode": 0, + "suppl_flash_sfdp_opcode": 0, + "ram_sfdp_opcode": 0, + "suppl_ram_sfdp_opcode": 0, + "flash_enter_dpd_opcode": 185, + "suppl_flash_enter_dpd_opcode": 0, + "flash_exit_dpd_opcode": 171, + "suppl_flash_exit_dpd_opcode": 0, + "ram_enter_dpd_opcode": 185, + "suppl_ram_enter_dpd_opcode": 0, + "ram_exit_dpd_opcode": 171, + "suppl_ram_exit_dpd_opcode": 0, + "flash_quad_enable_opcode": 56, + "suppl_flash_quad_enable_opcode": 0, + "flash_quad_disable_opcode": 255, + "suppl_flash_quad_disable_opcode": 0, + "flash_octal_enable_opcode": 0, + "suppl_flash_octal_enable_opcode": 0, + "flash_octal_disable_opcode": 0, + "suppl_flash_octal_disable_opcode": 0, + "ram_quad_enable_opcode": 56, + "suppl_ram_quad_enable_opcode": 0, + "ram_quad_disable_opcode": 255, + "suppl_ram_quad_disable_opcode": 0, + "ram_octal_enable_opcode": 0, + "suppl_ram_octal_enable_opcode": 0, + "ram_octal_disable_opcode": 0, + "suppl_ram_octal_disable_opcode": 0 + } + } + }, + "external_memory_reporting": { + "header": { + "flash_auto_polling_enable": 1, + "flash_wel_enable": 1, + "flash_write_protect_enable": 0, + "flash_alternate_polling_conf_enable": 0, + "ram_auto_polling_enable": 1, + "ram_wel_enable": 1, + "ram_write_protect_enable": 0, + "ram_alternate_polling_conf_enable": 0 + }, + "flash_auto_polling": { + "flash_polling_repetition_delay": 0, + "flash_polling_count": 4, + "flash_enable_polling_expiration": 0, + "flash_polling_polarity": 0, + "flash_polling_address_phase_enable": 0, + "flash_polling_bit_index": 0, + "flash_numbers_poll_cycles": 65535, + "flash_dummy_autopoll_cycles": 0 + }, + "ram_auto_polling": { + "ram_polling_repetition_delay": 0, + "ram_polling_count": 4, + "ram_enable_polling_expiration": 0, + "ram_polling_polarity": 0, + "ram_polling_address_phase_enable": 0, + "ram_polling_bit_index": 0, + "ram_numbers_poll_cycles": 65535, + "ram_dummy_autopoll_cycles": 0 + }, + "flash_polling_command": { + "flash_polling_opcode": 5, + "suppl_flash_polling_opcode": 0 + }, + "ram_polling_command": { + "ram_polling_opcode": 5, + "suppl_ram_polling_opcode": 0 + }, + "flash_alternate_polling": { + "flash_polling_resp_count": 1023, + "flash_polling_iterations": 1, + "flash_polling_enabled": 0, + "flash_polling_disabled": 0, + "flash_grant_sel": 0, + "flash_data_for_enable_poling_conf_0": 0, + "flash_offset_bits_for_enable_poling_conf_0": 0, + "flash_stop_bit_for_enable_poling_conf_0": 1, + "flash_data_for_enable_poling_conf_1": 0, + "flash_offset_bits_for_enable_poling_conf_1": 0, + "flash_stop_bit_for_enable_poling_conf_1": 1, + "flash_data_for_disable_poling_conf_0": 0, + "flash_offset_bits_for_disable_poling_conf_0": 0, + "flash_stop_bit_for_disable_poling_conf_0": 1, + "flash_data_for_disable_poling_conf_1": 0, + "flash_offset_bits_for_disable_poling_conf_1": 0, + "flash_stop_bit_for_disable_poling_conf_1": 1 + }, + "ram_alternate_polling": { + "ram_polling_resp_count": 1023, + "ram_polling_iterations": 1, + "ram_polling_enabled": 0, + "ram_polling_disabled": 0, + "ram_grant_sel": 0, + "ram_data_for_enable_poling_conf_0": 0, + "ram_offset_bits_for_enable_poling_conf_0": 0, + "ram_stop_bit_for_enable_poling_conf_0": 1, + "ram_data_for_enable_poling_conf_1": 0, + "ram_offset_bits_for_enable_poling_conf_1": 0, + "ram_stop_bit_for_enable_poling_conf_1": 1, + "ram_data_for_disable_poling_conf_0": 0, + "ram_offset_bits_for_disable_poling_conf_0": 0, + "ram_stop_bit_for_disable_poling_conf_0": 1, + "ram_data_for_disable_poling_conf_1": 0, + "ram_offset_bits_for_disable_poling_conf_1": 0, + "ram_stop_bit_for_disable_poling_conf_1": 1 + }, + "flash_wel_command": { + "flash_wel_opcode": 6, + "suppl_flash_wel_opcode": 0 + }, + "ram_wel_command": { + "ram_wel_opcode": 6, + "suppl_ram_wel_opcode": 0 + } + }, + "event": { + "host_nvic_irq": 0, + "core_10_mux_sel": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/fuse_prog_inst_param.json b/boards/ti/lp_em_cc35x1/config/fuse_prog_inst_param.json new file mode 100644 index 000000000000..7c75c3af701d --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/fuse_prog_inst_param.json @@ -0,0 +1,34 @@ +{ + "rot": null, + "security_failure_behavoral": 0, + "use_ti_root_of_trust_secondary": 0, + "otfde_protection_enable": 0, + "action_request_authentication_enable": 0, + "vendor_sbl_container_enable": 0, + "vendor_container_authentication_enable": 0, + "application_otp_usage": 1, + "crda_code_enable": 0, + "permanently_lock_debug_enable": 0, + "wifi6_disable": 0, + "qspi_ospi_flash_type": 0, + "flash_exist": 1, + "boot_sector_programmed": 0, + "flash_reset_type": 0, + "otp_structure_version": 0, + "vendor_restricted_ini": 0, + "mac_address_31_0": 0, + "mac_address_47_32": 0, + "crda_country_code": 0, + "wsoc_fw_rollback_protection_1": 0, + "wsoc_fw_rollback_protection_2": 0, + "wsoc_fw_rollback_protection_3": 0, + "ti_bootloader_fw_rollback_protection_1": 0, + "ti_bootloader_fw_rollback_protection_2": 0, + "ti_bootloader_fw_rollback_protection_3": 0, + "vendor_sbl_fw_rollback_protection_1": 0, + "vendor_sbl_fw_rollback_protection_2": 0, + "vendor_sbl_fw_rollback_protection_3": 0, + "vendor_image_rollback_protection_1": 0, + "vendor_image_rollback_protection_2": 0, + "app_otp": "" +} diff --git a/boards/ti/lp_em_cc35x1/config/tool_settings.json b/boards/ti/lp_em_cc35x1/config/tool_settings.json new file mode 100644 index 000000000000..d32bb433df56 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/tool_settings.json @@ -0,0 +1,61 @@ +{ + "ini_composer_outputs": { + "ini_to_h_paths": { + "ini_to_h": null + } + }, + "linker_update": { + "linker_cmd_paths": { + "linker_cmd_genlibs": null + } + }, + "vendor_unsigned_images_paths": { + "actions_req_paths": { + "query": null, + "programming": null, + "debug": null + }, + "vendor_images_paths": { + "programming_instructions": null, + "primary_vendor_image": null, + "secondary_vendor_image": null, + "primary_vendor_sbl": null, + "secondary_vendor_sbl": null + } + }, + "vendor_signed_container_and_action_req_generation": { + "signature_generation_info": { + "target_device_info": { + "id_list": {} + }, + "sig_generation_methodology": { + "type": "local" + }, + "public_key_path": null, + "info": null, + "siginning_credential": null, + "remote_serve_connection_info": null + } + }, + "programming_debug_and_ota_signed_components": { + "tbl_container_programming": null, + "primary_tbl": null, + "secondary_tbl": null, + "primary_ti_wsoc": null, + "secondary_ti_wsoc": null, + "primary_ti_wsoc_bl2": null, + "secondary_ti_wsoc_bl2": null, + "actions_req_paths": { + "query": null, + "programming": "zephyr/flash/programming_action_request.sign.bin", + "debug": "zephyr/flash/debug_action_request.sign.bin" + }, + "boot_sector": null, + "programming_instructions": "zephyr/flash/programming_instructions_image.sign.bin", + "primary_vendor_image": "zephyr/flash/vendor_image.sign.bin", + "secondary_vendor_image": null, + "primary_vendor_sbl": null, + "secondary_vendor_sbl": null, + "protected_storage": null + } +} diff --git a/boards/ti/lp_em_cc35x1/doc/index.rst b/boards/ti/lp_em_cc35x1/doc/index.rst new file mode 100644 index 000000000000..de8f7d66cdc7 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/doc/index.rst @@ -0,0 +1,61 @@ +.. _lp_em_cc35x1: + +.. |reg| unicode:: U+00AE +.. |trade| unicode:: U+2122 + +.. zephyr:board:: lp_em_cc35x1 + +TI cc35x1 Launchpad +##################### + +Overview +******** + +The Texas Instruments cc35x1 LaunchPad |trade| (LP_EM_CC35X1) is a +development kit for the SimpleLink |trade| multi-standard cc35x1 wireless MCU. + +See the `TI cc35x1 LaunchPad Product Page`_ for details. + +Hardware +******** + +The cc35x1 LaunchPad |trade| development kit features the cc3551e wireless MCU. +The board is equipped with two LEDs and two push buttons + +The cc35x1 wireless MCU has a 160 MHz Arm |reg| Cortex |reg|-M33 SoC and an +integrated 2.4 GHz transceiver supporting multiple protocols including Bluetooth +|reg| Low Energy and IEEE |reg| 802.15.4. + +See the `TI cc35x1 Product Page`_ for additional details. + +Supported Features +================== + +The cc35x1 LaunchPad board configuration supports the following hardware +features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. + +Programming and Debugging +************************* + +The LP_EM_CC35X1 requires an external debug probe such as the LP-XDS110 or +LP-XDS110ET. + +Currently there is no debug support in Zephyr for the LP_EM_CC35X1. Binaries can be flashed +with the standard ``west flash`` command. + +References +********** + +.. _TI cc35x1 LaunchPad Product Page: + https://www.ti.com/tool/LP-EM-CC35X1 + +.. _TI cc35x1 Product Page: + https://www.ti.com/product/CC3551E diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1-pinctrl.dtsi b/boards/ti/lp_em_cc35x1/lp_em_cc35x1-pinctrl.dtsi new file mode 100644 index 000000000000..33fd50cbd5f9 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1-pinctrl.dtsi @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2025 Conclusive Engineering Sp. z o.o. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = , ; + }; + }; + + uart1_default: uart1_default { + group1 { + pinmux = , ; + }; + }; + + uart2_default: uart2_default { + group1 { + pinmux = , ; + }; + }; + + spi0_slave: spi0_slave { + group1 { + pinmux = , + <(TI_CC35XX_PINCTRL_DIR_OUT | P28_SPI0_MISO)>, + <(TI_CC35XX_PINCTRL_DIR_IN | P29_SPI0_MOSI)>, + <(TI_CC35XX_PINCTRL_DIR_IN | P26_SPI0_CS1)>; + }; + }; + + spi0_master: spi0_master { + group1 { + pinmux = , + <(TI_CC35XX_PINCTRL_DIR_IN | P28_SPI0_MISO)>, + <(TI_CC35XX_PINCTRL_DIR_OUT | P29_SPI0_MOSI)>, + <(TI_CC35XX_PINCTRL_DIR_OUT | P26_SPI0_CS1)>; + }; + }; + + spi1_slave: spi1_slave { + group1 { + pinmux = , + <(TI_CC35XX_PINCTRL_DIR_OUT | P15_SPI1_MISO)>, + <(TI_CC35XX_PINCTRL_DIR_IN | P13_SPI1_MOSI)>, + <(TI_CC35XX_PINCTRL_DIR_IN | P12_SPI1_CS1)>; + }; + }; + + spi1_master: spi1_master { + group1 { + pinmux = , + <(TI_CC35XX_PINCTRL_DIR_IN | P15_SPI1_MISO)>, + <(TI_CC35XX_PINCTRL_DIR_OUT | P13_SPI1_MOSI)>, + <(TI_CC35XX_PINCTRL_DIR_OUT | P12_SPI1_CS1)>; + }; + }; + + adc0_default: adc0_default { + group1 { + pinmux = , ; + }; + }; + + pwm3_default: lgpt1_chan0_default { + group1 { + pinmux = ; + }; + }; + + pwm4_default: lgpt1_chan1_default { + group1 { + pinmux = ; + }; + }; + + pwm5_default: lgpt1_chan2_default { + group1 { + pinmux = ; + }; + }; + + i2c1_default: i2c1_default { + group1 { + pinmux = , ; + }; + }; + + i2s_default: i2s_default { + group1 { + pinmux = <(TI_CC35XX_PINCTRL_DIR_IN | P29_I2S_BCLK)>, + <(TI_CC35XX_PINCTRL_DIR_IN | P26_I2S_WCLK)>, + <(TI_CC35XX_PINCTRL_DIR_IN | P30_I2S_DATA0)>, + <(TI_CC35XX_PINCTRL_DIR_IN | P35_I2S_DATA1)>; + }; + }; + + can_default: can_default { + group1 { + pinmux = , + ; + }; + }; + + sdhc_mmc_default: sdhc_mmc_default { + group1 { + pinmux = <(TI_CC35XX_PINCTRL_PULL_UP | P10_SDIO_MMC_DATA_3)>, + <(TI_CC35XX_PINCTRL_PULL_UP | P11_SDIO_MMC_DATA_2)>, + <(TI_CC35XX_PINCTRL_PULL_UP | P12_SDIO_MMC_DATA_1)>, + <(TI_CC35XX_PINCTRL_PULL_UP | P13_SDIO_MMC_DATA_0)>, + <(TI_CC35XX_PINCTRL_PULL_UP | P14_SDIO_MMC_CLK)>, + <(TI_CC35XX_PINCTRL_PULL_UP | P15_SDIO_MMC_CMD)>; + }; + }; +}; diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml b/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml new file mode 100644 index 000000000000..b4293ec1512e --- /dev/null +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml @@ -0,0 +1,26 @@ +identifier: lp_em_cc35x1 +name: TI SimpleLink™ CC35x1 LaunchPad +type: mcu +arch: arm +ram: 1024 +flash: 4096 +toolchain: + - zephyr + - gnuarmemb +supported: + - adc + - can + - counter + - dma + - entropy + - gpio + - i2s + - pinctrl + - pwm + - rtc + - sdhc + - serial + - spi + - watchdog + - netif:wifi +vendor: ti diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_8m.overlay b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_8m.overlay new file mode 100644 index 000000000000..7d008a2272fe --- /dev/null +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_8m.overlay @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2026 Conclusive Engineering Sp. z o.o. + * SPDX-License-Identifier: Apache-2.0 + */ + +&extflash_ns { + reg = <0x10000000 DT_SIZE_M(8)>; +}; + +&extflash { + reg = <0x14000000 DT_SIZE_M(8)>; +}; + +&flash0 { + reg = <0x14000000 0x544000>, <0x2bc000 0x544000>; + + partitions { + /delete-node/ partition@0; + + vendor_image_partition: partition@0 { + label = "vendor-image"; + reg = <0x0 0x544000>; + }; + }; +}; + +&flash1 { + reg = <0xa0000000 0x1b2000>, <0x0 0x1b2000>; + + partitions { + /delete-node/ partition@68000; + /delete-node/ partition@da000; + + wifi_fw_slot1_partition: partition@ce000 { + label = "wifi-fw-1"; + reg = <0xce000 0x72000>; + }; + + wifi_fw_slot2_partition: partition@140000 { + label = "wifi-fw-2"; + reg = <0x140000 0x72000>; + }; + }; +}; + +&{/soc} { + /delete-node/ flash@a00da000; + + flash2: flash@a01b2000 { + compatible = "ti,cc35xx-nv-flash"; + reg = <0xa01b2000 0x10a000>, <0x1b2000 0x10a000>; + erase-block-size = <0x1000>; + write-block-size = <0x4>; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + wifi_nvs_partition: partition@0 { + label = "wifi-nvs"; + reg = <0x0 0x8000>; + }; + + storage_partition: partition@8000 { + label = "storage"; + reg = <0x8000 0x102000>; + }; + }; + }; +}; diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3500e.dts b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3500e.dts new file mode 100644 index 000000000000..38303a555356 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3500e.dts @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Conclusive Engineering Sp. z o.o. + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "lp_em_cc35x1_common.dtsi" diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3500e_defconfig b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3500e_defconfig new file mode 100644 index 000000000000..97551f745932 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3500e_defconfig @@ -0,0 +1,18 @@ +# +# Copyright (c) 2025-2026 Conclusive Engineering Sp. z o.o. +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_SHARED_MULTI_HEAP=y +CONFIG_THREAD_STACK_INFO=y +CONFIG_DYNAMIC_THREAD=y +CONFIG_TEST_RANDOM_GENERATOR=y +CONFIG_TIMER_RANDOM_GENERATOR=y + +CONFIG_GPIO=y + +CONFIG_SERIAL=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3501e.dts b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3501e.dts new file mode 100644 index 000000000000..a66baa0bb496 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3501e.dts @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Conclusive Engineering Sp. z o.o. + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "lp_em_cc35x1_common.dtsi" + +/ { + chosen { + zephyr,bt-hci = &hci0; + }; +}; diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3501e_defconfig b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3501e_defconfig new file mode 100644 index 000000000000..b9c47e7ab958 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3501e_defconfig @@ -0,0 +1,34 @@ +# +# Copyright (c) 2026 Conclusive Engineering Sp. z o.o. +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_SHARED_MULTI_HEAP=y + +CONFIG_GPIO=y +CONFIG_GPIO_GET_CONFIG=y +CONFIG_GPIO_GET_DIRECTION=y +CONFIG_GPIO_HOGS=y +CONFIG_GPIO_SHELL=y +CONFIG_GPIO_SHELL_INFO_CMD=y +CONFIG_GPIO_SHELL_TOGGLE_CMD=y +CONFIG_GPIO_SHELL_BLINK_CMD=y + +CONFIG_SERIAL=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SHELL=y +CONFIG_SHELL_STACK_SIZE=4096 +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN=y +CONFIG_SHELL_BACKEND_SERIAL_API_INTERRUPT_DRIVEN=y + +CONFIG_FLASH=y +CONFIG_SOC_FLASH_CC35XX=y +CONFIG_FLASH_SHELL=y + +# Required for BLE operation. Explicitly disable this config option here, as +# some BLE samples enable it by default. +CONFIG_BT_HCI_ACL_FLOW_CONTROL=n diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3550e.dts b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3550e.dts new file mode 100644 index 000000000000..38303a555356 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3550e.dts @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Conclusive Engineering Sp. z o.o. + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "lp_em_cc35x1_common.dtsi" diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3550e_defconfig b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3550e_defconfig new file mode 100644 index 000000000000..559cbc09d378 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3550e_defconfig @@ -0,0 +1,18 @@ +# +# Copyright (c) 2026 Conclusive Engineering Sp. z o.o. +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_SHARED_MULTI_HEAP=y +CONFIG_THREAD_STACK_INFO=y +CONFIG_DYNAMIC_THREAD=y +CONFIG_TEST_RANDOM_GENERATOR=y +CONFIG_TIMER_RANDOM_GENERATOR=y + +CONFIG_GPIO=y + +CONFIG_SERIAL=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3551e.dts b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3551e.dts new file mode 100644 index 000000000000..a66baa0bb496 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3551e.dts @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Conclusive Engineering Sp. z o.o. + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "lp_em_cc35x1_common.dtsi" + +/ { + chosen { + zephyr,bt-hci = &hci0; + }; +}; diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3551e.yaml b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3551e.yaml new file mode 100644 index 000000000000..7fd9c1ea7f20 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3551e.yaml @@ -0,0 +1,33 @@ +identifier: lp_em_cc35x1/cc3551e +name: TI SimpleLink CC3551E LaunchPad +type: mcu +arch: arm +ram: 1024 +flash: 4096 +toolchain: + - zephyr + - gnuarmemb +supported: + - spi + - uart + - drivers + - flash + - nvs + - pinctrl + - gpio + - serial + - entropy + - counter + - watchdog + - netif:wifi + - rtc + - adc + - pwm + - userspace + - dma + - i2s + - can + - disk +testing: + default: true +vendor: ti diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3551e_defconfig b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3551e_defconfig new file mode 100644 index 000000000000..6a2b48f9eee3 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3551e_defconfig @@ -0,0 +1,22 @@ +# +# Copyright (c) 2026 Conclusive Engineering Sp. z o.o. +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_SHARED_MULTI_HEAP=y +CONFIG_THREAD_STACK_INFO=y +CONFIG_DYNAMIC_THREAD=y +CONFIG_TEST_RANDOM_GENERATOR=y +CONFIG_TIMER_RANDOM_GENERATOR=y + +CONFIG_GPIO=y + +CONFIG_SERIAL=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Required for BLE operation. Explicitly disable this config option here, as +# some BLE samples enable it by default. +CONFIG_BT_HCI_ACL_FLOW_CONTROL=n diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi new file mode 100644 index 000000000000..c15a202cb3c3 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi @@ -0,0 +1,309 @@ +/* + * Copyright (c) 2025 Conclusive Engineering Sp. z o.o. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include "boosterpack_connector.dtsi" +#include "lp_em_cc35x1-pinctrl.dtsi" +#include + +/ { + model = "TI CC35X1E LaunchPad"; + compatible = "ti,launchpad-cc35x1e"; + + chosen { + zephyr,sram = &dmem_ns; + zephyr,flash = &extflash; + zephyr,itcm = &itcm_ns; + zephyr,dtcm = &dtcm_ns; + zephyr,code-partition = &dmem_ns; + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,rtc = &rtc; + zephyr,entropy = &entropy; + }; + + leds { + compatible = "gpio-leds"; + + red_led: red_led { + gpios = <&gpios 34 GPIO_ACTIVE_HIGH>; + label = "RED USER LED"; + }; + + blue_led: blue_led { + gpios = <&gpios 35 GPIO_ACTIVE_HIGH>; + label = "BLUE USER LED"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + green_pwm: pwm_led_0 { + pwms = <&pwm4 1 1000 PWM_POLARITY_NORMAL>; + label = "Green PWM LED"; + }; + }; + + buttons { + compatible = "gpio-keys"; + + user_switch_1: user_sw_1 { + gpios = <&gpios 2 GPIO_ACTIVE_LOW>; + label = "User SW1"; + zephyr,code = ; + }; + + user_switch_2: user_sw_2 { + gpios = <&gpios 36 GPIO_ACTIVE_LOW>; + label = "User SW2"; + zephyr,code = ; + }; + }; + + aliases { + led0 = &red_led; + led1 = &blue_led; + pwm-led0 = &green_pwm; + ambient-temp0 = &tmp1075_temperature; + sw0 = &user_switch_1; + sw1 = &user_switch_2; + adc0 = &adc0; + dma0 = &dma; + rtc = &rtc; + sdhc0 = &sdhc; + }; +}; + +&imem_ns { + status = "okay"; +}; + +&dmem_shared { + status = "okay"; +}; + +&dmem_ns { + status = "okay"; +}; + +&itcm_ns { + status = "okay"; +}; + +&dtcm_ns { + status = "okay"; +}; + +&itcm { + status = "okay"; +}; + +&dtcm { + status = "okay"; +}; + +&dma { + status = "okay"; +}; + +&spi0 { + status = "disabled"; + pinctrl-0 = <&spi0_master>; + pinctrl-names = "default"; + cs-gpios = <&gpios 26 GPIO_ACTIVE_LOW>; + dmas = <&dma 4 CC35XX_DMA_SET_CONFIG(CC35xx_DMA_PERIPH_SPI_0)>, + <&dma 5 CC35XX_DMA_SET_CONFIG(CC35xx_DMA_PERIPH_SPI_0)>; + dma-names = "tx", "rx"; +}; + +&spi1 { + status = "disabled"; + pinctrl-0 = <&spi1_slave>; + pinctrl-names = "default"; + dmas = <&dma 8 CC35XX_DMA_SET_CONFIG(CC35xx_DMA_PERIPH_SPI_1)>, + <&dma 9 CC35XX_DMA_SET_CONFIG(CC35xx_DMA_PERIPH_SPI_1)>; + dma-names = "tx", "rx"; +}; + +&flash0 { + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + vendor_image_partition: partition@0 { + label = "vendor-image"; + reg = <0x0 0x2fb000>; + }; + }; +}; + +&flash1 { + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + wifi_fw_slot1_partition: partition@68000 { + label = "wifi-fw-1"; + reg = <0x68000 0x72000>; + }; + + wifi_fw_slot2_partition: partition@da000 { + label = "wifi-fw-2"; + reg = <0xda000 0x2b000>; + }; + }; +}; + +&flash2 { + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* WiFi/BLE NVS: profiles, BLE security, connection policy */ + /* 8 sectors = 32 KB with wear-leveling */ + wifi_nvs_partition: partition@0 { + label = "wifi-nvs"; + reg = <0x0 0x8000>; + }; + + storage_partition: partition@8000 { + label = "storage"; + reg = <0x8000 0x23000>; + }; + }; +}; + +&i2c1 { + status = "disabled"; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; + + tmp1075_temperature: tmp1075@48 { + compatible = "lm75"; + friendly-name = "texas_temperature_tmp1075"; + reg = <0x48>; + }; + + bma4xx_accelerometer: bma4xx@18 { + compatible = "bosch,bma4xx"; + reg = <0x18>; + }; +}; + +&adc0 { + status = "disabled"; + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; + dmas = <&dma 6 CC35XX_DMA_SET_CONFIG(CC35xx_DMA_PERIPH_ADC)>; + vref-internal-mv = <1400>; + + channel@4 { + reg = <0x4>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + channel@5 { + reg = <0x5>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; +}; + +&uart0 { + status = "okay"; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; + dmas = <&dma 0 CC35XX_DMA_SET_CONFIG(CC35xx_DMA_PERIPH_UARTLIN_0)>, + <&dma 1 CC35XX_DMA_SET_CONFIG(CC35xx_DMA_PERIPH_UARTLIN_0)>; + dma-names = "rx", "tx"; +}; + +&uart1 { + status = "okay"; + pinctrl-0 = <&uart1_default>; + pinctrl-names = "default"; + dmas = <&dma 2 CC35XX_DMA_SET_CONFIG(CC35xx_DMA_PERIPH_UARTLIN_1)>, + <&dma 3 CC35XX_DMA_SET_CONFIG(CC35xx_DMA_PERIPH_UARTLIN_1)>; + dma-names = "rx", "tx"; +}; + +&timer1 { + clk-prescale = <0x1>; + status = "disabled"; +}; + +&pwm4 { + pinctrl-0 = <&pwm4_default>; + pinctrl-names = "default"; + status = "disabled"; +}; + +&wdt0 { + status = "okay"; +}; + +&hsm { + status = "okay"; +}; + +&entropy { + status = "okay"; +}; + +&crypto { + status = "okay"; +}; + +&i2s0 { + status = "disabled"; + pinctrl-0 = <&i2s_default>; + pinctrl-names = "default"; + clock-source = ; + pin-dir-sd0 = ; + pin-dir-sd1 = ; +}; + +&can0 { + status = "disabled"; + pinctrl-0 = <&can_default>; + pinctrl-names = "default"; +}; + +&sdhc { + status = "disabled"; + pinctrl-0 = <&sdhc_mmc_default>; + pinctrl-names = "default"; + max-bus-freq = ; + power-delay-ms = <500>; + card-always-present; + + sdmmc { + compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; + }; +}; diff --git a/boards/ti/lp_em_cc35x1/shared_mem.c b/boards/ti/lp_em_cc35x1/shared_mem.c new file mode 100644 index 000000000000..cae40d2ed8fd --- /dev/null +++ b/boards/ti/lp_em_cc35x1/shared_mem.c @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2026 Conclusive Engineering Sp. z o.o. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay) + +static struct shared_multi_heap_region dtcm_region = { + .addr = (uintptr_t)DT_REG_ADDR(DT_CHOSEN(zephyr_dtcm)), + .size = DT_REG_SIZE(DT_CHOSEN(zephyr_dtcm)), + .attr = SMH_REG_ATTR_NON_CACHEABLE, +}; + +static int cc35xx_multi_heap_init(void) +{ + int ret = shared_multi_heap_pool_init(); + + return ret ? ret : shared_multi_heap_add(&dtcm_region, NULL); +} + +SYS_INIT(cc35xx_multi_heap_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); + +#endif /* DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay) */ diff --git a/boards/ti/lp_em_cc35x1/support/openocd.cfg b/boards/ti/lp_em_cc35x1/support/openocd.cfg new file mode 100644 index 000000000000..66c4dfa59c71 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/support/openocd.cfg @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (C) 2025-2026 Texas Instruments Incorporated - https://www.ti.com/ +# + +source [find interface/cmsis-dap.cfg] +adapter speed 1000 +transport select swd +source [find ti_cc35x1e.cfg] diff --git a/boards/ti/lp_em_cc35x1/support/ti_cc35x1e.cfg b/boards/ti/lp_em_cc35x1/support/ti_cc35x1e.cfg new file mode 100644 index 000000000000..6251b6c50b09 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/support/ti_cc35x1e.cfg @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (C) 2025-2026 Texas Instruments Incorporated - https://www.ti.com/ +# + +source [find bitsbytes.tcl] + +#set _ENDIAN big + +# Device info +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME cc35x1e +} + +if { [info exists CPUTAPID] } { + set _DAP_TAPID $CPUTAPID +} else { + set _DAP_TAPID 0x0BB9602F + #set _DAP_TAPID 0x4ba02477 +} + +if { [info exists DAP_SWD_ID] } { + set _DAP_SWD_ID $DAP_SWD_ID +} else { + #set _DAP_SWD_ID 0x4ba02477 + set _DAP_SWD_ID 0x0BB9602F +} + +source [find target/swj-dp.tcl] + +if { [using_jtag] } { + set _DAP_ID $_DAP_TAPID +} else { + set _DAP_ID $_DAP_SWD_ID +} + +# Create and add DAP and target +swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_DAP_ID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap +$_TARGETNAME configure -rtos Zephyr + + +# Soft reset configuration (?) +cortex_m reset_config sysresetreq +gdb_breakpoint_override none + +gdb_report_register_access_error enable + +gdb_target_description enable +# Post init commands +lappend post_init_commands {echo "Open OCD for CC35x1e device successfully initialized."} diff --git a/boards/ti/lpf3_common/Kconfig b/boards/ti/lpf3_common/Kconfig new file mode 100644 index 000000000000..39567ab195c7 --- /dev/null +++ b/boards/ti/lpf3_common/Kconfig @@ -0,0 +1,31 @@ +# Copyright (c) 2024 Texas Instruments Incorporated +# +# SPDX-License-Identifier: Apache-2.0 + +config TI_MCUMGR_BT_OTA_DFU + bool "MCUMgr OTA DFU over Bluetooth" + select NET_BUF + select ZCBOR + select ZEPHYR_ZCBOR_MODULE + select CRC + select MCUMGR + select MCUMGR_TRANSPORT_BT + select MCUMGR_TRANSPORT_BT_REASSEMBLY + select IMG_MANAGER + select MCUMGR_GRP_IMG + select FLASH + select FLASH_MAP + select STREAM_FLASH + imply MCUMGR_GRP_OS + imply MCUMGR_GRP_OS_MCUMGR_PARAMS + imply MCUMGR_GRP_OS_BOOTLOADER_INFO + depends on BT + depends on BT_SMP + depends on BT_PERIPHERAL + depends on BOOTLOADER_MCUBOOT + default n + +config BT_LL_HEAP_SIZE + hex "TI BLE LL Heap Size" + depends on BT + default 0x4000 diff --git a/boards/ti/lpf3_common/Kconfig.defconfig b/boards/ti/lpf3_common/Kconfig.defconfig new file mode 100644 index 000000000000..04a82043650f --- /dev/null +++ b/boards/ti/lpf3_common/Kconfig.defconfig @@ -0,0 +1,105 @@ +# Copyright (c) 2024 Texas Instruments Incorporated +# +# SPDX-License-Identifier: Apache-2.0 + +if TI_MCUMGR_BT_OTA_DFU + config MCUMGR_TRANSPORT_NETBUF_SIZE + default 550 + config BT_L2CAP_TX_MTU + default 65 +endif # TI_MCUMGR_BT_OTA_DFU + +if BT + config ZEPHYR + bool + default y + + config CRYPTO + default y + + config ENTROPY_GENERATOR + default y + + config BT_BUF_EVT_RX_SIZE + default 255 + + config BT_BUF_ACL_RX_SIZE + default 255 + + config BT_BUF_ACL_TX_SIZE + default 255 + + config BT_BUF_CMD_TX_SIZE + default 255 + + config BT_COMPANY_ID + default 0x000D + + choice BT_RECV_CONTEXT + bool + default BT_RECV_WORKQ_BT if BT_MESH + default BT_RECV_WORKQ_SYS + endchoice +endif # BT + +if BT_MESH + config BT_HOST_CRYPTO_PRNG + default n + + config BT_CTLR_CRYPTO + default y + + config BT_HOST_CRYPTO + default y + +if BT_MESH_FRIEND + config BT_MESH_FRIEND_ADV_LATENCY + default 7 +endif # BT_MESH_FRIEND + +if BT_MESH_LOW_POWER + config BT_MESH_LPN_SCAN_LATENCY + default 3 + + config BT_MESH_GATT_PROXY + default n + + config BT_MESH_PRIV_BEACONS + default n + + config BT_MESH_BEACON_ENABLED + default n + + config BT_MESH_RELAY + default n + + config BT_MESH_FRIEND + default n + +endif # BT_MESH_LOW_POWER +endif # BT_MESH + +# Choose non-hardware based RNG +choice RNG_GENERATOR_CHOICE + default XOSHIRO_RANDOM_GENERATOR +endchoice + +# Use CTR DRBG since the entropy driver is not designed to provide continuous RNG +choice CSPRNG_GENERATOR_CHOICE + default CTR_DRBG_CSPRNG_GENERATOR +endchoice + +# By default mbedTLS uses RAM for AES tables, which are too big +if MBEDTLS + config MBEDTLS_AES_ROM_TABLES + default y + config TEST_EXTRA_STACK_SIZE + default 1024 +endif # MBEDTLS + +# Object tracking for semaphores is currently not supported +config OBJ_CORE_SEM + default n + +config TRACING_SEMAPHORE + default n diff --git a/drivers/adc/CMakeLists.txt b/drivers/adc/CMakeLists.txt index 6723094cb4ec..b0fde6ce3bbb 100644 --- a/drivers/adc/CMakeLists.txt +++ b/drivers/adc/CMakeLists.txt @@ -26,8 +26,8 @@ zephyr_library_sources_ifdef(CONFIG_ADC_ADS79XX adc_ads79xx.c) zephyr_library_sources_ifdef(CONFIG_ADC_AMBIQ adc_ambiq.c) zephyr_library_sources_ifdef(CONFIG_ADC_BFLB adc_bflb.c) zephyr_library_sources_ifdef(CONFIG_ADC_CC13XX_CC26XX adc_cc13xx_cc26xx.c) -zephyr_library_sources_ifdef(CONFIG_ADC_CC23X0 adc_cc23x0.c) zephyr_library_sources_ifdef(CONFIG_ADC_CC32XX adc_cc32xx.c) +zephyr_library_sources_ifdef(CONFIG_ADC_CC35XX adc_cc35xx.c) zephyr_library_sources_ifdef(CONFIG_ADC_CH32V00X adc_ch32v00x.c) zephyr_library_sources_ifdef(CONFIG_ADC_EMUL adc_emul.c) zephyr_library_sources_ifdef(CONFIG_ADC_ENE_KB106X adc_ene_kb106x.c) @@ -43,6 +43,7 @@ zephyr_library_sources_ifdef(CONFIG_ADC_INFINEON_SAR adc_infineon_sar.c) zephyr_library_sources_ifdef(CONFIG_ADC_ITE_IT51XXX adc_ite_it51xxx.c) zephyr_library_sources_ifdef(CONFIG_ADC_ITE_IT8XXX2 adc_ite_it8xxx2.c) zephyr_library_sources_ifdef(CONFIG_ADC_LMP90XXX adc_lmp90xxx.c) +zephyr_library_sources_ifdef(CONFIG_ADC_LPF3 adc_lpf3.c) zephyr_library_sources_ifdef(CONFIG_ADC_LTC2451 adc_ltc2451.c) zephyr_library_sources_ifdef(CONFIG_ADC_MAX11102_17 adc_max11102_17.c) zephyr_library_sources_ifdef(CONFIG_ADC_MAX1125X adc_max1125x.c) diff --git a/drivers/adc/Kconfig b/drivers/adc/Kconfig index c0c82f726aeb..37f32c9ab94a 100644 --- a/drivers/adc/Kconfig +++ b/drivers/adc/Kconfig @@ -114,8 +114,8 @@ source "drivers/adc/Kconfig.ambiq" source "drivers/adc/Kconfig.b91" source "drivers/adc/Kconfig.bflb" source "drivers/adc/Kconfig.cc13xx_cc26xx" -source "drivers/adc/Kconfig.cc23x0" source "drivers/adc/Kconfig.cc32xx" +source "drivers/adc/Kconfig.cc35xx" source "drivers/adc/Kconfig.ch32v00x" source "drivers/adc/Kconfig.ene" source "drivers/adc/Kconfig.esp32" @@ -127,6 +127,7 @@ source "drivers/adc/Kconfig.infineon_sar" source "drivers/adc/Kconfig.it51xxx" source "drivers/adc/Kconfig.it8xxx2" source "drivers/adc/Kconfig.lmp90xxx" +source "drivers/adc/Kconfig.lpf3" source "drivers/adc/Kconfig.ltc2451" source "drivers/adc/Kconfig.max11102_17" source "drivers/adc/Kconfig.max1125x" diff --git a/drivers/adc/Kconfig.cc23x0 b/drivers/adc/Kconfig.cc35xx similarity index 52% rename from drivers/adc/Kconfig.cc23x0 rename to drivers/adc/Kconfig.cc35xx index aecde132b294..1d503e109d6d 100644 --- a/drivers/adc/Kconfig.cc23x0 +++ b/drivers/adc/Kconfig.cc35xx @@ -1,17 +1,15 @@ -# Copyright (c) 2024 BayLibre, SAS # SPDX-License-Identifier: Apache-2.0 -config ADC_CC23X0 - bool "CC23X0 ADC driver" +config ADC_CC35XX + bool "CC35XX ADC driver" default y - depends on DT_HAS_TI_CC23X0_ADC_ENABLED - select PINCTRL + depends on DT_HAS_TI_CC35XX_ADC_ENABLED help - Enable the TI CC23X0 ADC driver. + This option enables the CC35XX ADC driver. -config ADC_CC23X0_DMA_DRIVEN - bool "DMA support for TI CC23X0 ADC devices" - depends on ADC_CC23X0 +config ADC_CC35XX_DMA_DRIVEN + bool "DMA support for TI CC35XX ADC devices" + depends on ADC_CC35XX select DMA help DMA driven mode offloads data transfer tasks from the CPU diff --git a/drivers/adc/Kconfig.lpf3 b/drivers/adc/Kconfig.lpf3 new file mode 100644 index 000000000000..b72c574acb43 --- /dev/null +++ b/drivers/adc/Kconfig.lpf3 @@ -0,0 +1,21 @@ +# Copyright (c) 2025 Texas Instruments Incorporated +# Copyright (c) 2024 BayLibre, SAS +# SPDX-License-Identifier: Apache-2.0 + +config ADC_LPF3 + bool "LPF3 ADC driver" + default y + depends on DT_HAS_TI_LPF3_ADC_ENABLED + select PINCTRL + help + Enable ADC driver for Texas Instruments LPF3 MCUs (CC23x0 and CC27xx). + +config ADC_LPF3_DMA_DRIVEN + bool "DMA support for ADC operation in Texas Instruments LPF3 MCUs (CC23x0 and CC27xx)" + depends on ADC_LPF3 + select DMA + help + DMA driven mode offloads data transfer tasks from the CPU + and requires fewer interrupts to handle the ADC sequence mode. + When DMA mode is used, the ADC internal gain is not compensated + for measurement adjustment. diff --git a/drivers/adc/adc_cc35xx.c b/drivers/adc/adc_cc35xx.c new file mode 100644 index 000000000000..bbafe0e1ba9e --- /dev/null +++ b/drivers/adc/adc_cc35xx.c @@ -0,0 +1,501 @@ +/* + * Copyright (c) 2025 Conclusive Engineering Sp. z o.o. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT ti_cc35xx_adc +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_ADC_CC35XX_DMA_DRIVEN +#include +#include +#include +#endif /* CONFIG_ADC_CC35XX_DMA_DRIVEN */ + +/* Driverlib includes */ +#include +#include +#include + +#define CC35XX_CHAN_COUNT 16 +/* hardware supports MEMCTL0..5 for sequence */ +#define CC35XX_SEQUENCE_MAX 6 + +#define ADC_CONTEXT_USES_KERNEL_TIMER +#include "adc_context.h" + +#define LOG_LEVEL CONFIG_ADC_LOG_LEVEL +LOG_MODULE_REGISTER(adc_cc35xx); + +#define ADC_INT_CHAN_MASK \ + (ADC_INT_MEMRES_00 | ADC_INT_MEMRES_01 | ADC_INT_MEMRES_02 | ADC_INT_MEMRES_03 | \ + ADC_INT_MEMRES_04 | ADC_INT_MEMRES_05 | ADC_INT_MEMRES_06 | ADC_INT_MEMRES_07 | \ + ADC_INT_MEMRES_08 | ADC_INT_MEMRES_09 | ADC_INT_MEMRES_10 | ADC_INT_MEMRES_11 | \ + ADC_INT_MEMRES_12 | ADC_INT_MEMRES_13 | ADC_INT_MEMRES_14 | ADC_INT_MEMRES_15) + +#ifdef CONFIG_ADC_CC35XX_DMA_DRIVEN + +struct adc_cc35xx_dma_stream { + const struct device *dev_dma; + uint32_t dma_channel; + struct dma_config dma_cfg; + struct dma_block_config blk_cfg; +}; +#endif /* CONFIG_ADC_CC35XX_DMA_DRIVEN */ + +struct adc_cc35xx_data { + struct adc_context ctx; + const struct device *dev; + uint16_t *buffer; + uint16_t *repeat_buffer; + uint32_t channels; + struct { + int vref; + } channel_config[CC35XX_CHAN_COUNT]; + size_t active_channels; + uint32_t clkdiv; +#ifdef CONFIG_ADC_CC35XX_DMA_DRIVEN + struct adc_cc35xx_dma_stream dma; +#endif /* CONFIG_ADC_CC35XX_DMA_DRIVEN */ +}; + +struct adc_cc35xx_cfg { + mem_addr_t base; + const struct pinctrl_dev_config *pcfg; + uint32_t clkdiv; + uint16_t sample_period; +}; + +#ifdef CONFIG_ADC_CC35XX_DMA_DRIVEN +static int adc_cc35xx_fifo_enable(const struct device *dev, bool enable) +{ + const struct adc_cc35xx_cfg *config = dev->config; + uint32_t ctl2_reg = sys_read32(config->base + ADC_O_CTL2); + + if (enable) { + ctl2_reg |= ADC_CTL2_FIFOEN_ENABLE; + } else { + ctl2_reg &= ~ADC_CTL2_FIFOEN_ENABLE; + } + sys_write32(ctl2_reg, config->base + ADC_O_CTL2); + + return 0; +} + +static void adc_context_start_sampling(struct adc_context *ctx) +{ + struct adc_cc35xx_data *data = CONTAINER_OF(ctx, struct adc_cc35xx_data, ctx); + uint32_t channel_irq = 0; + + const struct device *dev = data->dev; + const struct adc_cc35xx_cfg *config = data->dev->config; + mem_addr_t irq_set_reg; + int ret; + + data->channels = ctx->sequence.channels; + data->repeat_buffer = data->buffer; + /* wait for interrupt from the last configured channel, so we get + * single interrupt once all channels are done + */ + channel_irq = ADC_INT_MEMRES_00 << (data->active_channels - 1); + ADCClearInterrupt(ADC_INT_UVIFG); + ADCDisableConversion(); + + data->dma.blk_cfg.source_address = config->base + ADC_O_FIFODATA; + data->dma.blk_cfg.dest_address = (uint32_t)data->buffer; + data->dma.blk_cfg.block_size = sizeof(uint16_t) * data->active_channels; + + sys_write32(ADC_INT_CHAN_MASK, ADC_BASE + ADC_O_INTEVT2CLR); + ret = dma_config(data->dma.dev_dma, data->dma.dma_channel, &data->dma.dma_cfg); + if (ret) { + LOG_ERR("Error configuring DMA for ADC, error: %d", ret); + return; + } + ADCEnableDmaTrigger(); + ADCEnableInterrupt(ADC_INT_DMADONE); + ret = dma_start(data->dma.dev_dma, data->dma.dma_channel); + if (ret != 0) { + LOG_ERR("Error start DMA for ADC, error: %d", ret); + goto dma_error; + } + channel_irq |= ADC_INT_DMADONE; + irq_set_reg = ADC_BASE + ADC_O_INTEVT2BM; + + sys_write32(channel_irq, irq_set_reg); + adc_cc35xx_fifo_enable(dev, true); + + ADCEnableConversion(); + ADCStartConversion(); + + return; +dma_error: + ADCDisableInterrupt(ADC_INT_DMADONE); + ADCDisableDmaTrigger(); +} + +static void adc_context_stop_sampling(struct adc_context *ctx) +{ + struct adc_cc35xx_data *data = CONTAINER_OF(ctx, struct adc_cc35xx_data, ctx); + const struct device *dev = data->dev; + + ADCStopConversion(); + ADCDisableConversion(); + + dma_stop(data->dma.dev_dma, data->dma.dma_channel); + ADCDisableInterrupt(ADC_INT_DMADONE); + ADCDisableDmaTrigger(); + + adc_cc35xx_fifo_enable(dev, false); +} + +#else +static void adc_context_start_sampling(struct adc_context *ctx) +{ + struct adc_cc35xx_data *data = CONTAINER_OF(ctx, struct adc_cc35xx_data, ctx); + uint32_t channel_irq = 0; + + data->channels = ctx->sequence.channels; + data->repeat_buffer = data->buffer; + /* Wait for interrupt from the last configured channel, so we get + * single interrupt once all channels are done + */ + channel_irq = ADC_INT_MEMRES_00 << (data->active_channels - 1); + + ADCEnableConversion(); + ADCStartConversion(); + ADCEnableInterrupt(channel_irq); +} +#endif /* CONFIG_ADC_CC35XX_DMA_DRIVEN */ + +static void adc_context_update_buffer_pointer(struct adc_context *ctx, bool repeat) +{ + struct adc_cc35xx_data *data = CONTAINER_OF(ctx, struct adc_cc35xx_data, ctx); + + if (repeat) { + data->buffer = data->repeat_buffer; + } else { + data->buffer += data->active_channels; + } +} + +static int adc_cc35xx_get_reference(enum adc_reference zephyr_reference) +{ + switch (zephyr_reference) { + case ADC_REF_VDD_1: + return ADC_VDDA_REFERENCE; + + case ADC_REF_INTERNAL: + return ADC_INTERNAL_REFERENCE; + + case ADC_REF_EXTERNAL0: + return ADC_EXTERNAL_REFERENCE; + + default: + return -1; + } +} + +static int adc_cc35xx_channel_setup(const struct device *dev, + const struct adc_channel_cfg *channel_cfg) +{ + struct adc_cc35xx_data *data = dev->data; + const uint8_t ch = channel_cfg->channel_id; + int vref; + + if (ch >= CC35XX_CHAN_COUNT) { + LOG_ERR("Channel %d is not available, hardware max channel is %d", ch, + CC35XX_CHAN_COUNT); + return -EINVAL; + } + + if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) { + LOG_ERR("Acquisition time is not valid"); + return -EINVAL; + } + + if (channel_cfg->differential) { + LOG_ERR("Differential channels are not supported"); + return -EINVAL; + } + + if (channel_cfg->gain != ADC_GAIN_1) { + LOG_ERR("Gain is not valid"); + return -EINVAL; + } + + vref = adc_cc35xx_get_reference(channel_cfg->reference); + if (vref == -1) { + LOG_ERR("Reference is not valid"); + return -EINVAL; + } + + data->channel_config[ch].vref = vref; + + return 0; +} + +static int adc_cc35xx_read(const struct device *dev, const struct adc_sequence *sequence, + bool asynchronous, struct k_poll_signal *sig) +{ + struct adc_cc35xx_data *data = dev->data; + const struct adc_cc35xx_cfg *config = dev->config; + size_t exp_size; + int ret; + + if (sequence->resolution != 12) { + LOG_ERR("Only 12 bit resolution is supported, requested resolution is %d", + sequence->resolution); + return -EINVAL; + } + +#ifndef CONFIG_ADC_CC35XX_DMA_DRIVEN + ADCDisableConversion(); +#endif /* CONFIG_ADC_CC35XX_DMA_DRIVEN */ + + data->active_channels = 0; + for (int ch = 0; ch < CC35XX_CHAN_COUNT; ++ch) { + if (sequence->channels & BIT(ch)) { + ADCSetInput(data->channel_config[ch].vref, ch, ADC_FULL_SCALE_RANGE_0V0_3V3, + data->active_channels); + data->active_channels++; + } + } + exp_size = data->active_channels * sizeof(uint16_t); + + if (data->active_channels == 0) { + LOG_ERR("No channels selected for conversion"); + return -EINVAL; + } + + if (data->active_channels > CC35XX_SEQUENCE_MAX) { + LOG_ERR("Cannot convert more than 6 channels in a sequence"); + return -ERANGE; + } + + if (sequence->buffer_size < exp_size) { + LOG_ERR("Required buffer size is %u, but %u got", exp_size, sequence->buffer_size); + return -ENOMEM; + } + + data->buffer = sequence->buffer; + + ADCSetMemctlRange(0, data->active_channels - 1); + ADCSetSampleDuration(data->clkdiv, config->sample_period); + ADCSetSamplingMode(ADC_SAMPLE_MODE_AUTO); + ADCSetSequence(ADC_SEQUENCE_SEQUENCE); + ADCSetTriggerSource(ADC_TRIGGER_SOURCE_SOFTWARE); + + adc_context_lock(&data->ctx, asynchronous, sig); + adc_context_start_read(&data->ctx, sequence); + ret = adc_context_wait_for_completion(&data->ctx); + adc_context_release(&data->ctx, ret); + + return ret; +} + +static int adc_cc35xx_read_sync(const struct device *dev, const struct adc_sequence *sequence) +{ + return adc_cc35xx_read(dev, sequence, false, NULL); +} + +#ifdef CONFIG_ADC_ASYNC +static int adc_cc35xx_read_async(const struct device *dev, const struct adc_sequence *sequence, + struct k_poll_signal *async) +{ + return adc_cc35xx_read(dev, sequence, true, async); +} +#endif /* CONFIG_ADC_ASYNC */ + +#ifdef CONFIG_ADC_CC35XX_DMA_DRIVEN +static void adc_cc35xx_isr(const struct device *dev) +{ + uint32_t irq_status = ADCMaskedInterruptStatus(); + struct adc_cc35xx_data *data = dev->data; + + ADCDisableConversion(); + ADCStopConversion(); + + if (irq_status & ADC_INT_UVIFG) { + ADCClearInterrupt(ADC_INT_UVIFG); + adc_context_stop_sampling(&data->ctx); + adc_context_start_sampling(&data->ctx); + + return; + } + + if (irq_status & ADC_INT_DMADONE) { + ADCDisableInterrupt(ADC_INT_DMADONE); + ADCClearInterrupt(ADC_INT_DMADONE); + + ADCStopConversion(); + ADCDisableConversion(); + ADCDisableInterrupt(ADC_INT_DMADONE); + ADCDisableDmaTrigger(); + + adc_cc35xx_fifo_enable(dev, false); + + adc_context_on_sampling_done(&data->ctx, data->dev); + } + + if (irq_status & ADC_INT_CHAN_MASK) { + + ADCDisableInterrupt(ADC_INT_CHAN_MASK); + ADCClearInterrupt(ADC_INT_CHAN_MASK); + } +} +#else +static void adc_cc35xx_isr(const struct device *dev) +{ + const struct adc_cc35xx_cfg *config = dev->config; + struct adc_cc35xx_data *data = dev->data; + mem_addr_t reg; + uint32_t irq_status = ADCMaskedInterruptStatus(); + + if (irq_status & ADC_INT_UVIFG) { + ADCClearInterrupt(ADC_INT_UVIFG); + + return; + } + + if (irq_status & ADC_INT_CHAN_MASK) { + for (unsigned int chan = 0; chan < data->active_channels; chan++) { + reg = config->base + ADC_O_MEMRES_0 + 4 * chan; + *(data->buffer + chan) = sys_read16(reg); + } + + ADCDisableInterrupt(ADC_INT_CHAN_MASK); + ADCClearInterrupt(ADC_INT_CHAN_MASK); + ADCStopConversion(); + ADCDisableConversion(); + adc_context_on_sampling_done(&data->ctx, dev); + } +} +#endif /* CONFIG_ADC_CC35XX_DMA_DRIVEN */ + +/** + * Translate integer divide value user passes in DTS to register value + */ +static uint32_t adc_cc35xx_sclkdiv_reg_val(int div) +{ + switch (div) { + case 1: + return ADC_CLOCK_DIVIDER_1; + case 2: + return ADC_CLOCK_DIVIDER_2; + case 4: + return ADC_CLOCK_DIVIDER_4; + case 8: + return ADC_CLOCK_DIVIDER_8; + case 16: + return ADC_CLOCK_DIVIDER_16; + case 24: + return ADC_CLOCK_DIVIDER_24; + case 32: + return ADC_CLOCK_DIVIDER_32; + case 48: + return ADC_CLOCK_DIVIDER_48; + default: + __ASSERT(0, "Invalid ADC clock divider passed"); + return ADC_CLOCK_DIVIDER_1; + } +} + +static int adc_cc35xx_init(const struct device *dev) +{ + struct adc_cc35xx_data *data = dev->data; + const struct adc_cc35xx_cfg *config = dev->config; + int ret; + + data->dev = dev; + + LOG_DBG("Initializing..."); + + ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); + if (ret < 0) { + LOG_ERR("Applying ADC pinctrl state failed"); + return ret; + } + + data->clkdiv = adc_cc35xx_sclkdiv_reg_val(config->clkdiv); + ADCSetSamplingClk(ADC_SAMPLE_CLK_SOC_CLK); + ADCDisableInterrupt(ADC_INT_ALL); + sys_write32(ADC_CLKCFG_EN, config->base + ADC_O_CLKCFG); + IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), adc_cc35xx_isr, + DEVICE_DT_INST_GET(0), 0); + irq_enable(DT_INST_IRQN(0)); + +#ifdef CONFIG_ADC_CC35XX_DMA_DRIVEN + if (data->dma.dev_dma != NULL) { + if (!device_is_ready(data->dma.dev_dma)) { + return -ENODEV; + } + data->dma.blk_cfg.source_address = config->base + ADC_O_FIFODATA; + data->dma.dma_cfg.head_block = &data->dma.blk_cfg; + data->dma.dma_cfg.user_data = (void *)data; + } +#endif /* CONFIG_ADC_CC35XX_DMA_DRIVEN */ + + adc_context_unlock_unconditionally(&data->ctx); + + return 0; +} + +static DEVICE_API(adc, cc35xx_driver_api) = { + .channel_setup = adc_cc35xx_channel_setup, + .read = adc_cc35xx_read_sync, +#ifdef CONFIG_ADC_ASYNC + .read_async = adc_cc35xx_read_async, +#endif + .ref_internal = DT_INST_PROP(0, vref_internal_mv), +}; + +#ifdef CONFIG_ADC_CC35XX_DMA_DRIVEN +#define ADC_CC35XX_DMA_CHANNEL_INIT(n, dir, src_burst, dst_burst) \ + .dev_dma = DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_IDX(n, 0)), \ + .dma_channel = DT_INST_DMAS_CELL_BY_IDX(n, 0, channel), \ + .dma_cfg = { \ + .dma_slot = DT_INST_DMAS_CELL_BY_IDX(n, 0, channel_config), \ + .channel_direction = PERIPHERAL_TO_MEMORY, \ + .source_data_size = sizeof(uint32_t), \ + .dest_data_size = sizeof(uint32_t), \ + .source_burst_length = src_burst, \ + .dest_burst_length = dst_burst, \ + .block_count = 1, \ + }, + +#define ADC_CC35XX_DMA_CHANNEL(n, dir, src_burst, dst_burst) \ + .dma = {COND_CODE_1(DT_INST_NODE_HAS_PROP(n, dmas), \ + (ADC_CC35XX_DMA_CHANNEL_INIT(n, dir, src_burst, dst_burst)), (NULL))}, +#else +#define ADC_CC35XX_DMA_CHANNEL(n, dir, src_burst, dst_burst) +#endif + +#define CC35XX_ADC_INIT(n) \ + PINCTRL_DT_INST_DEFINE(n); \ + static const struct adc_cc35xx_cfg adc_cc35xx_cfg_##n = { \ + .base = DT_INST_REG_ADDR(n), \ + .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \ + .clkdiv = DT_INST_PROP(n, clkdiv), \ + .sample_period = DT_INST_PROP(n, sample_period), \ + }; \ + static struct adc_cc35xx_data adc_cc35xx_data_##n = { \ + ADC_CONTEXT_INIT_TIMER(adc_cc35xx_data_##n, ctx), \ + ADC_CONTEXT_INIT_LOCK(adc_cc35xx_data_##n, ctx), \ + ADC_CONTEXT_INIT_SYNC(adc_cc35xx_data_##n, ctx), \ + ADC_CC35XX_DMA_CHANNEL(n, rx, 1, 1)}; \ + DEVICE_DT_INST_DEFINE(n, &adc_cc35xx_init, NULL, &adc_cc35xx_data_##n, \ + &adc_cc35xx_cfg_##n, POST_KERNEL, CONFIG_ADC_INIT_PRIORITY, \ + &cc35xx_driver_api); + +DT_INST_FOREACH_STATUS_OKAY(CC35XX_ADC_INIT) diff --git a/drivers/adc/adc_cc23x0.c b/drivers/adc/adc_lpf3.c similarity index 52% rename from drivers/adc/adc_cc23x0.c rename to drivers/adc/adc_lpf3.c index b235e0a321de..e910c86abebd 100644 --- a/drivers/adc/adc_cc23x0.c +++ b/drivers/adc/adc_lpf3.c @@ -1,13 +1,14 @@ /* + * Copyright (c) 2025 Texas Instruments Incorporated * Copyright (c) 2024 BayLibre, SAS * * SPDX-License-Identifier: Apache-2.0 */ -#define DT_DRV_COMPAT ti_cc23x0_adc +#define DT_DRV_COMPAT ti_lpf3_adc #include -LOG_MODULE_REGISTER(adc_cc23x0, CONFIG_ADC_LOG_LEVEL); +LOG_MODULE_REGISTER(adc_lpf3, CONFIG_ADC_LOG_LEVEL); #include #include @@ -15,7 +16,6 @@ LOG_MODULE_REGISTER(adc_cc23x0, CONFIG_ADC_LOG_LEVEL); #include #include #include -#include #include #include @@ -27,60 +27,68 @@ LOG_MODULE_REGISTER(adc_cc23x0, CONFIG_ADC_LOG_LEVEL); #define ADC_CONTEXT_USES_KERNEL_TIMER #include "adc_context.h" -#define ADC_CC23X0_CH_UNDEF 0xff -#define ADC_CC23X0_CH_COUNT 16 -#define ADC_CC23X0_CH_MAX (ADC_CC23X0_CH_COUNT - 1) +#define ADC_LPF3_CH_UNDEF 0xff +#define ADC_LPF3_CH_COUNT 16 +#define ADC_LPF3_CH_MAX (ADC_LPF3_CH_COUNT - 1) /* ADC provides four result storage registers */ -#define ADC_CC23X0_MEM_COUNT 4 -#define ADC_CC23X0_MEM_MAX (ADC_CC23X0_MEM_COUNT - 1) +#define ADC_LPF3_MEM_COUNT 4 +#define ADC_LPF3_MEM_MAX (ADC_LPF3_MEM_COUNT - 1) -#define ADC_CC23X0_MAX_CYCLES 1023 +#define ADC_LPF3_MAX_CYCLES 1023 -#ifdef CONFIG_ADC_CC23X0_DMA_DRIVEN -#define ADC_CC23X0_REG_GET(offset) (ADC_BASE + (offset)) -#define ADC_CC23X0_INT_MASK ADC_INT_DMADONE +#ifdef CONFIG_ADC_LPF3_DMA_DRIVEN +#define ADC_LPF3_REG_GET(offset) (ADC_BASE + (offset)) +#define ADC_LPF3_INT_MASK ADC_INT_DMADONE #else -#define ADC_CC23X0_INT_MASK (ADC_INT_MEMRES_00 | \ - ADC_INT_MEMRES_01 | \ - ADC_INT_MEMRES_02 | \ - ADC_INT_MEMRES_03) +#define ADC_LPF3_INT_MASK \ + (ADC_INT_MEMRES_00 | ADC_INT_MEMRES_01 | ADC_INT_MEMRES_02 | ADC_INT_MEMRES_03) #endif -#define ADC_CC23X0_INT_MEMRES(i) (ADC_INT_MEMRES_00 << (i)) +#define ADC_LPF3_INT_MEMRES(i) (ADC_INT_MEMRES_00 << (i)) -#define ADC_CC23X0_MEMCTL(base, i) HWREG((base) + ADC_O_MEMCTL0 + sizeof(uint32_t) * (i)) +#define ADC_LPF3_MEMCTL(base, i) HWREG((base) + ADC_O_MEMCTL0 + sizeof(uint32_t) * (i)) static const uint8_t clk_dividers[] = {1, 2, 4, 8, 16, 24, 32, 48}; -struct adc_cc23x0_config { +struct adc_lpf3_config { const struct pinctrl_dev_config *pincfg; void (*irq_cfg_func)(void); uint32_t base; -#ifdef CONFIG_ADC_CC23X0_DMA_DRIVEN +#ifdef CONFIG_ADC_LPF3_DMA_DRIVEN const struct device *dma_dev; uint8_t dma_channel; uint8_t dma_trigsrc; #endif }; -struct adc_cc23x0_data { +#ifdef CONFIG_PM_DEVICE +struct adc_lpf3_mem_cfg { + bool configured; + uint8_t ch; + uint32_t ref; + uint32_t clkdiv_field; + uint16_t clk_cycles; +}; +#endif + +struct adc_lpf3_data { struct adc_context ctx; const struct device *dev; uint32_t res; - uint32_t ref_volt[ADC_CC23X0_CH_COUNT]; + uint32_t ref_volt[ADC_LPF3_CH_COUNT]; uint16_t clk_cycles; uint8_t clk_div; - uint8_t ch_sel[ADC_CC23X0_MEM_COUNT]; + uint8_t ch_sel[ADC_LPF3_MEM_COUNT]; uint8_t ch_count; uint8_t mem_index; uint16_t *buffer; #ifdef CONFIG_PM_DEVICE - bool configured; + struct adc_lpf3_mem_cfg mem_cfg[ADC_LPF3_MEM_COUNT]; #endif }; -static inline void adc_cc23x0_pm_policy_state_lock_get(void) +static inline void adc_lpf3_pm_policy_state_lock_get(void) { #ifdef CONFIG_PM_DEVICE pm_policy_state_lock_get(PM_STATE_RUNTIME_IDLE, PM_ALL_SUBSTATES); @@ -88,7 +96,7 @@ static inline void adc_cc23x0_pm_policy_state_lock_get(void) #endif } -static inline void adc_cc23x0_pm_policy_state_lock_put(void) +static inline void adc_lpf3_pm_policy_state_lock_put(void) { #ifdef CONFIG_PM_DEVICE pm_policy_state_lock_put(PM_STATE_STANDBY, PM_ALL_SUBSTATES); @@ -98,12 +106,12 @@ static inline void adc_cc23x0_pm_policy_state_lock_put(void) static void adc_context_start_sampling(struct adc_context *ctx) { - struct adc_cc23x0_data *data = CONTAINER_OF(ctx, struct adc_cc23x0_data, ctx); -#ifdef CONFIG_ADC_CC23X0_DMA_DRIVEN - const struct adc_cc23x0_config *cfg = data->dev->config; + struct adc_lpf3_data *data = CONTAINER_OF(ctx, struct adc_lpf3_data, ctx); +#ifdef CONFIG_ADC_LPF3_DMA_DRIVEN + const struct adc_lpf3_config *cfg = data->dev->config; struct dma_block_config block_cfg = { - .source_address = ADC_CC23X0_REG_GET(ADC_O_MEMRES0), + .source_address = ADC_LPF3_REG_GET(ADC_O_MEMRES0), .dest_address = (uint32_t)(data->buffer), .source_addr_adj = DMA_ADDR_ADJ_INCREMENT, .dest_addr_adj = DMA_ADDR_ADJ_INCREMENT, @@ -118,57 +126,59 @@ static void adc_context_start_sampling(struct adc_context *ctx) .source_data_size = sizeof(uint32_t), .dest_data_size = sizeof(*data->buffer), .source_burst_length = block_cfg.block_size, + .dest_burst_length = block_cfg.block_size, .dma_callback = NULL, .user_data = NULL, }; int ret; - ret = pm_device_runtime_get(cfg->dma_dev); - if (ret) { - LOG_ERR("Failed to resume DMA (%d)", ret); - return; - } - ret = dma_config(cfg->dma_dev, cfg->dma_channel, &dma_cfg); if (ret) { LOG_ERR("Failed to configure DMA (%d)", ret); return; } - ADCEnableDMATrigger(); + ADCEnableDmaTrigger(); dma_start(cfg->dma_dev, cfg->dma_channel); #else data->mem_index = 0; #endif + adc_lpf3_pm_policy_state_lock_get(); + + /* Set trigger source to software */ + ADCSetTriggerSource(ADC_TRIGGER_SOURCE_SOFTWARE); + + /* Set sampling mode to automatic, to use the sample duration configured + * with ADCSetSampleDuration() + */ + ADCSetSamplingMode(ADC_SAMPLE_MODE_AUTO); - adc_cc23x0_pm_policy_state_lock_get(); + /* Enable conversion. The ADC will wait for the software trigger */ + ADCEnableConversion(); - ADCManualTrigger(); + ADCStartConversion(); } static void adc_context_update_buffer_pointer(struct adc_context *ctx, bool repeat) { - struct adc_cc23x0_data *data = CONTAINER_OF(ctx, struct adc_cc23x0_data, ctx); + struct adc_lpf3_data *data = CONTAINER_OF(ctx, struct adc_lpf3_data, ctx); if (!repeat) { data->buffer += data->ch_count; } } -static void adc_cc23x0_isr(const struct device *dev) +static void adc_lpf3_isr(const struct device *dev) { - struct adc_cc23x0_data *data = dev->data; -#ifndef CONFIG_ADC_CC23X0_DMA_DRIVEN + struct adc_lpf3_data *data = dev->data; +#ifndef CONFIG_ADC_LPF3_DMA_DRIVEN uint32_t adc_val; uint8_t ch; #endif -#ifdef CONFIG_ADC_CC23X0_DMA_DRIVEN - const struct adc_cc23x0_config *cfg = dev->config; - int ret; - +#ifdef CONFIG_ADC_LPF3_DMA_DRIVEN /* * In DMA mode, do not compensate for the ADC internal gain with * ADCAdjustValueForGain() function. To perform this compensation, @@ -177,14 +187,7 @@ static void adc_cc23x0_isr(const struct device *dev) */ ADCClearInterrupt(ADC_INT_DMADONE); LOG_DBG("DMA done"); - - ret = pm_device_runtime_put(cfg->dma_dev); - if (ret) { - LOG_ERR("Failed to suspend DMA (%d)", ret); - return; - } - - adc_cc23x0_pm_policy_state_lock_put(); + adc_lpf3_pm_policy_state_lock_put(); adc_context_on_sampling_done(&data->ctx, dev); #else /* @@ -197,41 +200,46 @@ static void adc_cc23x0_isr(const struct device *dev) * Both adjustment offset and adjustment gain depend on reference source. * Internal gain is used for measurement compensation. */ - adc_val = ADCAdjustValueForGain(ADCReadResultNonBlocking(data->mem_index), - data->res, + adc_val = ADCAdjustValueForGain(ADCReadResultNonBlocking(data->mem_index), data->res, ADCGetAdjustmentGain(data->ref_volt[ch])); data->buffer[data->mem_index] = adc_val; - ADCClearInterrupt(ADC_CC23X0_INT_MEMRES(data->mem_index)); + ADCClearInterrupt(ADC_LPF3_INT_MEMRES(data->mem_index)); LOG_DBG("Mem %u, Ch %u, Val %d", data->mem_index, ch, adc_val); if (++data->mem_index < data->ch_count) { + /* Make sure conversion is disabled to allow configuration changes */ + ADCDisableConversion(); + /* Set adjustment offset for the next channel */ ch = data->ch_sel[data->mem_index]; ADCSetAdjustmentOffset(data->ref_volt[ch]); LOG_DBG("Next Ch %u", ch); - /* Trigger next conversion */ - ADCManualTrigger(); + /* Enable conversion. ADC will wait for trigger. */ + ADCEnableConversion(); + + /* Start conversion. No need to call ADCStopConversion() since that is + * only needed in manual sampling mode. + */ + ADCStartConversion(); } else { - adc_cc23x0_pm_policy_state_lock_put(); + adc_lpf3_pm_policy_state_lock_put(); adc_context_on_sampling_done(&data->ctx, dev); } #endif } -static int adc_cc23x0_read_common(const struct device *dev, - const struct adc_sequence *sequence, - bool asynchronous, - struct k_poll_signal *sig) +static int adc_lpf3_read_common(const struct device *dev, const struct adc_sequence *sequence, + bool asynchronous, struct k_poll_signal *sig) { -#ifndef CONFIG_ADC_CC23X0_DMA_DRIVEN - const struct adc_cc23x0_config *cfg = dev->config; +#ifndef CONFIG_ADC_LPF3_DMA_DRIVEN + const struct adc_lpf3_config *cfg = dev->config; #endif - struct adc_cc23x0_data *data = dev->data; + struct adc_lpf3_data *data = dev->data; uint32_t bitmask; - uint8_t ch_start = ADC_CC23X0_CH_UNDEF; + uint8_t ch_start = ADC_LPF3_CH_UNDEF; uint8_t mem_index = 0; size_t exp_size; int ret; @@ -253,6 +261,9 @@ static int adc_cc23x0_read_common(const struct device *dev, return -EINVAL; } + /* Make sure conversion is disabled to allow configuration changes */ + ADCDisableConversion(); + ADCSetResolution(data->res); /* Set sequence */ @@ -272,16 +283,16 @@ static int adc_cc23x0_read_common(const struct device *dev, /* Set adjustment offset for this channel */ ADCSetAdjustmentOffset(data->ref_volt[ch_start]); -#ifdef CONFIG_ADC_CC23X0_DMA_DRIVEN - ADCEnableDMAInterrupt(ADC_CC23X0_INT_MEMRES(0)); +#ifdef CONFIG_ADC_LPF3_DMA_DRIVEN + HWREG(ADC_BASE + ADC_O_IMASK2) |= ADC_LPF3_INT_MEMRES(0); #endif - } else if (data->ch_count <= ADC_CC23X0_MEM_COUNT) { - for (i = 0; i < ADC_CC23X0_CH_COUNT; i++) { + } else if (data->ch_count <= ADC_LPF3_MEM_COUNT) { + for (i = 0; i < ADC_LPF3_CH_COUNT; i++) { if (!(bitmask & BIT(i))) { continue; } - if (ch_start == ADC_CC23X0_CH_UNDEF) { + if (ch_start == ADC_LPF3_CH_UNDEF) { ch_start = i; } @@ -290,9 +301,9 @@ static int adc_cc23x0_read_common(const struct device *dev, /* Set input channel */ ADCSetInput(data->ref_volt[i], i, mem_index); -#ifndef CONFIG_ADC_CC23X0_DMA_DRIVEN +#ifndef CONFIG_ADC_LPF3_DMA_DRIVEN /* Set trigger policy so next conversion requires a trigger */ - ADC_CC23X0_MEMCTL(cfg->base, mem_index) |= ADC_MEMCTL0_TRG; + ADC_LPF3_MEMCTL(cfg->base, mem_index) |= ADC_MEMCTL0_TRG; #endif mem_index++; @@ -305,15 +316,15 @@ static int adc_cc23x0_read_common(const struct device *dev, /* Set adjustment offset for the first channel */ ADCSetAdjustmentOffset(data->ref_volt[ch_start]); -#ifdef CONFIG_ADC_CC23X0_DMA_DRIVEN +#ifdef CONFIG_ADC_LPF3_DMA_DRIVEN /* * DMA transfer will be triggered when the last storage register * of the sequence is loaded with a new conversion result */ - ADCEnableDMAInterrupt(ADC_CC23X0_INT_MEMRES(mem_index - 1)); + HWREG(ADC_BASE + ADC_O_IMASK2) |= ADC_LPF3_INT_MEMRES(mem_index - 1); #endif } else { - LOG_ERR("Too many channels in the sequence, max %u", ADC_CC23X0_MEM_COUNT); + LOG_ERR("Too many channels in the sequence, max %u", ADC_LPF3_MEM_COUNT); return -EINVAL; } @@ -338,22 +349,20 @@ static int adc_cc23x0_read_common(const struct device *dev, return ret; } -static int adc_cc23x0_read(const struct device *dev, - const struct adc_sequence *sequence) +static int adc_lpf3_read(const struct device *dev, const struct adc_sequence *sequence) { - return adc_cc23x0_read_common(dev, sequence, false, NULL); + return adc_lpf3_read_common(dev, sequence, false, NULL); } #ifdef CONFIG_ADC_ASYNC -static int adc_cc23x0_read_async(const struct device *dev, - const struct adc_sequence *sequence, - struct k_poll_signal *async) +static int adc_lpf3_read_async(const struct device *dev, const struct adc_sequence *sequence, + struct k_poll_signal *async) { - return adc_cc23x0_read_common(dev, sequence, true, async); + return adc_lpf3_read_common(dev, sequence, true, async); } #endif -static uint32_t adc_cc23x0_clkdiv_to_field(uint8_t clk_div) +static uint32_t adc_lpf3_clkdiv_to_field(uint8_t clk_div) { switch (clk_div) { case 2: @@ -375,12 +384,12 @@ static uint32_t adc_cc23x0_clkdiv_to_field(uint8_t clk_div) } } -static int adc_cc23x0_calc_clk_cfg(uint32_t acq_time_ns, uint8_t *clk_div, uint16_t *clk_cycles) +static int adc_lpf3_calc_clk_cfg(uint32_t acq_time_ns, uint8_t *clk_div, uint16_t *clk_cycles) { uint32_t samp_duration_ns; uint32_t min_delta_res = UINT32_MAX; uint32_t delta_res; - uint16_t min_cycles = ADC_CC23X0_MAX_CYCLES; + uint16_t min_cycles = ADC_LPF3_MAX_CYCLES; uint16_t cycles; uint8_t divider; float clock_period_ns; @@ -393,7 +402,7 @@ static int adc_cc23x0_calc_clk_cfg(uint32_t acq_time_ns, uint8_t *clk_div, uint1 /* Iterate through each divider */ ARRAY_FOR_EACH(clk_dividers, i) { divider = clk_dividers[i]; - clock_period_ns = 1.0E9 * divider / TI_CC23X0_DT_CPU_CLK_FREQ_HZ; + clock_period_ns = 1.0E9 * divider / TI_CC23X0_CC27XX_DT_CPU_CLK_FREQ_HZ; /* Calculate the number of cycles needed to meet or exceed acq_time_ns */ cycles = DIV_ROUND_UP(acq_time_ns, clock_period_ns); @@ -409,8 +418,8 @@ static int adc_cc23x0_calc_clk_cfg(uint32_t acq_time_ns, uint8_t *clk_div, uint1 *clk_div = divider; *clk_cycles = cycles; - LOG_DBG("Divider: %u, Cycles: %u, Actual sample duration: %u ns", - divider, cycles, samp_duration_ns); + LOG_DBG("Divider: %u, Cycles: %u, Actual sample duration: %u ns", divider, + cycles, samp_duration_ns); } } @@ -422,10 +431,10 @@ static int adc_cc23x0_calc_clk_cfg(uint32_t acq_time_ns, uint8_t *clk_div, uint1 return 0; } -static int adc_cc23x0_channel_setup(const struct device *dev, - const struct adc_channel_cfg *channel_cfg) +static int adc_lpf3_channel_setup(const struct device *dev, + const struct adc_channel_cfg *channel_cfg) { - struct adc_cc23x0_data *data = dev->data; + struct adc_lpf3_data *data = dev->data; const uint8_t ch = channel_cfg->channel_id; uint32_t ref; uint32_t acq_time_ns; @@ -435,8 +444,8 @@ static int adc_cc23x0_channel_setup(const struct device *dev, LOG_DBG("Channel %u", ch); - if (ch > ADC_CC23X0_CH_MAX) { - LOG_ERR("Channel %u is not supported, max %u", ch, ADC_CC23X0_CH_MAX); + if (ch > ADC_LPF3_CH_MAX) { + LOG_ERR("Channel %u is not supported, max %u", ch, ADC_LPF3_CH_MAX); return -EINVAL; } @@ -476,7 +485,7 @@ static int adc_cc23x0_channel_setup(const struct device *dev, break; case ADC_ACQ_TIME_MICROSECONDS: acq_time_ns = 1000 * (uint16_t)ADC_ACQ_TIME_VALUE(channel_cfg->acquisition_time); - ret = adc_cc23x0_calc_clk_cfg(acq_time_ns, &clk_div, &clk_cycles); + ret = adc_lpf3_calc_clk_cfg(acq_time_ns, &clk_div, &clk_cycles); if (ret) { LOG_DBG("No valid clock configuration found"); return ret; @@ -484,7 +493,7 @@ static int adc_cc23x0_channel_setup(const struct device *dev, break; case ADC_ACQ_TIME_NANOSECONDS: acq_time_ns = (uint16_t)ADC_ACQ_TIME_VALUE(channel_cfg->acquisition_time); - ret = adc_cc23x0_calc_clk_cfg(acq_time_ns, &clk_div, &clk_cycles); + ret = adc_lpf3_calc_clk_cfg(acq_time_ns, &clk_div, &clk_cycles); if (ret) { LOG_DBG("No valid clock configuration found"); return ret; @@ -495,26 +504,30 @@ static int adc_cc23x0_channel_setup(const struct device *dev, clk_cycles = 1; } +#ifdef CONFIG_PM_DEVICE + data->mem_cfg[data->mem_index].configured = true; + data->mem_cfg[data->mem_index].ch = ch; + data->mem_cfg[data->mem_index].ref = ref; + data->mem_cfg[data->mem_index].clkdiv_field = adc_lpf3_clkdiv_to_field(clk_div); + data->mem_cfg[data->mem_index].clk_cycles = clk_cycles; +#endif + if (!data->clk_cycles) { data->clk_div = clk_div; data->clk_cycles = clk_cycles; - ADCSetSampleDuration(adc_cc23x0_clkdiv_to_field(clk_div), data->clk_cycles); + ADCSetSampleDuration(adc_lpf3_clkdiv_to_field(clk_div), data->clk_cycles); } else if (clk_div != data->clk_div || clk_cycles != data->clk_cycles) { LOG_ERR("Multiple sample durations are not supported"); return -EINVAL; } -#ifdef CONFIG_PM_DEVICE - data->configured = true; -#endif - return 0; } -static int adc_cc23x0_init(const struct device *dev) +static int adc_lpf3_init(const struct device *dev) { - const struct adc_cc23x0_config *cfg = dev->config; - struct adc_cc23x0_data *data = dev->data; + const struct adc_lpf3_config *cfg = dev->config; + struct adc_lpf3_data *data = dev->data; int ret; ret = pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_DEFAULT); @@ -530,18 +543,12 @@ static int adc_cc23x0_init(const struct device *dev) CLKCTLEnable(CLKCTL_BASE, CLKCTL_ADC0); /* Enable interrupts */ - ADCEnableInterrupt(ADC_CC23X0_INT_MASK); + ADCEnableInterrupt(ADC_LPF3_INT_MASK); -#ifdef CONFIG_ADC_CC23X0_DMA_DRIVEN +#ifdef CONFIG_ADC_LPF3_DMA_DRIVEN if (!device_is_ready(cfg->dma_dev)) { return -ENODEV; } - - ret = pm_device_runtime_enable(cfg->dma_dev); - if (ret) { - LOG_ERR("Failed to enable DMA runtime PM"); - return ret; - } #endif adc_context_unlock_unconditionally(&data->ctx); @@ -551,9 +558,10 @@ static int adc_cc23x0_init(const struct device *dev) #ifdef CONFIG_PM_DEVICE -static int adc_cc23x0_pm_action(const struct device *dev, enum pm_device_action action) +static int adc_lpf3_pm_action(const struct device *dev, enum pm_device_action action) { - struct adc_cc23x0_data *data = dev->data; + struct adc_lpf3_data *data = dev->data; + int i = 0; switch (action) { case PM_DEVICE_ACTION_SUSPEND: @@ -561,12 +569,16 @@ static int adc_cc23x0_pm_action(const struct device *dev, enum pm_device_action return 0; case PM_DEVICE_ACTION_RESUME: CLKCTLEnable(CLKCTL_BASE, CLKCTL_ADC0); - ADCEnableInterrupt(ADC_CC23X0_INT_MASK); - - /* Restore context if needed */ - if (data->configured) { - ADCSetSampleDuration(adc_cc23x0_clkdiv_to_field(data->clk_div), - data->clk_cycles); + ADCEnableInterrupt(ADC_LPF3_INT_MASK); + + /* Restore context for the channels that were configured before */ + ARRAY_FOR_EACH_PTR(data->mem_cfg, mem_data) { + if (mem_data->configured) { + ADCSetInput(mem_data->ref, mem_data->ch, i); + ADCSetAdjustmentOffset(mem_data->ref); + ADCSetSampleDuration(mem_data->clkdiv_field, mem_data->clk_cycles); + } + i++; } return 0; @@ -577,57 +589,49 @@ static int adc_cc23x0_pm_action(const struct device *dev, enum pm_device_action #endif /* CONFIG_PM_DEVICE */ -static DEVICE_API(adc, adc_cc23x0_driver_api) = { - .channel_setup = adc_cc23x0_channel_setup, - .read = adc_cc23x0_read, +static DEVICE_API(adc, adc_lpf3_driver_api) = { + .channel_setup = adc_lpf3_channel_setup, + .read = adc_lpf3_read, #ifdef CONFIG_ADC_ASYNC - .read_async = adc_cc23x0_read_async, + .read_async = adc_lpf3_read_async, #endif .ref_internal = 1400, }; -#ifdef CONFIG_ADC_CC23X0_DMA_DRIVEN -#define ADC_CC23X0_DMA_INIT(n) \ - .dma_dev = DEVICE_DT_GET(TI_CC23X0_DT_INST_DMA_CTLR(n, dma)), \ - .dma_channel = TI_CC23X0_DT_INST_DMA_CHANNEL(n, dma), \ - .dma_trigsrc = TI_CC23X0_DT_INST_DMA_TRIGSRC(n, dma), +#ifdef CONFIG_ADC_LPF3_DMA_DRIVEN +#define ADC_LPF3_DMA_INIT(n) \ + .dma_dev = DEVICE_DT_GET(TI_CC23X0_CC27XX_DT_INST_DMA_CTLR(n, dma)), \ + .dma_channel = TI_CC23X0_CC27XX_DT_INST_DMA_CHANNEL(n, dma), \ + .dma_trigsrc = TI_CC23X0_CC27XX_DT_INST_DMA_TRIGSRC(n, dma), #else -#define ADC_CC23X0_DMA_INIT(n) +#define ADC_LPF3_DMA_INIT(n) #endif -#define CC23X0_ADC_INIT(n) \ - PINCTRL_DT_INST_DEFINE(n); \ - PM_DEVICE_DT_INST_DEFINE(n, adc_cc23x0_pm_action); \ - \ - static void adc_cc23x0_cfg_func_##n(void) \ - { \ - IRQ_CONNECT(DT_INST_IRQN(n), \ - DT_INST_IRQ(n, priority), \ - adc_cc23x0_isr, \ - DEVICE_DT_INST_GET(n), 0); \ - irq_enable(DT_INST_IRQN(n)); \ - } \ - \ - static const struct adc_cc23x0_config adc_cc23x0_config_##n = { \ - .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \ - .irq_cfg_func = adc_cc23x0_cfg_func_##n, \ - .base = DT_INST_REG_ADDR(n), \ - ADC_CC23X0_DMA_INIT(n) \ - }; \ - \ - static struct adc_cc23x0_data adc_cc23x0_data_##n = { \ - ADC_CONTEXT_INIT_TIMER(adc_cc23x0_data_##n, ctx), \ - ADC_CONTEXT_INIT_LOCK(adc_cc23x0_data_##n, ctx), \ - ADC_CONTEXT_INIT_SYNC(adc_cc23x0_data_##n, ctx), \ - }; \ - \ - DEVICE_DT_INST_DEFINE(n, \ - adc_cc23x0_init, \ - PM_DEVICE_DT_INST_GET(n), \ - &adc_cc23x0_data_##n, \ - &adc_cc23x0_config_##n, \ - POST_KERNEL, \ - CONFIG_ADC_INIT_PRIORITY, \ - &adc_cc23x0_driver_api); - -DT_INST_FOREACH_STATUS_OKAY(CC23X0_ADC_INIT) +#define LPF3_ADC_INIT(n) \ + PINCTRL_DT_INST_DEFINE(n); \ + PM_DEVICE_DT_INST_DEFINE(n, adc_lpf3_pm_action); \ + \ + static void adc_lpf3_cfg_func_##n(void) \ + { \ + IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), adc_lpf3_isr, \ + DEVICE_DT_INST_GET(n), 0); \ + irq_enable(DT_INST_IRQN(n)); \ + } \ + \ + static const struct adc_lpf3_config adc_lpf3_config_##n = { \ + .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \ + .irq_cfg_func = adc_lpf3_cfg_func_##n, \ + .base = DT_INST_REG_ADDR(n), \ + ADC_LPF3_DMA_INIT(n)}; \ + \ + static struct adc_lpf3_data adc_lpf3_data_##n = { \ + ADC_CONTEXT_INIT_TIMER(adc_lpf3_data_##n, ctx), \ + ADC_CONTEXT_INIT_LOCK(adc_lpf3_data_##n, ctx), \ + ADC_CONTEXT_INIT_SYNC(adc_lpf3_data_##n, ctx), \ + }; \ + \ + DEVICE_DT_INST_DEFINE(n, &adc_lpf3_init, PM_DEVICE_DT_INST_GET(n), &adc_lpf3_data_##n, \ + &adc_lpf3_config_##n, POST_KERNEL, CONFIG_ADC_INIT_PRIORITY, \ + &adc_lpf3_driver_api); + +DT_INST_FOREACH_STATUS_OKAY(LPF3_ADC_INIT) diff --git a/drivers/adc/adc_shell.c b/drivers/adc/adc_shell.c index 58d02d5a91ef..d2e9deaded39 100644 --- a/drivers/adc/adc_shell.c +++ b/drivers/adc/adc_shell.c @@ -11,39 +11,30 @@ #include #include - #define LOG_LEVEL CONFIG_LOG_DEFAULT_LEVEL #include LOG_MODULE_REGISTER(adc_shell); -#define CMD_HELP_ACQ_TIME \ - SHELL_HELP("Configure acquisition time", \ - "