From 4a7478838cc3553271c1e01387e7fb8491fb7d2c Mon Sep 17 00:00:00 2001 From: Vebjorn Myklebust Date: Fri, 16 Oct 2026 16:10:18 +0200 Subject: [PATCH 001/100] UPSTREAM-PEND: manifest: hal_ti: update hal_ti to point to downstream switch hal_ti to use the TI downstream fork Signed-off-by: Vebjorn Myklebust --- west.yml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 49c144964508..8bb05d1b8f8b 100644 --- a/west.yml +++ b/west.yml @@ -21,6 +21,8 @@ manifest: remotes: - name: upstream url-base: https://github.com/zephyrproject-rtos + - name: downstream + url-base: https://github.com/TexasInstruments - name: babblesim url-base: https://github.com/BabbleSim @@ -273,10 +275,12 @@ manifest: groups: - hal - name: hal_ti - revision: 53c80140dd69905cc5e034f637eff9c66b2f9654 + remote: downstream + revision: 8cac725a51e30313dae7db911c99029387841673 path: modules/hal/ti groups: - hal + - external - name: hal_wch revision: dd3855ea624b05de7e6e95584789615d2058a0f3 path: modules/hal/wch From 6f5b4e1f634ce1fa731b6d3ab098b5ff8350cefe Mon Sep 17 00:00:00 2001 From: Jacek Ozimek Date: Tue, 29 Jul 2025 13:14:25 +0200 Subject: [PATCH 002/100] UPSTREAM-PEND: soc: ti: Add support for cc35xxe SoC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for cc35xxe SoC Signed-off-by: Jacek Ozimek Signed-off-by: Michał Łyszczek --- dts/arm/ti/cc35xxe.dtsi | 214 ++++++++++++++++++ dts/bindings/dma/ti,cc35xx-dma.yaml | 17 ++ modules/Kconfig.simplelink | 5 + soc/ti/simplelink/cc35xxe/CMakeLists.txt | 8 + soc/ti/simplelink/cc35xxe/Kconfig | 13 ++ soc/ti/simplelink/cc35xxe/Kconfig.defconfig | 9 + .../cc35xxe/Kconfig.defconfig.cc3551e | 29 +++ soc/ti/simplelink/cc35xxe/Kconfig.soc | 19 ++ soc/ti/simplelink/cc35xxe/pinctrl_soc.h | 42 ++++ soc/ti/simplelink/cc35xxe/soc.c | 19 ++ soc/ti/simplelink/cc35xxe/soc.h | 15 ++ soc/ti/simplelink/soc.yml | 3 + 12 files changed, 393 insertions(+) create mode 100644 dts/arm/ti/cc35xxe.dtsi create mode 100644 dts/bindings/dma/ti,cc35xx-dma.yaml create mode 100644 soc/ti/simplelink/cc35xxe/CMakeLists.txt create mode 100644 soc/ti/simplelink/cc35xxe/Kconfig create mode 100644 soc/ti/simplelink/cc35xxe/Kconfig.defconfig create mode 100644 soc/ti/simplelink/cc35xxe/Kconfig.defconfig.cc3551e create mode 100644 soc/ti/simplelink/cc35xxe/Kconfig.soc create mode 100644 soc/ti/simplelink/cc35xxe/pinctrl_soc.h create mode 100644 soc/ti/simplelink/cc35xxe/soc.c create mode 100644 soc/ti/simplelink/cc35xxe/soc.h diff --git a/dts/arm/ti/cc35xxe.dtsi b/dts/arm/ti/cc35xxe.dtsi new file mode 100644 index 000000000000..e867311aceb6 --- /dev/null +++ b/dts/arm/ti/cc35xxe.dtsi @@ -0,0 +1,214 @@ +/* + * Copyright (c) 2025 Conclusive Engineering Sp. z o.o. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m33"; + reg = <0>; + }; + }; + + sysclk: system-clock { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + rtc_xtal: clock-rtc-xtal { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + uartclk: uart-clock { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + soc { + /* I-Cache and ITCM size options can be configured independently The user can + * decide how to split ITCM and I-Cache in the following configurations: + * 1. 32kB I-Cache + 32kB ITCM + * 2. 64kB I-Cache + 0kB ITCM + */ + icache_ns: icache_ns@0 { + status = "disabled"; + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x0 DT_SIZE_K(32)>; + zephyr,memory-region = "ICACHE_NS"; + }; + + icache: icache@4000000 { + status = "disabled"; + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x4000000 DT_SIZE_K(32)>; + zephyr,memory-region = "ICACHE"; + }; + + itcm_ns: itcm_ns@0 { + status = "disabled"; + compatible = "zephyr,memory-region", "arm,itcm"; + reg = <0x0 DT_SIZE_K(32)>; + zephyr,memory-region = "ITCM_NS"; + }; + + itcm: itcm@4000000 { + status = "disabled"; + compatible = "zephyr,memory-region", "arm,itcm"; + reg = <0x4000000 DT_SIZE_K(32)>; + zephyr,memory-region = "ITCM"; + }; + + imem_ns: imem_ns@8000000 { + status = "disabled"; + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x8000000 DT_SIZE_K(160)>; + zephyr,memory-region = "IMEM_NS"; + }; + + imem: imem@c000000 { + status = "disabled"; + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0xc000000 DT_SIZE_K(160)>; + zephyr,memory-region = "IMEM"; + }; + + dtcm_ns: dtcm_ns@20000000 { + status = "disabled"; + compatible = "zephyr,memory-region", "arm,dtcm"; + reg = <0x20000000 DT_SIZE_K(128)>; + zephyr,memory-region = "DTCM_NS"; + }; + + dtcm: dtcm@24000000 { + status = "disabled"; + compatible = "zephyr,memory-region", "arm,dtcm"; + reg = <0x24000000 DT_SIZE_K(128)>; + zephyr,memory-region = "DTCM"; + }; + + dmem_ns: dmem_ns@28000000 { + status = "disabled"; + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x28000000 DT_SIZE_K(256)>; + zephyr,memory-region = "DMEM_NS"; + }; + + dmem: dmem@2c000000 { + status = "disabled"; + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x2c000000 DT_SIZE_K(192)>; + zephyr,memory-region = "DMEM"; + }; + + extflash_ns: extflash@10000000 { + status = "disabled"; + compatible = "zephyr,memory-region"; + reg = <0x10000000 DT_SIZE_M(64)>; + zephyr,memory-region = "EXTFLASH_NS"; + }; + + extflash: extflash@14000000 { + status = "disabled"; + compatible = "zephyr,memory-region"; + reg = <0x14000000 DT_SIZE_M(64)>; + zephyr,memory-region = "EXTFLASH"; + }; + + uart0: uart@41240000 { + compatible = "ti,cc35xx-uart"; + reg = <0x41240000 0x1000>; + clocks = <&uartclk>; + status = "disabled"; + }; + + uart1: uart@41250000 { + compatible = "ti,cc35xx-uart"; + reg = <0x41250000 0x1000>; + clocks = <&uartclk>; + status = "disabled"; + }; + + dma: dma@41a00000 { + compatible = "ti,cc35xx-dma"; + reg = <0x41a00000 0x10000>; + #dma-cells = <1>; + status = "disabled"; + }; + + pinctrl: pin-controller@41140000 { + compatible = "ti,cc35xx-pinctrl"; + reg = <0x41140000 0x80000>; + + gpios: gpio { + compatible = "ti,cc35xx-gpio"; + status = "okay"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffe0 0xffffffc0>; + gpio-map-pass-thru = <0x1f 0x3f>; + gpio-map = < + 0x00 0x0 &gpio0_31 0x0 0x0 + 0x20 0x0 &gpio32_63 0x0 0x0 + >; + + gpio0_31: gpio0_31 { + compatible = "ti,cc35xx-gpio-port"; + status = "okay"; + gpio-controller; + #gpio-cells = <2>; + gpio-index-offset = <(0*32)>; + interrupts = <17 1>; + ngpios = <32>; + }; + + gpio32_63: gpio32_63 { + compatible = "ti,cc35xx-gpio-port"; + status = "okay"; + gpio-controller; + #gpio-cells = <2>; + gpio-index-offset = <(1*32)>; + interrupts = <17 1>; + ngpios = <12>; + }; + }; + }; + + flash0: flash@a0000000 { + compatible = "ti,cc35xx-nv-flash"; + reg = <0xa0000000 0x00033000>, <0x0 0x00033000>; + erase-block-size = ; + write-block-size = <4>; + }; + + flash1: flash@10000000 { + compatible = "ti,cc35xx-nv-flash"; + reg = <0x10000000 0x001e7000>, <0x00033000 0x001e7000>; + erase-block-size = ; + write-block-size = <4>; + }; + + flash2: flash@a0050000 { + compatible = "ti,cc35xx-nv-flash"; + reg = <0xa0050000 0x001ea000>, <0x0021a000 0x001ea000>; + erase-block-size = ; + write-block-size = <4>; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <4>; +}; diff --git a/dts/bindings/dma/ti,cc35xx-dma.yaml b/dts/bindings/dma/ti,cc35xx-dma.yaml new file mode 100644 index 000000000000..74631fa7d108 --- /dev/null +++ b/dts/bindings/dma/ti,cc35xx-dma.yaml @@ -0,0 +1,17 @@ +# Copyright (c) 2025 Conclusive Engineering Sp. z o.o. +# +# SPDX-License-Identifier: Apache-2.0 + +description: | + TI Simplelink DMA controller for the cc35xx chip family. + +compatible: "ti,cc35xx-dma" + +include: dma-controller.yaml + +properties: + "#dma-cells": + const: 1 + +dma-cells: + - channel diff --git a/modules/Kconfig.simplelink b/modules/Kconfig.simplelink index b2c11dca0b91..c0fc3fd915b8 100644 --- a/modules/Kconfig.simplelink +++ b/modules/Kconfig.simplelink @@ -37,3 +37,8 @@ config HAS_CC13X2X7_CC26X2X7_SDK config HAS_CC23X0_SDK bool + +# CC35XX SDK HAL configuration + +config HAS_CC35XX_SDK + bool diff --git a/soc/ti/simplelink/cc35xxe/CMakeLists.txt b/soc/ti/simplelink/cc35xxe/CMakeLists.txt new file mode 100644 index 000000000000..24f3c720fab2 --- /dev/null +++ b/soc/ti/simplelink/cc35xxe/CMakeLists.txt @@ -0,0 +1,8 @@ +# Copyright (c) 2025 Conclusive Engineering Sp. z o.o. +# +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(soc.c) +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/ti/simplelink/cc35xxe/Kconfig b/soc/ti/simplelink/cc35xxe/Kconfig new file mode 100644 index 000000000000..6f99904f4c20 --- /dev/null +++ b/soc/ti/simplelink/cc35xxe/Kconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2025 Conclusive Engineering Sp. z o.o. +# Texas Instruments CC35XXE +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_CC35XXE + select ARM + select CPU_CORTEX_M33 + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select HAS_CC35XX_SDK + select ARMV8_M_DSP + select DYNAMIC_INTERRUPTS diff --git a/soc/ti/simplelink/cc35xxe/Kconfig.defconfig b/soc/ti/simplelink/cc35xxe/Kconfig.defconfig new file mode 100644 index 000000000000..5484022ece32 --- /dev/null +++ b/soc/ti/simplelink/cc35xxe/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Conclusive Engineering Sp. z o.o. +# Texas Instruments SimpleLink Family +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_CC35XXE + +rsource "Kconfig.defconfig.cc35*e" + +endif # SOC_SERIES_CC35XXE diff --git a/soc/ti/simplelink/cc35xxe/Kconfig.defconfig.cc3551e b/soc/ti/simplelink/cc35xxe/Kconfig.defconfig.cc3551e new file mode 100644 index 000000000000..5a9d7c65b2b9 --- /dev/null +++ b/soc/ti/simplelink/cc35xxe/Kconfig.defconfig.cc3551e @@ -0,0 +1,29 @@ +# Copyright (c) 2025 Conclusive Engineering Sp. z o.o. +# Texas Instruments SimpleLink CC3551E SoC +# SPDX-License-Identifier: Apache-2.0 + +if SOC_CC3551E + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 160000000 + +config SYS_CLOCK_TICKS_PER_SEC + default 1000 + +config NUM_IRQS + default 48 + +config XIP + bool + default n + +config FLASH_LOAD_OFFSET + hex + default 0x2000 if XIP + default 0x0 if !XIP + +config ROM_START_OFFSET + hex + default 0x0 + +endif # SOC_CC3551E diff --git a/soc/ti/simplelink/cc35xxe/Kconfig.soc b/soc/ti/simplelink/cc35xxe/Kconfig.soc new file mode 100644 index 000000000000..8be2c5c48d2a --- /dev/null +++ b/soc/ti/simplelink/cc35xxe/Kconfig.soc @@ -0,0 +1,19 @@ +# Copyright (c) 2025 Conclusive Engineering Sp. z o.o. +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_CC35XXE + bool + select SOC_FAMILY_TI_SIMPLELINK + help + Enable support for TI SimpleLink CC35xxE SoCs + +config SOC_CC3551E + bool + select SOC_SERIES_CC35XXE + +config SOC_SERIES + default "cc35xxe" if SOC_SERIES_CC35XXE + +config SOC + default "cc3551e" if SOC_CC3551E diff --git a/soc/ti/simplelink/cc35xxe/pinctrl_soc.h b/soc/ti/simplelink/cc35xxe/pinctrl_soc.h new file mode 100644 index 000000000000..1eee38fd625e --- /dev/null +++ b/soc/ti/simplelink/cc35xxe/pinctrl_soc.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2025 Conclusive Engineering Sp. z o.o. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef TI_SIMPLELINK_CC35XX_SOC_PINCTRL_H_ +#define TI_SIMPLELINK_CC35XX_SOC_PINCTRL_H_ + +#include +#include + +typedef uint32_t pinctrl_soc_pin_t; + +#define TI_CC35XX_OPEN_DRAIN BIT(4) +#define TI_CC35XX_PULL_UP BIT(8) +#define TI_CC35XX_PULL_DOWN BIT(9) + +/** + * @brief Utility macro to initialize each pin. + * + * @param node_id Node identifier. + * @param prop Property name. + * @param idx Property entry index. + */ +#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \ + (DT_PROP_BY_IDX(node_id, prop, idx) | \ + (TI_CC35XX_OPEN_DRAIN * DT_PROP(node_id, drive_open_drain)) | \ + (TI_CC35XX_PULL_UP * DT_PROP(node_id, bias_pull_up)) | \ + (TI_CC35XX_PULL_DOWN * DT_PROP(node_id, bias_pull_down))), + +/** + * @brief Utility macro to initialize state pins contained in a given property. + * + * @param node_id Node identifier. + * @param prop Property name describing state pins. + */ +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + {DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux, \ + Z_PINCTRL_STATE_PIN_INIT)} + +#endif /* TI_SIMPLELINK_CC35XX_SOC_PINCTRL_H_ */ diff --git a/soc/ti/simplelink/cc35xxe/soc.c b/soc/ti/simplelink/cc35xxe/soc.c new file mode 100644 index 000000000000..a478f5409b29 --- /dev/null +++ b/soc/ti/simplelink/cc35xxe/soc.c @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2025 Conclusive Engineering Sp. z o.o. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +static int ti_cc35xx_init(void) +{ + /* Perform necessary trim of the device. */ + SetupTrimDevice(); + + return 0; +} + +/* Call initialization function as early as possible */ +SYS_INIT(ti_cc35xx_init, EARLY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); diff --git a/soc/ti/simplelink/cc35xxe/soc.h b/soc/ti/simplelink/cc35xxe/soc.h new file mode 100644 index 000000000000..944f89f151c4 --- /dev/null +++ b/soc/ti/simplelink/cc35xxe/soc.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2025 Conclusive Engineering Sp. z o.o. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef TI_SIMPLELINK_CC35XX_SOC_H_ +#define TI_SIMPLELINK_CC35XX_SOC_H_ + +#include +#include + +#include + +#endif /* TI_SIMPLELINK_CC35XX_SOC_H_ */ diff --git a/soc/ti/simplelink/soc.yml b/soc/ti/simplelink/soc.yml index 20ca3c56aa30..89488904a520 100644 --- a/soc/ti/simplelink/soc.yml +++ b/soc/ti/simplelink/soc.yml @@ -21,6 +21,9 @@ family: socs: - name: cc3220sf - name: cc3235sf + - name: cc35xxe + socs: + - name: cc3551e - name: msp432p4xx socs: - name: msp432p401r From 7de6e531a08106a4f52770b0a619df64d94dc3ea Mon Sep 17 00:00:00 2001 From: Jacek Ozimek Date: Tue, 29 Jul 2025 13:44:33 +0200 Subject: [PATCH 003/100] UPSTREAM-PEND: boards: ti: Add support for lp_em_cc35x1 board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Product URL: https://www.ti.com/tool/LP-EM-CC35X1 Signed-off-by: Jacek Ozimek Signed-off-by: Michał Łyszczek --- boards/ti/lp_em_cc35x1/Kconfig.lp_em_cc35x1 | 7 +++ boards/ti/lp_em_cc35x1/board.cmake | 3 + boards/ti/lp_em_cc35x1/board.yml | 6 ++ boards/ti/lp_em_cc35x1/doc/index.rst | 56 +++++++++++++++++++ boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts | 46 +++++++++++++++ boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml | 10 ++++ boards/ti/lp_em_cc35x1/lp_em_cc35x1_defconfig | 5 ++ .../cc35xxe/Kconfig.defconfig.cc3551e | 3 + soc/ti/simplelink/cc35xxe/Kconfig.soc | 2 + 9 files changed, 138 insertions(+) create mode 100644 boards/ti/lp_em_cc35x1/Kconfig.lp_em_cc35x1 create mode 100644 boards/ti/lp_em_cc35x1/board.cmake create mode 100644 boards/ti/lp_em_cc35x1/board.yml create mode 100644 boards/ti/lp_em_cc35x1/doc/index.rst create mode 100644 boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts create mode 100644 boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml create mode 100644 boards/ti/lp_em_cc35x1/lp_em_cc35x1_defconfig diff --git a/boards/ti/lp_em_cc35x1/Kconfig.lp_em_cc35x1 b/boards/ti/lp_em_cc35x1/Kconfig.lp_em_cc35x1 new file mode 100644 index 000000000000..2a79dec5ecff --- /dev/null +++ b/boards/ti/lp_em_cc35x1/Kconfig.lp_em_cc35x1 @@ -0,0 +1,7 @@ +# TI CC35X1 LaunchPad board +# Copyright (c) 2025 Conclusive Engineering Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LP_EM_CC35X1 + bool + select SOC_CC3551E diff --git a/boards/ti/lp_em_cc35x1/board.cmake b/boards/ti/lp_em_cc35x1/board.cmake new file mode 100644 index 000000000000..26fc91e01481 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/board.cmake @@ -0,0 +1,3 @@ +# Copyright (c) 2025 Conclusive Engineering Sp. z o.o. +# +# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/ti/lp_em_cc35x1/board.yml b/boards/ti/lp_em_cc35x1/board.yml new file mode 100644 index 000000000000..2b3723b8885e --- /dev/null +++ b/boards/ti/lp_em_cc35x1/board.yml @@ -0,0 +1,6 @@ +board: + name: lp_em_cc35x1 + full_name: CC35x1 LaunchPad + vendor: ti + socs: + - name: cc3551e diff --git a/boards/ti/lp_em_cc35x1/doc/index.rst b/boards/ti/lp_em_cc35x1/doc/index.rst new file mode 100644 index 000000000000..181b13a97382 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/doc/index.rst @@ -0,0 +1,56 @@ +.. _lp_em_cc35x1: + +TI cc35x1 Launchpad +##################### + +Overview +******** + +The Texas Instruments cc35x1 LaunchPad |trade| (LP_EM_CC35X1) is a +development kit for the SimpleLink |trade| multi-Standard cc35x1 wireless MCU. + +See the `TI cc35x1 LaunchPad Product Page`_ for details. + +Hardware +******** + +The cc35x1 LaunchPad |trade| development kit features the cc3551e wireless MCU. +The board is equipped with two LEDs and two push buttons + +The cc35x1 wireless MCU has a 160 MHz Arm |reg| Cortex |reg|-M33 SoC and an +integrated 2.4 GHz transceiver supporting multiple protocols including Bluetooth +|reg| Low Energy and IEEE |reg| 802.15.4. + +See the `TI cc35x1 Product Page`_ for additional details. + +Supported Features +================== + +The cc35x1 LaunchPad board configuration supports the following hardware +features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. + +Programming and Debugging +************************* + +The LP_EM_CC35X1 requires an external debug probe such as the LP-XDS110 or +LP-XDS110ET. + +Currently there is no debug support in Zephyr for the LP_EM_CC35X1. Binaries can be flashed +with standard `west flash` command. + +References +********** + +.. _TI cc35x1 LaunchPad Product Page: + https://www.ti.com/tool/LP-EM-CC35X1 + +.. _TI cc35x1 Product Page: + https://www.ti.com/product/CC3551E diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts b/boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts new file mode 100644 index 000000000000..a8ab0d57602a --- /dev/null +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2025 Conclusive Engineering Sp. z o.o. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +/ { + model = "TI CC35X1E LaunchPad"; + compatible = "ti,launchpad-cc35x1e"; + + chosen { + zephyr,sram = &dmem_ns; + zephyr,flash = &extflash; + zephyr,itcm = &itcm_ns; + zephyr,dtcm = &dtcm_ns; + zephyr,code-partition = &dmem_ns; + }; +}; + +&imem_ns { + status = "okay"; +}; + +&dmem_ns { + status = "okay"; +}; + +&itcm_ns { + status = "okay"; +}; + +&dtcm_ns { + status = "okay"; +}; + +&itcm { + status = "okay"; +}; + +&dtcm { + status = "okay"; +}; diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml b/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml new file mode 100644 index 000000000000..040c7382509a --- /dev/null +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml @@ -0,0 +1,10 @@ +identifier: lp_em_cc35x1 +name: TI SimpleLink™ CC35x1 LaunchPad +type: mcu +arch: arm +ram: 1024 +flash: 8192 +toolchain: + - zephyr + - gnuarmemb +vendor: ti diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_defconfig b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_defconfig new file mode 100644 index 000000000000..f46e2280bd2d --- /dev/null +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_defconfig @@ -0,0 +1,5 @@ +# +# Copyright (c) 2025 Conclusive Engineering Sp. z o.o. +# +# SPDX-License-Identifier: Apache-2.0 +# diff --git a/soc/ti/simplelink/cc35xxe/Kconfig.defconfig.cc3551e b/soc/ti/simplelink/cc35xxe/Kconfig.defconfig.cc3551e index 5a9d7c65b2b9..97a5907cbaac 100644 --- a/soc/ti/simplelink/cc35xxe/Kconfig.defconfig.cc3551e +++ b/soc/ti/simplelink/cc35xxe/Kconfig.defconfig.cc3551e @@ -5,12 +5,15 @@ if SOC_CC3551E config SYS_CLOCK_HW_CYCLES_PER_SEC + int default 160000000 config SYS_CLOCK_TICKS_PER_SEC + int default 1000 config NUM_IRQS + int default 48 config XIP diff --git a/soc/ti/simplelink/cc35xxe/Kconfig.soc b/soc/ti/simplelink/cc35xxe/Kconfig.soc index 8be2c5c48d2a..7a77706c8951 100644 --- a/soc/ti/simplelink/cc35xxe/Kconfig.soc +++ b/soc/ti/simplelink/cc35xxe/Kconfig.soc @@ -13,7 +13,9 @@ config SOC_CC3551E select SOC_SERIES_CC35XXE config SOC_SERIES + string default "cc35xxe" if SOC_SERIES_CC35XXE config SOC + string default "cc3551e" if SOC_CC3551E From 2eb4e402f08c755473cfe8ed3ad0158682d62204 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=81yszczek?= Date: Tue, 29 Jul 2025 14:00:54 +0200 Subject: [PATCH 004/100] UPSTREAM-PEND: drivers: pinctrl: cc35xxe: Add support for pinctrl MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for pinctrl to cc35xxe SoC Signed-off-by: Michał Łyszczek Signed-off-by: Jacek Ozimek --- .../ti/lp_em_cc35x1/lp_em_cc35x1-pinctrl.dtsi | 20 + boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts | 2 + boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml | 2 + drivers/pinctrl/CMakeLists.txt | 1 + drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/Kconfig.ti_cc35xx | 9 + drivers/pinctrl/pinctrl_ti_cc35xx.c | 61 ++ dts/bindings/pinctrl/ti,cc35xx-pinctrl.yaml | 32 + .../dt-bindings/pinctrl/ti-cc35xx-pinctrl.h | 751 ++++++++++++++++++ 9 files changed, 879 insertions(+) create mode 100644 boards/ti/lp_em_cc35x1/lp_em_cc35x1-pinctrl.dtsi create mode 100644 drivers/pinctrl/Kconfig.ti_cc35xx create mode 100644 drivers/pinctrl/pinctrl_ti_cc35xx.c create mode 100644 dts/bindings/pinctrl/ti,cc35xx-pinctrl.yaml create mode 100644 include/zephyr/dt-bindings/pinctrl/ti-cc35xx-pinctrl.h diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1-pinctrl.dtsi b/boards/ti/lp_em_cc35x1/lp_em_cc35x1-pinctrl.dtsi new file mode 100644 index 000000000000..5cb97c4ad6b0 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1-pinctrl.dtsi @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2025 Conclusive Engineering Sp. z o.o. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = , ; + }; + }; + uart1_default: uart1_default { + group1 { + pinmux = , ; + }; + }; +}; diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts b/boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts index a8ab0d57602a..a6609d6538eb 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts @@ -7,6 +7,7 @@ /dts-v1/; #include +#include "lp_em_cc35x1-pinctrl.dtsi" / { model = "TI CC35X1E LaunchPad"; @@ -19,6 +20,7 @@ zephyr,dtcm = &dtcm_ns; zephyr,code-partition = &dmem_ns; }; + }; &imem_ns { diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml b/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml index 040c7382509a..40ec537cdc52 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml @@ -7,4 +7,6 @@ flash: 8192 toolchain: - zephyr - gnuarmemb +supported: + - pinctrl vendor: ti diff --git a/drivers/pinctrl/CMakeLists.txt b/drivers/pinctrl/CMakeLists.txt index 63f96988f571..9af1d5390025 100644 --- a/drivers/pinctrl/CMakeLists.txt +++ b/drivers/pinctrl/CMakeLists.txt @@ -59,6 +59,7 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_SY1XX pinctrl_sy1xx.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_SYNA_SR100 pinctrl_syna_sr100.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_TELINK_B91 pinctrl_b91.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_TI_CC32XX pinctrl_ti_cc32xx.c) +zephyr_library_sources_ifdef(CONFIG_PINCTRL_TI_CC35XX pinctrl_ti_cc35xx.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_TI_K3 pinctrl_ti_k3.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_WCH_00X_AFIO pinctrl_wch_00x_afio.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_WCH_20X_30X_AFIO pinctrl_wch_20x_30x_afio.c) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 18d3f256cfed..af2c50c52afe 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -86,6 +86,7 @@ source "drivers/pinctrl/Kconfig.stm32" source "drivers/pinctrl/Kconfig.sy1xx" source "drivers/pinctrl/Kconfig.syna_sr100" source "drivers/pinctrl/Kconfig.ti_cc32xx" +source "drivers/pinctrl/Kconfig.ti_cc35xx" source "drivers/pinctrl/Kconfig.ti_k3" source "drivers/pinctrl/Kconfig.wch_00x_afio" source "drivers/pinctrl/Kconfig.wch_20x_30x_afio" diff --git a/drivers/pinctrl/Kconfig.ti_cc35xx b/drivers/pinctrl/Kconfig.ti_cc35xx new file mode 100644 index 000000000000..ce9a633ac483 --- /dev/null +++ b/drivers/pinctrl/Kconfig.ti_cc35xx @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Conclusive Engineering Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +config PINCTRL_TI_CC35XX + bool "TI CC35XX pinctrl driver" + default y + depends on DT_HAS_TI_CC35XX_PINCTRL_ENABLED + help + Enable the TI CC35XX pinctrl driver diff --git a/drivers/pinctrl/pinctrl_ti_cc35xx.c b/drivers/pinctrl/pinctrl_ti_cc35xx.c new file mode 100644 index 000000000000..85fd330ce3f6 --- /dev/null +++ b/drivers/pinctrl/pinctrl_ti_cc35xx.c @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2025 Conclusive Engineering Sp. z o.o. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT ti_cc35xx_pinctrl + +#include +#include +#include +#include + +#define MEM_GPIO_PAD_CONFIG_MSK 0xFFFU +#define MEM_GPIO0_PCFG_OFFSET 0x0002D004 + +#define MEM_GPIO0_CFG_OFFSET 0 +#define MEM_GPIO0_PCTL_OFFSET 4 +#define MEM_GPIO_NEXT_OFFSET 0x1000 +#define MEM_GPIO_IE_BIT 11 +#define MEM_GPIO_OUTDIS_BIT 12 + +static void pinctrl_configure_pin(pinctrl_soc_pin_t pincfg) +{ + uint8_t pin; + mem_addr_t reg; + uint32_t tmp; + int dir; + + pin = (pincfg >> TI_CC35XX_PIN_POS) & TI_CC35XX_PIN_MSK; + dir = TI_CC35XX_PINCTRL_DIR(pincfg); + + /* set pin function */ + reg = DT_INST_REG_ADDR(0) + MEM_GPIO0_PCFG_OFFSET + pin * sizeof(uint32_t); + sys_write32(pincfg & TI_CC35XX_MUX_MSK, reg); + + /* enable/disable receiver operation on pin */ + reg = DT_INST_REG_ADDR(0) + pin * MEM_GPIO_NEXT_OFFSET + MEM_GPIO0_CFG_OFFSET; + tmp = sys_read32(reg); + if (dir == TI_CC35XX_PINCTRL_DIR_IN) { + tmp |= BIT(MEM_GPIO_IE_BIT) | BIT(MEM_GPIO_OUTDIS_BIT); + } else { + tmp &= ~(BIT(MEM_GPIO_IE_BIT) | BIT(MEM_GPIO_OUTDIS_BIT)); + } + sys_write32(tmp, reg); + + /* give IP control over pull */ + reg = DT_INST_REG_ADDR(0) + pin * MEM_GPIO_NEXT_OFFSET + MEM_GPIO0_PCTL_OFFSET; + sys_write32(0, reg); +} + +int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg) +{ + ARG_UNUSED(reg); + + for (uint8_t i = 0; i < pin_cnt; i++) { + pinctrl_configure_pin(pins[i]); + } + + return 0; +} diff --git a/dts/bindings/pinctrl/ti,cc35xx-pinctrl.yaml b/dts/bindings/pinctrl/ti,cc35xx-pinctrl.yaml new file mode 100644 index 000000000000..2948278c8d83 --- /dev/null +++ b/dts/bindings/pinctrl/ti,cc35xx-pinctrl.yaml @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: Apache-2.0 + +description: | + The TI CC35XX pin controller is a singleton node responsible for controlling + pin function selection and pin properties. For example, you can + use this node to route UART0 RX to pin 55 and enable the pull-up resistor + on the pin. + +compatible: "ti,cc35xx-pinctrl" + +include: base.yaml + +child-binding: + child-binding: + include: + - name: pincfg-node.yaml + property-allowlist: + - drive-push-pull + - drive-open-drain + - bias-disable + - bias-pull-down + - bias-pull-up + - drive-strength + + properties: + pinmux: + required: true + type: array + description: | + An array of pins sharing the same group properties. The pins should + be defined using pre-defined macros or, alternatively, using the + TI_CC35XX_PINMUX helper macro. diff --git a/include/zephyr/dt-bindings/pinctrl/ti-cc35xx-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/ti-cc35xx-pinctrl.h new file mode 100644 index 000000000000..0deeb56e51f6 --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/ti-cc35xx-pinctrl.h @@ -0,0 +1,751 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_TI_CC35XX_PINCTRL_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_TI_CC35XX_PINCTRL_H_ + +/* + * The whole TI CC35XX pin configuration information is encoded in a 32-bit + * bitfield organized as follows: + * + * - 31..22: Reserved. + * - 21..16: Pin. + * - 15..11: Reserved. + * - 10: Pin direction + * - 9: Pull-down flag. + * - 8: Pull-up flag. + * - 7..5: Drive strength. + * - 4: Enable open-drain flag. + * - 3..0: Configuration mode. + */ + +/** + * @name TI CC35XX pin configuration bit field positions and masks. + * @{ + */ + +#define TI_CC35XX_PIN_MSK 0x3f +#define TI_CC35XX_PIN_POS 16 +#define TI_CC35XX_MUX_MSK 0x0f +#define TI_CC35XX_MUX_POS 0 +#define TI_CC35XX_DIR_MSK 0x01 +#define TI_CC35XX_DIR_POS 10 + +/** @} */ + +#define TI_CC35XX_PINCTRL_DIR_IN (1 << TI_CC35XX_DIR_POS) +#define TI_CC35XX_PINCTRL_DIR_OUT (0) + +#define TI_CC35XX_PINCTRL_PIN(PCFG) (((PCFG) >> TI_CC35XX_PIN_POS) & TI_CC35XX_PIN_MSK) +#define TI_CC35XX_PINCTRL_MUX(PCFG) (((PCFG) >> TI_CC35XX_MUX_POS) & TI_CC35XX_MUX_MSK) +#define TI_CC35XX_PINCTRL_DIR(PCFG) ((PCFG) & TI_CC35XX_PINCTRL_DIR_IN) + +/** + * @brief Utility macro to build TI CC35XX pinmux property entry. + * + * @param pin Pin + * @param mux Multiplexer choice + */ +#define TI_CC35XX_PINMUX(pin, mux) \ + ((((pin) & TI_CC35XX_PIN_MSK) << TI_CC35XX_PIN_POS) | \ + (((mux) & TI_CC35XX_MUX_MSK) << TI_CC35XX_MUX_POS)) + +/** + * @name TI CC35XX pinctrl pin functions (reference: SWRU626). + * @{ + */ + +#define P0_WIFI_GPIO_0 TI_CC35XX_PINMUX(0, 2) +#define P0_GPT1_1 TI_CC35XX_PINMUX(0, 9) +#define P0_GPT0_1 TI_CC35XX_PINMUX(0, 10) + +#define P1_LFXT_N TI_CC35XX_PINMUX(1, 0) +#define P1_WIFI_GPIO_1 TI_CC35XX_PINMUX(1, 2) +#define P1_GPT1_PRE_EVENT TI_CC35XX_PINMUX(1, 7) +#define P1_GPT0_PRE_EVENT TI_CC35XX_PINMUX(1, 8) +#define P1_GPT1_0 TI_CC35XX_PINMUX(1, 9) +#define P1_GPT0_0 TI_CC35XX_PINMUX(1, 10) +#define P1_GPT_INFRARED TI_CC35XX_PINMUX(1, 11) +#define P1_SDIO_OOB_IRQ TI_CC35XX_PINMUX(1, 19) +#define P1_COEX_GRANT TI_CC35XX_PINMUX(1, 20) +#define P1_ANT_SEL_0 TI_CC35XX_PINMUX(1, 23) + +#define P2_XSPI_RESET_RAM TI_CC35XX_PINMUX(2, 1) +#define P2_WIFI_GPIO_2 TI_CC35XX_PINMUX(2, 2) +#define P2_SDIO_MMC_CD TI_CC35XX_PINMUX(2, 3) +#define P2_I2C1_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(2, 6)) +#define P2_GPT1_3 TI_CC35XX_PINMUX(2, 9) +#define P2_DCAN_TX (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(2, 10)) +#define P2_WAKE_OBSERVE_BUS_6 TI_CC35XX_PINMUX(2, 11) +#define P2_DEBUG_BUS_4 TI_CC35XX_PINMUX(2, 12) +#define P2_SPI0_CS4 TI_CC35XX_PINMUX(2, 16) +#define P2_GPT1_PRE_EVENT TI_CC35XX_PINMUX(2, 18) +#define P2_SDIO_OOB_IRQ TI_CC35XX_PINMUX(2, 19) +#define P2_COEX_GRANT TI_CC35XX_PINMUX(2, 20) +#define P2_COEX_REQ TI_CC35XX_PINMUX(2, 21) +#define P2_BLE_RFTRC TI_CC35XX_PINMUX(2, 22) +#define P2_ANT_SEL_2 TI_CC35XX_PINMUX(2, 23) +#define P2_CCA TI_CC35XX_PINMUX(2, 24) +#define P2_TRCLK TI_CC35XX_PINMUX(2, 26) + +#define P3_UART1_TX (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(3, 1)) +#define P3_WIFI_GPIO_3 TI_CC35XX_PINMUX(3, 2) +#define P3_SDIO_MMC_WP TI_CC35XX_PINMUX(3, 3) +#define P3_SPI1_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(3, 4)) +#define P3_UART1_RTS (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(3, 5)) +#define P3_I2S_MCLK TI_CC35XX_PINMUX(3, 6) +#define P3_I2S_DATA0 TI_CC35XX_PINMUX(3, 7) +#define P3_PDM_DATA1 TI_CC35XX_PINMUX(3, 8) +#define P3_GPT1_0 TI_CC35XX_PINMUX(3, 9) +#define P3_DCAN_RX (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(3, 10)) +#define P3_WAKE_OBSERVE_BUS_7 TI_CC35XX_PINMUX(3, 11) +#define P3_DEBUG_BUS_0 TI_CC35XX_PINMUX(3, 12) +#define P3_SPI0_CS3 TI_CC35XX_PINMUX(3, 16) +#define P3_XSPI_CS_RAM TI_CC35XX_PINMUX(3, 17) +#define P3_GPT1_1_N TI_CC35XX_PINMUX(3, 18) +#define P3_SDIO_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(3, 19)) +#define P3_COEX_REQ TI_CC35XX_PINMUX(3, 20) +#define P3_GPT0_0_N TI_CC35XX_PINMUX(3, 21) +#define P3_GPT_INFRARED TI_CC35XX_PINMUX(3, 22) +#define P3_ANT_SEL_3 TI_CC35XX_PINMUX(3, 23) +#define P3_BLE_RFC_GPO_7 TI_CC35XX_PINMUX(3, 24) +#define P3_SWO_M3 TI_CC35XX_PINMUX(3, 25) +#define P3_SWO_M33 TI_CC35XX_PINMUX(3, 27) + +#define P4_UART1_RX (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(4, 1)) +#define P4_WIFI_GPIO_4 TI_CC35XX_PINMUX(4, 2) +#define P4_SDIO_MMC_CD TI_CC35XX_PINMUX(4, 3) +#define P4_SPI1_CS1 TI_CC35XX_PINMUX(4, 4) +#define P4_UART1_CTS (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(4, 5)) +#define P4_I2S_BCLK TI_CC35XX_PINMUX(4, 6) +#define P4_I2S_DATA1 TI_CC35XX_PINMUX(4, 7) +#define P4_PDM_BCLK TI_CC35XX_PINMUX(4, 8) +#define P4_GPT1_1 TI_CC35XX_PINMUX(4, 9) +#define P4_DCAN_TX (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(4, 10)) +#define P4_WAKE_OBSERVE_BUS_8 TI_CC35XX_PINMUX(4, 11) +#define P4_DEBUG_BUS_1 TI_CC35XX_PINMUX(4, 12) +#define P4_SPI0_CS2 TI_CC35XX_PINMUX(4, 16) +#define P4_EXT_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(4, 17)) +#define P4_GPT1_0_N TI_CC35XX_PINMUX(4, 18) +#define P4_SDIO_CMD TI_CC35XX_PINMUX(4, 19) +#define P4_COEX_PRIORITY TI_CC35XX_PINMUX(4, 20) +#define P4_GPT0_1_N TI_CC35XX_PINMUX(4, 21) +#define P4_BLE_RFC_GPO_6 TI_CC35XX_PINMUX(4, 24) + +#define P5_XSPI_RESET_RAM TI_CC35XX_PINMUX(5, 1) +#define P5_WIFI_GPIO_5 TI_CC35XX_PINMUX(5, 2) +#define P5_SDIO_MMC_POW2 TI_CC35XX_PINMUX(5, 3) +#define P5_SPI1_MISO TI_CC35XX_PINMUX(5, 4) +#define P5_UART1_TX (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(5, 5)) +#define P5_I2C0_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(5, 6)) +#define P5_I2S_MCLK TI_CC35XX_PINMUX(5, 7) +#define P5_PDM_BCLK TI_CC35XX_PINMUX(5, 8) +#define P5_GPT1_2 TI_CC35XX_PINMUX(5, 9) +#define P5_DCAN_TX (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(5, 10)) +#define P5_JTAG_TDI TI_CC35XX_PINMUX(5, 11) +#define P5_DEBUG_BUS_11 TI_CC35XX_PINMUX(5, 12) +#define P5_SPI0_CS4 TI_CC35XX_PINMUX(5, 16) +#define P5_EXT_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(5, 17)) +#define P5_GPT1_0_N TI_CC35XX_PINMUX(5, 18) +#define P5_SDIO_D0 TI_CC35XX_PINMUX(5, 19) +#define P5_COEX_REQ TI_CC35XX_PINMUX(5, 20) +#define P5_GPT0_2_N TI_CC35XX_PINMUX(5, 21) +#define P5_BLE_RFTRCN TI_CC35XX_PINMUX(5, 22) +#define P5_ANT_SEL_1 TI_CC35XX_PINMUX(5, 23) +#define P5_BLE_RFC_GPI_2 TI_CC35XX_PINMUX(5, 25) +#define P5_I2C1_DATA TI_CC35XX_PINMUX(5, 28) + +#define P6_XSPI_CS_RAM TI_CC35XX_PINMUX(6, 1) +#define P6_WIFI_GPIO_6 TI_CC35XX_PINMUX(6, 2) +#define P6_SDIO_MMC_POW1 TI_CC35XX_PINMUX(6, 3) +#define P6_SPI1_MOSI TI_CC35XX_PINMUX(6, 4) +#define P6_UART1_RX (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(6, 5)) +#define P6_I2C0_DATA TI_CC35XX_PINMUX(6, 6) +#define P6_I2S_WCLK TI_CC35XX_PINMUX(6, 7) +#define P6_PDM_DATA0 TI_CC35XX_PINMUX(6, 8) +#define P6_GPT1_3 TI_CC35XX_PINMUX(6, 9) +#define P6_DCAN_RX (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(6, 10)) +#define P6_SDIO_MMC_WP TI_CC35XX_PINMUX(6, 11) +#define P6_DEBUG_BUS_12 TI_CC35XX_PINMUX(6, 12) +#define P6_SPI0_CS4 TI_CC35XX_PINMUX(6, 16) +#define P6_I2S_BCLK TI_CC35XX_PINMUX(6, 17) +#define P6_GPT1_1_N TI_CC35XX_PINMUX(6, 18) +#define P6_SDIO_D1 TI_CC35XX_PINMUX(6, 19) +#define P6_COEX_PRIORITY TI_CC35XX_PINMUX(6, 20) +#define P6_GPT0_3_N TI_CC35XX_PINMUX(6, 21) +#define P6_GPT1_PRE_EVENT TI_CC35XX_PINMUX(6, 22) +#define P6_ANT_SEL_0 TI_CC35XX_PINMUX(6, 23) +#define P6_CCA TI_CC35XX_PINMUX(6, 24) +#define P6_BLE_RFC_GPI_3 TI_CC35XX_PINMUX(6, 25) +#define P6_COEX_GRANT TI_CC35XX_PINMUX(6, 26) +#define P6_I2C1_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(6, 28)) +#define P6_SDIO_MMC_POW2 TI_CC35XX_PINMUX(6, 29) + +#define P7_SWDIO TI_CC35XX_PINMUX(7, 0) +#define P7_WIFI_GPIO_7 TI_CC35XX_PINMUX(7, 2) +#define P7_SDIO_MMC_POW2 TI_CC35XX_PINMUX(7, 3) +#define P7_JTAG_TMS TI_CC35XX_PINMUX(7, 4) +#define P7_ANT_SEL_0 TI_CC35XX_PINMUX(7, 23) + +#define P8_SWCLK TI_CC35XX_PINMUX(8, 0) +#define P8_WIFI_GPIO_8 TI_CC35XX_PINMUX(8, 2) +#define P8_SDIO_MMC_POW1 TI_CC35XX_PINMUX(8, 3) +#define P8_JTAG_TCK TI_CC35XX_PINMUX(8, 4) +#define P8_ANT_SEL_1 TI_CC35XX_PINMUX(8, 23) + +#define P9_LOGGER TI_CC35XX_PINMUX(9, 1) +#define P9_WIFI_GPIO_9 TI_CC35XX_PINMUX(9, 2) +#define P9_SDIO_MMC_CD TI_CC35XX_PINMUX(9, 3) +#define P9_BLE_RFTRC TI_CC35XX_PINMUX(9, 4) +#define P9_JTAG_TDO TI_CC35XX_PINMUX(9, 11) +#define P9_ANT_SEL_2 TI_CC35XX_PINMUX(9, 23) +#define P9_SWO_M3 TI_CC35XX_PINMUX(9, 26) +#define P9_SWO_M33 TI_CC35XX_PINMUX(9, 27) + +#define P10_UART1_TX (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(10, 1)) +#define P10_WIFI_GPIO_10 TI_CC35XX_PINMUX(10, 2) +#define P10_SDIO_MMC_DATA_3 TI_CC35XX_PINMUX(10, 3) +#define P10_SPI1_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(10, 4)) +#define P10_UART1_RTS (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(10, 5)) +#define P10_I2C1_DATA TI_CC35XX_PINMUX(10, 6) +#define P10_I2S_DATA1 TI_CC35XX_PINMUX(10, 7) +#define P10_PDM_DATA1 TI_CC35XX_PINMUX(10, 8) +#define P10_GPT1_0 TI_CC35XX_PINMUX(10, 9) +#define P10_DCAN_RX (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(10, 10)) +#define P10_UART_RS232_RX (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(10, 11)) +#define P10_DEBUG_BUS_10 TI_CC35XX_PINMUX(10, 12) +#define P10_SPI0_CS3 TI_CC35XX_PINMUX(10, 16) +#define P10_GPT1_3_N TI_CC35XX_PINMUX(10, 18) +#define P10_SDIO_D3 TI_CC35XX_PINMUX(10, 19) +#define P10_COEX_PRIORITY TI_CC35XX_PINMUX(10, 20) +#define P10_COEX_GRANT TI_CC35XX_PINMUX(10, 21) +#define P10_ANT_SEL_2 TI_CC35XX_PINMUX(10, 23) +#define P10_CCA TI_CC35XX_PINMUX(10, 24) +#define P10_BLE_RFC_GPI_1 TI_CC35XX_PINMUX(10, 25) +#define P10_TRDATA_0 TI_CC35XX_PINMUX(10, 26) + +#define P11_UART1_RX (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(11, 1)) +#define P11_WIFI_GPIO_11 TI_CC35XX_PINMUX(11, 2) +#define P11_SDIO_MMC_DATA_2 TI_CC35XX_PINMUX(11, 3) +#define P11_SPI1_CS1 TI_CC35XX_PINMUX(11, 4) +#define P11_UART1_CTS (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(11, 5)) +#define P11_I2C1_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(11, 6)) +#define P11_I2S_DATA0 TI_CC35XX_PINMUX(11, 7) +#define P11_PDM_DATA0 TI_CC35XX_PINMUX(11, 8) +#define P11_GPT1_1 TI_CC35XX_PINMUX(11, 9) +#define P11_DCAN_TX (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(11, 10)) +#define P11_UART_RS232_TX (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(11, 11)) +#define P11_DEBUG_BUS_9 TI_CC35XX_PINMUX(11, 12) +#define P11_SPI0_CS2 TI_CC35XX_PINMUX(11, 16) +#define P11_EXT_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(11, 17)) +#define P11_GPT1_2_N TI_CC35XX_PINMUX(11, 18) +#define P11_SDIO_D2 TI_CC35XX_PINMUX(11, 19) +#define P11_COEX_REQ TI_CC35XX_PINMUX(11, 20) +#define P11_ANT_SEL_3 TI_CC35XX_PINMUX(11, 23) +#define P11_CCA TI_CC35XX_PINMUX(11, 24) +#define P11_SWO_M3 TI_CC35XX_PINMUX(11, 25) +#define P11_TRDATA_1 TI_CC35XX_PINMUX(11, 26) + +#define P12_WIFI_GPIO_12 TI_CC35XX_PINMUX(12, 2) +#define P12_SDIO_MMC_DATA_1 TI_CC35XX_PINMUX(12, 3) +#define P12_SPI1_CS1 TI_CC35XX_PINMUX(12, 4) +#define P12_UART1_RTS (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(12, 5)) +#define P12_UART0_RTS (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(12, 6)) +#define P12_I2S_WCLK TI_CC35XX_PINMUX(12, 7) +#define P12_GPT1_2 TI_CC35XX_PINMUX(12, 9) +#define P12_UART_RS232_TX (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(12, 10)) +#define P12_JTAG_TDO TI_CC35XX_PINMUX(12, 11) +#define P12_DEBUG_BUS_8 TI_CC35XX_PINMUX(12, 12) +#define P12_GPT0_PRE_EVENT TI_CC35XX_PINMUX(12, 16) +#define P12_GPT1_PRE_EVENT TI_CC35XX_PINMUX(12, 17) +#define P12_GPT1_3_N TI_CC35XX_PINMUX(12, 18) +#define P12_SDIO_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(12, 19)) +#define P12_BLE_RFC_GPO_7 TI_CC35XX_PINMUX(12, 22) +#define P12_ANT_SEL_1 TI_CC35XX_PINMUX(12, 23) +#define P12_BLE_RFC_GPI_2 TI_CC35XX_PINMUX(12, 25) +#define P12_TRDATA_2 TI_CC35XX_PINMUX(12, 26) + +#define P13_WIFI_GPIO_13 TI_CC35XX_PINMUX(13, 2) +#define P13_SDIO_MMC_DATA_0 TI_CC35XX_PINMUX(13, 3) +#define P13_SPI1_MOSI TI_CC35XX_PINMUX(13, 4) +#define P13_UART1_CTS (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(13, 5)) +#define P13_UART0_TX (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(13, 6)) +#define P13_I2S_BCLK TI_CC35XX_PINMUX(13, 7) +#define P13_I2S_MCLK TI_CC35XX_PINMUX(13, 8) +#define P13_GPT1_3 TI_CC35XX_PINMUX(13, 9) +#define P13_WAKE_OBSERVE_BUS_14 TI_CC35XX_PINMUX(13, 11) +#define P13_DEBUG_BUS_7 TI_CC35XX_PINMUX(13, 12) +#define P13_GPT1_2_N TI_CC35XX_PINMUX(13, 18) +#define P13_SDIO_CMD TI_CC35XX_PINMUX(13, 19) +#define P13_COEX_PRIORITY TI_CC35XX_PINMUX(13, 20) +#define P13_BLE_RFTRC TI_CC35XX_PINMUX(13, 21) +#define P13_BLE_RFC_GPO_6 TI_CC35XX_PINMUX(13, 22) +#define P13_ANT_SEL_0 TI_CC35XX_PINMUX(13, 23) +#define P13_BLE_RFC_GPI_1 TI_CC35XX_PINMUX(13, 25) +#define P13_TRDATA_3 TI_CC35XX_PINMUX(13, 26) + +#define P14_WIFI_GPIO_14 TI_CC35XX_PINMUX(14, 2) +#define P14_SDIO_MMC_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(14, 3)) +#define P14_SPI1_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(14, 4)) +#define P14_UART1_TX (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(14, 5)) +#define P14_UART0_RX (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(14, 6)) +#define P14_GPT1_0 TI_CC35XX_PINMUX(14, 9) +#define P14_WAKE_OBSERVE_BUS_15 TI_CC35XX_PINMUX(14, 11) +#define P14_DEBUG_BUS_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(14, 12)) +#define P14_SPI0_CS2 TI_CC35XX_PINMUX(14, 16) +#define P14_GPT1_PRE_EVENT TI_CC35XX_PINMUX(14, 17) +#define P14_GPT1_1_N TI_CC35XX_PINMUX(14, 18) +#define P14_SDIO_D0 TI_CC35XX_PINMUX(14, 19) +#define P14_COEX_GRANT TI_CC35XX_PINMUX(14, 20) +#define P14_BLE_RFC_GPO_4 TI_CC35XX_PINMUX(14, 22) +#define P14_BLE_RFC_GPI_2 TI_CC35XX_PINMUX(14, 24) +#define P14_BLE_RFC_GPI_1 TI_CC35XX_PINMUX(14, 25) +#define P14_TRCLK TI_CC35XX_PINMUX(14, 26) +#define P14_DIGITAL_FAST_CLK_IN TI_CC35XX_PINMUX(14, 27) + +#define P15_WIFI_GPIO_15 TI_CC35XX_PINMUX(15, 2) +#define P15_SDIO_MMC_CMD TI_CC35XX_PINMUX(15, 3) +#define P15_SPI1_MISO TI_CC35XX_PINMUX(15, 4) +#define P15_UART1_RX (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(15, 5)) +#define P15_UART0_CTS (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(15, 6)) +#define P15_GPT1_1 TI_CC35XX_PINMUX(15, 9) +#define P15_UART_RS232_RX (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(15, 10)) +#define P15_JTAG_TDI TI_CC35XX_PINMUX(15, 11) +#define P15_DEBUG_BUS_6 TI_CC35XX_PINMUX(15, 12) +#define P15_SPI1_CS2 TI_CC35XX_PINMUX(15, 16) +#define P15_GPT0_PRE_EVENT TI_CC35XX_PINMUX(15, 17) +#define P15_GPT1_0_N TI_CC35XX_PINMUX(15, 18) +#define P15_SDIO_D1 TI_CC35XX_PINMUX(15, 19) +#define P15_COEX_REQ TI_CC35XX_PINMUX(15, 20) +#define P15_BLE_RFTRC TI_CC35XX_PINMUX(15, 21) +#define P15_BLE_RFC_GPO_5 TI_CC35XX_PINMUX(15, 22) +#define P15_BLE_RFC_GPI_3 TI_CC35XX_PINMUX(15, 25) +#define P15_SWO_M3 TI_CC35XX_PINMUX(15, 26) +#define P15_SWO_M33 TI_CC35XX_PINMUX(15, 27) + +#define P16_WIFI_GPIO_16 TI_CC35XX_PINMUX(16, 2) +#define P16_SDIO_MMC_DATA_7 TI_CC35XX_PINMUX(16, 3) +#define P16_SPI0_CS1 TI_CC35XX_PINMUX(16, 4) +#define P16_UART0_RTS (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(16, 5)) +#define P16_I2C1_DATA TI_CC35XX_PINMUX(16, 6) +#define P16_I2S_WCLK TI_CC35XX_PINMUX(16, 7) +#define P16_PDM_BCLK TI_CC35XX_PINMUX(16, 8) +#define P16_GPT0_0 TI_CC35XX_PINMUX(16, 9) +#define P16_UART_RS232_RX (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(16, 10)) +#define P16_WAKE_OBSERVE_BUS_12 TI_CC35XX_PINMUX(16, 11) +#define P16_DEBUG_BUS_5 TI_CC35XX_PINMUX(16, 12) +#define P16_SPI1_CS2 TI_CC35XX_PINMUX(16, 16) +#define P16_GPT0_1_N TI_CC35XX_PINMUX(16, 18) +#define P16_SDIO_D2 TI_CC35XX_PINMUX(16, 19) +#define P16_GPT1_0_N TI_CC35XX_PINMUX(16, 21) +#define P16_GPT_INFRARED TI_CC35XX_PINMUX(16, 22) +#define P16_ANT_SEL_0 TI_CC35XX_PINMUX(16, 23) +#define P16_TRDATA_0 TI_CC35XX_PINMUX(16, 26) + +#define P17_SDIO_MMC_WP TI_CC35XX_PINMUX(17, 1) +#define P17_WIFI_GPIO_17 TI_CC35XX_PINMUX(17, 2) +#define P17_SDIO_MMC_DATA_6 TI_CC35XX_PINMUX(17, 3) +#define P17_SPI0_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(17, 4)) +#define P17_UART0_TX (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(17, 5)) +#define P17_I2C0_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(17, 6)) +#define P17_I2S_DATA1 TI_CC35XX_PINMUX(17, 7) +#define P17_PDM_DATA0 TI_CC35XX_PINMUX(17, 8) +#define P17_GPT0_1 TI_CC35XX_PINMUX(17, 9) +#define P17_UART_RS232_TX (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(17, 10)) +#define P17_WAKE_OBSERVE_BUS_9 TI_CC35XX_PINMUX(17, 11) +#define P17_DEBUG_BUS_2 TI_CC35XX_PINMUX(17, 12) +#define P17_SPI1_CS3 TI_CC35XX_PINMUX(17, 16) +#define P17_SDIO_OOB_IRQ TI_CC35XX_PINMUX(17, 17) +#define P17_GPT0_0_N TI_CC35XX_PINMUX(17, 18) +#define P17_COEX_GRANT TI_CC35XX_PINMUX(17, 20) +#define P17_GPT1_1_N TI_CC35XX_PINMUX(17, 21) +#define P17_ANT_SEL_1 TI_CC35XX_PINMUX(17, 23) +#define P17_TRDATA_1 TI_CC35XX_PINMUX(17, 26) + +#define P18_WIFI_GPIO_18 TI_CC35XX_PINMUX(18, 2) +#define P18_SDIO_MMC_DATA_5 TI_CC35XX_PINMUX(18, 3) +#define P18_SPI0_MISO TI_CC35XX_PINMUX(18, 4) +#define P18_UART0_RX (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(18, 5)) +#define P18_I2C0_DATA TI_CC35XX_PINMUX(18, 6) +#define P18_I2S_DATA0 TI_CC35XX_PINMUX(18, 7) +#define P18_PDM_DATA1 TI_CC35XX_PINMUX(18, 8) +#define P18_GPT0_2 TI_CC35XX_PINMUX(18, 9) +#define P18_DCAN_TX (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(18, 10)) +#define P18_WAKE_OBSERVE_BUS_10 TI_CC35XX_PINMUX(18, 11) +#define P18_DEBUG_BUS_3 TI_CC35XX_PINMUX(18, 12) +#define P18_SPI1_CS4 TI_CC35XX_PINMUX(18, 16) +#define P18_SDIO_OOB_IRQ TI_CC35XX_PINMUX(18, 17) +#define P18_GPT0_0_N TI_CC35XX_PINMUX(18, 18) +#define P18_COEX_REQ TI_CC35XX_PINMUX(18, 20) +#define P18_GPT1_2_N TI_CC35XX_PINMUX(18, 21) +#define P18_ANT_SEL_2 TI_CC35XX_PINMUX(18, 23) +#define P18_TRDATA_2 TI_CC35XX_PINMUX(18, 26) + +#define P19_WIFI_GPIO_19 TI_CC35XX_PINMUX(19, 2) +#define P19_SDIO_MMC_DATA_4 TI_CC35XX_PINMUX(19, 3) +#define P19_SPI0_MOSI TI_CC35XX_PINMUX(19, 4) +#define P19_UART0_CTS (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(19, 5)) +#define P19_I2C1_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(19, 6)) +#define P19_I2S_BCLK TI_CC35XX_PINMUX(19, 7) +#define P19_PDM_DATA0 TI_CC35XX_PINMUX(19, 8) +#define P19_GPT0_3 TI_CC35XX_PINMUX(19, 9) +#define P19_DCAN_RX (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(19, 10)) +#define P19_WAKE_OBSERVE_BUS_11 TI_CC35XX_PINMUX(19, 11) +#define P19_DEBUG_BUS_4 TI_CC35XX_PINMUX(19, 12) +#define P19_GPT0_PRE_EVENT TI_CC35XX_PINMUX(19, 16) +#define P19_SDIO_OOB_IRQ TI_CC35XX_PINMUX(19, 17) +#define P19_GPT0_1_N TI_CC35XX_PINMUX(19, 18) +#define P19_SDIO_D3 TI_CC35XX_PINMUX(19, 19) +#define P19_COEX_PRIORITY TI_CC35XX_PINMUX(19, 20) +#define P19_GPT1_3_N TI_CC35XX_PINMUX(19, 21) +#define P19_GPT_INFRARED TI_CC35XX_PINMUX(19, 22) +#define P19_ANT_SEL_3 TI_CC35XX_PINMUX(19, 23) +#define P19_TRDATA_3 TI_CC35XX_PINMUX(19, 26) + +#define P20_XSPI_CS_FLASH TI_CC35XX_PINMUX(20, 0) +#define P20_WIFI_GPIO_20 TI_CC35XX_PINMUX(20, 2) + +#define P21_XSPI_DATA_1 TI_CC35XX_PINMUX(21, 0) +#define P21_WIFI_GPIO_21 TI_CC35XX_PINMUX(21, 2) + +#define P22_XSPI_DATA_2 TI_CC35XX_PINMUX(22, 0) +#define P22_WIFI_GPIO_22 TI_CC35XX_PINMUX(22, 2) + +#define P23_XSPI_DATA_3 TI_CC35XX_PINMUX(23, 0) +#define P23_WIFI_GPIO_23 TI_CC35XX_PINMUX(23, 2) + +#define P24_XSPI_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(24, 0)) +#define P24_WIFI_GPIO_24 TI_CC35XX_PINMUX(24, 2) + +#define P25_XSPI_DATA_0 TI_CC35XX_PINMUX(25, 0) +#define P25_WIFI_GPIO_25 TI_CC35XX_PINMUX(25, 2) + +#define P26_XSPI_DATA_4 TI_CC35XX_PINMUX(26, 1) +#define P26_WIFI_GPIO_26 TI_CC35XX_PINMUX(26, 2) +#define P26_SPI0_CS1 TI_CC35XX_PINMUX(26, 4) +#define P26_UART0_RTS (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(26, 5)) +#define P26_I2C1_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(26, 6)) +#define P26_I2S_WCLK TI_CC35XX_PINMUX(26, 7) +#define P26_PDM_BCLK TI_CC35XX_PINMUX(26, 8) +#define P26_GPT0_0 TI_CC35XX_PINMUX(26, 9) +#define P26_DCAN_TX (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(26, 10)) +#define P26_WAKE_OBSERVE_BUS_0 TI_CC35XX_PINMUX(26, 11) +#define P26_DEBUG_BUS_13 TI_CC35XX_PINMUX(26, 12) +#define P26_SPI1_CS2 TI_CC35XX_PINMUX(26, 16) +#define P26_EXT_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(26, 17)) +#define P26_GPT0_1_N TI_CC35XX_PINMUX(26, 18) +#define P26_GPT1_0_N TI_CC35XX_PINMUX(26, 19) +#define P26_COEX_GRANT TI_CC35XX_PINMUX(26, 20) +#define P26_COEX_REQ TI_CC35XX_PINMUX(26, 21) +#define P26_BLE_RFC_GPO_4 TI_CC35XX_PINMUX(26, 22) +#define P26_ANT_SEL_0 TI_CC35XX_PINMUX(26, 23) +#define P26_GPT_INFRARED TI_CC35XX_PINMUX(26, 24) +#define P26_BLE_RFC_GPI_1 TI_CC35XX_PINMUX(26, 25) +#define P26_BLE_RFC_GPI_3 TI_CC35XX_PINMUX(26, 26) +#define P26_SDIO_OOB_IRQ TI_CC35XX_PINMUX(26, 30) + +#define P27_XSPI_DATA_5 TI_CC35XX_PINMUX(27, 1) +#define P27_WIFI_GPIO_27 TI_CC35XX_PINMUX(27, 2) +#define P27_SPI0_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(27, 4)) +#define P27_UART0_TX (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(27, 5)) +#define P27_I2C0_DATA TI_CC35XX_PINMUX(27, 6) +#define P27_I2S_DATA0 TI_CC35XX_PINMUX(27, 7) +#define P27_PDM_DATA0 TI_CC35XX_PINMUX(27, 8) +#define P27_GPT0_1 TI_CC35XX_PINMUX(27, 9) +#define P27_WAKE_OBSERVE_BUS_1 TI_CC35XX_PINMUX(27, 11) +#define P27_DEBUG_BUS_14 TI_CC35XX_PINMUX(27, 12) +#define P27_SPI1_CS3 TI_CC35XX_PINMUX(27, 16) +#define P27_GPT0_0_N TI_CC35XX_PINMUX(27, 18) +#define P27_GPT1_1_N TI_CC35XX_PINMUX(27, 19) +#define P27_COEX_REQ TI_CC35XX_PINMUX(27, 20) +#define P27_BLE_RFC_GPO_5 TI_CC35XX_PINMUX(27, 22) +#define P27_ANT_SEL_1 TI_CC35XX_PINMUX(27, 23) +#define P27_BLE_RFC_GPI_2 TI_CC35XX_PINMUX(27, 25) + +#define P28_XSPI_DATA_6 TI_CC35XX_PINMUX(28, 1) +#define P28_WIFI_GPIO_28 TI_CC35XX_PINMUX(28, 2) +#define P28_SPI0_MISO TI_CC35XX_PINMUX(28, 4) +#define P28_UART0_RX (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(28, 5)) +#define P28_I2C0_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(28, 6)) +#define P28_I2S_DATA1 TI_CC35XX_PINMUX(28, 7) +#define P28_PDM_BCLK TI_CC35XX_PINMUX(28, 8) +#define P28_GPT0_2 TI_CC35XX_PINMUX(28, 9) +#define P28_WAKE_OBSERVE_BUS_2 TI_CC35XX_PINMUX(28, 11) +#define P28_DEBUG_BUS_15 TI_CC35XX_PINMUX(28, 12) +#define P28_SPI1_CS4 TI_CC35XX_PINMUX(28, 16) +#define P28_GPT0_0_N TI_CC35XX_PINMUX(28, 18) +#define P28_GPT1_2_N TI_CC35XX_PINMUX(28, 19) +#define P28_COEX_PRIORITY TI_CC35XX_PINMUX(28, 20) +#define P28_BLE_RFC_GPO_6 TI_CC35XX_PINMUX(28, 22) +#define P28_ANT_SEL_2 TI_CC35XX_PINMUX(28, 23) +#define P28_GPT0_PRE_EVENT TI_CC35XX_PINMUX(28, 24) +#define P28_BLE_RFC_GPI_3 TI_CC35XX_PINMUX(28, 25) + +#define P29_XSPI_DATA_7 TI_CC35XX_PINMUX(29, 1) +#define P29_WIFI_GPIO_29 TI_CC35XX_PINMUX(29, 2) +#define P29_SPI0_MOSI TI_CC35XX_PINMUX(29, 4) +#define P29_UART0_CTS (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(29, 5)) +#define P29_I2C1_DATA TI_CC35XX_PINMUX(29, 6) +#define P29_I2S_BCLK TI_CC35XX_PINMUX(29, 7) +#define P29_PDM_DATA1 TI_CC35XX_PINMUX(29, 8) +#define P29_GPT0_3 TI_CC35XX_PINMUX(29, 9) +#define P29_DCAN_RX (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(29, 10)) +#define P29_WAKE_OBSERVE_BUS_3 TI_CC35XX_PINMUX(29, 11) +#define P29_I2S_MCLK TI_CC35XX_PINMUX(29, 12) +#define P29_SPI1_CS4 TI_CC35XX_PINMUX(29, 16) +#define P29_EXT_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(29, 17)) +#define P29_GPT0_1_N TI_CC35XX_PINMUX(29, 18) +#define P29_GPT1_3_N TI_CC35XX_PINMUX(29, 19) +#define P29_BLE_RFC_GPO_7 TI_CC35XX_PINMUX(29, 22) +#define P29_ANT_SEL_3 TI_CC35XX_PINMUX(29, 23) +#define P29_SDIO_OOB_IRQ TI_CC35XX_PINMUX(29, 30) + +#define P30_XSPI_DQS TI_CC35XX_PINMUX(30, 1) +#define P30_WIFI_GPIO_30 TI_CC35XX_PINMUX(30, 2) +#define P30_XSPI_RESET_FLASH TI_CC35XX_PINMUX(30, 3) +#define P30_XSPI_RESET_RAM TI_CC35XX_PINMUX(30, 4) +#define P30_I2C1_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(30, 5)) +#define P30_I2C0_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(30, 6)) +#define P30_I2S_DATA0 TI_CC35XX_PINMUX(30, 7) +#define P30_PDM_DATA0 TI_CC35XX_PINMUX(30, 8) +#define P30_GPT1_1 TI_CC35XX_PINMUX(30, 9) +#define P30_DCAN_TX (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(30, 10)) +#define P30_WAKE_OBSERVE_BUS_4 TI_CC35XX_PINMUX(30, 11) +#define P30_XSPI_CS_RAM TI_CC35XX_PINMUX(30, 12) +#define P30_SPI0_CS2 TI_CC35XX_PINMUX(30, 16) +#define P30_GPT0_2_N TI_CC35XX_PINMUX(30, 18) +#define P30_COEX_GRANT TI_CC35XX_PINMUX(30, 19) +#define P30_COEX_REQ TI_CC35XX_PINMUX(30, 20) +#define P30_BLE_RFTRC TI_CC35XX_PINMUX(30, 21) +#define P30_BLE_RFC_GPO_4 TI_CC35XX_PINMUX(30, 22) +#define P30_ANT_SEL_0 TI_CC35XX_PINMUX(30, 23) +#define P30_CCA TI_CC35XX_PINMUX(30, 24) +#define P30_BLE_RFC_GPI_1 TI_CC35XX_PINMUX(30, 25) +#define P30_SWO_M3 TI_CC35XX_PINMUX(30, 26) +#define P30_SWO_M33 TI_CC35XX_PINMUX(30, 27) +#define P30_GPT1_PRE_EVENT TI_CC35XX_PINMUX(30, 28) +#define P30_GPT0_PRE_EVENT TI_CC35XX_PINMUX(30, 29) +#define P30_SDIO_D3 TI_CC35XX_PINMUX(30, 30) + +#define P31_XSPI_CS_RAM TI_CC35XX_PINMUX(31, 1) +#define P31_WIFI_GPIO_31 TI_CC35XX_PINMUX(31, 2) +#define P31_XSPI_RESET_FLASH TI_CC35XX_PINMUX(31, 3) +#define P31_SPI1_CS1 TI_CC35XX_PINMUX(31, 4) +#define P31_UART1_RTS (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(31, 5)) +#define P31_I2C1_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(31, 6)) +#define P31_I2S_WCLK TI_CC35XX_PINMUX(31, 7) +#define P31_PDM_BCLK TI_CC35XX_PINMUX(31, 8) +#define P31_GPT1_0 TI_CC35XX_PINMUX(31, 9) +#define P31_DCAN_TX (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(31, 10)) +#define P31_SPI0_CS3 TI_CC35XX_PINMUX(31, 16) +#define P31_EXT_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(31, 17)) +#define P31_GPT1_1_N TI_CC35XX_PINMUX(31, 18) +#define P31_GPT0_0_N TI_CC35XX_PINMUX(31, 19) +#define P31_COEX_GRANT TI_CC35XX_PINMUX(31, 20) +#define P31_BLE_RFC_GPO_6 TI_CC35XX_PINMUX(31, 22) +#define P31_ANT_SEL_0 TI_CC35XX_PINMUX(31, 23) +#define P31_GPT_INFRARED TI_CC35XX_PINMUX(31, 24) +#define P31_BLE_RFC_GPI_3 TI_CC35XX_PINMUX(31, 25) +#define P31_SDIO_D2 TI_CC35XX_PINMUX(31, 30) + +#define P32_XSPI_CS_RAM TI_CC35XX_PINMUX(32, 1) +#define P32_WIFI_GPIO_32 TI_CC35XX_PINMUX(32, 2) +#define P32_SPI1_CS1 TI_CC35XX_PINMUX(32, 3) +#define P32_SPI1_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(32, 4)) +#define P32_UART1_TX (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(32, 5)) +#define P32_I2C0_DATA TI_CC35XX_PINMUX(32, 6) +#define P32_I2S_DATA1 TI_CC35XX_PINMUX(32, 7) +#define P32_PDM_BCLK TI_CC35XX_PINMUX(32, 8) +#define P32_GPT1_1 TI_CC35XX_PINMUX(32, 9) +#define P32_DCAN_RX (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(32, 10)) +#define P32_WAKE_OBSERVE_BUS_5 TI_CC35XX_PINMUX(32, 11) +#define P32_SPI0_CS3 TI_CC35XX_PINMUX(32, 16) +#define P32_GPT1_0_N TI_CC35XX_PINMUX(32, 18) +#define P32_GPT0_1_N TI_CC35XX_PINMUX(32, 19) +#define P32_COEX_REQ TI_CC35XX_PINMUX(32, 20) +#define P32_ANT_SEL_1 TI_CC35XX_PINMUX(32, 23) +#define P32_SDIO_D1 TI_CC35XX_PINMUX(32, 30) + +#define P33_WIFI_GPIO_33 TI_CC35XX_PINMUX(33, 2) +#define P33_SPI1_MISO TI_CC35XX_PINMUX(33, 4) +#define P33_UART1_RX (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(33, 5)) +#define P33_I2C0_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(33, 6)) +#define P33_I2S_DATA0 TI_CC35XX_PINMUX(33, 7) +#define P33_PDM_DATA0 TI_CC35XX_PINMUX(33, 8) +#define P33_GPT1_2 TI_CC35XX_PINMUX(33, 9) +#define P33_DCAN_TX (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(33, 10)) +#define P33_SPI0_CS4 TI_CC35XX_PINMUX(33, 16) +#define P33_GPT1_0_N TI_CC35XX_PINMUX(33, 18) +#define P33_GPT0_2_N TI_CC35XX_PINMUX(33, 19) +#define P33_COEX_GRANT TI_CC35XX_PINMUX(33, 20) +#define P33_ANT_SEL_2 TI_CC35XX_PINMUX(33, 23) +#define P33_GPT1_PRE_EVENT TI_CC35XX_PINMUX(33, 24) +#define P33_BLE_RFC_GPI_2 TI_CC35XX_PINMUX(33, 25) +#define P33_SDIO_D0 TI_CC35XX_PINMUX(33, 30) + +#define P34_XSPI_RESET_RAM TI_CC35XX_PINMUX(34, 1) +#define P34_WIFI_GPIO_34 TI_CC35XX_PINMUX(34, 2) +#define P34_SPI1_MOSI TI_CC35XX_PINMUX(34, 4) +#define P34_UART1_CTS (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(34, 5)) +#define P34_I2C1_DATA TI_CC35XX_PINMUX(34, 6) +#define P34_I2S_BCLK TI_CC35XX_PINMUX(34, 7) +#define P34_PDM_DATA1 TI_CC35XX_PINMUX(34, 8) +#define P34_GPT1_3 TI_CC35XX_PINMUX(34, 9) +#define P34_DCAN_RX (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(34, 10)) +#define P34_SPI0_CS2 TI_CC35XX_PINMUX(34, 16) +#define P34_GPT1_1_N TI_CC35XX_PINMUX(34, 18) +#define P34_GPT0_3_N TI_CC35XX_PINMUX(34, 19) +#define P34_COEX_REQ TI_CC35XX_PINMUX(34, 20) +#define P34_BLE_RFC_GPO_7 TI_CC35XX_PINMUX(34, 22) +#define P34_ANT_SEL_3 TI_CC35XX_PINMUX(34, 23) +#define P34_BLE_RFC_GPI_1 TI_CC35XX_PINMUX(34, 25) +#define P34_SDIO_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(34, 30)) + +#define P35_XSPI_RESET_FLASH TI_CC35XX_PINMUX(35, 1) +#define P35_WIFI_GPIO_35 TI_CC35XX_PINMUX(35, 2) +#define P35_SPI1_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(35, 3)) +#define P35_XSPI_RESET_RAM TI_CC35XX_PINMUX(35, 4) +#define P35_UART1_RX (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(35, 5)) +#define P35_I2C0_DATA TI_CC35XX_PINMUX(35, 6) +#define P35_I2S_DATA1 TI_CC35XX_PINMUX(35, 7) +#define P35_PDM_BCLK TI_CC35XX_PINMUX(35, 8) +#define P35_GPT0_1 TI_CC35XX_PINMUX(35, 9) +#define P35_DCAN_RX (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(35, 10)) +#define P35_I2C1_DATA TI_CC35XX_PINMUX(35, 11) +#define P35_XSPI_CS_RAM TI_CC35XX_PINMUX(35, 12) +#define P35_SPI0_CS4 TI_CC35XX_PINMUX(35, 16) +#define P35_SPI0_CS3 TI_CC35XX_PINMUX(35, 17) +#define P35_GPT0_2_N TI_CC35XX_PINMUX(35, 18) +#define P35_GPT1_2_N TI_CC35XX_PINMUX(35, 19) +#define P35_COEX_PRIORITY TI_CC35XX_PINMUX(35, 20) +#define P35_BLE_RFTRC TI_CC35XX_PINMUX(35, 21) +#define P35_BLE_RFC_GPO_5 TI_CC35XX_PINMUX(35, 22) +#define P35_ANT_SEL_0 TI_CC35XX_PINMUX(35, 23) +#define P35_GPT1_PRE_EVENT TI_CC35XX_PINMUX(35, 24) +#define P35_BLE_RFC_GPI_2 TI_CC35XX_PINMUX(35, 25) +#define P35_SWO_M3 TI_CC35XX_PINMUX(35, 26) +#define P35_SWO_M33 TI_CC35XX_PINMUX(35, 27) +#define P35_XSPI_DQS TI_CC35XX_PINMUX(35, 28) +#define P35_COEX_REQ TI_CC35XX_PINMUX(35, 29) +#define P35_SDIO_CMD TI_CC35XX_PINMUX(35, 30) + +#define P36_XSPI_CS_RAM TI_CC35XX_PINMUX(36, 1) +#define P36_WIFI_GPIO_36 TI_CC35XX_PINMUX(36, 2) +#define P36_SDIO_MMC_POW2 TI_CC35XX_PINMUX(36, 3) +#define P36_SDIO_MMC_WP TI_CC35XX_PINMUX(36, 4) +#define P36_WAKE_OBSERVE_BUS_13 TI_CC35XX_PINMUX(36, 11) +#define P36_DEBUG_BUS_1 TI_CC35XX_PINMUX(36, 12) +#define P36_FAST_CLK_REQ TI_CC35XX_PINMUX(36, 21) +#define P36_BLE_RFC_GPO_5 TI_CC35XX_PINMUX(36, 22) +#define P36_ANT_SEL_1 TI_CC35XX_PINMUX(36, 23) +#define P36_CCA TI_CC35XX_PINMUX(36, 24) +#define P36_BLE_RFC_GPI_2 TI_CC35XX_PINMUX(36, 25) + +#define P37_XSPI_CS_RAM TI_CC35XX_PINMUX(37, 1) +#define P37_WIFI_GPIO_37 TI_CC35XX_PINMUX(37, 2) +#define P37_SDIO_MMC_POW1 TI_CC35XX_PINMUX(37, 3) +#define P37_SDIO_MMC_WP TI_CC35XX_PINMUX(37, 4) +#define P37_WAKE_OBSERVE_BUS_12 TI_CC35XX_PINMUX(37, 11) +#define P37_DEBUG_BUS_0 TI_CC35XX_PINMUX(37, 12) +#define P37_SDIO_OOB_IRQ TI_CC35XX_PINMUX(37, 19) +#define P37_COEX_GRANT TI_CC35XX_PINMUX(37, 20) +#define P37_FAST_CLK_REQ TI_CC35XX_PINMUX(37, 21) +#define P37_BLE_RFC_GPO_4 TI_CC35XX_PINMUX(37, 22) +#define P37_ANT_SEL_0 TI_CC35XX_PINMUX(37, 23) +#define P37_CCA TI_CC35XX_PINMUX(37, 24) +#define P37_BLE_RFC_GPI_1 TI_CC35XX_PINMUX(37, 25) + +#define P38_XSPI_CS_RAM TI_CC35XX_PINMUX(38, 1) +#define P38_WIFI_GPIO_38 TI_CC35XX_PINMUX(38, 2) +#define P38_EXT_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(38, 3)) +#define P38_SPI1_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(38, 4)) +#define P38_UART0_CTS (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(38, 5)) +#define P38_I2C1_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(38, 6)) +#define P38_I2S_BCLK TI_CC35XX_PINMUX(38, 7) +#define P38_PDM_BCLK TI_CC35XX_PINMUX(38, 8) +#define P38_GPT1_0 TI_CC35XX_PINMUX(38, 9) +#define P38_DCAN_TX (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(38, 10)) +#define P38_GPT1_1_N TI_CC35XX_PINMUX(38, 18) +#define P38_COEX_GRANT TI_CC35XX_PINMUX(38, 20) +#define P38_ANT_SEL_0 TI_CC35XX_PINMUX(38, 23) +#define P38_COEX_REQ TI_CC35XX_PINMUX(38, 29) + +#define P39_XSPI_RESET_RAM TI_CC35XX_PINMUX(39, 1) +#define P39_WIFI_GPIO_39 TI_CC35XX_PINMUX(39, 2) +#define P39_UART0_RX (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(39, 3)) +#define P39_SPI1_MISO TI_CC35XX_PINMUX(39, 4) +#define P39_UART0_RTS (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(39, 5)) +#define P39_I2C1_DATA TI_CC35XX_PINMUX(39, 6) +#define P39_I2S_WCLK TI_CC35XX_PINMUX(39, 7) +#define P39_PDM_DATA0 TI_CC35XX_PINMUX(39, 8) +#define P39_GPT1_1 TI_CC35XX_PINMUX(39, 9) +#define P39_DCAN_RX (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(39, 10)) +#define P39_XSPI_DQS TI_CC35XX_PINMUX(39, 11) +#define P39_GPT1_0_N TI_CC35XX_PINMUX(39, 18) +#define P39_COEX_REQ TI_CC35XX_PINMUX(39, 20) +#define P39_ANT_SEL_1 TI_CC35XX_PINMUX(39, 23) +#define P39_COEX_PRIORITY TI_CC35XX_PINMUX(39, 29) + +#define P40_XSPI_CS_RAM TI_CC35XX_PINMUX(40, 1) +#define P40_WIFI_GPIO_40 TI_CC35XX_PINMUX(40, 2) +#define P40_SPI1_MOSI TI_CC35XX_PINMUX(40, 4) +#define P40_UART0_TX (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(40, 5)) +#define P40_I2S_DATA0 TI_CC35XX_PINMUX(40, 7) +#define P40_PDM_DATA1 TI_CC35XX_PINMUX(40, 8) +#define P40_GPT1_2 TI_CC35XX_PINMUX(40, 9) +#define P40_GPT1_PRE_EVENT TI_CC35XX_PINMUX(40, 16) +#define P40_GPT0_PRE_EVENT TI_CC35XX_PINMUX(40, 17) +#define P40_GPT1_2_N TI_CC35XX_PINMUX(40, 18) +#define P40_COEX_PRIORITY TI_CC35XX_PINMUX(40, 20) +#define P40_GPT_INFRARED TI_CC35XX_PINMUX(40, 22) +#define P40_ANT_SEL_2 TI_CC35XX_PINMUX(40, 23) +#define P40_COEX_GRANT TI_CC35XX_PINMUX(40, 29) + +#define P41_XSPI_CS_RAM TI_CC35XX_PINMUX(41, 1) +#define P41_WIFI_GPIO_41 TI_CC35XX_PINMUX(41, 2) +#define P41_SPI1_MISO TI_CC35XX_PINMUX(41, 4) +#define P41_UART1_CTS (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(41, 5)) +#define P41_I2S_DATA0 TI_CC35XX_PINMUX(41, 7) +#define P41_GPT0_0 TI_CC35XX_PINMUX(41, 9) +#define P41_GPT1_PRE_EVENT TI_CC35XX_PINMUX(41, 16) +#define P41_GPT0_PRE_EVENT TI_CC35XX_PINMUX(41, 17) +#define P41_GPT0_1_N TI_CC35XX_PINMUX(41, 18) +#define P41_GPT_INFRARED TI_CC35XX_PINMUX(41, 22) +#define P41_ANT_SEL_0 TI_CC35XX_PINMUX(41, 23) +#define P41_COEX_GRANT TI_CC35XX_PINMUX(41, 29) + +#define P42_XSPI_RESET_RAM TI_CC35XX_PINMUX(42, 1) +#define P42_WIFI_GPIO_42 TI_CC35XX_PINMUX(42, 2) +#define P42_UART1_RX (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(42, 3)) +#define P42_SPI1_MOSI TI_CC35XX_PINMUX(42, 4) +#define P42_UART1_RTS (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(42, 5)) +#define P42_I2C0_DATA TI_CC35XX_PINMUX(42, 6) +#define P42_I2S_WCLK TI_CC35XX_PINMUX(42, 7) +#define P42_PDM_DATA0 TI_CC35XX_PINMUX(42, 8) +#define P42_GPT0_1 TI_CC35XX_PINMUX(42, 9) +#define P42_DCAN_RX (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(42, 10)) +#define P42_XSPI_DQS TI_CC35XX_PINMUX(42, 11) +#define P42_GPT0_0_N TI_CC35XX_PINMUX(42, 18) +#define P42_ANT_SEL_1 TI_CC35XX_PINMUX(42, 23) +#define P42_COEX_REQ TI_CC35XX_PINMUX(42, 29) + +#define P43_XSPI_CS_RAM TI_CC35XX_PINMUX(43, 1) +#define P43_WIFI_GPIO_43 TI_CC35XX_PINMUX(43, 2) +#define P43_SPI1_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(43, 4)) +#define P43_UART1_TX (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(43, 5)) +#define P43_I2C0_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(43, 6)) +#define P43_I2S_BCLK TI_CC35XX_PINMUX(43, 7) +#define P43_PDM_BCLK TI_CC35XX_PINMUX(43, 8) +#define P43_GPT0_2 TI_CC35XX_PINMUX(43, 9) +#define P43_DCAN_TX (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(43, 10)) +#define P43_GPT0_2_N TI_CC35XX_PINMUX(43, 18) +#define P43_ANT_SEL_2 TI_CC35XX_PINMUX(43, 23) +#define P43_COEX_PRIORITY TI_CC35XX_PINMUX(43, 29) + +#define P44_XSPI_CLK_INPUT TI_CC35XX_PINMUX(44, 0) +#define P44_WIFI_GPIO_44 TI_CC35XX_PINMUX(44, 2) + +/** @} */ + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_TI_CC35XX_PINCTRL_H_ */ From fb12fefa85c6f10e80c28b7a3ad8510a938265d0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=81yszczek?= Date: Tue, 29 Jul 2025 14:10:01 +0200 Subject: [PATCH 005/100] UPSTREAM-PEND: drivers: serial: cc35xxe: Initial commit for serial MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for CC35xxE serial port Signed-off-by: Michał Łyszczek Signed-off-by: Jacek Ozimek Signed-off-by: Jakub Jarosinski --- boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts | 22 ++ boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml | 1 + boards/ti/lp_em_cc35x1/lp_em_cc35x1_defconfig | 9 + drivers/serial/CMakeLists.txt | 1 + drivers/serial/Kconfig | 1 + drivers/serial/Kconfig.cc35xx | 13 + drivers/serial/uart_cc35xx.c | 247 ++++++++++++++++++ dts/arm/ti/cc35xxe.dtsi | 13 + dts/bindings/serial/ti,cc35xx-uart.yaml | 15 ++ 9 files changed, 322 insertions(+) create mode 100644 drivers/serial/Kconfig.cc35xx create mode 100644 drivers/serial/uart_cc35xx.c create mode 100644 dts/bindings/serial/ti,cc35xx-uart.yaml diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts b/boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts index a6609d6538eb..7c97ad9d1fc9 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts @@ -19,6 +19,8 @@ zephyr,itcm = &itcm_ns; zephyr,dtcm = &dtcm_ns; zephyr,code-partition = &dmem_ns; + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; }; }; @@ -46,3 +48,23 @@ &dtcm { status = "okay"; }; + +&dma { + status = "okay"; +}; + +&uart0 { + status = "okay"; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; + dmas = <&dma 2>, <&dma 3>; + dma-names = "tx", "rx"; +}; + +&uart1 { + status = "okay"; + pinctrl-0 = <&uart1_default>; + pinctrl-names = "default"; + dmas = <&dma 0>, <&dma 1>; + dma-names = "tx", "rx"; +}; diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml b/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml index 40ec537cdc52..8344850c540f 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml @@ -9,4 +9,5 @@ toolchain: - gnuarmemb supported: - pinctrl + - serial vendor: ti diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_defconfig b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_defconfig index f46e2280bd2d..920a82db37d2 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_defconfig +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_defconfig @@ -3,3 +3,12 @@ # # SPDX-License-Identifier: Apache-2.0 # + +CONFIG_SERIAL=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SHELL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN=y +CONFIG_SHELL_BACKEND_SERIAL_API_INTERRUPT_DRIVEN=y diff --git a/drivers/serial/CMakeLists.txt b/drivers/serial/CMakeLists.txt index 4869c292b981..8c683edaebc0 100644 --- a/drivers/serial/CMakeLists.txt +++ b/drivers/serial/CMakeLists.txt @@ -32,6 +32,7 @@ zephyr_library_sources_ifdef(CONFIG_UART_BT uart_bt.c) zephyr_library_sources_ifdef(CONFIG_UART_CC13XX_CC26XX uart_cc13xx_cc26xx.c) zephyr_library_sources_ifdef(CONFIG_UART_CC23X0 uart_cc23x0.c) zephyr_library_sources_ifdef(CONFIG_UART_CC32XX uart_cc32xx.c) +zephyr_library_sources_ifdef(CONFIG_UART_CC35XX uart_cc35xx.c) zephyr_library_sources_ifdef(CONFIG_UART_CDNS uart_cdns.c) zephyr_library_sources_ifdef(CONFIG_UART_CMSDK_APB uart_cmsdk_apb.c) zephyr_library_sources_ifdef(CONFIG_UART_EFINIX_SAPPIHIRE uart_efinix_sapphire.c) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index ade5630b9773..05e7c1792045 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -173,6 +173,7 @@ rsource "Kconfig.bt" rsource "Kconfig.cc13xx_cc26xx" rsource "Kconfig.cc23x0" rsource "Kconfig.cc32xx" +rsource "Kconfig.cc35xx" rsource "Kconfig.cdns" rsource "Kconfig.cmsdk_apb" rsource "Kconfig.efinix_sapphire" diff --git a/drivers/serial/Kconfig.cc35xx b/drivers/serial/Kconfig.cc35xx new file mode 100644 index 000000000000..a92424e6fcf2 --- /dev/null +++ b/drivers/serial/Kconfig.cc35xx @@ -0,0 +1,13 @@ +# Copyright (c) 2025 Conclusive Engineering Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +config UART_CC35XX + bool "CC35XX UART driver" + default y + depends on DT_HAS_TI_CC35XX_UART_ENABLED + select SERIAL_HAS_DRIVER + select SERIAL_SUPPORT_INTERRUPT + select SERIAL_SUPPORT_ASYNC + select PINCTRL + help + This option enables the CC35XX UART driver diff --git a/drivers/serial/uart_cc35xx.c b/drivers/serial/uart_cc35xx.c new file mode 100644 index 000000000000..4bcd85b96d13 --- /dev/null +++ b/drivers/serial/uart_cc35xx.c @@ -0,0 +1,247 @@ +/* + * Copyright (c) 2025 Conclusive Engineering Sp. z o.o. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT ti_cc35xx_uart + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +LOG_MODULE_REGISTER(uart_cc35xx); + +struct uart_cc35xx_dev_config { + unsigned long base; + uint32_t sys_clk_freq; + const struct pinctrl_dev_config *pcfg; +#ifdef CONFIG_UART_INTERRUPT_DRIVEN + uart_irq_config_func_t irq_config_func; +#endif +}; + +struct uart_cc35xx_dev_data_t { + uint32_t baud_rate; + int id; + struct k_spinlock lock; +#ifdef CONFIG_UART_INTERRUPT_DRIVEN + uart_irq_callback_user_data_t cb; + void *cb_data; +#endif +}; + +static int uart_cc35xx_init(const struct device *dev) +{ + struct uart_cc35xx_dev_data_t *data = dev->data; + const struct uart_cc35xx_dev_config *config = dev->config; + int ret; + + ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); + if (ret < 0) { + return ret; + } + + UARTClockCtrl(config->base, true); + UARTConfigSetExpClk(config->base, config->sys_clk_freq, data->baud_rate, + UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE); + UARTDisableCts(config->base); + UARTDisableRts(config->base); + UARTDisableInt(config->base, UART_INT_ALL); + + UARTClearInt(config->base, UART_INT_RX); + UARTEnable(config->base); + /* UARTEnable() enables the FIFO, but we do not use it in this implementation. */ + UARTDisableFifo(config->base); +#ifdef CONFIG_UART_INTERRUPT_DRIVEN + config->irq_config_func(dev); +#endif + return 0; +} + +static int uart_cc35xx_fifo_fill(const struct device *dev, const uint8_t *tx_data, int size) +{ + const struct uart_cc35xx_dev_config *config = dev->config; + int i = 0; + + for (i = 0; i < size && UARTSpaceAvailable(config->base); i++) { + UARTPutCharNonBlocking(config->base, tx_data[i]); + } + + return i; +} + +static int uart_cc35xx_fifo_read(const struct device *dev, uint8_t *rx_data, int size) +{ + const struct uart_cc35xx_dev_config *config = dev->config; + int i = 0; + + for (i = 0; i < size && UARTCharAvailable(config->base); i++) { + rx_data[i] = UARTGetCharNonBlocking(config->base); + } + + return i; +} + +#ifdef CONFIG_UART_INTERRUPT_DRIVEN + +static void uart_cc35xx_irq_tx_enable(const struct device *dev) +{ + const struct uart_cc35xx_dev_config *config = dev->config; + + UARTEnableInt(config->base, UART_INT_TX); +} + +static void uart_cc35xx_irq_tx_disable(const struct device *dev) +{ + const struct uart_cc35xx_dev_config *config = dev->config; + + UARTDisableInt(config->base, UART_INT_TX); +} + +static int uart_cc35xx_irq_tx_ready(const struct device *dev) +{ + const struct uart_cc35xx_dev_config *config = dev->config; + uint32_t status; + + status = UARTIntStatus(config->base, true); + return !!(status & UART_INT_TX); +} + +static void uart_cc35xx_irq_rx_enable(const struct device *dev) +{ + const struct uart_cc35xx_dev_config *config = dev->config; + + UARTEnableInt(config->base, UART_INT_RX); +} + +static void uart_cc35xx_irq_rx_disable(const struct device *dev) +{ + const struct uart_cc35xx_dev_config *config = dev->config; + + UARTDisableInt(config->base, UART_INT_RX); +} + +static int uart_cc35xx_irq_tx_complete(const struct device *dev) +{ + const struct uart_cc35xx_dev_config *config = dev->config; + + return UARTBusy(config->base); +} + +static int uart_cc35xx_irq_rx_ready(const struct device *dev) +{ + const struct uart_cc35xx_dev_config *config = dev->config; + uint32_t status; + + status = UARTIntStatus(config->base, true); + return !!(status & UART_INT_RX); +} + +static int uart_cc35xx_irq_is_pending(const struct device *dev) +{ + const struct uart_cc35xx_dev_config *config = dev->config; + uint32_t status; + + status = UARTIntStatus(config->base, true); + return !!(status & (UART_INT_TX | UART_INT_RX)); +} + +static int uart_cc35xx_irq_update(const struct device *dev) +{ + ARG_UNUSED(dev); + + return 1; +} + +static void uart_cc35xx_irq_callback_set(const struct device *dev, uart_irq_callback_user_data_t cb, + void *cb_data) +{ + struct uart_cc35xx_dev_data_t *data = dev->data; + + data->cb = cb; + data->cb_data = cb_data; +} + +static void uart_cc35xx_isr(const struct device *dev) +{ + struct uart_cc35xx_dev_data_t *data = dev->data; + + if (data->cb) { + data->cb(dev, data->cb_data); + } +} + +#endif /* CONFIG_UART_INTERRUPT_DRIVEN */ + +static int uart_cc35xx_poll_in(const struct device *dev, unsigned char *c) +{ + return uart_cc35xx_fifo_read(dev, c, 1); +} + +static void uart_cc35xx_poll_out(const struct device *dev, unsigned char c) +{ + struct uart_cc35xx_dev_data_t *data = dev->data; + + K_SPINLOCK(&data->lock) { + while (uart_cc35xx_fifo_fill(dev, &c, 1) == 0) { + } + } +} + +static const struct uart_driver_api uart_cc35xx_driver_api = { + .poll_in = uart_cc35xx_poll_in, + .poll_out = uart_cc35xx_poll_out, +#ifdef CONFIG_UART_INTERRUPT_DRIVEN + .fifo_fill = uart_cc35xx_fifo_fill, + .fifo_read = uart_cc35xx_fifo_read, + .irq_tx_enable = uart_cc35xx_irq_tx_enable, + .irq_tx_disable = uart_cc35xx_irq_tx_disable, + .irq_tx_ready = uart_cc35xx_irq_tx_ready, + .irq_rx_enable = uart_cc35xx_irq_rx_enable, + .irq_rx_disable = uart_cc35xx_irq_rx_disable, + .irq_tx_complete = uart_cc35xx_irq_tx_complete, + .irq_rx_ready = uart_cc35xx_irq_rx_ready, + .irq_is_pending = uart_cc35xx_irq_is_pending, + .irq_update = uart_cc35xx_irq_update, + .irq_callback_set = uart_cc35xx_irq_callback_set, + +#endif +}; + +#define UART_35XX_DEVICE(idx) \ + PINCTRL_DT_INST_DEFINE(idx); \ + IF_ENABLED(CONFIG_UART_INTERRUPT_DRIVEN, ( \ + static void uart_cc35xx_cfg_func_##idx(const struct device *dev) \ + { \ + IF_ENABLED(CONFIG_UART_INTERRUPT_DRIVEN, ( \ + IRQ_CONNECT(DT_INST_IRQN(idx), \ + DT_INST_IRQ(idx, priority), \ + uart_cc35xx_isr, DEVICE_DT_INST_GET(idx), \ + 0); \ + irq_enable(DT_INST_IRQN(idx))) \ + ); \ + })); \ + static const struct uart_cc35xx_dev_config uart_cc35xx_dev_cfg_##idx = { \ + .base = DT_INST_REG_ADDR(idx), \ + .sys_clk_freq = DT_INST_PROP_BY_PHANDLE(idx, clocks, clock_frequency), \ + .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx), \ + IF_ENABLED(CONFIG_UART_INTERRUPT_DRIVEN, \ + (.irq_config_func = uart_cc35xx_cfg_func_##idx,)) }; \ + static struct uart_cc35xx_dev_data_t uart_cc35xx_dev_data_##idx = { \ + .baud_rate = DT_INST_PROP(idx, current_speed), \ + .id = idx, \ + }; \ + DEVICE_DT_INST_DEFINE(idx, uart_cc35xx_init, NULL, &uart_cc35xx_dev_data_##idx, \ + &uart_cc35xx_dev_cfg_##idx, PRE_KERNEL_1, \ + CONFIG_SERIAL_INIT_PRIORITY, (void *)&uart_cc35xx_driver_api); + +DT_INST_FOREACH_STATUS_OKAY(UART_35XX_DEVICE); diff --git a/dts/arm/ti/cc35xxe.dtsi b/dts/arm/ti/cc35xxe.dtsi index e867311aceb6..d5905c643906 100644 --- a/dts/arm/ti/cc35xxe.dtsi +++ b/dts/arm/ti/cc35xxe.dtsi @@ -8,6 +8,15 @@ #include #include +#define INT_SP_UART_0_INT_REQ 16 +#define INT_SP_UART_1_INT_REQ 17 +/* + * Note: Zephyr uses exception numbers, vs the IRQ used by the CC32XX SDK + * which are offset by 16: + */ +#define EXP_UARTA0 (INT_SP_UART_0_INT_REQ - 16) +#define EXP_UARTA1 (INT_SP_UART_1_INT_REQ - 16) + / { cpus { #address-cells = <1>; @@ -130,14 +139,18 @@ uart0: uart@41240000 { compatible = "ti,cc35xx-uart"; + current-speed = <115200>; reg = <0x41240000 0x1000>; + interrupts = ; clocks = <&uartclk>; status = "disabled"; }; uart1: uart@41250000 { compatible = "ti,cc35xx-uart"; + current-speed = <115200>; reg = <0x41250000 0x1000>; + interrupts = ; clocks = <&uartclk>; status = "disabled"; }; diff --git a/dts/bindings/serial/ti,cc35xx-uart.yaml b/dts/bindings/serial/ti,cc35xx-uart.yaml new file mode 100644 index 000000000000..688e3dc53749 --- /dev/null +++ b/dts/bindings/serial/ti,cc35xx-uart.yaml @@ -0,0 +1,15 @@ +description: TI CC35XX UART + +compatible: "ti,cc35xx-uart" + +include: [uart-controller.yaml, pinctrl-device.yaml] + +properties: + reg: + required: true + + pinctrl-0: + required: true + + pinctrl-names: + required: true From 889db209e5abdfb7e1020f79b92dc739ff1dba40 Mon Sep 17 00:00:00 2001 From: Jakub Klama Date: Mon, 28 Jul 2025 02:49:51 +0200 Subject: [PATCH 006/100] UPSTREAM-PEND: runners: Initial support for simplelink-wifi-toolbox runner MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add initial support for runner based on simplelink tools Signed-off-by: Jakub Klama Signed-off-by: Jacek Ozimek Signed-off-by: Michał Łyszczek --- boards/common/simplelink_toolbox.board.cmake | 7 ++ boards/ti/lp_em_cc35x1/board.cmake | 4 + scripts/west_commands/runners/__init__.py | 1 + .../runners/simplelink_toolbox.py | 76 +++++++++++++++++++ 4 files changed, 88 insertions(+) create mode 100644 boards/common/simplelink_toolbox.board.cmake create mode 100644 scripts/west_commands/runners/simplelink_toolbox.py diff --git a/boards/common/simplelink_toolbox.board.cmake b/boards/common/simplelink_toolbox.board.cmake new file mode 100644 index 000000000000..d6b22d3f4fdc --- /dev/null +++ b/boards/common/simplelink_toolbox.board.cmake @@ -0,0 +1,7 @@ +# Copyright (c) 2025 Conclusive Engineering Sp. z o.o. +# +# SPDX-License-Identifier: Apache-2.0 + +board_set_flasher_ifnset(simplelink_toolbox) +board_set_debugger_ifnset(simplelink_toolbox) +board_finalize_runner_args(simplelink_toolbox) diff --git a/boards/ti/lp_em_cc35x1/board.cmake b/boards/ti/lp_em_cc35x1/board.cmake index 26fc91e01481..e32d8525a739 100644 --- a/boards/ti/lp_em_cc35x1/board.cmake +++ b/boards/ti/lp_em_cc35x1/board.cmake @@ -1,3 +1,7 @@ # Copyright (c) 2025 Conclusive Engineering Sp. z o.o. # # SPDX-License-Identifier: Apache-2.0 + +set(BOARD_DIR ${CMAKE_CURRENT_LIST_DIR}) + +include(${ZEPHYR_BASE}/boards/common/simplelink_toolbox.board.cmake) diff --git a/scripts/west_commands/runners/__init__.py b/scripts/west_commands/runners/__init__.py index 7fa6845112b8..19c962e2e50b 100644 --- a/scripts/west_commands/runners/__init__.py +++ b/scripts/west_commands/runners/__init__.py @@ -62,6 +62,7 @@ def _import_runner_module(runner_name): 'rtsflash', 'sftool', 'silabs_commander', + 'simplelink_toolbox', 'spi_burn', 'spsdk', 'stlink_gdbserver', diff --git a/scripts/west_commands/runners/simplelink_toolbox.py b/scripts/west_commands/runners/simplelink_toolbox.py new file mode 100644 index 000000000000..51c14a3be592 --- /dev/null +++ b/scripts/west_commands/runners/simplelink_toolbox.py @@ -0,0 +1,76 @@ +# Copyright (c) 2025 Conclusive Engineering Sp. z o.o. +# +# SPDX-License-Identifier: Apache-2.0 + +'''Runner for simplelink-wifi-toolbox.''' + +import os +import subprocess +from pathlib import Path + +from runners.core import ZephyrBinaryRunner + + +class SimpleLinkBinaryRunner(ZephyrBinaryRunner): + '''Runner front-end for simplelink-wifi-toolbox.''' + + def __init__(self, cfg, simplelink_tool): + super().__init__(cfg) + + self.simplelink_tool = simplelink_tool + self.vendor_file = ( + Path(cfg.build_dir) / 'zephyr' / 'flash' / 'vendor_image.sign.bin' + ).resolve() + self.tool_setting_file = (Path(cfg.board_dir) / 'config' / 'tool_settings.json').resolve() + self.programming_report_file = ( + Path(self.cfg.build_dir) / 'simplelink_toolbox_report.txt' + ).resolve() + + @classmethod + def name(cls): + return 'simplelink_toolbox' + + @classmethod + def do_add_parser(cls, parser): + parser.add_argument( + '--simplelink-tool', + default='simplelink-wifi-toolbox', + help='path to simplelink tool, default is simplelink-wifi-toolbox', + ) + + @classmethod + def do_create(cls, cfg, args): + return SimpleLinkBinaryRunner(cfg, simplelink_tool=args.simplelink_tool) + + def do_run(self, command): + self.require(self.simplelink_tool) + if command == 'flash': + self.flash() + + def flash(self): + if self.vendor_file is not None and os.path.isfile(self.vendor_file): + fname = self.vendor_file + else: + raise ValueError(f'Cannot flash; no vendor ({self.vendor_file}) file found. ') + + cmd = [ + str(self.simplelink_tool), + 'programmer', + '-i', + 'XDS110', + '-param1', + 'auto', + 'programming', + '--tool_settings', + str(self.tool_setting_file), + '--report_file_name_path', + str(self.programming_report_file), + ] + + self.logger.info(f'Flashing file: {fname}') + + try: + self.check_output(cmd, cwd=Path(self.cfg.build_dir).resolve()) + self.logger.info('Success') + except subprocess.CalledProcessError as grepexc: + self.logger.error(f"Failure {grepexc.returncode}") From b7ad2045abb500894cdfd1a0e032f14a02adfea6 Mon Sep 17 00:00:00 2001 From: Jakub Klama Date: Sun, 27 Jul 2025 01:56:38 +0200 Subject: [PATCH 007/100] UPSTREAM-PEND: cc35xxe: Initial build integration with simplelink-wifi-t... MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ...oolbox. This commit adds an initial support to generate and sign images needed by the simplelink-wifi-toolbox programmer. Signed-off-by: Jakub Klama Signed-off-by: Jacek Ozimek Signed-off-by: Michał Łyszczek --- .../ti/lp_em_cc35x1/config/action_params.json | 132 +++++ .../config/flash_disc_param_ext_mem.json | 99 ++++ .../config/flash_disc_param_otfde.json | 286 +++++++++++ .../config/flash_disc_param_xspi.json | 485 ++++++++++++++++++ .../config/fuse_prog_inst_param.json | 43 ++ .../ti/lp_em_cc35x1/config/tool_settings.json | 60 +++ soc/ti/simplelink/cc35xxe/CMakeLists.txt | 2 + soc/ti/simplelink/cc35xxe/Kconfig.soc | 21 + .../cc35xxe/keys/cc35x1e_lp_em_prv_key.pem | 5 + .../cc35xxe/keys/cc35x1e_lp_em_pub_key.pem | 4 + soc/ti/simplelink/cc35xxe/toolbox.cmake | 134 +++++ 11 files changed, 1271 insertions(+) create mode 100644 boards/ti/lp_em_cc35x1/config/action_params.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash_disc_param_ext_mem.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash_disc_param_otfde.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash_disc_param_xspi.json create mode 100644 boards/ti/lp_em_cc35x1/config/fuse_prog_inst_param.json create mode 100644 boards/ti/lp_em_cc35x1/config/tool_settings.json create mode 100644 soc/ti/simplelink/cc35xxe/keys/cc35x1e_lp_em_prv_key.pem create mode 100644 soc/ti/simplelink/cc35xxe/keys/cc35x1e_lp_em_pub_key.pem create mode 100644 soc/ti/simplelink/cc35xxe/toolbox.cmake diff --git a/boards/ti/lp_em_cc35x1/config/action_params.json b/boards/ti/lp_em_cc35x1/config/action_params.json new file mode 100644 index 000000000000..cf37b571a6fb --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/action_params.json @@ -0,0 +1,132 @@ +{ + "programming": { + "header_version": 1, + "udid": "", + "pub_key": "", + "payload_param": { + "type_version": 0, + "payload": { + "prog_req_content": { + "fuse_programming_instruction_update": false, + "boot_sector": false, + "primary_tbl": false, + "secondary_tbl": false, + "primary_vendor_image": true, + "primary_vendor_sbl": false, + "secondary_vendor_image": false, + "secondary_vendor_sbl": false, + "primary_ti_wsoc": false, + "secondary_ti_wsoc": false, + "primary_ti_wsoc_bl2": false, + "secondary_ti_wsoc_bl2": false + }, + "prog_validation": { + "fuse_programming_instruction_update": false, + "boot_sector": false, + "primary_tbl": false, + "secondary_tbl": false, + "primary_vendor_image": false, + "primary_vendor_sbl": false, + "secondary_vendor_image": false, + "secondary_vendor_sbl": false, + "primary_ti_wsoc": false, + "secondary_ti_wsoc": false, + "primary_ti_wsoc_bl2": false, + "secondary_ti_wsoc_bl2": false + } + } + } + }, + "query": { + "header_version": 1, + "udid": "", + "pub_key": "", + "payload_param": { + "type_version": 0, + "payload": { + "query_req_content": { + "boot_sector_query": false, + "primary_ti_bootloader_query": false, + "secondary_ti_bootloader_query": false, + "primary_vendor_image_query": false, + "primary_vendor_sbl_query": false, + "secondary_vendor_image_query": false, + "secondary_vendor_sbl_query": false, + "primary_ti_wsoc_query": false, + "secondary_ti_wsoc_query": false, + "primary_ti_wsoc_bl2_query": false, + "secondary_ti_wsoc_bl2_query": false + } + } + } + }, + "debug": { + "header_version": 1, + "udid": "", + "pub_key": "", + "payload_param": { + "type_version": 0, + "payload": { + "vendor_debug_bypass": { + "efuse_crc_validation_bypass": false, + "otfde_protection_bypass": true, + "second_container_validation_bypass": true, + "rollback_validation_bypass": false, + "security_policy_bypass": false, + "security_Failure_Behavioral_bypass": false, + "primary_rot_switching_to_secondary_bypass": false, + "crc_efuse_validation_bypass": false, + "non_crc_efuse_validation_otp_bypass": false, + "non_crc_efuse_mismatch_bypass": false, + "soc_boot_configurations_bypass": false, + "host_boot_configurations_bypass": false, + "soc_security_configuration_bypass": false, + "host_security_configuration_bypass": false, + "host_services_irq_configurations_bypass": false, + "full_open_all_vendors_debug": false, + "full_open_vendors_all_ns_debug": false, + "full_open_vendors_all_s_debug": false, + "partial_open_all_vendors_debug": false, + "partial_open_vendors_all_ns_debug": false, + "partial_open_vendors_all_s_debug": false + }, + "vendor_efuse_crc_validation_bypass": { + "m33_halt_or_run": "halt", + "clear_errors_scratchpad": false + }, + "vendors_hide_and_lock_policy_instructions": { + "host_boot_done_set_bypass": false, + "host_peripherals_lock_set_bypass": false, + "icache_configurations_lock_set_bypass": false, + "m33_memory_partitioning_lock_set_bypass": false, + "memss_mode_and_firewall_lock_set_bypass": false, + "dma_channel_owner_lock_set_bypass": false, + "core_events_lock_set_bypass": false, + "otfde_region_lock_bypass": false + } + } + } + }, + "enter_rma": { + "header_version": 1, + "udid": "", + "pub_key": "", + "payload_param": { + "type_version": 0, + "payload": { + "enter_rma_option": { + "invalidate_vendor_rot_fuses": false, + "invalidate_other_vendor_fuses": false, + "invalidate_all_vendor_images": false, + "invalidate_internal_memory": false + }, + "enter_rma_validation": { + "invalidate_vendor_rot_fuses_validate": false, + "invalidate_other_vendor_fuses_validate": false, + "invalidate_all_vendor_images_validate": false, + "invalidate_internal_memory_validate": false + } + } + } + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash_disc_param_ext_mem.json b/boards/ti/lp_em_cc35x1/config/flash_disc_param_ext_mem.json new file mode 100644 index 000000000000..d054c36fe29d --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash_disc_param_ext_mem.json @@ -0,0 +1,99 @@ +{ + "vendor_primary_sbl": false, + "ti_wsoc_primary_container": true, + "ti_wsoc_bl2_primary_container": true, + "nvs_enable": false, + "vendor_alternate_image": false, + "vendor_sbl_alternate_image": false, + "ti_bl_alternate_image": false, + "ti_wsoc_alternate_image": false, + "ti_wsoc_bl2_alternate_image": false, + "region_0": { + "mem_region_0_start_phy_address": 208896, + "mem_region_0_end_phy_address": 2203647, + "region0_boot": false, + "region0_main_code": true, + "region0_nvs": false, + "region0_wsoc_code": false, + "region0_alternate_code": false + }, + "region_1": { + "mem_region_1_start_phy_address": 2203648, + "mem_region_1_end_phy_address": 4190207, + "region1_boot": false, + "region1_main_code": false, + "region1_nvs": true, + "region1_wsoc_code": true, + "region1_alternate_code": false + }, + "region_2": { + "mem_region_2_start_phy_address": 14888960, + "mem_region_2_end_phy_address": 26423295, + "region2_boot": false, + "region2_main_code": false, + "region2_nvs": false, + "region2_wsoc_code": false, + "region2_alternate_code": true + }, + "region_3": { + "mem_region_3_start_phy_address": 0, + "mem_region_3_end_phy_address": 208895, + "region3_boot": true, + "region3_main_code": false, + "region3_nvs": false, + "region3_wsoc_code": false, + "region3_alternate_code": false + }, + "boot_region_conf": { + "boot_region_size": 0, + "boot_region_flash_disco_param_start_address": 0, + "boot_region_primary_ti_bl_start_phy_address": 8188, + "boot_region_primary_ti_bl_magic": 0, + "boot_region_primary_ti_bl_major": 0, + "boot_region_primary_ti_bl_minor": 0, + "boot_region_sec_ti_bl_start_phy_address": 0, + "boot_region_sec_ti_bl_magic": 0, + "boot_region_sec_ti_bl_major": 0, + "boot_region_sec_ti_bl_minor": 0 + }, + "main_code_region_conf": { + "main_code_region_vendor_image_start_phy_address": 212988, + "main_code_region_vendor_image_magic": 0, + "main_code_region_vendor_image_major": 0, + "main_code_region_vendor_image_minor": 0, + "main_code_region_sbl_start_phy_address": 10698748, + "main_code_region_sbl_magic": 0, + "main_code_region_sbl_major": 0, + "main_code_region_sbl_minor": 0 + }, + "alt_code_region_conf": { + "alt_code_region_vendor_image_start_phy_address": 0, + "alt_code_region_vendor_image_magic": 0, + "alt_code_region_vendor_image_major": 0, + "alt_code_region_vendor_image_minor": 0, + "alt_code_region_sbl_start_phy_address": 0, + "alt_code_region_sbl_magic": 0, + "alt_code_region_sbl_major": 0, + "alt_code_region_sbl_minor": 0 + }, + "nvs_code_region_conf": { + "nvs_start_phy_address": 0, + "nvs_region_size": 0, + "nvs_region_primary_wsoc_start_phy_address": 0, + "nvs_region_primary_wsoc_magic": 0, + "nvs_region_primary_wsoc_major": 0, + "nvs_region_primary_wsoc_minor": 0, + "nvs_region_sec_wsoc_start_phy_address": 0, + "nvs_region_sec_wsoc_magic": 0, + "nvs_region_sec_wsoc_major": 0, + "nvs_region_sec_wsoc_minor": 0, + "nvs_region_primary_wsoc_bl2_start_phy_address": 0, + "nvs_region_primary_wsoc_bl2_magic": 0, + "nvs_region_primary_wsoc_bl2_major": 0, + "nvs_region_primary_wsoc_bl2_minor": 0, + "nvs_region_sec_wsoc_bl2_start_phy_address": 0, + "nvs_region_sec_wsoc_bl2_magic": 0, + "nvs_region_sec_wsoc_bl2_major": 0, + "nvs_region_sec_wsoc_bl2_minor": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash_disc_param_otfde.json b/boards/ti/lp_em_cc35x1/config/flash_disc_param_otfde.json new file mode 100644 index 000000000000..6c6c2219e54e --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash_disc_param_otfde.json @@ -0,0 +1,286 @@ +{ + "otfde_header": { + "name": "OTFDEWFF3", + "flash_only": true, + "ip_protection": false, + "regions_lock": false, + "regions_number": 4, + "flash_enabled": true + }, + "bl_conf": { + "host_boot_done_lock": true, + "host_peripherals_lock": true, + "icache_conf_lock": true, + "m33_mem_part_lock": true, + "memss_firewall_lock": true, + "dma_channel_owner_lock": true, + "otfde_region_lock": true, + "core_events_lock": true + }, + "otfde_general": { + "parameters": { + "mem_otfde_initial_delay": 10, + "otfde_global_watchdog_timer": 5 + }, + "events": { + "reset_evt_mask": false, + "reset_evt_suspend": false, + "sft_reset_evt_mask": false, + "sft_reset_evt_suspend": false, + "bypass_mode_evt_mask": false, + "bypass_mode_evt_suspend": false, + "debug_mode_evt_mask": false, + "debug_mode_evt_suspend": false, + "general_evt_mask": false, + "general_evt_suspend": false, + "xspi_data_path_evt_mask": false, + "xspi_data_path_evt_suspend": false, + "xspi_cnfg_path_evt_mask": false, + "xspi_cnfg_path_evt_suspend": false, + "xspi_service_interrupt_evt_mask": false, + "xspi_service_interrupt_evt_suspend": false, + "trans_device_disabled_evt_mask": false, + "trans_device_disabled_evt_suspend": false, + "trans_region_disabled_evt_mask": false, + "trans_region_disabled_evt_suspend": false, + "trans_region_params_conf_evt_mask": false, + "trans_region_params_conf_evt_suspend": false, + "trans_multiple_regions_mapped_evt_mask": false, + "trans_multiple_regions_mapped_evt_suspend": false, + "trans_address_not_32_bit_evt_mask": false, + "trans_address_not_32_bit_evt_suspend": false, + "trans_size_not_32_bit_evt_mask": false, + "trans_size_not_32_bit_evt_suspend": false, + "trans_burst_not_32_bit_evt_mask": false, + "trans_burst_not_32_bit_evt_suspend": false, + "region_read_write_def_evt_mask": false, + "region_read_write_def_evt_suspend": false, + "suspend_while_disabled_evt_mask": false, + "suspend_while_disabled_evt_suspend": false + } + }, + "regions_settings": { + "region_parameters_lock": { + "REGION_0_PARAMS_0": true, + "REGION_0_PARAMS_1": true, + "REGION_0_PARAMS_2": true, + "REGION_1_PARAMS_0": false, + "REGION_1_PARAMS_1": false, + "REGION_1_PARAMS_2": false, + "REGION_2_PARAMS_0": true, + "REGION_2_PARAMS_1": true, + "REGION_2_PARAMS_2": true, + "REGION_3_PARAMS_0": false, + "REGION_3_PARAMS_1": false, + "REGION_3_PARAMS_2": false + }, + "region_0_protection": { + "mem_region_0_enabled": true, + "mem_region_0_device_id": 0, + "mem_region_0_spi_write_enable": true, + "mem_region_0_spi_read_enable": true, + "mem_region_0_physical_offset": 51, + "mem_region_0_security_id_msb": 0, + "mem_region_0_start_address": 65536, + "mem_region_0_end_address": 66022, + "mem_region_0_security_id_lsb": 0, + "mem_otfde_region_0_write_lock_en": false, + "mem_otfde_region_0_enc_dec_bypass": "Bypass" + }, + "region_1_protection": { + "mem_region_1_enabled": true, + "mem_region_1_device_id": 0, + "mem_region_1_spi_write_enable": true, + "mem_region_1_spi_read_enable": true, + "mem_region_1_physical_offset": 458, + "mem_region_1_security_id_msb": 0, + "mem_region_1_start_address": 655440, + "mem_region_1_end_address": 655925, + "mem_region_1_security_id_lsb": 0, + "mem_otfde_region_1_write_lock_en": false, + "mem_otfde_region_1_enc_dec_bypass": "Bypass" + }, + "region_2_protection": { + "mem_region_2_enabled": false, + "mem_region_2_device_id": 0, + "mem_region_2_spi_write_enable": false, + "mem_region_2_spi_read_enable": false, + "mem_region_2_physical_offset": 0, + "mem_region_2_security_id_msb": 0, + "mem_region_2_start_address": 1, + "mem_region_2_end_address": 0, + "mem_region_2_security_id_lsb": 0, + "mem_otfde_region_2_write_lock_en": false, + "mem_otfde_region_2_enc_dec_bypass": "Bypass" + }, + "region_3_protection": { + "mem_region_3_enabled": true, + "mem_region_3_device_id": 0, + "mem_region_3_spi_write_enable": true, + "mem_region_3_spi_read_enable": true, + "mem_region_3_physical_offset": 0, + "mem_region_3_security_id_msb": 0, + "mem_region_3_start_address": 655360, + "mem_region_3_end_address": 655410, + "mem_region_3_security_id_lsb": 0, + "mem_otfde_region_3_write_lock_en": false, + "mem_otfde_region_3_enc_dec_bypass": "Bypass" + } + }, + "devices": { + "header": { + "flash_device_switch_conf": 1, + "ram_device_switch_conf": 1 + }, + "flash_switch": { + "flash_grant_sel": 0, + "flash_data_for_conf_0": 2181562505, + "flash_offset_bits_for_conf_0": 0, + "flash_stop_bit_for_conf_0": 0, + "flash_data_for_conf_1": 67248651, + "flash_offset_bits_for_conf_1": 1, + "flash_stop_bit_for_conf_1": 0, + "flash_data_for_conf_2": 139266, + "flash_offset_bits_for_conf_2": 2, + "flash_stop_bit_for_conf_2": 0, + "flash_data_for_conf_3": 1, + "flash_offset_bits_for_conf_3": 4, + "flash_stop_bit_for_conf_3": 0, + "flash_data_for_conf_4": 1076887634, + "flash_offset_bits_for_conf_4": 45, + "flash_stop_bit_for_conf_4": 0, + "flash_data_for_conf_5": 3224371282, + "flash_offset_bits_for_conf_5": 45, + "flash_stop_bit_for_conf_5": 0, + "flash_data_for_conf_6": 262149, + "flash_offset_bits_for_conf_6": 14, + "flash_stop_bit_for_conf_6": 0, + "flash_data_for_conf_7": 0, + "flash_offset_bits_for_conf_7": 44, + "flash_stop_bit_for_conf_7": 1, + "flash_data_for_conf_8": 0, + "flash_offset_bits_for_conf_8": 0, + "flash_stop_bit_for_conf_8": 1, + "flash_data_for_conf_9": 0, + "flash_offset_bits_for_conf_9": 0, + "flash_stop_bit_for_conf_9": 1, + "flash_data_for_conf_10": 0, + "flash_offset_bits_for_conf_10": 0, + "flash_stop_bit_for_conf_10": 1, + "flash_data_for_conf_11": 0, + "flash_offset_bits_for_conf_11": 0, + "flash_stop_bit_for_conf_11": 1, + "flash_data_for_conf_12": 0, + "flash_offset_bits_for_conf_12": 0, + "flash_stop_bit_for_conf_12": 1, + "flash_data_for_conf_13": 0, + "flash_offset_bits_for_conf_13": 0, + "flash_stop_bit_for_conf_13": 1, + "flash_data_for_conf_14": 0, + "flash_offset_bits_for_conf_14": 0, + "flash_stop_bit_for_conf_14": 1, + "flash_data_for_conf_15": 0, + "flash_offset_bits_for_conf_15": 0, + "flash_stop_bit_for_conf_15": 1, + "flash_data_for_conf_16": 0, + "flash_offset_bits_for_conf_16": 0, + "flash_stop_bit_for_conf_16": 1, + "flash_data_for_conf_17": 0, + "flash_offset_bits_for_conf_17": 0, + "flash_stop_bit_for_conf_17": 1, + "flash_data_for_conf_18": 0, + "flash_offset_bits_for_conf_18": 0, + "flash_stop_bit_for_conf_18": 1, + "flash_data_for_conf_19": 0, + "flash_offset_bits_for_conf_19": 0, + "flash_stop_bit_for_conf_19": 1, + "flash_data_for_conf_20": 0, + "flash_offset_bits_for_conf_20": 0, + "flash_stop_bit_for_conf_20": 1, + "flash_data_for_conf_21": 0, + "flash_offset_bits_for_conf_21": 0, + "flash_stop_bit_for_conf_21": 1, + "flash_data_for_conf_22": 0, + "flash_offset_bits_for_conf_22": 0, + "flash_stop_bit_for_conf_22": 1, + "flash_data_for_conf_23": 0, + "flash_offset_bits_for_conf_23": 0, + "flash_stop_bit_for_conf_23": 1 + }, + "ram_switch": { + "ram_grant_sel": 0, + "ram_data_for_conf_0": 2181562505, + "ram_offset_bits_for_conf_0": 0, + "ram_stop_bit_for_conf_0": 0, + "ram_data_for_conf_1": 67248651, + "ram_offset_bits_for_conf_1": 1, + "ram_stop_bit_for_conf_1": 0, + "ram_data_for_conf_2": 139266, + "ram_offset_bits_for_conf_2": 2, + "ram_stop_bit_for_conf_2": 0, + "ram_data_for_conf_3": 1, + "ram_offset_bits_for_conf_3": 4, + "ram_stop_bit_for_conf_3": 0, + "ram_data_for_conf_4": 1076887634, + "ram_offset_bits_for_conf_4": 45, + "ram_stop_bit_for_conf_4": 0, + "ram_data_for_conf_5": 3224371282, + "ram_offset_bits_for_conf_5": 45, + "ram_stop_bit_for_conf_5": 0, + "ram_data_for_conf_6": 262149, + "ram_offset_bits_for_conf_6": 14, + "ram_stop_bit_for_conf_6": 0, + "ram_data_for_conf_7": 0, + "ram_offset_bits_for_conf_7": 44, + "ram_stop_bit_for_conf_7": 1, + "ram_data_for_conf_8": 0, + "ram_offset_bits_for_conf_8": 0, + "ram_stop_bit_for_conf_8": 1, + "ram_data_for_conf_9": 0, + "ram_offset_bits_for_conf_9": 0, + "ram_stop_bit_for_conf_9": 1, + "ram_data_for_conf_10": 0, + "ram_offset_bits_for_conf_10": 0, + "ram_stop_bit_for_conf_10": 1, + "ram_data_for_conf_11": 0, + "ram_offset_bits_for_conf_11": 0, + "ram_stop_bit_for_conf_11": 1, + "ram_data_for_conf_12": 0, + "ram_offset_bits_for_conf_12": 0, + "ram_stop_bit_for_conf_12": 1, + "ram_data_for_conf_13": 0, + "ram_offset_bits_for_conf_13": 0, + "ram_stop_bit_for_conf_13": 1, + "ram_data_for_conf_14": 0, + "ram_offset_bits_for_conf_14": 0, + "ram_stop_bit_for_conf_14": 1, + "ram_data_for_conf_15": 0, + "ram_offset_bits_for_conf_15": 0, + "ram_stop_bit_for_conf_15": 1, + "ram_data_for_conf_16": 0, + "ram_offset_bits_for_conf_16": 0, + "ram_stop_bit_for_conf_16": 1, + "ram_data_for_conf_17": 0, + "ram_offset_bits_for_conf_17": 0, + "ram_stop_bit_for_conf_17": 1, + "ram_data_for_conf_18": 0, + "ram_offset_bits_for_conf_18": 0, + "ram_stop_bit_for_conf_18": 1, + "ram_data_for_conf_19": 0, + "ram_offset_bits_for_conf_19": 0, + "ram_stop_bit_for_conf_19": 1, + "ram_data_for_conf_20": 0, + "ram_offset_bits_for_conf_20": 0, + "ram_stop_bit_for_conf_20": 1, + "ram_data_for_conf_21": 0, + "ram_offset_bits_for_conf_21": 0, + "ram_stop_bit_for_conf_21": 1, + "ram_data_for_conf_22": 0, + "ram_offset_bits_for_conf_22": 0, + "ram_stop_bit_for_conf_22": 1, + "ram_data_for_conf_23": 0, + "ram_offset_bits_for_conf_23": 0, + "ram_stop_bit_for_conf_23": 1 + } + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash_disc_param_xspi.json b/boards/ti/lp_em_cc35x1/config/flash_disc_param_xspi.json new file mode 100644 index 000000000000..691dcf45cba8 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash_disc_param_xspi.json @@ -0,0 +1,485 @@ +{ + "xspi_header": { + "name": "xSPIWFF3", + "device": "CC3500", + "use_hardware": "IS25WJ032F", + "use_case": "Quadro", + "dqs_support": 0, + "flash_only": 1, + "flash_separate_reset": 0, + "ram_separate_reset": true, + "clock_frequency": 80, + "qospi_clock_divider": 1, + "flash_device_character_conf": 0, + "ram_device_character_conf": 0, + "header_advanced": 0, + "phy_mode_enable": 1, + "pipeline_mode_enable": 1, + "loopback_support": "No", + "qspi_ref_clock": 80, + "spi_clock_freq": 20, + "spi_clock_divider": 1, + "flash_device_size": 4, + "flash_bytes_per_block": 16, + "flash_bytes_per_page": 256, + "flash_number_of_address_bytes": 3, + "flash_dual_opcode": 0, + "flash_jedec_manufacturer_id": 0, + "flash_jedec_device_id": 0, + "flash_name": "IS25WJ032F", + "flash_page_size": 256, + "flash_sector_size": 4096, + "flash_cs_polarity": "ACTIVE_LOW", + "flash_sw_reset_type": "x1xxxx", + "ram_device_size": 4, + "ram_bytes_per_block": 16, + "ram_bytes_per_page": 256, + "ram_number_of_address_bytes": 3, + "ram_dual_opcode": 0, + "ram_jedec_manufacturer_id": 0, + "ram_jedec_device_id": 0, + "ram_name": "IS25WJ032F", + "ram_page_size": 256, + "ram_sector_size": 4096, + "ram_cs_polarity": "ACTIVE_LOW", + "ram_sw_reset_type": "x1xxxx", + "flash_write_operation_modes": "4S-4S-4S", + "flash_read_operation_modes": "4S-4S-4S", + "ram_write_operation_modes": "4S-4S-4S", + "ram_read_operation_modes": "4S-4S-4S", + "crc_enable": 0, + "enable_dtr": 0, + "enable_ahb_decoder": 0, + "enter_xip_mod_immediately": 0, + "enter_xip_mod_next_read": 0, + "ahb_address_remapping": 0, + "enable_dma": 0, + "select_decode": 0, + "legacy_ip_mode": 0, + "direct_access": 1 + }, + "xspi_pinmux": { + "xspi_clk_input": 44, + "xspi_clk_input_use_hw": 0, + "xspi_clk_input_mode": "Input", + "xspi_clk_input_pull": "None", + "xspi_clk_input_interrupt_trigger": "Low", + "xspi_clk_input_dont_conf": 0, + "xspi_clk_input_output_strength": "High", + "xspi_clk_input_initial_output_state": "High", + "xspi_clk": 24, + "xspi_clk_use_hw": "None", + "xspi_clk_mode": "Output", + "xspi_clk_pull": "None", + "xspi_clk_output_strength": "High", + "xspi_clk_initial_output_state": "High", + "xspi_clk_interrupt_trigger": "None", + "xspi_clk_dont_conf": 0, + "xspi_flash_cs": 20, + "xspi_flash_cs_use_hw": "None", + "xspi_flash_cs_mode": "Output", + "xspi_flash_cs_pull": "None", + "xspi_flash_cs_output_strength": "High", + "xspi_flash_cs_initial_output_state": "High", + "xspi_flash_cs_interrupt_trigger": "None", + "xspi_flash_cs_dont_conf": 0, + "xspi_data_0": 25, + "xspi_data_0_use_hw": "None", + "xspi_data_0_mode": "Input", + "xspi_data_0_pull": "None", + "xspi_data_0_output_strength": "High", + "xspi_data_0_initial_output_state": "High", + "xspi_data_0_interrupt_trigger": "Low", + "xspi_data_0_dont_conf": 0, + "xspi_data_1": 21, + "xspi_data_1_use_hw": "None", + "xspi_data_1_mode": "Input", + "xspi_data_1_pull": "None", + "xspi_data_1_output_strength": "High", + "xspi_data_1_initial_output_state": "High", + "xspi_data_1_interrupt_trigger": "Low", + "xspi_data_1_dont_conf": 0, + "xspi_data_2": 22, + "xspi_data_2_use_hw": "None", + "xspi_data_2_mode": "Input", + "xspi_data_2_pull": "None", + "xspi_data_2_output_strength": "High", + "xspi_data_2_initial_output_state": "High", + "xspi_data_2_interrupt_trigger": "Low", + "xspi_data_2_dont_conf": 0, + "xspi_data_3": 23, + "xspi_data_3_use_hw": "None", + "xspi_data_3_mode": "Input", + "xspi_data_3_pull": "None", + "xspi_data_3_output_strength": "High", + "xspi_data_3_initial_output_state": "High", + "xspi_data_3_interrupt_trigger": "Low", + "xspi_data_3_dont_conf": 0, + "xspi_data_4": 26, + "xspi_data_4_use_hw": "None", + "xspi_data_4_mode": "Input", + "xspi_data_4_pull": "None", + "xspi_data_4_output_strength": "High", + "xspi_data_4_initial_output_state": "High", + "xspi_data_4_interrupt_trigger": "None", + "xspi_data_4_dont_conf": 0, + "xspi_data_5": 27, + "xspi_data_5_use_hw": "None", + "xspi_data_5_mode": "Input", + "xspi_data_5_pull": "None", + "xspi_data_5_output_strength": "High", + "xspi_data_5_initial_output_state": "High", + "xspi_data_5_interrupt_trigger": "None", + "xspi_data_5_dont_conf": 0, + "xspi_data_6": 28, + "xspi_data_6_use_hw": "None", + "xspi_data_6_mode": "Input", + "xspi_data_6_pull": "None", + "xspi_data_6_output_strength": "High", + "xspi_data_6_initial_output_state": "High", + "xspi_data_6_interrupt_trigger": "None", + "xspi_data_6_dont_conf": 0, + "xspi_data_7": 29, + "xspi_data_7_use_hw": "None", + "xspi_data_7_mode": "Input", + "xspi_data_7_pull": "None", + "xspi_data_7_output_strength": "High", + "xspi_data_7_initial_output_state": "High", + "xspi_data_7_interrupt_trigger": "None", + "xspi_data_7_dont_conf": 0, + "xspi_reset_flash": 36, + "xspi_reset_flash_use_hw": "None", + "xspi_reset_flash_mode": "Output", + "xspi_reset_flash_pull": "None", + "xspi_reset_flash_output_strength": "High", + "xspi_reset_flash_initial_output_state": "High", + "xspi_reset_flash_interrupt_trigger": "None", + "xspi_reset_flash_dont_conf": 0, + "xspi_cs_ram": 3, + "xspi_cs_ram_use_hw": "None", + "xspi_cs_ram_mode": "Output", + "xspi_cs_ram_pull": "None", + "xspi_cs_ram_output_strength": "High", + "xspi_cs_ram_initial_output_state": "High", + "xspi_cs_ram_interrupt_trigger": "None", + "xspi_cs_ram_dont_conf": 0, + "xspi_dqs": 30, + "xspi_dqs_use_hw": "None", + "xspi_dqs_mode": "Input", + "xspi_dqs_pull": "None", + "xspi_dqs_output_strength": "High", + "xspi_dqs_initial_output_state": "High", + "xspi_dqs_interrupt_trigger": "None", + "xspi_dqs_dont_conf": 0, + "xspi_reset_ram": 2, + "xspi_reset_ram_use_hw": "None", + "xspi_reset_ram_mode": "Input", + "xspi_reset_ram_pull": "None", + "xspi_reset_ram_output_strength": "High", + "xspi_reset_ram_initial_output_state": "High", + "xspi_reset_ram_interrupt_trigger": "None", + "xspi_reset_ram_dont_conf": 0 + }, + "xspi_operations": { + "xspi_operations_clocks": { + "clock_phase": 0, + "clock_polarity": 0, + "spi_mode": "2'b00" + }, + "xspi_operations_chip_select": { + "csda": 2, + "csdads": 0, + "cseot": 4, + "cssot": 1 + }, + "xspi_operations_reset": { + "flash_jedec_reset": 0, + "ram_jedec_reset": 0, + "flash_treset": 20, + "ram_treset": 20 + }, + "xspi_phy_operations": { + "flash_rx_dll_bypass_bit": 0, + "flash_dll_tx_delay": 22, + "flash_dll_rx_delay": 34, + "ram_rx_dll_bypass_bit": 0, + "ram_dll_tx_delay": 22, + "ram_dll_rx_delay": 34 + }, + "xspi_read_operations": { + "flash_dummy_rd_cycles": 4, + "flash_read_opcode": 11, + "suppl_flash_read_opcode": 0, + "ram_dummy_rd_cycles": 4, + "ram_read_opcode": 11, + "suppl_ram_read_opcode": 0, + "flash_non_cont_read_enable": 0, + "flash_max_read_jobs": 256, + "ram_non_cont_read_enable": 0, + "ram_max_read_jobs": 256, + "rww_en": 0, + "device_size": 4, + "number_of_banks": 1, + "bank_size": 4, + "mode_bit_enable": 0 + }, + "xspi_write_operations": { + "flash_address_and_data": { + "flash_dummy_wr_cycles": 0 + }, + "flash_command": { + "flash_write_opcode": 2, + "suppl_flash_write_opcode": 0 + }, + "ram_address_and_data": { + "ram_dummy_wr_cycles": 0 + }, + "ram_command": { + "ram_write_opcode": 2, + "suppl_ram_write_opcode": 0 + }, + "write_to_buffer": { + "flash_write_to_buffer_support": 0, + "ram_write_to_buffer_support": 0 + }, + "non_continuous_write": { + "flash_non_cont_write_enable": 0, + "flash_max_write_jobs": 64, + "ram_non_cont_write_enable": 0, + "ram_max_read_jobs": 0 + }, + "flash_program_operation": { + "flash_min_program_size": "256 B", + "flash_program_opcode": 2, + "suppl_flash_program_opcode": 0, + "flash_maximum_program_time_limit": 1600 + }, + "flash_erase_operation": { + "flash_min_erase_size": "4 kB", + "flash_erase_opcode": 32, + "suppl_flash_erase_opcode": 0, + "flash_maximum_erase_time_limit": 4095 + }, + "flash_erase_conf": { + "flash_block_erase_opcode": 0, + "suppl_block_flash_erase_opcode": 0, + "flash_sector_erase_opcode": 0, + "suppl_sector_flash_erase_opcode": 0, + "flash_chip_erase_opcode": 0, + "suppl_chip_flash_erase_opcode": 0 + }, + "ram_program_operation": { + "ram_min_program_size": "256 B", + "ram_program_opcode": 2, + "suppl_ram_program_opcode": 0, + "ram_maximum_program_time_limit": 1600 + }, + "ram_erase_conf": { + "ram_block_erase_opcode": 0, + "suppl_block_ram_erase_opcode": 0, + "ram_sector_erase_opcode": 0, + "suppl_sector_ram_erase_opcode": 0, + "ram_chip_erase_opcode": 0, + "suppl_chip_ram_erase_opcode": 0 + }, + "flash_buffer_support": { + "flash_pre_write_sequence": 0, + "flash_post_write_sequence": 0, + "flash_write_protection_timer_en": 0, + "flash_write_buffer_timer_mode": 16, + "flash_write_buffer_timer_range": 0, + "flash_service_interrupt_criteria": 0 + }, + "ram_buffer_support": { + "ram_pre_write_sequence": 0, + "ram_post_write_sequence": 0, + "ram_write_protection_timer_en": 0, + "ram_write_buffer_timer_mode": 16, + "ram_write_buffer_timer_range": 0, + "ram_service_interrupt_criteria": 0 + }, + "flash_pre_write_conf": { + "flash_pre_write_job_done_grant_sel": 0, + "data_for_flash_pre_write_conf_0": 0, + "offset_bits_for_flash_pre_write_conf_0": 0, + "stop_bit_for_flash_pre_write_conf_0": 1, + "data_for_flash_pre_write_conf_1": 0, + "offset_bits_for_flash_pre_write_conf_1": 0 + }, + "flash_post_write_conf": { + "flash_post_write_job_done_grant_sel": 0, + "data_for_flash_post_write_conf_0": 0, + "offset_bits_for_flash_post_write_conf_0": 0, + "stop_bit_for_flash_post_write_conf_0": 1, + "data_for_flash_post_write_conf_1": 0, + "offset_bits_for_flash_post_write_conf_1": 0 + }, + "ram_pre_write_conf": { + "ram_pre_write_job_done_grant_sel": 0, + "data_for_ram_pre_write_conf_0": 0, + "offset_bits_for_ram_pre_write_conf_0": 0, + "stop_bit_for_ram_pre_write_conf_0": 1, + "data_for_ram_pre_write_conf_1": 0, + "offset_bits_for_ram_pre_write_conf_1": 0 + }, + "ram_post_write_conf": { + "ram_post_write_job_done_grant_sel": 0, + "data_for_ram_post_write_conf_0": 0, + "offset_bits_for_ram_post_write_conf_0": 0, + "stop_bit_for_ram_post_write_conf_0": 1, + "data_for_ram_post_write_conf_1": 0, + "offset_bits_for_ram_post_write_conf_1": 0 + } + }, + "xspi_capture_operations": { + "read_data_capture": { + "flash_delay_transmitted_data": 0, + "flash_loopback_clock": 0, + "flash_bypass_adapted_loopback": 1, + "flash_sample_edge_sel": 0, + "ram_delay_transmitted_data": 0, + "ram_loopback_clock": 0, + "ram_bypass_adapted_loopback": 1, + "ram_sample_edge_sel": 0 + }, + "delays": { + "flash_full_half_cycle_delay": 0, + "flash_dll_bypass_mode": 1, + "flash_phase_detect_sel": 0, + "flash_dll_lock_num": 0, + "flash_dll_start_point": 0, + "flash_loopback_clock": 0, + "ram_full_half_cycle_delay": 0, + "ram_dll_bypass_mode": 1, + "ram_phase_detect_sel": 0, + "ram_dll_lock_num": 0, + "ram_dll_start_point": 0, + "ram_loopback_clock": 0 + }, + "operation_modes": { + "flash_sfdp_support": 0, + "ram_sfdp_support": 0, + "flash_pm_support": 0, + "ram_pm_support": 0, + "flash_sfdp_opcode": 0, + "suppl_flash_sfdp_opcode": 0, + "ram_sfdp_opcode": 0, + "suppl_ram_sfdp_opcode": 0, + "flash_enter_dpd_opcode": 185, + "suppl_flash_enter_dpd_opcode": 0, + "flash_exit_dpd_opcode": 171, + "suppl_flash_exit_dpd_opcode": 0, + "ram_enter_dpd_opcode": 185, + "suppl_ram_enter_dpd_opcode": 0, + "ram_exit_dpd_opcode": 171, + "suppl_ram_exit_dpd_opcode": 0, + "flash_quad_enable_opcode": 56, + "suppl_flash_quad_enable_opcode": 0, + "flash_quad_disable_opcode": 255, + "suppl_flash_quad_disable_opcode": 0, + "flash_octal_enable_opcode": 0, + "suppl_flash_octal_enable_opcode": 0, + "flash_octal_disable_opcode": 0, + "suppl_flash_octal_disable_opcode": 0, + "ram_quad_enable_opcode": 56, + "suppl_ram_quad_enable_opcode": 0, + "ram_quad_disable_opcode": 255, + "suppl_ram_quad_disable_opcode": 0, + "ram_octal_enable_opcode": 0, + "suppl_ram_octal_enable_opcode": 0, + "ram_octal_disable_opcode": 0, + "suppl_ram_octal_disable_opcode": 0 + } + } + }, + "external_memory_reporting": { + "header": { + "flash_auto_polling_enable": 1, + "flash_wel_enable": 1, + "flash_write_protect_enable": 0, + "flash_alternate_polling_conf_enable": 0, + "ram_auto_polling_enable": 1, + "ram_wel_enable": 1, + "ram_write_protect_enable": 0, + "ram_alternate_polling_conf_enable": 0 + }, + "flash_auto_polling": { + "flash_polling_repetition_delay": 0, + "flash_polling_count": 4, + "flash_enable_polling_expiration": 0, + "flash_polling_polarity": 0, + "flash_polling_address_phase_enable": 0, + "flash_polling_bit_index": 0, + "flash_numbers_poll_cycles": 65535, + "flash_dummy_autopoll_cycles": 0 + }, + "ram_auto_polling": { + "ram_polling_repetition_delay": 0, + "ram_polling_count": 4, + "ram_enable_polling_expiration": 0, + "ram_polling_polarity": 0, + "ram_polling_address_phase_enable": 0, + "ram_polling_bit_index": 0, + "ram_numbers_poll_cycles": 65535, + "ram_dummy_autopoll_cycles": 0 + }, + "flash_polling_command": { + "flash_polling_opcode": 5, + "suppl_flash_polling_opcode": 0 + }, + "ram_polling_command": { + "ram_polling_opcode": 5, + "suppl_ram_polling_opcode": 0 + }, + "flash_alternate_polling": { + "flash_polling_resp_count": 1023, + "flash_polling_iterations": 1, + "flash_polling_enabled": 0, + "flash_polling_disabled": 0, + "flash_grant_sel": 0, + "flash_data_for_enable_poling_conf_0": 0, + "flash_offset_bits_for_enable_poling_conf_0": 0, + "flash_stop_bit_for_enable_poling_conf_0": 1, + "flash_data_for_enable_poling_conf_1": 0, + "flash_offset_bits_for_enable_poling_conf_1": 0, + "flash_stop_bit_for_enable_poling_conf_1": 1, + "flash_data_for_disable_poling_conf_0": 0, + "flash_offset_bits_for_disable_poling_conf_0": 0, + "flash_stop_bit_for_disable_poling_conf_0": 1, + "flash_data_for_disable_poling_conf_1": 0, + "flash_offset_bits_for_disable_poling_conf_1": 0, + "flash_stop_bit_for_disable_poling_conf_1": 1 + }, + "ram_alternate_polling": { + "ram_polling_resp_count": 1023, + "ram_polling_iterations": 1, + "ram_polling_enabled": 0, + "ram_polling_disabled": 0, + "ram_grant_sel": 0, + "ram_data_for_enable_poling_conf_0": 0, + "ram_offset_bits_for_enable_poling_conf_0": 0, + "ram_stop_bit_for_enable_poling_conf_0": 1, + "ram_data_for_enable_poling_conf_1": 0, + "ram_offset_bits_for_enable_poling_conf_1": 0, + "ram_stop_bit_for_enable_poling_conf_1": 1, + "ram_data_for_disable_poling_conf_0": 0, + "ram_offset_bits_for_disable_poling_conf_0": 0, + "ram_stop_bit_for_disable_poling_conf_0": 1, + "ram_data_for_disable_poling_conf_1": 0, + "ram_offset_bits_for_disable_poling_conf_1": 0, + "ram_stop_bit_for_disable_poling_conf_1": 1 + }, + "flash_wel_command": { + "flash_wel_opcode": 6, + "suppl_flash_wel_opcode": 0 + }, + "ram_wel_command": { + "ram_wel_opcode": 6, + "suppl_ram_wel_opcode": 0 + } + }, + "event": { + "host_nvic_irq": 0, + "core_10_mux_sel": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/fuse_prog_inst_param.json b/boards/ti/lp_em_cc35x1/config/fuse_prog_inst_param.json new file mode 100644 index 000000000000..0f91637c9a86 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/fuse_prog_inst_param.json @@ -0,0 +1,43 @@ +{ + "rot": "@CC35XXE_ROT_PUBLIC_KEY@", + "security_failure_behavoral": 0, + "use_ti_root_of_trust_secondary": 0, + "boot_roll_back_protection_initial_version": 0, + "permanently_lock_debug_enable": 0, + "debug_rot_enable": 0, + "otfde_protection_enable": 0, + "action_request_authentication_enable": 0, + "vendor_sbl_container_enable": 0, + "vendor_container_authentication_enable": 0, + "vendor_sbl_roll_back_protection_initial_version": 0, + "vendor_app_roll_back_protection_initial_version": 0, + "wsoc_fw_roll_back_initial_version": 0, + "production_done": 0, + "debug_crc_enable": 0, + "sw_crc3_enable": 0, + "reserved3": 0, + "qspi_ospi_flash_type": 0, + "flash_exist": 1, + "boot_sector_programmed": 0, + "flash_reset_type": 0, + "slow_clock_source": 0, + "xtal_drift_calibration_room_temp": 0, + "otp_structure_version": 0, + "vendor_use_2": 0, + "vendor_use_1": 0, + "vendor_use_3": 0, + "wsoc_fw_rollback_protection_1": 0, + "wsoc_fw_rollback_protection_2": 0, + "wsoc_fw_rollback_protection_3": 0, + "ti_bootloader_fw_rollback_protection_1": 0, + "ti_bootloader_fw_rollback_protection_2": 0, + "ti_bootloader_fw_rollback_protection_3": 0, + "vendor_sbl_fw_rollback_protection_1": 0, + "vendor_sbl_fw_rollback_protection_2": 0, + "vendor_sbl_fw_rollback_protection_3": 0, + "vendor_image_rollback_protection_1": 0, + "vendor_image_rollback_protection_2": 0, + "vendor_image_rollback_protection_3": 0, + "debug_rot": "", + "app_otp": 0 +} diff --git a/boards/ti/lp_em_cc35x1/config/tool_settings.json b/boards/ti/lp_em_cc35x1/config/tool_settings.json new file mode 100644 index 000000000000..a8b2075bc449 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/tool_settings.json @@ -0,0 +1,60 @@ +{ + "ini_composer_outputs": { + "ini_to_h_paths": { + "ini_to_h": null + } + }, + "linker_update": { + "linker_cmd_paths": { + "linker_cmd_genlibs": null + } + }, + "vendor_unsigned_images_paths": { + "actions_req_paths": { + "query": null, + "programming": null, + "debug": null + }, + "vendor_images_paths": { + "programming_instructions": null, + "primary_vendor_image": null, + "secondary_vendor_image": null, + "primary_vendor_sbl": null, + "secondary_vendor_sbl": null + } + }, + "vendor_signed_container_and_action_req_generation": { + "signature_generation_info": { + "target_device_info": { + "id_list": {} + }, + "sig_generation_methodology": { + "type": "local" + }, + "public_key_path": null, + "info": null, + "siginning_credential": null, + "remote_serve_connection_info": null + } + }, + "programming_debug_and_ota_signed_components": { + "tbl_container_programming": null, + "primary_tbl": null, + "secondary_tbl": null, + "primary_ti_wsoc": null, + "secondary_ti_wsoc": null, + "primary_ti_wsoc_bl2": null, + "secondary_ti_wsoc_bl2": null, + "actions_req_paths": { + "query": null, + "programming": "zephyr/flash/programming_action_request.sign.bin", + "debug": "zephyr/flash/debug_action_request.sign.bin" + }, + "boot_sector": null, + "programming_instructions": "zephyr/flash/programming_instructions_image.sign.bin", + "primary_vendor_image": "zephyr/flash/vendor_image.sign.bin", + "secondary_vendor_image": null, + "primary_vendor_sbl": null, + "secondary_vendor_sbl": null + } +} diff --git a/soc/ti/simplelink/cc35xxe/CMakeLists.txt b/soc/ti/simplelink/cc35xxe/CMakeLists.txt index 24f3c720fab2..5a018df98010 100644 --- a/soc/ti/simplelink/cc35xxe/CMakeLists.txt +++ b/soc/ti/simplelink/cc35xxe/CMakeLists.txt @@ -5,4 +5,6 @@ zephyr_sources(soc.c) zephyr_include_directories(.) +set_target_properties(zephyr_property_target PROPERTIES SIGNING_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/toolbox.cmake) + set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/ti/simplelink/cc35xxe/Kconfig.soc b/soc/ti/simplelink/cc35xxe/Kconfig.soc index 7a77706c8951..c2a6ef947baa 100644 --- a/soc/ti/simplelink/cc35xxe/Kconfig.soc +++ b/soc/ti/simplelink/cc35xxe/Kconfig.soc @@ -19,3 +19,24 @@ config SOC_SERIES config SOC string default "cc3551e" if SOC_CC3551E + +config CC35XXE_SIGN_PRIVATE_KEY_FILE + string "Path to the private key used to sign the image" + +config CC35XXE_SIGN_PUBLIC_KEY_FILE + string "Path to the public key used to sign the image" + +config CC35XXE_FLASH_DISCOVERY_CONFIG_OTFDE + string "Path to the OTFDE configuration file" + +config CC35XXE_FLASH_DISCOVERY_CONFIG_EXT_MEM + string "Path to the external memory configuration file" + +config CC35XXE_FLASH_DISCOVERY_CONFIG_XSPI + string "Path to the xSPI configuration file" + +config CC35XXE_FUSE_CONFIG + string "Path to the fuse configuration file" + +config CC35XXE_ACTION_PARAMS_FILE + string "Path to the action parameters file" diff --git a/soc/ti/simplelink/cc35xxe/keys/cc35x1e_lp_em_prv_key.pem b/soc/ti/simplelink/cc35xxe/keys/cc35x1e_lp_em_prv_key.pem new file mode 100644 index 000000000000..03241165a161 --- /dev/null +++ b/soc/ti/simplelink/cc35xxe/keys/cc35x1e_lp_em_prv_key.pem @@ -0,0 +1,5 @@ +-----BEGIN EC PRIVATE KEY----- +MHcCAQEEIL/UE5EzkLLndTQIzeFk7F0q76vw8+cM6trcLj9RUd1LoAoGCCqGSM49 +AwEHoUQDQgAEieMCg+Jw5Mt3k28QlvkxK3DlvLbXO7znS42d1xBj2Xy9G9AFdqZe +oYqT25ig7RA6EHt/DJrJc7zIXGCZvf4Kxg== +-----END EC PRIVATE KEY----- diff --git a/soc/ti/simplelink/cc35xxe/keys/cc35x1e_lp_em_pub_key.pem b/soc/ti/simplelink/cc35xxe/keys/cc35x1e_lp_em_pub_key.pem new file mode 100644 index 000000000000..b0f384b535e7 --- /dev/null +++ b/soc/ti/simplelink/cc35xxe/keys/cc35x1e_lp_em_pub_key.pem @@ -0,0 +1,4 @@ +-----BEGIN PUBLIC KEY----- +MFkwEwYHKoZIzj0CAQYIKoZIzj0DAQcDQgAEieMCg+Jw5Mt3k28QlvkxK3DlvLbX +O7znS42d1xBj2Xy9G9AFdqZeoYqT25ig7RA6EHt/DJrJc7zIXGCZvf4Kxg== +-----END PUBLIC KEY----- diff --git a/soc/ti/simplelink/cc35xxe/toolbox.cmake b/soc/ti/simplelink/cc35xxe/toolbox.cmake new file mode 100644 index 000000000000..b33382826182 --- /dev/null +++ b/soc/ti/simplelink/cc35xxe/toolbox.cmake @@ -0,0 +1,134 @@ +# Copyright (c) 2025 Conclusive Engineering Sp. z o.o. +# +# SPDX-License-Identifier: Apache-2.0 + +function(zephyr_simplelink_tasks) + set(SOC_DIR ${CMAKE_CURRENT_LIST_DIR}) + + string(CONFIGURE "${CONFIG_CC35XXE_SIGN_PUBLIC_KEY_FILE}" pubkey) + string(CONFIGURE "${CONFIG_CC35XXE_SIGN_PRIVATE_KEY_FILE}" privkey) + string(CONFIGURE "${CONFIG_CC35XXE_FLASH_DISCOVERY_CONFIG_OTFDE}" otfde) + string(CONFIGURE "${CONFIG_CC35XXE_FLASH_DISCOVERY_CONFIG_EXT_MEM}" ext_mem) + string(CONFIGURE "${CONFIG_CC35XXE_FLASH_DISCOVERY_CONFIG_XSPI}" xspi) + string(CONFIGURE "${CONFIG_CC35XXE_FUSE_CONFIG}" fuse_config) + string(CONFIGURE "${CONFIG_CC35XXE_ACTION_PARAMS_FILE}" action_params) + + # Use default keys if not set + if("${pubkey}" STREQUAL "") + set(pubkey "${SOC_DIR}/keys/cc35x1e_lp_em_pub_key.pem") + endif() + + if(NOT EXISTS "${pubkey}") + message(FATAL_ERROR "Public key file not found: ${pubkey}") + endif() + + if("${privkey}" STREQUAL "") + set(privkey "${SOC_DIR}/keys/cc35x1e_lp_em_prv_key.pem") + endif() + + if(NOT EXISTS "${privkey}") + message(FATAL_ERROR "Private key file not found: ${privkey}") + endif() + + # Use default config jsons if not set + if("${otfde}" STREQUAL "") + set(otfde "${BOARD_DIR}/config/flash_disc_param_otfde.json") + endif() + + if(NOT EXISTS "${otfde}") + message(FATAL_ERROR "OTFDE config file not found: ${otfde}") + endif() + + if("${ext_mem}" STREQUAL "") + set(ext_mem "${BOARD_DIR}/config/flash_disc_param_ext_mem.json") + endif() + + if(NOT EXISTS "${ext_mem}") + message(FATAL_ERROR "External memory config file not found: ${ext_mem}") + endif() + + if("${xspi}" STREQUAL "") + set(xspi "${BOARD_DIR}/config/flash_disc_param_xspi.json") + endif() + + if(NOT EXISTS "${xspi}") + message(FATAL_ERROR "xSPI config file not found: ${xspi}") + endif() + + if("${fuse_config}" STREQUAL "") + set(fuse_config "${BOARD_DIR}/config/fuse_prog_inst_param.json") + endif() + + if(NOT EXISTS "${fuse_config}") + message(FATAL_ERROR "Fuse config file not found: ${fuse_config}") + endif() + + if("${action_params}" STREQUAL "") + set(action_params "${BOARD_DIR}/config/action_params.json") + endif() + + if(NOT EXISTS "${action_params}") + message(FATAL_ERROR "Action parameters file not found: ${action_params}") + endif() + + set(outdir ${ZEPHYR_BINARY_DIR}/flash) + set(output ${ZEPHYR_BINARY_DIR}/${KERNEL_NAME}) + + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND + simplelink-wifi-toolbox flash-images-builder build programming_image + --flash_discovery_config_otfde ${otfde} + --flash_discovery_config_ext_mem ${ext_mem} + --flash_discovery_config_xspi ${xspi} + --fuses_programming_instructions ${fuse_config} + --dir_out_path ${outdir} + --use_my_jsons) + + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND + simplelink-wifi-toolbox flash-images-builder sign programming_image + --unsign_image ${outdir}/programming_instructions_image.unsign.bin + --private_key ${privkey} --public_key ${pubkey} + --dir_out_path ${outdir}) + + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND + simplelink-wifi-toolbox flash-images-builder build action_request + --type programming + --params_json ${action_params} + --dir_out_path ${outdir}) + + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND + simplelink-wifi-toolbox flash-images-builder sign action_request + --unsign_request ${outdir}/programming_action_request.unsign.bin + --private_key ${privkey} --public_key ${pubkey} + --dir_out_path ${outdir}) + + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND + simplelink-wifi-toolbox flash-images-builder build action_request + --type debug + --params_json ${action_params} + --dir_out_path ${outdir}) + + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND + simplelink-wifi-toolbox flash-images-builder sign action_request + --unsign_request ${outdir}/debug_action_request.unsign.bin + --private_key ${privkey} --public_key ${pubkey} + --dir_out_path ${outdir}) + + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND + simplelink-wifi-toolbox flash-images-builder build vendor_image + --vendor_out_file ${output}.elf + --dir_out_path ${outdir}) + + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND + simplelink-wifi-toolbox flash-images-builder sign vendor_image + --unsign_image ${outdir}/vendor_image.unsign.bin + --private_key ${privkey} --public_key ${pubkey} + --dir_out_path ${outdir}) + + set_property(GLOBAL APPEND PROPERTY extra_post_build_byproducts + "${outdir}/programming_instructions_image.sign.bin" + "${outdir}/programming_action_request.sign.bin" + "${outdir}/debug_action_request.sign.bin" + "${outdir}/vendor_image.sign.bin") +endfunction() + +zephyr_simplelink_tasks() From 8e2278804f51ec10fb083791d5078a30f2867bf9 Mon Sep 17 00:00:00 2001 From: Artur Rojek Date: Mon, 9 Feb 2026 18:49:57 +0100 Subject: [PATCH 008/100] UPSTREAM-PEND: cc35xxe: Update toolbox configuration for PG2 Provide configuration update necessary for usage with Simplelink Toolbox in version v4.0.13.1. Signed-off-by: Artur Rojek --- .../ti/lp_em_cc35x1/config/action_params.json | 19 ++++--- .../config/flash_disc_param_ext_mem.json | 52 +++++++++---------- .../config/flash_disc_param_otfde.json | 28 +++++----- .../config/flash_disc_param_xspi.json | 6 +-- .../config/fuse_prog_inst_param.json | 29 ++++------- .../ti/lp_em_cc35x1/config/tool_settings.json | 3 +- 6 files changed, 67 insertions(+), 70 deletions(-) diff --git a/boards/ti/lp_em_cc35x1/config/action_params.json b/boards/ti/lp_em_cc35x1/config/action_params.json index cf37b571a6fb..238f095917b7 100644 --- a/boards/ti/lp_em_cc35x1/config/action_params.json +++ b/boards/ti/lp_em_cc35x1/config/action_params.json @@ -8,6 +8,7 @@ "payload": { "prog_req_content": { "fuse_programming_instruction_update": false, + "flash_factory_reset": false, "boot_sector": false, "primary_tbl": false, "secondary_tbl": false, @@ -18,10 +19,12 @@ "primary_ti_wsoc": false, "secondary_ti_wsoc": false, "primary_ti_wsoc_bl2": false, - "secondary_ti_wsoc_bl2": false + "secondary_ti_wsoc_bl2": false, + "protected_storage": false }, "prog_validation": { "fuse_programming_instruction_update": false, + "flash_factory_reset": false, "boot_sector": false, "primary_tbl": false, "secondary_tbl": false, @@ -32,7 +35,8 @@ "primary_ti_wsoc": false, "secondary_ti_wsoc": false, "primary_ti_wsoc_bl2": false, - "secondary_ti_wsoc_bl2": false + "secondary_ti_wsoc_bl2": false, + "protected_storage": false } } } @@ -45,8 +49,8 @@ "type_version": 0, "payload": { "query_req_content": { - "boot_sector_query": false, - "primary_ti_bootloader_query": false, + "boot_sector_query": true, + "primary_ti_bootloader_query": true, "secondary_ti_bootloader_query": false, "primary_vendor_image_query": false, "primary_vendor_sbl_query": false, @@ -55,7 +59,8 @@ "primary_ti_wsoc_query": false, "secondary_ti_wsoc_query": false, "primary_ti_wsoc_bl2_query": false, - "secondary_ti_wsoc_bl2_query": false + "secondary_ti_wsoc_bl2_query": false, + "protected_storage_query": false } } } @@ -117,13 +122,13 @@ "enter_rma_option": { "invalidate_vendor_rot_fuses": false, "invalidate_other_vendor_fuses": false, - "invalidate_all_vendor_images": false, + "invalidate_all_vendor_components": false, "invalidate_internal_memory": false }, "enter_rma_validation": { "invalidate_vendor_rot_fuses_validate": false, "invalidate_other_vendor_fuses_validate": false, - "invalidate_all_vendor_images_validate": false, + "invalidate_all_vendor_components_validate": false, "invalidate_internal_memory_validate": false } } diff --git a/boards/ti/lp_em_cc35x1/config/flash_disc_param_ext_mem.json b/boards/ti/lp_em_cc35x1/config/flash_disc_param_ext_mem.json index d054c36fe29d..88025484f500 100644 --- a/boards/ti/lp_em_cc35x1/config/flash_disc_param_ext_mem.json +++ b/boards/ti/lp_em_cc35x1/config/flash_disc_param_ext_mem.json @@ -1,16 +1,16 @@ { - "vendor_primary_sbl": false, + "vendor_primary_sbl": true, "ti_wsoc_primary_container": true, "ti_wsoc_bl2_primary_container": true, - "nvs_enable": false, - "vendor_alternate_image": false, - "vendor_sbl_alternate_image": false, - "ti_bl_alternate_image": false, - "ti_wsoc_alternate_image": false, - "ti_wsoc_bl2_alternate_image": false, + "nvs_enable": true, + "vendor_alternate_image": true, + "vendor_sbl_alternate_image": true, + "ti_bl_alternate_image": true, + "ti_wsoc_alternate_image": true, + "ti_wsoc_bl2_alternate_image": true, "region_0": { - "mem_region_0_start_phy_address": 208896, - "mem_region_0_end_phy_address": 2203647, + "mem_region_0_start_phy_address": 1069056, + "mem_region_0_end_phy_address": 4194303, "region0_boot": false, "region0_main_code": true, "region0_nvs": false, @@ -18,17 +18,17 @@ "region0_alternate_code": false }, "region_1": { - "mem_region_1_start_phy_address": 2203648, - "mem_region_1_end_phy_address": 4190207, - "region1_boot": false, + "mem_region_1_start_phy_address": 0, + "mem_region_1_end_phy_address": 1069055, + "region1_boot": true, "region1_main_code": false, "region1_nvs": true, "region1_wsoc_code": true, "region1_alternate_code": false }, "region_2": { - "mem_region_2_start_phy_address": 14888960, - "mem_region_2_end_phy_address": 26423295, + "mem_region_2_start_phy_address": 0, + "mem_region_2_end_phy_address": 0, "region2_boot": false, "region2_main_code": false, "region2_nvs": false, @@ -37,8 +37,8 @@ }, "region_3": { "mem_region_3_start_phy_address": 0, - "mem_region_3_end_phy_address": 208895, - "region3_boot": true, + "mem_region_3_end_phy_address": 0, + "region3_boot": false, "region3_main_code": false, "region3_nvs": false, "region3_wsoc_code": false, @@ -47,27 +47,27 @@ "boot_region_conf": { "boot_region_size": 0, "boot_region_flash_disco_param_start_address": 0, - "boot_region_primary_ti_bl_start_phy_address": 8188, + "boot_region_primary_ti_bl_start_phy_address": 12284, "boot_region_primary_ti_bl_magic": 0, "boot_region_primary_ti_bl_major": 0, "boot_region_primary_ti_bl_minor": 0, - "boot_region_sec_ti_bl_start_phy_address": 0, + "boot_region_sec_ti_bl_start_phy_address": 430076, "boot_region_sec_ti_bl_magic": 0, "boot_region_sec_ti_bl_major": 0, "boot_region_sec_ti_bl_minor": 0 }, "main_code_region_conf": { - "main_code_region_vendor_image_start_phy_address": 212988, + "main_code_region_vendor_image_start_phy_address": 1073148, "main_code_region_vendor_image_magic": 0, "main_code_region_vendor_image_major": 0, "main_code_region_vendor_image_minor": 0, - "main_code_region_sbl_start_phy_address": 10698748, + "main_code_region_sbl_start_phy_address": 0, "main_code_region_sbl_magic": 0, "main_code_region_sbl_major": 0, "main_code_region_sbl_minor": 0 }, "alt_code_region_conf": { - "alt_code_region_vendor_image_start_phy_address": 0, + "alt_code_region_vendor_image_start_phy_address": 4194304, "alt_code_region_vendor_image_magic": 0, "alt_code_region_vendor_image_major": 0, "alt_code_region_vendor_image_minor": 0, @@ -77,13 +77,13 @@ "alt_code_region_sbl_minor": 0 }, "nvs_code_region_conf": { - "nvs_start_phy_address": 0, - "nvs_region_size": 0, - "nvs_region_primary_wsoc_start_phy_address": 0, + "nvs_start_phy_address": 892928, + "nvs_region_size": 176128, + "nvs_region_primary_wsoc_start_phy_address": 430076, "nvs_region_primary_wsoc_magic": 0, "nvs_region_primary_wsoc_major": 0, "nvs_region_primary_wsoc_minor": 0, - "nvs_region_sec_wsoc_start_phy_address": 0, + "nvs_region_sec_wsoc_start_phy_address": 897020, "nvs_region_sec_wsoc_magic": 0, "nvs_region_sec_wsoc_major": 0, "nvs_region_sec_wsoc_minor": 0, @@ -96,4 +96,4 @@ "nvs_region_sec_wsoc_bl2_major": 0, "nvs_region_sec_wsoc_bl2_minor": 0 } -} +} \ No newline at end of file diff --git a/boards/ti/lp_em_cc35x1/config/flash_disc_param_otfde.json b/boards/ti/lp_em_cc35x1/config/flash_disc_param_otfde.json index 6c6c2219e54e..635e11319c5d 100644 --- a/boards/ti/lp_em_cc35x1/config/flash_disc_param_otfde.json +++ b/boards/ti/lp_em_cc35x1/config/flash_disc_param_otfde.json @@ -79,23 +79,23 @@ "mem_region_0_device_id": 0, "mem_region_0_spi_write_enable": true, "mem_region_0_spi_read_enable": true, - "mem_region_0_physical_offset": 51, + "mem_region_0_physical_offset": 261, "mem_region_0_security_id_msb": 0, - "mem_region_0_start_address": 65536, - "mem_region_0_end_address": 66022, + "mem_region_0_start_address": 81920, + "mem_region_0_end_address": 82682, "mem_region_0_security_id_lsb": 0, "mem_otfde_region_0_write_lock_en": false, - "mem_otfde_region_0_enc_dec_bypass": "Bypass" + "mem_otfde_region_0_enc_dec_bypass": "EncryptOrDecrypt" }, "region_1_protection": { "mem_region_1_enabled": true, "mem_region_1_device_id": 0, "mem_region_1_spi_write_enable": true, "mem_region_1_spi_read_enable": true, - "mem_region_1_physical_offset": 458, + "mem_region_1_physical_offset": 0, "mem_region_1_security_id_msb": 0, - "mem_region_1_start_address": 655440, - "mem_region_1_end_address": 655925, + "mem_region_1_start_address": 655360, + "mem_region_1_end_address": 655620, "mem_region_1_security_id_lsb": 0, "mem_otfde_region_1_write_lock_en": false, "mem_otfde_region_1_enc_dec_bypass": "Bypass" @@ -103,25 +103,25 @@ "region_2_protection": { "mem_region_2_enabled": false, "mem_region_2_device_id": 0, - "mem_region_2_spi_write_enable": false, - "mem_region_2_spi_read_enable": false, + "mem_region_2_spi_write_enable": true, + "mem_region_2_spi_read_enable": true, "mem_region_2_physical_offset": 0, "mem_region_2_security_id_msb": 0, "mem_region_2_start_address": 1, "mem_region_2_end_address": 0, "mem_region_2_security_id_lsb": 0, "mem_otfde_region_2_write_lock_en": false, - "mem_otfde_region_2_enc_dec_bypass": "Bypass" + "mem_otfde_region_2_enc_dec_bypass": "EncryptOrDecrypt" }, "region_3_protection": { - "mem_region_3_enabled": true, - "mem_region_3_device_id": 0, + "mem_region_3_enabled": false, + "mem_region_3_device_id": 1, "mem_region_3_spi_write_enable": true, "mem_region_3_spi_read_enable": true, "mem_region_3_physical_offset": 0, "mem_region_3_security_id_msb": 0, - "mem_region_3_start_address": 655360, - "mem_region_3_end_address": 655410, + "mem_region_3_start_address": 1, + "mem_region_3_end_address": 0, "mem_region_3_security_id_lsb": 0, "mem_otfde_region_3_write_lock_en": false, "mem_otfde_region_3_enc_dec_bypass": "Bypass" diff --git a/boards/ti/lp_em_cc35x1/config/flash_disc_param_xspi.json b/boards/ti/lp_em_cc35x1/config/flash_disc_param_xspi.json index 691dcf45cba8..57b1c8146a1a 100644 --- a/boards/ti/lp_em_cc35x1/config/flash_disc_param_xspi.json +++ b/boards/ti/lp_em_cc35x1/config/flash_disc_param_xspi.json @@ -38,7 +38,7 @@ "ram_dual_opcode": 0, "ram_jedec_manufacturer_id": 0, "ram_jedec_device_id": 0, - "ram_name": "IS25WJ032F", + "ram_name": "NO_PSRAM", "ram_page_size": 256, "ram_sector_size": 4096, "ram_cs_polarity": "ACTIVE_LOW", @@ -246,7 +246,7 @@ "flash_non_cont_write_enable": 0, "flash_max_write_jobs": 64, "ram_non_cont_write_enable": 0, - "ram_max_read_jobs": 0 + "ram_max_write_jobs": 0 }, "flash_program_operation": { "flash_min_program_size": "256 B", @@ -482,4 +482,4 @@ "host_nvic_irq": 0, "core_10_mux_sel": 0 } -} +} \ No newline at end of file diff --git a/boards/ti/lp_em_cc35x1/config/fuse_prog_inst_param.json b/boards/ti/lp_em_cc35x1/config/fuse_prog_inst_param.json index 0f91637c9a86..7c75c3af701d 100644 --- a/boards/ti/lp_em_cc35x1/config/fuse_prog_inst_param.json +++ b/boards/ti/lp_em_cc35x1/config/fuse_prog_inst_param.json @@ -1,31 +1,24 @@ { - "rot": "@CC35XXE_ROT_PUBLIC_KEY@", + "rot": null, "security_failure_behavoral": 0, "use_ti_root_of_trust_secondary": 0, - "boot_roll_back_protection_initial_version": 0, - "permanently_lock_debug_enable": 0, - "debug_rot_enable": 0, "otfde_protection_enable": 0, "action_request_authentication_enable": 0, "vendor_sbl_container_enable": 0, "vendor_container_authentication_enable": 0, - "vendor_sbl_roll_back_protection_initial_version": 0, - "vendor_app_roll_back_protection_initial_version": 0, - "wsoc_fw_roll_back_initial_version": 0, - "production_done": 0, - "debug_crc_enable": 0, - "sw_crc3_enable": 0, - "reserved3": 0, + "application_otp_usage": 1, + "crda_code_enable": 0, + "permanently_lock_debug_enable": 0, + "wifi6_disable": 0, "qspi_ospi_flash_type": 0, "flash_exist": 1, "boot_sector_programmed": 0, "flash_reset_type": 0, - "slow_clock_source": 0, - "xtal_drift_calibration_room_temp": 0, "otp_structure_version": 0, - "vendor_use_2": 0, - "vendor_use_1": 0, - "vendor_use_3": 0, + "vendor_restricted_ini": 0, + "mac_address_31_0": 0, + "mac_address_47_32": 0, + "crda_country_code": 0, "wsoc_fw_rollback_protection_1": 0, "wsoc_fw_rollback_protection_2": 0, "wsoc_fw_rollback_protection_3": 0, @@ -37,7 +30,5 @@ "vendor_sbl_fw_rollback_protection_3": 0, "vendor_image_rollback_protection_1": 0, "vendor_image_rollback_protection_2": 0, - "vendor_image_rollback_protection_3": 0, - "debug_rot": "", - "app_otp": 0 + "app_otp": "" } diff --git a/boards/ti/lp_em_cc35x1/config/tool_settings.json b/boards/ti/lp_em_cc35x1/config/tool_settings.json index a8b2075bc449..d32bb433df56 100644 --- a/boards/ti/lp_em_cc35x1/config/tool_settings.json +++ b/boards/ti/lp_em_cc35x1/config/tool_settings.json @@ -55,6 +55,7 @@ "primary_vendor_image": "zephyr/flash/vendor_image.sign.bin", "secondary_vendor_image": null, "primary_vendor_sbl": null, - "secondary_vendor_sbl": null + "secondary_vendor_sbl": null, + "protected_storage": null } } From 7d7380f838cc8d945677c7628cfcfd0b4f10862e Mon Sep 17 00:00:00 2001 From: Jakub Jarosinski Date: Mon, 22 Jun 2026 22:39:21 +0200 Subject: [PATCH 009/100] UPSTREAM-PEND: build: embed cc35xx-conf.bin generation into vendor image Generate the TI connectivity configuration binary during the Zephyr build and pass it to the SimpleLink toolbox vendor image builder. Signed-off-by: Jakub Jarosinski --- soc/ti/simplelink/cc35xxe/Kconfig.soc | 8 + .../simplelink/cc35xxe/conf/cc35xx-conf.ini | 86 ++ soc/ti/simplelink/cc35xxe/conf/conf.key | 1 + soc/ti/simplelink/cc35xxe/conf/conf_cc35xx.h | 946 ++++++++++++++++++ .../cc35xxe/conf/default_cc35xx.conf | 435 ++++++++ .../cc35xxe/conf/dictionary_cc35xx.txt | 64 ++ soc/ti/simplelink/cc35xxe/toolbox.cmake | 18 + 7 files changed, 1558 insertions(+) create mode 100644 soc/ti/simplelink/cc35xxe/conf/cc35xx-conf.ini create mode 100644 soc/ti/simplelink/cc35xxe/conf/conf.key create mode 100644 soc/ti/simplelink/cc35xxe/conf/conf_cc35xx.h create mode 100644 soc/ti/simplelink/cc35xxe/conf/default_cc35xx.conf create mode 100644 soc/ti/simplelink/cc35xxe/conf/dictionary_cc35xx.txt diff --git a/soc/ti/simplelink/cc35xxe/Kconfig.soc b/soc/ti/simplelink/cc35xxe/Kconfig.soc index c2a6ef947baa..9377098ff0a3 100644 --- a/soc/ti/simplelink/cc35xxe/Kconfig.soc +++ b/soc/ti/simplelink/cc35xxe/Kconfig.soc @@ -40,3 +40,11 @@ config CC35XXE_FUSE_CONFIG config CC35XXE_ACTION_PARAMS_FILE string "Path to the action parameters file" + +config CC35XXE_CONF_INI_FILE + string "Path to the cc35xx-conf.ini file" + help + Override the default cc35xx-conf.ini file used to generate + cc35xx-conf.bin during the build. If left empty, the in-tree + default at soc/ti/simplelink/cc35xxe/conf/cc35xx-conf.ini is + used. diff --git a/soc/ti/simplelink/cc35xxe/conf/cc35xx-conf.ini b/soc/ti/simplelink/cc35xxe/conf/cc35xx-conf.ini new file mode 100644 index 000000000000..8cabe2242bdc --- /dev/null +++ b/soc/ti/simplelink/cc35xxe/conf/cc35xx-conf.ini @@ -0,0 +1,86 @@ +################################################## +## CC33XX INI Template ## +## All Param values are in HEX ## +################################################## + + +StaPowerSave = 00 # 00: Enabled (behavior according to PowerSaveScheme), 01: Disable (always active) +PowerSaveScheme = 05 # Power Save Scheme - 0 (PS_SCHEME_LEGACY), 1 (PS_SCHEME_UPSD_TRIGGER), 5 (PS_SCHEME_NOPSPOLL) +HE_Enable = 01 # Enable HE (11ax) +ListenInterval = 01 # Listen interval, when waking up for nDTIM (Only activated if WakeUpEvent is set to nDTIM), range 1-10 +WakeUpEvent = 01 # Firmware wakeup conditions configuration – 0x0 (beacon) / 0x1 (DTIM) / 0x2 (nDTIM) +ApMaxNumStations = 04 # (ApMaxNumStations can be either 4 decimal or 16 decimal ) -> 4 or 10 Hex +MaxRxAmpduLen = 00 # Sets the maximum A-MPDU size that the device can receive. 00: 8k bytes, 01: 16k bytes + +EnableBle = 01 # Enable BLE +DisableLogger = 00 # Disable Logger Prints (Except For FW Init Logs) +MixedModeSupport = 01 # Enables connection to AP’s with WPA mixed mode configuration +CountryCode = 3030 # World Wide (two letter country code) +DefaultAntenna = 00 # Default antenna to use: 0/1 + +# XTAL Settling Time +XTAL_SettlingTime = 6A5 # Units in us + +#Slow Clock Params +SlowClk_SampledCycles = 04 # Number of cycles to sample the slow clock +SlowClockSource = 00 # 0 = Internal Slow Clock, 1 = External Slow Clock + +#Slow Clock Drift +InternalSlowClkDrift_WakeupEarlier = 189C # Wakeup Earlier offset In Units of ppm, Default Value For Internal Slow Clock is 6300 (0x189C), External Slow Clock +InternalSlowClkDrift_OpenWindowLonger = 4588 # Beacon Open Window Offset As Result of Slow Clock Drift, For Internal Slow Clock Default is 17800ppm (0x4588) + +#External Slow Clock Drift +ExtSlowClkDrift_WakeupEarlier = 1F4 # Wakeup Earlier offset In Units of ppm, Default Value For Internal Slow Clock is 500 (0x1F4), External Slow Clock +ExtSlowClkDrift_OpenWindowLonger = 1F4 # Beacon Open Window Offset As Result of Slow Clock Drift, For Internal Slow Clock Default is 500ppm (0x1F4) + +BleUartBaudrate = 1c200 # 115200 in decimal, Ble Uart BaudRate +EnableUartFlowCtrl = 01 # Enable/Disable Uart Flow Control +BleDefaultTxPower = 0A # Default BLE TX Power in dBm: 0/5/10/20 + +OneTimeCalibrationOnly = 00 # Enable One Time calibration Only (Default is periodic Calibration) + +# |_________________CH 1_________________|_________________CH 2_________________|_________________CH 3_________________|_________________CH 4_________________|_________________CH 5_________________|_________________CH 6_________________|_________________CH 7_________________|_________________CH 8_________________|_________________CH 9_________________|_________________CH 10________________|_________________CH 11________________|_________________CH 12________________|_________________CH 13________________|_________________CH 14________________|_________________CH 36________________|_________________CH 40________________|_________________CH 44________________|_________________CH 48________________|_________________CH 52________________|_________________CH 56________________|_________________CH 60________________|_________________CH 64________________|________________CH 100________________|_________________CH 104_______________|_________________CH 108_______________|_________________CH 112_______________|_________________CH 116_______________|_________________CH 120_______________|_________________CH 124_______________|_________________CH 128_______________|_________________CH 132_______________|_________________CH 136_______________|_________________CH 140_______________|_________________CH 144_______________|_________________CH 149_______________|_________________CH 153_______________|_________________CH 157_______________|_________________CH 161_______________|_________________CH 165_______________|_________________CH 169_______________| +PowerLimitArray = 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f # Per channel power limit parameters, channel 14 not supported + +InsertionLoss_2_4GHz = 00 00 # [Trace to Ant-1, Trace to Ant-2]. Board trace loss for 2.4GHz band +InsertionLoss_5GHz = 00 00 # [Trace to Ant-1, Trace to Ant-2]. Board trace loss for 5GHz band +AntGain_2_4GHz = 00 00 # [Ant-1, Ant-2]. Antenna gain for 2.4GHz band +AntGain_5GHz = 00 00 # [Ant-1, Ant-2]. Antenna gain for 5GHz band +BleChLim1M = ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff # BLE Reg Domain +BleChLim2M = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # BLE Reg Domain - 2M PHY disabled (PG2 firmware bug) +IsDiplexerPresent = 01 # 0: Diplexer doesn’t exist; 1: Diplexer exists. Is diplexer for combining 2.4GHz trace and 5GHz traces, exists on board +NumOfAntennas = 01 # 1: Single antenna; 2: Two antennas. Number of antennas on board. Two for diversity. +RegDomain = 00 # 0: World Wide; 1: FCC; 2: ETSI +TxPsatCompensation_2_4GHz = 00 # PSAT compensation for 2.4GHz band. Can be used to reduce power by up to 1 dB in designs with excessive power. Possible values: 0 = 0dB, 1 = 0.5dB, 2 = 1dB. +TxPsatCompensation_5GHz = 00 # PSAT compensation for 5GHz band. Can be used to reduce power by up to 1 dB in designs with excessive power. Possible values: 0 = 0dB, 1 = 0.5dB, 2 = 1dB. + +# IOMUX pull value: 01-Pull up , 02-Pull down , 03-Pull disable , ff-default +# any other pull value isn't allowed +SLOW_CLOCK_IN_pull_val = ff +SDIO_CLK_pull_val = ff +SDIO_CMD_pull_val = ff +SDIO_D0_pull_val = ff +SDIO_D1_pull_val = ff +SDIO_D2_pull_val = ff +SDIO_D3_pull_val = ff +HOST_IRQ_WL_pull_val = ff +UART1_TX_pull_val = ff +UART1_RX_pull_val = ff +UART1_CTS_pull_val = ff +UART1_RTS_pull_val = ff +COEX_PRIORITY_pull_val = ff +COEX_REQ_pull_val = ff +COEX_GRANT_pull_val = ff +HOST_IRQ_BLE_pull_val = ff +FAST_CLK_REQ_pull_val = ff +ANT_SEL_pull_val = ff + +Is_ExtSoC_Connected = 00 # Yes/No Choose if External SoC entity is connected - 1 - YES, 0 - NO +ExtSoC_grant_polarity = 01 # External SoC grant polarity - 0 - Active High, 1 - Active Low (Default) +ExtSoC_priority_polarity = 01 # External SoC priority polarity - 0 - Active Low, 1 - Active High (Default) +ExtSoC_request_polarity = 01 # External SoC request polarity - 0 - Active Low, 1 - Active High (Default) +ExtSoC_min_grant_time = 96 # 150 in decimal, Minimum grant time for External SoC +ExtSoC_max_grant_time = 3fff # 16383 in decimal, Maximum available grant time for External SoC +ExtSoC_t2_time = 05 # T2 time for External SoC +ExtSoC_to_wifi_grant_delay = 1e # 30 in decimal, Maximum time for changing the grant from External SoC to WiFi +ExtSoC_to_ble_grant_delay = 23 # 35 in decimal, Maximum time for changing the grant from External SoC to BLE diff --git a/soc/ti/simplelink/cc35xxe/conf/conf.key b/soc/ti/simplelink/cc35xxe/conf/conf.key new file mode 100644 index 000000000000..e79e876aae97 --- /dev/null +++ b/soc/ti/simplelink/cc35xxe/conf/conf.key @@ -0,0 +1 @@ +0x00000000 diff --git a/soc/ti/simplelink/cc35xxe/conf/conf_cc35xx.h b/soc/ti/simplelink/cc35xxe/conf/conf_cc35xx.h new file mode 100644 index 000000000000..57490bf12629 --- /dev/null +++ b/soc/ti/simplelink/cc35xxe/conf/conf_cc35xx.h @@ -0,0 +1,946 @@ +/* + * This file is part of CC33XX + * + * Copyright (C) 2023 Texas Instruments + * + * Author: Bashar Badir + * + */ + +#ifndef __CONF_H__ +#define __CONF_H__ + +struct cc33xx_conf_header { + uint32_t magic; + uint16_t fw_major_version; + uint16_t fw_minor_version; + uint16_t fw_api_version; + uint16_t fw_build_version; + uint8_t sp_major_version; + uint8_t sp_minor_version; + uint16_t sp_revision_version; + uint32_t sp_build_version; + uint32_t checksum; +} __attribute__((__packed__)); + +#define CC33XX_CONF_MAGIC 0x10e100ca + +#define CC33XX_CONF_FW_MAJOR_VERSION 0x0001 +#define CC33XX_CONF_FW_MINOR_VERSION 0x0007 +#define CC33XX_CONF_FW_API_VERSION 0x0000 +#define CC33XX_CONF_FW_BUILD_VERSION 0x0121 + +#define CC33XX_CONF_SP_MAJOR_VERSION 0x00 +#define CC33XX_CONF_SP_MINOR_VERSION 0x00 +#define CC33XX_CONF_SP_REVISION_VERSION 0x0000 +#define CC33XX_CONF_SP_BUILD_VERSION 0x00000007 + +#define CC33XX_CONF_MASK 0x0000ffff +#define CC33X_CONF_SIZE (sizeof(struct cc33xx_conf_file)) + +enum { + CONF_HW_BIT_RATE_1MBPS = BIT(1), + CONF_HW_BIT_RATE_2MBPS = BIT(2), + CONF_HW_BIT_RATE_5_5MBPS = BIT(3), + CONF_HW_BIT_RATE_11MBPS = BIT(4), + CONF_HW_BIT_RATE_6MBPS = BIT(5), + CONF_HW_BIT_RATE_9MBPS = BIT(6), + CONF_HW_BIT_RATE_12MBPS = BIT(7), + CONF_HW_BIT_RATE_18MBPS = BIT(8), + CONF_HW_BIT_RATE_24MBPS = BIT(9), + CONF_HW_BIT_RATE_36MBPS = BIT(10), + CONF_HW_BIT_RATE_48MBPS = BIT(11), + CONF_HW_BIT_RATE_54MBPS = BIT(12), + CONF_HW_BIT_RATE_MCS_0 = BIT(13), + CONF_HW_BIT_RATE_MCS_1 = BIT(14), + CONF_HW_BIT_RATE_MCS_2 = BIT(15), + CONF_HW_BIT_RATE_MCS_3 = BIT(16), + CONF_HW_BIT_RATE_MCS_4 = BIT(17), + CONF_HW_BIT_RATE_MCS_5 = BIT(18), + CONF_HW_BIT_RATE_MCS_6 = BIT(19), + CONF_HW_BIT_RATE_MCS_7 = BIT(20) +}; + +struct cc33xx_clk_cfg { + uint32_t n; + uint32_t m; + uint32_t p; + uint32_t q; + uint8_t swallow; +}; + +#define CONF_TX_MAX_AC_COUNT 4 + +struct conf_tx_ac_category { + /* + * The AC class identifier. + * + * Range: enum conf_tx_ac + */ + uint8_t ac; + + /* + * The contention window minimum size (in slots) for the access + * class. + * + * Range: uint8_t + */ + uint8_t cw_min; + + /* + * The contention window maximum size (in slots) for the access + * class. + * + * Range: uint8_t + */ + uint16_t cw_max; + + /* + * The AIF value (in slots) for the access class. + * + * Range: uint8_t + */ + uint8_t aifsn; + + /* + * The TX Op Limit (in microseconds) for the access class. + * + * Range: uint16_t + */ + uint16_t tx_op_limit; + + /* + * Is the MU EDCA configured + * + * Range: uint8_t + */ + uint8_t is_mu_edca; + + /* + * The AIFSN value for the corresonding access class + * + * Range: uint8_t + */ + uint8_t mu_edca_aifs; + + /* + * The ECWmin and ECWmax value is indicating contention window maximum + * size (in slots) for the access + * + * Range: uint8_t + */ + uint8_t mu_edca_ecw_min_max; + + /* + * The MU EDCA timer (in microseconds) obtaining an EDCA TXOP + * for STA using MU EDCA parameters + * + * Range: uint8_t + */ + uint8_t mu_edca_timer; +} __attribute__((__packed__)); + +struct conf_tx_tid { + uint8_t channel_type; + uint8_t ps_scheme; +} __attribute__((__packed__)); + +struct conf_tx_settings { + /* + * Configuration for access categories for TX rate control. + */ + uint8_t ac_conf_count; + + /*struct conf_tx_ac_category ac_conf[CONF_TX_MAX_AC_COUNT];*/ + struct conf_tx_ac_category ac_conf0; + struct conf_tx_ac_category ac_conf1; + struct conf_tx_ac_category ac_conf2; + struct conf_tx_ac_category ac_conf3; + + /* + * AP-mode - allow this number of TX retries to a station before an + * event is triggered from FW. + * In AP-mode the hlids of unreachable stations are given in the + * "sta_tx_retry_exceeded" member in the event mailbox. + */ + uint8_t max_tx_retries; + + /* + * Configuration for TID parameters. + */ + uint8_t tid_conf_count; + + /* struct conf_tx_tid tid_conf[]; */ + struct conf_tx_tid tid_conf0; + struct conf_tx_tid tid_conf1; + struct conf_tx_tid tid_conf2; + struct conf_tx_tid tid_conf3; + struct conf_tx_tid tid_conf4; + struct conf_tx_tid tid_conf5; + struct conf_tx_tid tid_conf6; + struct conf_tx_tid tid_conf7; + + /* + * Max time in msec the FW may delay frame TX-Complete interrupt. + * + * Range: uint16_t + */ + uint16_t tx_compl_timeout; + + /* + * The rate used for control messages and scanning on the 2.4GHz band + * + * Range: CONF_HW_BIT_RATE_* bit mask + */ + uint32_t basic_rate; + + /* + * The rate used for control messages and scanning on the 5GHz band + * + * Range: CONF_HW_BIT_RATE_* bit mask + */ + uint32_t basic_rate_5; + + /* Time in ms for Tx watchdog timer to expire */ + uint32_t tx_watchdog_timeout; +} __attribute__((__packed__)); + +#define CONF_MAX_BCN_FILT_IE_COUNT 32 + +struct conf_bcn_filt_rule { + /* + * IE number to which to associate a rule. + * + * Range: uint8_t + */ + uint8_t ie; + + /* + * Rule to associate with the specific ie. + * + * Range: CONF_BCN_RULE_PASS_ON_* + */ + uint8_t rule; + + /* + * OUI for the vendor specifie IE (221) + */ + uint8_t oui[3]; + + /* + * Type for the vendor specifie IE (221) + */ + uint8_t type; + + /* + * Version for the vendor specifie IE (221) + */ + uint8_t version[2]; +} __attribute__((__packed__)); + +struct conf_conn_settings { + /* + * Enable or disable the beacon filtering. + * + * Range: CONF_BCN_FILT_MODE_* + */ + uint8_t bcn_filt_mode; + + /* + * Configure Beacon filter pass-thru rules. + */ + uint8_t bcn_filt_ie_count; + + /*struct conf_bcn_filt_rule bcn_filt_ie[CONF_MAX_BCN_FILT_IE_COUNT];*/ + /* struct conf_bcn_filt_rule bcn_filt_ie[32]; */ + struct conf_bcn_filt_rule bcn_filt_ie0; + struct conf_bcn_filt_rule bcn_filt_ie1; + struct conf_bcn_filt_rule bcn_filt_ie2; + struct conf_bcn_filt_rule bcn_filt_ie3; + struct conf_bcn_filt_rule bcn_filt_ie4; + struct conf_bcn_filt_rule bcn_filt_ie5; + struct conf_bcn_filt_rule bcn_filt_ie6; + struct conf_bcn_filt_rule bcn_filt_ie7; + struct conf_bcn_filt_rule bcn_filt_ie8; + struct conf_bcn_filt_rule bcn_filt_ie9; + struct conf_bcn_filt_rule bcn_filt_ie10; + struct conf_bcn_filt_rule bcn_filt_ie11; + struct conf_bcn_filt_rule bcn_filt_ie12; + struct conf_bcn_filt_rule bcn_filt_ie13; + struct conf_bcn_filt_rule bcn_filt_ie14; + struct conf_bcn_filt_rule bcn_filt_ie15; + struct conf_bcn_filt_rule bcn_filt_ie16; + struct conf_bcn_filt_rule bcn_filt_ie17; + struct conf_bcn_filt_rule bcn_filt_ie18; + struct conf_bcn_filt_rule bcn_filt_ie19; + struct conf_bcn_filt_rule bcn_filt_ie20; + struct conf_bcn_filt_rule bcn_filt_ie21; + struct conf_bcn_filt_rule bcn_filt_ie22; + struct conf_bcn_filt_rule bcn_filt_ie23; + struct conf_bcn_filt_rule bcn_filt_ie24; + struct conf_bcn_filt_rule bcn_filt_ie25; + struct conf_bcn_filt_rule bcn_filt_ie26; + struct conf_bcn_filt_rule bcn_filt_ie27; + struct conf_bcn_filt_rule bcn_filt_ie28; + struct conf_bcn_filt_rule bcn_filt_ie29; + struct conf_bcn_filt_rule bcn_filt_ie30; + struct conf_bcn_filt_rule bcn_filt_ie31; + + /* + * The number of consecutive beacons to lose, before the firmware + * becomes out of synch. + * + * Range: uint32_t + */ + uint32_t synch_fail_thold; + + /* + * After out-of-synch, the number of TU's to wait without a further + * received beacon (or probe response) before issuing the BSS_EVENT_LOSE + * event. + * + * Range: uint32_t + */ + uint32_t bss_lose_timeout; + + /* + * Specifies the dynamic PS timeout in ms that will be used + * by the FW when in AUTO_PS mode + */ + uint16_t dynamic_ps_timeout; + + /* + * Maximum listen interval supported by the driver in units of beacons. + * + * Range: uint16_t + */ + uint8_t max_listen_interval; + + /* + * Default sleep authorization for a new STA interface. This determines + * whether we can go to ELP. + */ + uint8_t sta_sleep_auth; + + /* + * Default RX BA Activity filter configuration + */ + uint8_t suspend_rx_ba_activity; +} __attribute__((__packed__)); + +struct conf_scan_settings { + /* + * The minimum time to wait on each channel for active scans + * This value will be used whenever there's a connected interface. + * + * Range: uint32_t tu/1000 + */ + uint32_t min_dwell_time_active; + + /* + * The maximum time to wait on each channel for active scans + * This value will be currently used whenever there's a + * connected interface. It shouldn't exceed 30000 (~30ms) to avoid + * possible interference of voip traffic going on while scanning. + * + * Range: uint32_t tu/1000 + */ + uint32_t max_dwell_time_active; + + /* The minimum time to wait on each channel for active scans + * when it's possible to have longer scan dwell times. + * Currently this is used whenever we're idle on all interfaces. + * Longer dwell times improve detection of networks within a + * single scan. + * + * Range: uint32_t tu/1000 + */ + uint32_t min_dwell_time_active_long; + + /* The maximum time to wait on each channel for active scans + * when it's possible to have longer scan dwell times. + * See min_dwell_time_active_long + * + * Range: uint32_t tu/1000 + */ + uint32_t max_dwell_time_active_long; + + /* time to wait on the channel for passive scans (in TU/1000) */ + uint32_t dwell_time_passive; + + /* time to wait on the channel for DFS scans (in TU/1000) */ + uint32_t dwell_time_dfs; + + /* + * Number of probe requests to transmit on each active scan channel + * + * Range: uint8_t + */ + uint16_t num_probe_reqs; + + /* + * Scan trigger (split scan) timeout. The FW will split the scan + * operation into slices of the given time and allow the FW to schedule + * other tasks in between. + * + * Range: uint32_t Microsecs + */ + uint32_t split_scan_timeout; +} __attribute__((__packed__)); + +struct conf_sched_scan_settings { + /* + * The base time to wait on the channel for active scans (in TU/1000). + * The minimum dwell time is calculated according to this: + * min_dwell_time = base + num_of_probes_to_be_sent * delta_per_probe + * The maximum dwell time is calculated according to this: + * max_dwell_time = min_dwell_time + max_dwell_time_delta + */ + uint32_t base_dwell_time; + + /* The delta between the min dwell time and max dwell time for + * active scans (in TU/1000s). The max dwell time is used by the FW once + * traffic is detected on the channel. + */ + uint32_t max_dwell_time_delta; + + /* Delta added to min dwell time per each probe in 2.4 GHz (TU/1000) */ + uint32_t dwell_time_delta_per_probe; + + /* Delta added to min dwell time per each probe in 5 GHz (TU/1000) */ + uint32_t dwell_time_delta_per_probe_5; + + /* time to wait on the channel for passive scans (in TU/1000) */ + uint32_t dwell_time_passive; + + /* time to wait on the channel for DFS scans (in TU/1000) */ + uint32_t dwell_time_dfs; + + /* number of probe requests to send on each channel in active scans */ + uint8_t num_probe_reqs; + + /* RSSI threshold to be used for filtering */ + int8_t rssi_threshold; + + /* SNR threshold to be used for filtering */ + int8_t snr_threshold; + + /* + * number of short intervals scheduled scan cycles before + * switching to long intervals + */ + uint8_t num_short_intervals; + + /* interval between each long scheduled scan cycle (in ms) */ + uint16_t long_interval; +} __attribute__((__packed__)); + +struct conf_ht_setting { + uint8_t rx_ba_win_size; + + /* DEFAULT / WIDE / SISO20 */ + uint8_t mode; +} __attribute__((__packed__)); + +struct conf_fwlog { + /* Continuous or on-demand */ + uint8_t mode; + + /* + * Number of memory blocks dedicated for the FW logger + * + * Range: 2-16, or 0 to disable the FW logger + */ + uint8_t mem_blocks; + + /* Minimum log level threshold */ + uint8_t severity; + + /* Include/exclude timestamps from the log messages */ + uint8_t timestamp; + + /* See enum cc33xx_fwlogger_output */ + uint8_t output; + + /* Regulates the frequency of log messages */ + uint8_t threshold; +} __attribute__((__packed__)); + +enum cc33xx_ht_mode { + /* Default - use MIMO, fallback to SISO20 */ + HT_MODE_DEFAULT = 0, + + /* Wide - use SISO40 */ + HT_MODE_WIDE = 1, + + /* Use SISO20 */ + HT_MODE_SISO20 = 2, +}; + +struct coex_wifi_group_priorities { + /* + * WLAN activity groups priorities + * + * Range: 0 - 15 + */ + uint8_t coex_enabled; + uint8_t wlan_group_core_active_priority; + uint8_t wlan_group_traffic_priority; + uint8_t wlan_group_scan_priority; + uint8_t wlan_group_twt_traffic_priority; + uint8_t wlan_group_management_sequence_priority; + uint8_t wlan_group_scan_high_priority; + uint8_t wlan_group_broadcast_multicast_priority; + uint8_t wlan_group_beacon_priority; + uint8_t wlan_group_management_sequence_urgent_priority; + uint8_t wlan_group_beacon_urgent_priority; + uint8_t wlan_group_phy_command_priority; +} __attribute__((__packed__)); + +struct coex_ble_group_priorities { + /* + * BLE command groups priorities + * + * Range: 0 - 15 + */ + uint8_t ble_group_test; + uint8_t ble_group_setup; + uint8_t ble_group_connected; + uint8_t ble_group_observer; + uint8_t ble_group_broadcaster; + uint8_t ble_group_initiator; + uint8_t ble_group_urgent_priority; +} __attribute__((__packed__)); + +struct coex_external_soc_priorities { + /* + * External SoC low and high priorities + * + * Range: 0 - 15 + */ + uint8_t low_priority; + uint8_t high_priority; +} __attribute__((__packed__)); + +struct conf_coex_configuration { + /* + * Work without Coex HW + * + * Range: 1 - YES, 0 - NO + */ + uint8_t Disable_coex; + + /* + * Tie breaker configuration + * + * Range: 0 - 3 for each tie breaker. + * + * 0 is lowest and 3 is the highest. + */ + uint8_t tie_breaker_ble; + uint8_t tie_breaker_wifi; + uint8_t tie_breaker_ext_soc; + + /* + * Coex BLE configuration + */ + uint8_t ble_enabled; + uint8_t ble_grant_polarity; + uint8_t ble_pta_signalling_mode; + uint8_t ble_tx_bypass_val; + uint8_t ble_rx_bypass_val; + + /* + * Coex WiFi configuration + */ + uint8_t wifi_enabled; + uint8_t wifi_grant_polarity; + uint8_t wifi_alt_band_input_bypass; + uint8_t wifi_rx_only_input_bypass; + uint8_t wifi_alt_band_input_bypass_val; + uint8_t wifi_rx_only_input_bypass_val; + + /* + * External SoC entity enable + * + * 0 - NO + * 1 - YES + */ + uint8_t is_Ext_soc_enable; + /* + * External SoC PTA signalling mode + * + * 00 - Reserved + * 01 - 1-wire + * 02 - 2-wires + * 11 - 3-wires + */ + uint8_t ext_soc_pta_signalling_mode; + /* + * External SoC request polarity + * + * 0 - Active Low (Default) + * + * 1 - Active High + */ + uint8_t ext_soc_request_polarity; + /* + * External SoC priority polarity + * + * 0 - Active Low (Default) + * + * 1 - Active High + */ + uint8_t ext_soc_priority_polarity; + /* + * External SoC grant polarity + * + * 0 - Active Low + * + * 1 - Active High (Default) + */ + uint8_t ext_soc_grant_polarity; + /* + * External SoC grant renew bypass + * + * 0 - SOC needs to renew grant. + * + * 1 - Bypass SOC grant renew + */ + uint8_t ext_soc_grant_renew_bypass; + /* + * External SoC request signal detection mechanism + * + * 00 - Rise edge detection (L -> H) + * 01 - Fall edge detection (H -> L) + * 10 - Level detection (active high) + * 11 - Level detection (active low) + */ + uint8_t ext_soc_request_signal_detection; + + /* + * External SoC GPIO pins + */ + uint8_t ext_soc_grant_pin; + uint8_t ext_soc_request_pin; + uint8_t ext_soc_priority_pin; + + /* + * Coex grant delays + * + * Range: 0 - 200 usec + */ + uint8_t wifi_to_ble_grant_delay; + uint8_t wifi_to_ext_soc_grant_delay; + uint8_t ble_to_wifi_grant_delay; + uint8_t ble_to_ext_soc_grant_delay; + uint8_t ext_soc_to_wifi_grant_delay; + uint8_t ext_soc_to_ble_grant_delay; + + /* + * Coex grant times + */ + uint16_t wifi_min_grant_time; + uint16_t ble_min_grant_time; + uint16_t ble_max_grant_time; + uint16_t ext_soc_min_grant_time; + uint16_t ext_soc_max_grant_time; + /* + * BLE T2 time + * + * Range: 0 - 50 us + */ + uint8_t ble_t2_time; + /* + * External SoC T2 time + * + * Range: 0 - 50 us + */ + uint8_t ext_soc_t2_time; + + struct coex_wifi_group_priorities wifi_group_priorities; + struct coex_ble_group_priorities ble_group_priorities; + struct coex_external_soc_priorities external_soc_priorities; + +} __attribute__((__packed__)); + +struct conf_iomux_configuration { + /* + * For any iomux pull value: + * 1: Pull up + * 2: Pull down + * 3: Pull disable + * ff: Default value set by HW + * ANY other value is invalid + */ + uint8_t slow_clock_in_pull_val; + uint8_t sdio_clk_pull_val; + uint8_t sdio_cmd_pull_val; + uint8_t sdio_d0_pull_val; + uint8_t sdio_d1_pull_val; + uint8_t sdio_d2_pull_val; + uint8_t sdio_d3_pull_val; + uint8_t host_irq_wl_pull_val; + uint8_t uart1_tx_pull_val; + uint8_t uart1_rx_pull_val; + uint8_t uart1_cts_pull_val; + uint8_t uart1_rts_pull_val; + uint8_t coex_priority_pull_val; + uint8_t coex_req_pull_val; + uint8_t coex_grant_pull_val; + uint8_t host_irq_ble_pull_val; + uint8_t fast_clk_req_pull_val; + uint8_t ant_sel_pull_val; +} __attribute__((__packed__)); + +struct conf_ant_diversity { + /* + * First beacons after antenna switch. + * In this window we asses our satisfaction from the new antenna. + */ + uint8_t fast_switching_window; + /* + * Deltas above this threshold between the curiosity score and + * the average RSSI will lead to antenna switch. + */ + uint8_t rssi_delta_for_switching; + /* + * Used in the first beacons after antenna switch: + * Deltas above this threshold between the average RSSI and + * the curiosity score will make us switch back the antennas. + */ + uint8_t rssi_delta_for_fast_switching; + /* + * Curiosity punishment in beacon timeout after an antenna switch. + */ + uint8_t curiosity_punish; + /* + * Curiosity raise in beacon timeout not after an antenna switch. + */ + uint8_t curiosity_raise; + /* + * Used for the average RSSI punishment in beacon timeout + * not after antenna switch. + */ + uint8_t consecutive_missed_beacons_threshold; + /* + * Used in the curiosity metric. + */ + uint8_t compensation_log; + /* + * Used in the average RSSI metric. + */ + uint8_t log_alpha; + /* + * Curiosity initialization score. + */ + int8_t initial_curiosity; + /* + * MR configuration: should the AP follow the STA antenna or use the default antenna. + */ + uint8_t ap_follows_sta; + /* + * MR configuration: should the BLE follow the STA antenna or use the default antenna. + */ + uint8_t ble_follows_sta; + /* + * The antenna to use when the diversity mechanism is not in charge. + */ + uint8_t default_antenna; + /* + * Rssi low limit + */ + uint8_t rssi_low_limit; + + /* + * Override Coex grant via SW + */ + uint8_t wifi_grant_override; + uint8_t wifi_grant_override_val; + uint8_t ext_soc_grant_override; + uint8_t ext_soc_grant_override_val; + uint8_t ble_grant_override; + uint8_t ble_grant_override_val; + + /* + * Override Coex grant + * + * 0 - External enable + * 1 - BLE only enable + * 2 - WiFi only enable + */ + uint8_t grant_override; + + /* + * SW enable grant (external mask) + * + * 0 - External mask mode + * 1 - BLE only enable + * 2 - WiFi only enable + */ + uint8_t external_mask; + + /* + * Antenna control MUX override + */ + uint8_t antenna_control_override; + + /* + * SW enable register (sw_antenna_control) + */ + uint8_t sw_enable_register; + + /* + * SW index + * Bit 0 - SW index value + * Bit 1 - SW index override + */ + uint8_t sw_index; + + /* + * GPIO antenna index (0-5) + */ + uint8_t gpio_antenna_index_0; + uint8_t gpio_antenna_index_1; + uint8_t gpio_antenna_index_2; + uint8_t gpio_antenna_index_3; + uint8_t gpio_antenna_index_4; + uint8_t gpio_antenna_index_5; + + /* + * Antenna selection bits + */ + uint8_t ant_sel_0; + uint8_t ant_sel_1; + uint8_t ant_sel_2; + uint8_t ant_sel_3; +} __attribute__((__packed__)); + +struct conf_thermal_thresholds { + int16_t high_threshold_24G; + int16_t low_threshold_24G; + int16_t high_threshold_5G; + int16_t low_threshold_5G; + int16_t high_sample_threshold; + uint8_t enable_value; +} __attribute__((__packed__)); + +struct conf_limit105c_params { + uint8_t enable_value; + uint8_t maxMCS; + uint8_t maxOFDM; +} __attribute__((__packed__)); + +struct conf_gpadc_params { + uint8_t overrideEn; + uint8_t disable_measuring; + uint8_t pmcioSlop; + uint16_t pmcioIntercept; + uint8_t rfcioSlop; + uint16_t rfcioIntercept; + uint32_t measurePeriodUsec; + uint8_t dcSlopExponent; +} __attribute__((__packed__)); + +struct cc33xx_core_conf { + uint8_t enable_5ghz; + uint8_t enable_ble; + uint8_t enable_at_test_debug; /* only for at-test chips, debug mode (ignoring disable + * efuses) + */ + uint8_t disable_beamforming_fftp; /* for PG version 2.0 */ + uint32_t BleUartBaudrate; + uint8_t enable_FlowCtrl; + int8_t ble_default_tx_power; + uint8_t listen_interval; + uint8_t wake_up_event; + uint8_t suspend_listen_interval; + uint8_t suspend_wake_up_event; + uint8_t per_channel_power_limit[520]; /* per channel power limitations */ + uint32_t internalSlowclk_wakeupEarlier; + uint32_t internalSlowclk_OpenWindowLonger; + uint32_t externalSlowclk_wakeupEarlier; + uint32_t externalSlowclk_OpenWindowLonger; + uint32_t slowclk_sampledCycles; + uint32_t mx_slowclk_source; + struct conf_coex_configuration coex_configuration; + /* Prevent HW recovery. FW will remain stuck. */ + uint8_t no_recovery; + uint8_t disable_logger; + uint8_t mixed_mode_support; + uint8_t sramLdo_voltageTrimming; + uint32_t xtal_SettlingTime_usec; + uint8_t max_rx_ampdu_len; + uint32_t country_code; + struct conf_ant_diversity ant_diversity; + struct conf_iomux_configuration iomux_configuration; + struct conf_thermal_thresholds thermal_thresholds; + struct conf_limit105c_params limit105c_params; + struct conf_gpadc_params gpadc_params; +} __attribute__((__packed__)); + +struct cc33xx_mac_conf { + uint8_t ps_mode; + uint8_t ps_scheme; + uint8_t he_enable; + uint8_t ApMaxNumStations; + uint8_t fw_defrag; + uint16_t rx_memblks_override; + uint8_t rts_mode; /* 0: dynamic rts, 1: always on, 2: always off */ +} __attribute__((__packed__)); + +struct cc33xx_phy_conf { + uint8_t insertion_loss_2_4GHz[2]; + uint8_t insertion_loss_5GHz[2]; + uint8_t reserved_0[2]; + uint8_t ant_gain_2_4GHz[2]; + uint8_t ant_gain_5GHz[2]; + uint8_t reserved_1[2]; + uint8_t ble_ch_lim_1M[40]; + uint8_t ble_ch_lim_2M[40]; + uint8_t one_time_calibration_only; + uint8_t is_diplexer_present; + uint8_t num_of_antennas; + uint8_t reg_domain; + uint16_t calib_period; + int8_t tx_psat_compensation_2_4GHz; + int8_t tx_psat_compensation_5GHz; + uint8_t Is85cDevice; + uint32_t gpio_data[4]; + int16_t xtalCorrAbove95C; +} __attribute__((__packed__)); + +struct cc33xx_host_conf { + struct conf_tx_settings tx; + struct conf_conn_settings conn; + struct conf_scan_settings scan; + struct conf_sched_scan_settings sched_scan; + struct conf_ht_setting ht; + struct conf_fwlog fwlog; +} __attribute__((__packed__)); + +struct cc33xx_crc_conf { + uint32_t userChecksum; +} __attribute__((__packed__)); + +struct cc33xx_extra_conf { + /* + * Used to distinguish between "product" types, like CC33xxMOD TI, + * or other that will come later. Needed to apply special settings, + * like RF params etc. + */ + uint16_t Product_type; + int8_t tx_psat_compensation_6GHz; /* Missing in psat reserved caused misalignment */ +} __attribute__((__packed__)); + +struct cc33xx_conf_file { + struct cc33xx_conf_header header; + struct cc33xx_phy_conf phy; + struct cc33xx_mac_conf mac; + struct cc33xx_core_conf core; + struct cc33xx_host_conf host_conf; + struct cc33xx_crc_conf crc_conf; + struct cc33xx_extra_conf extra_conf; +} __attribute__((__packed__)); + +#endif /* __CONF_H__ */ diff --git a/soc/ti/simplelink/cc35xxe/conf/default_cc35xx.conf b/soc/ti/simplelink/cc35xxe/conf/default_cc35xx.conf new file mode 100644 index 000000000000..e86ecda91729 --- /dev/null +++ b/soc/ti/simplelink/cc35xxe/conf/default_cc35xx.conf @@ -0,0 +1,435 @@ +phy.insertion_loss_2_4GHz = 0x00, 0x00 +phy.insertion_loss_5GHz = 0x00, 0x00 +phy.reserved_0 = 0x00, 0x00 +phy.ant_gain_2_4GHz = 0x00, 0x00 +phy.ant_gain_5GHz = 0x00, 0x00 +phy.reserved_1 = 0x00, 0x00 +phy.ble_ch_lim_1M = 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff +phy.ble_ch_lim_2M = 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff +phy.one_time_calibration_only = 0x00 +phy.is_diplexer_present = 0x01 +phy.num_of_antennas = 0x01 +phy.reg_domain = 0x00 +phy.calib_period = 0x12c +phy.tx_psat_compensation_2_4GHz = 0x00 +phy.tx_psat_compensation_5GHz = 0x00 +phy.Is85cDevice = 0x00 +phy.gpio_data = 0x00000000, 0x00000000, 0x00000000, 0x00000000 +phy.xtalCorrAbove95C = 0x0000 +mac.ps_mode = 0x00 +mac.ps_scheme = 0x05 +mac.he_enable = 0x01 +mac.ApMaxNumStations = 0x04 +mac.fw_defrag = 0x01 +mac.rx_memblks_override = 0x00 +mac.rts_mode = 0x00 +core.enable_5ghz = 0x01 +core.enable_ble = 0x01 +core.enable_at_test_debug = 0x1 +core.disable_beamforming_fftp = 0x0 +core.BleUartBaudrate = 0x0001c200 +core.enable_FlowCtrl = 0x01 +core.ble_default_tx_power = 0x0A +core.listen_interval = 0x01 +core.wake_up_event = 0x01 +core.suspend_listen_interval = 0x01 +core.suspend_wake_up_event = 0x01 +core.per_channel_power_limit = 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 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0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f +core.internalSlowclk_wakeupEarlier = 0x189C +core.internalSlowclk_OpenWindowLonger = 0x4588 +core.externalSlowclk_wakeupEarlier = 0x1F4 +core.externalSlowclk_OpenWindowLonger = 0x1F4 +core.slowclk_sampledCycles = 0x04 +core.mx_slowclk_source = 0x00 +core.coex_configuration.Disable_coex = 0x00 +core.coex_configuration.tie_breaker_ble = 0x03 +core.coex_configuration.tie_breaker_wifi = 0x02 +core.coex_configuration.tie_breaker_ext_soc = 0x00 +core.coex_configuration.ble_enabled = 0x01 +core.coex_configuration.ble_grant_polarity = 0x01 +core.coex_configuration.ble_pta_signalling_mode = 0x00 +core.coex_configuration.ble_tx_bypass_val = 0x00 +core.coex_configuration.ble_rx_bypass_val = 0x00 +core.coex_configuration.wifi_enabled = 0x01 +core.coex_configuration.wifi_grant_polarity = 0x01 +core.coex_configuration.wifi_alt_band_input_bypass = 0x00 +core.coex_configuration.wifi_rx_only_input_bypass = 0x00 +core.coex_configuration.wifi_alt_band_input_bypass_val = 0x00 +core.coex_configuration.wifi_rx_only_input_bypass_val = 0x00 +core.coex_configuration.is_Ext_soc_enable = 0x00 +core.coex_configuration.ext_soc_pta_signalling_mode = 0x03 +core.coex_configuration.ext_soc_request_polarity = 0x01 +core.coex_configuration.ext_soc_priority_polarity = 0x01 +core.coex_configuration.ext_soc_grant_polarity = 0x01 +core.coex_configuration.ext_soc_grant_renew_bypass = 0x01 +core.coex_configuration.ext_soc_request_signal_detection = 0x02 +core.coex_configuration.ext_soc_grant_pin = 0x00 +core.coex_configuration.ext_soc_request_pin = 0x00 +core.coex_configuration.ext_soc_priority_pin = 0x00 +core.coex_configuration.wifi_to_ble_grant_delay = 0x14 +core.coex_configuration.wifi_to_ext_soc_grant_delay = 0x14 +core.coex_configuration.ble_to_wifi_grant_delay = 0x32 +core.coex_configuration.ble_to_ext_soc_grant_delay = 0x14 +core.coex_configuration.ext_soc_to_wifi_grant_delay = 0x1e +core.coex_configuration.ext_soc_to_ble_grant_delay = 0x23 +core.coex_configuration.wifi_min_grant_time = 0x0023 +core.coex_configuration.ble_min_grant_time = 0x000a +core.coex_configuration.ble_max_grant_time = 0x2710 +core.coex_configuration.ext_soc_min_grant_time = 0x0096 +core.coex_configuration.ext_soc_max_grant_time = 0x3fff +core.coex_configuration.ble_t2_time = 0x05 +core.coex_configuration.ext_soc_t2_time = 0x05 +core.coex_configuration.wifi_group_priorities.coex_enabled = 0x00 +core.coex_configuration.wifi_group_priorities.wlan_group_core_active_priority = 0x01 +core.coex_configuration.wifi_group_priorities.wlan_group_traffic_priority = 0x03 +core.coex_configuration.wifi_group_priorities.wlan_group_scan_priority = 0x05 +core.coex_configuration.wifi_group_priorities.wlan_group_twt_traffic_priority = 0x07 +core.coex_configuration.wifi_group_priorities.wlan_group_management_sequence_priority = 0x07 +core.coex_configuration.wifi_group_priorities.wlan_group_scan_high_priority = 0x09 +core.coex_configuration.wifi_group_priorities.wlan_group_broadcast_multicast_priority = 0x0b +core.coex_configuration.wifi_group_priorities.wlan_group_beacon_priority = 0x0b +core.coex_configuration.wifi_group_priorities.wlan_group_management_sequence_urgent_priority = 0x0b +core.coex_configuration.wifi_group_priorities.wlan_group_beacon_urgent_priority = 0x0d +core.coex_configuration.wifi_group_priorities.wlan_group_phy_command_priority = 0x0f +core.coex_configuration.ble_group_priorities.ble_group_test = 0x01 +core.coex_configuration.ble_group_priorities.ble_group_setup = 0x02 +core.coex_configuration.ble_group_priorities.ble_group_connected = 0x06 +core.coex_configuration.ble_group_priorities.ble_group_observer = 0x08 +core.coex_configuration.ble_group_priorities.ble_group_broadcaster = 0x0a +core.coex_configuration.ble_group_priorities.ble_group_initiator = 0x0c +core.coex_configuration.ble_group_priorities.ble_group_urgent_priority = 0x0d +core.coex_configuration.external_soc_priorities.low_priority = 0x06 +core.coex_configuration.external_soc_priorities.high_priority = 0x0a +core.no_recovery = 0x00 +core.disable_logger = 0x00 +core.mixed_mode_support = 0x01 +core.sramLdo_voltageTrimming = 0x08 +core.xtal_SettlingTime_usec = 0x000006A5 +core.max_rx_ampdu_len = 0x00 +core.country_code = 0x3030 +core.ant_diversity.fast_switching_window = 0x03 +core.ant_diversity.rssi_delta_for_switching = 0x14 +core.ant_diversity.rssi_delta_for_fast_switching = 0x01 +core.ant_diversity.curiosity_punish = 0x03 +core.ant_diversity.curiosity_raise = 0x04 +core.ant_diversity.consecutive_missed_beacons_threshold = 0x03 +core.ant_diversity.compensation_log = 0x03 +core.ant_diversity.log_alpha = 0x05 +core.ant_diversity.initial_curiosity = 0x9c +core.ant_diversity.ap_follows_sta = 0x00 +core.ant_diversity.ble_follows_sta = 0x00 +core.ant_diversity.default_antenna = 0x00 +core.ant_diversity.rssi_low_limit = 0x2f +core.ant_diversity.wifi_grant_override = 0x00 +core.ant_diversity.wifi_grant_override_val = 0x00 +core.ant_diversity.ext_soc_grant_override = 0x00 +core.ant_diversity.ext_soc_grant_override_val = 0x00 +core.ant_diversity.ble_grant_override = 0x00 +core.ant_diversity.ble_grant_override_val = 0x00 +core.ant_diversity.grant_override = 0x00 +core.ant_diversity.external_mask = 0x00 +core.ant_diversity.antenna_control_override = 0x00 +core.ant_diversity.sw_enable_register = 0x00 +core.ant_diversity.sw_index = 0x00 +core.ant_diversity.gpio_antenna_index_0 = 0x00 +core.ant_diversity.gpio_antenna_index_1 = 0x00 +core.ant_diversity.gpio_antenna_index_2 = 0x00 +core.ant_diversity.gpio_antenna_index_3 = 0x00 +core.ant_diversity.gpio_antenna_index_4 = 0x00 +core.ant_diversity.gpio_antenna_index_5 = 0x00 +core.ant_diversity.ant_sel_0 = 0x00 +core.ant_diversity.ant_sel_1 = 0x00 +core.ant_diversity.ant_sel_2 = 0x00 +core.ant_diversity.ant_sel_3 = 0x00 +core.iomux_configuration.slow_clock_in_pull_val = 0xff +core.iomux_configuration.sdio_clk_pull_val = 0xff +core.iomux_configuration.sdio_cmd_pull_val = 0xff +core.iomux_configuration.sdio_d0_pull_val = 0xff +core.iomux_configuration.sdio_d1_pull_val = 0xff +core.iomux_configuration.sdio_d2_pull_val = 0xff +core.iomux_configuration.sdio_d3_pull_val = 0xff +core.iomux_configuration.host_irq_wl_pull_val = 0xff +core.iomux_configuration.uart1_tx_pull_val = 0xff +core.iomux_configuration.uart1_rx_pull_val = 0xff +core.iomux_configuration.uart1_cts_pull_val = 0xff +core.iomux_configuration.uart1_rts_pull_val = 0xff +core.iomux_configuration.coex_priority_pull_val = 0xff +core.iomux_configuration.coex_req_pull_val = 0xff +core.iomux_configuration.coex_grant_pull_val = 0xff +core.iomux_configuration.host_irq_ble_pull_val = 0xff +core.iomux_configuration.fast_clk_req_pull_val = 0xff +core.iomux_configuration.ant_sel_pull_val = 0xff +core.thermal_thresholds.high_threshold_24G = 0x005f +core.thermal_thresholds.low_threshold_24G = 0x005a +core.thermal_thresholds.high_threshold_5G = 0x0050 +core.thermal_thresholds.low_threshold_5G = 0x004B +core.thermal_thresholds.high_sample_threshold = 0x0032 +core.thermal_thresholds.enable_value = 0x01 +core.limit105c_params.enable_value = 0x01 +core.limit105c_params.maxMCS = 0x05 +core.limit105c_params.maxOFDM = 0x30 +core.gpadc_params.overrideEn = 0x01 +core.gpadc_params.disable_measuring = 0x00 +core.gpadc_params.pmcioSlop = 0x38 +core.gpadc_params.pmcioIntercept = 0x0226 +core.gpadc_params.rfcioSlop = 0x38 +core.gpadc_params.rfcioIntercept = 0x0244 +core.gpadc_params.measurePeriodUsec = 0x000f4240 +core.gpadc_params.dcSlopExponent = 0x28 +host_conf.tx.ac_conf_count = 0x04 +host_conf.tx.ac_conf0.ac = 0x00 +host_conf.tx.ac_conf0.cw_min = 0x0f +host_conf.tx.ac_conf0.cw_max = 0x003f +host_conf.tx.ac_conf0.aifsn = 0x03 +host_conf.tx.ac_conf0.tx_op_limit = 0x0000 +host_conf.tx.ac_conf0.is_mu_edca = 0x0000 +host_conf.tx.ac_conf0.mu_edca_aifs = 0x0000 +host_conf.tx.ac_conf0.mu_edca_ecw_min_max = 0x0000 +host_conf.tx.ac_conf0.mu_edca_timer = 0x0000 +host_conf.tx.ac_conf1.ac = 0x01 +host_conf.tx.ac_conf1.cw_min = 0x0f +host_conf.tx.ac_conf1.cw_max = 0x003f +host_conf.tx.ac_conf1.aifsn = 0x07 +host_conf.tx.ac_conf1.tx_op_limit = 0x0000 +host_conf.tx.ac_conf1.is_mu_edca = 0x0000 +host_conf.tx.ac_conf1.mu_edca_aifs = 0x0000 +host_conf.tx.ac_conf1.mu_edca_ecw_min_max = 0x0000 +host_conf.tx.ac_conf1.mu_edca_timer = 0x0000 +host_conf.tx.ac_conf2.ac = 0x02 +host_conf.tx.ac_conf2.cw_min = 0x0f +host_conf.tx.ac_conf2.cw_max = 0x003f +host_conf.tx.ac_conf2.aifsn = 0x01 +host_conf.tx.ac_conf2.tx_op_limit = 0x0bc0 +host_conf.tx.ac_conf2.is_mu_edca = 0x0000 +host_conf.tx.ac_conf2.mu_edca_aifs = 0x0000 +host_conf.tx.ac_conf2.mu_edca_ecw_min_max = 0x0000 +host_conf.tx.ac_conf2.mu_edca_timer = 0x0000 +host_conf.tx.ac_conf3.ac = 0x03 +host_conf.tx.ac_conf3.cw_min = 0x0f +host_conf.tx.ac_conf3.cw_max = 0x003f +host_conf.tx.ac_conf3.aifsn = 0x01 +host_conf.tx.ac_conf3.tx_op_limit = 0x05e0 +host_conf.tx.ac_conf3.is_mu_edca = 0x0000 +host_conf.tx.ac_conf3.mu_edca_aifs = 0x0000 +host_conf.tx.ac_conf3.mu_edca_ecw_min_max = 0x0000 +host_conf.tx.ac_conf3.mu_edca_timer = 0x0000 +host_conf.tx.max_tx_retries = 0x64 +host_conf.tx.tid_conf_count = 0x04 +host_conf.tx.tid_conf0.channel_type = 0x01 +host_conf.tx.tid_conf0.ps_scheme = 0x00 +host_conf.tx.tid_conf1.channel_type = 0x01 +host_conf.tx.tid_conf1.ps_scheme = 0x00 +host_conf.tx.tid_conf2.channel_type = 0x01 +host_conf.tx.tid_conf2.ps_scheme = 0x00 +host_conf.tx.tid_conf3.channel_type = 0x01 +host_conf.tx.tid_conf3.ps_scheme = 0x00 +host_conf.tx.tid_conf4.channel_type = 0x00 +host_conf.tx.tid_conf4.ps_scheme = 0x00 +host_conf.tx.tid_conf5.channel_type = 0x00 +host_conf.tx.tid_conf5.ps_scheme = 0x00 +host_conf.tx.tid_conf6.channel_type = 0x00 +host_conf.tx.tid_conf6.ps_scheme = 0x00 +host_conf.tx.tid_conf7.channel_type = 0x00 +host_conf.tx.tid_conf7.ps_scheme = 0x00 +host_conf.tx.tx_compl_timeout = 0x015e +host_conf.tx.basic_rate = 0x00000001 +host_conf.tx.basic_rate_5 = 0x00000008 +host_conf.tx.tx_watchdog_timeout = 0x00001388 +host_conf.conn.bcn_filt_mode = 0x01 +host_conf.conn.bcn_filt_ie_count = 0x03 +host_conf.conn.bcn_filt_ie0.ie = 0x25 +host_conf.conn.bcn_filt_ie0.rule = 0x02 +host_conf.conn.bcn_filt_ie0.oui = 0x00, 0x00, 0x00 +host_conf.conn.bcn_filt_ie0.type = 0x00 +host_conf.conn.bcn_filt_ie0.version = 0x00, 0x00 +host_conf.conn.bcn_filt_ie1.ie = 0x3d +host_conf.conn.bcn_filt_ie1.rule = 0x01 +host_conf.conn.bcn_filt_ie1.oui = 0x00, 0x00, 0x00 +host_conf.conn.bcn_filt_ie1.type = 0x00 +host_conf.conn.bcn_filt_ie1.version = 0x00, 0x00 +host_conf.conn.bcn_filt_ie2.ie = 0x2a +host_conf.conn.bcn_filt_ie2.rule = 0x01 +host_conf.conn.bcn_filt_ie2.oui = 0x00, 0x00, 0x00 +host_conf.conn.bcn_filt_ie2.type = 0x00 +host_conf.conn.bcn_filt_ie2.version = 0x00, 0x00 +host_conf.conn.bcn_filt_ie3.ie = 0x00 +host_conf.conn.bcn_filt_ie3.rule = 0x00 +host_conf.conn.bcn_filt_ie3.oui = 0x00, 0x00, 0x00 +host_conf.conn.bcn_filt_ie3.type = 0x00 +host_conf.conn.bcn_filt_ie3.version = 0x00, 0x00 +host_conf.conn.bcn_filt_ie4.ie = 0x00 +host_conf.conn.bcn_filt_ie4.rule = 0x00 +host_conf.conn.bcn_filt_ie4.oui = 0x00, 0x00, 0x00 +host_conf.conn.bcn_filt_ie4.type = 0x00 +host_conf.conn.bcn_filt_ie4.version = 0x00, 0x00 +host_conf.conn.bcn_filt_ie5.ie = 0x00 +host_conf.conn.bcn_filt_ie5.rule = 0x00 +host_conf.conn.bcn_filt_ie5.oui = 0x00, 0x00, 0x00 +host_conf.conn.bcn_filt_ie5.type = 0x00 +host_conf.conn.bcn_filt_ie5.version = 0x00, 0x00 +host_conf.conn.bcn_filt_ie6.ie = 0x00 +host_conf.conn.bcn_filt_ie6.rule = 0x00 +host_conf.conn.bcn_filt_ie6.oui = 0x00, 0x00, 0x00 +host_conf.conn.bcn_filt_ie6.type = 0x00 +host_conf.conn.bcn_filt_ie6.version = 0x00, 0x00 +host_conf.conn.bcn_filt_ie7.ie = 0x00 +host_conf.conn.bcn_filt_ie7.rule = 0x00 +host_conf.conn.bcn_filt_ie7.oui = 0x00, 0x00, 0x00 +host_conf.conn.bcn_filt_ie7.type = 0x00 +host_conf.conn.bcn_filt_ie7.version = 0x00, 0x00 +host_conf.conn.bcn_filt_ie8.ie = 0x00 +host_conf.conn.bcn_filt_ie8.rule = 0x00 +host_conf.conn.bcn_filt_ie8.oui = 0x00, 0x00, 0x00 +host_conf.conn.bcn_filt_ie8.type = 0x00 +host_conf.conn.bcn_filt_ie8.version = 0x00, 0x00 +host_conf.conn.bcn_filt_ie9.ie = 0x00 +host_conf.conn.bcn_filt_ie9.rule = 0x00 +host_conf.conn.bcn_filt_ie9.oui = 0x00, 0x00, 0x00 +host_conf.conn.bcn_filt_ie9.type = 0x00 +host_conf.conn.bcn_filt_ie9.version = 0x00, 0x00 +host_conf.conn.bcn_filt_ie10.ie = 0x00 +host_conf.conn.bcn_filt_ie10.rule = 0x00 +host_conf.conn.bcn_filt_ie10.oui = 0x00, 0x00, 0x00 +host_conf.conn.bcn_filt_ie10.type = 0x00 +host_conf.conn.bcn_filt_ie10.version = 0x00, 0x00 +host_conf.conn.bcn_filt_ie11.ie = 0x00 +host_conf.conn.bcn_filt_ie11.rule = 0x00 +host_conf.conn.bcn_filt_ie11.oui = 0x00, 0x00, 0x00 +host_conf.conn.bcn_filt_ie11.type = 0x00 +host_conf.conn.bcn_filt_ie11.version = 0x00, 0x00 +host_conf.conn.bcn_filt_ie12.ie = 0x00 +host_conf.conn.bcn_filt_ie12.rule = 0x00 +host_conf.conn.bcn_filt_ie12.oui = 0x00, 0x00, 0x00 +host_conf.conn.bcn_filt_ie12.type = 0x00 +host_conf.conn.bcn_filt_ie12.version = 0x00, 0x00 +host_conf.conn.bcn_filt_ie13.ie = 0x00 +host_conf.conn.bcn_filt_ie13.rule = 0x00 +host_conf.conn.bcn_filt_ie13.oui = 0x00, 0x00, 0x00 +host_conf.conn.bcn_filt_ie13.type = 0x00 +host_conf.conn.bcn_filt_ie13.version = 0x00, 0x00 +host_conf.conn.bcn_filt_ie14.ie = 0x00 +host_conf.conn.bcn_filt_ie14.rule = 0x00 +host_conf.conn.bcn_filt_ie14.oui = 0x00, 0x00, 0x00 +host_conf.conn.bcn_filt_ie14.type = 0x00 +host_conf.conn.bcn_filt_ie14.version = 0x00, 0x00 +host_conf.conn.bcn_filt_ie15.ie = 0x00 +host_conf.conn.bcn_filt_ie15.rule = 0x00 +host_conf.conn.bcn_filt_ie15.oui = 0x00, 0x00, 0x00 +host_conf.conn.bcn_filt_ie15.type = 0x00 +host_conf.conn.bcn_filt_ie15.version = 0x00, 0x00 +host_conf.conn.bcn_filt_ie16.ie = 0x00 +host_conf.conn.bcn_filt_ie16.rule = 0x00 +host_conf.conn.bcn_filt_ie16.oui = 0x00, 0x00, 0x00 +host_conf.conn.bcn_filt_ie16.type = 0x00 +host_conf.conn.bcn_filt_ie16.version = 0x00, 0x00 +host_conf.conn.bcn_filt_ie17.ie = 0x00 +host_conf.conn.bcn_filt_ie17.rule = 0x00 +host_conf.conn.bcn_filt_ie17.oui = 0x00, 0x00, 0x00 +host_conf.conn.bcn_filt_ie17.type = 0x00 +host_conf.conn.bcn_filt_ie17.version = 0x00, 0x00 +host_conf.conn.bcn_filt_ie18.ie = 0x00 +host_conf.conn.bcn_filt_ie18.rule = 0x00 +host_conf.conn.bcn_filt_ie18.oui = 0x00, 0x00, 0x00 +host_conf.conn.bcn_filt_ie18.type = 0x00 +host_conf.conn.bcn_filt_ie18.version = 0x00, 0x00 +host_conf.conn.bcn_filt_ie19.ie = 0x00 +host_conf.conn.bcn_filt_ie19.rule = 0x00 +host_conf.conn.bcn_filt_ie19.oui = 0x00, 0x00, 0x00 +host_conf.conn.bcn_filt_ie19.type = 0x00 +host_conf.conn.bcn_filt_ie19.version = 0x00, 0x00 +host_conf.conn.bcn_filt_ie20.ie = 0x00 +host_conf.conn.bcn_filt_ie20.rule = 0x00 +host_conf.conn.bcn_filt_ie20.oui = 0x00, 0x00, 0x00 +host_conf.conn.bcn_filt_ie20.type = 0x00 +host_conf.conn.bcn_filt_ie20.version = 0x00, 0x00 +host_conf.conn.bcn_filt_ie21.ie = 0x00 +host_conf.conn.bcn_filt_ie21.rule = 0x00 +host_conf.conn.bcn_filt_ie21.oui = 0x00, 0x00, 0x00 +host_conf.conn.bcn_filt_ie21.type = 0x00 +host_conf.conn.bcn_filt_ie21.version = 0x00, 0x00 +host_conf.conn.bcn_filt_ie22.ie = 0x00 +host_conf.conn.bcn_filt_ie22.rule = 0x00 +host_conf.conn.bcn_filt_ie22.oui = 0x00, 0x00, 0x00 +host_conf.conn.bcn_filt_ie22.type = 0x00 +host_conf.conn.bcn_filt_ie22.version = 0x00, 0x00 +host_conf.conn.bcn_filt_ie23.ie = 0x00 +host_conf.conn.bcn_filt_ie23.rule = 0x00 +host_conf.conn.bcn_filt_ie23.oui = 0x00, 0x00, 0x00 +host_conf.conn.bcn_filt_ie23.type = 0x00 +host_conf.conn.bcn_filt_ie23.version = 0x00, 0x00 +host_conf.conn.bcn_filt_ie24.ie = 0x00 +host_conf.conn.bcn_filt_ie24.rule = 0x00 +host_conf.conn.bcn_filt_ie24.oui = 0x00, 0x00, 0x00 +host_conf.conn.bcn_filt_ie24.type = 0x00 +host_conf.conn.bcn_filt_ie24.version = 0x00, 0x00 +host_conf.conn.bcn_filt_ie25.ie = 0x00 +host_conf.conn.bcn_filt_ie25.rule = 0x00 +host_conf.conn.bcn_filt_ie25.oui = 0x00, 0x00, 0x00 +host_conf.conn.bcn_filt_ie25.type = 0x00 +host_conf.conn.bcn_filt_ie25.version = 0x00, 0x00 +host_conf.conn.bcn_filt_ie26.ie = 0x00 +host_conf.conn.bcn_filt_ie26.rule = 0x00 +host_conf.conn.bcn_filt_ie26.oui = 0x00, 0x00, 0x00 +host_conf.conn.bcn_filt_ie26.type = 0x00 +host_conf.conn.bcn_filt_ie26.version = 0x00, 0x00 +host_conf.conn.bcn_filt_ie27.ie = 0x00 +host_conf.conn.bcn_filt_ie27.rule = 0x00 +host_conf.conn.bcn_filt_ie27.oui = 0x00, 0x00, 0x00 +host_conf.conn.bcn_filt_ie27.type = 0x00 +host_conf.conn.bcn_filt_ie27.version = 0x00, 0x00 +host_conf.conn.bcn_filt_ie28.ie = 0x00 +host_conf.conn.bcn_filt_ie28.rule = 0x00 +host_conf.conn.bcn_filt_ie28.oui = 0x00, 0x00, 0x00 +host_conf.conn.bcn_filt_ie28.type = 0x00 +host_conf.conn.bcn_filt_ie28.version = 0x00, 0x00 +host_conf.conn.bcn_filt_ie29.ie = 0x00 +host_conf.conn.bcn_filt_ie29.rule = 0x00 +host_conf.conn.bcn_filt_ie29.oui = 0x00, 0x00, 0x00 +host_conf.conn.bcn_filt_ie29.type = 0x00 +host_conf.conn.bcn_filt_ie29.version = 0x00, 0x00 +host_conf.conn.bcn_filt_ie30.ie = 0x00 +host_conf.conn.bcn_filt_ie30.rule = 0x00 +host_conf.conn.bcn_filt_ie30.oui = 0x00, 0x00, 0x00 +host_conf.conn.bcn_filt_ie30.type = 0x00 +host_conf.conn.bcn_filt_ie30.version = 0x00, 0x00 +host_conf.conn.bcn_filt_ie31.ie = 0x00 +host_conf.conn.bcn_filt_ie31.rule = 0x00 +host_conf.conn.bcn_filt_ie31.oui = 0x00, 0x00, 0x00 +host_conf.conn.bcn_filt_ie31.type = 0x00 +host_conf.conn.bcn_filt_ie31.version = 0x00, 0x00 +host_conf.conn.synch_fail_thold = 0x0000000c +host_conf.conn.bss_lose_timeout = 0x00000190 +host_conf.conn.dynamic_ps_timeout = 0x05dc +host_conf.conn.max_listen_interval = 0x14 +host_conf.conn.sta_sleep_auth = 0xff +host_conf.conn.suspend_rx_ba_activity = 0x00 +host_conf.scan.min_dwell_time_active_long = 0x000061a8 +host_conf.scan.max_dwell_time_active_long = 0x0000ea60 +host_conf.scan.min_dwell_time_active = 0x00001d4c +host_conf.scan.max_dwell_time_active = 0x00007530 +host_conf.scan.dwell_time_passive = 0x000186a0 +host_conf.scan.dwell_time_dfs = 0x000249f0 +host_conf.scan.num_probe_reqs = 0x0002 +host_conf.scan.split_scan_timeout = 0x0000c350 +host_conf.sched_scan.base_dwell_time = 0x00001d4c +host_conf.sched_scan.max_dwell_time_delta = 0x000057e4 +host_conf.sched_scan.dwell_time_delta_per_probe = 0x000007d0 +host_conf.sched_scan.dwell_time_delta_per_probe_5 = 0x0000015e +host_conf.sched_scan.dwell_time_passive = 0x000186a0 +host_conf.sched_scan.dwell_time_dfs = 0x000249f0 +host_conf.sched_scan.num_probe_reqs = 0x02 +host_conf.sched_scan.rssi_threshold = 0xa6 +host_conf.sched_scan.snr_threshold = 0x00 +host_conf.sched_scan.num_short_intervals = 0x0d +host_conf.sched_scan.long_interval = 0x7530 +host_conf.ht.rx_ba_win_size = 0x20 +host_conf.ht.mode = 0x02 +host_conf.fwlog.mode = 0x00 +host_conf.fwlog.mem_blocks = 0x02 +host_conf.fwlog.severity = 0x00 +host_conf.fwlog.timestamp = 0x00 +host_conf.fwlog.output = 0x01 +host_conf.fwlog.threshold = 0x00 +cc33xx_crc_conf.userChecksum = 0x00000000 +extra_conf.Product_type = 0x0000 +extra_conf.tx_psat_compensation_6GHz = 0x00 diff --git a/soc/ti/simplelink/cc35xxe/conf/dictionary_cc35xx.txt b/soc/ti/simplelink/cc35xxe/conf/dictionary_cc35xx.txt new file mode 100644 index 000000000000..8815ab480f4e --- /dev/null +++ b/soc/ti/simplelink/cc35xxe/conf/dictionary_cc35xx.txt @@ -0,0 +1,64 @@ +# Dictionary for INI version Demo Version + +StaPowerSave mac.ps_mode +PowerSaveScheme mac.ps_scheme +HE_Enable mac.he_enable +ListenInterval core.listen_interval +WakeUpEvent core.wake_up_event +ApMaxNumStations mac.ApMaxNumStations +MaxRxAmpduLen core.max_rx_ampdu_len +EnableBle core.enable_ble +DisableLogger core.disable_logger +MixedModeSupport core.mixed_mode_support +CountryCode core.country_code +DefaultAntenna core.ant_diversity.default_antenna +BleUartBaudrate core.BleUartBaudrate +EnableUartFlowCtrl core.enable_FlowCtrl +BleDefaultTxPower core.ble_default_tx_power +PowerLimitArray core.per_channel_power_limit +InsertionLoss_2_4GHz phy.insertion_loss_2_4GHz +InsertionLoss_5GHz phy.insertion_loss_5GHz +AntGain_2_4GHz phy.ant_gain_2_4GHz +AntGain_5GHz phy.ant_gain_5GHz +BleChLim1M phy.ble_ch_lim_1M +BleChLim2M phy.ble_ch_lim_2M +OneTimeCalibrationOnly phy.one_time_calibration_only +IsDiplexerPresent phy.is_diplexer_present +NumOfAntennas phy.num_of_antennas +RegDomain phy.reg_domain +TxPsatCompensation_2_4GHz phy.tx_psat_compensation_2_4GHz +TxPsatCompensation_5GHz phy.tx_psat_compensation_5GHz +InternalSlowClkDrift_WakeupEarlier core.internalSlowclk_wakeupEarlier +ExtSlowClkDrift_WakeupEarlier core.externalSlowclk_wakeupEarlier +InternalSlowClkDrift_OpenWindowLonger core.internalSlowclk_OpenWindowLonger +ExtSlowClkDrift_OpenWindowLonger core.externalSlowclk_OpenWindowLonger +SlowClk_SampledCycles core.slowclk_sampledCycles +SlowClockSource core.mx_slowclk_source +SLOW_CLOCK_IN_pull_val core.iomux_configuration.slow_clock_in_pull_val +SDIO_CLK_pull_val core.iomux_configuration.sdio_clk_pull_val +SDIO_CMD_pull_val core.iomux_configuration.sdio_cmd_pull_val +SDIO_D0_pull_val core.iomux_configuration.sdio_d0_pull_val +SDIO_D1_pull_val core.iomux_configuration.sdio_d1_pull_val +SDIO_D2_pull_val core.iomux_configuration.sdio_d2_pull_val +SDIO_D3_pull_val core.iomux_configuration.sdio_d3_pull_val +HOST_IRQ_WL_pull_val core.iomux_configuration.host_irq_wl_pull_val +UART1_TX_pull_val core.iomux_configuration.uart1_tx_pull_val +UART1_RX_pull_val core.iomux_configuration.uart1_rx_pull_val +UART1_CTS_pull_val core.iomux_configuration.uart1_cts_pull_val +UART1_RTS_pull_val core.iomux_configuration.uart1_rts_pull_val +COEX_PRIORITY_pull_val core.iomux_configuration.coex_priority_pull_val +COEX_REQ_pull_val core.iomux_configuration.coex_req_pull_val +COEX_GRANT_pull_val core.iomux_configuration.coex_grant_pull_val +HOST_IRQ_BLE_pull_val core.iomux_configuration.host_irq_ble_pull_val +FAST_CLK_REQ_pull_val core.iomux_configuration.fast_clk_req_pull_val +ANT_SEL_pull_val core.iomux_configuration.ant_sel_pull_val +Is_ExtSoC_Connected core.coex_configuration.is_Ext_soc_enable +ExtSoC_grant_polarity core.coex_configuration.ext_soc_grant_polarity +ExtSoC_priority_polarity core.coex_configuration.ext_soc_priority_polarity +ExtSoC_request_polarity core.coex_configuration.ext_soc_request_polarity +ExtSoC_min_grant_time core.coex_configuration.ext_soc_min_grant_time +ExtSoC_max_grant_time core.coex_configuration.ext_soc_max_grant_time +ExtSoC_t2_time core.coex_configuration.ext_soc_t2_time +ExtSoC_to_wifi_grant_delay core.coex_configuration.ext_soc_to_wifi_grant_delay +ExtSoC_to_ble_grant_delay core.coex_configuration.ext_soc_to_ble_grant_delay +XTAL_SettlingTime core.xtal_SettlingTime_usec diff --git a/soc/ti/simplelink/cc35xxe/toolbox.cmake b/soc/ti/simplelink/cc35xxe/toolbox.cmake index b33382826182..f9fde6183c9a 100644 --- a/soc/ti/simplelink/cc35xxe/toolbox.cmake +++ b/soc/ti/simplelink/cc35xxe/toolbox.cmake @@ -113,9 +113,27 @@ function(zephyr_simplelink_tasks) --private_key ${privkey} --public_key ${pubkey} --dir_out_path ${outdir}) + set(conf_default_dir "${SOC_DIR}/conf") + + string(CONFIGURE "${CONFIG_CC35XXE_CONF_INI_FILE}" conf_ini) + if("${conf_ini}" STREQUAL "") + set(conf_ini "${conf_default_dir}/cc35xx-conf.ini") + endif() + + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND + simplelink-wifi-toolbox ini-composer generate bin_from_files + --device_family CC35X1E + --dict "${conf_default_dir}/dictionary_cc35xx.txt" + --default_conf "${conf_default_dir}/default_cc35xx.conf" + --header "${conf_default_dir}/conf_cc35xx.h" + --ini "${conf_ini}" + --conf_key "${conf_default_dir}/conf.key" + --output "${outdir}/cc35xx-conf.bin") + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND simplelink-wifi-toolbox flash-images-builder build vendor_image --vendor_out_file ${output}.elf + --conf_bin_file ${outdir}/cc35xx-conf.bin --dir_out_path ${outdir}) set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND From 0922caed70a3d71c3c81167cb98c3e781c807d17 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=81yszczek?= Date: Wed, 3 Sep 2025 13:07:37 +0200 Subject: [PATCH 010/100] UPSTREAM-PEND: drivers: flash: cc35xxe: add flash driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add flash driver for CC35xxE Signed-off-by: Michał Łyszczek --- boards/ti/lp_em_cc35x1/lp_em_cc35x1_defconfig | 4 + drivers/flash/CMakeLists.txt | 1 + drivers/flash/Kconfig | 1 + drivers/flash/Kconfig.cc35xx | 13 ++ drivers/flash/soc_flash_cc35xx.c | 196 ++++++++++++++++++ dts/arm/ti/cc35xxe.dtsi | 27 +++ dts/bindings/mtd/ti,cc35xx-nv-flash.yaml | 9 + soc/ti/simplelink/cc35xxe/CMakeLists.txt | 1 + soc/ti/simplelink/cc35xxe/ramfunc_linker.ld | 1 + 9 files changed, 253 insertions(+) create mode 100644 drivers/flash/Kconfig.cc35xx create mode 100644 drivers/flash/soc_flash_cc35xx.c create mode 100644 dts/bindings/mtd/ti,cc35xx-nv-flash.yaml create mode 100644 soc/ti/simplelink/cc35xxe/ramfunc_linker.ld diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_defconfig b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_defconfig index 920a82db37d2..6ee853bfab6d 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_defconfig +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_defconfig @@ -12,3 +12,7 @@ CONFIG_SHELL=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN=y CONFIG_SHELL_BACKEND_SERIAL_API_INTERRUPT_DRIVEN=y + +CONFIG_FLASH=y +CONFIG_SOC_FLASH_CC35XX=y +CONFIG_FLASH_SHELL=y diff --git a/drivers/flash/CMakeLists.txt b/drivers/flash/CMakeLists.txt index 22a547ee9e9e..fb1e6c5e5fff 100644 --- a/drivers/flash/CMakeLists.txt +++ b/drivers/flash/CMakeLists.txt @@ -59,6 +59,7 @@ zephyr_library_sources_ifdef(CONFIG_NORDIC_QSPI_NOR nrf_qspi_nor.c) zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_BFLB flash_bflb.c) zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_CC13XX_CC26XX soc_flash_cc13xx_cc26xx.c) zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_CC23X0 soc_flash_cc23x0.c) +zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_CC35XX soc_flash_cc35xx.c) zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_ESP32 flash_esp32.c) zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_GECKO flash_gecko.c) zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_ITE_IT51XXX_M1K flash_ite_it51xxx_m1k.c) diff --git a/drivers/flash/Kconfig b/drivers/flash/Kconfig index 422de790fdcb..c39293ba421b 100644 --- a/drivers/flash/Kconfig +++ b/drivers/flash/Kconfig @@ -176,6 +176,7 @@ source "drivers/flash/Kconfig.cadence_nand" source "drivers/flash/Kconfig.cadence_qspi_nor" source "drivers/flash/Kconfig.cc13xx_cc26xx" source "drivers/flash/Kconfig.cc23x0" +source "drivers/flash/Kconfig.cc35xx" source "drivers/flash/Kconfig.esp32" source "drivers/flash/Kconfig.gd32" source "drivers/flash/Kconfig.gecko" diff --git a/drivers/flash/Kconfig.cc35xx b/drivers/flash/Kconfig.cc35xx new file mode 100644 index 000000000000..c840a38f9864 --- /dev/null +++ b/drivers/flash/Kconfig.cc35xx @@ -0,0 +1,13 @@ +# Copyright (c) 2025 Conclusive Engineering Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FLASH_CC35XX + bool "TI SimpleLink CC35xx flash driver" + default y + depends on DT_HAS_TI_CC35XX_NV_FLASH_ENABLED + select FLASH_HAS_PAGE_LAYOUT + select FLASH_HAS_DRIVER_ENABLED + select FLASH_HAS_EXPLICIT_ERASE + select MPU_ALLOW_FLASH_WRITE if ARM_MPU + help + Enables TI SimpleLink CC35xx flash driver. diff --git a/drivers/flash/soc_flash_cc35xx.c b/drivers/flash/soc_flash_cc35xx.c new file mode 100644 index 000000000000..3c8d7da7e703 --- /dev/null +++ b/drivers/flash/soc_flash_cc35xx.c @@ -0,0 +1,196 @@ +/* + * Copyright (c) 2025 Conclusive Engineering Sp. z o.o. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#define DT_DRV_COMPAT ti_cc35xx_nv_flash +#define CC35XX_ERASE_OPCODE 0x20 +#define CC35XX_ERASE_TIMEOUT 200 + +struct flash_cc35xx_config { + mem_addr_t base; + mem_addr_t phys_addr; + size_t size; + size_t erase_size; + const struct flash_pages_layout *layout; + const struct flash_parameters *parameters; +}; +static int flash_cc35xx_initialized; +static struct k_mutex flash_cc35xx_mutex; + +static mem_addr_t flash_cc35xx_offset_to_phys_addr(const struct device *dev, off_t offset) +{ + const struct flash_cc35xx_config *config = dev->config; + + return config->phys_addr + offset; +} + +static void *flash_cc35xx_offset_to_logic_addr(const struct device *dev, off_t offset) +{ + const struct flash_cc35xx_config *config = dev->config; + uintptr_t addr = config->base + offset; + + return (void *)addr; +} + +static bool flash_cc35xx_is_range_valid(const struct device *dev, off_t offset, size_t size) +{ + const struct flash_cc35xx_config *config = dev->config; + + return ((size_t)offset < config->size) && (size < config->size - offset); +} + +static int flash_cc35xx_init(const struct device *dev) +{ + ARG_UNUSED(dev); + + if (flash_cc35xx_initialized == 0) { + k_mutex_init(&flash_cc35xx_mutex); + flash_cc35xx_initialized = 1; + } + + return 0; +} + +__ramfunc static int flash_cc35xx_erase(const struct device *dev, off_t offset, size_t size) +{ + const struct flash_cc35xx_config *config = dev->config; + size_t erase_size = config->erase_size; + mem_addr_t addr = flash_cc35xx_offset_to_phys_addr(dev, offset); + int ret; + unsigned int key; + + if (offset % erase_size) { + return -EINVAL; + } + if (size % erase_size) { + return -EINVAL; + } + if (!flash_cc35xx_is_range_valid(dev, offset, size)) { + return -EINVAL; + } + + k_mutex_lock(&flash_cc35xx_mutex, K_FOREVER); + for (; size; size -= erase_size, addr += erase_size) { + key = irq_lock(); + ret = FlashSectorErase(addr, CC35XX_ERASE_OPCODE, CC35XX_ERASE_TIMEOUT); + /* BUG: FlashSectorErase() is supposed to wait for flash busy flag to + * go off after erasing sector. But it appears there is a bug somewhere + * with the logic, and if we unlock interrupts right after we exit that + * function, chip - most often than not - will go into lockup state + * due to XIP operation on busy flash. Adding busy-loop that is long + * enough works around that problem. Value has been chosen arbitrarily + * based on tests + */ + CPUDelay(2097152l); + irq_unlock(key); + if (ret) { + break; + } + } + k_mutex_unlock(&flash_cc35xx_mutex); + + return ret ? -ETIMEDOUT : 0; +} + +static int flash_cc35xx_write(const struct device *dev, off_t offset, const void *buf, size_t size) +{ + const struct flash_cc35xx_config *config = dev->config; + uint32_t *addr = flash_cc35xx_offset_to_logic_addr(dev, offset); + const uint32_t *buffer = buf; + + if (size % config->parameters->write_block_size) { + return -EINVAL; + } + if ((uintptr_t)buffer % config->parameters->write_block_size) { + return -EINVAL; + } + if (!flash_cc35xx_is_range_valid(dev, offset, size)) { + return -EINVAL; + } + + size /= sizeof(uint32_t); + k_mutex_lock(&flash_cc35xx_mutex, K_FOREVER); + for (size_t i = 0; i < size; i++) { + addr[i] = buffer[i]; + } + k_mutex_unlock(&flash_cc35xx_mutex); + + return 0; +} + +static int flash_cc35xx_read(const struct device *dev, off_t offset, void *buf, size_t size) +{ + void *addr = flash_cc35xx_offset_to_logic_addr(dev, offset); + + if (!flash_cc35xx_is_range_valid(dev, offset, size)) { + return -EINVAL; + } + + k_mutex_lock(&flash_cc35xx_mutex, K_FOREVER); + memcpy(buf, addr, size); + k_mutex_unlock(&flash_cc35xx_mutex); + + return 0; +} + +static const struct flash_parameters *flash_cc35xx_get_parameters(const struct device *dev) +{ + const struct flash_cc35xx_config *config = dev->config; + + return config->parameters; +} + +#if defined(CONFIG_FLASH_PAGE_LAYOUT) +static void flash_cc35xx_layout(const struct device *dev, const struct flash_pages_layout **layout, + size_t *layout_size) +{ + const struct flash_cc35xx_config *config = dev->config; + + *layout = config->layout; + *layout_size = 1; +} +#endif /* CONFIG_FLASH_PAGE_LAYOUT */ + +static const struct flash_driver_api flash_cc35xx_api = { + .erase = flash_cc35xx_erase, + .write = flash_cc35xx_write, + .read = flash_cc35xx_read, + .get_parameters = flash_cc35xx_get_parameters, +#if defined(CONFIG_FLASH_PAGE_LAYOUT) + .page_layout = flash_cc35xx_layout, +#endif +}; + +#define FLASH_CC35XX_DEVICE(n) \ + static const struct flash_pages_layout flash_cc35xx_layout_##n = { \ + .pages_size = DT_INST_PROP(n, write_block_size), \ + .pages_count = DT_INST_REG_SIZE_BY_IDX(n, 0) / DT_INST_PROP(n, write_block_size), \ + }; \ + static const struct flash_parameters flash_cc35xx_parameters_##n = { \ + .write_block_size = DT_INST_PROP(n, write_block_size), \ + .erase_value = 0xff, \ + }; \ + static const struct flash_cc35xx_config flash_cc35xx_config_##n = { \ + .base = DT_INST_REG_ADDR_BY_IDX(n, 0), \ + .size = DT_INST_REG_SIZE_BY_IDX(n, 0), \ + .phys_addr = DT_INST_REG_ADDR_BY_IDX(n, 1), \ + .erase_size = DT_INST_PROP(n, erase_block_size), \ + .layout = &flash_cc35xx_layout_##n, \ + .parameters = &flash_cc35xx_parameters_##n, \ + }; \ + DEVICE_DT_INST_DEFINE(n, flash_cc35xx_init, NULL, NULL, &flash_cc35xx_config_##n, \ + POST_KERNEL, CONFIG_FLASH_INIT_PRIORITY, &flash_cc35xx_api); + +DT_INST_FOREACH_STATUS_OKAY(FLASH_CC35XX_DEVICE) diff --git a/dts/arm/ti/cc35xxe.dtsi b/dts/arm/ti/cc35xxe.dtsi index d5905c643906..74f59fb82afd 100644 --- a/dts/arm/ti/cc35xxe.dtsi +++ b/dts/arm/ti/cc35xxe.dtsi @@ -219,6 +219,33 @@ erase-block-size = ; write-block-size = <4>; }; + + flash0: flash@a0000000 { + compatible = "ti,cc35xx-nv-flash"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xa0000000 0x00033000>, <0x0 0x00033000>; + erase-block-size = ; + write-block-size = <4>; + }; + + flash1: flash@10000000 { + compatible = "ti,cc35xx-nv-flash"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x10000000 0x001e7000>, <0x00033000 0x001e7000>; + erase-block-size = ; + write-block-size = <4>; + }; + + flash2: flash@a0050000 { + compatible = "ti,cc35xx-nv-flash"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xa0050000 0x001ea000>, <0x0021a000 0x001ea000>; + erase-block-size = ; + write-block-size = <4>; + }; }; }; diff --git a/dts/bindings/mtd/ti,cc35xx-nv-flash.yaml b/dts/bindings/mtd/ti,cc35xx-nv-flash.yaml new file mode 100644 index 000000000000..22b397ac1a79 --- /dev/null +++ b/dts/bindings/mtd/ti,cc35xx-nv-flash.yaml @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Conclusive Engineering Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +description: | + cc35xx flash memory. + +include: soc-nv-flash.yaml + +compatible: ti,cc35xx-nv-flash diff --git a/soc/ti/simplelink/cc35xxe/CMakeLists.txt b/soc/ti/simplelink/cc35xxe/CMakeLists.txt index 5a018df98010..1092ad9431ee 100644 --- a/soc/ti/simplelink/cc35xxe/CMakeLists.txt +++ b/soc/ti/simplelink/cc35xxe/CMakeLists.txt @@ -8,3 +8,4 @@ zephyr_include_directories(.) set_target_properties(zephyr_property_target PROPERTIES SIGNING_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/toolbox.cmake) set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") +zephyr_linker_sources(RAMFUNC_SECTION SORT_KEY 0 ramfunc_linker.ld) diff --git a/soc/ti/simplelink/cc35xxe/ramfunc_linker.ld b/soc/ti/simplelink/cc35xxe/ramfunc_linker.ld new file mode 100644 index 000000000000..2d3d515893d7 --- /dev/null +++ b/soc/ti/simplelink/cc35xxe/ramfunc_linker.ld @@ -0,0 +1 @@ +KEEP(*(.TI.ramfunc)) From 2d6ee3db59d4f6b34698c692818bf00bc9867dcf Mon Sep 17 00:00:00 2001 From: Artur Rojek Date: Mon, 9 Feb 2026 19:07:17 +0100 Subject: [PATCH 011/100] UPSTREAM-PEND: flash: cc35xxe: Update FlashSectorErase usage. Update FlashSectorErase() usage after function signature change in SDK 9.21. Signed-off-by: Artur Rojek --- drivers/flash/soc_flash_cc35xx.c | 33 ++++++++++++++++++-------------- 1 file changed, 19 insertions(+), 14 deletions(-) diff --git a/drivers/flash/soc_flash_cc35xx.c b/drivers/flash/soc_flash_cc35xx.c index 3c8d7da7e703..143e50278de6 100644 --- a/drivers/flash/soc_flash_cc35xx.c +++ b/drivers/flash/soc_flash_cc35xx.c @@ -83,18 +83,23 @@ __ramfunc static int flash_cc35xx_erase(const struct device *dev, off_t offset, k_mutex_lock(&flash_cc35xx_mutex, K_FOREVER); for (; size; size -= erase_size, addr += erase_size) { - key = irq_lock(); - ret = FlashSectorErase(addr, CC35XX_ERASE_OPCODE, CC35XX_ERASE_TIMEOUT); - /* BUG: FlashSectorErase() is supposed to wait for flash busy flag to - * go off after erasing sector. But it appears there is a bug somewhere - * with the logic, and if we unlock interrupts right after we exit that - * function, chip - most often than not - will go into lockup state - * due to XIP operation on busy flash. Adding busy-loop that is long - * enough works around that problem. Value has been chosen arbitrarily - * based on tests - */ - CPUDelay(2097152l); - irq_unlock(key); + for (int tries = 3; tries; tries--) { + key = irq_lock(); + ret = FlashSectorErase(addr, 0); + /* BUG: FlashSectorErase() is supposed to wait for flash busy flag to + * go off after erasing sector. But it appears there is a bug somewhere + * with the logic, and if we unlock interrupts right after we exit that + * function, chip - most often than not - will go into lockup state + * due to XIP operation on busy flash. Adding busy-loop that is long + * enough works around that problem. Value has been chosen arbitrarily + * based on tests + */ + CPUDelay(2097152l); + irq_unlock(key); + if (ret == 0) { + break; + } + } if (ret) { break; } @@ -175,8 +180,8 @@ static const struct flash_driver_api flash_cc35xx_api = { #define FLASH_CC35XX_DEVICE(n) \ static const struct flash_pages_layout flash_cc35xx_layout_##n = { \ - .pages_size = DT_INST_PROP(n, write_block_size), \ - .pages_count = DT_INST_REG_SIZE_BY_IDX(n, 0) / DT_INST_PROP(n, write_block_size), \ + .pages_size = DT_INST_PROP(n, erase_block_size), \ + .pages_count = DT_INST_REG_SIZE_BY_IDX(n, 0) / DT_INST_PROP(n, erase_block_size), \ }; \ static const struct flash_parameters flash_cc35xx_parameters_##n = { \ .write_block_size = DT_INST_PROP(n, write_block_size), \ From 3ffb27ebe753de99ac755f7bbb2cb440545bc5ca Mon Sep 17 00:00:00 2001 From: Artur Rojek Date: Thu, 5 Mar 2026 18:02:35 +0100 Subject: [PATCH 012/100] UPSTREAM-PEND: flash: cc35xxe: Fix flash erase on PG2 boards Flash erase on PG2 boards has been broken due to two independent issues: 1) XMEM operation requires the XMEMWFF3_hwAttrs.flashType global variable to be filled with flash chip specific information. 2) The CPUDelay() workaround in FlashSectorErase() for PG1 XIP access is actually triggering XIP access traps on PG2. Fix the above in the following way: 1) Provide flash parameters for IS25WJ032F flash chip. 2) Remove the CPUDelay(). Signed-off-by: Artur Rojek --- drivers/flash/soc_flash_cc35xx.c | 64 +++++++++++++++++++++++++++----- 1 file changed, 54 insertions(+), 10 deletions(-) diff --git a/drivers/flash/soc_flash_cc35xx.c b/drivers/flash/soc_flash_cc35xx.c index 143e50278de6..6de88074e00e 100644 --- a/drivers/flash/soc_flash_cc35xx.c +++ b/drivers/flash/soc_flash_cc35xx.c @@ -12,10 +12,10 @@ #include #include +#include #include #define DT_DRV_COMPAT ti_cc35xx_nv_flash -#define CC35XX_ERASE_OPCODE 0x20 #define CC35XX_ERASE_TIMEOUT 200 struct flash_cc35xx_config { @@ -51,6 +51,57 @@ static bool flash_cc35xx_is_range_valid(const struct device *dev, off_t offset, return ((size_t)offset < config->size) && (size < config->size - offset); } +extern XMEMWFF3_HWAttrs XMEMWFF3_hwAttrs; +static const FlashType flash_cc35xx_is25wj032f = { + /* Operations */ + .writeStigCfg.preStigCfg = 1, + .writeStigCfg.postStigCfg = 0, + .readStigCfg.preStigCfg = 0, + .readStigCfg.postStigCfg = 0, + .eraseStigCfg.preStigCfg = 1, + .eraseStigCfg.postStigCfg = 0, + .eraseStigCfg.StigCfg = 1, + + /* Enter STIG mode */ + .enterStigCfg[0].address = OSPI_REGS_BASE + OSPI_O_CONFIG, + .enterStigCfg[0].data = 0x82080089, + .enterStigCfg[1].address = OSPI_REGS_BASE + OSPI_O_DEV_INSTR_RD_CONFIG, + .enterStigCfg[1].data = 0x0402220b, + .enterStigCfg[2].address = OSPI_REGS_BASE + OSPI_O_DEV_INSTR_WR_CONFIG, + .enterStigCfg[2].data = 0x00022002, + + /* EXIT STIG mode */ + .exitStigCfg[0].address = OSPI_REGS_BASE + OSPI_O_CONFIG, + .exitStigCfg[0].data = 0x82080089, + .exitStigCfg[1].address = OSPI_REGS_BASE + OSPI_O_DEV_INSTR_RD_CONFIG, + .exitStigCfg[1].data = 0x0402220b, + .exitStigCfg[2].address = OSPI_REGS_BASE + OSPI_O_DEV_INSTR_WR_CONFIG, + .exitStigCfg[2].data = 0x00022002, + + /* Pre STIG configuration */ + .writeStigCfg.preStigOperation[0].address = OSPI_REGS_BASE + OSPI_O_FLASH_CMD_CTRL, + .writeStigCfg.preStigOperation[0].data = 0x06000001, + .eraseStigCfg.preStigOperation[0].address = OSPI_REGS_BASE + OSPI_O_FLASH_CMD_CTRL, + .eraseStigCfg.preStigOperation[0].data = 0x06000001, + + /* Execute STIG operation */ + .readStigCfg.stigOperation[0].address = OSPI_REGS_BASE + OSPI_O_FLASH_CMD_CTRL, + .readStigCfg.stigOperation[0].data = 0x0bba0200, + .writeStigCfg.stigOperation[0].address = OSPI_REGS_BASE + OSPI_O_FLASH_CMD_CTRL, + .writeStigCfg.stigOperation[0].data = 0x020ab000, + .eraseStigCfg.stigOperation[0].address = OSPI_REGS_BASE + OSPI_O_FLASH_CMD_CTRL, + .eraseStigCfg.stigOperation[0].data = 0x200a0000, + + /* Polling operation */ + .pollingCfg.command = 0x05900000, + .pollingCfg.timeOut = CC35XX_ERASE_TIMEOUT, + .pollingCfg.NumOfIteration = 4, + + /* General */ + .sectorSize = 0x1000, + .verifyBufSize = 256, +}; + static int flash_cc35xx_init(const struct device *dev) { ARG_UNUSED(dev); @@ -60,6 +111,8 @@ static int flash_cc35xx_init(const struct device *dev) flash_cc35xx_initialized = 1; } + XMEMWFF3_hwAttrs.flashType = flash_cc35xx_is25wj032f; + return 0; } @@ -86,15 +139,6 @@ __ramfunc static int flash_cc35xx_erase(const struct device *dev, off_t offset, for (int tries = 3; tries; tries--) { key = irq_lock(); ret = FlashSectorErase(addr, 0); - /* BUG: FlashSectorErase() is supposed to wait for flash busy flag to - * go off after erasing sector. But it appears there is a bug somewhere - * with the logic, and if we unlock interrupts right after we exit that - * function, chip - most often than not - will go into lockup state - * due to XIP operation on busy flash. Adding busy-loop that is long - * enough works around that problem. Value has been chosen arbitrarily - * based on tests - */ - CPUDelay(2097152l); irq_unlock(key); if (ret == 0) { break; From f2bcf7b6ab8f2cdc6cfe840a29b823091b0b0424 Mon Sep 17 00:00:00 2001 From: Jakub Jarosinski Date: Thu, 26 Mar 2026 21:21:56 +0100 Subject: [PATCH 013/100] UPSTREAM-PEND: boards: cc35x1: add flash partitions and NVS storage Add vendor_image_partition on flash0, WiFi FW slot partitions on flash1, WiFi NVS and storage partitions on flash2. Fix storage partition size to fit flash2 (140KB). Signed-off-by: Jakub Jarosinski --- boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts | 55 +++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts b/boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts index 7c97ad9d1fc9..2e8bb4d1ca8c 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts @@ -53,6 +53,61 @@ status = "okay"; }; +&flash0 { + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + vendor_image_partition: partition@0 { + label = "vendor-image"; + reg = <0x0 0x2fb000>; + }; + }; +}; + +&flash1 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + wifi_fw_slot1_partition: partition@68000 { + label = "wifi-fw-1"; + reg = <0x68000 0x72000>; + }; + + wifi_fw_slot2_partition: partition@da000 { + label = "wifi-fw-2"; + reg = <0xda000 0x2b000>; + }; + }; +}; + +&flash2 { + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* WiFi/BLE NVS: profiles, BLE security, connection policy */ + /* 8 sectors = 32 KB with wear-leveling */ + wifi_nvs_partition: partition@0 { + label = "wifi-nvs"; + reg = <0x0 0x8000>; + }; + + storage_partition: partition@8000 { + label = "storage"; + reg = <0x8000 0x23000>; + }; + }; +}; + &uart0 { status = "okay"; pinctrl-0 = <&uart0_default>; From 06ab4c7c4b04c0940bbb990f9af274ecff29d438 Mon Sep 17 00:00:00 2001 From: Jakub Jarosinski Date: Thu, 26 Mar 2026 21:22:18 +0100 Subject: [PATCH 014/100] UPSTREAM-PEND: flash: cc35xx: fix write rejecting unaligned source buffers Remove source buffer alignment check and use memcpy instead of word-by-word copy. NVS passes unaligned buffers which were incorrectly rejected with EINVAL. Signed-off-by: Jakub Jarosinski --- drivers/flash/soc_flash_cc35xx.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/drivers/flash/soc_flash_cc35xx.c b/drivers/flash/soc_flash_cc35xx.c index 6de88074e00e..82accf6773c1 100644 --- a/drivers/flash/soc_flash_cc35xx.c +++ b/drivers/flash/soc_flash_cc35xx.c @@ -156,24 +156,17 @@ __ramfunc static int flash_cc35xx_erase(const struct device *dev, off_t offset, static int flash_cc35xx_write(const struct device *dev, off_t offset, const void *buf, size_t size) { const struct flash_cc35xx_config *config = dev->config; - uint32_t *addr = flash_cc35xx_offset_to_logic_addr(dev, offset); - const uint32_t *buffer = buf; + void *addr = flash_cc35xx_offset_to_logic_addr(dev, offset); if (size % config->parameters->write_block_size) { return -EINVAL; } - if ((uintptr_t)buffer % config->parameters->write_block_size) { - return -EINVAL; - } if (!flash_cc35xx_is_range_valid(dev, offset, size)) { return -EINVAL; } - size /= sizeof(uint32_t); k_mutex_lock(&flash_cc35xx_mutex, K_FOREVER); - for (size_t i = 0; i < size; i++) { - addr[i] = buffer[i]; - } + memcpy(addr, buf, size); k_mutex_unlock(&flash_cc35xx_mutex); return 0; From 2fd6daf0e25793bd2d07ea573cc2ad6485bfb019 Mon Sep 17 00:00:00 2001 From: Jakub Jarosinski Date: Wed, 8 Apr 2026 12:01:34 +0200 Subject: [PATCH 015/100] UPSTREAM-PEND: boards: cc35x1: enable flash1 in board DTS Enable the flash1 node so its partitions are usable by samples. Signed-off-by: Jakub Jarosinski --- boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts b/boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts index 2e8bb4d1ca8c..3eda5388e23f 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts @@ -69,6 +69,8 @@ }; &flash1 { + status = "okay"; + partitions { compatible = "fixed-partitions"; #address-cells = <1>; From 1f8b895a55ae7e205857ec815063b4475c8ba62a Mon Sep 17 00:00:00 2001 From: Jacek Ozimek Date: Tue, 10 Jun 2025 10:12:45 +0200 Subject: [PATCH 016/100] UPSTREAM-PEND: drivers: gpio: cc35xxe: Initial commit for GPIO MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for CC35xxE GPIO Signed-off-by: Jacek Ozimek Signed-off-by: Michał Łyszczek --- boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts | 60 ++++ boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml | 1 + boards/ti/lp_em_cc35x1/lp_em_cc35x1_defconfig | 2 + drivers/gpio/CMakeLists.txt | 1 + drivers/gpio/Kconfig | 1 + drivers/gpio/Kconfig.cc35xx | 11 + drivers/gpio/gpio_cc35xx.c | 321 +++++++++++++++++ dts/arm/ti/cc35xxe.dtsi | 328 ++++++++++++++++++ .../gpio/ti,cc35xx-gpio-port-bank.yaml | 14 + .../gpio/ti,cc35xx-gpio-port-pin.yaml | 23 ++ 10 files changed, 762 insertions(+) create mode 100644 drivers/gpio/Kconfig.cc35xx create mode 100644 drivers/gpio/gpio_cc35xx.c create mode 100644 dts/bindings/gpio/ti,cc35xx-gpio-port-bank.yaml create mode 100644 dts/bindings/gpio/ti,cc35xx-gpio-port-pin.yaml diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts b/boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts index 3eda5388e23f..bd869d04d901 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts @@ -7,6 +7,7 @@ /dts-v1/; #include +#include #include "lp_em_cc35x1-pinctrl.dtsi" / { @@ -23,6 +24,65 @@ zephyr,shell-uart = &uart1; }; + leds { + compatible = "gpio-leds"; + green_led: green_led { + gpios = <&gpio30 0 GPIO_ACTIVE_HIGH>; + label = "GREEN USER LED"; + }; + red_led: red_led { + gpios = <&gpio34 0 GPIO_ACTIVE_HIGH>; + label = "RED USER LED"; + }; + blue_led: blue_led { + gpios = <&gpio35 0 GPIO_ACTIVE_HIGH>; + label = "BLUE USER LED"; + }; + }; + + buttons { + compatible = "gpio-keys"; + user_switch_1: user_sw_1 { + gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + label = "User SW1"; + }; + user_switch_2: user_sw_2{ + gpios = <&gpio36 0 GPIO_ACTIVE_LOW>; + label = "User SW2"; + }; + }; + + aliases { + led0 = &green_led; + led1 = &red_led; + led2 = &blue_led; + sw0 = &user_switch_1; + sw1 = &user_switch_2; + }; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio26 { + status = "okay"; +}; + +&gpio30 { + status = "okay"; +}; + +&gpio34 { + status = "okay"; +}; + +&gpio35 { + status = "okay"; +}; + +&gpio36 { + status = "okay"; }; &imem_ns { diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml b/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml index 8344850c540f..2ca1fea8c79e 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml @@ -8,6 +8,7 @@ toolchain: - zephyr - gnuarmemb supported: + - gpio - pinctrl - serial vendor: ti diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_defconfig b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_defconfig index 6ee853bfab6d..625f7743b11c 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_defconfig +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_defconfig @@ -16,3 +16,5 @@ CONFIG_SHELL_BACKEND_SERIAL_API_INTERRUPT_DRIVEN=y CONFIG_FLASH=y CONFIG_SOC_FLASH_CC35XX=y CONFIG_FLASH_SHELL=y + +CONFIG_GPIO=y diff --git a/drivers/gpio/CMakeLists.txt b/drivers/gpio/CMakeLists.txt index 063b3fccb039..0e5eca56723b 100644 --- a/drivers/gpio/CMakeLists.txt +++ b/drivers/gpio/CMakeLists.txt @@ -24,6 +24,7 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_BRCMSTB gpio_brcmstb.c) zephyr_library_sources_ifdef(CONFIG_GPIO_CC13XX_CC26XX gpio_cc13xx_cc26xx.c) zephyr_library_sources_ifdef(CONFIG_GPIO_CC23X0 gpio_cc23x0.c) zephyr_library_sources_ifdef(CONFIG_GPIO_CC32XX gpio_cc32xx.c) +zephyr_library_sources_ifdef(CONFIG_GPIO_CC35XX gpio_cc35xx.c) zephyr_library_sources_ifdef(CONFIG_GPIO_CMSDK_AHB gpio_cmsdk_ahb.c) zephyr_library_sources_ifdef(CONFIG_GPIO_CY8C95XX gpio_cy8c95xx.c) zephyr_library_sources_ifdef(CONFIG_GPIO_CYW43 gpio_cyw43.c) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index a65a6a94e8c0..ae2664733ab4 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -113,6 +113,7 @@ source "drivers/gpio/Kconfig.brcmstb" source "drivers/gpio/Kconfig.cc13xx_cc26xx" source "drivers/gpio/Kconfig.cc23x0" source "drivers/gpio/Kconfig.cc32xx" +source "drivers/gpio/Kconfig.cc35xx" source "drivers/gpio/Kconfig.cmsdk_ahb" source "drivers/gpio/Kconfig.creg_gpio" source "drivers/gpio/Kconfig.cy8c95xx" diff --git a/drivers/gpio/Kconfig.cc35xx b/drivers/gpio/Kconfig.cc35xx new file mode 100644 index 000000000000..a2f9aac5c638 --- /dev/null +++ b/drivers/gpio/Kconfig.cc35xx @@ -0,0 +1,11 @@ +# CC35XX GPIO configuration options + +# Copyright (c) 2025 Conclusive Engineering Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +config GPIO_CC35XX + bool "TI CC35XX GPIO driver" + default y + depends on DT_HAS_TI_CC35XX_GPIO_PORT_PIN_ENABLED + help + Enable the TI CC35XX GPIO driver diff --git a/drivers/gpio/gpio_cc35xx.c b/drivers/gpio/gpio_cc35xx.c new file mode 100644 index 000000000000..e7952808a508 --- /dev/null +++ b/drivers/gpio/gpio_cc35xx.c @@ -0,0 +1,321 @@ +/* + * Copyright (c) 2025 Conclusive Engineering Sp. z o.o. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT ti_cc35xx_gpio_port_bank + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +/* Missing defines from hw_hostmcu_aon.h */ +#define HOSTMCU_AON_CFGWICSNS_GPIO_AND_EN (1U << 1) +#define HOSTMCU_AON_CFGWICSNS_GPIO_OR_EN (1U << 2) +#define HOSTMCU_AON_CFGWUTP_GPIO_AND_FAST (1U << 1) +#define HOSTMCU_AON_CFGWUTP_GPIO_OR_FAST (1U << 2) + +struct cc35xx_gpio_port_pin_config { + /* gpio_driver_config needs to be first */ + struct gpio_driver_config common; + uint32_t gpio_index; +}; + +struct cc35xx_gpio_port_pin_data { + /* gpio_driver_data needs to be first */ + struct gpio_driver_data common; + const struct device *self; + sys_slist_t callbacks; +}; + +struct cc35xx_gpio_port_bank_config { + /* gpio_driver_config needs to be first */ + struct gpio_driver_config common; + uint32_t ngpios; + struct cc35xx_gpio_port_pin_config **port_pin_config; +}; + +struct cc35xx_gpio_port_bank_data { + /* gpio_driver_data needs to be first */ + struct gpio_driver_data common; + struct cc35xx_gpio_port_pin_data **port_pin_data; +}; + +static int cc35xx_gpio_port_get_raw(const struct device *dev, gpio_port_value_t *value) +{ + const struct cc35xx_gpio_port_pin_config *const dev_cfg = dev->config; + + *value = GPIO_read(dev_cfg->gpio_index); + return 0; +} + +static int cc35xx_gpio_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask, + gpio_port_value_t value) +{ + const struct cc35xx_gpio_port_pin_config *const dev_cfg = dev->config; + + GPIO_write(dev_cfg->gpio_index, value & mask); + return 0; +} + +static int cc35xx_gpio_port_set_bits_raw(const struct device *dev, gpio_port_pins_t mask) +{ + const struct cc35xx_gpio_port_pin_config *const dev_cfg = dev->config; + + GPIO_write(dev_cfg->gpio_index, BIT(0) & mask); + return 0; +} + +static int cc35xx_gpio_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t mask) +{ + const struct cc35xx_gpio_port_pin_config *const dev_cfg = dev->config; + + GPIO_write(dev_cfg->gpio_index, ~(BIT(0) & mask)); + return 0; +} + +static int cc35xx_gpio_port_toggle_bits(const struct device *dev, gpio_port_pins_t mask) +{ + const struct cc35xx_gpio_port_pin_config *const dev_cfg = dev->config; + + if (!(mask & BIT(0))) { + return -ENOTSUP; + } + + GPIO_toggle(dev_cfg->gpio_index); + return 0; +} + +static int cc35xx_gpio_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags) +{ + const struct cc35xx_gpio_port_pin_config *const dev_cfg = dev->config; + uint32_t config = 0; + + if (pin > 0) { + return -ENOTSUP; + } + + if ((flags & GPIO_DIR_MASK) == GPIO_DIR_MASK) { + return -ENOTSUP; + } + + if ((flags & GPIO_OUTPUT) && (flags & GPIO_LINE_OPEN_DRAIN)) { + return -ENOTSUP; + } + + if ((flags & GPIO_OUTPUT) && (flags & GPIO_LINE_OPEN_SOURCE)) { + return -ENOTSUP; + } + + if (flags & GPIO_OUTPUT) { + config |= GPIO_CFG_OUT_STD; + if (flags & GPIO_OUTPUT_INIT_HIGH) { + config |= GPIO_CFG_OUT_HIGH; + } else if (flags & GPIO_OUTPUT_INIT_LOW) { + config |= GPIO_CFG_OUT_LOW; + } + } else if (flags & GPIO_INPUT) { + if (flags & GPIO_PULL_UP) { + config |= GPIO_CFG_IN_PU; + } else if (flags & GPIO_PULL_DOWN) { + config |= GPIO_CFG_IN_PD; + } else { + config |= GPIO_CFG_IN_NOPULL; + } + } else { + config |= GPIO_CFG_NO_DIR; + } + + GPIO_setConfig(dev_cfg->gpio_index, config); + + return 0; +} + +static int cc35xx_gpio_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin, + enum gpio_int_mode mode, enum gpio_int_trig trig) +{ + uint32_t config = 0; + const struct cc35xx_gpio_port_pin_config *const dev_cfg = dev->config; + + if (mode == GPIO_INT_MODE_LEVEL) { + return -ENOTSUP; + } + + if (trig == GPIO_INT_TRIG_BOTH) { + return -ENOTSUP; + } + + switch (mode) { + case GPIO_INT_MODE_DISABLED: + config |= GPIO_CFG_INT_DISABLE; + break; + case GPIO_INT_MODE_EDGE: + config |= GPIO_CFG_INT_ENABLE; + config |= (trig == GPIO_INT_TRIG_HIGH) ? GPIO_CFG_IN_INT_RISING + : GPIO_CFG_IN_INT_FALLING; + break; + default: + return -ENOTSUP; + } + + GPIO_setInterruptConfig(dev_cfg->gpio_index, config); + + return 0; +} + +static int cc35xx_gpio_manage_callback(const struct device *dev, struct gpio_callback *callback, + bool set) +{ + struct cc35xx_gpio_port_pin_data *dev_data = dev->data; + + return gpio_manage_callback(&dev_data->callbacks, callback, set); +} + +static inline void cc35xx_event_mask_get(const struct device *dev, uint32_t event_mask, + bool low_interrupt) +{ + uint32_t flag_index; + struct cc35xx_gpio_port_pin_data *port_pin_data; + const struct cc35xx_gpio_port_bank_data *const dev_data = dev->data; + const struct cc35xx_gpio_port_bank_config *const dev_cfg = dev->config; + + while (event_mask) { + /* MASK_TO_PIN only detects the highest set bit */ + flag_index = GPIO_MASK_TO_PIN(event_mask); + if (unlikely(flag_index > dev_cfg->ngpios)) { + return; + } + + /* So it's safe to use PIN_TO_MASK to clear that bit */ + event_mask &= ~GPIO_PIN_TO_MASK(flag_index); + GPIO_clearInt(flag_index + (low_interrupt ? 0 : 32)); + port_pin_data = dev_data->port_pin_data[flag_index + (low_interrupt ? 0 : 32)]; + + if (likely(port_pin_data != NULL && port_pin_data->self != NULL)) { + /* BIT(0) - every port has only one pin */ + gpio_fire_callbacks(&port_pin_data->callbacks, port_pin_data->self, BIT(0)); + } + } +} + +static void cc35xx_gpio_port_bank_isr(const struct device *dev) +{ + uint32_t event_mask_0_31; + uint32_t event_mask_32_44; + + /* Get the masked interrupt status from the MIS registers */ + event_mask_0_31 = HWREG(SOC_AON_BASE + SOC_AON_O_GPIOMIS0S); + event_mask_32_44 = HWREG(SOC_AON_BASE + SOC_AON_O_GPIOMIS1S); + + cc35xx_event_mask_get(dev, event_mask_0_31, true); + cc35xx_event_mask_get(dev, event_mask_32_44, false); +} + +static int cc35xx_gpio_port_pin_init(const struct device *dev) +{ + struct cc35xx_gpio_port_pin_data *const dev_data = dev->data; + const struct cc35xx_gpio_port_pin_config *const dev_cfg = dev->config; + + dev_data->self = dev; + GPIO_setConfig(dev_cfg->gpio_index, GPIO_CFG_NO_DIR); + + return 0; +} + +static int cc35xx_gpio_port_bank_init(const struct device *dev) +{ + /* + * Make sure no GPIOs are wakeup sources. If the bit for a given GPIO is set + * in the mask, it means the event will not propagate to the wakeup + * interrupt. When interrupts are enabled/disabled for individual GPIOs, the + * corresponding bit in relevant mask will be cleared/set. + */ + HWREG(HOSTMCU_AON_BASE + HOSTMCU_AON_O_GPWUAND) = 0xFFFFFFFF; + HWREG(HOSTMCU_AON_BASE + HOSTMCU_AON_O_GPWUAND1) = 0xFFFFFFFF; + HWREG(HOSTMCU_AON_BASE + HOSTMCU_AON_O_GPWUOR) = 0xFFFFFFFF; + HWREG(HOSTMCU_AON_BASE + HOSTMCU_AON_O_GPWUOR1) = 0xFFFFFFFF; + + /* Disallow all GPIO interrupt sources to pass from RIS to MIS */ + HWREG(SOC_AON_BASE + SOC_AON_O_GPIOFNC0S) = 0; + HWREG(SOC_AON_BASE + SOC_AON_O_GPIOFNC1S) = 0; + + /* Enable IRQ */ + IRQ_CONNECT(DT_IRQN(DT_DRV_INST(0)), DT_IRQ(DT_DRV_INST(0), priority), + cc35xx_gpio_port_bank_isr, DEVICE_DT_GET(DT_INST(0, DT_DRV_COMPAT)), 0); + + irq_enable(DT_IRQN(DT_DRV_INST(0))); + + /* Configure the GPIO OR event as a sleep wakeup source */ + HWREG(HOSTMCU_AON_BASE + HOSTMCU_AON_O_CFGWICSNS) |= HOSTMCU_AON_CFGWICSNS_GPIO_OR_EN; + + /* Disable GPIO AND event as a sleep wakeup source */ + HWREG(HOSTMCU_AON_BASE + HOSTMCU_AON_O_CFGWICSNS) &= ~(HOSTMCU_AON_CFGWICSNS_GPIO_AND_EN); + + /* Configure the GPIO OR event to be a fast wakeup source */ + HWREG(HOSTMCU_AON_BASE + HOSTMCU_AON_O_CFGWUTP) |= HOSTMCU_AON_CFGWUTP_GPIO_OR_FAST; + + return 0; +} + +static const struct gpio_driver_api cc35xx_gpio_drv_api = { + .pin_configure = cc35xx_gpio_pin_configure, + .port_get_raw = cc35xx_gpio_port_get_raw, + .port_set_masked_raw = cc35xx_gpio_port_set_masked_raw, + .port_set_bits_raw = cc35xx_gpio_port_set_bits_raw, + .port_clear_bits_raw = cc35xx_gpio_port_clear_bits_raw, + .port_toggle_bits = cc35xx_gpio_port_toggle_bits, + .pin_interrupt_configure = cc35xx_gpio_pin_interrupt_configure, + .manage_callback = cc35xx_gpio_manage_callback, +}; + +#define CC35XX_GPIO_PORT_PIN_DEFINE(child_node_id) \ + static struct cc35xx_gpio_port_pin_data cc35xx_gpio_port_pin_data_##child_node_id; \ + static struct cc35xx_gpio_port_pin_config cc35xx_gpio_port_pin_config_##child_node_id = { \ + .gpio_index = DT_PROP(child_node_id, gpio_index), \ + .common.port_pin_mask = 1, \ + }; \ + DEVICE_DT_DEFINE(child_node_id, cc35xx_gpio_port_pin_init, NULL, \ + &cc35xx_gpio_port_pin_data_##child_node_id, \ + &cc35xx_gpio_port_pin_config_##child_node_id, PRE_KERNEL_1, \ + CONFIG_GPIO_INIT_PRIORITY, &cc35xx_gpio_drv_api) + +#define CC35XX_PIN_CONFIG_ENTRY(child) \ + [DT_PROP(child, gpio_index)] = &cc35xx_gpio_port_pin_config_##child, + +#define CC35XX_PIN_DATA_ENTRY(child) \ + [DT_PROP(child, gpio_index)] = &cc35xx_gpio_port_pin_data_##child, + +#define CC35XX_GPIO_PORT_BANK_DEFINE(inst) \ + DT_FOREACH_CHILD_STATUS_OKAY(DT_INST(inst, DT_DRV_COMPAT), CC35XX_GPIO_PORT_PIN_DEFINE); \ + static struct cc35xx_gpio_port_pin_data \ + *cc35xx_gpio_port_pin_data_array_##inst[DT_PROP(DT_DRV_INST(inst), ngpios)] = { \ + DT_FOREACH_CHILD_STATUS_OKAY(DT_INST(inst, DT_DRV_COMPAT), \ + CC35XX_PIN_DATA_ENTRY)}; \ + static struct cc35xx_gpio_port_pin_config \ + *cc35xx_gpio_port_pin_config_array_##inst[DT_PROP(DT_DRV_INST(inst), ngpios)] = { \ + DT_FOREACH_CHILD_STATUS_OKAY(DT_INST(inst, DT_DRV_COMPAT), \ + CC35XX_PIN_CONFIG_ENTRY)}; \ + static struct cc35xx_gpio_port_bank_data cc35xx_gpio_port_bank_data_##inst = { \ + .port_pin_data = cc35xx_gpio_port_pin_data_array_##inst, \ + }; \ + static const struct cc35xx_gpio_port_bank_config cc35xx_gpio_port_bank_config_##inst = { \ + .ngpios = DT_PROP(DT_DRV_INST(inst), ngpios), \ + .port_pin_config = cc35xx_gpio_port_pin_config_array_##inst, \ + }; \ + DEVICE_DT_INST_DEFINE(inst, cc35xx_gpio_port_bank_init, NULL, \ + &cc35xx_gpio_port_bank_data_##inst, \ + &cc35xx_gpio_port_bank_config_##inst, PRE_KERNEL_1, \ + CONFIG_GPIO_INIT_PRIORITY, NULL) + +DT_INST_FOREACH_STATUS_OKAY(CC35XX_GPIO_PORT_BANK_DEFINE) diff --git a/dts/arm/ti/cc35xxe.dtsi b/dts/arm/ti/cc35xxe.dtsi index 74f59fb82afd..05a5df2e4fac 100644 --- a/dts/arm/ti/cc35xxe.dtsi +++ b/dts/arm/ti/cc35xxe.dtsi @@ -220,6 +220,334 @@ write-block-size = <4>; }; + gpios: gpios@41100000 { + compatible = "ti,cc35xx-gpio-port-bank"; + status = "okay"; + ngpios = <40>; + interrupts = <17 1>; + reg = <0x41100000 0x4000>; + + gpio2: gpio2 { + compatible = "ti,cc35xx-gpio-port-pin"; + status = "disabled"; + gpio-controller; + #gpio-cells = <2>; + gpio-index = <2>; + }; + + gpio3: gpio3 { + compatible = "ti,cc35xx-gpio-port-pin"; + status = "disabled"; + gpio-controller; + #gpio-cells = <2>; + gpio-index = <3>; + }; + + gpio4: gpio4 { + compatible = "ti,cc35xx-gpio-port-pin"; + status = "disabled"; + gpio-controller; + #gpio-cells = <2>; + gpio-index = <4>; + }; + + gpio5: gpio5 { + compatible = "ti,cc35xx-gpio-port-pin"; + status = "disabled"; + gpio-controller; + #gpio-cells = <2>; + gpio-index = <5>; + }; + + gpio6: gpio6 { + compatible = "ti,cc35xx-gpio-port-pin"; + status = "disabled"; + gpio-controller; + #gpio-cells = <2>; + gpio-index = <6>; + }; + + gpio10: gpio10 { + compatible = "ti,cc35xx-gpio-port-pin"; + status = "disabled"; + gpio-controller; + #gpio-cells = <2>; + gpio-index = <10>; + }; + + gpio11: gpio11 { + compatible = "ti,cc35xx-gpio-port-pin"; + status = "disabled"; + gpio-controller; + #gpio-cells = <2>; + gpio-index = <11>; + }; + + gpio12: gpio12 { + compatible = "ti,cc35xx-gpio-port-pin"; + status = "disabled"; + gpio-controller; + #gpio-cells = <2>; + gpio-index = <12>; + }; + + gpio13: gpio13 { + compatible = "ti,cc35xx-gpio-port-pin"; + status = "disabled"; + gpio-controller; + #gpio-cells = <2>; + gpio-index = <13>; + }; + + gpio14: gpio14 { + compatible = "ti,cc35xx-gpio-port-pin"; + status = "disabled"; + gpio-controller; + #gpio-cells = <2>; + gpio-index = <14>; + }; + + gpio15: gpio15 { + compatible = "ti,cc35xx-gpio-port-pin"; + status = "disabled"; + gpio-controller; + #gpio-cells = <2>; + gpio-index = <15>; + }; + + gpio16: gpio16 { + compatible = "ti,cc35xx-gpio-port-pin"; + status = "disabled"; + gpio-controller; + #gpio-cells = <2>; + gpio-index = <16>; + }; + + gpio17: gpio17 { + compatible = "ti,cc35xx-gpio-port-pin"; + status = "disabled"; + gpio-controller; + #gpio-cells = <2>; + gpio-index = <17>; + }; + + gpio18: gpio18 { + compatible = "ti,cc35xx-gpio-port-pin"; + status = "disabled"; + gpio-controller; + #gpio-cells = <2>; + gpio-index = <18>; + }; + + gpio19: gpio19 { + compatible = "ti,cc35xx-gpio-port-pin"; + status = "disabled"; + gpio-controller; + #gpio-cells = <2>; + gpio-index = <19>; + }; + + gpio20: gpio20 { + compatible = "ti,cc35xx-gpio-port-pin"; + status = "disabled"; + gpio-controller; + #gpio-cells = <2>; + gpio-index = <20>; + }; + + gpio21: gpio21 { + compatible = "ti,cc35xx-gpio-port-pin"; + status = "disabled"; + gpio-controller; + #gpio-cells = <2>; + gpio-index = <21>; + }; + + gpio22: gpio22 { + compatible = "ti,cc35xx-gpio-port-pin"; + status = "disabled"; + gpio-controller; + #gpio-cells = <2>; + gpio-index = <22>; + }; + + gpio23: gpio23 { + compatible = "ti,cc35xx-gpio-port-pin"; + status = "disabled"; + gpio-controller; + #gpio-cells = <2>; + gpio-index = <23>; + }; + + gpio24: gpio24 { + compatible = "ti,cc35xx-gpio-port-pin"; + status = "disabled"; + gpio-controller; + #gpio-cells = <2>; + gpio-index = <24>; + }; + + gpio25: gpio25 { + compatible = "ti,cc35xx-gpio-port-pin"; + status = "disabled"; + gpio-controller; + #gpio-cells = <2>; + gpio-index = <25>; + }; + + gpio26: gpio26 { + compatible = "ti,cc35xx-gpio-port-pin"; + status = "disabled"; + gpio-controller; + #gpio-cells = <2>; + gpio-index = <26>; + }; + + gpio27: gpio27 { + compatible = "ti,cc35xx-gpio-port-pin"; + status = "disabled"; + gpio-controller; + #gpio-cells = <2>; + gpio-index = <27>; + }; + + gpio28: gpio28 { + compatible = "ti,cc35xx-gpio-port-pin"; + status = "disabled"; + gpio-controller; + #gpio-cells = <2>; + gpio-index = <28>; + }; + + gpio29: gpio29 { + compatible = "ti,cc35xx-gpio-port-pin"; + status = "disabled"; + gpio-controller; + #gpio-cells = <2>; + gpio-index = <29>; + }; + + gpio30: gpio30 { + compatible = "ti,cc35xx-gpio-port-pin"; + status = "disabled"; + gpio-controller; + #gpio-cells = <2>; + gpio-index = <30>; + }; + + gpio31: gpio31 { + compatible = "ti,cc35xx-gpio-port-pin"; + status = "disabled"; + gpio-controller; + #gpio-cells = <2>; + gpio-index = <31>; + }; + + gpio32: gpio32 { + compatible = "ti,cc35xx-gpio-port-pin"; + status = "disabled"; + gpio-controller; + #gpio-cells = <2>; + gpio-index = <32>; + }; + + gpio33: gpio33 { + compatible = "ti,cc35xx-gpio-port-pin"; + status = "disabled"; + gpio-controller; + #gpio-cells = <2>; + gpio-index = <33>; + }; + + gpio34: gpio34 { + compatible = "ti,cc35xx-gpio-port-pin"; + status = "disabled"; + gpio-controller; + #gpio-cells = <2>; + gpio-index = <34>; + }; + + gpio35: gpio35 { + compatible = "ti,cc35xx-gpio-port-pin"; + status = "disabled"; + gpio-controller; + #gpio-cells = <2>; + gpio-index = <35>; + }; + + gpio36: gpio36 { + compatible = "ti,cc35xx-gpio-port-pin"; + status = "disabled"; + gpio-controller; + #gpio-cells = <2>; + gpio-index = <36>; + }; + + gpio37: gpio37 { + compatible = "ti,cc35xx-gpio-port-pin"; + status = "disabled"; + gpio-controller; + #gpio-cells = <2>; + gpio-index = <37>; + }; + + gpio38: gpio38 { + compatible = "ti,cc35xx-gpio-port-pin"; + status = "disabled"; + gpio-controller; + #gpio-cells = <2>; + gpio-index = <38>; + }; + + gpio39: gpio39 { + compatible = "ti,cc35xx-gpio-port-pin"; + status = "disabled"; + gpio-controller; + #gpio-cells = <2>; + gpio-index = <39>; + }; + + gpio40: gpio40 { + compatible = "ti,cc35xx-gpio-port-pin"; + status = "disabled"; + gpio-controller; + #gpio-cells = <2>; + gpio-index = <40>; + }; + + gpio41: gpio41 { + compatible = "ti,cc35xx-gpio-port-pin"; + status = "disabled"; + gpio-controller; + #gpio-cells = <2>; + gpio-index = <41>; + }; + + gpio42: gpio42 { + compatible = "ti,cc35xx-gpio-port-pin"; + status = "disabled"; + gpio-controller; + #gpio-cells = <2>; + gpio-index = <42>; + }; + + gpio43: gpio43 { + compatible = "ti,cc35xx-gpio-port-pin"; + status = "disabled"; + gpio-controller; + #gpio-cells = <2>; + gpio-index = <43>; + }; + + gpio44: gpio44 { + compatible = "ti,cc35xx-gpio-port-pin"; + status = "disabled"; + gpio-controller; + #gpio-cells = <2>; + gpio-index = <44>; + }; + }; + flash0: flash@a0000000 { compatible = "ti,cc35xx-nv-flash"; #address-cells = <1>; diff --git a/dts/bindings/gpio/ti,cc35xx-gpio-port-bank.yaml b/dts/bindings/gpio/ti,cc35xx-gpio-port-bank.yaml new file mode 100644 index 000000000000..723bdcda5140 --- /dev/null +++ b/dts/bindings/gpio/ti,cc35xx-gpio-port-bank.yaml @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +description: TI GPIO ports bank node + +compatible: "ti,cc35xx-gpio-port-bank" + +include: [base.yaml] + +properties: + ngpios: + type: int + default: 40 + description: | + Number of GPIOs available on port bank. diff --git a/dts/bindings/gpio/ti,cc35xx-gpio-port-pin.yaml b/dts/bindings/gpio/ti,cc35xx-gpio-port-pin.yaml new file mode 100644 index 000000000000..825421ad81b6 --- /dev/null +++ b/dts/bindings/gpio/ti,cc35xx-gpio-port-pin.yaml @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: Apache-2.0 + +description: | + TI GPIO + +compatible: "ti,cc35xx-gpio-port-pin" + +include: [gpio-controller.yaml, base.yaml] + +properties: + npins: + type: int + const: 1 + description: | + Number of GPIOs available on port. + + gpio-index: + type: int + required: true + +gpio-cells: + - pin + - flags From 5a6532acd3344723f62df01afe149972f93853c0 Mon Sep 17 00:00:00 2001 From: Piotr Glinianowicz Date: Mon, 20 Oct 2025 11:48:10 +0200 Subject: [PATCH 017/100] UPSTREAM-PEND: gpio: Rework the GPIO driver to use gpio-nexus pin mappin... MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ...g mechanism. With this we don't need to instantiate a gpio-controller per pin and the translation between the global GPIO pin number and the per-port GPIO pin number is done automatically via gpio-map property. Signed-off-by: Piotr Glinianowicz Signed-off-by: Michał Łyszczek Signed-off-by: Jakub Jarosinski --- boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts | 34 +- boards/ti/lp_em_cc35x1/lp_em_cc35x1_defconfig | 13 +- drivers/gpio/Kconfig.cc35xx | 2 +- drivers/gpio/gpio_cc35xx.c | 713 ++++++++++++++---- dts/arm/ti/cc35xxe.dtsi | 355 --------- .../gpio/ti,cc35xx-gpio-port-bank.yaml | 14 - dts/bindings/gpio/ti,cc35xx-gpio-port.yaml | 31 + dts/bindings/gpio/ti,cc35xx-gpio.yaml | 8 + .../boards/lp_em_cc35x1.overlay | 13 + .../gpio_hogs/boards/lp_em_cc35x1.overlay | 37 + tests/drivers/gpio/gpio_hogs/testcase.yaml | 1 + 11 files changed, 687 insertions(+), 534 deletions(-) delete mode 100644 dts/bindings/gpio/ti,cc35xx-gpio-port-bank.yaml create mode 100644 dts/bindings/gpio/ti,cc35xx-gpio-port.yaml create mode 100644 dts/bindings/gpio/ti,cc35xx-gpio.yaml create mode 100644 tests/drivers/gpio/gpio_basic_api/boards/lp_em_cc35x1.overlay create mode 100644 tests/drivers/gpio/gpio_hogs/boards/lp_em_cc35x1.overlay diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts b/boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts index bd869d04d901..7f1e7841ac72 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts @@ -27,15 +27,15 @@ leds { compatible = "gpio-leds"; green_led: green_led { - gpios = <&gpio30 0 GPIO_ACTIVE_HIGH>; + gpios = <&gpios 30 GPIO_ACTIVE_HIGH>; label = "GREEN USER LED"; }; red_led: red_led { - gpios = <&gpio34 0 GPIO_ACTIVE_HIGH>; + gpios = <&gpios 34 GPIO_ACTIVE_HIGH>; label = "RED USER LED"; }; blue_led: blue_led { - gpios = <&gpio35 0 GPIO_ACTIVE_HIGH>; + gpios = <&gpios 35 GPIO_ACTIVE_HIGH>; label = "BLUE USER LED"; }; }; @@ -43,11 +43,11 @@ buttons { compatible = "gpio-keys"; user_switch_1: user_sw_1 { - gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + gpios = <&gpios 2 GPIO_ACTIVE_LOW>; label = "User SW1"; }; user_switch_2: user_sw_2{ - gpios = <&gpio36 0 GPIO_ACTIVE_LOW>; + gpios = <&gpios 36 GPIO_ACTIVE_LOW>; label = "User SW2"; }; }; @@ -61,30 +61,6 @@ }; }; -&gpio2 { - status = "okay"; -}; - -&gpio26 { - status = "okay"; -}; - -&gpio30 { - status = "okay"; -}; - -&gpio34 { - status = "okay"; -}; - -&gpio35 { - status = "okay"; -}; - -&gpio36 { - status = "okay"; -}; - &imem_ns { status = "okay"; }; diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_defconfig b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_defconfig index 625f7743b11c..bbaadbd81c49 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_defconfig +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_defconfig @@ -4,6 +4,17 @@ # SPDX-License-Identifier: Apache-2.0 # +CONFIG_SHARED_MULTI_HEAP=y + +CONFIG_GPIO=y +CONFIG_GPIO_GET_CONFIG=y +CONFIG_GPIO_GET_DIRECTION=y +CONFIG_GPIO_HOGS=y +CONFIG_GPIO_SHELL=y +CONFIG_GPIO_SHELL_INFO_CMD=y +CONFIG_GPIO_SHELL_TOGGLE_CMD=y +CONFIG_GPIO_SHELL_BLINK_CMD=y + CONFIG_SERIAL=y CONFIG_CONSOLE=y @@ -16,5 +27,3 @@ CONFIG_SHELL_BACKEND_SERIAL_API_INTERRUPT_DRIVEN=y CONFIG_FLASH=y CONFIG_SOC_FLASH_CC35XX=y CONFIG_FLASH_SHELL=y - -CONFIG_GPIO=y diff --git a/drivers/gpio/Kconfig.cc35xx b/drivers/gpio/Kconfig.cc35xx index a2f9aac5c638..8ed690cde100 100644 --- a/drivers/gpio/Kconfig.cc35xx +++ b/drivers/gpio/Kconfig.cc35xx @@ -6,6 +6,6 @@ config GPIO_CC35XX bool "TI CC35XX GPIO driver" default y - depends on DT_HAS_TI_CC35XX_GPIO_PORT_PIN_ENABLED + depends on DT_HAS_TI_CC35XX_GPIO_PORT_ENABLED help Enable the TI CC35XX GPIO driver diff --git a/drivers/gpio/gpio_cc35xx.c b/drivers/gpio/gpio_cc35xx.c index e7952808a508..60da8354bf95 100644 --- a/drivers/gpio/gpio_cc35xx.c +++ b/drivers/gpio/gpio_cc35xx.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#define DT_DRV_COMPAT ti_cc35xx_gpio_port_bank +#define DT_DRV_COMPAT ti_cc35xx_gpio_port #include #include @@ -20,90 +20,410 @@ #include #include -/* Missing defines from hw_hostmcu_aon.h */ +/* + * Below defines are copied from: + * modules/hal/ti/simplelink_wifi/source/ti/drivers/gpio/GPIOWFF3.c + */ + + /* Missing defines from hw_hostmcu_aon.h */ #define HOSTMCU_AON_CFGWICSNS_GPIO_AND_EN (1U << 1) #define HOSTMCU_AON_CFGWICSNS_GPIO_OR_EN (1U << 2) #define HOSTMCU_AON_CFGWUTP_GPIO_AND_FAST (1U << 1) #define HOSTMCU_AON_CFGWUTP_GPIO_OR_FAST (1U << 2) -struct cc35xx_gpio_port_pin_config { +/* The size of each IO region in IOMUX id 4KB */ +#define IOMUX_IO_REGION_SIZE (4096U) + +#define IOMUX_CFG_ADDR(index) \ + (IOMUX_BASE + IOMUX_O_SCLKICFG + ((index) * IOMUX_IO_REGION_SIZE) \ + + (IOMUX_O_GPIO2CFG - IOMUX_O_GPIO2CFG)) +#define IOMUX_PULLCTL_ADDR(index) \ + (IOMUX_BASE + IOMUX_O_SCLKICFG + ((index) * IOMUX_IO_REGION_SIZE) \ + + (IOMUX_O_GPIO2PCTL - IOMUX_O_GPIO2CFG)) +#define IOMUX_CTL_ADDR(index) \ + (IOMUX_BASE + IOMUX_O_SCLKICFG + ((index) * IOMUX_IO_REGION_SIZE) \ + + (IOMUX_O_GPIO2CTL - IOMUX_O_GPIO2CFG)) +#define IOMUX_EVTCTL_ADDR(index) \ + (IOMUX_BASE + IOMUX_O_SCLKICFG + ((index) * IOMUX_IO_REGION_SIZE) \ + + (IOMUX_O_GPIO2ECTL - IOMUX_O_GPIO2CFG)) +#define IOMUX_PORTCFG_ADDR(index) (IOMUX_BASE + IOMUX_O_SCLKIPCFG + ((index) << 2)) + +struct cc35xx_gpio_port_config { /* gpio_driver_config needs to be first */ struct gpio_driver_config common; - uint32_t gpio_index; + uint8_t ngpios; + uint32_t gpio_index_offset; }; -struct cc35xx_gpio_port_pin_data { +struct cc35xx_gpio_port_data { /* gpio_driver_data needs to be first */ struct gpio_driver_data common; - const struct device *self; sys_slist_t callbacks; }; -struct cc35xx_gpio_port_bank_config { - /* gpio_driver_config needs to be first */ - struct gpio_driver_config common; - uint32_t ngpios; - struct cc35xx_gpio_port_pin_config **port_pin_config; -}; +/* + * The "cc35xx_ll_*" functions come from TI HAL and were copied almost + * as-is, with a few exceptions to type changes and style to stay consistent + * with the rest of the Zephyr code. + * + * The cc35xx HW is organized into a single GPIO bank with single index space + * (0..44) and that's reflected in HAL functions - they accept the "global" + * index value (i.e. 0-44). + * + * The Zephyr driver organizes GPIO pins into 2 banks with up to 32 pins + * per bank. This is done to stay consistent with Zephyr GPIO API. + * This means that Zephyr API functions accept GPIO index as per-bank value + * (0.., where is the number of pins in given GPIO bank). + * + * The API functions also translate Zephyr GPIO flags to/from their + * HAL counterparts. + */ -struct cc35xx_gpio_port_bank_data { - /* gpio_driver_data needs to be first */ - struct gpio_driver_data common; - struct cc35xx_gpio_port_pin_data **port_pin_data; -}; +static uint8_t cc35xx_ll_gpio_read(uint8_t index) +{ + uint32_t ctlRegAddr = IOMUX_CTL_ADDR(index); + + return (sys_read32(ctlRegAddr) & IOMUX_GPIO2CTL_PADVAL_M) >> IOMUX_GPIO2CTL_PADVAL_S; +} + +static void cc35xx_ll_gpio_write(uint8_t index, uint32_t value) +{ + uint32_t ctlRegAddr; + uint32_t tmpctlReg; + uintptr_t key; + + ctlRegAddr = IOMUX_CTL_ADDR(index); + + /* Protect read-modify-write operation to write to GPIO. */ + key = irq_lock(); + tmpctlReg = sys_read32(ctlRegAddr); + tmpctlReg &= ~IOMUX_GPIO2CTL_OUT_M; + tmpctlReg |= (value & 0x1) << IOMUX_GPIO2CTL_OUT_S; + sys_write32(tmpctlReg, ctlRegAddr); + irq_unlock(key); +} + +static void cc35xx_ll_gpio_toggle(uint8_t index) +{ + uint32_t ctlRegAddr; + uint32_t tmpctlReg; + uintptr_t key; + + ctlRegAddr = IOMUX_CTL_ADDR(index); + + /* Protect read-modify-write operation to toggle GPIO. */ + key = irq_lock(); + tmpctlReg = sys_read32(ctlRegAddr); + tmpctlReg ^= IOMUX_GPIO2CTL_OUT; + sys_write32(tmpctlReg, ctlRegAddr); + irq_unlock(key); +} + +static void cc35xx_ll_gpio_disable_int(uint8_t index) +{ + uintptr_t key; + uint32_t val; + + /* Clear bit in IMASK register to disable interrupts */ + key = irq_lock(); + if (index >= 32) { + /* Disable interrupt by clearing functional mask bit */ + val = sys_read32(SOC_AON_BASE + SOC_AON_O_GPIOFNC1S); + val &= ~(1 << (index - 32)); + sys_write32(val, (SOC_AON_BASE + SOC_AON_O_GPIOFNC1S)); + + /* + * Disable wakeup event by setting the GPIO OR wakeup event mask bit. + * When the bit is set, the event is disabled. + */ + val = sys_read32(HOSTMCU_AON_BASE + HOSTMCU_AON_O_GPWUOR1); + val |= (1 << (index - 32)); + sys_write32(val, (HOSTMCU_AON_BASE + HOSTMCU_AON_O_GPWUOR1)); + } else { + /* Disable interrupt by clearing functional mask bit */ + val = sys_read32(SOC_AON_BASE + SOC_AON_O_GPIOFNC0S); + val &= ~(1 << index); + sys_write32(val, (SOC_AON_BASE + SOC_AON_O_GPIOFNC0S)); + + /* + * Disable wakeup event by setting the GPIO OR wakeup event mask bit. + * When the bit is set, the event is disabled. + */ + val = sys_read32(HOSTMCU_AON_BASE + HOSTMCU_AON_O_GPWUOR); + val |= (1 << index); + sys_write32(val, (HOSTMCU_AON_BASE + HOSTMCU_AON_O_GPWUOR)); + } + irq_unlock(key); +} + +static void cc35xx_ll_gpio_enable_int(uint8_t index) +{ + uintptr_t key; + uint32_t val; + + /* Set bit in IMASK register to enable interrupts */ + key = irq_lock(); + if (index >= 32) { + /* Enable interrupt by setting functional mask bit */ + val = sys_read32(SOC_AON_BASE + SOC_AON_O_GPIOFNC1S); + val |= (1 << (index - 32)); + sys_write32(val, (SOC_AON_BASE + SOC_AON_O_GPIOFNC1S)); + + /* + * Enable wakeup event by clearing the GPIO OR wakeup event mask bit. + * When the bit is cleared, the event is enabled. + */ + val = sys_read32(HOSTMCU_AON_BASE + HOSTMCU_AON_O_GPWUOR1); + val &= ~(1 << (index - 32)); + sys_write32(val, (HOSTMCU_AON_BASE + HOSTMCU_AON_O_GPWUOR1)); + } else { + /* Enable interrupt by setting functional mask bit (IMASK equivalent) */ + val = sys_read32(SOC_AON_BASE + SOC_AON_O_GPIOFNC0S); + val |= (1 << index); + sys_write32(val, (SOC_AON_BASE + SOC_AON_O_GPIOFNC0S)); + + /* + * Enable wakeup event by clearing the GPIO OR wakeup event mask bit. + * When the bit is cleared, the event is enabled. + */ + val = sys_read32(HOSTMCU_AON_BASE + HOSTMCU_AON_O_GPWUOR); + val &= ~(1 << index); + sys_write32(val, (HOSTMCU_AON_BASE + HOSTMCU_AON_O_GPWUOR)); + } + irq_unlock(key); +} + +static void cc35xx_ll_gpio_clear_int(uint8_t index) +{ + uintptr_t key; + uint32_t registerAddr; + uint32_t val; + + registerAddr = IOMUX_EVTCTL_ADDR(index); + + key = irq_lock(); + val = sys_read32(registerAddr); + val |= IOMUX_GPIO2ECTL_CLR; + sys_write32(val, registerAddr); + irq_unlock(key); +} + +static void cc35xx_ll_gpio_set_config_and_mux(uint8_t index, uint32_t config, uint32_t mux) +{ + uint32_t cfgRegAddr; + uint32_t pullctlRegAddr; + uint32_t ctlRegAddr; + uint32_t evtctlRegAddr; + uint32_t portcfgRegAddr; + uint32_t tmpCfgReg; + uint32_t tmpPullctlCfgReg; + uint32_t tmpctlReg; + uint32_t tmpEvtctlReg; + uint32_t tmpPortcfgReg; + + cfgRegAddr = IOMUX_CFG_ADDR(index); + pullctlRegAddr = IOMUX_PULLCTL_ADDR(index); + ctlRegAddr = IOMUX_CTL_ADDR(index); + evtctlRegAddr = IOMUX_EVTCTL_ADDR(index); + portcfgRegAddr = IOMUX_PORTCFG_ADDR(index); + + /* Extract register-specific values from compressed pin config */ + tmpCfgReg = (config & GPIOWFF3_CFG_CFG_M) >> GPIOWFF3_CFG_CFG_S; + tmpPullctlCfgReg = (config & GPIOWFF3_CFG_PULLCTL_M) >> GPIOWFF3_CFG_PULLCTL_S; + tmpctlReg = (config & GPIOWFF3_CFG_CTL_M) >> GPIOWFF3_CFG_CTL_S; + tmpEvtctlReg = (config & GPIOWFF3_CFG_EVTCTL_M) >> GPIOWFF3_CFG_EVTCTL_S; + tmpPortcfgReg = (mux << IOMUX_GPIO2PCFG_IOSEL_S) & IOMUX_GPIO2PCFG_IOSEL_M; + + /* + * If the IO is muxed to the analog IP for that IO, then the analog switch + * must be controlled by the analog IP. If not, the analog switch must be + * controlled by the SW to keep the switch open. + * If tmpCfgReg is kept unmodified from above, the analog switch will be + * controlled by the analog IP. So the value of tmpCfgReg needs to be + * changed if the IO is not muxed to the analog IP. + */ + if (!(mux & GPIOWFF3_MUX_ANALOG_INTERNAL)) { + /* + * Enable analog switch control override, and set the analog switch to + * be disabled (open) + */ + tmpCfgReg |= (IOMUX_GPIO2CFG_ANASWOVREN_ENABLE | IOMUX_GPIO2CFG_ANASW_DISABLE); + } + + if (mux == GPIO_MUX_GPIO) { + /* + * Mux to GPIO functionality. + * Change muxing after changing configuration to prevent glitching. + */ + sys_write32(tmpCfgReg, cfgRegAddr); + sys_write32(tmpPullctlCfgReg, pullctlRegAddr); + sys_write32(tmpctlReg, ctlRegAddr); + sys_write32(tmpEvtctlReg, evtctlRegAddr); + sys_write32(tmpPortcfgReg, portcfgRegAddr); + } else { + /* + * Change muxing before changing configuration + * This is to prevent glitching. If output was previously overridden, and + * if it will not be overridden by the new configuration, then the override + * will be disabled after the muxing has been changed. + */ + sys_write32(tmpPortcfgReg, portcfgRegAddr); + sys_write32(tmpCfgReg, cfgRegAddr); + sys_write32(tmpPullctlCfgReg, pullctlRegAddr); + sys_write32(tmpctlReg, ctlRegAddr); + sys_write32(tmpEvtctlReg, evtctlRegAddr); + } + + if (config & GPIO_CFG_INT_ENABLE) { + cc35xx_ll_gpio_enable_int(index); + } else { + cc35xx_ll_gpio_disable_int(index); + } +} + +#ifdef CONFIG_GPIO_GET_CONFIG +static void cc35xx_ll_gpio_get_config(uint8_t index, uint32_t *config) +{ + uint32_t cfgRegAddr; + uint32_t pullctlRegAddr; + uint32_t ctlRegAddr; + uint32_t evtctlRegAddr; + uint32_t tmpCfgReg; + uint32_t tmpPullctlCfgReg; + uint32_t tmpctlReg; + uint32_t tmpEvtctlReg; + uint32_t configValue; + uint32_t tmpCfgRegBit; + + cfgRegAddr = IOMUX_CFG_ADDR(index); + pullctlRegAddr = IOMUX_PULLCTL_ADDR(index); + ctlRegAddr = IOMUX_CTL_ADDR(index); + evtctlRegAddr = IOMUX_EVTCTL_ADDR(index); + + tmpCfgReg = sys_read32(cfgRegAddr); + tmpPullctlCfgReg = sys_read32(pullctlRegAddr); + tmpctlReg = sys_read32(ctlRegAddr); + tmpEvtctlReg = sys_read32(evtctlRegAddr); + + configValue = ((tmpCfgReg << GPIOWFF3_CFG_CFG_S) & GPIOWFF3_CFG_CFG_M) | + ((tmpPullctlCfgReg << GPIOWFF3_CFG_PULLCTL_S) & GPIOWFF3_CFG_PULLCTL_M) | + ((tmpctlReg << GPIOWFF3_CFG_CTL_S) & GPIOWFF3_CFG_CTL_M) | + ((tmpEvtctlReg << GPIOWFF3_CFG_EVTCTL_S) & GPIOWFF3_CFG_EVTCTL_M); + + /* If IMASK bit is set, the interrupt is enabled. */ + if (index >= 32) { + tmpCfgReg = sys_read32(SOC_AON_BASE + SOC_AON_O_GPIOFNC1S); + tmpCfgRegBit = 1 << (index - 32); + } else { + tmpCfgReg = sys_read32(SOC_AON_BASE + SOC_AON_O_GPIOFNC0S); + tmpCfgRegBit = 1 << index; + } + + if ((tmpCfgReg & tmpCfgRegBit) == tmpCfgRegBit) { + configValue |= GPIO_CFG_INT_ENABLE; + } + + /* Report current configuration */ + *config = configValue; +} +#endif + +static void cc35xx_ll_gpio_set_interrupt_config(uint8_t index, uint32_t config) +{ + uintptr_t key; + uint32_t evtctlRegAddr; + + /* The EVTCTL contains all the interrupt configuration */ + evtctlRegAddr = IOMUX_EVTCTL_ADDR(index); + + /* Mask away all non-interrupt configuration (all non-EVTCTL configuration) */ + uint32_t maskedConfig = (config & GPIOWFF3_CFG_EVTCTL_M) >> GPIOWFF3_CFG_EVTCTL_S; + + /* Invert the EVTCTL mask, mask out current interrupt config and apply the new one */ + key = irq_lock(); + uint32_t currentRegisterConfig = sys_read32(evtctlRegAddr); + + currentRegisterConfig &= ~(GPIOWFF3_CFG_EVTCTL_M >> GPIOWFF3_CFG_EVTCTL_S); + sys_write32((currentRegisterConfig | maskedConfig), evtctlRegAddr); + irq_unlock(key); + + if (config & GPIO_CFG_INT_ENABLE) { + cc35xx_ll_gpio_enable_int(index); + } else { + cc35xx_ll_gpio_disable_int(index); + } +} static int cc35xx_gpio_port_get_raw(const struct device *dev, gpio_port_value_t *value) { - const struct cc35xx_gpio_port_pin_config *const dev_cfg = dev->config; + const struct cc35xx_gpio_port_config *const port_cfg = dev->config; + + *value = 0; + for (int i = 0; i < port_cfg->ngpios; i++) { + *value = *value | (cc35xx_ll_gpio_read(port_cfg->gpio_index_offset + i) << i); + } - *value = GPIO_read(dev_cfg->gpio_index); return 0; } static int cc35xx_gpio_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask, - gpio_port_value_t value) + gpio_port_value_t value) { - const struct cc35xx_gpio_port_pin_config *const dev_cfg = dev->config; + const struct cc35xx_gpio_port_config *const port_cfg = dev->config; - GPIO_write(dev_cfg->gpio_index, value & mask); + for (int i = 0; i < port_cfg->ngpios; i++) { + if (mask & BIT(i)) { + cc35xx_ll_gpio_write(port_cfg->gpio_index_offset + i, + (BIT(i) & value) >> i); + } + } return 0; } static int cc35xx_gpio_port_set_bits_raw(const struct device *dev, gpio_port_pins_t mask) { - const struct cc35xx_gpio_port_pin_config *const dev_cfg = dev->config; + const struct cc35xx_gpio_port_config *const port_cfg = dev->config; - GPIO_write(dev_cfg->gpio_index, BIT(0) & mask); + for (int i = 0; i < port_cfg->ngpios; i++) { + if (mask & BIT(i)) { + cc35xx_ll_gpio_write(port_cfg->gpio_index_offset + i, 0x01); + } + } return 0; } static int cc35xx_gpio_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t mask) { - const struct cc35xx_gpio_port_pin_config *const dev_cfg = dev->config; + const struct cc35xx_gpio_port_config *const port_cfg = dev->config; - GPIO_write(dev_cfg->gpio_index, ~(BIT(0) & mask)); + for (int i = 0; i < port_cfg->ngpios; i++) { + if (mask & BIT(i)) { + cc35xx_ll_gpio_write(port_cfg->gpio_index_offset + i, 0x00); + } + } return 0; } static int cc35xx_gpio_port_toggle_bits(const struct device *dev, gpio_port_pins_t mask) { - const struct cc35xx_gpio_port_pin_config *const dev_cfg = dev->config; + const struct cc35xx_gpio_port_config *const port_cfg = dev->config; - if (!(mask & BIT(0))) { - return -ENOTSUP; + for (int i = 0; i < port_cfg->ngpios; i++) { + if (mask & BIT(i)) { + cc35xx_ll_gpio_toggle(port_cfg->gpio_index_offset + i); + } } - GPIO_toggle(dev_cfg->gpio_index); return 0; } static int cc35xx_gpio_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags) { - const struct cc35xx_gpio_port_pin_config *const dev_cfg = dev->config; + const struct cc35xx_gpio_port_config *const port_cfg = dev->config; uint32_t config = 0; - if (pin > 0) { - return -ENOTSUP; + if (pin >= port_cfg->ngpios) { + return -EINVAL; } if ((flags & GPIO_DIR_MASK) == GPIO_DIR_MASK) { @@ -126,9 +446,14 @@ static int cc35xx_gpio_pin_configure(const struct device *dev, gpio_pin_t pin, g config |= GPIO_CFG_OUT_LOW; } } else if (flags & GPIO_INPUT) { - if (flags & GPIO_PULL_UP) { + if (flags & GPIO_PULL_DOWN) { + /* + * The Pull up / Pull down definitions in HAL + * are reversed with regards to HW implementation + * so we adjust for that when configuring the pin. + */ config |= GPIO_CFG_IN_PU; - } else if (flags & GPIO_PULL_DOWN) { + } else if (flags & GPIO_PULL_UP) { config |= GPIO_CFG_IN_PD; } else { config |= GPIO_CFG_IN_NOPULL; @@ -137,16 +462,154 @@ static int cc35xx_gpio_pin_configure(const struct device *dev, gpio_pin_t pin, g config |= GPIO_CFG_NO_DIR; } - GPIO_setConfig(dev_cfg->gpio_index, config); + cc35xx_ll_gpio_set_config_and_mux(port_cfg->gpio_index_offset + pin, config, GPIO_MUX_GPIO); + + return 0; +} + +#ifdef CONFIG_GPIO_GET_CONFIG +static inline bool cc35xx_config_is_output(uint32_t config) +{ + if ((config & ~0x1ff) == (GPIO_CFG_OUTPUT)) { + return true; + } + return false; +} + +static inline bool cc35xx_config_is_output_high(uint32_t config) +{ + if (!cc35xx_config_is_output(config)) { + return false; + } + if ((config & 0x1ff) == (GPIO_CFG_OUT_HIGH)) { + return true; + } + return false; +} + +static inline bool cc35xx_config_is_output_low(uint32_t config) +{ + if (!cc35xx_config_is_output(config)) { + return false; + } + if ((config & 0x1ff) == (GPIO_CFG_OUT_LOW)) { + return true; + } + return false; +} + +static inline bool cc35xx_config_is_input(uint32_t config) +{ + if ((config & ~0x1ff) == (GPIO_CFG_INPUT)) { + return true; + } + return false; +} + +static inline bool cc35xx_config_is_input_pull_up(uint32_t config) +{ + if (!cc35xx_config_is_input(config)) { + return false; + } + /* + * The Pull up / Pull down definitions in HAL + * are reversed with regards to HW implementation + * so we adjust for that when reading pin config. + */ + if ((config & 0xff) == (IOMUX_GPIO2PCTL_CTL_DOWN)) { + return true; + } + return false; +} + +static inline bool cc35xx_config_is_input_pull_down(uint32_t config) +{ + if (!cc35xx_config_is_input(config)) { + return false; + } + /* + * The Pull up / Pull down definitions in HAL + * are reversed with regards to HW implementation + * so we adjust for that when reading pin config. + */ + if ((config & 0xff) == (IOMUX_GPIO2PCTL_CTL_UP)) { + return true; + } + return false; +} + +static int cc35xx_gpio_pin_get_config(const struct device *dev, gpio_pin_t pin, + gpio_flags_t *out_flags) +{ + const struct cc35xx_gpio_port_config *const port_cfg = dev->config; + uint32_t config = 0; + + if (pin >= port_cfg->ngpios) { + return -EINVAL; + } + + cc35xx_ll_gpio_get_config(port_cfg->gpio_index_offset + pin, &config); + + *out_flags = 0; + + if (cc35xx_config_is_output_high(config)) { + *out_flags = GPIO_OUTPUT | GPIO_OUTPUT_HIGH; + } else if (cc35xx_config_is_output_low(config)) { + *out_flags = GPIO_OUTPUT | GPIO_OUTPUT_LOW; + } else if (cc35xx_config_is_input_pull_down(config)) { + *out_flags = GPIO_INPUT | GPIO_PULL_DOWN; + } else if (cc35xx_config_is_input_pull_up(config)) { + *out_flags = GPIO_INPUT | GPIO_PULL_UP; + } else if (cc35xx_config_is_input(config)) { + *out_flags = GPIO_INPUT; + } else { + return -EINVAL; + } + + return 0; +} +#endif + +#ifdef CONFIG_GPIO_GET_DIRECTION +static int cc35xx_gpio_port_get_direction(const struct device *dev, gpio_port_pins_t map, + gpio_port_pins_t *inputs, gpio_port_pins_t *outputs) +{ + const struct cc35xx_gpio_port_config *const port_cfg = dev->config; + uint32_t config; + if (outputs != NULL) { + *outputs = 0; + } + if (inputs != NULL) { + *inputs = 0; + } + for (int i = 0; i < port_cfg->ngpios; i++) { + if ((map >> i) & 1) { + cc35xx_ll_gpio_get_config(port_cfg->gpio_index_offset + i, &config); + if (outputs != NULL) { + if (cc35xx_config_is_output(config)) { + *outputs |= (1 << i); + continue; + } + } + if (inputs != NULL) { + if (cc35xx_config_is_input(config)) { + *inputs |= (1 << i); + continue; + } + } + } + } return 0; } +#endif static int cc35xx_gpio_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin, - enum gpio_int_mode mode, enum gpio_int_trig trig) + enum gpio_int_mode mode, enum gpio_int_trig trig) { uint32_t config = 0; - const struct cc35xx_gpio_port_pin_config *const dev_cfg = dev->config; + const struct cc35xx_gpio_port_config *const port_cfg = dev->config; + uint32_t gpio_index = pin + port_cfg->gpio_index_offset; if (mode == GPIO_INT_MODE_LEVEL) { return -ENOTSUP; @@ -163,113 +626,121 @@ static int cc35xx_gpio_pin_interrupt_configure(const struct device *dev, gpio_pi case GPIO_INT_MODE_EDGE: config |= GPIO_CFG_INT_ENABLE; config |= (trig == GPIO_INT_TRIG_HIGH) ? GPIO_CFG_IN_INT_RISING - : GPIO_CFG_IN_INT_FALLING; + : GPIO_CFG_IN_INT_FALLING; break; default: return -ENOTSUP; } - GPIO_setInterruptConfig(dev_cfg->gpio_index, config); + cc35xx_ll_gpio_set_interrupt_config(gpio_index, config); return 0; } static int cc35xx_gpio_manage_callback(const struct device *dev, struct gpio_callback *callback, - bool set) + bool set) { - struct cc35xx_gpio_port_pin_data *dev_data = dev->data; + struct cc35xx_gpio_port_data *port_data = dev->data; - return gpio_manage_callback(&dev_data->callbacks, callback, set); + return gpio_manage_callback(&port_data->callbacks, callback, set); } -static inline void cc35xx_event_mask_get(const struct device *dev, uint32_t event_mask, - bool low_interrupt) +static void cc35xx_gpio_port_isr(const struct device *dev, uint32_t event_mask) { uint32_t flag_index; - struct cc35xx_gpio_port_pin_data *port_pin_data; - const struct cc35xx_gpio_port_bank_data *const dev_data = dev->data; - const struct cc35xx_gpio_port_bank_config *const dev_cfg = dev->config; + const struct cc35xx_gpio_port_config *port_cfg = dev->config; + struct cc35xx_gpio_port_data *port_data = dev->data; + + gpio_fire_callbacks(&port_data->callbacks, dev, event_mask); while (event_mask) { - /* MASK_TO_PIN only detects the highest set bit */ + /* MASK_TO_PIN returns the highest set bit */ flag_index = GPIO_MASK_TO_PIN(event_mask); - if (unlikely(flag_index > dev_cfg->ngpios)) { - return; - } - - /* So it's safe to use PIN_TO_MASK to clear that bit */ + cc35xx_ll_gpio_clear_int(flag_index + port_cfg->gpio_index_offset); event_mask &= ~GPIO_PIN_TO_MASK(flag_index); - GPIO_clearInt(flag_index + (low_interrupt ? 0 : 32)); - port_pin_data = dev_data->port_pin_data[flag_index + (low_interrupt ? 0 : 32)]; - - if (likely(port_pin_data != NULL && port_pin_data->self != NULL)) { - /* BIT(0) - every port has only one pin */ - gpio_fire_callbacks(&port_pin_data->callbacks, port_pin_data->self, BIT(0)); - } } } -static void cc35xx_gpio_port_bank_isr(const struct device *dev) +static void cc35xx_gpio_isr(const struct device *dev) { - uint32_t event_mask_0_31; - uint32_t event_mask_32_44; + ARG_UNUSED(dev); + uint32_t event_mask; - /* Get the masked interrupt status from the MIS registers */ - event_mask_0_31 = HWREG(SOC_AON_BASE + SOC_AON_O_GPIOMIS0S); - event_mask_32_44 = HWREG(SOC_AON_BASE + SOC_AON_O_GPIOMIS1S); + /* Lower bank */ + event_mask = sys_read32(SOC_AON_BASE + SOC_AON_O_GPIOMIS0S); + if (event_mask) { + const struct device *port = DEVICE_DT_INST_GET(0); - cc35xx_event_mask_get(dev, event_mask_0_31, true); - cc35xx_event_mask_get(dev, event_mask_32_44, false); -} + cc35xx_gpio_port_isr(port, event_mask); + } -static int cc35xx_gpio_port_pin_init(const struct device *dev) -{ - struct cc35xx_gpio_port_pin_data *const dev_data = dev->data; - const struct cc35xx_gpio_port_pin_config *const dev_cfg = dev->config; + /* Higher bank */ + event_mask = sys_read32(SOC_AON_BASE + SOC_AON_O_GPIOMIS1S); - dev_data->self = dev; - GPIO_setConfig(dev_cfg->gpio_index, GPIO_CFG_NO_DIR); + if (event_mask) { + const struct device *port = DEVICE_DT_INST_GET(1); - return 0; + cc35xx_gpio_port_isr(port, event_mask); + } } -static int cc35xx_gpio_port_bank_init(const struct device *dev) +static int cc35xx_gpio_init(const struct device *dev) { + static bool gpio_init_done; + uint32_t val; + + if (gpio_init_done) { + return 0; + } + /* * Make sure no GPIOs are wakeup sources. If the bit for a given GPIO is set * in the mask, it means the event will not propagate to the wakeup * interrupt. When interrupts are enabled/disabled for individual GPIOs, the * corresponding bit in relevant mask will be cleared/set. */ - HWREG(HOSTMCU_AON_BASE + HOSTMCU_AON_O_GPWUAND) = 0xFFFFFFFF; - HWREG(HOSTMCU_AON_BASE + HOSTMCU_AON_O_GPWUAND1) = 0xFFFFFFFF; - HWREG(HOSTMCU_AON_BASE + HOSTMCU_AON_O_GPWUOR) = 0xFFFFFFFF; - HWREG(HOSTMCU_AON_BASE + HOSTMCU_AON_O_GPWUOR1) = 0xFFFFFFFF; + sys_write32(0xFFFFFFFF, (HOSTMCU_AON_BASE + HOSTMCU_AON_O_GPWUAND)); + sys_write32(0xFFFFFFFF, (HOSTMCU_AON_BASE + HOSTMCU_AON_O_GPWUAND1)); + sys_write32(0xFFFFFFFF, (HOSTMCU_AON_BASE + HOSTMCU_AON_O_GPWUOR)); + sys_write32(0xFFFFFFFF, (HOSTMCU_AON_BASE + HOSTMCU_AON_O_GPWUOR1)); /* Disallow all GPIO interrupt sources to pass from RIS to MIS */ - HWREG(SOC_AON_BASE + SOC_AON_O_GPIOFNC0S) = 0; - HWREG(SOC_AON_BASE + SOC_AON_O_GPIOFNC1S) = 0; - - /* Enable IRQ */ - IRQ_CONNECT(DT_IRQN(DT_DRV_INST(0)), DT_IRQ(DT_DRV_INST(0), priority), - cc35xx_gpio_port_bank_isr, DEVICE_DT_GET(DT_INST(0, DT_DRV_COMPAT)), 0); - - irq_enable(DT_IRQN(DT_DRV_INST(0))); + sys_write32(0, (SOC_AON_BASE + SOC_AON_O_GPIOFNC0S)); + sys_write32(0, (SOC_AON_BASE + SOC_AON_O_GPIOFNC1S)); /* Configure the GPIO OR event as a sleep wakeup source */ - HWREG(HOSTMCU_AON_BASE + HOSTMCU_AON_O_CFGWICSNS) |= HOSTMCU_AON_CFGWICSNS_GPIO_OR_EN; + val = sys_read32(HOSTMCU_AON_BASE + HOSTMCU_AON_O_CFGWICSNS); + val |= HOSTMCU_AON_CFGWICSNS_GPIO_OR_EN; + sys_write32(val, (HOSTMCU_AON_BASE + HOSTMCU_AON_O_CFGWICSNS)); /* Disable GPIO AND event as a sleep wakeup source */ - HWREG(HOSTMCU_AON_BASE + HOSTMCU_AON_O_CFGWICSNS) &= ~(HOSTMCU_AON_CFGWICSNS_GPIO_AND_EN); + val = sys_read32(HOSTMCU_AON_BASE + HOSTMCU_AON_O_CFGWICSNS); + val &= ~(HOSTMCU_AON_CFGWICSNS_GPIO_AND_EN); + sys_write32(val, (HOSTMCU_AON_BASE + HOSTMCU_AON_O_CFGWICSNS)); /* Configure the GPIO OR event to be a fast wakeup source */ - HWREG(HOSTMCU_AON_BASE + HOSTMCU_AON_O_CFGWUTP) |= HOSTMCU_AON_CFGWUTP_GPIO_OR_FAST; + val = sys_read32(HOSTMCU_AON_BASE + HOSTMCU_AON_O_CFGWUTP); + val |= HOSTMCU_AON_CFGWUTP_GPIO_OR_FAST; + sys_write32(val, (HOSTMCU_AON_BASE + HOSTMCU_AON_O_CFGWUTP)); + + IRQ_CONNECT(DT_IRQN(DT_DRV_INST(0)), DT_IRQ(DT_DRV_INST(0), priority), + cc35xx_gpio_isr, DEVICE_DT_GET(DT_INST(0, DT_DRV_COMPAT)), 0); + + irq_enable(DT_IRQN(DT_DRV_INST(0))); + + gpio_init_done = true; return 0; } static const struct gpio_driver_api cc35xx_gpio_drv_api = { .pin_configure = cc35xx_gpio_pin_configure, +#ifdef CONFIG_GPIO_GET_CONFIG + .pin_get_config = cc35xx_gpio_pin_get_config, +#endif +#ifdef CONFIG_GPIO_GET_DIRECTION + .port_get_direction = cc35xx_gpio_port_get_direction, +#endif .port_get_raw = cc35xx_gpio_port_get_raw, .port_set_masked_raw = cc35xx_gpio_port_set_masked_raw, .port_set_bits_raw = cc35xx_gpio_port_set_bits_raw, @@ -279,43 +750,19 @@ static const struct gpio_driver_api cc35xx_gpio_drv_api = { .manage_callback = cc35xx_gpio_manage_callback, }; -#define CC35XX_GPIO_PORT_PIN_DEFINE(child_node_id) \ - static struct cc35xx_gpio_port_pin_data cc35xx_gpio_port_pin_data_##child_node_id; \ - static struct cc35xx_gpio_port_pin_config cc35xx_gpio_port_pin_config_##child_node_id = { \ - .gpio_index = DT_PROP(child_node_id, gpio_index), \ - .common.port_pin_mask = 1, \ - }; \ - DEVICE_DT_DEFINE(child_node_id, cc35xx_gpio_port_pin_init, NULL, \ - &cc35xx_gpio_port_pin_data_##child_node_id, \ - &cc35xx_gpio_port_pin_config_##child_node_id, PRE_KERNEL_1, \ - CONFIG_GPIO_INIT_PRIORITY, &cc35xx_gpio_drv_api) - -#define CC35XX_PIN_CONFIG_ENTRY(child) \ - [DT_PROP(child, gpio_index)] = &cc35xx_gpio_port_pin_config_##child, - -#define CC35XX_PIN_DATA_ENTRY(child) \ - [DT_PROP(child, gpio_index)] = &cc35xx_gpio_port_pin_data_##child, - -#define CC35XX_GPIO_PORT_BANK_DEFINE(inst) \ - DT_FOREACH_CHILD_STATUS_OKAY(DT_INST(inst, DT_DRV_COMPAT), CC35XX_GPIO_PORT_PIN_DEFINE); \ - static struct cc35xx_gpio_port_pin_data \ - *cc35xx_gpio_port_pin_data_array_##inst[DT_PROP(DT_DRV_INST(inst), ngpios)] = { \ - DT_FOREACH_CHILD_STATUS_OKAY(DT_INST(inst, DT_DRV_COMPAT), \ - CC35XX_PIN_DATA_ENTRY)}; \ - static struct cc35xx_gpio_port_pin_config \ - *cc35xx_gpio_port_pin_config_array_##inst[DT_PROP(DT_DRV_INST(inst), ngpios)] = { \ - DT_FOREACH_CHILD_STATUS_OKAY(DT_INST(inst, DT_DRV_COMPAT), \ - CC35XX_PIN_CONFIG_ENTRY)}; \ - static struct cc35xx_gpio_port_bank_data cc35xx_gpio_port_bank_data_##inst = { \ - .port_pin_data = cc35xx_gpio_port_pin_data_array_##inst, \ - }; \ - static const struct cc35xx_gpio_port_bank_config cc35xx_gpio_port_bank_config_##inst = { \ - .ngpios = DT_PROP(DT_DRV_INST(inst), ngpios), \ - .port_pin_config = cc35xx_gpio_port_pin_config_array_##inst, \ - }; \ - DEVICE_DT_INST_DEFINE(inst, cc35xx_gpio_port_bank_init, NULL, \ - &cc35xx_gpio_port_bank_data_##inst, \ - &cc35xx_gpio_port_bank_config_##inst, PRE_KERNEL_1, \ - CONFIG_GPIO_INIT_PRIORITY, NULL) - -DT_INST_FOREACH_STATUS_OKAY(CC35XX_GPIO_PORT_BANK_DEFINE) +#define CC35XX_GPIO_PORT_DEFINE(inst) \ + static struct cc35xx_gpio_port_data cc35xx_gpio_port_data_##inst; \ + static const struct cc35xx_gpio_port_config cc35xx_gpio_port_config_##inst = { \ + .common = \ + { \ + .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(inst), \ + }, \ + .ngpios = DT_PROP(DT_DRV_INST(inst), ngpios), \ + .gpio_index_offset = DT_PROP(DT_DRV_INST(inst), gpio_index_offset), \ + }; \ + DEVICE_DT_INST_DEFINE(inst, cc35xx_gpio_init, NULL, \ + &cc35xx_gpio_port_data_##inst, \ + &cc35xx_gpio_port_config_##inst, PRE_KERNEL_1, \ + CONFIG_GPIO_INIT_PRIORITY, &cc35xx_gpio_drv_api); + +DT_INST_FOREACH_STATUS_OKAY(CC35XX_GPIO_PORT_DEFINE) diff --git a/dts/arm/ti/cc35xxe.dtsi b/dts/arm/ti/cc35xxe.dtsi index 05a5df2e4fac..d5905c643906 100644 --- a/dts/arm/ti/cc35xxe.dtsi +++ b/dts/arm/ti/cc35xxe.dtsi @@ -219,361 +219,6 @@ erase-block-size = ; write-block-size = <4>; }; - - gpios: gpios@41100000 { - compatible = "ti,cc35xx-gpio-port-bank"; - status = "okay"; - ngpios = <40>; - interrupts = <17 1>; - reg = <0x41100000 0x4000>; - - gpio2: gpio2 { - compatible = "ti,cc35xx-gpio-port-pin"; - status = "disabled"; - gpio-controller; - #gpio-cells = <2>; - gpio-index = <2>; - }; - - gpio3: gpio3 { - compatible = "ti,cc35xx-gpio-port-pin"; - status = "disabled"; - gpio-controller; - #gpio-cells = <2>; - gpio-index = <3>; - }; - - gpio4: gpio4 { - compatible = "ti,cc35xx-gpio-port-pin"; - status = "disabled"; - gpio-controller; - #gpio-cells = <2>; - gpio-index = <4>; - }; - - gpio5: gpio5 { - compatible = "ti,cc35xx-gpio-port-pin"; - status = "disabled"; - gpio-controller; - #gpio-cells = <2>; - gpio-index = <5>; - }; - - gpio6: gpio6 { - compatible = "ti,cc35xx-gpio-port-pin"; - status = "disabled"; - gpio-controller; - #gpio-cells = <2>; - gpio-index = <6>; - }; - - gpio10: gpio10 { - compatible = "ti,cc35xx-gpio-port-pin"; - status = "disabled"; - gpio-controller; - #gpio-cells = <2>; - gpio-index = <10>; - }; - - gpio11: gpio11 { - compatible = "ti,cc35xx-gpio-port-pin"; - status = "disabled"; - gpio-controller; - #gpio-cells = <2>; - gpio-index = <11>; - }; - - gpio12: gpio12 { - compatible = "ti,cc35xx-gpio-port-pin"; - status = "disabled"; - gpio-controller; - #gpio-cells = <2>; - gpio-index = <12>; - }; - - gpio13: gpio13 { - compatible = "ti,cc35xx-gpio-port-pin"; - status = "disabled"; - gpio-controller; - #gpio-cells = <2>; - gpio-index = <13>; - }; - - gpio14: gpio14 { - compatible = "ti,cc35xx-gpio-port-pin"; - status = "disabled"; - gpio-controller; - #gpio-cells = <2>; - gpio-index = <14>; - }; - - gpio15: gpio15 { - compatible = "ti,cc35xx-gpio-port-pin"; - status = "disabled"; - gpio-controller; - #gpio-cells = <2>; - gpio-index = <15>; - }; - - gpio16: gpio16 { - compatible = "ti,cc35xx-gpio-port-pin"; - status = "disabled"; - gpio-controller; - #gpio-cells = <2>; - gpio-index = <16>; - }; - - gpio17: gpio17 { - compatible = "ti,cc35xx-gpio-port-pin"; - status = "disabled"; - gpio-controller; - #gpio-cells = <2>; - gpio-index = <17>; - }; - - gpio18: gpio18 { - compatible = "ti,cc35xx-gpio-port-pin"; - status = "disabled"; - gpio-controller; - #gpio-cells = <2>; - gpio-index = <18>; - }; - - gpio19: gpio19 { - compatible = "ti,cc35xx-gpio-port-pin"; - status = "disabled"; - gpio-controller; - #gpio-cells = <2>; - gpio-index = <19>; - }; - - gpio20: gpio20 { - compatible = "ti,cc35xx-gpio-port-pin"; - status = "disabled"; - gpio-controller; - #gpio-cells = <2>; - gpio-index = <20>; - }; - - gpio21: gpio21 { - compatible = "ti,cc35xx-gpio-port-pin"; - status = "disabled"; - gpio-controller; - #gpio-cells = <2>; - gpio-index = <21>; - }; - - gpio22: gpio22 { - compatible = "ti,cc35xx-gpio-port-pin"; - status = "disabled"; - gpio-controller; - #gpio-cells = <2>; - gpio-index = <22>; - }; - - gpio23: gpio23 { - compatible = "ti,cc35xx-gpio-port-pin"; - status = "disabled"; - gpio-controller; - #gpio-cells = <2>; - gpio-index = <23>; - }; - - gpio24: gpio24 { - compatible = "ti,cc35xx-gpio-port-pin"; - status = "disabled"; - gpio-controller; - #gpio-cells = <2>; - gpio-index = <24>; - }; - - gpio25: gpio25 { - compatible = "ti,cc35xx-gpio-port-pin"; - status = "disabled"; - gpio-controller; - #gpio-cells = <2>; - gpio-index = <25>; - }; - - gpio26: gpio26 { - compatible = "ti,cc35xx-gpio-port-pin"; - status = "disabled"; - gpio-controller; - #gpio-cells = <2>; - gpio-index = <26>; - }; - - gpio27: gpio27 { - compatible = "ti,cc35xx-gpio-port-pin"; - status = "disabled"; - gpio-controller; - #gpio-cells = <2>; - gpio-index = <27>; - }; - - gpio28: gpio28 { - compatible = "ti,cc35xx-gpio-port-pin"; - status = "disabled"; - gpio-controller; - #gpio-cells = <2>; - gpio-index = <28>; - }; - - gpio29: gpio29 { - compatible = "ti,cc35xx-gpio-port-pin"; - status = "disabled"; - gpio-controller; - #gpio-cells = <2>; - gpio-index = <29>; - }; - - gpio30: gpio30 { - compatible = "ti,cc35xx-gpio-port-pin"; - status = "disabled"; - gpio-controller; - #gpio-cells = <2>; - gpio-index = <30>; - }; - - gpio31: gpio31 { - compatible = "ti,cc35xx-gpio-port-pin"; - status = "disabled"; - gpio-controller; - #gpio-cells = <2>; - gpio-index = <31>; - }; - - gpio32: gpio32 { - compatible = "ti,cc35xx-gpio-port-pin"; - status = "disabled"; - gpio-controller; - #gpio-cells = <2>; - gpio-index = <32>; - }; - - gpio33: gpio33 { - compatible = "ti,cc35xx-gpio-port-pin"; - status = "disabled"; - gpio-controller; - #gpio-cells = <2>; - gpio-index = <33>; - }; - - gpio34: gpio34 { - compatible = "ti,cc35xx-gpio-port-pin"; - status = "disabled"; - gpio-controller; - #gpio-cells = <2>; - gpio-index = <34>; - }; - - gpio35: gpio35 { - compatible = "ti,cc35xx-gpio-port-pin"; - status = "disabled"; - gpio-controller; - #gpio-cells = <2>; - gpio-index = <35>; - }; - - gpio36: gpio36 { - compatible = "ti,cc35xx-gpio-port-pin"; - status = "disabled"; - gpio-controller; - #gpio-cells = <2>; - gpio-index = <36>; - }; - - gpio37: gpio37 { - compatible = "ti,cc35xx-gpio-port-pin"; - status = "disabled"; - gpio-controller; - #gpio-cells = <2>; - gpio-index = <37>; - }; - - gpio38: gpio38 { - compatible = "ti,cc35xx-gpio-port-pin"; - status = "disabled"; - gpio-controller; - #gpio-cells = <2>; - gpio-index = <38>; - }; - - gpio39: gpio39 { - compatible = "ti,cc35xx-gpio-port-pin"; - status = "disabled"; - gpio-controller; - #gpio-cells = <2>; - gpio-index = <39>; - }; - - gpio40: gpio40 { - compatible = "ti,cc35xx-gpio-port-pin"; - status = "disabled"; - gpio-controller; - #gpio-cells = <2>; - gpio-index = <40>; - }; - - gpio41: gpio41 { - compatible = "ti,cc35xx-gpio-port-pin"; - status = "disabled"; - gpio-controller; - #gpio-cells = <2>; - gpio-index = <41>; - }; - - gpio42: gpio42 { - compatible = "ti,cc35xx-gpio-port-pin"; - status = "disabled"; - gpio-controller; - #gpio-cells = <2>; - gpio-index = <42>; - }; - - gpio43: gpio43 { - compatible = "ti,cc35xx-gpio-port-pin"; - status = "disabled"; - gpio-controller; - #gpio-cells = <2>; - gpio-index = <43>; - }; - - gpio44: gpio44 { - compatible = "ti,cc35xx-gpio-port-pin"; - status = "disabled"; - gpio-controller; - #gpio-cells = <2>; - gpio-index = <44>; - }; - }; - - flash0: flash@a0000000 { - compatible = "ti,cc35xx-nv-flash"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xa0000000 0x00033000>, <0x0 0x00033000>; - erase-block-size = ; - write-block-size = <4>; - }; - - flash1: flash@10000000 { - compatible = "ti,cc35xx-nv-flash"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x10000000 0x001e7000>, <0x00033000 0x001e7000>; - erase-block-size = ; - write-block-size = <4>; - }; - - flash2: flash@a0050000 { - compatible = "ti,cc35xx-nv-flash"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xa0050000 0x001ea000>, <0x0021a000 0x001ea000>; - erase-block-size = ; - write-block-size = <4>; - }; }; }; diff --git a/dts/bindings/gpio/ti,cc35xx-gpio-port-bank.yaml b/dts/bindings/gpio/ti,cc35xx-gpio-port-bank.yaml deleted file mode 100644 index 723bdcda5140..000000000000 --- a/dts/bindings/gpio/ti,cc35xx-gpio-port-bank.yaml +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -description: TI GPIO ports bank node - -compatible: "ti,cc35xx-gpio-port-bank" - -include: [base.yaml] - -properties: - ngpios: - type: int - default: 40 - description: | - Number of GPIOs available on port bank. diff --git a/dts/bindings/gpio/ti,cc35xx-gpio-port.yaml b/dts/bindings/gpio/ti,cc35xx-gpio-port.yaml new file mode 100644 index 000000000000..ea5d07e91565 --- /dev/null +++ b/dts/bindings/gpio/ti,cc35xx-gpio-port.yaml @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: Apache-2.0 + +description: | + TI GPIO port node + +compatible: "ti,cc35xx-gpio-port" + +include: [gpio-controller.yaml, base.yaml] + +properties: + "#gpio-cells": + const: 2 + + gpio-index-offset: + type: int + required: true + description: | + The cc35xx hardware has a single GPIO controller + which aggregates all the available GPIO pins. + The indexes range from 0 to + + In Zephyr the GPIOs are split into ports, + each aggregating up to 32 pins. + First port indexes match the global indexes (0-31), + second port is offset by 32 + (0-31 port pins map to 32-63 pins in the global pool). + and so on. + +gpio-cells: + - pin + - flags diff --git a/dts/bindings/gpio/ti,cc35xx-gpio.yaml b/dts/bindings/gpio/ti,cc35xx-gpio.yaml new file mode 100644 index 000000000000..470956aab709 --- /dev/null +++ b/dts/bindings/gpio/ti,cc35xx-gpio.yaml @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +description: | + TI GPIO nexus node. + +compatible: "ti,cc35xx-gpio" + +include: [gpio-nexus.yaml, base.yaml] diff --git a/tests/drivers/gpio/gpio_basic_api/boards/lp_em_cc35x1.overlay b/tests/drivers/gpio/gpio_basic_api/boards/lp_em_cc35x1.overlay new file mode 100644 index 000000000000..5d7c2421ce0b --- /dev/null +++ b/tests/drivers/gpio/gpio_basic_api/boards/lp_em_cc35x1.overlay @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2025 Conclusive Engineering Sp. z o.o. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + resources { + compatible = "test-gpio-basic-api"; + out-gpios = <&gpios 27 0>; /* Pin 7 (SPI0_CLK) (&gpio0_31 27) */ + in-gpios = <&gpios 29 0>; /* Pin 15 (SPI0_PICO) (&gpio0_31 29) */ + }; +}; diff --git a/tests/drivers/gpio/gpio_hogs/boards/lp_em_cc35x1.overlay b/tests/drivers/gpio/gpio_hogs/boards/lp_em_cc35x1.overlay new file mode 100644 index 000000000000..3d7880507f22 --- /dev/null +++ b/tests/drivers/gpio/gpio_hogs/boards/lp_em_cc35x1.overlay @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2025 Conclusive Engineering Sp. z o.o. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + zephyr,user { + output-high-gpios = <&gpio0_31 30 GPIO_ACTIVE_LOW>; /* GPIO30, Green LED */ + output-low-gpios = <&gpio32_63 2 GPIO_ACTIVE_HIGH>; /* GPIO34, Red LED */ + input-gpios = <&gpio0_31 2 GPIO_ACTIVE_HIGH>; /* GPIO2, SW 1 */ + }; +}; + +&gpio0_31 { + hog1 { + gpio-hog; + gpios = <30 GPIO_ACTIVE_LOW>; + output-high; + }; + + hog3 { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + input; + }; +}; + +&gpio32_63 { + hog2 { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-low; + }; +}; diff --git a/tests/drivers/gpio/gpio_hogs/testcase.yaml b/tests/drivers/gpio/gpio_hogs/testcase.yaml index 05496eecca11..978cfe063a58 100644 --- a/tests/drivers/gpio/gpio_hogs/testcase.yaml +++ b/tests/drivers/gpio/gpio_hogs/testcase.yaml @@ -23,6 +23,7 @@ tests: - s32z2xxdc2/s32z270/rtu1 - s32z2xxdc2@D/s32z270/rtu0 - s32z2xxdc2@D/s32z270/rtu1 + - lp_em_cc35x1 - xg29_rb4412a - bg29_rb4420a - sam_e54_xpro From c58a10c182cc2833af52bb889116097d646fbc8f Mon Sep 17 00:00:00 2001 From: Jakub Jarosinski Date: Thu, 9 Jul 2026 09:42:56 +0200 Subject: [PATCH 018/100] UPSTREAM-PEND: boards: ti: lp_em_cc35x1: add BoosterPack header Describe the LaunchPad BoosterPack header pins in devicetree so shields and overlays can reference the connector in the usual way. Signed-off-by: Jakub Jarosinski --- .../lp_em_cc35x1/boosterpack_connector.dtsi | 39 +++++++++++++++++++ boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts | 1 + 2 files changed, 40 insertions(+) create mode 100644 boards/ti/lp_em_cc35x1/boosterpack_connector.dtsi diff --git a/boards/ti/lp_em_cc35x1/boosterpack_connector.dtsi b/boards/ti/lp_em_cc35x1/boosterpack_connector.dtsi new file mode 100644 index 000000000000..d68963facc2a --- /dev/null +++ b/boards/ti/lp_em_cc35x1/boosterpack_connector.dtsi @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2026 Conclusive Engineering Sp. z o.o. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + boosterpack_header: connector { + compatible = "ti,boosterpack-header"; + #gpio-cells = <2>; + gpio-map = <3 0 &gpios 18 0>, /* UART0_RX */ + <4 0 &gpios 17 0>, /* UART0_TX */ + <5 0 &gpios 10 0>, /* I2C1_DATA */ + <6 0 &gpios 11 0>, /* I2C1_CLK */ + <7 0 &gpios 27 0>, /* SPI0_CLK */ + <8 0 &gpios 14 0>, /* SPI1_CLK */ + <9 0 &gpios 33 0>, /* I2C0_CLK */ + <10 0 &gpios 32 0>, /* I2C0_DATA */ + <11 0 &gpios 15 0>, /* SPI1_MISO */ + <12 0 &gpios 12 0>, /* SPI1_CS */ + <13 0 &gpios 13 0>, /* SPI1_MOSI */ + <14 0 &gpios 28 0>, /* SPI0_MISO */ + <15 0 &gpios 29 0>, /* SPI0_MOSI */ + <17 0 &gpios 30 0>, /* PWM / Green LED */ + <18 0 &gpios 26 0>, /* SPI0_CS */ + <19 0 &gpios 2 0>, /* Button 1 */ + <25 0 &gpios 4 0>, /* ADC4 */ + <26 0 &gpios 3 0>, /* ADC5 */ + <30 0 &gpios 31 0>, /* I2S_DATA1 */ + <31 0 &gpios 34 0>, /* CAN_RX / Red LED */ + <32 0 &gpios 30 0>, /* CAN_TX */ + <36 0 &gpios 35 0>, /* Blue LED */ + <37 0 &gpios 16 0>, /* UART0_RTS */ + <38 0 &gpios 19 0>, /* UART0_CTS */ + <40 0 &gpios 36 0>; /* Button 2 */ + }; +}; + +boosterpack_serial: &uart0 {}; diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts b/boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts index 7f1e7841ac72..0a4d1062b6bd 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts @@ -8,6 +8,7 @@ #include #include +#include "boosterpack_connector.dtsi" #include "lp_em_cc35x1-pinctrl.dtsi" / { From 2911f006230a556f5b802158d5b1f04d52bdb555 Mon Sep 17 00:00:00 2001 From: Jakub Jarosinski Date: Wed, 10 Jun 2026 15:09:53 +0200 Subject: [PATCH 019/100] UPSTREAM-PEND: drivers: flash: cc35xx: write flash through uDMA Use the external-memory uDMA flash path for writes while preserving read-modify-write handling for partial write chunks. Signed-off-by: Jakub Jarosinski --- drivers/flash/soc_flash_cc35xx.c | 64 +++++++++++++++++++++++++++++--- 1 file changed, 59 insertions(+), 5 deletions(-) diff --git a/drivers/flash/soc_flash_cc35xx.c b/drivers/flash/soc_flash_cc35xx.c index 82accf6773c1..5b1adeda6f81 100644 --- a/drivers/flash/soc_flash_cc35xx.c +++ b/drivers/flash/soc_flash_cc35xx.c @@ -17,6 +17,7 @@ #define DT_DRV_COMPAT ti_cc35xx_nv_flash #define CC35XX_ERASE_TIMEOUT 200 +#define CC35XX_FLASH_WRITE_SIZE 256 struct flash_cc35xx_config { mem_addr_t base; @@ -28,6 +29,7 @@ struct flash_cc35xx_config { }; static int flash_cc35xx_initialized; static struct k_mutex flash_cc35xx_mutex; +static uint8_t flash_cc35xx_write_buf[CC35XX_FLASH_WRITE_SIZE] __aligned(sizeof(uint32_t)); static mem_addr_t flash_cc35xx_offset_to_phys_addr(const struct device *dev, off_t offset) { @@ -48,7 +50,23 @@ static bool flash_cc35xx_is_range_valid(const struct device *dev, off_t offset, { const struct flash_cc35xx_config *config = dev->config; - return ((size_t)offset < config->size) && (size < config->size - offset); + if ((offset < 0) || ((size_t)offset > config->size)) { + return false; + } + + return size <= config->size - (size_t)offset; +} + +static int flash_cc35xx_get_udma_status(void) +{ + uint32_t status; + + status = XIPGetUDMAIrqStatus(XIP_UDMA_SECURE_CHANNEL); + if (status != XIP_UDMA_JOB_IRQ_STATUS_DONE) { + return -EIO; + } + + return 0; } extern XMEMWFF3_HWAttrs XMEMWFF3_hwAttrs; @@ -121,7 +139,7 @@ __ramfunc static int flash_cc35xx_erase(const struct device *dev, off_t offset, const struct flash_cc35xx_config *config = dev->config; size_t erase_size = config->erase_size; mem_addr_t addr = flash_cc35xx_offset_to_phys_addr(dev, offset); - int ret; + int ret = 0; unsigned int key; if (offset % erase_size) { @@ -156,20 +174,56 @@ __ramfunc static int flash_cc35xx_erase(const struct device *dev, off_t offset, static int flash_cc35xx_write(const struct device *dev, off_t offset, const void *buf, size_t size) { const struct flash_cc35xx_config *config = dev->config; - void *addr = flash_cc35xx_offset_to_logic_addr(dev, offset); + const uint8_t *src = buf; + size_t remaining = size; + int ret = 0; + + if (!size) { + return 0; + } if (size % config->parameters->write_block_size) { return -EINVAL; } + if (!flash_cc35xx_is_range_valid(dev, offset, size)) { return -EINVAL; } + if (offset % config->parameters->write_block_size) { + return -EINVAL; + } + k_mutex_lock(&flash_cc35xx_mutex, K_FOREVER); - memcpy(addr, buf, size); + while (remaining) { + off_t chunk_offset = offset & ~(CC35XX_FLASH_WRITE_SIZE - 1); + size_t chunk_pos = offset - chunk_offset; + size_t chunk_len = MIN(remaining, CC35XX_FLASH_WRITE_SIZE - chunk_pos); + uint8_t *addr = flash_cc35xx_offset_to_logic_addr(dev, chunk_offset); + + if (chunk_pos != 0 || chunk_len != sizeof(flash_cc35xx_write_buf)) { + FlashRead((uint32_t *)addr, (uint32_t *)flash_cc35xx_write_buf, + sizeof(flash_cc35xx_write_buf)); + ret = flash_cc35xx_get_udma_status(); + if (ret) { + break; + } + } + memcpy(&flash_cc35xx_write_buf[chunk_pos], src, chunk_len); + FlashWrite((uint32_t *)flash_cc35xx_write_buf, (uint32_t *)addr, + sizeof(flash_cc35xx_write_buf)); + ret = flash_cc35xx_get_udma_status(); + if (ret) { + break; + } + + src += chunk_len; + offset += chunk_len; + remaining -= chunk_len; + } k_mutex_unlock(&flash_cc35xx_mutex); - return 0; + return ret; } static int flash_cc35xx_read(const struct device *dev, off_t offset, void *buf, size_t size) From 0da62113d3b6783f65cf8147f88ce4bb1478b231 Mon Sep 17 00:00:00 2001 From: Jakub Jarosinski Date: Mon, 1 Jun 2026 15:37:43 +0200 Subject: [PATCH 020/100] UPSTREAM-PEND: soc: ti: add CC35xxE variants Add CC3500E, CC3501E, CC3550E, and CC3551E SoC variants for the LP-EM-CC35X1 board. Model Wi-Fi, 5 GHz Wi-Fi, and Bluetooth capabilities through SoC feature symbols. Signed-off-by: Jakub Jarosinski --- boards/ti/lp_em_cc35x1/Kconfig.lp_em_cc35x1 | 5 ++- boards/ti/lp_em_cc35x1/board.yml | 3 ++ .../ti/lp_em_cc35x1/lp_em_cc35x1_cc3500e.dts | 3 ++ .../lp_em_cc35x1_cc3500e_defconfig | 18 ++++++++++ .../ti/lp_em_cc35x1/lp_em_cc35x1_cc3501e.dts | 3 ++ ...fconfig => lp_em_cc35x1_cc3501e_defconfig} | 2 +- .../ti/lp_em_cc35x1/lp_em_cc35x1_cc3550e.dts | 3 ++ .../lp_em_cc35x1_cc3550e_defconfig | 18 ++++++++++ .../ti/lp_em_cc35x1/lp_em_cc35x1_cc3551e.dts | 3 ++ .../ti/lp_em_cc35x1/lp_em_cc35x1_cc3551e.yaml | 33 +++++++++++++++++++ .../lp_em_cc35x1_cc3551e_defconfig | 18 ++++++++++ ...em_cc35x1.dts => lp_em_cc35x1_common.dtsi} | 0 .../cc35xxe/Kconfig.defconfig.cc3551e | 4 +-- soc/ti/simplelink/cc35xxe/Kconfig.soc | 32 ++++++++++++++++++ soc/ti/simplelink/soc.yml | 3 ++ 15 files changed, 144 insertions(+), 4 deletions(-) create mode 100644 boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3500e.dts create mode 100644 boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3500e_defconfig create mode 100644 boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3501e.dts rename boards/ti/lp_em_cc35x1/{lp_em_cc35x1_defconfig => lp_em_cc35x1_cc3501e_defconfig} (90%) create mode 100644 boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3550e.dts create mode 100644 boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3550e_defconfig create mode 100644 boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3551e.dts create mode 100644 boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3551e.yaml create mode 100644 boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3551e_defconfig rename boards/ti/lp_em_cc35x1/{lp_em_cc35x1.dts => lp_em_cc35x1_common.dtsi} (100%) diff --git a/boards/ti/lp_em_cc35x1/Kconfig.lp_em_cc35x1 b/boards/ti/lp_em_cc35x1/Kconfig.lp_em_cc35x1 index 2a79dec5ecff..6574430eca66 100644 --- a/boards/ti/lp_em_cc35x1/Kconfig.lp_em_cc35x1 +++ b/boards/ti/lp_em_cc35x1/Kconfig.lp_em_cc35x1 @@ -4,4 +4,7 @@ config BOARD_LP_EM_CC35X1 bool - select SOC_CC3551E + select SOC_CC3500E if BOARD_LP_EM_CC35X1_CC3500E + select SOC_CC3501E if BOARD_LP_EM_CC35X1_CC3501E + select SOC_CC3550E if BOARD_LP_EM_CC35X1_CC3550E + select SOC_CC3551E if BOARD_LP_EM_CC35X1_CC3551E diff --git a/boards/ti/lp_em_cc35x1/board.yml b/boards/ti/lp_em_cc35x1/board.yml index 2b3723b8885e..1ce99b67bcf0 100644 --- a/boards/ti/lp_em_cc35x1/board.yml +++ b/boards/ti/lp_em_cc35x1/board.yml @@ -3,4 +3,7 @@ board: full_name: CC35x1 LaunchPad vendor: ti socs: + - name: cc3500e + - name: cc3501e + - name: cc3550e - name: cc3551e diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3500e.dts b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3500e.dts new file mode 100644 index 000000000000..4c2647f98ef1 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3500e.dts @@ -0,0 +1,3 @@ +/dts-v1/; + +#include "lp_em_cc35x1_common.dtsi" diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3500e_defconfig b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3500e_defconfig new file mode 100644 index 000000000000..97551f745932 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3500e_defconfig @@ -0,0 +1,18 @@ +# +# Copyright (c) 2025-2026 Conclusive Engineering Sp. z o.o. +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_SHARED_MULTI_HEAP=y +CONFIG_THREAD_STACK_INFO=y +CONFIG_DYNAMIC_THREAD=y +CONFIG_TEST_RANDOM_GENERATOR=y +CONFIG_TIMER_RANDOM_GENERATOR=y + +CONFIG_GPIO=y + +CONFIG_SERIAL=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3501e.dts b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3501e.dts new file mode 100644 index 000000000000..4c2647f98ef1 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3501e.dts @@ -0,0 +1,3 @@ +/dts-v1/; + +#include "lp_em_cc35x1_common.dtsi" diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_defconfig b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3501e_defconfig similarity index 90% rename from boards/ti/lp_em_cc35x1/lp_em_cc35x1_defconfig rename to boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3501e_defconfig index bbaadbd81c49..85106161c86c 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_defconfig +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3501e_defconfig @@ -1,5 +1,5 @@ # -# Copyright (c) 2025 Conclusive Engineering Sp. z o.o. +# Copyright (c) 2026 Conclusive Engineering Sp. z o.o. # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3550e.dts b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3550e.dts new file mode 100644 index 000000000000..4c2647f98ef1 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3550e.dts @@ -0,0 +1,3 @@ +/dts-v1/; + +#include "lp_em_cc35x1_common.dtsi" diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3550e_defconfig b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3550e_defconfig new file mode 100644 index 000000000000..559cbc09d378 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3550e_defconfig @@ -0,0 +1,18 @@ +# +# Copyright (c) 2026 Conclusive Engineering Sp. z o.o. +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_SHARED_MULTI_HEAP=y +CONFIG_THREAD_STACK_INFO=y +CONFIG_DYNAMIC_THREAD=y +CONFIG_TEST_RANDOM_GENERATOR=y +CONFIG_TIMER_RANDOM_GENERATOR=y + +CONFIG_GPIO=y + +CONFIG_SERIAL=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3551e.dts b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3551e.dts new file mode 100644 index 000000000000..4c2647f98ef1 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3551e.dts @@ -0,0 +1,3 @@ +/dts-v1/; + +#include "lp_em_cc35x1_common.dtsi" diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3551e.yaml b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3551e.yaml new file mode 100644 index 000000000000..7fd9c1ea7f20 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3551e.yaml @@ -0,0 +1,33 @@ +identifier: lp_em_cc35x1/cc3551e +name: TI SimpleLink CC3551E LaunchPad +type: mcu +arch: arm +ram: 1024 +flash: 4096 +toolchain: + - zephyr + - gnuarmemb +supported: + - spi + - uart + - drivers + - flash + - nvs + - pinctrl + - gpio + - serial + - entropy + - counter + - watchdog + - netif:wifi + - rtc + - adc + - pwm + - userspace + - dma + - i2s + - can + - disk +testing: + default: true +vendor: ti diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3551e_defconfig b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3551e_defconfig new file mode 100644 index 000000000000..559cbc09d378 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3551e_defconfig @@ -0,0 +1,18 @@ +# +# Copyright (c) 2026 Conclusive Engineering Sp. z o.o. +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_SHARED_MULTI_HEAP=y +CONFIG_THREAD_STACK_INFO=y +CONFIG_DYNAMIC_THREAD=y +CONFIG_TEST_RANDOM_GENERATOR=y +CONFIG_TIMER_RANDOM_GENERATOR=y + +CONFIG_GPIO=y + +CONFIG_SERIAL=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi similarity index 100% rename from boards/ti/lp_em_cc35x1/lp_em_cc35x1.dts rename to boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi diff --git a/soc/ti/simplelink/cc35xxe/Kconfig.defconfig.cc3551e b/soc/ti/simplelink/cc35xxe/Kconfig.defconfig.cc3551e index 97a5907cbaac..986af0268f1e 100644 --- a/soc/ti/simplelink/cc35xxe/Kconfig.defconfig.cc3551e +++ b/soc/ti/simplelink/cc35xxe/Kconfig.defconfig.cc3551e @@ -2,7 +2,7 @@ # Texas Instruments SimpleLink CC3551E SoC # SPDX-License-Identifier: Apache-2.0 -if SOC_CC3551E +if SOC_SERIES_CC35XXE config SYS_CLOCK_HW_CYCLES_PER_SEC int @@ -29,4 +29,4 @@ config ROM_START_OFFSET hex default 0x0 -endif # SOC_CC3551E +endif # SOC_SERIES_CC35XXE diff --git a/soc/ti/simplelink/cc35xxe/Kconfig.soc b/soc/ti/simplelink/cc35xxe/Kconfig.soc index 9377098ff0a3..5cb65fa53eb4 100644 --- a/soc/ti/simplelink/cc35xxe/Kconfig.soc +++ b/soc/ti/simplelink/cc35xxe/Kconfig.soc @@ -8,9 +8,38 @@ config SOC_SERIES_CC35XXE help Enable support for TI SimpleLink CC35xxE SoCs +config SOC_CC3500E + bool + select SOC_SERIES_CC35XXE + select SOC_CC35XXE_HAS_WIFI + +config SOC_CC3501E + bool + select SOC_SERIES_CC35XXE + select SOC_CC35XXE_HAS_WIFI + select SOC_CC35XXE_HAS_BT + +config SOC_CC3550E + bool + select SOC_SERIES_CC35XXE + select SOC_CC35XXE_HAS_WIFI + select SOC_CC35XXE_HAS_WIFI_5GHZ + config SOC_CC3551E bool select SOC_SERIES_CC35XXE + select SOC_CC35XXE_HAS_WIFI + select SOC_CC35XXE_HAS_WIFI_5GHZ + select SOC_CC35XXE_HAS_BT + +config SOC_CC35XXE_HAS_WIFI + bool + +config SOC_CC35XXE_HAS_WIFI_5GHZ + bool + +config SOC_CC35XXE_HAS_BT + bool config SOC_SERIES string @@ -18,6 +47,9 @@ config SOC_SERIES config SOC string + default "cc3500e" if SOC_CC3500E + default "cc3501e" if SOC_CC3501E + default "cc3550e" if SOC_CC3550E default "cc3551e" if SOC_CC3551E config CC35XXE_SIGN_PRIVATE_KEY_FILE diff --git a/soc/ti/simplelink/soc.yml b/soc/ti/simplelink/soc.yml index 89488904a520..904b9e0eb25e 100644 --- a/soc/ti/simplelink/soc.yml +++ b/soc/ti/simplelink/soc.yml @@ -23,6 +23,9 @@ family: - name: cc3235sf - name: cc35xxe socs: + - name: cc3500e + - name: cc3501e + - name: cc3550e - name: cc3551e - name: msp432p4xx socs: From b98dbbcd6651e76e181b5c1eb7fc58baf4b3df1e Mon Sep 17 00:00:00 2001 From: Jakub Jarosinski Date: Wed, 10 Jun 2026 13:02:40 +0200 Subject: [PATCH 021/100] UPSTREAM-PEND: boards: ti: add CC35xx flash profiles Add selectable SimpleLink Toolbox flash profiles for supported CC35xx external flash devices. Signed-off-by: Jakub Jarosinski --- .../gd25lf32e/flash_disc_param_ext_mem.json | 99 ++++ .../gd25lf32e/flash_disc_param_otfde.json | 286 +++++++++++ .../gd25lf32e/flash_disc_param_xspi.json | 485 ++++++++++++++++++ .../gd25lf64e/flash_disc_param_ext_mem.json | 99 ++++ .../gd25lf64e/flash_disc_param_otfde.json | 286 +++++++++++ .../gd25lf64e/flash_disc_param_xspi.json | 485 ++++++++++++++++++ .../is25wj032f/flash_disc_param_ext_mem.json | 99 ++++ .../is25wj032f/flash_disc_param_otfde.json | 286 +++++++++++ .../is25wj032f/flash_disc_param_xspi.json | 485 ++++++++++++++++++ .../is25wj064f/flash_disc_param_ext_mem.json | 99 ++++ .../is25wj064f/flash_disc_param_otfde.json | 286 +++++++++++ .../is25wj064f/flash_disc_param_xspi.json | 485 ++++++++++++++++++ .../is25wj128f/flash_disc_param_ext_mem.json | 99 ++++ .../is25wj128f/flash_disc_param_otfde.json | 286 +++++++++++ .../is25wj128f/flash_disc_param_xspi.json | 485 ++++++++++++++++++ .../mx25u12843g/flash_disc_param_ext_mem.json | 99 ++++ .../mx25u12843g/flash_disc_param_otfde.json | 286 +++++++++++ .../mx25u12843g/flash_disc_param_xspi.json | 485 ++++++++++++++++++ .../mx25u3235f/flash_disc_param_ext_mem.json | 99 ++++ .../mx25u3235f/flash_disc_param_otfde.json | 286 +++++++++++ .../mx25u3235f/flash_disc_param_xspi.json | 485 ++++++++++++++++++ .../mx25u6435f/flash_disc_param_ext_mem.json | 99 ++++ .../mx25u6435f/flash_disc_param_otfde.json | 286 +++++++++++ .../mx25u6435f/flash_disc_param_xspi.json | 485 ++++++++++++++++++ .../py25q128la/flash_disc_param_ext_mem.json | 99 ++++ .../py25q128la/flash_disc_param_otfde.json | 286 +++++++++++ .../py25q128la/flash_disc_param_xspi.json | 485 ++++++++++++++++++ .../py25q256lc/flash_disc_param_ext_mem.json | 99 ++++ .../py25q256lc/flash_disc_param_otfde.json | 286 +++++++++++ .../py25q256lc/flash_disc_param_xspi.json | 485 ++++++++++++++++++ .../py25q32lb/flash_disc_param_ext_mem.json | 99 ++++ .../py25q32lb/flash_disc_param_otfde.json | 286 +++++++++++ .../py25q32lb/flash_disc_param_xspi.json | 485 ++++++++++++++++++ .../py25q64lb/flash_disc_param_ext_mem.json | 99 ++++ .../py25q64lb/flash_disc_param_otfde.json | 286 +++++++++++ .../py25q64lb/flash_disc_param_xspi.json | 485 ++++++++++++++++++ .../w25q12pw/flash_disc_param_ext_mem.json | 99 ++++ .../w25q12pw/flash_disc_param_otfde.json | 286 +++++++++++ .../flash/w25q12pw/flash_disc_param_xspi.json | 485 ++++++++++++++++++ .../w25q32jw/flash_disc_param_ext_mem.json | 99 ++++ .../w25q32jw/flash_disc_param_otfde.json | 286 +++++++++++ .../flash/w25q32jw/flash_disc_param_xspi.json | 485 ++++++++++++++++++ .../w25q33pw/flash_disc_param_ext_mem.json | 99 ++++ .../w25q33pw/flash_disc_param_otfde.json | 286 +++++++++++ .../flash/w25q33pw/flash_disc_param_xspi.json | 485 ++++++++++++++++++ .../w25q64jw/flash_disc_param_ext_mem.json | 99 ++++ .../w25q64jw/flash_disc_param_otfde.json | 286 +++++++++++ .../flash/w25q64jw/flash_disc_param_xspi.json | 485 ++++++++++++++++++ .../w25q64pw/flash_disc_param_ext_mem.json | 99 ++++ .../w25q64pw/flash_disc_param_otfde.json | 286 +++++++++++ .../flash/w25q64pw/flash_disc_param_xspi.json | 485 ++++++++++++++++++ boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml | 2 +- .../ti/lp_em_cc35x1/lp_em_cc35x1_8m.overlay | 67 +++ dts/arm/ti/cc35xxe.dtsi | 4 +- .../runners/simplelink_toolbox.py | 4 +- soc/ti/simplelink/cc35xxe/Kconfig.soc | 85 +++ soc/ti/simplelink/cc35xxe/toolbox.cmake | 34 +- 57 files changed, 14976 insertions(+), 10 deletions(-) create mode 100644 boards/ti/lp_em_cc35x1/config/flash/gd25lf32e/flash_disc_param_ext_mem.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/gd25lf32e/flash_disc_param_otfde.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/gd25lf32e/flash_disc_param_xspi.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/gd25lf64e/flash_disc_param_ext_mem.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/gd25lf64e/flash_disc_param_otfde.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/gd25lf64e/flash_disc_param_xspi.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/is25wj032f/flash_disc_param_ext_mem.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/is25wj032f/flash_disc_param_otfde.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/is25wj032f/flash_disc_param_xspi.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/is25wj064f/flash_disc_param_ext_mem.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/is25wj064f/flash_disc_param_otfde.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/is25wj064f/flash_disc_param_xspi.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/is25wj128f/flash_disc_param_ext_mem.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/is25wj128f/flash_disc_param_otfde.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/is25wj128f/flash_disc_param_xspi.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/mx25u12843g/flash_disc_param_ext_mem.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/mx25u12843g/flash_disc_param_otfde.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/mx25u12843g/flash_disc_param_xspi.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/mx25u3235f/flash_disc_param_ext_mem.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/mx25u3235f/flash_disc_param_otfde.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/mx25u3235f/flash_disc_param_xspi.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/mx25u6435f/flash_disc_param_ext_mem.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/mx25u6435f/flash_disc_param_otfde.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/mx25u6435f/flash_disc_param_xspi.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/py25q128la/flash_disc_param_ext_mem.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/py25q128la/flash_disc_param_otfde.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/py25q128la/flash_disc_param_xspi.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/py25q256lc/flash_disc_param_ext_mem.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/py25q256lc/flash_disc_param_otfde.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/py25q256lc/flash_disc_param_xspi.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/py25q32lb/flash_disc_param_ext_mem.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/py25q32lb/flash_disc_param_otfde.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/py25q32lb/flash_disc_param_xspi.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/py25q64lb/flash_disc_param_ext_mem.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/py25q64lb/flash_disc_param_otfde.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/py25q64lb/flash_disc_param_xspi.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/w25q12pw/flash_disc_param_ext_mem.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/w25q12pw/flash_disc_param_otfde.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/w25q12pw/flash_disc_param_xspi.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/w25q32jw/flash_disc_param_ext_mem.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/w25q32jw/flash_disc_param_otfde.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/w25q32jw/flash_disc_param_xspi.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/w25q33pw/flash_disc_param_ext_mem.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/w25q33pw/flash_disc_param_otfde.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/w25q33pw/flash_disc_param_xspi.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/w25q64jw/flash_disc_param_ext_mem.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/w25q64jw/flash_disc_param_otfde.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/w25q64jw/flash_disc_param_xspi.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/w25q64pw/flash_disc_param_ext_mem.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/w25q64pw/flash_disc_param_otfde.json create mode 100644 boards/ti/lp_em_cc35x1/config/flash/w25q64pw/flash_disc_param_xspi.json create mode 100644 boards/ti/lp_em_cc35x1/lp_em_cc35x1_8m.overlay diff --git a/boards/ti/lp_em_cc35x1/config/flash/gd25lf32e/flash_disc_param_ext_mem.json b/boards/ti/lp_em_cc35x1/config/flash/gd25lf32e/flash_disc_param_ext_mem.json new file mode 100644 index 000000000000..321810768be1 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/gd25lf32e/flash_disc_param_ext_mem.json @@ -0,0 +1,99 @@ +{ + "vendor_primary_sbl": true, + "ti_wsoc_primary_container": true, + "ti_wsoc_bl2_primary_container": true, + "nvs_enable": true, + "vendor_alternate_image": true, + "vendor_sbl_alternate_image": true, + "ti_bl_alternate_image": true, + "ti_wsoc_alternate_image": true, + "ti_wsoc_bl2_alternate_image": true, + "region_0": { + "mem_region_0_start_phy_address": 1069056, + "mem_region_0_end_phy_address": 4194303, + "region0_boot": false, + "region0_main_code": true, + "region0_nvs": false, + "region0_wsoc_code": false, + "region0_alternate_code": false + }, + "region_1": { + "mem_region_1_start_phy_address": 0, + "mem_region_1_end_phy_address": 1069055, + "region1_boot": true, + "region1_main_code": false, + "region1_nvs": true, + "region1_wsoc_code": true, + "region1_alternate_code": false + }, + "region_2": { + "mem_region_2_start_phy_address": 0, + "mem_region_2_end_phy_address": 0, + "region2_boot": false, + "region2_main_code": false, + "region2_nvs": false, + "region2_wsoc_code": false, + "region2_alternate_code": true + }, + "region_3": { + "mem_region_3_start_phy_address": 0, + "mem_region_3_end_phy_address": 0, + "region3_boot": false, + "region3_main_code": false, + "region3_nvs": false, + "region3_wsoc_code": false, + "region3_alternate_code": false + }, + "boot_region_conf": { + "boot_region_size": 0, + "boot_region_flash_disco_param_start_address": 0, + "boot_region_primary_ti_bl_start_phy_address": 12284, + "boot_region_primary_ti_bl_magic": 0, + "boot_region_primary_ti_bl_major": 0, + "boot_region_primary_ti_bl_minor": 0, + "boot_region_sec_ti_bl_start_phy_address": 430076, + "boot_region_sec_ti_bl_magic": 0, + "boot_region_sec_ti_bl_major": 0, + "boot_region_sec_ti_bl_minor": 0 + }, + "main_code_region_conf": { + "main_code_region_vendor_image_start_phy_address": 1073148, + "main_code_region_vendor_image_magic": 0, + "main_code_region_vendor_image_major": 0, + "main_code_region_vendor_image_minor": 0, + "main_code_region_sbl_start_phy_address": 0, + "main_code_region_sbl_magic": 0, + "main_code_region_sbl_major": 0, + "main_code_region_sbl_minor": 0 + }, + "alt_code_region_conf": { + "alt_code_region_vendor_image_start_phy_address": 4194304, + "alt_code_region_vendor_image_magic": 0, + "alt_code_region_vendor_image_major": 0, + "alt_code_region_vendor_image_minor": 0, + "alt_code_region_sbl_start_phy_address": 0, + "alt_code_region_sbl_magic": 0, + "alt_code_region_sbl_major": 0, + "alt_code_region_sbl_minor": 0 + }, + "nvs_code_region_conf": { + "nvs_start_phy_address": 892928, + "nvs_region_size": 176128, + "nvs_region_primary_wsoc_start_phy_address": 430076, + "nvs_region_primary_wsoc_magic": 0, + "nvs_region_primary_wsoc_major": 0, + "nvs_region_primary_wsoc_minor": 0, + "nvs_region_sec_wsoc_start_phy_address": 897020, + "nvs_region_sec_wsoc_magic": 0, + "nvs_region_sec_wsoc_major": 0, + "nvs_region_sec_wsoc_minor": 0, + "nvs_region_primary_wsoc_bl2_start_phy_address": 0, + "nvs_region_primary_wsoc_bl2_magic": 0, + "nvs_region_primary_wsoc_bl2_major": 0, + "nvs_region_primary_wsoc_bl2_minor": 0, + "nvs_region_sec_wsoc_bl2_start_phy_address": 0, + "nvs_region_sec_wsoc_bl2_magic": 0, + "nvs_region_sec_wsoc_bl2_major": 0, + "nvs_region_sec_wsoc_bl2_minor": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/gd25lf32e/flash_disc_param_otfde.json b/boards/ti/lp_em_cc35x1/config/flash/gd25lf32e/flash_disc_param_otfde.json new file mode 100644 index 000000000000..635e11319c5d --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/gd25lf32e/flash_disc_param_otfde.json @@ -0,0 +1,286 @@ +{ + "otfde_header": { + "name": "OTFDEWFF3", + "flash_only": true, + "ip_protection": false, + "regions_lock": false, + "regions_number": 4, + "flash_enabled": true + }, + "bl_conf": { + "host_boot_done_lock": true, + "host_peripherals_lock": true, + "icache_conf_lock": true, + "m33_mem_part_lock": true, + "memss_firewall_lock": true, + "dma_channel_owner_lock": true, + "otfde_region_lock": true, + "core_events_lock": true + }, + "otfde_general": { + "parameters": { + "mem_otfde_initial_delay": 10, + "otfde_global_watchdog_timer": 5 + }, + "events": { + "reset_evt_mask": false, + "reset_evt_suspend": false, + "sft_reset_evt_mask": false, + "sft_reset_evt_suspend": false, + "bypass_mode_evt_mask": false, + "bypass_mode_evt_suspend": false, + "debug_mode_evt_mask": false, + "debug_mode_evt_suspend": false, + "general_evt_mask": false, + "general_evt_suspend": false, + "xspi_data_path_evt_mask": false, + "xspi_data_path_evt_suspend": false, + "xspi_cnfg_path_evt_mask": false, + "xspi_cnfg_path_evt_suspend": false, + "xspi_service_interrupt_evt_mask": false, + "xspi_service_interrupt_evt_suspend": false, + "trans_device_disabled_evt_mask": false, + "trans_device_disabled_evt_suspend": false, + "trans_region_disabled_evt_mask": false, + "trans_region_disabled_evt_suspend": false, + "trans_region_params_conf_evt_mask": false, + "trans_region_params_conf_evt_suspend": false, + "trans_multiple_regions_mapped_evt_mask": false, + "trans_multiple_regions_mapped_evt_suspend": false, + "trans_address_not_32_bit_evt_mask": false, + "trans_address_not_32_bit_evt_suspend": false, + "trans_size_not_32_bit_evt_mask": false, + "trans_size_not_32_bit_evt_suspend": false, + "trans_burst_not_32_bit_evt_mask": false, + "trans_burst_not_32_bit_evt_suspend": false, + "region_read_write_def_evt_mask": false, + "region_read_write_def_evt_suspend": false, + "suspend_while_disabled_evt_mask": false, + "suspend_while_disabled_evt_suspend": false + } + }, + "regions_settings": { + "region_parameters_lock": { + "REGION_0_PARAMS_0": true, + "REGION_0_PARAMS_1": true, + "REGION_0_PARAMS_2": true, + "REGION_1_PARAMS_0": false, + "REGION_1_PARAMS_1": false, + "REGION_1_PARAMS_2": false, + "REGION_2_PARAMS_0": true, + "REGION_2_PARAMS_1": true, + "REGION_2_PARAMS_2": true, + "REGION_3_PARAMS_0": false, + "REGION_3_PARAMS_1": false, + "REGION_3_PARAMS_2": false + }, + "region_0_protection": { + "mem_region_0_enabled": true, + "mem_region_0_device_id": 0, + "mem_region_0_spi_write_enable": true, + "mem_region_0_spi_read_enable": true, + "mem_region_0_physical_offset": 261, + "mem_region_0_security_id_msb": 0, + "mem_region_0_start_address": 81920, + "mem_region_0_end_address": 82682, + "mem_region_0_security_id_lsb": 0, + "mem_otfde_region_0_write_lock_en": false, + "mem_otfde_region_0_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_1_protection": { + "mem_region_1_enabled": true, + "mem_region_1_device_id": 0, + "mem_region_1_spi_write_enable": true, + "mem_region_1_spi_read_enable": true, + "mem_region_1_physical_offset": 0, + "mem_region_1_security_id_msb": 0, + "mem_region_1_start_address": 655360, + "mem_region_1_end_address": 655620, + "mem_region_1_security_id_lsb": 0, + "mem_otfde_region_1_write_lock_en": false, + "mem_otfde_region_1_enc_dec_bypass": "Bypass" + }, + "region_2_protection": { + "mem_region_2_enabled": false, + "mem_region_2_device_id": 0, + "mem_region_2_spi_write_enable": true, + "mem_region_2_spi_read_enable": true, + "mem_region_2_physical_offset": 0, + "mem_region_2_security_id_msb": 0, + "mem_region_2_start_address": 1, + "mem_region_2_end_address": 0, + "mem_region_2_security_id_lsb": 0, + "mem_otfde_region_2_write_lock_en": false, + "mem_otfde_region_2_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_3_protection": { + "mem_region_3_enabled": false, + "mem_region_3_device_id": 1, + "mem_region_3_spi_write_enable": true, + "mem_region_3_spi_read_enable": true, + "mem_region_3_physical_offset": 0, + "mem_region_3_security_id_msb": 0, + "mem_region_3_start_address": 1, + "mem_region_3_end_address": 0, + "mem_region_3_security_id_lsb": 0, + "mem_otfde_region_3_write_lock_en": false, + "mem_otfde_region_3_enc_dec_bypass": "Bypass" + } + }, + "devices": { + "header": { + "flash_device_switch_conf": 1, + "ram_device_switch_conf": 1 + }, + "flash_switch": { + "flash_grant_sel": 0, + "flash_data_for_conf_0": 2181562505, + "flash_offset_bits_for_conf_0": 0, + "flash_stop_bit_for_conf_0": 0, + "flash_data_for_conf_1": 67248651, + "flash_offset_bits_for_conf_1": 1, + "flash_stop_bit_for_conf_1": 0, + "flash_data_for_conf_2": 139266, + "flash_offset_bits_for_conf_2": 2, + "flash_stop_bit_for_conf_2": 0, + "flash_data_for_conf_3": 1, + "flash_offset_bits_for_conf_3": 4, + "flash_stop_bit_for_conf_3": 0, + "flash_data_for_conf_4": 1076887634, + "flash_offset_bits_for_conf_4": 45, + "flash_stop_bit_for_conf_4": 0, + "flash_data_for_conf_5": 3224371282, + "flash_offset_bits_for_conf_5": 45, + "flash_stop_bit_for_conf_5": 0, + "flash_data_for_conf_6": 262149, + "flash_offset_bits_for_conf_6": 14, + "flash_stop_bit_for_conf_6": 0, + "flash_data_for_conf_7": 0, + "flash_offset_bits_for_conf_7": 44, + "flash_stop_bit_for_conf_7": 1, + "flash_data_for_conf_8": 0, + "flash_offset_bits_for_conf_8": 0, + "flash_stop_bit_for_conf_8": 1, + "flash_data_for_conf_9": 0, + "flash_offset_bits_for_conf_9": 0, + "flash_stop_bit_for_conf_9": 1, + "flash_data_for_conf_10": 0, + "flash_offset_bits_for_conf_10": 0, + "flash_stop_bit_for_conf_10": 1, + "flash_data_for_conf_11": 0, + "flash_offset_bits_for_conf_11": 0, + "flash_stop_bit_for_conf_11": 1, + "flash_data_for_conf_12": 0, + "flash_offset_bits_for_conf_12": 0, + "flash_stop_bit_for_conf_12": 1, + "flash_data_for_conf_13": 0, + "flash_offset_bits_for_conf_13": 0, + "flash_stop_bit_for_conf_13": 1, + "flash_data_for_conf_14": 0, + "flash_offset_bits_for_conf_14": 0, + "flash_stop_bit_for_conf_14": 1, + "flash_data_for_conf_15": 0, + "flash_offset_bits_for_conf_15": 0, + "flash_stop_bit_for_conf_15": 1, + "flash_data_for_conf_16": 0, + "flash_offset_bits_for_conf_16": 0, + "flash_stop_bit_for_conf_16": 1, + "flash_data_for_conf_17": 0, + "flash_offset_bits_for_conf_17": 0, + "flash_stop_bit_for_conf_17": 1, + "flash_data_for_conf_18": 0, + "flash_offset_bits_for_conf_18": 0, + "flash_stop_bit_for_conf_18": 1, + "flash_data_for_conf_19": 0, + "flash_offset_bits_for_conf_19": 0, + "flash_stop_bit_for_conf_19": 1, + "flash_data_for_conf_20": 0, + "flash_offset_bits_for_conf_20": 0, + "flash_stop_bit_for_conf_20": 1, + "flash_data_for_conf_21": 0, + "flash_offset_bits_for_conf_21": 0, + "flash_stop_bit_for_conf_21": 1, + "flash_data_for_conf_22": 0, + "flash_offset_bits_for_conf_22": 0, + "flash_stop_bit_for_conf_22": 1, + "flash_data_for_conf_23": 0, + "flash_offset_bits_for_conf_23": 0, + "flash_stop_bit_for_conf_23": 1 + }, + "ram_switch": { + "ram_grant_sel": 0, + "ram_data_for_conf_0": 2181562505, + "ram_offset_bits_for_conf_0": 0, + "ram_stop_bit_for_conf_0": 0, + "ram_data_for_conf_1": 67248651, + "ram_offset_bits_for_conf_1": 1, + "ram_stop_bit_for_conf_1": 0, + "ram_data_for_conf_2": 139266, + "ram_offset_bits_for_conf_2": 2, + "ram_stop_bit_for_conf_2": 0, + "ram_data_for_conf_3": 1, + "ram_offset_bits_for_conf_3": 4, + "ram_stop_bit_for_conf_3": 0, + "ram_data_for_conf_4": 1076887634, + "ram_offset_bits_for_conf_4": 45, + "ram_stop_bit_for_conf_4": 0, + "ram_data_for_conf_5": 3224371282, + "ram_offset_bits_for_conf_5": 45, + "ram_stop_bit_for_conf_5": 0, + "ram_data_for_conf_6": 262149, + "ram_offset_bits_for_conf_6": 14, + "ram_stop_bit_for_conf_6": 0, + "ram_data_for_conf_7": 0, + "ram_offset_bits_for_conf_7": 44, + "ram_stop_bit_for_conf_7": 1, + "ram_data_for_conf_8": 0, + "ram_offset_bits_for_conf_8": 0, + "ram_stop_bit_for_conf_8": 1, + "ram_data_for_conf_9": 0, + "ram_offset_bits_for_conf_9": 0, + "ram_stop_bit_for_conf_9": 1, + "ram_data_for_conf_10": 0, + "ram_offset_bits_for_conf_10": 0, + "ram_stop_bit_for_conf_10": 1, + "ram_data_for_conf_11": 0, + "ram_offset_bits_for_conf_11": 0, + "ram_stop_bit_for_conf_11": 1, + "ram_data_for_conf_12": 0, + "ram_offset_bits_for_conf_12": 0, + "ram_stop_bit_for_conf_12": 1, + "ram_data_for_conf_13": 0, + "ram_offset_bits_for_conf_13": 0, + "ram_stop_bit_for_conf_13": 1, + "ram_data_for_conf_14": 0, + "ram_offset_bits_for_conf_14": 0, + "ram_stop_bit_for_conf_14": 1, + "ram_data_for_conf_15": 0, + "ram_offset_bits_for_conf_15": 0, + "ram_stop_bit_for_conf_15": 1, + "ram_data_for_conf_16": 0, + "ram_offset_bits_for_conf_16": 0, + "ram_stop_bit_for_conf_16": 1, + "ram_data_for_conf_17": 0, + "ram_offset_bits_for_conf_17": 0, + "ram_stop_bit_for_conf_17": 1, + "ram_data_for_conf_18": 0, + "ram_offset_bits_for_conf_18": 0, + "ram_stop_bit_for_conf_18": 1, + "ram_data_for_conf_19": 0, + "ram_offset_bits_for_conf_19": 0, + "ram_stop_bit_for_conf_19": 1, + "ram_data_for_conf_20": 0, + "ram_offset_bits_for_conf_20": 0, + "ram_stop_bit_for_conf_20": 1, + "ram_data_for_conf_21": 0, + "ram_offset_bits_for_conf_21": 0, + "ram_stop_bit_for_conf_21": 1, + "ram_data_for_conf_22": 0, + "ram_offset_bits_for_conf_22": 0, + "ram_stop_bit_for_conf_22": 1, + "ram_data_for_conf_23": 0, + "ram_offset_bits_for_conf_23": 0, + "ram_stop_bit_for_conf_23": 1 + } + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/gd25lf32e/flash_disc_param_xspi.json b/boards/ti/lp_em_cc35x1/config/flash/gd25lf32e/flash_disc_param_xspi.json new file mode 100644 index 000000000000..8d7f8d001a98 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/gd25lf32e/flash_disc_param_xspi.json @@ -0,0 +1,485 @@ +{ + "xspi_header": { + "name": "xSPIWFF3", + "device": "CC3500", + "use_hardware": "GD25LF32E", + "use_case": "Quadro", + "dqs_support": 0, + "flash_only": 1, + "flash_separate_reset": 0, + "ram_separate_reset": true, + "clock_frequency": 80, + "qospi_clock_divider": 1, + "flash_device_character_conf": 0, + "ram_device_character_conf": 0, + "header_advanced": 0, + "phy_mode_enable": 1, + "pipeline_mode_enable": 1, + "loopback_support": "No", + "qspi_ref_clock": 80, + "spi_clock_freq": 20, + "spi_clock_divider": 1, + "flash_device_size": 4, + "flash_bytes_per_block": 16, + "flash_bytes_per_page": 256, + "flash_number_of_address_bytes": 3, + "flash_dual_opcode": 0, + "flash_jedec_manufacturer_id": 0, + "flash_jedec_device_id": 0, + "flash_name": "GD25LF32E", + "flash_page_size": 256, + "flash_sector_size": 4096, + "flash_cs_polarity": "ACTIVE_LOW", + "flash_sw_reset_type": "x1xxxx", + "ram_device_size": 4, + "ram_bytes_per_block": 16, + "ram_bytes_per_page": 256, + "ram_number_of_address_bytes": 3, + "ram_dual_opcode": 0, + "ram_jedec_manufacturer_id": 0, + "ram_jedec_device_id": 0, + "ram_name": "NO_PSRAM", + "ram_page_size": 256, + "ram_sector_size": 4096, + "ram_cs_polarity": "ACTIVE_LOW", + "ram_sw_reset_type": "x1xxxx", + "flash_write_operation_modes": "4S-4S-4S", + "flash_read_operation_modes": "4S-4S-4S", + "ram_write_operation_modes": "4S-4S-4S", + "ram_read_operation_modes": "4S-4S-4S", + "crc_enable": 0, + "enable_dtr": 0, + "enable_ahb_decoder": 0, + "enter_xip_mod_immediately": 0, + "enter_xip_mod_next_read": 0, + "ahb_address_remapping": 0, + "enable_dma": 0, + "select_decode": 0, + "legacy_ip_mode": 0, + "direct_access": 1 + }, + "xspi_pinmux": { + "xspi_clk_input": 44, + "xspi_clk_input_use_hw": 0, + "xspi_clk_input_mode": "Input", + "xspi_clk_input_pull": "None", + "xspi_clk_input_interrupt_trigger": "Low", + "xspi_clk_input_dont_conf": 0, + "xspi_clk_input_output_strength": "High", + "xspi_clk_input_initial_output_state": "High", + "xspi_clk": 24, + "xspi_clk_use_hw": "None", + "xspi_clk_mode": "Output", + "xspi_clk_pull": "None", + "xspi_clk_output_strength": "High", + "xspi_clk_initial_output_state": "High", + "xspi_clk_interrupt_trigger": "None", + "xspi_clk_dont_conf": 0, + "xspi_flash_cs": 20, + "xspi_flash_cs_use_hw": "None", + "xspi_flash_cs_mode": "Output", + "xspi_flash_cs_pull": "None", + "xspi_flash_cs_output_strength": "High", + "xspi_flash_cs_initial_output_state": "High", + "xspi_flash_cs_interrupt_trigger": "None", + "xspi_flash_cs_dont_conf": 0, + "xspi_data_0": 25, + "xspi_data_0_use_hw": "None", + "xspi_data_0_mode": "Input", + "xspi_data_0_pull": "None", + "xspi_data_0_output_strength": "High", + "xspi_data_0_initial_output_state": "High", + "xspi_data_0_interrupt_trigger": "Low", + "xspi_data_0_dont_conf": 0, + "xspi_data_1": 21, + "xspi_data_1_use_hw": "None", + "xspi_data_1_mode": "Input", + "xspi_data_1_pull": "None", + "xspi_data_1_output_strength": "High", + "xspi_data_1_initial_output_state": "High", + "xspi_data_1_interrupt_trigger": "Low", + "xspi_data_1_dont_conf": 0, + "xspi_data_2": 22, + "xspi_data_2_use_hw": "None", + "xspi_data_2_mode": "Input", + "xspi_data_2_pull": "None", + "xspi_data_2_output_strength": "High", + "xspi_data_2_initial_output_state": "High", + "xspi_data_2_interrupt_trigger": "Low", + "xspi_data_2_dont_conf": 0, + "xspi_data_3": 23, + "xspi_data_3_use_hw": "None", + "xspi_data_3_mode": "Input", + "xspi_data_3_pull": "None", + "xspi_data_3_output_strength": "High", + "xspi_data_3_initial_output_state": "High", + "xspi_data_3_interrupt_trigger": "Low", + "xspi_data_3_dont_conf": 0, + "xspi_data_4": 26, + "xspi_data_4_use_hw": "None", + "xspi_data_4_mode": "Input", + "xspi_data_4_pull": "None", + "xspi_data_4_output_strength": "High", + "xspi_data_4_initial_output_state": "High", + "xspi_data_4_interrupt_trigger": "None", + "xspi_data_4_dont_conf": 0, + "xspi_data_5": 27, + "xspi_data_5_use_hw": "None", + "xspi_data_5_mode": "Input", + "xspi_data_5_pull": "None", + "xspi_data_5_output_strength": "High", + "xspi_data_5_initial_output_state": "High", + "xspi_data_5_interrupt_trigger": "None", + "xspi_data_5_dont_conf": 0, + "xspi_data_6": 28, + "xspi_data_6_use_hw": "None", + "xspi_data_6_mode": "Input", + "xspi_data_6_pull": "None", + "xspi_data_6_output_strength": "High", + "xspi_data_6_initial_output_state": "High", + "xspi_data_6_interrupt_trigger": "None", + "xspi_data_6_dont_conf": 0, + "xspi_data_7": 29, + "xspi_data_7_use_hw": "None", + "xspi_data_7_mode": "Input", + "xspi_data_7_pull": "None", + "xspi_data_7_output_strength": "High", + "xspi_data_7_initial_output_state": "High", + "xspi_data_7_interrupt_trigger": "None", + "xspi_data_7_dont_conf": 0, + "xspi_reset_flash": 36, + "xspi_reset_flash_use_hw": "None", + "xspi_reset_flash_mode": "Output", + "xspi_reset_flash_pull": "None", + "xspi_reset_flash_output_strength": "High", + "xspi_reset_flash_initial_output_state": "High", + "xspi_reset_flash_interrupt_trigger": "None", + "xspi_reset_flash_dont_conf": 0, + "xspi_cs_ram": 3, + "xspi_cs_ram_use_hw": "None", + "xspi_cs_ram_mode": "Output", + "xspi_cs_ram_pull": "None", + "xspi_cs_ram_output_strength": "High", + "xspi_cs_ram_initial_output_state": "High", + "xspi_cs_ram_interrupt_trigger": "None", + "xspi_cs_ram_dont_conf": 0, + "xspi_dqs": 30, + "xspi_dqs_use_hw": "None", + "xspi_dqs_mode": "Input", + "xspi_dqs_pull": "None", + "xspi_dqs_output_strength": "High", + "xspi_dqs_initial_output_state": "High", + "xspi_dqs_interrupt_trigger": "None", + "xspi_dqs_dont_conf": 0, + "xspi_reset_ram": 2, + "xspi_reset_ram_use_hw": "None", + "xspi_reset_ram_mode": "Input", + "xspi_reset_ram_pull": "None", + "xspi_reset_ram_output_strength": "High", + "xspi_reset_ram_initial_output_state": "High", + "xspi_reset_ram_interrupt_trigger": "None", + "xspi_reset_ram_dont_conf": 0 + }, + "xspi_operations": { + "xspi_operations_clocks": { + "clock_phase": 0, + "clock_polarity": 0, + "spi_mode": "2'b00" + }, + "xspi_operations_chip_select": { + "csda": 2, + "csdads": 0, + "cseot": 4, + "cssot": 1 + }, + "xspi_operations_reset": { + "flash_jedec_reset": 0, + "ram_jedec_reset": 0, + "flash_treset": 20, + "ram_treset": 20 + }, + "xspi_phy_operations": { + "flash_rx_dll_bypass_bit": 0, + "flash_dll_tx_delay": 22, + "flash_dll_rx_delay": 34, + "ram_rx_dll_bypass_bit": 0, + "ram_dll_tx_delay": 22, + "ram_dll_rx_delay": 34 + }, + "xspi_read_operations": { + "flash_dummy_rd_cycles": 4, + "flash_read_opcode": 11, + "suppl_flash_read_opcode": 0, + "ram_dummy_rd_cycles": 4, + "ram_read_opcode": 11, + "suppl_ram_read_opcode": 0, + "flash_non_cont_read_enable": 0, + "flash_max_read_jobs": 256, + "ram_non_cont_read_enable": 0, + "ram_max_read_jobs": 256, + "rww_en": 0, + "device_size": 4, + "number_of_banks": 1, + "bank_size": 4, + "mode_bit_enable": 0 + }, + "xspi_write_operations": { + "flash_address_and_data": { + "flash_dummy_wr_cycles": 0 + }, + "flash_command": { + "flash_write_opcode": 2, + "suppl_flash_write_opcode": 0 + }, + "ram_address_and_data": { + "ram_dummy_wr_cycles": 0 + }, + "ram_command": { + "ram_write_opcode": 2, + "suppl_ram_write_opcode": 0 + }, + "write_to_buffer": { + "flash_write_to_buffer_support": 0, + "ram_write_to_buffer_support": 0 + }, + "non_continuous_write": { + "flash_non_cont_write_enable": 0, + "flash_max_write_jobs": 64, + "ram_non_cont_write_enable": 0, + "ram_max_write_jobs": 0 + }, + "flash_program_operation": { + "flash_min_program_size": "256 B", + "flash_program_opcode": 2, + "suppl_flash_program_opcode": 0, + "flash_maximum_program_time_limit": 1600 + }, + "flash_erase_operation": { + "flash_min_erase_size": "4 kB", + "flash_erase_opcode": 32, + "suppl_flash_erase_opcode": 0, + "flash_maximum_erase_time_limit": 4095 + }, + "flash_erase_conf": { + "flash_block_erase_opcode": 0, + "suppl_block_flash_erase_opcode": 0, + "flash_sector_erase_opcode": 0, + "suppl_sector_flash_erase_opcode": 0, + "flash_chip_erase_opcode": 0, + "suppl_chip_flash_erase_opcode": 0 + }, + "ram_program_operation": { + "ram_min_program_size": "256 B", + "ram_program_opcode": 2, + "suppl_ram_program_opcode": 0, + "ram_maximum_program_time_limit": 1600 + }, + "ram_erase_conf": { + "ram_block_erase_opcode": 0, + "suppl_block_ram_erase_opcode": 0, + "ram_sector_erase_opcode": 0, + "suppl_sector_ram_erase_opcode": 0, + "ram_chip_erase_opcode": 0, + "suppl_chip_ram_erase_opcode": 0 + }, + "flash_buffer_support": { + "flash_pre_write_sequence": 0, + "flash_post_write_sequence": 0, + "flash_write_protection_timer_en": 0, + "flash_write_buffer_timer_mode": 16, + "flash_write_buffer_timer_range": 0, + "flash_service_interrupt_criteria": 0 + }, + "ram_buffer_support": { + "ram_pre_write_sequence": 0, + "ram_post_write_sequence": 0, + "ram_write_protection_timer_en": 0, + "ram_write_buffer_timer_mode": 16, + "ram_write_buffer_timer_range": 0, + "ram_service_interrupt_criteria": 0 + }, + "flash_pre_write_conf": { + "flash_pre_write_job_done_grant_sel": 0, + "data_for_flash_pre_write_conf_0": 0, + "offset_bits_for_flash_pre_write_conf_0": 0, + "stop_bit_for_flash_pre_write_conf_0": 1, + "data_for_flash_pre_write_conf_1": 0, + "offset_bits_for_flash_pre_write_conf_1": 0 + }, + "flash_post_write_conf": { + "flash_post_write_job_done_grant_sel": 0, + "data_for_flash_post_write_conf_0": 0, + "offset_bits_for_flash_post_write_conf_0": 0, + "stop_bit_for_flash_post_write_conf_0": 1, + "data_for_flash_post_write_conf_1": 0, + "offset_bits_for_flash_post_write_conf_1": 0 + }, + "ram_pre_write_conf": { + "ram_pre_write_job_done_grant_sel": 0, + "data_for_ram_pre_write_conf_0": 0, + "offset_bits_for_ram_pre_write_conf_0": 0, + "stop_bit_for_ram_pre_write_conf_0": 1, + "data_for_ram_pre_write_conf_1": 0, + "offset_bits_for_ram_pre_write_conf_1": 0 + }, + "ram_post_write_conf": { + "ram_post_write_job_done_grant_sel": 0, + "data_for_ram_post_write_conf_0": 0, + "offset_bits_for_ram_post_write_conf_0": 0, + "stop_bit_for_ram_post_write_conf_0": 1, + "data_for_ram_post_write_conf_1": 0, + "offset_bits_for_ram_post_write_conf_1": 0 + } + }, + "xspi_capture_operations": { + "read_data_capture": { + "flash_delay_transmitted_data": 0, + "flash_loopback_clock": 0, + "flash_bypass_adapted_loopback": 1, + "flash_sample_edge_sel": 0, + "ram_delay_transmitted_data": 0, + "ram_loopback_clock": 0, + "ram_bypass_adapted_loopback": 1, + "ram_sample_edge_sel": 0 + }, + "delays": { + "flash_full_half_cycle_delay": 0, + "flash_dll_bypass_mode": 1, + "flash_phase_detect_sel": 0, + "flash_dll_lock_num": 0, + "flash_dll_start_point": 0, + "flash_loopback_clock": 0, + "ram_full_half_cycle_delay": 0, + "ram_dll_bypass_mode": 1, + "ram_phase_detect_sel": 0, + "ram_dll_lock_num": 0, + "ram_dll_start_point": 0, + "ram_loopback_clock": 0 + }, + "operation_modes": { + "flash_sfdp_support": 0, + "ram_sfdp_support": 0, + "flash_pm_support": 0, + "ram_pm_support": 0, + "flash_sfdp_opcode": 0, + "suppl_flash_sfdp_opcode": 0, + "ram_sfdp_opcode": 0, + "suppl_ram_sfdp_opcode": 0, + "flash_enter_dpd_opcode": 185, + "suppl_flash_enter_dpd_opcode": 0, + "flash_exit_dpd_opcode": 171, + "suppl_flash_exit_dpd_opcode": 0, + "ram_enter_dpd_opcode": 185, + "suppl_ram_enter_dpd_opcode": 0, + "ram_exit_dpd_opcode": 171, + "suppl_ram_exit_dpd_opcode": 0, + "flash_quad_enable_opcode": 56, + "suppl_flash_quad_enable_opcode": 0, + "flash_quad_disable_opcode": 255, + "suppl_flash_quad_disable_opcode": 0, + "flash_octal_enable_opcode": 0, + "suppl_flash_octal_enable_opcode": 0, + "flash_octal_disable_opcode": 0, + "suppl_flash_octal_disable_opcode": 0, + "ram_quad_enable_opcode": 56, + "suppl_ram_quad_enable_opcode": 0, + "ram_quad_disable_opcode": 255, + "suppl_ram_quad_disable_opcode": 0, + "ram_octal_enable_opcode": 0, + "suppl_ram_octal_enable_opcode": 0, + "ram_octal_disable_opcode": 0, + "suppl_ram_octal_disable_opcode": 0 + } + } + }, + "external_memory_reporting": { + "header": { + "flash_auto_polling_enable": 1, + "flash_wel_enable": 1, + "flash_write_protect_enable": 0, + "flash_alternate_polling_conf_enable": 0, + "ram_auto_polling_enable": 1, + "ram_wel_enable": 1, + "ram_write_protect_enable": 0, + "ram_alternate_polling_conf_enable": 0 + }, + "flash_auto_polling": { + "flash_polling_repetition_delay": 0, + "flash_polling_count": 4, + "flash_enable_polling_expiration": 0, + "flash_polling_polarity": 0, + "flash_polling_address_phase_enable": 0, + "flash_polling_bit_index": 0, + "flash_numbers_poll_cycles": 65535, + "flash_dummy_autopoll_cycles": 0 + }, + "ram_auto_polling": { + "ram_polling_repetition_delay": 0, + "ram_polling_count": 4, + "ram_enable_polling_expiration": 0, + "ram_polling_polarity": 0, + "ram_polling_address_phase_enable": 0, + "ram_polling_bit_index": 0, + "ram_numbers_poll_cycles": 65535, + "ram_dummy_autopoll_cycles": 0 + }, + "flash_polling_command": { + "flash_polling_opcode": 5, + "suppl_flash_polling_opcode": 0 + }, + "ram_polling_command": { + "ram_polling_opcode": 5, + "suppl_ram_polling_opcode": 0 + }, + "flash_alternate_polling": { + "flash_polling_resp_count": 1023, + "flash_polling_iterations": 1, + "flash_polling_enabled": 0, + "flash_polling_disabled": 0, + "flash_grant_sel": 0, + "flash_data_for_enable_poling_conf_0": 0, + "flash_offset_bits_for_enable_poling_conf_0": 0, + "flash_stop_bit_for_enable_poling_conf_0": 1, + "flash_data_for_enable_poling_conf_1": 0, + "flash_offset_bits_for_enable_poling_conf_1": 0, + "flash_stop_bit_for_enable_poling_conf_1": 1, + "flash_data_for_disable_poling_conf_0": 0, + "flash_offset_bits_for_disable_poling_conf_0": 0, + "flash_stop_bit_for_disable_poling_conf_0": 1, + "flash_data_for_disable_poling_conf_1": 0, + "flash_offset_bits_for_disable_poling_conf_1": 0, + "flash_stop_bit_for_disable_poling_conf_1": 1 + }, + "ram_alternate_polling": { + "ram_polling_resp_count": 1023, + "ram_polling_iterations": 1, + "ram_polling_enabled": 0, + "ram_polling_disabled": 0, + "ram_grant_sel": 0, + "ram_data_for_enable_poling_conf_0": 0, + "ram_offset_bits_for_enable_poling_conf_0": 0, + "ram_stop_bit_for_enable_poling_conf_0": 1, + "ram_data_for_enable_poling_conf_1": 0, + "ram_offset_bits_for_enable_poling_conf_1": 0, + "ram_stop_bit_for_enable_poling_conf_1": 1, + "ram_data_for_disable_poling_conf_0": 0, + "ram_offset_bits_for_disable_poling_conf_0": 0, + "ram_stop_bit_for_disable_poling_conf_0": 1, + "ram_data_for_disable_poling_conf_1": 0, + "ram_offset_bits_for_disable_poling_conf_1": 0, + "ram_stop_bit_for_disable_poling_conf_1": 1 + }, + "flash_wel_command": { + "flash_wel_opcode": 6, + "suppl_flash_wel_opcode": 0 + }, + "ram_wel_command": { + "ram_wel_opcode": 6, + "suppl_ram_wel_opcode": 0 + } + }, + "event": { + "host_nvic_irq": 0, + "core_10_mux_sel": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/gd25lf64e/flash_disc_param_ext_mem.json b/boards/ti/lp_em_cc35x1/config/flash/gd25lf64e/flash_disc_param_ext_mem.json new file mode 100644 index 000000000000..6585853ccd5e --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/gd25lf64e/flash_disc_param_ext_mem.json @@ -0,0 +1,99 @@ +{ + "vendor_primary_sbl": true, + "ti_wsoc_primary_container": true, + "ti_wsoc_bl2_primary_container": true, + "nvs_enable": true, + "vendor_alternate_image": true, + "vendor_sbl_alternate_image": true, + "ti_bl_alternate_image": true, + "ti_wsoc_alternate_image": true, + "ti_wsoc_bl2_alternate_image": true, + "region_0": { + "mem_region_0_start_phy_address": 2867200, + "mem_region_0_end_phy_address": 5627903, + "region0_boot": false, + "region0_main_code": true, + "region0_nvs": false, + "region0_wsoc_code": false, + "region0_alternate_code": false + }, + "region_1": { + "mem_region_1_start_phy_address": 0, + "mem_region_1_end_phy_address": 2867199, + "region1_boot": true, + "region1_main_code": false, + "region1_nvs": true, + "region1_wsoc_code": true, + "region1_alternate_code": false + }, + "region_2": { + "mem_region_2_start_phy_address": 5627904, + "mem_region_2_end_phy_address": 8388607, + "region2_boot": false, + "region2_main_code": false, + "region2_nvs": false, + "region2_wsoc_code": false, + "region2_alternate_code": true + }, + "region_3": { + "mem_region_3_start_phy_address": 0, + "mem_region_3_end_phy_address": 0, + "region3_boot": false, + "region3_main_code": false, + "region3_nvs": false, + "region3_wsoc_code": false, + "region3_alternate_code": false + }, + "boot_region_conf": { + "boot_region_size": 0, + "boot_region_flash_disco_param_start_address": 0, + "boot_region_primary_ti_bl_start_phy_address": 12284, + "boot_region_primary_ti_bl_magic": 0, + "boot_region_primary_ti_bl_major": 0, + "boot_region_primary_ti_bl_minor": 0, + "boot_region_sec_ti_bl_start_phy_address": 430076, + "boot_region_sec_ti_bl_magic": 0, + "boot_region_sec_ti_bl_major": 0, + "boot_region_sec_ti_bl_minor": 0 + }, + "main_code_region_conf": { + "main_code_region_vendor_image_start_phy_address": 2871292, + "main_code_region_vendor_image_magic": 0, + "main_code_region_vendor_image_major": 0, + "main_code_region_vendor_image_minor": 0, + "main_code_region_sbl_start_phy_address": 0, + "main_code_region_sbl_magic": 0, + "main_code_region_sbl_major": 0, + "main_code_region_sbl_minor": 0 + }, + "alt_code_region_conf": { + "alt_code_region_vendor_image_start_phy_address": 5631996, + "alt_code_region_vendor_image_magic": 0, + "alt_code_region_vendor_image_major": 0, + "alt_code_region_vendor_image_minor": 0, + "alt_code_region_sbl_start_phy_address": 0, + "alt_code_region_sbl_magic": 0, + "alt_code_region_sbl_major": 0, + "alt_code_region_sbl_minor": 0 + }, + "nvs_code_region_conf": { + "nvs_start_phy_address": 1777664, + "nvs_region_size": 1089536, + "nvs_region_primary_wsoc_start_phy_address": 847868, + "nvs_region_primary_wsoc_magic": 0, + "nvs_region_primary_wsoc_major": 0, + "nvs_region_primary_wsoc_minor": 0, + "nvs_region_sec_wsoc_start_phy_address": 1314812, + "nvs_region_sec_wsoc_magic": 0, + "nvs_region_sec_wsoc_major": 0, + "nvs_region_sec_wsoc_minor": 0, + "nvs_region_primary_wsoc_bl2_start_phy_address": 0, + "nvs_region_primary_wsoc_bl2_magic": 0, + "nvs_region_primary_wsoc_bl2_major": 0, + "nvs_region_primary_wsoc_bl2_minor": 0, + "nvs_region_sec_wsoc_bl2_start_phy_address": 0, + "nvs_region_sec_wsoc_bl2_magic": 0, + "nvs_region_sec_wsoc_bl2_major": 0, + "nvs_region_sec_wsoc_bl2_minor": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/gd25lf64e/flash_disc_param_otfde.json b/boards/ti/lp_em_cc35x1/config/flash/gd25lf64e/flash_disc_param_otfde.json new file mode 100644 index 000000000000..22a24d3d5430 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/gd25lf64e/flash_disc_param_otfde.json @@ -0,0 +1,286 @@ +{ + "otfde_header": { + "name": "OTFDEWFF3", + "flash_only": true, + "ip_protection": false, + "regions_lock": false, + "regions_number": 4, + "flash_enabled": true + }, + "bl_conf": { + "host_boot_done_lock": true, + "host_peripherals_lock": true, + "icache_conf_lock": true, + "m33_mem_part_lock": true, + "memss_firewall_lock": true, + "dma_channel_owner_lock": true, + "otfde_region_lock": true, + "core_events_lock": true + }, + "otfde_general": { + "parameters": { + "mem_otfde_initial_delay": 10, + "otfde_global_watchdog_timer": 5 + }, + "events": { + "reset_evt_mask": false, + "reset_evt_suspend": false, + "sft_reset_evt_mask": false, + "sft_reset_evt_suspend": false, + "bypass_mode_evt_mask": false, + "bypass_mode_evt_suspend": false, + "debug_mode_evt_mask": false, + "debug_mode_evt_suspend": false, + "general_evt_mask": false, + "general_evt_suspend": false, + "xspi_data_path_evt_mask": false, + "xspi_data_path_evt_suspend": false, + "xspi_cnfg_path_evt_mask": false, + "xspi_cnfg_path_evt_suspend": false, + "xspi_service_interrupt_evt_mask": false, + "xspi_service_interrupt_evt_suspend": false, + "trans_device_disabled_evt_mask": false, + "trans_device_disabled_evt_suspend": false, + "trans_region_disabled_evt_mask": false, + "trans_region_disabled_evt_suspend": false, + "trans_region_params_conf_evt_mask": false, + "trans_region_params_conf_evt_suspend": false, + "trans_multiple_regions_mapped_evt_mask": false, + "trans_multiple_regions_mapped_evt_suspend": false, + "trans_address_not_32_bit_evt_mask": false, + "trans_address_not_32_bit_evt_suspend": false, + "trans_size_not_32_bit_evt_mask": false, + "trans_size_not_32_bit_evt_suspend": false, + "trans_burst_not_32_bit_evt_mask": false, + "trans_burst_not_32_bit_evt_suspend": false, + "region_read_write_def_evt_mask": false, + "region_read_write_def_evt_suspend": false, + "suspend_while_disabled_evt_mask": false, + "suspend_while_disabled_evt_suspend": false + } + }, + "regions_settings": { + "region_parameters_lock": { + "REGION_0_PARAMS_0": true, + "REGION_0_PARAMS_1": true, + "REGION_0_PARAMS_2": true, + "REGION_1_PARAMS_0": false, + "REGION_1_PARAMS_1": false, + "REGION_1_PARAMS_2": false, + "REGION_2_PARAMS_0": true, + "REGION_2_PARAMS_1": true, + "REGION_2_PARAMS_2": true, + "REGION_3_PARAMS_0": false, + "REGION_3_PARAMS_1": false, + "REGION_3_PARAMS_2": false + }, + "region_0_protection": { + "mem_region_0_enabled": true, + "mem_region_0_device_id": 0, + "mem_region_0_spi_write_enable": true, + "mem_region_0_spi_read_enable": true, + "mem_region_0_physical_offset": 700, + "mem_region_0_security_id_msb": 0, + "mem_region_0_start_address": 81920, + "mem_region_0_end_address": 82593, + "mem_region_0_security_id_lsb": 0, + "mem_otfde_region_0_write_lock_en": false, + "mem_otfde_region_0_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_1_protection": { + "mem_region_1_enabled": true, + "mem_region_1_device_id": 0, + "mem_region_1_spi_write_enable": true, + "mem_region_1_spi_read_enable": true, + "mem_region_1_physical_offset": 0, + "mem_region_1_security_id_msb": 0, + "mem_region_1_start_address": 655360, + "mem_region_1_end_address": 656059, + "mem_region_1_security_id_lsb": 0, + "mem_otfde_region_1_write_lock_en": false, + "mem_otfde_region_1_enc_dec_bypass": "Bypass" + }, + "region_2_protection": { + "mem_region_2_enabled": true, + "mem_region_2_device_id": 0, + "mem_region_2_spi_write_enable": true, + "mem_region_2_spi_read_enable": true, + "mem_region_2_physical_offset": 1374, + "mem_region_2_security_id_msb": 0, + "mem_region_2_start_address": 671744, + "mem_region_2_end_address": 672417, + "mem_region_2_security_id_lsb": 0, + "mem_otfde_region_2_write_lock_en": false, + "mem_otfde_region_2_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_3_protection": { + "mem_region_3_enabled": false, + "mem_region_3_device_id": 1, + "mem_region_3_spi_write_enable": true, + "mem_region_3_spi_read_enable": true, + "mem_region_3_physical_offset": 0, + "mem_region_3_security_id_msb": 0, + "mem_region_3_start_address": 1, + "mem_region_3_end_address": 0, + "mem_region_3_security_id_lsb": 0, + "mem_otfde_region_3_write_lock_en": false, + "mem_otfde_region_3_enc_dec_bypass": "Bypass" + } + }, + "devices": { + "header": { + "flash_device_switch_conf": 1, + "ram_device_switch_conf": 1 + }, + "flash_switch": { + "flash_grant_sel": 0, + "flash_data_for_conf_0": 2181562505, + "flash_offset_bits_for_conf_0": 0, + "flash_stop_bit_for_conf_0": 0, + "flash_data_for_conf_1": 67248651, + "flash_offset_bits_for_conf_1": 1, + "flash_stop_bit_for_conf_1": 0, + "flash_data_for_conf_2": 139266, + "flash_offset_bits_for_conf_2": 2, + "flash_stop_bit_for_conf_2": 0, + "flash_data_for_conf_3": 1, + "flash_offset_bits_for_conf_3": 4, + "flash_stop_bit_for_conf_3": 0, + "flash_data_for_conf_4": 1076887634, + "flash_offset_bits_for_conf_4": 45, + "flash_stop_bit_for_conf_4": 0, + "flash_data_for_conf_5": 3224371282, + "flash_offset_bits_for_conf_5": 45, + "flash_stop_bit_for_conf_5": 0, + "flash_data_for_conf_6": 262149, + "flash_offset_bits_for_conf_6": 14, + "flash_stop_bit_for_conf_6": 0, + "flash_data_for_conf_7": 0, + "flash_offset_bits_for_conf_7": 44, + "flash_stop_bit_for_conf_7": 1, + "flash_data_for_conf_8": 0, + "flash_offset_bits_for_conf_8": 0, + "flash_stop_bit_for_conf_8": 1, + "flash_data_for_conf_9": 0, + "flash_offset_bits_for_conf_9": 0, + "flash_stop_bit_for_conf_9": 1, + "flash_data_for_conf_10": 0, + "flash_offset_bits_for_conf_10": 0, + "flash_stop_bit_for_conf_10": 1, + "flash_data_for_conf_11": 0, + "flash_offset_bits_for_conf_11": 0, + "flash_stop_bit_for_conf_11": 1, + "flash_data_for_conf_12": 0, + "flash_offset_bits_for_conf_12": 0, + "flash_stop_bit_for_conf_12": 1, + "flash_data_for_conf_13": 0, + "flash_offset_bits_for_conf_13": 0, + "flash_stop_bit_for_conf_13": 1, + "flash_data_for_conf_14": 0, + "flash_offset_bits_for_conf_14": 0, + "flash_stop_bit_for_conf_14": 1, + "flash_data_for_conf_15": 0, + "flash_offset_bits_for_conf_15": 0, + "flash_stop_bit_for_conf_15": 1, + "flash_data_for_conf_16": 0, + "flash_offset_bits_for_conf_16": 0, + "flash_stop_bit_for_conf_16": 1, + "flash_data_for_conf_17": 0, + "flash_offset_bits_for_conf_17": 0, + "flash_stop_bit_for_conf_17": 1, + "flash_data_for_conf_18": 0, + "flash_offset_bits_for_conf_18": 0, + "flash_stop_bit_for_conf_18": 1, + "flash_data_for_conf_19": 0, + "flash_offset_bits_for_conf_19": 0, + "flash_stop_bit_for_conf_19": 1, + "flash_data_for_conf_20": 0, + "flash_offset_bits_for_conf_20": 0, + "flash_stop_bit_for_conf_20": 1, + "flash_data_for_conf_21": 0, + "flash_offset_bits_for_conf_21": 0, + "flash_stop_bit_for_conf_21": 1, + "flash_data_for_conf_22": 0, + "flash_offset_bits_for_conf_22": 0, + "flash_stop_bit_for_conf_22": 1, + "flash_data_for_conf_23": 0, + "flash_offset_bits_for_conf_23": 0, + "flash_stop_bit_for_conf_23": 1 + }, + "ram_switch": { + "ram_grant_sel": 0, + "ram_data_for_conf_0": 2181562505, + "ram_offset_bits_for_conf_0": 0, + "ram_stop_bit_for_conf_0": 0, + "ram_data_for_conf_1": 67248651, + "ram_offset_bits_for_conf_1": 1, + "ram_stop_bit_for_conf_1": 0, + "ram_data_for_conf_2": 139266, + "ram_offset_bits_for_conf_2": 2, + "ram_stop_bit_for_conf_2": 0, + "ram_data_for_conf_3": 1, + "ram_offset_bits_for_conf_3": 4, + "ram_stop_bit_for_conf_3": 0, + "ram_data_for_conf_4": 1076887634, + "ram_offset_bits_for_conf_4": 45, + "ram_stop_bit_for_conf_4": 0, + "ram_data_for_conf_5": 3224371282, + "ram_offset_bits_for_conf_5": 45, + "ram_stop_bit_for_conf_5": 0, + "ram_data_for_conf_6": 262149, + "ram_offset_bits_for_conf_6": 14, + "ram_stop_bit_for_conf_6": 0, + "ram_data_for_conf_7": 0, + "ram_offset_bits_for_conf_7": 44, + "ram_stop_bit_for_conf_7": 1, + "ram_data_for_conf_8": 0, + "ram_offset_bits_for_conf_8": 0, + "ram_stop_bit_for_conf_8": 1, + "ram_data_for_conf_9": 0, + "ram_offset_bits_for_conf_9": 0, + "ram_stop_bit_for_conf_9": 1, + "ram_data_for_conf_10": 0, + "ram_offset_bits_for_conf_10": 0, + "ram_stop_bit_for_conf_10": 1, + "ram_data_for_conf_11": 0, + "ram_offset_bits_for_conf_11": 0, + "ram_stop_bit_for_conf_11": 1, + "ram_data_for_conf_12": 0, + "ram_offset_bits_for_conf_12": 0, + "ram_stop_bit_for_conf_12": 1, + "ram_data_for_conf_13": 0, + "ram_offset_bits_for_conf_13": 0, + "ram_stop_bit_for_conf_13": 1, + "ram_data_for_conf_14": 0, + "ram_offset_bits_for_conf_14": 0, + "ram_stop_bit_for_conf_14": 1, + "ram_data_for_conf_15": 0, + "ram_offset_bits_for_conf_15": 0, + "ram_stop_bit_for_conf_15": 1, + "ram_data_for_conf_16": 0, + "ram_offset_bits_for_conf_16": 0, + "ram_stop_bit_for_conf_16": 1, + "ram_data_for_conf_17": 0, + "ram_offset_bits_for_conf_17": 0, + "ram_stop_bit_for_conf_17": 1, + "ram_data_for_conf_18": 0, + "ram_offset_bits_for_conf_18": 0, + "ram_stop_bit_for_conf_18": 1, + "ram_data_for_conf_19": 0, + "ram_offset_bits_for_conf_19": 0, + "ram_stop_bit_for_conf_19": 1, + "ram_data_for_conf_20": 0, + "ram_offset_bits_for_conf_20": 0, + "ram_stop_bit_for_conf_20": 1, + "ram_data_for_conf_21": 0, + "ram_offset_bits_for_conf_21": 0, + "ram_stop_bit_for_conf_21": 1, + "ram_data_for_conf_22": 0, + "ram_offset_bits_for_conf_22": 0, + "ram_stop_bit_for_conf_22": 1, + "ram_data_for_conf_23": 0, + "ram_offset_bits_for_conf_23": 0, + "ram_stop_bit_for_conf_23": 1 + } + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/gd25lf64e/flash_disc_param_xspi.json b/boards/ti/lp_em_cc35x1/config/flash/gd25lf64e/flash_disc_param_xspi.json new file mode 100644 index 000000000000..ecd4d20bdd53 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/gd25lf64e/flash_disc_param_xspi.json @@ -0,0 +1,485 @@ +{ + "xspi_header": { + "name": "xSPIWFF3", + "device": "CC3500", + "use_hardware": "GD25LF64E", + "use_case": "Quadro", + "dqs_support": 0, + "flash_only": 1, + "flash_separate_reset": 0, + "ram_separate_reset": true, + "clock_frequency": 80, + "qospi_clock_divider": 1, + "flash_device_character_conf": 0, + "ram_device_character_conf": 0, + "header_advanced": 0, + "phy_mode_enable": 1, + "pipeline_mode_enable": 1, + "loopback_support": "No", + "qspi_ref_clock": 80, + "spi_clock_freq": 20, + "spi_clock_divider": 1, + "flash_device_size": 8, + "flash_bytes_per_block": 16, + "flash_bytes_per_page": 256, + "flash_number_of_address_bytes": 3, + "flash_dual_opcode": 0, + "flash_jedec_manufacturer_id": 0, + "flash_jedec_device_id": 0, + "flash_name": "GD25LF64E", + "flash_page_size": 256, + "flash_sector_size": 4096, + "flash_cs_polarity": "ACTIVE_LOW", + "flash_sw_reset_type": "x1xxxx", + "ram_device_size": 8, + "ram_bytes_per_block": 16, + "ram_bytes_per_page": 256, + "ram_number_of_address_bytes": 3, + "ram_dual_opcode": 0, + "ram_jedec_manufacturer_id": 0, + "ram_jedec_device_id": 0, + "ram_name": "NO_PSRAM", + "ram_page_size": 256, + "ram_sector_size": 4096, + "ram_cs_polarity": "ACTIVE_LOW", + "ram_sw_reset_type": "x1xxxx", + "flash_write_operation_modes": "4S-4S-4S", + "flash_read_operation_modes": "4S-4S-4S", + "ram_write_operation_modes": "4S-4S-4S", + "ram_read_operation_modes": "4S-4S-4S", + "crc_enable": 0, + "enable_dtr": 0, + "enable_ahb_decoder": 0, + "enter_xip_mod_immediately": 0, + "enter_xip_mod_next_read": 0, + "ahb_address_remapping": 0, + "enable_dma": 0, + "select_decode": 0, + "legacy_ip_mode": 0, + "direct_access": 1 + }, + "xspi_pinmux": { + "xspi_clk_input": 44, + "xspi_clk_input_use_hw": 0, + "xspi_clk_input_mode": "Input", + "xspi_clk_input_pull": "None", + "xspi_clk_input_interrupt_trigger": "Low", + "xspi_clk_input_dont_conf": 0, + "xspi_clk_input_output_strength": "High", + "xspi_clk_input_initial_output_state": "High", + "xspi_clk": 24, + "xspi_clk_use_hw": "None", + "xspi_clk_mode": "Output", + "xspi_clk_pull": "None", + "xspi_clk_output_strength": "High", + "xspi_clk_initial_output_state": "High", + "xspi_clk_interrupt_trigger": "None", + "xspi_clk_dont_conf": 0, + "xspi_flash_cs": 20, + "xspi_flash_cs_use_hw": "None", + "xspi_flash_cs_mode": "Output", + "xspi_flash_cs_pull": "None", + "xspi_flash_cs_output_strength": "High", + "xspi_flash_cs_initial_output_state": "High", + "xspi_flash_cs_interrupt_trigger": "None", + "xspi_flash_cs_dont_conf": 0, + "xspi_data_0": 25, + "xspi_data_0_use_hw": "None", + "xspi_data_0_mode": "Input", + "xspi_data_0_pull": "None", + "xspi_data_0_output_strength": "High", + "xspi_data_0_initial_output_state": "High", + "xspi_data_0_interrupt_trigger": "Low", + "xspi_data_0_dont_conf": 0, + "xspi_data_1": 21, + "xspi_data_1_use_hw": "None", + "xspi_data_1_mode": "Input", + "xspi_data_1_pull": "None", + "xspi_data_1_output_strength": "High", + "xspi_data_1_initial_output_state": "High", + "xspi_data_1_interrupt_trigger": "Low", + "xspi_data_1_dont_conf": 0, + "xspi_data_2": 22, + "xspi_data_2_use_hw": "None", + "xspi_data_2_mode": "Input", + "xspi_data_2_pull": "None", + "xspi_data_2_output_strength": "High", + "xspi_data_2_initial_output_state": "High", + "xspi_data_2_interrupt_trigger": "Low", + "xspi_data_2_dont_conf": 0, + "xspi_data_3": 23, + "xspi_data_3_use_hw": "None", + "xspi_data_3_mode": "Input", + "xspi_data_3_pull": "None", + "xspi_data_3_output_strength": "High", + "xspi_data_3_initial_output_state": "High", + "xspi_data_3_interrupt_trigger": "Low", + "xspi_data_3_dont_conf": 0, + "xspi_data_4": 26, + "xspi_data_4_use_hw": "None", + "xspi_data_4_mode": "Input", + "xspi_data_4_pull": "None", + "xspi_data_4_output_strength": "High", + "xspi_data_4_initial_output_state": "High", + "xspi_data_4_interrupt_trigger": "None", + "xspi_data_4_dont_conf": 0, + "xspi_data_5": 27, + "xspi_data_5_use_hw": "None", + "xspi_data_5_mode": "Input", + "xspi_data_5_pull": "None", + "xspi_data_5_output_strength": "High", + "xspi_data_5_initial_output_state": "High", + "xspi_data_5_interrupt_trigger": "None", + "xspi_data_5_dont_conf": 0, + "xspi_data_6": 28, + "xspi_data_6_use_hw": "None", + "xspi_data_6_mode": "Input", + "xspi_data_6_pull": "None", + "xspi_data_6_output_strength": "High", + "xspi_data_6_initial_output_state": "High", + "xspi_data_6_interrupt_trigger": "None", + "xspi_data_6_dont_conf": 0, + "xspi_data_7": 29, + "xspi_data_7_use_hw": "None", + "xspi_data_7_mode": "Input", + "xspi_data_7_pull": "None", + "xspi_data_7_output_strength": "High", + "xspi_data_7_initial_output_state": "High", + "xspi_data_7_interrupt_trigger": "None", + "xspi_data_7_dont_conf": 0, + "xspi_reset_flash": 36, + "xspi_reset_flash_use_hw": "None", + "xspi_reset_flash_mode": "Output", + "xspi_reset_flash_pull": "None", + "xspi_reset_flash_output_strength": "High", + "xspi_reset_flash_initial_output_state": "High", + "xspi_reset_flash_interrupt_trigger": "None", + "xspi_reset_flash_dont_conf": 0, + "xspi_cs_ram": 3, + "xspi_cs_ram_use_hw": "None", + "xspi_cs_ram_mode": "Output", + "xspi_cs_ram_pull": "None", + "xspi_cs_ram_output_strength": "High", + "xspi_cs_ram_initial_output_state": "High", + "xspi_cs_ram_interrupt_trigger": "None", + "xspi_cs_ram_dont_conf": 0, + "xspi_dqs": 30, + "xspi_dqs_use_hw": "None", + "xspi_dqs_mode": "Input", + "xspi_dqs_pull": "None", + "xspi_dqs_output_strength": "High", + "xspi_dqs_initial_output_state": "High", + "xspi_dqs_interrupt_trigger": "None", + "xspi_dqs_dont_conf": 0, + "xspi_reset_ram": 2, + "xspi_reset_ram_use_hw": "None", + "xspi_reset_ram_mode": "Input", + "xspi_reset_ram_pull": "None", + "xspi_reset_ram_output_strength": "High", + "xspi_reset_ram_initial_output_state": "High", + "xspi_reset_ram_interrupt_trigger": "None", + "xspi_reset_ram_dont_conf": 0 + }, + "xspi_operations": { + "xspi_operations_clocks": { + "clock_phase": 0, + "clock_polarity": 0, + "spi_mode": "2'b00" + }, + "xspi_operations_chip_select": { + "csda": 2, + "csdads": 0, + "cseot": 4, + "cssot": 1 + }, + "xspi_operations_reset": { + "flash_jedec_reset": 0, + "ram_jedec_reset": 0, + "flash_treset": 20, + "ram_treset": 20 + }, + "xspi_phy_operations": { + "flash_rx_dll_bypass_bit": 0, + "flash_dll_tx_delay": 22, + "flash_dll_rx_delay": 34, + "ram_rx_dll_bypass_bit": 0, + "ram_dll_tx_delay": 22, + "ram_dll_rx_delay": 34 + }, + "xspi_read_operations": { + "flash_dummy_rd_cycles": 4, + "flash_read_opcode": 11, + "suppl_flash_read_opcode": 0, + "ram_dummy_rd_cycles": 4, + "ram_read_opcode": 11, + "suppl_ram_read_opcode": 0, + "flash_non_cont_read_enable": 0, + "flash_max_read_jobs": 256, + "ram_non_cont_read_enable": 0, + "ram_max_read_jobs": 256, + "rww_en": 0, + "device_size": 8, + "number_of_banks": 1, + "bank_size": 8, + "mode_bit_enable": 0 + }, + "xspi_write_operations": { + "flash_address_and_data": { + "flash_dummy_wr_cycles": 0 + }, + "flash_command": { + "flash_write_opcode": 2, + "suppl_flash_write_opcode": 0 + }, + "ram_address_and_data": { + "ram_dummy_wr_cycles": 0 + }, + "ram_command": { + "ram_write_opcode": 2, + "suppl_ram_write_opcode": 0 + }, + "write_to_buffer": { + "flash_write_to_buffer_support": 0, + "ram_write_to_buffer_support": 0 + }, + "non_continuous_write": { + "flash_non_cont_write_enable": 0, + "flash_max_write_jobs": 64, + "ram_non_cont_write_enable": 0, + "ram_max_write_jobs": 0 + }, + "flash_program_operation": { + "flash_min_program_size": "256 B", + "flash_program_opcode": 2, + "suppl_flash_program_opcode": 0, + "flash_maximum_program_time_limit": 1600 + }, + "flash_erase_operation": { + "flash_min_erase_size": "4 kB", + "flash_erase_opcode": 32, + "suppl_flash_erase_opcode": 0, + "flash_maximum_erase_time_limit": 4095 + }, + "flash_erase_conf": { + "flash_block_erase_opcode": 0, + "suppl_block_flash_erase_opcode": 0, + "flash_sector_erase_opcode": 0, + "suppl_sector_flash_erase_opcode": 0, + "flash_chip_erase_opcode": 0, + "suppl_chip_flash_erase_opcode": 0 + }, + "ram_program_operation": { + "ram_min_program_size": "256 B", + "ram_program_opcode": 2, + "suppl_ram_program_opcode": 0, + "ram_maximum_program_time_limit": 1600 + }, + "ram_erase_conf": { + "ram_block_erase_opcode": 0, + "suppl_block_ram_erase_opcode": 0, + "ram_sector_erase_opcode": 0, + "suppl_sector_ram_erase_opcode": 0, + "ram_chip_erase_opcode": 0, + "suppl_chip_ram_erase_opcode": 0 + }, + "flash_buffer_support": { + "flash_pre_write_sequence": 0, + "flash_post_write_sequence": 0, + "flash_write_protection_timer_en": 0, + "flash_write_buffer_timer_mode": 16, + "flash_write_buffer_timer_range": 0, + "flash_service_interrupt_criteria": 0 + }, + "ram_buffer_support": { + "ram_pre_write_sequence": 0, + "ram_post_write_sequence": 0, + "ram_write_protection_timer_en": 0, + "ram_write_buffer_timer_mode": 16, + "ram_write_buffer_timer_range": 0, + "ram_service_interrupt_criteria": 0 + }, + "flash_pre_write_conf": { + "flash_pre_write_job_done_grant_sel": 0, + "data_for_flash_pre_write_conf_0": 0, + "offset_bits_for_flash_pre_write_conf_0": 0, + "stop_bit_for_flash_pre_write_conf_0": 1, + "data_for_flash_pre_write_conf_1": 0, + "offset_bits_for_flash_pre_write_conf_1": 0 + }, + "flash_post_write_conf": { + "flash_post_write_job_done_grant_sel": 0, + "data_for_flash_post_write_conf_0": 0, + "offset_bits_for_flash_post_write_conf_0": 0, + "stop_bit_for_flash_post_write_conf_0": 1, + "data_for_flash_post_write_conf_1": 0, + "offset_bits_for_flash_post_write_conf_1": 0 + }, + "ram_pre_write_conf": { + "ram_pre_write_job_done_grant_sel": 0, + "data_for_ram_pre_write_conf_0": 0, + "offset_bits_for_ram_pre_write_conf_0": 0, + "stop_bit_for_ram_pre_write_conf_0": 1, + "data_for_ram_pre_write_conf_1": 0, + "offset_bits_for_ram_pre_write_conf_1": 0 + }, + "ram_post_write_conf": { + "ram_post_write_job_done_grant_sel": 0, + "data_for_ram_post_write_conf_0": 0, + "offset_bits_for_ram_post_write_conf_0": 0, + "stop_bit_for_ram_post_write_conf_0": 1, + "data_for_ram_post_write_conf_1": 0, + "offset_bits_for_ram_post_write_conf_1": 0 + } + }, + "xspi_capture_operations": { + "read_data_capture": { + "flash_delay_transmitted_data": 0, + "flash_loopback_clock": 0, + "flash_bypass_adapted_loopback": 1, + "flash_sample_edge_sel": 0, + "ram_delay_transmitted_data": 0, + "ram_loopback_clock": 0, + "ram_bypass_adapted_loopback": 1, + "ram_sample_edge_sel": 0 + }, + "delays": { + "flash_full_half_cycle_delay": 0, + "flash_dll_bypass_mode": 1, + "flash_phase_detect_sel": 0, + "flash_dll_lock_num": 0, + "flash_dll_start_point": 0, + "flash_loopback_clock": 0, + "ram_full_half_cycle_delay": 0, + "ram_dll_bypass_mode": 1, + "ram_phase_detect_sel": 0, + "ram_dll_lock_num": 0, + "ram_dll_start_point": 0, + "ram_loopback_clock": 0 + }, + "operation_modes": { + "flash_sfdp_support": 0, + "ram_sfdp_support": 0, + "flash_pm_support": 0, + "ram_pm_support": 0, + "flash_sfdp_opcode": 0, + "suppl_flash_sfdp_opcode": 0, + "ram_sfdp_opcode": 0, + "suppl_ram_sfdp_opcode": 0, + "flash_enter_dpd_opcode": 185, + "suppl_flash_enter_dpd_opcode": 0, + "flash_exit_dpd_opcode": 171, + "suppl_flash_exit_dpd_opcode": 0, + "ram_enter_dpd_opcode": 185, + "suppl_ram_enter_dpd_opcode": 0, + "ram_exit_dpd_opcode": 171, + "suppl_ram_exit_dpd_opcode": 0, + "flash_quad_enable_opcode": 56, + "suppl_flash_quad_enable_opcode": 0, + "flash_quad_disable_opcode": 255, + "suppl_flash_quad_disable_opcode": 0, + "flash_octal_enable_opcode": 0, + "suppl_flash_octal_enable_opcode": 0, + "flash_octal_disable_opcode": 0, + "suppl_flash_octal_disable_opcode": 0, + "ram_quad_enable_opcode": 56, + "suppl_ram_quad_enable_opcode": 0, + "ram_quad_disable_opcode": 255, + "suppl_ram_quad_disable_opcode": 0, + "ram_octal_enable_opcode": 0, + "suppl_ram_octal_enable_opcode": 0, + "ram_octal_disable_opcode": 0, + "suppl_ram_octal_disable_opcode": 0 + } + } + }, + "external_memory_reporting": { + "header": { + "flash_auto_polling_enable": 1, + "flash_wel_enable": 1, + "flash_write_protect_enable": 0, + "flash_alternate_polling_conf_enable": 0, + "ram_auto_polling_enable": 1, + "ram_wel_enable": 1, + "ram_write_protect_enable": 0, + "ram_alternate_polling_conf_enable": 0 + }, + "flash_auto_polling": { + "flash_polling_repetition_delay": 0, + "flash_polling_count": 4, + "flash_enable_polling_expiration": 0, + "flash_polling_polarity": 0, + "flash_polling_address_phase_enable": 0, + "flash_polling_bit_index": 0, + "flash_numbers_poll_cycles": 65535, + "flash_dummy_autopoll_cycles": 0 + }, + "ram_auto_polling": { + "ram_polling_repetition_delay": 0, + "ram_polling_count": 4, + "ram_enable_polling_expiration": 0, + "ram_polling_polarity": 0, + "ram_polling_address_phase_enable": 0, + "ram_polling_bit_index": 0, + "ram_numbers_poll_cycles": 65535, + "ram_dummy_autopoll_cycles": 0 + }, + "flash_polling_command": { + "flash_polling_opcode": 5, + "suppl_flash_polling_opcode": 0 + }, + "ram_polling_command": { + "ram_polling_opcode": 5, + "suppl_ram_polling_opcode": 0 + }, + "flash_alternate_polling": { + "flash_polling_resp_count": 1023, + "flash_polling_iterations": 1, + "flash_polling_enabled": 0, + "flash_polling_disabled": 0, + "flash_grant_sel": 0, + "flash_data_for_enable_poling_conf_0": 0, + "flash_offset_bits_for_enable_poling_conf_0": 0, + "flash_stop_bit_for_enable_poling_conf_0": 1, + "flash_data_for_enable_poling_conf_1": 0, + "flash_offset_bits_for_enable_poling_conf_1": 0, + "flash_stop_bit_for_enable_poling_conf_1": 1, + "flash_data_for_disable_poling_conf_0": 0, + "flash_offset_bits_for_disable_poling_conf_0": 0, + "flash_stop_bit_for_disable_poling_conf_0": 1, + "flash_data_for_disable_poling_conf_1": 0, + "flash_offset_bits_for_disable_poling_conf_1": 0, + "flash_stop_bit_for_disable_poling_conf_1": 1 + }, + "ram_alternate_polling": { + "ram_polling_resp_count": 1023, + "ram_polling_iterations": 1, + "ram_polling_enabled": 0, + "ram_polling_disabled": 0, + "ram_grant_sel": 0, + "ram_data_for_enable_poling_conf_0": 0, + "ram_offset_bits_for_enable_poling_conf_0": 0, + "ram_stop_bit_for_enable_poling_conf_0": 1, + "ram_data_for_enable_poling_conf_1": 0, + "ram_offset_bits_for_enable_poling_conf_1": 0, + "ram_stop_bit_for_enable_poling_conf_1": 1, + "ram_data_for_disable_poling_conf_0": 0, + "ram_offset_bits_for_disable_poling_conf_0": 0, + "ram_stop_bit_for_disable_poling_conf_0": 1, + "ram_data_for_disable_poling_conf_1": 0, + "ram_offset_bits_for_disable_poling_conf_1": 0, + "ram_stop_bit_for_disable_poling_conf_1": 1 + }, + "flash_wel_command": { + "flash_wel_opcode": 6, + "suppl_flash_wel_opcode": 0 + }, + "ram_wel_command": { + "ram_wel_opcode": 6, + "suppl_ram_wel_opcode": 0 + } + }, + "event": { + "host_nvic_irq": 0, + "core_10_mux_sel": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/is25wj032f/flash_disc_param_ext_mem.json b/boards/ti/lp_em_cc35x1/config/flash/is25wj032f/flash_disc_param_ext_mem.json new file mode 100644 index 000000000000..321810768be1 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/is25wj032f/flash_disc_param_ext_mem.json @@ -0,0 +1,99 @@ +{ + "vendor_primary_sbl": true, + "ti_wsoc_primary_container": true, + "ti_wsoc_bl2_primary_container": true, + "nvs_enable": true, + "vendor_alternate_image": true, + "vendor_sbl_alternate_image": true, + "ti_bl_alternate_image": true, + "ti_wsoc_alternate_image": true, + "ti_wsoc_bl2_alternate_image": true, + "region_0": { + "mem_region_0_start_phy_address": 1069056, + "mem_region_0_end_phy_address": 4194303, + "region0_boot": false, + "region0_main_code": true, + "region0_nvs": false, + "region0_wsoc_code": false, + "region0_alternate_code": false + }, + "region_1": { + "mem_region_1_start_phy_address": 0, + "mem_region_1_end_phy_address": 1069055, + "region1_boot": true, + "region1_main_code": false, + "region1_nvs": true, + "region1_wsoc_code": true, + "region1_alternate_code": false + }, + "region_2": { + "mem_region_2_start_phy_address": 0, + "mem_region_2_end_phy_address": 0, + "region2_boot": false, + "region2_main_code": false, + "region2_nvs": false, + "region2_wsoc_code": false, + "region2_alternate_code": true + }, + "region_3": { + "mem_region_3_start_phy_address": 0, + "mem_region_3_end_phy_address": 0, + "region3_boot": false, + "region3_main_code": false, + "region3_nvs": false, + "region3_wsoc_code": false, + "region3_alternate_code": false + }, + "boot_region_conf": { + "boot_region_size": 0, + "boot_region_flash_disco_param_start_address": 0, + "boot_region_primary_ti_bl_start_phy_address": 12284, + "boot_region_primary_ti_bl_magic": 0, + "boot_region_primary_ti_bl_major": 0, + "boot_region_primary_ti_bl_minor": 0, + "boot_region_sec_ti_bl_start_phy_address": 430076, + "boot_region_sec_ti_bl_magic": 0, + "boot_region_sec_ti_bl_major": 0, + "boot_region_sec_ti_bl_minor": 0 + }, + "main_code_region_conf": { + "main_code_region_vendor_image_start_phy_address": 1073148, + "main_code_region_vendor_image_magic": 0, + "main_code_region_vendor_image_major": 0, + "main_code_region_vendor_image_minor": 0, + "main_code_region_sbl_start_phy_address": 0, + "main_code_region_sbl_magic": 0, + "main_code_region_sbl_major": 0, + "main_code_region_sbl_minor": 0 + }, + "alt_code_region_conf": { + "alt_code_region_vendor_image_start_phy_address": 4194304, + "alt_code_region_vendor_image_magic": 0, + "alt_code_region_vendor_image_major": 0, + "alt_code_region_vendor_image_minor": 0, + "alt_code_region_sbl_start_phy_address": 0, + "alt_code_region_sbl_magic": 0, + "alt_code_region_sbl_major": 0, + "alt_code_region_sbl_minor": 0 + }, + "nvs_code_region_conf": { + "nvs_start_phy_address": 892928, + "nvs_region_size": 176128, + "nvs_region_primary_wsoc_start_phy_address": 430076, + "nvs_region_primary_wsoc_magic": 0, + "nvs_region_primary_wsoc_major": 0, + "nvs_region_primary_wsoc_minor": 0, + "nvs_region_sec_wsoc_start_phy_address": 897020, + "nvs_region_sec_wsoc_magic": 0, + "nvs_region_sec_wsoc_major": 0, + "nvs_region_sec_wsoc_minor": 0, + "nvs_region_primary_wsoc_bl2_start_phy_address": 0, + "nvs_region_primary_wsoc_bl2_magic": 0, + "nvs_region_primary_wsoc_bl2_major": 0, + "nvs_region_primary_wsoc_bl2_minor": 0, + "nvs_region_sec_wsoc_bl2_start_phy_address": 0, + "nvs_region_sec_wsoc_bl2_magic": 0, + "nvs_region_sec_wsoc_bl2_major": 0, + "nvs_region_sec_wsoc_bl2_minor": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/is25wj032f/flash_disc_param_otfde.json b/boards/ti/lp_em_cc35x1/config/flash/is25wj032f/flash_disc_param_otfde.json new file mode 100644 index 000000000000..635e11319c5d --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/is25wj032f/flash_disc_param_otfde.json @@ -0,0 +1,286 @@ +{ + "otfde_header": { + "name": "OTFDEWFF3", + "flash_only": true, + "ip_protection": false, + "regions_lock": false, + "regions_number": 4, + "flash_enabled": true + }, + "bl_conf": { + "host_boot_done_lock": true, + "host_peripherals_lock": true, + "icache_conf_lock": true, + "m33_mem_part_lock": true, + "memss_firewall_lock": true, + "dma_channel_owner_lock": true, + "otfde_region_lock": true, + "core_events_lock": true + }, + "otfde_general": { + "parameters": { + "mem_otfde_initial_delay": 10, + "otfde_global_watchdog_timer": 5 + }, + "events": { + "reset_evt_mask": false, + "reset_evt_suspend": false, + "sft_reset_evt_mask": false, + "sft_reset_evt_suspend": false, + "bypass_mode_evt_mask": false, + "bypass_mode_evt_suspend": false, + "debug_mode_evt_mask": false, + "debug_mode_evt_suspend": false, + "general_evt_mask": false, + "general_evt_suspend": false, + "xspi_data_path_evt_mask": false, + "xspi_data_path_evt_suspend": false, + "xspi_cnfg_path_evt_mask": false, + "xspi_cnfg_path_evt_suspend": false, + "xspi_service_interrupt_evt_mask": false, + "xspi_service_interrupt_evt_suspend": false, + "trans_device_disabled_evt_mask": false, + "trans_device_disabled_evt_suspend": false, + "trans_region_disabled_evt_mask": false, + "trans_region_disabled_evt_suspend": false, + "trans_region_params_conf_evt_mask": false, + "trans_region_params_conf_evt_suspend": false, + "trans_multiple_regions_mapped_evt_mask": false, + "trans_multiple_regions_mapped_evt_suspend": false, + "trans_address_not_32_bit_evt_mask": false, + "trans_address_not_32_bit_evt_suspend": false, + "trans_size_not_32_bit_evt_mask": false, + "trans_size_not_32_bit_evt_suspend": false, + "trans_burst_not_32_bit_evt_mask": false, + "trans_burst_not_32_bit_evt_suspend": false, + "region_read_write_def_evt_mask": false, + "region_read_write_def_evt_suspend": false, + "suspend_while_disabled_evt_mask": false, + "suspend_while_disabled_evt_suspend": false + } + }, + "regions_settings": { + "region_parameters_lock": { + "REGION_0_PARAMS_0": true, + "REGION_0_PARAMS_1": true, + "REGION_0_PARAMS_2": true, + "REGION_1_PARAMS_0": false, + "REGION_1_PARAMS_1": false, + "REGION_1_PARAMS_2": false, + "REGION_2_PARAMS_0": true, + "REGION_2_PARAMS_1": true, + "REGION_2_PARAMS_2": true, + "REGION_3_PARAMS_0": false, + "REGION_3_PARAMS_1": false, + "REGION_3_PARAMS_2": false + }, + "region_0_protection": { + "mem_region_0_enabled": true, + "mem_region_0_device_id": 0, + "mem_region_0_spi_write_enable": true, + "mem_region_0_spi_read_enable": true, + "mem_region_0_physical_offset": 261, + "mem_region_0_security_id_msb": 0, + "mem_region_0_start_address": 81920, + "mem_region_0_end_address": 82682, + "mem_region_0_security_id_lsb": 0, + "mem_otfde_region_0_write_lock_en": false, + "mem_otfde_region_0_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_1_protection": { + "mem_region_1_enabled": true, + "mem_region_1_device_id": 0, + "mem_region_1_spi_write_enable": true, + "mem_region_1_spi_read_enable": true, + "mem_region_1_physical_offset": 0, + "mem_region_1_security_id_msb": 0, + "mem_region_1_start_address": 655360, + "mem_region_1_end_address": 655620, + "mem_region_1_security_id_lsb": 0, + "mem_otfde_region_1_write_lock_en": false, + "mem_otfde_region_1_enc_dec_bypass": "Bypass" + }, + "region_2_protection": { + "mem_region_2_enabled": false, + "mem_region_2_device_id": 0, + "mem_region_2_spi_write_enable": true, + "mem_region_2_spi_read_enable": true, + "mem_region_2_physical_offset": 0, + "mem_region_2_security_id_msb": 0, + "mem_region_2_start_address": 1, + "mem_region_2_end_address": 0, + "mem_region_2_security_id_lsb": 0, + "mem_otfde_region_2_write_lock_en": false, + "mem_otfde_region_2_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_3_protection": { + "mem_region_3_enabled": false, + "mem_region_3_device_id": 1, + "mem_region_3_spi_write_enable": true, + "mem_region_3_spi_read_enable": true, + "mem_region_3_physical_offset": 0, + "mem_region_3_security_id_msb": 0, + "mem_region_3_start_address": 1, + "mem_region_3_end_address": 0, + "mem_region_3_security_id_lsb": 0, + "mem_otfde_region_3_write_lock_en": false, + "mem_otfde_region_3_enc_dec_bypass": "Bypass" + } + }, + "devices": { + "header": { + "flash_device_switch_conf": 1, + "ram_device_switch_conf": 1 + }, + "flash_switch": { + "flash_grant_sel": 0, + "flash_data_for_conf_0": 2181562505, + "flash_offset_bits_for_conf_0": 0, + "flash_stop_bit_for_conf_0": 0, + "flash_data_for_conf_1": 67248651, + "flash_offset_bits_for_conf_1": 1, + "flash_stop_bit_for_conf_1": 0, + "flash_data_for_conf_2": 139266, + "flash_offset_bits_for_conf_2": 2, + "flash_stop_bit_for_conf_2": 0, + "flash_data_for_conf_3": 1, + "flash_offset_bits_for_conf_3": 4, + "flash_stop_bit_for_conf_3": 0, + "flash_data_for_conf_4": 1076887634, + "flash_offset_bits_for_conf_4": 45, + "flash_stop_bit_for_conf_4": 0, + "flash_data_for_conf_5": 3224371282, + "flash_offset_bits_for_conf_5": 45, + "flash_stop_bit_for_conf_5": 0, + "flash_data_for_conf_6": 262149, + "flash_offset_bits_for_conf_6": 14, + "flash_stop_bit_for_conf_6": 0, + "flash_data_for_conf_7": 0, + "flash_offset_bits_for_conf_7": 44, + "flash_stop_bit_for_conf_7": 1, + "flash_data_for_conf_8": 0, + "flash_offset_bits_for_conf_8": 0, + "flash_stop_bit_for_conf_8": 1, + "flash_data_for_conf_9": 0, + "flash_offset_bits_for_conf_9": 0, + "flash_stop_bit_for_conf_9": 1, + "flash_data_for_conf_10": 0, + "flash_offset_bits_for_conf_10": 0, + "flash_stop_bit_for_conf_10": 1, + "flash_data_for_conf_11": 0, + "flash_offset_bits_for_conf_11": 0, + "flash_stop_bit_for_conf_11": 1, + "flash_data_for_conf_12": 0, + "flash_offset_bits_for_conf_12": 0, + "flash_stop_bit_for_conf_12": 1, + "flash_data_for_conf_13": 0, + "flash_offset_bits_for_conf_13": 0, + "flash_stop_bit_for_conf_13": 1, + "flash_data_for_conf_14": 0, + "flash_offset_bits_for_conf_14": 0, + "flash_stop_bit_for_conf_14": 1, + "flash_data_for_conf_15": 0, + "flash_offset_bits_for_conf_15": 0, + "flash_stop_bit_for_conf_15": 1, + "flash_data_for_conf_16": 0, + "flash_offset_bits_for_conf_16": 0, + "flash_stop_bit_for_conf_16": 1, + "flash_data_for_conf_17": 0, + "flash_offset_bits_for_conf_17": 0, + "flash_stop_bit_for_conf_17": 1, + "flash_data_for_conf_18": 0, + "flash_offset_bits_for_conf_18": 0, + "flash_stop_bit_for_conf_18": 1, + "flash_data_for_conf_19": 0, + "flash_offset_bits_for_conf_19": 0, + "flash_stop_bit_for_conf_19": 1, + "flash_data_for_conf_20": 0, + "flash_offset_bits_for_conf_20": 0, + "flash_stop_bit_for_conf_20": 1, + "flash_data_for_conf_21": 0, + "flash_offset_bits_for_conf_21": 0, + "flash_stop_bit_for_conf_21": 1, + "flash_data_for_conf_22": 0, + "flash_offset_bits_for_conf_22": 0, + "flash_stop_bit_for_conf_22": 1, + "flash_data_for_conf_23": 0, + "flash_offset_bits_for_conf_23": 0, + "flash_stop_bit_for_conf_23": 1 + }, + "ram_switch": { + "ram_grant_sel": 0, + "ram_data_for_conf_0": 2181562505, + "ram_offset_bits_for_conf_0": 0, + "ram_stop_bit_for_conf_0": 0, + "ram_data_for_conf_1": 67248651, + "ram_offset_bits_for_conf_1": 1, + "ram_stop_bit_for_conf_1": 0, + "ram_data_for_conf_2": 139266, + "ram_offset_bits_for_conf_2": 2, + "ram_stop_bit_for_conf_2": 0, + "ram_data_for_conf_3": 1, + "ram_offset_bits_for_conf_3": 4, + "ram_stop_bit_for_conf_3": 0, + "ram_data_for_conf_4": 1076887634, + "ram_offset_bits_for_conf_4": 45, + "ram_stop_bit_for_conf_4": 0, + "ram_data_for_conf_5": 3224371282, + "ram_offset_bits_for_conf_5": 45, + "ram_stop_bit_for_conf_5": 0, + "ram_data_for_conf_6": 262149, + "ram_offset_bits_for_conf_6": 14, + "ram_stop_bit_for_conf_6": 0, + "ram_data_for_conf_7": 0, + "ram_offset_bits_for_conf_7": 44, + "ram_stop_bit_for_conf_7": 1, + "ram_data_for_conf_8": 0, + "ram_offset_bits_for_conf_8": 0, + "ram_stop_bit_for_conf_8": 1, + "ram_data_for_conf_9": 0, + "ram_offset_bits_for_conf_9": 0, + "ram_stop_bit_for_conf_9": 1, + "ram_data_for_conf_10": 0, + "ram_offset_bits_for_conf_10": 0, + "ram_stop_bit_for_conf_10": 1, + "ram_data_for_conf_11": 0, + "ram_offset_bits_for_conf_11": 0, + "ram_stop_bit_for_conf_11": 1, + "ram_data_for_conf_12": 0, + "ram_offset_bits_for_conf_12": 0, + "ram_stop_bit_for_conf_12": 1, + "ram_data_for_conf_13": 0, + "ram_offset_bits_for_conf_13": 0, + "ram_stop_bit_for_conf_13": 1, + "ram_data_for_conf_14": 0, + "ram_offset_bits_for_conf_14": 0, + "ram_stop_bit_for_conf_14": 1, + "ram_data_for_conf_15": 0, + "ram_offset_bits_for_conf_15": 0, + "ram_stop_bit_for_conf_15": 1, + "ram_data_for_conf_16": 0, + "ram_offset_bits_for_conf_16": 0, + "ram_stop_bit_for_conf_16": 1, + "ram_data_for_conf_17": 0, + "ram_offset_bits_for_conf_17": 0, + "ram_stop_bit_for_conf_17": 1, + "ram_data_for_conf_18": 0, + "ram_offset_bits_for_conf_18": 0, + "ram_stop_bit_for_conf_18": 1, + "ram_data_for_conf_19": 0, + "ram_offset_bits_for_conf_19": 0, + "ram_stop_bit_for_conf_19": 1, + "ram_data_for_conf_20": 0, + "ram_offset_bits_for_conf_20": 0, + "ram_stop_bit_for_conf_20": 1, + "ram_data_for_conf_21": 0, + "ram_offset_bits_for_conf_21": 0, + "ram_stop_bit_for_conf_21": 1, + "ram_data_for_conf_22": 0, + "ram_offset_bits_for_conf_22": 0, + "ram_stop_bit_for_conf_22": 1, + "ram_data_for_conf_23": 0, + "ram_offset_bits_for_conf_23": 0, + "ram_stop_bit_for_conf_23": 1 + } + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/is25wj032f/flash_disc_param_xspi.json b/boards/ti/lp_em_cc35x1/config/flash/is25wj032f/flash_disc_param_xspi.json new file mode 100644 index 000000000000..c96cbac6431a --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/is25wj032f/flash_disc_param_xspi.json @@ -0,0 +1,485 @@ +{ + "xspi_header": { + "name": "xSPIWFF3", + "device": "CC3500", + "use_hardware": "IS25WJ032F", + "use_case": "Quadro", + "dqs_support": 0, + "flash_only": 1, + "flash_separate_reset": 0, + "ram_separate_reset": true, + "clock_frequency": 80, + "qospi_clock_divider": 1, + "flash_device_character_conf": 0, + "ram_device_character_conf": 0, + "header_advanced": 0, + "phy_mode_enable": 1, + "pipeline_mode_enable": 1, + "loopback_support": "No", + "qspi_ref_clock": 80, + "spi_clock_freq": 20, + "spi_clock_divider": 1, + "flash_device_size": 4, + "flash_bytes_per_block": 16, + "flash_bytes_per_page": 256, + "flash_number_of_address_bytes": 3, + "flash_dual_opcode": 0, + "flash_jedec_manufacturer_id": 0, + "flash_jedec_device_id": 0, + "flash_name": "IS25WJ032F", + "flash_page_size": 256, + "flash_sector_size": 4096, + "flash_cs_polarity": "ACTIVE_LOW", + "flash_sw_reset_type": "x1xxxx", + "ram_device_size": 4, + "ram_bytes_per_block": 16, + "ram_bytes_per_page": 256, + "ram_number_of_address_bytes": 3, + "ram_dual_opcode": 0, + "ram_jedec_manufacturer_id": 0, + "ram_jedec_device_id": 0, + "ram_name": "NO_PSRAM", + "ram_page_size": 256, + "ram_sector_size": 4096, + "ram_cs_polarity": "ACTIVE_LOW", + "ram_sw_reset_type": "x1xxxx", + "flash_write_operation_modes": "4S-4S-4S", + "flash_read_operation_modes": "4S-4S-4S", + "ram_write_operation_modes": "4S-4S-4S", + "ram_read_operation_modes": "4S-4S-4S", + "crc_enable": 0, + "enable_dtr": 0, + "enable_ahb_decoder": 0, + "enter_xip_mod_immediately": 0, + "enter_xip_mod_next_read": 0, + "ahb_address_remapping": 0, + "enable_dma": 0, + "select_decode": 0, + "legacy_ip_mode": 0, + "direct_access": 1 + }, + "xspi_pinmux": { + "xspi_clk_input": 44, + "xspi_clk_input_use_hw": 0, + "xspi_clk_input_mode": "Input", + "xspi_clk_input_pull": "None", + "xspi_clk_input_interrupt_trigger": "Low", + "xspi_clk_input_dont_conf": 0, + "xspi_clk_input_output_strength": "High", + "xspi_clk_input_initial_output_state": "High", + "xspi_clk": 24, + "xspi_clk_use_hw": "None", + "xspi_clk_mode": "Output", + "xspi_clk_pull": "None", + "xspi_clk_output_strength": "High", + "xspi_clk_initial_output_state": "High", + "xspi_clk_interrupt_trigger": "None", + "xspi_clk_dont_conf": 0, + "xspi_flash_cs": 20, + "xspi_flash_cs_use_hw": "None", + "xspi_flash_cs_mode": "Output", + "xspi_flash_cs_pull": "None", + "xspi_flash_cs_output_strength": "High", + "xspi_flash_cs_initial_output_state": "High", + "xspi_flash_cs_interrupt_trigger": "None", + "xspi_flash_cs_dont_conf": 0, + "xspi_data_0": 25, + "xspi_data_0_use_hw": "None", + "xspi_data_0_mode": "Input", + "xspi_data_0_pull": "None", + "xspi_data_0_output_strength": "High", + "xspi_data_0_initial_output_state": "High", + "xspi_data_0_interrupt_trigger": "Low", + "xspi_data_0_dont_conf": 0, + "xspi_data_1": 21, + "xspi_data_1_use_hw": "None", + "xspi_data_1_mode": "Input", + "xspi_data_1_pull": "None", + "xspi_data_1_output_strength": "High", + "xspi_data_1_initial_output_state": "High", + "xspi_data_1_interrupt_trigger": "Low", + "xspi_data_1_dont_conf": 0, + "xspi_data_2": 22, + "xspi_data_2_use_hw": "None", + "xspi_data_2_mode": "Input", + "xspi_data_2_pull": "None", + "xspi_data_2_output_strength": "High", + "xspi_data_2_initial_output_state": "High", + "xspi_data_2_interrupt_trigger": "Low", + "xspi_data_2_dont_conf": 0, + "xspi_data_3": 23, + "xspi_data_3_use_hw": "None", + "xspi_data_3_mode": "Input", + "xspi_data_3_pull": "None", + "xspi_data_3_output_strength": "High", + "xspi_data_3_initial_output_state": "High", + "xspi_data_3_interrupt_trigger": "Low", + "xspi_data_3_dont_conf": 0, + "xspi_data_4": 26, + "xspi_data_4_use_hw": "None", + "xspi_data_4_mode": "Input", + "xspi_data_4_pull": "None", + "xspi_data_4_output_strength": "High", + "xspi_data_4_initial_output_state": "High", + "xspi_data_4_interrupt_trigger": "None", + "xspi_data_4_dont_conf": 0, + "xspi_data_5": 27, + "xspi_data_5_use_hw": "None", + "xspi_data_5_mode": "Input", + "xspi_data_5_pull": "None", + "xspi_data_5_output_strength": "High", + "xspi_data_5_initial_output_state": "High", + "xspi_data_5_interrupt_trigger": "None", + "xspi_data_5_dont_conf": 0, + "xspi_data_6": 28, + "xspi_data_6_use_hw": "None", + "xspi_data_6_mode": "Input", + "xspi_data_6_pull": "None", + "xspi_data_6_output_strength": "High", + "xspi_data_6_initial_output_state": "High", + "xspi_data_6_interrupt_trigger": "None", + "xspi_data_6_dont_conf": 0, + "xspi_data_7": 29, + "xspi_data_7_use_hw": "None", + "xspi_data_7_mode": "Input", + "xspi_data_7_pull": "None", + "xspi_data_7_output_strength": "High", + "xspi_data_7_initial_output_state": "High", + "xspi_data_7_interrupt_trigger": "None", + "xspi_data_7_dont_conf": 0, + "xspi_reset_flash": 36, + "xspi_reset_flash_use_hw": "None", + "xspi_reset_flash_mode": "Output", + "xspi_reset_flash_pull": "None", + "xspi_reset_flash_output_strength": "High", + "xspi_reset_flash_initial_output_state": "High", + "xspi_reset_flash_interrupt_trigger": "None", + "xspi_reset_flash_dont_conf": 0, + "xspi_cs_ram": 3, + "xspi_cs_ram_use_hw": "None", + "xspi_cs_ram_mode": "Output", + "xspi_cs_ram_pull": "None", + "xspi_cs_ram_output_strength": "High", + "xspi_cs_ram_initial_output_state": "High", + "xspi_cs_ram_interrupt_trigger": "None", + "xspi_cs_ram_dont_conf": 0, + "xspi_dqs": 30, + "xspi_dqs_use_hw": "None", + "xspi_dqs_mode": "Input", + "xspi_dqs_pull": "None", + "xspi_dqs_output_strength": "High", + "xspi_dqs_initial_output_state": "High", + "xspi_dqs_interrupt_trigger": "None", + "xspi_dqs_dont_conf": 0, + "xspi_reset_ram": 2, + "xspi_reset_ram_use_hw": "None", + "xspi_reset_ram_mode": "Input", + "xspi_reset_ram_pull": "None", + "xspi_reset_ram_output_strength": "High", + "xspi_reset_ram_initial_output_state": "High", + "xspi_reset_ram_interrupt_trigger": "None", + "xspi_reset_ram_dont_conf": 0 + }, + "xspi_operations": { + "xspi_operations_clocks": { + "clock_phase": 0, + "clock_polarity": 0, + "spi_mode": "2'b00" + }, + "xspi_operations_chip_select": { + "csda": 2, + "csdads": 0, + "cseot": 4, + "cssot": 1 + }, + "xspi_operations_reset": { + "flash_jedec_reset": 0, + "ram_jedec_reset": 0, + "flash_treset": 20, + "ram_treset": 20 + }, + "xspi_phy_operations": { + "flash_rx_dll_bypass_bit": 0, + "flash_dll_tx_delay": 22, + "flash_dll_rx_delay": 34, + "ram_rx_dll_bypass_bit": 0, + "ram_dll_tx_delay": 22, + "ram_dll_rx_delay": 34 + }, + "xspi_read_operations": { + "flash_dummy_rd_cycles": 4, + "flash_read_opcode": 11, + "suppl_flash_read_opcode": 0, + "ram_dummy_rd_cycles": 4, + "ram_read_opcode": 11, + "suppl_ram_read_opcode": 0, + "flash_non_cont_read_enable": 0, + "flash_max_read_jobs": 256, + "ram_non_cont_read_enable": 0, + "ram_max_read_jobs": 256, + "rww_en": 0, + "device_size": 4, + "number_of_banks": 1, + "bank_size": 4, + "mode_bit_enable": 0 + }, + "xspi_write_operations": { + "flash_address_and_data": { + "flash_dummy_wr_cycles": 0 + }, + "flash_command": { + "flash_write_opcode": 2, + "suppl_flash_write_opcode": 0 + }, + "ram_address_and_data": { + "ram_dummy_wr_cycles": 0 + }, + "ram_command": { + "ram_write_opcode": 2, + "suppl_ram_write_opcode": 0 + }, + "write_to_buffer": { + "flash_write_to_buffer_support": 0, + "ram_write_to_buffer_support": 0 + }, + "non_continuous_write": { + "flash_non_cont_write_enable": 0, + "flash_max_write_jobs": 64, + "ram_non_cont_write_enable": 0, + "ram_max_write_jobs": 0 + }, + "flash_program_operation": { + "flash_min_program_size": "256 B", + "flash_program_opcode": 2, + "suppl_flash_program_opcode": 0, + "flash_maximum_program_time_limit": 1600 + }, + "flash_erase_operation": { + "flash_min_erase_size": "4 kB", + "flash_erase_opcode": 32, + "suppl_flash_erase_opcode": 0, + "flash_maximum_erase_time_limit": 4095 + }, + "flash_erase_conf": { + "flash_block_erase_opcode": 0, + "suppl_block_flash_erase_opcode": 0, + "flash_sector_erase_opcode": 0, + "suppl_sector_flash_erase_opcode": 0, + "flash_chip_erase_opcode": 0, + "suppl_chip_flash_erase_opcode": 0 + }, + "ram_program_operation": { + "ram_min_program_size": "256 B", + "ram_program_opcode": 2, + "suppl_ram_program_opcode": 0, + "ram_maximum_program_time_limit": 1600 + }, + "ram_erase_conf": { + "ram_block_erase_opcode": 0, + "suppl_block_ram_erase_opcode": 0, + "ram_sector_erase_opcode": 0, + "suppl_sector_ram_erase_opcode": 0, + "ram_chip_erase_opcode": 0, + "suppl_chip_ram_erase_opcode": 0 + }, + "flash_buffer_support": { + "flash_pre_write_sequence": 0, + "flash_post_write_sequence": 0, + "flash_write_protection_timer_en": 0, + "flash_write_buffer_timer_mode": 16, + "flash_write_buffer_timer_range": 0, + "flash_service_interrupt_criteria": 0 + }, + "ram_buffer_support": { + "ram_pre_write_sequence": 0, + "ram_post_write_sequence": 0, + "ram_write_protection_timer_en": 0, + "ram_write_buffer_timer_mode": 16, + "ram_write_buffer_timer_range": 0, + "ram_service_interrupt_criteria": 0 + }, + "flash_pre_write_conf": { + "flash_pre_write_job_done_grant_sel": 0, + "data_for_flash_pre_write_conf_0": 0, + "offset_bits_for_flash_pre_write_conf_0": 0, + "stop_bit_for_flash_pre_write_conf_0": 1, + "data_for_flash_pre_write_conf_1": 0, + "offset_bits_for_flash_pre_write_conf_1": 0 + }, + "flash_post_write_conf": { + "flash_post_write_job_done_grant_sel": 0, + "data_for_flash_post_write_conf_0": 0, + "offset_bits_for_flash_post_write_conf_0": 0, + "stop_bit_for_flash_post_write_conf_0": 1, + "data_for_flash_post_write_conf_1": 0, + "offset_bits_for_flash_post_write_conf_1": 0 + }, + "ram_pre_write_conf": { + "ram_pre_write_job_done_grant_sel": 0, + "data_for_ram_pre_write_conf_0": 0, + "offset_bits_for_ram_pre_write_conf_0": 0, + "stop_bit_for_ram_pre_write_conf_0": 1, + "data_for_ram_pre_write_conf_1": 0, + "offset_bits_for_ram_pre_write_conf_1": 0 + }, + "ram_post_write_conf": { + "ram_post_write_job_done_grant_sel": 0, + "data_for_ram_post_write_conf_0": 0, + "offset_bits_for_ram_post_write_conf_0": 0, + "stop_bit_for_ram_post_write_conf_0": 1, + "data_for_ram_post_write_conf_1": 0, + "offset_bits_for_ram_post_write_conf_1": 0 + } + }, + "xspi_capture_operations": { + "read_data_capture": { + "flash_delay_transmitted_data": 0, + "flash_loopback_clock": 0, + "flash_bypass_adapted_loopback": 1, + "flash_sample_edge_sel": 0, + "ram_delay_transmitted_data": 0, + "ram_loopback_clock": 0, + "ram_bypass_adapted_loopback": 1, + "ram_sample_edge_sel": 0 + }, + "delays": { + "flash_full_half_cycle_delay": 0, + "flash_dll_bypass_mode": 1, + "flash_phase_detect_sel": 0, + "flash_dll_lock_num": 0, + "flash_dll_start_point": 0, + "flash_loopback_clock": 0, + "ram_full_half_cycle_delay": 0, + "ram_dll_bypass_mode": 1, + "ram_phase_detect_sel": 0, + "ram_dll_lock_num": 0, + "ram_dll_start_point": 0, + "ram_loopback_clock": 0 + }, + "operation_modes": { + "flash_sfdp_support": 0, + "ram_sfdp_support": 0, + "flash_pm_support": 0, + "ram_pm_support": 0, + "flash_sfdp_opcode": 0, + "suppl_flash_sfdp_opcode": 0, + "ram_sfdp_opcode": 0, + "suppl_ram_sfdp_opcode": 0, + "flash_enter_dpd_opcode": 185, + "suppl_flash_enter_dpd_opcode": 0, + "flash_exit_dpd_opcode": 171, + "suppl_flash_exit_dpd_opcode": 0, + "ram_enter_dpd_opcode": 185, + "suppl_ram_enter_dpd_opcode": 0, + "ram_exit_dpd_opcode": 171, + "suppl_ram_exit_dpd_opcode": 0, + "flash_quad_enable_opcode": 56, + "suppl_flash_quad_enable_opcode": 0, + "flash_quad_disable_opcode": 255, + "suppl_flash_quad_disable_opcode": 0, + "flash_octal_enable_opcode": 0, + "suppl_flash_octal_enable_opcode": 0, + "flash_octal_disable_opcode": 0, + "suppl_flash_octal_disable_opcode": 0, + "ram_quad_enable_opcode": 56, + "suppl_ram_quad_enable_opcode": 0, + "ram_quad_disable_opcode": 255, + "suppl_ram_quad_disable_opcode": 0, + "ram_octal_enable_opcode": 0, + "suppl_ram_octal_enable_opcode": 0, + "ram_octal_disable_opcode": 0, + "suppl_ram_octal_disable_opcode": 0 + } + } + }, + "external_memory_reporting": { + "header": { + "flash_auto_polling_enable": 1, + "flash_wel_enable": 1, + "flash_write_protect_enable": 0, + "flash_alternate_polling_conf_enable": 0, + "ram_auto_polling_enable": 1, + "ram_wel_enable": 1, + "ram_write_protect_enable": 0, + "ram_alternate_polling_conf_enable": 0 + }, + "flash_auto_polling": { + "flash_polling_repetition_delay": 0, + "flash_polling_count": 4, + "flash_enable_polling_expiration": 0, + "flash_polling_polarity": 0, + "flash_polling_address_phase_enable": 0, + "flash_polling_bit_index": 0, + "flash_numbers_poll_cycles": 65535, + "flash_dummy_autopoll_cycles": 0 + }, + "ram_auto_polling": { + "ram_polling_repetition_delay": 0, + "ram_polling_count": 4, + "ram_enable_polling_expiration": 0, + "ram_polling_polarity": 0, + "ram_polling_address_phase_enable": 0, + "ram_polling_bit_index": 0, + "ram_numbers_poll_cycles": 65535, + "ram_dummy_autopoll_cycles": 0 + }, + "flash_polling_command": { + "flash_polling_opcode": 5, + "suppl_flash_polling_opcode": 0 + }, + "ram_polling_command": { + "ram_polling_opcode": 5, + "suppl_ram_polling_opcode": 0 + }, + "flash_alternate_polling": { + "flash_polling_resp_count": 1023, + "flash_polling_iterations": 1, + "flash_polling_enabled": 0, + "flash_polling_disabled": 0, + "flash_grant_sel": 0, + "flash_data_for_enable_poling_conf_0": 0, + "flash_offset_bits_for_enable_poling_conf_0": 0, + "flash_stop_bit_for_enable_poling_conf_0": 1, + "flash_data_for_enable_poling_conf_1": 0, + "flash_offset_bits_for_enable_poling_conf_1": 0, + "flash_stop_bit_for_enable_poling_conf_1": 1, + "flash_data_for_disable_poling_conf_0": 0, + "flash_offset_bits_for_disable_poling_conf_0": 0, + "flash_stop_bit_for_disable_poling_conf_0": 1, + "flash_data_for_disable_poling_conf_1": 0, + "flash_offset_bits_for_disable_poling_conf_1": 0, + "flash_stop_bit_for_disable_poling_conf_1": 1 + }, + "ram_alternate_polling": { + "ram_polling_resp_count": 1023, + "ram_polling_iterations": 1, + "ram_polling_enabled": 0, + "ram_polling_disabled": 0, + "ram_grant_sel": 0, + "ram_data_for_enable_poling_conf_0": 0, + "ram_offset_bits_for_enable_poling_conf_0": 0, + "ram_stop_bit_for_enable_poling_conf_0": 1, + "ram_data_for_enable_poling_conf_1": 0, + "ram_offset_bits_for_enable_poling_conf_1": 0, + "ram_stop_bit_for_enable_poling_conf_1": 1, + "ram_data_for_disable_poling_conf_0": 0, + "ram_offset_bits_for_disable_poling_conf_0": 0, + "ram_stop_bit_for_disable_poling_conf_0": 1, + "ram_data_for_disable_poling_conf_1": 0, + "ram_offset_bits_for_disable_poling_conf_1": 0, + "ram_stop_bit_for_disable_poling_conf_1": 1 + }, + "flash_wel_command": { + "flash_wel_opcode": 6, + "suppl_flash_wel_opcode": 0 + }, + "ram_wel_command": { + "ram_wel_opcode": 6, + "suppl_ram_wel_opcode": 0 + } + }, + "event": { + "host_nvic_irq": 0, + "core_10_mux_sel": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/is25wj064f/flash_disc_param_ext_mem.json b/boards/ti/lp_em_cc35x1/config/flash/is25wj064f/flash_disc_param_ext_mem.json new file mode 100644 index 000000000000..6585853ccd5e --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/is25wj064f/flash_disc_param_ext_mem.json @@ -0,0 +1,99 @@ +{ + "vendor_primary_sbl": true, + "ti_wsoc_primary_container": true, + "ti_wsoc_bl2_primary_container": true, + "nvs_enable": true, + "vendor_alternate_image": true, + "vendor_sbl_alternate_image": true, + "ti_bl_alternate_image": true, + "ti_wsoc_alternate_image": true, + "ti_wsoc_bl2_alternate_image": true, + "region_0": { + "mem_region_0_start_phy_address": 2867200, + "mem_region_0_end_phy_address": 5627903, + "region0_boot": false, + "region0_main_code": true, + "region0_nvs": false, + "region0_wsoc_code": false, + "region0_alternate_code": false + }, + "region_1": { + "mem_region_1_start_phy_address": 0, + "mem_region_1_end_phy_address": 2867199, + "region1_boot": true, + "region1_main_code": false, + "region1_nvs": true, + "region1_wsoc_code": true, + "region1_alternate_code": false + }, + "region_2": { + "mem_region_2_start_phy_address": 5627904, + "mem_region_2_end_phy_address": 8388607, + "region2_boot": false, + "region2_main_code": false, + "region2_nvs": false, + "region2_wsoc_code": false, + "region2_alternate_code": true + }, + "region_3": { + "mem_region_3_start_phy_address": 0, + "mem_region_3_end_phy_address": 0, + "region3_boot": false, + "region3_main_code": false, + "region3_nvs": false, + "region3_wsoc_code": false, + "region3_alternate_code": false + }, + "boot_region_conf": { + "boot_region_size": 0, + "boot_region_flash_disco_param_start_address": 0, + "boot_region_primary_ti_bl_start_phy_address": 12284, + "boot_region_primary_ti_bl_magic": 0, + "boot_region_primary_ti_bl_major": 0, + "boot_region_primary_ti_bl_minor": 0, + "boot_region_sec_ti_bl_start_phy_address": 430076, + "boot_region_sec_ti_bl_magic": 0, + "boot_region_sec_ti_bl_major": 0, + "boot_region_sec_ti_bl_minor": 0 + }, + "main_code_region_conf": { + "main_code_region_vendor_image_start_phy_address": 2871292, + "main_code_region_vendor_image_magic": 0, + "main_code_region_vendor_image_major": 0, + "main_code_region_vendor_image_minor": 0, + "main_code_region_sbl_start_phy_address": 0, + "main_code_region_sbl_magic": 0, + "main_code_region_sbl_major": 0, + "main_code_region_sbl_minor": 0 + }, + "alt_code_region_conf": { + "alt_code_region_vendor_image_start_phy_address": 5631996, + "alt_code_region_vendor_image_magic": 0, + "alt_code_region_vendor_image_major": 0, + "alt_code_region_vendor_image_minor": 0, + "alt_code_region_sbl_start_phy_address": 0, + "alt_code_region_sbl_magic": 0, + "alt_code_region_sbl_major": 0, + "alt_code_region_sbl_minor": 0 + }, + "nvs_code_region_conf": { + "nvs_start_phy_address": 1777664, + "nvs_region_size": 1089536, + "nvs_region_primary_wsoc_start_phy_address": 847868, + "nvs_region_primary_wsoc_magic": 0, + "nvs_region_primary_wsoc_major": 0, + "nvs_region_primary_wsoc_minor": 0, + "nvs_region_sec_wsoc_start_phy_address": 1314812, + "nvs_region_sec_wsoc_magic": 0, + "nvs_region_sec_wsoc_major": 0, + "nvs_region_sec_wsoc_minor": 0, + "nvs_region_primary_wsoc_bl2_start_phy_address": 0, + "nvs_region_primary_wsoc_bl2_magic": 0, + "nvs_region_primary_wsoc_bl2_major": 0, + "nvs_region_primary_wsoc_bl2_minor": 0, + "nvs_region_sec_wsoc_bl2_start_phy_address": 0, + "nvs_region_sec_wsoc_bl2_magic": 0, + "nvs_region_sec_wsoc_bl2_major": 0, + "nvs_region_sec_wsoc_bl2_minor": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/is25wj064f/flash_disc_param_otfde.json b/boards/ti/lp_em_cc35x1/config/flash/is25wj064f/flash_disc_param_otfde.json new file mode 100644 index 000000000000..22a24d3d5430 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/is25wj064f/flash_disc_param_otfde.json @@ -0,0 +1,286 @@ +{ + "otfde_header": { + "name": "OTFDEWFF3", + "flash_only": true, + "ip_protection": false, + "regions_lock": false, + "regions_number": 4, + "flash_enabled": true + }, + "bl_conf": { + "host_boot_done_lock": true, + "host_peripherals_lock": true, + "icache_conf_lock": true, + "m33_mem_part_lock": true, + "memss_firewall_lock": true, + "dma_channel_owner_lock": true, + "otfde_region_lock": true, + "core_events_lock": true + }, + "otfde_general": { + "parameters": { + "mem_otfde_initial_delay": 10, + "otfde_global_watchdog_timer": 5 + }, + "events": { + "reset_evt_mask": false, + "reset_evt_suspend": false, + "sft_reset_evt_mask": false, + "sft_reset_evt_suspend": false, + "bypass_mode_evt_mask": false, + "bypass_mode_evt_suspend": false, + "debug_mode_evt_mask": false, + "debug_mode_evt_suspend": false, + "general_evt_mask": false, + "general_evt_suspend": false, + "xspi_data_path_evt_mask": false, + "xspi_data_path_evt_suspend": false, + "xspi_cnfg_path_evt_mask": false, + "xspi_cnfg_path_evt_suspend": false, + "xspi_service_interrupt_evt_mask": false, + "xspi_service_interrupt_evt_suspend": false, + "trans_device_disabled_evt_mask": false, + "trans_device_disabled_evt_suspend": false, + "trans_region_disabled_evt_mask": false, + "trans_region_disabled_evt_suspend": false, + "trans_region_params_conf_evt_mask": false, + "trans_region_params_conf_evt_suspend": false, + "trans_multiple_regions_mapped_evt_mask": false, + "trans_multiple_regions_mapped_evt_suspend": false, + "trans_address_not_32_bit_evt_mask": false, + "trans_address_not_32_bit_evt_suspend": false, + "trans_size_not_32_bit_evt_mask": false, + "trans_size_not_32_bit_evt_suspend": false, + "trans_burst_not_32_bit_evt_mask": false, + "trans_burst_not_32_bit_evt_suspend": false, + "region_read_write_def_evt_mask": false, + "region_read_write_def_evt_suspend": false, + "suspend_while_disabled_evt_mask": false, + "suspend_while_disabled_evt_suspend": false + } + }, + "regions_settings": { + "region_parameters_lock": { + "REGION_0_PARAMS_0": true, + "REGION_0_PARAMS_1": true, + "REGION_0_PARAMS_2": true, + "REGION_1_PARAMS_0": false, + "REGION_1_PARAMS_1": false, + "REGION_1_PARAMS_2": false, + "REGION_2_PARAMS_0": true, + "REGION_2_PARAMS_1": true, + "REGION_2_PARAMS_2": true, + "REGION_3_PARAMS_0": false, + "REGION_3_PARAMS_1": false, + "REGION_3_PARAMS_2": false + }, + "region_0_protection": { + "mem_region_0_enabled": true, + "mem_region_0_device_id": 0, + "mem_region_0_spi_write_enable": true, + "mem_region_0_spi_read_enable": true, + "mem_region_0_physical_offset": 700, + "mem_region_0_security_id_msb": 0, + "mem_region_0_start_address": 81920, + "mem_region_0_end_address": 82593, + "mem_region_0_security_id_lsb": 0, + "mem_otfde_region_0_write_lock_en": false, + "mem_otfde_region_0_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_1_protection": { + "mem_region_1_enabled": true, + "mem_region_1_device_id": 0, + "mem_region_1_spi_write_enable": true, + "mem_region_1_spi_read_enable": true, + "mem_region_1_physical_offset": 0, + "mem_region_1_security_id_msb": 0, + "mem_region_1_start_address": 655360, + "mem_region_1_end_address": 656059, + "mem_region_1_security_id_lsb": 0, + "mem_otfde_region_1_write_lock_en": false, + "mem_otfde_region_1_enc_dec_bypass": "Bypass" + }, + "region_2_protection": { + "mem_region_2_enabled": true, + "mem_region_2_device_id": 0, + "mem_region_2_spi_write_enable": true, + "mem_region_2_spi_read_enable": true, + "mem_region_2_physical_offset": 1374, + "mem_region_2_security_id_msb": 0, + "mem_region_2_start_address": 671744, + "mem_region_2_end_address": 672417, + "mem_region_2_security_id_lsb": 0, + "mem_otfde_region_2_write_lock_en": false, + "mem_otfde_region_2_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_3_protection": { + "mem_region_3_enabled": false, + "mem_region_3_device_id": 1, + "mem_region_3_spi_write_enable": true, + "mem_region_3_spi_read_enable": true, + "mem_region_3_physical_offset": 0, + "mem_region_3_security_id_msb": 0, + "mem_region_3_start_address": 1, + "mem_region_3_end_address": 0, + "mem_region_3_security_id_lsb": 0, + "mem_otfde_region_3_write_lock_en": false, + "mem_otfde_region_3_enc_dec_bypass": "Bypass" + } + }, + "devices": { + "header": { + "flash_device_switch_conf": 1, + "ram_device_switch_conf": 1 + }, + "flash_switch": { + "flash_grant_sel": 0, + "flash_data_for_conf_0": 2181562505, + "flash_offset_bits_for_conf_0": 0, + "flash_stop_bit_for_conf_0": 0, + "flash_data_for_conf_1": 67248651, + "flash_offset_bits_for_conf_1": 1, + "flash_stop_bit_for_conf_1": 0, + "flash_data_for_conf_2": 139266, + "flash_offset_bits_for_conf_2": 2, + "flash_stop_bit_for_conf_2": 0, + "flash_data_for_conf_3": 1, + "flash_offset_bits_for_conf_3": 4, + "flash_stop_bit_for_conf_3": 0, + "flash_data_for_conf_4": 1076887634, + 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"ram_stop_bit_for_conf_18": 1, + "ram_data_for_conf_19": 0, + "ram_offset_bits_for_conf_19": 0, + "ram_stop_bit_for_conf_19": 1, + "ram_data_for_conf_20": 0, + "ram_offset_bits_for_conf_20": 0, + "ram_stop_bit_for_conf_20": 1, + "ram_data_for_conf_21": 0, + "ram_offset_bits_for_conf_21": 0, + "ram_stop_bit_for_conf_21": 1, + "ram_data_for_conf_22": 0, + "ram_offset_bits_for_conf_22": 0, + "ram_stop_bit_for_conf_22": 1, + "ram_data_for_conf_23": 0, + "ram_offset_bits_for_conf_23": 0, + "ram_stop_bit_for_conf_23": 1 + } + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/is25wj064f/flash_disc_param_xspi.json b/boards/ti/lp_em_cc35x1/config/flash/is25wj064f/flash_disc_param_xspi.json new file mode 100644 index 000000000000..1c27fb760476 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/is25wj064f/flash_disc_param_xspi.json @@ -0,0 +1,485 @@ +{ + "xspi_header": { + "name": "xSPIWFF3", + "device": "CC3500", + "use_hardware": "IS25WJ064F", + "use_case": "Quadro", + "dqs_support": 0, + "flash_only": 1, + "flash_separate_reset": 0, + "ram_separate_reset": true, + "clock_frequency": 80, + "qospi_clock_divider": 1, + "flash_device_character_conf": 0, + "ram_device_character_conf": 0, + "header_advanced": 0, + "phy_mode_enable": 1, + "pipeline_mode_enable": 1, + "loopback_support": "No", + "qspi_ref_clock": 80, + "spi_clock_freq": 20, + "spi_clock_divider": 1, + "flash_device_size": 8, + "flash_bytes_per_block": 16, + "flash_bytes_per_page": 256, + "flash_number_of_address_bytes": 3, + "flash_dual_opcode": 0, + "flash_jedec_manufacturer_id": 0, + "flash_jedec_device_id": 0, + "flash_name": "IS25WJ064F", + "flash_page_size": 256, + "flash_sector_size": 4096, + "flash_cs_polarity": "ACTIVE_LOW", + "flash_sw_reset_type": "x1xxxx", + "ram_device_size": 8, + "ram_bytes_per_block": 16, + "ram_bytes_per_page": 256, + "ram_number_of_address_bytes": 3, + "ram_dual_opcode": 0, + "ram_jedec_manufacturer_id": 0, + "ram_jedec_device_id": 0, + "ram_name": "NO_PSRAM", + "ram_page_size": 256, + "ram_sector_size": 4096, + "ram_cs_polarity": "ACTIVE_LOW", + "ram_sw_reset_type": "x1xxxx", + "flash_write_operation_modes": "4S-4S-4S", + "flash_read_operation_modes": "4S-4S-4S", + "ram_write_operation_modes": "4S-4S-4S", + "ram_read_operation_modes": "4S-4S-4S", + "crc_enable": 0, + "enable_dtr": 0, + "enable_ahb_decoder": 0, + "enter_xip_mod_immediately": 0, + "enter_xip_mod_next_read": 0, + "ahb_address_remapping": 0, + "enable_dma": 0, + "select_decode": 0, + "legacy_ip_mode": 0, + "direct_access": 1 + }, + "xspi_pinmux": { + "xspi_clk_input": 44, + "xspi_clk_input_use_hw": 0, + "xspi_clk_input_mode": "Input", + "xspi_clk_input_pull": "None", + "xspi_clk_input_interrupt_trigger": "Low", + "xspi_clk_input_dont_conf": 0, + "xspi_clk_input_output_strength": "High", + "xspi_clk_input_initial_output_state": "High", + "xspi_clk": 24, + "xspi_clk_use_hw": "None", + "xspi_clk_mode": "Output", + "xspi_clk_pull": "None", + "xspi_clk_output_strength": "High", + "xspi_clk_initial_output_state": "High", + "xspi_clk_interrupt_trigger": "None", + "xspi_clk_dont_conf": 0, + "xspi_flash_cs": 20, + "xspi_flash_cs_use_hw": "None", + "xspi_flash_cs_mode": "Output", + "xspi_flash_cs_pull": "None", + "xspi_flash_cs_output_strength": "High", + "xspi_flash_cs_initial_output_state": "High", + "xspi_flash_cs_interrupt_trigger": "None", + "xspi_flash_cs_dont_conf": 0, + "xspi_data_0": 25, + "xspi_data_0_use_hw": "None", + "xspi_data_0_mode": "Input", + "xspi_data_0_pull": "None", + "xspi_data_0_output_strength": "High", + "xspi_data_0_initial_output_state": "High", + "xspi_data_0_interrupt_trigger": "Low", + "xspi_data_0_dont_conf": 0, + "xspi_data_1": 21, + "xspi_data_1_use_hw": "None", + "xspi_data_1_mode": "Input", + "xspi_data_1_pull": "None", + "xspi_data_1_output_strength": "High", + "xspi_data_1_initial_output_state": "High", + "xspi_data_1_interrupt_trigger": "Low", + "xspi_data_1_dont_conf": 0, + "xspi_data_2": 22, + "xspi_data_2_use_hw": "None", + "xspi_data_2_mode": "Input", + "xspi_data_2_pull": "None", + "xspi_data_2_output_strength": "High", + "xspi_data_2_initial_output_state": "High", + "xspi_data_2_interrupt_trigger": "Low", + "xspi_data_2_dont_conf": 0, + "xspi_data_3": 23, + "xspi_data_3_use_hw": "None", + "xspi_data_3_mode": "Input", + "xspi_data_3_pull": "None", + "xspi_data_3_output_strength": "High", + "xspi_data_3_initial_output_state": "High", + "xspi_data_3_interrupt_trigger": "Low", + "xspi_data_3_dont_conf": 0, + "xspi_data_4": 26, + "xspi_data_4_use_hw": "None", + "xspi_data_4_mode": "Input", + "xspi_data_4_pull": "None", + "xspi_data_4_output_strength": "High", + "xspi_data_4_initial_output_state": "High", + "xspi_data_4_interrupt_trigger": "None", + "xspi_data_4_dont_conf": 0, + "xspi_data_5": 27, + "xspi_data_5_use_hw": "None", + "xspi_data_5_mode": "Input", + "xspi_data_5_pull": "None", + "xspi_data_5_output_strength": "High", + "xspi_data_5_initial_output_state": "High", + "xspi_data_5_interrupt_trigger": "None", + "xspi_data_5_dont_conf": 0, + "xspi_data_6": 28, + "xspi_data_6_use_hw": "None", + "xspi_data_6_mode": "Input", + "xspi_data_6_pull": "None", + "xspi_data_6_output_strength": "High", + "xspi_data_6_initial_output_state": "High", + "xspi_data_6_interrupt_trigger": "None", + "xspi_data_6_dont_conf": 0, + "xspi_data_7": 29, + "xspi_data_7_use_hw": "None", + "xspi_data_7_mode": "Input", + "xspi_data_7_pull": "None", + "xspi_data_7_output_strength": "High", + "xspi_data_7_initial_output_state": "High", + "xspi_data_7_interrupt_trigger": "None", + "xspi_data_7_dont_conf": 0, + "xspi_reset_flash": 36, + "xspi_reset_flash_use_hw": "None", + "xspi_reset_flash_mode": "Output", + "xspi_reset_flash_pull": "None", + "xspi_reset_flash_output_strength": "High", + "xspi_reset_flash_initial_output_state": "High", + "xspi_reset_flash_interrupt_trigger": "None", + "xspi_reset_flash_dont_conf": 0, + "xspi_cs_ram": 3, + "xspi_cs_ram_use_hw": "None", + "xspi_cs_ram_mode": "Output", + "xspi_cs_ram_pull": "None", + "xspi_cs_ram_output_strength": "High", + "xspi_cs_ram_initial_output_state": "High", + "xspi_cs_ram_interrupt_trigger": "None", + "xspi_cs_ram_dont_conf": 0, + "xspi_dqs": 30, + "xspi_dqs_use_hw": "None", + "xspi_dqs_mode": "Input", + "xspi_dqs_pull": "None", + "xspi_dqs_output_strength": "High", + "xspi_dqs_initial_output_state": "High", + "xspi_dqs_interrupt_trigger": "None", + "xspi_dqs_dont_conf": 0, + "xspi_reset_ram": 2, + "xspi_reset_ram_use_hw": "None", + "xspi_reset_ram_mode": "Input", + "xspi_reset_ram_pull": "None", + "xspi_reset_ram_output_strength": "High", + "xspi_reset_ram_initial_output_state": "High", + "xspi_reset_ram_interrupt_trigger": "None", + "xspi_reset_ram_dont_conf": 0 + }, + "xspi_operations": { + "xspi_operations_clocks": { + "clock_phase": 0, + "clock_polarity": 0, + "spi_mode": "2'b00" + }, + "xspi_operations_chip_select": { + "csda": 2, + "csdads": 0, + "cseot": 4, + "cssot": 1 + }, + "xspi_operations_reset": { + "flash_jedec_reset": 0, + "ram_jedec_reset": 0, + "flash_treset": 20, + "ram_treset": 20 + }, + "xspi_phy_operations": { + "flash_rx_dll_bypass_bit": 0, + "flash_dll_tx_delay": 22, + "flash_dll_rx_delay": 34, + "ram_rx_dll_bypass_bit": 0, + "ram_dll_tx_delay": 22, + "ram_dll_rx_delay": 34 + }, + "xspi_read_operations": { + "flash_dummy_rd_cycles": 4, + "flash_read_opcode": 11, + "suppl_flash_read_opcode": 0, + "ram_dummy_rd_cycles": 4, + "ram_read_opcode": 11, + "suppl_ram_read_opcode": 0, + "flash_non_cont_read_enable": 0, + "flash_max_read_jobs": 256, + "ram_non_cont_read_enable": 0, + "ram_max_read_jobs": 256, + "rww_en": 0, + "device_size": 8, + "number_of_banks": 1, + "bank_size": 8, + "mode_bit_enable": 0 + }, + "xspi_write_operations": { + "flash_address_and_data": { + "flash_dummy_wr_cycles": 0 + }, + "flash_command": { + "flash_write_opcode": 2, + "suppl_flash_write_opcode": 0 + }, + "ram_address_and_data": { + "ram_dummy_wr_cycles": 0 + }, + "ram_command": { + "ram_write_opcode": 2, + "suppl_ram_write_opcode": 0 + }, + "write_to_buffer": { + "flash_write_to_buffer_support": 0, + "ram_write_to_buffer_support": 0 + }, + "non_continuous_write": { + "flash_non_cont_write_enable": 0, + "flash_max_write_jobs": 64, + "ram_non_cont_write_enable": 0, + "ram_max_write_jobs": 0 + }, + "flash_program_operation": { + "flash_min_program_size": "256 B", + "flash_program_opcode": 2, + "suppl_flash_program_opcode": 0, + "flash_maximum_program_time_limit": 1600 + }, + "flash_erase_operation": { + "flash_min_erase_size": "4 kB", + "flash_erase_opcode": 32, + "suppl_flash_erase_opcode": 0, + "flash_maximum_erase_time_limit": 4095 + }, + "flash_erase_conf": { + "flash_block_erase_opcode": 0, + "suppl_block_flash_erase_opcode": 0, + "flash_sector_erase_opcode": 0, + "suppl_sector_flash_erase_opcode": 0, + "flash_chip_erase_opcode": 0, + "suppl_chip_flash_erase_opcode": 0 + }, + "ram_program_operation": { + "ram_min_program_size": "256 B", + "ram_program_opcode": 2, + "suppl_ram_program_opcode": 0, + "ram_maximum_program_time_limit": 1600 + }, + "ram_erase_conf": { + "ram_block_erase_opcode": 0, + "suppl_block_ram_erase_opcode": 0, + "ram_sector_erase_opcode": 0, + "suppl_sector_ram_erase_opcode": 0, + "ram_chip_erase_opcode": 0, + "suppl_chip_ram_erase_opcode": 0 + }, + "flash_buffer_support": { + "flash_pre_write_sequence": 0, + "flash_post_write_sequence": 0, + "flash_write_protection_timer_en": 0, + "flash_write_buffer_timer_mode": 16, + "flash_write_buffer_timer_range": 0, + "flash_service_interrupt_criteria": 0 + }, + "ram_buffer_support": { + "ram_pre_write_sequence": 0, + "ram_post_write_sequence": 0, + "ram_write_protection_timer_en": 0, + "ram_write_buffer_timer_mode": 16, + "ram_write_buffer_timer_range": 0, + "ram_service_interrupt_criteria": 0 + }, + "flash_pre_write_conf": { + "flash_pre_write_job_done_grant_sel": 0, + "data_for_flash_pre_write_conf_0": 0, + "offset_bits_for_flash_pre_write_conf_0": 0, + "stop_bit_for_flash_pre_write_conf_0": 1, + "data_for_flash_pre_write_conf_1": 0, + "offset_bits_for_flash_pre_write_conf_1": 0 + }, + "flash_post_write_conf": { + "flash_post_write_job_done_grant_sel": 0, + "data_for_flash_post_write_conf_0": 0, + "offset_bits_for_flash_post_write_conf_0": 0, + "stop_bit_for_flash_post_write_conf_0": 1, + "data_for_flash_post_write_conf_1": 0, + "offset_bits_for_flash_post_write_conf_1": 0 + }, + "ram_pre_write_conf": { + "ram_pre_write_job_done_grant_sel": 0, + "data_for_ram_pre_write_conf_0": 0, + "offset_bits_for_ram_pre_write_conf_0": 0, + "stop_bit_for_ram_pre_write_conf_0": 1, + "data_for_ram_pre_write_conf_1": 0, + "offset_bits_for_ram_pre_write_conf_1": 0 + }, + "ram_post_write_conf": { + "ram_post_write_job_done_grant_sel": 0, + "data_for_ram_post_write_conf_0": 0, + "offset_bits_for_ram_post_write_conf_0": 0, + "stop_bit_for_ram_post_write_conf_0": 1, + "data_for_ram_post_write_conf_1": 0, + "offset_bits_for_ram_post_write_conf_1": 0 + } + }, + "xspi_capture_operations": { + "read_data_capture": { + "flash_delay_transmitted_data": 0, + "flash_loopback_clock": 0, + "flash_bypass_adapted_loopback": 1, + "flash_sample_edge_sel": 0, + "ram_delay_transmitted_data": 0, + "ram_loopback_clock": 0, + "ram_bypass_adapted_loopback": 1, + "ram_sample_edge_sel": 0 + }, + "delays": { + "flash_full_half_cycle_delay": 0, + "flash_dll_bypass_mode": 1, + "flash_phase_detect_sel": 0, + "flash_dll_lock_num": 0, + "flash_dll_start_point": 0, + "flash_loopback_clock": 0, + "ram_full_half_cycle_delay": 0, + "ram_dll_bypass_mode": 1, + "ram_phase_detect_sel": 0, + "ram_dll_lock_num": 0, + "ram_dll_start_point": 0, + "ram_loopback_clock": 0 + }, + "operation_modes": { + "flash_sfdp_support": 0, + "ram_sfdp_support": 0, + "flash_pm_support": 0, + "ram_pm_support": 0, + "flash_sfdp_opcode": 0, + "suppl_flash_sfdp_opcode": 0, + "ram_sfdp_opcode": 0, + "suppl_ram_sfdp_opcode": 0, + "flash_enter_dpd_opcode": 185, + "suppl_flash_enter_dpd_opcode": 0, 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"ram_auto_polling_enable": 1, + "ram_wel_enable": 1, + "ram_write_protect_enable": 0, + "ram_alternate_polling_conf_enable": 0 + }, + "flash_auto_polling": { + "flash_polling_repetition_delay": 0, + "flash_polling_count": 4, + "flash_enable_polling_expiration": 0, + "flash_polling_polarity": 0, + "flash_polling_address_phase_enable": 0, + "flash_polling_bit_index": 0, + "flash_numbers_poll_cycles": 65535, + "flash_dummy_autopoll_cycles": 0 + }, + "ram_auto_polling": { + "ram_polling_repetition_delay": 0, + "ram_polling_count": 4, + "ram_enable_polling_expiration": 0, + "ram_polling_polarity": 0, + "ram_polling_address_phase_enable": 0, + "ram_polling_bit_index": 0, + "ram_numbers_poll_cycles": 65535, + "ram_dummy_autopoll_cycles": 0 + }, + "flash_polling_command": { + "flash_polling_opcode": 5, + "suppl_flash_polling_opcode": 0 + }, + "ram_polling_command": { + "ram_polling_opcode": 5, + "suppl_ram_polling_opcode": 0 + }, + "flash_alternate_polling": { + "flash_polling_resp_count": 1023, + "flash_polling_iterations": 1, + "flash_polling_enabled": 0, + "flash_polling_disabled": 0, + "flash_grant_sel": 0, + "flash_data_for_enable_poling_conf_0": 0, + "flash_offset_bits_for_enable_poling_conf_0": 0, + "flash_stop_bit_for_enable_poling_conf_0": 1, + "flash_data_for_enable_poling_conf_1": 0, + "flash_offset_bits_for_enable_poling_conf_1": 0, + "flash_stop_bit_for_enable_poling_conf_1": 1, + "flash_data_for_disable_poling_conf_0": 0, + "flash_offset_bits_for_disable_poling_conf_0": 0, + "flash_stop_bit_for_disable_poling_conf_0": 1, + "flash_data_for_disable_poling_conf_1": 0, + "flash_offset_bits_for_disable_poling_conf_1": 0, + "flash_stop_bit_for_disable_poling_conf_1": 1 + }, + "ram_alternate_polling": { + "ram_polling_resp_count": 1023, + "ram_polling_iterations": 1, + "ram_polling_enabled": 0, + "ram_polling_disabled": 0, + "ram_grant_sel": 0, + "ram_data_for_enable_poling_conf_0": 0, + "ram_offset_bits_for_enable_poling_conf_0": 0, + "ram_stop_bit_for_enable_poling_conf_0": 1, + "ram_data_for_enable_poling_conf_1": 0, + "ram_offset_bits_for_enable_poling_conf_1": 0, + "ram_stop_bit_for_enable_poling_conf_1": 1, + "ram_data_for_disable_poling_conf_0": 0, + "ram_offset_bits_for_disable_poling_conf_0": 0, + "ram_stop_bit_for_disable_poling_conf_0": 1, + "ram_data_for_disable_poling_conf_1": 0, + "ram_offset_bits_for_disable_poling_conf_1": 0, + "ram_stop_bit_for_disable_poling_conf_1": 1 + }, + "flash_wel_command": { + "flash_wel_opcode": 6, + "suppl_flash_wel_opcode": 0 + }, + "ram_wel_command": { + "ram_wel_opcode": 6, + "suppl_ram_wel_opcode": 0 + } + }, + "event": { + "host_nvic_irq": 0, + "core_10_mux_sel": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/is25wj128f/flash_disc_param_ext_mem.json b/boards/ti/lp_em_cc35x1/config/flash/is25wj128f/flash_disc_param_ext_mem.json new file mode 100644 index 000000000000..14d05d9aba5a --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/is25wj128f/flash_disc_param_ext_mem.json @@ -0,0 +1,99 @@ +{ + "vendor_primary_sbl": true, + "ti_wsoc_primary_container": true, + "ti_wsoc_bl2_primary_container": true, + "nvs_enable": true, + "vendor_alternate_image": true, + "vendor_sbl_alternate_image": true, + "ti_bl_alternate_image": true, + "ti_wsoc_alternate_image": true, + "ti_wsoc_bl2_alternate_image": true, + "region_0": { + "mem_region_0_start_phy_address": 2867200, + "mem_region_0_end_phy_address": 9822207, + "region0_boot": false, + "region0_main_code": true, + "region0_nvs": false, + "region0_wsoc_code": false, + "region0_alternate_code": false + }, + "region_1": { + "mem_region_1_start_phy_address": 0, + "mem_region_1_end_phy_address": 2867199, + "region1_boot": true, + "region1_main_code": false, + "region1_nvs": true, + "region1_wsoc_code": true, + "region1_alternate_code": false + }, + "region_2": { + "mem_region_2_start_phy_address": 9822208, + "mem_region_2_end_phy_address": 16777215, + "region2_boot": false, + "region2_main_code": false, + "region2_nvs": false, + "region2_wsoc_code": false, + "region2_alternate_code": true + }, + "region_3": { + "mem_region_3_start_phy_address": 0, + "mem_region_3_end_phy_address": 0, + "region3_boot": false, + "region3_main_code": false, + "region3_nvs": false, + "region3_wsoc_code": false, + "region3_alternate_code": false + }, + "boot_region_conf": { + "boot_region_size": 0, + "boot_region_flash_disco_param_start_address": 0, + "boot_region_primary_ti_bl_start_phy_address": 12284, + "boot_region_primary_ti_bl_magic": 0, + "boot_region_primary_ti_bl_major": 0, + "boot_region_primary_ti_bl_minor": 0, + "boot_region_sec_ti_bl_start_phy_address": 430076, + "boot_region_sec_ti_bl_magic": 0, + "boot_region_sec_ti_bl_major": 0, + "boot_region_sec_ti_bl_minor": 0 + }, + "main_code_region_conf": { + "main_code_region_vendor_image_start_phy_address": 2871292, + "main_code_region_vendor_image_magic": 0, + "main_code_region_vendor_image_major": 0, + "main_code_region_vendor_image_minor": 0, + "main_code_region_sbl_start_phy_address": 0, + "main_code_region_sbl_magic": 0, + "main_code_region_sbl_major": 0, + "main_code_region_sbl_minor": 0 + }, + "alt_code_region_conf": { + "alt_code_region_vendor_image_start_phy_address": 9826300, + "alt_code_region_vendor_image_magic": 0, + "alt_code_region_vendor_image_major": 0, + "alt_code_region_vendor_image_minor": 0, + "alt_code_region_sbl_start_phy_address": 0, + "alt_code_region_sbl_magic": 0, + "alt_code_region_sbl_major": 0, + "alt_code_region_sbl_minor": 0 + }, + "nvs_code_region_conf": { + "nvs_start_phy_address": 1777664, + "nvs_region_size": 1089536, + "nvs_region_primary_wsoc_start_phy_address": 847868, + "nvs_region_primary_wsoc_magic": 0, + "nvs_region_primary_wsoc_major": 0, + "nvs_region_primary_wsoc_minor": 0, + "nvs_region_sec_wsoc_start_phy_address": 1314812, + "nvs_region_sec_wsoc_magic": 0, + "nvs_region_sec_wsoc_major": 0, + "nvs_region_sec_wsoc_minor": 0, + "nvs_region_primary_wsoc_bl2_start_phy_address": 0, + "nvs_region_primary_wsoc_bl2_magic": 0, + "nvs_region_primary_wsoc_bl2_major": 0, + "nvs_region_primary_wsoc_bl2_minor": 0, + "nvs_region_sec_wsoc_bl2_start_phy_address": 0, + "nvs_region_sec_wsoc_bl2_magic": 0, + "nvs_region_sec_wsoc_bl2_major": 0, + "nvs_region_sec_wsoc_bl2_minor": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/is25wj128f/flash_disc_param_otfde.json b/boards/ti/lp_em_cc35x1/config/flash/is25wj128f/flash_disc_param_otfde.json new file mode 100644 index 000000000000..a39371a15d7d --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/is25wj128f/flash_disc_param_otfde.json @@ -0,0 +1,286 @@ +{ + "otfde_header": { + "name": "OTFDEWFF3", + "flash_only": true, + "ip_protection": false, + "regions_lock": false, + "regions_number": 4, + "flash_enabled": true + }, + "bl_conf": { + "host_boot_done_lock": true, + "host_peripherals_lock": true, + "icache_conf_lock": true, + "m33_mem_part_lock": true, + "memss_firewall_lock": true, + "dma_channel_owner_lock": true, + "otfde_region_lock": true, + "core_events_lock": true + }, + "otfde_general": { + "parameters": { + "mem_otfde_initial_delay": 10, + "otfde_global_watchdog_timer": 5 + }, + "events": { + "reset_evt_mask": false, + "reset_evt_suspend": false, + "sft_reset_evt_mask": false, + "sft_reset_evt_suspend": false, + "bypass_mode_evt_mask": false, + "bypass_mode_evt_suspend": false, + "debug_mode_evt_mask": false, + "debug_mode_evt_suspend": false, + "general_evt_mask": false, + "general_evt_suspend": false, + "xspi_data_path_evt_mask": false, + "xspi_data_path_evt_suspend": false, + "xspi_cnfg_path_evt_mask": false, + "xspi_cnfg_path_evt_suspend": false, + "xspi_service_interrupt_evt_mask": false, + "xspi_service_interrupt_evt_suspend": false, + "trans_device_disabled_evt_mask": false, + "trans_device_disabled_evt_suspend": false, + "trans_region_disabled_evt_mask": false, + "trans_region_disabled_evt_suspend": false, + "trans_region_params_conf_evt_mask": false, + "trans_region_params_conf_evt_suspend": false, + "trans_multiple_regions_mapped_evt_mask": false, + "trans_multiple_regions_mapped_evt_suspend": false, + "trans_address_not_32_bit_evt_mask": false, + "trans_address_not_32_bit_evt_suspend": false, + "trans_size_not_32_bit_evt_mask": false, + "trans_size_not_32_bit_evt_suspend": false, + "trans_burst_not_32_bit_evt_mask": false, + "trans_burst_not_32_bit_evt_suspend": false, + "region_read_write_def_evt_mask": false, + "region_read_write_def_evt_suspend": false, + "suspend_while_disabled_evt_mask": false, + "suspend_while_disabled_evt_suspend": false + } + }, + "regions_settings": { + "region_parameters_lock": { + "REGION_0_PARAMS_0": true, + "REGION_0_PARAMS_1": true, + "REGION_0_PARAMS_2": true, + "REGION_1_PARAMS_0": false, + "REGION_1_PARAMS_1": false, + "REGION_1_PARAMS_2": false, + "REGION_2_PARAMS_0": true, + "REGION_2_PARAMS_1": true, + "REGION_2_PARAMS_2": true, + "REGION_3_PARAMS_0": false, + "REGION_3_PARAMS_1": false, + "REGION_3_PARAMS_2": false + }, + "region_0_protection": { + "mem_region_0_enabled": true, + "mem_region_0_device_id": 0, + "mem_region_0_spi_write_enable": true, + "mem_region_0_spi_read_enable": true, + "mem_region_0_physical_offset": 700, + "mem_region_0_security_id_msb": 0, + "mem_region_0_start_address": 81920, + "mem_region_0_end_address": 83617, + "mem_region_0_security_id_lsb": 0, + "mem_otfde_region_0_write_lock_en": false, + "mem_otfde_region_0_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_1_protection": { + "mem_region_1_enabled": true, + "mem_region_1_device_id": 0, + "mem_region_1_spi_write_enable": true, + "mem_region_1_spi_read_enable": true, + "mem_region_1_physical_offset": 0, + "mem_region_1_security_id_msb": 0, + "mem_region_1_start_address": 655360, + "mem_region_1_end_address": 656059, + "mem_region_1_security_id_lsb": 0, + "mem_otfde_region_1_write_lock_en": false, + "mem_otfde_region_1_enc_dec_bypass": "Bypass" + }, + "region_2_protection": { + "mem_region_2_enabled": true, + "mem_region_2_device_id": 0, + "mem_region_2_spi_write_enable": true, + "mem_region_2_spi_read_enable": true, + "mem_region_2_physical_offset": 2398, + "mem_region_2_security_id_msb": 0, + "mem_region_2_start_address": 671744, + "mem_region_2_end_address": 673441, + "mem_region_2_security_id_lsb": 0, + "mem_otfde_region_2_write_lock_en": false, + "mem_otfde_region_2_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_3_protection": { + "mem_region_3_enabled": false, + "mem_region_3_device_id": 1, + "mem_region_3_spi_write_enable": true, + "mem_region_3_spi_read_enable": true, + "mem_region_3_physical_offset": 0, + "mem_region_3_security_id_msb": 0, + "mem_region_3_start_address": 1, + "mem_region_3_end_address": 0, + "mem_region_3_security_id_lsb": 0, + "mem_otfde_region_3_write_lock_en": false, + "mem_otfde_region_3_enc_dec_bypass": "Bypass" + } + }, + "devices": { + "header": { + "flash_device_switch_conf": 1, + "ram_device_switch_conf": 1 + }, + "flash_switch": { + "flash_grant_sel": 0, + "flash_data_for_conf_0": 2181562505, + "flash_offset_bits_for_conf_0": 0, + "flash_stop_bit_for_conf_0": 0, + "flash_data_for_conf_1": 100803083, + "flash_offset_bits_for_conf_1": 1, + "flash_stop_bit_for_conf_1": 0, + "flash_data_for_conf_2": 139266, + "flash_offset_bits_for_conf_2": 2, + "flash_stop_bit_for_conf_2": 0, + "flash_data_for_conf_3": 1, + "flash_offset_bits_for_conf_3": 4, + "flash_stop_bit_for_conf_3": 0, + "flash_data_for_conf_4": 1076887634, + "flash_offset_bits_for_conf_4": 45, + "flash_stop_bit_for_conf_4": 0, + "flash_data_for_conf_5": 3224371282, + "flash_offset_bits_for_conf_5": 45, + "flash_stop_bit_for_conf_5": 0, + "flash_data_for_conf_6": 262149, + "flash_offset_bits_for_conf_6": 14, + "flash_stop_bit_for_conf_6": 0, + "flash_data_for_conf_7": 0, + "flash_offset_bits_for_conf_7": 44, + "flash_stop_bit_for_conf_7": 1, + "flash_data_for_conf_8": 0, + "flash_offset_bits_for_conf_8": 0, + "flash_stop_bit_for_conf_8": 1, + "flash_data_for_conf_9": 0, + "flash_offset_bits_for_conf_9": 0, + "flash_stop_bit_for_conf_9": 1, + "flash_data_for_conf_10": 0, + "flash_offset_bits_for_conf_10": 0, + "flash_stop_bit_for_conf_10": 1, + "flash_data_for_conf_11": 0, + "flash_offset_bits_for_conf_11": 0, + "flash_stop_bit_for_conf_11": 1, + "flash_data_for_conf_12": 0, + "flash_offset_bits_for_conf_12": 0, + "flash_stop_bit_for_conf_12": 1, + "flash_data_for_conf_13": 0, + "flash_offset_bits_for_conf_13": 0, + "flash_stop_bit_for_conf_13": 1, + "flash_data_for_conf_14": 0, + "flash_offset_bits_for_conf_14": 0, + "flash_stop_bit_for_conf_14": 1, + "flash_data_for_conf_15": 0, + "flash_offset_bits_for_conf_15": 0, + "flash_stop_bit_for_conf_15": 1, + "flash_data_for_conf_16": 0, + "flash_offset_bits_for_conf_16": 0, + "flash_stop_bit_for_conf_16": 1, + "flash_data_for_conf_17": 0, + "flash_offset_bits_for_conf_17": 0, + "flash_stop_bit_for_conf_17": 1, + "flash_data_for_conf_18": 0, + "flash_offset_bits_for_conf_18": 0, + "flash_stop_bit_for_conf_18": 1, + "flash_data_for_conf_19": 0, + "flash_offset_bits_for_conf_19": 0, + "flash_stop_bit_for_conf_19": 1, + "flash_data_for_conf_20": 0, + "flash_offset_bits_for_conf_20": 0, + "flash_stop_bit_for_conf_20": 1, + "flash_data_for_conf_21": 0, + "flash_offset_bits_for_conf_21": 0, + "flash_stop_bit_for_conf_21": 1, + "flash_data_for_conf_22": 0, + "flash_offset_bits_for_conf_22": 0, + "flash_stop_bit_for_conf_22": 1, + "flash_data_for_conf_23": 0, + "flash_offset_bits_for_conf_23": 0, + "flash_stop_bit_for_conf_23": 1 + }, + "ram_switch": { + "ram_grant_sel": 0, + "ram_data_for_conf_0": 2181562505, + "ram_offset_bits_for_conf_0": 0, + "ram_stop_bit_for_conf_0": 0, + "ram_data_for_conf_1": 67248651, + "ram_offset_bits_for_conf_1": 1, + "ram_stop_bit_for_conf_1": 0, + "ram_data_for_conf_2": 139266, + "ram_offset_bits_for_conf_2": 2, + "ram_stop_bit_for_conf_2": 0, + "ram_data_for_conf_3": 1, + "ram_offset_bits_for_conf_3": 4, + "ram_stop_bit_for_conf_3": 0, + "ram_data_for_conf_4": 1076887634, + "ram_offset_bits_for_conf_4": 45, + "ram_stop_bit_for_conf_4": 0, + "ram_data_for_conf_5": 3224371282, + "ram_offset_bits_for_conf_5": 45, + "ram_stop_bit_for_conf_5": 0, + "ram_data_for_conf_6": 262149, + "ram_offset_bits_for_conf_6": 14, + "ram_stop_bit_for_conf_6": 0, + "ram_data_for_conf_7": 0, + "ram_offset_bits_for_conf_7": 44, + "ram_stop_bit_for_conf_7": 1, + "ram_data_for_conf_8": 0, + "ram_offset_bits_for_conf_8": 0, + "ram_stop_bit_for_conf_8": 1, + "ram_data_for_conf_9": 0, + "ram_offset_bits_for_conf_9": 0, + "ram_stop_bit_for_conf_9": 1, + "ram_data_for_conf_10": 0, + "ram_offset_bits_for_conf_10": 0, + "ram_stop_bit_for_conf_10": 1, + "ram_data_for_conf_11": 0, + "ram_offset_bits_for_conf_11": 0, + "ram_stop_bit_for_conf_11": 1, + "ram_data_for_conf_12": 0, + "ram_offset_bits_for_conf_12": 0, + "ram_stop_bit_for_conf_12": 1, + "ram_data_for_conf_13": 0, + "ram_offset_bits_for_conf_13": 0, + "ram_stop_bit_for_conf_13": 1, + "ram_data_for_conf_14": 0, + "ram_offset_bits_for_conf_14": 0, + "ram_stop_bit_for_conf_14": 1, + "ram_data_for_conf_15": 0, + "ram_offset_bits_for_conf_15": 0, + "ram_stop_bit_for_conf_15": 1, + "ram_data_for_conf_16": 0, + "ram_offset_bits_for_conf_16": 0, + "ram_stop_bit_for_conf_16": 1, + "ram_data_for_conf_17": 0, + "ram_offset_bits_for_conf_17": 0, + "ram_stop_bit_for_conf_17": 1, + "ram_data_for_conf_18": 0, + "ram_offset_bits_for_conf_18": 0, + "ram_stop_bit_for_conf_18": 1, + "ram_data_for_conf_19": 0, + "ram_offset_bits_for_conf_19": 0, + "ram_stop_bit_for_conf_19": 1, + "ram_data_for_conf_20": 0, + "ram_offset_bits_for_conf_20": 0, + "ram_stop_bit_for_conf_20": 1, + "ram_data_for_conf_21": 0, + "ram_offset_bits_for_conf_21": 0, + "ram_stop_bit_for_conf_21": 1, + "ram_data_for_conf_22": 0, + "ram_offset_bits_for_conf_22": 0, + "ram_stop_bit_for_conf_22": 1, + "ram_data_for_conf_23": 0, + "ram_offset_bits_for_conf_23": 0, + "ram_stop_bit_for_conf_23": 1 + } + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/is25wj128f/flash_disc_param_xspi.json b/boards/ti/lp_em_cc35x1/config/flash/is25wj128f/flash_disc_param_xspi.json new file mode 100644 index 000000000000..d5e12d823532 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/is25wj128f/flash_disc_param_xspi.json @@ -0,0 +1,485 @@ +{ + "xspi_header": { + "name": "xSPIWFF3", + "device": "CC3500", + "use_hardware": "IS25WJ128F", + "use_case": "Quadro", + "dqs_support": 0, + "flash_only": 1, + "flash_separate_reset": 0, + "ram_separate_reset": true, + "clock_frequency": 80, + "qospi_clock_divider": 1, + "flash_device_character_conf": 0, + "ram_device_character_conf": 0, + "header_advanced": 0, + "phy_mode_enable": 1, + "pipeline_mode_enable": 1, + "loopback_support": "No", + "qspi_ref_clock": 80, + "spi_clock_freq": 20, + "spi_clock_divider": 1, + "flash_device_size": 16, + "flash_bytes_per_block": 16, + "flash_bytes_per_page": 256, + "flash_number_of_address_bytes": 3, + "flash_dual_opcode": 0, + "flash_jedec_manufacturer_id": 0, + "flash_jedec_device_id": 0, + "flash_name": "IS25WJ128F", + "flash_page_size": 256, + "flash_sector_size": 4096, + "flash_cs_polarity": "ACTIVE_LOW", + "flash_sw_reset_type": "x1xxxx", + "ram_device_size": 8, + "ram_bytes_per_block": 16, + "ram_bytes_per_page": 256, + "ram_number_of_address_bytes": 3, + "ram_dual_opcode": 0, + "ram_jedec_manufacturer_id": 0, + "ram_jedec_device_id": 0, + "ram_name": "NO_PSRAM", + "ram_page_size": 256, + "ram_sector_size": 4096, + "ram_cs_polarity": "ACTIVE_LOW", + "ram_sw_reset_type": "x1xxxx", + "flash_write_operation_modes": "4S-4S-4S", + "flash_read_operation_modes": "4S-4S-4S", + "ram_write_operation_modes": "4S-4S-4S", + "ram_read_operation_modes": "4S-4S-4S", + "crc_enable": 0, + "enable_dtr": 0, + "enable_ahb_decoder": 0, + "enter_xip_mod_immediately": 0, + "enter_xip_mod_next_read": 0, + "ahb_address_remapping": 0, + "enable_dma": 0, + "select_decode": 0, + "legacy_ip_mode": 0, + "direct_access": 1 + }, + "xspi_pinmux": { + "xspi_clk_input": 44, + "xspi_clk_input_use_hw": 0, + "xspi_clk_input_mode": "Input", + "xspi_clk_input_pull": "None", + "xspi_clk_input_interrupt_trigger": "Low", + "xspi_clk_input_dont_conf": 0, + "xspi_clk_input_output_strength": "High", + "xspi_clk_input_initial_output_state": "High", + "xspi_clk": 24, + "xspi_clk_use_hw": "None", + "xspi_clk_mode": "Output", + "xspi_clk_pull": "None", + "xspi_clk_output_strength": "High", + "xspi_clk_initial_output_state": "High", + "xspi_clk_interrupt_trigger": "None", + "xspi_clk_dont_conf": 0, + "xspi_flash_cs": 20, + "xspi_flash_cs_use_hw": "None", + "xspi_flash_cs_mode": "Output", + "xspi_flash_cs_pull": "None", + "xspi_flash_cs_output_strength": "High", + "xspi_flash_cs_initial_output_state": "High", + "xspi_flash_cs_interrupt_trigger": "None", + "xspi_flash_cs_dont_conf": 0, + "xspi_data_0": 25, + "xspi_data_0_use_hw": "None", + "xspi_data_0_mode": "Input", + "xspi_data_0_pull": "None", + "xspi_data_0_output_strength": "High", + "xspi_data_0_initial_output_state": "High", + "xspi_data_0_interrupt_trigger": "Low", + "xspi_data_0_dont_conf": 0, + "xspi_data_1": 21, + "xspi_data_1_use_hw": "None", + "xspi_data_1_mode": "Input", + "xspi_data_1_pull": "None", + "xspi_data_1_output_strength": "High", + "xspi_data_1_initial_output_state": "High", + "xspi_data_1_interrupt_trigger": "Low", + "xspi_data_1_dont_conf": 0, + "xspi_data_2": 22, + "xspi_data_2_use_hw": "None", + "xspi_data_2_mode": "Input", + "xspi_data_2_pull": "None", + "xspi_data_2_output_strength": "High", + "xspi_data_2_initial_output_state": "High", + "xspi_data_2_interrupt_trigger": "Low", + "xspi_data_2_dont_conf": 0, + "xspi_data_3": 23, + "xspi_data_3_use_hw": "None", + "xspi_data_3_mode": "Input", + "xspi_data_3_pull": "None", + "xspi_data_3_output_strength": "High", + "xspi_data_3_initial_output_state": "High", + "xspi_data_3_interrupt_trigger": "Low", + "xspi_data_3_dont_conf": 0, + "xspi_data_4": 26, + "xspi_data_4_use_hw": "None", + "xspi_data_4_mode": "Input", + "xspi_data_4_pull": "None", + "xspi_data_4_output_strength": "High", + "xspi_data_4_initial_output_state": "High", + "xspi_data_4_interrupt_trigger": "None", + "xspi_data_4_dont_conf": 0, + "xspi_data_5": 27, + "xspi_data_5_use_hw": "None", + "xspi_data_5_mode": "Input", + "xspi_data_5_pull": "None", + "xspi_data_5_output_strength": "High", + "xspi_data_5_initial_output_state": "High", + "xspi_data_5_interrupt_trigger": "None", + "xspi_data_5_dont_conf": 0, + "xspi_data_6": 28, + "xspi_data_6_use_hw": "None", + "xspi_data_6_mode": "Input", + "xspi_data_6_pull": "None", + "xspi_data_6_output_strength": "High", + "xspi_data_6_initial_output_state": "High", + "xspi_data_6_interrupt_trigger": "None", + "xspi_data_6_dont_conf": 0, + "xspi_data_7": 29, + "xspi_data_7_use_hw": "None", + "xspi_data_7_mode": "Input", + "xspi_data_7_pull": "None", + "xspi_data_7_output_strength": "High", + "xspi_data_7_initial_output_state": "High", + "xspi_data_7_interrupt_trigger": "None", + "xspi_data_7_dont_conf": 0, + "xspi_reset_flash": 36, + "xspi_reset_flash_use_hw": "None", + "xspi_reset_flash_mode": "Output", + "xspi_reset_flash_pull": "None", + "xspi_reset_flash_output_strength": "High", + "xspi_reset_flash_initial_output_state": "High", + "xspi_reset_flash_interrupt_trigger": "None", + "xspi_reset_flash_dont_conf": 0, + "xspi_cs_ram": 3, + "xspi_cs_ram_use_hw": "None", + "xspi_cs_ram_mode": "Output", + "xspi_cs_ram_pull": "None", + "xspi_cs_ram_output_strength": "High", + "xspi_cs_ram_initial_output_state": "High", + "xspi_cs_ram_interrupt_trigger": "None", + "xspi_cs_ram_dont_conf": 0, + "xspi_dqs": 30, + "xspi_dqs_use_hw": "None", + "xspi_dqs_mode": "Input", + "xspi_dqs_pull": "None", + "xspi_dqs_output_strength": "High", + "xspi_dqs_initial_output_state": "High", + "xspi_dqs_interrupt_trigger": "None", + "xspi_dqs_dont_conf": 0, + "xspi_reset_ram": 2, + "xspi_reset_ram_use_hw": "None", + "xspi_reset_ram_mode": "Input", + "xspi_reset_ram_pull": "None", + "xspi_reset_ram_output_strength": "High", + "xspi_reset_ram_initial_output_state": "High", + "xspi_reset_ram_interrupt_trigger": "None", + "xspi_reset_ram_dont_conf": 0 + }, + "xspi_operations": { + "xspi_operations_clocks": { + "clock_phase": 0, + "clock_polarity": 0, + "spi_mode": "2'b00" + }, + "xspi_operations_chip_select": { + "csda": 2, + "csdads": 0, + "cseot": 4, + "cssot": 1 + }, + "xspi_operations_reset": { + "flash_jedec_reset": 0, + "ram_jedec_reset": 0, + "flash_treset": 20, + "ram_treset": 20 + }, + "xspi_phy_operations": { + "flash_rx_dll_bypass_bit": 0, + "flash_dll_tx_delay": 22, + "flash_dll_rx_delay": 34, + "ram_rx_dll_bypass_bit": 0, + "ram_dll_tx_delay": 22, + "ram_dll_rx_delay": 34 + }, + "xspi_read_operations": { + "flash_dummy_rd_cycles": 6, + "flash_read_opcode": 11, + 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"flash_program_opcode": 2, + "suppl_flash_program_opcode": 0, + "flash_maximum_program_time_limit": 1600 + }, + "flash_erase_operation": { + "flash_min_erase_size": "4 kB", + "flash_erase_opcode": 32, + "suppl_flash_erase_opcode": 0, + "flash_maximum_erase_time_limit": 4095 + }, + "flash_erase_conf": { + "flash_block_erase_opcode": 0, + "suppl_block_flash_erase_opcode": 0, + "flash_sector_erase_opcode": 0, + "suppl_sector_flash_erase_opcode": 0, + "flash_chip_erase_opcode": 0, + "suppl_chip_flash_erase_opcode": 0 + }, + "ram_program_operation": { + "ram_min_program_size": "256 B", + "ram_program_opcode": 2, + "suppl_ram_program_opcode": 0, + "ram_maximum_program_time_limit": 1600 + }, + "ram_erase_conf": { + "ram_block_erase_opcode": 0, + "suppl_block_ram_erase_opcode": 0, + "ram_sector_erase_opcode": 0, + "suppl_sector_ram_erase_opcode": 0, + "ram_chip_erase_opcode": 0, + "suppl_chip_ram_erase_opcode": 0 + }, + "flash_buffer_support": { + "flash_pre_write_sequence": 0, + "flash_post_write_sequence": 0, + "flash_write_protection_timer_en": 0, + "flash_write_buffer_timer_mode": 16, + "flash_write_buffer_timer_range": 0, + "flash_service_interrupt_criteria": 0 + }, + "ram_buffer_support": { + "ram_pre_write_sequence": 0, + "ram_post_write_sequence": 0, + "ram_write_protection_timer_en": 0, + "ram_write_buffer_timer_mode": 16, + "ram_write_buffer_timer_range": 0, + "ram_service_interrupt_criteria": 0 + }, + "flash_pre_write_conf": { + "flash_pre_write_job_done_grant_sel": 0, + "data_for_flash_pre_write_conf_0": 0, + "offset_bits_for_flash_pre_write_conf_0": 0, + "stop_bit_for_flash_pre_write_conf_0": 1, + "data_for_flash_pre_write_conf_1": 0, + "offset_bits_for_flash_pre_write_conf_1": 0 + }, + "flash_post_write_conf": { + "flash_post_write_job_done_grant_sel": 0, + "data_for_flash_post_write_conf_0": 0, + "offset_bits_for_flash_post_write_conf_0": 0, + "stop_bit_for_flash_post_write_conf_0": 1, + "data_for_flash_post_write_conf_1": 0, + "offset_bits_for_flash_post_write_conf_1": 0 + }, + "ram_pre_write_conf": { + "ram_pre_write_job_done_grant_sel": 0, + "data_for_ram_pre_write_conf_0": 0, + "offset_bits_for_ram_pre_write_conf_0": 0, + "stop_bit_for_ram_pre_write_conf_0": 1, + "data_for_ram_pre_write_conf_1": 0, + "offset_bits_for_ram_pre_write_conf_1": 0 + }, + "ram_post_write_conf": { + "ram_post_write_job_done_grant_sel": 0, + "data_for_ram_post_write_conf_0": 0, + "offset_bits_for_ram_post_write_conf_0": 0, + "stop_bit_for_ram_post_write_conf_0": 1, + "data_for_ram_post_write_conf_1": 0, + "offset_bits_for_ram_post_write_conf_1": 0 + } + }, + "xspi_capture_operations": { + "read_data_capture": { + "flash_delay_transmitted_data": 0, + "flash_loopback_clock": 0, + "flash_bypass_adapted_loopback": 1, + "flash_sample_edge_sel": 0, + "ram_delay_transmitted_data": 0, + "ram_loopback_clock": 0, + "ram_bypass_adapted_loopback": 1, + "ram_sample_edge_sel": 0 + }, + "delays": { + "flash_full_half_cycle_delay": 0, + "flash_dll_bypass_mode": 1, + "flash_phase_detect_sel": 0, + "flash_dll_lock_num": 0, + "flash_dll_start_point": 0, + "flash_loopback_clock": 0, + "ram_full_half_cycle_delay": 0, + "ram_dll_bypass_mode": 1, + "ram_phase_detect_sel": 0, + "ram_dll_lock_num": 0, + "ram_dll_start_point": 0, + "ram_loopback_clock": 0 + }, + "operation_modes": { + "flash_sfdp_support": 0, + "ram_sfdp_support": 0, + "flash_pm_support": 0, + "ram_pm_support": 0, + "flash_sfdp_opcode": 0, + "suppl_flash_sfdp_opcode": 0, + "ram_sfdp_opcode": 0, + "suppl_ram_sfdp_opcode": 0, + "flash_enter_dpd_opcode": 185, + "suppl_flash_enter_dpd_opcode": 0, + "flash_exit_dpd_opcode": 171, + "suppl_flash_exit_dpd_opcode": 0, + "ram_enter_dpd_opcode": 185, + "suppl_ram_enter_dpd_opcode": 0, + "ram_exit_dpd_opcode": 171, + "suppl_ram_exit_dpd_opcode": 0, + "flash_quad_enable_opcode": 56, + "suppl_flash_quad_enable_opcode": 0, + "flash_quad_disable_opcode": 255, + "suppl_flash_quad_disable_opcode": 0, + "flash_octal_enable_opcode": 0, + "suppl_flash_octal_enable_opcode": 0, + "flash_octal_disable_opcode": 0, + "suppl_flash_octal_disable_opcode": 0, + "ram_quad_enable_opcode": 56, + "suppl_ram_quad_enable_opcode": 0, + "ram_quad_disable_opcode": 255, + "suppl_ram_quad_disable_opcode": 0, + "ram_octal_enable_opcode": 0, + "suppl_ram_octal_enable_opcode": 0, + "ram_octal_disable_opcode": 0, + "suppl_ram_octal_disable_opcode": 0 + } + } + }, + "external_memory_reporting": { + "header": { + "flash_auto_polling_enable": 1, + "flash_wel_enable": 1, + "flash_write_protect_enable": 0, + "flash_alternate_polling_conf_enable": 0, + "ram_auto_polling_enable": 1, + "ram_wel_enable": 1, + "ram_write_protect_enable": 0, + "ram_alternate_polling_conf_enable": 0 + }, + "flash_auto_polling": { + "flash_polling_repetition_delay": 0, + "flash_polling_count": 4, + "flash_enable_polling_expiration": 0, + "flash_polling_polarity": 0, + "flash_polling_address_phase_enable": 0, + "flash_polling_bit_index": 0, + "flash_numbers_poll_cycles": 65535, + "flash_dummy_autopoll_cycles": 0 + }, + "ram_auto_polling": { + "ram_polling_repetition_delay": 0, + "ram_polling_count": 4, + "ram_enable_polling_expiration": 0, + "ram_polling_polarity": 0, + "ram_polling_address_phase_enable": 0, + "ram_polling_bit_index": 0, + "ram_numbers_poll_cycles": 65535, + "ram_dummy_autopoll_cycles": 0 + }, + "flash_polling_command": { + "flash_polling_opcode": 5, + "suppl_flash_polling_opcode": 0 + }, + "ram_polling_command": { + "ram_polling_opcode": 5, + "suppl_ram_polling_opcode": 0 + }, + "flash_alternate_polling": { + "flash_polling_resp_count": 1023, + "flash_polling_iterations": 1, + "flash_polling_enabled": 0, + "flash_polling_disabled": 0, + "flash_grant_sel": 0, + "flash_data_for_enable_poling_conf_0": 0, + "flash_offset_bits_for_enable_poling_conf_0": 0, + "flash_stop_bit_for_enable_poling_conf_0": 1, + "flash_data_for_enable_poling_conf_1": 0, + "flash_offset_bits_for_enable_poling_conf_1": 0, + "flash_stop_bit_for_enable_poling_conf_1": 1, + "flash_data_for_disable_poling_conf_0": 0, + "flash_offset_bits_for_disable_poling_conf_0": 0, + "flash_stop_bit_for_disable_poling_conf_0": 1, + "flash_data_for_disable_poling_conf_1": 0, + "flash_offset_bits_for_disable_poling_conf_1": 0, + "flash_stop_bit_for_disable_poling_conf_1": 1 + }, + "ram_alternate_polling": { + "ram_polling_resp_count": 1023, + "ram_polling_iterations": 1, + "ram_polling_enabled": 0, + "ram_polling_disabled": 0, + "ram_grant_sel": 0, + "ram_data_for_enable_poling_conf_0": 0, + "ram_offset_bits_for_enable_poling_conf_0": 0, + "ram_stop_bit_for_enable_poling_conf_0": 1, + "ram_data_for_enable_poling_conf_1": 0, + "ram_offset_bits_for_enable_poling_conf_1": 0, + "ram_stop_bit_for_enable_poling_conf_1": 1, + "ram_data_for_disable_poling_conf_0": 0, + "ram_offset_bits_for_disable_poling_conf_0": 0, + "ram_stop_bit_for_disable_poling_conf_0": 1, + "ram_data_for_disable_poling_conf_1": 0, + "ram_offset_bits_for_disable_poling_conf_1": 0, + "ram_stop_bit_for_disable_poling_conf_1": 1 + }, + "flash_wel_command": { + "flash_wel_opcode": 6, + "suppl_flash_wel_opcode": 0 + }, + "ram_wel_command": { + "ram_wel_opcode": 6, + "suppl_ram_wel_opcode": 0 + } + }, + "event": { + "host_nvic_irq": 0, + "core_10_mux_sel": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/mx25u12843g/flash_disc_param_ext_mem.json b/boards/ti/lp_em_cc35x1/config/flash/mx25u12843g/flash_disc_param_ext_mem.json new file mode 100644 index 000000000000..14d05d9aba5a --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/mx25u12843g/flash_disc_param_ext_mem.json @@ -0,0 +1,99 @@ +{ + "vendor_primary_sbl": true, + "ti_wsoc_primary_container": true, + "ti_wsoc_bl2_primary_container": true, + "nvs_enable": true, + "vendor_alternate_image": true, + "vendor_sbl_alternate_image": true, + "ti_bl_alternate_image": true, + "ti_wsoc_alternate_image": true, + "ti_wsoc_bl2_alternate_image": true, + "region_0": { + "mem_region_0_start_phy_address": 2867200, + "mem_region_0_end_phy_address": 9822207, + "region0_boot": false, + "region0_main_code": true, + "region0_nvs": false, + "region0_wsoc_code": false, + "region0_alternate_code": false + }, + "region_1": { + "mem_region_1_start_phy_address": 0, + "mem_region_1_end_phy_address": 2867199, + "region1_boot": true, + "region1_main_code": false, + "region1_nvs": true, + "region1_wsoc_code": true, + "region1_alternate_code": false + }, + "region_2": { + "mem_region_2_start_phy_address": 9822208, + "mem_region_2_end_phy_address": 16777215, + "region2_boot": false, + "region2_main_code": false, + "region2_nvs": false, + "region2_wsoc_code": false, + "region2_alternate_code": true + }, + "region_3": { + "mem_region_3_start_phy_address": 0, + "mem_region_3_end_phy_address": 0, + "region3_boot": false, + "region3_main_code": false, + "region3_nvs": false, + "region3_wsoc_code": false, + "region3_alternate_code": false + }, + "boot_region_conf": { + "boot_region_size": 0, + "boot_region_flash_disco_param_start_address": 0, + "boot_region_primary_ti_bl_start_phy_address": 12284, + "boot_region_primary_ti_bl_magic": 0, + "boot_region_primary_ti_bl_major": 0, + "boot_region_primary_ti_bl_minor": 0, + "boot_region_sec_ti_bl_start_phy_address": 430076, + "boot_region_sec_ti_bl_magic": 0, + "boot_region_sec_ti_bl_major": 0, + "boot_region_sec_ti_bl_minor": 0 + }, + "main_code_region_conf": { + "main_code_region_vendor_image_start_phy_address": 2871292, + "main_code_region_vendor_image_magic": 0, + "main_code_region_vendor_image_major": 0, + "main_code_region_vendor_image_minor": 0, + "main_code_region_sbl_start_phy_address": 0, + "main_code_region_sbl_magic": 0, + "main_code_region_sbl_major": 0, + "main_code_region_sbl_minor": 0 + }, + "alt_code_region_conf": { + "alt_code_region_vendor_image_start_phy_address": 9826300, + "alt_code_region_vendor_image_magic": 0, + "alt_code_region_vendor_image_major": 0, + "alt_code_region_vendor_image_minor": 0, + "alt_code_region_sbl_start_phy_address": 0, + "alt_code_region_sbl_magic": 0, + "alt_code_region_sbl_major": 0, + "alt_code_region_sbl_minor": 0 + }, + "nvs_code_region_conf": { + "nvs_start_phy_address": 1777664, + "nvs_region_size": 1089536, + "nvs_region_primary_wsoc_start_phy_address": 847868, + "nvs_region_primary_wsoc_magic": 0, + "nvs_region_primary_wsoc_major": 0, + "nvs_region_primary_wsoc_minor": 0, + "nvs_region_sec_wsoc_start_phy_address": 1314812, + "nvs_region_sec_wsoc_magic": 0, + "nvs_region_sec_wsoc_major": 0, + "nvs_region_sec_wsoc_minor": 0, + "nvs_region_primary_wsoc_bl2_start_phy_address": 0, + "nvs_region_primary_wsoc_bl2_magic": 0, + "nvs_region_primary_wsoc_bl2_major": 0, + "nvs_region_primary_wsoc_bl2_minor": 0, + "nvs_region_sec_wsoc_bl2_start_phy_address": 0, + "nvs_region_sec_wsoc_bl2_magic": 0, + "nvs_region_sec_wsoc_bl2_major": 0, + "nvs_region_sec_wsoc_bl2_minor": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/mx25u12843g/flash_disc_param_otfde.json b/boards/ti/lp_em_cc35x1/config/flash/mx25u12843g/flash_disc_param_otfde.json new file mode 100644 index 000000000000..4c0fe6211e50 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/mx25u12843g/flash_disc_param_otfde.json @@ -0,0 +1,286 @@ +{ + "otfde_header": { + "name": "OTFDEWFF3", + "flash_only": true, + "ip_protection": false, + "regions_lock": false, + "regions_number": 4, + "flash_enabled": true + }, + "bl_conf": { + "host_boot_done_lock": true, + "host_peripherals_lock": true, + "icache_conf_lock": true, + "m33_mem_part_lock": true, + "memss_firewall_lock": true, + "dma_channel_owner_lock": true, + "otfde_region_lock": true, + "core_events_lock": true + }, + "otfde_general": { + "parameters": { + "mem_otfde_initial_delay": 10, + "otfde_global_watchdog_timer": 5 + }, + "events": { + "reset_evt_mask": false, + "reset_evt_suspend": false, + "sft_reset_evt_mask": false, + "sft_reset_evt_suspend": false, + "bypass_mode_evt_mask": false, + "bypass_mode_evt_suspend": false, + "debug_mode_evt_mask": false, + "debug_mode_evt_suspend": false, + "general_evt_mask": false, + "general_evt_suspend": false, + "xspi_data_path_evt_mask": false, + "xspi_data_path_evt_suspend": false, + "xspi_cnfg_path_evt_mask": false, + "xspi_cnfg_path_evt_suspend": false, + "xspi_service_interrupt_evt_mask": false, + "xspi_service_interrupt_evt_suspend": false, + "trans_device_disabled_evt_mask": false, + "trans_device_disabled_evt_suspend": false, + "trans_region_disabled_evt_mask": false, + "trans_region_disabled_evt_suspend": false, + "trans_region_params_conf_evt_mask": false, + "trans_region_params_conf_evt_suspend": false, + "trans_multiple_regions_mapped_evt_mask": false, + "trans_multiple_regions_mapped_evt_suspend": false, + "trans_address_not_32_bit_evt_mask": false, + "trans_address_not_32_bit_evt_suspend": false, + "trans_size_not_32_bit_evt_mask": false, + "trans_size_not_32_bit_evt_suspend": false, + "trans_burst_not_32_bit_evt_mask": false, + "trans_burst_not_32_bit_evt_suspend": false, + "region_read_write_def_evt_mask": false, + "region_read_write_def_evt_suspend": false, + "suspend_while_disabled_evt_mask": false, + "suspend_while_disabled_evt_suspend": false + } + }, + "regions_settings": { + "region_parameters_lock": { + "REGION_0_PARAMS_0": true, + "REGION_0_PARAMS_1": true, + "REGION_0_PARAMS_2": true, + "REGION_1_PARAMS_0": false, + "REGION_1_PARAMS_1": false, + "REGION_1_PARAMS_2": false, + "REGION_2_PARAMS_0": true, + "REGION_2_PARAMS_1": true, + "REGION_2_PARAMS_2": true, + "REGION_3_PARAMS_0": false, + "REGION_3_PARAMS_1": false, + "REGION_3_PARAMS_2": false + }, + "region_0_protection": { + "mem_region_0_enabled": true, + "mem_region_0_device_id": 0, + "mem_region_0_spi_write_enable": true, + "mem_region_0_spi_read_enable": true, + "mem_region_0_physical_offset": 700, + "mem_region_0_security_id_msb": 0, + "mem_region_0_start_address": 81920, + "mem_region_0_end_address": 83617, + "mem_region_0_security_id_lsb": 0, + "mem_otfde_region_0_write_lock_en": false, + "mem_otfde_region_0_enc_dec_bypass": "Bypass" + }, + "region_1_protection": { + "mem_region_1_enabled": true, + "mem_region_1_device_id": 0, + "mem_region_1_spi_write_enable": true, + "mem_region_1_spi_read_enable": true, + "mem_region_1_physical_offset": 0, + "mem_region_1_security_id_msb": 0, + "mem_region_1_start_address": 655360, + "mem_region_1_end_address": 656059, + "mem_region_1_security_id_lsb": 0, + "mem_otfde_region_1_write_lock_en": false, + "mem_otfde_region_1_enc_dec_bypass": "Bypass" + }, + "region_2_protection": { + "mem_region_2_enabled": true, + "mem_region_2_device_id": 0, + "mem_region_2_spi_write_enable": true, + "mem_region_2_spi_read_enable": true, + "mem_region_2_physical_offset": 2398, + "mem_region_2_security_id_msb": 0, + "mem_region_2_start_address": 671744, + "mem_region_2_end_address": 673441, + "mem_region_2_security_id_lsb": 0, + "mem_otfde_region_2_write_lock_en": false, + "mem_otfde_region_2_enc_dec_bypass": "Bypass" + }, + "region_3_protection": { + "mem_region_3_enabled": false, + "mem_region_3_device_id": 1, + "mem_region_3_spi_write_enable": true, + "mem_region_3_spi_read_enable": true, + "mem_region_3_physical_offset": 0, + "mem_region_3_security_id_msb": 0, + "mem_region_3_start_address": 1, + "mem_region_3_end_address": 0, + "mem_region_3_security_id_lsb": 0, + "mem_otfde_region_3_write_lock_en": false, + "mem_otfde_region_3_enc_dec_bypass": "Bypass" + } + }, + "devices": { + "header": { + "flash_device_switch_conf": 1, + "ram_device_switch_conf": 1 + }, + "flash_switch": { + "flash_grant_sel": 0, + "flash_data_for_conf_0": 2181562505, + "flash_offset_bits_for_conf_0": 0, + "flash_stop_bit_for_conf_0": 0, + "flash_data_for_conf_1": 100803307, + "flash_offset_bits_for_conf_1": 1, + "flash_stop_bit_for_conf_1": 0, + "flash_data_for_conf_2": 139266, + "flash_offset_bits_for_conf_2": 2, + "flash_stop_bit_for_conf_2": 0, + "flash_data_for_conf_3": 1, + "flash_offset_bits_for_conf_3": 4, + "flash_stop_bit_for_conf_3": 0, + "flash_data_for_conf_4": 1076887634, + "flash_offset_bits_for_conf_4": 45, + "flash_stop_bit_for_conf_4": 0, + "flash_data_for_conf_5": 3224371282, + "flash_offset_bits_for_conf_5": 45, + "flash_stop_bit_for_conf_5": 0, + "flash_data_for_conf_6": 262149, + "flash_offset_bits_for_conf_6": 14, + "flash_stop_bit_for_conf_6": 0, + "flash_data_for_conf_7": 0, + "flash_offset_bits_for_conf_7": 44, + "flash_stop_bit_for_conf_7": 1, + "flash_data_for_conf_8": 0, + "flash_offset_bits_for_conf_8": 0, + "flash_stop_bit_for_conf_8": 1, + "flash_data_for_conf_9": 0, + "flash_offset_bits_for_conf_9": 0, + "flash_stop_bit_for_conf_9": 1, + "flash_data_for_conf_10": 0, + "flash_offset_bits_for_conf_10": 0, + "flash_stop_bit_for_conf_10": 1, + "flash_data_for_conf_11": 0, + "flash_offset_bits_for_conf_11": 0, + "flash_stop_bit_for_conf_11": 1, + "flash_data_for_conf_12": 0, + "flash_offset_bits_for_conf_12": 0, + "flash_stop_bit_for_conf_12": 1, + "flash_data_for_conf_13": 0, + "flash_offset_bits_for_conf_13": 0, + "flash_stop_bit_for_conf_13": 1, + "flash_data_for_conf_14": 0, + "flash_offset_bits_for_conf_14": 0, + "flash_stop_bit_for_conf_14": 1, + "flash_data_for_conf_15": 0, + "flash_offset_bits_for_conf_15": 0, + "flash_stop_bit_for_conf_15": 1, + "flash_data_for_conf_16": 0, + "flash_offset_bits_for_conf_16": 0, + "flash_stop_bit_for_conf_16": 1, + "flash_data_for_conf_17": 0, + "flash_offset_bits_for_conf_17": 0, + "flash_stop_bit_for_conf_17": 1, + "flash_data_for_conf_18": 0, + "flash_offset_bits_for_conf_18": 0, + "flash_stop_bit_for_conf_18": 1, + "flash_data_for_conf_19": 0, + "flash_offset_bits_for_conf_19": 0, + "flash_stop_bit_for_conf_19": 1, + "flash_data_for_conf_20": 0, + "flash_offset_bits_for_conf_20": 0, + "flash_stop_bit_for_conf_20": 1, + "flash_data_for_conf_21": 0, + "flash_offset_bits_for_conf_21": 0, + "flash_stop_bit_for_conf_21": 1, + "flash_data_for_conf_22": 0, + "flash_offset_bits_for_conf_22": 0, + "flash_stop_bit_for_conf_22": 1, + "flash_data_for_conf_23": 0, + "flash_offset_bits_for_conf_23": 0, + "flash_stop_bit_for_conf_23": 1 + }, + "ram_switch": { + "ram_grant_sel": 0, + "ram_data_for_conf_0": 2181562505, + "ram_offset_bits_for_conf_0": 0, + "ram_stop_bit_for_conf_0": 0, + "ram_data_for_conf_1": 100803307, + "ram_offset_bits_for_conf_1": 1, + "ram_stop_bit_for_conf_1": 0, + "ram_data_for_conf_2": 139266, + "ram_offset_bits_for_conf_2": 2, + "ram_stop_bit_for_conf_2": 0, + "ram_data_for_conf_3": 1, + "ram_offset_bits_for_conf_3": 4, + "ram_stop_bit_for_conf_3": 0, + "ram_data_for_conf_4": 1076887634, + "ram_offset_bits_for_conf_4": 45, + "ram_stop_bit_for_conf_4": 0, + "ram_data_for_conf_5": 3224371282, + "ram_offset_bits_for_conf_5": 45, + "ram_stop_bit_for_conf_5": 0, + "ram_data_for_conf_6": 262149, + "ram_offset_bits_for_conf_6": 14, + "ram_stop_bit_for_conf_6": 0, + "ram_data_for_conf_7": 0, + "ram_offset_bits_for_conf_7": 44, + "ram_stop_bit_for_conf_7": 1, + "ram_data_for_conf_8": 0, + "ram_offset_bits_for_conf_8": 0, + "ram_stop_bit_for_conf_8": 1, + "ram_data_for_conf_9": 0, + "ram_offset_bits_for_conf_9": 0, + "ram_stop_bit_for_conf_9": 1, + "ram_data_for_conf_10": 0, + "ram_offset_bits_for_conf_10": 0, + "ram_stop_bit_for_conf_10": 1, + "ram_data_for_conf_11": 0, + "ram_offset_bits_for_conf_11": 0, + "ram_stop_bit_for_conf_11": 1, + "ram_data_for_conf_12": 0, + "ram_offset_bits_for_conf_12": 0, + "ram_stop_bit_for_conf_12": 1, + "ram_data_for_conf_13": 0, + "ram_offset_bits_for_conf_13": 0, + "ram_stop_bit_for_conf_13": 1, + "ram_data_for_conf_14": 0, + "ram_offset_bits_for_conf_14": 0, + "ram_stop_bit_for_conf_14": 1, + "ram_data_for_conf_15": 0, + "ram_offset_bits_for_conf_15": 0, + "ram_stop_bit_for_conf_15": 1, + "ram_data_for_conf_16": 0, + "ram_offset_bits_for_conf_16": 0, + "ram_stop_bit_for_conf_16": 1, + "ram_data_for_conf_17": 0, + "ram_offset_bits_for_conf_17": 0, + "ram_stop_bit_for_conf_17": 1, + "ram_data_for_conf_18": 0, + "ram_offset_bits_for_conf_18": 0, + "ram_stop_bit_for_conf_18": 1, + "ram_data_for_conf_19": 0, + "ram_offset_bits_for_conf_19": 0, + "ram_stop_bit_for_conf_19": 1, + "ram_data_for_conf_20": 0, + "ram_offset_bits_for_conf_20": 0, + "ram_stop_bit_for_conf_20": 1, + "ram_data_for_conf_21": 0, + "ram_offset_bits_for_conf_21": 0, + "ram_stop_bit_for_conf_21": 1, + "ram_data_for_conf_22": 0, + "ram_offset_bits_for_conf_22": 0, + "ram_stop_bit_for_conf_22": 1, + "ram_data_for_conf_23": 0, + "ram_offset_bits_for_conf_23": 0, + "ram_stop_bit_for_conf_23": 1 + } + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/mx25u12843g/flash_disc_param_xspi.json b/boards/ti/lp_em_cc35x1/config/flash/mx25u12843g/flash_disc_param_xspi.json new file mode 100644 index 000000000000..3b54f8d1f2be --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/mx25u12843g/flash_disc_param_xspi.json @@ -0,0 +1,485 @@ +{ + "xspi_header": { + "name": "xSPIWFF3", + "device": "CC3500", + "use_hardware": "MX25U12843G", + "use_case": "Quadro", + "dqs_support": 0, + "flash_only": 1, + "flash_separate_reset": 0, + "ram_separate_reset": true, + "clock_frequency": 80, + "qospi_clock_divider": 1, + "flash_device_character_conf": 0, + "ram_device_character_conf": 0, + "header_advanced": 0, + "phy_mode_enable": 1, + "pipeline_mode_enable": 1, + "loopback_support": "No", + "qspi_ref_clock": 80, + "spi_clock_freq": 20, + "spi_clock_divider": 1, + "flash_device_size": 16, + "flash_bytes_per_block": 16, + "flash_bytes_per_page": 256, + "flash_number_of_address_bytes": 3, + "flash_dual_opcode": 0, + "flash_jedec_manufacturer_id": 0, + "flash_jedec_device_id": 0, + "flash_name": "MX25U12843G", + "flash_page_size": 256, + "flash_sector_size": 4096, + "flash_cs_polarity": "ACTIVE_LOW", + "flash_sw_reset_type": "x1xxxx", + "ram_device_size": 8, + "ram_bytes_per_block": 16, + "ram_bytes_per_page": 256, + "ram_number_of_address_bytes": 3, + "ram_dual_opcode": 0, + "ram_jedec_manufacturer_id": 0, + "ram_jedec_device_id": 0, + "ram_name": "NO_PSRAM", + "ram_page_size": 256, + "ram_sector_size": 4096, + "ram_cs_polarity": "ACTIVE_LOW", + "ram_sw_reset_type": "x1xxxx", + "flash_write_operation_modes": "4S-4S-4S", + "flash_read_operation_modes": "4S-4S-4S", + "ram_write_operation_modes": "4S-4S-4S", + "ram_read_operation_modes": "4S-4S-4S", + "crc_enable": 0, + "enable_dtr": 0, + "enable_ahb_decoder": 0, + "enter_xip_mod_immediately": 0, + "enter_xip_mod_next_read": 0, + "ahb_address_remapping": 0, + "enable_dma": 0, + "select_decode": 0, + "legacy_ip_mode": 0, + "direct_access": 1 + }, + "xspi_pinmux": { + "xspi_clk_input": 44, + "xspi_clk_input_use_hw": 0, + "xspi_clk_input_mode": "Input", + "xspi_clk_input_pull": "None", + "xspi_clk_input_interrupt_trigger": "Low", + "xspi_clk_input_dont_conf": 0, + "xspi_clk_input_output_strength": "High", + "xspi_clk_input_initial_output_state": "High", + "xspi_clk": 24, + "xspi_clk_use_hw": "None", + "xspi_clk_mode": "Output", + "xspi_clk_pull": "None", + "xspi_clk_output_strength": "High", + "xspi_clk_initial_output_state": "High", + "xspi_clk_interrupt_trigger": "None", + "xspi_clk_dont_conf": 0, + "xspi_flash_cs": 20, + "xspi_flash_cs_use_hw": "None", + "xspi_flash_cs_mode": "Output", + "xspi_flash_cs_pull": "None", + "xspi_flash_cs_output_strength": "High", + "xspi_flash_cs_initial_output_state": "High", + "xspi_flash_cs_interrupt_trigger": "None", + "xspi_flash_cs_dont_conf": 0, + "xspi_data_0": 25, + "xspi_data_0_use_hw": "None", + "xspi_data_0_mode": "Input", + "xspi_data_0_pull": "None", + "xspi_data_0_output_strength": "High", + "xspi_data_0_initial_output_state": "High", + "xspi_data_0_interrupt_trigger": "Low", + "xspi_data_0_dont_conf": 0, + "xspi_data_1": 21, + "xspi_data_1_use_hw": "None", + "xspi_data_1_mode": "Input", + "xspi_data_1_pull": "None", + "xspi_data_1_output_strength": "High", + "xspi_data_1_initial_output_state": "High", + "xspi_data_1_interrupt_trigger": "Low", + "xspi_data_1_dont_conf": 0, + "xspi_data_2": 22, + "xspi_data_2_use_hw": "None", + "xspi_data_2_mode": "Input", + "xspi_data_2_pull": "None", + "xspi_data_2_output_strength": "High", + "xspi_data_2_initial_output_state": "High", + "xspi_data_2_interrupt_trigger": "Low", + "xspi_data_2_dont_conf": 0, + "xspi_data_3": 23, + "xspi_data_3_use_hw": "None", + "xspi_data_3_mode": "Input", + "xspi_data_3_pull": "None", + "xspi_data_3_output_strength": "High", + "xspi_data_3_initial_output_state": "High", + "xspi_data_3_interrupt_trigger": "Low", + "xspi_data_3_dont_conf": 0, + "xspi_data_4": 26, + "xspi_data_4_use_hw": "None", + "xspi_data_4_mode": "Input", + "xspi_data_4_pull": "None", + "xspi_data_4_output_strength": "High", + "xspi_data_4_initial_output_state": "High", + "xspi_data_4_interrupt_trigger": "None", + "xspi_data_4_dont_conf": 0, + "xspi_data_5": 27, + "xspi_data_5_use_hw": "None", + "xspi_data_5_mode": "Input", + "xspi_data_5_pull": "None", + "xspi_data_5_output_strength": "High", + "xspi_data_5_initial_output_state": "High", + "xspi_data_5_interrupt_trigger": "None", + "xspi_data_5_dont_conf": 0, + "xspi_data_6": 28, + "xspi_data_6_use_hw": "None", + "xspi_data_6_mode": "Input", + "xspi_data_6_pull": "None", + "xspi_data_6_output_strength": "High", + "xspi_data_6_initial_output_state": "High", + "xspi_data_6_interrupt_trigger": "None", + "xspi_data_6_dont_conf": 0, + "xspi_data_7": 29, + "xspi_data_7_use_hw": "None", + "xspi_data_7_mode": "Input", + "xspi_data_7_pull": "None", + "xspi_data_7_output_strength": "High", + "xspi_data_7_initial_output_state": "High", + "xspi_data_7_interrupt_trigger": "None", + "xspi_data_7_dont_conf": 0, + "xspi_reset_flash": 36, + "xspi_reset_flash_use_hw": "None", + "xspi_reset_flash_mode": "Output", + "xspi_reset_flash_pull": "None", + "xspi_reset_flash_output_strength": "High", + "xspi_reset_flash_initial_output_state": "High", + "xspi_reset_flash_interrupt_trigger": "None", + "xspi_reset_flash_dont_conf": 0, + "xspi_cs_ram": 3, + "xspi_cs_ram_use_hw": "None", + "xspi_cs_ram_mode": "Output", + "xspi_cs_ram_pull": "None", + "xspi_cs_ram_output_strength": "High", + "xspi_cs_ram_initial_output_state": "High", + "xspi_cs_ram_interrupt_trigger": "None", + "xspi_cs_ram_dont_conf": 0, + "xspi_dqs": 30, + "xspi_dqs_use_hw": "None", + "xspi_dqs_mode": "Input", + "xspi_dqs_pull": "None", + "xspi_dqs_output_strength": "High", + "xspi_dqs_initial_output_state": "High", + "xspi_dqs_interrupt_trigger": "None", + "xspi_dqs_dont_conf": 0, + "xspi_reset_ram": 2, + "xspi_reset_ram_use_hw": "None", + "xspi_reset_ram_mode": "Input", + "xspi_reset_ram_pull": "None", + "xspi_reset_ram_output_strength": "High", + "xspi_reset_ram_initial_output_state": "High", + "xspi_reset_ram_interrupt_trigger": "None", + "xspi_reset_ram_dont_conf": 0 + }, + "xspi_operations": { + "xspi_operations_clocks": { + "clock_phase": 0, + "clock_polarity": 0, + "spi_mode": "2'b00" + }, + "xspi_operations_chip_select": { + "csda": 2, + "csdads": 0, + "cseot": 4, + "cssot": 1 + }, + "xspi_operations_reset": { + "flash_jedec_reset": 0, + "ram_jedec_reset": 0, + "flash_treset": 20, + "ram_treset": 20 + }, + "xspi_phy_operations": { + "flash_rx_dll_bypass_bit": 0, + "flash_dll_tx_delay": 42, + "flash_dll_rx_delay": 62, + "ram_rx_dll_bypass_bit": 0, + "ram_dll_tx_delay": 42, + "ram_dll_rx_delay": 62 + }, + "xspi_read_operations": { + "flash_dummy_rd_cycles": 4, + "flash_read_opcode": 11, + "suppl_flash_read_opcode": 0, + "ram_dummy_rd_cycles": 4, + "ram_read_opcode": 11, + "suppl_ram_read_opcode": 0, + "flash_non_cont_read_enable": 0, + "flash_max_read_jobs": 256, + "ram_non_cont_read_enable": 0, + "ram_max_read_jobs": 256, + "rww_en": 0, + "device_size": 8, + "number_of_banks": 1, + "bank_size": 8, + "mode_bit_enable": 0 + }, + "xspi_write_operations": { + "flash_address_and_data": { + "flash_dummy_wr_cycles": 0 + }, + "flash_command": { + "flash_write_opcode": 2, + "suppl_flash_write_opcode": 0 + }, + "ram_address_and_data": { + "ram_dummy_wr_cycles": 0 + }, + "ram_command": { + "ram_write_opcode": 2, + "suppl_ram_write_opcode": 0 + }, + "write_to_buffer": { + "flash_write_to_buffer_support": 0, + "ram_write_to_buffer_support": 0 + }, + "non_continuous_write": { + "flash_non_cont_write_enable": 0, + "flash_max_write_jobs": 64, + "ram_non_cont_write_enable": 0, + "ram_max_write_jobs": 0 + }, + "flash_program_operation": { + "flash_min_program_size": "256 B", + "flash_program_opcode": 2, + "suppl_flash_program_opcode": 0, + "flash_maximum_program_time_limit": 1600 + }, + "flash_erase_operation": { + "flash_min_erase_size": "4 kB", + "flash_erase_opcode": 32, + "suppl_flash_erase_opcode": 0, + "flash_maximum_erase_time_limit": 4095 + }, + "flash_erase_conf": { + "flash_block_erase_opcode": 0, + "suppl_block_flash_erase_opcode": 0, + "flash_sector_erase_opcode": 0, + "suppl_sector_flash_erase_opcode": 0, + "flash_chip_erase_opcode": 0, + "suppl_chip_flash_erase_opcode": 0 + }, + "ram_program_operation": { + "ram_min_program_size": "256 B", + "ram_program_opcode": 2, + "suppl_ram_program_opcode": 0, + "ram_maximum_program_time_limit": 1600 + }, + "ram_erase_conf": { + "ram_block_erase_opcode": 0, + "suppl_block_ram_erase_opcode": 0, + "ram_sector_erase_opcode": 0, + "suppl_sector_ram_erase_opcode": 0, + "ram_chip_erase_opcode": 0, + "suppl_chip_ram_erase_opcode": 0 + }, + "flash_buffer_support": { + "flash_pre_write_sequence": 0, + "flash_post_write_sequence": 0, + "flash_write_protection_timer_en": 0, + "flash_write_buffer_timer_mode": 16, + "flash_write_buffer_timer_range": 0, + "flash_service_interrupt_criteria": 0 + }, + "ram_buffer_support": { + "ram_pre_write_sequence": 0, + "ram_post_write_sequence": 0, + "ram_write_protection_timer_en": 0, + "ram_write_buffer_timer_mode": 16, + "ram_write_buffer_timer_range": 0, + "ram_service_interrupt_criteria": 0 + }, + "flash_pre_write_conf": { + "flash_pre_write_job_done_grant_sel": 0, + "data_for_flash_pre_write_conf_0": 0, + "offset_bits_for_flash_pre_write_conf_0": 0, + "stop_bit_for_flash_pre_write_conf_0": 1, + "data_for_flash_pre_write_conf_1": 0, + "offset_bits_for_flash_pre_write_conf_1": 0 + }, + "flash_post_write_conf": { + "flash_post_write_job_done_grant_sel": 0, + "data_for_flash_post_write_conf_0": 0, + "offset_bits_for_flash_post_write_conf_0": 0, + "stop_bit_for_flash_post_write_conf_0": 1, + "data_for_flash_post_write_conf_1": 0, + "offset_bits_for_flash_post_write_conf_1": 0 + }, + "ram_pre_write_conf": { + "ram_pre_write_job_done_grant_sel": 0, + "data_for_ram_pre_write_conf_0": 0, + "offset_bits_for_ram_pre_write_conf_0": 0, + "stop_bit_for_ram_pre_write_conf_0": 1, + "data_for_ram_pre_write_conf_1": 0, + "offset_bits_for_ram_pre_write_conf_1": 0 + }, + "ram_post_write_conf": { + "ram_post_write_job_done_grant_sel": 0, + "data_for_ram_post_write_conf_0": 0, + "offset_bits_for_ram_post_write_conf_0": 0, + "stop_bit_for_ram_post_write_conf_0": 1, + "data_for_ram_post_write_conf_1": 0, + "offset_bits_for_ram_post_write_conf_1": 0 + } + }, + "xspi_capture_operations": { + "read_data_capture": { + "flash_delay_transmitted_data": 0, + "flash_loopback_clock": 0, + "flash_bypass_adapted_loopback": 1, + "flash_sample_edge_sel": 0, + "ram_delay_transmitted_data": 0, + "ram_loopback_clock": 0, + "ram_bypass_adapted_loopback": 1, + "ram_sample_edge_sel": 0 + }, + "delays": { + "flash_full_half_cycle_delay": 0, + "flash_dll_bypass_mode": 1, + "flash_phase_detect_sel": 0, + "flash_dll_lock_num": 0, + "flash_dll_start_point": 0, + "flash_loopback_clock": 0, + "ram_full_half_cycle_delay": 0, + "ram_dll_bypass_mode": 1, + "ram_phase_detect_sel": 0, + "ram_dll_lock_num": 0, + "ram_dll_start_point": 0, + "ram_loopback_clock": 0 + }, + "operation_modes": { + "flash_sfdp_support": 0, + "ram_sfdp_support": 0, + "flash_pm_support": 0, + "ram_pm_support": 0, + "flash_sfdp_opcode": 0, + "suppl_flash_sfdp_opcode": 0, + "ram_sfdp_opcode": 0, + "suppl_ram_sfdp_opcode": 0, + "flash_enter_dpd_opcode": 185, + "suppl_flash_enter_dpd_opcode": 0, + "flash_exit_dpd_opcode": 171, + "suppl_flash_exit_dpd_opcode": 0, + "ram_enter_dpd_opcode": 185, + "suppl_ram_enter_dpd_opcode": 0, + "ram_exit_dpd_opcode": 171, + "suppl_ram_exit_dpd_opcode": 0, + "flash_quad_enable_opcode": 53, + "suppl_flash_quad_enable_opcode": 0, + "flash_quad_disable_opcode": 245, + "suppl_flash_quad_disable_opcode": 0, + "flash_octal_enable_opcode": 0, + "suppl_flash_octal_enable_opcode": 0, + "flash_octal_disable_opcode": 0, + "suppl_flash_octal_disable_opcode": 0, + "ram_quad_enable_opcode": 53, + "suppl_ram_quad_enable_opcode": 0, + "ram_quad_disable_opcode": 245, + "suppl_ram_quad_disable_opcode": 0, + "ram_octal_enable_opcode": 0, + "suppl_ram_octal_enable_opcode": 0, + "ram_octal_disable_opcode": 0, + "suppl_ram_octal_disable_opcode": 0 + } + } + }, + "external_memory_reporting": { + "header": { + "flash_auto_polling_enable": 1, + "flash_wel_enable": 1, + "flash_write_protect_enable": 0, + "flash_alternate_polling_conf_enable": 0, + "ram_auto_polling_enable": 1, + "ram_wel_enable": 1, + "ram_write_protect_enable": 0, + "ram_alternate_polling_conf_enable": 0 + }, + "flash_auto_polling": { + "flash_polling_repetition_delay": 0, + "flash_polling_count": 4, + "flash_enable_polling_expiration": 0, + "flash_polling_polarity": 0, + "flash_polling_address_phase_enable": 0, + "flash_polling_bit_index": 0, + "flash_numbers_poll_cycles": 65535, + "flash_dummy_autopoll_cycles": 0 + }, + "ram_auto_polling": { + "ram_polling_repetition_delay": 0, + "ram_polling_count": 4, + "ram_enable_polling_expiration": 0, + "ram_polling_polarity": 0, + "ram_polling_address_phase_enable": 0, + "ram_polling_bit_index": 0, + "ram_numbers_poll_cycles": 65535, + "ram_dummy_autopoll_cycles": 0 + }, + "flash_polling_command": { + "flash_polling_opcode": 5, + "suppl_flash_polling_opcode": 0 + }, + "ram_polling_command": { + "ram_polling_opcode": 5, + "suppl_ram_polling_opcode": 0 + }, + "flash_alternate_polling": { + "flash_polling_resp_count": 1023, + "flash_polling_iterations": 1, + "flash_polling_enabled": 0, + "flash_polling_disabled": 0, + "flash_grant_sel": 0, + "flash_data_for_enable_poling_conf_0": 0, + "flash_offset_bits_for_enable_poling_conf_0": 0, + "flash_stop_bit_for_enable_poling_conf_0": 1, + "flash_data_for_enable_poling_conf_1": 0, + "flash_offset_bits_for_enable_poling_conf_1": 0, + "flash_stop_bit_for_enable_poling_conf_1": 1, + "flash_data_for_disable_poling_conf_0": 0, + "flash_offset_bits_for_disable_poling_conf_0": 0, + "flash_stop_bit_for_disable_poling_conf_0": 1, + "flash_data_for_disable_poling_conf_1": 0, + "flash_offset_bits_for_disable_poling_conf_1": 0, + "flash_stop_bit_for_disable_poling_conf_1": 1 + }, + "ram_alternate_polling": { + "ram_polling_resp_count": 1023, + "ram_polling_iterations": 1, + "ram_polling_enabled": 0, + "ram_polling_disabled": 0, + "ram_grant_sel": 0, + "ram_data_for_enable_poling_conf_0": 0, + "ram_offset_bits_for_enable_poling_conf_0": 0, + "ram_stop_bit_for_enable_poling_conf_0": 1, + "ram_data_for_enable_poling_conf_1": 0, + "ram_offset_bits_for_enable_poling_conf_1": 0, + "ram_stop_bit_for_enable_poling_conf_1": 1, + "ram_data_for_disable_poling_conf_0": 0, + "ram_offset_bits_for_disable_poling_conf_0": 0, + "ram_stop_bit_for_disable_poling_conf_0": 1, + "ram_data_for_disable_poling_conf_1": 0, + "ram_offset_bits_for_disable_poling_conf_1": 0, + "ram_stop_bit_for_disable_poling_conf_1": 1 + }, + "flash_wel_command": { + "flash_wel_opcode": 6, + "suppl_flash_wel_opcode": 0 + }, + "ram_wel_command": { + "ram_wel_opcode": 6, + "suppl_ram_wel_opcode": 0 + } + }, + "event": { + "host_nvic_irq": 0, + "core_10_mux_sel": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/mx25u3235f/flash_disc_param_ext_mem.json b/boards/ti/lp_em_cc35x1/config/flash/mx25u3235f/flash_disc_param_ext_mem.json new file mode 100644 index 000000000000..321810768be1 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/mx25u3235f/flash_disc_param_ext_mem.json @@ -0,0 +1,99 @@ +{ + "vendor_primary_sbl": true, + "ti_wsoc_primary_container": true, + "ti_wsoc_bl2_primary_container": true, + "nvs_enable": true, + "vendor_alternate_image": true, + "vendor_sbl_alternate_image": true, + "ti_bl_alternate_image": true, + "ti_wsoc_alternate_image": true, + "ti_wsoc_bl2_alternate_image": true, + "region_0": { + "mem_region_0_start_phy_address": 1069056, + "mem_region_0_end_phy_address": 4194303, + "region0_boot": false, + "region0_main_code": true, + "region0_nvs": false, + "region0_wsoc_code": false, + "region0_alternate_code": false + }, + "region_1": { + "mem_region_1_start_phy_address": 0, + "mem_region_1_end_phy_address": 1069055, + "region1_boot": true, + "region1_main_code": false, + "region1_nvs": true, + "region1_wsoc_code": true, + "region1_alternate_code": false + }, + "region_2": { + "mem_region_2_start_phy_address": 0, + "mem_region_2_end_phy_address": 0, + "region2_boot": false, + "region2_main_code": false, + "region2_nvs": false, + "region2_wsoc_code": false, + "region2_alternate_code": true + }, + "region_3": { + "mem_region_3_start_phy_address": 0, + "mem_region_3_end_phy_address": 0, + "region3_boot": false, + "region3_main_code": false, + "region3_nvs": false, + "region3_wsoc_code": false, + "region3_alternate_code": false + }, + "boot_region_conf": { + "boot_region_size": 0, + "boot_region_flash_disco_param_start_address": 0, + "boot_region_primary_ti_bl_start_phy_address": 12284, + "boot_region_primary_ti_bl_magic": 0, + "boot_region_primary_ti_bl_major": 0, + "boot_region_primary_ti_bl_minor": 0, + "boot_region_sec_ti_bl_start_phy_address": 430076, + "boot_region_sec_ti_bl_magic": 0, + "boot_region_sec_ti_bl_major": 0, + "boot_region_sec_ti_bl_minor": 0 + }, + "main_code_region_conf": { + "main_code_region_vendor_image_start_phy_address": 1073148, + "main_code_region_vendor_image_magic": 0, + "main_code_region_vendor_image_major": 0, + "main_code_region_vendor_image_minor": 0, + "main_code_region_sbl_start_phy_address": 0, + "main_code_region_sbl_magic": 0, + "main_code_region_sbl_major": 0, + "main_code_region_sbl_minor": 0 + }, + "alt_code_region_conf": { + "alt_code_region_vendor_image_start_phy_address": 4194304, + "alt_code_region_vendor_image_magic": 0, + "alt_code_region_vendor_image_major": 0, + "alt_code_region_vendor_image_minor": 0, + "alt_code_region_sbl_start_phy_address": 0, + "alt_code_region_sbl_magic": 0, + "alt_code_region_sbl_major": 0, + "alt_code_region_sbl_minor": 0 + }, + "nvs_code_region_conf": { + "nvs_start_phy_address": 892928, + "nvs_region_size": 176128, + "nvs_region_primary_wsoc_start_phy_address": 430076, + "nvs_region_primary_wsoc_magic": 0, + "nvs_region_primary_wsoc_major": 0, + "nvs_region_primary_wsoc_minor": 0, + "nvs_region_sec_wsoc_start_phy_address": 897020, + "nvs_region_sec_wsoc_magic": 0, + "nvs_region_sec_wsoc_major": 0, + "nvs_region_sec_wsoc_minor": 0, + "nvs_region_primary_wsoc_bl2_start_phy_address": 0, + "nvs_region_primary_wsoc_bl2_magic": 0, + "nvs_region_primary_wsoc_bl2_major": 0, + "nvs_region_primary_wsoc_bl2_minor": 0, + "nvs_region_sec_wsoc_bl2_start_phy_address": 0, + "nvs_region_sec_wsoc_bl2_magic": 0, + "nvs_region_sec_wsoc_bl2_major": 0, + "nvs_region_sec_wsoc_bl2_minor": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/mx25u3235f/flash_disc_param_otfde.json b/boards/ti/lp_em_cc35x1/config/flash/mx25u3235f/flash_disc_param_otfde.json new file mode 100644 index 000000000000..e1106f2330ac --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/mx25u3235f/flash_disc_param_otfde.json @@ -0,0 +1,286 @@ +{ + "otfde_header": { + "name": "OTFDEWFF3", + "flash_only": true, + "ip_protection": false, + "regions_lock": false, + "regions_number": 4, + "flash_enabled": true + }, + "bl_conf": { + "host_boot_done_lock": true, + "host_peripherals_lock": true, + "icache_conf_lock": true, + "m33_mem_part_lock": true, + "memss_firewall_lock": true, + "dma_channel_owner_lock": true, + "otfde_region_lock": true, + "core_events_lock": true + }, + "otfde_general": { + "parameters": { + "mem_otfde_initial_delay": 10, + "otfde_global_watchdog_timer": 5 + }, + "events": { + "reset_evt_mask": false, + "reset_evt_suspend": false, + "sft_reset_evt_mask": false, + "sft_reset_evt_suspend": false, + "bypass_mode_evt_mask": false, + "bypass_mode_evt_suspend": false, + "debug_mode_evt_mask": false, + "debug_mode_evt_suspend": false, + "general_evt_mask": false, + "general_evt_suspend": false, + "xspi_data_path_evt_mask": false, + "xspi_data_path_evt_suspend": false, + "xspi_cnfg_path_evt_mask": false, + "xspi_cnfg_path_evt_suspend": false, + "xspi_service_interrupt_evt_mask": false, + "xspi_service_interrupt_evt_suspend": false, + "trans_device_disabled_evt_mask": false, + "trans_device_disabled_evt_suspend": false, + "trans_region_disabled_evt_mask": false, + "trans_region_disabled_evt_suspend": false, + "trans_region_params_conf_evt_mask": false, + "trans_region_params_conf_evt_suspend": false, + "trans_multiple_regions_mapped_evt_mask": false, + "trans_multiple_regions_mapped_evt_suspend": false, + "trans_address_not_32_bit_evt_mask": false, + "trans_address_not_32_bit_evt_suspend": false, + "trans_size_not_32_bit_evt_mask": false, + "trans_size_not_32_bit_evt_suspend": false, + "trans_burst_not_32_bit_evt_mask": false, + "trans_burst_not_32_bit_evt_suspend": false, + "region_read_write_def_evt_mask": false, + "region_read_write_def_evt_suspend": false, + "suspend_while_disabled_evt_mask": false, + "suspend_while_disabled_evt_suspend": false + } + }, + "regions_settings": { + "region_parameters_lock": { + "REGION_0_PARAMS_0": true, + "REGION_0_PARAMS_1": true, + "REGION_0_PARAMS_2": true, + "REGION_1_PARAMS_0": false, + "REGION_1_PARAMS_1": false, + "REGION_1_PARAMS_2": false, + "REGION_2_PARAMS_0": true, + "REGION_2_PARAMS_1": true, + "REGION_2_PARAMS_2": true, + "REGION_3_PARAMS_0": false, + "REGION_3_PARAMS_1": false, + "REGION_3_PARAMS_2": false + }, + "region_0_protection": { + "mem_region_0_enabled": true, + "mem_region_0_device_id": 0, + "mem_region_0_spi_write_enable": true, + "mem_region_0_spi_read_enable": true, + "mem_region_0_physical_offset": 261, + "mem_region_0_security_id_msb": 0, + "mem_region_0_start_address": 81920, + "mem_region_0_end_address": 82682, + "mem_region_0_security_id_lsb": 0, + "mem_otfde_region_0_write_lock_en": false, + "mem_otfde_region_0_enc_dec_bypass": "Bypass" + }, + "region_1_protection": { + "mem_region_1_enabled": true, + "mem_region_1_device_id": 0, + "mem_region_1_spi_write_enable": true, + "mem_region_1_spi_read_enable": true, + "mem_region_1_physical_offset": 0, + "mem_region_1_security_id_msb": 0, + "mem_region_1_start_address": 655360, + "mem_region_1_end_address": 655620, + "mem_region_1_security_id_lsb": 0, + "mem_otfde_region_1_write_lock_en": false, + "mem_otfde_region_1_enc_dec_bypass": "Bypass" + }, + "region_2_protection": { + "mem_region_2_enabled": false, + "mem_region_2_device_id": 0, + "mem_region_2_spi_write_enable": true, + "mem_region_2_spi_read_enable": true, + "mem_region_2_physical_offset": 0, + "mem_region_2_security_id_msb": 0, + "mem_region_2_start_address": 1, + "mem_region_2_end_address": 0, + "mem_region_2_security_id_lsb": 0, + "mem_otfde_region_2_write_lock_en": false, + "mem_otfde_region_2_enc_dec_bypass": "Bypass" + }, + "region_3_protection": { + "mem_region_3_enabled": false, + "mem_region_3_device_id": 1, + "mem_region_3_spi_write_enable": true, + "mem_region_3_spi_read_enable": true, + "mem_region_3_physical_offset": 0, + "mem_region_3_security_id_msb": 0, + "mem_region_3_start_address": 1, + "mem_region_3_end_address": 0, + "mem_region_3_security_id_lsb": 0, + "mem_otfde_region_3_write_lock_en": false, + "mem_otfde_region_3_enc_dec_bypass": "Bypass" + } + }, + "devices": { + "header": { + "flash_device_switch_conf": 1, + "ram_device_switch_conf": 1 + }, + "flash_switch": { + "flash_grant_sel": 0, + "flash_data_for_conf_0": 2181562505, + "flash_offset_bits_for_conf_0": 0, + "flash_stop_bit_for_conf_0": 0, + "flash_data_for_conf_1": 67248651, + "flash_offset_bits_for_conf_1": 1, + "flash_stop_bit_for_conf_1": 0, + "flash_data_for_conf_2": 139266, + "flash_offset_bits_for_conf_2": 2, + "flash_stop_bit_for_conf_2": 0, + "flash_data_for_conf_3": 1, + "flash_offset_bits_for_conf_3": 4, + "flash_stop_bit_for_conf_3": 0, + "flash_data_for_conf_4": 1076887634, + "flash_offset_bits_for_conf_4": 45, + "flash_stop_bit_for_conf_4": 0, + "flash_data_for_conf_5": 3224371282, + "flash_offset_bits_for_conf_5": 45, + "flash_stop_bit_for_conf_5": 0, + "flash_data_for_conf_6": 262149, + "flash_offset_bits_for_conf_6": 14, + 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"ram_offset_bits_for_conf_21": 0, + "ram_stop_bit_for_conf_21": 1, + "ram_data_for_conf_22": 0, + "ram_offset_bits_for_conf_22": 0, + "ram_stop_bit_for_conf_22": 1, + "ram_data_for_conf_23": 0, + "ram_offset_bits_for_conf_23": 0, + "ram_stop_bit_for_conf_23": 1 + } + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/mx25u3235f/flash_disc_param_xspi.json b/boards/ti/lp_em_cc35x1/config/flash/mx25u3235f/flash_disc_param_xspi.json new file mode 100644 index 000000000000..87a7d3543805 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/mx25u3235f/flash_disc_param_xspi.json @@ -0,0 +1,485 @@ +{ + "xspi_header": { + "name": "xSPIWFF3", + "device": "CC3500", + "use_hardware": "MX25U3235F", + "use_case": "Quadro", + "dqs_support": 0, + "flash_only": 1, + "flash_separate_reset": 0, + "ram_separate_reset": true, + "clock_frequency": 80, + "qospi_clock_divider": 1, + "flash_device_character_conf": 0, + "ram_device_character_conf": 0, + "header_advanced": 0, + "phy_mode_enable": 1, + "pipeline_mode_enable": 1, + "loopback_support": "No", + "qspi_ref_clock": 80, + "spi_clock_freq": 20, + "spi_clock_divider": 1, + "flash_device_size": 4, + "flash_bytes_per_block": 16, + "flash_bytes_per_page": 256, + "flash_number_of_address_bytes": 3, + "flash_dual_opcode": 0, + "flash_jedec_manufacturer_id": 0, + "flash_jedec_device_id": 0, + "flash_name": "MX25U3235F", + "flash_page_size": 256, + "flash_sector_size": 4096, + "flash_cs_polarity": "ACTIVE_LOW", + "flash_sw_reset_type": "x1xxxx", + "ram_device_size": 4, + "ram_bytes_per_block": 16, + "ram_bytes_per_page": 256, + "ram_number_of_address_bytes": 3, + "ram_dual_opcode": 0, + "ram_jedec_manufacturer_id": 0, + "ram_jedec_device_id": 0, + "ram_name": "NO_PSRAM", + "ram_page_size": 256, + "ram_sector_size": 4096, + "ram_cs_polarity": "ACTIVE_LOW", + "ram_sw_reset_type": "x1xxxx", + "flash_write_operation_modes": "4S-4S-4S", + "flash_read_operation_modes": "4S-4S-4S", + "ram_write_operation_modes": "4S-4S-4S", + "ram_read_operation_modes": "4S-4S-4S", + "crc_enable": 0, + "enable_dtr": 0, + "enable_ahb_decoder": 0, + "enter_xip_mod_immediately": 0, + "enter_xip_mod_next_read": 0, + "ahb_address_remapping": 0, + "enable_dma": 0, + "select_decode": 0, + "legacy_ip_mode": 0, + "direct_access": 1 + }, + "xspi_pinmux": { + "xspi_clk_input": 44, + "xspi_clk_input_use_hw": 0, + "xspi_clk_input_mode": "Input", + "xspi_clk_input_pull": "None", + "xspi_clk_input_interrupt_trigger": "Low", + "xspi_clk_input_dont_conf": 0, + "xspi_clk_input_output_strength": "High", + "xspi_clk_input_initial_output_state": "High", + "xspi_clk": 24, + "xspi_clk_use_hw": "None", + "xspi_clk_mode": "Output", + "xspi_clk_pull": "None", + "xspi_clk_output_strength": "High", + "xspi_clk_initial_output_state": "High", + "xspi_clk_interrupt_trigger": "None", + "xspi_clk_dont_conf": 0, + "xspi_flash_cs": 20, + "xspi_flash_cs_use_hw": "None", + "xspi_flash_cs_mode": "Output", + "xspi_flash_cs_pull": "None", + "xspi_flash_cs_output_strength": "High", + "xspi_flash_cs_initial_output_state": "High", + "xspi_flash_cs_interrupt_trigger": "None", + "xspi_flash_cs_dont_conf": 0, + "xspi_data_0": 25, + "xspi_data_0_use_hw": "None", + "xspi_data_0_mode": "Input", + "xspi_data_0_pull": "None", + "xspi_data_0_output_strength": "High", + "xspi_data_0_initial_output_state": "High", + "xspi_data_0_interrupt_trigger": "Low", + "xspi_data_0_dont_conf": 0, + "xspi_data_1": 21, + "xspi_data_1_use_hw": "None", + "xspi_data_1_mode": "Input", + "xspi_data_1_pull": "None", + "xspi_data_1_output_strength": "High", + "xspi_data_1_initial_output_state": "High", + "xspi_data_1_interrupt_trigger": "Low", + "xspi_data_1_dont_conf": 0, + "xspi_data_2": 22, + "xspi_data_2_use_hw": "None", + "xspi_data_2_mode": "Input", + "xspi_data_2_pull": "None", + "xspi_data_2_output_strength": "High", + "xspi_data_2_initial_output_state": "High", + "xspi_data_2_interrupt_trigger": "Low", + "xspi_data_2_dont_conf": 0, + "xspi_data_3": 23, + "xspi_data_3_use_hw": "None", + "xspi_data_3_mode": "Input", + "xspi_data_3_pull": "None", + "xspi_data_3_output_strength": "High", + "xspi_data_3_initial_output_state": "High", + "xspi_data_3_interrupt_trigger": "Low", + "xspi_data_3_dont_conf": 0, + "xspi_data_4": 26, + "xspi_data_4_use_hw": "None", + "xspi_data_4_mode": "Input", + "xspi_data_4_pull": "None", + "xspi_data_4_output_strength": "High", + "xspi_data_4_initial_output_state": "High", + "xspi_data_4_interrupt_trigger": "None", + "xspi_data_4_dont_conf": 0, + "xspi_data_5": 27, + "xspi_data_5_use_hw": "None", + "xspi_data_5_mode": "Input", + "xspi_data_5_pull": "None", + "xspi_data_5_output_strength": "High", + "xspi_data_5_initial_output_state": "High", + "xspi_data_5_interrupt_trigger": "None", + "xspi_data_5_dont_conf": 0, + "xspi_data_6": 28, + "xspi_data_6_use_hw": "None", + "xspi_data_6_mode": "Input", + "xspi_data_6_pull": "None", + "xspi_data_6_output_strength": "High", + "xspi_data_6_initial_output_state": "High", + "xspi_data_6_interrupt_trigger": "None", + "xspi_data_6_dont_conf": 0, + "xspi_data_7": 29, + "xspi_data_7_use_hw": "None", + "xspi_data_7_mode": "Input", + "xspi_data_7_pull": "None", + "xspi_data_7_output_strength": "High", + "xspi_data_7_initial_output_state": "High", + "xspi_data_7_interrupt_trigger": "None", + "xspi_data_7_dont_conf": 0, + "xspi_reset_flash": 36, + "xspi_reset_flash_use_hw": "None", + "xspi_reset_flash_mode": "Output", + "xspi_reset_flash_pull": "None", + "xspi_reset_flash_output_strength": "High", + "xspi_reset_flash_initial_output_state": "High", + "xspi_reset_flash_interrupt_trigger": "None", + "xspi_reset_flash_dont_conf": 0, + "xspi_cs_ram": 3, + "xspi_cs_ram_use_hw": "None", + "xspi_cs_ram_mode": "Output", + "xspi_cs_ram_pull": "None", + "xspi_cs_ram_output_strength": "High", + "xspi_cs_ram_initial_output_state": "High", + "xspi_cs_ram_interrupt_trigger": "None", + "xspi_cs_ram_dont_conf": 0, + "xspi_dqs": 30, + "xspi_dqs_use_hw": "None", + "xspi_dqs_mode": "Input", + "xspi_dqs_pull": "None", + "xspi_dqs_output_strength": "High", + "xspi_dqs_initial_output_state": "High", + "xspi_dqs_interrupt_trigger": "None", + "xspi_dqs_dont_conf": 0, + "xspi_reset_ram": 2, + "xspi_reset_ram_use_hw": "None", + "xspi_reset_ram_mode": "Input", + "xspi_reset_ram_pull": "None", + "xspi_reset_ram_output_strength": "High", + "xspi_reset_ram_initial_output_state": "High", + "xspi_reset_ram_interrupt_trigger": "None", + "xspi_reset_ram_dont_conf": 0 + }, + "xspi_operations": { + "xspi_operations_clocks": { + "clock_phase": 0, + "clock_polarity": 0, + "spi_mode": "2'b00" + }, + "xspi_operations_chip_select": { + "csda": 2, + "csdads": 0, + "cseot": 4, + "cssot": 1 + }, + "xspi_operations_reset": { + "flash_jedec_reset": 0, + "ram_jedec_reset": 0, + "flash_treset": 20, + "ram_treset": 20 + }, + "xspi_phy_operations": { + "flash_rx_dll_bypass_bit": 0, + "flash_dll_tx_delay": 42, + "flash_dll_rx_delay": 62, + "ram_rx_dll_bypass_bit": 0, + "ram_dll_tx_delay": 42, + "ram_dll_rx_delay": 62 + }, + "xspi_read_operations": { + "flash_dummy_rd_cycles": 4, + "flash_read_opcode": 11, + "suppl_flash_read_opcode": 0, + "ram_dummy_rd_cycles": 4, + "ram_read_opcode": 11, + "suppl_ram_read_opcode": 0, + "flash_non_cont_read_enable": 0, + "flash_max_read_jobs": 256, + "ram_non_cont_read_enable": 0, + "ram_max_read_jobs": 256, + "rww_en": 0, + "device_size": 4, + "number_of_banks": 1, + "bank_size": 4, + "mode_bit_enable": 0 + }, + "xspi_write_operations": { + "flash_address_and_data": { + "flash_dummy_wr_cycles": 0 + }, + "flash_command": { + "flash_write_opcode": 2, + "suppl_flash_write_opcode": 0 + }, + "ram_address_and_data": { + "ram_dummy_wr_cycles": 0 + }, + "ram_command": { + "ram_write_opcode": 2, + "suppl_ram_write_opcode": 0 + }, + "write_to_buffer": { + "flash_write_to_buffer_support": 0, + "ram_write_to_buffer_support": 0 + }, + "non_continuous_write": { + "flash_non_cont_write_enable": 0, + "flash_max_write_jobs": 64, + "ram_non_cont_write_enable": 0, + "ram_max_write_jobs": 0 + }, + "flash_program_operation": { + "flash_min_program_size": "256 B", + "flash_program_opcode": 2, + "suppl_flash_program_opcode": 0, + "flash_maximum_program_time_limit": 1600 + }, + "flash_erase_operation": { + "flash_min_erase_size": "4 kB", + "flash_erase_opcode": 32, + "suppl_flash_erase_opcode": 0, + "flash_maximum_erase_time_limit": 4095 + }, + "flash_erase_conf": { + "flash_block_erase_opcode": 0, + "suppl_block_flash_erase_opcode": 0, + "flash_sector_erase_opcode": 0, + "suppl_sector_flash_erase_opcode": 0, + "flash_chip_erase_opcode": 0, + "suppl_chip_flash_erase_opcode": 0 + }, + "ram_program_operation": { + "ram_min_program_size": "256 B", + "ram_program_opcode": 2, + "suppl_ram_program_opcode": 0, + "ram_maximum_program_time_limit": 1600 + }, + "ram_erase_conf": { + "ram_block_erase_opcode": 0, + "suppl_block_ram_erase_opcode": 0, + "ram_sector_erase_opcode": 0, + "suppl_sector_ram_erase_opcode": 0, + "ram_chip_erase_opcode": 0, + "suppl_chip_ram_erase_opcode": 0 + }, + "flash_buffer_support": { + "flash_pre_write_sequence": 0, + "flash_post_write_sequence": 0, + "flash_write_protection_timer_en": 0, + "flash_write_buffer_timer_mode": 16, + "flash_write_buffer_timer_range": 0, + "flash_service_interrupt_criteria": 0 + }, + "ram_buffer_support": { + "ram_pre_write_sequence": 0, + "ram_post_write_sequence": 0, + "ram_write_protection_timer_en": 0, + "ram_write_buffer_timer_mode": 16, + "ram_write_buffer_timer_range": 0, + "ram_service_interrupt_criteria": 0 + }, + "flash_pre_write_conf": { + "flash_pre_write_job_done_grant_sel": 0, + "data_for_flash_pre_write_conf_0": 0, + "offset_bits_for_flash_pre_write_conf_0": 0, + "stop_bit_for_flash_pre_write_conf_0": 1, + "data_for_flash_pre_write_conf_1": 0, + "offset_bits_for_flash_pre_write_conf_1": 0 + }, + "flash_post_write_conf": { + "flash_post_write_job_done_grant_sel": 0, + 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0, + "flash_quad_enable_opcode": 53, + "suppl_flash_quad_enable_opcode": 0, + "flash_quad_disable_opcode": 245, + "suppl_flash_quad_disable_opcode": 0, + "flash_octal_enable_opcode": 0, + "suppl_flash_octal_enable_opcode": 0, + "flash_octal_disable_opcode": 0, + "suppl_flash_octal_disable_opcode": 0, + "ram_quad_enable_opcode": 53, + "suppl_ram_quad_enable_opcode": 0, + "ram_quad_disable_opcode": 245, + "suppl_ram_quad_disable_opcode": 0, + "ram_octal_enable_opcode": 0, + "suppl_ram_octal_enable_opcode": 0, + "ram_octal_disable_opcode": 0, + "suppl_ram_octal_disable_opcode": 0 + } + } + }, + "external_memory_reporting": { + "header": { + "flash_auto_polling_enable": 1, + "flash_wel_enable": 1, + "flash_write_protect_enable": 0, + "flash_alternate_polling_conf_enable": 0, + "ram_auto_polling_enable": 1, + "ram_wel_enable": 1, + "ram_write_protect_enable": 0, + "ram_alternate_polling_conf_enable": 0 + }, + "flash_auto_polling": { + "flash_polling_repetition_delay": 0, + "flash_polling_count": 4, + "flash_enable_polling_expiration": 0, + "flash_polling_polarity": 0, + "flash_polling_address_phase_enable": 0, + "flash_polling_bit_index": 0, + "flash_numbers_poll_cycles": 65535, + "flash_dummy_autopoll_cycles": 0 + }, + "ram_auto_polling": { + "ram_polling_repetition_delay": 0, + "ram_polling_count": 4, + "ram_enable_polling_expiration": 0, + "ram_polling_polarity": 0, + "ram_polling_address_phase_enable": 0, + "ram_polling_bit_index": 0, + "ram_numbers_poll_cycles": 65535, + "ram_dummy_autopoll_cycles": 0 + }, + "flash_polling_command": { + "flash_polling_opcode": 5, + "suppl_flash_polling_opcode": 0 + }, + "ram_polling_command": { + "ram_polling_opcode": 5, + "suppl_ram_polling_opcode": 0 + }, + "flash_alternate_polling": { + "flash_polling_resp_count": 1023, + "flash_polling_iterations": 1, + "flash_polling_enabled": 0, + "flash_polling_disabled": 0, + "flash_grant_sel": 0, + "flash_data_for_enable_poling_conf_0": 0, + "flash_offset_bits_for_enable_poling_conf_0": 0, + "flash_stop_bit_for_enable_poling_conf_0": 1, + "flash_data_for_enable_poling_conf_1": 0, + "flash_offset_bits_for_enable_poling_conf_1": 0, + "flash_stop_bit_for_enable_poling_conf_1": 1, + "flash_data_for_disable_poling_conf_0": 0, + "flash_offset_bits_for_disable_poling_conf_0": 0, + "flash_stop_bit_for_disable_poling_conf_0": 1, + "flash_data_for_disable_poling_conf_1": 0, + "flash_offset_bits_for_disable_poling_conf_1": 0, + "flash_stop_bit_for_disable_poling_conf_1": 1 + }, + "ram_alternate_polling": { + "ram_polling_resp_count": 1023, + "ram_polling_iterations": 1, + "ram_polling_enabled": 0, + "ram_polling_disabled": 0, + "ram_grant_sel": 0, + "ram_data_for_enable_poling_conf_0": 0, + "ram_offset_bits_for_enable_poling_conf_0": 0, + "ram_stop_bit_for_enable_poling_conf_0": 1, + "ram_data_for_enable_poling_conf_1": 0, + "ram_offset_bits_for_enable_poling_conf_1": 0, + "ram_stop_bit_for_enable_poling_conf_1": 1, + "ram_data_for_disable_poling_conf_0": 0, + "ram_offset_bits_for_disable_poling_conf_0": 0, + "ram_stop_bit_for_disable_poling_conf_0": 1, + "ram_data_for_disable_poling_conf_1": 0, + "ram_offset_bits_for_disable_poling_conf_1": 0, + "ram_stop_bit_for_disable_poling_conf_1": 1 + }, + "flash_wel_command": { + "flash_wel_opcode": 6, + "suppl_flash_wel_opcode": 0 + }, + "ram_wel_command": { + "ram_wel_opcode": 6, + "suppl_ram_wel_opcode": 0 + } + }, + "event": { + "host_nvic_irq": 0, + "core_10_mux_sel": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/mx25u6435f/flash_disc_param_ext_mem.json b/boards/ti/lp_em_cc35x1/config/flash/mx25u6435f/flash_disc_param_ext_mem.json new file mode 100644 index 000000000000..6585853ccd5e --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/mx25u6435f/flash_disc_param_ext_mem.json @@ -0,0 +1,99 @@ +{ + "vendor_primary_sbl": true, + "ti_wsoc_primary_container": true, + "ti_wsoc_bl2_primary_container": true, + "nvs_enable": true, + "vendor_alternate_image": true, + "vendor_sbl_alternate_image": true, + "ti_bl_alternate_image": true, + "ti_wsoc_alternate_image": true, + "ti_wsoc_bl2_alternate_image": true, + "region_0": { + "mem_region_0_start_phy_address": 2867200, + "mem_region_0_end_phy_address": 5627903, + "region0_boot": false, + "region0_main_code": true, + "region0_nvs": false, + "region0_wsoc_code": false, + "region0_alternate_code": false + }, + "region_1": { + "mem_region_1_start_phy_address": 0, + "mem_region_1_end_phy_address": 2867199, + "region1_boot": true, + "region1_main_code": false, + "region1_nvs": true, + "region1_wsoc_code": true, + "region1_alternate_code": false + }, + "region_2": { + "mem_region_2_start_phy_address": 5627904, + "mem_region_2_end_phy_address": 8388607, + "region2_boot": false, + "region2_main_code": false, + "region2_nvs": false, + "region2_wsoc_code": false, + "region2_alternate_code": true + }, + "region_3": { + "mem_region_3_start_phy_address": 0, + "mem_region_3_end_phy_address": 0, + "region3_boot": false, + "region3_main_code": false, + "region3_nvs": false, + "region3_wsoc_code": false, + "region3_alternate_code": false + }, + "boot_region_conf": { + "boot_region_size": 0, + "boot_region_flash_disco_param_start_address": 0, + "boot_region_primary_ti_bl_start_phy_address": 12284, + "boot_region_primary_ti_bl_magic": 0, + "boot_region_primary_ti_bl_major": 0, + "boot_region_primary_ti_bl_minor": 0, + "boot_region_sec_ti_bl_start_phy_address": 430076, + "boot_region_sec_ti_bl_magic": 0, + "boot_region_sec_ti_bl_major": 0, + "boot_region_sec_ti_bl_minor": 0 + }, + "main_code_region_conf": { + "main_code_region_vendor_image_start_phy_address": 2871292, + "main_code_region_vendor_image_magic": 0, + "main_code_region_vendor_image_major": 0, + "main_code_region_vendor_image_minor": 0, + "main_code_region_sbl_start_phy_address": 0, + "main_code_region_sbl_magic": 0, + "main_code_region_sbl_major": 0, + "main_code_region_sbl_minor": 0 + }, + "alt_code_region_conf": { + "alt_code_region_vendor_image_start_phy_address": 5631996, + "alt_code_region_vendor_image_magic": 0, + "alt_code_region_vendor_image_major": 0, + "alt_code_region_vendor_image_minor": 0, + "alt_code_region_sbl_start_phy_address": 0, + "alt_code_region_sbl_magic": 0, + "alt_code_region_sbl_major": 0, + "alt_code_region_sbl_minor": 0 + }, + "nvs_code_region_conf": { + "nvs_start_phy_address": 1777664, + "nvs_region_size": 1089536, + "nvs_region_primary_wsoc_start_phy_address": 847868, + "nvs_region_primary_wsoc_magic": 0, + "nvs_region_primary_wsoc_major": 0, + "nvs_region_primary_wsoc_minor": 0, + "nvs_region_sec_wsoc_start_phy_address": 1314812, + "nvs_region_sec_wsoc_magic": 0, + "nvs_region_sec_wsoc_major": 0, + "nvs_region_sec_wsoc_minor": 0, + "nvs_region_primary_wsoc_bl2_start_phy_address": 0, + "nvs_region_primary_wsoc_bl2_magic": 0, + "nvs_region_primary_wsoc_bl2_major": 0, + "nvs_region_primary_wsoc_bl2_minor": 0, + "nvs_region_sec_wsoc_bl2_start_phy_address": 0, + "nvs_region_sec_wsoc_bl2_magic": 0, + "nvs_region_sec_wsoc_bl2_major": 0, + "nvs_region_sec_wsoc_bl2_minor": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/mx25u6435f/flash_disc_param_otfde.json b/boards/ti/lp_em_cc35x1/config/flash/mx25u6435f/flash_disc_param_otfde.json new file mode 100644 index 000000000000..40d31f025e3c --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/mx25u6435f/flash_disc_param_otfde.json @@ -0,0 +1,286 @@ +{ + "otfde_header": { + "name": "OTFDEWFF3", + "flash_only": true, + "ip_protection": false, + "regions_lock": false, + "regions_number": 4, + "flash_enabled": true + }, + "bl_conf": { + "host_boot_done_lock": true, + "host_peripherals_lock": true, + "icache_conf_lock": true, + "m33_mem_part_lock": true, + "memss_firewall_lock": true, + "dma_channel_owner_lock": true, + "otfde_region_lock": true, + "core_events_lock": true + }, + "otfde_general": { + "parameters": { + "mem_otfde_initial_delay": 10, + "otfde_global_watchdog_timer": 5 + }, + "events": { + "reset_evt_mask": false, + "reset_evt_suspend": false, + "sft_reset_evt_mask": false, + "sft_reset_evt_suspend": false, + "bypass_mode_evt_mask": false, + "bypass_mode_evt_suspend": false, + "debug_mode_evt_mask": false, + "debug_mode_evt_suspend": false, + "general_evt_mask": false, + "general_evt_suspend": false, + "xspi_data_path_evt_mask": false, + "xspi_data_path_evt_suspend": false, + "xspi_cnfg_path_evt_mask": false, + "xspi_cnfg_path_evt_suspend": false, + "xspi_service_interrupt_evt_mask": false, + "xspi_service_interrupt_evt_suspend": false, + "trans_device_disabled_evt_mask": false, + "trans_device_disabled_evt_suspend": false, + "trans_region_disabled_evt_mask": false, + "trans_region_disabled_evt_suspend": false, + "trans_region_params_conf_evt_mask": false, + "trans_region_params_conf_evt_suspend": false, + "trans_multiple_regions_mapped_evt_mask": false, + "trans_multiple_regions_mapped_evt_suspend": false, + "trans_address_not_32_bit_evt_mask": false, + "trans_address_not_32_bit_evt_suspend": false, + "trans_size_not_32_bit_evt_mask": false, + "trans_size_not_32_bit_evt_suspend": false, + "trans_burst_not_32_bit_evt_mask": false, + "trans_burst_not_32_bit_evt_suspend": false, + "region_read_write_def_evt_mask": false, + "region_read_write_def_evt_suspend": false, + "suspend_while_disabled_evt_mask": false, + "suspend_while_disabled_evt_suspend": false + } + }, + "regions_settings": { + "region_parameters_lock": { + "REGION_0_PARAMS_0": true, + "REGION_0_PARAMS_1": true, + "REGION_0_PARAMS_2": true, + "REGION_1_PARAMS_0": false, + "REGION_1_PARAMS_1": false, + "REGION_1_PARAMS_2": false, + "REGION_2_PARAMS_0": true, + "REGION_2_PARAMS_1": true, + "REGION_2_PARAMS_2": true, + "REGION_3_PARAMS_0": false, + "REGION_3_PARAMS_1": false, + "REGION_3_PARAMS_2": false + }, + "region_0_protection": { + "mem_region_0_enabled": true, + "mem_region_0_device_id": 0, + "mem_region_0_spi_write_enable": true, + "mem_region_0_spi_read_enable": true, + "mem_region_0_physical_offset": 700, + "mem_region_0_security_id_msb": 0, + "mem_region_0_start_address": 81920, + "mem_region_0_end_address": 82593, + "mem_region_0_security_id_lsb": 0, + "mem_otfde_region_0_write_lock_en": false, + "mem_otfde_region_0_enc_dec_bypass": "Bypass" + }, + "region_1_protection": { + "mem_region_1_enabled": true, + "mem_region_1_device_id": 0, + "mem_region_1_spi_write_enable": true, + "mem_region_1_spi_read_enable": true, + "mem_region_1_physical_offset": 0, + "mem_region_1_security_id_msb": 0, + "mem_region_1_start_address": 655360, + "mem_region_1_end_address": 656059, + "mem_region_1_security_id_lsb": 0, + "mem_otfde_region_1_write_lock_en": false, + "mem_otfde_region_1_enc_dec_bypass": "Bypass" + }, + "region_2_protection": { + "mem_region_2_enabled": true, + "mem_region_2_device_id": 0, + "mem_region_2_spi_write_enable": true, + "mem_region_2_spi_read_enable": true, + "mem_region_2_physical_offset": 1374, + "mem_region_2_security_id_msb": 0, + "mem_region_2_start_address": 671744, + "mem_region_2_end_address": 672417, + "mem_region_2_security_id_lsb": 0, + "mem_otfde_region_2_write_lock_en": false, + "mem_otfde_region_2_enc_dec_bypass": "Bypass" + }, + "region_3_protection": { + "mem_region_3_enabled": false, + "mem_region_3_device_id": 1, + "mem_region_3_spi_write_enable": true, + "mem_region_3_spi_read_enable": true, + "mem_region_3_physical_offset": 0, + "mem_region_3_security_id_msb": 0, + "mem_region_3_start_address": 1, + "mem_region_3_end_address": 0, + "mem_region_3_security_id_lsb": 0, + "mem_otfde_region_3_write_lock_en": false, + "mem_otfde_region_3_enc_dec_bypass": "Bypass" + } + }, + "devices": { + "header": { + "flash_device_switch_conf": 1, + "ram_device_switch_conf": 1 + }, + "flash_switch": { + "flash_grant_sel": 0, + "flash_data_for_conf_0": 2181562505, + "flash_offset_bits_for_conf_0": 0, + "flash_stop_bit_for_conf_0": 0, + "flash_data_for_conf_1": 67248651, + "flash_offset_bits_for_conf_1": 1, + "flash_stop_bit_for_conf_1": 0, + "flash_data_for_conf_2": 139266, + "flash_offset_bits_for_conf_2": 2, + "flash_stop_bit_for_conf_2": 0, + "flash_data_for_conf_3": 1, + "flash_offset_bits_for_conf_3": 4, + "flash_stop_bit_for_conf_3": 0, + "flash_data_for_conf_4": 1076887634, + "flash_offset_bits_for_conf_4": 45, + "flash_stop_bit_for_conf_4": 0, + "flash_data_for_conf_5": 3224371282, + "flash_offset_bits_for_conf_5": 45, + "flash_stop_bit_for_conf_5": 0, + "flash_data_for_conf_6": 262149, + "flash_offset_bits_for_conf_6": 14, + "flash_stop_bit_for_conf_6": 0, + "flash_data_for_conf_7": 0, + "flash_offset_bits_for_conf_7": 44, + "flash_stop_bit_for_conf_7": 1, + "flash_data_for_conf_8": 0, + "flash_offset_bits_for_conf_8": 0, + "flash_stop_bit_for_conf_8": 1, + "flash_data_for_conf_9": 0, + "flash_offset_bits_for_conf_9": 0, + "flash_stop_bit_for_conf_9": 1, + "flash_data_for_conf_10": 0, + "flash_offset_bits_for_conf_10": 0, + "flash_stop_bit_for_conf_10": 1, + "flash_data_for_conf_11": 0, + "flash_offset_bits_for_conf_11": 0, + "flash_stop_bit_for_conf_11": 1, + "flash_data_for_conf_12": 0, + "flash_offset_bits_for_conf_12": 0, + "flash_stop_bit_for_conf_12": 1, + "flash_data_for_conf_13": 0, + "flash_offset_bits_for_conf_13": 0, + "flash_stop_bit_for_conf_13": 1, + "flash_data_for_conf_14": 0, + "flash_offset_bits_for_conf_14": 0, + "flash_stop_bit_for_conf_14": 1, + "flash_data_for_conf_15": 0, + "flash_offset_bits_for_conf_15": 0, + "flash_stop_bit_for_conf_15": 1, + "flash_data_for_conf_16": 0, + "flash_offset_bits_for_conf_16": 0, + "flash_stop_bit_for_conf_16": 1, + "flash_data_for_conf_17": 0, + "flash_offset_bits_for_conf_17": 0, + "flash_stop_bit_for_conf_17": 1, + "flash_data_for_conf_18": 0, + "flash_offset_bits_for_conf_18": 0, + "flash_stop_bit_for_conf_18": 1, + "flash_data_for_conf_19": 0, + "flash_offset_bits_for_conf_19": 0, + "flash_stop_bit_for_conf_19": 1, + "flash_data_for_conf_20": 0, + "flash_offset_bits_for_conf_20": 0, + "flash_stop_bit_for_conf_20": 1, + "flash_data_for_conf_21": 0, + "flash_offset_bits_for_conf_21": 0, + "flash_stop_bit_for_conf_21": 1, + "flash_data_for_conf_22": 0, + "flash_offset_bits_for_conf_22": 0, + "flash_stop_bit_for_conf_22": 1, + "flash_data_for_conf_23": 0, + "flash_offset_bits_for_conf_23": 0, + "flash_stop_bit_for_conf_23": 1 + }, + "ram_switch": { + "ram_grant_sel": 0, + "ram_data_for_conf_0": 2181562505, + "ram_offset_bits_for_conf_0": 0, + "ram_stop_bit_for_conf_0": 0, + "ram_data_for_conf_1": 67248651, + "ram_offset_bits_for_conf_1": 1, + "ram_stop_bit_for_conf_1": 0, + "ram_data_for_conf_2": 139266, + "ram_offset_bits_for_conf_2": 2, + "ram_stop_bit_for_conf_2": 0, + "ram_data_for_conf_3": 1, + "ram_offset_bits_for_conf_3": 4, + "ram_stop_bit_for_conf_3": 0, + "ram_data_for_conf_4": 1076887634, + "ram_offset_bits_for_conf_4": 45, + "ram_stop_bit_for_conf_4": 0, + "ram_data_for_conf_5": 3224371282, + "ram_offset_bits_for_conf_5": 45, + "ram_stop_bit_for_conf_5": 0, + "ram_data_for_conf_6": 262149, + "ram_offset_bits_for_conf_6": 14, + "ram_stop_bit_for_conf_6": 0, + "ram_data_for_conf_7": 0, + "ram_offset_bits_for_conf_7": 44, + "ram_stop_bit_for_conf_7": 1, + "ram_data_for_conf_8": 0, + "ram_offset_bits_for_conf_8": 0, + "ram_stop_bit_for_conf_8": 1, + "ram_data_for_conf_9": 0, + "ram_offset_bits_for_conf_9": 0, + "ram_stop_bit_for_conf_9": 1, + "ram_data_for_conf_10": 0, + "ram_offset_bits_for_conf_10": 0, + "ram_stop_bit_for_conf_10": 1, + "ram_data_for_conf_11": 0, + "ram_offset_bits_for_conf_11": 0, + "ram_stop_bit_for_conf_11": 1, + "ram_data_for_conf_12": 0, + "ram_offset_bits_for_conf_12": 0, + "ram_stop_bit_for_conf_12": 1, + "ram_data_for_conf_13": 0, + "ram_offset_bits_for_conf_13": 0, + "ram_stop_bit_for_conf_13": 1, + "ram_data_for_conf_14": 0, + "ram_offset_bits_for_conf_14": 0, + "ram_stop_bit_for_conf_14": 1, + "ram_data_for_conf_15": 0, + "ram_offset_bits_for_conf_15": 0, + "ram_stop_bit_for_conf_15": 1, + "ram_data_for_conf_16": 0, + "ram_offset_bits_for_conf_16": 0, + "ram_stop_bit_for_conf_16": 1, + "ram_data_for_conf_17": 0, + "ram_offset_bits_for_conf_17": 0, + "ram_stop_bit_for_conf_17": 1, + "ram_data_for_conf_18": 0, + "ram_offset_bits_for_conf_18": 0, + "ram_stop_bit_for_conf_18": 1, + "ram_data_for_conf_19": 0, + "ram_offset_bits_for_conf_19": 0, + "ram_stop_bit_for_conf_19": 1, + "ram_data_for_conf_20": 0, + "ram_offset_bits_for_conf_20": 0, + "ram_stop_bit_for_conf_20": 1, + "ram_data_for_conf_21": 0, + "ram_offset_bits_for_conf_21": 0, + "ram_stop_bit_for_conf_21": 1, + "ram_data_for_conf_22": 0, + "ram_offset_bits_for_conf_22": 0, + "ram_stop_bit_for_conf_22": 1, + "ram_data_for_conf_23": 0, + "ram_offset_bits_for_conf_23": 0, + "ram_stop_bit_for_conf_23": 1 + } + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/mx25u6435f/flash_disc_param_xspi.json b/boards/ti/lp_em_cc35x1/config/flash/mx25u6435f/flash_disc_param_xspi.json new file mode 100644 index 000000000000..6d30f5b1665e --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/mx25u6435f/flash_disc_param_xspi.json @@ -0,0 +1,485 @@ +{ + "xspi_header": { + "name": "xSPIWFF3", + "device": "CC3500", + "use_hardware": "MX25U6435F", + "use_case": "Quadro", + "dqs_support": 0, + "flash_only": 1, + "flash_separate_reset": 0, + "ram_separate_reset": true, + "clock_frequency": 80, + "qospi_clock_divider": 1, + "flash_device_character_conf": 0, + "ram_device_character_conf": 0, + "header_advanced": 0, + "phy_mode_enable": 1, + "pipeline_mode_enable": 1, + "loopback_support": "No", + "qspi_ref_clock": 80, + "spi_clock_freq": 20, + "spi_clock_divider": 1, + "flash_device_size": 8, + "flash_bytes_per_block": 16, + "flash_bytes_per_page": 256, + "flash_number_of_address_bytes": 3, + "flash_dual_opcode": 0, + "flash_jedec_manufacturer_id": 0, + "flash_jedec_device_id": 0, + "flash_name": "MX25U6435F", + "flash_page_size": 256, + "flash_sector_size": 4096, + "flash_cs_polarity": "ACTIVE_LOW", + "flash_sw_reset_type": "x1xxxx", + "ram_device_size": 8, + "ram_bytes_per_block": 16, + "ram_bytes_per_page": 256, + "ram_number_of_address_bytes": 3, + "ram_dual_opcode": 0, + "ram_jedec_manufacturer_id": 0, + "ram_jedec_device_id": 0, + "ram_name": "NO_PSRAM", + "ram_page_size": 256, + "ram_sector_size": 4096, + "ram_cs_polarity": "ACTIVE_LOW", + "ram_sw_reset_type": "x1xxxx", + "flash_write_operation_modes": "4S-4S-4S", + "flash_read_operation_modes": "4S-4S-4S", + "ram_write_operation_modes": "4S-4S-4S", + "ram_read_operation_modes": "4S-4S-4S", + "crc_enable": 0, + "enable_dtr": 0, + "enable_ahb_decoder": 0, + "enter_xip_mod_immediately": 0, + "enter_xip_mod_next_read": 0, + "ahb_address_remapping": 0, + "enable_dma": 0, + "select_decode": 0, + "legacy_ip_mode": 0, + "direct_access": 1 + }, + "xspi_pinmux": { + "xspi_clk_input": 44, + "xspi_clk_input_use_hw": 0, + "xspi_clk_input_mode": "Input", + "xspi_clk_input_pull": "None", + "xspi_clk_input_interrupt_trigger": "Low", + "xspi_clk_input_dont_conf": 0, + "xspi_clk_input_output_strength": "High", + "xspi_clk_input_initial_output_state": "High", + "xspi_clk": 24, + "xspi_clk_use_hw": "None", + "xspi_clk_mode": "Output", + "xspi_clk_pull": "None", + "xspi_clk_output_strength": "High", + "xspi_clk_initial_output_state": "High", + "xspi_clk_interrupt_trigger": "None", + "xspi_clk_dont_conf": 0, + "xspi_flash_cs": 20, + "xspi_flash_cs_use_hw": "None", + "xspi_flash_cs_mode": "Output", + "xspi_flash_cs_pull": "None", + "xspi_flash_cs_output_strength": "High", + "xspi_flash_cs_initial_output_state": "High", + "xspi_flash_cs_interrupt_trigger": "None", + "xspi_flash_cs_dont_conf": 0, + "xspi_data_0": 25, + "xspi_data_0_use_hw": "None", + "xspi_data_0_mode": "Input", + "xspi_data_0_pull": "None", + "xspi_data_0_output_strength": "High", + "xspi_data_0_initial_output_state": "High", + "xspi_data_0_interrupt_trigger": "Low", + "xspi_data_0_dont_conf": 0, + "xspi_data_1": 21, + "xspi_data_1_use_hw": "None", + "xspi_data_1_mode": "Input", + "xspi_data_1_pull": "None", + "xspi_data_1_output_strength": "High", + "xspi_data_1_initial_output_state": "High", + "xspi_data_1_interrupt_trigger": "Low", + "xspi_data_1_dont_conf": 0, + "xspi_data_2": 22, + "xspi_data_2_use_hw": "None", + "xspi_data_2_mode": "Input", + "xspi_data_2_pull": "None", + "xspi_data_2_output_strength": "High", + "xspi_data_2_initial_output_state": "High", + "xspi_data_2_interrupt_trigger": "Low", + "xspi_data_2_dont_conf": 0, + "xspi_data_3": 23, + "xspi_data_3_use_hw": "None", + "xspi_data_3_mode": "Input", + "xspi_data_3_pull": "None", + "xspi_data_3_output_strength": "High", + "xspi_data_3_initial_output_state": "High", + "xspi_data_3_interrupt_trigger": "Low", + "xspi_data_3_dont_conf": 0, + "xspi_data_4": 26, + "xspi_data_4_use_hw": "None", + "xspi_data_4_mode": "Input", + "xspi_data_4_pull": "None", + "xspi_data_4_output_strength": "High", + "xspi_data_4_initial_output_state": "High", + "xspi_data_4_interrupt_trigger": "None", + "xspi_data_4_dont_conf": 0, + "xspi_data_5": 27, + "xspi_data_5_use_hw": "None", + "xspi_data_5_mode": "Input", + "xspi_data_5_pull": "None", + "xspi_data_5_output_strength": "High", + "xspi_data_5_initial_output_state": "High", + "xspi_data_5_interrupt_trigger": "None", + "xspi_data_5_dont_conf": 0, + "xspi_data_6": 28, + "xspi_data_6_use_hw": "None", + "xspi_data_6_mode": "Input", + "xspi_data_6_pull": "None", + "xspi_data_6_output_strength": "High", + "xspi_data_6_initial_output_state": "High", + "xspi_data_6_interrupt_trigger": "None", + "xspi_data_6_dont_conf": 0, + "xspi_data_7": 29, + "xspi_data_7_use_hw": "None", + "xspi_data_7_mode": "Input", + "xspi_data_7_pull": "None", + "xspi_data_7_output_strength": "High", + "xspi_data_7_initial_output_state": "High", + "xspi_data_7_interrupt_trigger": "None", + "xspi_data_7_dont_conf": 0, + "xspi_reset_flash": 36, + "xspi_reset_flash_use_hw": "None", + "xspi_reset_flash_mode": "Output", + "xspi_reset_flash_pull": "None", + "xspi_reset_flash_output_strength": "High", + "xspi_reset_flash_initial_output_state": "High", + "xspi_reset_flash_interrupt_trigger": "None", + "xspi_reset_flash_dont_conf": 0, + "xspi_cs_ram": 3, + "xspi_cs_ram_use_hw": "None", + "xspi_cs_ram_mode": "Output", + "xspi_cs_ram_pull": "None", + "xspi_cs_ram_output_strength": "High", + "xspi_cs_ram_initial_output_state": "High", + "xspi_cs_ram_interrupt_trigger": "None", + "xspi_cs_ram_dont_conf": 0, + "xspi_dqs": 30, + "xspi_dqs_use_hw": "None", + "xspi_dqs_mode": "Input", + "xspi_dqs_pull": "None", + "xspi_dqs_output_strength": "High", + "xspi_dqs_initial_output_state": "High", + "xspi_dqs_interrupt_trigger": "None", + "xspi_dqs_dont_conf": 0, + "xspi_reset_ram": 2, + "xspi_reset_ram_use_hw": "None", + "xspi_reset_ram_mode": "Input", + "xspi_reset_ram_pull": "None", + "xspi_reset_ram_output_strength": "High", + "xspi_reset_ram_initial_output_state": "High", + "xspi_reset_ram_interrupt_trigger": "None", + "xspi_reset_ram_dont_conf": 0 + }, + "xspi_operations": { + "xspi_operations_clocks": { + "clock_phase": 0, + "clock_polarity": 0, + "spi_mode": "2'b00" + }, + "xspi_operations_chip_select": { + "csda": 2, + "csdads": 0, + "cseot": 4, + "cssot": 1 + }, + "xspi_operations_reset": { + "flash_jedec_reset": 0, + "ram_jedec_reset": 0, + "flash_treset": 20, + "ram_treset": 20 + }, + "xspi_phy_operations": { + "flash_rx_dll_bypass_bit": 0, + "flash_dll_tx_delay": 42, + "flash_dll_rx_delay": 62, + "ram_rx_dll_bypass_bit": 0, + "ram_dll_tx_delay": 42, + "ram_dll_rx_delay": 62 + }, + "xspi_read_operations": { + "flash_dummy_rd_cycles": 4, + "flash_read_opcode": 11, + "suppl_flash_read_opcode": 0, + "ram_dummy_rd_cycles": 4, + "ram_read_opcode": 11, + "suppl_ram_read_opcode": 0, + "flash_non_cont_read_enable": 0, + "flash_max_read_jobs": 256, + "ram_non_cont_read_enable": 0, + "ram_max_read_jobs": 256, + "rww_en": 0, + "device_size": 8, + "number_of_banks": 1, + "bank_size": 8, + "mode_bit_enable": 0 + }, + "xspi_write_operations": { + "flash_address_and_data": { + "flash_dummy_wr_cycles": 0 + }, + "flash_command": { + "flash_write_opcode": 2, + "suppl_flash_write_opcode": 0 + }, + "ram_address_and_data": { + "ram_dummy_wr_cycles": 0 + }, + "ram_command": { + "ram_write_opcode": 2, + "suppl_ram_write_opcode": 0 + }, + "write_to_buffer": { + "flash_write_to_buffer_support": 0, + "ram_write_to_buffer_support": 0 + }, + "non_continuous_write": { + "flash_non_cont_write_enable": 0, + "flash_max_write_jobs": 64, + "ram_non_cont_write_enable": 0, + "ram_max_write_jobs": 0 + }, + "flash_program_operation": { + "flash_min_program_size": "256 B", + "flash_program_opcode": 2, + "suppl_flash_program_opcode": 0, + "flash_maximum_program_time_limit": 1600 + }, + "flash_erase_operation": { + "flash_min_erase_size": "4 kB", + "flash_erase_opcode": 32, + "suppl_flash_erase_opcode": 0, + "flash_maximum_erase_time_limit": 4095 + }, + "flash_erase_conf": { + "flash_block_erase_opcode": 0, + "suppl_block_flash_erase_opcode": 0, + "flash_sector_erase_opcode": 0, + "suppl_sector_flash_erase_opcode": 0, + "flash_chip_erase_opcode": 0, + "suppl_chip_flash_erase_opcode": 0 + }, + "ram_program_operation": { + "ram_min_program_size": "256 B", + "ram_program_opcode": 2, + "suppl_ram_program_opcode": 0, + "ram_maximum_program_time_limit": 1600 + }, + "ram_erase_conf": { + "ram_block_erase_opcode": 0, + "suppl_block_ram_erase_opcode": 0, + "ram_sector_erase_opcode": 0, + "suppl_sector_ram_erase_opcode": 0, + "ram_chip_erase_opcode": 0, + "suppl_chip_ram_erase_opcode": 0 + }, + "flash_buffer_support": { + "flash_pre_write_sequence": 0, + "flash_post_write_sequence": 0, + "flash_write_protection_timer_en": 0, + "flash_write_buffer_timer_mode": 16, + "flash_write_buffer_timer_range": 0, + "flash_service_interrupt_criteria": 0 + }, + "ram_buffer_support": { + "ram_pre_write_sequence": 0, + "ram_post_write_sequence": 0, + "ram_write_protection_timer_en": 0, + "ram_write_buffer_timer_mode": 16, + "ram_write_buffer_timer_range": 0, + "ram_service_interrupt_criteria": 0 + }, + "flash_pre_write_conf": { + "flash_pre_write_job_done_grant_sel": 0, + "data_for_flash_pre_write_conf_0": 0, + "offset_bits_for_flash_pre_write_conf_0": 0, + "stop_bit_for_flash_pre_write_conf_0": 1, + "data_for_flash_pre_write_conf_1": 0, + "offset_bits_for_flash_pre_write_conf_1": 0 + }, + "flash_post_write_conf": { + "flash_post_write_job_done_grant_sel": 0, + "data_for_flash_post_write_conf_0": 0, + "offset_bits_for_flash_post_write_conf_0": 0, + "stop_bit_for_flash_post_write_conf_0": 1, + "data_for_flash_post_write_conf_1": 0, + "offset_bits_for_flash_post_write_conf_1": 0 + }, + "ram_pre_write_conf": { + "ram_pre_write_job_done_grant_sel": 0, + "data_for_ram_pre_write_conf_0": 0, + "offset_bits_for_ram_pre_write_conf_0": 0, + "stop_bit_for_ram_pre_write_conf_0": 1, + "data_for_ram_pre_write_conf_1": 0, + "offset_bits_for_ram_pre_write_conf_1": 0 + }, + "ram_post_write_conf": { + "ram_post_write_job_done_grant_sel": 0, + "data_for_ram_post_write_conf_0": 0, + "offset_bits_for_ram_post_write_conf_0": 0, + "stop_bit_for_ram_post_write_conf_0": 1, + "data_for_ram_post_write_conf_1": 0, + "offset_bits_for_ram_post_write_conf_1": 0 + } + }, + "xspi_capture_operations": { + "read_data_capture": { + "flash_delay_transmitted_data": 0, + "flash_loopback_clock": 0, + "flash_bypass_adapted_loopback": 1, + "flash_sample_edge_sel": 0, + "ram_delay_transmitted_data": 0, + "ram_loopback_clock": 0, + "ram_bypass_adapted_loopback": 1, + "ram_sample_edge_sel": 0 + }, + "delays": { + "flash_full_half_cycle_delay": 0, + "flash_dll_bypass_mode": 1, + "flash_phase_detect_sel": 0, + "flash_dll_lock_num": 0, + "flash_dll_start_point": 0, + "flash_loopback_clock": 0, + "ram_full_half_cycle_delay": 0, + "ram_dll_bypass_mode": 1, + "ram_phase_detect_sel": 0, + "ram_dll_lock_num": 0, + "ram_dll_start_point": 0, + "ram_loopback_clock": 0 + }, + "operation_modes": { + "flash_sfdp_support": 0, + "ram_sfdp_support": 0, + "flash_pm_support": 0, + "ram_pm_support": 0, + "flash_sfdp_opcode": 0, + "suppl_flash_sfdp_opcode": 0, + "ram_sfdp_opcode": 0, + "suppl_ram_sfdp_opcode": 0, + "flash_enter_dpd_opcode": 185, + "suppl_flash_enter_dpd_opcode": 0, + "flash_exit_dpd_opcode": 171, + "suppl_flash_exit_dpd_opcode": 0, + "ram_enter_dpd_opcode": 185, + "suppl_ram_enter_dpd_opcode": 0, + "ram_exit_dpd_opcode": 171, + "suppl_ram_exit_dpd_opcode": 0, + "flash_quad_enable_opcode": 53, + "suppl_flash_quad_enable_opcode": 0, + "flash_quad_disable_opcode": 245, + "suppl_flash_quad_disable_opcode": 0, + "flash_octal_enable_opcode": 0, + "suppl_flash_octal_enable_opcode": 0, + "flash_octal_disable_opcode": 0, + "suppl_flash_octal_disable_opcode": 0, + "ram_quad_enable_opcode": 53, + "suppl_ram_quad_enable_opcode": 0, + "ram_quad_disable_opcode": 245, + "suppl_ram_quad_disable_opcode": 0, + "ram_octal_enable_opcode": 0, + "suppl_ram_octal_enable_opcode": 0, + "ram_octal_disable_opcode": 0, + "suppl_ram_octal_disable_opcode": 0 + } + } + }, + "external_memory_reporting": { + "header": { + "flash_auto_polling_enable": 1, + "flash_wel_enable": 1, + "flash_write_protect_enable": 0, + "flash_alternate_polling_conf_enable": 0, + "ram_auto_polling_enable": 1, + "ram_wel_enable": 1, + "ram_write_protect_enable": 0, + "ram_alternate_polling_conf_enable": 0 + }, + "flash_auto_polling": { + "flash_polling_repetition_delay": 0, + "flash_polling_count": 4, + "flash_enable_polling_expiration": 0, + "flash_polling_polarity": 0, + "flash_polling_address_phase_enable": 0, + "flash_polling_bit_index": 0, + "flash_numbers_poll_cycles": 65535, + "flash_dummy_autopoll_cycles": 0 + }, + "ram_auto_polling": { + "ram_polling_repetition_delay": 0, + "ram_polling_count": 4, + "ram_enable_polling_expiration": 0, + "ram_polling_polarity": 0, + "ram_polling_address_phase_enable": 0, + "ram_polling_bit_index": 0, + "ram_numbers_poll_cycles": 65535, + "ram_dummy_autopoll_cycles": 0 + }, + "flash_polling_command": { + "flash_polling_opcode": 5, + "suppl_flash_polling_opcode": 0 + }, + "ram_polling_command": { + "ram_polling_opcode": 5, + "suppl_ram_polling_opcode": 0 + }, + "flash_alternate_polling": { + "flash_polling_resp_count": 1023, + "flash_polling_iterations": 1, + "flash_polling_enabled": 0, + "flash_polling_disabled": 0, + "flash_grant_sel": 0, + "flash_data_for_enable_poling_conf_0": 0, + "flash_offset_bits_for_enable_poling_conf_0": 0, + "flash_stop_bit_for_enable_poling_conf_0": 1, + "flash_data_for_enable_poling_conf_1": 0, + "flash_offset_bits_for_enable_poling_conf_1": 0, + "flash_stop_bit_for_enable_poling_conf_1": 1, + "flash_data_for_disable_poling_conf_0": 0, + "flash_offset_bits_for_disable_poling_conf_0": 0, + "flash_stop_bit_for_disable_poling_conf_0": 1, + "flash_data_for_disable_poling_conf_1": 0, + "flash_offset_bits_for_disable_poling_conf_1": 0, + "flash_stop_bit_for_disable_poling_conf_1": 1 + }, + "ram_alternate_polling": { + "ram_polling_resp_count": 1023, + "ram_polling_iterations": 1, + "ram_polling_enabled": 0, + "ram_polling_disabled": 0, + "ram_grant_sel": 0, + "ram_data_for_enable_poling_conf_0": 0, + "ram_offset_bits_for_enable_poling_conf_0": 0, + "ram_stop_bit_for_enable_poling_conf_0": 1, + "ram_data_for_enable_poling_conf_1": 0, + "ram_offset_bits_for_enable_poling_conf_1": 0, + "ram_stop_bit_for_enable_poling_conf_1": 1, + "ram_data_for_disable_poling_conf_0": 0, + "ram_offset_bits_for_disable_poling_conf_0": 0, + "ram_stop_bit_for_disable_poling_conf_0": 1, + "ram_data_for_disable_poling_conf_1": 0, + "ram_offset_bits_for_disable_poling_conf_1": 0, + "ram_stop_bit_for_disable_poling_conf_1": 1 + }, + "flash_wel_command": { + "flash_wel_opcode": 6, + "suppl_flash_wel_opcode": 0 + }, + "ram_wel_command": { + "ram_wel_opcode": 6, + "suppl_ram_wel_opcode": 0 + } + }, + "event": { + "host_nvic_irq": 0, + "core_10_mux_sel": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/py25q128la/flash_disc_param_ext_mem.json b/boards/ti/lp_em_cc35x1/config/flash/py25q128la/flash_disc_param_ext_mem.json new file mode 100644 index 000000000000..14d05d9aba5a --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/py25q128la/flash_disc_param_ext_mem.json @@ -0,0 +1,99 @@ +{ + "vendor_primary_sbl": true, + "ti_wsoc_primary_container": true, + "ti_wsoc_bl2_primary_container": true, + "nvs_enable": true, + "vendor_alternate_image": true, + "vendor_sbl_alternate_image": true, + "ti_bl_alternate_image": true, + "ti_wsoc_alternate_image": true, + "ti_wsoc_bl2_alternate_image": true, + "region_0": { + "mem_region_0_start_phy_address": 2867200, + "mem_region_0_end_phy_address": 9822207, + "region0_boot": false, + "region0_main_code": true, + "region0_nvs": false, + "region0_wsoc_code": false, + "region0_alternate_code": false + }, + "region_1": { + "mem_region_1_start_phy_address": 0, + "mem_region_1_end_phy_address": 2867199, + "region1_boot": true, + "region1_main_code": false, + "region1_nvs": true, + "region1_wsoc_code": true, + "region1_alternate_code": false + }, + "region_2": { + "mem_region_2_start_phy_address": 9822208, + "mem_region_2_end_phy_address": 16777215, + "region2_boot": false, + "region2_main_code": false, + "region2_nvs": false, + "region2_wsoc_code": false, + "region2_alternate_code": true + }, + "region_3": { + "mem_region_3_start_phy_address": 0, + "mem_region_3_end_phy_address": 0, + "region3_boot": false, + "region3_main_code": false, + "region3_nvs": false, + "region3_wsoc_code": false, + "region3_alternate_code": false + }, + "boot_region_conf": { + "boot_region_size": 0, + "boot_region_flash_disco_param_start_address": 0, + "boot_region_primary_ti_bl_start_phy_address": 12284, + "boot_region_primary_ti_bl_magic": 0, + "boot_region_primary_ti_bl_major": 0, + "boot_region_primary_ti_bl_minor": 0, + "boot_region_sec_ti_bl_start_phy_address": 430076, + "boot_region_sec_ti_bl_magic": 0, + "boot_region_sec_ti_bl_major": 0, + "boot_region_sec_ti_bl_minor": 0 + }, + "main_code_region_conf": { + "main_code_region_vendor_image_start_phy_address": 2871292, + "main_code_region_vendor_image_magic": 0, + "main_code_region_vendor_image_major": 0, + "main_code_region_vendor_image_minor": 0, + "main_code_region_sbl_start_phy_address": 0, + "main_code_region_sbl_magic": 0, + "main_code_region_sbl_major": 0, + "main_code_region_sbl_minor": 0 + }, + "alt_code_region_conf": { + "alt_code_region_vendor_image_start_phy_address": 9826300, + "alt_code_region_vendor_image_magic": 0, + "alt_code_region_vendor_image_major": 0, + "alt_code_region_vendor_image_minor": 0, + "alt_code_region_sbl_start_phy_address": 0, + "alt_code_region_sbl_magic": 0, + "alt_code_region_sbl_major": 0, + "alt_code_region_sbl_minor": 0 + }, + "nvs_code_region_conf": { + "nvs_start_phy_address": 1777664, + "nvs_region_size": 1089536, + "nvs_region_primary_wsoc_start_phy_address": 847868, + "nvs_region_primary_wsoc_magic": 0, + "nvs_region_primary_wsoc_major": 0, + "nvs_region_primary_wsoc_minor": 0, + "nvs_region_sec_wsoc_start_phy_address": 1314812, + "nvs_region_sec_wsoc_magic": 0, + "nvs_region_sec_wsoc_major": 0, + "nvs_region_sec_wsoc_minor": 0, + "nvs_region_primary_wsoc_bl2_start_phy_address": 0, + "nvs_region_primary_wsoc_bl2_magic": 0, + "nvs_region_primary_wsoc_bl2_major": 0, + "nvs_region_primary_wsoc_bl2_minor": 0, + "nvs_region_sec_wsoc_bl2_start_phy_address": 0, + "nvs_region_sec_wsoc_bl2_magic": 0, + "nvs_region_sec_wsoc_bl2_major": 0, + "nvs_region_sec_wsoc_bl2_minor": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/py25q128la/flash_disc_param_otfde.json b/boards/ti/lp_em_cc35x1/config/flash/py25q128la/flash_disc_param_otfde.json new file mode 100644 index 000000000000..b7de9063e057 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/py25q128la/flash_disc_param_otfde.json @@ -0,0 +1,286 @@ +{ + "otfde_header": { + "name": "OTFDEWFF3", + "flash_only": true, + "ip_protection": false, + "regions_lock": false, + "regions_number": 4, + "flash_enabled": true + }, + "bl_conf": { + "host_boot_done_lock": true, + "host_peripherals_lock": true, + "icache_conf_lock": true, + "m33_mem_part_lock": true, + "memss_firewall_lock": true, + "dma_channel_owner_lock": true, + "otfde_region_lock": true, + "core_events_lock": true + }, + "otfde_general": { + "parameters": { + "mem_otfde_initial_delay": 10, + "otfde_global_watchdog_timer": 5 + }, + "events": { + "reset_evt_mask": false, + "reset_evt_suspend": false, + "sft_reset_evt_mask": false, + "sft_reset_evt_suspend": false, + "bypass_mode_evt_mask": false, + "bypass_mode_evt_suspend": false, + "debug_mode_evt_mask": false, + "debug_mode_evt_suspend": false, + "general_evt_mask": false, + "general_evt_suspend": false, + "xspi_data_path_evt_mask": false, + "xspi_data_path_evt_suspend": false, + "xspi_cnfg_path_evt_mask": false, + "xspi_cnfg_path_evt_suspend": false, + "xspi_service_interrupt_evt_mask": false, + "xspi_service_interrupt_evt_suspend": false, + "trans_device_disabled_evt_mask": false, + "trans_device_disabled_evt_suspend": false, + "trans_region_disabled_evt_mask": false, + "trans_region_disabled_evt_suspend": false, + "trans_region_params_conf_evt_mask": false, + "trans_region_params_conf_evt_suspend": false, + "trans_multiple_regions_mapped_evt_mask": false, + "trans_multiple_regions_mapped_evt_suspend": false, + "trans_address_not_32_bit_evt_mask": false, + "trans_address_not_32_bit_evt_suspend": false, + "trans_size_not_32_bit_evt_mask": false, + "trans_size_not_32_bit_evt_suspend": false, + "trans_burst_not_32_bit_evt_mask": false, + "trans_burst_not_32_bit_evt_suspend": false, + "region_read_write_def_evt_mask": false, + "region_read_write_def_evt_suspend": false, + "suspend_while_disabled_evt_mask": false, + "suspend_while_disabled_evt_suspend": false + } + }, + "regions_settings": { + "region_parameters_lock": { + "REGION_0_PARAMS_0": true, + "REGION_0_PARAMS_1": true, + "REGION_0_PARAMS_2": true, + "REGION_1_PARAMS_0": false, + "REGION_1_PARAMS_1": false, + "REGION_1_PARAMS_2": false, + "REGION_2_PARAMS_0": true, + "REGION_2_PARAMS_1": true, + "REGION_2_PARAMS_2": true, + "REGION_3_PARAMS_0": false, + "REGION_3_PARAMS_1": false, + "REGION_3_PARAMS_2": false + }, + "region_0_protection": { + "mem_region_0_enabled": true, + "mem_region_0_device_id": 0, + "mem_region_0_spi_write_enable": true, + "mem_region_0_spi_read_enable": true, + "mem_region_0_physical_offset": 700, + "mem_region_0_security_id_msb": 0, + "mem_region_0_start_address": 81920, + "mem_region_0_end_address": 83617, + "mem_region_0_security_id_lsb": 0, + "mem_otfde_region_0_write_lock_en": false, + "mem_otfde_region_0_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_1_protection": { + "mem_region_1_enabled": true, + "mem_region_1_device_id": 0, + "mem_region_1_spi_write_enable": true, + "mem_region_1_spi_read_enable": true, + "mem_region_1_physical_offset": 0, + "mem_region_1_security_id_msb": 0, + "mem_region_1_start_address": 655360, + "mem_region_1_end_address": 656059, + "mem_region_1_security_id_lsb": 0, + "mem_otfde_region_1_write_lock_en": false, + "mem_otfde_region_1_enc_dec_bypass": "Bypass" + }, + "region_2_protection": { + "mem_region_2_enabled": true, + "mem_region_2_device_id": 0, + "mem_region_2_spi_write_enable": true, + "mem_region_2_spi_read_enable": true, + "mem_region_2_physical_offset": 2398, + "mem_region_2_security_id_msb": 0, + "mem_region_2_start_address": 671744, + "mem_region_2_end_address": 673441, + "mem_region_2_security_id_lsb": 0, + "mem_otfde_region_2_write_lock_en": false, + "mem_otfde_region_2_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_3_protection": { + "mem_region_3_enabled": false, + "mem_region_3_device_id": 1, + "mem_region_3_spi_write_enable": true, + "mem_region_3_spi_read_enable": true, + "mem_region_3_physical_offset": 0, + "mem_region_3_security_id_msb": 0, + "mem_region_3_start_address": 1, + "mem_region_3_end_address": 0, + "mem_region_3_security_id_lsb": 0, + "mem_otfde_region_3_write_lock_en": false, + "mem_otfde_region_3_enc_dec_bypass": "Bypass" + } + }, + "devices": { + "header": { + "flash_device_switch_conf": 1, + "ram_device_switch_conf": 1 + }, + "flash_switch": { + "flash_grant_sel": 0, + "flash_data_for_conf_0": 2181562505, + "flash_offset_bits_for_conf_0": 0, + "flash_stop_bit_for_conf_0": 0, + "flash_data_for_conf_1": 167911947, + "flash_offset_bits_for_conf_1": 1, + "flash_stop_bit_for_conf_1": 0, + "flash_data_for_conf_2": 139266, + "flash_offset_bits_for_conf_2": 2, + "flash_stop_bit_for_conf_2": 0, + "flash_data_for_conf_3": 1, + "flash_offset_bits_for_conf_3": 4, + "flash_stop_bit_for_conf_3": 0, + "flash_data_for_conf_4": 1076887634, + "flash_offset_bits_for_conf_4": 45, + "flash_stop_bit_for_conf_4": 0, + "flash_data_for_conf_5": 3224371282, + "flash_offset_bits_for_conf_5": 45, + "flash_stop_bit_for_conf_5": 0, + "flash_data_for_conf_6": 262149, + "flash_offset_bits_for_conf_6": 14, + "flash_stop_bit_for_conf_6": 0, + "flash_data_for_conf_7": 0, + "flash_offset_bits_for_conf_7": 44, + "flash_stop_bit_for_conf_7": 1, + "flash_data_for_conf_8": 0, + "flash_offset_bits_for_conf_8": 0, + "flash_stop_bit_for_conf_8": 1, + "flash_data_for_conf_9": 0, + "flash_offset_bits_for_conf_9": 0, + "flash_stop_bit_for_conf_9": 1, + "flash_data_for_conf_10": 0, + "flash_offset_bits_for_conf_10": 0, + "flash_stop_bit_for_conf_10": 1, + "flash_data_for_conf_11": 0, + "flash_offset_bits_for_conf_11": 0, + "flash_stop_bit_for_conf_11": 1, + "flash_data_for_conf_12": 0, + "flash_offset_bits_for_conf_12": 0, + "flash_stop_bit_for_conf_12": 1, + "flash_data_for_conf_13": 0, + "flash_offset_bits_for_conf_13": 0, + "flash_stop_bit_for_conf_13": 1, + "flash_data_for_conf_14": 0, + "flash_offset_bits_for_conf_14": 0, + "flash_stop_bit_for_conf_14": 1, + "flash_data_for_conf_15": 0, + "flash_offset_bits_for_conf_15": 0, + "flash_stop_bit_for_conf_15": 1, + "flash_data_for_conf_16": 0, + "flash_offset_bits_for_conf_16": 0, + "flash_stop_bit_for_conf_16": 1, + "flash_data_for_conf_17": 0, + "flash_offset_bits_for_conf_17": 0, + "flash_stop_bit_for_conf_17": 1, + "flash_data_for_conf_18": 0, + "flash_offset_bits_for_conf_18": 0, + "flash_stop_bit_for_conf_18": 1, + "flash_data_for_conf_19": 0, + "flash_offset_bits_for_conf_19": 0, + "flash_stop_bit_for_conf_19": 1, + "flash_data_for_conf_20": 0, + "flash_offset_bits_for_conf_20": 0, + "flash_stop_bit_for_conf_20": 1, + "flash_data_for_conf_21": 0, + "flash_offset_bits_for_conf_21": 0, + "flash_stop_bit_for_conf_21": 1, + "flash_data_for_conf_22": 0, + "flash_offset_bits_for_conf_22": 0, + "flash_stop_bit_for_conf_22": 1, + "flash_data_for_conf_23": 0, + "flash_offset_bits_for_conf_23": 0, + "flash_stop_bit_for_conf_23": 1 + }, + "ram_switch": { + "ram_grant_sel": 0, + "ram_data_for_conf_0": 2181562505, + "ram_offset_bits_for_conf_0": 0, + "ram_stop_bit_for_conf_0": 0, + "ram_data_for_conf_1": 67248651, + "ram_offset_bits_for_conf_1": 1, + "ram_stop_bit_for_conf_1": 0, + "ram_data_for_conf_2": 139266, + "ram_offset_bits_for_conf_2": 2, + "ram_stop_bit_for_conf_2": 0, + "ram_data_for_conf_3": 1, + "ram_offset_bits_for_conf_3": 4, + "ram_stop_bit_for_conf_3": 0, + "ram_data_for_conf_4": 1076887634, + "ram_offset_bits_for_conf_4": 45, + "ram_stop_bit_for_conf_4": 0, + "ram_data_for_conf_5": 3224371282, + "ram_offset_bits_for_conf_5": 45, + "ram_stop_bit_for_conf_5": 0, + "ram_data_for_conf_6": 262149, + "ram_offset_bits_for_conf_6": 14, + "ram_stop_bit_for_conf_6": 0, + "ram_data_for_conf_7": 0, + "ram_offset_bits_for_conf_7": 44, + "ram_stop_bit_for_conf_7": 1, + "ram_data_for_conf_8": 0, + "ram_offset_bits_for_conf_8": 0, + "ram_stop_bit_for_conf_8": 1, + "ram_data_for_conf_9": 0, + "ram_offset_bits_for_conf_9": 0, + "ram_stop_bit_for_conf_9": 1, + "ram_data_for_conf_10": 0, + "ram_offset_bits_for_conf_10": 0, + "ram_stop_bit_for_conf_10": 1, + "ram_data_for_conf_11": 0, + "ram_offset_bits_for_conf_11": 0, + "ram_stop_bit_for_conf_11": 1, + "ram_data_for_conf_12": 0, + "ram_offset_bits_for_conf_12": 0, + "ram_stop_bit_for_conf_12": 1, + "ram_data_for_conf_13": 0, + "ram_offset_bits_for_conf_13": 0, + "ram_stop_bit_for_conf_13": 1, + "ram_data_for_conf_14": 0, + "ram_offset_bits_for_conf_14": 0, + "ram_stop_bit_for_conf_14": 1, + "ram_data_for_conf_15": 0, + "ram_offset_bits_for_conf_15": 0, + "ram_stop_bit_for_conf_15": 1, + "ram_data_for_conf_16": 0, + "ram_offset_bits_for_conf_16": 0, + "ram_stop_bit_for_conf_16": 1, + "ram_data_for_conf_17": 0, + "ram_offset_bits_for_conf_17": 0, + "ram_stop_bit_for_conf_17": 1, + "ram_data_for_conf_18": 0, + "ram_offset_bits_for_conf_18": 0, + "ram_stop_bit_for_conf_18": 1, + "ram_data_for_conf_19": 0, + "ram_offset_bits_for_conf_19": 0, + "ram_stop_bit_for_conf_19": 1, + "ram_data_for_conf_20": 0, + "ram_offset_bits_for_conf_20": 0, + "ram_stop_bit_for_conf_20": 1, + "ram_data_for_conf_21": 0, + "ram_offset_bits_for_conf_21": 0, + "ram_stop_bit_for_conf_21": 1, + "ram_data_for_conf_22": 0, + "ram_offset_bits_for_conf_22": 0, + "ram_stop_bit_for_conf_22": 1, + "ram_data_for_conf_23": 0, + "ram_offset_bits_for_conf_23": 0, + "ram_stop_bit_for_conf_23": 1 + } + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/py25q128la/flash_disc_param_xspi.json b/boards/ti/lp_em_cc35x1/config/flash/py25q128la/flash_disc_param_xspi.json new file mode 100644 index 000000000000..229e12c5f41d --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/py25q128la/flash_disc_param_xspi.json @@ -0,0 +1,485 @@ +{ + "xspi_header": { + "name": "xSPIWFF3", + "device": "CC3500", + "use_hardware": "PY25Q128LA", + "use_case": "Quadro", + "dqs_support": 0, + "flash_only": 1, + "flash_separate_reset": 0, + "ram_separate_reset": true, + "clock_frequency": 80, + "qospi_clock_divider": 1, + "flash_device_character_conf": 0, + "ram_device_character_conf": 0, + "header_advanced": 0, + "phy_mode_enable": 1, + "pipeline_mode_enable": 1, + "loopback_support": "No", + "qspi_ref_clock": 80, + "spi_clock_freq": 20, + "spi_clock_divider": 1, + "flash_device_size": 16, + "flash_bytes_per_block": 16, + "flash_bytes_per_page": 256, + "flash_number_of_address_bytes": 3, + "flash_dual_opcode": 0, + "flash_jedec_manufacturer_id": 0, + "flash_jedec_device_id": 0, + "flash_name": "PY25Q128LA", + "flash_page_size": 256, + "flash_sector_size": 4096, + "flash_cs_polarity": "ACTIVE_LOW", + "flash_sw_reset_type": "x1xxxx", + "ram_device_size": 8, + "ram_bytes_per_block": 16, + "ram_bytes_per_page": 256, + "ram_number_of_address_bytes": 3, + "ram_dual_opcode": 0, + "ram_jedec_manufacturer_id": 0, + "ram_jedec_device_id": 0, + "ram_name": "NO_PSRAM", + "ram_page_size": 256, + "ram_sector_size": 4096, + "ram_cs_polarity": "ACTIVE_LOW", + "ram_sw_reset_type": "x1xxxx", + "flash_write_operation_modes": "4S-4S-4S", + "flash_read_operation_modes": "4S-4S-4S", + "ram_write_operation_modes": "4S-4S-4S", + "ram_read_operation_modes": "4S-4S-4S", + "crc_enable": 0, + "enable_dtr": 0, + "enable_ahb_decoder": 0, + "enter_xip_mod_immediately": 0, + "enter_xip_mod_next_read": 0, + "ahb_address_remapping": 0, + "enable_dma": 0, + "select_decode": 0, + "legacy_ip_mode": 0, + "direct_access": 1 + }, + "xspi_pinmux": { + "xspi_clk_input": 44, + "xspi_clk_input_use_hw": 0, + "xspi_clk_input_mode": "Input", + "xspi_clk_input_pull": "None", + "xspi_clk_input_interrupt_trigger": "Low", + "xspi_clk_input_dont_conf": 0, + "xspi_clk_input_output_strength": "High", + "xspi_clk_input_initial_output_state": "High", + "xspi_clk": 24, + "xspi_clk_use_hw": "None", + "xspi_clk_mode": "Output", + "xspi_clk_pull": "None", + "xspi_clk_output_strength": "High", + "xspi_clk_initial_output_state": "High", + "xspi_clk_interrupt_trigger": "None", + "xspi_clk_dont_conf": 0, + "xspi_flash_cs": 20, + "xspi_flash_cs_use_hw": "None", + "xspi_flash_cs_mode": "Output", + "xspi_flash_cs_pull": "None", + "xspi_flash_cs_output_strength": "High", + "xspi_flash_cs_initial_output_state": "High", + "xspi_flash_cs_interrupt_trigger": "None", + "xspi_flash_cs_dont_conf": 0, + "xspi_data_0": 25, + "xspi_data_0_use_hw": "None", + "xspi_data_0_mode": "Input", + "xspi_data_0_pull": "None", + "xspi_data_0_output_strength": "High", + "xspi_data_0_initial_output_state": "High", + "xspi_data_0_interrupt_trigger": "Low", + "xspi_data_0_dont_conf": 0, + "xspi_data_1": 21, + "xspi_data_1_use_hw": "None", + "xspi_data_1_mode": "Input", + "xspi_data_1_pull": "None", + "xspi_data_1_output_strength": "High", + "xspi_data_1_initial_output_state": "High", + "xspi_data_1_interrupt_trigger": "Low", + "xspi_data_1_dont_conf": 0, + "xspi_data_2": 22, + "xspi_data_2_use_hw": "None", + "xspi_data_2_mode": "Input", + "xspi_data_2_pull": "None", + "xspi_data_2_output_strength": "High", + "xspi_data_2_initial_output_state": "High", + "xspi_data_2_interrupt_trigger": "Low", + "xspi_data_2_dont_conf": 0, + "xspi_data_3": 23, + "xspi_data_3_use_hw": "None", + "xspi_data_3_mode": "Input", + "xspi_data_3_pull": "None", + "xspi_data_3_output_strength": "High", + "xspi_data_3_initial_output_state": "High", + "xspi_data_3_interrupt_trigger": "Low", + "xspi_data_3_dont_conf": 0, + "xspi_data_4": 26, + "xspi_data_4_use_hw": "None", + "xspi_data_4_mode": "Input", + "xspi_data_4_pull": "None", + "xspi_data_4_output_strength": "High", + "xspi_data_4_initial_output_state": "High", + "xspi_data_4_interrupt_trigger": "None", + "xspi_data_4_dont_conf": 0, + "xspi_data_5": 27, + "xspi_data_5_use_hw": "None", + "xspi_data_5_mode": "Input", + "xspi_data_5_pull": "None", + "xspi_data_5_output_strength": "High", + "xspi_data_5_initial_output_state": "High", + "xspi_data_5_interrupt_trigger": "None", + "xspi_data_5_dont_conf": 0, + "xspi_data_6": 28, + "xspi_data_6_use_hw": "None", + "xspi_data_6_mode": "Input", + "xspi_data_6_pull": "None", + "xspi_data_6_output_strength": "High", + "xspi_data_6_initial_output_state": "High", + "xspi_data_6_interrupt_trigger": "None", + "xspi_data_6_dont_conf": 0, + "xspi_data_7": 29, + "xspi_data_7_use_hw": "None", + "xspi_data_7_mode": "Input", + "xspi_data_7_pull": "None", + "xspi_data_7_output_strength": "High", + "xspi_data_7_initial_output_state": "High", + "xspi_data_7_interrupt_trigger": "None", + "xspi_data_7_dont_conf": 0, + "xspi_reset_flash": 36, + "xspi_reset_flash_use_hw": "None", + "xspi_reset_flash_mode": "Output", + "xspi_reset_flash_pull": "None", + "xspi_reset_flash_output_strength": "High", + "xspi_reset_flash_initial_output_state": "High", + "xspi_reset_flash_interrupt_trigger": "None", + "xspi_reset_flash_dont_conf": 0, + "xspi_cs_ram": 3, + "xspi_cs_ram_use_hw": "None", + "xspi_cs_ram_mode": "Output", + "xspi_cs_ram_pull": "None", + "xspi_cs_ram_output_strength": "High", + "xspi_cs_ram_initial_output_state": "High", + "xspi_cs_ram_interrupt_trigger": "None", + "xspi_cs_ram_dont_conf": 0, + "xspi_dqs": 30, + "xspi_dqs_use_hw": "None", + "xspi_dqs_mode": "Input", + "xspi_dqs_pull": "None", + "xspi_dqs_output_strength": "High", + "xspi_dqs_initial_output_state": "High", + "xspi_dqs_interrupt_trigger": "None", + "xspi_dqs_dont_conf": 0, + "xspi_reset_ram": 2, + "xspi_reset_ram_use_hw": "None", + "xspi_reset_ram_mode": "Input", + "xspi_reset_ram_pull": "None", + "xspi_reset_ram_output_strength": "High", + "xspi_reset_ram_initial_output_state": "High", + "xspi_reset_ram_interrupt_trigger": "None", + "xspi_reset_ram_dont_conf": 0 + }, + "xspi_operations": { + "xspi_operations_clocks": { + "clock_phase": 0, + "clock_polarity": 0, + "spi_mode": "2'b00" + }, + "xspi_operations_chip_select": { + "csda": 2, + "csdads": 0, + "cseot": 4, + "cssot": 1 + }, + "xspi_operations_reset": { + "flash_jedec_reset": 0, + "ram_jedec_reset": 0, + "flash_treset": 20, + "ram_treset": 20 + }, + "xspi_phy_operations": { + "flash_rx_dll_bypass_bit": 0, + "flash_dll_tx_delay": 22, + "flash_dll_rx_delay": 34, + "ram_rx_dll_bypass_bit": 0, + "ram_dll_tx_delay": 22, + "ram_dll_rx_delay": 34 + }, + "xspi_read_operations": { + "flash_dummy_rd_cycles": 10, + "flash_read_opcode": 11, + "suppl_flash_read_opcode": 0, + "ram_dummy_rd_cycles": 10, + "ram_read_opcode": 11, + "suppl_ram_read_opcode": 0, + "flash_non_cont_read_enable": 0, + "flash_max_read_jobs": 256, + "ram_non_cont_read_enable": 0, + "ram_max_read_jobs": 256, + "rww_en": 0, + "device_size": 8, + "number_of_banks": 1, + "bank_size": 8, + "mode_bit_enable": 0 + }, + "xspi_write_operations": { + "flash_address_and_data": { + "flash_dummy_wr_cycles": 0 + }, + "flash_command": { + "flash_write_opcode": 2, + "suppl_flash_write_opcode": 0 + }, + "ram_address_and_data": { + "ram_dummy_wr_cycles": 0 + }, + "ram_command": { + "ram_write_opcode": 2, + "suppl_ram_write_opcode": 0 + }, + "write_to_buffer": { + "flash_write_to_buffer_support": 0, + "ram_write_to_buffer_support": 0 + }, + "non_continuous_write": { + "flash_non_cont_write_enable": 0, + "flash_max_write_jobs": 64, + "ram_non_cont_write_enable": 0, + "ram_max_write_jobs": 0 + }, + "flash_program_operation": { + "flash_min_program_size": "256 B", + "flash_program_opcode": 2, + "suppl_flash_program_opcode": 0, + "flash_maximum_program_time_limit": 1600 + }, + "flash_erase_operation": { + "flash_min_erase_size": "4 kB", + "flash_erase_opcode": 32, + "suppl_flash_erase_opcode": 0, + "flash_maximum_erase_time_limit": 4095 + }, + "flash_erase_conf": { + "flash_block_erase_opcode": 0, + "suppl_block_flash_erase_opcode": 0, + "flash_sector_erase_opcode": 0, + "suppl_sector_flash_erase_opcode": 0, + "flash_chip_erase_opcode": 0, + "suppl_chip_flash_erase_opcode": 0 + }, + "ram_program_operation": { + "ram_min_program_size": "256 B", + "ram_program_opcode": 2, + "suppl_ram_program_opcode": 0, + "ram_maximum_program_time_limit": 1600 + }, + "ram_erase_conf": { + "ram_block_erase_opcode": 0, + "suppl_block_ram_erase_opcode": 0, + "ram_sector_erase_opcode": 0, + "suppl_sector_ram_erase_opcode": 0, + "ram_chip_erase_opcode": 0, + "suppl_chip_ram_erase_opcode": 0 + }, + "flash_buffer_support": { + "flash_pre_write_sequence": 0, + "flash_post_write_sequence": 0, + "flash_write_protection_timer_en": 0, + "flash_write_buffer_timer_mode": 16, + "flash_write_buffer_timer_range": 0, + "flash_service_interrupt_criteria": 0 + }, + "ram_buffer_support": { + "ram_pre_write_sequence": 0, + "ram_post_write_sequence": 0, + "ram_write_protection_timer_en": 0, + "ram_write_buffer_timer_mode": 16, + "ram_write_buffer_timer_range": 0, + "ram_service_interrupt_criteria": 0 + }, + "flash_pre_write_conf": { + "flash_pre_write_job_done_grant_sel": 0, + "data_for_flash_pre_write_conf_0": 0, + "offset_bits_for_flash_pre_write_conf_0": 0, + "stop_bit_for_flash_pre_write_conf_0": 1, + "data_for_flash_pre_write_conf_1": 0, + "offset_bits_for_flash_pre_write_conf_1": 0 + }, + "flash_post_write_conf": { + "flash_post_write_job_done_grant_sel": 0, + "data_for_flash_post_write_conf_0": 0, + "offset_bits_for_flash_post_write_conf_0": 0, + "stop_bit_for_flash_post_write_conf_0": 1, + "data_for_flash_post_write_conf_1": 0, + "offset_bits_for_flash_post_write_conf_1": 0 + }, + "ram_pre_write_conf": { + "ram_pre_write_job_done_grant_sel": 0, + "data_for_ram_pre_write_conf_0": 0, + "offset_bits_for_ram_pre_write_conf_0": 0, + "stop_bit_for_ram_pre_write_conf_0": 1, + "data_for_ram_pre_write_conf_1": 0, + "offset_bits_for_ram_pre_write_conf_1": 0 + }, + "ram_post_write_conf": { + "ram_post_write_job_done_grant_sel": 0, + "data_for_ram_post_write_conf_0": 0, + "offset_bits_for_ram_post_write_conf_0": 0, + "stop_bit_for_ram_post_write_conf_0": 1, + "data_for_ram_post_write_conf_1": 0, + "offset_bits_for_ram_post_write_conf_1": 0 + } + }, + "xspi_capture_operations": { + "read_data_capture": { + "flash_delay_transmitted_data": 0, + "flash_loopback_clock": 0, + "flash_bypass_adapted_loopback": 1, + "flash_sample_edge_sel": 0, + "ram_delay_transmitted_data": 0, + "ram_loopback_clock": 0, + "ram_bypass_adapted_loopback": 1, + "ram_sample_edge_sel": 0 + }, + "delays": { + "flash_full_half_cycle_delay": 0, + "flash_dll_bypass_mode": 1, + "flash_phase_detect_sel": 0, + "flash_dll_lock_num": 0, + "flash_dll_start_point": 0, + "flash_loopback_clock": 0, + "ram_full_half_cycle_delay": 0, + "ram_dll_bypass_mode": 1, + "ram_phase_detect_sel": 0, + "ram_dll_lock_num": 0, + "ram_dll_start_point": 0, + "ram_loopback_clock": 0 + }, + "operation_modes": { + "flash_sfdp_support": 0, + "ram_sfdp_support": 0, + "flash_pm_support": 0, + "ram_pm_support": 0, + "flash_sfdp_opcode": 0, + "suppl_flash_sfdp_opcode": 0, + "ram_sfdp_opcode": 0, + "suppl_ram_sfdp_opcode": 0, + "flash_enter_dpd_opcode": 185, + "suppl_flash_enter_dpd_opcode": 0, + "flash_exit_dpd_opcode": 171, + "suppl_flash_exit_dpd_opcode": 0, + "ram_enter_dpd_opcode": 185, + "suppl_ram_enter_dpd_opcode": 0, + "ram_exit_dpd_opcode": 171, + "suppl_ram_exit_dpd_opcode": 0, + "flash_quad_enable_opcode": 56, + "suppl_flash_quad_enable_opcode": 0, + "flash_quad_disable_opcode": 255, + "suppl_flash_quad_disable_opcode": 0, + "flash_octal_enable_opcode": 0, + "suppl_flash_octal_enable_opcode": 0, + "flash_octal_disable_opcode": 0, + "suppl_flash_octal_disable_opcode": 0, + "ram_quad_enable_opcode": 56, + "suppl_ram_quad_enable_opcode": 0, + "ram_quad_disable_opcode": 255, + "suppl_ram_quad_disable_opcode": 0, + "ram_octal_enable_opcode": 0, + "suppl_ram_octal_enable_opcode": 0, + "ram_octal_disable_opcode": 0, + "suppl_ram_octal_disable_opcode": 0 + } + } + }, + "external_memory_reporting": { + "header": { + "flash_auto_polling_enable": 1, + "flash_wel_enable": 1, + "flash_write_protect_enable": 0, + "flash_alternate_polling_conf_enable": 0, + "ram_auto_polling_enable": 1, + "ram_wel_enable": 1, + "ram_write_protect_enable": 0, + "ram_alternate_polling_conf_enable": 0 + }, + "flash_auto_polling": { + "flash_polling_repetition_delay": 0, + "flash_polling_count": 4, + "flash_enable_polling_expiration": 0, + "flash_polling_polarity": 0, + "flash_polling_address_phase_enable": 0, + "flash_polling_bit_index": 0, + "flash_numbers_poll_cycles": 65535, + "flash_dummy_autopoll_cycles": 0 + }, + "ram_auto_polling": { + "ram_polling_repetition_delay": 0, + "ram_polling_count": 4, + "ram_enable_polling_expiration": 0, + "ram_polling_polarity": 0, + "ram_polling_address_phase_enable": 0, + "ram_polling_bit_index": 0, + "ram_numbers_poll_cycles": 65535, + "ram_dummy_autopoll_cycles": 0 + }, + "flash_polling_command": { + "flash_polling_opcode": 5, + "suppl_flash_polling_opcode": 0 + }, + "ram_polling_command": { + "ram_polling_opcode": 5, + "suppl_ram_polling_opcode": 0 + }, + "flash_alternate_polling": { + "flash_polling_resp_count": 1023, + "flash_polling_iterations": 1, + "flash_polling_enabled": 0, + "flash_polling_disabled": 0, + "flash_grant_sel": 0, + "flash_data_for_enable_poling_conf_0": 0, + "flash_offset_bits_for_enable_poling_conf_0": 0, + "flash_stop_bit_for_enable_poling_conf_0": 1, + "flash_data_for_enable_poling_conf_1": 0, + "flash_offset_bits_for_enable_poling_conf_1": 0, + "flash_stop_bit_for_enable_poling_conf_1": 1, + "flash_data_for_disable_poling_conf_0": 0, + "flash_offset_bits_for_disable_poling_conf_0": 0, + "flash_stop_bit_for_disable_poling_conf_0": 1, + "flash_data_for_disable_poling_conf_1": 0, + "flash_offset_bits_for_disable_poling_conf_1": 0, + "flash_stop_bit_for_disable_poling_conf_1": 1 + }, + "ram_alternate_polling": { + "ram_polling_resp_count": 1023, + "ram_polling_iterations": 1, + "ram_polling_enabled": 0, + "ram_polling_disabled": 0, + "ram_grant_sel": 0, + "ram_data_for_enable_poling_conf_0": 0, + "ram_offset_bits_for_enable_poling_conf_0": 0, + "ram_stop_bit_for_enable_poling_conf_0": 1, + "ram_data_for_enable_poling_conf_1": 0, + "ram_offset_bits_for_enable_poling_conf_1": 0, + "ram_stop_bit_for_enable_poling_conf_1": 1, + "ram_data_for_disable_poling_conf_0": 0, + "ram_offset_bits_for_disable_poling_conf_0": 0, + "ram_stop_bit_for_disable_poling_conf_0": 1, + "ram_data_for_disable_poling_conf_1": 0, + "ram_offset_bits_for_disable_poling_conf_1": 0, + "ram_stop_bit_for_disable_poling_conf_1": 1 + }, + "flash_wel_command": { + "flash_wel_opcode": 6, + "suppl_flash_wel_opcode": 0 + }, + "ram_wel_command": { + "ram_wel_opcode": 6, + "suppl_ram_wel_opcode": 0 + } + }, + "event": { + "host_nvic_irq": 0, + "core_10_mux_sel": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/py25q256lc/flash_disc_param_ext_mem.json b/boards/ti/lp_em_cc35x1/config/flash/py25q256lc/flash_disc_param_ext_mem.json new file mode 100644 index 000000000000..22b8d198bffd --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/py25q256lc/flash_disc_param_ext_mem.json @@ -0,0 +1,99 @@ +{ + "vendor_primary_sbl": true, + "ti_wsoc_primary_container": true, + "ti_wsoc_bl2_primary_container": true, + "nvs_enable": true, + "vendor_alternate_image": true, + "vendor_sbl_alternate_image": true, + "ti_bl_alternate_image": true, + "ti_wsoc_alternate_image": true, + "ti_wsoc_bl2_alternate_image": true, + "region_0": { + "mem_region_0_start_phy_address": 16760832, + "mem_region_0_end_phy_address": 25157631, + "region0_boot": false, + "region0_main_code": true, + "region0_nvs": false, + "region0_wsoc_code": false, + "region0_alternate_code": false + }, + "region_1": { + "mem_region_1_start_phy_address": 0, + "mem_region_1_end_phy_address": 16760831, + "region1_boot": true, + "region1_main_code": false, + "region1_nvs": true, + "region1_wsoc_code": true, + "region1_alternate_code": false + }, + "region_2": { + "mem_region_2_start_phy_address": 25157632, + "mem_region_2_end_phy_address": 33554431, + "region2_boot": false, + "region2_main_code": false, + "region2_nvs": false, + "region2_wsoc_code": false, + "region2_alternate_code": true + }, + "region_3": { + "mem_region_3_start_phy_address": 0, + "mem_region_3_end_phy_address": 0, + "region3_boot": false, + "region3_main_code": false, + "region3_nvs": false, + "region3_wsoc_code": false, + "region3_alternate_code": false + }, + "boot_region_conf": { + "boot_region_size": 0, + "boot_region_flash_disco_param_start_address": 0, + "boot_region_primary_ti_bl_start_phy_address": 12284, + "boot_region_primary_ti_bl_magic": 0, + "boot_region_primary_ti_bl_major": 0, + "boot_region_primary_ti_bl_minor": 0, + "boot_region_sec_ti_bl_start_phy_address": 430076, + "boot_region_sec_ti_bl_magic": 0, + "boot_region_sec_ti_bl_major": 0, + "boot_region_sec_ti_bl_minor": 0 + }, + "main_code_region_conf": { + "main_code_region_vendor_image_start_phy_address": 16764924, + "main_code_region_vendor_image_magic": 0, + "main_code_region_vendor_image_major": 0, + "main_code_region_vendor_image_minor": 0, + "main_code_region_sbl_start_phy_address": 0, + "main_code_region_sbl_magic": 0, + "main_code_region_sbl_major": 0, + "main_code_region_sbl_minor": 0 + }, + "alt_code_region_conf": { + "alt_code_region_vendor_image_start_phy_address": 25161724, + "alt_code_region_vendor_image_magic": 0, + "alt_code_region_vendor_image_major": 0, + "alt_code_region_vendor_image_minor": 0, + "alt_code_region_sbl_start_phy_address": 0, + "alt_code_region_sbl_magic": 0, + "alt_code_region_sbl_major": 0, + "alt_code_region_sbl_minor": 0 + }, + "nvs_code_region_conf": { + "nvs_start_phy_address": 1777664, + "nvs_region_size": 14983168, + "nvs_region_primary_wsoc_start_phy_address": 847868, + "nvs_region_primary_wsoc_magic": 0, + "nvs_region_primary_wsoc_major": 0, + "nvs_region_primary_wsoc_minor": 0, + "nvs_region_sec_wsoc_start_phy_address": 1314812, + "nvs_region_sec_wsoc_magic": 0, + "nvs_region_sec_wsoc_major": 0, + "nvs_region_sec_wsoc_minor": 0, + "nvs_region_primary_wsoc_bl2_start_phy_address": 0, + "nvs_region_primary_wsoc_bl2_magic": 0, + "nvs_region_primary_wsoc_bl2_major": 0, + "nvs_region_primary_wsoc_bl2_minor": 0, + "nvs_region_sec_wsoc_bl2_start_phy_address": 0, + "nvs_region_sec_wsoc_bl2_magic": 0, + "nvs_region_sec_wsoc_bl2_major": 0, + "nvs_region_sec_wsoc_bl2_minor": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/py25q256lc/flash_disc_param_otfde.json b/boards/ti/lp_em_cc35x1/config/flash/py25q256lc/flash_disc_param_otfde.json new file mode 100644 index 000000000000..6a1724457bbe --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/py25q256lc/flash_disc_param_otfde.json @@ -0,0 +1,286 @@ +{ + "otfde_header": { + "name": "OTFDEWFF3", + "flash_only": true, + "ip_protection": false, + "regions_lock": false, + "regions_number": 4, + "flash_enabled": true + }, + "bl_conf": { + "host_boot_done_lock": true, + "host_peripherals_lock": true, + "icache_conf_lock": true, + "m33_mem_part_lock": true, + "memss_firewall_lock": true, + "dma_channel_owner_lock": true, + "otfde_region_lock": true, + "core_events_lock": true + }, + "otfde_general": { + "parameters": { + "mem_otfde_initial_delay": 10, + "otfde_global_watchdog_timer": 5 + }, + "events": { + "reset_evt_mask": false, + "reset_evt_suspend": false, + "sft_reset_evt_mask": false, + "sft_reset_evt_suspend": false, + "bypass_mode_evt_mask": false, + "bypass_mode_evt_suspend": false, + "debug_mode_evt_mask": false, + "debug_mode_evt_suspend": false, + "general_evt_mask": false, + "general_evt_suspend": false, + "xspi_data_path_evt_mask": false, + "xspi_data_path_evt_suspend": false, + "xspi_cnfg_path_evt_mask": false, + "xspi_cnfg_path_evt_suspend": false, + "xspi_service_interrupt_evt_mask": false, + "xspi_service_interrupt_evt_suspend": false, + "trans_device_disabled_evt_mask": false, + "trans_device_disabled_evt_suspend": false, + "trans_region_disabled_evt_mask": false, + "trans_region_disabled_evt_suspend": false, + "trans_region_params_conf_evt_mask": false, + "trans_region_params_conf_evt_suspend": false, + "trans_multiple_regions_mapped_evt_mask": false, + "trans_multiple_regions_mapped_evt_suspend": false, + "trans_address_not_32_bit_evt_mask": false, + "trans_address_not_32_bit_evt_suspend": false, + "trans_size_not_32_bit_evt_mask": false, + "trans_size_not_32_bit_evt_suspend": false, + "trans_burst_not_32_bit_evt_mask": false, + "trans_burst_not_32_bit_evt_suspend": false, + "region_read_write_def_evt_mask": false, + "region_read_write_def_evt_suspend": false, + "suspend_while_disabled_evt_mask": false, + "suspend_while_disabled_evt_suspend": false + } + }, + "regions_settings": { + "region_parameters_lock": { + "REGION_0_PARAMS_0": true, + "REGION_0_PARAMS_1": true, + "REGION_0_PARAMS_2": true, + "REGION_1_PARAMS_0": false, + "REGION_1_PARAMS_1": false, + "REGION_1_PARAMS_2": false, + "REGION_2_PARAMS_0": true, + "REGION_2_PARAMS_1": true, + "REGION_2_PARAMS_2": true, + "REGION_3_PARAMS_0": false, + "REGION_3_PARAMS_1": false, + "REGION_3_PARAMS_2": false + }, + "region_0_protection": { + "mem_region_0_enabled": true, + "mem_region_0_device_id": 0, + "mem_region_0_spi_write_enable": true, + "mem_region_0_spi_read_enable": true, + "mem_region_0_physical_offset": 4092, + "mem_region_0_security_id_msb": 0, + "mem_region_0_start_address": 81920, + "mem_region_0_end_address": 83969, + "mem_region_0_security_id_lsb": 0, + "mem_otfde_region_0_write_lock_en": false, + "mem_otfde_region_0_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_1_protection": { + "mem_region_1_enabled": true, + "mem_region_1_device_id": 0, + "mem_region_1_spi_write_enable": true, + "mem_region_1_spi_read_enable": true, + "mem_region_1_physical_offset": 0, + "mem_region_1_security_id_msb": 0, + "mem_region_1_start_address": 655360, + "mem_region_1_end_address": 659451, + "mem_region_1_security_id_lsb": 0, + "mem_otfde_region_1_write_lock_en": false, + "mem_otfde_region_1_enc_dec_bypass": "Bypass" + }, + "region_2_protection": { + "mem_region_2_enabled": true, + "mem_region_2_device_id": 0, + "mem_region_2_spi_write_enable": true, + "mem_region_2_spi_read_enable": true, + "mem_region_2_physical_offset": 6142, + "mem_region_2_security_id_msb": 0, + "mem_region_2_start_address": 671744, + "mem_region_2_end_address": 673793, + "mem_region_2_security_id_lsb": 0, + "mem_otfde_region_2_write_lock_en": false, + "mem_otfde_region_2_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_3_protection": { + "mem_region_3_enabled": false, + "mem_region_3_device_id": 1, + "mem_region_3_spi_write_enable": true, + "mem_region_3_spi_read_enable": true, + "mem_region_3_physical_offset": 0, + "mem_region_3_security_id_msb": 0, + "mem_region_3_start_address": 1, + "mem_region_3_end_address": 0, + "mem_region_3_security_id_lsb": 0, + "mem_otfde_region_3_write_lock_en": false, + "mem_otfde_region_3_enc_dec_bypass": "Bypass" + } + }, + "devices": { + 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"ram_stop_bit_for_conf_22": 1, + "ram_data_for_conf_23": 0, + "ram_offset_bits_for_conf_23": 0, + "ram_stop_bit_for_conf_23": 1 + } + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/py25q256lc/flash_disc_param_xspi.json b/boards/ti/lp_em_cc35x1/config/flash/py25q256lc/flash_disc_param_xspi.json new file mode 100644 index 000000000000..c95741a7111d --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/py25q256lc/flash_disc_param_xspi.json @@ -0,0 +1,485 @@ +{ + "xspi_header": { + "name": "xSPIWFF3", + "device": "CC3500", + "use_hardware": "PY25Q256LC", + "use_case": "Quadro", + "dqs_support": 0, + "flash_only": 1, + "flash_separate_reset": 0, + "ram_separate_reset": true, + "clock_frequency": 80, + "qospi_clock_divider": 1, + "flash_device_character_conf": 0, + "ram_device_character_conf": 0, + "header_advanced": 0, + "phy_mode_enable": 1, + "pipeline_mode_enable": 1, + "loopback_support": "No", + "qspi_ref_clock": 80, + "spi_clock_freq": 20, + "spi_clock_divider": 1, + "flash_device_size": 32, + "flash_bytes_per_block": 16, + "flash_bytes_per_page": 256, + "flash_number_of_address_bytes": 4, + "flash_dual_opcode": 0, + "flash_jedec_manufacturer_id": 0, + "flash_jedec_device_id": 0, + "flash_name": "PY25Q256LC", + "flash_page_size": 256, + "flash_sector_size": 4096, + "flash_cs_polarity": "ACTIVE_LOW", + "flash_sw_reset_type": "x1xxxx", + "ram_device_size": 8, + "ram_bytes_per_block": 16, + "ram_bytes_per_page": 256, + "ram_number_of_address_bytes": 3, + "ram_dual_opcode": 0, + "ram_jedec_manufacturer_id": 0, + "ram_jedec_device_id": 0, + "ram_name": "NO_PSRAM", + "ram_page_size": 256, + "ram_sector_size": 4096, + "ram_cs_polarity": "ACTIVE_LOW", + "ram_sw_reset_type": "x1xxxx", + "flash_write_operation_modes": "4S-4S-4S", + "flash_read_operation_modes": "4S-4S-4S", + "ram_write_operation_modes": "4S-4S-4S", + "ram_read_operation_modes": "4S-4S-4S", + "crc_enable": 0, + "enable_dtr": 0, + "enable_ahb_decoder": 0, + "enter_xip_mod_immediately": 0, + "enter_xip_mod_next_read": 0, + "ahb_address_remapping": 0, + "enable_dma": 0, + "select_decode": 0, + "legacy_ip_mode": 0, + "direct_access": 1 + }, + "xspi_pinmux": { + "xspi_clk_input": 44, + "xspi_clk_input_use_hw": 0, + "xspi_clk_input_mode": "Input", + "xspi_clk_input_pull": "None", + "xspi_clk_input_interrupt_trigger": "Low", + "xspi_clk_input_dont_conf": 0, + "xspi_clk_input_output_strength": "High", + "xspi_clk_input_initial_output_state": "High", + "xspi_clk": 24, + "xspi_clk_use_hw": "None", + "xspi_clk_mode": "Output", + "xspi_clk_pull": "None", + "xspi_clk_output_strength": "High", + "xspi_clk_initial_output_state": "High", + "xspi_clk_interrupt_trigger": "None", + "xspi_clk_dont_conf": 0, + "xspi_flash_cs": 20, + "xspi_flash_cs_use_hw": "None", + "xspi_flash_cs_mode": "Output", + "xspi_flash_cs_pull": "None", + "xspi_flash_cs_output_strength": "High", + "xspi_flash_cs_initial_output_state": "High", + "xspi_flash_cs_interrupt_trigger": "None", + "xspi_flash_cs_dont_conf": 0, + "xspi_data_0": 25, + "xspi_data_0_use_hw": "None", + "xspi_data_0_mode": "Input", + "xspi_data_0_pull": "None", + "xspi_data_0_output_strength": "High", + "xspi_data_0_initial_output_state": "High", + "xspi_data_0_interrupt_trigger": "Low", + "xspi_data_0_dont_conf": 0, + "xspi_data_1": 21, + "xspi_data_1_use_hw": "None", + "xspi_data_1_mode": "Input", + "xspi_data_1_pull": "None", + "xspi_data_1_output_strength": "High", + "xspi_data_1_initial_output_state": "High", + "xspi_data_1_interrupt_trigger": "Low", + "xspi_data_1_dont_conf": 0, + "xspi_data_2": 22, + "xspi_data_2_use_hw": "None", + "xspi_data_2_mode": "Input", + "xspi_data_2_pull": "None", + "xspi_data_2_output_strength": "High", + "xspi_data_2_initial_output_state": "High", + "xspi_data_2_interrupt_trigger": "Low", + "xspi_data_2_dont_conf": 0, + "xspi_data_3": 23, + "xspi_data_3_use_hw": "None", + "xspi_data_3_mode": "Input", + "xspi_data_3_pull": "None", + "xspi_data_3_output_strength": "High", + "xspi_data_3_initial_output_state": "High", + "xspi_data_3_interrupt_trigger": "Low", + "xspi_data_3_dont_conf": 0, + "xspi_data_4": 26, + "xspi_data_4_use_hw": "None", + "xspi_data_4_mode": "Input", + "xspi_data_4_pull": "None", + "xspi_data_4_output_strength": "High", + "xspi_data_4_initial_output_state": "High", + "xspi_data_4_interrupt_trigger": "None", + "xspi_data_4_dont_conf": 0, + "xspi_data_5": 27, + "xspi_data_5_use_hw": "None", + "xspi_data_5_mode": "Input", + "xspi_data_5_pull": "None", + "xspi_data_5_output_strength": "High", + "xspi_data_5_initial_output_state": "High", + "xspi_data_5_interrupt_trigger": "None", + "xspi_data_5_dont_conf": 0, + "xspi_data_6": 28, + "xspi_data_6_use_hw": "None", + "xspi_data_6_mode": "Input", + "xspi_data_6_pull": "None", + "xspi_data_6_output_strength": "High", + "xspi_data_6_initial_output_state": "High", + "xspi_data_6_interrupt_trigger": "None", + "xspi_data_6_dont_conf": 0, + "xspi_data_7": 29, + "xspi_data_7_use_hw": "None", + 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"flash_octal_enable_opcode": 0, + "suppl_flash_octal_enable_opcode": 0, + "flash_octal_disable_opcode": 0, + "suppl_flash_octal_disable_opcode": 0, + "ram_quad_enable_opcode": 56, + "suppl_ram_quad_enable_opcode": 0, + "ram_quad_disable_opcode": 255, + "suppl_ram_quad_disable_opcode": 0, + "ram_octal_enable_opcode": 0, + "suppl_ram_octal_enable_opcode": 0, + "ram_octal_disable_opcode": 0, + "suppl_ram_octal_disable_opcode": 0 + } + } + }, + "external_memory_reporting": { + "header": { + "flash_auto_polling_enable": 1, + "flash_wel_enable": 1, + "flash_write_protect_enable": 0, + "flash_alternate_polling_conf_enable": 0, + "ram_auto_polling_enable": 1, + "ram_wel_enable": 1, + "ram_write_protect_enable": 0, + "ram_alternate_polling_conf_enable": 0 + }, + "flash_auto_polling": { + "flash_polling_repetition_delay": 0, + "flash_polling_count": 4, + "flash_enable_polling_expiration": 0, + "flash_polling_polarity": 0, + "flash_polling_address_phase_enable": 0, + "flash_polling_bit_index": 0, + "flash_numbers_poll_cycles": 65535, + "flash_dummy_autopoll_cycles": 0 + }, + "ram_auto_polling": { + "ram_polling_repetition_delay": 0, + "ram_polling_count": 4, + "ram_enable_polling_expiration": 0, + "ram_polling_polarity": 0, + "ram_polling_address_phase_enable": 0, + "ram_polling_bit_index": 0, + "ram_numbers_poll_cycles": 65535, + "ram_dummy_autopoll_cycles": 0 + }, + "flash_polling_command": { + "flash_polling_opcode": 5, + "suppl_flash_polling_opcode": 0 + }, + "ram_polling_command": { + "ram_polling_opcode": 5, + "suppl_ram_polling_opcode": 0 + }, + "flash_alternate_polling": { + "flash_polling_resp_count": 1023, + "flash_polling_iterations": 1, + "flash_polling_enabled": 0, + "flash_polling_disabled": 0, + "flash_grant_sel": 0, + "flash_data_for_enable_poling_conf_0": 0, + "flash_offset_bits_for_enable_poling_conf_0": 0, + "flash_stop_bit_for_enable_poling_conf_0": 1, + "flash_data_for_enable_poling_conf_1": 0, + "flash_offset_bits_for_enable_poling_conf_1": 0, + "flash_stop_bit_for_enable_poling_conf_1": 1, + "flash_data_for_disable_poling_conf_0": 0, + "flash_offset_bits_for_disable_poling_conf_0": 0, + "flash_stop_bit_for_disable_poling_conf_0": 1, + "flash_data_for_disable_poling_conf_1": 0, + "flash_offset_bits_for_disable_poling_conf_1": 0, + "flash_stop_bit_for_disable_poling_conf_1": 1 + }, + "ram_alternate_polling": { + "ram_polling_resp_count": 1023, + "ram_polling_iterations": 1, + "ram_polling_enabled": 0, + "ram_polling_disabled": 0, + "ram_grant_sel": 0, + "ram_data_for_enable_poling_conf_0": 0, + "ram_offset_bits_for_enable_poling_conf_0": 0, + "ram_stop_bit_for_enable_poling_conf_0": 1, + "ram_data_for_enable_poling_conf_1": 0, + "ram_offset_bits_for_enable_poling_conf_1": 0, + "ram_stop_bit_for_enable_poling_conf_1": 1, + "ram_data_for_disable_poling_conf_0": 0, + "ram_offset_bits_for_disable_poling_conf_0": 0, + "ram_stop_bit_for_disable_poling_conf_0": 1, + "ram_data_for_disable_poling_conf_1": 0, + "ram_offset_bits_for_disable_poling_conf_1": 0, + "ram_stop_bit_for_disable_poling_conf_1": 1 + }, + "flash_wel_command": { + "flash_wel_opcode": 6, + "suppl_flash_wel_opcode": 0 + }, + "ram_wel_command": { + "ram_wel_opcode": 6, + "suppl_ram_wel_opcode": 0 + } + }, + "event": { + "host_nvic_irq": 0, + "core_10_mux_sel": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/py25q32lb/flash_disc_param_ext_mem.json b/boards/ti/lp_em_cc35x1/config/flash/py25q32lb/flash_disc_param_ext_mem.json new file mode 100644 index 000000000000..321810768be1 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/py25q32lb/flash_disc_param_ext_mem.json @@ -0,0 +1,99 @@ +{ + "vendor_primary_sbl": true, + "ti_wsoc_primary_container": true, + "ti_wsoc_bl2_primary_container": true, + "nvs_enable": true, + "vendor_alternate_image": true, + "vendor_sbl_alternate_image": true, + "ti_bl_alternate_image": true, + "ti_wsoc_alternate_image": true, + "ti_wsoc_bl2_alternate_image": true, + "region_0": { + "mem_region_0_start_phy_address": 1069056, + "mem_region_0_end_phy_address": 4194303, + "region0_boot": false, + "region0_main_code": true, + "region0_nvs": false, + "region0_wsoc_code": false, + "region0_alternate_code": false + }, + "region_1": { + "mem_region_1_start_phy_address": 0, + "mem_region_1_end_phy_address": 1069055, + "region1_boot": true, + "region1_main_code": false, + "region1_nvs": true, + "region1_wsoc_code": true, + "region1_alternate_code": false + }, + "region_2": { + "mem_region_2_start_phy_address": 0, + "mem_region_2_end_phy_address": 0, + "region2_boot": false, + "region2_main_code": false, + "region2_nvs": false, + "region2_wsoc_code": false, + "region2_alternate_code": true + }, + "region_3": { + "mem_region_3_start_phy_address": 0, + "mem_region_3_end_phy_address": 0, + "region3_boot": false, + "region3_main_code": false, + "region3_nvs": false, + "region3_wsoc_code": false, + "region3_alternate_code": false + }, + "boot_region_conf": { + "boot_region_size": 0, + "boot_region_flash_disco_param_start_address": 0, + "boot_region_primary_ti_bl_start_phy_address": 12284, + "boot_region_primary_ti_bl_magic": 0, + "boot_region_primary_ti_bl_major": 0, + "boot_region_primary_ti_bl_minor": 0, + "boot_region_sec_ti_bl_start_phy_address": 430076, + "boot_region_sec_ti_bl_magic": 0, + "boot_region_sec_ti_bl_major": 0, + "boot_region_sec_ti_bl_minor": 0 + }, + "main_code_region_conf": { + "main_code_region_vendor_image_start_phy_address": 1073148, + "main_code_region_vendor_image_magic": 0, + "main_code_region_vendor_image_major": 0, + "main_code_region_vendor_image_minor": 0, + "main_code_region_sbl_start_phy_address": 0, + "main_code_region_sbl_magic": 0, + "main_code_region_sbl_major": 0, + "main_code_region_sbl_minor": 0 + }, + "alt_code_region_conf": { + "alt_code_region_vendor_image_start_phy_address": 4194304, + "alt_code_region_vendor_image_magic": 0, + "alt_code_region_vendor_image_major": 0, + "alt_code_region_vendor_image_minor": 0, + "alt_code_region_sbl_start_phy_address": 0, + "alt_code_region_sbl_magic": 0, + "alt_code_region_sbl_major": 0, + "alt_code_region_sbl_minor": 0 + }, + "nvs_code_region_conf": { + "nvs_start_phy_address": 892928, + "nvs_region_size": 176128, + "nvs_region_primary_wsoc_start_phy_address": 430076, + "nvs_region_primary_wsoc_magic": 0, + "nvs_region_primary_wsoc_major": 0, + "nvs_region_primary_wsoc_minor": 0, + "nvs_region_sec_wsoc_start_phy_address": 897020, + "nvs_region_sec_wsoc_magic": 0, + "nvs_region_sec_wsoc_major": 0, + "nvs_region_sec_wsoc_minor": 0, + "nvs_region_primary_wsoc_bl2_start_phy_address": 0, + "nvs_region_primary_wsoc_bl2_magic": 0, + "nvs_region_primary_wsoc_bl2_major": 0, + "nvs_region_primary_wsoc_bl2_minor": 0, + "nvs_region_sec_wsoc_bl2_start_phy_address": 0, + "nvs_region_sec_wsoc_bl2_magic": 0, + "nvs_region_sec_wsoc_bl2_major": 0, + "nvs_region_sec_wsoc_bl2_minor": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/py25q32lb/flash_disc_param_otfde.json b/boards/ti/lp_em_cc35x1/config/flash/py25q32lb/flash_disc_param_otfde.json new file mode 100644 index 000000000000..3cd58d686a45 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/py25q32lb/flash_disc_param_otfde.json @@ -0,0 +1,286 @@ +{ + "otfde_header": { + "name": "OTFDEWFF3", + "flash_only": true, + "ip_protection": false, + "regions_lock": false, + "regions_number": 4, + "flash_enabled": true + }, + "bl_conf": { + "host_boot_done_lock": true, + "host_peripherals_lock": true, + "icache_conf_lock": true, + "m33_mem_part_lock": true, + "memss_firewall_lock": true, + "dma_channel_owner_lock": true, + "otfde_region_lock": true, + "core_events_lock": true + }, + "otfde_general": { + "parameters": { + "mem_otfde_initial_delay": 10, + "otfde_global_watchdog_timer": 5 + }, + "events": { + "reset_evt_mask": false, + "reset_evt_suspend": false, + "sft_reset_evt_mask": false, + "sft_reset_evt_suspend": false, + "bypass_mode_evt_mask": false, + "bypass_mode_evt_suspend": false, + "debug_mode_evt_mask": false, + "debug_mode_evt_suspend": false, + "general_evt_mask": false, + "general_evt_suspend": false, + "xspi_data_path_evt_mask": false, + "xspi_data_path_evt_suspend": false, + "xspi_cnfg_path_evt_mask": false, + "xspi_cnfg_path_evt_suspend": false, + "xspi_service_interrupt_evt_mask": false, + "xspi_service_interrupt_evt_suspend": false, + "trans_device_disabled_evt_mask": false, + "trans_device_disabled_evt_suspend": false, + "trans_region_disabled_evt_mask": false, + "trans_region_disabled_evt_suspend": false, + "trans_region_params_conf_evt_mask": false, + "trans_region_params_conf_evt_suspend": false, + "trans_multiple_regions_mapped_evt_mask": false, + "trans_multiple_regions_mapped_evt_suspend": false, + "trans_address_not_32_bit_evt_mask": false, + "trans_address_not_32_bit_evt_suspend": false, + "trans_size_not_32_bit_evt_mask": false, + "trans_size_not_32_bit_evt_suspend": false, + "trans_burst_not_32_bit_evt_mask": false, + "trans_burst_not_32_bit_evt_suspend": false, + "region_read_write_def_evt_mask": false, + "region_read_write_def_evt_suspend": false, + "suspend_while_disabled_evt_mask": false, + "suspend_while_disabled_evt_suspend": false + } + }, + "regions_settings": { + "region_parameters_lock": { + "REGION_0_PARAMS_0": true, + "REGION_0_PARAMS_1": true, + "REGION_0_PARAMS_2": true, + "REGION_1_PARAMS_0": false, + "REGION_1_PARAMS_1": false, + "REGION_1_PARAMS_2": false, + "REGION_2_PARAMS_0": true, + "REGION_2_PARAMS_1": true, + "REGION_2_PARAMS_2": true, + "REGION_3_PARAMS_0": false, + "REGION_3_PARAMS_1": false, + "REGION_3_PARAMS_2": false + }, + "region_0_protection": { + "mem_region_0_enabled": true, + "mem_region_0_device_id": 0, + "mem_region_0_spi_write_enable": true, + "mem_region_0_spi_read_enable": true, + "mem_region_0_physical_offset": 261, + "mem_region_0_security_id_msb": 0, + "mem_region_0_start_address": 81920, + "mem_region_0_end_address": 82682, + "mem_region_0_security_id_lsb": 0, + "mem_otfde_region_0_write_lock_en": false, + "mem_otfde_region_0_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_1_protection": { + "mem_region_1_enabled": true, + "mem_region_1_device_id": 0, + "mem_region_1_spi_write_enable": true, + "mem_region_1_spi_read_enable": true, + "mem_region_1_physical_offset": 0, + "mem_region_1_security_id_msb": 0, + "mem_region_1_start_address": 655360, + "mem_region_1_end_address": 655620, + "mem_region_1_security_id_lsb": 0, + "mem_otfde_region_1_write_lock_en": false, + "mem_otfde_region_1_enc_dec_bypass": "Bypass" + }, + "region_2_protection": { + "mem_region_2_enabled": false, + "mem_region_2_device_id": 0, + "mem_region_2_spi_write_enable": true, + "mem_region_2_spi_read_enable": true, + "mem_region_2_physical_offset": 0, + "mem_region_2_security_id_msb": 0, + "mem_region_2_start_address": 1, + "mem_region_2_end_address": 0, + "mem_region_2_security_id_lsb": 0, + "mem_otfde_region_2_write_lock_en": false, + "mem_otfde_region_2_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_3_protection": { + "mem_region_3_enabled": false, + "mem_region_3_device_id": 1, + "mem_region_3_spi_write_enable": true, + "mem_region_3_spi_read_enable": true, + "mem_region_3_physical_offset": 0, + "mem_region_3_security_id_msb": 0, + "mem_region_3_start_address": 1, + "mem_region_3_end_address": 0, + "mem_region_3_security_id_lsb": 0, + "mem_otfde_region_3_write_lock_en": false, + "mem_otfde_region_3_enc_dec_bypass": "Bypass" + } + }, + "devices": { + "header": { + "flash_device_switch_conf": 1, + "ram_device_switch_conf": 1 + }, + "flash_switch": { + "flash_grant_sel": 0, + "flash_data_for_conf_0": 2181562505, + "flash_offset_bits_for_conf_0": 0, + "flash_stop_bit_for_conf_0": 0, + "flash_data_for_conf_1": 167911947, + "flash_offset_bits_for_conf_1": 1, + "flash_stop_bit_for_conf_1": 0, + "flash_data_for_conf_2": 139266, + "flash_offset_bits_for_conf_2": 2, + "flash_stop_bit_for_conf_2": 0, + "flash_data_for_conf_3": 1, + "flash_offset_bits_for_conf_3": 4, + "flash_stop_bit_for_conf_3": 0, + "flash_data_for_conf_4": 1076887634, + "flash_offset_bits_for_conf_4": 45, + "flash_stop_bit_for_conf_4": 0, + "flash_data_for_conf_5": 3224371282, + "flash_offset_bits_for_conf_5": 45, + "flash_stop_bit_for_conf_5": 0, + "flash_data_for_conf_6": 262149, + "flash_offset_bits_for_conf_6": 14, + "flash_stop_bit_for_conf_6": 0, + "flash_data_for_conf_7": 0, + "flash_offset_bits_for_conf_7": 44, + "flash_stop_bit_for_conf_7": 1, + "flash_data_for_conf_8": 0, + "flash_offset_bits_for_conf_8": 0, + "flash_stop_bit_for_conf_8": 1, + "flash_data_for_conf_9": 0, + "flash_offset_bits_for_conf_9": 0, + "flash_stop_bit_for_conf_9": 1, + "flash_data_for_conf_10": 0, + "flash_offset_bits_for_conf_10": 0, + "flash_stop_bit_for_conf_10": 1, + "flash_data_for_conf_11": 0, + "flash_offset_bits_for_conf_11": 0, + "flash_stop_bit_for_conf_11": 1, + "flash_data_for_conf_12": 0, + "flash_offset_bits_for_conf_12": 0, + "flash_stop_bit_for_conf_12": 1, + "flash_data_for_conf_13": 0, + "flash_offset_bits_for_conf_13": 0, + "flash_stop_bit_for_conf_13": 1, + "flash_data_for_conf_14": 0, + "flash_offset_bits_for_conf_14": 0, + "flash_stop_bit_for_conf_14": 1, + "flash_data_for_conf_15": 0, + "flash_offset_bits_for_conf_15": 0, + "flash_stop_bit_for_conf_15": 1, + "flash_data_for_conf_16": 0, + "flash_offset_bits_for_conf_16": 0, + "flash_stop_bit_for_conf_16": 1, + "flash_data_for_conf_17": 0, + "flash_offset_bits_for_conf_17": 0, + "flash_stop_bit_for_conf_17": 1, + "flash_data_for_conf_18": 0, + "flash_offset_bits_for_conf_18": 0, + "flash_stop_bit_for_conf_18": 1, + "flash_data_for_conf_19": 0, + "flash_offset_bits_for_conf_19": 0, + "flash_stop_bit_for_conf_19": 1, + "flash_data_for_conf_20": 0, + "flash_offset_bits_for_conf_20": 0, + "flash_stop_bit_for_conf_20": 1, + "flash_data_for_conf_21": 0, + "flash_offset_bits_for_conf_21": 0, + "flash_stop_bit_for_conf_21": 1, + "flash_data_for_conf_22": 0, + "flash_offset_bits_for_conf_22": 0, + "flash_stop_bit_for_conf_22": 1, + "flash_data_for_conf_23": 0, + "flash_offset_bits_for_conf_23": 0, + "flash_stop_bit_for_conf_23": 1 + }, + "ram_switch": { + "ram_grant_sel": 0, + "ram_data_for_conf_0": 2181562505, + "ram_offset_bits_for_conf_0": 0, + "ram_stop_bit_for_conf_0": 0, + "ram_data_for_conf_1": 67248651, + "ram_offset_bits_for_conf_1": 1, + "ram_stop_bit_for_conf_1": 0, + "ram_data_for_conf_2": 139266, + "ram_offset_bits_for_conf_2": 2, + "ram_stop_bit_for_conf_2": 0, + "ram_data_for_conf_3": 1, + "ram_offset_bits_for_conf_3": 4, + "ram_stop_bit_for_conf_3": 0, + "ram_data_for_conf_4": 1076887634, + "ram_offset_bits_for_conf_4": 45, + "ram_stop_bit_for_conf_4": 0, + "ram_data_for_conf_5": 3224371282, + "ram_offset_bits_for_conf_5": 45, + "ram_stop_bit_for_conf_5": 0, + "ram_data_for_conf_6": 262149, + "ram_offset_bits_for_conf_6": 14, + "ram_stop_bit_for_conf_6": 0, + "ram_data_for_conf_7": 0, + "ram_offset_bits_for_conf_7": 44, + "ram_stop_bit_for_conf_7": 1, + "ram_data_for_conf_8": 0, + "ram_offset_bits_for_conf_8": 0, + "ram_stop_bit_for_conf_8": 1, + "ram_data_for_conf_9": 0, + "ram_offset_bits_for_conf_9": 0, + "ram_stop_bit_for_conf_9": 1, + "ram_data_for_conf_10": 0, + "ram_offset_bits_for_conf_10": 0, + "ram_stop_bit_for_conf_10": 1, + "ram_data_for_conf_11": 0, + "ram_offset_bits_for_conf_11": 0, + "ram_stop_bit_for_conf_11": 1, + "ram_data_for_conf_12": 0, + "ram_offset_bits_for_conf_12": 0, + "ram_stop_bit_for_conf_12": 1, + "ram_data_for_conf_13": 0, + "ram_offset_bits_for_conf_13": 0, + "ram_stop_bit_for_conf_13": 1, + "ram_data_for_conf_14": 0, + "ram_offset_bits_for_conf_14": 0, + "ram_stop_bit_for_conf_14": 1, + "ram_data_for_conf_15": 0, + "ram_offset_bits_for_conf_15": 0, + "ram_stop_bit_for_conf_15": 1, + "ram_data_for_conf_16": 0, + "ram_offset_bits_for_conf_16": 0, + "ram_stop_bit_for_conf_16": 1, + "ram_data_for_conf_17": 0, + "ram_offset_bits_for_conf_17": 0, + "ram_stop_bit_for_conf_17": 1, + "ram_data_for_conf_18": 0, + "ram_offset_bits_for_conf_18": 0, + "ram_stop_bit_for_conf_18": 1, + "ram_data_for_conf_19": 0, + "ram_offset_bits_for_conf_19": 0, + "ram_stop_bit_for_conf_19": 1, + "ram_data_for_conf_20": 0, + "ram_offset_bits_for_conf_20": 0, + "ram_stop_bit_for_conf_20": 1, + "ram_data_for_conf_21": 0, + "ram_offset_bits_for_conf_21": 0, + "ram_stop_bit_for_conf_21": 1, + "ram_data_for_conf_22": 0, + "ram_offset_bits_for_conf_22": 0, + "ram_stop_bit_for_conf_22": 1, + "ram_data_for_conf_23": 0, + "ram_offset_bits_for_conf_23": 0, + "ram_stop_bit_for_conf_23": 1 + } + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/py25q32lb/flash_disc_param_xspi.json b/boards/ti/lp_em_cc35x1/config/flash/py25q32lb/flash_disc_param_xspi.json new file mode 100644 index 000000000000..4e40e5c6e041 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/py25q32lb/flash_disc_param_xspi.json @@ -0,0 +1,485 @@ +{ + "xspi_header": { + "name": "xSPIWFF3", + "device": "CC3500", + "use_hardware": "PY25Q32LB", + "use_case": "Quadro", + "dqs_support": 0, + "flash_only": 1, + "flash_separate_reset": 0, + "ram_separate_reset": true, + "clock_frequency": 80, + "qospi_clock_divider": 1, + "flash_device_character_conf": 0, + "ram_device_character_conf": 0, + "header_advanced": 0, + "phy_mode_enable": 1, + "pipeline_mode_enable": 1, + "loopback_support": "No", + "qspi_ref_clock": 80, + "spi_clock_freq": 20, + "spi_clock_divider": 1, + "flash_device_size": 4, + "flash_bytes_per_block": 16, + "flash_bytes_per_page": 256, + "flash_number_of_address_bytes": 3, + "flash_dual_opcode": 0, + "flash_jedec_manufacturer_id": 0, + "flash_jedec_device_id": 0, + "flash_name": "PY25Q32LB", + "flash_page_size": 256, + "flash_sector_size": 4096, + "flash_cs_polarity": "ACTIVE_LOW", + "flash_sw_reset_type": "x1xxxx", + "ram_device_size": 4, + "ram_bytes_per_block": 16, + "ram_bytes_per_page": 256, + "ram_number_of_address_bytes": 3, + "ram_dual_opcode": 0, + "ram_jedec_manufacturer_id": 0, + "ram_jedec_device_id": 0, + "ram_name": "NO_PSRAM", + "ram_page_size": 256, + "ram_sector_size": 4096, + "ram_cs_polarity": "ACTIVE_LOW", + "ram_sw_reset_type": "x1xxxx", + "flash_write_operation_modes": "4S-4S-4S", + "flash_read_operation_modes": "4S-4S-4S", + "ram_write_operation_modes": "4S-4S-4S", + "ram_read_operation_modes": "4S-4S-4S", + "crc_enable": 0, + "enable_dtr": 0, + "enable_ahb_decoder": 0, + "enter_xip_mod_immediately": 0, + "enter_xip_mod_next_read": 0, + "ahb_address_remapping": 0, + "enable_dma": 0, + "select_decode": 0, + "legacy_ip_mode": 0, + "direct_access": 1 + }, + "xspi_pinmux": { + "xspi_clk_input": 44, + "xspi_clk_input_use_hw": 0, + "xspi_clk_input_mode": "Input", + "xspi_clk_input_pull": "None", + "xspi_clk_input_interrupt_trigger": "Low", + "xspi_clk_input_dont_conf": 0, + "xspi_clk_input_output_strength": "High", + "xspi_clk_input_initial_output_state": "High", + "xspi_clk": 24, + "xspi_clk_use_hw": "None", + "xspi_clk_mode": "Output", + "xspi_clk_pull": "None", + "xspi_clk_output_strength": "High", + "xspi_clk_initial_output_state": "High", + "xspi_clk_interrupt_trigger": "None", + "xspi_clk_dont_conf": 0, + "xspi_flash_cs": 20, + "xspi_flash_cs_use_hw": "None", + "xspi_flash_cs_mode": "Output", + "xspi_flash_cs_pull": "None", + "xspi_flash_cs_output_strength": "High", + "xspi_flash_cs_initial_output_state": "High", + "xspi_flash_cs_interrupt_trigger": "None", + "xspi_flash_cs_dont_conf": 0, + "xspi_data_0": 25, + "xspi_data_0_use_hw": "None", + "xspi_data_0_mode": "Input", + "xspi_data_0_pull": "None", + "xspi_data_0_output_strength": "High", + "xspi_data_0_initial_output_state": "High", + "xspi_data_0_interrupt_trigger": "Low", + "xspi_data_0_dont_conf": 0, + "xspi_data_1": 21, + "xspi_data_1_use_hw": "None", + "xspi_data_1_mode": "Input", + "xspi_data_1_pull": "None", + "xspi_data_1_output_strength": "High", + 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"xspi_data_5_mode": "Input", + "xspi_data_5_pull": "None", + "xspi_data_5_output_strength": "High", + "xspi_data_5_initial_output_state": "High", + "xspi_data_5_interrupt_trigger": "None", + "xspi_data_5_dont_conf": 0, + "xspi_data_6": 28, + "xspi_data_6_use_hw": "None", + "xspi_data_6_mode": "Input", + "xspi_data_6_pull": "None", + "xspi_data_6_output_strength": "High", + "xspi_data_6_initial_output_state": "High", + "xspi_data_6_interrupt_trigger": "None", + "xspi_data_6_dont_conf": 0, + "xspi_data_7": 29, + "xspi_data_7_use_hw": "None", + "xspi_data_7_mode": "Input", + "xspi_data_7_pull": "None", + "xspi_data_7_output_strength": "High", + "xspi_data_7_initial_output_state": "High", + "xspi_data_7_interrupt_trigger": "None", + "xspi_data_7_dont_conf": 0, + "xspi_reset_flash": 36, + "xspi_reset_flash_use_hw": "None", + "xspi_reset_flash_mode": "Output", + "xspi_reset_flash_pull": "None", + "xspi_reset_flash_output_strength": "High", + "xspi_reset_flash_initial_output_state": "High", + "xspi_reset_flash_interrupt_trigger": "None", + "xspi_reset_flash_dont_conf": 0, + "xspi_cs_ram": 3, + "xspi_cs_ram_use_hw": "None", + "xspi_cs_ram_mode": "Output", + "xspi_cs_ram_pull": "None", + "xspi_cs_ram_output_strength": "High", + "xspi_cs_ram_initial_output_state": "High", + "xspi_cs_ram_interrupt_trigger": "None", + "xspi_cs_ram_dont_conf": 0, + "xspi_dqs": 30, + "xspi_dqs_use_hw": "None", + "xspi_dqs_mode": "Input", + "xspi_dqs_pull": "None", + "xspi_dqs_output_strength": "High", + "xspi_dqs_initial_output_state": "High", + "xspi_dqs_interrupt_trigger": "None", + "xspi_dqs_dont_conf": 0, + "xspi_reset_ram": 2, + "xspi_reset_ram_use_hw": "None", + "xspi_reset_ram_mode": "Input", + "xspi_reset_ram_pull": "None", + "xspi_reset_ram_output_strength": "High", + "xspi_reset_ram_initial_output_state": "High", + "xspi_reset_ram_interrupt_trigger": "None", + "xspi_reset_ram_dont_conf": 0 + }, + "xspi_operations": { + "xspi_operations_clocks": { + "clock_phase": 0, + "clock_polarity": 0, + "spi_mode": "2'b00" + }, + "xspi_operations_chip_select": { + "csda": 2, + "csdads": 0, + "cseot": 4, + "cssot": 1 + }, + "xspi_operations_reset": { + "flash_jedec_reset": 0, + "ram_jedec_reset": 0, + "flash_treset": 20, + "ram_treset": 20 + }, + "xspi_phy_operations": { + "flash_rx_dll_bypass_bit": 0, + "flash_dll_tx_delay": 22, + "flash_dll_rx_delay": 34, + "ram_rx_dll_bypass_bit": 0, + "ram_dll_tx_delay": 22, + "ram_dll_rx_delay": 34 + }, + "xspi_read_operations": { + "flash_dummy_rd_cycles": 10, + "flash_read_opcode": 11, + "suppl_flash_read_opcode": 0, + "ram_dummy_rd_cycles": 10, + "ram_read_opcode": 11, + "suppl_ram_read_opcode": 0, + "flash_non_cont_read_enable": 0, + "flash_max_read_jobs": 256, + "ram_non_cont_read_enable": 0, + "ram_max_read_jobs": 256, + "rww_en": 0, + "device_size": 4, + "number_of_banks": 1, + "bank_size": 4, + "mode_bit_enable": 0 + }, + "xspi_write_operations": { + "flash_address_and_data": { + "flash_dummy_wr_cycles": 0 + }, + "flash_command": { + "flash_write_opcode": 2, + "suppl_flash_write_opcode": 0 + }, + "ram_address_and_data": { + "ram_dummy_wr_cycles": 0 + }, + "ram_command": { + "ram_write_opcode": 2, + "suppl_ram_write_opcode": 0 + }, + "write_to_buffer": { + "flash_write_to_buffer_support": 0, + "ram_write_to_buffer_support": 0 + }, + "non_continuous_write": { + "flash_non_cont_write_enable": 0, + "flash_max_write_jobs": 64, + "ram_non_cont_write_enable": 0, + "ram_max_write_jobs": 0 + }, + "flash_program_operation": { + "flash_min_program_size": "256 B", + "flash_program_opcode": 2, + "suppl_flash_program_opcode": 0, + "flash_maximum_program_time_limit": 1600 + }, + "flash_erase_operation": { + "flash_min_erase_size": "4 kB", + "flash_erase_opcode": 32, + "suppl_flash_erase_opcode": 0, + "flash_maximum_erase_time_limit": 4095 + }, + "flash_erase_conf": { + "flash_block_erase_opcode": 0, + "suppl_block_flash_erase_opcode": 0, + "flash_sector_erase_opcode": 0, + "suppl_sector_flash_erase_opcode": 0, + "flash_chip_erase_opcode": 0, + "suppl_chip_flash_erase_opcode": 0 + }, + "ram_program_operation": { + "ram_min_program_size": "256 B", + "ram_program_opcode": 2, + "suppl_ram_program_opcode": 0, + "ram_maximum_program_time_limit": 1600 + }, + "ram_erase_conf": { + "ram_block_erase_opcode": 0, + "suppl_block_ram_erase_opcode": 0, + "ram_sector_erase_opcode": 0, + "suppl_sector_ram_erase_opcode": 0, + "ram_chip_erase_opcode": 0, + "suppl_chip_ram_erase_opcode": 0 + }, + "flash_buffer_support": { + "flash_pre_write_sequence": 0, + "flash_post_write_sequence": 0, + "flash_write_protection_timer_en": 0, + "flash_write_buffer_timer_mode": 16, + "flash_write_buffer_timer_range": 0, + "flash_service_interrupt_criteria": 0 + }, + "ram_buffer_support": { + "ram_pre_write_sequence": 0, + "ram_post_write_sequence": 0, + "ram_write_protection_timer_en": 0, + "ram_write_buffer_timer_mode": 16, + "ram_write_buffer_timer_range": 0, + "ram_service_interrupt_criteria": 0 + }, + "flash_pre_write_conf": { + "flash_pre_write_job_done_grant_sel": 0, + "data_for_flash_pre_write_conf_0": 0, + "offset_bits_for_flash_pre_write_conf_0": 0, + "stop_bit_for_flash_pre_write_conf_0": 1, + "data_for_flash_pre_write_conf_1": 0, + "offset_bits_for_flash_pre_write_conf_1": 0 + }, + "flash_post_write_conf": { + "flash_post_write_job_done_grant_sel": 0, + "data_for_flash_post_write_conf_0": 0, + "offset_bits_for_flash_post_write_conf_0": 0, + "stop_bit_for_flash_post_write_conf_0": 1, + "data_for_flash_post_write_conf_1": 0, + "offset_bits_for_flash_post_write_conf_1": 0 + }, + "ram_pre_write_conf": { + "ram_pre_write_job_done_grant_sel": 0, + "data_for_ram_pre_write_conf_0": 0, + "offset_bits_for_ram_pre_write_conf_0": 0, + "stop_bit_for_ram_pre_write_conf_0": 1, + "data_for_ram_pre_write_conf_1": 0, + "offset_bits_for_ram_pre_write_conf_1": 0 + }, + "ram_post_write_conf": { + "ram_post_write_job_done_grant_sel": 0, + "data_for_ram_post_write_conf_0": 0, + "offset_bits_for_ram_post_write_conf_0": 0, + "stop_bit_for_ram_post_write_conf_0": 1, + "data_for_ram_post_write_conf_1": 0, + "offset_bits_for_ram_post_write_conf_1": 0 + } + }, + "xspi_capture_operations": { + "read_data_capture": { + "flash_delay_transmitted_data": 0, + "flash_loopback_clock": 0, + "flash_bypass_adapted_loopback": 1, + "flash_sample_edge_sel": 0, + "ram_delay_transmitted_data": 0, + "ram_loopback_clock": 0, + "ram_bypass_adapted_loopback": 1, + "ram_sample_edge_sel": 0 + }, + "delays": { + "flash_full_half_cycle_delay": 0, + "flash_dll_bypass_mode": 1, + "flash_phase_detect_sel": 0, + "flash_dll_lock_num": 0, + "flash_dll_start_point": 0, + "flash_loopback_clock": 0, + "ram_full_half_cycle_delay": 0, + "ram_dll_bypass_mode": 1, + "ram_phase_detect_sel": 0, + "ram_dll_lock_num": 0, + "ram_dll_start_point": 0, + "ram_loopback_clock": 0 + }, + "operation_modes": { + "flash_sfdp_support": 0, + "ram_sfdp_support": 0, + "flash_pm_support": 0, + "ram_pm_support": 0, + "flash_sfdp_opcode": 0, + "suppl_flash_sfdp_opcode": 0, + "ram_sfdp_opcode": 0, + "suppl_ram_sfdp_opcode": 0, + "flash_enter_dpd_opcode": 185, + "suppl_flash_enter_dpd_opcode": 0, + "flash_exit_dpd_opcode": 171, + "suppl_flash_exit_dpd_opcode": 0, + "ram_enter_dpd_opcode": 185, + "suppl_ram_enter_dpd_opcode": 0, + "ram_exit_dpd_opcode": 171, + "suppl_ram_exit_dpd_opcode": 0, + "flash_quad_enable_opcode": 56, + "suppl_flash_quad_enable_opcode": 0, + "flash_quad_disable_opcode": 255, + "suppl_flash_quad_disable_opcode": 0, + "flash_octal_enable_opcode": 0, + "suppl_flash_octal_enable_opcode": 0, + "flash_octal_disable_opcode": 0, + "suppl_flash_octal_disable_opcode": 0, + "ram_quad_enable_opcode": 56, + "suppl_ram_quad_enable_opcode": 0, + "ram_quad_disable_opcode": 255, + "suppl_ram_quad_disable_opcode": 0, + "ram_octal_enable_opcode": 0, + "suppl_ram_octal_enable_opcode": 0, + "ram_octal_disable_opcode": 0, + "suppl_ram_octal_disable_opcode": 0 + } + } + }, + "external_memory_reporting": { + "header": { + "flash_auto_polling_enable": 1, + "flash_wel_enable": 1, + "flash_write_protect_enable": 0, + "flash_alternate_polling_conf_enable": 0, + "ram_auto_polling_enable": 1, + "ram_wel_enable": 1, + "ram_write_protect_enable": 0, + "ram_alternate_polling_conf_enable": 0 + }, + "flash_auto_polling": { + "flash_polling_repetition_delay": 0, + "flash_polling_count": 4, + "flash_enable_polling_expiration": 0, + "flash_polling_polarity": 0, + "flash_polling_address_phase_enable": 0, + "flash_polling_bit_index": 0, + "flash_numbers_poll_cycles": 65535, + "flash_dummy_autopoll_cycles": 0 + }, + "ram_auto_polling": { + "ram_polling_repetition_delay": 0, + "ram_polling_count": 4, + "ram_enable_polling_expiration": 0, + "ram_polling_polarity": 0, + "ram_polling_address_phase_enable": 0, + "ram_polling_bit_index": 0, + "ram_numbers_poll_cycles": 65535, + "ram_dummy_autopoll_cycles": 0 + }, + "flash_polling_command": { + "flash_polling_opcode": 5, + "suppl_flash_polling_opcode": 0 + }, + "ram_polling_command": { + "ram_polling_opcode": 5, + "suppl_ram_polling_opcode": 0 + }, + "flash_alternate_polling": { + "flash_polling_resp_count": 1023, + "flash_polling_iterations": 1, + "flash_polling_enabled": 0, + "flash_polling_disabled": 0, + "flash_grant_sel": 0, + "flash_data_for_enable_poling_conf_0": 0, + "flash_offset_bits_for_enable_poling_conf_0": 0, + "flash_stop_bit_for_enable_poling_conf_0": 1, + "flash_data_for_enable_poling_conf_1": 0, + "flash_offset_bits_for_enable_poling_conf_1": 0, + "flash_stop_bit_for_enable_poling_conf_1": 1, + "flash_data_for_disable_poling_conf_0": 0, + "flash_offset_bits_for_disable_poling_conf_0": 0, + "flash_stop_bit_for_disable_poling_conf_0": 1, + "flash_data_for_disable_poling_conf_1": 0, + "flash_offset_bits_for_disable_poling_conf_1": 0, + "flash_stop_bit_for_disable_poling_conf_1": 1 + }, + "ram_alternate_polling": { + "ram_polling_resp_count": 1023, + "ram_polling_iterations": 1, + "ram_polling_enabled": 0, + "ram_polling_disabled": 0, + "ram_grant_sel": 0, + "ram_data_for_enable_poling_conf_0": 0, + "ram_offset_bits_for_enable_poling_conf_0": 0, + "ram_stop_bit_for_enable_poling_conf_0": 1, + "ram_data_for_enable_poling_conf_1": 0, + "ram_offset_bits_for_enable_poling_conf_1": 0, + "ram_stop_bit_for_enable_poling_conf_1": 1, + "ram_data_for_disable_poling_conf_0": 0, + "ram_offset_bits_for_disable_poling_conf_0": 0, + "ram_stop_bit_for_disable_poling_conf_0": 1, + "ram_data_for_disable_poling_conf_1": 0, + "ram_offset_bits_for_disable_poling_conf_1": 0, + "ram_stop_bit_for_disable_poling_conf_1": 1 + }, + "flash_wel_command": { + "flash_wel_opcode": 6, + "suppl_flash_wel_opcode": 0 + }, + "ram_wel_command": { + "ram_wel_opcode": 6, + "suppl_ram_wel_opcode": 0 + } + }, + "event": { + "host_nvic_irq": 0, + "core_10_mux_sel": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/py25q64lb/flash_disc_param_ext_mem.json b/boards/ti/lp_em_cc35x1/config/flash/py25q64lb/flash_disc_param_ext_mem.json new file mode 100644 index 000000000000..6585853ccd5e --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/py25q64lb/flash_disc_param_ext_mem.json @@ -0,0 +1,99 @@ +{ + "vendor_primary_sbl": true, + "ti_wsoc_primary_container": true, + "ti_wsoc_bl2_primary_container": true, + "nvs_enable": true, + "vendor_alternate_image": true, + "vendor_sbl_alternate_image": true, + "ti_bl_alternate_image": true, + "ti_wsoc_alternate_image": true, + "ti_wsoc_bl2_alternate_image": true, + "region_0": { + "mem_region_0_start_phy_address": 2867200, + "mem_region_0_end_phy_address": 5627903, + "region0_boot": false, + "region0_main_code": true, + "region0_nvs": false, + "region0_wsoc_code": false, + "region0_alternate_code": false + }, + "region_1": { + "mem_region_1_start_phy_address": 0, + "mem_region_1_end_phy_address": 2867199, + "region1_boot": true, + "region1_main_code": false, + "region1_nvs": true, + "region1_wsoc_code": true, + "region1_alternate_code": false + }, + "region_2": { + "mem_region_2_start_phy_address": 5627904, + "mem_region_2_end_phy_address": 8388607, + "region2_boot": false, + "region2_main_code": false, + "region2_nvs": false, + "region2_wsoc_code": false, + "region2_alternate_code": true + }, + "region_3": { + "mem_region_3_start_phy_address": 0, + "mem_region_3_end_phy_address": 0, + "region3_boot": false, + "region3_main_code": false, + "region3_nvs": false, + "region3_wsoc_code": false, + "region3_alternate_code": false + }, + "boot_region_conf": { + "boot_region_size": 0, + "boot_region_flash_disco_param_start_address": 0, + "boot_region_primary_ti_bl_start_phy_address": 12284, + "boot_region_primary_ti_bl_magic": 0, + "boot_region_primary_ti_bl_major": 0, + "boot_region_primary_ti_bl_minor": 0, + "boot_region_sec_ti_bl_start_phy_address": 430076, + "boot_region_sec_ti_bl_magic": 0, + "boot_region_sec_ti_bl_major": 0, + "boot_region_sec_ti_bl_minor": 0 + }, + "main_code_region_conf": { + "main_code_region_vendor_image_start_phy_address": 2871292, + "main_code_region_vendor_image_magic": 0, + "main_code_region_vendor_image_major": 0, + "main_code_region_vendor_image_minor": 0, + "main_code_region_sbl_start_phy_address": 0, + "main_code_region_sbl_magic": 0, + "main_code_region_sbl_major": 0, + "main_code_region_sbl_minor": 0 + }, + "alt_code_region_conf": { + "alt_code_region_vendor_image_start_phy_address": 5631996, + "alt_code_region_vendor_image_magic": 0, + "alt_code_region_vendor_image_major": 0, + "alt_code_region_vendor_image_minor": 0, + "alt_code_region_sbl_start_phy_address": 0, + "alt_code_region_sbl_magic": 0, + "alt_code_region_sbl_major": 0, + "alt_code_region_sbl_minor": 0 + }, + "nvs_code_region_conf": { + "nvs_start_phy_address": 1777664, + "nvs_region_size": 1089536, + "nvs_region_primary_wsoc_start_phy_address": 847868, + "nvs_region_primary_wsoc_magic": 0, + "nvs_region_primary_wsoc_major": 0, + "nvs_region_primary_wsoc_minor": 0, + "nvs_region_sec_wsoc_start_phy_address": 1314812, + "nvs_region_sec_wsoc_magic": 0, + "nvs_region_sec_wsoc_major": 0, + "nvs_region_sec_wsoc_minor": 0, + "nvs_region_primary_wsoc_bl2_start_phy_address": 0, + "nvs_region_primary_wsoc_bl2_magic": 0, + "nvs_region_primary_wsoc_bl2_major": 0, + "nvs_region_primary_wsoc_bl2_minor": 0, + "nvs_region_sec_wsoc_bl2_start_phy_address": 0, + "nvs_region_sec_wsoc_bl2_magic": 0, + "nvs_region_sec_wsoc_bl2_major": 0, + "nvs_region_sec_wsoc_bl2_minor": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/py25q64lb/flash_disc_param_otfde.json b/boards/ti/lp_em_cc35x1/config/flash/py25q64lb/flash_disc_param_otfde.json new file mode 100644 index 000000000000..b361706e76c1 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/py25q64lb/flash_disc_param_otfde.json @@ -0,0 +1,286 @@ +{ + "otfde_header": { + "name": "OTFDEWFF3", + "flash_only": true, + "ip_protection": false, + "regions_lock": false, + "regions_number": 4, + "flash_enabled": true + }, + "bl_conf": { + "host_boot_done_lock": true, + "host_peripherals_lock": true, + "icache_conf_lock": true, + "m33_mem_part_lock": true, + "memss_firewall_lock": true, + "dma_channel_owner_lock": true, + "otfde_region_lock": true, + "core_events_lock": true + }, + "otfde_general": { + "parameters": { + "mem_otfde_initial_delay": 10, + "otfde_global_watchdog_timer": 5 + }, + "events": { + "reset_evt_mask": false, + "reset_evt_suspend": false, + "sft_reset_evt_mask": false, + "sft_reset_evt_suspend": false, + "bypass_mode_evt_mask": false, + "bypass_mode_evt_suspend": false, + "debug_mode_evt_mask": false, + "debug_mode_evt_suspend": false, + "general_evt_mask": false, + "general_evt_suspend": false, + "xspi_data_path_evt_mask": false, + "xspi_data_path_evt_suspend": false, + "xspi_cnfg_path_evt_mask": false, + "xspi_cnfg_path_evt_suspend": false, + "xspi_service_interrupt_evt_mask": false, + "xspi_service_interrupt_evt_suspend": false, + "trans_device_disabled_evt_mask": false, + "trans_device_disabled_evt_suspend": false, + "trans_region_disabled_evt_mask": false, + "trans_region_disabled_evt_suspend": false, + "trans_region_params_conf_evt_mask": false, + "trans_region_params_conf_evt_suspend": false, + "trans_multiple_regions_mapped_evt_mask": false, + "trans_multiple_regions_mapped_evt_suspend": false, + "trans_address_not_32_bit_evt_mask": false, + "trans_address_not_32_bit_evt_suspend": false, + "trans_size_not_32_bit_evt_mask": false, + "trans_size_not_32_bit_evt_suspend": false, + "trans_burst_not_32_bit_evt_mask": false, + "trans_burst_not_32_bit_evt_suspend": false, + "region_read_write_def_evt_mask": false, + "region_read_write_def_evt_suspend": false, + "suspend_while_disabled_evt_mask": false, + "suspend_while_disabled_evt_suspend": false + } + }, + "regions_settings": { + "region_parameters_lock": { + "REGION_0_PARAMS_0": true, + "REGION_0_PARAMS_1": true, + "REGION_0_PARAMS_2": true, + "REGION_1_PARAMS_0": false, + "REGION_1_PARAMS_1": false, + "REGION_1_PARAMS_2": false, + "REGION_2_PARAMS_0": true, + "REGION_2_PARAMS_1": true, + "REGION_2_PARAMS_2": true, + "REGION_3_PARAMS_0": false, + "REGION_3_PARAMS_1": false, + "REGION_3_PARAMS_2": false + }, + "region_0_protection": { + "mem_region_0_enabled": true, + "mem_region_0_device_id": 0, + "mem_region_0_spi_write_enable": true, + "mem_region_0_spi_read_enable": true, + "mem_region_0_physical_offset": 700, + "mem_region_0_security_id_msb": 0, + "mem_region_0_start_address": 81920, + "mem_region_0_end_address": 82593, + "mem_region_0_security_id_lsb": 0, + "mem_otfde_region_0_write_lock_en": false, + "mem_otfde_region_0_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_1_protection": { + "mem_region_1_enabled": true, + "mem_region_1_device_id": 0, + "mem_region_1_spi_write_enable": true, + "mem_region_1_spi_read_enable": true, + "mem_region_1_physical_offset": 0, + "mem_region_1_security_id_msb": 0, + "mem_region_1_start_address": 655360, + "mem_region_1_end_address": 656059, + "mem_region_1_security_id_lsb": 0, + "mem_otfde_region_1_write_lock_en": false, + "mem_otfde_region_1_enc_dec_bypass": "Bypass" + }, + "region_2_protection": { + "mem_region_2_enabled": true, + "mem_region_2_device_id": 0, + "mem_region_2_spi_write_enable": true, + "mem_region_2_spi_read_enable": true, + "mem_region_2_physical_offset": 1374, + "mem_region_2_security_id_msb": 0, + "mem_region_2_start_address": 671744, + "mem_region_2_end_address": 672417, + "mem_region_2_security_id_lsb": 0, + "mem_otfde_region_2_write_lock_en": false, + "mem_otfde_region_2_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_3_protection": { + "mem_region_3_enabled": false, + "mem_region_3_device_id": 1, + "mem_region_3_spi_write_enable": true, + "mem_region_3_spi_read_enable": true, + "mem_region_3_physical_offset": 0, + "mem_region_3_security_id_msb": 0, + "mem_region_3_start_address": 1, + "mem_region_3_end_address": 0, + "mem_region_3_security_id_lsb": 0, + "mem_otfde_region_3_write_lock_en": false, + "mem_otfde_region_3_enc_dec_bypass": "Bypass" + } + }, + "devices": { + "header": { + "flash_device_switch_conf": 1, + "ram_device_switch_conf": 1 + }, + "flash_switch": { + "flash_grant_sel": 0, + "flash_data_for_conf_0": 2181562505, + "flash_offset_bits_for_conf_0": 0, + "flash_stop_bit_for_conf_0": 0, + "flash_data_for_conf_1": 167911947, + "flash_offset_bits_for_conf_1": 1, + "flash_stop_bit_for_conf_1": 0, + "flash_data_for_conf_2": 139266, + "flash_offset_bits_for_conf_2": 2, + "flash_stop_bit_for_conf_2": 0, + "flash_data_for_conf_3": 1, + "flash_offset_bits_for_conf_3": 4, + "flash_stop_bit_for_conf_3": 0, + "flash_data_for_conf_4": 1076887634, + "flash_offset_bits_for_conf_4": 45, + "flash_stop_bit_for_conf_4": 0, + "flash_data_for_conf_5": 3224371282, + "flash_offset_bits_for_conf_5": 45, + "flash_stop_bit_for_conf_5": 0, + "flash_data_for_conf_6": 262149, + "flash_offset_bits_for_conf_6": 14, + "flash_stop_bit_for_conf_6": 0, + "flash_data_for_conf_7": 0, + "flash_offset_bits_for_conf_7": 44, + "flash_stop_bit_for_conf_7": 1, + "flash_data_for_conf_8": 0, + "flash_offset_bits_for_conf_8": 0, + "flash_stop_bit_for_conf_8": 1, + "flash_data_for_conf_9": 0, + "flash_offset_bits_for_conf_9": 0, + "flash_stop_bit_for_conf_9": 1, + "flash_data_for_conf_10": 0, + "flash_offset_bits_for_conf_10": 0, + "flash_stop_bit_for_conf_10": 1, + "flash_data_for_conf_11": 0, + "flash_offset_bits_for_conf_11": 0, + "flash_stop_bit_for_conf_11": 1, + "flash_data_for_conf_12": 0, + "flash_offset_bits_for_conf_12": 0, + "flash_stop_bit_for_conf_12": 1, + "flash_data_for_conf_13": 0, + "flash_offset_bits_for_conf_13": 0, + "flash_stop_bit_for_conf_13": 1, + "flash_data_for_conf_14": 0, + "flash_offset_bits_for_conf_14": 0, + "flash_stop_bit_for_conf_14": 1, + "flash_data_for_conf_15": 0, + "flash_offset_bits_for_conf_15": 0, + "flash_stop_bit_for_conf_15": 1, + "flash_data_for_conf_16": 0, + "flash_offset_bits_for_conf_16": 0, + "flash_stop_bit_for_conf_16": 1, + "flash_data_for_conf_17": 0, + "flash_offset_bits_for_conf_17": 0, + "flash_stop_bit_for_conf_17": 1, + "flash_data_for_conf_18": 0, + "flash_offset_bits_for_conf_18": 0, + "flash_stop_bit_for_conf_18": 1, + "flash_data_for_conf_19": 0, + "flash_offset_bits_for_conf_19": 0, + "flash_stop_bit_for_conf_19": 1, + "flash_data_for_conf_20": 0, + "flash_offset_bits_for_conf_20": 0, + "flash_stop_bit_for_conf_20": 1, + "flash_data_for_conf_21": 0, + "flash_offset_bits_for_conf_21": 0, + "flash_stop_bit_for_conf_21": 1, + "flash_data_for_conf_22": 0, + "flash_offset_bits_for_conf_22": 0, + "flash_stop_bit_for_conf_22": 1, + "flash_data_for_conf_23": 0, + "flash_offset_bits_for_conf_23": 0, + "flash_stop_bit_for_conf_23": 1 + }, + "ram_switch": { + "ram_grant_sel": 0, + "ram_data_for_conf_0": 2181562505, + "ram_offset_bits_for_conf_0": 0, + "ram_stop_bit_for_conf_0": 0, + "ram_data_for_conf_1": 67248651, + "ram_offset_bits_for_conf_1": 1, + "ram_stop_bit_for_conf_1": 0, + "ram_data_for_conf_2": 139266, + "ram_offset_bits_for_conf_2": 2, + "ram_stop_bit_for_conf_2": 0, + "ram_data_for_conf_3": 1, + "ram_offset_bits_for_conf_3": 4, + "ram_stop_bit_for_conf_3": 0, + "ram_data_for_conf_4": 1076887634, + "ram_offset_bits_for_conf_4": 45, + "ram_stop_bit_for_conf_4": 0, + "ram_data_for_conf_5": 3224371282, + "ram_offset_bits_for_conf_5": 45, + "ram_stop_bit_for_conf_5": 0, + "ram_data_for_conf_6": 262149, + "ram_offset_bits_for_conf_6": 14, + "ram_stop_bit_for_conf_6": 0, + "ram_data_for_conf_7": 0, + "ram_offset_bits_for_conf_7": 44, + "ram_stop_bit_for_conf_7": 1, + "ram_data_for_conf_8": 0, + "ram_offset_bits_for_conf_8": 0, + "ram_stop_bit_for_conf_8": 1, + "ram_data_for_conf_9": 0, + "ram_offset_bits_for_conf_9": 0, + "ram_stop_bit_for_conf_9": 1, + "ram_data_for_conf_10": 0, + "ram_offset_bits_for_conf_10": 0, + "ram_stop_bit_for_conf_10": 1, + "ram_data_for_conf_11": 0, + "ram_offset_bits_for_conf_11": 0, + "ram_stop_bit_for_conf_11": 1, + "ram_data_for_conf_12": 0, + "ram_offset_bits_for_conf_12": 0, + "ram_stop_bit_for_conf_12": 1, + "ram_data_for_conf_13": 0, + "ram_offset_bits_for_conf_13": 0, + "ram_stop_bit_for_conf_13": 1, + "ram_data_for_conf_14": 0, + "ram_offset_bits_for_conf_14": 0, + "ram_stop_bit_for_conf_14": 1, + "ram_data_for_conf_15": 0, + "ram_offset_bits_for_conf_15": 0, + "ram_stop_bit_for_conf_15": 1, + "ram_data_for_conf_16": 0, + "ram_offset_bits_for_conf_16": 0, + "ram_stop_bit_for_conf_16": 1, + "ram_data_for_conf_17": 0, + "ram_offset_bits_for_conf_17": 0, + "ram_stop_bit_for_conf_17": 1, + "ram_data_for_conf_18": 0, + "ram_offset_bits_for_conf_18": 0, + "ram_stop_bit_for_conf_18": 1, + "ram_data_for_conf_19": 0, + "ram_offset_bits_for_conf_19": 0, + "ram_stop_bit_for_conf_19": 1, + "ram_data_for_conf_20": 0, + "ram_offset_bits_for_conf_20": 0, + "ram_stop_bit_for_conf_20": 1, + "ram_data_for_conf_21": 0, + "ram_offset_bits_for_conf_21": 0, + "ram_stop_bit_for_conf_21": 1, + "ram_data_for_conf_22": 0, + "ram_offset_bits_for_conf_22": 0, + "ram_stop_bit_for_conf_22": 1, + "ram_data_for_conf_23": 0, + "ram_offset_bits_for_conf_23": 0, + "ram_stop_bit_for_conf_23": 1 + } + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/py25q64lb/flash_disc_param_xspi.json b/boards/ti/lp_em_cc35x1/config/flash/py25q64lb/flash_disc_param_xspi.json new file mode 100644 index 000000000000..90b40802d176 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/py25q64lb/flash_disc_param_xspi.json @@ -0,0 +1,485 @@ +{ + "xspi_header": { + "name": "xSPIWFF3", + "device": "CC3500", + "use_hardware": "PY25Q64LB", + "use_case": "Quadro", + "dqs_support": 0, + "flash_only": 1, + "flash_separate_reset": 0, + "ram_separate_reset": true, + "clock_frequency": 80, + "qospi_clock_divider": 1, + "flash_device_character_conf": 0, + "ram_device_character_conf": 0, + "header_advanced": 0, + "phy_mode_enable": 1, + "pipeline_mode_enable": 1, + "loopback_support": "No", + "qspi_ref_clock": 80, + "spi_clock_freq": 20, + "spi_clock_divider": 1, + "flash_device_size": 8, + "flash_bytes_per_block": 16, + "flash_bytes_per_page": 256, + "flash_number_of_address_bytes": 3, + "flash_dual_opcode": 0, + "flash_jedec_manufacturer_id": 0, + "flash_jedec_device_id": 0, + "flash_name": "PY25Q64LB", + "flash_page_size": 256, + "flash_sector_size": 4096, + "flash_cs_polarity": "ACTIVE_LOW", + "flash_sw_reset_type": "x1xxxx", + "ram_device_size": 8, + "ram_bytes_per_block": 16, + "ram_bytes_per_page": 256, + "ram_number_of_address_bytes": 3, + "ram_dual_opcode": 0, + "ram_jedec_manufacturer_id": 0, + "ram_jedec_device_id": 0, + "ram_name": "NO_PSRAM", + "ram_page_size": 256, + "ram_sector_size": 4096, + "ram_cs_polarity": "ACTIVE_LOW", + "ram_sw_reset_type": "x1xxxx", + "flash_write_operation_modes": "4S-4S-4S", + "flash_read_operation_modes": "4S-4S-4S", + "ram_write_operation_modes": "4S-4S-4S", + "ram_read_operation_modes": "4S-4S-4S", + "crc_enable": 0, + "enable_dtr": 0, + "enable_ahb_decoder": 0, + "enter_xip_mod_immediately": 0, + "enter_xip_mod_next_read": 0, + "ahb_address_remapping": 0, + "enable_dma": 0, + "select_decode": 0, + "legacy_ip_mode": 0, + "direct_access": 1 + }, + "xspi_pinmux": { + "xspi_clk_input": 44, + "xspi_clk_input_use_hw": 0, + "xspi_clk_input_mode": "Input", + "xspi_clk_input_pull": "None", + "xspi_clk_input_interrupt_trigger": "Low", + "xspi_clk_input_dont_conf": 0, + "xspi_clk_input_output_strength": "High", + "xspi_clk_input_initial_output_state": "High", + "xspi_clk": 24, + "xspi_clk_use_hw": "None", + "xspi_clk_mode": "Output", + "xspi_clk_pull": "None", + "xspi_clk_output_strength": "High", + "xspi_clk_initial_output_state": "High", + "xspi_clk_interrupt_trigger": "None", + "xspi_clk_dont_conf": 0, + "xspi_flash_cs": 20, + "xspi_flash_cs_use_hw": "None", + "xspi_flash_cs_mode": "Output", + "xspi_flash_cs_pull": "None", + "xspi_flash_cs_output_strength": "High", + "xspi_flash_cs_initial_output_state": "High", + "xspi_flash_cs_interrupt_trigger": "None", + "xspi_flash_cs_dont_conf": 0, + "xspi_data_0": 25, + "xspi_data_0_use_hw": "None", + "xspi_data_0_mode": "Input", + "xspi_data_0_pull": "None", + "xspi_data_0_output_strength": "High", + "xspi_data_0_initial_output_state": "High", + "xspi_data_0_interrupt_trigger": "Low", + "xspi_data_0_dont_conf": 0, + "xspi_data_1": 21, + "xspi_data_1_use_hw": "None", + "xspi_data_1_mode": "Input", + "xspi_data_1_pull": "None", + "xspi_data_1_output_strength": "High", + "xspi_data_1_initial_output_state": "High", + "xspi_data_1_interrupt_trigger": "Low", + "xspi_data_1_dont_conf": 0, + "xspi_data_2": 22, + "xspi_data_2_use_hw": "None", + "xspi_data_2_mode": "Input", + "xspi_data_2_pull": "None", + "xspi_data_2_output_strength": "High", + "xspi_data_2_initial_output_state": "High", + "xspi_data_2_interrupt_trigger": "Low", + "xspi_data_2_dont_conf": 0, + "xspi_data_3": 23, + "xspi_data_3_use_hw": "None", + "xspi_data_3_mode": "Input", + "xspi_data_3_pull": "None", + "xspi_data_3_output_strength": "High", + "xspi_data_3_initial_output_state": "High", + "xspi_data_3_interrupt_trigger": "Low", + "xspi_data_3_dont_conf": 0, + "xspi_data_4": 26, + "xspi_data_4_use_hw": "None", + "xspi_data_4_mode": "Input", + "xspi_data_4_pull": "None", + "xspi_data_4_output_strength": "High", + "xspi_data_4_initial_output_state": "High", + "xspi_data_4_interrupt_trigger": "None", + "xspi_data_4_dont_conf": 0, + "xspi_data_5": 27, + "xspi_data_5_use_hw": "None", + "xspi_data_5_mode": "Input", + "xspi_data_5_pull": "None", + "xspi_data_5_output_strength": "High", + "xspi_data_5_initial_output_state": "High", + "xspi_data_5_interrupt_trigger": "None", + "xspi_data_5_dont_conf": 0, + "xspi_data_6": 28, + "xspi_data_6_use_hw": "None", + "xspi_data_6_mode": "Input", + "xspi_data_6_pull": "None", + "xspi_data_6_output_strength": "High", + "xspi_data_6_initial_output_state": "High", + "xspi_data_6_interrupt_trigger": "None", + "xspi_data_6_dont_conf": 0, + "xspi_data_7": 29, + "xspi_data_7_use_hw": "None", + "xspi_data_7_mode": "Input", + "xspi_data_7_pull": "None", + "xspi_data_7_output_strength": "High", + "xspi_data_7_initial_output_state": "High", + "xspi_data_7_interrupt_trigger": "None", + "xspi_data_7_dont_conf": 0, + "xspi_reset_flash": 36, + "xspi_reset_flash_use_hw": "None", + "xspi_reset_flash_mode": "Output", + "xspi_reset_flash_pull": "None", + "xspi_reset_flash_output_strength": "High", + "xspi_reset_flash_initial_output_state": "High", + "xspi_reset_flash_interrupt_trigger": "None", + "xspi_reset_flash_dont_conf": 0, + "xspi_cs_ram": 3, + "xspi_cs_ram_use_hw": "None", + "xspi_cs_ram_mode": "Output", + "xspi_cs_ram_pull": "None", + "xspi_cs_ram_output_strength": "High", + "xspi_cs_ram_initial_output_state": "High", + "xspi_cs_ram_interrupt_trigger": "None", + "xspi_cs_ram_dont_conf": 0, + "xspi_dqs": 30, + "xspi_dqs_use_hw": "None", + "xspi_dqs_mode": "Input", + "xspi_dqs_pull": "None", + "xspi_dqs_output_strength": "High", + "xspi_dqs_initial_output_state": "High", + "xspi_dqs_interrupt_trigger": "None", + "xspi_dqs_dont_conf": 0, + "xspi_reset_ram": 2, + "xspi_reset_ram_use_hw": "None", + "xspi_reset_ram_mode": "Input", + "xspi_reset_ram_pull": "None", + "xspi_reset_ram_output_strength": "High", + "xspi_reset_ram_initial_output_state": "High", + "xspi_reset_ram_interrupt_trigger": "None", + "xspi_reset_ram_dont_conf": 0 + }, + "xspi_operations": { + "xspi_operations_clocks": { + "clock_phase": 0, + "clock_polarity": 0, + "spi_mode": "2'b00" + }, + "xspi_operations_chip_select": { + "csda": 2, + "csdads": 0, + "cseot": 4, + "cssot": 1 + }, + "xspi_operations_reset": { + "flash_jedec_reset": 0, + "ram_jedec_reset": 0, + "flash_treset": 20, + "ram_treset": 20 + }, + "xspi_phy_operations": { + "flash_rx_dll_bypass_bit": 0, + "flash_dll_tx_delay": 22, + "flash_dll_rx_delay": 34, + "ram_rx_dll_bypass_bit": 0, + "ram_dll_tx_delay": 22, + "ram_dll_rx_delay": 34 + }, + "xspi_read_operations": { + "flash_dummy_rd_cycles": 10, + "flash_read_opcode": 11, + "suppl_flash_read_opcode": 0, + "ram_dummy_rd_cycles": 10, + "ram_read_opcode": 11, + "suppl_ram_read_opcode": 0, + "flash_non_cont_read_enable": 0, + "flash_max_read_jobs": 256, + "ram_non_cont_read_enable": 0, + "ram_max_read_jobs": 256, + "rww_en": 0, + "device_size": 8, + "number_of_banks": 1, + "bank_size": 8, + "mode_bit_enable": 0 + }, + "xspi_write_operations": { + "flash_address_and_data": { + "flash_dummy_wr_cycles": 0 + }, + "flash_command": { + "flash_write_opcode": 2, + "suppl_flash_write_opcode": 0 + }, + "ram_address_and_data": { + "ram_dummy_wr_cycles": 0 + }, + "ram_command": { + "ram_write_opcode": 2, + "suppl_ram_write_opcode": 0 + }, + "write_to_buffer": { + "flash_write_to_buffer_support": 0, + "ram_write_to_buffer_support": 0 + }, + "non_continuous_write": { + "flash_non_cont_write_enable": 0, + "flash_max_write_jobs": 64, + "ram_non_cont_write_enable": 0, + "ram_max_write_jobs": 0 + }, + "flash_program_operation": { + "flash_min_program_size": "256 B", + "flash_program_opcode": 2, + "suppl_flash_program_opcode": 0, + "flash_maximum_program_time_limit": 1600 + }, + "flash_erase_operation": { + "flash_min_erase_size": "4 kB", + "flash_erase_opcode": 32, + "suppl_flash_erase_opcode": 0, + "flash_maximum_erase_time_limit": 4095 + }, + "flash_erase_conf": { + "flash_block_erase_opcode": 0, + "suppl_block_flash_erase_opcode": 0, + "flash_sector_erase_opcode": 0, + "suppl_sector_flash_erase_opcode": 0, + "flash_chip_erase_opcode": 0, + "suppl_chip_flash_erase_opcode": 0 + }, + "ram_program_operation": { + "ram_min_program_size": "256 B", + "ram_program_opcode": 2, + "suppl_ram_program_opcode": 0, + "ram_maximum_program_time_limit": 1600 + }, + "ram_erase_conf": { + "ram_block_erase_opcode": 0, + "suppl_block_ram_erase_opcode": 0, + "ram_sector_erase_opcode": 0, + "suppl_sector_ram_erase_opcode": 0, + "ram_chip_erase_opcode": 0, + "suppl_chip_ram_erase_opcode": 0 + }, + "flash_buffer_support": { + "flash_pre_write_sequence": 0, + "flash_post_write_sequence": 0, + "flash_write_protection_timer_en": 0, + "flash_write_buffer_timer_mode": 16, + "flash_write_buffer_timer_range": 0, + "flash_service_interrupt_criteria": 0 + }, + "ram_buffer_support": { + "ram_pre_write_sequence": 0, + "ram_post_write_sequence": 0, + "ram_write_protection_timer_en": 0, + "ram_write_buffer_timer_mode": 16, + "ram_write_buffer_timer_range": 0, + "ram_service_interrupt_criteria": 0 + }, + "flash_pre_write_conf": { + "flash_pre_write_job_done_grant_sel": 0, + "data_for_flash_pre_write_conf_0": 0, + "offset_bits_for_flash_pre_write_conf_0": 0, + "stop_bit_for_flash_pre_write_conf_0": 1, + "data_for_flash_pre_write_conf_1": 0, + "offset_bits_for_flash_pre_write_conf_1": 0 + }, + "flash_post_write_conf": { + "flash_post_write_job_done_grant_sel": 0, + "data_for_flash_post_write_conf_0": 0, + "offset_bits_for_flash_post_write_conf_0": 0, + "stop_bit_for_flash_post_write_conf_0": 1, + "data_for_flash_post_write_conf_1": 0, + "offset_bits_for_flash_post_write_conf_1": 0 + }, + "ram_pre_write_conf": { + "ram_pre_write_job_done_grant_sel": 0, + "data_for_ram_pre_write_conf_0": 0, + "offset_bits_for_ram_pre_write_conf_0": 0, + "stop_bit_for_ram_pre_write_conf_0": 1, + "data_for_ram_pre_write_conf_1": 0, + "offset_bits_for_ram_pre_write_conf_1": 0 + }, + "ram_post_write_conf": { + "ram_post_write_job_done_grant_sel": 0, + "data_for_ram_post_write_conf_0": 0, + "offset_bits_for_ram_post_write_conf_0": 0, + "stop_bit_for_ram_post_write_conf_0": 1, + "data_for_ram_post_write_conf_1": 0, + "offset_bits_for_ram_post_write_conf_1": 0 + } + }, + "xspi_capture_operations": { + "read_data_capture": { + "flash_delay_transmitted_data": 0, + "flash_loopback_clock": 0, + "flash_bypass_adapted_loopback": 1, + "flash_sample_edge_sel": 0, + "ram_delay_transmitted_data": 0, + "ram_loopback_clock": 0, + "ram_bypass_adapted_loopback": 1, + "ram_sample_edge_sel": 0 + }, + "delays": { + "flash_full_half_cycle_delay": 0, + "flash_dll_bypass_mode": 1, + "flash_phase_detect_sel": 0, + "flash_dll_lock_num": 0, + "flash_dll_start_point": 0, + "flash_loopback_clock": 0, + "ram_full_half_cycle_delay": 0, + "ram_dll_bypass_mode": 1, + "ram_phase_detect_sel": 0, + "ram_dll_lock_num": 0, + "ram_dll_start_point": 0, + "ram_loopback_clock": 0 + }, + "operation_modes": { + "flash_sfdp_support": 0, + "ram_sfdp_support": 0, + "flash_pm_support": 0, + "ram_pm_support": 0, + "flash_sfdp_opcode": 0, + "suppl_flash_sfdp_opcode": 0, + "ram_sfdp_opcode": 0, + "suppl_ram_sfdp_opcode": 0, + "flash_enter_dpd_opcode": 185, + "suppl_flash_enter_dpd_opcode": 0, + "flash_exit_dpd_opcode": 171, + "suppl_flash_exit_dpd_opcode": 0, + "ram_enter_dpd_opcode": 185, + "suppl_ram_enter_dpd_opcode": 0, + "ram_exit_dpd_opcode": 171, + "suppl_ram_exit_dpd_opcode": 0, + "flash_quad_enable_opcode": 56, + "suppl_flash_quad_enable_opcode": 0, + "flash_quad_disable_opcode": 255, + "suppl_flash_quad_disable_opcode": 0, + "flash_octal_enable_opcode": 0, + "suppl_flash_octal_enable_opcode": 0, + "flash_octal_disable_opcode": 0, + "suppl_flash_octal_disable_opcode": 0, + "ram_quad_enable_opcode": 56, + "suppl_ram_quad_enable_opcode": 0, + "ram_quad_disable_opcode": 255, + "suppl_ram_quad_disable_opcode": 0, + "ram_octal_enable_opcode": 0, + "suppl_ram_octal_enable_opcode": 0, + "ram_octal_disable_opcode": 0, + "suppl_ram_octal_disable_opcode": 0 + } + } + }, + "external_memory_reporting": { + "header": { + "flash_auto_polling_enable": 1, + "flash_wel_enable": 1, + "flash_write_protect_enable": 0, + "flash_alternate_polling_conf_enable": 0, + "ram_auto_polling_enable": 1, + "ram_wel_enable": 1, + "ram_write_protect_enable": 0, + "ram_alternate_polling_conf_enable": 0 + }, + "flash_auto_polling": { + "flash_polling_repetition_delay": 0, + "flash_polling_count": 4, + "flash_enable_polling_expiration": 0, + "flash_polling_polarity": 0, + "flash_polling_address_phase_enable": 0, + "flash_polling_bit_index": 0, + "flash_numbers_poll_cycles": 65535, + "flash_dummy_autopoll_cycles": 0 + }, + "ram_auto_polling": { + "ram_polling_repetition_delay": 0, + "ram_polling_count": 4, + "ram_enable_polling_expiration": 0, + "ram_polling_polarity": 0, + "ram_polling_address_phase_enable": 0, + "ram_polling_bit_index": 0, + "ram_numbers_poll_cycles": 65535, + "ram_dummy_autopoll_cycles": 0 + }, + "flash_polling_command": { + "flash_polling_opcode": 5, + "suppl_flash_polling_opcode": 0 + }, + "ram_polling_command": { + "ram_polling_opcode": 5, + "suppl_ram_polling_opcode": 0 + }, + "flash_alternate_polling": { + "flash_polling_resp_count": 1023, + "flash_polling_iterations": 1, + "flash_polling_enabled": 0, + "flash_polling_disabled": 0, + "flash_grant_sel": 0, + "flash_data_for_enable_poling_conf_0": 0, + "flash_offset_bits_for_enable_poling_conf_0": 0, + "flash_stop_bit_for_enable_poling_conf_0": 1, + "flash_data_for_enable_poling_conf_1": 0, + "flash_offset_bits_for_enable_poling_conf_1": 0, + "flash_stop_bit_for_enable_poling_conf_1": 1, + "flash_data_for_disable_poling_conf_0": 0, + "flash_offset_bits_for_disable_poling_conf_0": 0, + "flash_stop_bit_for_disable_poling_conf_0": 1, + "flash_data_for_disable_poling_conf_1": 0, + "flash_offset_bits_for_disable_poling_conf_1": 0, + "flash_stop_bit_for_disable_poling_conf_1": 1 + }, + "ram_alternate_polling": { + "ram_polling_resp_count": 1023, + "ram_polling_iterations": 1, + "ram_polling_enabled": 0, + "ram_polling_disabled": 0, + "ram_grant_sel": 0, + "ram_data_for_enable_poling_conf_0": 0, + "ram_offset_bits_for_enable_poling_conf_0": 0, + "ram_stop_bit_for_enable_poling_conf_0": 1, + "ram_data_for_enable_poling_conf_1": 0, + "ram_offset_bits_for_enable_poling_conf_1": 0, + "ram_stop_bit_for_enable_poling_conf_1": 1, + "ram_data_for_disable_poling_conf_0": 0, + "ram_offset_bits_for_disable_poling_conf_0": 0, + "ram_stop_bit_for_disable_poling_conf_0": 1, + "ram_data_for_disable_poling_conf_1": 0, + "ram_offset_bits_for_disable_poling_conf_1": 0, + "ram_stop_bit_for_disable_poling_conf_1": 1 + }, + "flash_wel_command": { + "flash_wel_opcode": 6, + "suppl_flash_wel_opcode": 0 + }, + "ram_wel_command": { + "ram_wel_opcode": 6, + "suppl_ram_wel_opcode": 0 + } + }, + "event": { + "host_nvic_irq": 0, + "core_10_mux_sel": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/w25q12pw/flash_disc_param_ext_mem.json b/boards/ti/lp_em_cc35x1/config/flash/w25q12pw/flash_disc_param_ext_mem.json new file mode 100644 index 000000000000..14d05d9aba5a --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/w25q12pw/flash_disc_param_ext_mem.json @@ -0,0 +1,99 @@ +{ + "vendor_primary_sbl": true, + "ti_wsoc_primary_container": true, + "ti_wsoc_bl2_primary_container": true, + "nvs_enable": true, + "vendor_alternate_image": true, + "vendor_sbl_alternate_image": true, + "ti_bl_alternate_image": true, + "ti_wsoc_alternate_image": true, + "ti_wsoc_bl2_alternate_image": true, + "region_0": { + "mem_region_0_start_phy_address": 2867200, + "mem_region_0_end_phy_address": 9822207, + "region0_boot": false, + "region0_main_code": true, + "region0_nvs": false, + "region0_wsoc_code": false, + "region0_alternate_code": false + }, + "region_1": { + "mem_region_1_start_phy_address": 0, + "mem_region_1_end_phy_address": 2867199, + "region1_boot": true, + "region1_main_code": false, + "region1_nvs": true, + "region1_wsoc_code": true, + "region1_alternate_code": false + }, + "region_2": { + "mem_region_2_start_phy_address": 9822208, + "mem_region_2_end_phy_address": 16777215, + "region2_boot": false, + "region2_main_code": false, + "region2_nvs": false, + "region2_wsoc_code": false, + "region2_alternate_code": true + }, + "region_3": { + "mem_region_3_start_phy_address": 0, + "mem_region_3_end_phy_address": 0, + "region3_boot": false, + "region3_main_code": false, + "region3_nvs": false, + "region3_wsoc_code": false, + "region3_alternate_code": false + }, + "boot_region_conf": { + "boot_region_size": 0, + "boot_region_flash_disco_param_start_address": 0, + "boot_region_primary_ti_bl_start_phy_address": 12284, + "boot_region_primary_ti_bl_magic": 0, + "boot_region_primary_ti_bl_major": 0, + "boot_region_primary_ti_bl_minor": 0, + "boot_region_sec_ti_bl_start_phy_address": 430076, + "boot_region_sec_ti_bl_magic": 0, + "boot_region_sec_ti_bl_major": 0, + "boot_region_sec_ti_bl_minor": 0 + }, + "main_code_region_conf": { + "main_code_region_vendor_image_start_phy_address": 2871292, + "main_code_region_vendor_image_magic": 0, + "main_code_region_vendor_image_major": 0, + "main_code_region_vendor_image_minor": 0, + "main_code_region_sbl_start_phy_address": 0, + "main_code_region_sbl_magic": 0, + "main_code_region_sbl_major": 0, + "main_code_region_sbl_minor": 0 + }, + "alt_code_region_conf": { + "alt_code_region_vendor_image_start_phy_address": 9826300, + "alt_code_region_vendor_image_magic": 0, + "alt_code_region_vendor_image_major": 0, + "alt_code_region_vendor_image_minor": 0, + "alt_code_region_sbl_start_phy_address": 0, + "alt_code_region_sbl_magic": 0, + "alt_code_region_sbl_major": 0, + "alt_code_region_sbl_minor": 0 + }, + "nvs_code_region_conf": { + "nvs_start_phy_address": 1777664, + "nvs_region_size": 1089536, + "nvs_region_primary_wsoc_start_phy_address": 847868, + "nvs_region_primary_wsoc_magic": 0, + "nvs_region_primary_wsoc_major": 0, + "nvs_region_primary_wsoc_minor": 0, + "nvs_region_sec_wsoc_start_phy_address": 1314812, + "nvs_region_sec_wsoc_magic": 0, + "nvs_region_sec_wsoc_major": 0, + "nvs_region_sec_wsoc_minor": 0, + "nvs_region_primary_wsoc_bl2_start_phy_address": 0, + "nvs_region_primary_wsoc_bl2_magic": 0, + "nvs_region_primary_wsoc_bl2_major": 0, + "nvs_region_primary_wsoc_bl2_minor": 0, + "nvs_region_sec_wsoc_bl2_start_phy_address": 0, + "nvs_region_sec_wsoc_bl2_magic": 0, + "nvs_region_sec_wsoc_bl2_major": 0, + "nvs_region_sec_wsoc_bl2_minor": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/w25q12pw/flash_disc_param_otfde.json b/boards/ti/lp_em_cc35x1/config/flash/w25q12pw/flash_disc_param_otfde.json new file mode 100644 index 000000000000..0a4af30e7551 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/w25q12pw/flash_disc_param_otfde.json @@ -0,0 +1,286 @@ +{ + "otfde_header": { + "name": "OTFDEWFF3", + "flash_only": true, + "ip_protection": false, + "regions_lock": false, + "regions_number": 4, + "flash_enabled": true + }, + "bl_conf": { + "host_boot_done_lock": true, + "host_peripherals_lock": true, + "icache_conf_lock": true, + "m33_mem_part_lock": true, + "memss_firewall_lock": true, + "dma_channel_owner_lock": true, + "otfde_region_lock": true, + "core_events_lock": true + }, + "otfde_general": { + "parameters": { + "mem_otfde_initial_delay": 10, + "otfde_global_watchdog_timer": 5 + }, + "events": { + "reset_evt_mask": false, + "reset_evt_suspend": false, + "sft_reset_evt_mask": false, + "sft_reset_evt_suspend": false, + "bypass_mode_evt_mask": false, + "bypass_mode_evt_suspend": false, + "debug_mode_evt_mask": false, + "debug_mode_evt_suspend": false, + "general_evt_mask": false, + "general_evt_suspend": false, + "xspi_data_path_evt_mask": false, + "xspi_data_path_evt_suspend": false, + "xspi_cnfg_path_evt_mask": false, + "xspi_cnfg_path_evt_suspend": false, + "xspi_service_interrupt_evt_mask": false, + "xspi_service_interrupt_evt_suspend": false, + "trans_device_disabled_evt_mask": false, + "trans_device_disabled_evt_suspend": false, + "trans_region_disabled_evt_mask": false, + "trans_region_disabled_evt_suspend": false, + "trans_region_params_conf_evt_mask": false, + "trans_region_params_conf_evt_suspend": false, + "trans_multiple_regions_mapped_evt_mask": false, + "trans_multiple_regions_mapped_evt_suspend": false, + "trans_address_not_32_bit_evt_mask": false, + "trans_address_not_32_bit_evt_suspend": false, + "trans_size_not_32_bit_evt_mask": false, + "trans_size_not_32_bit_evt_suspend": false, + "trans_burst_not_32_bit_evt_mask": false, + "trans_burst_not_32_bit_evt_suspend": false, + "region_read_write_def_evt_mask": false, + "region_read_write_def_evt_suspend": false, + "suspend_while_disabled_evt_mask": false, + "suspend_while_disabled_evt_suspend": false + } + }, + "regions_settings": { + "region_parameters_lock": { + "REGION_0_PARAMS_0": true, + "REGION_0_PARAMS_1": true, + "REGION_0_PARAMS_2": true, + "REGION_1_PARAMS_0": false, + "REGION_1_PARAMS_1": false, + "REGION_1_PARAMS_2": false, + "REGION_2_PARAMS_0": true, + "REGION_2_PARAMS_1": true, + "REGION_2_PARAMS_2": true, + "REGION_3_PARAMS_0": false, + "REGION_3_PARAMS_1": false, + "REGION_3_PARAMS_2": false + }, + "region_0_protection": { + "mem_region_0_enabled": true, + "mem_region_0_device_id": 0, + "mem_region_0_spi_write_enable": true, + "mem_region_0_spi_read_enable": true, + "mem_region_0_physical_offset": 700, + "mem_region_0_security_id_msb": 0, + "mem_region_0_start_address": 81920, + "mem_region_0_end_address": 83617, + "mem_region_0_security_id_lsb": 0, + "mem_otfde_region_0_write_lock_en": false, + "mem_otfde_region_0_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_1_protection": { + "mem_region_1_enabled": true, + "mem_region_1_device_id": 0, + "mem_region_1_spi_write_enable": true, + "mem_region_1_spi_read_enable": true, + "mem_region_1_physical_offset": 0, + "mem_region_1_security_id_msb": 0, + "mem_region_1_start_address": 655360, + "mem_region_1_end_address": 656059, + "mem_region_1_security_id_lsb": 0, + "mem_otfde_region_1_write_lock_en": false, + "mem_otfde_region_1_enc_dec_bypass": "Bypass" + }, + "region_2_protection": { + "mem_region_2_enabled": true, + "mem_region_2_device_id": 0, + "mem_region_2_spi_write_enable": true, + "mem_region_2_spi_read_enable": true, + "mem_region_2_physical_offset": 2398, + "mem_region_2_security_id_msb": 0, + "mem_region_2_start_address": 671744, + "mem_region_2_end_address": 673441, + "mem_region_2_security_id_lsb": 0, + "mem_otfde_region_2_write_lock_en": false, + "mem_otfde_region_2_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_3_protection": { + "mem_region_3_enabled": false, + "mem_region_3_device_id": 1, + "mem_region_3_spi_write_enable": true, + "mem_region_3_spi_read_enable": true, + "mem_region_3_physical_offset": 0, + "mem_region_3_security_id_msb": 0, + "mem_region_3_start_address": 1, + "mem_region_3_end_address": 0, + "mem_region_3_security_id_lsb": 0, + "mem_otfde_region_3_write_lock_en": false, + "mem_otfde_region_3_enc_dec_bypass": "Bypass" + } + }, + "devices": { + "header": { + "flash_device_switch_conf": 1, + "ram_device_switch_conf": 1 + }, + "flash_switch": { + "flash_grant_sel": 0, + "flash_data_for_conf_0": 2181562505, + "flash_offset_bits_for_conf_0": 0, + "flash_stop_bit_for_conf_0": 0, + "flash_data_for_conf_1": 100803083, + "flash_offset_bits_for_conf_1": 1, + "flash_stop_bit_for_conf_1": 0, + "flash_data_for_conf_2": 139266, + "flash_offset_bits_for_conf_2": 2, + "flash_stop_bit_for_conf_2": 0, + "flash_data_for_conf_3": 1, + "flash_offset_bits_for_conf_3": 4, + "flash_stop_bit_for_conf_3": 0, + "flash_data_for_conf_4": 1076887634, + "flash_offset_bits_for_conf_4": 45, + "flash_stop_bit_for_conf_4": 0, + "flash_data_for_conf_5": 3224371282, + "flash_offset_bits_for_conf_5": 45, + "flash_stop_bit_for_conf_5": 0, + "flash_data_for_conf_6": 262149, + "flash_offset_bits_for_conf_6": 14, + "flash_stop_bit_for_conf_6": 0, + "flash_data_for_conf_7": 0, + "flash_offset_bits_for_conf_7": 44, + "flash_stop_bit_for_conf_7": 1, + "flash_data_for_conf_8": 0, + "flash_offset_bits_for_conf_8": 0, + "flash_stop_bit_for_conf_8": 1, + "flash_data_for_conf_9": 0, + "flash_offset_bits_for_conf_9": 0, + "flash_stop_bit_for_conf_9": 1, + "flash_data_for_conf_10": 0, + "flash_offset_bits_for_conf_10": 0, + "flash_stop_bit_for_conf_10": 1, + "flash_data_for_conf_11": 0, + "flash_offset_bits_for_conf_11": 0, + "flash_stop_bit_for_conf_11": 1, + "flash_data_for_conf_12": 0, + "flash_offset_bits_for_conf_12": 0, + "flash_stop_bit_for_conf_12": 1, + "flash_data_for_conf_13": 0, + "flash_offset_bits_for_conf_13": 0, + "flash_stop_bit_for_conf_13": 1, + "flash_data_for_conf_14": 0, + "flash_offset_bits_for_conf_14": 0, + "flash_stop_bit_for_conf_14": 1, + "flash_data_for_conf_15": 0, + "flash_offset_bits_for_conf_15": 0, + "flash_stop_bit_for_conf_15": 1, + "flash_data_for_conf_16": 0, + "flash_offset_bits_for_conf_16": 0, + "flash_stop_bit_for_conf_16": 1, + "flash_data_for_conf_17": 0, + "flash_offset_bits_for_conf_17": 0, + "flash_stop_bit_for_conf_17": 1, + "flash_data_for_conf_18": 0, + "flash_offset_bits_for_conf_18": 0, + "flash_stop_bit_for_conf_18": 1, + "flash_data_for_conf_19": 0, + "flash_offset_bits_for_conf_19": 0, + "flash_stop_bit_for_conf_19": 1, + "flash_data_for_conf_20": 0, + "flash_offset_bits_for_conf_20": 0, + "flash_stop_bit_for_conf_20": 1, + "flash_data_for_conf_21": 0, + "flash_offset_bits_for_conf_21": 0, + "flash_stop_bit_for_conf_21": 1, + "flash_data_for_conf_22": 0, + "flash_offset_bits_for_conf_22": 0, + "flash_stop_bit_for_conf_22": 1, + "flash_data_for_conf_23": 0, + "flash_offset_bits_for_conf_23": 0, + "flash_stop_bit_for_conf_23": 1 + }, + "ram_switch": { + "ram_grant_sel": 0, + "ram_data_for_conf_0": 2181562505, + "ram_offset_bits_for_conf_0": 0, + "ram_stop_bit_for_conf_0": 0, + "ram_data_for_conf_1": 100803083, + "ram_offset_bits_for_conf_1": 1, + "ram_stop_bit_for_conf_1": 0, + "ram_data_for_conf_2": 139266, + "ram_offset_bits_for_conf_2": 2, + "ram_stop_bit_for_conf_2": 0, + "ram_data_for_conf_3": 1, + "ram_offset_bits_for_conf_3": 4, + "ram_stop_bit_for_conf_3": 0, + "ram_data_for_conf_4": 1076887634, + "ram_offset_bits_for_conf_4": 45, + "ram_stop_bit_for_conf_4": 0, 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"ram_data_for_conf_15": 0, + "ram_offset_bits_for_conf_15": 0, + "ram_stop_bit_for_conf_15": 1, + "ram_data_for_conf_16": 0, + "ram_offset_bits_for_conf_16": 0, + "ram_stop_bit_for_conf_16": 1, + "ram_data_for_conf_17": 0, + "ram_offset_bits_for_conf_17": 0, + "ram_stop_bit_for_conf_17": 1, + "ram_data_for_conf_18": 0, + "ram_offset_bits_for_conf_18": 0, + "ram_stop_bit_for_conf_18": 1, + "ram_data_for_conf_19": 0, + "ram_offset_bits_for_conf_19": 0, + "ram_stop_bit_for_conf_19": 1, + "ram_data_for_conf_20": 0, + "ram_offset_bits_for_conf_20": 0, + "ram_stop_bit_for_conf_20": 1, + "ram_data_for_conf_21": 0, + "ram_offset_bits_for_conf_21": 0, + "ram_stop_bit_for_conf_21": 1, + "ram_data_for_conf_22": 0, + "ram_offset_bits_for_conf_22": 0, + "ram_stop_bit_for_conf_22": 1, + "ram_data_for_conf_23": 0, + "ram_offset_bits_for_conf_23": 0, + "ram_stop_bit_for_conf_23": 1 + } + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/w25q12pw/flash_disc_param_xspi.json b/boards/ti/lp_em_cc35x1/config/flash/w25q12pw/flash_disc_param_xspi.json new file mode 100644 index 000000000000..61763985c259 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/w25q12pw/flash_disc_param_xspi.json @@ -0,0 +1,485 @@ +{ + "xspi_header": { + "name": "xSPIWFF3", + "device": "CC3500", + "use_hardware": "W25Q12PW", + "use_case": "Quadro", + "dqs_support": 0, + "flash_only": 1, + "flash_separate_reset": 0, + "ram_separate_reset": true, + "clock_frequency": 80, + "qospi_clock_divider": 1, + "flash_device_character_conf": 0, + "ram_device_character_conf": 0, + "header_advanced": 0, + "phy_mode_enable": 1, + "pipeline_mode_enable": 1, + "loopback_support": "No", + "qspi_ref_clock": 80, + "spi_clock_freq": 20, + "spi_clock_divider": 1, + "flash_device_size": 16, + "flash_bytes_per_block": 65535, + "flash_bytes_per_page": 256, + "flash_number_of_address_bytes": 3, + "flash_dual_opcode": 0, + "flash_jedec_manufacturer_id": 0, + "flash_jedec_device_id": 0, + "flash_name": "W25Q12PW", + "flash_page_size": 256, + "flash_sector_size": 4096, + "flash_cs_polarity": "ACTIVE_LOW", + "flash_sw_reset_type": "x1xxxx", + "ram_device_size": 16, + "ram_bytes_per_block": 65535, + "ram_bytes_per_page": 256, + "ram_number_of_address_bytes": 3, + "ram_dual_opcode": 0, + "ram_jedec_manufacturer_id": 0, + "ram_jedec_device_id": 0, + "ram_name": "NO_PSRAM", + "ram_page_size": 256, + "ram_sector_size": 4096, + "ram_cs_polarity": "ACTIVE_LOW", + "ram_sw_reset_type": "x1xxxx", + "flash_write_operation_modes": "4S-4S-4S", + "flash_read_operation_modes": "4S-4S-4S", + "ram_write_operation_modes": "4S-4S-4S", + "ram_read_operation_modes": "4S-4S-4S", + "crc_enable": 0, + "enable_dtr": 0, + "enable_ahb_decoder": 0, + "enter_xip_mod_immediately": 0, + "enter_xip_mod_next_read": 0, + "ahb_address_remapping": 0, + "enable_dma": 0, + "select_decode": 0, + "legacy_ip_mode": 0, + "direct_access": 1 + }, + "xspi_pinmux": { + "xspi_clk_input": 44, + "xspi_clk_input_use_hw": 0, + "xspi_clk_input_mode": "Input", + "xspi_clk_input_pull": "None", + "xspi_clk_input_interrupt_trigger": "Low", + "xspi_clk_input_dont_conf": 0, + "xspi_clk_input_output_strength": "High", + "xspi_clk_input_initial_output_state": "High", + "xspi_clk": 24, + "xspi_clk_use_hw": "None", + "xspi_clk_mode": "Output", + "xspi_clk_pull": "None", + "xspi_clk_output_strength": "High", + "xspi_clk_initial_output_state": "High", + "xspi_clk_interrupt_trigger": "None", + "xspi_clk_dont_conf": 0, + "xspi_flash_cs": 20, + "xspi_flash_cs_use_hw": "None", + "xspi_flash_cs_mode": "Output", + "xspi_flash_cs_pull": "None", + "xspi_flash_cs_output_strength": "High", + "xspi_flash_cs_initial_output_state": "High", + "xspi_flash_cs_interrupt_trigger": "None", + "xspi_flash_cs_dont_conf": 0, + "xspi_data_0": 25, + "xspi_data_0_use_hw": "None", + "xspi_data_0_mode": "Input", + "xspi_data_0_pull": "None", + "xspi_data_0_output_strength": "High", + "xspi_data_0_initial_output_state": "High", + "xspi_data_0_interrupt_trigger": "Low", + "xspi_data_0_dont_conf": 0, + "xspi_data_1": 21, + "xspi_data_1_use_hw": "None", + "xspi_data_1_mode": "Input", + "xspi_data_1_pull": "None", + "xspi_data_1_output_strength": "High", + "xspi_data_1_initial_output_state": "High", + "xspi_data_1_interrupt_trigger": "Low", + "xspi_data_1_dont_conf": 0, + "xspi_data_2": 22, + "xspi_data_2_use_hw": "None", + "xspi_data_2_mode": "Input", + "xspi_data_2_pull": "None", + "xspi_data_2_output_strength": "High", + "xspi_data_2_initial_output_state": "High", + "xspi_data_2_interrupt_trigger": "Low", + "xspi_data_2_dont_conf": 0, + "xspi_data_3": 23, + "xspi_data_3_use_hw": "None", + "xspi_data_3_mode": "Input", + "xspi_data_3_pull": "None", + "xspi_data_3_output_strength": "High", + "xspi_data_3_initial_output_state": "High", + "xspi_data_3_interrupt_trigger": "Low", + "xspi_data_3_dont_conf": 0, + "xspi_data_4": 26, + "xspi_data_4_use_hw": "None", + "xspi_data_4_mode": "Input", + "xspi_data_4_pull": "None", + "xspi_data_4_output_strength": "High", + "xspi_data_4_initial_output_state": "High", + "xspi_data_4_interrupt_trigger": "None", + "xspi_data_4_dont_conf": 0, + "xspi_data_5": 27, + "xspi_data_5_use_hw": "None", + "xspi_data_5_mode": "Input", + "xspi_data_5_pull": "None", + "xspi_data_5_output_strength": "High", + "xspi_data_5_initial_output_state": "High", + "xspi_data_5_interrupt_trigger": "None", + "xspi_data_5_dont_conf": 0, + "xspi_data_6": 28, + "xspi_data_6_use_hw": "None", + "xspi_data_6_mode": "Input", + "xspi_data_6_pull": "None", + "xspi_data_6_output_strength": "High", + "xspi_data_6_initial_output_state": "High", + "xspi_data_6_interrupt_trigger": "None", + "xspi_data_6_dont_conf": 0, + "xspi_data_7": 29, + "xspi_data_7_use_hw": "None", + "xspi_data_7_mode": "Input", + "xspi_data_7_pull": "None", + "xspi_data_7_output_strength": "High", + "xspi_data_7_initial_output_state": "High", + "xspi_data_7_interrupt_trigger": "None", + "xspi_data_7_dont_conf": 0, + "xspi_reset_flash": 36, + "xspi_reset_flash_use_hw": "None", + "xspi_reset_flash_mode": "Output", + "xspi_reset_flash_pull": "None", + "xspi_reset_flash_output_strength": "High", + "xspi_reset_flash_initial_output_state": "High", + "xspi_reset_flash_interrupt_trigger": "None", + "xspi_reset_flash_dont_conf": 0, + "xspi_cs_ram": 3, + "xspi_cs_ram_use_hw": "None", + "xspi_cs_ram_mode": "Output", + "xspi_cs_ram_pull": "None", + "xspi_cs_ram_output_strength": "High", + "xspi_cs_ram_initial_output_state": "High", + "xspi_cs_ram_interrupt_trigger": "None", + "xspi_cs_ram_dont_conf": 0, + "xspi_dqs": 30, + "xspi_dqs_use_hw": "None", + "xspi_dqs_mode": "Input", + "xspi_dqs_pull": "None", + "xspi_dqs_output_strength": "High", + "xspi_dqs_initial_output_state": "High", + "xspi_dqs_interrupt_trigger": "None", + "xspi_dqs_dont_conf": 0, + "xspi_reset_ram": 2, + "xspi_reset_ram_use_hw": "None", + "xspi_reset_ram_mode": "Input", + "xspi_reset_ram_pull": "None", + "xspi_reset_ram_output_strength": "High", + "xspi_reset_ram_initial_output_state": "High", + "xspi_reset_ram_interrupt_trigger": "None", + "xspi_reset_ram_dont_conf": 0 + }, + "xspi_operations": { + "xspi_operations_clocks": { + "clock_phase": 0, + "clock_polarity": 0, + "spi_mode": "2'b00" + }, + "xspi_operations_chip_select": { + "csda": 2, + "csdads": 0, + "cseot": 4, + "cssot": 1 + }, + "xspi_operations_reset": { + "flash_jedec_reset": 0, + "ram_jedec_reset": 0, + "flash_treset": 20, + "ram_treset": 20 + }, + "xspi_phy_operations": { + "flash_rx_dll_bypass_bit": 0, + "flash_dll_tx_delay": 42, + "flash_dll_rx_delay": 62, + "ram_rx_dll_bypass_bit": 0, + "ram_dll_tx_delay": 42, + "ram_dll_rx_delay": 62 + }, + "xspi_read_operations": { + "flash_dummy_rd_cycles": 6, + "flash_read_opcode": 11, + "suppl_flash_read_opcode": 0, + "ram_dummy_rd_cycles": 6, + "ram_read_opcode": 11, + "suppl_ram_read_opcode": 0, + "flash_non_cont_read_enable": 0, + "flash_max_read_jobs": 256, + "ram_non_cont_read_enable": 0, + "ram_max_read_jobs": 256, + "rww_en": 0, + "device_size": 16, + "number_of_banks": 1, + "bank_size": 16, + "mode_bit_enable": 0 + }, + "xspi_write_operations": { + "flash_address_and_data": { + "flash_dummy_wr_cycles": 0 + }, + "flash_command": { + "flash_write_opcode": 2, + "suppl_flash_write_opcode": 0 + }, + "ram_address_and_data": { + "ram_dummy_wr_cycles": 0 + }, + "ram_command": { + "ram_write_opcode": 2, + "suppl_ram_write_opcode": 0 + }, + "write_to_buffer": { + "flash_write_to_buffer_support": 0, + "ram_write_to_buffer_support": 0 + }, + "non_continuous_write": { + "flash_non_cont_write_enable": 0, + "flash_max_write_jobs": 64, + "ram_non_cont_write_enable": 0, + "ram_max_write_jobs": 0 + }, + "flash_program_operation": { + "flash_min_program_size": "256 B", + "flash_program_opcode": 2, + "suppl_flash_program_opcode": 0, + "flash_maximum_program_time_limit": 1600 + }, + "flash_erase_operation": { + "flash_min_erase_size": "4 kB", + "flash_erase_opcode": 32, + "suppl_flash_erase_opcode": 0, + "flash_maximum_erase_time_limit": 4095 + }, + "flash_erase_conf": { + "flash_block_erase_opcode": 0, + "suppl_block_flash_erase_opcode": 0, + "flash_sector_erase_opcode": 0, + "suppl_sector_flash_erase_opcode": 0, + "flash_chip_erase_opcode": 0, + "suppl_chip_flash_erase_opcode": 0 + }, + "ram_program_operation": { + "ram_min_program_size": "256 B", + "ram_program_opcode": 2, + "suppl_ram_program_opcode": 0, + "ram_maximum_program_time_limit": 1600 + }, + "ram_erase_conf": { + "ram_block_erase_opcode": 0, + "suppl_block_ram_erase_opcode": 0, + "ram_sector_erase_opcode": 0, + "suppl_sector_ram_erase_opcode": 0, + "ram_chip_erase_opcode": 0, + "suppl_chip_ram_erase_opcode": 0 + }, + "flash_buffer_support": { + "flash_pre_write_sequence": 0, + "flash_post_write_sequence": 0, + "flash_write_protection_timer_en": 0, + "flash_write_buffer_timer_mode": 16, + "flash_write_buffer_timer_range": 0, + "flash_service_interrupt_criteria": 0 + }, + "ram_buffer_support": { + "ram_pre_write_sequence": 0, + "ram_post_write_sequence": 0, + "ram_write_protection_timer_en": 0, + "ram_write_buffer_timer_mode": 16, + "ram_write_buffer_timer_range": 0, + "ram_service_interrupt_criteria": 0 + }, + "flash_pre_write_conf": { + "flash_pre_write_job_done_grant_sel": 0, + "data_for_flash_pre_write_conf_0": 0, + "offset_bits_for_flash_pre_write_conf_0": 0, + "stop_bit_for_flash_pre_write_conf_0": 1, + "data_for_flash_pre_write_conf_1": 0, + "offset_bits_for_flash_pre_write_conf_1": 0 + }, + "flash_post_write_conf": { + "flash_post_write_job_done_grant_sel": 0, + "data_for_flash_post_write_conf_0": 0, + "offset_bits_for_flash_post_write_conf_0": 0, + "stop_bit_for_flash_post_write_conf_0": 1, + "data_for_flash_post_write_conf_1": 0, + "offset_bits_for_flash_post_write_conf_1": 0 + }, + "ram_pre_write_conf": { + "ram_pre_write_job_done_grant_sel": 0, + "data_for_ram_pre_write_conf_0": 0, + "offset_bits_for_ram_pre_write_conf_0": 0, + "stop_bit_for_ram_pre_write_conf_0": 1, + "data_for_ram_pre_write_conf_1": 0, + "offset_bits_for_ram_pre_write_conf_1": 0 + }, + "ram_post_write_conf": { + "ram_post_write_job_done_grant_sel": 0, + "data_for_ram_post_write_conf_0": 0, + "offset_bits_for_ram_post_write_conf_0": 0, + "stop_bit_for_ram_post_write_conf_0": 1, + "data_for_ram_post_write_conf_1": 0, + "offset_bits_for_ram_post_write_conf_1": 0 + } + }, + "xspi_capture_operations": { + "read_data_capture": { + "flash_delay_transmitted_data": 0, + "flash_loopback_clock": 0, + "flash_bypass_adapted_loopback": 1, + "flash_sample_edge_sel": 0, + "ram_delay_transmitted_data": 0, + "ram_loopback_clock": 0, + "ram_bypass_adapted_loopback": 1, + "ram_sample_edge_sel": 0 + }, + "delays": { + "flash_full_half_cycle_delay": 0, + "flash_dll_bypass_mode": 1, + "flash_phase_detect_sel": 0, + "flash_dll_lock_num": 0, + "flash_dll_start_point": 0, + "flash_loopback_clock": 0, + "ram_full_half_cycle_delay": 0, + "ram_dll_bypass_mode": 1, + "ram_phase_detect_sel": 0, + "ram_dll_lock_num": 0, + "ram_dll_start_point": 0, + "ram_loopback_clock": 0 + }, + "operation_modes": { + "flash_sfdp_support": 0, + "ram_sfdp_support": 0, + "flash_pm_support": 0, + "ram_pm_support": 0, + "flash_sfdp_opcode": 0, + "suppl_flash_sfdp_opcode": 0, + "ram_sfdp_opcode": 0, + "suppl_ram_sfdp_opcode": 0, + "flash_enter_dpd_opcode": 185, + "suppl_flash_enter_dpd_opcode": 0, + "flash_exit_dpd_opcode": 171, + "suppl_flash_exit_dpd_opcode": 0, + "ram_enter_dpd_opcode": 185, + "suppl_ram_enter_dpd_opcode": 0, + "ram_exit_dpd_opcode": 171, + "suppl_ram_exit_dpd_opcode": 0, + "flash_quad_enable_opcode": 56, + "suppl_flash_quad_enable_opcode": 0, + "flash_quad_disable_opcode": 255, + "suppl_flash_quad_disable_opcode": 0, + "flash_octal_enable_opcode": 0, + "suppl_flash_octal_enable_opcode": 0, + "flash_octal_disable_opcode": 0, + "suppl_flash_octal_disable_opcode": 0, + "ram_quad_enable_opcode": 56, + "suppl_ram_quad_enable_opcode": 0, + "ram_quad_disable_opcode": 255, + "suppl_ram_quad_disable_opcode": 0, + "ram_octal_enable_opcode": 0, + "suppl_ram_octal_enable_opcode": 0, + "ram_octal_disable_opcode": 0, + "suppl_ram_octal_disable_opcode": 0 + } + } + }, + "external_memory_reporting": { + "header": { + "flash_auto_polling_enable": 1, + "flash_wel_enable": 1, + "flash_write_protect_enable": 0, + "flash_alternate_polling_conf_enable": 0, + "ram_auto_polling_enable": 1, + "ram_wel_enable": 1, + "ram_write_protect_enable": 0, + "ram_alternate_polling_conf_enable": 0 + }, + "flash_auto_polling": { + "flash_polling_repetition_delay": 0, + "flash_polling_count": 4, + "flash_enable_polling_expiration": 0, + "flash_polling_polarity": 0, + "flash_polling_address_phase_enable": 0, + "flash_polling_bit_index": 0, + "flash_numbers_poll_cycles": 65535, + "flash_dummy_autopoll_cycles": 0 + }, + "ram_auto_polling": { + "ram_polling_repetition_delay": 0, + "ram_polling_count": 4, + "ram_enable_polling_expiration": 0, + "ram_polling_polarity": 0, + "ram_polling_address_phase_enable": 0, + "ram_polling_bit_index": 0, + "ram_numbers_poll_cycles": 65535, + "ram_dummy_autopoll_cycles": 0 + }, + "flash_polling_command": { + "flash_polling_opcode": 5, + "suppl_flash_polling_opcode": 0 + }, + "ram_polling_command": { + "ram_polling_opcode": 5, + "suppl_ram_polling_opcode": 0 + }, + "flash_alternate_polling": { + "flash_polling_resp_count": 1023, + "flash_polling_iterations": 1, + "flash_polling_enabled": 0, + "flash_polling_disabled": 0, + "flash_grant_sel": 0, + "flash_data_for_enable_poling_conf_0": 0, + "flash_offset_bits_for_enable_poling_conf_0": 0, + "flash_stop_bit_for_enable_poling_conf_0": 1, + "flash_data_for_enable_poling_conf_1": 0, + "flash_offset_bits_for_enable_poling_conf_1": 0, + "flash_stop_bit_for_enable_poling_conf_1": 1, + "flash_data_for_disable_poling_conf_0": 0, + "flash_offset_bits_for_disable_poling_conf_0": 0, + "flash_stop_bit_for_disable_poling_conf_0": 1, + "flash_data_for_disable_poling_conf_1": 0, + "flash_offset_bits_for_disable_poling_conf_1": 0, + "flash_stop_bit_for_disable_poling_conf_1": 1 + }, + "ram_alternate_polling": { + "ram_polling_resp_count": 1023, + "ram_polling_iterations": 1, + "ram_polling_enabled": 0, + "ram_polling_disabled": 0, + "ram_grant_sel": 0, + "ram_data_for_enable_poling_conf_0": 0, + "ram_offset_bits_for_enable_poling_conf_0": 0, + "ram_stop_bit_for_enable_poling_conf_0": 1, + "ram_data_for_enable_poling_conf_1": 0, + "ram_offset_bits_for_enable_poling_conf_1": 0, + "ram_stop_bit_for_enable_poling_conf_1": 1, + "ram_data_for_disable_poling_conf_0": 0, + "ram_offset_bits_for_disable_poling_conf_0": 0, + "ram_stop_bit_for_disable_poling_conf_0": 1, + "ram_data_for_disable_poling_conf_1": 0, + "ram_offset_bits_for_disable_poling_conf_1": 0, + "ram_stop_bit_for_disable_poling_conf_1": 1 + }, + "flash_wel_command": { + "flash_wel_opcode": 6, + "suppl_flash_wel_opcode": 0 + }, + "ram_wel_command": { + "ram_wel_opcode": 6, + "suppl_ram_wel_opcode": 0 + } + }, + "event": { + "host_nvic_irq": 0, + "core_10_mux_sel": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/w25q32jw/flash_disc_param_ext_mem.json b/boards/ti/lp_em_cc35x1/config/flash/w25q32jw/flash_disc_param_ext_mem.json new file mode 100644 index 000000000000..321810768be1 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/w25q32jw/flash_disc_param_ext_mem.json @@ -0,0 +1,99 @@ +{ + "vendor_primary_sbl": true, + "ti_wsoc_primary_container": true, + "ti_wsoc_bl2_primary_container": true, + "nvs_enable": true, + "vendor_alternate_image": true, + "vendor_sbl_alternate_image": true, + "ti_bl_alternate_image": true, + "ti_wsoc_alternate_image": true, + "ti_wsoc_bl2_alternate_image": true, + "region_0": { + "mem_region_0_start_phy_address": 1069056, + "mem_region_0_end_phy_address": 4194303, + "region0_boot": false, + "region0_main_code": true, + "region0_nvs": false, + "region0_wsoc_code": false, + "region0_alternate_code": false + }, + "region_1": { + "mem_region_1_start_phy_address": 0, + "mem_region_1_end_phy_address": 1069055, + "region1_boot": true, + "region1_main_code": false, + "region1_nvs": true, + "region1_wsoc_code": true, + "region1_alternate_code": false + }, + "region_2": { + "mem_region_2_start_phy_address": 0, + "mem_region_2_end_phy_address": 0, + "region2_boot": false, + "region2_main_code": false, + "region2_nvs": false, + "region2_wsoc_code": false, + "region2_alternate_code": true + }, + "region_3": { + "mem_region_3_start_phy_address": 0, + "mem_region_3_end_phy_address": 0, + "region3_boot": false, + "region3_main_code": false, + "region3_nvs": false, + "region3_wsoc_code": false, + "region3_alternate_code": false + }, + "boot_region_conf": { + "boot_region_size": 0, + "boot_region_flash_disco_param_start_address": 0, + "boot_region_primary_ti_bl_start_phy_address": 12284, + "boot_region_primary_ti_bl_magic": 0, + "boot_region_primary_ti_bl_major": 0, + "boot_region_primary_ti_bl_minor": 0, + "boot_region_sec_ti_bl_start_phy_address": 430076, + "boot_region_sec_ti_bl_magic": 0, + "boot_region_sec_ti_bl_major": 0, + "boot_region_sec_ti_bl_minor": 0 + }, + "main_code_region_conf": { + "main_code_region_vendor_image_start_phy_address": 1073148, + "main_code_region_vendor_image_magic": 0, + "main_code_region_vendor_image_major": 0, + "main_code_region_vendor_image_minor": 0, + "main_code_region_sbl_start_phy_address": 0, + "main_code_region_sbl_magic": 0, + "main_code_region_sbl_major": 0, + "main_code_region_sbl_minor": 0 + }, + "alt_code_region_conf": { + "alt_code_region_vendor_image_start_phy_address": 4194304, + "alt_code_region_vendor_image_magic": 0, + "alt_code_region_vendor_image_major": 0, + "alt_code_region_vendor_image_minor": 0, + "alt_code_region_sbl_start_phy_address": 0, + "alt_code_region_sbl_magic": 0, + "alt_code_region_sbl_major": 0, + "alt_code_region_sbl_minor": 0 + }, + "nvs_code_region_conf": { + "nvs_start_phy_address": 892928, + "nvs_region_size": 176128, + "nvs_region_primary_wsoc_start_phy_address": 430076, + "nvs_region_primary_wsoc_magic": 0, + "nvs_region_primary_wsoc_major": 0, + "nvs_region_primary_wsoc_minor": 0, + "nvs_region_sec_wsoc_start_phy_address": 897020, + "nvs_region_sec_wsoc_magic": 0, + "nvs_region_sec_wsoc_major": 0, + "nvs_region_sec_wsoc_minor": 0, + "nvs_region_primary_wsoc_bl2_start_phy_address": 0, + "nvs_region_primary_wsoc_bl2_magic": 0, + "nvs_region_primary_wsoc_bl2_major": 0, + "nvs_region_primary_wsoc_bl2_minor": 0, + "nvs_region_sec_wsoc_bl2_start_phy_address": 0, + "nvs_region_sec_wsoc_bl2_magic": 0, + "nvs_region_sec_wsoc_bl2_major": 0, + "nvs_region_sec_wsoc_bl2_minor": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/w25q32jw/flash_disc_param_otfde.json b/boards/ti/lp_em_cc35x1/config/flash/w25q32jw/flash_disc_param_otfde.json new file mode 100644 index 000000000000..efd3377fcf69 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/w25q32jw/flash_disc_param_otfde.json @@ -0,0 +1,286 @@ +{ + "otfde_header": { + "name": "OTFDEWFF3", + "flash_only": true, + "ip_protection": false, + "regions_lock": false, + "regions_number": 4, + "flash_enabled": true + }, + "bl_conf": { + "host_boot_done_lock": true, + "host_peripherals_lock": true, + "icache_conf_lock": true, + "m33_mem_part_lock": true, + "memss_firewall_lock": true, + "dma_channel_owner_lock": true, + "otfde_region_lock": true, + "core_events_lock": true + }, + "otfde_general": { + "parameters": { + "mem_otfde_initial_delay": 10, + "otfde_global_watchdog_timer": 5 + }, + "events": { + "reset_evt_mask": false, + "reset_evt_suspend": false, + "sft_reset_evt_mask": false, + "sft_reset_evt_suspend": false, + "bypass_mode_evt_mask": false, + "bypass_mode_evt_suspend": false, + "debug_mode_evt_mask": false, + "debug_mode_evt_suspend": false, + "general_evt_mask": false, + "general_evt_suspend": false, + "xspi_data_path_evt_mask": false, + "xspi_data_path_evt_suspend": false, + "xspi_cnfg_path_evt_mask": false, + "xspi_cnfg_path_evt_suspend": false, + "xspi_service_interrupt_evt_mask": false, + "xspi_service_interrupt_evt_suspend": false, + "trans_device_disabled_evt_mask": false, + "trans_device_disabled_evt_suspend": false, + "trans_region_disabled_evt_mask": false, + "trans_region_disabled_evt_suspend": false, + "trans_region_params_conf_evt_mask": false, + "trans_region_params_conf_evt_suspend": false, + "trans_multiple_regions_mapped_evt_mask": false, + "trans_multiple_regions_mapped_evt_suspend": false, + "trans_address_not_32_bit_evt_mask": false, + "trans_address_not_32_bit_evt_suspend": false, + "trans_size_not_32_bit_evt_mask": false, + "trans_size_not_32_bit_evt_suspend": false, + "trans_burst_not_32_bit_evt_mask": false, + "trans_burst_not_32_bit_evt_suspend": false, + "region_read_write_def_evt_mask": false, + "region_read_write_def_evt_suspend": false, + "suspend_while_disabled_evt_mask": false, + "suspend_while_disabled_evt_suspend": false + } + }, + "regions_settings": { + "region_parameters_lock": { + "REGION_0_PARAMS_0": true, + "REGION_0_PARAMS_1": true, + "REGION_0_PARAMS_2": true, + "REGION_1_PARAMS_0": false, + "REGION_1_PARAMS_1": false, + "REGION_1_PARAMS_2": false, + "REGION_2_PARAMS_0": true, + "REGION_2_PARAMS_1": true, + "REGION_2_PARAMS_2": true, + "REGION_3_PARAMS_0": false, + "REGION_3_PARAMS_1": false, + "REGION_3_PARAMS_2": false + }, + "region_0_protection": { + "mem_region_0_enabled": true, + "mem_region_0_device_id": 0, + "mem_region_0_spi_write_enable": true, + "mem_region_0_spi_read_enable": true, + "mem_region_0_physical_offset": 261, + "mem_region_0_security_id_msb": 0, + "mem_region_0_start_address": 81920, + "mem_region_0_end_address": 82682, + "mem_region_0_security_id_lsb": 0, + "mem_otfde_region_0_write_lock_en": false, + "mem_otfde_region_0_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_1_protection": { + "mem_region_1_enabled": true, + "mem_region_1_device_id": 0, + "mem_region_1_spi_write_enable": true, + "mem_region_1_spi_read_enable": true, + "mem_region_1_physical_offset": 0, + "mem_region_1_security_id_msb": 0, + "mem_region_1_start_address": 655360, + "mem_region_1_end_address": 655620, + "mem_region_1_security_id_lsb": 0, + "mem_otfde_region_1_write_lock_en": false, + "mem_otfde_region_1_enc_dec_bypass": "Bypass" + }, + "region_2_protection": { + "mem_region_2_enabled": false, + "mem_region_2_device_id": 0, + "mem_region_2_spi_write_enable": true, + "mem_region_2_spi_read_enable": true, + "mem_region_2_physical_offset": 0, + "mem_region_2_security_id_msb": 0, + "mem_region_2_start_address": 1, + "mem_region_2_end_address": 0, + "mem_region_2_security_id_lsb": 0, + "mem_otfde_region_2_write_lock_en": false, + "mem_otfde_region_2_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_3_protection": { + "mem_region_3_enabled": false, + "mem_region_3_device_id": 1, + "mem_region_3_spi_write_enable": true, + "mem_region_3_spi_read_enable": true, + "mem_region_3_physical_offset": 0, + "mem_region_3_security_id_msb": 0, + "mem_region_3_start_address": 1, + "mem_region_3_end_address": 0, + "mem_region_3_security_id_lsb": 0, + "mem_otfde_region_3_write_lock_en": false, + "mem_otfde_region_3_enc_dec_bypass": "Bypass" + } + }, + "devices": { + "header": { + "flash_device_switch_conf": 1, + "ram_device_switch_conf": 1 + }, + "flash_switch": { + "flash_grant_sel": 0, + "flash_data_for_conf_0": 2181562505, + "flash_offset_bits_for_conf_0": 0, + "flash_stop_bit_for_conf_0": 0, + "flash_data_for_conf_1": 134357515, + "flash_offset_bits_for_conf_1": 1, + "flash_stop_bit_for_conf_1": 0, + "flash_data_for_conf_2": 139266, + "flash_offset_bits_for_conf_2": 2, + "flash_stop_bit_for_conf_2": 0, + "flash_data_for_conf_3": 1, + "flash_offset_bits_for_conf_3": 4, + "flash_stop_bit_for_conf_3": 0, + "flash_data_for_conf_4": 1077739587, + "flash_offset_bits_for_conf_4": 45, + "flash_stop_bit_for_conf_4": 0, + "flash_data_for_conf_5": 3225223235, + "flash_offset_bits_for_conf_5": 45, + "flash_stop_bit_for_conf_5": 0, + "flash_data_for_conf_6": 262149, + "flash_offset_bits_for_conf_6": 14, + "flash_stop_bit_for_conf_6": 0, + "flash_data_for_conf_7": 0, + "flash_offset_bits_for_conf_7": 44, + "flash_stop_bit_for_conf_7": 1, + "flash_data_for_conf_8": 0, + "flash_offset_bits_for_conf_8": 0, + "flash_stop_bit_for_conf_8": 1, + "flash_data_for_conf_9": 0, + "flash_offset_bits_for_conf_9": 0, + "flash_stop_bit_for_conf_9": 1, + "flash_data_for_conf_10": 0, + "flash_offset_bits_for_conf_10": 0, + "flash_stop_bit_for_conf_10": 1, + "flash_data_for_conf_11": 0, + "flash_offset_bits_for_conf_11": 0, + "flash_stop_bit_for_conf_11": 1, + "flash_data_for_conf_12": 0, + "flash_offset_bits_for_conf_12": 0, + "flash_stop_bit_for_conf_12": 1, + "flash_data_for_conf_13": 0, + "flash_offset_bits_for_conf_13": 0, + "flash_stop_bit_for_conf_13": 1, + "flash_data_for_conf_14": 0, + "flash_offset_bits_for_conf_14": 0, + "flash_stop_bit_for_conf_14": 1, + "flash_data_for_conf_15": 0, + "flash_offset_bits_for_conf_15": 0, + "flash_stop_bit_for_conf_15": 1, + "flash_data_for_conf_16": 0, + "flash_offset_bits_for_conf_16": 0, + "flash_stop_bit_for_conf_16": 1, + "flash_data_for_conf_17": 0, + "flash_offset_bits_for_conf_17": 0, + "flash_stop_bit_for_conf_17": 1, + "flash_data_for_conf_18": 0, + "flash_offset_bits_for_conf_18": 0, + "flash_stop_bit_for_conf_18": 1, + "flash_data_for_conf_19": 0, + "flash_offset_bits_for_conf_19": 0, + "flash_stop_bit_for_conf_19": 1, + "flash_data_for_conf_20": 0, + "flash_offset_bits_for_conf_20": 0, + "flash_stop_bit_for_conf_20": 1, + "flash_data_for_conf_21": 0, + "flash_offset_bits_for_conf_21": 0, + "flash_stop_bit_for_conf_21": 1, + "flash_data_for_conf_22": 0, + "flash_offset_bits_for_conf_22": 0, + "flash_stop_bit_for_conf_22": 1, + "flash_data_for_conf_23": 0, + "flash_offset_bits_for_conf_23": 0, + "flash_stop_bit_for_conf_23": 1 + }, + "ram_switch": { + "ram_grant_sel": 0, + "ram_data_for_conf_0": 2181563529, + "ram_offset_bits_for_conf_0": 0, + "ram_stop_bit_for_conf_0": 0, + "ram_data_for_conf_1": 100803307, + "ram_offset_bits_for_conf_1": 1, + "ram_stop_bit_for_conf_1": 0, + "ram_data_for_conf_2": 139320, + "ram_offset_bits_for_conf_2": 2, + "ram_stop_bit_for_conf_2": 0, + "ram_data_for_conf_3": 3089693184, + "ram_offset_bits_for_conf_3": 56, + "ram_stop_bit_for_conf_3": 0, + "ram_data_for_conf_4": 1, + "ram_offset_bits_for_conf_4": 4, + "ram_stop_bit_for_conf_4": 0, + "ram_data_for_conf_5": 1076494399, + "ram_offset_bits_for_conf_5": 45, + "ram_stop_bit_for_conf_5": 0, + "ram_data_for_conf_6": 3223978047, + "ram_offset_bits_for_conf_6": 45, + "ram_stop_bit_for_conf_6": 0, + "ram_data_for_conf_7": 278533, + "ram_offset_bits_for_conf_7": 14, + "ram_stop_bit_for_conf_7": 0, + "ram_data_for_conf_8": 0, + "ram_offset_bits_for_conf_8": 44, + "ram_stop_bit_for_conf_8": 1, + "ram_data_for_conf_9": 0, + "ram_offset_bits_for_conf_9": 0, + "ram_stop_bit_for_conf_9": 1, + "ram_data_for_conf_10": 0, + "ram_offset_bits_for_conf_10": 0, + "ram_stop_bit_for_conf_10": 1, + "ram_data_for_conf_11": 0, + "ram_offset_bits_for_conf_11": 0, + "ram_stop_bit_for_conf_11": 1, + "ram_data_for_conf_12": 0, + "ram_offset_bits_for_conf_12": 0, + "ram_stop_bit_for_conf_12": 1, + "ram_data_for_conf_13": 0, + "ram_offset_bits_for_conf_13": 0, + "ram_stop_bit_for_conf_13": 1, + "ram_data_for_conf_14": 0, + "ram_offset_bits_for_conf_14": 0, + "ram_stop_bit_for_conf_14": 1, + "ram_data_for_conf_15": 0, + "ram_offset_bits_for_conf_15": 0, + "ram_stop_bit_for_conf_15": 1, + "ram_data_for_conf_16": 0, + "ram_offset_bits_for_conf_16": 0, + "ram_stop_bit_for_conf_16": 1, + "ram_data_for_conf_17": 0, + "ram_offset_bits_for_conf_17": 0, + "ram_stop_bit_for_conf_17": 1, + "ram_data_for_conf_18": 0, + "ram_offset_bits_for_conf_18": 0, + "ram_stop_bit_for_conf_18": 1, + "ram_data_for_conf_19": 0, + "ram_offset_bits_for_conf_19": 0, + "ram_stop_bit_for_conf_19": 1, + "ram_data_for_conf_20": 0, + "ram_offset_bits_for_conf_20": 0, + "ram_stop_bit_for_conf_20": 1, + "ram_data_for_conf_21": 0, + "ram_offset_bits_for_conf_21": 0, + "ram_stop_bit_for_conf_21": 1, + "ram_data_for_conf_22": 0, + "ram_offset_bits_for_conf_22": 0, + "ram_stop_bit_for_conf_22": 1, + "ram_data_for_conf_23": 0, + "ram_offset_bits_for_conf_23": 0, + "ram_stop_bit_for_conf_23": 1 + } + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/w25q32jw/flash_disc_param_xspi.json b/boards/ti/lp_em_cc35x1/config/flash/w25q32jw/flash_disc_param_xspi.json new file mode 100644 index 000000000000..28d58bb7fba2 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/w25q32jw/flash_disc_param_xspi.json @@ -0,0 +1,485 @@ +{ + "xspi_header": { + "name": "xSPIWFF3", + "device": "CC3500", + "use_hardware": "W25Q32JW", + "use_case": "Quadro", + "dqs_support": 0, + "flash_only": 1, + "flash_separate_reset": 0, + "ram_separate_reset": true, + "clock_frequency": 80, + "qospi_clock_divider": 1, + "flash_device_character_conf": 0, + "ram_device_character_conf": 0, + "header_advanced": 0, + "phy_mode_enable": 1, + "pipeline_mode_enable": 1, + "loopback_support": "No", + "qspi_ref_clock": 80, + "spi_clock_freq": 20, + "spi_clock_divider": 1, + "flash_device_size": 4, + "flash_bytes_per_block": 16, + "flash_bytes_per_page": 256, + "flash_number_of_address_bytes": 3, + "flash_dual_opcode": 0, + "flash_jedec_manufacturer_id": 0, + "flash_jedec_device_id": 0, + "flash_name": "W25Q32JW", + "flash_page_size": 256, + "flash_sector_size": 4096, + "flash_cs_polarity": "ACTIVE_LOW", + "flash_sw_reset_type": "x1xxxx", + "ram_device_size": 4, + "ram_bytes_per_block": 16, + "ram_bytes_per_page": 256, + "ram_number_of_address_bytes": 3, + "ram_dual_opcode": 0, + "ram_jedec_manufacturer_id": 0, + "ram_jedec_device_id": 0, + "ram_name": "NO_PSRAM", + "ram_page_size": 256, + "ram_sector_size": 4096, + "ram_cs_polarity": "ACTIVE_LOW", + "ram_sw_reset_type": "x1xxxx", + "flash_write_operation_modes": "4S-4S-4S", + "flash_read_operation_modes": "4S-4S-4S", + "ram_write_operation_modes": "4S-4S-4S", + "ram_read_operation_modes": "4S-4S-4S", + "crc_enable": 0, + "enable_dtr": 0, + "enable_ahb_decoder": 0, + "enter_xip_mod_immediately": 0, + "enter_xip_mod_next_read": 0, + "ahb_address_remapping": 0, + "enable_dma": 0, + "select_decode": 0, + "legacy_ip_mode": 0, + "direct_access": 1 + }, + "xspi_pinmux": { + "xspi_clk_input": 44, + "xspi_clk_input_use_hw": 0, + "xspi_clk_input_mode": "Input", + "xspi_clk_input_pull": "None", + "xspi_clk_input_interrupt_trigger": "Low", + "xspi_clk_input_dont_conf": 0, + "xspi_clk_input_output_strength": "High", + "xspi_clk_input_initial_output_state": "High", + "xspi_clk": 24, + "xspi_clk_use_hw": "None", + "xspi_clk_mode": "Output", + "xspi_clk_pull": "None", + "xspi_clk_output_strength": "High", + "xspi_clk_initial_output_state": "High", + "xspi_clk_interrupt_trigger": "None", + "xspi_clk_dont_conf": 0, + "xspi_flash_cs": 20, + "xspi_flash_cs_use_hw": "None", + "xspi_flash_cs_mode": "Output", + "xspi_flash_cs_pull": "None", + "xspi_flash_cs_output_strength": "High", + "xspi_flash_cs_initial_output_state": "High", + "xspi_flash_cs_interrupt_trigger": "None", + "xspi_flash_cs_dont_conf": 0, + "xspi_data_0": 25, + "xspi_data_0_use_hw": "None", + "xspi_data_0_mode": "Input", + "xspi_data_0_pull": "None", + "xspi_data_0_output_strength": "High", + "xspi_data_0_initial_output_state": "High", + "xspi_data_0_interrupt_trigger": "Low", + "xspi_data_0_dont_conf": 0, + "xspi_data_1": 21, + "xspi_data_1_use_hw": "None", + "xspi_data_1_mode": "Input", + "xspi_data_1_pull": "None", + "xspi_data_1_output_strength": "High", + "xspi_data_1_initial_output_state": "High", + "xspi_data_1_interrupt_trigger": "Low", + "xspi_data_1_dont_conf": 0, + "xspi_data_2": 22, + "xspi_data_2_use_hw": "None", + "xspi_data_2_mode": "Input", + "xspi_data_2_pull": "None", + "xspi_data_2_output_strength": "High", + "xspi_data_2_initial_output_state": "High", + "xspi_data_2_interrupt_trigger": "Low", + "xspi_data_2_dont_conf": 0, + "xspi_data_3": 23, + "xspi_data_3_use_hw": "None", + "xspi_data_3_mode": "Input", + "xspi_data_3_pull": "None", + "xspi_data_3_output_strength": "High", + "xspi_data_3_initial_output_state": "High", + "xspi_data_3_interrupt_trigger": "Low", + "xspi_data_3_dont_conf": 0, + "xspi_data_4": 26, + "xspi_data_4_use_hw": "None", + "xspi_data_4_mode": "Input", + "xspi_data_4_pull": "None", + "xspi_data_4_output_strength": "High", + "xspi_data_4_initial_output_state": "High", + "xspi_data_4_interrupt_trigger": "None", + "xspi_data_4_dont_conf": 0, + "xspi_data_5": 27, + "xspi_data_5_use_hw": "None", + "xspi_data_5_mode": "Input", + "xspi_data_5_pull": "None", + "xspi_data_5_output_strength": "High", + "xspi_data_5_initial_output_state": "High", + "xspi_data_5_interrupt_trigger": "None", + "xspi_data_5_dont_conf": 0, + "xspi_data_6": 28, + "xspi_data_6_use_hw": "None", + "xspi_data_6_mode": "Input", + "xspi_data_6_pull": "None", + "xspi_data_6_output_strength": "High", + "xspi_data_6_initial_output_state": "High", + "xspi_data_6_interrupt_trigger": "None", + "xspi_data_6_dont_conf": 0, + "xspi_data_7": 29, + "xspi_data_7_use_hw": "None", + "xspi_data_7_mode": "Input", + "xspi_data_7_pull": "None", + "xspi_data_7_output_strength": "High", + "xspi_data_7_initial_output_state": "High", + "xspi_data_7_interrupt_trigger": "None", + "xspi_data_7_dont_conf": 0, + "xspi_reset_flash": 36, + "xspi_reset_flash_use_hw": "None", + "xspi_reset_flash_mode": "Output", + "xspi_reset_flash_pull": "None", + "xspi_reset_flash_output_strength": "High", + "xspi_reset_flash_initial_output_state": "High", + "xspi_reset_flash_interrupt_trigger": "None", + "xspi_reset_flash_dont_conf": 0, + "xspi_cs_ram": 3, + "xspi_cs_ram_use_hw": "None", + "xspi_cs_ram_mode": "Output", + "xspi_cs_ram_pull": "None", + "xspi_cs_ram_output_strength": "High", + "xspi_cs_ram_initial_output_state": "High", + "xspi_cs_ram_interrupt_trigger": "None", + "xspi_cs_ram_dont_conf": 0, + "xspi_dqs": 30, + "xspi_dqs_use_hw": "None", + "xspi_dqs_mode": "Input", + "xspi_dqs_pull": "None", + "xspi_dqs_output_strength": "High", + "xspi_dqs_initial_output_state": "High", + "xspi_dqs_interrupt_trigger": "None", + "xspi_dqs_dont_conf": 0, + "xspi_reset_ram": 2, + "xspi_reset_ram_use_hw": "None", + "xspi_reset_ram_mode": "Input", + "xspi_reset_ram_pull": "None", + "xspi_reset_ram_output_strength": "High", + "xspi_reset_ram_initial_output_state": "High", + "xspi_reset_ram_interrupt_trigger": "None", + "xspi_reset_ram_dont_conf": 0 + }, + "xspi_operations": { + "xspi_operations_clocks": { + "clock_phase": 0, + "clock_polarity": 0, + "spi_mode": "2'b00" + }, + "xspi_operations_chip_select": { + "csda": 2, + "csdads": 0, + "cseot": 4, + "cssot": 1 + }, + "xspi_operations_reset": { + "flash_jedec_reset": 0, + "ram_jedec_reset": 0, + "flash_treset": 20, + "ram_treset": 20 + }, + "xspi_phy_operations": { + "flash_rx_dll_bypass_bit": 0, + "flash_dll_tx_delay": 61, + "flash_dll_rx_delay": 65, + "ram_rx_dll_bypass_bit": 0, + "ram_dll_tx_delay": 61, + "ram_dll_rx_delay": 65 + }, + "xspi_read_operations": { + "flash_dummy_rd_cycles": 8, + "flash_read_opcode": 11, + "suppl_flash_read_opcode": 0, + "ram_dummy_rd_cycles": 8, + "ram_read_opcode": 11, + "suppl_ram_read_opcode": 0, + "flash_non_cont_read_enable": 0, + "flash_max_read_jobs": 256, + "ram_non_cont_read_enable": 0, + "ram_max_read_jobs": 256, + "rww_en": 0, + "device_size": 4, + "number_of_banks": 1, + "bank_size": 4, + "mode_bit_enable": 0 + }, + "xspi_write_operations": { + "flash_address_and_data": { + "flash_dummy_wr_cycles": 0 + }, + "flash_command": { + "flash_write_opcode": 2, + "suppl_flash_write_opcode": 0 + }, + "ram_address_and_data": { + "ram_dummy_wr_cycles": 0 + }, + "ram_command": { + "ram_write_opcode": 2, + "suppl_ram_write_opcode": 0 + }, + "write_to_buffer": { + "flash_write_to_buffer_support": 0, + "ram_write_to_buffer_support": 0 + }, + "non_continuous_write": { + "flash_non_cont_write_enable": 0, + "flash_max_write_jobs": 64, + "ram_non_cont_write_enable": 0, + "ram_max_write_jobs": 0 + }, + "flash_program_operation": { + "flash_min_program_size": "256 B", + "flash_program_opcode": 2, + "suppl_flash_program_opcode": 0, + "flash_maximum_program_time_limit": 1600 + }, + "flash_erase_operation": { + "flash_min_erase_size": "4 kB", + "flash_erase_opcode": 32, + "suppl_flash_erase_opcode": 0, + "flash_maximum_erase_time_limit": 4095 + }, + "flash_erase_conf": { + "flash_block_erase_opcode": 0, + "suppl_block_flash_erase_opcode": 0, + "flash_sector_erase_opcode": 0, + "suppl_sector_flash_erase_opcode": 0, + "flash_chip_erase_opcode": 0, + "suppl_chip_flash_erase_opcode": 0 + }, + "ram_program_operation": { + "ram_min_program_size": "256 B", + "ram_program_opcode": 2, + "suppl_ram_program_opcode": 0, + "ram_maximum_program_time_limit": 1600 + }, + "ram_erase_conf": { + "ram_block_erase_opcode": 0, + "suppl_block_ram_erase_opcode": 0, + "ram_sector_erase_opcode": 0, + "suppl_sector_ram_erase_opcode": 0, + "ram_chip_erase_opcode": 0, + "suppl_chip_ram_erase_opcode": 0 + }, + "flash_buffer_support": { + "flash_pre_write_sequence": 0, + "flash_post_write_sequence": 0, + "flash_write_protection_timer_en": 0, + "flash_write_buffer_timer_mode": 16, + "flash_write_buffer_timer_range": 0, + "flash_service_interrupt_criteria": 0 + }, + "ram_buffer_support": { + "ram_pre_write_sequence": 0, + "ram_post_write_sequence": 0, + "ram_write_protection_timer_en": 0, + "ram_write_buffer_timer_mode": 16, + "ram_write_buffer_timer_range": 0, + "ram_service_interrupt_criteria": 0 + }, + "flash_pre_write_conf": { + "flash_pre_write_job_done_grant_sel": 0, + "data_for_flash_pre_write_conf_0": 0, + "offset_bits_for_flash_pre_write_conf_0": 0, + "stop_bit_for_flash_pre_write_conf_0": 1, + "data_for_flash_pre_write_conf_1": 0, + "offset_bits_for_flash_pre_write_conf_1": 0 + }, + "flash_post_write_conf": { + "flash_post_write_job_done_grant_sel": 0, + "data_for_flash_post_write_conf_0": 0, + "offset_bits_for_flash_post_write_conf_0": 0, + "stop_bit_for_flash_post_write_conf_0": 1, + "data_for_flash_post_write_conf_1": 0, + "offset_bits_for_flash_post_write_conf_1": 0 + }, + "ram_pre_write_conf": { + "ram_pre_write_job_done_grant_sel": 0, + "data_for_ram_pre_write_conf_0": 0, + "offset_bits_for_ram_pre_write_conf_0": 0, + "stop_bit_for_ram_pre_write_conf_0": 1, + "data_for_ram_pre_write_conf_1": 0, + "offset_bits_for_ram_pre_write_conf_1": 0 + }, + "ram_post_write_conf": { + "ram_post_write_job_done_grant_sel": 0, + "data_for_ram_post_write_conf_0": 0, + "offset_bits_for_ram_post_write_conf_0": 0, + "stop_bit_for_ram_post_write_conf_0": 1, + "data_for_ram_post_write_conf_1": 0, + "offset_bits_for_ram_post_write_conf_1": 0 + } + }, + "xspi_capture_operations": { + "read_data_capture": { + "flash_delay_transmitted_data": 0, + "flash_loopback_clock": 0, + "flash_bypass_adapted_loopback": 1, + "flash_sample_edge_sel": 0, + "ram_delay_transmitted_data": 0, + "ram_loopback_clock": 0, + "ram_bypass_adapted_loopback": 1, + "ram_sample_edge_sel": 0 + }, + "delays": { + "flash_full_half_cycle_delay": 0, + "flash_dll_bypass_mode": 1, + "flash_phase_detect_sel": 0, + "flash_dll_lock_num": 0, + "flash_dll_start_point": 0, + "flash_loopback_clock": 0, + "ram_full_half_cycle_delay": 0, + "ram_dll_bypass_mode": 1, + "ram_phase_detect_sel": 0, + "ram_dll_lock_num": 0, + "ram_dll_start_point": 0, + "ram_loopback_clock": 0 + }, + "operation_modes": { + "flash_sfdp_support": 0, + "ram_sfdp_support": 0, + "flash_pm_support": 0, + "ram_pm_support": 0, + "flash_sfdp_opcode": 0, + "suppl_flash_sfdp_opcode": 0, + "ram_sfdp_opcode": 0, + "suppl_ram_sfdp_opcode": 0, + "flash_enter_dpd_opcode": 185, + "suppl_flash_enter_dpd_opcode": 0, + "flash_exit_dpd_opcode": 171, + "suppl_flash_exit_dpd_opcode": 0, + "ram_enter_dpd_opcode": 185, + "suppl_ram_enter_dpd_opcode": 0, + "ram_exit_dpd_opcode": 171, + "suppl_ram_exit_dpd_opcode": 0, + "flash_quad_enable_opcode": 56, + "suppl_flash_quad_enable_opcode": 0, + "flash_quad_disable_opcode": 255, + "suppl_flash_quad_disable_opcode": 0, + "flash_octal_enable_opcode": 0, + "suppl_flash_octal_enable_opcode": 0, + "flash_octal_disable_opcode": 0, + "suppl_flash_octal_disable_opcode": 0, + "ram_quad_enable_opcode": 56, + "suppl_ram_quad_enable_opcode": 0, + "ram_quad_disable_opcode": 255, + "suppl_ram_quad_disable_opcode": 0, + "ram_octal_enable_opcode": 0, + "suppl_ram_octal_enable_opcode": 0, + "ram_octal_disable_opcode": 0, + "suppl_ram_octal_disable_opcode": 0 + } + } + }, + "external_memory_reporting": { + "header": { + "flash_auto_polling_enable": 1, + "flash_wel_enable": 1, + "flash_write_protect_enable": 0, + "flash_alternate_polling_conf_enable": 0, + "ram_auto_polling_enable": 1, + "ram_wel_enable": 1, + "ram_write_protect_enable": 0, + "ram_alternate_polling_conf_enable": 0 + }, + "flash_auto_polling": { + "flash_polling_repetition_delay": 0, + "flash_polling_count": 4, + "flash_enable_polling_expiration": 0, + "flash_polling_polarity": 0, + "flash_polling_address_phase_enable": 0, + "flash_polling_bit_index": 0, + "flash_numbers_poll_cycles": 65535, + "flash_dummy_autopoll_cycles": 0 + }, + "ram_auto_polling": { + "ram_polling_repetition_delay": 0, + "ram_polling_count": 4, + "ram_enable_polling_expiration": 0, + "ram_polling_polarity": 0, + "ram_polling_address_phase_enable": 0, + "ram_polling_bit_index": 0, + "ram_numbers_poll_cycles": 65535, + "ram_dummy_autopoll_cycles": 0 + }, + "flash_polling_command": { + "flash_polling_opcode": 5, + "suppl_flash_polling_opcode": 0 + }, + "ram_polling_command": { + "ram_polling_opcode": 5, + "suppl_ram_polling_opcode": 0 + }, + "flash_alternate_polling": { + "flash_polling_resp_count": 1023, + "flash_polling_iterations": 1, + "flash_polling_enabled": 0, + "flash_polling_disabled": 0, + "flash_grant_sel": 0, + "flash_data_for_enable_poling_conf_0": 0, + "flash_offset_bits_for_enable_poling_conf_0": 0, + "flash_stop_bit_for_enable_poling_conf_0": 1, + "flash_data_for_enable_poling_conf_1": 0, + "flash_offset_bits_for_enable_poling_conf_1": 0, + "flash_stop_bit_for_enable_poling_conf_1": 1, + "flash_data_for_disable_poling_conf_0": 0, + "flash_offset_bits_for_disable_poling_conf_0": 0, + "flash_stop_bit_for_disable_poling_conf_0": 1, + "flash_data_for_disable_poling_conf_1": 0, + "flash_offset_bits_for_disable_poling_conf_1": 0, + "flash_stop_bit_for_disable_poling_conf_1": 1 + }, + "ram_alternate_polling": { + "ram_polling_resp_count": 1023, + "ram_polling_iterations": 1, + "ram_polling_enabled": 0, + "ram_polling_disabled": 0, + "ram_grant_sel": 0, + "ram_data_for_enable_poling_conf_0": 0, + "ram_offset_bits_for_enable_poling_conf_0": 0, + "ram_stop_bit_for_enable_poling_conf_0": 1, + "ram_data_for_enable_poling_conf_1": 0, + "ram_offset_bits_for_enable_poling_conf_1": 0, + "ram_stop_bit_for_enable_poling_conf_1": 1, + "ram_data_for_disable_poling_conf_0": 0, + "ram_offset_bits_for_disable_poling_conf_0": 0, + "ram_stop_bit_for_disable_poling_conf_0": 1, + "ram_data_for_disable_poling_conf_1": 0, + "ram_offset_bits_for_disable_poling_conf_1": 0, + "ram_stop_bit_for_disable_poling_conf_1": 1 + }, + "flash_wel_command": { + "flash_wel_opcode": 6, + "suppl_flash_wel_opcode": 0 + }, + "ram_wel_command": { + "ram_wel_opcode": 6, + "suppl_ram_wel_opcode": 0 + } + }, + "event": { + "host_nvic_irq": 0, + "core_10_mux_sel": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/w25q33pw/flash_disc_param_ext_mem.json b/boards/ti/lp_em_cc35x1/config/flash/w25q33pw/flash_disc_param_ext_mem.json new file mode 100644 index 000000000000..321810768be1 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/w25q33pw/flash_disc_param_ext_mem.json @@ -0,0 +1,99 @@ +{ + "vendor_primary_sbl": true, + "ti_wsoc_primary_container": true, + "ti_wsoc_bl2_primary_container": true, + "nvs_enable": true, + "vendor_alternate_image": true, + "vendor_sbl_alternate_image": true, + "ti_bl_alternate_image": true, + "ti_wsoc_alternate_image": true, + "ti_wsoc_bl2_alternate_image": true, + "region_0": { + "mem_region_0_start_phy_address": 1069056, + "mem_region_0_end_phy_address": 4194303, + "region0_boot": false, + "region0_main_code": true, + "region0_nvs": false, + "region0_wsoc_code": false, + "region0_alternate_code": false + }, + "region_1": { + "mem_region_1_start_phy_address": 0, + "mem_region_1_end_phy_address": 1069055, + "region1_boot": true, + "region1_main_code": false, + "region1_nvs": true, + "region1_wsoc_code": true, + "region1_alternate_code": false + }, + "region_2": { + "mem_region_2_start_phy_address": 0, + "mem_region_2_end_phy_address": 0, + "region2_boot": false, + "region2_main_code": false, + "region2_nvs": false, + "region2_wsoc_code": false, + "region2_alternate_code": true + }, + "region_3": { + "mem_region_3_start_phy_address": 0, + "mem_region_3_end_phy_address": 0, + "region3_boot": false, + "region3_main_code": false, + "region3_nvs": false, + "region3_wsoc_code": false, + "region3_alternate_code": false + }, + "boot_region_conf": { + "boot_region_size": 0, + "boot_region_flash_disco_param_start_address": 0, + "boot_region_primary_ti_bl_start_phy_address": 12284, + "boot_region_primary_ti_bl_magic": 0, + "boot_region_primary_ti_bl_major": 0, + "boot_region_primary_ti_bl_minor": 0, + "boot_region_sec_ti_bl_start_phy_address": 430076, + "boot_region_sec_ti_bl_magic": 0, + "boot_region_sec_ti_bl_major": 0, + "boot_region_sec_ti_bl_minor": 0 + }, + "main_code_region_conf": { + "main_code_region_vendor_image_start_phy_address": 1073148, + "main_code_region_vendor_image_magic": 0, + "main_code_region_vendor_image_major": 0, + "main_code_region_vendor_image_minor": 0, + "main_code_region_sbl_start_phy_address": 0, + "main_code_region_sbl_magic": 0, + "main_code_region_sbl_major": 0, + "main_code_region_sbl_minor": 0 + }, + "alt_code_region_conf": { + "alt_code_region_vendor_image_start_phy_address": 4194304, + "alt_code_region_vendor_image_magic": 0, + "alt_code_region_vendor_image_major": 0, + "alt_code_region_vendor_image_minor": 0, + "alt_code_region_sbl_start_phy_address": 0, + "alt_code_region_sbl_magic": 0, + "alt_code_region_sbl_major": 0, + "alt_code_region_sbl_minor": 0 + }, + "nvs_code_region_conf": { + "nvs_start_phy_address": 892928, + "nvs_region_size": 176128, + "nvs_region_primary_wsoc_start_phy_address": 430076, + "nvs_region_primary_wsoc_magic": 0, + "nvs_region_primary_wsoc_major": 0, + "nvs_region_primary_wsoc_minor": 0, + "nvs_region_sec_wsoc_start_phy_address": 897020, + "nvs_region_sec_wsoc_magic": 0, + "nvs_region_sec_wsoc_major": 0, + "nvs_region_sec_wsoc_minor": 0, + "nvs_region_primary_wsoc_bl2_start_phy_address": 0, + "nvs_region_primary_wsoc_bl2_magic": 0, + "nvs_region_primary_wsoc_bl2_major": 0, + "nvs_region_primary_wsoc_bl2_minor": 0, + "nvs_region_sec_wsoc_bl2_start_phy_address": 0, + "nvs_region_sec_wsoc_bl2_magic": 0, + "nvs_region_sec_wsoc_bl2_major": 0, + "nvs_region_sec_wsoc_bl2_minor": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/w25q33pw/flash_disc_param_otfde.json b/boards/ti/lp_em_cc35x1/config/flash/w25q33pw/flash_disc_param_otfde.json new file mode 100644 index 000000000000..e4949eaa1add --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/w25q33pw/flash_disc_param_otfde.json @@ -0,0 +1,286 @@ +{ + "otfde_header": { + "name": "OTFDEWFF3", + "flash_only": true, + "ip_protection": false, + "regions_lock": false, + "regions_number": 4, + "flash_enabled": true + }, + "bl_conf": { + "host_boot_done_lock": true, + "host_peripherals_lock": true, + "icache_conf_lock": true, + "m33_mem_part_lock": true, + "memss_firewall_lock": true, + "dma_channel_owner_lock": true, + "otfde_region_lock": true, + "core_events_lock": true + }, + "otfde_general": { + "parameters": { + "mem_otfde_initial_delay": 10, + "otfde_global_watchdog_timer": 5 + }, + "events": { + "reset_evt_mask": false, + "reset_evt_suspend": false, + "sft_reset_evt_mask": false, + "sft_reset_evt_suspend": false, + "bypass_mode_evt_mask": false, + "bypass_mode_evt_suspend": false, + "debug_mode_evt_mask": false, + "debug_mode_evt_suspend": false, + "general_evt_mask": false, + "general_evt_suspend": false, + "xspi_data_path_evt_mask": false, + "xspi_data_path_evt_suspend": false, + "xspi_cnfg_path_evt_mask": false, + "xspi_cnfg_path_evt_suspend": false, + "xspi_service_interrupt_evt_mask": false, + "xspi_service_interrupt_evt_suspend": false, + "trans_device_disabled_evt_mask": false, + "trans_device_disabled_evt_suspend": false, + "trans_region_disabled_evt_mask": false, + "trans_region_disabled_evt_suspend": false, + "trans_region_params_conf_evt_mask": false, + "trans_region_params_conf_evt_suspend": false, + "trans_multiple_regions_mapped_evt_mask": false, + "trans_multiple_regions_mapped_evt_suspend": false, + "trans_address_not_32_bit_evt_mask": false, + "trans_address_not_32_bit_evt_suspend": false, + "trans_size_not_32_bit_evt_mask": false, + "trans_size_not_32_bit_evt_suspend": false, + "trans_burst_not_32_bit_evt_mask": false, + "trans_burst_not_32_bit_evt_suspend": false, + "region_read_write_def_evt_mask": false, + "region_read_write_def_evt_suspend": false, + "suspend_while_disabled_evt_mask": false, + "suspend_while_disabled_evt_suspend": false + } + }, + "regions_settings": { + "region_parameters_lock": { + "REGION_0_PARAMS_0": true, + "REGION_0_PARAMS_1": true, + "REGION_0_PARAMS_2": true, + "REGION_1_PARAMS_0": false, + "REGION_1_PARAMS_1": false, + "REGION_1_PARAMS_2": false, + "REGION_2_PARAMS_0": true, + "REGION_2_PARAMS_1": true, + "REGION_2_PARAMS_2": true, + "REGION_3_PARAMS_0": false, + "REGION_3_PARAMS_1": false, + "REGION_3_PARAMS_2": false + }, + "region_0_protection": { + "mem_region_0_enabled": true, + "mem_region_0_device_id": 0, + "mem_region_0_spi_write_enable": true, + "mem_region_0_spi_read_enable": true, + "mem_region_0_physical_offset": 261, + "mem_region_0_security_id_msb": 0, + "mem_region_0_start_address": 81920, + "mem_region_0_end_address": 82682, + "mem_region_0_security_id_lsb": 0, + "mem_otfde_region_0_write_lock_en": false, + "mem_otfde_region_0_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_1_protection": { + "mem_region_1_enabled": true, + "mem_region_1_device_id": 0, + "mem_region_1_spi_write_enable": true, + "mem_region_1_spi_read_enable": true, + "mem_region_1_physical_offset": 0, + "mem_region_1_security_id_msb": 0, + "mem_region_1_start_address": 655360, + "mem_region_1_end_address": 655620, + "mem_region_1_security_id_lsb": 0, + "mem_otfde_region_1_write_lock_en": false, + "mem_otfde_region_1_enc_dec_bypass": "Bypass" + }, + "region_2_protection": { + "mem_region_2_enabled": false, + "mem_region_2_device_id": 0, + "mem_region_2_spi_write_enable": true, + "mem_region_2_spi_read_enable": true, + "mem_region_2_physical_offset": 0, + "mem_region_2_security_id_msb": 0, + "mem_region_2_start_address": 1, + "mem_region_2_end_address": 0, + "mem_region_2_security_id_lsb": 0, + "mem_otfde_region_2_write_lock_en": false, + "mem_otfde_region_2_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_3_protection": { + "mem_region_3_enabled": false, + "mem_region_3_device_id": 1, + "mem_region_3_spi_write_enable": true, + "mem_region_3_spi_read_enable": true, + "mem_region_3_physical_offset": 0, + "mem_region_3_security_id_msb": 0, + "mem_region_3_start_address": 1, + "mem_region_3_end_address": 0, + "mem_region_3_security_id_lsb": 0, + "mem_otfde_region_3_write_lock_en": false, + "mem_otfde_region_3_enc_dec_bypass": "Bypass" + } + }, + "devices": { + "header": { + "flash_device_switch_conf": 1, + "ram_device_switch_conf": 1 + }, + "flash_switch": { + "flash_grant_sel": 0, + "flash_data_for_conf_0": 2181562505, + "flash_offset_bits_for_conf_0": 0, + "flash_stop_bit_for_conf_0": 0, + "flash_data_for_conf_1": 100803083, + "flash_offset_bits_for_conf_1": 1, + "flash_stop_bit_for_conf_1": 0, + "flash_data_for_conf_2": 139266, + "flash_offset_bits_for_conf_2": 2, + "flash_stop_bit_for_conf_2": 0, + "flash_data_for_conf_3": 1, + "flash_offset_bits_for_conf_3": 4, + "flash_stop_bit_for_conf_3": 0, + "flash_data_for_conf_4": 1076887634, + "flash_offset_bits_for_conf_4": 45, + "flash_stop_bit_for_conf_4": 0, + "flash_data_for_conf_5": 3224371282, + "flash_offset_bits_for_conf_5": 45, + "flash_stop_bit_for_conf_5": 0, + "flash_data_for_conf_6": 262149, + "flash_offset_bits_for_conf_6": 14, + "flash_stop_bit_for_conf_6": 0, + "flash_data_for_conf_7": 0, + "flash_offset_bits_for_conf_7": 44, + "flash_stop_bit_for_conf_7": 1, + "flash_data_for_conf_8": 0, + "flash_offset_bits_for_conf_8": 0, + "flash_stop_bit_for_conf_8": 1, + "flash_data_for_conf_9": 0, + "flash_offset_bits_for_conf_9": 0, + "flash_stop_bit_for_conf_9": 1, + "flash_data_for_conf_10": 0, + "flash_offset_bits_for_conf_10": 0, + "flash_stop_bit_for_conf_10": 1, + "flash_data_for_conf_11": 0, + "flash_offset_bits_for_conf_11": 0, + "flash_stop_bit_for_conf_11": 1, + "flash_data_for_conf_12": 0, + "flash_offset_bits_for_conf_12": 0, + "flash_stop_bit_for_conf_12": 1, + "flash_data_for_conf_13": 0, + "flash_offset_bits_for_conf_13": 0, + "flash_stop_bit_for_conf_13": 1, + "flash_data_for_conf_14": 0, + "flash_offset_bits_for_conf_14": 0, + "flash_stop_bit_for_conf_14": 1, + "flash_data_for_conf_15": 0, + "flash_offset_bits_for_conf_15": 0, + "flash_stop_bit_for_conf_15": 1, + "flash_data_for_conf_16": 0, + "flash_offset_bits_for_conf_16": 0, + "flash_stop_bit_for_conf_16": 1, + "flash_data_for_conf_17": 0, + "flash_offset_bits_for_conf_17": 0, + "flash_stop_bit_for_conf_17": 1, + "flash_data_for_conf_18": 0, + "flash_offset_bits_for_conf_18": 0, + "flash_stop_bit_for_conf_18": 1, + "flash_data_for_conf_19": 0, + "flash_offset_bits_for_conf_19": 0, + "flash_stop_bit_for_conf_19": 1, + "flash_data_for_conf_20": 0, + "flash_offset_bits_for_conf_20": 0, + "flash_stop_bit_for_conf_20": 1, + "flash_data_for_conf_21": 0, + "flash_offset_bits_for_conf_21": 0, + "flash_stop_bit_for_conf_21": 1, + "flash_data_for_conf_22": 0, + "flash_offset_bits_for_conf_22": 0, + "flash_stop_bit_for_conf_22": 1, + "flash_data_for_conf_23": 0, + "flash_offset_bits_for_conf_23": 0, + "flash_stop_bit_for_conf_23": 1 + }, + "ram_switch": { + "ram_grant_sel": 0, + "ram_data_for_conf_0": 2181563529, + "ram_offset_bits_for_conf_0": 0, + "ram_stop_bit_for_conf_0": 0, + "ram_data_for_conf_1": 100803307, + "ram_offset_bits_for_conf_1": 1, + "ram_stop_bit_for_conf_1": 0, + "ram_data_for_conf_2": 139320, + "ram_offset_bits_for_conf_2": 2, + "ram_stop_bit_for_conf_2": 0, + "ram_data_for_conf_3": 3089693184, + "ram_offset_bits_for_conf_3": 56, + "ram_stop_bit_for_conf_3": 0, + "ram_data_for_conf_4": 1, + "ram_offset_bits_for_conf_4": 4, + "ram_stop_bit_for_conf_4": 0, + "ram_data_for_conf_5": 1076494399, + "ram_offset_bits_for_conf_5": 45, + "ram_stop_bit_for_conf_5": 0, + "ram_data_for_conf_6": 3223978047, + "ram_offset_bits_for_conf_6": 45, + "ram_stop_bit_for_conf_6": 0, + "ram_data_for_conf_7": 278533, + "ram_offset_bits_for_conf_7": 14, + "ram_stop_bit_for_conf_7": 0, + "ram_data_for_conf_8": 0, + "ram_offset_bits_for_conf_8": 44, + "ram_stop_bit_for_conf_8": 1, + "ram_data_for_conf_9": 0, + "ram_offset_bits_for_conf_9": 0, + "ram_stop_bit_for_conf_9": 1, + "ram_data_for_conf_10": 0, + "ram_offset_bits_for_conf_10": 0, + "ram_stop_bit_for_conf_10": 1, + "ram_data_for_conf_11": 0, + "ram_offset_bits_for_conf_11": 0, + "ram_stop_bit_for_conf_11": 1, + "ram_data_for_conf_12": 0, + "ram_offset_bits_for_conf_12": 0, + "ram_stop_bit_for_conf_12": 1, + "ram_data_for_conf_13": 0, + "ram_offset_bits_for_conf_13": 0, + "ram_stop_bit_for_conf_13": 1, + "ram_data_for_conf_14": 0, + "ram_offset_bits_for_conf_14": 0, + "ram_stop_bit_for_conf_14": 1, + "ram_data_for_conf_15": 0, + "ram_offset_bits_for_conf_15": 0, + "ram_stop_bit_for_conf_15": 1, + "ram_data_for_conf_16": 0, + "ram_offset_bits_for_conf_16": 0, + "ram_stop_bit_for_conf_16": 1, + "ram_data_for_conf_17": 0, + "ram_offset_bits_for_conf_17": 0, + "ram_stop_bit_for_conf_17": 1, + "ram_data_for_conf_18": 0, + "ram_offset_bits_for_conf_18": 0, + "ram_stop_bit_for_conf_18": 1, + "ram_data_for_conf_19": 0, + "ram_offset_bits_for_conf_19": 0, + "ram_stop_bit_for_conf_19": 1, + "ram_data_for_conf_20": 0, + "ram_offset_bits_for_conf_20": 0, + "ram_stop_bit_for_conf_20": 1, + "ram_data_for_conf_21": 0, + "ram_offset_bits_for_conf_21": 0, + "ram_stop_bit_for_conf_21": 1, + "ram_data_for_conf_22": 0, + "ram_offset_bits_for_conf_22": 0, + "ram_stop_bit_for_conf_22": 1, + "ram_data_for_conf_23": 0, + "ram_offset_bits_for_conf_23": 0, + "ram_stop_bit_for_conf_23": 1 + } + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/w25q33pw/flash_disc_param_xspi.json b/boards/ti/lp_em_cc35x1/config/flash/w25q33pw/flash_disc_param_xspi.json new file mode 100644 index 000000000000..f4dbbdd0eba9 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/w25q33pw/flash_disc_param_xspi.json @@ -0,0 +1,485 @@ +{ + "xspi_header": { + "name": "xSPIWFF3", + "device": "CC3500", + "use_hardware": "W25Q33PW", + "use_case": "Quadro", + "dqs_support": 0, + "flash_only": 1, + "flash_separate_reset": 0, + "ram_separate_reset": true, + "clock_frequency": 80, + "qospi_clock_divider": 1, + "flash_device_character_conf": 0, + "ram_device_character_conf": 0, + "header_advanced": 0, + "phy_mode_enable": 1, + "pipeline_mode_enable": 1, + "loopback_support": "No", + "qspi_ref_clock": 80, + "spi_clock_freq": 20, + "spi_clock_divider": 1, + "flash_device_size": 4, + "flash_bytes_per_block": 16, + "flash_bytes_per_page": 256, + "flash_number_of_address_bytes": 3, + "flash_dual_opcode": 0, + "flash_jedec_manufacturer_id": 0, + "flash_jedec_device_id": 32790, + "flash_name": "W25Q33PW", + "flash_page_size": 256, + "flash_sector_size": 4096, + "flash_cs_polarity": "ACTIVE_LOW", + "flash_sw_reset_type": "x1xxxx", + "ram_device_size": 4, + "ram_bytes_per_block": 16, + "ram_bytes_per_page": 256, + "ram_number_of_address_bytes": 3, + "ram_dual_opcode": 0, + "ram_jedec_manufacturer_id": 0, + "ram_jedec_device_id": 32790, + "ram_name": "NO_PSRAM", + "ram_page_size": 256, + "ram_sector_size": 4096, + "ram_cs_polarity": "ACTIVE_LOW", + "ram_sw_reset_type": "x1xxxx", + "flash_write_operation_modes": "4S-4S-4S", + "flash_read_operation_modes": "4S-4S-4S", + "ram_write_operation_modes": "4S-4S-4S", + "ram_read_operation_modes": "4S-4S-4S", + "crc_enable": 0, + "enable_dtr": 0, + "enable_ahb_decoder": 0, + "enter_xip_mod_immediately": 0, + "enter_xip_mod_next_read": 0, + "ahb_address_remapping": 0, + "enable_dma": 0, + "select_decode": 0, + "legacy_ip_mode": 0, + "direct_access": 1 + }, + "xspi_pinmux": { + "xspi_clk_input": 44, + "xspi_clk_input_use_hw": 0, + "xspi_clk_input_mode": "Input", + "xspi_clk_input_pull": "None", + "xspi_clk_input_interrupt_trigger": "Low", + "xspi_clk_input_dont_conf": 0, + "xspi_clk_input_output_strength": "High", + "xspi_clk_input_initial_output_state": "High", + "xspi_clk": 24, + "xspi_clk_use_hw": "None", + "xspi_clk_mode": "Output", + "xspi_clk_pull": "None", + "xspi_clk_output_strength": "High", + "xspi_clk_initial_output_state": "High", + "xspi_clk_interrupt_trigger": "None", + "xspi_clk_dont_conf": 0, + "xspi_flash_cs": 20, + "xspi_flash_cs_use_hw": "None", + "xspi_flash_cs_mode": "Output", + "xspi_flash_cs_pull": "None", + "xspi_flash_cs_output_strength": "High", + "xspi_flash_cs_initial_output_state": "High", + "xspi_flash_cs_interrupt_trigger": "None", + "xspi_flash_cs_dont_conf": 0, + "xspi_data_0": 25, + "xspi_data_0_use_hw": "None", + "xspi_data_0_mode": "Input", + "xspi_data_0_pull": "None", + "xspi_data_0_output_strength": "High", + "xspi_data_0_initial_output_state": "High", + "xspi_data_0_interrupt_trigger": "Low", + "xspi_data_0_dont_conf": 0, + "xspi_data_1": 21, + "xspi_data_1_use_hw": "None", + "xspi_data_1_mode": "Input", + "xspi_data_1_pull": "None", + "xspi_data_1_output_strength": "High", + "xspi_data_1_initial_output_state": "High", + "xspi_data_1_interrupt_trigger": "Low", + "xspi_data_1_dont_conf": 0, + "xspi_data_2": 22, + "xspi_data_2_use_hw": "None", + "xspi_data_2_mode": "Input", + "xspi_data_2_pull": "None", + "xspi_data_2_output_strength": "High", + "xspi_data_2_initial_output_state": "High", + "xspi_data_2_interrupt_trigger": "Low", + "xspi_data_2_dont_conf": 0, + "xspi_data_3": 23, + "xspi_data_3_use_hw": "None", + "xspi_data_3_mode": "Input", + "xspi_data_3_pull": "None", + "xspi_data_3_output_strength": "High", + "xspi_data_3_initial_output_state": "High", + "xspi_data_3_interrupt_trigger": "Low", + "xspi_data_3_dont_conf": 0, + "xspi_data_4": 26, + "xspi_data_4_use_hw": "None", + "xspi_data_4_mode": "Input", + "xspi_data_4_pull": "None", + "xspi_data_4_output_strength": "High", + "xspi_data_4_initial_output_state": "High", + "xspi_data_4_interrupt_trigger": "None", + "xspi_data_4_dont_conf": 0, + "xspi_data_5": 27, + "xspi_data_5_use_hw": "None", + "xspi_data_5_mode": "Input", + "xspi_data_5_pull": "None", + "xspi_data_5_output_strength": "High", + "xspi_data_5_initial_output_state": "High", + "xspi_data_5_interrupt_trigger": "None", + "xspi_data_5_dont_conf": 0, + "xspi_data_6": 28, + "xspi_data_6_use_hw": "None", + "xspi_data_6_mode": "Input", + "xspi_data_6_pull": "None", + "xspi_data_6_output_strength": "High", + "xspi_data_6_initial_output_state": "High", + "xspi_data_6_interrupt_trigger": "None", + "xspi_data_6_dont_conf": 0, + "xspi_data_7": 29, + "xspi_data_7_use_hw": "None", + "xspi_data_7_mode": "Input", + "xspi_data_7_pull": "None", + "xspi_data_7_output_strength": "High", + "xspi_data_7_initial_output_state": "High", + "xspi_data_7_interrupt_trigger": "None", + "xspi_data_7_dont_conf": 0, + "xspi_reset_flash": 36, + "xspi_reset_flash_use_hw": "None", + "xspi_reset_flash_mode": "Output", + "xspi_reset_flash_pull": "None", + "xspi_reset_flash_output_strength": "High", + "xspi_reset_flash_initial_output_state": "High", + "xspi_reset_flash_interrupt_trigger": "None", + "xspi_reset_flash_dont_conf": 0, + "xspi_cs_ram": 3, + "xspi_cs_ram_use_hw": "None", + "xspi_cs_ram_mode": "Output", + "xspi_cs_ram_pull": "None", + "xspi_cs_ram_output_strength": "High", + "xspi_cs_ram_initial_output_state": "High", + "xspi_cs_ram_interrupt_trigger": "None", + "xspi_cs_ram_dont_conf": 0, + "xspi_dqs": 30, + "xspi_dqs_use_hw": "None", + "xspi_dqs_mode": "Input", + "xspi_dqs_pull": "None", + "xspi_dqs_output_strength": "High", + "xspi_dqs_initial_output_state": "High", + "xspi_dqs_interrupt_trigger": "None", + "xspi_dqs_dont_conf": 0, + "xspi_reset_ram": 2, + "xspi_reset_ram_use_hw": "None", + "xspi_reset_ram_mode": "Input", + "xspi_reset_ram_pull": "None", + "xspi_reset_ram_output_strength": "High", + "xspi_reset_ram_initial_output_state": "High", + "xspi_reset_ram_interrupt_trigger": "None", + "xspi_reset_ram_dont_conf": 0 + }, + "xspi_operations": { + "xspi_operations_clocks": { + "clock_phase": 0, + "clock_polarity": 0, + "spi_mode": "2'b00" + }, + "xspi_operations_chip_select": { + "csda": 2, + "csdads": 0, + "cseot": 4, + "cssot": 1 + }, + "xspi_operations_reset": { + "flash_jedec_reset": 1, + "ram_jedec_reset": 1, + "flash_treset": 20, + "ram_treset": 20 + }, + "xspi_phy_operations": { + "flash_rx_dll_bypass_bit": 0, + "flash_dll_tx_delay": 61, + "flash_dll_rx_delay": 65, + "ram_rx_dll_bypass_bit": 0, + "ram_dll_tx_delay": 61, + "ram_dll_rx_delay": 65 + }, + "xspi_read_operations": { + "flash_dummy_rd_cycles": 6, + "flash_read_opcode": 11, + "suppl_flash_read_opcode": 0, + "ram_dummy_rd_cycles": 6, + "ram_read_opcode": 11, + "suppl_ram_read_opcode": 0, + "flash_non_cont_read_enable": 0, + "flash_max_read_jobs": 256, + "ram_non_cont_read_enable": 0, + "ram_max_read_jobs": 256, + "rww_en": 0, + "device_size": 4, + "number_of_banks": 1, + "bank_size": 4, + "mode_bit_enable": 0 + }, + "xspi_write_operations": { + "flash_address_and_data": { + "flash_dummy_wr_cycles": 0 + }, + "flash_command": { + "flash_write_opcode": 2, + "suppl_flash_write_opcode": 0 + }, + "ram_address_and_data": { + "ram_dummy_wr_cycles": 0 + }, + "ram_command": { + "ram_write_opcode": 2, + "suppl_ram_write_opcode": 0 + }, + "write_to_buffer": { + "flash_write_to_buffer_support": 0, + "ram_write_to_buffer_support": 0 + }, + "non_continuous_write": { + "flash_non_cont_write_enable": 0, + "flash_max_write_jobs": 64, + "ram_non_cont_write_enable": 0, + "ram_max_write_jobs": 0 + }, + "flash_program_operation": { + "flash_min_program_size": "256 B", + "flash_program_opcode": 2, + "suppl_flash_program_opcode": 0, + "flash_maximum_program_time_limit": 1600 + }, + "flash_erase_operation": { + "flash_min_erase_size": "4 kB", + "flash_erase_opcode": 32, + "suppl_flash_erase_opcode": 0, + "flash_maximum_erase_time_limit": 4095 + }, + "flash_erase_conf": { + "flash_block_erase_opcode": 0, + "suppl_block_flash_erase_opcode": 0, + "flash_sector_erase_opcode": 0, + "suppl_sector_flash_erase_opcode": 0, + "flash_chip_erase_opcode": 0, + "suppl_chip_flash_erase_opcode": 0 + }, + "ram_program_operation": { + "ram_min_program_size": "256 B", + "ram_program_opcode": 2, + "suppl_ram_program_opcode": 0, + "ram_maximum_program_time_limit": 1600 + }, + "ram_erase_conf": { + "ram_block_erase_opcode": 0, + "suppl_block_ram_erase_opcode": 0, + "ram_sector_erase_opcode": 0, + "suppl_sector_ram_erase_opcode": 0, + "ram_chip_erase_opcode": 0, + "suppl_chip_ram_erase_opcode": 0 + }, + "flash_buffer_support": { + "flash_pre_write_sequence": 0, + "flash_post_write_sequence": 0, + "flash_write_protection_timer_en": 0, + "flash_write_buffer_timer_mode": 16, + "flash_write_buffer_timer_range": 0, + "flash_service_interrupt_criteria": 0 + }, + "ram_buffer_support": { + "ram_pre_write_sequence": 0, + "ram_post_write_sequence": 0, + "ram_write_protection_timer_en": 0, + "ram_write_buffer_timer_mode": 16, + "ram_write_buffer_timer_range": 0, + "ram_service_interrupt_criteria": 0 + }, + "flash_pre_write_conf": { + "flash_pre_write_job_done_grant_sel": 0, + "data_for_flash_pre_write_conf_0": 0, + "offset_bits_for_flash_pre_write_conf_0": 0, + "stop_bit_for_flash_pre_write_conf_0": 1, + "data_for_flash_pre_write_conf_1": 0, + "offset_bits_for_flash_pre_write_conf_1": 0 + }, + "flash_post_write_conf": { + "flash_post_write_job_done_grant_sel": 0, + "data_for_flash_post_write_conf_0": 0, + "offset_bits_for_flash_post_write_conf_0": 0, + "stop_bit_for_flash_post_write_conf_0": 1, + "data_for_flash_post_write_conf_1": 0, + "offset_bits_for_flash_post_write_conf_1": 0 + }, + "ram_pre_write_conf": { + "ram_pre_write_job_done_grant_sel": 0, + "data_for_ram_pre_write_conf_0": 0, + "offset_bits_for_ram_pre_write_conf_0": 0, + "stop_bit_for_ram_pre_write_conf_0": 1, + "data_for_ram_pre_write_conf_1": 0, + "offset_bits_for_ram_pre_write_conf_1": 0 + }, + "ram_post_write_conf": { + "ram_post_write_job_done_grant_sel": 0, + "data_for_ram_post_write_conf_0": 0, + "offset_bits_for_ram_post_write_conf_0": 0, + "stop_bit_for_ram_post_write_conf_0": 1, + "data_for_ram_post_write_conf_1": 0, + "offset_bits_for_ram_post_write_conf_1": 0 + } + }, + "xspi_capture_operations": { + "read_data_capture": { + "flash_delay_transmitted_data": 0, + "flash_loopback_clock": 0, + "flash_bypass_adapted_loopback": 1, + "flash_sample_edge_sel": 0, + "ram_delay_transmitted_data": 0, + "ram_loopback_clock": 0, + "ram_bypass_adapted_loopback": 1, + "ram_sample_edge_sel": 0 + }, + "delays": { + "flash_full_half_cycle_delay": 0, + "flash_dll_bypass_mode": 1, + "flash_phase_detect_sel": 0, + "flash_dll_lock_num": 0, + "flash_dll_start_point": 0, + "flash_loopback_clock": 0, + "ram_full_half_cycle_delay": 0, + "ram_dll_bypass_mode": 1, + "ram_phase_detect_sel": 0, + "ram_dll_lock_num": 0, + "ram_dll_start_point": 0, + "ram_loopback_clock": 0 + }, + "operation_modes": { + "flash_sfdp_support": 0, + "ram_sfdp_support": 0, + "flash_pm_support": 0, + "ram_pm_support": 0, + "flash_sfdp_opcode": 0, + "suppl_flash_sfdp_opcode": 0, + "ram_sfdp_opcode": 0, + "suppl_ram_sfdp_opcode": 0, + "flash_enter_dpd_opcode": 185, + "suppl_flash_enter_dpd_opcode": 0, + "flash_exit_dpd_opcode": 171, + "suppl_flash_exit_dpd_opcode": 0, + "ram_enter_dpd_opcode": 185, + "suppl_ram_enter_dpd_opcode": 0, + "ram_exit_dpd_opcode": 171, + "suppl_ram_exit_dpd_opcode": 0, + "flash_quad_enable_opcode": 56, + "suppl_flash_quad_enable_opcode": 0, + "flash_quad_disable_opcode": 255, + "suppl_flash_quad_disable_opcode": 0, + "flash_octal_enable_opcode": 0, + "suppl_flash_octal_enable_opcode": 0, + "flash_octal_disable_opcode": 0, + "suppl_flash_octal_disable_opcode": 0, + "ram_quad_enable_opcode": 56, + "suppl_ram_quad_enable_opcode": 0, + "ram_quad_disable_opcode": 255, + "suppl_ram_quad_disable_opcode": 0, + "ram_octal_enable_opcode": 0, + "suppl_ram_octal_enable_opcode": 0, + "ram_octal_disable_opcode": 0, + "suppl_ram_octal_disable_opcode": 0 + } + } + }, + "external_memory_reporting": { + "header": { + "flash_auto_polling_enable": 1, + "flash_wel_enable": 1, + "flash_write_protect_enable": 0, + "flash_alternate_polling_conf_enable": 0, + "ram_auto_polling_enable": 1, + "ram_wel_enable": 1, + "ram_write_protect_enable": 0, + "ram_alternate_polling_conf_enable": 0 + }, + "flash_auto_polling": { + "flash_polling_repetition_delay": 0, + "flash_polling_count": 4, + "flash_enable_polling_expiration": 0, + "flash_polling_polarity": 0, + "flash_polling_address_phase_enable": 0, + "flash_polling_bit_index": 0, + "flash_numbers_poll_cycles": 65535, + "flash_dummy_autopoll_cycles": 0 + }, + "ram_auto_polling": { + "ram_polling_repetition_delay": 0, + "ram_polling_count": 4, + "ram_enable_polling_expiration": 0, + "ram_polling_polarity": 0, + "ram_polling_address_phase_enable": 0, + "ram_polling_bit_index": 0, + "ram_numbers_poll_cycles": 65535, + "ram_dummy_autopoll_cycles": 0 + }, + "flash_polling_command": { + "flash_polling_opcode": 5, + "suppl_flash_polling_opcode": 0 + }, + "ram_polling_command": { + "ram_polling_opcode": 5, + "suppl_ram_polling_opcode": 0 + }, + "flash_alternate_polling": { + "flash_polling_resp_count": 1023, + "flash_polling_iterations": 1, + "flash_polling_enabled": 0, + "flash_polling_disabled": 0, + "flash_grant_sel": 0, + "flash_data_for_enable_poling_conf_0": 0, + "flash_offset_bits_for_enable_poling_conf_0": 0, + "flash_stop_bit_for_enable_poling_conf_0": 1, + "flash_data_for_enable_poling_conf_1": 0, + "flash_offset_bits_for_enable_poling_conf_1": 0, + "flash_stop_bit_for_enable_poling_conf_1": 1, + "flash_data_for_disable_poling_conf_0": 0, + "flash_offset_bits_for_disable_poling_conf_0": 0, + "flash_stop_bit_for_disable_poling_conf_0": 1, + "flash_data_for_disable_poling_conf_1": 0, + "flash_offset_bits_for_disable_poling_conf_1": 0, + "flash_stop_bit_for_disable_poling_conf_1": 1 + }, + "ram_alternate_polling": { + "ram_polling_resp_count": 1023, + "ram_polling_iterations": 1, + "ram_polling_enabled": 0, + "ram_polling_disabled": 0, + "ram_grant_sel": 0, + "ram_data_for_enable_poling_conf_0": 0, + "ram_offset_bits_for_enable_poling_conf_0": 0, + "ram_stop_bit_for_enable_poling_conf_0": 1, + "ram_data_for_enable_poling_conf_1": 0, + "ram_offset_bits_for_enable_poling_conf_1": 0, + "ram_stop_bit_for_enable_poling_conf_1": 1, + "ram_data_for_disable_poling_conf_0": 0, + "ram_offset_bits_for_disable_poling_conf_0": 0, + "ram_stop_bit_for_disable_poling_conf_0": 1, + "ram_data_for_disable_poling_conf_1": 0, + "ram_offset_bits_for_disable_poling_conf_1": 0, + "ram_stop_bit_for_disable_poling_conf_1": 1 + }, + "flash_wel_command": { + "flash_wel_opcode": 6, + "suppl_flash_wel_opcode": 0 + }, + "ram_wel_command": { + "ram_wel_opcode": 6, + "suppl_ram_wel_opcode": 0 + } + }, + "event": { + "host_nvic_irq": 0, + "core_10_mux_sel": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/w25q64jw/flash_disc_param_ext_mem.json b/boards/ti/lp_em_cc35x1/config/flash/w25q64jw/flash_disc_param_ext_mem.json new file mode 100644 index 000000000000..6585853ccd5e --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/w25q64jw/flash_disc_param_ext_mem.json @@ -0,0 +1,99 @@ +{ + "vendor_primary_sbl": true, + "ti_wsoc_primary_container": true, + "ti_wsoc_bl2_primary_container": true, + "nvs_enable": true, + "vendor_alternate_image": true, + "vendor_sbl_alternate_image": true, + "ti_bl_alternate_image": true, + "ti_wsoc_alternate_image": true, + "ti_wsoc_bl2_alternate_image": true, + "region_0": { + "mem_region_0_start_phy_address": 2867200, + "mem_region_0_end_phy_address": 5627903, + "region0_boot": false, + "region0_main_code": true, + "region0_nvs": false, + "region0_wsoc_code": false, + "region0_alternate_code": false + }, + "region_1": { + "mem_region_1_start_phy_address": 0, + "mem_region_1_end_phy_address": 2867199, + "region1_boot": true, + "region1_main_code": false, + "region1_nvs": true, + "region1_wsoc_code": true, + "region1_alternate_code": false + }, + "region_2": { + "mem_region_2_start_phy_address": 5627904, + "mem_region_2_end_phy_address": 8388607, + "region2_boot": false, + "region2_main_code": false, + "region2_nvs": false, + "region2_wsoc_code": false, + "region2_alternate_code": true + }, + "region_3": { + "mem_region_3_start_phy_address": 0, + "mem_region_3_end_phy_address": 0, + "region3_boot": false, + "region3_main_code": false, + "region3_nvs": false, + "region3_wsoc_code": false, + "region3_alternate_code": false + }, + "boot_region_conf": { + "boot_region_size": 0, + "boot_region_flash_disco_param_start_address": 0, + "boot_region_primary_ti_bl_start_phy_address": 12284, + "boot_region_primary_ti_bl_magic": 0, + "boot_region_primary_ti_bl_major": 0, + "boot_region_primary_ti_bl_minor": 0, + "boot_region_sec_ti_bl_start_phy_address": 430076, + "boot_region_sec_ti_bl_magic": 0, + "boot_region_sec_ti_bl_major": 0, + "boot_region_sec_ti_bl_minor": 0 + }, + "main_code_region_conf": { + "main_code_region_vendor_image_start_phy_address": 2871292, + "main_code_region_vendor_image_magic": 0, + "main_code_region_vendor_image_major": 0, + "main_code_region_vendor_image_minor": 0, + "main_code_region_sbl_start_phy_address": 0, + "main_code_region_sbl_magic": 0, + "main_code_region_sbl_major": 0, + "main_code_region_sbl_minor": 0 + }, + "alt_code_region_conf": { + "alt_code_region_vendor_image_start_phy_address": 5631996, + "alt_code_region_vendor_image_magic": 0, + "alt_code_region_vendor_image_major": 0, + "alt_code_region_vendor_image_minor": 0, + "alt_code_region_sbl_start_phy_address": 0, + "alt_code_region_sbl_magic": 0, + "alt_code_region_sbl_major": 0, + "alt_code_region_sbl_minor": 0 + }, + "nvs_code_region_conf": { + "nvs_start_phy_address": 1777664, + "nvs_region_size": 1089536, + "nvs_region_primary_wsoc_start_phy_address": 847868, + "nvs_region_primary_wsoc_magic": 0, + "nvs_region_primary_wsoc_major": 0, + "nvs_region_primary_wsoc_minor": 0, + "nvs_region_sec_wsoc_start_phy_address": 1314812, + "nvs_region_sec_wsoc_magic": 0, + "nvs_region_sec_wsoc_major": 0, + "nvs_region_sec_wsoc_minor": 0, + "nvs_region_primary_wsoc_bl2_start_phy_address": 0, + "nvs_region_primary_wsoc_bl2_magic": 0, + "nvs_region_primary_wsoc_bl2_major": 0, + "nvs_region_primary_wsoc_bl2_minor": 0, + "nvs_region_sec_wsoc_bl2_start_phy_address": 0, + "nvs_region_sec_wsoc_bl2_magic": 0, + "nvs_region_sec_wsoc_bl2_major": 0, + "nvs_region_sec_wsoc_bl2_minor": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/w25q64jw/flash_disc_param_otfde.json b/boards/ti/lp_em_cc35x1/config/flash/w25q64jw/flash_disc_param_otfde.json new file mode 100644 index 000000000000..9d566e87bc6a --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/w25q64jw/flash_disc_param_otfde.json @@ -0,0 +1,286 @@ +{ + "otfde_header": { + "name": "OTFDEWFF3", + "flash_only": true, + "ip_protection": false, + "regions_lock": false, + "regions_number": 4, + "flash_enabled": true + }, + "bl_conf": { + "host_boot_done_lock": true, + "host_peripherals_lock": true, + "icache_conf_lock": true, + "m33_mem_part_lock": true, + "memss_firewall_lock": true, + "dma_channel_owner_lock": true, + "otfde_region_lock": true, + "core_events_lock": true + }, + "otfde_general": { + "parameters": { + "mem_otfde_initial_delay": 10, + "otfde_global_watchdog_timer": 5 + }, + "events": { + "reset_evt_mask": false, + "reset_evt_suspend": false, + "sft_reset_evt_mask": false, + "sft_reset_evt_suspend": false, + "bypass_mode_evt_mask": false, + "bypass_mode_evt_suspend": false, + "debug_mode_evt_mask": false, + "debug_mode_evt_suspend": false, + "general_evt_mask": false, + "general_evt_suspend": false, + "xspi_data_path_evt_mask": false, + "xspi_data_path_evt_suspend": false, + "xspi_cnfg_path_evt_mask": false, + "xspi_cnfg_path_evt_suspend": false, + "xspi_service_interrupt_evt_mask": false, + "xspi_service_interrupt_evt_suspend": false, + "trans_device_disabled_evt_mask": false, + "trans_device_disabled_evt_suspend": false, + "trans_region_disabled_evt_mask": false, + "trans_region_disabled_evt_suspend": false, + "trans_region_params_conf_evt_mask": false, + "trans_region_params_conf_evt_suspend": false, + "trans_multiple_regions_mapped_evt_mask": false, + "trans_multiple_regions_mapped_evt_suspend": false, + "trans_address_not_32_bit_evt_mask": false, + "trans_address_not_32_bit_evt_suspend": false, + "trans_size_not_32_bit_evt_mask": false, + "trans_size_not_32_bit_evt_suspend": false, + "trans_burst_not_32_bit_evt_mask": false, + "trans_burst_not_32_bit_evt_suspend": false, + "region_read_write_def_evt_mask": false, + "region_read_write_def_evt_suspend": false, + "suspend_while_disabled_evt_mask": false, + "suspend_while_disabled_evt_suspend": false + } + }, + "regions_settings": { + "region_parameters_lock": { + "REGION_0_PARAMS_0": true, + "REGION_0_PARAMS_1": true, + "REGION_0_PARAMS_2": true, + "REGION_1_PARAMS_0": false, + "REGION_1_PARAMS_1": false, + "REGION_1_PARAMS_2": false, + "REGION_2_PARAMS_0": true, + "REGION_2_PARAMS_1": true, + "REGION_2_PARAMS_2": true, + "REGION_3_PARAMS_0": false, + "REGION_3_PARAMS_1": false, + "REGION_3_PARAMS_2": false + }, + "region_0_protection": { + "mem_region_0_enabled": true, + "mem_region_0_device_id": 0, + "mem_region_0_spi_write_enable": true, + "mem_region_0_spi_read_enable": true, + "mem_region_0_physical_offset": 700, + "mem_region_0_security_id_msb": 0, + "mem_region_0_start_address": 81920, + "mem_region_0_end_address": 82593, + "mem_region_0_security_id_lsb": 0, + "mem_otfde_region_0_write_lock_en": false, + "mem_otfde_region_0_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_1_protection": { + "mem_region_1_enabled": true, + "mem_region_1_device_id": 0, + "mem_region_1_spi_write_enable": true, + "mem_region_1_spi_read_enable": true, + "mem_region_1_physical_offset": 0, + "mem_region_1_security_id_msb": 0, + "mem_region_1_start_address": 655360, + "mem_region_1_end_address": 656059, + "mem_region_1_security_id_lsb": 0, + "mem_otfde_region_1_write_lock_en": false, + "mem_otfde_region_1_enc_dec_bypass": "Bypass" + }, + "region_2_protection": { + "mem_region_2_enabled": true, + "mem_region_2_device_id": 0, + "mem_region_2_spi_write_enable": true, + "mem_region_2_spi_read_enable": true, + "mem_region_2_physical_offset": 1374, + "mem_region_2_security_id_msb": 0, + "mem_region_2_start_address": 671744, + "mem_region_2_end_address": 672417, + "mem_region_2_security_id_lsb": 0, + "mem_otfde_region_2_write_lock_en": false, + "mem_otfde_region_2_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_3_protection": { + "mem_region_3_enabled": false, + "mem_region_3_device_id": 1, + "mem_region_3_spi_write_enable": true, + "mem_region_3_spi_read_enable": true, + "mem_region_3_physical_offset": 0, + "mem_region_3_security_id_msb": 0, + "mem_region_3_start_address": 1, + "mem_region_3_end_address": 0, + "mem_region_3_security_id_lsb": 0, + "mem_otfde_region_3_write_lock_en": false, + "mem_otfde_region_3_enc_dec_bypass": "Bypass" + } + }, + "devices": { + "header": { + "flash_device_switch_conf": 1, + "ram_device_switch_conf": 1 + }, + "flash_switch": { + "flash_grant_sel": 0, + "flash_data_for_conf_0": 2181562505, + "flash_offset_bits_for_conf_0": 0, + "flash_stop_bit_for_conf_0": 0, + "flash_data_for_conf_1": 134357515, + "flash_offset_bits_for_conf_1": 1, + "flash_stop_bit_for_conf_1": 0, + "flash_data_for_conf_2": 139266, + "flash_offset_bits_for_conf_2": 2, + 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"ram_stop_bit_for_conf_16": 1, + "ram_data_for_conf_17": 0, + "ram_offset_bits_for_conf_17": 0, + "ram_stop_bit_for_conf_17": 1, + "ram_data_for_conf_18": 0, + "ram_offset_bits_for_conf_18": 0, + "ram_stop_bit_for_conf_18": 1, + "ram_data_for_conf_19": 0, + "ram_offset_bits_for_conf_19": 0, + "ram_stop_bit_for_conf_19": 1, + "ram_data_for_conf_20": 0, + "ram_offset_bits_for_conf_20": 0, + "ram_stop_bit_for_conf_20": 1, + "ram_data_for_conf_21": 0, + "ram_offset_bits_for_conf_21": 0, + "ram_stop_bit_for_conf_21": 1, + "ram_data_for_conf_22": 0, + "ram_offset_bits_for_conf_22": 0, + "ram_stop_bit_for_conf_22": 1, + "ram_data_for_conf_23": 0, + "ram_offset_bits_for_conf_23": 0, + "ram_stop_bit_for_conf_23": 1 + } + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/w25q64jw/flash_disc_param_xspi.json b/boards/ti/lp_em_cc35x1/config/flash/w25q64jw/flash_disc_param_xspi.json new file mode 100644 index 000000000000..e2981a0f06d2 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/w25q64jw/flash_disc_param_xspi.json @@ -0,0 +1,485 @@ +{ + "xspi_header": { + "name": "xSPIWFF3", + "device": "CC3500", + "use_hardware": "W25Q64JW", + "use_case": "Quadro", + "dqs_support": 0, + "flash_only": 1, + "flash_separate_reset": 0, + "ram_separate_reset": true, + "clock_frequency": 80, + "qospi_clock_divider": 1, + "flash_device_character_conf": 0, + "ram_device_character_conf": 0, + "header_advanced": 0, + "phy_mode_enable": 1, + "pipeline_mode_enable": 1, + "loopback_support": "No", + "qspi_ref_clock": 80, + "spi_clock_freq": 20, + "spi_clock_divider": 1, + "flash_device_size": 8, + "flash_bytes_per_block": 16, + "flash_bytes_per_page": 256, + "flash_number_of_address_bytes": 3, + "flash_dual_opcode": 0, + "flash_jedec_manufacturer_id": 0, + "flash_jedec_device_id": 0, + "flash_name": "W25Q64JW", + "flash_page_size": 256, + "flash_sector_size": 4096, + "flash_cs_polarity": "ACTIVE_LOW", + "flash_sw_reset_type": "x1xxxx", + "ram_device_size": 8, + "ram_bytes_per_block": 16, + "ram_bytes_per_page": 256, + "ram_number_of_address_bytes": 3, + "ram_dual_opcode": 0, + "ram_jedec_manufacturer_id": 0, + "ram_jedec_device_id": 0, + "ram_name": "NO_PSRAM", + "ram_page_size": 256, + "ram_sector_size": 4096, + "ram_cs_polarity": "ACTIVE_LOW", + "ram_sw_reset_type": "x1xxxx", + "flash_write_operation_modes": "4S-4S-4S", + "flash_read_operation_modes": "4S-4S-4S", + "ram_write_operation_modes": "4S-4S-4S", + "ram_read_operation_modes": "4S-4S-4S", + "crc_enable": 0, + "enable_dtr": 0, + "enable_ahb_decoder": 0, + "enter_xip_mod_immediately": 0, + "enter_xip_mod_next_read": 0, + "ahb_address_remapping": 0, + "enable_dma": 0, + "select_decode": 0, + "legacy_ip_mode": 0, + "direct_access": 1 + }, + "xspi_pinmux": { + "xspi_clk_input": 44, + "xspi_clk_input_use_hw": 0, + "xspi_clk_input_mode": "Input", + "xspi_clk_input_pull": "None", + "xspi_clk_input_interrupt_trigger": "Low", + "xspi_clk_input_dont_conf": 0, + "xspi_clk_input_output_strength": "High", + "xspi_clk_input_initial_output_state": "High", + "xspi_clk": 24, + "xspi_clk_use_hw": "None", + "xspi_clk_mode": "Output", + "xspi_clk_pull": "None", + "xspi_clk_output_strength": "High", + "xspi_clk_initial_output_state": "High", + "xspi_clk_interrupt_trigger": "None", + "xspi_clk_dont_conf": 0, + "xspi_flash_cs": 20, + "xspi_flash_cs_use_hw": "None", + "xspi_flash_cs_mode": "Output", + "xspi_flash_cs_pull": "None", + "xspi_flash_cs_output_strength": "High", + "xspi_flash_cs_initial_output_state": "High", + "xspi_flash_cs_interrupt_trigger": "None", + "xspi_flash_cs_dont_conf": 0, + "xspi_data_0": 25, + "xspi_data_0_use_hw": "None", + "xspi_data_0_mode": "Input", + "xspi_data_0_pull": "None", + "xspi_data_0_output_strength": "High", + "xspi_data_0_initial_output_state": "High", + "xspi_data_0_interrupt_trigger": "Low", + "xspi_data_0_dont_conf": 0, + "xspi_data_1": 21, + "xspi_data_1_use_hw": "None", + "xspi_data_1_mode": "Input", + "xspi_data_1_pull": "None", + "xspi_data_1_output_strength": "High", + "xspi_data_1_initial_output_state": "High", + "xspi_data_1_interrupt_trigger": "Low", + "xspi_data_1_dont_conf": 0, + "xspi_data_2": 22, + "xspi_data_2_use_hw": "None", + "xspi_data_2_mode": "Input", + "xspi_data_2_pull": "None", + "xspi_data_2_output_strength": "High", + "xspi_data_2_initial_output_state": "High", + "xspi_data_2_interrupt_trigger": "Low", + "xspi_data_2_dont_conf": 0, + "xspi_data_3": 23, + "xspi_data_3_use_hw": "None", + "xspi_data_3_mode": "Input", + "xspi_data_3_pull": "None", + "xspi_data_3_output_strength": "High", + "xspi_data_3_initial_output_state": "High", + "xspi_data_3_interrupt_trigger": "Low", + "xspi_data_3_dont_conf": 0, + "xspi_data_4": 26, + "xspi_data_4_use_hw": "None", + "xspi_data_4_mode": "Input", + "xspi_data_4_pull": "None", + "xspi_data_4_output_strength": "High", + "xspi_data_4_initial_output_state": "High", + "xspi_data_4_interrupt_trigger": "None", + "xspi_data_4_dont_conf": 0, + "xspi_data_5": 27, + "xspi_data_5_use_hw": "None", + "xspi_data_5_mode": "Input", + "xspi_data_5_pull": "None", + "xspi_data_5_output_strength": "High", + "xspi_data_5_initial_output_state": "High", + "xspi_data_5_interrupt_trigger": "None", + "xspi_data_5_dont_conf": 0, + "xspi_data_6": 28, + "xspi_data_6_use_hw": "None", + "xspi_data_6_mode": "Input", + "xspi_data_6_pull": "None", + "xspi_data_6_output_strength": "High", + "xspi_data_6_initial_output_state": "High", + "xspi_data_6_interrupt_trigger": "None", + "xspi_data_6_dont_conf": 0, + "xspi_data_7": 29, + "xspi_data_7_use_hw": "None", + "xspi_data_7_mode": "Input", + "xspi_data_7_pull": "None", + "xspi_data_7_output_strength": "High", + "xspi_data_7_initial_output_state": "High", + "xspi_data_7_interrupt_trigger": "None", + "xspi_data_7_dont_conf": 0, + "xspi_reset_flash": 36, + "xspi_reset_flash_use_hw": "None", + "xspi_reset_flash_mode": "Output", + "xspi_reset_flash_pull": "None", + "xspi_reset_flash_output_strength": "High", + "xspi_reset_flash_initial_output_state": "High", + "xspi_reset_flash_interrupt_trigger": "None", + "xspi_reset_flash_dont_conf": 0, + "xspi_cs_ram": 3, + "xspi_cs_ram_use_hw": "None", + "xspi_cs_ram_mode": "Output", + "xspi_cs_ram_pull": "None", + "xspi_cs_ram_output_strength": "High", + "xspi_cs_ram_initial_output_state": "High", + "xspi_cs_ram_interrupt_trigger": "None", + "xspi_cs_ram_dont_conf": 0, + "xspi_dqs": 30, + "xspi_dqs_use_hw": "None", + "xspi_dqs_mode": "Input", + "xspi_dqs_pull": "None", + "xspi_dqs_output_strength": "High", + "xspi_dqs_initial_output_state": "High", + "xspi_dqs_interrupt_trigger": "None", + "xspi_dqs_dont_conf": 0, + "xspi_reset_ram": 2, + "xspi_reset_ram_use_hw": "None", + "xspi_reset_ram_mode": "Input", + "xspi_reset_ram_pull": "None", + "xspi_reset_ram_output_strength": "High", + "xspi_reset_ram_initial_output_state": "High", + "xspi_reset_ram_interrupt_trigger": "None", + "xspi_reset_ram_dont_conf": 0 + }, + "xspi_operations": { + "xspi_operations_clocks": { + "clock_phase": 0, + "clock_polarity": 0, + "spi_mode": "2'b00" + }, + "xspi_operations_chip_select": { + "csda": 2, + "csdads": 0, + "cseot": 4, + "cssot": 1 + }, + "xspi_operations_reset": { + "flash_jedec_reset": 0, + "ram_jedec_reset": 0, + "flash_treset": 20, + "ram_treset": 20 + }, + "xspi_phy_operations": { + "flash_rx_dll_bypass_bit": 0, + "flash_dll_tx_delay": 61, + "flash_dll_rx_delay": 65, + "ram_rx_dll_bypass_bit": 0, + "ram_dll_tx_delay": 61, + "ram_dll_rx_delay": 65 + }, + "xspi_read_operations": { + "flash_dummy_rd_cycles": 8, + "flash_read_opcode": 11, + "suppl_flash_read_opcode": 0, + "ram_dummy_rd_cycles": 8, + "ram_read_opcode": 11, + "suppl_ram_read_opcode": 0, + "flash_non_cont_read_enable": 0, + "flash_max_read_jobs": 256, + "ram_non_cont_read_enable": 0, + "ram_max_read_jobs": 256, + "rww_en": 0, + "device_size": 8, + "number_of_banks": 1, + "bank_size": 8, + "mode_bit_enable": 0 + }, + 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"ram_octal_disable_opcode": 0, + "suppl_ram_octal_disable_opcode": 0 + } + } + }, + "external_memory_reporting": { + "header": { + "flash_auto_polling_enable": 1, + "flash_wel_enable": 1, + "flash_write_protect_enable": 0, + "flash_alternate_polling_conf_enable": 0, + "ram_auto_polling_enable": 1, + "ram_wel_enable": 1, + "ram_write_protect_enable": 0, + "ram_alternate_polling_conf_enable": 0 + }, + "flash_auto_polling": { + "flash_polling_repetition_delay": 0, + "flash_polling_count": 4, + "flash_enable_polling_expiration": 0, + "flash_polling_polarity": 0, + "flash_polling_address_phase_enable": 0, + "flash_polling_bit_index": 0, + "flash_numbers_poll_cycles": 65535, + "flash_dummy_autopoll_cycles": 0 + }, + "ram_auto_polling": { + "ram_polling_repetition_delay": 0, + "ram_polling_count": 4, + "ram_enable_polling_expiration": 0, + "ram_polling_polarity": 0, + "ram_polling_address_phase_enable": 0, + "ram_polling_bit_index": 0, + "ram_numbers_poll_cycles": 65535, + "ram_dummy_autopoll_cycles": 0 + }, + "flash_polling_command": { + "flash_polling_opcode": 5, + "suppl_flash_polling_opcode": 0 + }, + "ram_polling_command": { + "ram_polling_opcode": 5, + "suppl_ram_polling_opcode": 0 + }, + "flash_alternate_polling": { + "flash_polling_resp_count": 1023, + "flash_polling_iterations": 1, + "flash_polling_enabled": 0, + "flash_polling_disabled": 0, + "flash_grant_sel": 0, + "flash_data_for_enable_poling_conf_0": 0, + "flash_offset_bits_for_enable_poling_conf_0": 0, + "flash_stop_bit_for_enable_poling_conf_0": 1, + "flash_data_for_enable_poling_conf_1": 0, + "flash_offset_bits_for_enable_poling_conf_1": 0, + "flash_stop_bit_for_enable_poling_conf_1": 1, + "flash_data_for_disable_poling_conf_0": 0, + "flash_offset_bits_for_disable_poling_conf_0": 0, + "flash_stop_bit_for_disable_poling_conf_0": 1, + "flash_data_for_disable_poling_conf_1": 0, + "flash_offset_bits_for_disable_poling_conf_1": 0, + "flash_stop_bit_for_disable_poling_conf_1": 1 + }, + "ram_alternate_polling": { + "ram_polling_resp_count": 1023, + "ram_polling_iterations": 1, + "ram_polling_enabled": 0, + "ram_polling_disabled": 0, + "ram_grant_sel": 0, + "ram_data_for_enable_poling_conf_0": 0, + "ram_offset_bits_for_enable_poling_conf_0": 0, + "ram_stop_bit_for_enable_poling_conf_0": 1, + "ram_data_for_enable_poling_conf_1": 0, + "ram_offset_bits_for_enable_poling_conf_1": 0, + "ram_stop_bit_for_enable_poling_conf_1": 1, + "ram_data_for_disable_poling_conf_0": 0, + "ram_offset_bits_for_disable_poling_conf_0": 0, + "ram_stop_bit_for_disable_poling_conf_0": 1, + "ram_data_for_disable_poling_conf_1": 0, + "ram_offset_bits_for_disable_poling_conf_1": 0, + "ram_stop_bit_for_disable_poling_conf_1": 1 + }, + "flash_wel_command": { + "flash_wel_opcode": 6, + "suppl_flash_wel_opcode": 0 + }, + "ram_wel_command": { + "ram_wel_opcode": 6, + "suppl_ram_wel_opcode": 0 + } + }, + "event": { + "host_nvic_irq": 0, + "core_10_mux_sel": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/w25q64pw/flash_disc_param_ext_mem.json b/boards/ti/lp_em_cc35x1/config/flash/w25q64pw/flash_disc_param_ext_mem.json new file mode 100644 index 000000000000..6585853ccd5e --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/w25q64pw/flash_disc_param_ext_mem.json @@ -0,0 +1,99 @@ +{ + "vendor_primary_sbl": true, + "ti_wsoc_primary_container": true, + "ti_wsoc_bl2_primary_container": true, + "nvs_enable": true, + "vendor_alternate_image": true, + "vendor_sbl_alternate_image": true, + "ti_bl_alternate_image": true, + "ti_wsoc_alternate_image": true, + "ti_wsoc_bl2_alternate_image": true, + "region_0": { + "mem_region_0_start_phy_address": 2867200, + "mem_region_0_end_phy_address": 5627903, + "region0_boot": false, + "region0_main_code": true, + "region0_nvs": false, + "region0_wsoc_code": false, + "region0_alternate_code": false + }, + "region_1": { + "mem_region_1_start_phy_address": 0, + "mem_region_1_end_phy_address": 2867199, + "region1_boot": true, + "region1_main_code": false, + "region1_nvs": true, + "region1_wsoc_code": true, + "region1_alternate_code": false + }, + "region_2": { + "mem_region_2_start_phy_address": 5627904, + "mem_region_2_end_phy_address": 8388607, + "region2_boot": false, + "region2_main_code": false, + "region2_nvs": false, + "region2_wsoc_code": false, + "region2_alternate_code": true + }, + "region_3": { + "mem_region_3_start_phy_address": 0, + "mem_region_3_end_phy_address": 0, + "region3_boot": false, + "region3_main_code": false, + "region3_nvs": false, + "region3_wsoc_code": false, + "region3_alternate_code": false + }, + "boot_region_conf": { + "boot_region_size": 0, + "boot_region_flash_disco_param_start_address": 0, + "boot_region_primary_ti_bl_start_phy_address": 12284, + "boot_region_primary_ti_bl_magic": 0, + "boot_region_primary_ti_bl_major": 0, + "boot_region_primary_ti_bl_minor": 0, + "boot_region_sec_ti_bl_start_phy_address": 430076, + "boot_region_sec_ti_bl_magic": 0, + "boot_region_sec_ti_bl_major": 0, + "boot_region_sec_ti_bl_minor": 0 + }, + "main_code_region_conf": { + "main_code_region_vendor_image_start_phy_address": 2871292, + "main_code_region_vendor_image_magic": 0, + "main_code_region_vendor_image_major": 0, + "main_code_region_vendor_image_minor": 0, + "main_code_region_sbl_start_phy_address": 0, + "main_code_region_sbl_magic": 0, + "main_code_region_sbl_major": 0, + "main_code_region_sbl_minor": 0 + }, + "alt_code_region_conf": { + "alt_code_region_vendor_image_start_phy_address": 5631996, + "alt_code_region_vendor_image_magic": 0, + "alt_code_region_vendor_image_major": 0, + "alt_code_region_vendor_image_minor": 0, + "alt_code_region_sbl_start_phy_address": 0, + "alt_code_region_sbl_magic": 0, + "alt_code_region_sbl_major": 0, + "alt_code_region_sbl_minor": 0 + }, + "nvs_code_region_conf": { + "nvs_start_phy_address": 1777664, + "nvs_region_size": 1089536, + "nvs_region_primary_wsoc_start_phy_address": 847868, + "nvs_region_primary_wsoc_magic": 0, + "nvs_region_primary_wsoc_major": 0, + "nvs_region_primary_wsoc_minor": 0, + "nvs_region_sec_wsoc_start_phy_address": 1314812, + "nvs_region_sec_wsoc_magic": 0, + "nvs_region_sec_wsoc_major": 0, + "nvs_region_sec_wsoc_minor": 0, + "nvs_region_primary_wsoc_bl2_start_phy_address": 0, + "nvs_region_primary_wsoc_bl2_magic": 0, + "nvs_region_primary_wsoc_bl2_major": 0, + "nvs_region_primary_wsoc_bl2_minor": 0, + "nvs_region_sec_wsoc_bl2_start_phy_address": 0, + "nvs_region_sec_wsoc_bl2_magic": 0, + "nvs_region_sec_wsoc_bl2_major": 0, + "nvs_region_sec_wsoc_bl2_minor": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/w25q64pw/flash_disc_param_otfde.json b/boards/ti/lp_em_cc35x1/config/flash/w25q64pw/flash_disc_param_otfde.json new file mode 100644 index 000000000000..b0110e0b1ae7 --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/w25q64pw/flash_disc_param_otfde.json @@ -0,0 +1,286 @@ +{ + "otfde_header": { + "name": "OTFDEWFF3", + "flash_only": true, + "ip_protection": false, + "regions_lock": false, + "regions_number": 4, + "flash_enabled": true + }, + "bl_conf": { + "host_boot_done_lock": true, + "host_peripherals_lock": true, + "icache_conf_lock": true, + "m33_mem_part_lock": true, + "memss_firewall_lock": true, + "dma_channel_owner_lock": true, + "otfde_region_lock": true, + "core_events_lock": true + }, + "otfde_general": { + "parameters": { + "mem_otfde_initial_delay": 10, + "otfde_global_watchdog_timer": 5 + }, + "events": { + "reset_evt_mask": false, + "reset_evt_suspend": false, + "sft_reset_evt_mask": false, + "sft_reset_evt_suspend": false, + "bypass_mode_evt_mask": false, + "bypass_mode_evt_suspend": false, + "debug_mode_evt_mask": false, + "debug_mode_evt_suspend": false, + "general_evt_mask": false, + "general_evt_suspend": false, + "xspi_data_path_evt_mask": false, + "xspi_data_path_evt_suspend": false, + "xspi_cnfg_path_evt_mask": false, + "xspi_cnfg_path_evt_suspend": false, + "xspi_service_interrupt_evt_mask": false, + "xspi_service_interrupt_evt_suspend": false, + "trans_device_disabled_evt_mask": false, + "trans_device_disabled_evt_suspend": false, + "trans_region_disabled_evt_mask": false, + "trans_region_disabled_evt_suspend": false, + "trans_region_params_conf_evt_mask": false, + "trans_region_params_conf_evt_suspend": false, + "trans_multiple_regions_mapped_evt_mask": false, + "trans_multiple_regions_mapped_evt_suspend": false, + "trans_address_not_32_bit_evt_mask": false, + "trans_address_not_32_bit_evt_suspend": false, + "trans_size_not_32_bit_evt_mask": false, + "trans_size_not_32_bit_evt_suspend": false, + "trans_burst_not_32_bit_evt_mask": false, + "trans_burst_not_32_bit_evt_suspend": false, + "region_read_write_def_evt_mask": false, + "region_read_write_def_evt_suspend": false, + "suspend_while_disabled_evt_mask": false, + "suspend_while_disabled_evt_suspend": false + } + }, + "regions_settings": { + "region_parameters_lock": { + "REGION_0_PARAMS_0": true, + "REGION_0_PARAMS_1": true, + "REGION_0_PARAMS_2": true, + "REGION_1_PARAMS_0": false, + "REGION_1_PARAMS_1": false, + "REGION_1_PARAMS_2": false, + "REGION_2_PARAMS_0": true, + "REGION_2_PARAMS_1": true, + "REGION_2_PARAMS_2": true, + "REGION_3_PARAMS_0": false, + "REGION_3_PARAMS_1": false, + "REGION_3_PARAMS_2": false + }, + "region_0_protection": { + "mem_region_0_enabled": true, + "mem_region_0_device_id": 0, + "mem_region_0_spi_write_enable": true, + "mem_region_0_spi_read_enable": true, + "mem_region_0_physical_offset": 700, + "mem_region_0_security_id_msb": 0, + "mem_region_0_start_address": 81920, + "mem_region_0_end_address": 82593, + "mem_region_0_security_id_lsb": 0, + "mem_otfde_region_0_write_lock_en": false, + "mem_otfde_region_0_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_1_protection": { + "mem_region_1_enabled": true, + "mem_region_1_device_id": 0, + "mem_region_1_spi_write_enable": true, + "mem_region_1_spi_read_enable": true, + "mem_region_1_physical_offset": 0, + "mem_region_1_security_id_msb": 0, + "mem_region_1_start_address": 655360, + "mem_region_1_end_address": 656059, + "mem_region_1_security_id_lsb": 0, + "mem_otfde_region_1_write_lock_en": false, + "mem_otfde_region_1_enc_dec_bypass": "Bypass" + }, + "region_2_protection": { + "mem_region_2_enabled": true, + "mem_region_2_device_id": 0, + "mem_region_2_spi_write_enable": true, + "mem_region_2_spi_read_enable": true, + "mem_region_2_physical_offset": 1374, + "mem_region_2_security_id_msb": 0, + "mem_region_2_start_address": 671744, + "mem_region_2_end_address": 672417, + "mem_region_2_security_id_lsb": 0, + "mem_otfde_region_2_write_lock_en": false, + "mem_otfde_region_2_enc_dec_bypass": "EncryptOrDecrypt" + }, + "region_3_protection": { + "mem_region_3_enabled": false, + "mem_region_3_device_id": 1, + "mem_region_3_spi_write_enable": true, + "mem_region_3_spi_read_enable": true, + "mem_region_3_physical_offset": 0, + "mem_region_3_security_id_msb": 0, + "mem_region_3_start_address": 1, + "mem_region_3_end_address": 0, + "mem_region_3_security_id_lsb": 0, + "mem_otfde_region_3_write_lock_en": false, + "mem_otfde_region_3_enc_dec_bypass": "Bypass" + } + }, + "devices": { + "header": { + "flash_device_switch_conf": 1, + "ram_device_switch_conf": 1 + }, + "flash_switch": { + "flash_grant_sel": 0, + "flash_data_for_conf_0": 2181562505, + "flash_offset_bits_for_conf_0": 0, + "flash_stop_bit_for_conf_0": 0, + "flash_data_for_conf_1": 100803083, + "flash_offset_bits_for_conf_1": 1, + "flash_stop_bit_for_conf_1": 0, + "flash_data_for_conf_2": 139266, + "flash_offset_bits_for_conf_2": 2, + "flash_stop_bit_for_conf_2": 0, + "flash_data_for_conf_3": 1, + "flash_offset_bits_for_conf_3": 4, + "flash_stop_bit_for_conf_3": 0, + "flash_data_for_conf_4": 1076887634, + "flash_offset_bits_for_conf_4": 45, + "flash_stop_bit_for_conf_4": 0, + "flash_data_for_conf_5": 3224371282, + "flash_offset_bits_for_conf_5": 45, + "flash_stop_bit_for_conf_5": 0, + "flash_data_for_conf_6": 262149, + "flash_offset_bits_for_conf_6": 14, + "flash_stop_bit_for_conf_6": 0, + "flash_data_for_conf_7": 0, + "flash_offset_bits_for_conf_7": 44, + "flash_stop_bit_for_conf_7": 1, + "flash_data_for_conf_8": 0, + "flash_offset_bits_for_conf_8": 0, + "flash_stop_bit_for_conf_8": 1, + "flash_data_for_conf_9": 0, + "flash_offset_bits_for_conf_9": 0, + "flash_stop_bit_for_conf_9": 1, + "flash_data_for_conf_10": 0, + "flash_offset_bits_for_conf_10": 0, + "flash_stop_bit_for_conf_10": 1, + "flash_data_for_conf_11": 0, + "flash_offset_bits_for_conf_11": 0, + "flash_stop_bit_for_conf_11": 1, + "flash_data_for_conf_12": 0, + "flash_offset_bits_for_conf_12": 0, + "flash_stop_bit_for_conf_12": 1, + "flash_data_for_conf_13": 0, + "flash_offset_bits_for_conf_13": 0, + "flash_stop_bit_for_conf_13": 1, + "flash_data_for_conf_14": 0, + "flash_offset_bits_for_conf_14": 0, + "flash_stop_bit_for_conf_14": 1, + "flash_data_for_conf_15": 0, + "flash_offset_bits_for_conf_15": 0, + "flash_stop_bit_for_conf_15": 1, + "flash_data_for_conf_16": 0, + "flash_offset_bits_for_conf_16": 0, + "flash_stop_bit_for_conf_16": 1, + "flash_data_for_conf_17": 0, + "flash_offset_bits_for_conf_17": 0, + "flash_stop_bit_for_conf_17": 1, + "flash_data_for_conf_18": 0, + "flash_offset_bits_for_conf_18": 0, + "flash_stop_bit_for_conf_18": 1, + "flash_data_for_conf_19": 0, + "flash_offset_bits_for_conf_19": 0, + "flash_stop_bit_for_conf_19": 1, + "flash_data_for_conf_20": 0, + "flash_offset_bits_for_conf_20": 0, + "flash_stop_bit_for_conf_20": 1, + "flash_data_for_conf_21": 0, + "flash_offset_bits_for_conf_21": 0, + "flash_stop_bit_for_conf_21": 1, + "flash_data_for_conf_22": 0, + "flash_offset_bits_for_conf_22": 0, + "flash_stop_bit_for_conf_22": 1, + "flash_data_for_conf_23": 0, + "flash_offset_bits_for_conf_23": 0, + "flash_stop_bit_for_conf_23": 1 + }, + "ram_switch": { + "ram_grant_sel": 0, + "ram_data_for_conf_0": 2181563529, + "ram_offset_bits_for_conf_0": 0, + "ram_stop_bit_for_conf_0": 0, + "ram_data_for_conf_1": 100803307, + "ram_offset_bits_for_conf_1": 1, + "ram_stop_bit_for_conf_1": 0, + "ram_data_for_conf_2": 139320, + "ram_offset_bits_for_conf_2": 2, + "ram_stop_bit_for_conf_2": 0, + "ram_data_for_conf_3": 3089693184, + "ram_offset_bits_for_conf_3": 56, + "ram_stop_bit_for_conf_3": 0, + "ram_data_for_conf_4": 1, + "ram_offset_bits_for_conf_4": 4, + "ram_stop_bit_for_conf_4": 0, + "ram_data_for_conf_5": 1076494399, + "ram_offset_bits_for_conf_5": 45, + "ram_stop_bit_for_conf_5": 0, + "ram_data_for_conf_6": 3223978047, + "ram_offset_bits_for_conf_6": 45, + "ram_stop_bit_for_conf_6": 0, + "ram_data_for_conf_7": 278533, + "ram_offset_bits_for_conf_7": 14, + "ram_stop_bit_for_conf_7": 0, + "ram_data_for_conf_8": 0, + "ram_offset_bits_for_conf_8": 44, + "ram_stop_bit_for_conf_8": 1, + "ram_data_for_conf_9": 0, + "ram_offset_bits_for_conf_9": 0, + "ram_stop_bit_for_conf_9": 1, + "ram_data_for_conf_10": 0, + "ram_offset_bits_for_conf_10": 0, + "ram_stop_bit_for_conf_10": 1, + "ram_data_for_conf_11": 0, + "ram_offset_bits_for_conf_11": 0, + "ram_stop_bit_for_conf_11": 1, + "ram_data_for_conf_12": 0, + "ram_offset_bits_for_conf_12": 0, + "ram_stop_bit_for_conf_12": 1, + "ram_data_for_conf_13": 0, + "ram_offset_bits_for_conf_13": 0, + "ram_stop_bit_for_conf_13": 1, + "ram_data_for_conf_14": 0, + "ram_offset_bits_for_conf_14": 0, + "ram_stop_bit_for_conf_14": 1, + "ram_data_for_conf_15": 0, + "ram_offset_bits_for_conf_15": 0, + "ram_stop_bit_for_conf_15": 1, + "ram_data_for_conf_16": 0, + "ram_offset_bits_for_conf_16": 0, + "ram_stop_bit_for_conf_16": 1, + "ram_data_for_conf_17": 0, + "ram_offset_bits_for_conf_17": 0, + "ram_stop_bit_for_conf_17": 1, + "ram_data_for_conf_18": 0, + "ram_offset_bits_for_conf_18": 0, + "ram_stop_bit_for_conf_18": 1, + "ram_data_for_conf_19": 0, + "ram_offset_bits_for_conf_19": 0, + "ram_stop_bit_for_conf_19": 1, + "ram_data_for_conf_20": 0, + "ram_offset_bits_for_conf_20": 0, + "ram_stop_bit_for_conf_20": 1, + "ram_data_for_conf_21": 0, + "ram_offset_bits_for_conf_21": 0, + "ram_stop_bit_for_conf_21": 1, + "ram_data_for_conf_22": 0, + "ram_offset_bits_for_conf_22": 0, + "ram_stop_bit_for_conf_22": 1, + "ram_data_for_conf_23": 0, + "ram_offset_bits_for_conf_23": 0, + "ram_stop_bit_for_conf_23": 1 + } + } +} diff --git a/boards/ti/lp_em_cc35x1/config/flash/w25q64pw/flash_disc_param_xspi.json b/boards/ti/lp_em_cc35x1/config/flash/w25q64pw/flash_disc_param_xspi.json new file mode 100644 index 000000000000..53c8328e751c --- /dev/null +++ b/boards/ti/lp_em_cc35x1/config/flash/w25q64pw/flash_disc_param_xspi.json @@ -0,0 +1,485 @@ +{ + "xspi_header": { + "name": "xSPIWFF3", + "device": "CC3500", + "use_hardware": "W25Q64PW", + "use_case": "Quadro", + "dqs_support": 0, + "flash_only": 1, + "flash_separate_reset": 0, + "ram_separate_reset": true, + "clock_frequency": 80, + "qospi_clock_divider": 1, + "flash_device_character_conf": 0, + "ram_device_character_conf": 0, + "header_advanced": 0, + "phy_mode_enable": 1, + "pipeline_mode_enable": 1, + "loopback_support": "No", + "qspi_ref_clock": 80, + "spi_clock_freq": 20, + "spi_clock_divider": 1, + "flash_device_size": 8, + "flash_bytes_per_block": 16, + "flash_bytes_per_page": 256, + "flash_number_of_address_bytes": 3, + "flash_dual_opcode": 0, + "flash_jedec_manufacturer_id": 0, + "flash_jedec_device_id": 32791, + "flash_name": "W25Q64PW", + "flash_page_size": 256, + "flash_sector_size": 4096, + "flash_cs_polarity": "ACTIVE_LOW", + "flash_sw_reset_type": "x1xxxx", + "ram_device_size": 8, + "ram_bytes_per_block": 16, + "ram_bytes_per_page": 256, + "ram_number_of_address_bytes": 3, + "ram_dual_opcode": 0, + "ram_jedec_manufacturer_id": 0, + "ram_jedec_device_id": 32791, + "ram_name": "NO_PSRAM", + "ram_page_size": 256, + "ram_sector_size": 4096, + "ram_cs_polarity": "ACTIVE_LOW", + "ram_sw_reset_type": "x1xxxx", + "flash_write_operation_modes": "4S-4S-4S", + "flash_read_operation_modes": "4S-4S-4S", + "ram_write_operation_modes": "4S-4S-4S", + "ram_read_operation_modes": "4S-4S-4S", + "crc_enable": 0, + "enable_dtr": 0, + "enable_ahb_decoder": 0, + "enter_xip_mod_immediately": 0, + "enter_xip_mod_next_read": 0, + "ahb_address_remapping": 0, + "enable_dma": 0, + "select_decode": 0, + "legacy_ip_mode": 0, + "direct_access": 1 + }, + "xspi_pinmux": { + "xspi_clk_input": 44, + "xspi_clk_input_use_hw": 0, + "xspi_clk_input_mode": "Input", + "xspi_clk_input_pull": "None", + "xspi_clk_input_interrupt_trigger": "Low", + "xspi_clk_input_dont_conf": 0, + "xspi_clk_input_output_strength": "High", + "xspi_clk_input_initial_output_state": "High", + "xspi_clk": 24, + "xspi_clk_use_hw": "None", + "xspi_clk_mode": "Output", + "xspi_clk_pull": "None", + "xspi_clk_output_strength": "High", + "xspi_clk_initial_output_state": "High", + "xspi_clk_interrupt_trigger": "None", + "xspi_clk_dont_conf": 0, + "xspi_flash_cs": 20, + "xspi_flash_cs_use_hw": "None", + "xspi_flash_cs_mode": "Output", + "xspi_flash_cs_pull": "None", + "xspi_flash_cs_output_strength": "High", + "xspi_flash_cs_initial_output_state": "High", + "xspi_flash_cs_interrupt_trigger": "None", + "xspi_flash_cs_dont_conf": 0, + "xspi_data_0": 25, + "xspi_data_0_use_hw": "None", + "xspi_data_0_mode": "Input", + "xspi_data_0_pull": "None", + "xspi_data_0_output_strength": "High", + "xspi_data_0_initial_output_state": "High", + "xspi_data_0_interrupt_trigger": "Low", + "xspi_data_0_dont_conf": 0, + "xspi_data_1": 21, + "xspi_data_1_use_hw": "None", + "xspi_data_1_mode": "Input", + "xspi_data_1_pull": "None", + "xspi_data_1_output_strength": "High", + "xspi_data_1_initial_output_state": "High", + "xspi_data_1_interrupt_trigger": "Low", + "xspi_data_1_dont_conf": 0, + "xspi_data_2": 22, + "xspi_data_2_use_hw": "None", + "xspi_data_2_mode": "Input", + "xspi_data_2_pull": "None", + "xspi_data_2_output_strength": "High", + "xspi_data_2_initial_output_state": "High", + "xspi_data_2_interrupt_trigger": "Low", + "xspi_data_2_dont_conf": 0, + "xspi_data_3": 23, + "xspi_data_3_use_hw": "None", + "xspi_data_3_mode": "Input", + "xspi_data_3_pull": "None", + "xspi_data_3_output_strength": "High", + "xspi_data_3_initial_output_state": "High", + "xspi_data_3_interrupt_trigger": "Low", + "xspi_data_3_dont_conf": 0, + "xspi_data_4": 26, + "xspi_data_4_use_hw": "None", + "xspi_data_4_mode": "Input", + "xspi_data_4_pull": "None", + "xspi_data_4_output_strength": "High", + "xspi_data_4_initial_output_state": "High", + "xspi_data_4_interrupt_trigger": "None", + "xspi_data_4_dont_conf": 0, + "xspi_data_5": 27, + "xspi_data_5_use_hw": "None", + "xspi_data_5_mode": "Input", + "xspi_data_5_pull": "None", + "xspi_data_5_output_strength": "High", + "xspi_data_5_initial_output_state": "High", + "xspi_data_5_interrupt_trigger": "None", + "xspi_data_5_dont_conf": 0, + "xspi_data_6": 28, + "xspi_data_6_use_hw": "None", + "xspi_data_6_mode": "Input", + "xspi_data_6_pull": "None", + "xspi_data_6_output_strength": "High", + "xspi_data_6_initial_output_state": "High", + "xspi_data_6_interrupt_trigger": "None", + "xspi_data_6_dont_conf": 0, + "xspi_data_7": 29, + "xspi_data_7_use_hw": "None", + "xspi_data_7_mode": "Input", + "xspi_data_7_pull": "None", + "xspi_data_7_output_strength": "High", + "xspi_data_7_initial_output_state": "High", + "xspi_data_7_interrupt_trigger": "None", + "xspi_data_7_dont_conf": 0, + "xspi_reset_flash": 36, + "xspi_reset_flash_use_hw": "None", + "xspi_reset_flash_mode": "Output", + "xspi_reset_flash_pull": "None", + "xspi_reset_flash_output_strength": "High", + "xspi_reset_flash_initial_output_state": "High", + "xspi_reset_flash_interrupt_trigger": "None", + "xspi_reset_flash_dont_conf": 0, + "xspi_cs_ram": 3, + "xspi_cs_ram_use_hw": "None", + "xspi_cs_ram_mode": "Output", + "xspi_cs_ram_pull": "None", + "xspi_cs_ram_output_strength": "High", + "xspi_cs_ram_initial_output_state": "High", + "xspi_cs_ram_interrupt_trigger": "None", + "xspi_cs_ram_dont_conf": 0, + "xspi_dqs": 30, + "xspi_dqs_use_hw": "None", + "xspi_dqs_mode": "Input", + "xspi_dqs_pull": "None", + "xspi_dqs_output_strength": "High", + "xspi_dqs_initial_output_state": "High", + "xspi_dqs_interrupt_trigger": "None", + "xspi_dqs_dont_conf": 0, + "xspi_reset_ram": 2, + "xspi_reset_ram_use_hw": "None", + "xspi_reset_ram_mode": "Input", + "xspi_reset_ram_pull": "None", + "xspi_reset_ram_output_strength": "High", + "xspi_reset_ram_initial_output_state": "High", + "xspi_reset_ram_interrupt_trigger": "None", + "xspi_reset_ram_dont_conf": 0 + }, + "xspi_operations": { + "xspi_operations_clocks": { + "clock_phase": 0, + "clock_polarity": 0, + "spi_mode": "2'b00" + }, + "xspi_operations_chip_select": { + "csda": 2, + "csdads": 0, + "cseot": 4, + "cssot": 1 + }, + "xspi_operations_reset": { + "flash_jedec_reset": 0, + "ram_jedec_reset": 0, + "flash_treset": 20, + "ram_treset": 20 + }, + "xspi_phy_operations": { + "flash_rx_dll_bypass_bit": 0, + "flash_dll_tx_delay": 61, + "flash_dll_rx_delay": 65, + "ram_rx_dll_bypass_bit": 0, + "ram_dll_tx_delay": 61, + "ram_dll_rx_delay": 65 + }, + "xspi_read_operations": { + "flash_dummy_rd_cycles": 6, + "flash_read_opcode": 11, + "suppl_flash_read_opcode": 0, + "ram_dummy_rd_cycles": 8, + "ram_read_opcode": 11, + "suppl_ram_read_opcode": 0, + "flash_non_cont_read_enable": 0, + "flash_max_read_jobs": 256, + "ram_non_cont_read_enable": 0, + "ram_max_read_jobs": 256, + "rww_en": 0, + "device_size": 8, + "number_of_banks": 1, + "bank_size": 8, + "mode_bit_enable": 0 + }, + "xspi_write_operations": { + "flash_address_and_data": { + "flash_dummy_wr_cycles": 0 + }, + "flash_command": { + "flash_write_opcode": 2, + "suppl_flash_write_opcode": 0 + }, + "ram_address_and_data": { + "ram_dummy_wr_cycles": 0 + }, + "ram_command": { + "ram_write_opcode": 2, + "suppl_ram_write_opcode": 0 + }, + "write_to_buffer": { + "flash_write_to_buffer_support": 0, + "ram_write_to_buffer_support": 0 + }, + "non_continuous_write": { + "flash_non_cont_write_enable": 0, + "flash_max_write_jobs": 64, + "ram_non_cont_write_enable": 0, + "ram_max_write_jobs": 0 + }, + "flash_program_operation": { + "flash_min_program_size": "256 B", + "flash_program_opcode": 2, + "suppl_flash_program_opcode": 0, + "flash_maximum_program_time_limit": 1600 + }, + "flash_erase_operation": { + "flash_min_erase_size": "4 kB", + "flash_erase_opcode": 32, + "suppl_flash_erase_opcode": 0, + "flash_maximum_erase_time_limit": 4095 + }, + "flash_erase_conf": { + "flash_block_erase_opcode": 0, + "suppl_block_flash_erase_opcode": 0, + "flash_sector_erase_opcode": 0, + "suppl_sector_flash_erase_opcode": 0, + "flash_chip_erase_opcode": 0, + "suppl_chip_flash_erase_opcode": 0 + }, + "ram_program_operation": { + "ram_min_program_size": "256 B", + "ram_program_opcode": 2, + "suppl_ram_program_opcode": 0, + "ram_maximum_program_time_limit": 1600 + }, + "ram_erase_conf": { + "ram_block_erase_opcode": 0, + "suppl_block_ram_erase_opcode": 0, + "ram_sector_erase_opcode": 0, + "suppl_sector_ram_erase_opcode": 0, + "ram_chip_erase_opcode": 0, + "suppl_chip_ram_erase_opcode": 0 + }, + "flash_buffer_support": { + "flash_pre_write_sequence": 0, + "flash_post_write_sequence": 0, + "flash_write_protection_timer_en": 0, + "flash_write_buffer_timer_mode": 16, + "flash_write_buffer_timer_range": 0, + "flash_service_interrupt_criteria": 0 + }, + "ram_buffer_support": { + "ram_pre_write_sequence": 0, + "ram_post_write_sequence": 0, + "ram_write_protection_timer_en": 0, + "ram_write_buffer_timer_mode": 16, + "ram_write_buffer_timer_range": 0, + "ram_service_interrupt_criteria": 0 + }, + "flash_pre_write_conf": { + "flash_pre_write_job_done_grant_sel": 0, + "data_for_flash_pre_write_conf_0": 0, + "offset_bits_for_flash_pre_write_conf_0": 0, + "stop_bit_for_flash_pre_write_conf_0": 1, + "data_for_flash_pre_write_conf_1": 0, + "offset_bits_for_flash_pre_write_conf_1": 0 + }, + "flash_post_write_conf": { + "flash_post_write_job_done_grant_sel": 0, + "data_for_flash_post_write_conf_0": 0, + "offset_bits_for_flash_post_write_conf_0": 0, + "stop_bit_for_flash_post_write_conf_0": 1, + "data_for_flash_post_write_conf_1": 0, + "offset_bits_for_flash_post_write_conf_1": 0 + }, + "ram_pre_write_conf": { + "ram_pre_write_job_done_grant_sel": 0, + "data_for_ram_pre_write_conf_0": 0, + "offset_bits_for_ram_pre_write_conf_0": 0, + "stop_bit_for_ram_pre_write_conf_0": 1, + "data_for_ram_pre_write_conf_1": 0, + "offset_bits_for_ram_pre_write_conf_1": 0 + }, + "ram_post_write_conf": { + "ram_post_write_job_done_grant_sel": 0, + "data_for_ram_post_write_conf_0": 0, + "offset_bits_for_ram_post_write_conf_0": 0, + "stop_bit_for_ram_post_write_conf_0": 1, + "data_for_ram_post_write_conf_1": 0, + "offset_bits_for_ram_post_write_conf_1": 0 + } + }, + "xspi_capture_operations": { + "read_data_capture": { + "flash_delay_transmitted_data": 0, + "flash_loopback_clock": 0, + "flash_bypass_adapted_loopback": 1, + "flash_sample_edge_sel": 0, + "ram_delay_transmitted_data": 0, + "ram_loopback_clock": 0, + "ram_bypass_adapted_loopback": 1, + "ram_sample_edge_sel": 0 + }, + "delays": { + "flash_full_half_cycle_delay": 0, + "flash_dll_bypass_mode": 1, + "flash_phase_detect_sel": 0, + "flash_dll_lock_num": 0, + "flash_dll_start_point": 0, + "flash_loopback_clock": 0, + "ram_full_half_cycle_delay": 0, + "ram_dll_bypass_mode": 1, + "ram_phase_detect_sel": 0, + "ram_dll_lock_num": 0, + "ram_dll_start_point": 0, + "ram_loopback_clock": 0 + }, + "operation_modes": { + "flash_sfdp_support": 0, + "ram_sfdp_support": 0, + "flash_pm_support": 0, + "ram_pm_support": 0, + "flash_sfdp_opcode": 0, + "suppl_flash_sfdp_opcode": 0, + "ram_sfdp_opcode": 0, + "suppl_ram_sfdp_opcode": 0, + "flash_enter_dpd_opcode": 185, + "suppl_flash_enter_dpd_opcode": 0, + "flash_exit_dpd_opcode": 171, + "suppl_flash_exit_dpd_opcode": 0, + "ram_enter_dpd_opcode": 185, + "suppl_ram_enter_dpd_opcode": 0, + "ram_exit_dpd_opcode": 171, + "suppl_ram_exit_dpd_opcode": 0, + "flash_quad_enable_opcode": 56, + "suppl_flash_quad_enable_opcode": 0, + "flash_quad_disable_opcode": 255, + "suppl_flash_quad_disable_opcode": 0, + "flash_octal_enable_opcode": 0, + "suppl_flash_octal_enable_opcode": 0, + "flash_octal_disable_opcode": 0, + "suppl_flash_octal_disable_opcode": 0, + "ram_quad_enable_opcode": 56, + "suppl_ram_quad_enable_opcode": 0, + "ram_quad_disable_opcode": 255, + "suppl_ram_quad_disable_opcode": 0, + "ram_octal_enable_opcode": 0, + "suppl_ram_octal_enable_opcode": 0, + "ram_octal_disable_opcode": 0, + "suppl_ram_octal_disable_opcode": 0 + } + } + }, + "external_memory_reporting": { + "header": { + "flash_auto_polling_enable": 1, + "flash_wel_enable": 1, + "flash_write_protect_enable": 0, + "flash_alternate_polling_conf_enable": 0, + "ram_auto_polling_enable": 1, + "ram_wel_enable": 1, + "ram_write_protect_enable": 0, + "ram_alternate_polling_conf_enable": 0 + }, + "flash_auto_polling": { + "flash_polling_repetition_delay": 0, + "flash_polling_count": 4, + "flash_enable_polling_expiration": 0, + "flash_polling_polarity": 0, + "flash_polling_address_phase_enable": 0, + "flash_polling_bit_index": 0, + "flash_numbers_poll_cycles": 65535, + "flash_dummy_autopoll_cycles": 0 + }, + "ram_auto_polling": { + "ram_polling_repetition_delay": 0, + "ram_polling_count": 4, + "ram_enable_polling_expiration": 0, + "ram_polling_polarity": 0, + "ram_polling_address_phase_enable": 0, + "ram_polling_bit_index": 0, + "ram_numbers_poll_cycles": 65535, + "ram_dummy_autopoll_cycles": 0 + }, + "flash_polling_command": { + "flash_polling_opcode": 5, + "suppl_flash_polling_opcode": 0 + }, + "ram_polling_command": { + "ram_polling_opcode": 5, + "suppl_ram_polling_opcode": 0 + }, + "flash_alternate_polling": { + "flash_polling_resp_count": 1023, + "flash_polling_iterations": 1, + "flash_polling_enabled": 0, + "flash_polling_disabled": 0, + "flash_grant_sel": 0, + "flash_data_for_enable_poling_conf_0": 0, + "flash_offset_bits_for_enable_poling_conf_0": 0, + "flash_stop_bit_for_enable_poling_conf_0": 1, + "flash_data_for_enable_poling_conf_1": 0, + "flash_offset_bits_for_enable_poling_conf_1": 0, + "flash_stop_bit_for_enable_poling_conf_1": 1, + "flash_data_for_disable_poling_conf_0": 0, + "flash_offset_bits_for_disable_poling_conf_0": 0, + "flash_stop_bit_for_disable_poling_conf_0": 1, + "flash_data_for_disable_poling_conf_1": 0, + "flash_offset_bits_for_disable_poling_conf_1": 0, + "flash_stop_bit_for_disable_poling_conf_1": 1 + }, + "ram_alternate_polling": { + "ram_polling_resp_count": 1023, + "ram_polling_iterations": 1, + "ram_polling_enabled": 0, + "ram_polling_disabled": 0, + "ram_grant_sel": 0, + "ram_data_for_enable_poling_conf_0": 0, + "ram_offset_bits_for_enable_poling_conf_0": 0, + "ram_stop_bit_for_enable_poling_conf_0": 1, + "ram_data_for_enable_poling_conf_1": 0, + "ram_offset_bits_for_enable_poling_conf_1": 0, + "ram_stop_bit_for_enable_poling_conf_1": 1, + "ram_data_for_disable_poling_conf_0": 0, + "ram_offset_bits_for_disable_poling_conf_0": 0, + "ram_stop_bit_for_disable_poling_conf_0": 1, + "ram_data_for_disable_poling_conf_1": 0, + "ram_offset_bits_for_disable_poling_conf_1": 0, + "ram_stop_bit_for_disable_poling_conf_1": 1 + }, + "flash_wel_command": { + "flash_wel_opcode": 6, + "suppl_flash_wel_opcode": 0 + }, + "ram_wel_command": { + "ram_wel_opcode": 6, + "suppl_ram_wel_opcode": 0 + } + }, + "event": { + "host_nvic_irq": 0, + "core_10_mux_sel": 0 + } +} diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml b/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml index 2ca1fea8c79e..55af4d052712 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml @@ -3,7 +3,7 @@ name: TI SimpleLink™ CC35x1 LaunchPad type: mcu arch: arm ram: 1024 -flash: 8192 +flash: 4096 toolchain: - zephyr - gnuarmemb diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_8m.overlay b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_8m.overlay new file mode 100644 index 000000000000..70378e5a215b --- /dev/null +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_8m.overlay @@ -0,0 +1,67 @@ +&extflash_ns { + reg = <0x10000000 DT_SIZE_M(8)>; +}; + +&extflash { + reg = <0x14000000 DT_SIZE_M(8)>; +}; + +&flash0 { + reg = <0x14000000 0x544000>, <0x2bc000 0x544000>; + + partitions { + /delete-node/ partition@0; + + vendor_image_partition: partition@0 { + label = "vendor-image"; + reg = <0x0 0x544000>; + }; + }; +}; + +&flash1 { + reg = <0xa0000000 0x1b2000>, <0x0 0x1b2000>; + + partitions { + /delete-node/ partition@68000; + /delete-node/ partition@da000; + + wifi_fw_slot1_partition: partition@ce000 { + label = "wifi-fw-1"; + reg = <0xce000 0x72000>; + }; + + wifi_fw_slot2_partition: partition@140000 { + label = "wifi-fw-2"; + reg = <0x140000 0x72000>; + }; + }; +}; + +&{/soc} { + /delete-node/ flash@a00da000; + + flash2: flash@a01b2000 { + compatible = "ti,cc35xx-nv-flash"; + reg = <0xa01b2000 0x10a000>, <0x1b2000 0x10a000>; + erase-block-size = <0x1000>; + write-block-size = <0x4>; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + wifi_nvs_partition: partition@0 { + label = "wifi-nvs"; + reg = <0x0 0x8000>; + }; + + storage_partition: partition@8000 { + label = "storage"; + reg = <0x8000 0x102000>; + }; + }; + }; +}; diff --git a/dts/arm/ti/cc35xxe.dtsi b/dts/arm/ti/cc35xxe.dtsi index d5905c643906..1545a120e3fc 100644 --- a/dts/arm/ti/cc35xxe.dtsi +++ b/dts/arm/ti/cc35xxe.dtsi @@ -126,14 +126,14 @@ extflash_ns: extflash@10000000 { status = "disabled"; compatible = "zephyr,memory-region"; - reg = <0x10000000 DT_SIZE_M(64)>; + reg = <0x10000000 DT_SIZE_M(4)>; zephyr,memory-region = "EXTFLASH_NS"; }; extflash: extflash@14000000 { status = "disabled"; compatible = "zephyr,memory-region"; - reg = <0x14000000 DT_SIZE_M(64)>; + reg = <0x14000000 DT_SIZE_M(4)>; zephyr,memory-region = "EXTFLASH"; }; diff --git a/scripts/west_commands/runners/simplelink_toolbox.py b/scripts/west_commands/runners/simplelink_toolbox.py index 51c14a3be592..9fd0f2b5fcf1 100644 --- a/scripts/west_commands/runners/simplelink_toolbox.py +++ b/scripts/west_commands/runners/simplelink_toolbox.py @@ -21,7 +21,9 @@ def __init__(self, cfg, simplelink_tool): self.vendor_file = ( Path(cfg.build_dir) / 'zephyr' / 'flash' / 'vendor_image.sign.bin' ).resolve() - self.tool_setting_file = (Path(cfg.board_dir) / 'config' / 'tool_settings.json').resolve() + self.tool_setting_file = ( + Path(cfg.build_dir) / 'zephyr' / 'flash' / 'tool_settings.json' + ).resolve() self.programming_report_file = ( Path(self.cfg.build_dir) / 'simplelink_toolbox_report.txt' ).resolve() diff --git a/soc/ti/simplelink/cc35xxe/Kconfig.soc b/soc/ti/simplelink/cc35xxe/Kconfig.soc index 5cb65fa53eb4..682ac64c409b 100644 --- a/soc/ti/simplelink/cc35xxe/Kconfig.soc +++ b/soc/ti/simplelink/cc35xxe/Kconfig.soc @@ -67,12 +67,97 @@ config CC35XXE_FLASH_DISCOVERY_CONFIG_EXT_MEM config CC35XXE_FLASH_DISCOVERY_CONFIG_XSPI string "Path to the xSPI configuration file" +choice CC35XXE_FLASH_PROFILE_SELECT + prompt "External flash configuration profile" + default CC35XXE_FLASH_PROFILE_IS25WJ032F + help + Select the board flash profile used by the SimpleLink toolbox image + builder. The profile name maps to a directory under the board + config/flash directory. Explicit CC35XXE_FLASH_DISCOVERY_CONFIG_* + paths override this profile. + +config CC35XXE_FLASH_PROFILE_GD25LF32E + bool "gd25lf32e" + +config CC35XXE_FLASH_PROFILE_GD25LF64E + bool "gd25lf64e" + +config CC35XXE_FLASH_PROFILE_IS25WJ032F + bool "is25wj032f" + +config CC35XXE_FLASH_PROFILE_IS25WJ064F + bool "is25wj064f" + +config CC35XXE_FLASH_PROFILE_IS25WJ128F + bool "is25wj128f" + +config CC35XXE_FLASH_PROFILE_MX25U12843G + bool "mx25u12843g" + +config CC35XXE_FLASH_PROFILE_MX25U3235F + bool "mx25u3235f" + +config CC35XXE_FLASH_PROFILE_MX25U6435F + bool "mx25u6435f" + +config CC35XXE_FLASH_PROFILE_PY25Q128LA + bool "py25q128la" + +config CC35XXE_FLASH_PROFILE_PY25Q256LC + bool "py25q256lc" + +config CC35XXE_FLASH_PROFILE_PY25Q32LB + bool "py25q32lb" + +config CC35XXE_FLASH_PROFILE_PY25Q64LB + bool "py25q64lb" + +config CC35XXE_FLASH_PROFILE_W25Q12PW + bool "w25q12pw" + +config CC35XXE_FLASH_PROFILE_W25Q32JW + bool "w25q32jw" + +config CC35XXE_FLASH_PROFILE_W25Q33PW + bool "w25q33pw" + +config CC35XXE_FLASH_PROFILE_W25Q64JW + bool "w25q64jw" + +config CC35XXE_FLASH_PROFILE_W25Q64PW + bool "w25q64pw" + +endchoice + +config CC35XXE_FLASH_PROFILE + string + default "gd25lf32e" if CC35XXE_FLASH_PROFILE_GD25LF32E + default "gd25lf64e" if CC35XXE_FLASH_PROFILE_GD25LF64E + default "is25wj032f" if CC35XXE_FLASH_PROFILE_IS25WJ032F + default "is25wj064f" if CC35XXE_FLASH_PROFILE_IS25WJ064F + default "is25wj128f" if CC35XXE_FLASH_PROFILE_IS25WJ128F + default "mx25u12843g" if CC35XXE_FLASH_PROFILE_MX25U12843G + default "mx25u3235f" if CC35XXE_FLASH_PROFILE_MX25U3235F + default "mx25u6435f" if CC35XXE_FLASH_PROFILE_MX25U6435F + default "py25q128la" if CC35XXE_FLASH_PROFILE_PY25Q128LA + default "py25q256lc" if CC35XXE_FLASH_PROFILE_PY25Q256LC + default "py25q32lb" if CC35XXE_FLASH_PROFILE_PY25Q32LB + default "py25q64lb" if CC35XXE_FLASH_PROFILE_PY25Q64LB + default "w25q12pw" if CC35XXE_FLASH_PROFILE_W25Q12PW + default "w25q32jw" if CC35XXE_FLASH_PROFILE_W25Q32JW + default "w25q33pw" if CC35XXE_FLASH_PROFILE_W25Q33PW + default "w25q64jw" if CC35XXE_FLASH_PROFILE_W25Q64JW + default "w25q64pw" if CC35XXE_FLASH_PROFILE_W25Q64PW + config CC35XXE_FUSE_CONFIG string "Path to the fuse configuration file" config CC35XXE_ACTION_PARAMS_FILE string "Path to the action parameters file" +config CC35XXE_TOOL_SETTINGS_FILE + string "Path to the SimpleLink toolbox settings file" + config CC35XXE_CONF_INI_FILE string "Path to the cc35xx-conf.ini file" help diff --git a/soc/ti/simplelink/cc35xxe/toolbox.cmake b/soc/ti/simplelink/cc35xxe/toolbox.cmake index f9fde6183c9a..20cc40448f75 100644 --- a/soc/ti/simplelink/cc35xxe/toolbox.cmake +++ b/soc/ti/simplelink/cc35xxe/toolbox.cmake @@ -10,8 +10,10 @@ function(zephyr_simplelink_tasks) string(CONFIGURE "${CONFIG_CC35XXE_FLASH_DISCOVERY_CONFIG_OTFDE}" otfde) string(CONFIGURE "${CONFIG_CC35XXE_FLASH_DISCOVERY_CONFIG_EXT_MEM}" ext_mem) string(CONFIGURE "${CONFIG_CC35XXE_FLASH_DISCOVERY_CONFIG_XSPI}" xspi) + string(CONFIGURE "${CONFIG_CC35XXE_FLASH_PROFILE}" flash_profile) string(CONFIGURE "${CONFIG_CC35XXE_FUSE_CONFIG}" fuse_config) string(CONFIGURE "${CONFIG_CC35XXE_ACTION_PARAMS_FILE}" action_params) + string(CONFIGURE "${CONFIG_CC35XXE_TOOL_SETTINGS_FILE}" tool_settings) # Use default keys if not set if("${pubkey}" STREQUAL "") @@ -31,8 +33,14 @@ function(zephyr_simplelink_tasks) endif() # Use default config jsons if not set + if("${flash_profile}" STREQUAL "") + set(flash_profile "is25wj032f") + endif() + + set(flash_profile_dir "${BOARD_DIR}/config/flash/${flash_profile}") + if("${otfde}" STREQUAL "") - set(otfde "${BOARD_DIR}/config/flash_disc_param_otfde.json") + set(otfde "${flash_profile_dir}/flash_disc_param_otfde.json") endif() if(NOT EXISTS "${otfde}") @@ -40,7 +48,7 @@ function(zephyr_simplelink_tasks) endif() if("${ext_mem}" STREQUAL "") - set(ext_mem "${BOARD_DIR}/config/flash_disc_param_ext_mem.json") + set(ext_mem "${flash_profile_dir}/flash_disc_param_ext_mem.json") endif() if(NOT EXISTS "${ext_mem}") @@ -48,7 +56,7 @@ function(zephyr_simplelink_tasks) endif() if("${xspi}" STREQUAL "") - set(xspi "${BOARD_DIR}/config/flash_disc_param_xspi.json") + set(xspi "${flash_profile_dir}/flash_disc_param_xspi.json") endif() if(NOT EXISTS "${xspi}") @@ -71,17 +79,30 @@ function(zephyr_simplelink_tasks) message(FATAL_ERROR "Action parameters file not found: ${action_params}") endif() + if("${tool_settings}" STREQUAL "") + set(tool_settings "${BOARD_DIR}/config/tool_settings.json") + endif() + + if(NOT EXISTS "${tool_settings}") + message(FATAL_ERROR "Tool settings file not found: ${tool_settings}") + endif() + set(outdir ${ZEPHYR_BINARY_DIR}/flash) set(output ${ZEPHYR_BINARY_DIR}/${KERNEL_NAME}) + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND + ${CMAKE_COMMAND} -E make_directory ${outdir}) + + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND + ${CMAKE_COMMAND} -E copy ${tool_settings} ${outdir}/tool_settings.json) + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND simplelink-wifi-toolbox flash-images-builder build programming_image --flash_discovery_config_otfde ${otfde} --flash_discovery_config_ext_mem ${ext_mem} --flash_discovery_config_xspi ${xspi} --fuses_programming_instructions ${fuse_config} - --dir_out_path ${outdir} - --use_my_jsons) + --dir_out_path ${outdir}) set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND simplelink-wifi-toolbox flash-images-builder sign programming_image @@ -146,7 +167,8 @@ function(zephyr_simplelink_tasks) "${outdir}/programming_instructions_image.sign.bin" "${outdir}/programming_action_request.sign.bin" "${outdir}/debug_action_request.sign.bin" - "${outdir}/vendor_image.sign.bin") + "${outdir}/vendor_image.sign.bin" + "${outdir}/tool_settings.json") endfunction() zephyr_simplelink_tasks() From cd45bbe9db2537be5be3e88a9481c1877aa0ac78 Mon Sep 17 00:00:00 2001 From: Jakub Jarosinski Date: Fri, 24 Jul 2026 15:30:42 +0200 Subject: [PATCH 022/100] UPSTREAM-PEND: boards: ti: default CC35xx test target Map the legacy board name to the CC3551E target and update CC35xx test metadata to use the explicit target. Signed-off-by: Jakub Jarosinski --- boards/deprecated.cmake | 4 ++++ .../{lp_em_cc35x1.overlay => lp_em_cc35x1_cc3551e.overlay} | 0 .../{lp_em_cc35x1.overlay => lp_em_cc35x1_cc3551e.overlay} | 0 tests/drivers/gpio/gpio_hogs/testcase.yaml | 2 +- 4 files changed, 5 insertions(+), 1 deletion(-) rename tests/drivers/gpio/gpio_basic_api/boards/{lp_em_cc35x1.overlay => lp_em_cc35x1_cc3551e.overlay} (100%) rename tests/drivers/gpio/gpio_hogs/boards/{lp_em_cc35x1.overlay => lp_em_cc35x1_cc3551e.overlay} (100%) diff --git a/boards/deprecated.cmake b/boards/deprecated.cmake index 3277b7540fb4..68263d829dd5 100644 --- a/boards/deprecated.cmake +++ b/boards/deprecated.cmake @@ -13,6 +13,10 @@ # https://docs.zephyrproject.org/latest/develop/api/api_lifecycle.html#deprecated, # so these aliases are eventually removed +set(lp_em_cc35x1/_DEPRECATED + lp_em_cc35x1/cc3551e +) + set(arduino_uno_r4_minima_DEPRECATED arduino_uno_r4@minima ) diff --git a/tests/drivers/gpio/gpio_basic_api/boards/lp_em_cc35x1.overlay b/tests/drivers/gpio/gpio_basic_api/boards/lp_em_cc35x1_cc3551e.overlay similarity index 100% rename from tests/drivers/gpio/gpio_basic_api/boards/lp_em_cc35x1.overlay rename to tests/drivers/gpio/gpio_basic_api/boards/lp_em_cc35x1_cc3551e.overlay diff --git a/tests/drivers/gpio/gpio_hogs/boards/lp_em_cc35x1.overlay b/tests/drivers/gpio/gpio_hogs/boards/lp_em_cc35x1_cc3551e.overlay similarity index 100% rename from tests/drivers/gpio/gpio_hogs/boards/lp_em_cc35x1.overlay rename to tests/drivers/gpio/gpio_hogs/boards/lp_em_cc35x1_cc3551e.overlay diff --git a/tests/drivers/gpio/gpio_hogs/testcase.yaml b/tests/drivers/gpio/gpio_hogs/testcase.yaml index 978cfe063a58..b6402ea6529c 100644 --- a/tests/drivers/gpio/gpio_hogs/testcase.yaml +++ b/tests/drivers/gpio/gpio_hogs/testcase.yaml @@ -23,7 +23,7 @@ tests: - s32z2xxdc2/s32z270/rtu1 - s32z2xxdc2@D/s32z270/rtu0 - s32z2xxdc2@D/s32z270/rtu1 - - lp_em_cc35x1 + - lp_em_cc35x1/cc3551e - xg29_rb4412a - bg29_rb4420a - sam_e54_xpro From 56eb932d674f2c98bfaf449a3833b58a3e0eff52 Mon Sep 17 00:00:00 2001 From: Jakub Jarosinski Date: Tue, 7 Jul 2026 16:21:59 +0200 Subject: [PATCH 023/100] UPSTREAM-PEND: soc: dts: ti: cc35xxe: update SoC config for PG2 Provide SoC and Device Tree updates for PG2 boards. Signed-off-by: Jakub Jarosinski --- .../ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi | 4 +++ dts/arm/ti/cc35xxe.dtsi | 26 +++++++++++++------ 2 files changed, 22 insertions(+), 8 deletions(-) diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi index 0a4d1062b6bd..4e185e6dced2 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi @@ -66,6 +66,10 @@ status = "okay"; }; +&dmem_shared { + status = "okay"; +}; + &dmem_ns { status = "okay"; }; diff --git a/dts/arm/ti/cc35xxe.dtsi b/dts/arm/ti/cc35xxe.dtsi index 1545a120e3fc..ce949db2a49e 100644 --- a/dts/arm/ti/cc35xxe.dtsi +++ b/dts/arm/ti/cc35xxe.dtsi @@ -109,10 +109,17 @@ zephyr,memory-region = "DTCM"; }; - dmem_ns: dmem_ns@28000000 { + dmem_shared: dmem@28000000 { status = "disabled"; compatible = "zephyr,memory-region", "mmio-sram"; - reg = <0x28000000 DT_SIZE_K(256)>; + reg = <0x28000000 0xdb0>; + zephyr,memory-region = "DMEM_SHARED"; + }; + + dmem_ns: dmem_ns@28000db0 { + status = "disabled"; + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x28000db0 0x7f250>; zephyr,memory-region = "DMEM_NS"; }; @@ -199,25 +206,28 @@ }; }; - flash0: flash@a0000000 { + flash0: flash@14000000 { compatible = "ti,cc35xx-nv-flash"; - reg = <0xa0000000 0x00033000>, <0x0 0x00033000>; + reg = <0x14000000 0x2fb000>, <0x105000 0x2fb000>; erase-block-size = ; write-block-size = <4>; + status = "disabled"; }; - flash1: flash@10000000 { + flash1: flash@a0000000 { compatible = "ti,cc35xx-nv-flash"; - reg = <0x10000000 0x001e7000>, <0x00033000 0x001e7000>; + reg = <0xa0000000 0xda000>, <0x0 0xda000>; erase-block-size = ; write-block-size = <4>; + status = "disabled"; }; - flash2: flash@a0050000 { + flash2: flash@a00da000 { compatible = "ti,cc35xx-nv-flash"; - reg = <0xa0050000 0x001ea000>, <0x0021a000 0x001ea000>; + reg = <0xa00da000 0x2b000>, <0xda000 0x2b000>; erase-block-size = ; write-block-size = <4>; + status = "disabled"; }; }; }; From 9d79acc9fbcfdf855fb08fdf740a4a4e2afb3efb Mon Sep 17 00:00:00 2001 From: Jakub Jarosinski Date: Wed, 29 Jul 2026 13:16:05 +0200 Subject: [PATCH 024/100] UPSTREAM-PEND: drivers: gpio: cc35xx: fix pull configuration Map Zephyr pull flags directly to the corresponding TI IOMUX controls. Signed-off-by: Jakub Jarosinski --- drivers/gpio/gpio_cc35xx.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/gpio/gpio_cc35xx.c b/drivers/gpio/gpio_cc35xx.c index 60da8354bf95..78d25951bdb1 100644 --- a/drivers/gpio/gpio_cc35xx.c +++ b/drivers/gpio/gpio_cc35xx.c @@ -447,14 +447,9 @@ static int cc35xx_gpio_pin_configure(const struct device *dev, gpio_pin_t pin, g } } else if (flags & GPIO_INPUT) { if (flags & GPIO_PULL_DOWN) { - /* - * The Pull up / Pull down definitions in HAL - * are reversed with regards to HW implementation - * so we adjust for that when configuring the pin. - */ - config |= GPIO_CFG_IN_PU; - } else if (flags & GPIO_PULL_UP) { config |= GPIO_CFG_IN_PD; + } else if (flags & GPIO_PULL_UP) { + config |= GPIO_CFG_IN_PU; } else { config |= GPIO_CFG_IN_NOPULL; } From 87c8fac68a3e0ef1ffc33218aa1b95669d30c1ac Mon Sep 17 00:00:00 2001 From: Jakub Jarosinski Date: Thu, 30 Jul 2026 14:50:36 +0200 Subject: [PATCH 025/100] UPSTREAM-PEND: drivers: cc35xx: use iterable device APIs Use DEVICE_API() declarations for the CC35xx flash, GPIO, and UART drivers. Signed-off-by: Jakub Jarosinski --- drivers/flash/soc_flash_cc35xx.c | 2 +- drivers/gpio/gpio_cc35xx.c | 2 +- drivers/serial/uart_cc35xx.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/flash/soc_flash_cc35xx.c b/drivers/flash/soc_flash_cc35xx.c index 5b1adeda6f81..dc7a611fcaa1 100644 --- a/drivers/flash/soc_flash_cc35xx.c +++ b/drivers/flash/soc_flash_cc35xx.c @@ -259,7 +259,7 @@ static void flash_cc35xx_layout(const struct device *dev, const struct flash_pag } #endif /* CONFIG_FLASH_PAGE_LAYOUT */ -static const struct flash_driver_api flash_cc35xx_api = { +static DEVICE_API(flash, flash_cc35xx_api) = { .erase = flash_cc35xx_erase, .write = flash_cc35xx_write, .read = flash_cc35xx_read, diff --git a/drivers/gpio/gpio_cc35xx.c b/drivers/gpio/gpio_cc35xx.c index 78d25951bdb1..6dba66e5748b 100644 --- a/drivers/gpio/gpio_cc35xx.c +++ b/drivers/gpio/gpio_cc35xx.c @@ -728,7 +728,7 @@ static int cc35xx_gpio_init(const struct device *dev) return 0; } -static const struct gpio_driver_api cc35xx_gpio_drv_api = { +static DEVICE_API(gpio, cc35xx_gpio_drv_api) = { .pin_configure = cc35xx_gpio_pin_configure, #ifdef CONFIG_GPIO_GET_CONFIG .pin_get_config = cc35xx_gpio_pin_get_config, diff --git a/drivers/serial/uart_cc35xx.c b/drivers/serial/uart_cc35xx.c index 4bcd85b96d13..f8e741ad9ed2 100644 --- a/drivers/serial/uart_cc35xx.c +++ b/drivers/serial/uart_cc35xx.c @@ -197,7 +197,7 @@ static void uart_cc35xx_poll_out(const struct device *dev, unsigned char c) } } -static const struct uart_driver_api uart_cc35xx_driver_api = { +static DEVICE_API(uart, uart_cc35xx_driver_api) = { .poll_in = uart_cc35xx_poll_in, .poll_out = uart_cc35xx_poll_out, #ifdef CONFIG_UART_INTERRUPT_DRIVEN From de4a5d0490fc5efc0344e50576a5a6d4f70e0c35 Mon Sep 17 00:00:00 2001 From: Jakub Jarosinski Date: Thu, 30 Jul 2026 14:50:36 +0200 Subject: [PATCH 026/100] UPSTREAM-PEND: boards: ti: fix CC35xx documentation markup Use an inline literal for the west flash command. Signed-off-by: Jakub Jarosinski --- boards/ti/lp_em_cc35x1/doc/index.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/ti/lp_em_cc35x1/doc/index.rst b/boards/ti/lp_em_cc35x1/doc/index.rst index 181b13a97382..bcf8e16ce6e4 100644 --- a/boards/ti/lp_em_cc35x1/doc/index.rst +++ b/boards/ti/lp_em_cc35x1/doc/index.rst @@ -44,7 +44,7 @@ The LP_EM_CC35X1 requires an external debug probe such as the LP-XDS110 or LP-XDS110ET. Currently there is no debug support in Zephyr for the LP_EM_CC35X1. Binaries can be flashed -with standard `west flash` command. +with the standard ``west flash`` command. References ********** From cf3f7146307985fbd793c626256e14330a40c952 Mon Sep 17 00:00:00 2001 From: Jakub Jarosinski Date: Thu, 30 Jul 2026 15:02:39 +0200 Subject: [PATCH 027/100] UPSTREAM-PEND: drivers: cc35xx: format source files Format CC35xx flash, GPIO, and UART drivers with clang-format. Signed-off-by: Jakub Jarosinski --- drivers/flash/soc_flash_cc35xx.c | 4 +- drivers/gpio/gpio_cc35xx.c | 105 +++++++++++++++---------------- drivers/serial/uart_cc35xx.c | 54 ++++++++-------- 3 files changed, 82 insertions(+), 81 deletions(-) diff --git a/drivers/flash/soc_flash_cc35xx.c b/drivers/flash/soc_flash_cc35xx.c index dc7a611fcaa1..e4ca9b60237d 100644 --- a/drivers/flash/soc_flash_cc35xx.c +++ b/drivers/flash/soc_flash_cc35xx.c @@ -15,8 +15,8 @@ #include #include -#define DT_DRV_COMPAT ti_cc35xx_nv_flash -#define CC35XX_ERASE_TIMEOUT 200 +#define DT_DRV_COMPAT ti_cc35xx_nv_flash +#define CC35XX_ERASE_TIMEOUT 200 #define CC35XX_FLASH_WRITE_SIZE 256 struct flash_cc35xx_config { diff --git a/drivers/gpio/gpio_cc35xx.c b/drivers/gpio/gpio_cc35xx.c index 6dba66e5748b..b231f0473f74 100644 --- a/drivers/gpio/gpio_cc35xx.c +++ b/drivers/gpio/gpio_cc35xx.c @@ -25,7 +25,7 @@ * modules/hal/ti/simplelink_wifi/source/ti/drivers/gpio/GPIOWFF3.c */ - /* Missing defines from hw_hostmcu_aon.h */ +/* Missing defines from hw_hostmcu_aon.h */ #define HOSTMCU_AON_CFGWICSNS_GPIO_AND_EN (1U << 1) #define HOSTMCU_AON_CFGWICSNS_GPIO_OR_EN (1U << 2) #define HOSTMCU_AON_CFGWUTP_GPIO_AND_FAST (1U << 1) @@ -34,18 +34,18 @@ /* The size of each IO region in IOMUX id 4KB */ #define IOMUX_IO_REGION_SIZE (4096U) -#define IOMUX_CFG_ADDR(index) \ - (IOMUX_BASE + IOMUX_O_SCLKICFG + ((index) * IOMUX_IO_REGION_SIZE) \ - + (IOMUX_O_GPIO2CFG - IOMUX_O_GPIO2CFG)) -#define IOMUX_PULLCTL_ADDR(index) \ - (IOMUX_BASE + IOMUX_O_SCLKICFG + ((index) * IOMUX_IO_REGION_SIZE) \ - + (IOMUX_O_GPIO2PCTL - IOMUX_O_GPIO2CFG)) -#define IOMUX_CTL_ADDR(index) \ - (IOMUX_BASE + IOMUX_O_SCLKICFG + ((index) * IOMUX_IO_REGION_SIZE) \ - + (IOMUX_O_GPIO2CTL - IOMUX_O_GPIO2CFG)) -#define IOMUX_EVTCTL_ADDR(index) \ - (IOMUX_BASE + IOMUX_O_SCLKICFG + ((index) * IOMUX_IO_REGION_SIZE) \ - + (IOMUX_O_GPIO2ECTL - IOMUX_O_GPIO2CFG)) +#define IOMUX_CFG_ADDR(index) \ + (IOMUX_BASE + IOMUX_O_SCLKICFG + ((index) * IOMUX_IO_REGION_SIZE) + \ + (IOMUX_O_GPIO2CFG - IOMUX_O_GPIO2CFG)) +#define IOMUX_PULLCTL_ADDR(index) \ + (IOMUX_BASE + IOMUX_O_SCLKICFG + ((index) * IOMUX_IO_REGION_SIZE) + \ + (IOMUX_O_GPIO2PCTL - IOMUX_O_GPIO2CFG)) +#define IOMUX_CTL_ADDR(index) \ + (IOMUX_BASE + IOMUX_O_SCLKICFG + ((index) * IOMUX_IO_REGION_SIZE) + \ + (IOMUX_O_GPIO2CTL - IOMUX_O_GPIO2CFG)) +#define IOMUX_EVTCTL_ADDR(index) \ + (IOMUX_BASE + IOMUX_O_SCLKICFG + ((index) * IOMUX_IO_REGION_SIZE) + \ + (IOMUX_O_GPIO2ECTL - IOMUX_O_GPIO2CFG)) #define IOMUX_PORTCFG_ADDR(index) (IOMUX_BASE + IOMUX_O_SCLKIPCFG + ((index) << 2)) struct cc35xx_gpio_port_config { @@ -224,15 +224,15 @@ static void cc35xx_ll_gpio_set_config_and_mux(uint8_t index, uint32_t config, ui cfgRegAddr = IOMUX_CFG_ADDR(index); pullctlRegAddr = IOMUX_PULLCTL_ADDR(index); ctlRegAddr = IOMUX_CTL_ADDR(index); - evtctlRegAddr = IOMUX_EVTCTL_ADDR(index); + evtctlRegAddr = IOMUX_EVTCTL_ADDR(index); portcfgRegAddr = IOMUX_PORTCFG_ADDR(index); /* Extract register-specific values from compressed pin config */ - tmpCfgReg = (config & GPIOWFF3_CFG_CFG_M) >> GPIOWFF3_CFG_CFG_S; + tmpCfgReg = (config & GPIOWFF3_CFG_CFG_M) >> GPIOWFF3_CFG_CFG_S; tmpPullctlCfgReg = (config & GPIOWFF3_CFG_PULLCTL_M) >> GPIOWFF3_CFG_PULLCTL_S; - tmpctlReg = (config & GPIOWFF3_CFG_CTL_M) >> GPIOWFF3_CFG_CTL_S; - tmpEvtctlReg = (config & GPIOWFF3_CFG_EVTCTL_M) >> GPIOWFF3_CFG_EVTCTL_S; - tmpPortcfgReg = (mux << IOMUX_GPIO2PCFG_IOSEL_S) & IOMUX_GPIO2PCFG_IOSEL_M; + tmpctlReg = (config & GPIOWFF3_CFG_CTL_M) >> GPIOWFF3_CFG_CTL_S; + tmpEvtctlReg = (config & GPIOWFF3_CFG_EVTCTL_M) >> GPIOWFF3_CFG_EVTCTL_S; + tmpPortcfgReg = (mux << IOMUX_GPIO2PCFG_IOSEL_S) & IOMUX_GPIO2PCFG_IOSEL_M; /* * If the IO is muxed to the analog IP for that IO, then the analog switch @@ -295,27 +295,27 @@ static void cc35xx_ll_gpio_get_config(uint8_t index, uint32_t *config) uint32_t configValue; uint32_t tmpCfgRegBit; - cfgRegAddr = IOMUX_CFG_ADDR(index); + cfgRegAddr = IOMUX_CFG_ADDR(index); pullctlRegAddr = IOMUX_PULLCTL_ADDR(index); - ctlRegAddr = IOMUX_CTL_ADDR(index); - evtctlRegAddr = IOMUX_EVTCTL_ADDR(index); + ctlRegAddr = IOMUX_CTL_ADDR(index); + evtctlRegAddr = IOMUX_EVTCTL_ADDR(index); - tmpCfgReg = sys_read32(cfgRegAddr); + tmpCfgReg = sys_read32(cfgRegAddr); tmpPullctlCfgReg = sys_read32(pullctlRegAddr); - tmpctlReg = sys_read32(ctlRegAddr); - tmpEvtctlReg = sys_read32(evtctlRegAddr); + tmpctlReg = sys_read32(ctlRegAddr); + tmpEvtctlReg = sys_read32(evtctlRegAddr); configValue = ((tmpCfgReg << GPIOWFF3_CFG_CFG_S) & GPIOWFF3_CFG_CFG_M) | - ((tmpPullctlCfgReg << GPIOWFF3_CFG_PULLCTL_S) & GPIOWFF3_CFG_PULLCTL_M) | - ((tmpctlReg << GPIOWFF3_CFG_CTL_S) & GPIOWFF3_CFG_CTL_M) | - ((tmpEvtctlReg << GPIOWFF3_CFG_EVTCTL_S) & GPIOWFF3_CFG_EVTCTL_M); + ((tmpPullctlCfgReg << GPIOWFF3_CFG_PULLCTL_S) & GPIOWFF3_CFG_PULLCTL_M) | + ((tmpctlReg << GPIOWFF3_CFG_CTL_S) & GPIOWFF3_CFG_CTL_M) | + ((tmpEvtctlReg << GPIOWFF3_CFG_EVTCTL_S) & GPIOWFF3_CFG_EVTCTL_M); /* If IMASK bit is set, the interrupt is enabled. */ if (index >= 32) { - tmpCfgReg = sys_read32(SOC_AON_BASE + SOC_AON_O_GPIOFNC1S); + tmpCfgReg = sys_read32(SOC_AON_BASE + SOC_AON_O_GPIOFNC1S); tmpCfgRegBit = 1 << (index - 32); } else { - tmpCfgReg = sys_read32(SOC_AON_BASE + SOC_AON_O_GPIOFNC0S); + tmpCfgReg = sys_read32(SOC_AON_BASE + SOC_AON_O_GPIOFNC0S); tmpCfgRegBit = 1 << index; } @@ -343,7 +343,7 @@ static void cc35xx_ll_gpio_set_interrupt_config(uint8_t index, uint32_t config) key = irq_lock(); uint32_t currentRegisterConfig = sys_read32(evtctlRegAddr); - currentRegisterConfig &= ~(GPIOWFF3_CFG_EVTCTL_M >> GPIOWFF3_CFG_EVTCTL_S); + currentRegisterConfig &= ~(GPIOWFF3_CFG_EVTCTL_M >> GPIOWFF3_CFG_EVTCTL_S); sys_write32((currentRegisterConfig | maskedConfig), evtctlRegAddr); irq_unlock(key); @@ -367,14 +367,14 @@ static int cc35xx_gpio_port_get_raw(const struct device *dev, gpio_port_value_t } static int cc35xx_gpio_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask, - gpio_port_value_t value) + gpio_port_value_t value) { const struct cc35xx_gpio_port_config *const port_cfg = dev->config; for (int i = 0; i < port_cfg->ngpios; i++) { if (mask & BIT(i)) { cc35xx_ll_gpio_write(port_cfg->gpio_index_offset + i, - (BIT(i) & value) >> i); + (BIT(i) & value) >> i); } } return 0; @@ -534,7 +534,7 @@ static inline bool cc35xx_config_is_input_pull_down(uint32_t config) } static int cc35xx_gpio_pin_get_config(const struct device *dev, gpio_pin_t pin, - gpio_flags_t *out_flags) + gpio_flags_t *out_flags) { const struct cc35xx_gpio_port_config *const port_cfg = dev->config; uint32_t config = 0; @@ -567,7 +567,7 @@ static int cc35xx_gpio_pin_get_config(const struct device *dev, gpio_pin_t pin, #ifdef CONFIG_GPIO_GET_DIRECTION static int cc35xx_gpio_port_get_direction(const struct device *dev, gpio_port_pins_t map, - gpio_port_pins_t *inputs, gpio_port_pins_t *outputs) + gpio_port_pins_t *inputs, gpio_port_pins_t *outputs) { const struct cc35xx_gpio_port_config *const port_cfg = dev->config; uint32_t config; @@ -600,7 +600,7 @@ static int cc35xx_gpio_port_get_direction(const struct device *dev, gpio_port_pi #endif static int cc35xx_gpio_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin, - enum gpio_int_mode mode, enum gpio_int_trig trig) + enum gpio_int_mode mode, enum gpio_int_trig trig) { uint32_t config = 0; const struct cc35xx_gpio_port_config *const port_cfg = dev->config; @@ -621,7 +621,7 @@ static int cc35xx_gpio_pin_interrupt_configure(const struct device *dev, gpio_pi case GPIO_INT_MODE_EDGE: config |= GPIO_CFG_INT_ENABLE; config |= (trig == GPIO_INT_TRIG_HIGH) ? GPIO_CFG_IN_INT_RISING - : GPIO_CFG_IN_INT_FALLING; + : GPIO_CFG_IN_INT_FALLING; break; default: return -ENOTSUP; @@ -633,7 +633,7 @@ static int cc35xx_gpio_pin_interrupt_configure(const struct device *dev, gpio_pi } static int cc35xx_gpio_manage_callback(const struct device *dev, struct gpio_callback *callback, - bool set) + bool set) { struct cc35xx_gpio_port_data *port_data = dev->data; @@ -718,8 +718,8 @@ static int cc35xx_gpio_init(const struct device *dev) val |= HOSTMCU_AON_CFGWUTP_GPIO_OR_FAST; sys_write32(val, (HOSTMCU_AON_BASE + HOSTMCU_AON_O_CFGWUTP)); - IRQ_CONNECT(DT_IRQN(DT_DRV_INST(0)), DT_IRQ(DT_DRV_INST(0), priority), - cc35xx_gpio_isr, DEVICE_DT_GET(DT_INST(0, DT_DRV_COMPAT)), 0); + IRQ_CONNECT(DT_IRQN(DT_DRV_INST(0)), DT_IRQ(DT_DRV_INST(0), priority), cc35xx_gpio_isr, + DEVICE_DT_GET(DT_INST(0, DT_DRV_COMPAT)), 0); irq_enable(DT_IRQN(DT_DRV_INST(0))); @@ -745,19 +745,18 @@ static DEVICE_API(gpio, cc35xx_gpio_drv_api) = { .manage_callback = cc35xx_gpio_manage_callback, }; -#define CC35XX_GPIO_PORT_DEFINE(inst) \ - static struct cc35xx_gpio_port_data cc35xx_gpio_port_data_##inst; \ - static const struct cc35xx_gpio_port_config cc35xx_gpio_port_config_##inst = { \ - .common = \ - { \ - .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(inst), \ - }, \ - .ngpios = DT_PROP(DT_DRV_INST(inst), ngpios), \ - .gpio_index_offset = DT_PROP(DT_DRV_INST(inst), gpio_index_offset), \ - }; \ - DEVICE_DT_INST_DEFINE(inst, cc35xx_gpio_init, NULL, \ - &cc35xx_gpio_port_data_##inst, \ - &cc35xx_gpio_port_config_##inst, PRE_KERNEL_1, \ - CONFIG_GPIO_INIT_PRIORITY, &cc35xx_gpio_drv_api); +#define CC35XX_GPIO_PORT_DEFINE(inst) \ + static struct cc35xx_gpio_port_data cc35xx_gpio_port_data_##inst; \ + static const struct cc35xx_gpio_port_config cc35xx_gpio_port_config_##inst = { \ + .common = \ + { \ + .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(inst), \ + }, \ + .ngpios = DT_PROP(DT_DRV_INST(inst), ngpios), \ + .gpio_index_offset = DT_PROP(DT_DRV_INST(inst), gpio_index_offset), \ + }; \ + DEVICE_DT_INST_DEFINE(inst, cc35xx_gpio_init, NULL, &cc35xx_gpio_port_data_##inst, \ + &cc35xx_gpio_port_config_##inst, PRE_KERNEL_1, \ + CONFIG_GPIO_INIT_PRIORITY, &cc35xx_gpio_drv_api); DT_INST_FOREACH_STATUS_OKAY(CC35XX_GPIO_PORT_DEFINE) diff --git a/drivers/serial/uart_cc35xx.c b/drivers/serial/uart_cc35xx.c index f8e741ad9ed2..5d053a6e5221 100644 --- a/drivers/serial/uart_cc35xx.c +++ b/drivers/serial/uart_cc35xx.c @@ -217,31 +217,33 @@ static DEVICE_API(uart, uart_cc35xx_driver_api) = { #endif }; -#define UART_35XX_DEVICE(idx) \ - PINCTRL_DT_INST_DEFINE(idx); \ - IF_ENABLED(CONFIG_UART_INTERRUPT_DRIVEN, ( \ - static void uart_cc35xx_cfg_func_##idx(const struct device *dev) \ - { \ - IF_ENABLED(CONFIG_UART_INTERRUPT_DRIVEN, ( \ - IRQ_CONNECT(DT_INST_IRQN(idx), \ - DT_INST_IRQ(idx, priority), \ - uart_cc35xx_isr, DEVICE_DT_INST_GET(idx), \ - 0); \ - irq_enable(DT_INST_IRQN(idx))) \ - ); \ - })); \ - static const struct uart_cc35xx_dev_config uart_cc35xx_dev_cfg_##idx = { \ - .base = DT_INST_REG_ADDR(idx), \ - .sys_clk_freq = DT_INST_PROP_BY_PHANDLE(idx, clocks, clock_frequency), \ - .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx), \ - IF_ENABLED(CONFIG_UART_INTERRUPT_DRIVEN, \ - (.irq_config_func = uart_cc35xx_cfg_func_##idx,)) }; \ - static struct uart_cc35xx_dev_data_t uart_cc35xx_dev_data_##idx = { \ - .baud_rate = DT_INST_PROP(idx, current_speed), \ - .id = idx, \ - }; \ - DEVICE_DT_INST_DEFINE(idx, uart_cc35xx_init, NULL, &uart_cc35xx_dev_data_##idx, \ - &uart_cc35xx_dev_cfg_##idx, PRE_KERNEL_1, \ +/* clang-format off */ +#define UART_DEVICE(idx) \ + PINCTRL_DT_INST_DEFINE(idx); \ + IF_ENABLED(CONFIG_UART_INTERRUPT_DRIVEN, ( \ + static void uart_cc35xx_cfg_func_##idx(const struct device *dev) \ + { \ + IF_ENABLED(CONFIG_UART_INTERRUPT_DRIVEN, ( \ + IRQ_CONNECT(DT_INST_IRQN(idx), \ + DT_INST_IRQ(idx, priority), \ + uart_cc35xx_isr, DEVICE_DT_INST_GET(idx), \ + 0); \ + irq_enable(DT_INST_IRQN(idx))) \ + ); \ + })); \ + static const struct uart_cc35xx_dev_config uart_cc35xx_dev_cfg_##idx = { \ + .base = DT_INST_REG_ADDR(idx), \ + .sys_clk_freq = DT_INST_PROP_BY_PHANDLE(idx, clocks, clock_frequency), \ + .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx), \ + IF_ENABLED(CONFIG_UART_INTERRUPT_DRIVEN, \ + (.irq_config_func = uart_cc35xx_cfg_func_##idx,)) }; \ + static struct uart_cc35xx_dev_data_t uart_cc35xx_dev_data_##idx = { \ + .baud_rate = DT_INST_PROP(idx, current_speed), \ + .id = idx, \ + }; \ + DEVICE_DT_INST_DEFINE(idx, uart_cc35xx_init, NULL, &uart_cc35xx_dev_data_##idx, \ + &uart_cc35xx_dev_cfg_##idx, PRE_KERNEL_1, \ CONFIG_SERIAL_INIT_PRIORITY, (void *)&uart_cc35xx_driver_api); +/* clang-format on */ -DT_INST_FOREACH_STATUS_OKAY(UART_35XX_DEVICE); +DT_INST_FOREACH_STATUS_OKAY(UART_DEVICE); From 3e0a9d42fa86b88d3826e2aca7d66ca2d066f5d8 Mon Sep 17 00:00:00 2001 From: Jakub Jarosinski Date: Thu, 30 Jul 2026 15:02:40 +0200 Subject: [PATCH 028/100] UPSTREAM-PEND: boards: ti: add CC35xx SPDX metadata Add SPDX metadata to CC35xx board and Toolbox files. Signed-off-by: Jakub Jarosinski --- boards/ti/lp_em_cc35x1/lp_em_cc35x1_8m.overlay | 5 +++++ boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3500e.dts | 5 +++++ boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3501e.dts | 5 +++++ boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3550e.dts | 5 +++++ boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3551e.dts | 5 +++++ include/zephyr/dt-bindings/pinctrl/ti-cc35xx-pinctrl.h | 1 + soc/ti/simplelink/cc35xxe/conf/cc35xx-conf.ini | 3 +++ soc/ti/simplelink/cc35xxe/conf/conf.key.license | 2 ++ soc/ti/simplelink/cc35xxe/conf/conf_cc35xx.h | 3 +++ soc/ti/simplelink/cc35xxe/conf/dictionary_cc35xx.txt | 3 +++ .../cc35xxe/keys/cc35x1e_lp_em_prv_key.pem.license | 2 ++ .../cc35xxe/keys/cc35x1e_lp_em_pub_key.pem.license | 2 ++ soc/ti/simplelink/cc35xxe/ramfunc_linker.ld | 5 +++++ 13 files changed, 46 insertions(+) create mode 100644 soc/ti/simplelink/cc35xxe/conf/conf.key.license create mode 100644 soc/ti/simplelink/cc35xxe/keys/cc35x1e_lp_em_prv_key.pem.license create mode 100644 soc/ti/simplelink/cc35xxe/keys/cc35x1e_lp_em_pub_key.pem.license diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_8m.overlay b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_8m.overlay index 70378e5a215b..7d008a2272fe 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_8m.overlay +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_8m.overlay @@ -1,3 +1,8 @@ +/* + * Copyright (c) 2026 Conclusive Engineering Sp. z o.o. + * SPDX-License-Identifier: Apache-2.0 + */ + &extflash_ns { reg = <0x10000000 DT_SIZE_M(8)>; }; diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3500e.dts b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3500e.dts index 4c2647f98ef1..38303a555356 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3500e.dts +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3500e.dts @@ -1,3 +1,8 @@ +/* + * Copyright (c) 2025 Conclusive Engineering Sp. z o.o. + * SPDX-License-Identifier: Apache-2.0 + */ + /dts-v1/; #include "lp_em_cc35x1_common.dtsi" diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3501e.dts b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3501e.dts index 4c2647f98ef1..38303a555356 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3501e.dts +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3501e.dts @@ -1,3 +1,8 @@ +/* + * Copyright (c) 2025 Conclusive Engineering Sp. z o.o. + * SPDX-License-Identifier: Apache-2.0 + */ + /dts-v1/; #include "lp_em_cc35x1_common.dtsi" diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3550e.dts b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3550e.dts index 4c2647f98ef1..38303a555356 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3550e.dts +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3550e.dts @@ -1,3 +1,8 @@ +/* + * Copyright (c) 2025 Conclusive Engineering Sp. z o.o. + * SPDX-License-Identifier: Apache-2.0 + */ + /dts-v1/; #include "lp_em_cc35x1_common.dtsi" diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3551e.dts b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3551e.dts index 4c2647f98ef1..38303a555356 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3551e.dts +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3551e.dts @@ -1,3 +1,8 @@ +/* + * Copyright (c) 2025 Conclusive Engineering Sp. z o.o. + * SPDX-License-Identifier: Apache-2.0 + */ + /dts-v1/; #include "lp_em_cc35x1_common.dtsi" diff --git a/include/zephyr/dt-bindings/pinctrl/ti-cc35xx-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/ti-cc35xx-pinctrl.h index 0deeb56e51f6..5385b95eec34 100644 --- a/include/zephyr/dt-bindings/pinctrl/ti-cc35xx-pinctrl.h +++ b/include/zephyr/dt-bindings/pinctrl/ti-cc35xx-pinctrl.h @@ -1,4 +1,5 @@ /* + * Copyright (c) 2025 Conclusive Engineering Sp. z o.o. * SPDX-License-Identifier: Apache-2.0 */ diff --git a/soc/ti/simplelink/cc35xxe/conf/cc35xx-conf.ini b/soc/ti/simplelink/cc35xxe/conf/cc35xx-conf.ini index 8cabe2242bdc..f4581c39ece7 100644 --- a/soc/ti/simplelink/cc35xxe/conf/cc35xx-conf.ini +++ b/soc/ti/simplelink/cc35xxe/conf/cc35xx-conf.ini @@ -1,3 +1,6 @@ +# SPDX-FileCopyrightText: Copyright (c) 2023 Texas Instruments Incorporated +# SPDX-License-Identifier: Apache-2.0 + ################################################## ## CC33XX INI Template ## ## All Param values are in HEX ## diff --git a/soc/ti/simplelink/cc35xxe/conf/conf.key.license b/soc/ti/simplelink/cc35xxe/conf/conf.key.license new file mode 100644 index 000000000000..ea8b065bcb2a --- /dev/null +++ b/soc/ti/simplelink/cc35xxe/conf/conf.key.license @@ -0,0 +1,2 @@ +SPDX-FileCopyrightText: Copyright (c) 2026 Texas Instruments Incorporated +SPDX-License-Identifier: Apache-2.0 diff --git a/soc/ti/simplelink/cc35xxe/conf/conf_cc35xx.h b/soc/ti/simplelink/cc35xxe/conf/conf_cc35xx.h index 57490bf12629..d5b554d4d371 100644 --- a/soc/ti/simplelink/cc35xxe/conf/conf_cc35xx.h +++ b/soc/ti/simplelink/cc35xxe/conf/conf_cc35xx.h @@ -1,4 +1,7 @@ /* + * SPDX-FileCopyrightText: Copyright (c) 2023 Texas Instruments Incorporated + * SPDX-License-Identifier: Apache-2.0 + * * This file is part of CC33XX * * Copyright (C) 2023 Texas Instruments diff --git a/soc/ti/simplelink/cc35xxe/conf/dictionary_cc35xx.txt b/soc/ti/simplelink/cc35xxe/conf/dictionary_cc35xx.txt index 8815ab480f4e..87abcd27296c 100644 --- a/soc/ti/simplelink/cc35xxe/conf/dictionary_cc35xx.txt +++ b/soc/ti/simplelink/cc35xxe/conf/dictionary_cc35xx.txt @@ -1,3 +1,6 @@ +# SPDX-FileCopyrightText: Copyright (c) 2023 Texas Instruments Incorporated +# SPDX-License-Identifier: Apache-2.0 + # Dictionary for INI version Demo Version StaPowerSave mac.ps_mode diff --git a/soc/ti/simplelink/cc35xxe/keys/cc35x1e_lp_em_prv_key.pem.license b/soc/ti/simplelink/cc35xxe/keys/cc35x1e_lp_em_prv_key.pem.license new file mode 100644 index 000000000000..ea8b065bcb2a --- /dev/null +++ b/soc/ti/simplelink/cc35xxe/keys/cc35x1e_lp_em_prv_key.pem.license @@ -0,0 +1,2 @@ +SPDX-FileCopyrightText: Copyright (c) 2026 Texas Instruments Incorporated +SPDX-License-Identifier: Apache-2.0 diff --git a/soc/ti/simplelink/cc35xxe/keys/cc35x1e_lp_em_pub_key.pem.license b/soc/ti/simplelink/cc35xxe/keys/cc35x1e_lp_em_pub_key.pem.license new file mode 100644 index 000000000000..ea8b065bcb2a --- /dev/null +++ b/soc/ti/simplelink/cc35xxe/keys/cc35x1e_lp_em_pub_key.pem.license @@ -0,0 +1,2 @@ +SPDX-FileCopyrightText: Copyright (c) 2026 Texas Instruments Incorporated +SPDX-License-Identifier: Apache-2.0 diff --git a/soc/ti/simplelink/cc35xxe/ramfunc_linker.ld b/soc/ti/simplelink/cc35xxe/ramfunc_linker.ld index 2d3d515893d7..af23721546dd 100644 --- a/soc/ti/simplelink/cc35xxe/ramfunc_linker.ld +++ b/soc/ti/simplelink/cc35xxe/ramfunc_linker.ld @@ -1 +1,6 @@ +/* + * Copyright (c) 2025 Conclusive Engineering Sp. z o.o. + * SPDX-License-Identifier: Apache-2.0 + */ + KEEP(*(.TI.ramfunc)) From f237b318c2f34b2abb144fd40b0088eda636c41a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=81yszczek?= Date: Mon, 8 Sep 2025 12:11:30 +0200 Subject: [PATCH 029/100] UPSTREAM-PEND: drivers: spi: cc35xxe: add spi driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add spi driver for CC35xxE Signed-off-by: Michał Łyszczek --- .../ti/lp_em_cc35x1/lp_em_cc35x1-pinctrl.dtsi | 34 ++ .../lp_em_cc35x1_cc3501e_defconfig | 4 + .../ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi | 13 + drivers/spi/CMakeLists.txt | 1 + drivers/spi/Kconfig | 1 + drivers/spi/Kconfig.cc35xx | 9 + drivers/spi/spi_cc35xx.c | 394 ++++++++++++++++++ dts/arm/ti/cc35xxe.dtsi | 30 ++ dts/bindings/spi/ti,cc35xx-spi.yaml | 12 + 9 files changed, 498 insertions(+) create mode 100644 drivers/spi/Kconfig.cc35xx create mode 100644 drivers/spi/spi_cc35xx.c create mode 100644 dts/bindings/spi/ti,cc35xx-spi.yaml diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1-pinctrl.dtsi b/boards/ti/lp_em_cc35x1/lp_em_cc35x1-pinctrl.dtsi index 5cb97c4ad6b0..c0911857e504 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1-pinctrl.dtsi +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1-pinctrl.dtsi @@ -17,4 +17,38 @@ pinmux = , ; }; }; + + spi0_slave: spi0_slave { + group1 { + pinmux = , + <(TI_CC35XX_PINCTRL_DIR_OUT | P28_SPI0_MISO)>, + <(TI_CC35XX_PINCTRL_DIR_IN | P29_SPI0_MOSI)>, + <(TI_CC35XX_PINCTRL_DIR_IN | P26_SPI0_CS1)>; + }; + }; + spi0_master: spi0_master { + group1 { + pinmux = , + <(TI_CC35XX_PINCTRL_DIR_IN | P28_SPI0_MISO)>, + <(TI_CC35XX_PINCTRL_DIR_OUT | P29_SPI0_MOSI)>, + <(TI_CC35XX_PINCTRL_DIR_OUT | P26_SPI0_CS1)>; + }; + }; + + spi1_slave: spi1_slave { + group1 { + pinmux = , + <(TI_CC35XX_PINCTRL_DIR_OUT | P15_SPI1_MISO)>, + <(TI_CC35XX_PINCTRL_DIR_IN | P13_SPI1_MOSI)>, + <(TI_CC35XX_PINCTRL_DIR_IN | P12_SPI1_CS1)>; + }; + }; + spi1_master: spi1_master { + group1 { + pinmux = , + <(TI_CC35XX_PINCTRL_DIR_IN | P15_SPI1_MISO)>, + <(TI_CC35XX_PINCTRL_DIR_OUT | P13_SPI1_MOSI)>, + <(TI_CC35XX_PINCTRL_DIR_OUT | P12_SPI1_CS1)>; + }; + }; }; diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3501e_defconfig b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3501e_defconfig index 85106161c86c..6dcdd4e9f903 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3501e_defconfig +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3501e_defconfig @@ -27,3 +27,7 @@ CONFIG_SHELL_BACKEND_SERIAL_API_INTERRUPT_DRIVEN=y CONFIG_FLASH=y CONFIG_SOC_FLASH_CC35XX=y CONFIG_FLASH_SHELL=y + +CONFIG_SPI=y +CONFIG_SPI_CC35XX=y +CONFIG_SPI_SHELL=y diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi index 4e185e6dced2..be4348ff44db 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi @@ -94,6 +94,19 @@ status = "okay"; }; +&spi0 { + status = "okay"; + pinctrl-0 = <&spi0_master>; + pinctrl-names = "default"; + cs-gpios = <&gpios 26 GPIO_ACTIVE_LOW>; +}; + +&spi1 { + status = "okay"; + pinctrl-0 = <&spi1_slave>; + pinctrl-names = "default"; +}; + &flash0 { status = "okay"; diff --git a/drivers/spi/CMakeLists.txt b/drivers/spi/CMakeLists.txt index 30b7c824c99b..5a0d48c9d1ac 100644 --- a/drivers/spi/CMakeLists.txt +++ b/drivers/spi/CMakeLists.txt @@ -22,6 +22,7 @@ zephyr_library_sources_ifdef(CONFIG_SPI_BFLB spi_bflb.c) zephyr_library_sources_ifdef(CONFIG_SPI_BITBANG spi_bitbang.c) zephyr_library_sources_ifdef(CONFIG_SPI_CC13XX_CC26XX spi_cc13xx_cc26xx.c) zephyr_library_sources_ifdef(CONFIG_SPI_CC23X0 spi_cc23x0.c) +zephyr_library_sources_ifdef(CONFIG_SPI_CC35XX spi_cc35xx.c) zephyr_library_sources_ifdef(CONFIG_SPI_CDNS spi_cdns.c) zephyr_library_sources_ifdef(CONFIG_SPI_DW spi_dw.c) zephyr_library_sources_ifdef(CONFIG_SPI_EGIS_ET171 spi_egis_et171.c) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 887e75c7e067..b5f84c3d6dec 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -111,6 +111,7 @@ source "drivers/spi/Kconfig.bflb" source "drivers/spi/Kconfig.bitbang" source "drivers/spi/Kconfig.cc13xx_cc26xx" source "drivers/spi/Kconfig.cc23x0" +source "drivers/spi/Kconfig.cc35xx" source "drivers/spi/Kconfig.cdns" source "drivers/spi/Kconfig.dw" source "drivers/spi/Kconfig.egis_et171" diff --git a/drivers/spi/Kconfig.cc35xx b/drivers/spi/Kconfig.cc35xx new file mode 100644 index 000000000000..9089e5326d6a --- /dev/null +++ b/drivers/spi/Kconfig.cc35xx @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +config SPI_CC35XX + bool "TI SimpleLink CC35xx SPI driver" + default y + depends on DT_HAS_TI_CC35XX_SPI_ENABLED + select PINCTRL + help + Enable support for the TI SimpleLink CC35xx SPI peripheral diff --git a/drivers/spi/spi_cc35xx.c b/drivers/spi/spi_cc35xx.c new file mode 100644 index 000000000000..994794eed846 --- /dev/null +++ b/drivers/spi/spi_cc35xx.c @@ -0,0 +1,394 @@ +/* + * Copyright (c) 2025 Conclusive Engineering Sp. z o.o. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT ti_cc35xx_spi + +#define LOG_LEVEL CONFIG_SPI_LOG_LEVEL +#include +LOG_MODULE_REGISTER(spi_cc35xx); + +#include +#include +#include +#include +#include + +#include +#include + +#include "spi_context.h" + +#define SPI_INT_ALL \ + (SPI_MIS_TX_SET | SPI_MIS_RX_SET | SPI_MIS_RXOVF_SET | SPI_MIS_IDLE_SET | \ + SPI_MIS_TXEMPTY_SET | SPI_MIS_PER_SET | SPI_MIS_RTOUT_SET | SPI_MIS_DMARX_SET | \ + SPI_MIS_DMATX_SET) +#define IDLE_CHAR 0x00 +#define SPI_SLAVE_BUS_MAX_FREQ 40000000l + +struct spi_cc35xx_config { + uint32_t base; + const struct pinctrl_dev_config *pcfg; + uint32_t sys_clk_freq; +}; + +struct spi_cc35xx_data { + struct spi_context ctx; + size_t rxleft; +}; + +static void spi_cc35xx_read_rx_fifo(const struct device *dev) +{ + const struct spi_cc35xx_config *cfg = dev->config; + struct spi_cc35xx_data *data = dev->data; + struct spi_context *ctx = &data->ctx; + uint32_t rxd; + + while (SPIGetDataNonBlocking(cfg->base, &rxd)) { + if (spi_context_rx_buf_on(ctx)) { + *ctx->rx_buf = rxd; + } + spi_context_update_rx(ctx, 1, 1); + } +} + +static void spi_cc35xx_fill_tx_fifo(const struct device *dev) +{ + const struct spi_cc35xx_config *cfg = dev->config; + struct spi_cc35xx_data *data = dev->data; + struct spi_context *ctx = &data->ctx; + uint32_t txd; + + while (sys_read32(cfg->base + SPI_O_STA) & SPI_STA_TNF_NOT_FULL) { + if (!spi_context_tx_on(ctx) && !data->rxleft) { + return; + } + + if (data->rxleft) { + data->rxleft--; + } + + /* Fill TX fifo with idle chars if we have data to read, + * but nothing to send + */ + txd = IDLE_CHAR; + if (spi_context_tx_buf_on(ctx)) { + txd = *ctx->tx_buf; + } + spi_context_update_tx(ctx, 1, 1); + + SPIPutData(cfg->base, txd); + } +} + +static void spi_cc35xx_flush_fifo(mem_addr_t base) +{ + sys_write32(sys_read32(base + SPI_O_CTL0) | SPI_CTL0_FIFORST_RST_TRIG | + SPI_CTL0_IDLEPOCI_IDLE_ONE, base + SPI_O_CTL0); + while (sys_read32(base + SPI_O_CTL0) & SPI_CTL0_FIFORST) { + } +} + +static int spi_cc35xx_configure(const struct device *dev, const struct spi_config *config) +{ + const struct spi_cc35xx_config *cfg = dev->config; + struct spi_cc35xx_data *data = dev->data; + struct spi_context *ctx = &data->ctx; + int is_master = SPI_OP_MODE_GET(config->operation) == SPI_OP_MODE_MASTER; + uint32_t prot, freq; + int ret, mode; + + if (spi_context_configured(ctx, config)) { + return 0; + } + + SPIDisable(cfg->base); + SPIDisableInt(cfg->base, SPI_INT_ALL); + SPIClearInt(cfg->base, SPI_INT_ALL); + + if (config->operation & SPI_HALF_DUPLEX) { + LOG_ERR("Half-duplex not supported"); + return -ENOTSUP; + } + + if (SPI_WORD_SIZE_GET(config->operation) != 8) { + LOG_ERR("Word sizes other than 8 bits are not supported"); + return -ENOTSUP; + } + + ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); + if (ret < 0) { + LOG_ERR("Applying SPI pinctrl state failed"); + return ret; + } + + mode = is_master ? SPI_MODE_CONTROLLER : SPI_MODE_PERIPHERAL; + prot = is_master ? SPI_CTL0_FRF_MOTOROLA_3WIRE : SPI_CTL0_FRF_MOTOROLA_4WIRE; + freq = is_master ? config->frequency : SPI_SLAVE_BUS_MAX_FREQ; + prot |= SPI_MODE_GET(config->operation) & SPI_MODE_CPOL ? + SPI_CTL0_SPO_HIGH : SPI_CTL0_SPO_LOW; + prot |= SPI_MODE_GET(config->operation) & SPI_MODE_CPHA ? + SPI_CTL0_SPH_SECOND : SPI_CTL0_SPH_FIRST; + + SPIConfigSetExpClk(cfg->base, cfg->sys_clk_freq, prot, mode, freq, 8); + sys_write32(SPI_IFLS_RXSEL_LVL_1_2 | SPI_IFLS_TXSEL_LVL_1_2, cfg->base + SPI_O_IFLS); + if (config->operation & SPI_TRANSFER_LSB) { + sys_write32((sys_read32(cfg->base + SPI_O_CTL1) & ~SPI_CTL1_MSB_M) | + SPI_CTL1_MSB_LSB, + cfg->base + SPI_O_CTL1); + } + + SPIEnable(cfg->base); + sys_write32(BIT(0), cfg->base + SPI_O_CLKCFG); + spi_cc35xx_flush_fifo(cfg->base); + + ctx->config = config; + return 0; +} + +static void spi_cc35xx_master_transceive(const struct device *dev) +{ + const struct spi_cc35xx_config *cfg = dev->config; + struct spi_cc35xx_data *data = dev->data; + struct spi_context *ctx = &data->ctx; + + spi_cc35xx_flush_fifo(cfg->base); + spi_context_cs_control(ctx, true); + + spi_cc35xx_fill_tx_fifo(dev); + SPIEnableInt(cfg->base, SPI_MIS_TX_SET); +} + +#ifdef CONFIG_SPI_SLAVE + +static void spi_cc35xx_slave_transceive(const struct device *dev) +{ + const struct spi_cc35xx_config *cfg = dev->config; + + spi_cc35xx_flush_fifo(cfg->base); + spi_cc35xx_fill_tx_fifo(dev); + SPIEnableInt(cfg->base, SPI_MIS_RX_SET); +} +#endif + +static int spi_cc35xx_transceive(const struct device *dev, + const struct spi_config *config, + const struct spi_buf_set *tx_bufs, + const struct spi_buf_set *rx_bufs, + spi_callback_t cb, void *userdata, int async) +{ + struct spi_cc35xx_data *data = dev->data; + struct spi_context *ctx = &data->ctx; + int err; + + spi_context_lock(ctx, async, cb, userdata, config); + + pm_policy_state_lock_get(PM_STATE_RUNTIME_IDLE, PM_ALL_SUBSTATES); + pm_policy_state_lock_get(PM_STATE_STANDBY, PM_ALL_SUBSTATES); + + err = spi_cc35xx_configure(dev, config); + if (err) { + goto done; + } + + spi_context_buffers_setup(ctx, tx_bufs, rx_bufs, 1); + data->rxleft = spi_context_total_rx_len(ctx); + +#ifdef CONFIG_SPI_SLAVE + if (spi_context_is_slave(ctx)) { + spi_cc35xx_slave_transceive(dev); + } else +#endif + { + spi_cc35xx_master_transceive(dev); + } + +done: + spi_context_wait_for_completion(ctx); + + pm_policy_state_lock_put(PM_STATE_STANDBY, PM_ALL_SUBSTATES); + pm_policy_state_lock_put(PM_STATE_RUNTIME_IDLE, PM_ALL_SUBSTATES); + + spi_context_release(ctx, err); +#ifdef CONFIG_SPI_SLAVE + if (spi_context_is_slave(ctx) && !err) { + err = ctx->recv_frames; + } +#endif + + return err; + +} + +static int spi_cc35xx_release(const struct device *dev, const struct spi_config *config) +{ + const struct spi_cc35xx_config *cfg = dev->config; + struct spi_cc35xx_data *data = dev->data; + struct spi_context *ctx = &data->ctx; + + if (!spi_context_configured(ctx, config)) { + return -EINVAL; + } + + if (SPIBusy(cfg->base)) { + return -EBUSY; + } + + spi_context_unlock_unconditionally(ctx); + + return 0; +} + +static void spi_cc35xx_isr(const struct device *dev) +{ + const struct spi_cc35xx_config *cfg = dev->config; + struct spi_cc35xx_data *data = dev->data; + struct spi_context *ctx = &data->ctx; + uint32_t txrx_irq = SPIIntStatus(cfg->base, true) & (SPI_MIS_RX | SPI_MIS_TX); + + if (txrx_irq) { + SPIClearInt(cfg->base, txrx_irq); + spi_cc35xx_read_rx_fifo(dev); + + if (!spi_context_rx_on(ctx) && !spi_context_tx_on(ctx)) { + SPIDisableInt(cfg->base, txrx_irq); + + if (txrx_irq & SPI_MIS_RX) { + spi_context_complete(ctx, dev, 0); + } else { + SPIClearInt(cfg->base, SPI_MIS_IDLE_SET); + SPIEnableInt(cfg->base, SPI_MIS_IDLE_SET); + } + return; + } + + spi_cc35xx_fill_tx_fifo(dev); + } + + if (SPIIntStatus(cfg->base, true) & SPI_MIS_IDLE) { + SPIDisableInt(cfg->base, SPI_MIS_IDLE); + SPIClearInt(cfg->base, SPI_MIS_IDLE); + spi_context_cs_control(ctx, false); + spi_context_complete(ctx, dev, 0); + } +} + +#ifdef CONFIG_SPI_ASYNC +static int spi_cc35xx_transceive_async(const struct device *dev, + const struct spi_config *config, + const struct spi_buf_set *tx_bufs, + const struct spi_buf_set *rx_bufs, + spi_callback_t cb, void *userdata) +{ + return spi_cc35xx_transceive(dev, config, tx_bufs, rx_bufs, cb, userdata, 1); +} +#endif + +static int spi_cc35xx_transceive_sync(const struct device *dev, + const struct spi_config *config, + const struct spi_buf_set *tx_bufs, + const struct spi_buf_set *rx_bufs) +{ + return spi_cc35xx_transceive(dev, config, tx_bufs, rx_bufs, NULL, NULL, 0); +} + +static const struct spi_driver_api spi_cc35xx_driver_api = { + .transceive = spi_cc35xx_transceive_sync, +#ifdef CONFIG_SPI_ASYNC + .transceive_async = spi_cc35xx_transceive_async, +#endif + .release = spi_cc35xx_release, +}; + +static enum cc35xx_pm_resource spi_cc35xx_power_id(uint32_t base) +{ + switch (base) { + case SPI0_BASE: + return CC35XX_PM_RESOURCE_SPI0; + default: + return CC35XX_PM_RESOURCE_SPI1; + } +} + +#ifdef CONFIG_PM_DEVICE +static int spi_cc35xx_pm_action(const struct device *dev, + enum pm_device_action action) +{ + const struct spi_cc35xx_config *cfg = dev->config; + int ret; + + switch (action) { + case PM_DEVICE_ACTION_SUSPEND: + SPIDisable(cfg->base); + SPIDisableInt(cfg->base, SPI_INT_ALL); + return cc35xx_pm_resource_put(spi_cc35xx_power_id(cfg->base)); + case PM_DEVICE_ACTION_RESUME: + ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); + if (ret < 0) { + return ret; + } + ret = cc35xx_pm_resource_get(spi_cc35xx_power_id(cfg->base)); + if (ret < 0) { + return ret; + } + SPIDisable(cfg->base); + SPIDisableInt(cfg->base, SPI_INT_ALL); + return 0; + default: + return -ENOTSUP; + } +} +#endif /* CONFIG_PM_DEVICE */ + +#define SPI_CC35XX_DEVICE_INIT(n) \ + PM_DEVICE_DT_INST_DEFINE(n, spi_cc35xx_pm_action); \ + DEVICE_DT_INST_DEFINE(n, spi_cc35xx_init_##n, PM_DEVICE_DT_INST_GET(n), \ + &spi_cc35xx_data_##n, &spi_cc35xx_config_##n, POST_KERNEL, \ + CONFIG_SPI_INIT_PRIORITY, &spi_cc35xx_driver_api) + +#define SPI_CC35XX_INIT_FUNC(n) \ + static int spi_cc35xx_init_##n(const struct device *dev) \ + { \ + struct spi_cc35xx_data *data = dev->data; \ + const struct spi_cc35xx_config *cfg = dev->config; \ + int err; \ + \ + data->ctx.config = NULL; \ + err = spi_context_cs_configure_all(&data->ctx); \ + if (err < 0) \ + return err; \ + \ + err = cc35xx_pm_resource_get(spi_cc35xx_power_id(cfg->base)); \ + if (err < 0) \ + return err; \ + \ + spi_context_unlock_unconditionally(&data->ctx); \ + SPIDisable(cfg->base); \ + SPIDisableInt(cfg->base, SPI_INT_ALL); \ + IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), spi_cc35xx_isr, \ + DEVICE_DT_INST_GET(n), 0); \ + irq_enable(DT_INST_IRQN(n)); \ + \ + return 0; \ + } + +#define SPI_CC35XX_INIT(n) \ + PINCTRL_DT_INST_DEFINE(n); \ + SPI_CC35XX_INIT_FUNC(n) \ + \ + static const struct spi_cc35xx_config spi_cc35xx_config_##n = { \ + .base = DT_INST_REG_ADDR(n), \ + .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \ + .sys_clk_freq = DT_INST_PROP_BY_PHANDLE(n, clocks, clock_frequency), \ + }; \ + \ + static struct spi_cc35xx_data spi_cc35xx_data_##n = { \ + SPI_CONTEXT_INIT_LOCK(spi_cc35xx_data_##n, ctx), \ + SPI_CONTEXT_INIT_SYNC(spi_cc35xx_data_##n, ctx), \ + SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(n), ctx)}; \ + \ + SPI_CC35XX_DEVICE_INIT(n); + +DT_INST_FOREACH_STATUS_OKAY(SPI_CC35XX_INIT) diff --git a/dts/arm/ti/cc35xxe.dtsi b/dts/arm/ti/cc35xxe.dtsi index ce949db2a49e..d72aaf5c2d67 100644 --- a/dts/arm/ti/cc35xxe.dtsi +++ b/dts/arm/ti/cc35xxe.dtsi @@ -10,12 +10,16 @@ #define INT_SP_UART_0_INT_REQ 16 #define INT_SP_UART_1_INT_REQ 17 +#define INT_SP_SPI_0_EVT_REQ 20 +#define INT_SP_SPI_1_EVT_REQ 21 /* * Note: Zephyr uses exception numbers, vs the IRQ used by the CC32XX SDK * which are offset by 16: */ #define EXP_UARTA0 (INT_SP_UART_0_INT_REQ - 16) #define EXP_UARTA1 (INT_SP_UART_1_INT_REQ - 16) +#define EXP_SPI0 (INT_SP_SPI_0_EVT_REQ - 16) +#define EXP_SPI1 (INT_SP_SPI_1_EVT_REQ - 16) / { cpus { @@ -47,6 +51,12 @@ #clock-cells = <0>; }; + spiclk: spi-clock { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + soc { /* I-Cache and ITCM size options can be configured independently The user can * decide how to split ITCM and I-Cache in the following configurations: @@ -229,6 +239,26 @@ write-block-size = <4>; status = "disabled"; }; + + spi0: spi@41220000 { + compatible = "ti,cc35xx-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x41220000 0x10000>; + interrupts = ; + clocks = <&spiclk>; + status = "disabled"; + }; + + spi1: spi@41230000 { + compatible = "ti,cc35xx-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x41230000 0x10000>; + interrupts = ; + clocks = <&spiclk>; + status = "disabled"; + }; }; }; diff --git a/dts/bindings/spi/ti,cc35xx-spi.yaml b/dts/bindings/spi/ti,cc35xx-spi.yaml new file mode 100644 index 000000000000..6692ed82ebc4 --- /dev/null +++ b/dts/bindings/spi/ti,cc35xx-spi.yaml @@ -0,0 +1,12 @@ +# Copyright (c) 2019 Brett Witherspoon +# SPDX-License-Identifier: Apache-2.0 + +description: TI SimpleLink CC35xx + +compatible: "ti,cc35xx-spi" + +include: [spi-controller.yaml, pinctrl-device.yaml, base.yaml] + +properties: + reg: + required: true From 0f7e5844ec3fad19037a7cdcf55d5dd4384646d9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=81yszczek?= Date: Mon, 6 Oct 2025 09:08:43 +0200 Subject: [PATCH 030/100] UPSTREAM-PEND: tests: add twister tests, fix some drivers according to t... MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ...ests - add twisters tests - fix issues in uart, flash and soc accord to tests, all tests pass now Signed-off-by: Michał Łyszczek --- drivers/spi/spi_cc35xx.c | 6 ++++-- .../boards/lp_em_cc35x1.conf | 1 + .../boards/lp_em_cc35x1.overlay | 16 ++++++++++++++++ .../spi/spi_controller_peripheral/testcase.yaml | 3 +++ .../spi/spi_loopback/boards/lp_em_cc35x1.conf | 1 + .../spi/spi_loopback/boards/lp_em_cc35x1.overlay | 16 ++++++++++++++++ 6 files changed, 41 insertions(+), 2 deletions(-) create mode 100644 tests/drivers/spi/spi_controller_peripheral/boards/lp_em_cc35x1.conf create mode 100644 tests/drivers/spi/spi_controller_peripheral/boards/lp_em_cc35x1.overlay create mode 100644 tests/drivers/spi/spi_loopback/boards/lp_em_cc35x1.conf create mode 100644 tests/drivers/spi/spi_loopback/boards/lp_em_cc35x1.overlay diff --git a/drivers/spi/spi_cc35xx.c b/drivers/spi/spi_cc35xx.c index 994794eed846..325247fe66f8 100644 --- a/drivers/spi/spi_cc35xx.c +++ b/drivers/spi/spi_cc35xx.c @@ -50,7 +50,9 @@ static void spi_cc35xx_read_rx_fifo(const struct device *dev) if (spi_context_rx_buf_on(ctx)) { *ctx->rx_buf = rxd; } - spi_context_update_rx(ctx, 1, 1); + if (spi_context_rx_on(ctx)) { + spi_context_update_rx(ctx, 1, 1); + } } } @@ -133,7 +135,7 @@ static int spi_cc35xx_configure(const struct device *dev, const struct spi_confi SPI_CTL0_SPH_SECOND : SPI_CTL0_SPH_FIRST; SPIConfigSetExpClk(cfg->base, cfg->sys_clk_freq, prot, mode, freq, 8); - sys_write32(SPI_IFLS_RXSEL_LVL_1_2 | SPI_IFLS_TXSEL_LVL_1_2, cfg->base + SPI_O_IFLS); + sys_write32(SPI_IFLS_RXSEL_LEVEL_1 | SPI_IFLS_TXSEL_LVL_1_2, cfg->base + SPI_O_IFLS); if (config->operation & SPI_TRANSFER_LSB) { sys_write32((sys_read32(cfg->base + SPI_O_CTL1) & ~SPI_CTL1_MSB_M) | SPI_CTL1_MSB_LSB, diff --git a/tests/drivers/spi/spi_controller_peripheral/boards/lp_em_cc35x1.conf b/tests/drivers/spi/spi_controller_peripheral/boards/lp_em_cc35x1.conf new file mode 100644 index 000000000000..3eb27a803420 --- /dev/null +++ b/tests/drivers/spi/spi_controller_peripheral/boards/lp_em_cc35x1.conf @@ -0,0 +1 @@ +CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=2048 diff --git a/tests/drivers/spi/spi_controller_peripheral/boards/lp_em_cc35x1.overlay b/tests/drivers/spi/spi_controller_peripheral/boards/lp_em_cc35x1.overlay new file mode 100644 index 000000000000..cb5a518add53 --- /dev/null +++ b/tests/drivers/spi/spi_controller_peripheral/boards/lp_em_cc35x1.overlay @@ -0,0 +1,16 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + */ + +&spi0 { + status = "okay"; + dut_spi_dt: test-spi-dev@0 { + compatible = "vnd,spi-device"; + reg = <0>; + spi-max-frequency = ; + }; +}; + +dut_spis: &spi1 { + status = "okay"; +}; diff --git a/tests/drivers/spi/spi_controller_peripheral/testcase.yaml b/tests/drivers/spi/spi_controller_peripheral/testcase.yaml index 1920bb095574..b04daec1bd17 100644 --- a/tests/drivers/spi/spi_controller_peripheral/testcase.yaml +++ b/tests/drivers/spi/spi_controller_peripheral/testcase.yaml @@ -17,6 +17,7 @@ common: - nrf54lm20dk/nrf54lm20a/cpuapp - nrf54lm20dk/nrf54lm20b/cpuapp - nrf7120dk/nrf7120/cpuapp + - lp_em_cc35x1 - ophelia4ev/nrf54l15/cpuapp tests: @@ -92,6 +93,7 @@ tests: - nrf54lm20dk/nrf54lm20a/cpuapp - nrf54lm20dk/nrf54lm20b/cpuapp - nrf7120dk/nrf7120/cpuapp + - lp_em_cc35x1 - ophelia4ev/nrf54l15/cpuapp drivers.spi.spis_fast: @@ -109,6 +111,7 @@ tests: - nrf54lm20dk/nrf54lm20a/cpuapp - nrf54lm20dk/nrf54lm20b/cpuapp - nrf7120dk/nrf7120/cpuapp + - lp_em_cc35x1 - ophelia4ev/nrf54l15/cpuapp drivers.spi.pm_runtime: diff --git a/tests/drivers/spi/spi_loopback/boards/lp_em_cc35x1.conf b/tests/drivers/spi/spi_loopback/boards/lp_em_cc35x1.conf new file mode 100644 index 000000000000..b89b107d9f70 --- /dev/null +++ b/tests/drivers/spi/spi_loopback/boards/lp_em_cc35x1.conf @@ -0,0 +1 @@ +CONFIG_TEST_EXTRA_STACK_SIZE=2048 diff --git a/tests/drivers/spi/spi_loopback/boards/lp_em_cc35x1.overlay b/tests/drivers/spi/spi_loopback/boards/lp_em_cc35x1.overlay new file mode 100644 index 000000000000..b0ef13487321 --- /dev/null +++ b/tests/drivers/spi/spi_loopback/boards/lp_em_cc35x1.overlay @@ -0,0 +1,16 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + */ + +&spi0 { + slow@0 { + compatible = "test-spi-loopback-slow"; + reg = <0>; + spi-max-frequency = <100000>; + }; + fast@0 { + compatible = "test-spi-loopback-fast"; + reg = <0>; + spi-max-frequency = ; + }; +}; From 9ccf3b44d0498ca8d93e6d514cf89299d24ea970 Mon Sep 17 00:00:00 2001 From: Radoslaw Adamczyk Date: Mon, 16 Mar 2026 10:17:03 +0100 Subject: [PATCH 031/100] UPSTREAM-PEND: drivers: spi: cc35xxe: Support for DMA (+ASYNC) Added support for DMA Added support for Async transfers Signed-off-by: Radoslaw Adamczyk --- .../ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi | 7 + drivers/spi/Kconfig.cc35xx | 12 + drivers/spi/spi_cc35xx.c | 515 +++++++++++++++--- dts/bindings/spi/ti,cc35xx-spi.yaml | 30 +- .../boards/lp_em_cc35x1.overlay | 2 +- 5 files changed, 478 insertions(+), 88 deletions(-) diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi index be4348ff44db..56f8e25cf587 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi @@ -8,6 +8,7 @@ #include #include +#include #include "boosterpack_connector.dtsi" #include "lp_em_cc35x1-pinctrl.dtsi" @@ -99,12 +100,18 @@ pinctrl-0 = <&spi0_master>; pinctrl-names = "default"; cs-gpios = <&gpios 26 GPIO_ACTIVE_LOW>; + dmas = <&dma 4 CC35XX_DMA_SET_CONFIG(CC35xx_DMA_PERIPH_SPI_0)>, + <&dma 5 CC35XX_DMA_SET_CONFIG(CC35xx_DMA_PERIPH_SPI_0)>; + dma-names = "tx", "rx"; }; &spi1 { status = "okay"; pinctrl-0 = <&spi1_slave>; pinctrl-names = "default"; + dmas = <&dma 8 CC35XX_DMA_SET_CONFIG(CC35xx_DMA_PERIPH_SPI_1)>, + <&dma 9 CC35XX_DMA_SET_CONFIG(CC35xx_DMA_PERIPH_SPI_1)>; + dma-names = "tx", "rx"; }; &flash0 { diff --git a/drivers/spi/Kconfig.cc35xx b/drivers/spi/Kconfig.cc35xx index 9089e5326d6a..0f54f2d31ee6 100644 --- a/drivers/spi/Kconfig.cc35xx +++ b/drivers/spi/Kconfig.cc35xx @@ -1,3 +1,4 @@ +# Copyright (c) 2025-2026 Conclusive Engineering # SPDX-License-Identifier: Apache-2.0 config SPI_CC35XX @@ -7,3 +8,14 @@ config SPI_CC35XX select PINCTRL help Enable support for the TI SimpleLink CC35xx SPI peripheral + +if SPI_CC35XX + +config SPI_CC35XX_DMA_DRIVEN + bool "CC35XX SPI DMA support" + default n + select DMA + help + Enables DMA for SPI transfers. + +endif # SPI_CC35XX diff --git a/drivers/spi/spi_cc35xx.c b/drivers/spi/spi_cc35xx.c index 325247fe66f8..91d31a529e27 100644 --- a/drivers/spi/spi_cc35xx.c +++ b/drivers/spi/spi_cc35xx.c @@ -6,18 +6,23 @@ #define DT_DRV_COMPAT ti_cc35xx_spi -#define LOG_LEVEL CONFIG_SPI_LOG_LEVEL #include -LOG_MODULE_REGISTER(spi_cc35xx); -#include +LOG_MODULE_REGISTER(spi_cc35xx, CONFIG_SPI_LOG_LEVEL); + +#include #include +#include #include #include -#include +#include #include #include +#ifdef CONFIG_SPI_CC35XX_DMA_DRIVEN +#include +#include +#endif /* CONFIG_SPI_CC35XX_DMA_DRIVEN */ #include "spi_context.h" @@ -26,19 +31,60 @@ LOG_MODULE_REGISTER(spi_cc35xx); SPI_MIS_TXEMPTY_SET | SPI_MIS_PER_SET | SPI_MIS_RTOUT_SET | SPI_MIS_DMARX_SET | \ SPI_MIS_DMATX_SET) #define IDLE_CHAR 0x00 -#define SPI_SLAVE_BUS_MAX_FREQ 40000000l +#define SPI_SLAVE_BUS_MAX_FREQ 40000000L + +#define SPI_CC35XX_DATA_WIDTH 8 +#define SPI_CC35XX_DFS (SPI_CC35XX_DATA_WIDTH >> 3) + +#ifdef CONFIG_SPI_CC35XX_DMA_DRIVEN + +static uint32_t dummy_tx = IDLE_CHAR; +static uint32_t dummy_rx; + +#define SPI_CC35XX_DMA_RX_TRANSFER_DONE BIT(0) +#define SPI_CC35XX_DMA_TX_TRANSFER_DONE BIT(1) + +enum transfer_direction { + SPI_CC35XX_TRANSFER_DIR_NONE, + SPI_CC35XX_TRANSFER_DIR_TX, + SPI_CC35XX_TRANSFER_DIR_RX, + SPI_CC35XX_TRANSFER_DIR_BOTH +}; + +struct spi_cc35xx_dma_stream { + const struct device *dev_dma; + uint32_t dma_channel; + struct dma_config dma_cfg; + struct dma_block_config blk_cfg; + size_t transfer_length; +}; +#endif /* CONFIG_SPI_CC35XX_DMA_DRIVEN */ struct spi_cc35xx_config { uint32_t base; const struct pinctrl_dev_config *pcfg; uint32_t sys_clk_freq; + const uint8_t irq_num; }; struct spi_cc35xx_data { struct spi_context ctx; +#ifdef CONFIG_SPI_CC35XX_DMA_DRIVEN + struct spi_cc35xx_dma_stream dma_rx; + struct spi_cc35xx_dma_stream dma_tx; + uint8_t dma_status_flags; +#endif /* CONFIG_SPI_CC35XX_DMA_DRIVEN */ size_t rxleft; }; +#ifdef CONFIG_SPI_CC35XX_DMA_DRIVEN +static int spi_cc35xx_dma_start(const struct device *dev, enum transfer_direction dir); +static void spi_cc35xx_dma_stop(const struct device *dev); +static int spi_cc35xx_dma_load_tx(const struct device *dev, + const uint8_t *tx_data, size_t buf_size); +static int spi_cc35xx_dma_load_rx(const struct device *dev, uint8_t *rx_data, size_t buf_size); +#endif /* CONFIG_SPI_CC35XX_DMA_DRIVEN */ + static void spi_cc35xx_read_rx_fifo(const struct device *dev) { const struct spi_cc35xx_config *cfg = dev->config; @@ -51,7 +97,7 @@ static void spi_cc35xx_read_rx_fifo(const struct device *dev) *ctx->rx_buf = rxd; } if (spi_context_rx_on(ctx)) { - spi_context_update_rx(ctx, 1, 1); + spi_context_update_rx(ctx, SPI_CC35XX_DFS, 1); } } } @@ -79,17 +125,22 @@ static void spi_cc35xx_fill_tx_fifo(const struct device *dev) if (spi_context_tx_buf_on(ctx)) { txd = *ctx->tx_buf; } - spi_context_update_tx(ctx, 1, 1); - + if (spi_context_tx_on(ctx)) { + spi_context_update_tx(ctx, SPI_CC35XX_DFS, 1); + } SPIPutData(cfg->base, txd); } } -static void spi_cc35xx_flush_fifo(mem_addr_t base) +static void spi_cc35xx_flush_fifo(const struct device *dev) { - sys_write32(sys_read32(base + SPI_O_CTL0) | SPI_CTL0_FIFORST_RST_TRIG | - SPI_CTL0_IDLEPOCI_IDLE_ONE, base + SPI_O_CTL0); - while (sys_read32(base + SPI_O_CTL0) & SPI_CTL0_FIFORST) { + const struct spi_cc35xx_config *cfg = dev->config; + + sys_write32(sys_read32(cfg->base + SPI_O_CTL0) | SPI_CTL0_FIFORST_RST_TRIG | + SPI_CTL0_IDLEPOCI_IDLE_ONE, cfg->base + SPI_O_CTL0); + + while (sys_read32(cfg->base + SPI_O_CTL0) & SPI_CTL0_FIFORST) { + /* NOP */ } } @@ -127,6 +178,10 @@ static int spi_cc35xx_configure(const struct device *dev, const struct spi_confi } mode = is_master ? SPI_MODE_CONTROLLER : SPI_MODE_PERIPHERAL; + if (config->operation & SPI_MODE_LOOP) { + mode |= SPI_CTL1_LBM_ENABLE; + } + prot = is_master ? SPI_CTL0_FRF_MOTOROLA_3WIRE : SPI_CTL0_FRF_MOTOROLA_4WIRE; freq = is_master ? config->frequency : SPI_SLAVE_BUS_MAX_FREQ; prot |= SPI_MODE_GET(config->operation) & SPI_MODE_CPOL ? @@ -136,92 +191,195 @@ static int spi_cc35xx_configure(const struct device *dev, const struct spi_confi SPIConfigSetExpClk(cfg->base, cfg->sys_clk_freq, prot, mode, freq, 8); sys_write32(SPI_IFLS_RXSEL_LEVEL_1 | SPI_IFLS_TXSEL_LVL_1_2, cfg->base + SPI_O_IFLS); + if (config->operation & SPI_TRANSFER_LSB) { sys_write32((sys_read32(cfg->base + SPI_O_CTL1) & ~SPI_CTL1_MSB_M) | SPI_CTL1_MSB_LSB, cfg->base + SPI_O_CTL1); } - SPIEnable(cfg->base); sys_write32(BIT(0), cfg->base + SPI_O_CLKCFG); - spi_cc35xx_flush_fifo(cfg->base); + + SPIEnable(cfg->base); + + spi_cc35xx_flush_fifo(dev); ctx->config = config; return 0; } +#ifdef CONFIG_SPI_CC35XX_DMA_DRIVEN +static inline size_t spi_cc35xx_dma_transfer_size(const struct device *dev) +{ + struct spi_cc35xx_data *data = dev->data; + + if (data->ctx.rx_len == 0) { + return data->ctx.tx_len; + } else if (data->ctx.tx_len == 0) { + return data->ctx.rx_len; + } else { + return MIN(data->ctx.tx_len, data->ctx.rx_len); + } +} + +static int spi_cc35xx_dma_transmit_next_packet(const struct device *dev, + enum transfer_direction dir) +{ + struct spi_cc35xx_data *data = dev->data; + struct spi_context *ctx = &data->ctx; + int ret; + size_t tx_dma_len; + size_t rx_dma_len; + + if ((dir == SPI_CC35XX_TRANSFER_DIR_RX) || (dir == SPI_CC35XX_TRANSFER_DIR_BOTH)) { + if (dir == SPI_CC35XX_TRANSFER_DIR_RX) { + rx_dma_len = ctx->rx_len ? ctx->rx_len : + ctx->tx_len - data->dma_tx.transfer_length; + data->dma_rx.transfer_length = ctx->rx_len ? rx_dma_len : 0; + } else { + rx_dma_len = spi_cc35xx_dma_transfer_size(dev); + data->dma_rx.transfer_length = rx_dma_len; + } + if (data->dma_rx.dev_dma && rx_dma_len) { + ret = spi_cc35xx_dma_load_rx(dev, ctx->rx_buf, rx_dma_len); + if (ret) { + LOG_ERR("%s: Failed load RX DMA", dev->name); + return ret; + } + } else { + dir = (dir == SPI_CC35XX_TRANSFER_DIR_BOTH) ? SPI_CC35XX_TRANSFER_DIR_TX : + SPI_CC35XX_TRANSFER_DIR_NONE; + } + + data->dma_status_flags &= ~SPI_CC35XX_DMA_RX_TRANSFER_DONE; + } + + if ((dir == SPI_CC35XX_TRANSFER_DIR_TX) || (dir == SPI_CC35XX_TRANSFER_DIR_BOTH)) { + if (dir == SPI_CC35XX_TRANSFER_DIR_TX) { + tx_dma_len = ctx->tx_len ? ctx->tx_len : + ctx->rx_len - data->dma_rx.transfer_length; + data->dma_tx.transfer_length = ctx->tx_len ? tx_dma_len : 0; + } else { + tx_dma_len = spi_cc35xx_dma_transfer_size(dev); + data->dma_tx.transfer_length = tx_dma_len; + } + if (data->dma_tx.dev_dma && tx_dma_len) { + ret = spi_cc35xx_dma_load_tx(dev, ctx->tx_buf, tx_dma_len); + if (ret) { + LOG_ERR("%s: Failed load TX DMA", dev->name); + return ret; + } + } else { + dir = (dir == SPI_CC35XX_TRANSFER_DIR_BOTH) ? SPI_CC35XX_TRANSFER_DIR_RX : + SPI_CC35XX_TRANSFER_DIR_NONE; + } + + data->dma_status_flags &= ~SPI_CC35XX_DMA_TX_TRANSFER_DONE; + } + + spi_cc35xx_dma_start(dev, dir); + + return 0; +} +#else static void spi_cc35xx_master_transceive(const struct device *dev) { const struct spi_cc35xx_config *cfg = dev->config; struct spi_cc35xx_data *data = dev->data; struct spi_context *ctx = &data->ctx; - spi_cc35xx_flush_fifo(cfg->base); + spi_cc35xx_flush_fifo(dev); spi_context_cs_control(ctx, true); - spi_cc35xx_fill_tx_fifo(dev); + SPIClearInt(cfg->base, SPI_MIS_TX_SET); SPIEnableInt(cfg->base, SPI_MIS_TX_SET); } #ifdef CONFIG_SPI_SLAVE - static void spi_cc35xx_slave_transceive(const struct device *dev) { const struct spi_cc35xx_config *cfg = dev->config; - spi_cc35xx_flush_fifo(cfg->base); + spi_cc35xx_flush_fifo(dev); spi_cc35xx_fill_tx_fifo(dev); + SPIClearInt(cfg->base, SPI_MIS_RX_SET); SPIEnableInt(cfg->base, SPI_MIS_RX_SET); } -#endif +#endif /* CONFIG_SPI_SLAVE */ +#endif /* CONFIG_SPI_CC35XX_DMA_DRIVEN */ static int spi_cc35xx_transceive(const struct device *dev, const struct spi_config *config, const struct spi_buf_set *tx_bufs, const struct spi_buf_set *rx_bufs, - spi_callback_t cb, void *userdata, int async) + spi_callback_t cb, void *userdata, bool async) { struct spi_cc35xx_data *data = dev->data; struct spi_context *ctx = &data->ctx; - int err; + int ret; spi_context_lock(ctx, async, cb, userdata, config); - pm_policy_state_lock_get(PM_STATE_RUNTIME_IDLE, PM_ALL_SUBSTATES); - pm_policy_state_lock_get(PM_STATE_STANDBY, PM_ALL_SUBSTATES); + ret = spi_cc35xx_configure(dev, config); + if (ret) { + goto ctx_release; + } - err = spi_cc35xx_configure(dev, config); - if (err) { - goto done; + spi_cc35xx_flush_fifo(dev); + + spi_context_buffers_setup(ctx, tx_bufs, rx_bufs, SPI_CC35XX_DFS); + + if (!spi_context_rx_buf_on(ctx) && !spi_context_tx_buf_on(ctx)) { + goto ctx_release; + } + +#ifdef CONFIG_SPI_CC35XX_DMA_DRIVEN +#ifdef CONFIG_SPI_SLAVE + if (!spi_context_is_slave(ctx)) { + spi_context_cs_control(ctx, true); } +#else + spi_context_cs_control(ctx, true); +#endif /* CONFIG_SPI_SLAVE */ - spi_context_buffers_setup(ctx, tx_bufs, rx_bufs, 1); + spi_cc35xx_dma_transmit_next_packet(dev, SPI_CC35XX_TRANSFER_DIR_BOTH); +#else data->rxleft = spi_context_total_rx_len(ctx); -#ifdef CONFIG_SPI_SLAVE - if (spi_context_is_slave(ctx)) { + if (IS_ENABLED(CONFIG_SPI_SLAVE) && spi_context_is_slave(ctx)) { spi_cc35xx_slave_transceive(dev); - } else -#endif - { + } else { spi_cc35xx_master_transceive(dev); } +#endif /* CONFIG_SPI_CC35XX_DMA_DRIVEN */ -done: - spi_context_wait_for_completion(ctx); + ret = spi_context_wait_for_completion(ctx); - pm_policy_state_lock_put(PM_STATE_STANDBY, PM_ALL_SUBSTATES); - pm_policy_state_lock_put(PM_STATE_RUNTIME_IDLE, PM_ALL_SUBSTATES); + if (async) { + spi_context_release(ctx, ret); + return 0; + } - spi_context_release(ctx, err); +ctx_release: #ifdef CONFIG_SPI_SLAVE - if (spi_context_is_slave(ctx) && !err) { - err = ctx->recv_frames; + if (!spi_context_is_slave(ctx)) { + if (!(ctx->config->operation & SPI_HOLD_ON_CS)) { + spi_context_cs_control(ctx, false); + } + } else if (!ret) { + ret = data->ctx.recv_frames; } -#endif - - return err; +#else + if (!(ctx->config->operation & SPI_HOLD_ON_CS)) { + spi_context_cs_control(ctx, false); + } +#endif /* CONFIG_SPI_SLAVE */ +#ifdef CONFIG_SPI_CC35XX_DMA_DRIVEN + spi_cc35xx_dma_stop(dev); +#endif /* CONFIG_SPI_CC35XX_DMA_DRIVEN */ + spi_context_release(ctx, ret); + return ret; } static int spi_cc35xx_release(const struct device *dev, const struct spi_config *config) @@ -248,7 +406,8 @@ static void spi_cc35xx_isr(const struct device *dev) const struct spi_cc35xx_config *cfg = dev->config; struct spi_cc35xx_data *data = dev->data; struct spi_context *ctx = &data->ctx; - uint32_t txrx_irq = SPIIntStatus(cfg->base, true) & (SPI_MIS_RX | SPI_MIS_TX); + uint32_t irq_status = SPIIntStatus(cfg->base, true); + uint32_t txrx_irq = irq_status & (SPI_MIS_RX | SPI_MIS_TX); if (txrx_irq) { SPIClearInt(cfg->base, txrx_irq); @@ -269,12 +428,90 @@ static void spi_cc35xx_isr(const struct device *dev) spi_cc35xx_fill_tx_fifo(dev); } - if (SPIIntStatus(cfg->base, true) & SPI_MIS_IDLE) { + if (irq_status & SPI_MIS_IDLE) { SPIDisableInt(cfg->base, SPI_MIS_IDLE); SPIClearInt(cfg->base, SPI_MIS_IDLE); spi_context_cs_control(ctx, false); spi_context_complete(ctx, dev, 0); } + + if (irq_status & SPI_MIS_RXOVF) { + SPIClearInt(cfg->base, SPI_MIS_RXOVF); + LOG_ERR("%s: RX overflow occurred", dev->name); + spi_cc35xx_read_rx_fifo(dev); + /* flush RX FIFO to clear overflow condition */ + spi_cc35xx_flush_fifo(dev); + spi_context_cs_control(ctx, false); + spi_context_complete(ctx, dev, -EIO); + } + +#ifdef CONFIG_SPI_CC35XX_DMA_DRIVEN + if (irq_status & SPI_MIS_DMARX) { + SPIDisableInt(cfg->base, SPI_MIS_DMARX); + SPIClearInt(cfg->base, SPI_MIS_DMARX); + data->dma_status_flags |= SPI_CC35XX_DMA_RX_TRANSFER_DONE; + } + + if (irq_status & SPI_MIS_DMATX) { + SPIDisableInt(cfg->base, SPI_MIS_DMATX); + SPIClearInt(cfg->base, SPI_MIS_DMATX); + data->dma_status_flags |= SPI_CC35XX_DMA_TX_TRANSFER_DONE; + } + +#ifdef CONFIG_SPI_SLAVE + if (spi_context_is_slave(ctx)) { + + bool tx_done = data->dma_status_flags & SPI_CC35XX_DMA_TX_TRANSFER_DONE; + bool rx_done = data->dma_status_flags & SPI_CC35XX_DMA_RX_TRANSFER_DONE; + + if (rx_done) { + spi_context_update_rx(&data->ctx, SPI_CC35XX_DFS, + data->ctx.rx_len ? data->dma_rx.transfer_length : 0); + } + if (tx_done) { + spi_context_update_tx(&data->ctx, SPI_CC35XX_DFS, + data->ctx.tx_len ? data->dma_tx.transfer_length : 0); + } + + if (!spi_context_rx_buf_on(ctx) && !spi_context_tx_buf_on(ctx)) { + /* nothing left to rx or tx, we're done! */ + spi_cc35xx_dma_stop(dev); + spi_context_complete(&data->ctx, dev, 0); + + return; + } + + if (rx_done) { + spi_cc35xx_dma_transmit_next_packet(dev, SPI_CC35XX_TRANSFER_DIR_RX); + } + + if (tx_done) { + spi_cc35xx_dma_transmit_next_packet(dev, SPI_CC35XX_TRANSFER_DIR_TX); + } + return; + } +#endif /* CONFIG_SPI_SLAVE */ + + if (data->dma_status_flags == (SPI_CC35XX_DMA_RX_TRANSFER_DONE | + SPI_CC35XX_DMA_TX_TRANSFER_DONE)) { + spi_context_update_rx(&data->ctx, SPI_CC35XX_DFS, + data->ctx.rx_len ? data->dma_rx.transfer_length : 0); + spi_context_update_tx(&data->ctx, SPI_CC35XX_DFS, + data->ctx.tx_len ? data->dma_tx.transfer_length : 0); + + if (!spi_context_rx_buf_on(ctx) && !spi_context_tx_buf_on(ctx)) { + /* nothing left to rx or tx, we're done! */ + spi_context_cs_control(&data->ctx, false); + spi_cc35xx_dma_stop(dev); + spi_context_complete(&data->ctx, dev, 0); + + return; + } + + spi_cc35xx_dma_transmit_next_packet(dev, SPI_CC35XX_TRANSFER_DIR_BOTH); + } +#endif /* CONFIG_SPI_CC35XX_DMA_DRIVEN */ + } #ifdef CONFIG_SPI_ASYNC @@ -284,71 +521,172 @@ static int spi_cc35xx_transceive_async(const struct device *dev, const struct spi_buf_set *rx_bufs, spi_callback_t cb, void *userdata) { - return spi_cc35xx_transceive(dev, config, tx_bufs, rx_bufs, cb, userdata, 1); + return spi_cc35xx_transceive(dev, config, tx_bufs, rx_bufs, cb, userdata, true); } -#endif +#endif /* CONFIG_SPI_ASYNC */ static int spi_cc35xx_transceive_sync(const struct device *dev, const struct spi_config *config, const struct spi_buf_set *tx_bufs, const struct spi_buf_set *rx_bufs) { - return spi_cc35xx_transceive(dev, config, tx_bufs, rx_bufs, NULL, NULL, 0); + return spi_cc35xx_transceive(dev, config, tx_bufs, rx_bufs, NULL, NULL, false); } static const struct spi_driver_api spi_cc35xx_driver_api = { .transceive = spi_cc35xx_transceive_sync, #ifdef CONFIG_SPI_ASYNC .transceive_async = spi_cc35xx_transceive_async, -#endif +#endif /* CONFIG_SPI_ASYNC */ .release = spi_cc35xx_release, }; -static enum cc35xx_pm_resource spi_cc35xx_power_id(uint32_t base) +#ifdef CONFIG_SPI_CC35XX_DMA_DRIVEN +static void spi_cc35xx_dma_stop(const struct device *dev) +{ + const struct spi_cc35xx_config *cfg = dev->config; + struct spi_cc35xx_data *data = dev->data; + + SPIDisableDMA(cfg->base, SPI_DMACR_TXEN | SPI_DMACR_RXEN); + SPIDisableInt(cfg->base, SPI_MIS_DMATX_SET | SPI_MIS_DMARX_SET | SPI_MIS_RXOVF); + dma_stop(data->dma_rx.dev_dma, data->dma_rx.dma_channel); + dma_stop(data->dma_tx.dev_dma, data->dma_tx.dma_channel); +} + +static int spi_cc35xx_dma_load_tx(const struct device *dev, const uint8_t *tx_data, size_t buf_size) { - switch (base) { - case SPI0_BASE: - return CC35XX_PM_RESOURCE_SPI0; - default: - return CC35XX_PM_RESOURCE_SPI1; + const struct spi_cc35xx_config *cfg = dev->config; + struct spi_cc35xx_data *data = dev->data; + struct spi_context *ctx = &data->ctx; + int ret; + + data->dma_tx.blk_cfg.dest_address = cfg->base + SPI_O_TXDATA; + data->dma_tx.blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; + data->dma_tx.blk_cfg.block_size = buf_size; + if (spi_context_tx_buf_on(ctx)) { + data->dma_tx.blk_cfg.source_address = (uint32_t)tx_data; + data->dma_tx.blk_cfg.source_addr_adj = DMA_ADDR_ADJ_INCREMENT; + } else { + data->dma_tx.blk_cfg.source_address = (uint32_t)&dummy_tx; + data->dma_tx.blk_cfg.source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; } + + ret = dma_config(data->dma_tx.dev_dma, data->dma_tx.dma_channel, &data->dma_tx.dma_cfg); + + return ret; } -#ifdef CONFIG_PM_DEVICE -static int spi_cc35xx_pm_action(const struct device *dev, - enum pm_device_action action) +static int spi_cc35xx_dma_load_rx(const struct device *dev, uint8_t *rx_data, size_t buf_size) { const struct spi_cc35xx_config *cfg = dev->config; + struct spi_cc35xx_data *data = dev->data; + struct spi_context *ctx = &data->ctx; int ret; - switch (action) { - case PM_DEVICE_ACTION_SUSPEND: - SPIDisable(cfg->base); - SPIDisableInt(cfg->base, SPI_INT_ALL); - return cc35xx_pm_resource_put(spi_cc35xx_power_id(cfg->base)); - case PM_DEVICE_ACTION_RESUME: - ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); - if (ret < 0) { + data->dma_rx.blk_cfg.source_address = cfg->base + SPI_O_RXDATA; + data->dma_rx.blk_cfg.source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; + data->dma_rx.blk_cfg.block_size = buf_size; + + if (spi_context_rx_buf_on(ctx)) { + data->dma_rx.blk_cfg.dest_address = (uint32_t)rx_data; + data->dma_rx.blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_INCREMENT; + } else { + data->dma_rx.blk_cfg.dest_address = (uint32_t)&dummy_rx; + data->dma_rx.blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; + } + + ret = dma_config(data->dma_rx.dev_dma, data->dma_rx.dma_channel, &data->dma_rx.dma_cfg); + + return ret; +} + +static int spi_cc35xx_dma_start(const struct device *dev, enum transfer_direction dir) +{ + const struct spi_cc35xx_config *cfg = dev->config; + struct spi_cc35xx_data *data = dev->data; + int ret; + + if ((dir == SPI_CC35XX_TRANSFER_DIR_TX) || (dir == SPI_CC35XX_TRANSFER_DIR_BOTH)) { + SPIDisableDMA(cfg->base, SPI_DMACR_TXEN); + + SPIClearInt(cfg->base, SPI_MIS_DMATX_SET); + SPIEnableInt(cfg->base, SPI_MIS_DMATX_SET); + + ret = dma_start(data->dma_tx.dev_dma, data->dma_tx.dma_channel); + if (ret) { return ret; } - ret = cc35xx_pm_resource_get(spi_cc35xx_power_id(cfg->base)); - if (ret < 0) { + SPIEnableDMA(cfg->base, SPI_DMACR_TXEN); + + } + + if ((dir == SPI_CC35XX_TRANSFER_DIR_RX) || (dir == SPI_CC35XX_TRANSFER_DIR_BOTH)) { + SPIDisableDMA(cfg->base, SPI_DMACR_RXEN); + + SPIClearInt(cfg->base, SPI_MIS_DMARX_SET | SPI_MIS_RXOVF); + SPIEnableInt(cfg->base, SPI_MIS_DMARX_SET | SPI_MIS_RXOVF); + + ret = dma_start(data->dma_rx.dev_dma, data->dma_rx.dma_channel); + if (ret) { return ret; } - SPIDisable(cfg->base); - SPIDisableInt(cfg->base, SPI_INT_ALL); - return 0; - default: - return -ENOTSUP; + + SPIEnableDMA(cfg->base, SPI_DMACR_RXEN); } + + return 0; } -#endif /* CONFIG_PM_DEVICE */ +static int spi_cc35xx_dma_init(const struct device *dev) +{ + const struct spi_cc35xx_config *cfg = dev->config; + struct spi_cc35xx_data *data = dev->data; -#define SPI_CC35XX_DEVICE_INIT(n) \ - PM_DEVICE_DT_INST_DEFINE(n, spi_cc35xx_pm_action); \ - DEVICE_DT_INST_DEFINE(n, spi_cc35xx_init_##n, PM_DEVICE_DT_INST_GET(n), \ - &spi_cc35xx_data_##n, &spi_cc35xx_config_##n, POST_KERNEL, \ - CONFIG_SPI_INIT_PRIORITY, &spi_cc35xx_driver_api) + if (data->dma_rx.dev_dma != NULL) { + if (!device_is_ready(data->dma_rx.dev_dma)) { + LOG_ERR("%s: RX DMA channel not ready", dev->name); + return -ENODEV; + } + data->dma_rx.dma_cfg.head_block = &data->dma_rx.blk_cfg; + data->dma_rx.dma_cfg.user_data = (void *)data; + } + + if (data->dma_tx.dev_dma != NULL) { + if (!device_is_ready(data->dma_tx.dev_dma)) { + LOG_ERR("%s: TX DMA channel not ready", dev->name); + return -ENODEV; + } + data->dma_tx.dma_cfg.head_block = &data->dma_tx.blk_cfg; + data->dma_tx.dma_cfg.user_data = (void *)data; + } + + return 0; +} + + +#define SPI_CC35XX_DMA_CHANNEL_INIT(n, dir, ch_dir, src_burst, dst_burst) \ + .dev_dma = DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(n, dir)), \ + .dma_channel = DT_INST_DMAS_CELL_BY_NAME(n, dir, channel), \ + .dma_cfg = { \ + .dma_slot = DT_INST_DMAS_CELL_BY_NAME(n, dir, channel_config), \ + .channel_direction = ch_dir, \ + .source_data_size = 1, \ + .dest_data_size = 1, \ + .source_burst_length = src_burst, \ + .dest_burst_length = dst_burst, \ + .block_count = 1, \ + } + +#define SPI_CC35XX_DMA_CHANNEL(n, dir, ch_dir, src_burst, dst_burst) \ + .dma_##dir = {COND_CODE_1( \ + DT_INST_DMAS_HAS_NAME(n, dir), \ + (SPI_CC35XX_DMA_CHANNEL_INIT(n, dir, ch_dir, src_burst, dst_burst)), (NULL))}, + +#define SPI_CC35XX_DMA_INIT_FUNC(dev) spi_cc35xx_dma_init(dev) +#else +#define SPI_CC35XX_DMA_CHANNEL(n, dir, ch_dir, src_burst, dst_burst) + +#define SPI_CC35XX_DMA_INIT_FUNC +#endif /* CONFIG_SPI_CC35XX_DMA_DRIVEN */ #define SPI_CC35XX_INIT_FUNC(n) \ static int spi_cc35xx_init_##n(const struct device *dev) \ @@ -359,10 +697,6 @@ static int spi_cc35xx_pm_action(const struct device *dev, \ data->ctx.config = NULL; \ err = spi_context_cs_configure_all(&data->ctx); \ - if (err < 0) \ - return err; \ - \ - err = cc35xx_pm_resource_get(spi_cc35xx_power_id(cfg->base)); \ if (err < 0) \ return err; \ \ @@ -371,26 +705,35 @@ static int spi_cc35xx_pm_action(const struct device *dev, SPIDisableInt(cfg->base, SPI_INT_ALL); \ IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), spi_cc35xx_isr, \ DEVICE_DT_INST_GET(n), 0); \ - irq_enable(DT_INST_IRQN(n)); \ + irq_enable(cfg->irq_num); \ + SPI_CC35XX_DMA_INIT_FUNC(dev); \ \ return 0; \ } +#define SPI_CC35XX_DEVICE_INIT(n) \ + DEVICE_DT_INST_DEFINE(n, spi_cc35xx_init_##n, PM_DEVICE_DT_INST_GET(n), \ + &spi_cc35xx_data_##n, &spi_cc35xx_config_##n, POST_KERNEL, \ + CONFIG_SPI_INIT_PRIORITY, &spi_cc35xx_driver_api) + #define SPI_CC35XX_INIT(n) \ PINCTRL_DT_INST_DEFINE(n); \ - SPI_CC35XX_INIT_FUNC(n) \ + SPI_CC35XX_INIT_FUNC(n); \ \ static const struct spi_cc35xx_config spi_cc35xx_config_##n = { \ .base = DT_INST_REG_ADDR(n), \ .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \ .sys_clk_freq = DT_INST_PROP_BY_PHANDLE(n, clocks, clock_frequency), \ + .irq_num = DT_INST_IRQN(n), \ }; \ \ static struct spi_cc35xx_data spi_cc35xx_data_##n = { \ SPI_CONTEXT_INIT_LOCK(spi_cc35xx_data_##n, ctx), \ SPI_CONTEXT_INIT_SYNC(spi_cc35xx_data_##n, ctx), \ - SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(n), ctx)}; \ - \ + SPI_CC35XX_DMA_CHANNEL(n, tx, MEMORY_TO_PERIPHERAL, 8, 1) \ + SPI_CC35XX_DMA_CHANNEL(n, rx, PERIPHERAL_TO_MEMORY, 1, 8) \ + SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(n), ctx) \ + }; \ SPI_CC35XX_DEVICE_INIT(n); DT_INST_FOREACH_STATUS_OKAY(SPI_CC35XX_INIT) diff --git a/dts/bindings/spi/ti,cc35xx-spi.yaml b/dts/bindings/spi/ti,cc35xx-spi.yaml index 6692ed82ebc4..d4c7839ffd78 100644 --- a/dts/bindings/spi/ti,cc35xx-spi.yaml +++ b/dts/bindings/spi/ti,cc35xx-spi.yaml @@ -1,4 +1,4 @@ -# Copyright (c) 2019 Brett Witherspoon +# Copyright (c) 2025-2026 Conclusive Engineering # SPDX-License-Identifier: Apache-2.0 description: TI SimpleLink CC35xx @@ -10,3 +10,31 @@ include: [spi-controller.yaml, pinctrl-device.yaml, base.yaml] properties: reg: required: true + + interrupts: + required: true + + pinctrl-0: + required: true + + pinctrl-names: + required: true + + dmas: + description: | + Optional TX & RX dma specifiers used by async SPI. + The dmas are referenced in the SPI node using the following syntax: + + dmas = <&dma 0 CC35XX_DMA_SET_CONFIG(CC35xx_DMA_PERIPH_SPI_0)>, + <&dma 1 CC35XX_DMA_SET_CONFIG(CC35xx_DMA_PERIPH_SPI_0)>; + where the first entry is for the TX, and the second for RX. + + The parameters in the dma entry are: dma device phandle, dma channel, dma_peripheral + + dma-names: + description: | + Required if the dmas property exists. Should be set to "tx" and "rx" + to match the dmas property. + + For example + dma-names = "tx", "rx"; diff --git a/tests/drivers/spi/spi_controller_peripheral/boards/lp_em_cc35x1.overlay b/tests/drivers/spi/spi_controller_peripheral/boards/lp_em_cc35x1.overlay index cb5a518add53..7609f74c8046 100644 --- a/tests/drivers/spi/spi_controller_peripheral/boards/lp_em_cc35x1.overlay +++ b/tests/drivers/spi/spi_controller_peripheral/boards/lp_em_cc35x1.overlay @@ -7,7 +7,7 @@ dut_spi_dt: test-spi-dev@0 { compatible = "vnd,spi-device"; reg = <0>; - spi-max-frequency = ; + spi-max-frequency = ; }; }; From 8ab7235ec338ae11c3b6b5b2aa101b6acb75ec08 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=81yszczek?= Date: Tue, 16 Dec 2025 15:11:18 +0100 Subject: [PATCH 032/100] UPSTREAM-PEND: drivers/dma/dma_cc35xx: add dma for ti cc35xx chip MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add dma supporting memory to memory operations Co-authored-by: Radoslaw Adamczyk Signed-off-by: Michał Łyszczek Signed-off-by: Radoslaw Adamczyk Signed-off-by: Jakub Jarosinski --- .../lp_em_cc35x1_cc3501e_defconfig | 2 + .../ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi | 5 +- drivers/dma/CMakeLists.txt | 1 + drivers/dma/Kconfig | 2 + drivers/dma/Kconfig.ti_cc35xx | 9 + drivers/dma/dma_ti_cc35xx.c | 323 ++++++++++++++++++ dts/arm/ti/cc35xxe.dtsi | 6 +- dts/bindings/dma/ti,cc35xx-dma.yaml | 27 +- .../zephyr/dt-bindings/dma/ti-cc35xx-dma.h | 34 ++ .../loop_transfer/boards/lp_em_cc35x1.overlay | 9 + 10 files changed, 411 insertions(+), 7 deletions(-) create mode 100644 drivers/dma/Kconfig.ti_cc35xx create mode 100644 drivers/dma/dma_ti_cc35xx.c create mode 100644 include/zephyr/dt-bindings/dma/ti-cc35xx-dma.h create mode 100644 tests/drivers/dma/loop_transfer/boards/lp_em_cc35x1.overlay diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3501e_defconfig b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3501e_defconfig index 6dcdd4e9f903..d99cc8eb4e41 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3501e_defconfig +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3501e_defconfig @@ -31,3 +31,5 @@ CONFIG_FLASH_SHELL=y CONFIG_SPI=y CONFIG_SPI_CC35XX=y CONFIG_SPI_SHELL=y + +CONFIG_DMA=y diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi index 56f8e25cf587..fc9247385526 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi @@ -60,6 +60,7 @@ led2 = &blue_led; sw0 = &user_switch_1; sw1 = &user_switch_2; + dma0 = &dma; }; }; @@ -175,14 +176,10 @@ status = "okay"; pinctrl-0 = <&uart0_default>; pinctrl-names = "default"; - dmas = <&dma 2>, <&dma 3>; - dma-names = "tx", "rx"; }; &uart1 { status = "okay"; pinctrl-0 = <&uart1_default>; pinctrl-names = "default"; - dmas = <&dma 0>, <&dma 1>; - dma-names = "tx", "rx"; }; diff --git a/drivers/dma/CMakeLists.txt b/drivers/dma/CMakeLists.txt index a7db9821062c..a84a1078b0b2 100644 --- a/drivers/dma/CMakeLists.txt +++ b/drivers/dma/CMakeLists.txt @@ -59,6 +59,7 @@ zephyr_library_sources_ifdef(CONFIG_DMA_STM32_BDMA dma_stm32_bdma.c) zephyr_library_sources_ifdef(CONFIG_DMA_STM32_V1 dma_stm32.c dma_stm32_v1.c) zephyr_library_sources_ifdef(CONFIG_DMA_STM32_V2 dma_stm32.c dma_stm32_v2.c) zephyr_library_sources_ifdef(CONFIG_DMA_TI_CC23X0 dma_ti_cc23x0.c) +zephyr_library_sources_ifdef(CONFIG_DMA_TI_CC35XX dma_ti_cc35xx.c) zephyr_library_sources_ifdef(CONFIG_DMA_TI_MSPM0 dma_ti_mspm0.c) zephyr_library_sources_ifdef(CONFIG_DMA_WCH dma_wch.c) zephyr_library_sources_ifdef(CONFIG_DMA_XILINX_AXI_DMA dma_xilinx_axi_dma.c) diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 3dbfb2ae3917..f2f8537168ef 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -72,4 +72,6 @@ source "drivers/dma/Kconfig.xilinx_axi_dma" source "drivers/dma/Kconfig.xmc4xxx" # zephyr-keep-sorted-stop +source "drivers/dma/Kconfig.ti_cc35xx" + endif # DMA diff --git a/drivers/dma/Kconfig.ti_cc35xx b/drivers/dma/Kconfig.ti_cc35xx new file mode 100644 index 000000000000..acef647cdf31 --- /dev/null +++ b/drivers/dma/Kconfig.ti_cc35xx @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Conclusive Engineering Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +config DMA_TI_CC35XX + bool "CC35XX MCU DMA driver" + default y + depends on DT_HAS_TI_CC35XX_DMA_ENABLED + help + Enable DMA support on the CC35XX family of processors. diff --git a/drivers/dma/dma_ti_cc35xx.c b/drivers/dma/dma_ti_cc35xx.c new file mode 100644 index 000000000000..4c198c0d4119 --- /dev/null +++ b/drivers/dma/dma_ti_cc35xx.c @@ -0,0 +1,323 @@ +/* + * Copyright (c) 2025-2026 Conclusive Engineering Sp. z o.o. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT ti_cc35xx_dma + +#include +LOG_MODULE_REGISTER(dma_cc45xx, CONFIG_DMA_LOG_LEVEL); + +#include +#include +#include +#include +#include +#include + +#include + +#include + +#define DMA_INT_ALL SOC_AAON_DMANSICLR_ICLR_M + +struct dma_cc35xx_config { + int src_block_size; +}; + +struct dma_cc35xx_channel { + uint32_t *dst; + uint32_t *src; + uint16_t len; + dma_callback_t cb; + void *user_data; +}; + +struct dma_cc35xx_data { + struct dma_context ctx; + struct dma_cc35xx_channel *channels; + uint32_t channel_control; +}; + +static inline void dma_cc35xx_int_disable(uint32_t mask) +{ + mem_addr_t addr = SOC_AAON_BASE + SOC_AAON_O_DMANSIMASK; + + sys_write32(sys_read32(addr) & ~mask, addr); +} + +static inline void dma_cc35xx_int_enable(uint32_t mask) +{ + mem_addr_t addr = SOC_AAON_BASE + SOC_AAON_O_DMANSIMASK; + + sys_write32(sys_read32(addr) | mask, addr); +} + +static inline uint32_t dma_cc35xx_int_status(void) +{ + return sys_read32(SOC_AAON_BASE + SOC_AAON_O_DMANSMIS); +} + +static inline void dma_cc35xx_int_clear(uint32_t mask) +{ + sys_write32(mask, SOC_AAON_BASE + SOC_AAON_O_DMANSICLR); +} + +static inline uint32_t dma_cc35xx_get_channel_config_reg(uint32_t channel) +{ + return sys_read32(HOST_DMA_TGT_BASE + HOST_DMA_O_CH0JCTL + (channel * DMA_CH_OFFSET)); +} + +static inline uint32_t dma_cc35xx_get_channel_status_reg(uint32_t channel) +{ + return sys_read32(HOST_DMA_TGT_BASE + HOST_DMA_O_CH0TSTA + (channel * DMA_CH_OFFSET)); +} + +static inline uint32_t dma_cc35xx_pending_length(uint32_t channel) +{ + return (dma_cc35xx_get_channel_status_reg(channel) & + HOST_DMA_CH0TSTA_REMAINB_M) >> HOST_DMA_CH0TSTA_REMAINB_S; +} + +static void dma_cc35xx_disable_channel(uint32_t channel) +{ + uint32_t addr; + + addr = HOST_DMA_TGT_BASE + HOST_DMA_O_CH0TCTL2 + (channel * DMA_CH_OFFSET); + sys_write32(DMA_CMD_ABORT, addr); + + /* Wait for ABORT command to finish. + * The command finishes within maximum eight clock cycles. + */ + addr = HOST_DMA_TGT_BASE + HOST_DMA_O_CH0STA + (channel * DMA_CH_OFFSET); + + while ((sys_read32(addr) & HOST_DMA_CH0STA_RUN_M) == HOST_DMA_CH0STA_RUN) { + } +} + +static void dma_cc35xx_init_channel(uint32_t channel) +{ + uint32_t addr; + + addr = HOST_DMA_TGT_BASE + HOST_DMA_O_CH0TCTL2 + (channel * DMA_CH_OFFSET); + sys_write32(DMA_CMD_INIT, addr); +} + + +static int dma_cc35xx_config(const struct device *dev, uint32_t channel, + struct dma_config *config) +{ + struct dma_cc35xx_data *data = dev->data; + struct dma_cc35xx_channel *ch_data; + int num_dma_channels = data->ctx.dma_channels; + uint32_t dma_config, dma_word_size; + uint8_t periph_index; + + if (channel >= num_dma_channels) { + LOG_ERR("Channel %d is out of the range", channel); + return -ERANGE; + } + + if (!config || !config->head_block || config->block_count < 1) { + return -EINVAL; + } + + periph_index = CC35xx_DMA_GET_PERIPH_INDEX(config->dma_slot); + dma_config = DMA_CONFIG_CLEAR_AT_JOB_START; + + if (!periph_index && ((config->channel_direction == MEMORY_TO_PERIPHERAL) + || (config->channel_direction == PERIPHERAL_TO_MEMORY))) { + LOG_ERR("Invalid configuration, peripheral not selected"); + return -EINVAL; + } + + switch (config->channel_direction) { + case MEMORY_TO_MEMORY: + dma_config |= DMA_CONFIG_FORCE_REQ; + break; + case MEMORY_TO_PERIPHERAL: + dma_config |= DMA_CONFIG_DST_PTR_FIFO | DMA_CONFIG_TX; + break; + case PERIPHERAL_TO_MEMORY: + dma_config |= DMA_CONFIG_SRC_PTR_FIFO | DMA_CONFIG_RX; + break; + default: + LOG_ERR("Unsupported channel direction"); + return -EINVAL; + } + + if (config->dest_data_size != 1 && config->dest_data_size != 2 && + config->dest_data_size != 4) { + LOG_ERR("Invalid dest size, Only 1,2,4 bytes supported"); + return -EINVAL; + } + + if (config->source_data_size != 1 && config->source_data_size != 2 && + config->source_data_size != 4) { + LOG_ERR("Invalid source size, Only 1,2,4 bytes supported"); + return -EINVAL; + } + + dma_word_size = DMA_WORD_SIZE_1B - __builtin_ctz((config->source_data_size)); + + ch_data = &data->channels[channel]; + + ch_data->src = (uint32_t *)config->head_block->source_address; + ch_data->dst = (uint32_t *)config->head_block->dest_address; + ch_data->len = config->head_block->block_size; + ch_data->cb = config->dma_callback; + ch_data->user_data = config->user_data; + data->channel_control |= BIT(channel); + + if (periph_index) { + DMAInitChannel(channel, periph_index - 1); + } + DMAConfigureChannel(channel, config->source_burst_length, dma_word_size, dma_config); + + return 0; +} + +static int dma_cc35xx_start(const struct device *dev, uint32_t channel) +{ + struct dma_cc35xx_data *data = dev->data; + struct dma_cc35xx_channel *ch_data; + int num_dma_channels = data->ctx.dma_channels; + + if (channel >= num_dma_channels) { + return -EINVAL; + } + + dma_cc35xx_init_channel(channel); + ch_data = &data->channels[channel]; + DMAStartTransaction(channel, ch_data->src, ch_data->dst, ch_data->len, true); + + dma_cc35xx_int_enable(BIT(channel)); + + return 0; +} + +static int dma_cc35xx_stop(const struct device *dev, uint32_t channel) +{ + struct dma_cc35xx_data *data = dev->data; + int num_dma_channels = data->ctx.dma_channels; + + if (channel >= num_dma_channels) { + return -EINVAL; + } + + dma_cc35xx_int_disable(BIT(channel)); + dma_cc35xx_int_clear(BIT(channel)); + + dma_cc35xx_disable_channel(channel); + + return 0; +} + +static int dma_cc35xx_reload(const struct device *dev, uint32_t channel, + uint32_t src, uint32_t dst, size_t size) +{ + struct dma_cc35xx_data *data = dev->data; + int num_dma_channels = data->ctx.dma_channels; + + if (channel >= num_dma_channels) { + return -EINVAL; + } + + dma_cc35xx_init_channel(channel); + + DMAStartTransaction(channel, (uint32_t *)src, (uint32_t *)dst, size, true); + dma_cc35xx_int_enable(BIT(channel)); + + return 0; +} + +static int dma_cc35xx_get_status(const struct device *dev, uint32_t channel, + struct dma_status *stat) +{ + struct dma_cc35xx_data *data = dev->data; + int num_dma_channels = data->ctx.dma_channels; + uint32_t channel_config; + + if ((channel >= num_dma_channels) || !stat) { + return -EINVAL; + } + + channel_config = dma_cc35xx_get_channel_config_reg(channel); + + if (channel_config & DMA_CONFIG_FORCE_REQ) { + stat->dir = MEMORY_TO_MEMORY; + } else if (DMAGetChannelDirection(channel) == DMA_CONFIG_TX) { + stat->dir = MEMORY_TO_PERIPHERAL; + } else { + stat->dir = PERIPHERAL_TO_MEMORY; + } + + stat->busy = (DMAGetChannelStatus(channel) == 0); + stat->pending_length = dma_cc35xx_pending_length(channel); + + return 0; +} + +static void dma_cc35xx_isr(const struct device *dev) +{ + struct dma_cc35xx_data *data = dev->data; + struct dma_cc35xx_channel *ch_data; + int num_dma_channels = data->ctx.dma_channels; + uint32_t i, done_status = dma_cc35xx_int_status(); + + for (i = 0; i < num_dma_channels; i++) { + if (done_status & BIT(i)) { + ch_data = &data->channels[i]; + if (ch_data->cb) { + ch_data->cb(dev, ch_data->user_data, i, DMA_STATUS_COMPLETE); + } + + dma_cc35xx_int_clear(done_status & BIT(i)); + } + } +} + +static int dma_cc35xx_init(const struct device *dev) +{ + struct dma_cc35xx_data *data = dev->data; + + data->channel_control = 0; + + IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), + dma_cc35xx_isr, DEVICE_DT_INST_GET(0), 0); + irq_enable(DT_INST_IRQN(0)); + + dma_cc35xx_int_disable(DMA_INT_ALL); + dma_cc35xx_int_clear(DMA_INT_ALL); + return 0; +} + +static const struct dma_driver_api dma_cc35xx_driver_api = { + .config = dma_cc35xx_config, + .reload = dma_cc35xx_reload, + .get_status = dma_cc35xx_get_status, + .start = dma_cc35xx_start, + .stop = dma_cc35xx_stop, +}; + +#define CC35XX_DMA_INIT(inst) \ + \ + static struct dma_cc35xx_channel \ + dma_cc35xx##inst##_channels[DT_INST_PROP(inst, dma_channels)]; \ + ATOMIC_DEFINE(dma_cc35xx_atomic##inst, \ + DT_INST_PROP(inst, dma_channels)); \ + static struct dma_cc35xx_data dma_cc35xx##inst##_data = { \ + .ctx = { \ + .magic = DMA_MAGIC, \ + .atomic = dma_cc35xx_atomic##inst, \ + .dma_channels = DT_INST_PROP(inst, dma_channels), \ + }, \ + .channels = dma_cc35xx##inst##_channels, \ + }; \ + DEVICE_DT_INST_DEFINE(inst, &dma_cc35xx_init, NULL, \ + &dma_cc35xx##inst##_data, \ + &dma_cc35xx_config, PRE_KERNEL_1, \ + CONFIG_DMA_INIT_PRIORITY, &dma_cc35xx_driver_api); + +DT_INST_FOREACH_STATUS_OKAY(CC35XX_DMA_INIT) diff --git a/dts/arm/ti/cc35xxe.dtsi b/dts/arm/ti/cc35xxe.dtsi index d72aaf5c2d67..0544f4d51253 100644 --- a/dts/arm/ti/cc35xxe.dtsi +++ b/dts/arm/ti/cc35xxe.dtsi @@ -12,6 +12,7 @@ #define INT_SP_UART_1_INT_REQ 17 #define INT_SP_SPI_0_EVT_REQ 20 #define INT_SP_SPI_1_EVT_REQ 21 +#define INT_NON_SECURED_DMA_IRQ_EVT_IND_OUT 41 /* * Note: Zephyr uses exception numbers, vs the IRQ used by the CC32XX SDK * which are offset by 16: @@ -20,6 +21,7 @@ #define EXP_UARTA1 (INT_SP_UART_1_INT_REQ - 16) #define EXP_SPI0 (INT_SP_SPI_0_EVT_REQ - 16) #define EXP_SPI1 (INT_SP_SPI_1_EVT_REQ - 16) +#define EXP_DMA_NS (INT_NON_SECURED_DMA_IRQ_EVT_IND_OUT - 16) / { cpus { @@ -175,7 +177,9 @@ dma: dma@41a00000 { compatible = "ti,cc35xx-dma"; reg = <0x41a00000 0x10000>; - #dma-cells = <1>; + interrupts = ; + dma-channels = <14>; + #dma-cells = <2>; status = "disabled"; }; diff --git a/dts/bindings/dma/ti,cc35xx-dma.yaml b/dts/bindings/dma/ti,cc35xx-dma.yaml index 74631fa7d108..0cf64fc0dbc2 100644 --- a/dts/bindings/dma/ti,cc35xx-dma.yaml +++ b/dts/bindings/dma/ti,cc35xx-dma.yaml @@ -1,17 +1,40 @@ -# Copyright (c) 2025 Conclusive Engineering Sp. z o.o. +# Copyright (c) 2025-2026 Conclusive Engineering Sp. z o.o. # # SPDX-License-Identifier: Apache-2.0 +# description: | TI Simplelink DMA controller for the cc35xx chip family. + + The TI CC35xx SoC has a general-purpose direct memory access controller + capable of supporting 12independent DMA channels. DMA clients connected + to the DMA controller must use three-cell specifier for each channel: + a phandle to the DMA controller plus the following two integer cells: + 1. channel: the DMA stream from 0 to 11 (max 12 channels). + Note that channel 11 is reserved for the BT/WIFI subsystem, and cannot + be used directly in the DTS + 2. channel-config: A 32bit mask specifying the DMA channel configuration + which is device and peripheral dependent: + -bit 0-3 Peripheral index + + Example of devicetree configuration + + Client side: + uart0 { + dmas = <&dma1 3 CC35XX_DMA_SET_CONFIG(CC35xx_DMA_PERIPH_UARTLIN_0)>, + <&dma1 2 CC35XX_DMA_SET_CONFIG(CC35xx_DMA_PERIPH_UARTLIN_0)> + dma-names = "tx", "rx"; + } + compatible: "ti,cc35xx-dma" include: dma-controller.yaml properties: "#dma-cells": - const: 1 + const: 2 dma-cells: - channel + - channel-config diff --git a/include/zephyr/dt-bindings/dma/ti-cc35xx-dma.h b/include/zephyr/dt-bindings/dma/ti-cc35xx-dma.h new file mode 100644 index 000000000000..579f9c6c14d4 --- /dev/null +++ b/include/zephyr/dt-bindings/dma/ti-cc35xx-dma.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2025-2026 Conclusive Engineering Sp. z o.o. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_TI_CC35XX_DMA_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_TI_CC35XX_DMA_H_ + + +/** DMA Peripheral index on bit 0-3*/ +#define CC35xx_DMA_PERIPH_INDEX(val) ((val & 0xf)) +#define CC35xx_DMA_GET_PERIPH_INDEX(cfg) ((cfg) & 0xf) + +/** DMA Available peripheral indexes: */ +#define CC35xx_DMA_PERIPH_NONE CC35xx_DMA_PERIPH_INDEX(0) /*!< NONE */ +#define CC35xx_DMA_PERIPH_UARTLIN_0 CC35xx_DMA_PERIPH_INDEX(1) /*!< UARTLIN0 */ +#define CC35xx_DMA_PERIPH_UARTLIN_1 CC35xx_DMA_PERIPH_INDEX(2) /*!< UARTLIN1 */ +#define CC35xx_DMA_PERIPH_SPI_0 CC35xx_DMA_PERIPH_INDEX(3) /*!< SPI0 */ +#define CC35xx_DMA_PERIPH_SPI_1 CC35xx_DMA_PERIPH_INDEX(4) /*!< SPI1 */ +#define CC35xx_DMA_PERIPH_I2C_0 CC35xx_DMA_PERIPH_INDEX(5) /*!< I2C0 */ +#define CC35xx_DMA_PERIPH_I2C_1 CC35xx_DMA_PERIPH_INDEX(6) /*!< I2C1 */ +#define CC35xx_DMA_PERIPH_SDMMC CC35xx_DMA_PERIPH_INDEX(7) /*!< SDMMC */ +#define CC35xx_DMA_PERIPH_SDIO CC35xx_DMA_PERIPH_INDEX(8) /*!< SDIO */ +#define CC35xx_DMA_PERIPH_MCAN CC35xx_DMA_PERIPH_INDEX(9) /*!< MCAN */ +#define CC35xx_DMA_PERIPH_ADC CC35xx_DMA_PERIPH_INDEX(10) /*!< ADC */ +#define CC35xx_DMA_PERIPH_PDM CC35xx_DMA_PERIPH_INDEX(11) /*!< PDM */ +#define CC35xx_DMA_PERIPH_HIF CC35xx_DMA_PERIPH_INDEX(12) /*!< HIF */ +#define CC35xx_DMA_PERIPH_UARTLIN_2 CC35xx_DMA_PERIPH_INDEX(13) /*!< UARTLIN2 */ + + +#define CC35XX_DMA_SET_CONFIG(peripheral) (peripheral) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DMA_TI_CC35XX_DMA_H_ */ diff --git a/tests/drivers/dma/loop_transfer/boards/lp_em_cc35x1.overlay b/tests/drivers/dma/loop_transfer/boards/lp_em_cc35x1.overlay new file mode 100644 index 000000000000..fc45ecd7188a --- /dev/null +++ b/tests/drivers/dma/loop_transfer/boards/lp_em_cc35x1.overlay @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025-2026 Conclusive Engineering Sp. z o.o. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +tst_dma0: &dma { + status = "okay"; +}; From 39a2d5b9cea90083c76e8decc7bf856ad363462f Mon Sep 17 00:00:00 2001 From: Jakub Jarosinski Date: Mon, 6 Jul 2026 11:10:30 +0200 Subject: [PATCH 033/100] UPSTREAM-PEND: drivers: spi: cc35xx: validate config before disable Validate the SPI config before touching controller state so invalid transfers fail before disable handling runs. Signed-off-by: Jakub Jarosinski --- drivers/spi/spi_cc35xx.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/spi/spi_cc35xx.c b/drivers/spi/spi_cc35xx.c index 91d31a529e27..b38e0e3d7714 100644 --- a/drivers/spi/spi_cc35xx.c +++ b/drivers/spi/spi_cc35xx.c @@ -157,10 +157,6 @@ static int spi_cc35xx_configure(const struct device *dev, const struct spi_confi return 0; } - SPIDisable(cfg->base); - SPIDisableInt(cfg->base, SPI_INT_ALL); - SPIClearInt(cfg->base, SPI_INT_ALL); - if (config->operation & SPI_HALF_DUPLEX) { LOG_ERR("Half-duplex not supported"); return -ENOTSUP; @@ -171,6 +167,10 @@ static int spi_cc35xx_configure(const struct device *dev, const struct spi_confi return -ENOTSUP; } + SPIDisable(cfg->base); + SPIDisableInt(cfg->base, SPI_INT_ALL); + SPIClearInt(cfg->base, SPI_INT_ALL); + ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); if (ret < 0) { LOG_ERR("Applying SPI pinctrl state failed"); @@ -346,11 +346,15 @@ static int spi_cc35xx_transceive(const struct device *dev, #else data->rxleft = spi_context_total_rx_len(ctx); - if (IS_ENABLED(CONFIG_SPI_SLAVE) && spi_context_is_slave(ctx)) { +#ifdef CONFIG_SPI_SLAVE + if (spi_context_is_slave(ctx)) { spi_cc35xx_slave_transceive(dev); } else { spi_cc35xx_master_transceive(dev); } +#else + spi_cc35xx_master_transceive(dev); +#endif /* CONFIG_SPI_SLAVE */ #endif /* CONFIG_SPI_CC35XX_DMA_DRIVEN */ ret = spi_context_wait_for_completion(ctx); @@ -685,7 +689,7 @@ static int spi_cc35xx_dma_init(const struct device *dev) #else #define SPI_CC35XX_DMA_CHANNEL(n, dir, ch_dir, src_burst, dst_burst) -#define SPI_CC35XX_DMA_INIT_FUNC +#define SPI_CC35XX_DMA_INIT_FUNC(dev) do { } while (0) #endif /* CONFIG_SPI_CC35XX_DMA_DRIVEN */ #define SPI_CC35XX_INIT_FUNC(n) \ From e127ec0e5e37c42b6fea788697b08ae6c3c0f2a9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=81yszczek?= Date: Fri, 5 Sep 2025 18:24:25 +0200 Subject: [PATCH 034/100] UPSTREAM-PEND: drivers: i2c: cc35xxe: add i2c support for master operations MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add i2c for cc35xxe chip for master operations Signed-off-by: Michał Łyszczek Signed-off-by: Radoslaw Adamczyk --- .../ti/lp_em_cc35x1/lp_em_cc35x1-pinctrl.dtsi | 28 ++ .../lp_em_cc35x1_cc3501e_defconfig | 5 + .../ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi | 19 + drivers/i2c/CMakeLists.txt | 1 + drivers/i2c/Kconfig | 8 + drivers/i2c/i2c_cc35xx.c | 351 ++++++++++++++++++ drivers/pinctrl/pinctrl_ti_cc35xx.c | 29 +- dts/arm/ti/cc35xxe.dtsi | 63 +++- dts/bindings/i2c/ti,cc35xx-i2c.yaml | 18 + .../dt-bindings/pinctrl/ti-cc35xx-pinctrl.h | 75 ++-- 10 files changed, 544 insertions(+), 53 deletions(-) create mode 100644 drivers/i2c/i2c_cc35xx.c create mode 100644 dts/bindings/i2c/ti,cc35xx-i2c.yaml diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1-pinctrl.dtsi b/boards/ti/lp_em_cc35x1/lp_em_cc35x1-pinctrl.dtsi index c0911857e504..154875a372ca 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1-pinctrl.dtsi +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1-pinctrl.dtsi @@ -51,4 +51,32 @@ <(TI_CC35XX_PINCTRL_DIR_OUT | P12_SPI1_CS1)>; }; }; + + adc0_default: adc0_default { + group1 { + pinmux = , ; + }; + }; + + pwm3_default: lgpt1_chan0_default { + group1 { + pinmux = ; + }; + }; + pwm4_default: lgpt1_chan1_default { + group1 { + pinmux = ; + }; + }; + pwm5_default: lgpt1_chan2_default { + group1 { + pinmux = ; + }; + }; + + i2c1_default: i2c1_default { + group1 { + pinmux = , ; + }; + }; }; diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3501e_defconfig b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3501e_defconfig index d99cc8eb4e41..4fd9874f94c2 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3501e_defconfig +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3501e_defconfig @@ -20,6 +20,7 @@ CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SHELL=y +CONFIG_SHELL_STACK_SIZE=4096 CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN=y CONFIG_SHELL_BACKEND_SERIAL_API_INTERRUPT_DRIVEN=y @@ -33,3 +34,7 @@ CONFIG_SPI_CC35XX=y CONFIG_SPI_SHELL=y CONFIG_DMA=y + +CONFIG_I2C=y +CONFIG_I2C_CC35XX=y +CONFIG_I2C_SHELL=y diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi index fc9247385526..75cd41ff6308 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi @@ -172,6 +172,25 @@ }; }; +&i2c1 { + status = "okay"; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; + + tmp1075_temperature: tmp1075@48 { + compatible = "lm75"; + friendly-name = "texas_temperature_tmp1075"; + reg = <0x48>; + status = "okay"; + }; + + bma4xx_accelerometer: bma4xx@18 { + compatible = "bosch,bma4xx"; + reg = <0x18>; + status = "okay"; + }; +}; + &uart0 { status = "okay"; pinctrl-0 = <&uart0_default>; diff --git a/drivers/i2c/CMakeLists.txt b/drivers/i2c/CMakeLists.txt index 4ee7c159fcd5..1c413f618d33 100644 --- a/drivers/i2c/CMakeLists.txt +++ b/drivers/i2c/CMakeLists.txt @@ -9,6 +9,7 @@ zephyr_library_sources(i2c_common.c) # zephyr-keep-sorted-start zephyr_library_sources_ifdef(CONFIG_GPIO_I2C_SWITCH gpio_i2c_switch.c) zephyr_library_sources_ifdef(CONFIG_I2C_BITBANG i2c_bitbang.c) +zephyr_library_sources_ifdef(CONFIG_I2C_CC35XX i2c_cc35xx.c) zephyr_library_sources_ifdef(CONFIG_I2C_EMUL i2c_emul.c) zephyr_library_sources_ifdef(CONFIG_I2C_GPIO i2c_gpio.c) zephyr_library_sources_ifdef(CONFIG_I2C_RTIO i2c_rtio.c i2c_rtio_default.c) diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 756b5485cf1f..6500b2c9c437 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -275,6 +275,14 @@ config I2C_CC32XX help Enable the CC32XX I2C driver. +config I2C_CC35XX + bool "CC35XX I2C driver" + default y + depends on DT_HAS_TI_CC35XX_I2C_ENABLED + select PINCTRL + help + Enable the CC35XX I2C driver. + config I2C_BITBANG bool help diff --git a/drivers/i2c/i2c_cc35xx.c b/drivers/i2c/i2c_cc35xx.c new file mode 100644 index 000000000000..03882ba51c5a --- /dev/null +++ b/drivers/i2c/i2c_cc35xx.c @@ -0,0 +1,351 @@ +/* + * Copyright (c) 2025 Conclusive Engineering Sp. z o.o. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT ti_cc35xx_i2c + +#include +#include +#include +#include +#include + +#include +#include + +#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL +#include +#include +LOG_MODULE_REGISTER(i2c_cc35xx); + +struct i2c_cc35xx_config { + uint32_t base; + uint32_t sys_clk_freq; + void (*irq_config_func)(void); + const struct pinctrl_dev_config *pcfg; +}; + +struct i2c_cc35xx_data { + struct k_mutex mutex; + struct k_sem i2c_msg_done; + uint8_t *buf; + int buflen; + int bufpos; + int bus_error; + int flags; +}; + +static int i2c_cc35xx_configure(const struct device *dev, uint32_t dev_config_raw) +{ + const struct i2c_cc35xx_config *config = dev->config; + struct i2c_cc35xx_data *data = dev->data; + uint32_t mode; + + switch (I2C_SPEED_GET(dev_config_raw)) { + case I2C_SPEED_STANDARD: + mode = I2C_MODE_STANDARD; + break; + case I2C_SPEED_FAST: + mode = I2C_MODE_FAST; + break; + case I2C_SPEED_FAST_PLUS: + mode = I2C_MODE_FAST_PLUS; + break; + default: + return -EIO; + } + + k_mutex_lock(&data->mutex, K_FOREVER); + I2CControllerDisable(config->base); + I2CControllerInit(config->base, I2C_CONTROLLER_CONFIG_CLOCK_STRETCHING_DETECTION, mode); + k_mutex_unlock(&data->mutex); + + return 0; +} + +/** + * Transmit data from internal #dev buffer. Function will put as much + * data as it can onto i2c fifo buffer and will return once buffer is + * full or there is no more data to transfer. Function will modify, + * buffer state in #dev, so function can be called multiple times until + * all data are transferred out. + * + * @return 1 when all data within #dev internal state machine is sent out + * @return 0 when there is still data in #dev buffers to be sent out. You can + * call this again to transmit what is left. + */ +static int i2c_cc35xx_fifo_put(const struct device *dev) +{ + const struct i2c_cc35xx_config *config = dev->config; + struct i2c_cc35xx_data *data = dev->data; + + for (; data->bufpos < data->buflen; data->bufpos++) { + if (I2CPutDataNonBlocking(config->base, data->buf[data->bufpos]) == 0) { + break; + } + } + + return data->bufpos == data->buflen; +} + +/** + * Same principle as with i2c_cc35xx_fifo_put but is used to read data from + * i2c receive buffer + */ +static int i2c_cc35xx_fifo_get(const struct device *dev) +{ + const struct i2c_cc35xx_config *config = dev->config; + struct i2c_cc35xx_data *data = dev->data; + + for (; data->bufpos < data->buflen; data->bufpos++) { + if (I2CGetDataNonBlocking(config->base, &data->buf[data->bufpos]) == 0) { + break; + } + } + + return data->bufpos == data->buflen; +} + +/** + * Start single i2c transfer. Function will prepare buffer to receive/send + * data, enable interrupts, and will wait until i2c transfer completes. Once + * transfer is started and function waits for semaphore, all logic happens + * via interrupts at that point. + * + * @return 0 transfer was completed without error + * @return -EIO error during transfer like not getting ACK from peripheral. + * @return -ETIMEDOUT is returned when we don't get interrupt from i2c after + * transfer is started + */ +static int i2c_cc35xx_prime_transfer(const struct device *dev, uint8_t *buf, uint32_t len, + uint16_t addr, int flags) +{ + struct i2c_cc35xx_data *data = dev->data; + const struct i2c_cc35xx_config *config = dev->config; + bool is_read = flags & I2C_MSG_READ; + bool is_start = flags & I2C_MSG_RESTART; + uint32_t cmd = 0; + uint32_t direction = is_read ? I2C_CONTROLLER_DIR_RECEIVE : I2C_CONTROLLER_DIR_TRANSMIT; + uint32_t addr_mode = flags & I2C_MSG_ADDR_10_BITS ? + I2C_CONTROLLER_ADDR_MODE_10_BIT : I2C_CONTROLLER_ADDR_MODE_7_BIT; + uint32_t enable_interrupt = I2C_CONTROLLER_INT_ARB_LOST | + I2C_CONTROLLER_INT_STOP | I2C_CONTROLLER_INT_NACK; + + data->buf = buf; + data->buflen = len; + data->bufpos = 0; + data->bus_error = 0; + data->flags = flags; + + if (is_read) { + cmd = is_start ? I2C_CONTROLLER_CMD_BURST_RECEIVE_START : + I2C_CONTROLLER_CMD_BURST_RECEIVE_CONT; + } else { + cmd = is_start ? I2C_CONTROLLER_CMD_BURST_SEND_START : + I2C_CONTROLLER_CMD_BURST_SEND_CONT; + } + if (is_start && len == 0) { + cmd = I2C_CONTROLLER_CMD_SINGLE_SEND; + } + + if (is_read) { + enable_interrupt |= I2C_CONTROLLER_INT_RX_FIFO_TRIGGER | + I2C_CONTROLLER_INT_RX_DONE; + } else { + i2c_cc35xx_fifo_put(dev); + enable_interrupt |= I2C_CONTROLLER_INT_TX_FIFO_TRIGGER | + I2C_CONTROLLER_INT_TX_DONE; + } + + I2CEnableInt(config->base, enable_interrupt); + I2CControllerSetTargetAddr(config->base, addr_mode, addr, direction); + I2CControllerSetCommand(config->base, cmd, data->buflen); + if (k_sem_take(&data->i2c_msg_done, K_MSEC(100))) { + return -ETIMEDOUT; + } + + return data->bus_error ? -EIO : 0; +} + +static int i2c_cc35xx_transfer(const struct device *dev, struct i2c_msg *msgs, + uint8_t num_msgs, uint16_t addr) +{ + struct i2c_cc35xx_data *data = dev->data; + const struct i2c_cc35xx_config *config = dev->config; + struct i2c_msg *msg; + int ret = 0, retries, flags; + uint16_t timeout = UINT16_MAX; + + k_mutex_lock(&data->mutex, K_FOREVER); + k_sem_reset(&data->i2c_msg_done); + + + while (I2CControllerIsBusy(config->base) && --timeout) { + k_busy_wait(USEC_PER_MSEC); + } + + if (!timeout) { + k_mutex_unlock(&data->mutex); + + return -EBUSY; + } + + I2CFlushFifos(config->base); + I2CClearInt(config->base, I2C_INT_ALL); + + for (int i = 0; i < num_msgs; i++) { + msg = msgs + i; + if (msg->len > I2C_CONTROLLER_TRANSACTION_LENGTH_MAX) { + LOG_ERR("Single transaction cannot be larger than %d\n", + I2C_CONTROLLER_TRANSACTION_LENGTH_MAX); + return -EINVAL; + } + + flags = msg->flags; + if (i == 0) { + flags |= I2C_MSG_RESTART; + } + if (i == (num_msgs - 1)) { + flags |= I2C_MSG_STOP; + } + + for (retries = 3; retries; retries--) { + ret = i2c_cc35xx_prime_transfer(dev, msg->buf, msg->len, addr, flags); + if (ret != -ETIMEDOUT) { + break; + } + } + + if (ret != 0) { + goto error; + } + } + +error: + k_mutex_unlock(&data->mutex); + + return ret; +} + +static void i2c_cc35xx_isr(const struct device *dev) +{ + struct i2c_cc35xx_data *data = dev->data; + const struct i2c_cc35xx_config *config = dev->config; + uint32_t int_status; + uint32_t tx_fifo_int = I2C_CONTROLLER_INT_TX_FIFO_TRIGGER; + uint32_t rx_fifo_int = I2C_CONTROLLER_INT_RX_FIFO_TRIGGER; + uint32_t finish_int = I2C_CONTROLLER_INT_STOP | I2C_CONTROLLER_INT_TX_DONE | + I2C_CONTROLLER_INT_RX_DONE; + uint32_t i2c_error = I2CControllerGetError(config->base); + + if (i2c_error) { + if (!(i2c_error & I2C_CONTROLLER_ERR_ARB_LOST)) { + I2CControllerSetCommand(config->base, + I2C_CONTROLLER_CMD_BURST_FINISH, + I2C_CONTROLLER_TRANSACTION_LENGTH_NONE); + } + data->bus_error = 1; + I2CDisableInt(config->base, I2C_INT_ALL); + I2CClearInt(config->base, I2C_INT_ALL); + + k_sem_give(&data->i2c_msg_done); + + return; + } + + while ((int_status = I2CIntStatus(config->base, true))) { + if (int_status & tx_fifo_int) { + if (i2c_cc35xx_fifo_put(dev)) { + I2CDisableInt(config->base, I2C_CONTROLLER_INT_TX_FIFO_TRIGGER); + } + + I2CClearInt(config->base, tx_fifo_int); + } else if (int_status & rx_fifo_int) { + if (i2c_cc35xx_fifo_get(dev)) { + I2CDisableInt(config->base, I2C_CONTROLLER_INT_RX_FIFO_TRIGGER); + } + + I2CClearInt(config->base, rx_fifo_int); + } else if (int_status & finish_int) { + if (int_status & I2C_CONTROLLER_INT_RX_DONE) { + i2c_cc35xx_fifo_get(dev); + } + + data->bus_error = 0; + I2CDisableInt(config->base, I2C_INT_ALL); + I2CClearInt(config->base, I2C_INT_ALL); + if (data->flags & I2C_MSG_STOP) { + I2CControllerSetCommand(config->base, + I2C_CONTROLLER_CMD_BURST_FINISH, + I2C_CONTROLLER_TRANSACTION_LENGTH_NONE); + } + + k_sem_give(&data->i2c_msg_done); + } else { + __ASSERT(false, "Unhandled I2C Interrupt"); + data->bus_error = 1; + I2CControllerSetCommand(config->base, I2C_CONTROLLER_CMD_BURST_FINISH, + I2C_CONTROLLER_TRANSACTION_LENGTH_NONE); + I2CDisableInt(config->base, I2C_INT_ALL); + I2CClearInt(config->base, I2C_INT_ALL); + + k_sem_give(&data->i2c_msg_done); + } + } +} + +static int i2c_cc35xx_init(const struct device *dev) +{ + const struct i2c_cc35xx_config *config = dev->config; + struct i2c_cc35xx_data *data = dev->data; + int error; + + error = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); + if (error < 0) { + return error; + } + + k_mutex_init(&data->mutex); + k_sem_init(&data->i2c_msg_done, 0, 1); + + sys_write32(I2C_CLKCFG_ENABLE_EN, config->base + I2C_O_CLKCFG); + I2CControllerDisable(config->base); + I2CDisableInt(config->base, I2C_INT_ALL); + config->irq_config_func(); + I2CFlushFifos(config->base); + I2CSetTxFifoTrigger(config->base, I2C_TX_FIFO_SIZE / 2); + I2CSetRxFifoTrigger(config->base, I2C_RX_FIFO_SIZE / 2); + I2CControllerInit(config->base, I2C_CONTROLLER_CONFIG_CLOCK_STRETCHING_DETECTION, + I2C_MODE_STANDARD); + I2CClearInt(config->base, I2C_INT_ALL); + + return 0; +} + +static const struct i2c_driver_api i2c_cc35xx_driver_api = { + .configure = i2c_cc35xx_configure, + .transfer = i2c_cc35xx_transfer, +}; + +#define I2C_CC35XX_DEVICE(n) \ + PINCTRL_DT_INST_DEFINE(n); \ + static void i2c_cc35xx_irq_config_##n(void) \ + { \ + IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), i2c_cc35xx_isr, \ + DEVICE_DT_INST_GET(n), 0); \ + irq_enable(DT_INST_IRQN(n)); \ + } \ + static struct i2c_cc35xx_data i2c_cc35xx_data_##n; \ + static const struct i2c_cc35xx_config i2c_cc35xx_config_##n = { \ + .base = DT_INST_REG_ADDR(n), \ + .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \ + .irq_config_func = i2c_cc35xx_irq_config_##n, \ + .sys_clk_freq = DT_INST_PROP_BY_PHANDLE(n, clocks, clock_frequency), \ + }; \ + I2C_DEVICE_DT_INST_DEFINE(n, i2c_cc35xx_init, NULL, &i2c_cc35xx_data_##n, \ + &i2c_cc35xx_config_##n, POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \ + &i2c_cc35xx_driver_api) + +DT_INST_FOREACH_STATUS_OKAY(I2C_CC35XX_DEVICE); diff --git a/drivers/pinctrl/pinctrl_ti_cc35xx.c b/drivers/pinctrl/pinctrl_ti_cc35xx.c index 85fd330ce3f6..c2345d5392c4 100644 --- a/drivers/pinctrl/pinctrl_ti_cc35xx.c +++ b/drivers/pinctrl/pinctrl_ti_cc35xx.c @@ -14,33 +14,38 @@ #define MEM_GPIO_PAD_CONFIG_MSK 0xFFFU #define MEM_GPIO0_PCFG_OFFSET 0x0002D004 -#define MEM_GPIO0_CFG_OFFSET 0 -#define MEM_GPIO0_PCTL_OFFSET 4 -#define MEM_GPIO_NEXT_OFFSET 0x1000 -#define MEM_GPIO_IE_BIT 11 -#define MEM_GPIO_OUTDIS_BIT 12 +#define MEM_GPIO0_CFG_OFFSET 0 +#define MEM_GPIO0_PCTL_OFFSET 4 +#define MEM_GPIO_NEXT_OFFSET 0x1000 +#define MEM_GPIO_ANASWOVREN_BIT 9 +#define MEM_GPIO_ANASW_BIT 10 +#define MEM_GPIO_IE_BIT 11 +#define MEM_GPIO_OUTDIS_BIT 12 +#define MEM_GPIO_ODISOVEN_BIT 13 static void pinctrl_configure_pin(pinctrl_soc_pin_t pincfg) { uint8_t pin; mem_addr_t reg; uint32_t tmp; - int dir; pin = (pincfg >> TI_CC35XX_PIN_POS) & TI_CC35XX_PIN_MSK; - dir = TI_CC35XX_PINCTRL_DIR(pincfg); /* set pin function */ reg = DT_INST_REG_ADDR(0) + MEM_GPIO0_PCFG_OFFSET + pin * sizeof(uint32_t); sys_write32(pincfg & TI_CC35XX_MUX_MSK, reg); - /* enable/disable receiver operation on pin */ + /* disable both input and output function of pin */ reg = DT_INST_REG_ADDR(0) + pin * MEM_GPIO_NEXT_OFFSET + MEM_GPIO0_CFG_OFFSET; tmp = sys_read32(reg); - if (dir == TI_CC35XX_PINCTRL_DIR_IN) { - tmp |= BIT(MEM_GPIO_IE_BIT) | BIT(MEM_GPIO_OUTDIS_BIT); - } else { - tmp &= ~(BIT(MEM_GPIO_IE_BIT) | BIT(MEM_GPIO_OUTDIS_BIT)); + tmp &= ~BIT(MEM_GPIO_IE_BIT); + tmp |= BIT(MEM_GPIO_OUTDIS_BIT); + tmp &= ~BIT(MEM_GPIO_ODISOVEN_BIT); + if (pincfg & TI_CC35XX_PINCTRL_DIR_IN) { + tmp |= BIT(MEM_GPIO_IE_BIT); + } + if (pincfg & TI_CC35XX_PINCTRL_DIR_OUT) { + tmp &= ~BIT(MEM_GPIO_OUTDIS_BIT); } sys_write32(tmp, reg); diff --git a/dts/arm/ti/cc35xxe.dtsi b/dts/arm/ti/cc35xxe.dtsi index 0544f4d51253..e87c160a3947 100644 --- a/dts/arm/ti/cc35xxe.dtsi +++ b/dts/arm/ti/cc35xxe.dtsi @@ -8,20 +8,36 @@ #include #include -#define INT_SP_UART_0_INT_REQ 16 -#define INT_SP_UART_1_INT_REQ 17 -#define INT_SP_SPI_0_EVT_REQ 20 -#define INT_SP_SPI_1_EVT_REQ 21 +#define INT_SP_UART_0_INT_REQ 16 +#define INT_SP_UART_1_INT_REQ 17 +#define INT_SP_I2C_0_INTREQ 18 +#define INT_SP_I2C_1_INTREQ 19 +#define INT_SP_SPI_0_EVT_REQ 20 +#define INT_SP_SPI_1_EVT_REQ 21 +#define INT_GPTIMER_0_EVT_CPU_IRQ 22 +#define INT_GPTIMER_1_EVT_CPU_IRQ 23 +#define INT_ULL_USC_ULPADCHP_PUB_EVT0_REQ 31 +#define INT_OSPR_HSM_HOST_0_SEC_IRQ 34 #define INT_NON_SECURED_DMA_IRQ_EVT_IND_OUT 41 +#define INT_HOST_ELP_TMR_WAKEUP_REQ 62 +#define INT_NAB_HOST_IRQ 63 /* * Note: Zephyr uses exception numbers, vs the IRQ used by the CC32XX SDK * which are offset by 16: */ -#define EXP_UARTA0 (INT_SP_UART_0_INT_REQ - 16) -#define EXP_UARTA1 (INT_SP_UART_1_INT_REQ - 16) -#define EXP_SPI0 (INT_SP_SPI_0_EVT_REQ - 16) -#define EXP_SPI1 (INT_SP_SPI_1_EVT_REQ - 16) +#define EXP_UARTA0 (INT_SP_UART_0_INT_REQ - 16) +#define EXP_UARTA1 (INT_SP_UART_1_INT_REQ - 16) +#define EXP_I2C0 (INT_SP_I2C_0_INTREQ - 16) +#define EXP_I2C1 (INT_SP_I2C_1_INTREQ - 16) +#define EXP_SPI0 (INT_SP_SPI_0_EVT_REQ - 16) +#define EXP_SPI1 (INT_SP_SPI_1_EVT_REQ - 16) +#define EXP_GPT0 (INT_GPTIMER_0_EVT_CPU_IRQ - 16) +#define EXP_GPT1 (INT_GPTIMER_1_EVT_CPU_IRQ - 16) +#define EXP_ADC (INT_ULL_USC_ULPADCHP_PUB_EVT0_REQ - 16) +#define EXP_HSM (INT_OSPR_HSM_HOST_0_SEC_IRQ - 16) #define EXP_DMA_NS (INT_NON_SECURED_DMA_IRQ_EVT_IND_OUT - 16) +#define EXP_NAB_HOST (INT_NAB_HOST_IRQ - 16) +#define EXP_WDT (INT_HOST_ELP_TMR_WAKEUP_REQ - 16) / { cpus { @@ -59,6 +75,18 @@ #clock-cells = <0>; }; + gptimerclk: gptimer-clock { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + i2cclk: i2c-clock { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + soc { /* I-Cache and ITCM size options can be configured independently The user can * decide how to split ITCM and I-Cache in the following configurations: @@ -261,6 +289,25 @@ reg = <0x41230000 0x10000>; interrupts = ; clocks = <&spiclk>; + }; + + i2c0: i2c@41200000 { + compatible = "ti,cc35xx-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x41200000 0x10000>; + interrupts = ; + clocks = <&i2cclk>; + status = "disabled"; + }; + + i2c1: i2c@41210000 { + compatible = "ti,cc35xx-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x41210000 0x10000>; + interrupts = ; + clocks = <&i2cclk>; status = "disabled"; }; }; diff --git a/dts/bindings/i2c/ti,cc35xx-i2c.yaml b/dts/bindings/i2c/ti,cc35xx-i2c.yaml new file mode 100644 index 000000000000..723b56858ed9 --- /dev/null +++ b/dts/bindings/i2c/ti,cc35xx-i2c.yaml @@ -0,0 +1,18 @@ +description: TI CC35XX I2C controller + +compatible: "ti,cc35xx-i2c" + +include: [i2c-controller.yaml, pinctrl-device.yaml] + +properties: + reg: + required: true + + interrupts: + required: true + + pinctrl-0: + required: true + + pinctrl-names: + required: true diff --git a/include/zephyr/dt-bindings/pinctrl/ti-cc35xx-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/ti-cc35xx-pinctrl.h index 5385b95eec34..3a894b0d1d96 100644 --- a/include/zephyr/dt-bindings/pinctrl/ti-cc35xx-pinctrl.h +++ b/include/zephyr/dt-bindings/pinctrl/ti-cc35xx-pinctrl.h @@ -13,7 +13,7 @@ * - 31..22: Reserved. * - 21..16: Pin. * - 15..11: Reserved. - * - 10: Pin direction + * - 11..10: Pin direction. * - 9: Pull-down flag. * - 8: Pull-up flag. * - 7..5: Drive strength. @@ -30,17 +30,22 @@ #define TI_CC35XX_PIN_POS 16 #define TI_CC35XX_MUX_MSK 0x0f #define TI_CC35XX_MUX_POS 0 -#define TI_CC35XX_DIR_MSK 0x01 +#define TI_CC35XX_DIR_MSK 0x03 #define TI_CC35XX_DIR_POS 10 +#define TI_CC35XX_PU_PD_MSK 0x03 +#define TI_CC35XX_PU_PD_POS 8 /** @} */ -#define TI_CC35XX_PINCTRL_DIR_IN (1 << TI_CC35XX_DIR_POS) -#define TI_CC35XX_PINCTRL_DIR_OUT (0) +#define TI_CC35XX_PINCTRL_DIR_BI (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINCTRL_DIR_OUT) +#define TI_CC35XX_PINCTRL_DIR_IN (2 << TI_CC35XX_DIR_POS) +#define TI_CC35XX_PINCTRL_DIR_OUT (1 << TI_CC35XX_DIR_POS) +#define TI_CC35XX_PINCTRL_PULL_UP (1 << TI_CC35XX_PU_PD_POS) +#define TI_CC35XX_PINCTRL_PULL_DOWN (2 << TI_CC35XX_PU_PD_POS) +#define TI_CC35XX_PINCTRL_PULL_DISABLE (3 << TI_CC35XX_PU_PD_POS) #define TI_CC35XX_PINCTRL_PIN(PCFG) (((PCFG) >> TI_CC35XX_PIN_POS) & TI_CC35XX_PIN_MSK) #define TI_CC35XX_PINCTRL_MUX(PCFG) (((PCFG) >> TI_CC35XX_MUX_POS) & TI_CC35XX_MUX_MSK) -#define TI_CC35XX_PINCTRL_DIR(PCFG) ((PCFG) & TI_CC35XX_PINCTRL_DIR_IN) /** * @brief Utility macro to build TI CC35XX pinmux property entry. @@ -52,6 +57,9 @@ ((((pin) & TI_CC35XX_PIN_MSK) << TI_CC35XX_PIN_POS) | \ (((mux) & TI_CC35XX_MUX_MSK) << TI_CC35XX_MUX_POS)) +#define TI_CC35XX_ANALOG_MUX 0x0d +#define TI_CC35XX_ANALOG(pin) (TI_CC35XX_PINMUX(pin, TI_CC35XX_ANALOG_MUX) | TI_CC35XX_PINCTRL_DIR_IN) + /** * @name TI CC35XX pinctrl pin functions (reference: SWRU626). * @{ @@ -75,7 +83,7 @@ #define P2_XSPI_RESET_RAM TI_CC35XX_PINMUX(2, 1) #define P2_WIFI_GPIO_2 TI_CC35XX_PINMUX(2, 2) #define P2_SDIO_MMC_CD TI_CC35XX_PINMUX(2, 3) -#define P2_I2C1_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(2, 6)) +#define P2_I2C1_CLK (TI_CC35XX_PINCTRL_DIR_BI | TI_CC35XX_PINMUX(2, 6)) #define P2_GPT1_3 TI_CC35XX_PINMUX(2, 9) #define P2_DCAN_TX (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(2, 10)) #define P2_WAKE_OBSERVE_BUS_6 TI_CC35XX_PINMUX(2, 11) @@ -136,10 +144,11 @@ #define P5_XSPI_RESET_RAM TI_CC35XX_PINMUX(5, 1) #define P5_WIFI_GPIO_5 TI_CC35XX_PINMUX(5, 2) +#define P5_WIFI_AIN5 TI_CC35XX_ANALOG(3) #define P5_SDIO_MMC_POW2 TI_CC35XX_PINMUX(5, 3) #define P5_SPI1_MISO TI_CC35XX_PINMUX(5, 4) #define P5_UART1_TX (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(5, 5)) -#define P5_I2C0_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(5, 6)) +#define P5_I2C0_CLK (TI_CC35XX_PINCTRL_DIR_BI | TI_CC35XX_PINMUX(5, 6)) #define P5_I2S_MCLK TI_CC35XX_PINMUX(5, 7) #define P5_PDM_BCLK TI_CC35XX_PINMUX(5, 8) #define P5_GPT1_2 TI_CC35XX_PINMUX(5, 9) @@ -155,14 +164,15 @@ #define P5_BLE_RFTRCN TI_CC35XX_PINMUX(5, 22) #define P5_ANT_SEL_1 TI_CC35XX_PINMUX(5, 23) #define P5_BLE_RFC_GPI_2 TI_CC35XX_PINMUX(5, 25) -#define P5_I2C1_DATA TI_CC35XX_PINMUX(5, 28) +#define P5_I2C1_DATA (TI_CC35XX_PINCTRL_DIR_BI | TI_CC35XX_PINMUX(5, 28)) #define P6_XSPI_CS_RAM TI_CC35XX_PINMUX(6, 1) #define P6_WIFI_GPIO_6 TI_CC35XX_PINMUX(6, 2) +#define P6_WIFI_AIN6 TI_CC35XX_ANALOG(2) #define P6_SDIO_MMC_POW1 TI_CC35XX_PINMUX(6, 3) #define P6_SPI1_MOSI TI_CC35XX_PINMUX(6, 4) #define P6_UART1_RX (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(6, 5)) -#define P6_I2C0_DATA TI_CC35XX_PINMUX(6, 6) +#define P6_I2C0_DATA (TI_CC35XX_PINCTRL_DIR_BI | TI_CC35XX_PINMUX(6, 6)) #define P6_I2S_WCLK TI_CC35XX_PINMUX(6, 7) #define P6_PDM_DATA0 TI_CC35XX_PINMUX(6, 8) #define P6_GPT1_3 TI_CC35XX_PINMUX(6, 9) @@ -180,7 +190,7 @@ #define P6_CCA TI_CC35XX_PINMUX(6, 24) #define P6_BLE_RFC_GPI_3 TI_CC35XX_PINMUX(6, 25) #define P6_COEX_GRANT TI_CC35XX_PINMUX(6, 26) -#define P6_I2C1_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(6, 28)) +#define P6_I2C1_CLK (TI_CC35XX_PINCTRL_DIR_BI | TI_CC35XX_PINMUX(6, 28)) #define P6_SDIO_MMC_POW2 TI_CC35XX_PINMUX(6, 29) #define P7_SWDIO TI_CC35XX_PINMUX(7, 0) @@ -209,7 +219,7 @@ #define P10_SDIO_MMC_DATA_3 TI_CC35XX_PINMUX(10, 3) #define P10_SPI1_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(10, 4)) #define P10_UART1_RTS (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(10, 5)) -#define P10_I2C1_DATA TI_CC35XX_PINMUX(10, 6) +#define P10_I2C1_DATA (TI_CC35XX_PINCTRL_DIR_BI | TI_CC35XX_PINMUX(10, 6)) #define P10_I2S_DATA1 TI_CC35XX_PINMUX(10, 7) #define P10_PDM_DATA1 TI_CC35XX_PINMUX(10, 8) #define P10_GPT1_0 TI_CC35XX_PINMUX(10, 9) @@ -231,7 +241,7 @@ #define P11_SDIO_MMC_DATA_2 TI_CC35XX_PINMUX(11, 3) #define P11_SPI1_CS1 TI_CC35XX_PINMUX(11, 4) #define P11_UART1_CTS (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(11, 5)) -#define P11_I2C1_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(11, 6)) +#define P11_I2C1_CLK (TI_CC35XX_PINCTRL_DIR_BI | TI_CC35XX_PINMUX(11, 6)) #define P11_I2S_DATA0 TI_CC35XX_PINMUX(11, 7) #define P11_PDM_DATA0 TI_CC35XX_PINMUX(11, 8) #define P11_GPT1_1 TI_CC35XX_PINMUX(11, 9) @@ -329,7 +339,7 @@ #define P16_SDIO_MMC_DATA_7 TI_CC35XX_PINMUX(16, 3) #define P16_SPI0_CS1 TI_CC35XX_PINMUX(16, 4) #define P16_UART0_RTS (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(16, 5)) -#define P16_I2C1_DATA TI_CC35XX_PINMUX(16, 6) +#define P16_I2C1_DATA (TI_CC35XX_PINCTRL_DIR_BI | TI_CC35XX_PINMUX(16, 6)) #define P16_I2S_WCLK TI_CC35XX_PINMUX(16, 7) #define P16_PDM_BCLK TI_CC35XX_PINMUX(16, 8) #define P16_GPT0_0 TI_CC35XX_PINMUX(16, 9) @@ -349,7 +359,7 @@ #define P17_SDIO_MMC_DATA_6 TI_CC35XX_PINMUX(17, 3) #define P17_SPI0_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(17, 4)) #define P17_UART0_TX (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(17, 5)) -#define P17_I2C0_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(17, 6)) +#define P17_I2C0_CLK (TI_CC35XX_PINCTRL_DIR_BI | TI_CC35XX_PINMUX(17, 6)) #define P17_I2S_DATA1 TI_CC35XX_PINMUX(17, 7) #define P17_PDM_DATA0 TI_CC35XX_PINMUX(17, 8) #define P17_GPT0_1 TI_CC35XX_PINMUX(17, 9) @@ -368,7 +378,7 @@ #define P18_SDIO_MMC_DATA_5 TI_CC35XX_PINMUX(18, 3) #define P18_SPI0_MISO TI_CC35XX_PINMUX(18, 4) #define P18_UART0_RX (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(18, 5)) -#define P18_I2C0_DATA TI_CC35XX_PINMUX(18, 6) +#define P18_I2C0_DATA (TI_CC35XX_PINCTRL_DIR_BI | TI_CC35XX_PINMUX(18, 6)) #define P18_I2S_DATA0 TI_CC35XX_PINMUX(18, 7) #define P18_PDM_DATA1 TI_CC35XX_PINMUX(18, 8) #define P18_GPT0_2 TI_CC35XX_PINMUX(18, 9) @@ -387,7 +397,7 @@ #define P19_SDIO_MMC_DATA_4 TI_CC35XX_PINMUX(19, 3) #define P19_SPI0_MOSI TI_CC35XX_PINMUX(19, 4) #define P19_UART0_CTS (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(19, 5)) -#define P19_I2C1_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(19, 6)) +#define P19_I2C1_CLK (TI_CC35XX_PINCTRL_DIR_BI | TI_CC35XX_PINMUX(19, 6)) #define P19_I2S_BCLK TI_CC35XX_PINMUX(19, 7) #define P19_PDM_DATA0 TI_CC35XX_PINMUX(19, 8) #define P19_GPT0_3 TI_CC35XX_PINMUX(19, 9) @@ -426,7 +436,7 @@ #define P26_WIFI_GPIO_26 TI_CC35XX_PINMUX(26, 2) #define P26_SPI0_CS1 TI_CC35XX_PINMUX(26, 4) #define P26_UART0_RTS (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(26, 5)) -#define P26_I2C1_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(26, 6)) +#define P26_I2C1_CLK (TI_CC35XX_PINCTRL_DIR_BI | TI_CC35XX_PINMUX(26, 6)) #define P26_I2S_WCLK TI_CC35XX_PINMUX(26, 7) #define P26_PDM_BCLK TI_CC35XX_PINMUX(26, 8) #define P26_GPT0_0 TI_CC35XX_PINMUX(26, 9) @@ -450,7 +460,7 @@ #define P27_WIFI_GPIO_27 TI_CC35XX_PINMUX(27, 2) #define P27_SPI0_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(27, 4)) #define P27_UART0_TX (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(27, 5)) -#define P27_I2C0_DATA TI_CC35XX_PINMUX(27, 6) +#define P27_I2C0_DATA (TI_CC35XX_PINCTRL_DIR_BI | TI_CC35XX_PINMUX(27, 6)) #define P27_I2S_DATA0 TI_CC35XX_PINMUX(27, 7) #define P27_PDM_DATA0 TI_CC35XX_PINMUX(27, 8) #define P27_GPT0_1 TI_CC35XX_PINMUX(27, 9) @@ -468,7 +478,7 @@ #define P28_WIFI_GPIO_28 TI_CC35XX_PINMUX(28, 2) #define P28_SPI0_MISO TI_CC35XX_PINMUX(28, 4) #define P28_UART0_RX (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(28, 5)) -#define P28_I2C0_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(28, 6)) +#define P28_I2C0_CLK (TI_CC35XX_PINCTRL_DIR_BI | TI_CC35XX_PINMUX(28, 6)) #define P28_I2S_DATA1 TI_CC35XX_PINMUX(28, 7) #define P28_PDM_BCLK TI_CC35XX_PINMUX(28, 8) #define P28_GPT0_2 TI_CC35XX_PINMUX(28, 9) @@ -487,7 +497,7 @@ #define P29_WIFI_GPIO_29 TI_CC35XX_PINMUX(29, 2) #define P29_SPI0_MOSI TI_CC35XX_PINMUX(29, 4) #define P29_UART0_CTS (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(29, 5)) -#define P29_I2C1_DATA TI_CC35XX_PINMUX(29, 6) +#define P29_I2C1_DATA (TI_CC35XX_PINCTRL_DIR_BI | TI_CC35XX_PINMUX(29, 6)) #define P29_I2S_BCLK TI_CC35XX_PINMUX(29, 7) #define P29_PDM_DATA1 TI_CC35XX_PINMUX(29, 8) #define P29_GPT0_3 TI_CC35XX_PINMUX(29, 9) @@ -506,8 +516,8 @@ #define P30_WIFI_GPIO_30 TI_CC35XX_PINMUX(30, 2) #define P30_XSPI_RESET_FLASH TI_CC35XX_PINMUX(30, 3) #define P30_XSPI_RESET_RAM TI_CC35XX_PINMUX(30, 4) -#define P30_I2C1_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(30, 5)) -#define P30_I2C0_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(30, 6)) +#define P30_I2C1_CLK (TI_CC35XX_PINCTRL_DIR_BI | TI_CC35XX_PINMUX(30, 5)) +#define P30_I2C0_CLK (TI_CC35XX_PINCTRL_DIR_BI | TI_CC35XX_PINMUX(30, 6)) #define P30_I2S_DATA0 TI_CC35XX_PINMUX(30, 7) #define P30_PDM_DATA0 TI_CC35XX_PINMUX(30, 8) #define P30_GPT1_1 TI_CC35XX_PINMUX(30, 9) @@ -534,7 +544,7 @@ #define P31_XSPI_RESET_FLASH TI_CC35XX_PINMUX(31, 3) #define P31_SPI1_CS1 TI_CC35XX_PINMUX(31, 4) #define P31_UART1_RTS (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(31, 5)) -#define P31_I2C1_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(31, 6)) +#define P31_I2C1_CLK (TI_CC35XX_PINCTRL_DIR_BI | TI_CC35XX_PINMUX(31, 6)) #define P31_I2S_WCLK TI_CC35XX_PINMUX(31, 7) #define P31_PDM_BCLK TI_CC35XX_PINMUX(31, 8) #define P31_GPT1_0 TI_CC35XX_PINMUX(31, 9) @@ -555,7 +565,7 @@ #define P32_SPI1_CS1 TI_CC35XX_PINMUX(32, 3) #define P32_SPI1_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(32, 4)) #define P32_UART1_TX (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(32, 5)) -#define P32_I2C0_DATA TI_CC35XX_PINMUX(32, 6) +#define P32_I2C0_DATA (TI_CC35XX_PINCTRL_DIR_BI | TI_CC35XX_PINMUX(32, 6)) #define P32_I2S_DATA1 TI_CC35XX_PINMUX(32, 7) #define P32_PDM_BCLK TI_CC35XX_PINMUX(32, 8) #define P32_GPT1_1 TI_CC35XX_PINMUX(32, 9) @@ -571,7 +581,7 @@ #define P33_WIFI_GPIO_33 TI_CC35XX_PINMUX(33, 2) #define P33_SPI1_MISO TI_CC35XX_PINMUX(33, 4) #define P33_UART1_RX (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(33, 5)) -#define P33_I2C0_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(33, 6)) +#define P33_I2C0_CLK (TI_CC35XX_PINCTRL_DIR_BI | TI_CC35XX_PINMUX(33, 6)) #define P33_I2S_DATA0 TI_CC35XX_PINMUX(33, 7) #define P33_PDM_DATA0 TI_CC35XX_PINMUX(33, 8) #define P33_GPT1_2 TI_CC35XX_PINMUX(33, 9) @@ -589,7 +599,7 @@ #define P34_WIFI_GPIO_34 TI_CC35XX_PINMUX(34, 2) #define P34_SPI1_MOSI TI_CC35XX_PINMUX(34, 4) #define P34_UART1_CTS (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(34, 5)) -#define P34_I2C1_DATA TI_CC35XX_PINMUX(34, 6) +#define P34_I2C1_DATA (TI_CC35XX_PINCTRL_DIR_BI | TI_CC35XX_PINMUX(34, 6)) #define P34_I2S_BCLK TI_CC35XX_PINMUX(34, 7) #define P34_PDM_DATA1 TI_CC35XX_PINMUX(34, 8) #define P34_GPT1_3 TI_CC35XX_PINMUX(34, 9) @@ -608,12 +618,12 @@ #define P35_SPI1_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(35, 3)) #define P35_XSPI_RESET_RAM TI_CC35XX_PINMUX(35, 4) #define P35_UART1_RX (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(35, 5)) -#define P35_I2C0_DATA TI_CC35XX_PINMUX(35, 6) +#define P35_I2C0_DATA (TI_CC35XX_PINCTRL_DIR_BI | TI_CC35XX_PINMUX(35, 6)) #define P35_I2S_DATA1 TI_CC35XX_PINMUX(35, 7) #define P35_PDM_BCLK TI_CC35XX_PINMUX(35, 8) #define P35_GPT0_1 TI_CC35XX_PINMUX(35, 9) #define P35_DCAN_RX (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(35, 10)) -#define P35_I2C1_DATA TI_CC35XX_PINMUX(35, 11) +#define P35_I2C1_DATA (TI_CC35XX_PINCTRL_DIR_BI | TI_CC35XX_PINMUX(35, 11)) #define P35_XSPI_CS_RAM TI_CC35XX_PINMUX(35, 12) #define P35_SPI0_CS4 TI_CC35XX_PINMUX(35, 16) #define P35_SPI0_CS3 TI_CC35XX_PINMUX(35, 17) @@ -662,7 +672,7 @@ #define P38_EXT_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(38, 3)) #define P38_SPI1_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(38, 4)) #define P38_UART0_CTS (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(38, 5)) -#define P38_I2C1_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(38, 6)) +#define P38_I2C1_CLK (TI_CC35XX_PINCTRL_DIR_BI | TI_CC35XX_PINMUX(38, 6)) #define P38_I2S_BCLK TI_CC35XX_PINMUX(38, 7) #define P38_PDM_BCLK TI_CC35XX_PINMUX(38, 8) #define P38_GPT1_0 TI_CC35XX_PINMUX(38, 9) @@ -677,7 +687,7 @@ #define P39_UART0_RX (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(39, 3)) #define P39_SPI1_MISO TI_CC35XX_PINMUX(39, 4) #define P39_UART0_RTS (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(39, 5)) -#define P39_I2C1_DATA TI_CC35XX_PINMUX(39, 6) +#define P39_I2C1_DATA (TI_CC35XX_PINCTRL_DIR_BI | TI_CC35XX_PINMUX(39, 6)) #define P39_I2S_WCLK TI_CC35XX_PINMUX(39, 7) #define P39_PDM_DATA0 TI_CC35XX_PINMUX(39, 8) #define P39_GPT1_1 TI_CC35XX_PINMUX(39, 9) @@ -721,7 +731,7 @@ #define P42_UART1_RX (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(42, 3)) #define P42_SPI1_MOSI TI_CC35XX_PINMUX(42, 4) #define P42_UART1_RTS (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(42, 5)) -#define P42_I2C0_DATA TI_CC35XX_PINMUX(42, 6) +#define P42_I2C0_DATA (TI_CC35XX_PINCTRL_DIR_BI | TI_CC35XX_PINMUX(42, 6)) #define P42_I2S_WCLK TI_CC35XX_PINMUX(42, 7) #define P42_PDM_DATA0 TI_CC35XX_PINMUX(42, 8) #define P42_GPT0_1 TI_CC35XX_PINMUX(42, 9) @@ -735,7 +745,7 @@ #define P43_WIFI_GPIO_43 TI_CC35XX_PINMUX(43, 2) #define P43_SPI1_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(43, 4)) #define P43_UART1_TX (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(43, 5)) -#define P43_I2C0_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(43, 6)) +#define P43_I2C0_CLK (TI_CC35XX_PINCTRL_DIR_BI | TI_CC35XX_PINMUX(43, 6)) #define P43_I2S_BCLK TI_CC35XX_PINMUX(43, 7) #define P43_PDM_BCLK TI_CC35XX_PINMUX(43, 8) #define P43_GPT0_2 TI_CC35XX_PINMUX(43, 9) @@ -746,7 +756,6 @@ #define P44_XSPI_CLK_INPUT TI_CC35XX_PINMUX(44, 0) #define P44_WIFI_GPIO_44 TI_CC35XX_PINMUX(44, 2) - /** @} */ #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_TI_CC35XX_PINCTRL_H_ */ From b04948e1d633f743d636b297d0d1a87cf83bcd86 Mon Sep 17 00:00:00 2001 From: Radoslaw Adamczyk Date: Fri, 13 Feb 2026 11:26:10 +0100 Subject: [PATCH 035/100] UPSTREAM-PEND: drivers: i2c_cc35xx: remove waiting if controller is busy Remove waiting loop if controller is busy. Signed-off-by: Radoslaw Adamczyk Signed-off-by: Artur Rojek --- drivers/i2c/i2c_cc35xx.c | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/drivers/i2c/i2c_cc35xx.c b/drivers/i2c/i2c_cc35xx.c index 03882ba51c5a..f515dad66b25 100644 --- a/drivers/i2c/i2c_cc35xx.c +++ b/drivers/i2c/i2c_cc35xx.c @@ -176,22 +176,14 @@ static int i2c_cc35xx_transfer(const struct device *dev, struct i2c_msg *msgs, const struct i2c_cc35xx_config *config = dev->config; struct i2c_msg *msg; int ret = 0, retries, flags; - uint16_t timeout = UINT16_MAX; - - k_mutex_lock(&data->mutex, K_FOREVER); - k_sem_reset(&data->i2c_msg_done); - - - while (I2CControllerIsBusy(config->base) && --timeout) { - k_busy_wait(USEC_PER_MSEC); - } - - if (!timeout) { - k_mutex_unlock(&data->mutex); + if (I2CControllerIsBusy(config->base)) { return -EBUSY; } + k_mutex_lock(&data->mutex, K_FOREVER); + k_sem_reset(&data->i2c_msg_done); + I2CFlushFifos(config->base); I2CClearInt(config->base, I2C_INT_ALL); From 5180187c9a19b779943affbe9bbc39dc44504970 Mon Sep 17 00:00:00 2001 From: Jakub Jarosinski Date: Fri, 24 Apr 2026 18:44:47 +0200 Subject: [PATCH 036/100] =?UTF-8?q?UPSTREAM-PEND:=20drivers:=20i2c:=20cc35?= =?UTF-8?q?xx:=20post-SetCommand=20settle=20per=20TRM=20=C2=A719.4?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 500 us settle is required after CCTR is written for the controller FSM to progress before the event IRQ takes over. Signed-off-by: Jakub Jarosinski --- drivers/i2c/i2c_cc35xx.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/i2c_cc35xx.c b/drivers/i2c/i2c_cc35xx.c index f515dad66b25..348b721f1598 100644 --- a/drivers/i2c/i2c_cc35xx.c +++ b/drivers/i2c/i2c_cc35xx.c @@ -162,7 +162,15 @@ static int i2c_cc35xx_prime_transfer(const struct device *dev, uint8_t *buf, uin I2CEnableInt(config->base, enable_interrupt); I2CControllerSetTargetAddr(config->base, addr_mode, addr, direction); I2CControllerSetCommand(config->base, cmd, data->buflen); - if (k_sem_take(&data->i2c_msg_done, K_MSEC(100))) { + /* + * TRM §19.4: after issuing CCTR, "Wait until the transmission + * completes by polling the CSR register's BUSY bit until it has + * been cleared." ~500 us settle is required here for the + * controller FSM to progress before the event IRQ takes over. + */ + k_busy_wait(500); + int st = k_sem_take(&data->i2c_msg_done, K_MSEC(100)); + if (st) { return -ETIMEDOUT; } @@ -185,7 +193,7 @@ static int i2c_cc35xx_transfer(const struct device *dev, struct i2c_msg *msgs, k_sem_reset(&data->i2c_msg_done); I2CFlushFifos(config->base); - I2CClearInt(config->base, I2C_INT_ALL); + I2CClearInt(config->base, I2C_INT_ALL); /* 10ms match swuart print delay */ for (int i = 0; i < num_msgs; i++) { msg = msgs + i; From 3cffab2bc00bb391b02c4ba670a67366bf1cd3cd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=81yszczek?= Date: Thu, 11 Dec 2025 23:23:13 +0100 Subject: [PATCH 037/100] UPSTREAM-PEND: drivers/pwm: add pwm for cc35xx chip MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add PWM drivers based on counter for cc35xx chip Signed-off-by: Michał Łyszczek --- boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml | 1 + .../lp_em_cc35x1_cc3501e_defconfig | 3 + .../ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi | 26 ++++- drivers/pwm/CMakeLists.txt | 1 + drivers/pwm/Kconfig | 1 + drivers/pwm/Kconfig.cc35xx_timer | 10 ++ drivers/pwm/pwm_cc35xx_timer.c | 106 ++++++++++++++++++ dts/arm/ti/cc35xxe.dtsi | 52 +++++++++ dts/bindings/pwm/ti,cc35xx-lgpt-pwm.yaml | 20 ++++ .../pwm/pwm_api/boards/lp_em_cc35x1.overlay | 11 ++ 10 files changed, 226 insertions(+), 5 deletions(-) create mode 100644 drivers/pwm/Kconfig.cc35xx_timer create mode 100644 drivers/pwm/pwm_cc35xx_timer.c create mode 100644 dts/bindings/pwm/ti,cc35xx-lgpt-pwm.yaml create mode 100644 tests/drivers/pwm/pwm_api/boards/lp_em_cc35x1.overlay diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml b/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml index 55af4d052712..478f16307368 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml @@ -11,4 +11,5 @@ supported: - gpio - pinctrl - serial + - pwm vendor: ti diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3501e_defconfig b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3501e_defconfig index 4fd9874f94c2..71bcdc300bf5 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3501e_defconfig +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3501e_defconfig @@ -38,3 +38,6 @@ CONFIG_DMA=y CONFIG_I2C=y CONFIG_I2C_CC35XX=y CONFIG_I2C_SHELL=y + +CONFIG_PWM=y +CONFIG_PWM_CC35XX_TIMER=y diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi index 75cd41ff6308..0306b234b251 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi @@ -11,6 +11,7 @@ #include #include "boosterpack_connector.dtsi" #include "lp_em_cc35x1-pinctrl.dtsi" +#include / { model = "TI CC35X1E LaunchPad"; @@ -28,10 +29,6 @@ leds { compatible = "gpio-leds"; - green_led: green_led { - gpios = <&gpios 30 GPIO_ACTIVE_HIGH>; - label = "GREEN USER LED"; - }; red_led: red_led { gpios = <&gpios 34 GPIO_ACTIVE_HIGH>; label = "RED USER LED"; @@ -42,6 +39,14 @@ }; }; + pwmleds { + compatible = "pwm-leds"; + green_pwm: pwm_led_0 { + pwms = <&pwm4 1 1000 PWM_POLARITY_NORMAL>; + label = "Green PWM LED"; + }; + }; + buttons { compatible = "gpio-keys"; user_switch_1: user_sw_1 { @@ -55,9 +60,9 @@ }; aliases { - led0 = &green_led; led1 = &red_led; led2 = &blue_led; + pwm-led0 = &green_pwm; sw0 = &user_switch_1; sw1 = &user_switch_2; dma0 = &dma; @@ -202,3 +207,14 @@ pinctrl-0 = <&uart1_default>; pinctrl-names = "default"; }; + +&timer1 { + clk-prescale = <0x1>; + status = "okay"; +}; + +&pwm4 { + pinctrl-0 = <&pwm4_default>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/drivers/pwm/CMakeLists.txt b/drivers/pwm/CMakeLists.txt index 98b59aa35e77..7df6316fd4c5 100644 --- a/drivers/pwm/CMakeLists.txt +++ b/drivers/pwm/CMakeLists.txt @@ -17,6 +17,7 @@ zephyr_library_sources_ifdef(CONFIG_PWM_BFLB_1 pwm_bflb_1.c) zephyr_library_sources_ifdef(CONFIG_PWM_BFLB_2 pwm_bflb_2.c) zephyr_library_sources_ifdef(CONFIG_PWM_CC13XX_CC26XX_TIMER pwm_cc13xx_cc26xx_timer.c) zephyr_library_sources_ifdef(CONFIG_PWM_CC23X0_TIMER pwm_cc23x0_timer.c) +zephyr_library_sources_ifdef(CONFIG_PWM_CC35XX_TIMER pwm_cc35xx_timer.c) zephyr_library_sources_ifdef(CONFIG_PWM_ENE_KB106X pwm_ene_kb106x.c) zephyr_library_sources_ifdef(CONFIG_PWM_ENE_KB1200 pwm_ene_kb1200.c) zephyr_library_sources_ifdef(CONFIG_PWM_FAKE pwm_fake.c) diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index d6b985cdb5b3..403100a8ec55 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -45,6 +45,7 @@ source "drivers/pwm/Kconfig.b91" source "drivers/pwm/Kconfig.bflb" source "drivers/pwm/Kconfig.cc13xx_cc26xx_timer" source "drivers/pwm/Kconfig.cc23x0_timer" +source "drivers/pwm/Kconfig.cc35xx_timer" source "drivers/pwm/Kconfig.ene" source "drivers/pwm/Kconfig.esp32" source "drivers/pwm/Kconfig.fake" diff --git a/drivers/pwm/Kconfig.cc35xx_timer b/drivers/pwm/Kconfig.cc35xx_timer new file mode 100644 index 000000000000..f5583a0a3a0e --- /dev/null +++ b/drivers/pwm/Kconfig.cc35xx_timer @@ -0,0 +1,10 @@ +# Copyright (c) 2025 Conclusive Engineering Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +config PWM_CC35XX_TIMER + bool "TI SimpleLink CC35XX LGPT PWM driver" + default y + depends on DT_HAS_TI_CC35XX_LGPT_PWM_ENABLED + select PINCTRL + help + Enables TI SimpleLink CC35XX LGPT PWM driver. diff --git a/drivers/pwm/pwm_cc35xx_timer.c b/drivers/pwm/pwm_cc35xx_timer.c new file mode 100644 index 000000000000..c80635e3876b --- /dev/null +++ b/drivers/pwm/pwm_cc35xx_timer.c @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2025 Conclusive Engineering Sp. z o.o. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT ti_cc35xx_lgpt_pwm + +#include +#include +#include + +#include +#include + +#include +#define LOG_MODULE_NAME pwm_cc35xx_lgpt +LOG_MODULE_REGISTER(LOG_MODULE_NAME, CONFIG_PWM_LOG_LEVEL); + +#define GPTIMER_O_CXCC(index) (GPTIMER_O_C0CC + ((index) * 4)) +#define GPTIMER_O_CXCFG(index) (GPTIMER_O_C0CFG + ((index) * 4)) +#define TI_CC35XX_CNTR_START 0x01 +#define TI_CC35XX_CNTR_STOP 0x00 + +struct pwm_cc35xx_config { + const uint32_t base; + const struct pinctrl_dev_config *pcfg; + uint32_t freq; + uint32_t prescale; + uint8_t channel; +}; + +static int pwm_cc35xx_set_cycles(const struct device *dev, uint32_t channel, uint32_t period, + uint32_t pulse, pwm_flags_t flags) +{ + const struct pwm_cc35xx_config *config = dev->config; + uint32_t chcfg = GPTIMER_C1CFG_OUT0_EN << channel | 0xa; + uint32_t reg_ctl_val = sys_read32(config->base + GPTIMER_O_CTL); + + ARG_UNUSED(flags); + + if (channel >= 3) { + LOG_ERR("Invalid channel %u, must be 0-2", channel); + return -EINVAL; + } + + LOG_DBG("set cycles period[%x] pulse[%x]", period, pulse); + + sys_write32(period, config->base + GPTIMER_O_TGT); + sys_write32(pulse, config->base + GPTIMER_O_CXCC(channel)); + sys_write32(chcfg, config->base + GPTIMER_O_CXCFG(channel)); + reg_ctl_val &= ~GPTIMER_CTL_MODE_M; + reg_ctl_val |= GPTIMER_CTL_MODE_UP_PER; + sys_write32(reg_ctl_val, config->base + GPTIMER_O_CTL); + sys_write32(TI_CC35XX_CNTR_START, config->base + GPTIMER_O_STARTCFG); + + return 0; +} + +static int pwm_cc35xx_get_cycles_per_sec(const struct device *dev, uint32_t channel, + uint64_t *cycles) +{ + const struct pwm_cc35xx_config *config = dev->config; + + ARG_UNUSED(channel); + *cycles = config->freq / (config->prescale + 1); + + return 0; +} + +static const struct pwm_driver_api pwm_cc35xx_api = { + .set_cycles = pwm_cc35xx_set_cycles, + .get_cycles_per_sec = pwm_cc35xx_get_cycles_per_sec, +}; + +#define DT_TIMER(n) DT_INST_PARENT(n) +#define DT_TIMER_BASE_ADDR(n) (DT_REG_ADDR(DT_TIMER(n))) + +#define PWM_CC35XX_INIT_FUNC(n) \ + static int pwm_cc35xx_init_##n(const struct device *dev) \ + { \ + const struct pwm_cc35xx_config *config = dev->config; \ + int ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); \ + if (ret < 0) { \ + LOG_ERR("[ERR] failed to setup PWM pinctrl"); \ + return ret; \ + } \ + return 0; \ + } + +#define PWM_CC35XX_INIT(n) \ + PWM_CC35XX_INIT_FUNC(n); \ + PINCTRL_DT_INST_DEFINE(n); \ + LOG_INSTANCE_REGISTER(LOG_MODULE_NAME, n, CONFIG_PWM_LOG_LEVEL); \ + \ + static const struct pwm_cc35xx_config cc35xx_pwm_config_##n = { \ + .base = DT_TIMER_BASE_ADDR(n), \ + .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \ + .freq = DT_PROP(DT_PATH(gptimer_clock), clock_frequency), \ + .prescale = DT_PROP(DT_INST_PARENT(n), clk_prescale), \ + .channel = n, \ + }; \ + DEVICE_DT_INST_DEFINE(n, &pwm_cc35xx_init_##n, NULL, NULL, &cc35xx_pwm_config_##n, \ + POST_KERNEL, CONFIG_PWM_INIT_PRIORITY, &pwm_cc35xx_api); + +DT_INST_FOREACH_STATUS_OKAY(PWM_CC35XX_INIT); diff --git a/dts/arm/ti/cc35xxe.dtsi b/dts/arm/ti/cc35xxe.dtsi index e87c160a3947..9e764cf7644e 100644 --- a/dts/arm/ti/cc35xxe.dtsi +++ b/dts/arm/ti/cc35xxe.dtsi @@ -202,6 +202,58 @@ status = "disabled"; }; + timer0: gpt@41260000 { + compatible = "ti,cc35xx-lgpt"; + reg = <0x41260000 0x8000>; + interrupts = ; + clocks = <&gptimerclk>; + max-top-value = <0xFFFFFFFF>; + clk-prescale = <0xFF>; + status = "disabled"; + + pwm0: pwm0 { + compatible = "ti,cc35xx-lgpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + pwm1: pwm1 { + compatible = "ti,cc35xx-lgpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + pwm2: pwm2 { + compatible = "ti,cc35xx-lgpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + timer1: gpt@41268000 { + compatible = "ti,cc35xx-lgpt"; + reg = <0x41268000 0x8000>; + interrupts = ; + clocks = <&gptimerclk>; + max-top-value = <0xFFFFFFFF>; + clk-prescale = <0xFF>; + status = "disabled"; + + pwm3: pwm0 { + compatible = "ti,cc35xx-lgpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + pwm4: pwm1 { + compatible = "ti,cc35xx-lgpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + pwm5: pwm2 { + compatible = "ti,cc35xx-lgpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + dma: dma@41a00000 { compatible = "ti,cc35xx-dma"; reg = <0x41a00000 0x10000>; diff --git a/dts/bindings/pwm/ti,cc35xx-lgpt-pwm.yaml b/dts/bindings/pwm/ti,cc35xx-lgpt-pwm.yaml new file mode 100644 index 000000000000..8d9e90892634 --- /dev/null +++ b/dts/bindings/pwm/ti,cc35xx-lgpt-pwm.yaml @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 + +description: | + TI CC35XX LGPT PWM Controller Node + +compatible: "ti,cc35xx-lgpt-pwm" + +include: [base.yaml, pwm-controller.yaml, pinctrl-device.yaml] + +properties: + pinctrl-0: + required: true + + pinctrl-names: + required: true + +pwm-cells: + - channel + - period + - flags diff --git a/tests/drivers/pwm/pwm_api/boards/lp_em_cc35x1.overlay b/tests/drivers/pwm/pwm_api/boards/lp_em_cc35x1.overlay new file mode 100644 index 000000000000..eeb7f1a45d0f --- /dev/null +++ b/tests/drivers/pwm/pwm_api/boards/lp_em_cc35x1.overlay @@ -0,0 +1,11 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + aliases { + pwm-0 = &pwm4; + }; +}; From 73b6c72af90ed6f2f9c78237e1e8ba3ebad434c0 Mon Sep 17 00:00:00 2001 From: Jakub Jarosinski Date: Wed, 22 Apr 2026 00:31:38 +0200 Subject: [PATCH 038/100] UPSTREAM-PEND: drivers: timer: cc35xx: add Kconfig for RTC system clock Define CC35XX_RTC_TIMER selecting TICKLESS_CAPABLE, gated on HAS_CC35XX_SDK. Signed-off-by: Jakub Jarosinski --- drivers/timer/Kconfig.cc35xx_rtc | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 drivers/timer/Kconfig.cc35xx_rtc diff --git a/drivers/timer/Kconfig.cc35xx_rtc b/drivers/timer/Kconfig.cc35xx_rtc new file mode 100644 index 000000000000..d4f3bb7f52e4 --- /dev/null +++ b/drivers/timer/Kconfig.cc35xx_rtc @@ -0,0 +1,13 @@ +# Copyright (c) 2026 Conclusive Engineering Sp. z o.o. +# +# SPDX-License-Identifier: Apache-2.0 + +config CC35XX_RTC_TIMER + bool "TI SimpleLink CC35XX RTC system clock timer" + default n + depends on HAS_CC35XX_SDK + select TICKLESS_CAPABLE + help + This module provides the RTC as "system clock driver" interface + for the TI SimpleLink CC35XX devices. The RTC runs at 1us + resolution (1 MHz effective rate). From 2dd2367a34afceccbdbe06339b70f2f9bfed1e7d Mon Sep 17 00:00:00 2001 From: Jakub Jarosinski Date: Wed, 22 Apr 2026 00:31:52 +0200 Subject: [PATCH 039/100] UPSTREAM-PEND: drivers: timer: source Kconfig.cc35xx_rtc Wire the CC35XX RTC timer Kconfig into the timer driver menu. Signed-off-by: Jakub Jarosinski --- drivers/timer/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index f84baa857e92..30c04b8e57a3 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -90,6 +90,7 @@ source "drivers/timer/Kconfig.arm_arch" source "drivers/timer/Kconfig.cavs" source "drivers/timer/Kconfig.cc13xx_cc26xx_rtc" source "drivers/timer/Kconfig.cc23x0" +source "drivers/timer/Kconfig.cc35xx_rtc" source "drivers/timer/Kconfig.cortex_m_systick" source "drivers/timer/Kconfig.esp32" source "drivers/timer/Kconfig.gecko" From c906f2d3c359f7846badc6a36321d73aa6623636 Mon Sep 17 00:00:00 2001 From: Jakub Jarosinski Date: Wed, 22 Apr 2026 11:39:19 +0200 Subject: [PATCH 040/100] UPSTREAM-PEND: drivers: timer: cc35xx: add RTC-based system clock driver Tickless system timer driver backed by the CC35XX RTC peripheral. The RTC provides a free-running 32-bit 1us counter with a compare channel used to drive kernel ticks. Gated on CC35XX_RTC_TIMER. Signed-off-by: Jakub Jarosinski --- drivers/timer/CMakeLists.txt | 1 + drivers/timer/cc35xx_rtc_timer.c | 178 +++++++++++++++++++++++++++++++ 2 files changed, 179 insertions(+) create mode 100644 drivers/timer/cc35xx_rtc_timer.c diff --git a/drivers/timer/CMakeLists.txt b/drivers/timer/CMakeLists.txt index f3b0599cdcb7..9baf0afbdd90 100644 --- a/drivers/timer/CMakeLists.txt +++ b/drivers/timer/CMakeLists.txt @@ -13,6 +13,7 @@ zephyr_library_sources_ifdef(CONFIG_ARM_ARCH_TIMER arm_arch_timer.c) zephyr_library_sources_ifdef(CONFIG_CC13XX_CC26XX_RTC_TIMER cc13xx_cc26xx_rtc_timer.c) zephyr_library_sources_ifdef(CONFIG_CC23X0_RTC_TIMER cc23x0_rtc_timer.c) zephyr_library_sources_ifdef(CONFIG_CC23X0_SYSTIM_TIMER cc23x0_systim_timer.c) +zephyr_library_sources_ifdef(CONFIG_CC35XX_RTC_TIMER cc35xx_rtc_timer.c) zephyr_library_sources_ifdef(CONFIG_CH32V00X_SYSTICK wch_systick_ch32v00x.c) zephyr_library_sources_ifdef(CONFIG_CORTEX_M_SYSTICK cortex_m_systick.c) zephyr_library_sources_ifdef(CONFIG_ESP32_SYS_TIMER esp32_sys_timer.c) diff --git a/drivers/timer/cc35xx_rtc_timer.c b/drivers/timer/cc35xx_rtc_timer.c new file mode 100644 index 000000000000..8234cd90c562 --- /dev/null +++ b/drivers/timer/cc35xx_rtc_timer.c @@ -0,0 +1,178 @@ +/* + * Copyright (c) 2026 Conclusive Engineering Sp. z o.o. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* TI SimpleLink CC35XX timer driver based on RTC */ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +/* Kernel tick period in microseconds (same timebase as RTC) */ +#define TICK_PERIOD_SYS (USEC_PER_SEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC) + +/* + * Max number of RTC ticks into the future + * + * Under the hood, the kernel timer uses the RTC whose events trigger + * immediately if the compare value is less than 2^22 RTC ticks in the past + * (4.194sec at 1us resolution). Therefore, the max number of RTC ticks you + * can schedule into the future is 2^32 - 2^22 - 1 ticks (~= 4290 sec at 1us + * resolution). + */ +#define RTC_TIMEOUT_MAX 0xFFBFFFFFU + +/* Set RTC interrupt to lowest priority */ +#define RTC_ISR_PRIORITY 3U +#define CC35XX_RTC_NODE DT_NODELABEL(rtc) +#define CC35XX_RTC_BASE DT_REG_ADDR(CC35XX_RTC_NODE) + +static struct k_spinlock lock; + +/* Keep track of RTC counter at previous announcement to the kernel */ +static uint32_t last_rtc_count; + +static void rtc_isr(const void *arg); +static int sys_clock_driver_init(void); +static uint32_t sys_clock_elapsed_ticks(uint32_t current, uint32_t last); + + +/* + * Set system clock timeout. + */ +void sys_clock_set_timeout(int32_t ticks, bool idle) +{ + ARG_UNUSED(idle); + + k_spinlock_key_t key = k_spin_lock(&lock); + /* If timeout is necessary */ + if (ticks != K_TICKS_FOREVER) { + uint32_t now_tick = sys_read32(CC35XX_RTC_BASE + RTC_O_TIME1U); + uint32_t elapsed = now_tick - last_rtc_count; + uint32_t timeout; + + /* + * Zephyr passes the number of ticks until the next timeout. + * Program the comparator relative to the last announced + * kernel tick so we do not leave CH0 behind "now" when PM + * reaches the sleep hook late in the current tick. + */ + ticks = CLAMP(ticks - 1, 0, (int32_t)(RTC_TIMEOUT_MAX / TICK_PERIOD_SYS)); + timeout = (ticks * TICK_PERIOD_SYS) + elapsed; + timeout = DIV_ROUND_UP(timeout, TICK_PERIOD_SYS) * TICK_PERIOD_SYS; + + if (timeout > RTC_TIMEOUT_MAX) { + timeout = RTC_TIMEOUT_MAX; + /* Make sure timeout is a multiple of TICK_PERIOD_SYS */ + timeout -= timeout % TICK_PERIOD_SYS; + } + /* This should wrap around */ + sys_write32(last_rtc_count + timeout, CC35XX_RTC_BASE + RTC_O_CH0CC1U); + } else { + sys_write32(last_rtc_count + RTC_TIMEOUT_MAX, + CC35XX_RTC_BASE + RTC_O_CH0CC1U); + } + k_spin_unlock(&lock, key); +} + +uint32_t sys_clock_elapsed(void) +{ + k_spinlock_key_t key = k_spin_lock(&lock); + /* Get current value as early as possible */ + uint32_t current_rtc_count = sys_read32(CC35XX_RTC_BASE + RTC_O_TIME1U); + + int32_t elapsed_ticks = sys_clock_elapsed_ticks(current_rtc_count, last_rtc_count); + + k_spin_unlock(&lock, key); + return elapsed_ticks; +} + +uint32_t sys_clock_cycle_get_32(void) +{ + return sys_read32(CC35XX_RTC_BASE + RTC_O_TIME1U); +} + +void sys_clock_idle_exit(void) +{ + /* + * PM resume can return with the RTC interrupt disabled after the TI + * sleep path manipulated NVIC state internally. Do not clear RTC/NVIC + * pending state here, as that can consume the wake event before the + * normal RTC ISR path handles it. + */ + irq_enable(INT_RTC_EVENT_IRQn); +} + +void rtc_isr(const void *arg) +{ + ARG_UNUSED(arg); + + /* Clear CH0 interrupt — RTC requires explicit clear unlike SYSTIM */ + sys_write32(RTC_ICLR_EV0_CLR, CC35XX_RTC_BASE + RTC_O_ICLR); + + k_spinlock_key_t key = k_spin_lock(&lock); + /* Get current value as early as possible */ + uint32_t current_rtc_count = sys_read32(CC35XX_RTC_BASE + RTC_O_TIME1U); + uint32_t elapsed_ticks = sys_clock_elapsed_ticks(current_rtc_count, last_rtc_count); + last_rtc_count = current_rtc_count; + k_spin_unlock(&lock, key); + sys_clock_announce(elapsed_ticks); + + + /* Do not re-arm RTC. Zephyr will do so through sys_clock_set_timeout */ +} + +static int sys_clock_driver_init(void) +{ + uint32_t nowTick; + + /* Get current value as early as possible */ + nowTick = sys_read32(CC35XX_RTC_BASE + RTC_O_TIME1U); + last_rtc_count = nowTick; + + /* Clear any pending interrupts on RTC channel 0 */ + sys_write32(RTC_ICLR_EV0_CLR, CC35XX_RTC_BASE + RTC_O_ICLR); + + /* Make RTC halt on CPU debug halt */ + sys_write32(RTC_EMU_HALT_STOP, CC35XX_RTC_BASE + RTC_O_EMU); + + /* + * Set IMASK for channel 0. IMASK is used by the power driver to know + * which RTC channels are active. + */ + sys_write32(RTC_IMSET_EV0_SET, CC35XX_RTC_BASE + RTC_O_IMSET); + + /* This should wrap around and set a maximum timeout */ + sys_write32(nowTick + RTC_TIMEOUT_MAX, CC35XX_RTC_BASE + RTC_O_CH0CC1U); + + /* Take RTC interrupt (CMSIS IRQn 49) */ + IRQ_CONNECT(INT_RTC_EVENT_IRQn, RTC_ISR_PRIORITY, rtc_isr, 0, 0); + irq_enable(INT_RTC_EVENT_IRQn); + + return 0; +} + +static uint32_t sys_clock_elapsed_ticks(uint32_t current, uint32_t last) +{ + if (current >= last) { + return (current / TICK_PERIOD_SYS) - (last / TICK_PERIOD_SYS); + } else { + return ((0xFFFFFFFF - last) / TICK_PERIOD_SYS) + + (current / TICK_PERIOD_SYS); + } +} + +SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2, CONFIG_SYSTEM_CLOCK_INIT_PRIORITY); From df30e9b9482bfd875bb1967ec6207ccba5508984 Mon Sep 17 00:00:00 2001 From: Jakub Jarosinski Date: Mon, 6 Jul 2026 15:23:15 +0200 Subject: [PATCH 041/100] UPSTREAM-PEND: boards: ti: lp_em_cc35x1: fix peripheral test wiring Add the board-specific overlays and configuration needed by peripheral runtime tests to match the CC35xx LaunchPad wiring. Signed-off-by: Jakub Jarosinski --- .../ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi | 1 + dts/arm/ti/cc35xxe.dtsi | 9 +++++++++ dts/bindings/counter/ti,cc35xx-lgpt.yaml | 19 +++++++++++++++++++ dts/bindings/rtc/ti,cc35xx-rtc-timer.yaml | 13 +++++++++++++ .../dt-bindings/pinctrl/ti-cc35xx-pinctrl.h | 2 ++ .../cc35xxe/Kconfig.defconfig.cc3551e | 9 +++++++-- .../pwm/pwm_api/boards/lp_em_cc35x1.overlay | 2 +- 7 files changed, 52 insertions(+), 3 deletions(-) create mode 100644 dts/bindings/counter/ti,cc35xx-lgpt.yaml create mode 100644 dts/bindings/rtc/ti,cc35xx-rtc-timer.yaml diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi index 0306b234b251..2a4446123ff3 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi @@ -63,6 +63,7 @@ led1 = &red_led; led2 = &blue_led; pwm-led0 = &green_pwm; + ambient-temp0 = &tmp1075_temperature; sw0 = &user_switch_1; sw1 = &user_switch_2; dma0 = &dma; diff --git a/dts/arm/ti/cc35xxe.dtsi b/dts/arm/ti/cc35xxe.dtsi index 9e764cf7644e..da8eef1d9432 100644 --- a/dts/arm/ti/cc35xxe.dtsi +++ b/dts/arm/ti/cc35xxe.dtsi @@ -21,6 +21,7 @@ #define INT_NON_SECURED_DMA_IRQ_EVT_IND_OUT 41 #define INT_HOST_ELP_TMR_WAKEUP_REQ 62 #define INT_NAB_HOST_IRQ 63 +#define INT_RTC_EVENT_IRQ 65 /* * Note: Zephyr uses exception numbers, vs the IRQ used by the CC32XX SDK * which are offset by 16: @@ -38,6 +39,7 @@ #define EXP_DMA_NS (INT_NON_SECURED_DMA_IRQ_EVT_IND_OUT - 16) #define EXP_NAB_HOST (INT_NAB_HOST_IRQ - 16) #define EXP_WDT (INT_HOST_ELP_TMR_WAKEUP_REQ - 16) +#define EXP_RTC (INT_RTC_EVENT_IRQ - 16) / { cpus { @@ -254,6 +256,13 @@ }; }; + rtc: rtc@41108000 { + compatible = "ti,cc35xx-rtc-timer"; + reg = <0x41108000 0x4000>; + interrupts = ; + status = "okay"; + }; + dma: dma@41a00000 { compatible = "ti,cc35xx-dma"; reg = <0x41a00000 0x10000>; diff --git a/dts/bindings/counter/ti,cc35xx-lgpt.yaml b/dts/bindings/counter/ti,cc35xx-lgpt.yaml new file mode 100644 index 000000000000..5153c7f1567e --- /dev/null +++ b/dts/bindings/counter/ti,cc35xx-lgpt.yaml @@ -0,0 +1,19 @@ +description: TI CC35XX LGPT counter driver + +compatible: "ti,cc35xx-lgpt" + +include: base.yaml + +properties: + interrupts: + required: true + + clk-prescale: + type: int + required: true + description: Counter clock prescale + + max-top-value: + type: int + required: true + description: Max allowed value for counter diff --git a/dts/bindings/rtc/ti,cc35xx-rtc-timer.yaml b/dts/bindings/rtc/ti,cc35xx-rtc-timer.yaml new file mode 100644 index 000000000000..571ec143ebfb --- /dev/null +++ b/dts/bindings/rtc/ti,cc35xx-rtc-timer.yaml @@ -0,0 +1,13 @@ +# Copyright (c) 2025 Conclusive Engineering Sp. z o.o. +# +# SPDX-License-Identifier: Apache-2.0 + +description: TI SimpleLink cc35xx RTC + +compatible: "ti,cc35xx-rtc-timer" + +include: rtc.yaml + +properties: + reg: + required: true diff --git a/include/zephyr/dt-bindings/pinctrl/ti-cc35xx-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/ti-cc35xx-pinctrl.h index 3a894b0d1d96..2903bdf4083b 100644 --- a/include/zephyr/dt-bindings/pinctrl/ti-cc35xx-pinctrl.h +++ b/include/zephyr/dt-bindings/pinctrl/ti-cc35xx-pinctrl.h @@ -100,6 +100,7 @@ #define P3_UART1_TX (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(3, 1)) #define P3_WIFI_GPIO_3 TI_CC35XX_PINMUX(3, 2) +#define P3_WIFI_AIN5 TI_CC35XX_ANALOG(3) #define P3_SDIO_MMC_WP TI_CC35XX_PINMUX(3, 3) #define P3_SPI1_CLK (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(3, 4)) #define P3_UART1_RTS (TI_CC35XX_PINCTRL_DIR_OUT | TI_CC35XX_PINMUX(3, 5)) @@ -124,6 +125,7 @@ #define P4_UART1_RX (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(4, 1)) #define P4_WIFI_GPIO_4 TI_CC35XX_PINMUX(4, 2) +#define P4_WIFI_AIN4 TI_CC35XX_ANALOG(4) #define P4_SDIO_MMC_CD TI_CC35XX_PINMUX(4, 3) #define P4_SPI1_CS1 TI_CC35XX_PINMUX(4, 4) #define P4_UART1_CTS (TI_CC35XX_PINCTRL_DIR_IN | TI_CC35XX_PINMUX(4, 5)) diff --git a/soc/ti/simplelink/cc35xxe/Kconfig.defconfig.cc3551e b/soc/ti/simplelink/cc35xxe/Kconfig.defconfig.cc3551e index 986af0268f1e..123bfbe4ceb3 100644 --- a/soc/ti/simplelink/cc35xxe/Kconfig.defconfig.cc3551e +++ b/soc/ti/simplelink/cc35xxe/Kconfig.defconfig.cc3551e @@ -6,7 +6,8 @@ if SOC_SERIES_CC35XXE config SYS_CLOCK_HW_CYCLES_PER_SEC int - default 160000000 + default 1000000 if CC35XX_RTC_TIMER + default 160000000 if !CC35XX_RTC_TIMER config SYS_CLOCK_TICKS_PER_SEC int @@ -14,7 +15,11 @@ config SYS_CLOCK_TICKS_PER_SEC config NUM_IRQS int - default 48 + default 53 + +config CORTEX_M_SYSTICK + default y if !CC35XX_RTC_TIMER + default n if CC35XX_RTC_TIMER config XIP bool diff --git a/tests/drivers/pwm/pwm_api/boards/lp_em_cc35x1.overlay b/tests/drivers/pwm/pwm_api/boards/lp_em_cc35x1.overlay index eeb7f1a45d0f..06215793f162 100644 --- a/tests/drivers/pwm/pwm_api/boards/lp_em_cc35x1.overlay +++ b/tests/drivers/pwm/pwm_api/boards/lp_em_cc35x1.overlay @@ -6,6 +6,6 @@ / { aliases { - pwm-0 = &pwm4; + pwm-test = &pwm4; }; }; From 5282a5c319157682904e9187daa865adafbdeac5 Mon Sep 17 00:00:00 2001 From: Jacek Ozimek Date: Wed, 3 Sep 2025 23:04:05 +0200 Subject: [PATCH 042/100] UPSTREAM-PEND: drivers: counter: cc35xx: Add counter support Implement support for the TI CC35xx General Purpose Timer peripheral. Signed-off-by: Jacek Ozimek Signed-off-by: Artur Rojek --- boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml | 1 + drivers/counter/CMakeLists.txt | 1 + drivers/counter/Kconfig | 2 + drivers/counter/Kconfig.cc35xx | 10 + drivers/counter/counter_cc35xx_lgpt.c | 257 ++++++++++++++++++ .../counter/alarm/boards/lp_em_cc35x1.overlay | 3 + samples/drivers/counter/alarm/sample.yaml | 1 + samples/drivers/counter/alarm/src/main.c | 2 + 8 files changed, 277 insertions(+) create mode 100644 drivers/counter/Kconfig.cc35xx create mode 100644 drivers/counter/counter_cc35xx_lgpt.c create mode 100644 samples/drivers/counter/alarm/boards/lp_em_cc35x1.overlay diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml b/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml index 478f16307368..eeb03d4aa7fc 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml @@ -8,6 +8,7 @@ toolchain: - zephyr - gnuarmemb supported: + - counter - gpio - pinctrl - serial diff --git a/drivers/counter/CMakeLists.txt b/drivers/counter/CMakeLists.txt index bc0a6522bcb9..c6abc97b9633 100644 --- a/drivers/counter/CMakeLists.txt +++ b/drivers/counter/CMakeLists.txt @@ -22,6 +22,7 @@ zephyr_library_sources_ifdef(CONFIG_COUNTER_BFLB_RTC counter_bflb_rtc.c) zephyr_library_sources_ifdef(CONFIG_COUNTER_BFLB_TIMER counter_bflb_timer.c) zephyr_library_sources_ifdef(CONFIG_COUNTER_CC23X0_LGPT counter_cc23x0_lgpt.c) zephyr_library_sources_ifdef(CONFIG_COUNTER_CC23X0_RTC counter_cc23x0_rtc.c) +zephyr_library_sources_ifdef(CONFIG_COUNTER_CC35XX_LGPT counter_cc35xx_lgpt.c) zephyr_library_sources_ifdef(CONFIG_COUNTER_CMOS counter_cmos.c) zephyr_library_sources_ifdef(CONFIG_COUNTER_GECKO_RTCC counter_gecko_rtcc.c) zephyr_library_sources_ifdef(CONFIG_COUNTER_GECKO_STIMER counter_gecko_stimer.c) diff --git a/drivers/counter/Kconfig b/drivers/counter/Kconfig index 9f1dcfe48dd4..b1b30dfeefaa 100644 --- a/drivers/counter/Kconfig +++ b/drivers/counter/Kconfig @@ -12,6 +12,7 @@ if COUNTER config COUNTER_INIT_PRIORITY int "Counter init priority" + default 40 if COUNTER_CC35XX_LGPT default KERNEL_INIT_PRIORITY_DEVICE help Counter driver device initialization priority. @@ -56,6 +57,7 @@ source "drivers/counter/Kconfig.bee_timer" source "drivers/counter/Kconfig.bflb" source "drivers/counter/Kconfig.cc23x0_lgpt" source "drivers/counter/Kconfig.cc23x0_rtc" +source "drivers/counter/Kconfig.cc35xx" source "drivers/counter/Kconfig.cmos" source "drivers/counter/Kconfig.dtmr_cmsdk_apb" source "drivers/counter/Kconfig.dw" diff --git a/drivers/counter/Kconfig.cc35xx b/drivers/counter/Kconfig.cc35xx new file mode 100644 index 000000000000..90f1cbd3407c --- /dev/null +++ b/drivers/counter/Kconfig.cc35xx @@ -0,0 +1,10 @@ +# Copyright (c) 2025 Conclusive Engineering Sp. z o.o. +# +# SPDX-License-Identifier: Apache-2.0 + +config COUNTER_CC35XX_LGPT + bool "TI CC35XX Counter Driver" + default y + depends on DT_HAS_TI_CC35XX_LGPT_ENABLED + help + Enables the Counter driver for TI CC35XX devices. diff --git a/drivers/counter/counter_cc35xx_lgpt.c b/drivers/counter/counter_cc35xx_lgpt.c new file mode 100644 index 000000000000..79137d4617b4 --- /dev/null +++ b/drivers/counter/counter_cc35xx_lgpt.c @@ -0,0 +1,257 @@ +/* + * Copyright (c) 2024 BayLibre, SAS + * Copyright (c) 2025 Conclusive Engineering Sp. z o.o. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT ti_cc35xx_lgpt + +#include +#include +#include +#include +#include + +#include +#include +#include + +#define TI_CC35XX_COUNTER_CHANNELS 4 +#define TI_CC35XX_CXCFG \ + (GPTIMER_C0CFG_EDGE_RISE | GPTIMER_C0CFG_INPUT_EV | GPTIMER_C0CFG_CCACT_TGL_ON_CMP) +#define TI_CC35XX_CHAN_DISABLE 0 +#define TI_CC35XX_CNTR_START 0x01 +#define TI_CC35XX_CNTR_STOP 0x00 + +#define GPTIMER_O_CXCC(index) (GPTIMER_O_C0CC + ((index) * 4)) +#define GPTIMER_O_CXCFG(index) (GPTIMER_O_C0CFG + ((index) * 4)) + +#define GPTIMER_IMCLR_CXCC_CLR(index) (GPTIMER_IMCLR_C0CC_CLR << (index)) +#define GPTIMER_IMSET_CXCC_SET(index) (GPTIMER_IMSET_C0CC_SET << (index)) + +struct counter_cc35xx_gptimer_config { + struct counter_config_info counter_info; + uint32_t base; + uint32_t prescale; + uint32_t freq; +}; + +struct counter_cc35xx_gptimer_data { + struct counter_alarm_cfg alarm_cfg[TI_CC35XX_COUNTER_CHANNELS]; + struct counter_top_cfg target_cfg; +}; + +static int counter_cc35xx_gptimer_get_value(const struct device *dev, uint32_t *ticks) +{ + const struct counter_cc35xx_gptimer_config *config = dev->config; + + *ticks = sys_read32(config->base + GPTIMER_O_CNTR); + + return 0; +} + +static void counter_cc35xx_gptimer_isr(const struct device *dev) +{ + const struct counter_cc35xx_gptimer_config *config = dev->config; + const struct counter_cc35xx_gptimer_data *data = dev->data; + uint32_t counter = sys_read32(config->base + GPTIMER_O_CNTR); + uint32_t reg_ris = sys_read32(config->base + GPTIMER_O_RIS); + uint32_t reg_mis = sys_read32(config->base + GPTIMER_O_MIS); + int i; + + sys_write32(reg_ris, config->base + GPTIMER_O_ICLR); + sys_write32(reg_mis, config->base + GPTIMER_O_IMCLR); + + if ((reg_mis & GPTIMER_MIS_TGT) && data->target_cfg.callback) { + data->target_cfg.callback(dev, data->target_cfg.user_data); + } + + for (i = 0; i < TI_CC35XX_COUNTER_CHANNELS; i++) { + if ((reg_mis & GPTIMER_MIS_C0CC << i) && data->alarm_cfg[i].callback) { + data->alarm_cfg[i].callback(dev, i, counter, + data->alarm_cfg[i].user_data); + } + } +} + +static uint32_t counter_cc35xx_gptimer_get_freq(const struct device *dev) +{ + const struct counter_cc35xx_gptimer_config *config = dev->config; + + /* Timer frequency, per SWRU626_TRM, p. 921: [TICKSRC]/([TICKDIV]+1) */ + return (config->freq / (config->prescale + 1)); +} + +static int counter_cc35xx_gptimer_set_alarm(const struct device *dev, uint8_t chan_id, + const struct counter_alarm_cfg *alarm_cfg) +{ + const struct counter_cc35xx_gptimer_config *config = dev->config; + struct counter_cc35xx_gptimer_data *data = dev->data; + uint32_t ticks = alarm_cfg->ticks; + + if (chan_id >= TI_CC35XX_COUNTER_CHANNELS) { + return -EINVAL; + } + + /* + * Capture compare register always compares against the absolute value + * of the counter register. + * In order to handle alarms relative to the current counter value, + * increment the ticks appropriately. + */ + if (!(alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE)) { + ticks += sys_read32(config->base + GPTIMER_O_CNTR); + } + + if (ticks > config->counter_info.max_top_value) { + return -ERANGE; + } + + sys_write32(GPTIMER_IMSET_CXCC_SET(chan_id), config->base + GPTIMER_O_IMSET); + sys_write32(ticks, config->base + GPTIMER_O_CXCC(chan_id)); + sys_write32(TI_CC35XX_CXCFG, config->base + GPTIMER_O_CXCFG(chan_id)); + + data->alarm_cfg[chan_id].flags = alarm_cfg->flags; + data->alarm_cfg[chan_id].ticks = alarm_cfg->ticks; + data->alarm_cfg[chan_id].callback = alarm_cfg->callback; + data->alarm_cfg[chan_id].user_data = alarm_cfg->user_data; + + return 0; +} + +static int counter_cc35xx_gptimer_cancel_alarm(const struct device *dev, uint8_t chan_id) +{ + const struct counter_cc35xx_gptimer_config *config = dev->config; + struct counter_cc35xx_gptimer_data *data = dev->data; + + if (chan_id >= TI_CC35XX_COUNTER_CHANNELS) { + return -EINVAL; + } + + sys_write32(GPTIMER_IMCLR_CXCC_CLR(chan_id), config->base + GPTIMER_O_IMCLR); + sys_write32(TI_CC35XX_CHAN_DISABLE, config->base + GPTIMER_O_CXCC(chan_id)); + sys_write32(TI_CC35XX_CHAN_DISABLE, config->base + GPTIMER_O_CXCFG(chan_id)); + + data->alarm_cfg[chan_id].flags = 0; + data->alarm_cfg[chan_id].ticks = 0; + data->alarm_cfg[chan_id].callback = NULL; + data->alarm_cfg[chan_id].user_data = NULL; + + return 0; +} + +static uint32_t counter_cc35xx_gptimer_get_top_value(const struct device *dev) +{ + const struct counter_cc35xx_gptimer_config *config = dev->config; + + return sys_read32(config->base + GPTIMER_O_TGTNC); +} + +static int counter_cc35xx_gptimer_set_top_value(const struct device *dev, + const struct counter_top_cfg *cfg) +{ + const struct counter_cc35xx_gptimer_config *config = dev->config; + struct counter_cc35xx_gptimer_data *data = dev->data; + + /* If running return -EBUSY */ + if (sys_read32(config->base + GPTIMER_O_STARTCFG)) { + return -EBUSY; + } + + if (cfg->ticks > config->counter_info.max_top_value) { + return -EINVAL; + } + + if (cfg->flags & COUNTER_TOP_CFG_DONT_RESET) { + return -ENOTSUP; + } + + sys_write32(GPTIMER_IMSET_TGT_SET, config->base + GPTIMER_O_IMSET); + sys_write32(cfg->ticks, config->base + GPTIMER_O_TGT); + + data->target_cfg.flags = 0; + data->target_cfg.ticks = cfg->ticks; + data->target_cfg.callback = cfg->callback; + data->target_cfg.user_data = cfg->user_data; + + return 0; +} + +static uint32_t counter_cc35xx_gptimer_get_pending_int(const struct device *dev) +{ + const struct counter_cc35xx_gptimer_config *config = dev->config; + + return !!sys_read32(config->base + GPTIMER_O_MIS); +} + +static int counter_cc35xx_gptimer_start(const struct device *dev) +{ + const struct counter_cc35xx_gptimer_config *config = dev->config; + uint32_t reg = sys_read32(config->base + GPTIMER_O_CTL); + + /* Zephyr uses single-shot alarms. */ + sys_write32(reg | GPTIMER_CTL_MODE_UP_ONCE, config->base + GPTIMER_O_CTL); + + sys_write32(TI_CC35XX_CNTR_START, config->base + GPTIMER_O_STARTCFG); + + return 0; +} + +static int counter_cc35xx_gptimer_stop(const struct device *dev) +{ + const struct counter_cc35xx_gptimer_config *config = dev->config; + + sys_write32(TI_CC35XX_CNTR_STOP, config->base + GPTIMER_O_STARTCFG); + + return 0; +} + +static const struct counter_driver_api cc35xx_counter_api = { + .start = counter_cc35xx_gptimer_start, + .stop = counter_cc35xx_gptimer_stop, + .get_value = counter_cc35xx_gptimer_get_value, + .set_alarm = counter_cc35xx_gptimer_set_alarm, + .cancel_alarm = counter_cc35xx_gptimer_cancel_alarm, + .get_top_value = counter_cc35xx_gptimer_get_top_value, + .set_top_value = counter_cc35xx_gptimer_set_top_value, + .get_pending_int = counter_cc35xx_gptimer_get_pending_int, + .get_freq = counter_cc35xx_gptimer_get_freq, +}; + +#define GPTIMER_CLK_PRESCALE(pres) ((pres) << 8) + +#define COUNTER_CC35XX_INIT_FUNC(inst) \ + static int counter_cc35xx_init_##inst(const struct device *dev) \ + { \ + const struct counter_cc35xx_gptimer_config *config = dev->config; \ + sys_write32(GPTIMER_CLKCFG_ENABLE, config->base + GPTIMER_O_CLKCFG); \ + sys_write32(GPTIMER_CTL_CMPDIR_BOTH | GPTIMER_EMU_HALT_EN, \ + config->base + GPTIMER_O_CTL); \ + IRQ_CONNECT(DT_INST_IRQN(inst), DT_INST_IRQ(inst, priority), \ + counter_cc35xx_gptimer_isr, DEVICE_DT_INST_GET(inst), 0); \ + irq_enable(DT_INST_IRQN(inst)); \ + sys_write32(config->counter_info.max_top_value, config->base + GPTIMER_O_TGT); \ + sys_write32(GPTIMER_CLK_PRESCALE(config->prescale), \ + config->base + GPTIMER_O_PRECFG); \ + return 0; \ + } + +#define COUNTER_CC35XX_INIT(inst) \ + COUNTER_CC35XX_INIT_FUNC(inst); \ + static const struct counter_cc35xx_gptimer_config cc35xx_counter_config_##inst = { \ + .counter_info = { \ + .max_top_value = DT_INST_PROP(inst, max_top_value), \ + .flags = COUNTER_CONFIG_INFO_COUNT_UP, \ + .channels = TI_CC35XX_COUNTER_CHANNELS, \ + }, \ + .base = DT_INST_REG_ADDR(inst), \ + .prescale = DT_INST_PROP(inst, clk_prescale), \ + .freq = DT_INST_PROP_BY_PHANDLE(inst, clocks, clock_frequency) \ + }; \ + static struct counter_cc35xx_gptimer_data cc35xx_counter_data_##inst; \ + DEVICE_DT_INST_DEFINE(inst, &counter_cc35xx_init_##inst, NULL, \ + &cc35xx_counter_data_##inst, &cc35xx_counter_config_##inst, \ + POST_KERNEL, CONFIG_COUNTER_INIT_PRIORITY, &cc35xx_counter_api); + +DT_INST_FOREACH_STATUS_OKAY(COUNTER_CC35XX_INIT); diff --git a/samples/drivers/counter/alarm/boards/lp_em_cc35x1.overlay b/samples/drivers/counter/alarm/boards/lp_em_cc35x1.overlay new file mode 100644 index 000000000000..241947b06437 --- /dev/null +++ b/samples/drivers/counter/alarm/boards/lp_em_cc35x1.overlay @@ -0,0 +1,3 @@ +&timer0 { + status = "okay"; +}; diff --git a/samples/drivers/counter/alarm/sample.yaml b/samples/drivers/counter/alarm/sample.yaml index 59b0ca18d83d..4d1cdd0d7137 100644 --- a/samples/drivers/counter/alarm/sample.yaml +++ b/samples/drivers/counter/alarm/sample.yaml @@ -57,6 +57,7 @@ tests: - xg24_rb4187c - xg27_rb4194a - xg29_rb4412a + - lp_em_cc35x1 integration_platforms: - nucleo_f746zg sample.drivers.counter.alarm.stm32_rtc: diff --git a/samples/drivers/counter/alarm/src/main.c b/samples/drivers/counter/alarm/src/main.c index ded53d5631db..a421d751dcfc 100644 --- a/samples/drivers/counter/alarm/src/main.c +++ b/samples/drivers/counter/alarm/src/main.c @@ -72,6 +72,8 @@ struct counter_alarm_cfg alarm_cfg; #define SAMPLE_TIMER DT_INST(0, renesas_rz_gtm_counter) #elif defined(CONFIG_COUNTER_CC23X0_RTC) #define SAMPLE_TIMER DT_NODELABEL(rtc0) +#elif defined(CONFIG_COUNTER_CC35XX_LGPT) +#define SAMPLE_TIMER DT_NODELABEL(timer0) #elif defined(CONFIG_COUNTER_RENESAS_RZ_CMTW) #define SAMPLE_TIMER DT_INST(0, renesas_rz_cmtw_counter) #elif defined(CONFIG_COUNTER_MCHP_SAM_PIT64B) From fe0e2c99d14d2bf4c71577d776ac62480a315645 Mon Sep 17 00:00:00 2001 From: Jacek Ozimek Date: Wed, 10 Sep 2025 12:06:19 +0200 Subject: [PATCH 043/100] UPSTREAM-PEND: drivers: rtc: cc35xxe: Add support for RTC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add RTC support for CC35xxE Signed-off-by: Jacek Ozimek Signed-off-by: Michał Łyszczek --- boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml | 3 +- .../ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi | 2 + drivers/rtc/CMakeLists.txt | 1 + drivers/rtc/Kconfig | 1 + drivers/rtc/Kconfig.cc35xx | 16 ++ drivers/rtc/rtc_cc35xx.c | 191 ++++++++++++++++++ 6 files changed, 213 insertions(+), 1 deletion(-) create mode 100644 drivers/rtc/Kconfig.cc35xx create mode 100644 drivers/rtc/rtc_cc35xx.c diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml b/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml index eeb03d4aa7fc..e13be29d65af 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml @@ -11,6 +11,7 @@ supported: - counter - gpio - pinctrl - - serial - pwm + - rtc + - serial vendor: ti diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi index 2a4446123ff3..14c5b0f146fb 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi @@ -25,6 +25,7 @@ zephyr,code-partition = &dmem_ns; zephyr,console = &uart1; zephyr,shell-uart = &uart1; + zephyr,rtc = &rtc; }; leds { @@ -67,6 +68,7 @@ sw0 = &user_switch_1; sw1 = &user_switch_2; dma0 = &dma; + rtc = &rtc; }; }; diff --git a/drivers/rtc/CMakeLists.txt b/drivers/rtc/CMakeLists.txt index 624d90767c24..cbbb3bd71273 100644 --- a/drivers/rtc/CMakeLists.txt +++ b/drivers/rtc/CMakeLists.txt @@ -45,6 +45,7 @@ zephyr_library_sources_ifdef(CONFIG_RTC_SF32LB rtc_sf32lb.c) zephyr_library_sources_ifdef(CONFIG_RTC_SILABS_SIWX91X rtc_silabs_siwx91x.c) zephyr_library_sources_ifdef(CONFIG_RTC_SMARTBOND rtc_smartbond.c) zephyr_library_sources_ifdef(CONFIG_RTC_STM32 rtc_stm32.c) +zephyr_library_sources_ifdef(CONFIG_RTC_TI_CC35XX rtc_cc35xx.c) zephyr_library_sources_ifdef(CONFIG_RTC_TI_MSPM0 rtc_ti_mspm0.c) zephyr_library_sources_ifdef(CONFIG_RTC_XMC4XXX rtc_xmc4xxx.c) # zephyr-keep-sorted-stop diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index f9c6e351ea83..81f753010294 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -45,6 +45,7 @@ config RTC_SHELL source "drivers/rtc/Kconfig.am1805" source "drivers/rtc/Kconfig.ambiq" source "drivers/rtc/Kconfig.bq32002" +source "drivers/rtc/Kconfig.cc35xx" source "drivers/rtc/Kconfig.counter" source "drivers/rtc/Kconfig.ds1302" source "drivers/rtc/Kconfig.ds1307" diff --git a/drivers/rtc/Kconfig.cc35xx b/drivers/rtc/Kconfig.cc35xx new file mode 100644 index 000000000000..3a8f1d7092f3 --- /dev/null +++ b/drivers/rtc/Kconfig.cc35xx @@ -0,0 +1,16 @@ +# Copyright (c) 2025 Conclusive Engineering Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +config RTC_TI_CC35XX + bool "TI Simplelink cc35xx RTC driver" + default y + depends on DT_HAS_TI_CC35XX_RTC_TIMER_ENABLED + help + TI Simplelink cc35xx Real-Time Clock (RTC) driver. + +config RTC_TI_CC35XX_EPOCH_YEAR + int "Epoch year for TI cc35xx RTC" + default 2020 + depends on RTC_TI_CC35XX + help + TI Simplelink cc35xx RTC driver epoch year. diff --git a/drivers/rtc/rtc_cc35xx.c b/drivers/rtc/rtc_cc35xx.c new file mode 100644 index 000000000000..60d232c42e5b --- /dev/null +++ b/drivers/rtc/rtc_cc35xx.c @@ -0,0 +1,191 @@ +/* + * Copyright (c) 2025 Conclusive Engineering Sp. z o.o. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT ti_cc35xx_rtc_timer + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include "rtc_utils.h" + +#define RTC_TI_CC35XX_STEP_MASK (0x7FFFFFFF) +#define RTC_TI_CC35XX_HIGH_RES_RANGE_US (134LL * USEC_PER_SEC) +#define RTC_TI_CC35XX_HIGH_RES_STEP_SHIFT (2) +#define RTC_TI_CC35XX_LOW_RES_STEP_SHIFT (20) +#define RTC_TI_CC35XX_DTIME_EXP (1 << 31) + +#define RTC_TI_CC35XX_EPOCH_YEAR (CONFIG_RTC_TI_CC35XX_EPOCH_YEAR - 1900) + +#define RTC_TI_CC35XX_TOP_19_BITS_MASK 0xFFFFE000 + +struct rtc_ti_cc35xx_data { + struct k_spinlock lock; +}; + +static inline int64_t rtc_bias_1970_to_xxxx(int reduced_year) +{ + struct tm t = { + .tm_year = reduced_year, + .tm_mon = 0, + .tm_mday = 1, + .tm_hour = 0, + .tm_min = 0, + .tm_sec = 0, + .tm_isdst = 0, + }; + return timeutil_timegm64(&t); +} + +static int rtc_ti_cc35xx_init(const struct device *dev) +{ + /* Configure RTC to halt when CPU stopped during debug */ + sys_write32(RTC_EMU_HALT_STOP, RTC_BASE + RTC_O_EMU); + return 0; +} + +static uint64_t rtc_ti_cc35xx_get_raw_time(struct rtc_ti_cc35xx_data *data) +{ + k_spinlock_key_t key; + uint64_t usec; + uint32_t time524m; + uint32_t time1u; + + key = k_spin_lock(&data->lock); + + while (true) { + time1u = sys_read32(RTC_BASE + RTC_O_TIME1U); + time524m = sys_read32(RTC_BASE + RTC_O_TIME524M); + /* + * Check if TIME1U wrapped around. + * In such case read time again to get correct + * concatenated value. + */ + if ((time1u >> 31) == 1) { + if ((sys_read32(RTC_BASE + RTC_O_TIME1U) >> 31) == 0) { + continue; + } + } + break; + } + + usec = (uint64_t)(time524m & RTC_TI_CC35XX_TOP_19_BITS_MASK) << 19; + usec |= time1u; + k_spin_unlock(&data->lock, key); + + return usec; +} + +static void rtc_ti_cc35xx_set_dtime(struct rtc_ti_cc35xx_data *data, int64_t delta_us) +{ + k_spinlock_key_t key; + uint32_t raw_data; + + if (IN_RANGE(delta_us, -RTC_TI_CC35XX_HIGH_RES_RANGE_US, + RTC_TI_CC35XX_HIGH_RES_RANGE_US - 1)) { + raw_data = (uint32_t)((delta_us << RTC_TI_CC35XX_HIGH_RES_STEP_SHIFT) & + RTC_TI_CC35XX_STEP_MASK); + } else { + raw_data = RTC_TI_CC35XX_DTIME_EXP; + raw_data |= (uint32_t)((delta_us >> RTC_TI_CC35XX_LOW_RES_STEP_SHIFT) & + RTC_TI_CC35XX_STEP_MASK); + } + + key = k_spin_lock(&data->lock); + + sys_write32(raw_data, RTC_BASE + RTC_O_DTIME); + + /* Set SYNCUP bit to synchronize RTC with system timer */ + sys_write32(SYSTIM_STA_SYNCUP_SET, SYSTIM_BASE + SYSTIM_O_STA); + /* + * Waiting for SYNCUP bit to be cleared which indicated lftick. + * This should not take more than one Slow Clock period. + */ + while (sys_read32(SYSTIM_BASE + SYSTIM_O_STA) != SYSTIM_STA_VAL_RUN) { + } + k_spin_unlock(&data->lock, key); +} + +static int rtc_ti_cc35xx_set_time(const struct device *dev, const struct rtc_time *timeptr) +{ + struct rtc_ti_cc35xx_data *data = dev->data; + int64_t sec_unix_target; + int64_t sec_hw_target; + int64_t usec_hw_target; + uint64_t usec_hw_time; + uint64_t sec_bias; + int64_t delta_us; + + if (!timeptr || (timeptr->tm_year < RTC_TI_CC35XX_EPOCH_YEAR)) { + return -EINVAL; + } + + sec_unix_target = timeutil_timegm64((const struct tm *)timeptr); + if (sec_unix_target > INT64_MAX / USEC_PER_SEC) { + return -ERANGE; + } + + sec_bias = (uint64_t)rtc_bias_1970_to_xxxx(RTC_TI_CC35XX_EPOCH_YEAR); + sec_hw_target = sec_unix_target - sec_bias; + usec_hw_target = sec_hw_target * USEC_PER_SEC; + /* + * This function is for setting time using low resolution (1.049s) + * so truncate anything smaller to avoid rounding issues. + */ + usec_hw_time = (rtc_ti_cc35xx_get_raw_time(data) / USEC_PER_SEC) * USEC_PER_SEC; + + delta_us = usec_hw_target - usec_hw_time; + + rtc_ti_cc35xx_set_dtime(data, delta_us); + + return 0; +} + +static int rtc_ti_cc35xx_get_time(const struct device *dev, struct rtc_time *timeptr) +{ + struct rtc_ti_cc35xx_data *data = dev->data; + uint64_t sec_hw_time; + uint64_t usec_hw_time; + uint64_t sec_unix_time; + uint64_t sec_bias; + + usec_hw_time = rtc_ti_cc35xx_get_raw_time(data); + sec_hw_time = usec_hw_time / USEC_PER_SEC; + sec_bias = (uint64_t)rtc_bias_1970_to_xxxx(RTC_TI_CC35XX_EPOCH_YEAR); + sec_unix_time = sec_hw_time + sec_bias; + + gmtime_r(&sec_unix_time, (struct tm *)timeptr); + + /* Unsupported */ + timeptr->tm_isdst = -1; + /* Unsupported */ + timeptr->tm_nsec = 0; + + return 0; +} + +static const struct rtc_driver_api rtc_ti_cc35xx_driver_api = { + .set_time = rtc_ti_cc35xx_set_time, + .get_time = rtc_ti_cc35xx_get_time, +}; + +#define RTC_TI_CC35XX_DEVICE(id) \ + static struct rtc_ti_cc35xx_data rtc_ti_cc35xx_data_##id; \ + \ + DEVICE_DT_INST_DEFINE(id, rtc_ti_cc35xx_init, NULL, &rtc_ti_cc35xx_data_##id, NULL, \ + POST_KERNEL, CONFIG_RTC_INIT_PRIORITY, &rtc_ti_cc35xx_driver_api); + +DT_INST_FOREACH_STATUS_OKAY(RTC_TI_CC35XX_DEVICE); From 68199e3ecaa05419abc24c19800c826083799115 Mon Sep 17 00:00:00 2001 From: Jacek Ozimek Date: Tue, 8 Jul 2025 17:26:09 +0200 Subject: [PATCH 044/100] UPSTREAM-PEND: drivers: entropy: cc35xxe: initial support for TI HSM MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a new HSM (entropy) driver based on the TI Simplelink SDK Signed-off-by: Jacek Ozimek Signed-off-by: Michał Łyszczek --- boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml | 1 + .../ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi | 5 + drivers/entropy/CMakeLists.txt | 1 + drivers/entropy/Kconfig | 1 + drivers/entropy/Kconfig.cc35xx | 31 ++ drivers/entropy/entropy_cc35xx.c | 381 ++++++++++++++++++ dts/arm/ti/cc35xxe.dtsi | 9 +- dts/bindings/rng/ti,cc35xx-hsm.yaml | 8 + 8 files changed, 436 insertions(+), 1 deletion(-) create mode 100644 drivers/entropy/Kconfig.cc35xx create mode 100644 drivers/entropy/entropy_cc35xx.c create mode 100644 dts/bindings/rng/ti,cc35xx-hsm.yaml diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml b/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml index e13be29d65af..b0ddfda26d63 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml @@ -9,6 +9,7 @@ toolchain: - gnuarmemb supported: - counter + - entropy - gpio - pinctrl - pwm diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi index 14c5b0f146fb..2cb628b26203 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi @@ -26,6 +26,7 @@ zephyr,console = &uart1; zephyr,shell-uart = &uart1; zephyr,rtc = &rtc; + zephyr,entropy = &hsm; }; leds { @@ -221,3 +222,7 @@ pinctrl-names = "default"; status = "okay"; }; + +&hsm { + status = "okay"; +}; diff --git a/drivers/entropy/CMakeLists.txt b/drivers/entropy/CMakeLists.txt index f074a0fc77c7..952b1e7b776a 100644 --- a/drivers/entropy/CMakeLists.txt +++ b/drivers/entropy/CMakeLists.txt @@ -17,6 +17,7 @@ zephyr_library_sources_ifdef(CONFIG_ENTROPY_BFLB_SEC_ENG entropy_bflb_sec_eng.c) zephyr_library_sources_ifdef(CONFIG_ENTROPY_BRCM_IPROC_RNG200 entropy_iproc_rng200.c) zephyr_library_sources_ifdef(CONFIG_ENTROPY_BT_HCI entropy_bt_hci.c) zephyr_library_sources_ifdef(CONFIG_ENTROPY_CC13XX_CC26XX_RNG entropy_cc13xx_cc26xx.c) +zephyr_library_sources_ifdef(CONFIG_ENTROPY_CC35XX_RNG entropy_cc35xx.c) zephyr_library_sources_ifdef(CONFIG_ENTROPY_ESP32_RNG entropy_esp32.c) zephyr_library_sources_ifdef(CONFIG_ENTROPY_GD32_TRNG entropy_gd32.c) zephyr_library_sources_ifdef(CONFIG_ENTROPY_GECKO_SE entropy_gecko_se.c) diff --git a/drivers/entropy/Kconfig b/drivers/entropy/Kconfig index 16d9f54191af..0ffef559634f 100644 --- a/drivers/entropy/Kconfig +++ b/drivers/entropy/Kconfig @@ -26,6 +26,7 @@ source "drivers/entropy/Kconfig.b91" source "drivers/entropy/Kconfig.bflb" source "drivers/entropy/Kconfig.bt_hci" source "drivers/entropy/Kconfig.cc13xx_cc26xx" +source "drivers/entropy/Kconfig.cc35xx" source "drivers/entropy/Kconfig.esp32" source "drivers/entropy/Kconfig.gd32" source "drivers/entropy/Kconfig.gecko" diff --git a/drivers/entropy/Kconfig.cc35xx b/drivers/entropy/Kconfig.cc35xx new file mode 100644 index 000000000000..912b98cb7bdf --- /dev/null +++ b/drivers/entropy/Kconfig.cc35xx @@ -0,0 +1,31 @@ +# TI CC35xxE entropy driver configuration + +# Copyright (c) 2025 Conclusive Engineering Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +config ENTROPY_CC35XX_RNG + bool "TI SimpleLink CC35xxE Hardware Security Module (HSM)" + default y + depends on DT_HAS_TI_CC35XX_HSM_ENABLED + select TI_CC35XX_HSM + select ENTROPY_HAS_DRIVER + select RING_BUFFER + help + This option enables the driver for the Hardware Security Module (HSM) + for TI SimpleLink CC35xxE SoCs. + +config TI_CC35XX_HSM + bool + depends on DT_HAS_TI_CC35XX_HSM_ENABLED + +if ENTROPY_CC35XX_RNG + +config ENTROPY_CC35XX_POOL_SIZE + int "Number of bytes in the entropy pool" + default 512 + range 256 65536 + help + The size in bytes of the buffer used to store entropy generated by the + hardware. Should be a power of two for high performance. + +endif # ENTROPY_CC35XX_RNG diff --git a/drivers/entropy/entropy_cc35xx.c b/drivers/entropy/entropy_cc35xx.c new file mode 100644 index 000000000000..2161f0b08d0f --- /dev/null +++ b/drivers/entropy/entropy_cc35xx.c @@ -0,0 +1,381 @@ +/* + * Copyright (c) 2025 Conclusive Engineering Sp. z o.o. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT ti_cc35xx_hsm + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define SYSTEMINFO_TOKEN_WORD0 0x0F030000 +#define CRYPTO_OFFICER_ID 0x4F5A3647 +#define OUTPUT_TOKEN_ERROR 0x80000000 +#define HSM_TRNG_RAW_KEY_ENC 0x5244 +#define HSM_O_UNLOCK_CPUID0_CPUID1 0xFFFFFCFC +#define HSM_O_CPUID0_MB1_MB2_UNLOCK 0xFFFFFF77 + +#define HSMCRYPTO_BASE HSM_BASE +#define HSMCRYPTO_O_MBSTA HSM_O_MBXSTA +#define HSMCRYPTO_MBSTA_MB1IN_M HSM_MBXSTA_INFULL1 +#define HSMCRYPTO_MBSTA_MB1IN_FULL HSM_MBXSTA_INFULL1 +#define HSMCRYPTO_O_MB1IN HSM_O_EIP130_072_MAILBOX1_IN +#define HSMCRYPTO_O_MBCTL HSM_O_MBXCTL +#define HSMCRYPTO_MBCTL_MB1IN_FULL HSM_MBXCTL_INFULL1 +#define HSMCRYPTO_MBCTL_MB1LNK_LNK HSM_MBXCTL_LINK1 +#define HSMCRYPTO_O_MBLNKID HSM_O_MBXLINKID +#define HSMCRYPTO_O_MBLCKOUT HSM_O_MBXLCKOUT +#define HSMCRYPTO_MBSTA_MB1OUT_M HSM_MBXSTA_OUTFULL1 +#define HSMCRYPTO_MBSTA_MB1OUT_FULL HSM_MBXSTA_OUTFULL1 +#define HSMCRYPTO_O_MB1OUT HSM_O_EIP130_072_MAILBOX1_IN +#define HSMCRYPTO_MBCTL_MB1OUT_EMTY HSM_MBXCTL_OUTEMP1 + +#define HSMLPF3_STATUS_SUCCESS ((int_fast16_t)0) +#define HSMLPF3_STATUS_ERROR ((int_fast16_t)-1) +#define HSM_RAW_RNG_BLOCK_SIZE (256U) +#define HSM_BUFFER_SIZE HSM_RAW_RNG_BLOCK_SIZE +#define HSM_RAW_RNG_BLOCK_NUM (HSM_BUFFER_SIZE / HSM_RAW_RNG_BLOCK_SIZE) + +/* Adjusted experimentally */ +#define HSM_OPERATION_RETRIES 10 +#define HSM_WAIT_FOR_RESULT_RETRIES 10 +#define HSM_OPERATION_SEM_TIMEOUT_MS 10 + +struct entropy_cc35xx_hsm { + struct k_sem operation; + uint32_t retries; + uint8_t buffer[HSM_BUFFER_SIZE]; +}; + +struct entropy_cc35xx_data { + struct k_sem pool_lock; + struct k_work trng_work; + struct entropy_cc35xx_hsm hsm; + struct ring_buf pool; + uint8_t buffer[CONFIG_ENTROPY_CC35XX_POOL_SIZE]; +}; + +static inline int entropy_cc35xx_read_hsm_result(void) +{ + Eip130Token_Result_t result_token; + uint8_t mailbox_number; + + mailbox_number = HSMSAL_GetMailBoxNumber(); + return (HSMSAL_ScanAndReadMailbox(&result_token, mailbox_number) == HSMSAL_SUCCESS) ? 0 + : -EIO; +} + +static inline int entropy_cc35xx_wait_for_hsm(void) +{ + for (int i = 0; i < HSM_WAIT_FOR_RESULT_RETRIES; ++i) { + if (!entropy_cc35xx_read_hsm_result()) { + return 0; + } + } + + return -ETIMEDOUT; +} + +static void entropy_cc35xx_hsm_init_aic(void) +{ + Device_Handle_t gl_aic = Device_Find("EIP130_AIC"); + + if (gl_aic != NULL) { + /* + * Configure all sources for edge detect. Future improvement + * is to only enable the interrupts we need. We could also + * use EIP201_Config_Change(), but there is no adapter function() + */ + EIP201_SourceSettings_t settings = { + .Source = 0xFF, + .Config = EIP201_CONFIG_RISING_EDGE, + .fEnable = false /* enable source only when active */ + }; + EIP201_Initialize(gl_aic, &settings, 1); + } +} + +static inline void entropy_cc35xx_kick_trng_config(struct entropy_cc35xx_data *data) +{ + uintptr_t key; + Eip130Token_Command_t command_token; + + data->hsm.retries = 0; + + memset(&command_token, 0, sizeof(command_token)); + + Eip130Token_Command_RandomNumber_Generate(&command_token, HSM_RAW_RNG_BLOCK_NUM, + (uintptr_t)data->hsm.buffer); + Eip130Token_Command_RandomNumber_SetRawKey(&command_token, HSM_TRNG_RAW_KEY_ENC); + + key = irq_lock(); + HSMSAL_SubmitPhysicalToken(&command_token); + irq_unlock(key); +} + +static void entropy_cc35xx_kick_trng(struct entropy_cc35xx_data *data) +{ + if (ring_buf_space_get(&data->pool) == 0) { + /* Ring buffer is full. Refill not needed so far */ + return; + } + + if (data->hsm.retries++ >= HSM_OPERATION_RETRIES) { + /* HSM recovering */ + NVIC_ClearPendingIRQ(DT_INST_IRQN(0)); + irq_disable(DT_INST_IRQN(0)); + entropy_cc35xx_wait_for_hsm(); + k_sem_give(&data->hsm.operation); + } else if (k_sem_take(&data->hsm.operation, K_MSEC(HSM_OPERATION_SEM_TIMEOUT_MS)) != 0) { + return; + } + + entropy_cc35xx_kick_trng_config(data); + + irq_enable(DT_INST_IRQN(0)); +} + +static void entropy_cc35xx_trng_work_handler(struct k_work *work) +{ + struct entropy_cc35xx_data *data = + CONTAINER_OF(work, struct entropy_cc35xx_data, trng_work); + entropy_cc35xx_kick_trng(data); +} + +static int entropy_cc35xx_get_entropy(const struct device *dev, uint8_t *buf, uint16_t len) +{ + struct entropy_cc35xx_data *data = dev->data; + uint32_t cnt; + + if (len == 0 || len > sizeof(data->buffer)) { + return -EINVAL; + } + + entropy_cc35xx_kick_trng(data); + + while (len) { + k_sem_take(&data->pool_lock, K_FOREVER); + cnt = ring_buf_get(&data->pool, buf, len); + k_sem_give(&data->pool_lock); + + entropy_cc35xx_kick_trng(data); + + buf += cnt; + len -= cnt; + } + + return 0; +} + +static void entropy_cc35xx_isr(const struct device *dev) +{ + struct entropy_cc35xx_data *data = dev->data; + + NVIC_ClearPendingIRQ(DT_INST_IRQN(0)); + irq_disable(DT_INST_IRQN(0)); + + entropy_cc35xx_read_hsm_result(); + + ring_buf_put(&data->pool, data->hsm.buffer, sizeof(data->hsm.buffer)); + k_sem_give(&data->hsm.operation); + + k_work_submit(&data->trng_work); +} + +static int entropy_cc35xx_init(const struct device *dev) +{ + struct entropy_cc35xx_data *data = dev->data; + + uint32_t result = HSMLPF3_STATUS_ERROR; + uint32_t token[] = {SYSTEMINFO_TOKEN_WORD0, CRYPTO_OFFICER_ID}; + const uint32_t hsm_clk_enable = HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_EN | + HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_EN | + HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_EN | + HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_M3_EN | + HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_M3_EN | + HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_M3_EN; + const uint32_t hsm_clk_mask = HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_M | + HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_M | + HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_M | + HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_M3_M | + HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_M3_M | + HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_M3_M; + + uint32_t idx, hsm_status, hsm_reg_value; + uintptr_t key, hsm_reg_addr; + + k_work_init(&data->trng_work, entropy_cc35xx_trng_work_handler); + + /* Initialize ring buffer */ + ring_buf_init(&data->pool, sizeof(data->buffer), data->buffer); + + /* Initialize HSM clock and mailbox, then boot it */ + hsm_reg_addr = SOC_AON_BASE + SOC_AON_O_HSMCFG; + hsm_reg_value = sys_read32(hsm_reg_addr) | SOC_AON_HSMCFG_FIREWALL; + sys_write32(hsm_reg_value, hsm_reg_addr); + + key = irq_lock(); + + /* Disable HSM Clock */ + hsm_reg_addr = HSM_NON_SEC_BASE + HSM_NON_SEC_O_CLK_MEM_CTRL; + hsm_reg_value = sys_read32(hsm_reg_addr) & ~(hsm_clk_mask); + sys_write32(hsm_reg_value, hsm_reg_addr); + + hsm_reg_addr = HSM_SEC_BASE + HSM_SEC_O_CLKCTL; + hsm_reg_value = + sys_read32(hsm_reg_addr) & ~(HSM_SEC_CLKCTL_CLKGO_EN | HSM_SEC_CLKCTL_HIFCLKGO_EN | + HSM_SEC_CLKCTL_CNTCLKGO_EN); + sys_write32(hsm_reg_value, hsm_reg_addr); + + /* Initialize HSM Clock */ + hsm_reg_addr = HSM_NON_SEC_BASE + HSM_NON_SEC_O_CLK_MEM_CTRL; + sys_write32(hsm_reg_value, hsm_clk_enable); + + hsm_reg_addr = HSM_SEC_BASE + HSM_SEC_O_CLKCTL; + hsm_reg_value = + sys_read32(hsm_reg_addr) | + (HSM_SEC_CLKCTL_CLKGO_EN | HSM_SEC_CLKCTL_HIFCLKGO_EN | HSM_SEC_CLKCTL_CNTCLKGO_EN); + sys_write32(hsm_reg_value, hsm_reg_addr); + + /* Unlock CPUID0 and CPUID1 */ + hsm_reg_addr = HSMCRYPTO_BASE + HSMCRYPTO_O_MBLCKOUT; + hsm_reg_value = HSM_O_UNLOCK_CPUID0_CPUID1; + sys_write32(hsm_reg_value, hsm_reg_addr); + + /* Link mailbox */ + hsm_reg_addr = HSMCRYPTO_BASE + HSMCRYPTO_O_MBSTA; + hsm_reg_value = sys_read32(hsm_reg_addr) | HSMCRYPTO_MBCTL_MB1LNK_LNK; + hsm_reg_addr = HSMCRYPTO_BASE + HSMCRYPTO_O_MBCTL; + sys_write32(hsm_reg_value, hsm_reg_addr); + + /* Allow non-secure/secure access (Set bits 7 and 3 to 1 if we need secure access) */ + hsm_reg_addr = HSMCRYPTO_BASE + HSMCRYPTO_O_MBLNKID; + hsm_reg_value = (0 << HSM_MBXLINKID_LINKID1_S) | (0 << HSM_MBXLINKID_LINKID2_S) | + (0 << HSM_MBXLINKID_PROTACC1_S) | (0 << HSM_MBXLINKID_PORTACC2_S); + sys_write32(hsm_reg_value, hsm_reg_addr); + + /* Make sure CPU_ID=0 host can access mailbox 1 & 2 (no lockout) */ + hsm_reg_addr = HSMCRYPTO_BASE + HSMCRYPTO_O_MBLCKOUT; + hsm_reg_value = sys_read32(hsm_reg_addr) & HSM_O_CPUID0_MB1_MB2_UNLOCK; + sys_write32(hsm_reg_value, hsm_reg_addr); + + entropy_cc35xx_hsm_init_aic(); + + hsm_reg_addr = HSMCRYPTO_BASE + HSM_O_MODULESTA; + hsm_status = sys_read32(hsm_reg_addr); + if ((hsm_status & HSM_MODULESTA_FATALERR) == 0) { + /* + * At PRE_KERNEL_1 we don't use k_sleep() and other scheduling + * functions, so we use a busy wait loop here to wait for the + * input token to be processed inside the HSM. + * Based on experiments, it usually takes 0 cycles of the while loop + * to process the input token. + */ + hsm_reg_addr = HSMCRYPTO_BASE + HSMCRYPTO_O_MBSTA; + while ((sys_read32(hsm_reg_addr) & HSMCRYPTO_MBSTA_MB1IN_M) == + HSMCRYPTO_MBSTA_MB1IN_FULL) + ; + + /* Mailbox is empty so we can write the system info token to mbx1_in */ + for (idx = 0; idx < ARRAY_SIZE(token); idx++) { + hsm_reg_addr = HSMCRYPTO_BASE + HSMCRYPTO_O_MB1IN + idx * 4; + sys_write32(token[idx], hsm_reg_addr); + } + + /* Mark mbx1 in as full */ + hsm_reg_addr = HSMCRYPTO_BASE + HSMCRYPTO_O_MBCTL; + hsm_reg_value = HSMCRYPTO_MBCTL_MB1IN_FULL; + sys_write32(hsm_reg_value, hsm_reg_addr); + + /* + * At PRE_KERNEL_1 we don't use k_sleep() and other scheduling + * functions, so we use a busy wait loop here to wait for the + * output token to be available in mbx1_out. + * Based on experiments, it usually takes 12 cycles of the while loop + * to get response from HSM. + */ + hsm_reg_addr = HSMCRYPTO_BASE + HSMCRYPTO_O_MBSTA; + while ((sys_read32(hsm_reg_addr) & HSMCRYPTO_MBSTA_MB1OUT_M) != + HSMCRYPTO_MBSTA_MB1OUT_FULL) + ; + + /* Check for output token error */ + hsm_reg_addr = HSMCRYPTO_BASE + HSMCRYPTO_O_MB1OUT; + hsm_reg_value = sys_read32(hsm_reg_addr); + if ((hsm_reg_value & OUTPUT_TOKEN_ERROR) == 0) { + result = HSMLPF3_STATUS_SUCCESS; + } + + hsm_reg_addr = HSMCRYPTO_BASE + HSMCRYPTO_O_MBCTL; + hsm_reg_value = HSMCRYPTO_MBCTL_MB1OUT_EMTY; + sys_write32(hsm_reg_value, hsm_reg_addr); + } + + irq_unlock(key); + + if (result != HSMLPF3_STATUS_SUCCESS) { + return -EIO; + } + + if (HSMSAL_Init() != HSMSAL_SUCCESS) { + return -EIO; + } + + /* + * According to the CC35XX SDK: + * Reset of HSM, as well as HUK (Hardware Unique Key) provisioning on CC35XX, is performed + * at boot time by the TI Device boot loader. As a result, HUK provisioning is not needed. + */ + key = irq_lock(); + NVIC_ClearPendingIRQ(DT_INST_IRQN(0)); + irq_unlock(key); + + entropy_cc35xx_kick_trng_config(data); + + IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), entropy_cc35xx_isr, + DEVICE_DT_INST_GET(0), 0); + + irq_enable(DT_INST_IRQN(0)); + + return 0; +} + +static const struct entropy_driver_api entropy_cc35xx_driver_api = { + .get_entropy = entropy_cc35xx_get_entropy, +}; + +static struct entropy_cc35xx_data entropy_cc35xx_data = { + .pool_lock = Z_SEM_INITIALIZER(entropy_cc35xx_data.pool_lock, 1, 1), + .hsm.operation = Z_SEM_INITIALIZER(entropy_cc35xx_data.hsm.operation, 1, 1), +}; + +DEVICE_DT_INST_DEFINE(0, entropy_cc35xx_init, NULL, &entropy_cc35xx_data, NULL, PRE_KERNEL_1, + CONFIG_ENTROPY_INIT_PRIORITY, &entropy_cc35xx_driver_api); diff --git a/dts/arm/ti/cc35xxe.dtsi b/dts/arm/ti/cc35xxe.dtsi index da8eef1d9432..56a996b544d3 100644 --- a/dts/arm/ti/cc35xxe.dtsi +++ b/dts/arm/ti/cc35xxe.dtsi @@ -23,7 +23,7 @@ #define INT_NAB_HOST_IRQ 63 #define INT_RTC_EVENT_IRQ 65 /* - * Note: Zephyr uses exception numbers, vs the IRQ used by the CC32XX SDK + * Note: Zephyr uses exception numbers, vs the IRQ used by the TI SimpleLink WFF3 SDK * which are offset by 16: */ #define EXP_UARTA0 (INT_SP_UART_0_INT_REQ - 16) @@ -272,6 +272,13 @@ status = "disabled"; }; + hsm: hsm@41b00000 { + compatible = "ti,cc35xx-hsm"; + interrupts = ; + reg = <0x41b00000 0x100000>; + status = "disabled"; + }; + pinctrl: pin-controller@41140000 { compatible = "ti,cc35xx-pinctrl"; reg = <0x41140000 0x80000>; diff --git a/dts/bindings/rng/ti,cc35xx-hsm.yaml b/dts/bindings/rng/ti,cc35xx-hsm.yaml new file mode 100644 index 000000000000..cb18bc7c11b2 --- /dev/null +++ b/dts/bindings/rng/ti,cc35xx-hsm.yaml @@ -0,0 +1,8 @@ +# Copyright (c) 2025 Conclusive Engineering Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +description: TI SimpleLink CC35xxE HSM (Hardware Security Module) + +compatible: "ti,cc35xx-hsm" + +include: base.yaml From 1e834e479284c45398ad5c9be2ca1fac1bd9c54a Mon Sep 17 00:00:00 2001 From: Jacek Ozimek Date: Fri, 29 Aug 2025 09:48:28 +0200 Subject: [PATCH 045/100] UPSTREAM-PEND: drivers: crypto: cc35xx: initial support for TI HSM Crypto Add HSM, entropy and crypto drivers based on the TI Simplelink SDK Signed-off-by: Jacek Ozimek Signed-off-by: Artur Rojek --- .../ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi | 10 +- drivers/crypto/CMakeLists.txt | 1 + drivers/crypto/Kconfig | 1 + drivers/crypto/Kconfig.cc35xx | 11 + drivers/crypto/crypto_cc35xx.c | 278 ++++++++ drivers/entropy/Kconfig.cc35xx | 25 +- drivers/entropy/entropy_cc35xx.c | 367 +---------- drivers/misc/CMakeLists.txt | 1 + drivers/misc/Kconfig | 1 + drivers/misc/ti_cc35xx_hsm/CMakeLists.txt | 7 + drivers/misc/ti_cc35xx_hsm/Kconfig | 32 + drivers/misc/ti_cc35xx_hsm/ti_cc35xx_hsm.c | 621 ++++++++++++++++++ dts/arm/ti/cc35xxe.dtsi | 13 + .../ti,cc35xx-hsm-crypto.yaml} | 4 +- dts/bindings/misc/ti,cc35xx-hsm.yaml | 14 + dts/bindings/rng/ti,cc35xx-hsm-trng.yaml | 12 + .../misc/ti_cc35xx_hsm/ti_cc35xx_hsm.h | 33 + .../crypto/boards/lp_em_cc35x1.overlay | 9 + samples/drivers/crypto/src/main.c | 2 + 19 files changed, 1072 insertions(+), 370 deletions(-) create mode 100644 drivers/crypto/Kconfig.cc35xx create mode 100644 drivers/crypto/crypto_cc35xx.c create mode 100644 drivers/misc/ti_cc35xx_hsm/CMakeLists.txt create mode 100644 drivers/misc/ti_cc35xx_hsm/Kconfig create mode 100644 drivers/misc/ti_cc35xx_hsm/ti_cc35xx_hsm.c rename dts/bindings/{rng/ti,cc35xx-hsm.yaml => crypto/ti,cc35xx-hsm-crypto.yaml} (55%) create mode 100644 dts/bindings/misc/ti,cc35xx-hsm.yaml create mode 100644 dts/bindings/rng/ti,cc35xx-hsm-trng.yaml create mode 100644 include/zephyr/drivers/misc/ti_cc35xx_hsm/ti_cc35xx_hsm.h create mode 100644 samples/drivers/crypto/boards/lp_em_cc35x1.overlay diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi index 2cb628b26203..96248ccf82b3 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi @@ -26,7 +26,7 @@ zephyr,console = &uart1; zephyr,shell-uart = &uart1; zephyr,rtc = &rtc; - zephyr,entropy = &hsm; + zephyr,entropy = &entropy; }; leds { @@ -226,3 +226,11 @@ &hsm { status = "okay"; }; + +&entropy { + status = "okay"; +}; + +&crypto { + status = "okay"; +}; diff --git a/drivers/crypto/CMakeLists.txt b/drivers/crypto/CMakeLists.txt index 9947042346cd..c6ef57af2b3a 100644 --- a/drivers/crypto/CMakeLists.txt +++ b/drivers/crypto/CMakeLists.txt @@ -31,4 +31,5 @@ zephyr_library_sources_ifdef(CONFIG_CRYPTO_SI32 crypto_si32.c) zephyr_library_sources_ifdef(CONFIG_CRYPTO_SMARTBOND crypto_smartbond.c) zephyr_library_sources_ifdef(CONFIG_CRYPTO_STM32 crypto_stm32.c) zephyr_library_sources_ifdef(CONFIG_CRYPTO_STM32_HASH crypto_stm32_hash.c) +zephyr_library_sources_ifdef(CONFIG_CRYPTO_TI_CC35XX crypto_cc35xx.c) # zephyr-keep-sorted-stop diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 94b49ef6418f..c70bd50461db 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -58,6 +58,7 @@ config CRYPTO_MBEDTLS_SHIM_MAX_SESSION source "drivers/crypto/Kconfig.ataes132a" source "drivers/crypto/Kconfig.bflb" source "drivers/crypto/Kconfig.cc23x0" +source "drivers/crypto/Kconfig.cc35xx" source "drivers/crypto/Kconfig.esp32" source "drivers/crypto/Kconfig.intel" source "drivers/crypto/Kconfig.it51xxx" diff --git a/drivers/crypto/Kconfig.cc35xx b/drivers/crypto/Kconfig.cc35xx new file mode 100644 index 000000000000..44c2405049c5 --- /dev/null +++ b/drivers/crypto/Kconfig.cc35xx @@ -0,0 +1,11 @@ +# Copyright (c) 2025 Conclusive Engineering Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +config CRYPTO_TI_CC35XX + bool "TI Crypto driver" + default y + depends on DT_HAS_TI_CC35XX_HSM_CRYPTO_ENABLED + select TI_CC35XX_HSM + help + This option enables the driver for the HSM Crypto submodule + for TI SimpleLink CC35xx SoCs. diff --git a/drivers/crypto/crypto_cc35xx.c b/drivers/crypto/crypto_cc35xx.c new file mode 100644 index 000000000000..afc4bae70c40 --- /dev/null +++ b/drivers/crypto/crypto_cc35xx.c @@ -0,0 +1,278 @@ +/* + * Copyright (c) 2025 Conclusive Engineering Sp. z o.o. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT ti_cc35xx_hsm_crypto + +#include +#include +#include + +#include + +#include + +struct crypto_ti_cc35xx_data { + const struct device *hsm; +}; + +static int crypto_ti_cc35xx_do(enum cipher_mode mode, enum cipher_op op_type, + struct cipher_ctx *ctx, void *pkt) +{ + struct crypto_ti_cc35xx_data *data; + struct hsm_ti_cc35xx_driver_api *api; + + if (ctx == NULL || ctx->device == NULL || ctx->device->data == NULL) { + return -ENODEV; + } + + data = (struct crypto_ti_cc35xx_data *)ctx->device->data; + if (data->hsm == NULL || data->hsm->api == NULL) { + return -EINVAL; + } + + api = (struct hsm_ti_cc35xx_driver_api *)data->hsm->api; + if (api->do_crypto == NULL) { + return -EINVAL; + } + + return api->do_crypto(data->hsm, CRYPTO_CIPHER_ALGO_AES, mode, op_type, ctx, pkt); +} + +static int crypto_ti_cc35xx_do_ecb_encrypt(struct cipher_ctx *ctx, struct cipher_pkt *pkt) +{ + int result; + + if (pkt->in_len > HSM_AES_BLOCK_SIZE) { + return -EINVAL; + } + + result = crypto_ti_cc35xx_do(CRYPTO_CIPHER_MODE_ECB, CRYPTO_CIPHER_OP_ENCRYPT, ctx, pkt); + + if (result == 0) { + pkt->out_len = HSM_AES_BLOCK_SIZE; + } + + return result; +} + +static int crypto_ti_cc35xx_do_ecb_decrypt(struct cipher_ctx *ctx, struct cipher_pkt *pkt) +{ + int result; + + if (pkt->in_len > HSM_AES_BLOCK_SIZE) { + return -EINVAL; + } + + result = crypto_ti_cc35xx_do(CRYPTO_CIPHER_MODE_ECB, CRYPTO_CIPHER_OP_DECRYPT, ctx, pkt); + + if (result == 0) { + pkt->out_len = HSM_AES_BLOCK_SIZE; + } + + return result; +} + +static int crypto_ti_cc35xx_do_ctr_encrypt(struct cipher_ctx *ctx, struct cipher_pkt *pkt, + uint8_t *iv) +{ + int result; + struct hsm_ti_cc35xx_driver_session *session; + int ivlen; + + if (ctx == NULL || pkt == NULL || ctx->drv_sessn_state == NULL) { + return -EINVAL; + } + + session = (struct hsm_ti_cc35xx_driver_session *const)(ctx->drv_sessn_state); + ivlen = sizeof(session->ctr) - (ctx->mode_params.ctr_info.ctr_len >> 3); + + if (ivlen < 0 || (sizeof(session->ctr) < ivlen) || ((sizeof(session->ctr) % 4) != 0)) { + return -EINVAL; + } + + memcpy(session->ctr, iv, ivlen); + + result = crypto_ti_cc35xx_do(CRYPTO_CIPHER_MODE_CTR, CRYPTO_CIPHER_OP_ENCRYPT, ctx, pkt); + if (result == 0) { + pkt->out_len = pkt->in_len; + } + + return result; +} + +static int crypto_ti_cc35xx_do_ctr_decrypt(struct cipher_ctx *ctx, struct cipher_pkt *pkt, + uint8_t *iv) +{ + int result; + struct hsm_ti_cc35xx_driver_session *session; + int ivlen; + + if (ctx == NULL || pkt == NULL || ctx->drv_sessn_state == NULL) { + return -EINVAL; + } + + session = (struct hsm_ti_cc35xx_driver_session *const)(ctx->drv_sessn_state); + ivlen = sizeof(session->ctr) - (ctx->mode_params.ctr_info.ctr_len >> 3); + + if (ivlen < 0 || (sizeof(session->ctr) < ivlen) || ((sizeof(session->ctr) % 4) != 0)) { + return -EINVAL; + } + + memcpy(session->ctr, iv, ivlen); + + result = crypto_ti_cc35xx_do(CRYPTO_CIPHER_MODE_CTR, CRYPTO_CIPHER_OP_ENCRYPT, ctx, pkt); + if (result == 0) { + pkt->out_len = pkt->in_len; + } + + return result; +} + +static int crypto_ti_cc35xx_do_ccm_encrypt(struct cipher_ctx *ctx, struct cipher_aead_pkt *pkt, + uint8_t *nonce) +{ + int result; + struct hsm_ti_cc35xx_driver_session *session; + + session = (struct hsm_ti_cc35xx_driver_session *const)(ctx->drv_sessn_state); + session->nonce = nonce; + + result = crypto_ti_cc35xx_do(CRYPTO_CIPHER_MODE_CCM, CRYPTO_CIPHER_OP_ENCRYPT, ctx, pkt); + if (result == 0) { + pkt->pkt->out_len = pkt->pkt->in_len + ctx->mode_params.ccm_info.tag_len; + } + + return result; +} + +static int crypto_ti_cc35xx_do_ccm_decrypt(struct cipher_ctx *ctx, struct cipher_aead_pkt *pkt, + uint8_t *nonce) +{ + int result; + struct hsm_ti_cc35xx_driver_session *session; + + session = (struct hsm_ti_cc35xx_driver_session *const)(ctx->drv_sessn_state); + session->nonce = nonce; + + result = crypto_ti_cc35xx_do(CRYPTO_CIPHER_MODE_CCM, CRYPTO_CIPHER_OP_DECRYPT, ctx, pkt); + + if (result == 0) { + pkt->pkt->out_len = pkt->pkt->in_len + ctx->mode_params.ccm_info.tag_len; + } + + return result; +} + +static int crypto_ti_cc35xx_query_caps(const struct device *dev) +{ + struct crypto_ti_cc35xx_data *data; + struct hsm_ti_cc35xx_driver_api *api; + + if (dev == NULL || dev->data == NULL) { + return -ENODEV; + } + + data = (struct crypto_ti_cc35xx_data *)dev->data; + if (data->hsm == NULL || data->hsm->api == NULL) { + return -EINVAL; + } + + api = (struct hsm_ti_cc35xx_driver_api *)data->hsm->api; + if (api->get_hw_caps == NULL) { + return -EINVAL; + } + + return api->get_hw_caps(data->hsm); +} + +static int crypto_ti_cc35xx_session_setup(const struct device *dev, struct cipher_ctx *ctx, + enum cipher_algo algo, enum cipher_mode mode, + enum cipher_op op_type) +{ + static struct hsm_ti_cc35xx_driver_session session = {0}; + + if (ctx->key.bit_stream == NULL) { + return -EINVAL; + } + + if (op_type == CRYPTO_CIPHER_OP_ENCRYPT) { + switch (mode) { + case CRYPTO_CIPHER_MODE_ECB: + ctx->ops.block_crypt_hndlr = crypto_ti_cc35xx_do_ecb_encrypt; + break; + case CRYPTO_CIPHER_MODE_CTR: + ctx->ops.ctr_crypt_hndlr = crypto_ti_cc35xx_do_ctr_encrypt; + break; + case CRYPTO_CIPHER_MODE_CCM: + ctx->ops.ccm_crypt_hndlr = crypto_ti_cc35xx_do_ccm_encrypt; + break; + default: + return -ENOTSUP; + } + } else { + switch (mode) { + case CRYPTO_CIPHER_MODE_ECB: + ctx->ops.block_crypt_hndlr = crypto_ti_cc35xx_do_ecb_decrypt; + break; + case CRYPTO_CIPHER_MODE_CTR: + ctx->ops.ctr_crypt_hndlr = crypto_ti_cc35xx_do_ctr_decrypt; + break; + case CRYPTO_CIPHER_MODE_CCM: + ctx->ops.ccm_crypt_hndlr = crypto_ti_cc35xx_do_ccm_decrypt; + break; + default: + return -ENOTSUP; + } + } + + ctx->ops.cipher_mode = mode; + ctx->drv_sessn_state = &session; + ctx->device = dev; + + return 0; +} + +static int crypto_ti_cc35xx_session_free(const struct device *dev, struct cipher_ctx *ctx) +{ + ARG_UNUSED(dev); + struct hsm_ti_cc35xx_driver_session *session; + + if (ctx == NULL || ctx->drv_sessn_state == NULL) { + return -EINVAL; + } + + session = (struct hsm_ti_cc35xx_driver_session *)ctx->drv_sessn_state; + memset(session, 0, sizeof(struct hsm_ti_cc35xx_driver_session)); + ctx->drv_sessn_state = NULL; + ctx->device = NULL; + + return 0; +} + +static int crypto_ti_cc35xx_init(const struct device *dev) +{ + const struct device *parent = DEVICE_DT_GET(DT_NODELABEL(hsm)); + struct crypto_ti_cc35xx_data *data = dev->data; + + if (!device_is_ready(parent)) { + return -ENODEV; + } + + data->hsm = parent; + + return 0; +} + +static struct crypto_driver_api crypto_ti_cc35xx_driver_api = { + .cipher_begin_session = crypto_ti_cc35xx_session_setup, + .cipher_free_session = crypto_ti_cc35xx_session_free, + .query_hw_caps = crypto_ti_cc35xx_query_caps, +}; + +static struct crypto_ti_cc35xx_data crypto_data; + +DEVICE_DT_INST_DEFINE(0, crypto_ti_cc35xx_init, PM_DEVICE_DT_INST_GET(0), &crypto_data, NULL, + POST_KERNEL, CONFIG_CRYPTO_INIT_PRIORITY, &crypto_ti_cc35xx_driver_api); diff --git a/drivers/entropy/Kconfig.cc35xx b/drivers/entropy/Kconfig.cc35xx index 912b98cb7bdf..a8dad6f0db8a 100644 --- a/drivers/entropy/Kconfig.cc35xx +++ b/drivers/entropy/Kconfig.cc35xx @@ -4,28 +4,11 @@ # SPDX-License-Identifier: Apache-2.0 config ENTROPY_CC35XX_RNG - bool "TI SimpleLink CC35xxE Hardware Security Module (HSM)" + bool "TI SimpleLink CC35xxE Hardware Security Module (HSM) Entropy submodule" default y - depends on DT_HAS_TI_CC35XX_HSM_ENABLED + depends on DT_HAS_TI_CC35XX_HSM_TRNG_ENABLED select TI_CC35XX_HSM select ENTROPY_HAS_DRIVER - select RING_BUFFER help - This option enables the driver for the Hardware Security Module (HSM) - for TI SimpleLink CC35xxE SoCs. - -config TI_CC35XX_HSM - bool - depends on DT_HAS_TI_CC35XX_HSM_ENABLED - -if ENTROPY_CC35XX_RNG - -config ENTROPY_CC35XX_POOL_SIZE - int "Number of bytes in the entropy pool" - default 512 - range 256 65536 - help - The size in bytes of the buffer used to store entropy generated by the - hardware. Should be a power of two for high performance. - -endif # ENTROPY_CC35XX_RNG + This option enables the driver for the HSM Entropy submodule + for TI SimpleLink CC35xx SoCs. diff --git a/drivers/entropy/entropy_cc35xx.c b/drivers/entropy/entropy_cc35xx.c index 2161f0b08d0f..ed3c7e55df33 100644 --- a/drivers/entropy/entropy_cc35xx.c +++ b/drivers/entropy/entropy_cc35xx.c @@ -4,378 +4,53 @@ * SPDX-License-Identifier: Apache-2.0 */ -#define DT_DRV_COMPAT ti_cc35xx_hsm +#define DT_DRV_COMPAT ti_cc35xx_hsm_trng #include #include #include #include #include -#include -#include -#include -#include -#include -#include +#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#define SYSTEMINFO_TOKEN_WORD0 0x0F030000 -#define CRYPTO_OFFICER_ID 0x4F5A3647 -#define OUTPUT_TOKEN_ERROR 0x80000000 -#define HSM_TRNG_RAW_KEY_ENC 0x5244 -#define HSM_O_UNLOCK_CPUID0_CPUID1 0xFFFFFCFC -#define HSM_O_CPUID0_MB1_MB2_UNLOCK 0xFFFFFF77 - -#define HSMCRYPTO_BASE HSM_BASE -#define HSMCRYPTO_O_MBSTA HSM_O_MBXSTA -#define HSMCRYPTO_MBSTA_MB1IN_M HSM_MBXSTA_INFULL1 -#define HSMCRYPTO_MBSTA_MB1IN_FULL HSM_MBXSTA_INFULL1 -#define HSMCRYPTO_O_MB1IN HSM_O_EIP130_072_MAILBOX1_IN -#define HSMCRYPTO_O_MBCTL HSM_O_MBXCTL -#define HSMCRYPTO_MBCTL_MB1IN_FULL HSM_MBXCTL_INFULL1 -#define HSMCRYPTO_MBCTL_MB1LNK_LNK HSM_MBXCTL_LINK1 -#define HSMCRYPTO_O_MBLNKID HSM_O_MBXLINKID -#define HSMCRYPTO_O_MBLCKOUT HSM_O_MBXLCKOUT -#define HSMCRYPTO_MBSTA_MB1OUT_M HSM_MBXSTA_OUTFULL1 -#define HSMCRYPTO_MBSTA_MB1OUT_FULL HSM_MBXSTA_OUTFULL1 -#define HSMCRYPTO_O_MB1OUT HSM_O_EIP130_072_MAILBOX1_IN -#define HSMCRYPTO_MBCTL_MB1OUT_EMTY HSM_MBXCTL_OUTEMP1 - -#define HSMLPF3_STATUS_SUCCESS ((int_fast16_t)0) -#define HSMLPF3_STATUS_ERROR ((int_fast16_t)-1) -#define HSM_RAW_RNG_BLOCK_SIZE (256U) -#define HSM_BUFFER_SIZE HSM_RAW_RNG_BLOCK_SIZE -#define HSM_RAW_RNG_BLOCK_NUM (HSM_BUFFER_SIZE / HSM_RAW_RNG_BLOCK_SIZE) - -/* Adjusted experimentally */ -#define HSM_OPERATION_RETRIES 10 -#define HSM_WAIT_FOR_RESULT_RETRIES 10 -#define HSM_OPERATION_SEM_TIMEOUT_MS 10 - -struct entropy_cc35xx_hsm { - struct k_sem operation; - uint32_t retries; - uint8_t buffer[HSM_BUFFER_SIZE]; +struct entropy_ti_cc35xx_data { + const struct device *hsm_dev; }; -struct entropy_cc35xx_data { - struct k_sem pool_lock; - struct k_work trng_work; - struct entropy_cc35xx_hsm hsm; - struct ring_buf pool; - uint8_t buffer[CONFIG_ENTROPY_CC35XX_POOL_SIZE]; -}; - -static inline int entropy_cc35xx_read_hsm_result(void) +static int ti_cc35xx_get_entropy(const struct device *dev, uint8_t *buf, uint16_t len) { - Eip130Token_Result_t result_token; - uint8_t mailbox_number; + struct entropy_ti_cc35xx_data *data = dev->data; - mailbox_number = HSMSAL_GetMailBoxNumber(); - return (HSMSAL_ScanAndReadMailbox(&result_token, mailbox_number) == HSMSAL_SUCCESS) ? 0 - : -EIO; -} - -static inline int entropy_cc35xx_wait_for_hsm(void) -{ - for (int i = 0; i < HSM_WAIT_FOR_RESULT_RETRIES; ++i) { - if (!entropy_cc35xx_read_hsm_result()) { - return 0; - } - } - - return -ETIMEDOUT; -} - -static void entropy_cc35xx_hsm_init_aic(void) -{ - Device_Handle_t gl_aic = Device_Find("EIP130_AIC"); - - if (gl_aic != NULL) { - /* - * Configure all sources for edge detect. Future improvement - * is to only enable the interrupts we need. We could also - * use EIP201_Config_Change(), but there is no adapter function() - */ - EIP201_SourceSettings_t settings = { - .Source = 0xFF, - .Config = EIP201_CONFIG_RISING_EDGE, - .fEnable = false /* enable source only when active */ - }; - EIP201_Initialize(gl_aic, &settings, 1); - } -} - -static inline void entropy_cc35xx_kick_trng_config(struct entropy_cc35xx_data *data) -{ - uintptr_t key; - Eip130Token_Command_t command_token; - - data->hsm.retries = 0; - - memset(&command_token, 0, sizeof(command_token)); - - Eip130Token_Command_RandomNumber_Generate(&command_token, HSM_RAW_RNG_BLOCK_NUM, - (uintptr_t)data->hsm.buffer); - Eip130Token_Command_RandomNumber_SetRawKey(&command_token, HSM_TRNG_RAW_KEY_ENC); - - key = irq_lock(); - HSMSAL_SubmitPhysicalToken(&command_token); - irq_unlock(key); -} - -static void entropy_cc35xx_kick_trng(struct entropy_cc35xx_data *data) -{ - if (ring_buf_space_get(&data->pool) == 0) { - /* Ring buffer is full. Refill not needed so far */ - return; - } - - if (data->hsm.retries++ >= HSM_OPERATION_RETRIES) { - /* HSM recovering */ - NVIC_ClearPendingIRQ(DT_INST_IRQN(0)); - irq_disable(DT_INST_IRQN(0)); - entropy_cc35xx_wait_for_hsm(); - k_sem_give(&data->hsm.operation); - } else if (k_sem_take(&data->hsm.operation, K_MSEC(HSM_OPERATION_SEM_TIMEOUT_MS)) != 0) { - return; - } - - entropy_cc35xx_kick_trng_config(data); - - irq_enable(DT_INST_IRQN(0)); -} - -static void entropy_cc35xx_trng_work_handler(struct k_work *work) -{ - struct entropy_cc35xx_data *data = - CONTAINER_OF(work, struct entropy_cc35xx_data, trng_work); - entropy_cc35xx_kick_trng(data); -} - -static int entropy_cc35xx_get_entropy(const struct device *dev, uint8_t *buf, uint16_t len) -{ - struct entropy_cc35xx_data *data = dev->data; - uint32_t cnt; - - if (len == 0 || len > sizeof(data->buffer)) { + if (len == 0 || buf == NULL) { return -EINVAL; } - entropy_cc35xx_kick_trng(data); - - while (len) { - k_sem_take(&data->pool_lock, K_FOREVER); - cnt = ring_buf_get(&data->pool, buf, len); - k_sem_give(&data->pool_lock); + const struct hsm_ti_cc35xx_driver_api *api = + (const struct hsm_ti_cc35xx_driver_api *)data->hsm_dev->api; - entropy_cc35xx_kick_trng(data); - - buf += cnt; - len -= cnt; - } - - return 0; -} - -static void entropy_cc35xx_isr(const struct device *dev) -{ - struct entropy_cc35xx_data *data = dev->data; - - NVIC_ClearPendingIRQ(DT_INST_IRQN(0)); - irq_disable(DT_INST_IRQN(0)); - - entropy_cc35xx_read_hsm_result(); - - ring_buf_put(&data->pool, data->hsm.buffer, sizeof(data->hsm.buffer)); - k_sem_give(&data->hsm.operation); - - k_work_submit(&data->trng_work); + return api->get_entropy(data->hsm_dev, buf, len); } -static int entropy_cc35xx_init(const struct device *dev) +static int entropy_ti_cc35xx_init(const struct device *dev) { - struct entropy_cc35xx_data *data = dev->data; - - uint32_t result = HSMLPF3_STATUS_ERROR; - uint32_t token[] = {SYSTEMINFO_TOKEN_WORD0, CRYPTO_OFFICER_ID}; - const uint32_t hsm_clk_enable = HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_EN | - HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_EN | - HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_EN | - HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_M3_EN | - HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_M3_EN | - HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_M3_EN; - const uint32_t hsm_clk_mask = HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_M | - HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_M | - HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_M | - HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_M3_M | - HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_M3_M | - HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_M3_M; - - uint32_t idx, hsm_status, hsm_reg_value; - uintptr_t key, hsm_reg_addr; - - k_work_init(&data->trng_work, entropy_cc35xx_trng_work_handler); - - /* Initialize ring buffer */ - ring_buf_init(&data->pool, sizeof(data->buffer), data->buffer); - - /* Initialize HSM clock and mailbox, then boot it */ - hsm_reg_addr = SOC_AON_BASE + SOC_AON_O_HSMCFG; - hsm_reg_value = sys_read32(hsm_reg_addr) | SOC_AON_HSMCFG_FIREWALL; - sys_write32(hsm_reg_value, hsm_reg_addr); - - key = irq_lock(); - - /* Disable HSM Clock */ - hsm_reg_addr = HSM_NON_SEC_BASE + HSM_NON_SEC_O_CLK_MEM_CTRL; - hsm_reg_value = sys_read32(hsm_reg_addr) & ~(hsm_clk_mask); - sys_write32(hsm_reg_value, hsm_reg_addr); - - hsm_reg_addr = HSM_SEC_BASE + HSM_SEC_O_CLKCTL; - hsm_reg_value = - sys_read32(hsm_reg_addr) & ~(HSM_SEC_CLKCTL_CLKGO_EN | HSM_SEC_CLKCTL_HIFCLKGO_EN | - HSM_SEC_CLKCTL_CNTCLKGO_EN); - sys_write32(hsm_reg_value, hsm_reg_addr); - - /* Initialize HSM Clock */ - hsm_reg_addr = HSM_NON_SEC_BASE + HSM_NON_SEC_O_CLK_MEM_CTRL; - sys_write32(hsm_reg_value, hsm_clk_enable); + const struct device *parent = DEVICE_DT_GET(DT_NODELABEL(hsm)); + struct entropy_ti_cc35xx_data *data = dev->data; - hsm_reg_addr = HSM_SEC_BASE + HSM_SEC_O_CLKCTL; - hsm_reg_value = - sys_read32(hsm_reg_addr) | - (HSM_SEC_CLKCTL_CLKGO_EN | HSM_SEC_CLKCTL_HIFCLKGO_EN | HSM_SEC_CLKCTL_CNTCLKGO_EN); - sys_write32(hsm_reg_value, hsm_reg_addr); - - /* Unlock CPUID0 and CPUID1 */ - hsm_reg_addr = HSMCRYPTO_BASE + HSMCRYPTO_O_MBLCKOUT; - hsm_reg_value = HSM_O_UNLOCK_CPUID0_CPUID1; - sys_write32(hsm_reg_value, hsm_reg_addr); - - /* Link mailbox */ - hsm_reg_addr = HSMCRYPTO_BASE + HSMCRYPTO_O_MBSTA; - hsm_reg_value = sys_read32(hsm_reg_addr) | HSMCRYPTO_MBCTL_MB1LNK_LNK; - hsm_reg_addr = HSMCRYPTO_BASE + HSMCRYPTO_O_MBCTL; - sys_write32(hsm_reg_value, hsm_reg_addr); - - /* Allow non-secure/secure access (Set bits 7 and 3 to 1 if we need secure access) */ - hsm_reg_addr = HSMCRYPTO_BASE + HSMCRYPTO_O_MBLNKID; - hsm_reg_value = (0 << HSM_MBXLINKID_LINKID1_S) | (0 << HSM_MBXLINKID_LINKID2_S) | - (0 << HSM_MBXLINKID_PROTACC1_S) | (0 << HSM_MBXLINKID_PORTACC2_S); - sys_write32(hsm_reg_value, hsm_reg_addr); - - /* Make sure CPU_ID=0 host can access mailbox 1 & 2 (no lockout) */ - hsm_reg_addr = HSMCRYPTO_BASE + HSMCRYPTO_O_MBLCKOUT; - hsm_reg_value = sys_read32(hsm_reg_addr) & HSM_O_CPUID0_MB1_MB2_UNLOCK; - sys_write32(hsm_reg_value, hsm_reg_addr); - - entropy_cc35xx_hsm_init_aic(); - - hsm_reg_addr = HSMCRYPTO_BASE + HSM_O_MODULESTA; - hsm_status = sys_read32(hsm_reg_addr); - if ((hsm_status & HSM_MODULESTA_FATALERR) == 0) { - /* - * At PRE_KERNEL_1 we don't use k_sleep() and other scheduling - * functions, so we use a busy wait loop here to wait for the - * input token to be processed inside the HSM. - * Based on experiments, it usually takes 0 cycles of the while loop - * to process the input token. - */ - hsm_reg_addr = HSMCRYPTO_BASE + HSMCRYPTO_O_MBSTA; - while ((sys_read32(hsm_reg_addr) & HSMCRYPTO_MBSTA_MB1IN_M) == - HSMCRYPTO_MBSTA_MB1IN_FULL) - ; - - /* Mailbox is empty so we can write the system info token to mbx1_in */ - for (idx = 0; idx < ARRAY_SIZE(token); idx++) { - hsm_reg_addr = HSMCRYPTO_BASE + HSMCRYPTO_O_MB1IN + idx * 4; - sys_write32(token[idx], hsm_reg_addr); - } - - /* Mark mbx1 in as full */ - hsm_reg_addr = HSMCRYPTO_BASE + HSMCRYPTO_O_MBCTL; - hsm_reg_value = HSMCRYPTO_MBCTL_MB1IN_FULL; - sys_write32(hsm_reg_value, hsm_reg_addr); - - /* - * At PRE_KERNEL_1 we don't use k_sleep() and other scheduling - * functions, so we use a busy wait loop here to wait for the - * output token to be available in mbx1_out. - * Based on experiments, it usually takes 12 cycles of the while loop - * to get response from HSM. - */ - hsm_reg_addr = HSMCRYPTO_BASE + HSMCRYPTO_O_MBSTA; - while ((sys_read32(hsm_reg_addr) & HSMCRYPTO_MBSTA_MB1OUT_M) != - HSMCRYPTO_MBSTA_MB1OUT_FULL) - ; - - /* Check for output token error */ - hsm_reg_addr = HSMCRYPTO_BASE + HSMCRYPTO_O_MB1OUT; - hsm_reg_value = sys_read32(hsm_reg_addr); - if ((hsm_reg_value & OUTPUT_TOKEN_ERROR) == 0) { - result = HSMLPF3_STATUS_SUCCESS; - } - - hsm_reg_addr = HSMCRYPTO_BASE + HSMCRYPTO_O_MBCTL; - hsm_reg_value = HSMCRYPTO_MBCTL_MB1OUT_EMTY; - sys_write32(hsm_reg_value, hsm_reg_addr); - } - - irq_unlock(key); - - if (result != HSMLPF3_STATUS_SUCCESS) { - return -EIO; - } - - if (HSMSAL_Init() != HSMSAL_SUCCESS) { - return -EIO; + if (!device_is_ready(parent)) { + return -ENODEV; } - /* - * According to the CC35XX SDK: - * Reset of HSM, as well as HUK (Hardware Unique Key) provisioning on CC35XX, is performed - * at boot time by the TI Device boot loader. As a result, HUK provisioning is not needed. - */ - key = irq_lock(); - NVIC_ClearPendingIRQ(DT_INST_IRQN(0)); - irq_unlock(key); - - entropy_cc35xx_kick_trng_config(data); - - IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), entropy_cc35xx_isr, - DEVICE_DT_INST_GET(0), 0); - - irq_enable(DT_INST_IRQN(0)); + data->hsm_dev = parent; return 0; } -static const struct entropy_driver_api entropy_cc35xx_driver_api = { - .get_entropy = entropy_cc35xx_get_entropy, +static struct entropy_driver_api entropy_ti_cc35xx_driver_api = { + .get_entropy = ti_cc35xx_get_entropy, }; -static struct entropy_cc35xx_data entropy_cc35xx_data = { - .pool_lock = Z_SEM_INITIALIZER(entropy_cc35xx_data.pool_lock, 1, 1), - .hsm.operation = Z_SEM_INITIALIZER(entropy_cc35xx_data.hsm.operation, 1, 1), -}; +static struct entropy_ti_cc35xx_data entropy_data; -DEVICE_DT_INST_DEFINE(0, entropy_cc35xx_init, NULL, &entropy_cc35xx_data, NULL, PRE_KERNEL_1, - CONFIG_ENTROPY_INIT_PRIORITY, &entropy_cc35xx_driver_api); +DEVICE_DT_INST_DEFINE(0, entropy_ti_cc35xx_init, PM_DEVICE_DT_INST_GET(0), &entropy_data, NULL, + PRE_KERNEL_2, CONFIG_ENTROPY_INIT_PRIORITY, &entropy_ti_cc35xx_driver_api); diff --git a/drivers/misc/CMakeLists.txt b/drivers/misc/CMakeLists.txt index ca81e74375f7..ecc6e1d6eb5a 100644 --- a/drivers/misc/CMakeLists.txt +++ b/drivers/misc/CMakeLists.txt @@ -18,6 +18,7 @@ add_subdirectory_ifdef(CONFIG_RENESAS_RA_EXTERNAL_INTERRUPT renesas_ra_external_ add_subdirectory_ifdef(CONFIG_RENESAS_RX_DTC renesas_rx_dtc) add_subdirectory_ifdef(CONFIG_RENESAS_RX_EXTERNAL_INTERRUPT renesas_rx_external_interrupt) add_subdirectory_ifdef(CONFIG_STM32N6_AXISRAM stm32n6_axisram) +add_subdirectory_ifdef(CONFIG_TI_CC35XX_HSM ti_cc35xx_hsm) add_subdirectory_ifdef(CONFIG_TIMEAWARE_GPIO timeaware_gpio) add_subdirectory_ifdef(CONFIG_TI_UNICOMM ti_unicomm) # zephyr-keep-sorted-stop diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 2f4032d42df8..b3621c0bd5f2 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -25,6 +25,7 @@ source "drivers/misc/renesas_ra_external_interrupt/Kconfig" source "drivers/misc/renesas_rx_dtc/Kconfig" source "drivers/misc/renesas_rx_external_interrupt/Kconfig" source "drivers/misc/stm32n6_axisram/Kconfig" +source "drivers/misc/ti_cc35xx_hsm/Kconfig" source "drivers/misc/ti_unicomm/Kconfig" source "drivers/misc/timeaware_gpio/Kconfig" # zephyr-keep-sorted-stop diff --git a/drivers/misc/ti_cc35xx_hsm/CMakeLists.txt b/drivers/misc/ti_cc35xx_hsm/CMakeLists.txt new file mode 100644 index 000000000000..c2a004f0ca81 --- /dev/null +++ b/drivers/misc/ti_cc35xx_hsm/CMakeLists.txt @@ -0,0 +1,7 @@ +# Copyright (c) 2025 Conclusive Engineering Sp. z o.o. +# +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() + +zephyr_library_sources_ifdef(CONFIG_TI_CC35XX_HSM ti_cc35xx_hsm.c) diff --git a/drivers/misc/ti_cc35xx_hsm/Kconfig b/drivers/misc/ti_cc35xx_hsm/Kconfig new file mode 100644 index 000000000000..aea5ae4e102b --- /dev/null +++ b/drivers/misc/ti_cc35xx_hsm/Kconfig @@ -0,0 +1,32 @@ +# TI CC35xxE HSM driver configuration +# Copyright (c) 2025 Conclusive Engineering Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +config TI_CC35XX_HSM + bool "TI SimpleLink CC35xx Hardware Security Module (HSM)" + default n + depends on DT_HAS_TI_CC35XX_HSM_ENABLED + select RING_BUFFER + help + This option enables the driver for the Hardware Security Module (HSM) + for TI SimpleLink CC35xx family SoCs. + +if TI_CC35XX_HSM + +config TI_CC35XX_HSM_INIT_PRIORITY + int "TI CC35XX HSM driver init priority" + depends on TI_CC35XX_HSM + default KERNEL_INIT_PRIORITY_DEVICE + help + TI CC35XX HSM driver device initialization priority. + + +config TI_CC35XX_HSM_ENTROPY_POOL_SIZE + int "Number of bytes in the entropy pool" + default 512 + range 256 65536 + help + The size in bytes of the buffer used to store entropy generated by the + hardware. Should be a power of two for high performance. + +endif # TI_CC35XX_HSM diff --git a/drivers/misc/ti_cc35xx_hsm/ti_cc35xx_hsm.c b/drivers/misc/ti_cc35xx_hsm/ti_cc35xx_hsm.c new file mode 100644 index 000000000000..d911242af4db --- /dev/null +++ b/drivers/misc/ti_cc35xx_hsm/ti_cc35xx_hsm.c @@ -0,0 +1,621 @@ +/* + * Copyright (c) 2025 Conclusive Engineering Sp. z o.o. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT ti_cc35xx_hsm + +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include + +#define SYSTEMINFO_TOKEN_WORD0 0x0F030000 +#define CRYPTO_OFFICER_ID 0x4F5A3647 +#define OUTPUT_TOKEN_ERROR 0x80000000 +#define HSM_TRNG_RAW_KEY_ENC 0x5244 +#define HSM_O_UNLOCK_CPUID0_CPUID1 0xFFFFFCFC +#define HSM_O_CPUID0_MB1_MB2_UNLOCK 0xFFFFFF77 + +#define HSMCRYPTO_BASE HSM_BASE +#define HSMCRYPTO_O_MBSTA HSM_O_MAILBOX_STAT +#define HSMCRYPTO_MBSTA_MB1IN_M HSM_MAILBOX_STAT_INFULL1 +#define HSMCRYPTO_MBSTA_MB1IN_FULL HSM_MAILBOX_STAT_INFULL1 +#define HSMCRYPTO_O_MB1IN HSM_O_EIP130_072_MAILBOX1_IN +#define HSMCRYPTO_O_MBCTL HSM_O_MBXCTL +#define HSMCRYPTO_MBCTL_MB1IN_FULL HSM_MBXCTL_INFULL1 +#define HSMCRYPTO_MBCTL_MB1LNK_LNK HSM_MBXCTL_LINK1 +#define HSMCRYPTO_O_MBLNKID HSM_O_MAILBOX_LINKID +#define HSMCRYPTO_O_MBLCKOUT HSM_O_MAILBOX_LOCKOUT +#define HSMCRYPTO_MBSTA_MB1OUT_M HSM_MAILBOX_STAT_OUTFULL1 +#define HSMCRYPTO_MBSTA_MB1OUT_FULL HSM_MAILBOX_STAT_OUTFULL1 +#define HSMCRYPTO_O_MB1OUT HSM_O_EIP130_072_MAILBOX1_IN +#define HSMCRYPTO_MBCTL_MB1OUT_EMTY HSM_MBXCTL_OUTEMP1 + +#define HSM_RAW_RNG_BLOCK_SIZE (256U) + +#define TI_CC35XX_HSM_CLK_MEM_CTRL_MSK (HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_M | \ + HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_M | \ + HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_M | \ + HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_M3_M | \ + HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_M3_M | \ + HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_M3_M) + +#define HSM_OPERATION_SEM_TIMEOUT_MS 1000 + +#define HSM_TRNG_RESCHEDULE_DELAY_MS 100 + +const AESECB_Params AESECB_defaultParams = { + .returnBehavior = AESECB_RETURN_BEHAVIOR_POLLING, + .callbackFxn = NULL, + .timeout = SemaphoreP_WAIT_FOREVER, + .custom = NULL, +}; + +const AESCTR_Params AESCTR_defaultParams = { + .returnBehavior = AESCTR_RETURN_BEHAVIOR_POLLING, + .callbackFxn = NULL, + .timeout = SemaphoreP_WAIT_FOREVER, + .custom = NULL, +}; + +const AESCCM_Params AESCCM_defaultParams = { + .returnBehavior = AESCCM_RETURN_BEHAVIOR_POLLING, + .callbackFxn = NULL, + .timeout = SemaphoreP_WAIT_FOREVER, + .custom = NULL, +}; + +struct entropy_ctx { + int ret; + struct k_sem sem; + struct ring_buf pool; + uint8_t buffer[CONFIG_TI_CC35XX_HSM_ENTROPY_POOL_SIZE] __aligned(4); + struct k_work_delayable trng_work; +}; + +struct hsm_ti_cc35xx_data { + struct k_sem pool_lock; + struct k_sem operation_sem; + struct entropy_ctx entropy; +}; + +static int hsm_ti_cc35xx_get_hw_caps(const struct device *dev) +{ + return (CAP_RAW_KEY | CAP_SEPARATE_IO_BUFS | CAP_SYNC_OPS); +} + +static int hsm_ti_cc35xx_init_clock(void) +{ + uintptr_t key; + uint32_t hsm_reg_value; + uintptr_t hsm_reg_addr; + + key = irq_lock(); + + /* Disable HSM Clock */ + hsm_reg_addr = HSM_NON_SEC_BASE + HSM_NON_SEC_O_CLK_MEM_CTRL; + hsm_reg_value = sys_read32(hsm_reg_addr) & ~TI_CC35XX_HSM_CLK_MEM_CTRL_MSK; + sys_write32(hsm_reg_value, hsm_reg_addr); + + hsm_reg_addr = HSM_SEC_BASE + HSM_SEC_O_CLKCTL; + hsm_reg_value = sys_read32(hsm_reg_addr) & ~(HSM_SEC_CLKCTL_CLKGO_M | + HSM_SEC_CLKCTL_HIFCLKGO_M | + HSM_SEC_CLKCTL_CNTCLKGO_M); + sys_write32(hsm_reg_value, hsm_reg_addr); + + /* Initialize HSM Clock */ + hsm_reg_addr = HSM_NON_SEC_BASE + HSM_NON_SEC_O_CLK_MEM_CTRL; + hsm_reg_value = TI_CC35XX_HSM_CLK_MEM_CTRL_MSK; + sys_write32(hsm_reg_value, hsm_reg_addr); + + hsm_reg_addr = HSM_SEC_BASE + HSM_SEC_O_CLKCTL; + hsm_reg_value = sys_read32(hsm_reg_addr) | HSM_SEC_CLKCTL_CLKGO_EN | + HSM_SEC_CLKCTL_HIFCLKGO_EN | + HSM_SEC_CLKCTL_CNTCLKGO_EN; + sys_write32(hsm_reg_value, hsm_reg_addr); + + irq_unlock(key); + + return 0; +} + +static int hsm_ti_cc35xx_unlock_cpus(void) +{ + uintptr_t key; + uint32_t hsm_reg_value; + uintptr_t hsm_reg_addr; + + key = irq_lock(); + + /* Unlock CPUID0 and CPUID1 */ + hsm_reg_addr = HSMCRYPTO_BASE + HSMCRYPTO_O_MBLCKOUT; + hsm_reg_value = HSM_O_UNLOCK_CPUID0_CPUID1; + sys_write32(hsm_reg_value, hsm_reg_addr); + + irq_unlock(key); + + return 0; +} + +static int hsm_ti_cc35xx_init_mailbox(void) +{ + uintptr_t key; + uint32_t hsm_reg_value; + uintptr_t hsm_reg_addr; + + key = irq_lock(); + + /* Link mailbox */ + hsm_reg_addr = HSMCRYPTO_BASE + HSMCRYPTO_O_MBSTA; + hsm_reg_value = sys_read32(hsm_reg_addr) | HSMCRYPTO_MBCTL_MB1LNK_LNK; + hsm_reg_addr = HSMCRYPTO_BASE + HSMCRYPTO_O_MBCTL; + sys_write32(hsm_reg_value, hsm_reg_addr); + + /* Allow non-secure/secure access (Set bits 7 and 3 to 1 if we need secure access) */ + hsm_reg_addr = HSMCRYPTO_BASE + HSMCRYPTO_O_MBLNKID; + hsm_reg_value = (0 << HSM_MAILBOX_LINKID_LINKID1_S) | (0 << HSM_MAILBOX_LINKID_LINKID2_S) | + (0 << HSM_MAILBOX_LINKID_PROTACC1_S) | (0 << HSM_MAILBOX_LINKID_PORTACC2_S); + sys_write32(hsm_reg_value, hsm_reg_addr); + + /* Make sure CPU_ID=0 host can access mailbox 1 & 2 (no lockout) */ + hsm_reg_addr = HSMCRYPTO_BASE + HSMCRYPTO_O_MBLCKOUT; + hsm_reg_value = sys_read32(hsm_reg_addr) & HSM_O_CPUID0_MB1_MB2_UNLOCK; + sys_write32(hsm_reg_value, hsm_reg_addr); + + irq_unlock(key); + + return 0; +} + +static int hsm_ti_cc35xx_init_aic(void) +{ + Device_Handle_t gl_aic; + uintptr_t key; + + /* Initialize AIC for EIP130 */ + key = irq_lock(); + gl_aic = Device_Find("EIP130_AIC"); + if (gl_aic != NULL) { + /* + * Configure all sources for edge detect. Future improvement + * is to only enable the interrupts we need. We could also + * use EIP201_Config_Change(), but there is no adapter function() + */ + EIP201_SourceSettings_t settings = { + .Source = 0xFF, + .Config = EIP201_CONFIG_RISING_EDGE, + .fEnable = false /* enable source only when active */ + }; + EIP201_Initialize(gl_aic, &settings, 1); + } + + irq_unlock(key); + + return 0; +} + +static void hsm_ti_cc35xx_kick_trng(struct hsm_ti_cc35xx_data *data) +{ + TRNG_Handle trng_handle = NULL; + TRNG_Params trng_params; + TRNG_Config trng_config; + TRNGLPF3HSM_Object trng_object = {}; + TRNGLPF3HSM_HWAttrs trng_hw_attrs = {.intPriority = (~0)}; + uint8_t *ring_buf_dst; + size_t buffer_space; + + if (ring_buf_space_get(&data->entropy.pool) == 0) { + /* Entropy ring buffer is full. Refill not needed so far */ + return; + } else if (k_sem_take(&data->operation_sem, K_MSEC(HSM_OPERATION_SEM_TIMEOUT_MS)) != 0) { + return; + } + + TRNG_init(); + TRNG_Params_init(&trng_params); + trng_params.returnBehavior = TRNG_RETURN_BEHAVIOR_POLLING; + trng_config.object = &trng_object; + trng_config.hwAttrs = &trng_hw_attrs; + trng_handle = TRNG_construct(&trng_config, &trng_params); + buffer_space = + ring_buf_put_claim(&data->entropy.pool, &ring_buf_dst, HSM_RAW_RNG_BLOCK_SIZE); + TRNG_getRandomBytes(trng_handle, ring_buf_dst, buffer_space); + ring_buf_put_finish(&data->entropy.pool, buffer_space); + TRNG_close(trng_handle); + + k_sem_give(&data->entropy.sem); + k_sem_give(&data->operation_sem); + k_work_reschedule(&data->entropy.trng_work, K_MSEC(HSM_TRNG_RESCHEDULE_DELAY_MS)); +} + +static void hsm_ti_cc35xx_trng_work_handler(struct k_work *work) +{ + struct k_work_delayable *dwork = CONTAINER_OF(work, struct k_work_delayable, work); + + struct hsm_ti_cc35xx_data *data = + CONTAINER_OF(dwork, struct hsm_ti_cc35xx_data, entropy.trng_work); + hsm_ti_cc35xx_kick_trng(data); +} + +static int hsm_ti_cc35xx_get_entropy(const struct device *dev, uint8_t *buf, uint16_t len) +{ + struct hsm_ti_cc35xx_data *data = dev->data; + uint32_t cnt; + + while (len) { + k_sem_take(&data->pool_lock, K_FOREVER); + cnt = ring_buf_get(&data->entropy.pool, buf, len); + k_sem_give(&data->pool_lock); + + buf += cnt; + len -= cnt; + + if (cnt == 0) { + k_work_reschedule(&data->entropy.trng_work, K_NO_WAIT); + k_sem_take(&data->entropy.sem, K_FOREVER); + } + } + + k_work_reschedule(&data->entropy.trng_work, K_MSEC(HSM_TRNG_RESCHEDULE_DELAY_MS)); + + return 0; +} + +static int hsm_ti_cc35xx_do_crypto_aes_ecb(struct hsm_ti_cc35xx_data *data, + enum cipher_op op_type, struct cipher_ctx *ctx, + struct cipher_pkt *pkt) +{ + int result; + AESECB_Handle aesecb_handler = NULL; + AESECB_Config aesecb_config; + AESECBLPF3_Object aesecb_object = {}; + CryptoKey crypto_key; + AESECBLPF3_HWAttrs aesecb_hw_attrs = {.intPriority = (~0)}; + AESECB_Operation operation = {}; + const AESECB_Params *aesecb_params = &AESECB_defaultParams; + + if (ctx->key.bit_stream == NULL || pkt->in_buf == NULL || pkt->out_buf == NULL) { + return -EINVAL; + } + + AESECB_init(); + aesecb_config.object = &aesecb_object; + aesecb_config.hwAttrs = &aesecb_hw_attrs; + + aesecb_handler = AESECB_construct(&aesecb_config, aesecb_params); + + if (aesecb_handler == NULL) { + return -EIO; + } + + CryptoKeyPlaintextHSM_initKey(&crypto_key, (uint8_t *)ctx->key.bit_stream, ctx->keylen); + + operation.key = &crypto_key; + operation.input = pkt->in_buf; + operation.inputLength = pkt->in_len; + operation.output = pkt->out_buf; + + switch (op_type) { + case CRYPTO_CIPHER_OP_ENCRYPT: + result = AESECB_oneStepEncrypt(aesecb_handler, &operation); + break; + case CRYPTO_CIPHER_OP_DECRYPT: + result = AESECB_oneStepDecrypt(aesecb_handler, &operation); + break; + default: + result = AESECB_STATUS_FEATURE_NOT_SUPPORTED; + break; + } + + AESECB_close(aesecb_handler); + + return result == AESECB_STATUS_SUCCESS ? 0 : -EIO; +} + +static int hsm_ti_cc35xx_do_crypto_aes_ctr(struct hsm_ti_cc35xx_data *data, + enum cipher_op op_type, struct cipher_ctx *ctx, + struct cipher_pkt *pkt) +{ + int result; + struct hsm_ti_cc35xx_driver_session *session; + AESCTR_Handle aesctr_handler = NULL; + AESCTRLPF3_Object aesctr_object = {}; + AESCTR_Config aesctr_config; + AESCTR_Operation operation = {}; + CryptoKey crypto_key; + AESCTRLPF3_HWAttrs aesctr_hw_attrs = {.intPriority = (~0)}; + const AESCTR_Params *aesctr_params = &AESCTR_defaultParams; + + if (ctx->key.bit_stream == NULL || pkt->in_buf == NULL || pkt->out_buf == NULL || + ctx->drv_sessn_state == NULL) { + return -EINVAL; + } + session = ((struct hsm_ti_cc35xx_driver_session *)(ctx)->drv_sessn_state); + + AESCTR_init(); + aesctr_config.object = &aesctr_object; + aesctr_config.hwAttrs = &aesctr_hw_attrs; + + aesctr_handler = AESCTR_construct(&aesctr_config, aesctr_params); + + if (aesctr_handler == NULL) { + return -EIO; + } + + CryptoKeyPlaintextHSM_initKey(&crypto_key, (uint8_t *)ctx->key.bit_stream, ctx->keylen); + + operation.key = &crypto_key; + operation.input = pkt->in_buf; + operation.inputLength = pkt->in_len; + operation.output = pkt->out_buf; + + operation.initialCounter = session->ctr; + + switch (op_type) { + case CRYPTO_CIPHER_OP_ENCRYPT: + result = AESCTR_oneStepEncrypt(aesctr_handler, &operation); + break; + case CRYPTO_CIPHER_OP_DECRYPT: + result = AESCTR_oneStepDecrypt(aesctr_handler, &operation); + break; + default: + result = AESCTR_STATUS_FEATURE_NOT_SUPPORTED; + break; + } + + AESCTR_close(aesctr_handler); + + return result == AESCTR_STATUS_SUCCESS ? 0 : -EIO; +} + +static int hsm_ti_cc35xx_do_crypto_aes_ccm(struct hsm_ti_cc35xx_data *data, + enum cipher_op op_type, struct cipher_ctx *ctx, + struct cipher_aead_pkt *pkt) +{ + int result; + struct hsm_ti_cc35xx_driver_session *session; + AESCCM_Handle aesccm_handler = NULL; + AESCCMLPF3_Object aesccm_object = {}; + AESCCM_Config aesccm_config; + AESCCM_OneStepOperation operation = {}; + CryptoKey crypto_key; + AESCCMLPF3_HWAttrs aesccm_hw_attrs = {.intPriority = (~0)}; + const AESCCM_Params *aesccm_params = &AESCCM_defaultParams; + + if (ctx->key.bit_stream == NULL || pkt->pkt == NULL || pkt->pkt->in_buf == NULL || + pkt->pkt->out_buf == NULL || ctx->drv_sessn_state == NULL) { + return -EINVAL; + } + session = ((struct hsm_ti_cc35xx_driver_session *)(ctx)->drv_sessn_state); + + if (session->nonce == NULL) { + return -EINVAL; + } + + AESCCM_init(); + aesccm_config.object = &aesccm_object; + aesccm_config.hwAttrs = &aesccm_hw_attrs; + + aesccm_handler = AESCCM_construct(&aesccm_config, aesccm_params); + + if (aesccm_handler == NULL) { + return -EIO; + } + + CryptoKeyPlaintextHSM_initKey(&crypto_key, (uint8_t *)ctx->key.bit_stream, ctx->keylen); + + operation.key = &crypto_key; + operation.aad = pkt->ad; + operation.aadLength = pkt->ad_len; + operation.input = pkt->pkt->in_buf; + operation.output = pkt->pkt->out_buf; + operation.inputLength = pkt->pkt->in_len; + operation.nonce = session->nonce; + operation.nonceLength = ctx->mode_params.ccm_info.nonce_len; + operation.mac = pkt->tag; + operation.macLength = ctx->mode_params.ccm_info.tag_len; + + switch (op_type) { + case CRYPTO_CIPHER_OP_ENCRYPT: + result = AESCCM_oneStepEncrypt(aesccm_handler, &operation); + break; + case CRYPTO_CIPHER_OP_DECRYPT: + result = AESCCM_oneStepDecrypt(aesccm_handler, &operation); + break; + default: + result = AESCCM_STATUS_FEATURE_NOT_SUPPORTED; + break; + } + + AESCCM_close(aesccm_handler); + + return result == AESCCM_STATUS_SUCCESS ? 0 : -EIO; +} + +static int hsm_ti_cc35xx_do_crypto(const struct device *dev, enum cipher_algo algo, + enum cipher_mode mode, enum cipher_op op_type, + struct cipher_ctx *ctx, void *pkt) +{ + struct hsm_ti_cc35xx_data *data; + int result = 0; + struct cipher_pkt *cphr_pkt; + struct cipher_aead_pkt *aead_pkt; + + if (dev == NULL || dev->data == NULL || ctx == NULL || pkt == NULL) { + return -EINVAL; + } + + if (algo != CRYPTO_CIPHER_ALGO_AES) { + return -ENOTSUP; + } + + data = dev->data; + + /* Wait for HSM to be ready */ + if (k_sem_take(&data->operation_sem, K_MSEC(HSM_OPERATION_SEM_TIMEOUT_MS)) != 0) { + return -EBUSY; + } + + switch (mode) { + case CRYPTO_CIPHER_MODE_ECB: + cphr_pkt = (struct cipher_pkt *)pkt; + result = hsm_ti_cc35xx_do_crypto_aes_ecb(data, op_type, ctx, cphr_pkt); + break; + + case CRYPTO_CIPHER_MODE_CTR: + cphr_pkt = (struct cipher_pkt *)pkt; + result = hsm_ti_cc35xx_do_crypto_aes_ctr(data, op_type, ctx, cphr_pkt); + break; + + case CRYPTO_CIPHER_MODE_CCM: + aead_pkt = (struct cipher_aead_pkt *)pkt; + result = hsm_ti_cc35xx_do_crypto_aes_ccm(data, op_type, ctx, aead_pkt); + break; + + default: + result = -ENOTSUP; + } + + k_sem_give(&data->operation_sem); + + return result; +} + +static int hsm_ti_cc35xx_init(const struct device *dev) +{ + struct hsm_ti_cc35xx_data *data = dev->data; + + uint32_t result = HSMLPF3_STATUS_ERROR; + uint32_t token[] = {SYSTEMINFO_TOKEN_WORD0, CRYPTO_OFFICER_ID}; + + uint32_t idx, hsm_status, hsm_reg_value; + uintptr_t key, hsm_reg_addr; + + k_work_init_delayable(&data->entropy.trng_work, hsm_ti_cc35xx_trng_work_handler); + + /* Initialize ring buffer */ + ring_buf_init(&data->entropy.pool, sizeof(data->entropy.buffer), data->entropy.buffer); + + /* Initialize HSM clock and mailbox, then boot it */ + hsm_reg_addr = SOC_AON_BASE + SOC_AON_O_HSMCFG; + hsm_reg_value = sys_read32(hsm_reg_addr) | SOC_AON_HSMCFG_FIREWALL; + sys_write32(hsm_reg_value, hsm_reg_addr); + + hsm_ti_cc35xx_init_clock(); + hsm_ti_cc35xx_unlock_cpus(); + hsm_ti_cc35xx_init_mailbox(); + hsm_ti_cc35xx_init_aic(); + + key = irq_lock(); + + hsm_reg_addr = HSMCRYPTO_BASE + HSM_O_MODULE_STATUS; + hsm_status = sys_read32(hsm_reg_addr); + if ((hsm_status & HSM_MODULE_STATUS_FATALERR) == 0) { + /* + * At PRE_KERNEL_1 we don't use k_sleep() and other scheduling + * functions, so we use a busy wait loop here to wait for the + * input token to be processed inside the HSM. + * Based on experiments, it usually takes 0 cycles of the while loop + * to process the input token. + */ + hsm_reg_addr = HSMCRYPTO_BASE + HSMCRYPTO_O_MBSTA; + while ((sys_read32(hsm_reg_addr) & HSMCRYPTO_MBSTA_MB1IN_M) == + HSMCRYPTO_MBSTA_MB1IN_FULL) + ; + + /* Mailbox is empty so we can write the system info token to mbx1_in */ + for (idx = 0; idx < ARRAY_SIZE(token); idx++) { + hsm_reg_addr = HSMCRYPTO_BASE + HSMCRYPTO_O_MB1IN + idx * 4; + sys_write32(token[idx], hsm_reg_addr); + } + + /* Mark mbx1 in as full */ + hsm_reg_addr = HSMCRYPTO_BASE + HSMCRYPTO_O_MBCTL; + hsm_reg_value = HSMCRYPTO_MBCTL_MB1IN_FULL; + sys_write32(hsm_reg_value, hsm_reg_addr); + + /* + * At PRE_KERNEL_1 we don't use k_sleep() and other scheduling + * functions, so we use a busy wait loop here to wait for the + * output token to be available in mbx1_out. + * Based on experiments, it usually takes 12 cycles of the while loop + * to get response from HSM. + */ + hsm_reg_addr = HSMCRYPTO_BASE + HSMCRYPTO_O_MBSTA; + while ((sys_read32(hsm_reg_addr) & HSMCRYPTO_MBSTA_MB1OUT_M) != + HSMCRYPTO_MBSTA_MB1OUT_FULL) + ; + + /* Check for output token error */ + hsm_reg_addr = HSMCRYPTO_BASE + HSMCRYPTO_O_MB1OUT; + hsm_reg_value = sys_read32(hsm_reg_addr); + if ((hsm_reg_value & OUTPUT_TOKEN_ERROR) == 0) { + result = HSMLPF3_STATUS_SUCCESS; + } + + hsm_reg_addr = HSMCRYPTO_BASE + HSMCRYPTO_O_MBCTL; + hsm_reg_value = HSMCRYPTO_MBCTL_MB1OUT_EMTY; + sys_write32(hsm_reg_value, hsm_reg_addr); + } + + irq_unlock(key); + + if (result != HSMLPF3_STATUS_SUCCESS) { + return -EIO; + } + + if (HSMSAL_Init() != HSMSAL_SUCCESS) { + return -EIO; + } + + /* + * According to the CC35XX SDK: + * Reset of HSM, as well as HUK (Hardware Unique Key) provisioning on CC35XX, is performed + * at boot time by the TI Device boot loader. As a result, HUK provisioning is not needed. + */ + + key = irq_lock(); + NVIC_ClearPendingIRQ(DT_INST_IRQN(0)); + irq_unlock(key); + + k_work_reschedule(&data->entropy.trng_work, K_MSEC(HSM_TRNG_RESCHEDULE_DELAY_MS)); + + return 0; +} + +static struct hsm_ti_cc35xx_driver_api hsm_ti_cc35xx_driver_api = { + .get_entropy = hsm_ti_cc35xx_get_entropy, + .do_crypto = hsm_ti_cc35xx_do_crypto, + .get_hw_caps = hsm_ti_cc35xx_get_hw_caps, +}; + +static struct hsm_ti_cc35xx_data hsm_ti_cc35xx_data = { + .pool_lock = Z_SEM_INITIALIZER(hsm_ti_cc35xx_data.pool_lock, 1, 1), + .operation_sem = Z_SEM_INITIALIZER(hsm_ti_cc35xx_data.operation_sem, 1, 1), + .entropy.sem = Z_SEM_INITIALIZER(hsm_ti_cc35xx_data.entropy.sem, 0, 1), +}; + +DEVICE_DT_INST_DEFINE(0, hsm_ti_cc35xx_init, PM_DEVICE_DT_INST_GET(0), &hsm_ti_cc35xx_data, NULL, + PRE_KERNEL_1, CONFIG_TI_CC35XX_HSM_INIT_PRIORITY, + &hsm_ti_cc35xx_driver_api); diff --git a/dts/arm/ti/cc35xxe.dtsi b/dts/arm/ti/cc35xxe.dtsi index 56a996b544d3..b3063ba93d5f 100644 --- a/dts/arm/ti/cc35xxe.dtsi +++ b/dts/arm/ti/cc35xxe.dtsi @@ -276,7 +276,20 @@ compatible = "ti,cc35xx-hsm"; interrupts = ; reg = <0x41b00000 0x100000>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; + + entropy: entropy@0 { + compatible = "ti,cc35xx-hsm-trng"; + reg = <0>; + status = "disabled"; + }; + crypto: crypto@1 { + compatible = "ti,cc35xx-hsm-crypto"; + reg = <1>; + status = "disabled"; + }; }; pinctrl: pin-controller@41140000 { diff --git a/dts/bindings/rng/ti,cc35xx-hsm.yaml b/dts/bindings/crypto/ti,cc35xx-hsm-crypto.yaml similarity index 55% rename from dts/bindings/rng/ti,cc35xx-hsm.yaml rename to dts/bindings/crypto/ti,cc35xx-hsm-crypto.yaml index cb18bc7c11b2..85504d473038 100644 --- a/dts/bindings/rng/ti,cc35xx-hsm.yaml +++ b/dts/bindings/crypto/ti,cc35xx-hsm-crypto.yaml @@ -1,8 +1,8 @@ # Copyright (c) 2025 Conclusive Engineering Sp. z o.o. # SPDX-License-Identifier: Apache-2.0 -description: TI SimpleLink CC35xxE HSM (Hardware Security Module) +description: TI SimpleLink CC35xx HSM Crypto -compatible: "ti,cc35xx-hsm" +compatible: "ti,cc35xx-hsm-crypto" include: base.yaml diff --git a/dts/bindings/misc/ti,cc35xx-hsm.yaml b/dts/bindings/misc/ti,cc35xx-hsm.yaml new file mode 100644 index 000000000000..e48ba4bb38ce --- /dev/null +++ b/dts/bindings/misc/ti,cc35xx-hsm.yaml @@ -0,0 +1,14 @@ +# Copyright (c) 2025 Conclusive Engineering Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +description: TI SimpleLink CC35xx HSM (Hardware Security Module) + +compatible: "ti,cc35xx-hsm" + +include: base.yaml + +properties: + "#address-cells": + const: 1 + "#size-cells": + const: 0 diff --git a/dts/bindings/rng/ti,cc35xx-hsm-trng.yaml b/dts/bindings/rng/ti,cc35xx-hsm-trng.yaml new file mode 100644 index 000000000000..e84fa5a8eebc --- /dev/null +++ b/dts/bindings/rng/ti,cc35xx-hsm-trng.yaml @@ -0,0 +1,12 @@ +# Copyright (c) 2025 Conclusive Engineering Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +description: TI SimpleLink CC35xx HSM TRNG / Entropy + +compatible: "ti,cc35xx-hsm-trng" + +# properties: +# reg: +# required: true +# type: array +# description: Index of the HSM subsystem to use for entropy. diff --git a/include/zephyr/drivers/misc/ti_cc35xx_hsm/ti_cc35xx_hsm.h b/include/zephyr/drivers/misc/ti_cc35xx_hsm/ti_cc35xx_hsm.h new file mode 100644 index 000000000000..ba67432d1ceb --- /dev/null +++ b/include/zephyr/drivers/misc/ti_cc35xx_hsm/ti_cc35xx_hsm.h @@ -0,0 +1,33 @@ +#ifndef DEVICE_TI_CC35XX_HSM_H_ +#define DEVICE_TI_CC35XX_HSM_H_ + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define HSM_AES_BLOCK_SIZE 16U + +struct hsm_ti_cc35xx_driver_session { + union { + uint8_t key[HSM_AES_BLOCK_SIZE]; + uint8_t ctr[HSM_AES_BLOCK_SIZE]; + }; + uint8_t *nonce; +}; + +__subsystem struct hsm_ti_cc35xx_driver_api { + int (*get_entropy)(const struct device *dev, uint8_t *buf, uint16_t len); + int (*do_crypto)(const struct device *dev, enum cipher_algo algo, enum cipher_mode mode, + enum cipher_op op_type, struct cipher_ctx *ctx, void *pkt); + int (*get_hw_caps)(const struct device *dev); +}; + +#ifdef __cplusplus +} +#endif + +#endif /* DEVICE_TI_CC35XX_HSM_H_ */ diff --git a/samples/drivers/crypto/boards/lp_em_cc35x1.overlay b/samples/drivers/crypto/boards/lp_em_cc35x1.overlay new file mode 100644 index 000000000000..518784250ef4 --- /dev/null +++ b/samples/drivers/crypto/boards/lp_em_cc35x1.overlay @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Conclusive Engineering Sp. z o.o. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&crypto { + status = "okay"; +}; diff --git a/samples/drivers/crypto/src/main.c b/samples/drivers/crypto/src/main.c index ea2952ec32f7..525726dd1813 100644 --- a/samples/drivers/crypto/src/main.c +++ b/samples/drivers/crypto/src/main.c @@ -47,6 +47,8 @@ LOG_MODULE_REGISTER(main); #define CRYPTO_DEV_COMPAT ti_mspm0_aes #elif CONFIG_CRYPTO_MSPM0_AES_ADV #define CRYPTO_DEV_COMPAT ti_mspm0_aes_adv +#elif DT_HAS_COMPAT_STATUS_OKAY(ti_cc35xx_hsm_crypto) +#define CRYPTO_DEV_COMPAT ti_cc35xx_hsm_crypto #else #error "You need to enable one crypto device" #endif From 0ab877ee589db1d92894fb82fbf88be04937bed2 Mon Sep 17 00:00:00 2001 From: Artur Rojek Date: Mon, 9 Feb 2026 19:05:14 +0100 Subject: [PATCH 046/100] UPSTREAM-PEND: crypto: cc35xx: update HAL usage Amend HAL usage after update to SDK 9.21. Signed-off-by: Artur Rojek --- drivers/misc/ti_cc35xx_hsm/ti_cc35xx_hsm.c | 50 ++++++++++------------ 1 file changed, 23 insertions(+), 27 deletions(-) diff --git a/drivers/misc/ti_cc35xx_hsm/ti_cc35xx_hsm.c b/drivers/misc/ti_cc35xx_hsm/ti_cc35xx_hsm.c index d911242af4db..be3975c34ad4 100644 --- a/drivers/misc/ti_cc35xx_hsm/ti_cc35xx_hsm.c +++ b/drivers/misc/ti_cc35xx_hsm/ti_cc35xx_hsm.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include @@ -38,17 +38,17 @@ #define HSM_O_CPUID0_MB1_MB2_UNLOCK 0xFFFFFF77 #define HSMCRYPTO_BASE HSM_BASE -#define HSMCRYPTO_O_MBSTA HSM_O_MAILBOX_STAT -#define HSMCRYPTO_MBSTA_MB1IN_M HSM_MAILBOX_STAT_INFULL1 -#define HSMCRYPTO_MBSTA_MB1IN_FULL HSM_MAILBOX_STAT_INFULL1 +#define HSMCRYPTO_O_MBSTA HSM_O_MBXSTA +#define HSMCRYPTO_MBSTA_MB1IN_M HSM_MBXSTA_INFULL1 +#define HSMCRYPTO_MBSTA_MB1IN_FULL HSM_MBXSTA_INFULL1 #define HSMCRYPTO_O_MB1IN HSM_O_EIP130_072_MAILBOX1_IN #define HSMCRYPTO_O_MBCTL HSM_O_MBXCTL #define HSMCRYPTO_MBCTL_MB1IN_FULL HSM_MBXCTL_INFULL1 #define HSMCRYPTO_MBCTL_MB1LNK_LNK HSM_MBXCTL_LINK1 -#define HSMCRYPTO_O_MBLNKID HSM_O_MAILBOX_LINKID -#define HSMCRYPTO_O_MBLCKOUT HSM_O_MAILBOX_LOCKOUT -#define HSMCRYPTO_MBSTA_MB1OUT_M HSM_MAILBOX_STAT_OUTFULL1 -#define HSMCRYPTO_MBSTA_MB1OUT_FULL HSM_MAILBOX_STAT_OUTFULL1 +#define HSMCRYPTO_O_MBLNKID HSM_O_MBXLINKID +#define HSMCRYPTO_O_MBLCKOUT HSM_O_MBXLCKOUT +#define HSMCRYPTO_MBSTA_MB1OUT_M HSM_MBXSTA_OUTFULL1 +#define HSMCRYPTO_MBSTA_MB1OUT_FULL HSM_MBXSTA_OUTFULL1 #define HSMCRYPTO_O_MB1OUT HSM_O_EIP130_072_MAILBOX1_IN #define HSMCRYPTO_MBCTL_MB1OUT_EMTY HSM_MBXCTL_OUTEMP1 @@ -174,8 +174,8 @@ static int hsm_ti_cc35xx_init_mailbox(void) /* Allow non-secure/secure access (Set bits 7 and 3 to 1 if we need secure access) */ hsm_reg_addr = HSMCRYPTO_BASE + HSMCRYPTO_O_MBLNKID; - hsm_reg_value = (0 << HSM_MAILBOX_LINKID_LINKID1_S) | (0 << HSM_MAILBOX_LINKID_LINKID2_S) | - (0 << HSM_MAILBOX_LINKID_PROTACC1_S) | (0 << HSM_MAILBOX_LINKID_PORTACC2_S); + hsm_reg_value = (0 << HSM_MBXLINKID_LINKID1_S) | (0 << HSM_MBXLINKID_LINKID2_S) | + (0 << HSM_MBXLINKID_PROTACC1_S) | (0 << HSM_MBXLINKID_PORTACC2_S); sys_write32(hsm_reg_value, hsm_reg_addr); /* Make sure CPU_ID=0 host can access mailbox 1 & 2 (no lockout) */ @@ -220,8 +220,8 @@ static void hsm_ti_cc35xx_kick_trng(struct hsm_ti_cc35xx_data *data) TRNG_Handle trng_handle = NULL; TRNG_Params trng_params; TRNG_Config trng_config; - TRNGLPF3HSM_Object trng_object = {}; - TRNGLPF3HSM_HWAttrs trng_hw_attrs = {.intPriority = (~0)}; + TRNGXXF3HSM_Object trng_object = {}; + TRNGXXF3HSM_HWAttrs trng_hw_attrs = {}; uint8_t *ring_buf_dst; size_t buffer_space; @@ -289,9 +289,9 @@ static int hsm_ti_cc35xx_do_crypto_aes_ecb(struct hsm_ti_cc35xx_data *data, int result; AESECB_Handle aesecb_handler = NULL; AESECB_Config aesecb_config; - AESECBLPF3_Object aesecb_object = {}; + AESECBXXF3_Object aesecb_object = {}; CryptoKey crypto_key; - AESECBLPF3_HWAttrs aesecb_hw_attrs = {.intPriority = (~0)}; + AESECBXXF3_HWAttrs aesecb_hw_attrs = {.intPriority = (~0)}; AESECB_Operation operation = {}; const AESECB_Params *aesecb_params = &AESECB_defaultParams; @@ -340,11 +340,11 @@ static int hsm_ti_cc35xx_do_crypto_aes_ctr(struct hsm_ti_cc35xx_data *data, int result; struct hsm_ti_cc35xx_driver_session *session; AESCTR_Handle aesctr_handler = NULL; - AESCTRLPF3_Object aesctr_object = {}; + AESCTRXXF3_Object aesctr_object = {}; AESCTR_Config aesctr_config; AESCTR_Operation operation = {}; CryptoKey crypto_key; - AESCTRLPF3_HWAttrs aesctr_hw_attrs = {.intPriority = (~0)}; + AESCTRXXF3_HWAttrs aesctr_hw_attrs = {.intPriority = (~0)}; const AESCTR_Params *aesctr_params = &AESCTR_defaultParams; if (ctx->key.bit_stream == NULL || pkt->in_buf == NULL || pkt->out_buf == NULL || @@ -396,11 +396,11 @@ static int hsm_ti_cc35xx_do_crypto_aes_ccm(struct hsm_ti_cc35xx_data *data, int result; struct hsm_ti_cc35xx_driver_session *session; AESCCM_Handle aesccm_handler = NULL; - AESCCMLPF3_Object aesccm_object = {}; + AESCCMXXF3_Object aesccm_object = {}; AESCCM_Config aesccm_config; AESCCM_OneStepOperation operation = {}; CryptoKey crypto_key; - AESCCMLPF3_HWAttrs aesccm_hw_attrs = {.intPriority = (~0)}; + AESCCMXXF3_HWAttrs aesccm_hw_attrs = {.intPriority = (~0)}; const AESCCM_Params *aesccm_params = &AESCCM_defaultParams; if (ctx->key.bit_stream == NULL || pkt->pkt == NULL || pkt->pkt->in_buf == NULL || @@ -506,7 +506,7 @@ static int hsm_ti_cc35xx_init(const struct device *dev) { struct hsm_ti_cc35xx_data *data = dev->data; - uint32_t result = HSMLPF3_STATUS_ERROR; + uint32_t result = HSMXXF3_STATUS_ERROR; uint32_t token[] = {SYSTEMINFO_TOKEN_WORD0, CRYPTO_OFFICER_ID}; uint32_t idx, hsm_status, hsm_reg_value; @@ -518,10 +518,6 @@ static int hsm_ti_cc35xx_init(const struct device *dev) ring_buf_init(&data->entropy.pool, sizeof(data->entropy.buffer), data->entropy.buffer); /* Initialize HSM clock and mailbox, then boot it */ - hsm_reg_addr = SOC_AON_BASE + SOC_AON_O_HSMCFG; - hsm_reg_value = sys_read32(hsm_reg_addr) | SOC_AON_HSMCFG_FIREWALL; - sys_write32(hsm_reg_value, hsm_reg_addr); - hsm_ti_cc35xx_init_clock(); hsm_ti_cc35xx_unlock_cpus(); hsm_ti_cc35xx_init_mailbox(); @@ -529,9 +525,9 @@ static int hsm_ti_cc35xx_init(const struct device *dev) key = irq_lock(); - hsm_reg_addr = HSMCRYPTO_BASE + HSM_O_MODULE_STATUS; + hsm_reg_addr = HSMCRYPTO_BASE + HSM_O_MODULESTA; hsm_status = sys_read32(hsm_reg_addr); - if ((hsm_status & HSM_MODULE_STATUS_FATALERR) == 0) { + if ((hsm_status & HSM_MODULESTA_FATALERR) == 0) { /* * At PRE_KERNEL_1 we don't use k_sleep() and other scheduling * functions, so we use a busy wait loop here to wait for the @@ -571,7 +567,7 @@ static int hsm_ti_cc35xx_init(const struct device *dev) hsm_reg_addr = HSMCRYPTO_BASE + HSMCRYPTO_O_MB1OUT; hsm_reg_value = sys_read32(hsm_reg_addr); if ((hsm_reg_value & OUTPUT_TOKEN_ERROR) == 0) { - result = HSMLPF3_STATUS_SUCCESS; + result = HSMXXF3_STATUS_SUCCESS; } hsm_reg_addr = HSMCRYPTO_BASE + HSMCRYPTO_O_MBCTL; @@ -581,7 +577,7 @@ static int hsm_ti_cc35xx_init(const struct device *dev) irq_unlock(key); - if (result != HSMLPF3_STATUS_SUCCESS) { + if (result != HSMXXF3_STATUS_SUCCESS) { return -EIO; } From 5a47ca891f06acc1def606d219acb7e919a5f368 Mon Sep 17 00:00:00 2001 From: Jakub Jarosinski Date: Mon, 6 Jul 2026 16:18:54 +0200 Subject: [PATCH 047/100] UPSTREAM-PEND: tests: crypto: enable AES test on CC35xx Add the CC35xx HSM crypto device to the AES test platform list so the hardware-backed crypto path is covered. Signed-off-by: Jakub Jarosinski --- tests/crypto/crypto_aes/src/main.c | 2 ++ tests/crypto/crypto_aes/testcase.yaml | 1 + 2 files changed, 3 insertions(+) diff --git a/tests/crypto/crypto_aes/src/main.c b/tests/crypto/crypto_aes/src/main.c index c7425eeda42e..95a16e90827c 100644 --- a/tests/crypto/crypto_aes/src/main.c +++ b/tests/crypto/crypto_aes/src/main.c @@ -22,6 +22,8 @@ #define CRYPTO_DEV_COMPAT st_stm32_cryp #elif DT_HAS_COMPAT_STATUS_OKAY(bflb_sec_eng_aes) #define CRYPTO_DEV_COMPAT bflb_sec_eng_aes +#elif DT_HAS_COMPAT_STATUS_OKAY(ti_cc35xx_hsm_crypto) +#define CRYPTO_DEV_COMPAT ti_cc35xx_hsm_crypto #else #error "You need to enable one crypto device" #endif diff --git a/tests/crypto/crypto_aes/testcase.yaml b/tests/crypto/crypto_aes/testcase.yaml index e2194866963c..4bfc457a3315 100644 --- a/tests/crypto/crypto_aes/testcase.yaml +++ b/tests/crypto/crypto_aes/testcase.yaml @@ -17,4 +17,5 @@ tests: - nucleo_h753zi - sama7g54_ek - sf32lb52_devkit_lcd + - lp_em_cc35x1 tags: crypto From aa2ab18cf5d7b382e3608a09113ed36dc052843c Mon Sep 17 00:00:00 2001 From: Jakub Jarosinski Date: Mon, 6 Jul 2026 17:14:15 +0200 Subject: [PATCH 048/100] UPSTREAM-PEND: drivers: counter: cc35xx: fix generic API test Include the CC35xx LGPT compatible in the generic counter device discovery used by the basic API test. Signed-off-by: Jakub Jarosinski --- drivers/counter/counter_cc35xx_lgpt.c | 67 +++++++++++++------ .../counter_basic_api/src/test_counter.c | 1 + 2 files changed, 46 insertions(+), 22 deletions(-) diff --git a/drivers/counter/counter_cc35xx_lgpt.c b/drivers/counter/counter_cc35xx_lgpt.c index 79137d4617b4..591c1df93fa1 100644 --- a/drivers/counter/counter_cc35xx_lgpt.c +++ b/drivers/counter/counter_cc35xx_lgpt.c @@ -19,7 +19,7 @@ #define TI_CC35XX_COUNTER_CHANNELS 4 #define TI_CC35XX_CXCFG \ - (GPTIMER_C0CFG_EDGE_RISE | GPTIMER_C0CFG_INPUT_EV | GPTIMER_C0CFG_CCACT_TGL_ON_CMP) + (GPTIMER_C0CFG_EDGE_RISE | GPTIMER_C0CFG_INPUT_EV | GPTIMER_C0CFG_CCACT_TGL_ON_CMP_DIS) #define TI_CC35XX_CHAN_DISABLE 0 #define TI_CC35XX_CNTR_START 0x01 #define TI_CC35XX_CNTR_STOP 0x00 @@ -54,14 +54,13 @@ static int counter_cc35xx_gptimer_get_value(const struct device *dev, uint32_t * static void counter_cc35xx_gptimer_isr(const struct device *dev) { const struct counter_cc35xx_gptimer_config *config = dev->config; - const struct counter_cc35xx_gptimer_data *data = dev->data; + struct counter_cc35xx_gptimer_data *data = dev->data; uint32_t counter = sys_read32(config->base + GPTIMER_O_CNTR); uint32_t reg_ris = sys_read32(config->base + GPTIMER_O_RIS); uint32_t reg_mis = sys_read32(config->base + GPTIMER_O_MIS); int i; sys_write32(reg_ris, config->base + GPTIMER_O_ICLR); - sys_write32(reg_mis, config->base + GPTIMER_O_IMCLR); if ((reg_mis & GPTIMER_MIS_TGT) && data->target_cfg.callback) { data->target_cfg.callback(dev, data->target_cfg.user_data); @@ -69,8 +68,15 @@ static void counter_cc35xx_gptimer_isr(const struct device *dev) for (i = 0; i < TI_CC35XX_COUNTER_CHANNELS; i++) { if ((reg_mis & GPTIMER_MIS_C0CC << i) && data->alarm_cfg[i].callback) { - data->alarm_cfg[i].callback(dev, i, counter, - data->alarm_cfg[i].user_data); + counter_alarm_callback_t callback = data->alarm_cfg[i].callback; + void *user_data = data->alarm_cfg[i].user_data; + + data->alarm_cfg[i].flags = 0; + data->alarm_cfg[i].ticks = 0; + data->alarm_cfg[i].callback = NULL; + data->alarm_cfg[i].user_data = NULL; + + callback(dev, i, counter, user_data); } } } @@ -89,23 +95,28 @@ static int counter_cc35xx_gptimer_set_alarm(const struct device *dev, uint8_t ch const struct counter_cc35xx_gptimer_config *config = dev->config; struct counter_cc35xx_gptimer_data *data = dev->data; uint32_t ticks = alarm_cfg->ticks; + uint32_t top = sys_read32(config->base + GPTIMER_O_TGTNC); if (chan_id >= TI_CC35XX_COUNTER_CHANNELS) { + return -ENOTSUP; + } + + if (ticks > top) { return -EINVAL; } /* * Capture compare register always compares against the absolute value * of the counter register. - * In order to handle alarms relative to the current counter value, - * increment the ticks appropriately. */ if (!(alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE)) { - ticks += sys_read32(config->base + GPTIMER_O_CNTR); - } + uint64_t absolute_ticks = (uint64_t)sys_read32(config->base + GPTIMER_O_CNTR) + ticks; + + if (top != UINT32_MAX) { + absolute_ticks %= (uint64_t)top + 1U; + } - if (ticks > config->counter_info.max_top_value) { - return -ERANGE; + ticks = (uint32_t)absolute_ticks; } sys_write32(GPTIMER_IMSET_CXCC_SET(chan_id), config->base + GPTIMER_O_IMSET); @@ -126,7 +137,7 @@ static int counter_cc35xx_gptimer_cancel_alarm(const struct device *dev, uint8_t struct counter_cc35xx_gptimer_data *data = dev->data; if (chan_id >= TI_CC35XX_COUNTER_CHANNELS) { - return -EINVAL; + return -ENOTSUP; } sys_write32(GPTIMER_IMCLR_CXCC_CLR(chan_id), config->base + GPTIMER_O_IMCLR); @@ -153,24 +164,36 @@ static int counter_cc35xx_gptimer_set_top_value(const struct device *dev, { const struct counter_cc35xx_gptimer_config *config = dev->config; struct counter_cc35xx_gptimer_data *data = dev->data; + uint32_t current = sys_read32(config->base + GPTIMER_O_CNTR); - /* If running return -EBUSY */ - if (sys_read32(config->base + GPTIMER_O_STARTCFG)) { - return -EBUSY; + for (uint8_t chan_id = 0; chan_id < TI_CC35XX_COUNTER_CHANNELS; chan_id++) { + if (data->alarm_cfg[chan_id].callback != NULL) { + return -EBUSY; + } } if (cfg->ticks > config->counter_info.max_top_value) { return -EINVAL; } - if (cfg->flags & COUNTER_TOP_CFG_DONT_RESET) { - return -ENOTSUP; + if ((cfg->flags & COUNTER_TOP_CFG_DONT_RESET) && (cfg->ticks < current)) { + if (cfg->flags & COUNTER_TOP_CFG_RESET_WHEN_LATE) { + sys_write32(sys_read32(config->base + GPTIMER_O_CTL) & ~GPTIMER_CTL_MODE_M, + config->base + GPTIMER_O_CTL); + } else { + return -ETIME; + } + } + + if (cfg->callback != NULL) { + sys_write32(GPTIMER_IMSET_TGT_SET, config->base + GPTIMER_O_IMSET); + } else { + sys_write32(GPTIMER_IMCLR_TGT_CLR, config->base + GPTIMER_O_IMCLR); } - sys_write32(GPTIMER_IMSET_TGT_SET, config->base + GPTIMER_O_IMSET); - sys_write32(cfg->ticks, config->base + GPTIMER_O_TGT); + sys_write32(cfg->ticks, config->base + GPTIMER_O_TGTNC); - data->target_cfg.flags = 0; + data->target_cfg.flags = cfg->flags; data->target_cfg.ticks = cfg->ticks; data->target_cfg.callback = cfg->callback; data->target_cfg.user_data = cfg->user_data; @@ -190,8 +213,8 @@ static int counter_cc35xx_gptimer_start(const struct device *dev) const struct counter_cc35xx_gptimer_config *config = dev->config; uint32_t reg = sys_read32(config->base + GPTIMER_O_CTL); - /* Zephyr uses single-shot alarms. */ - sys_write32(reg | GPTIMER_CTL_MODE_UP_ONCE, config->base + GPTIMER_O_CTL); + sys_write32((reg & ~GPTIMER_CTL_MODE_M) | GPTIMER_CTL_MODE_UP_PER, + config->base + GPTIMER_O_CTL); sys_write32(TI_CC35XX_CNTR_START, config->base + GPTIMER_O_STARTCFG); diff --git a/tests/drivers/counter/counter_basic_api/src/test_counter.c b/tests/drivers/counter/counter_basic_api/src/test_counter.c index 308f8b20fcb9..9e3b9984fe09 100644 --- a/tests/drivers/counter/counter_basic_api/src/test_counter.c +++ b/tests/drivers/counter/counter_basic_api/src/test_counter.c @@ -202,6 +202,7 @@ static const struct device *const devices[] = { #ifdef CONFIG_COUNTER_MSPM0_TIMER DEVS_FOR_DT_COMPAT(ti_mspm0_timer_counter) #endif + DEVS_FOR_DT_COMPAT(ti_cc35xx_lgpt) }; static const struct device *const period_devs[] = { From e12873d60e62392a7fd38d81c9f3e41c77d07102 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=81yszczek?= Date: Thu, 28 Aug 2025 09:52:57 +0200 Subject: [PATCH 049/100] UPSTREAM-PEND: drivers: adc: cc35xxe: add ADC driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add ADC driver for cc35xxe chip Signed-off-by: Michał Łyszczek --- boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml | 1 + .../lp_em_cc35x1_cc3501e_defconfig | 4 + .../ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi | 28 ++ drivers/adc/CMakeLists.txt | 1 + drivers/adc/Kconfig | 1 + drivers/adc/Kconfig.cc35xx | 8 + drivers/adc/adc_cc35xx.c | 321 ++++++++++++++++++ drivers/adc/adc_shell.c | 178 +++++----- drivers/pinctrl/pinctrl_ti_cc35xx.c | 10 + dts/arm/ti/cc35xxe.dtsi | 12 + dts/bindings/adc/ti,cc35xx-adc.yaml | 27 ++ 11 files changed, 489 insertions(+), 102 deletions(-) create mode 100644 drivers/adc/Kconfig.cc35xx create mode 100644 drivers/adc/adc_cc35xx.c create mode 100644 dts/bindings/adc/ti,cc35xx-adc.yaml diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml b/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml index b0ddfda26d63..d753d7d6d107 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1.yaml @@ -8,6 +8,7 @@ toolchain: - zephyr - gnuarmemb supported: + - adc - counter - entropy - gpio diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3501e_defconfig b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3501e_defconfig index 71bcdc300bf5..6e752065d4da 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3501e_defconfig +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_cc3501e_defconfig @@ -35,6 +35,10 @@ CONFIG_SPI_SHELL=y CONFIG_DMA=y +CONFIG_ADC=y +CONFIG_ADC_CC35XX=y +CONFIG_ADC_SHELL=y + CONFIG_I2C=y CONFIG_I2C_CC35XX=y CONFIG_I2C_SHELL=y diff --git a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi index 96248ccf82b3..0e71a3bcb31c 100644 --- a/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi +++ b/boards/ti/lp_em_cc35x1/lp_em_cc35x1_common.dtsi @@ -7,6 +7,7 @@ /dts-v1/; #include +#include #include #include #include "boosterpack_connector.dtsi" @@ -17,6 +18,10 @@ model = "TI CC35X1E LaunchPad"; compatible = "ti,launchpad-cc35x1e"; + zephyr,user { + io-channels = <&adc0 4>, <&adc0 5>; + }; + chosen { zephyr,sram = &dmem_ns; zephyr,flash = &extflash; @@ -68,6 +73,7 @@ ambient-temp0 = &tmp1075_temperature; sw0 = &user_switch_1; sw1 = &user_switch_2; + adc0 = &adc0; dma0 = &dma; rtc = &rtc; }; @@ -200,6 +206,28 @@ }; }; +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; + + channel@4 { + reg = <0x4>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + channel@5 { + reg = <0x5>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; +}; + &uart0 { status = "okay"; pinctrl-0 = <&uart0_default>; diff --git a/drivers/adc/CMakeLists.txt b/drivers/adc/CMakeLists.txt index 6723094cb4ec..a9932d37b1fe 100644 --- a/drivers/adc/CMakeLists.txt +++ b/drivers/adc/CMakeLists.txt @@ -28,6 +28,7 @@ zephyr_library_sources_ifdef(CONFIG_ADC_BFLB adc_bflb.c) zephyr_library_sources_ifdef(CONFIG_ADC_CC13XX_CC26XX adc_cc13xx_cc26xx.c) zephyr_library_sources_ifdef(CONFIG_ADC_CC23X0 adc_cc23x0.c) zephyr_library_sources_ifdef(CONFIG_ADC_CC32XX adc_cc32xx.c) +zephyr_library_sources_ifdef(CONFIG_ADC_CC35XX adc_cc35xx.c) zephyr_library_sources_ifdef(CONFIG_ADC_CH32V00X adc_ch32v00x.c) zephyr_library_sources_ifdef(CONFIG_ADC_EMUL adc_emul.c) zephyr_library_sources_ifdef(CONFIG_ADC_ENE_KB106X adc_ene_kb106x.c) diff --git a/drivers/adc/Kconfig b/drivers/adc/Kconfig index c0c82f726aeb..53c83cfd6c15 100644 --- a/drivers/adc/Kconfig +++ b/drivers/adc/Kconfig @@ -116,6 +116,7 @@ source "drivers/adc/Kconfig.bflb" source "drivers/adc/Kconfig.cc13xx_cc26xx" source "drivers/adc/Kconfig.cc23x0" source "drivers/adc/Kconfig.cc32xx" +source "drivers/adc/Kconfig.cc35xx" source "drivers/adc/Kconfig.ch32v00x" source "drivers/adc/Kconfig.ene" source "drivers/adc/Kconfig.esp32" diff --git a/drivers/adc/Kconfig.cc35xx b/drivers/adc/Kconfig.cc35xx new file mode 100644 index 000000000000..2efa90631b27 --- /dev/null +++ b/drivers/adc/Kconfig.cc35xx @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +config ADC_CC35XX + bool "CC35XX ADC driver" + default y + depends on DT_HAS_TI_CC35XX_ADC_ENABLED + help + This option enables the CC35XX ADC driver. diff --git a/drivers/adc/adc_cc35xx.c b/drivers/adc/adc_cc35xx.c new file mode 100644 index 000000000000..6850e7f4d8bf --- /dev/null +++ b/drivers/adc/adc_cc35xx.c @@ -0,0 +1,321 @@ +/* + * Copyright (c) 2025 Conclusive Engineering Sp. z o.o. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT ti_cc35xx_adc + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Driverlib includes */ +#include +#include +#include + +#define CC35XX_CHAN_COUNT 16 +/* hardware supports MEMCTL0..5 for sequence */ +#define CC35XX_SEQUENCE_MAX 6 + +#define ADC_CONTEXT_USES_KERNEL_TIMER +#include "adc_context.h" + +#define LOG_LEVEL CONFIG_ADC_LOG_LEVEL +LOG_MODULE_REGISTER(adc_cc35xx); + +#define ADC_INT_CHAN_MASK \ + (ADC_INT_MEMRES_00 | ADC_INT_MEMRES_01 | ADC_INT_MEMRES_02 | ADC_INT_MEMRES_03 | \ + ADC_INT_MEMRES_04 | ADC_INT_MEMRES_05 | ADC_INT_MEMRES_06 | ADC_INT_MEMRES_07 | \ + ADC_INT_MEMRES_08 | ADC_INT_MEMRES_09 | ADC_INT_MEMRES_10 | ADC_INT_MEMRES_11 | \ + ADC_INT_MEMRES_12 | ADC_INT_MEMRES_13 | ADC_INT_MEMRES_14 | ADC_INT_MEMRES_15) + +#define ADC_INT_ALL \ + (ADC_INT_UVIFG | ADC_INT_DMADONE | ADC_INT_INIFG | ADC_INT_LOWIFG | ADC_INT_HIGHIFG | \ + ADC_INT_TOVIFG | ADC_INT_OVIFG | ADC_INT_CHAN_MASK) + +struct adc_cc35xx_data { + struct adc_context ctx; + const struct device *dev; + uint16_t *buffer; + uint16_t *repeat_buffer; + uint32_t channels; + struct { + int vref; + } channel_config[CC35XX_CHAN_COUNT]; + size_t active_channels; + uint32_t clkdiv; +}; + +struct adc_cc35xx_cfg { + mem_addr_t base; + const struct pinctrl_dev_config *pcfg; + uint32_t clkdiv; + uint16_t sample_period; +}; + +static void adc_context_start_sampling(struct adc_context *ctx) +{ + struct adc_cc35xx_data *data = CONTAINER_OF(ctx, struct adc_cc35xx_data, ctx); + uint32_t channel_irq = 0; + + data->channels = ctx->sequence.channels; + data->repeat_buffer = data->buffer; + /* wait for interrupt from the last configured channel, so we get + * single interrupt once all channels are done + */ + channel_irq = ADC_INT_MEMRES_00 << (data->active_channels - 1); + + ADCEnableConversion(); + ADCStartConversion(); + ADCEnableInterrupt(channel_irq); +} + +static void adc_context_update_buffer_pointer(struct adc_context *ctx, bool repeat) +{ + struct adc_cc35xx_data *data = CONTAINER_OF(ctx, struct adc_cc35xx_data, ctx); + + if (repeat) { + data->buffer = data->repeat_buffer; + } else { + data->buffer += data->active_channels; + } +} + +static int adc_cc35xx_get_reference(enum adc_reference zephyr_reference) +{ + switch (zephyr_reference) { + case ADC_REF_VDD_1: + return ADC_VDDA_REFERENCE; + + case ADC_REF_INTERNAL: + return ADC_INTERNAL_REFERENCE; + + case ADC_REF_EXTERNAL0: + return ADC_EXTERNAL_REFERENCE; + + default: + return -1; + } +} + +static int adc_cc35xx_channel_setup(const struct device *dev, + const struct adc_channel_cfg *channel_cfg) +{ + struct adc_cc35xx_data *data = dev->data; + const uint8_t ch = channel_cfg->channel_id; + int vref; + + if (ch >= CC35XX_CHAN_COUNT) { + LOG_ERR("Channel %d is not available, hardware max channel is %d", + ch, CC35XX_CHAN_COUNT); + return -EINVAL; + } + + if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) { + LOG_ERR("Acquisition time is not valid"); + return -EINVAL; + } + + if (channel_cfg->differential) { + LOG_ERR("Differential channels are not supported"); + return -ENOTSUP; + } + + if (channel_cfg->gain != ADC_GAIN_1) { + LOG_ERR("Gain is not valid"); + return -EINVAL; + } + + vref = adc_cc35xx_get_reference(channel_cfg->reference); + if (vref == -1) { + LOG_ERR("Reference is not valid"); + return -EINVAL; + } + + LOG_DBG("Setup %d", ch); + data->channel_config[ch].vref = vref; + + return 0; +} + +static int adc_cc35xx_read(const struct device *dev, const struct adc_sequence *sequence, + bool asynchronous, struct k_poll_signal *sig) +{ + struct adc_cc35xx_data *data = dev->data; + const struct adc_cc35xx_cfg *config = dev->config; + size_t exp_size; + int rv; + + if (sequence->resolution != 12) { + LOG_ERR("Only 12 bit resolution is supported, requested resolution is %d", + sequence->resolution); + return -EINVAL; + } + + ADCDisableConversion(); + + data->active_channels = 0; + for (int ch = 0; ch < CC35XX_CHAN_COUNT; ++ch) { + if (sequence->channels & BIT(ch)) { + ADCSetInput(data->channel_config[ch].vref, ch, ADC_FULL_SCALE_RANGE_0V0_3V3, + data->active_channels); + data->active_channels++; + } + } + exp_size = data->active_channels * sizeof(uint16_t); + + if (data->active_channels == 0) { + LOG_ERR("No channels selected for conversion"); + return -EINVAL; + } + + if (data->active_channels > CC35XX_SEQUENCE_MAX) { + LOG_ERR("Cannot convert more than 6 channels in a sequence"); + return -EINVAL; + } + + if (sequence->buffer_size < exp_size) { + LOG_ERR("Required buffer size is %u, but %u got", exp_size, sequence->buffer_size); + return -ENOMEM; + } + + data->buffer = sequence->buffer; + + ADCSetMemctlRange(0, data->active_channels - 1); + ADCSetSampleDuration(data->clkdiv, config->sample_period); + ADCSetSamplingMode(ADC_SAMPLE_MODE_AUTO); + ADCSetSequence(ADC_SEQUENCE_SEQUENCE); + ADCSetTriggerSource(ADC_TRIGGER_SOURCE_SOFTWARE); + + adc_context_lock(&data->ctx, asynchronous, sig); + adc_context_start_read(&data->ctx, sequence); + rv = adc_context_wait_for_completion(&data->ctx); + adc_context_release(&data->ctx, rv); + return rv; +} + +static int adc_cc35xx_read_sync(const struct device *dev, const struct adc_sequence *sequence) +{ + return adc_cc35xx_read(dev, sequence, false, NULL); +} + +#ifdef CONFIG_ADC_ASYNC +static int adc_cc35xx_read_async(const struct device *dev, const struct adc_sequence *sequence, + struct k_poll_signal *async) +{ + return adc_cc35xx_read(dev, sequence, true, async); +} +#endif + +static void adc_cc35xx_isr(const struct device *dev) +{ + const struct adc_cc35xx_cfg *config = dev->config; + struct adc_cc35xx_data *data = dev->data; + mem_addr_t reg; + uint32_t irq_status = ADCMaskedInterruptStatus(); + + if (irq_status & ADC_INT_UVIFG) { + ADCClearInterrupt(ADC_INT_UVIFG); + return; + } + + if (irq_status & ADC_INT_CHAN_MASK) { + for (unsigned int chan = 0; chan < data->active_channels; chan++) { + reg = config->base + ADC_O_MEMRES_0 + 4 * chan; + *(data->buffer + chan) = sys_read16(reg); + } + + ADCDisableInterrupt(ADC_INT_CHAN_MASK); + ADCClearInterrupt(ADC_INT_CHAN_MASK); + ADCStopConversion(); + ADCDisableConversion(); + adc_context_on_sampling_done(&data->ctx, dev); + } +} + +/** + * Translate integer divide value user passes in DTS to register value + */ +static uint32_t adc_cc35xx_sclkdiv_reg_val(int div) +{ + switch (div) { + case 1: return ADC_CLOCK_DIVIDER_1; + case 2: return ADC_CLOCK_DIVIDER_2; + case 4: return ADC_CLOCK_DIVIDER_4; + case 8: return ADC_CLOCK_DIVIDER_8; + case 16: return ADC_CLOCK_DIVIDER_16; + case 24: return ADC_CLOCK_DIVIDER_24; + case 32: return ADC_CLOCK_DIVIDER_32; + case 48: return ADC_CLOCK_DIVIDER_48; + default: + __ASSERT(0, "Invalid ADC clock divider passed"); + return ADC_CLOCK_DIVIDER_1; + } +} + +static int adc_cc35xx_init(const struct device *dev) +{ + struct adc_cc35xx_data *data = dev->data; + const struct adc_cc35xx_cfg *config = dev->config; + int ret; + + data->dev = dev; + + LOG_DBG("Initializing..."); + + ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); + if (ret < 0) { + LOG_ERR("applying ADC pinctrl state failed"); + return ret; + } + + data->clkdiv = adc_cc35xx_sclkdiv_reg_val(config->clkdiv); + ADCSetSamplingClk(ADC_SAMPLE_CLK_SOC_CLK); + ADCDisableInterrupt(ADC_INT_ALL); + sys_write32(ADC_CLKCFG_EN, config->base + ADC_O_CLKCFG); + IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), adc_cc35xx_isr, + DEVICE_DT_INST_GET(0), 0); + irq_enable(DT_INST_IRQN(0)); + + adc_context_unlock_unconditionally(&data->ctx); + return 0; +} + +static const struct adc_driver_api cc35xx_driver_api = { + .channel_setup = adc_cc35xx_channel_setup, + .read = adc_cc35xx_read_sync, +#ifdef CONFIG_ADC_ASYNC + .read_async = adc_cc35xx_read_async, +#endif + .ref_internal = 1400, +}; + +#define CC35XX_ADC_INIT(n) \ + PINCTRL_DT_INST_DEFINE(n); \ + static const struct adc_cc35xx_cfg adc_cc35xx_cfg_##n = { \ + .base = DT_INST_REG_ADDR(n), \ + .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \ + .clkdiv = DT_INST_PROP(n, clkdiv), \ + .sample_period = DT_INST_PROP(n, sample_period), \ + }; \ + static struct adc_cc35xx_data adc_cc35xx_data_##n = { \ + ADC_CONTEXT_INIT_TIMER(adc_cc35xx_data_##n, ctx), \ + ADC_CONTEXT_INIT_LOCK(adc_cc35xx_data_##n, ctx), \ + ADC_CONTEXT_INIT_SYNC(adc_cc35xx_data_##n, ctx), \ + }; \ + \ + DEVICE_DT_INST_DEFINE(n, &adc_cc35xx_init, NULL, &adc_cc35xx_data_##n, \ + &adc_cc35xx_cfg_##n, POST_KERNEL, CONFIG_ADC_INIT_PRIORITY, \ + &cc35xx_driver_api); + +DT_INST_FOREACH_STATUS_OKAY(CC35XX_ADC_INIT) diff --git a/drivers/adc/adc_shell.c b/drivers/adc/adc_shell.c index 58d02d5a91ef..d2e9deaded39 100644 --- a/drivers/adc/adc_shell.c +++ b/drivers/adc/adc_shell.c @@ -11,39 +11,30 @@ #include #include - #define LOG_LEVEL CONFIG_LOG_DEFAULT_LEVEL #include LOG_MODULE_REGISTER(adc_shell); -#define CMD_HELP_ACQ_TIME \ - SHELL_HELP("Configure acquisition time", \ - "