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eyckeyck
committed
implements HW breakpoints
1 parent 612ad19 commit 4db3ef1

13 files changed

Lines changed: 42 additions & 38 deletions

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‎CMakeLists.txt‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@ if(NOT TARGET dbt-rise-core)
2727
FetchContent_Declare(
2828
dbt_rise_core_git
2929
GIT_REPOSITORY "https://github.com/Minres/DBT-RISE-Core.git"
30-
GIT_TAG e17e1b58
30+
GIT_TAG c1def072
3131
GIT_SHALLOW OFF
3232
UPDATE_DISCONNECTED NOT ${UPDATE_EXTERNAL_PROJECT} # When enabled, this option causes the update step to be skipped.
3333
)

‎gen_input/templates/interp/CORENAME.cpp.gtl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -361,7 +361,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
361361
!(is_icount_limit_enabled(cond) && icount >= count_limit) &&
362362
!(is_fcount_limit_enabled(cond) && fetch_count >= count_limit)){
363363
if(this->debugging_enabled())
364-
this->tgt_adapter->check_continue(*PC);
364+
this->tgt_adapter->check_break_on_pc(*PC);
365365
pc.val=*PC;
366366
if(fetch_ins(pc, data)!=iss::Ok){
367367
if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, std::numeric_limits<unsigned>::max());

‎src/iss/arch/riscv_hart_common.h‎

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -57,14 +57,6 @@
5757
#include <util/logging.h>
5858
#include <util/sparse_array.h>
5959

60-
#if defined(__GNUC__)
61-
#define likely(x) ::__builtin_expect(!!(x), 1)
62-
#define unlikely(x) ::__builtin_expect(!!(x), 0)
63-
#else
64-
#define likely(x) x
65-
#define unlikely(x) x
66-
#endif
67-
6860
namespace iss {
6961
namespace arch {
7062

‎src/iss/debugger/riscv_target_adapter.h‎

Lines changed: 31 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,7 @@
3434
#define _ISS_ARCH_DEBUGGER_RISCV_TARGET_ADAPTER_H_
3535

3636
#include "iss/arch_if.h"
37+
#include "iss/debugger/target_adapter_if.h"
3738
#include <iss/arch/traits.h>
3839
#include <iss/debugger/target_adapter_base.h>
3940
#include <iss/iss.h>
@@ -343,40 +344,51 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::packetsize_query(std
343344
}
344345

345346
template <typename ARCH> status riscv_target_adapter<ARCH>::add_break(break_type type, uint64_t addr, unsigned int length) {
347+
auto f = [](riscv_target_adapter<ARCH>* self, util::range_lut<uint64_t>& lut, uint64_t addr, unsigned int length) {
348+
auto saddr = map_addr({iss::address_type::PHYSICAL, iss::access_type::FETCH, 0, addr});
349+
auto eaddr = map_addr({iss::address_type::PHYSICAL, iss::access_type::FETCH, 0, addr + length});
350+
lut.addEntry(++self->bp_count, saddr.val, eaddr.val - saddr.val);
351+
CPPLOG(TRACE) << "Adding breakpoint with handle " << self->bp_count << " for addr 0x" << std::hex << saddr.val << std::dec;
352+
CPPLOG(TRACE) << "Now having " << self->bp_lut.size() + self->wr_lut.size() + self->rd_lut.size() << " breakpoints";
353+
return Ok;
354+
};
346355
switch(type) {
347356
default:
348357
return Err;
349358
case SW_EXEC:
350-
case HW_EXEC: {
351-
auto saddr = map_addr({iss::address_type::PHYSICAL, iss::access_type::FETCH, 0, addr});
352-
auto eaddr = map_addr({iss::address_type::PHYSICAL, iss::access_type::FETCH, 0, addr + length});
353-
target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val - saddr.val);
354-
CPPLOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex << saddr.val
355-
<< std::dec;
356-
CPPLOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
357-
return Ok;
358-
}
359+
case HW_EXEC:
360+
return f(this, this->bp_lut, addr, length);
361+
case RD_WATCH:
362+
return f(this, this->rd_lut, addr, length);
363+
case WR_WATCH:
364+
return f(this, this->wr_lut, addr, length);
359365
}
360366
}
361367

362368
template <typename ARCH> status riscv_target_adapter<ARCH>::remove_break(break_type type, uint64_t addr, unsigned int length) {
363-
switch(type) {
364-
default:
365-
return Err;
366-
case SW_EXEC:
367-
case HW_EXEC: {
369+
auto f = [](riscv_target_adapter<ARCH>* self, util::range_lut<uint64_t>& lut, uint64_t addr, unsigned int length) {
368370
auto saddr = map_addr({iss::address_type::PHYSICAL, iss::access_type::FETCH, 0, addr});
369-
unsigned handle = target_adapter_base::bp_lut.getEntry(saddr.val);
371+
unsigned handle = lut.getEntry(saddr.val);
370372
if(handle) {
371373
CPPLOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val << std::dec;
372374
// TODO: check length of addr range
373-
target_adapter_base::bp_lut.removeEntry(handle);
374-
CPPLOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
375+
lut.removeEntry(handle);
376+
CPPLOG(TRACE) << "Now having " << self->bp_lut.size() + self->wr_lut.size() + self->rd_lut.size() << " breakpoints";
375377
return Ok;
376378
}
377-
CPPLOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
379+
CPPLOG(TRACE) << "Now having " << self->bp_lut.size() + self->wr_lut.size() + self->rd_lut.size() << " breakpoints";
378380
return Err;
379-
}
381+
};
382+
switch(type) {
383+
default:
384+
return Err;
385+
case SW_EXEC:
386+
case HW_EXEC:
387+
return f(this, this->bp_lut, addr, length);
388+
case RD_WATCH:
389+
return f(this, this->rd_lut, addr, length);
390+
case WR_WATCH:
391+
return f(this, this->wr_lut, addr, length);
380392
}
381393
}
382394

‎src/vm/interp/vm_rv32gc.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -425,7 +425,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
425425
!(is_icount_limit_enabled(cond) && icount >= count_limit) &&
426426
!(is_fcount_limit_enabled(cond) && fetch_count >= count_limit)){
427427
if(this->debugging_enabled())
428-
this->tgt_adapter->check_continue(*PC);
428+
this->tgt_adapter->check_break_on_pc(*PC);
429429
pc.val=*PC;
430430
if(fetch_ins(pc, data)!=iss::Ok){
431431
if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, std::numeric_limits<unsigned>::max());

‎src/vm/interp/vm_rv32gcv.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1396,7 +1396,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
13961396
!(is_icount_limit_enabled(cond) && icount >= count_limit) &&
13971397
!(is_fcount_limit_enabled(cond) && fetch_count >= count_limit)){
13981398
if(this->debugging_enabled())
1399-
this->tgt_adapter->check_continue(*PC);
1399+
this->tgt_adapter->check_break_on_pc(*PC);
14001400
pc.val=*PC;
14011401
if(fetch_ins(pc, data)!=iss::Ok){
14021402
if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, std::numeric_limits<unsigned>::max());

‎src/vm/interp/vm_rv32i.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -281,7 +281,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
281281
!(is_icount_limit_enabled(cond) && icount >= count_limit) &&
282282
!(is_fcount_limit_enabled(cond) && fetch_count >= count_limit)){
283283
if(this->debugging_enabled())
284-
this->tgt_adapter->check_continue(*PC);
284+
this->tgt_adapter->check_break_on_pc(*PC);
285285
pc.val=*PC;
286286
if(fetch_ins(pc, data)!=iss::Ok){
287287
if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, std::numeric_limits<unsigned>::max());

‎src/vm/interp/vm_rv32imac.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -330,7 +330,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
330330
!(is_icount_limit_enabled(cond) && icount >= count_limit) &&
331331
!(is_fcount_limit_enabled(cond) && fetch_count >= count_limit)){
332332
if(this->debugging_enabled())
333-
this->tgt_adapter->check_continue(*PC);
333+
this->tgt_adapter->check_break_on_pc(*PC);
334334
pc.val=*PC;
335335
if(fetch_ins(pc, data)!=iss::Ok){
336336
if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, std::numeric_limits<unsigned>::max());

‎src/vm/interp/vm_rv64gc.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -465,7 +465,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
465465
!(is_icount_limit_enabled(cond) && icount >= count_limit) &&
466466
!(is_fcount_limit_enabled(cond) && fetch_count >= count_limit)){
467467
if(this->debugging_enabled())
468-
this->tgt_adapter->check_continue(*PC);
468+
this->tgt_adapter->check_break_on_pc(*PC);
469469
pc.val=*PC;
470470
if(fetch_ins(pc, data)!=iss::Ok){
471471
if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, std::numeric_limits<unsigned>::max());

‎src/vm/interp/vm_rv64gcv.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1436,7 +1436,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
14361436
!(is_icount_limit_enabled(cond) && icount >= count_limit) &&
14371437
!(is_fcount_limit_enabled(cond) && fetch_count >= count_limit)){
14381438
if(this->debugging_enabled())
1439-
this->tgt_adapter->check_continue(*PC);
1439+
this->tgt_adapter->check_break_on_pc(*PC);
14401440
pc.val=*PC;
14411441
if(fetch_ins(pc, data)!=iss::Ok){
14421442
if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, std::numeric_limits<unsigned>::max());

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