fix: report an instruction access fault for a denied fetch

riscv_hart_m_p::read set RV_CAUSE_LOAD_ACCESS unconditionally when the memory
chain returned an error, so a PMP-denied instruction fetch surfaced as a load
access fault. RV_CAUSE_FETCH_ACCESS was consumed by the trap dispatch switch
but never assigned in this wrapper.

riscv_hart_mu_p and riscv_hart_msu_vp already selected the cause on is_fetch,
so this was an oversight in the M-mode wrapper alone; it now matches them.

The two fetch tests only asserted that some trap fired, which is why this
went unnoticed; both now assert the cause.

Author: cphurley82

src/iss/arch/riscv_hart_m_p.h

@@ -187,7 +187,8 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read(const addr_t& a, const unsigned len
                 }
                 auto res = this->memory.rd_mem({address_type::PHYSICAL, a.access, a.space, a.val}, length, data);
                 if(unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) {
-                    this->reg.trap_state = (1UL << 31) | traits<BASE>::RV_CAUSE_LOAD_ACCESS << 16;
+                    auto trap_id = is_fetch(a.access) ? traits<BASE>::RV_CAUSE_FETCH_ACCESS : traits<BASE>::RV_CAUSE_LOAD_ACCESS;
+                    this->reg.trap_state = (1UL << 31) | trap_id << 16;
                     this->fault_data = addr;
                 }
                 return res;