From fb888aea48f3fdc8b0b0d9524448b45774db5dcf Mon Sep 17 00:00:00 2001 From: Daniel Hansen Date: Sat, 22 Aug 2026 20:13:01 -0700 Subject: [PATCH 01/17] Probably 6-8 hours worth of work... Signed-off-by: Daniel Hansen --- CMakeLists.txt | 167 +++++++------- Lib/cmake/cube.cmake | 294 +++++++++++++++++++++++++ Lib/cmake/gr-lib.cmake | 2 +- Testbench/CUBEMXTESTING/CMakeLists.txt | 37 +--- 4 files changed, 393 insertions(+), 107 deletions(-) create mode 100644 Lib/cmake/cube.cmake diff --git a/CMakeLists.txt b/CMakeLists.txt index 40e5a1cb0..6d4fb866a 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1,8 +1,8 @@ cmake_minimum_required(VERSION 3.25) project(Firmware) enable_language( - C - ASM + C + ASM ) # Setup compiler settings @@ -13,105 +13,122 @@ set(CMAKE_EXPORT_COMPILE_COMMANDS TRUE) # Messages if(NOT DEFINED CMAKE_PRESET_NAME) - message( - FATAL_ERROR - "This project requires configuration using a CMake preset. Please use 'cmake --preset ' or select a preset in your IDE." - ) + message( + FATAL_ERROR + "This project requires configuration using a CMake preset. Please use 'cmake --preset ' or select a preset in your IDE." + ) endif() message( - STATUS - "Build type: " - ${CMAKE_BUILD_TYPE} + STATUS + "Build type: " + ${CMAKE_BUILD_TYPE} ) message(STATUS "Target type: ${TARGET_TYPE}") message( - STATUS - "Active CMake Preset: " - ${CMAKE_PRESET_NAME} + STATUS + "Active CMake Preset: " + ${CMAKE_PRESET_NAME} ) # Shared Compiler Cache Configuration find_program(SCCACHE_PROGRAM sccache) if( - SCCACHE_PROGRAM - AND - NOT - CMAKE_C_COMPILER_LAUNCHER - AND - NOT - CMAKE_ASM_COMPILER_LAUNCHER + SCCACHE_PROGRAM + AND + NOT + CMAKE_C_COMPILER_LAUNCHER + AND + NOT + CMAKE_ASM_COMPILER_LAUNCHER ) - message(STATUS "Found sccache: ${SCCACHE_PROGRAM}") - set(SCCACHE_DIR_PATH "${CMAKE_SOURCE_DIR}/sccache") - set( - CMAKE_C_COMPILER_LAUNCHER - "${CMAKE_COMMAND}" - -E - env - "SCCACHE_DIR=${SCCACHE_DIR_PATH}" - "${SCCACHE_PROGRAM}" - ) - set( - CMAKE_ASM_COMPILER_LAUNCHER - "${CMAKE_COMMAND}" - -E - env - "SCCACHE_DIR=${SCCACHE_DIR_PATH}" - "${SCCACHE_PROGRAM}" - ) - message(STATUS "sccache directory: ${SCCACHE_DIR_PATH}") + message(STATUS "Found sccache: ${SCCACHE_PROGRAM}") + set(SCCACHE_DIR_PATH "${CMAKE_SOURCE_DIR}/sccache") + set( + CMAKE_C_COMPILER_LAUNCHER + "${CMAKE_COMMAND}" + -E + env + "SCCACHE_DIR=${SCCACHE_DIR_PATH}" + "${SCCACHE_PROGRAM}" + ) + set( + CMAKE_ASM_COMPILER_LAUNCHER + "${CMAKE_COMMAND}" + -E + env + "SCCACHE_DIR=${SCCACHE_DIR_PATH}" + "${SCCACHE_PROGRAM}" + ) + message(STATUS "sccache directory: ${SCCACHE_DIR_PATH}") elseif(CMAKE_C_COMPILER_LAUNCHER OR CMAKE_ASM_COMPILER_LAUNCHER) - message( - STATUS - "Not using sccache: CMAKE_C_COMPILER_LAUNCHER already set to '${CMAKE_C_COMPILER_LAUNCHER}' or CMAKE_ASM_COMPILER_LAUNCHER already set to '${CMAKE_ASM_COMPILER_LAUNCHER}'" - ) + message( + STATUS + "Not using sccache: CMAKE_C_COMPILER_LAUNCHER already set to '${CMAKE_C_COMPILER_LAUNCHER}' or CMAKE_ASM_COMPILER_LAUNCHER already set to '${CMAKE_ASM_COMPILER_LAUNCHER}'" + ) else() - message(STATUS "Not using sccache: sccache not found in PATH") + message(STATUS "Not using sccache: sccache not found in PATH") endif() # Compiler Cache Configuration find_program(CCACHE_PROGRAM ccache) if( - CCACHE_PROGRAM - AND - NOT - CMAKE_C_COMPILER_LAUNCHER - AND - NOT - CMAKE_ASM_COMPILER_LAUNCHER + CCACHE_PROGRAM + AND + NOT + CMAKE_C_COMPILER_LAUNCHER + AND + NOT + CMAKE_ASM_COMPILER_LAUNCHER ) - message(STATUS "Found ccache: ${CCACHE_PROGRAM}") - set(CCACHE_DIR_PATH "${CMAKE_SOURCE_DIR}/ccache") - set( - CMAKE_C_COMPILER_LAUNCHER - "${CMAKE_COMMAND}" - -E - env - "CCACHE_DIR=${CCACHE_DIR_PATH}" - "${CCACHE_PROGRAM}" - ) - set( - CMAKE_ASM_COMPILER_LAUNCHER - "${CMAKE_COMMAND}" - -E - env - "CCACHE_DIR=${CCACHE_DIR_PATH}" - "${CCACHE_PROGRAM}" - ) - message(STATUS "ccache directory: ${CCACHE_DIR_PATH}") + message(STATUS "Found ccache: ${CCACHE_PROGRAM}") + set(CCACHE_DIR_PATH "${CMAKE_SOURCE_DIR}/ccache") + set( + CMAKE_C_COMPILER_LAUNCHER + "${CMAKE_COMMAND}" + -E + env + "CCACHE_DIR=${CCACHE_DIR_PATH}" + "${CCACHE_PROGRAM}" + ) + set( + CMAKE_ASM_COMPILER_LAUNCHER + "${CMAKE_COMMAND}" + -E + env + "CCACHE_DIR=${CCACHE_DIR_PATH}" + "${CCACHE_PROGRAM}" + ) + message(STATUS "ccache directory: ${CCACHE_DIR_PATH}") elseif(CMAKE_C_COMPILER_LAUNCHER OR CMAKE_ASM_COMPILER_LAUNCHER) - message( - STATUS - "Not using ccache: CMAKE_C_COMPILER_LAUNCHER already set to '${CMAKE_C_COMPILER_LAUNCHER}' or CMAKE_ASM_COMPILER_LAUNCHER already set to '${CMAKE_ASM_COMPILER_LAUNCHER}'" - ) + message( + STATUS + "Not using ccache: CMAKE_C_COMPILER_LAUNCHER already set to '${CMAKE_C_COMPILER_LAUNCHER}' or CMAKE_ASM_COMPILER_LAUNCHER already set to '${CMAKE_ASM_COMPILER_LAUNCHER}'" + ) else() - message(STATUS "Not using ccache: ccache not found in PATH") + message(STATUS "Not using ccache: ccache not found in PATH") endif() # Globals set(lib_path "Lib") set(platform_path "${lib_path}/Platform") +include("${lib_path}/cmake/cube.cmake") + +add_arm_cmsis_core( + MAJOR "5" + GIT_TAG "5.9.0" # https://github.com/ARM-software/CMSIS_5/tree/5.9.0 +) + +add_project( + NAME "CUBEMXTESTING" + PATH "Testbench/CUBEMXTESTING" + SERIES "g4" + SPECIFIER "g474re" + HAL_GIT_TAG "v1.2.7" # https://github.com/STMicroelectronics/stm32g4xx-hal-driver/tree/v1.2.7 + CMSIS_GIT_TAG "v1.2.6" # https://github.com/STMicroelectronics/cmsis-device-g4/tree/v1.2.6 + CMSIS_MAJOR "5" +) + # Vendor include("${lib_path}/Vendor/CMSIS_5/cmsis_5.cmake") include("${lib_path}/Vendor/STM32_HAL_LL/cube.cmake") @@ -161,7 +178,7 @@ add_gr_project(STM32G431x8 OutboardSensors BrakeTemp) # Development add_gr_project(STM32G474xE Testbench G4NEOTESTING) -add_gr_project(STM32G474xE Testbench CUBEMXTESTING) +# add_gr_project(STM32G474xE Testbench CUBEMXTESTING) # BLINKY Demos add_gr_project(STM32G474xE BLINKY G4BLINKY) diff --git a/Lib/cmake/cube.cmake b/Lib/cmake/cube.cmake new file mode 100644 index 000000000..0e9733936 --- /dev/null +++ b/Lib/cmake/cube.cmake @@ -0,0 +1,294 @@ +# Prefer calling add_project() instead of the other functions directly +# Note that add_project() will automatically add the project to the build system and link it against the appropriate CMSIS and HAL libraries +# Link your user code against "${NAME}_USER_CODE" to ensure proper linking with the STM32 HAL and CMSIS libraries + +include(FetchContent) + +function(download_git) + if(NOT ${ARGC} EQUAL 10) + message( + FATAL_ERROR + "You called download_git with an unsupported number of inputs/arguments! Do better please :)" + ) + endif() + + set(one_value_args NAME GIT_REPOSITORY GIT_TAG OUTPUT_PATH_VAR) + set(multi_value_args TARGET_FOLDER) + unset(DOWNLOAD_GIT_ARG_NAME) + unset(DOWNLOAD_GIT_ARG_GIT_REPOSITORY) + unset(DOWNLOAD_GIT_ARG_GIT_TAG) + unset(DOWNLOAD_GIT_ARG_OUTPUT_PATH_VAR) + unset(DOWNLOAD_GIT_ARG_TARGET_FOLDER) + cmake_parse_arguments("DOWNLOAD_GIT_ARG" "" "${one_value_args}" "${multi_value_args}" ${ARGN}) + + message(STATUS "This may take a moment, fetching content for ${DOWNLOAD_GIT_ARG_NAME} from ${DOWNLOAD_GIT_ARG_GIT_REPOSITORY} at tag ${DOWNLOAD_GIT_ARG_GIT_TAG}") + + FetchContent_Declare( + "${DOWNLOAD_GIT_ARG_NAME}" + GIT_REPOSITORY "${DOWNLOAD_GIT_ARG_GIT_REPOSITORY}" + GIT_TAG "${DOWNLOAD_GIT_ARG_GIT_TAG}" + GIT_SHALLOW ON + GIT_SUBMODULES "" + UPDATE_DISCONNECTED TRUE + GIT_CONFIG "core.sparseCheckout=true" + ) + + string(TOLOWER "${DOWNLOAD_GIT_ARG_NAME}" NAME_LOWER) + + FetchContent_GetProperties(${NAME_LOWER}) + + if(NOT ${NAME_LOWER}_POPULATED) + FetchContent_Populate(${NAME_LOWER}) + separate_arguments(TARGET_FOLDER_LIST NATIVE_COMMAND "${DOWNLOAD_GIT_ARG_TARGET_FOLDER}") + execute_process( + COMMAND git sparse-checkout set ${TARGET_FOLDER_LIST} + WORKING_DIRECTORY "${${NAME_LOWER}_SOURCE_DIR}" + ) + execute_process( + COMMAND git checkout + WORKING_DIRECTORY "${${NAME_LOWER}_SOURCE_DIR}" + ) + endif() + + message(STATUS "Successfully fetched content for ${DOWNLOAD_GIT_ARG_NAME} from ${DOWNLOAD_GIT_ARG_GIT_REPOSITORY} at tag ${DOWNLOAD_GIT_ARG_GIT_TAG} to ${${DOWNLOAD_GIT_ARG_NAME}_SOURCE_DIR}") + + set("${DOWNLOAD_GIT_ARG_OUTPUT_PATH_VAR}" "${${DOWNLOAD_GIT_ARG_NAME}_SOURCE_DIR}") + return(PROPAGATE "${DOWNLOAD_GIT_ARG_OUTPUT_PATH_VAR}") +endfunction() + +#[[ +@brief Adds the ARM CMSIS core to the build system +@param MAJOR The major version of the CMSIS core to use (e.g., "5") +@param GIT_TAG The git tag for the CMSIS core to use +@note Link your user code against "CMSIS_${MAJOR}_Core" to ensure proper linking with the CMSIS core libraries +@remark Prefer calling add_project() instead of this function directly +]] +function(add_arm_cmsis_core) + if(NOT ${ARGC} EQUAL 4) + message( + FATAL_ERROR + "You called add_arm_cmsis_core with an unsupported number of inputs/arguments! Do better please :)" + ) + endif() + + set(one_value_args MAJOR GIT_TAG) + unset(ARM_CMSIS_CORE_ARG_MAJOR) + unset(ARM_CMSIS_CORE_ARG_GIT_TAG) + cmake_parse_arguments("ARM_CMSIS_CORE_ARG" "" "${one_value_args}" "" ${ARGN}) + + if(NOT ARM_CMSIS_CORE_ARG_MAJOR MATCHES "^[0-9]$") + message(FATAL_ERROR "MAJOR '${ARM_CMSIS_CORE_ARG_MAJOR}' is not a valid version number (ie '5')") + endif() + + download_git( + NAME "arm_cmsis_${ARM_CMSIS_CORE_ARG_MAJOR}" + GIT_REPOSITORY "https://github.com/arm-software/cmsis_${ARM_CMSIS_CORE_ARG_MAJOR}.git" + GIT_TAG "${ARM_CMSIS_CORE_ARG_GIT_TAG}" + OUTPUT_PATH_VAR ARM_CMSIS_CORE_PATH + TARGET_FOLDER "CMSIS/Core/Include" + ) + message(STATUS "Successfully fetched content for ARM CMSIS core version ${ARM_CMSIS_CORE_ARG_MAJOR} from ${ARM_CMSIS_CORE_ARG_GIT_TAG} to ${ARM_CMSIS_CORE_PATH}") + add_library(CMSIS_${ARM_CMSIS_CORE_ARG_MAJOR}_Core INTERFACE) + target_include_directories( + CMSIS_${ARM_CMSIS_CORE_ARG_MAJOR}_Core + INTERFACE + "${ARM_CMSIS_CORE_PATH}/CMSIS/Core/Include" + ) +endfunction() + +#[[ +@brief Adds the ARM CMSIS device interface to the build system +@param SERIES The STM32 series (e.g., "g4") +@param SPECIFIER The STM32 specifier (e.g., "g474re") +@param GIT_TAG The git tag for the CMSIS device to use +@note Link your user code against "CMSIS_Device_${SPECIFIER}" to ensure proper linking with the CMSIS device libraries +@remark Prefer calling add_project() instead of this function directly +]] +function(add_arm_cmsis_interface) + if(NOT ${ARGC} EQUAL 6) + message( + FATAL_ERROR + "You called add_arm_cmsis_interface with an unsupported number of inputs/arguments! Do better please :)" + ) + endif() + + set(one_value_args SERIES SPECIFIER GIT_TAG) + unset(ARM_CMSIS_INTERFACE_ARG_SERIES) + unset(ARM_CMSIS_INTERFACE_ARG_SPECIFIER) + unset(ARM_CMSIS_INTERFACE_ARG_GIT_TAG) + cmake_parse_arguments("ARM_CMSIS_INTERFACE_ARG" "" "${one_value_args}" "" ${ARGN}) + + message(VERBOSE "Adding ARM CMSIS device interface for SERIES '${ARM_CMSIS_INTERFACE_ARG_SERIES}', SPECIFIER '${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}', and GIT_TAG '${ARM_CMSIS_INTERFACE_ARG_GIT_TAG}'") + + string(LENGTH "${ARM_CMSIS_INTERFACE_ARG_SERIES}" SERIES_LENGTH) + if(NOT SERIES_LENGTH EQUAL 2) + message(FATAL_ERROR "SERIES '${ARM_CMSIS_INTERFACE_ARG_SERIES}' must be 2 characters long (ie 'g4')") + endif() + string(TOLOWER "${ARM_CMSIS_INTERFACE_ARG_SERIES}" SERIES_LOWER) + + string(LENGTH "${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}" SPECIFIER_LENGTH) + if(SPECIFIER_LENGTH LESS 6) + message(FATAL_ERROR "SPECIFIER '${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}' must be at least 6 characters long (ie 'g474re' or 'g474ret6')") + endif() + string(TOLOWER "${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}" SPECIFIER_LOWER) + string(TOUPPER "${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}" SPECIFIER_UPPER) + + string(FIND "${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}" "${ARM_CMSIS_INTERFACE_ARG_SERIES}" SERIES_POSITION_IN_SPECIFIER) + if(NOT SERIES_POSITION_IN_SPECIFIER EQUAL 0) + message(FATAL_ERROR "SPECIFIER '${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}' must start with SERIES '${ARM_CMSIS_INTERFACE_ARG_SERIES}' at the beginning (eg 'g4' and 'g474ret6')") + endif() + + download_git( + NAME "cmsis_device_${SERIES_LOWER}" + GIT_REPOSITORY "https://github.com/STMicroelectronics/cmsis-device-${SERIES_LOWER}.git" + GIT_TAG ${ARM_CMSIS_INTERFACE_ARG_GIT_TAG} + TARGET_FOLDER "Include Source/Templates/gcc" + OUTPUT_PATH_VAR CMSIS_DEVICE_PATH + ) + message(STATUS "Successfully fetched content for ARM CMSIS device ${SPECIFIER_UPPER} from ${ARM_CMSIS_INTERFACE_ARG_GIT_TAG} to ${CMSIS_DEVICE_PATH}") + add_library("CMSIS_Device_${SPECIFIER_UPPER}" INTERFACE) + target_include_directories( + "CMSIS_Device_${SPECIFIER_UPPER}" + INTERFACE + "${CMSIS_DEVICE_PATH}/Include" + ) + target_sources( + "CMSIS_Device_${SPECIFIER_UPPER}" + INTERFACE + "${CMSIS_DEVICE_PATH}/Source/Templates/gcc/startup_stm32${SPECIFIER_LOWER}.s" + "${CMSIS_DEVICE_PATH}/Source/Templates/system_stm32${SERIES_LOWER}xx.c" + ) +endfunction() + +#[[ +@brief Adds the STM32 HAL driver interface to the build system +@param SERIES The STM32 series (e.g., "g4") +@param GIT_TAG The git tag for the STM32 HAL driver to use +@note Link your user code against "STM32HAL_${SERIES}" to ensure proper linking with the STM32 HAL libraries +@remark Prefer calling add_project() instead of this function directly +]] +function(add_stm32_hal_interface) + if(NOT ${ARGC} EQUAL 4) + message( + FATAL_ERROR + "You called add_stm32_hal_interface with an unsupported number of inputs/arguments! Do better please :)" + ) + endif() + + set(one_value_args SERIES GIT_TAG) + unset(STM32_HAL_ARG_SERIES) + unset(STM32_HAL_ARG_GIT_TAG) + cmake_parse_arguments("STM32_HAL_ARG" "" "${one_value_args}" "" ${ARGN}) + + message(VERBOSE "Adding STM32 HAL driver interface for SERIES '${STM32_HAL_ARG_SERIES}' with GIT_TAG '${STM32_HAL_ARG_GIT_TAG}'") + + string(LENGTH "${STM32_HAL_ARG_SERIES}" SERIES_LENGTH) + if(NOT SERIES_LENGTH EQUAL 2) + message(FATAL_ERROR "SERIES '${STM32_HAL_ARG_SERIES}' must be 2 characters long (ie 'g4')") + endif() + + string(TOLOWER "${STM32_HAL_ARG_SERIES}" SERIES_LOWER) + string(TOUPPER "${STM32_HAL_ARG_SERIES}" SERIES_UPPER) + + download_git( + NAME "stm32_hal_driver_${SERIES_LOWER}" + GIT_REPOSITORY "https://github.com/STMicroelectronics/stm32${SERIES_LOWER}xx-hal-driver.git" + GIT_TAG ${STM32_HAL_ARG_GIT_TAG} + TARGET_FOLDER "Inc Src" + OUTPUT_PATH_VAR STM32_HAL_DRIVER_PATH + ) + message(STATUS "Successfully fetched content for STM32 HAL driver ${SERIES_UPPER} from ${STM32_HAL_ARG_GIT_TAG} to ${STM32_HAL_DRIVER_PATH}") + add_library("STM32HAL_${SERIES_UPPER}" INTERFACE) + + target_include_directories( + "STM32HAL_${SERIES_UPPER}" + INTERFACE + "${STM32_HAL_DRIVER_PATH}/Inc" + "${STM32_HAL_DRIVER_PATH}/Inc/Legacy" + ) + + file(GLOB_RECURSE HAL_SOURCES "${STM32_HAL_DRIVER_PATH}/Src/*.c") + list(FILTER HAL_SOURCES EXCLUDE REGEX ".*_template\.c$") + target_sources( + "STM32HAL_${SERIES_UPPER}" + INTERFACE + ${HAL_SOURCES} + ) +endfunction() + +#[[ +@brief Adds a project to the build system +@param NAME The name of the project +@param PATH The location of the project relative to the CMakeLists.txt file +@param SERIES The STM32 series (e.g., "g4") +@param SPECIFIER The STM32 specifier (e.g., "g474re") +@param HAL_GIT_TAG The git tag for the STM32 HAL driver to use +@param CMSIS_GIT_TAG The git tag for the CMSIS device to use +@param CMSIS_MAJOR The major version of the CMSIS device to use +@note Link your user code against "${NAME}_USER_CODE" to ensure proper linking with the STM32 HAL and CMSIS libraries +]] +function(add_project) + if(NOT ${ARGC} EQUAL 14) + message( + FATAL_ERROR + "You called add_project with an unsupported number of inputs/arguments! Do better please :)" + ) + endif() + + set(one_value_args NAME PATH SERIES SPECIFIER HAL_GIT_TAG CMSIS_GIT_TAG CMSIS_MAJOR) + cmake_parse_arguments("ARG" "" "${one_value_args}" "" ${ARGN}) + + message(DEBUG "Adding project '${ARG_NAME}' at path '${ARG_PATH}' with SERIES '${ARG_SERIES}', SPECIFIER '${ARG_SPECIFIER}', HAL_GIT_TAG '${ARG_HAL_GIT_TAG}', CMSIS_GIT_TAG '${ARG_CMSIS_GIT_TAG}', and CMSIS_MAJOR '${ARG_CMSIS_MAJOR}'") + + add_arm_cmsis_interface( + SERIES ${ARG_SERIES} + SPECIFIER ${ARG_SPECIFIER} + GIT_TAG ${ARG_CMSIS_GIT_TAG} + ) + + add_stm32_hal_interface( + SERIES ${ARG_SERIES} + GIT_TAG ${ARG_HAL_GIT_TAG} + ) + + if(CMAKE_PRESET_NAME STREQUAL "HOOTLTest") + # TODO Later, out of scope for now + else() + message(STATUS "Adding project '${ARG_NAME}'") + add_executable("${ARG_NAME}") + + target_link_libraries( + "${ARG_NAME}" + PRIVATE + "CMSIS_Device_${ARG_SPECIFIER}" + "CMSIS_${ARG_CMSIS_MAJOR}_Core" + "STM32HAL_${ARG_SERIES}" + GLOBALSHARE_LIB + m + ) + + target_link_options( + "${ARG_NAME}" + PRIVATE + "LINKER:-Map=$/$.map" + ) + + target_compile_definitions( + "${ARG_NAME}" + PRIVATE + STM32${SERIES_UPPER}xx + USE_HAL_DRIVER + ${SPECIFIER_UPPER} + ) + endif() + + if(DEFINED NODE) + target_compile_definitions("${ARG_NAME}" PRIVATE NODE=${NODE}) + endif() + + block() + set(TARGET_NAME "${ARG_NAME}") + add_subdirectory("${PROJECT_SOURCE_DIR}/${ARG_PATH}") + # set_subdirectory_properties(PROPERTIES TARGET_NAME "${TARGET_NAME}") + endblock() +endfunction() diff --git a/Lib/cmake/gr-lib.cmake b/Lib/cmake/gr-lib.cmake index 619031bd6..3b931b8a0 100644 --- a/Lib/cmake/gr-lib.cmake +++ b/Lib/cmake/gr-lib.cmake @@ -41,7 +41,7 @@ function(add_gr_project) target_link_options( ${TARGET_NAME} PRIVATE - LINKER:-Map,$/$.map + "LINKER:-Map=$/$.map" ) if(DEFINED NODE) diff --git a/Testbench/CUBEMXTESTING/CMakeLists.txt b/Testbench/CUBEMXTESTING/CMakeLists.txt index a5341ae8f..350d7d986 100644 --- a/Testbench/CUBEMXTESTING/CMakeLists.txt +++ b/Testbench/CUBEMXTESTING/CMakeLists.txt @@ -1,31 +1,6 @@ -cmake_minimum_required(VERSION 3.25) - -# Setup compiler settings -set(CMAKE_C_STANDARD 11) -set(CMAKE_C_STANDARD_REQUIRED ON) -set(CMAKE_C_EXTENSIONS ON) - -# Define the build type -if(NOT CMAKE_BUILD_TYPE) - set(CMAKE_BUILD_TYPE "Debug") -endif() - -# Enable CMake support for ASM and C languages -enable_language( - C - ASM -) - -# Core project settings -project(${CMAKE_PROJECT_NAME}) - -# what, does in fact not get the filename of somthing but rather the name of the project from the path -get_filename_component(PROJECT_NAME ${CMAKE_CURRENT_SOURCE_DIR} NAME) - -add_library(${PROJECT_NAME}_USER_CODE INTERFACE) target_sources( - ${PROJECT_NAME}_USER_CODE - INTERFACE + ${TARGET_NAME} + PRIVATE Application/Src/CANdler.c Application/Src/Loop.c Core/Src/fdcan.c @@ -37,16 +12,16 @@ target_sources( ) target_link_libraries( - ${PROJECT_NAME}_USER_CODE - INTERFACE + ${TARGET_NAME} + PRIVATE CUBE_CAN_LIB CUBE_VCP_LIB LOGOMATIC_LIB ) target_include_directories( - ${PROJECT_NAME}_USER_CODE - INTERFACE + ${TARGET_NAME} + PRIVATE Core/Inc Application/Inc ) From cc5203ff82c47d6fe560cebc78ecd81ef1dfac4e Mon Sep 17 00:00:00 2001 From: Daniel Hansen Date: Sun, 23 Aug 2026 02:52:55 -0700 Subject: [PATCH 02/17] Linker hell (format) Signed-off-by: Daniel Hansen --- .gitignore | 18 +- Lib/Vendor/TargetFlags/README.md | 3 + Lib/Vendor/TargetFlags/stm32g4xx.cmake | 17 + Lib/Vendor/TargetFlags/stm32h5xx.cmake | 8 + Lib/Vendor/TargetFlags/stm32l4xx.cmake | 8 + Lib/Vendor/TargetFlags/stm32u5xx.cmake | 8 + Lib/cmake/cube.cmake | 74 ++- Testbench/CUBEMXTESTING/CMakeLists.txt | 67 +- Testbench/CUBEMXTESTING/CUBEMXTESTING.ioc | 2 +- Testbench/CUBEMXTESTING/Core/Inc/fdcan.h | 1 + Testbench/CUBEMXTESTING/Core/Inc/gpio.h | 1 + Testbench/CUBEMXTESTING/Core/Inc/main.h | 13 +- .../CUBEMXTESTING/Core/Inc/stm32_assert.h | 53 ++ .../Core/Inc/stm32g4xx_hal_conf.h | 215 ++++--- Testbench/CUBEMXTESTING/Core/Inc/tim.h | 1 + Testbench/CUBEMXTESTING/Core/Inc/usart.h | 1 + Testbench/CUBEMXTESTING/Core/Src/fdcan.c | 525 ++++++++-------- Testbench/CUBEMXTESTING/Core/Src/gpio.c | 537 ++++++++-------- Testbench/CUBEMXTESTING/Core/Src/main.c | 169 ++--- .../Core/Src/stm32g4xx_hal_msp.c | 24 +- .../CUBEMXTESTING/Core/Src/stm32g4xx_it.c | 211 ++++--- Testbench/CUBEMXTESTING/Core/Src/syscalls.c | 244 ++++++++ Testbench/CUBEMXTESTING/Core/Src/sysmem.c | 87 +++ .../CUBEMXTESTING/Core/Src/system_stm32g4xx.c | 287 +++++++++ Testbench/CUBEMXTESTING/Core/Src/tim.c | 113 ++-- Testbench/CUBEMXTESTING/Core/Src/usart.c | 164 ++--- Testbench/CUBEMXTESTING/STM32G474xx_FLASH.ld | 250 ++++++++ Testbench/CUBEMXTESTING/startup_stm32g474xx.s | 592 ++++++++++++++++++ 28 files changed, 2673 insertions(+), 1020 deletions(-) create mode 100644 Lib/Vendor/TargetFlags/README.md create mode 100644 Lib/Vendor/TargetFlags/stm32g4xx.cmake create mode 100644 Lib/Vendor/TargetFlags/stm32h5xx.cmake create mode 100644 Lib/Vendor/TargetFlags/stm32l4xx.cmake create mode 100644 Lib/Vendor/TargetFlags/stm32u5xx.cmake create mode 100644 Testbench/CUBEMXTESTING/Core/Inc/stm32_assert.h create mode 100644 Testbench/CUBEMXTESTING/Core/Src/syscalls.c create mode 100644 Testbench/CUBEMXTESTING/Core/Src/sysmem.c create mode 100644 Testbench/CUBEMXTESTING/Core/Src/system_stm32g4xx.c create mode 100644 Testbench/CUBEMXTESTING/STM32G474xx_FLASH.ld create mode 100644 Testbench/CUBEMXTESTING/startup_stm32g474xx.s diff --git a/.gitignore b/.gitignore index fbae0bc9a..531012429 100644 --- a/.gitignore +++ b/.gitignore @@ -85,7 +85,17 @@ GNUmakefile # CubeMX Integration EWARM .mxproject -*/Core/Src/system_stm32*xx.c -*/*/Core/Src/system_stm32*xx.c -*/Core/Inc/stm32_assert.h -*/*/Core/Inc/stm32_assert.h +*/cmake/stm32cubemx +*/*/cmake/stm32cubemx +*/cmake/CMakeLists.txt +*/*/cmake/CMakeLists.txt +*/cmake/gcc-arm-none-eabi.cmake +*/*/cmake/gcc-arm-none-eabi.cmake +*/cmake/starm-clang.cmake +*/*/cmake/starm-clang.cmake +*/Drivers +*/*/Drivers +*/CMakeLists.txt +*/*/CMakeLists.txt +*/CMakePresets.json +*/*/CMakePresets.json diff --git a/Lib/Vendor/TargetFlags/README.md b/Lib/Vendor/TargetFlags/README.md new file mode 100644 index 000000000..e714aca70 --- /dev/null +++ b/Lib/Vendor/TargetFlags/README.md @@ -0,0 +1,3 @@ +# Vendor Target Flags + +TODO diff --git a/Lib/Vendor/TargetFlags/stm32g4xx.cmake b/Lib/Vendor/TargetFlags/stm32g4xx.cmake new file mode 100644 index 000000000..89405f61f --- /dev/null +++ b/Lib/Vendor/TargetFlags/stm32g4xx.cmake @@ -0,0 +1,17 @@ +target_compile_options( + ${TARGET_NAME} + PRIVATE + -mcpu=cortex-m4 + -mfpu=fpv4-sp-d16 + -mfloat-abi=hard + -mthumb +) + +target_link_options( + ${TARGET_NAME} + PRIVATE + -mcpu=cortex-m4 + -mfpu=fpv4-sp-d16 + -mfloat-abi=hard + -mthumb +) diff --git a/Lib/Vendor/TargetFlags/stm32h5xx.cmake b/Lib/Vendor/TargetFlags/stm32h5xx.cmake new file mode 100644 index 000000000..372a7a537 --- /dev/null +++ b/Lib/Vendor/TargetFlags/stm32h5xx.cmake @@ -0,0 +1,8 @@ +target_compile_options( + ${TARGET_NAME} + PRIVATE + -mcpu=cortex-m33 + -mfpu=fpv5-sp-d16 + -mfloat-abi=hard + -mthumb +) diff --git a/Lib/Vendor/TargetFlags/stm32l4xx.cmake b/Lib/Vendor/TargetFlags/stm32l4xx.cmake new file mode 100644 index 000000000..0f074d3d0 --- /dev/null +++ b/Lib/Vendor/TargetFlags/stm32l4xx.cmake @@ -0,0 +1,8 @@ +target_compile_options( + ${TARGET_NAME} + PRIVATE + -mcpu=cortex-m4 + -mfpu=fpv4-sp-d16 + -mfloat-abi=hard + -mthumb +) diff --git a/Lib/Vendor/TargetFlags/stm32u5xx.cmake b/Lib/Vendor/TargetFlags/stm32u5xx.cmake new file mode 100644 index 000000000..3f127fcf2 --- /dev/null +++ b/Lib/Vendor/TargetFlags/stm32u5xx.cmake @@ -0,0 +1,8 @@ +target_compile_options( + ${TARGET_NAME} + PRIVATE + -mcpu=cortex-m33 + -mfpu=fpv4-sp-d16 + -mfloat-abi=hard + -mthumb +) diff --git a/Lib/cmake/cube.cmake b/Lib/cmake/cube.cmake index 0e9733936..a8caf1b4f 100644 --- a/Lib/cmake/cube.cmake +++ b/Lib/cmake/cube.cmake @@ -1,9 +1,16 @@ -# Prefer calling add_project() instead of the other functions directly -# Note that add_project() will automatically add the project to the build system and link it against the appropriate CMSIS and HAL libraries -# Link your user code against "${NAME}_USER_CODE" to ensure proper linking with the STM32 HAL and CMSIS libraries - +cmake_minimum_required(VERSION 3.25) include(FetchContent) +#[[ +@brief Downloads a git repository and checks out a specific tag, using sparse checkout to only fetch specific folders +@param NAME The name of the git repository (used for FetchContent) +@param GIT_REPOSITORY The URL of the git repository to download +@param GIT_TAG The git tag to checkout +@param OUTPUT_PATH_VAR The variable to set with the path to the downloaded repository +@param TARGET_FOLDER The folder(s) to fetch from the repository (sparse checkout) +@note This function uses FetchContent to download the repository and sparse checkout to only fetch the specified folder(s) +@remark Prefer calling add_project() instead of this function directly +]] function(download_git) if(NOT ${ARGC} EQUAL 10) message( @@ -92,7 +99,7 @@ function(add_arm_cmsis_core) target_include_directories( CMSIS_${ARM_CMSIS_CORE_ARG_MAJOR}_Core INTERFACE - "${ARM_CMSIS_CORE_PATH}/CMSIS/Core/Include" + $ ) endfunction() @@ -142,7 +149,7 @@ function(add_arm_cmsis_interface) NAME "cmsis_device_${SERIES_LOWER}" GIT_REPOSITORY "https://github.com/STMicroelectronics/cmsis-device-${SERIES_LOWER}.git" GIT_TAG ${ARM_CMSIS_INTERFACE_ARG_GIT_TAG} - TARGET_FOLDER "Include Source/Templates/gcc" + TARGET_FOLDER "Include" OUTPUT_PATH_VAR CMSIS_DEVICE_PATH ) message(STATUS "Successfully fetched content for ARM CMSIS device ${SPECIFIER_UPPER} from ${ARM_CMSIS_INTERFACE_ARG_GIT_TAG} to ${CMSIS_DEVICE_PATH}") @@ -150,13 +157,13 @@ function(add_arm_cmsis_interface) target_include_directories( "CMSIS_Device_${SPECIFIER_UPPER}" INTERFACE - "${CMSIS_DEVICE_PATH}/Include" + $ ) - target_sources( + target_compile_definitions( "CMSIS_Device_${SPECIFIER_UPPER}" INTERFACE - "${CMSIS_DEVICE_PATH}/Source/Templates/gcc/startup_stm32${SPECIFIER_LOWER}.s" - "${CMSIS_DEVICE_PATH}/Source/Templates/system_stm32${SERIES_LOWER}xx.c" + "STM32${SERIES_UPPER}xx" + "USE_HAL_DRIVER" ) endfunction() @@ -176,8 +183,6 @@ function(add_stm32_hal_interface) endif() set(one_value_args SERIES GIT_TAG) - unset(STM32_HAL_ARG_SERIES) - unset(STM32_HAL_ARG_GIT_TAG) cmake_parse_arguments("STM32_HAL_ARG" "" "${one_value_args}" "" ${ARGN}) message(VERBOSE "Adding STM32 HAL driver interface for SERIES '${STM32_HAL_ARG_SERIES}' with GIT_TAG '${STM32_HAL_ARG_GIT_TAG}'") @@ -203,11 +208,11 @@ function(add_stm32_hal_interface) target_include_directories( "STM32HAL_${SERIES_UPPER}" INTERFACE - "${STM32_HAL_DRIVER_PATH}/Inc" - "${STM32_HAL_DRIVER_PATH}/Inc/Legacy" + $ + $ ) - file(GLOB_RECURSE HAL_SOURCES "${STM32_HAL_DRIVER_PATH}/Src/*.c") + file(GLOB_RECURSE HAL_SOURCES CONFIGURE_DEPENDS "${STM32_HAL_DRIVER_PATH}/Src/*.c") list(FILTER HAL_SOURCES EXCLUDE REGEX ".*_template\.c$") target_sources( "STM32HAL_${SERIES_UPPER}" @@ -237,6 +242,9 @@ function(add_project) set(one_value_args NAME PATH SERIES SPECIFIER HAL_GIT_TAG CMSIS_GIT_TAG CMSIS_MAJOR) cmake_parse_arguments("ARG" "" "${one_value_args}" "" ${ARGN}) + string(TOUPPER "${ARG_SERIES}" SERIES_UPPER) + string(TOLOWER "${ARG_SERIES}" SERIES_LOWER) + string(TOUPPER "${ARG_SPECIFIER}" SPECIFIER_UPPER) message(DEBUG "Adding project '${ARG_NAME}' at path '${ARG_PATH}' with SERIES '${ARG_SERIES}', SPECIFIER '${ARG_SPECIFIER}', HAL_GIT_TAG '${ARG_HAL_GIT_TAG}', CMSIS_GIT_TAG '${ARG_CMSIS_GIT_TAG}', and CMSIS_MAJOR '${ARG_CMSIS_MAJOR}'") @@ -254,31 +262,41 @@ function(add_project) if(CMAKE_PRESET_NAME STREQUAL "HOOTLTest") # TODO Later, out of scope for now else() - message(STATUS "Adding project '${ARG_NAME}'") - add_executable("${ARG_NAME}") + set(TARGET_NAME "${ARG_NAME}") + message(STATUS "Adding project '${TARGET_NAME}'") + add_executable("${TARGET_NAME}") + + include("${PROJECT_SOURCE_DIR}/Lib/Vendor/TargetFlags/stm32${SERIES_LOWER}xx.cmake") + + target_compile_options( + "${TARGET_NAME}" + PRIVATE + "${stm32${SERIES_LOWER}xx_flags}" + ) target_link_libraries( - "${ARG_NAME}" + "${TARGET_NAME}" PRIVATE - "CMSIS_Device_${ARG_SPECIFIER}" + "CMSIS_Device_${SPECIFIER_UPPER}" "CMSIS_${ARG_CMSIS_MAJOR}_Core" - "STM32HAL_${ARG_SERIES}" + "STM32HAL_${SERIES_UPPER}" + # "stm32${SERIES_LOWER}xx_flags" GLOBALSHARE_LIB m ) target_link_options( - "${ARG_NAME}" + "${TARGET_NAME}" PRIVATE - "LINKER:-Map=$/$.map" + "LINKER:-Map=$/$.map" ) target_compile_definitions( - "${ARG_NAME}" + "${TARGET_NAME}" PRIVATE - STM32${SERIES_UPPER}xx USE_HAL_DRIVER - ${SPECIFIER_UPPER} + USE_FULL_LL_DRIVER + STM32${SERIES_UPPER}xx ) endif() @@ -286,9 +304,5 @@ function(add_project) target_compile_definitions("${ARG_NAME}" PRIVATE NODE=${NODE}) endif() - block() - set(TARGET_NAME "${ARG_NAME}") - add_subdirectory("${PROJECT_SOURCE_DIR}/${ARG_PATH}") - # set_subdirectory_properties(PROPERTIES TARGET_NAME "${TARGET_NAME}") - endblock() + add_subdirectory("${PROJECT_SOURCE_DIR}/${ARG_PATH}") endfunction() diff --git a/Testbench/CUBEMXTESTING/CMakeLists.txt b/Testbench/CUBEMXTESTING/CMakeLists.txt index 350d7d986..a3c82d523 100644 --- a/Testbench/CUBEMXTESTING/CMakeLists.txt +++ b/Testbench/CUBEMXTESTING/CMakeLists.txt @@ -1,27 +1,52 @@ -target_sources( - ${TARGET_NAME} - PRIVATE - Application/Src/CANdler.c - Application/Src/Loop.c - Core/Src/fdcan.c - Core/Src/gpio.c - Core/Src/main.c - Core/Src/stm32g4xx_it.c - Core/Src/tim.c - Core/Src/usart.c +#[[ +Required components (orderless) +- Link options for the GCC linker script +- Compile definitions for the chip subfamily +- Includes for the project +- Sources for the project +- Additional link libraries for the project +]] + +target_link_options( + ${TARGET_NAME} + PRIVATE + -T "${CMAKE_CURRENT_SOURCE_DIR}/STM32G474xx_FLASH.ld" ) -target_link_libraries( - ${TARGET_NAME} - PRIVATE - CUBE_CAN_LIB - CUBE_VCP_LIB - LOGOMATIC_LIB +target_compile_definitions( + ${TARGET_NAME} + PRIVATE + STM32G474xx ) target_include_directories( - ${TARGET_NAME} - PRIVATE - Core/Inc - Application/Inc + ${TARGET_NAME} + PRIVATE + Core/Inc + Application/Inc +) + +target_sources( + ${TARGET_NAME} + PRIVATE + Application/Src/CANdler.c + Application/Src/Loop.c + Core/Src/fdcan.c + Core/Src/gpio.c + Core/Src/main.c + Core/Src/stm32g4xx_it.c + Core/Src/syscalls.c + Core/Src/sysmem.c + Core/Src/system_stm32g4xx.c + Core/Src/tim.c + Core/Src/usart.c + startup_stm32g474xx.s +) + +target_link_libraries( + ${TARGET_NAME} + PRIVATE + CUBE_CAN_LIB + CUBE_VCP_LIB + LOGOMATIC_LIB ) diff --git a/Testbench/CUBEMXTESTING/CUBEMXTESTING.ioc b/Testbench/CUBEMXTESTING/CUBEMXTESTING.ioc index eb06b6e12..e2ae4489b 100644 --- a/Testbench/CUBEMXTESTING/CUBEMXTESTING.ioc +++ b/Testbench/CUBEMXTESTING/CUBEMXTESTING.ioc @@ -155,7 +155,7 @@ ProjectManager.ProjectName=CUBEMXTESTING ProjectManager.ProjectStructure= ProjectManager.RegisterCallBack= ProjectManager.StackSize=0x400 -ProjectManager.TargetToolchain=EWARM V8.50 +ProjectManager.TargetToolchain=CMake ProjectManager.TemplateDestinationPath=C\:\\Users\\maxnm\\Firmware\\CUBEMXTESTING ProjectManager.TemplateSourcePath=C\:\\Users\\maxnm\\Firmware\\Lib\\CubeMXTemplates ProjectManager.TemplatesList=\\Autogen\\Inc\\can_cfg_h.ftl, diff --git a/Testbench/CUBEMXTESTING/Core/Inc/fdcan.h b/Testbench/CUBEMXTESTING/Core/Inc/fdcan.h index 3597c6476..21271cf64 100644 --- a/Testbench/CUBEMXTESTING/Core/Inc/fdcan.h +++ b/Testbench/CUBEMXTESTING/Core/Inc/fdcan.h @@ -55,3 +55,4 @@ void MX_FDCAN3_Init(void); #endif #endif /* __FDCAN_H__ */ + diff --git a/Testbench/CUBEMXTESTING/Core/Inc/gpio.h b/Testbench/CUBEMXTESTING/Core/Inc/gpio.h index 37dcc0a5c..03c2faca5 100644 --- a/Testbench/CUBEMXTESTING/Core/Inc/gpio.h +++ b/Testbench/CUBEMXTESTING/Core/Inc/gpio.h @@ -46,3 +46,4 @@ void MX_GPIO_Init(void); } #endif #endif /*__ GPIO_H__ */ + diff --git a/Testbench/CUBEMXTESTING/Core/Inc/main.h b/Testbench/CUBEMXTESTING/Core/Inc/main.h index cbeced83f..2b50abc31 100644 --- a/Testbench/CUBEMXTESTING/Core/Inc/main.h +++ b/Testbench/CUBEMXTESTING/Core/Inc/main.h @@ -28,16 +28,17 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" + +#include "stm32g4xx_ll_rcc.h" #include "stm32g4xx_ll_bus.h" -#include "stm32g4xx_ll_cortex.h" #include "stm32g4xx_ll_crs.h" -#include "stm32g4xx_ll_dma.h" -#include "stm32g4xx_ll_exti.h" -#include "stm32g4xx_ll_gpio.h" -#include "stm32g4xx_ll_pwr.h" -#include "stm32g4xx_ll_rcc.h" #include "stm32g4xx_ll_system.h" +#include "stm32g4xx_ll_exti.h" +#include "stm32g4xx_ll_cortex.h" #include "stm32g4xx_ll_utils.h" +#include "stm32g4xx_ll_pwr.h" +#include "stm32g4xx_ll_dma.h" +#include "stm32g4xx_ll_gpio.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ diff --git a/Testbench/CUBEMXTESTING/Core/Inc/stm32_assert.h b/Testbench/CUBEMXTESTING/Core/Inc/stm32_assert.h new file mode 100644 index 000000000..61631c41e --- /dev/null +++ b/Testbench/CUBEMXTESTING/Core/Inc/stm32_assert.h @@ -0,0 +1,53 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32_assert.h + * @author MCD Application Team + * @brief STM32 assert file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_ASSERT_H +#define __STM32_ASSERT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Includes ------------------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ +void assert_failed(uint8_t *file, uint32_t line); +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_ASSERT_H */ + diff --git a/Testbench/CUBEMXTESTING/Core/Inc/stm32g4xx_hal_conf.h b/Testbench/CUBEMXTESTING/Core/Inc/stm32g4xx_hal_conf.h index d12d585bd..e4db34d37 100644 --- a/Testbench/CUBEMXTESTING/Core/Inc/stm32g4xx_hal_conf.h +++ b/Testbench/CUBEMXTESTING/Core/Inc/stm32g4xx_hal_conf.h @@ -23,7 +23,7 @@ #define STM32G4xx_HAL_CONF_H #ifdef __cplusplus -extern "C" { + extern "C" { #endif /* Exported types ------------------------------------------------------------*/ @@ -31,12 +31,12 @@ extern "C" { /* ########################## Module Selection ############################## */ /** - * @brief This is the list of modules to be used in the HAL driver - */ + * @brief This is the list of modules to be used in the HAL driver + */ #define HAL_MODULE_ENABLED -/*#define HAL_ADC_MODULE_ENABLED */ + /*#define HAL_ADC_MODULE_ENABLED */ /*#define HAL_COMP_MODULE_ENABLED */ /*#define HAL_CORDIC_MODULE_ENABLED */ /*#define HAL_CRC_MODULE_ENABLED */ @@ -76,124 +76,123 @@ extern "C" { /* ########################## Register Callbacks selection ############################## */ /** - * @brief This is the list of modules where register callback can be used - */ -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U -#define USE_HAL_COMP_REGISTER_CALLBACKS 0U -#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U -#define USE_HAL_EXTI_REGISTER_CALLBACKS 0U -#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U -#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U -#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U -#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U -#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U -#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U -#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U -#define USE_HAL_UART_REGISTER_CALLBACKS 0U -#define USE_HAL_USART_REGISTER_CALLBACKS 0U -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U + * @brief This is the list of modules where register callback can be used + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U +#define USE_HAL_COMP_REGISTER_CALLBACKS 0U +#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U +#define USE_HAL_EXTI_REGISTER_CALLBACKS 0U +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U +#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U +#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U +#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U +#define USE_HAL_UART_REGISTER_CALLBACKS 0U +#define USE_HAL_USART_REGISTER_CALLBACKS 0U +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* ########################## Oscillator Values adaptation ####################*/ /** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined(HSE_VALUE) -#define HSE_VALUE (16000000UL) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined(HSE_STARTUP_TIMEOUT) -#define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE (16000000UL) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ /** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined(HSI_VALUE) -#define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ /** - * @brief Internal High Speed oscillator (HSI48) value for USB FS and RNG. - * This internal oscillator is mainly dedicated to provide a high precision clock to - * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. - * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency - * which is subject to manufacturing process variations. - */ -#if !defined(HSI48_VALUE) -#define HSI48_VALUE \ - (48000000UL) /*!< Value of the Internal High Speed oscillator for USB FS/RNG in Hz. \ - The real value my vary depending on manufacturing process variations.*/ -#endif /* HSI48_VALUE */ + * @brief Internal High Speed oscillator (HSI48) value for USB FS and RNG. + * This internal oscillator is mainly dedicated to provide a high precision clock to + * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. + * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency + * which is subject to manufacturing process variations. + */ +#if !defined (HSI48_VALUE) + #define HSI48_VALUE (48000000UL) /*!< Value of the Internal High Speed oscillator for USB FS/RNG in Hz. + The real value my vary depending on manufacturing process variations.*/ +#endif /* HSI48_VALUE */ /** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined(LSI_VALUE) + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature.*/ -#define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/ -#endif /* LSI_VALUE */ +#define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /** - * @brief External Low Speed oscillator (LSE) value. - * This value is used by the UART, RTC HAL module to compute the system frequency - */ -#if !defined(LSE_VALUE) -#define LSE_VALUE (32768UL) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) +#define LSE_VALUE (32768UL) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ -#if !defined(LSE_STARTUP_TIMEOUT) -#define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ +#if !defined (LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ /** - * @brief External clock source for I2S and SAI peripherals - * This value is used by the I2S and SAI HAL modules to compute the I2S and SAI clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined(EXTERNAL_CLOCK_VALUE) -#define EXTERNAL_CLOCK_VALUE (12288000UL) /*!< Value of the External oscillator in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ + * @brief External clock source for I2S and SAI peripherals + * This value is used by the I2S and SAI HAL modules to compute the I2S and SAI clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) +#define EXTERNAL_CLOCK_VALUE (12288000UL) /*!< Value of the External oscillator in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ /* Tip: To avoid modifying this file each time you need to use different HSE, === you can define the HSE value in your toolchain compiler preprocessor. */ /* ########################### System Configuration ######################### */ /** - * @brief This is the HAL system configuration section - */ + * @brief This is the HAL system configuration section + */ -#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority (lowest by default) */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 0U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U +#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority (lowest by default) */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 0U +#define INSTRUCTION_CACHE_ENABLE 1U +#define DATA_CACHE_ENABLE 1U /* ########################## Assert Selection ############################## */ /** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -#define USE_FULL_ASSERT 1U + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ + #define USE_FULL_ASSERT 1U /* ################## SPI peripheral configuration ########################## */ @@ -202,12 +201,12 @@ The real value may vary depending on the variations in voltage and temperature.* * Deactivated: CRC code cleaned from driver */ -#define USE_SPI_CRC 0U +#define USE_SPI_CRC 0U /* Includes ------------------------------------------------------------------*/ /** - * @brief Include module's header file - */ + * @brief Include module's header file + */ #ifdef HAL_RCC_MODULE_ENABLED #include "stm32g4xx_hal_rcc.h" @@ -358,15 +357,15 @@ The real value may vary depending on the variations in voltage and temperature.* #endif /* HAL_WWDG_MODULE_ENABLED */ /* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT +#ifdef USE_FULL_ASSERT /** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) /* Exported functions ------------------------------------------------------- */ void assert_failed(uint8_t *file, uint32_t line); diff --git a/Testbench/CUBEMXTESTING/Core/Inc/tim.h b/Testbench/CUBEMXTESTING/Core/Inc/tim.h index 2d20bd560..b90657cf4 100644 --- a/Testbench/CUBEMXTESTING/Core/Inc/tim.h +++ b/Testbench/CUBEMXTESTING/Core/Inc/tim.h @@ -49,3 +49,4 @@ void MX_TIM5_Init(void); #endif #endif /* __TIM_H__ */ + diff --git a/Testbench/CUBEMXTESTING/Core/Inc/usart.h b/Testbench/CUBEMXTESTING/Core/Inc/usart.h index bdec0c9cb..49dd0cccc 100644 --- a/Testbench/CUBEMXTESTING/Core/Inc/usart.h +++ b/Testbench/CUBEMXTESTING/Core/Inc/usart.h @@ -49,3 +49,4 @@ void MX_LPUART1_UART_Init(void); #endif #endif /* __USART_H__ */ + diff --git a/Testbench/CUBEMXTESTING/Core/Src/fdcan.c b/Testbench/CUBEMXTESTING/Core/Src/fdcan.c index 30b3c9dc1..08b2a1b8a 100644 --- a/Testbench/CUBEMXTESTING/Core/Src/fdcan.c +++ b/Testbench/CUBEMXTESTING/Core/Src/fdcan.c @@ -32,281 +32,298 @@ FDCAN_HandleTypeDef hfdcan3; void MX_FDCAN1_Init(void) { - /* USER CODE BEGIN FDCAN1_Init 0 */ - - /* USER CODE END FDCAN1_Init 0 */ - - /* USER CODE BEGIN FDCAN1_Init 1 */ - - /* USER CODE END FDCAN1_Init 1 */ - hfdcan1.Instance = FDCAN1; - hfdcan1.Init.ClockDivider = FDCAN_CLOCK_DIV1; - hfdcan1.Init.FrameFormat = FDCAN_FRAME_CLASSIC; - hfdcan1.Init.Mode = FDCAN_MODE_INTERNAL_LOOPBACK; - hfdcan1.Init.AutoRetransmission = ENABLE; - hfdcan1.Init.TransmitPause = DISABLE; - hfdcan1.Init.ProtocolException = ENABLE; - hfdcan1.Init.NominalPrescaler = 1; - hfdcan1.Init.NominalSyncJumpWidth = 16; - hfdcan1.Init.NominalTimeSeg1 = 119; - hfdcan1.Init.NominalTimeSeg2 = 40; - hfdcan1.Init.DataPrescaler = 8; - hfdcan1.Init.DataSyncJumpWidth = 16; - hfdcan1.Init.DataTimeSeg1 = 14; - hfdcan1.Init.DataTimeSeg2 = 5; - hfdcan1.Init.StdFiltersNbr = 0; - hfdcan1.Init.ExtFiltersNbr = 2; - hfdcan1.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; - if (HAL_FDCAN_Init(&hfdcan1) != HAL_OK) { - Error_Handler(); - } - /* USER CODE BEGIN FDCAN1_Init 2 */ - - /* USER CODE END FDCAN1_Init 2 */ + /* USER CODE BEGIN FDCAN1_Init 0 */ + + /* USER CODE END FDCAN1_Init 0 */ + + /* USER CODE BEGIN FDCAN1_Init 1 */ + + /* USER CODE END FDCAN1_Init 1 */ + hfdcan1.Instance = FDCAN1; + hfdcan1.Init.ClockDivider = FDCAN_CLOCK_DIV1; + hfdcan1.Init.FrameFormat = FDCAN_FRAME_CLASSIC; + hfdcan1.Init.Mode = FDCAN_MODE_INTERNAL_LOOPBACK; + hfdcan1.Init.AutoRetransmission = ENABLE; + hfdcan1.Init.TransmitPause = DISABLE; + hfdcan1.Init.ProtocolException = ENABLE; + hfdcan1.Init.NominalPrescaler = 1; + hfdcan1.Init.NominalSyncJumpWidth = 16; + hfdcan1.Init.NominalTimeSeg1 = 119; + hfdcan1.Init.NominalTimeSeg2 = 40; + hfdcan1.Init.DataPrescaler = 8; + hfdcan1.Init.DataSyncJumpWidth = 16; + hfdcan1.Init.DataTimeSeg1 = 14; + hfdcan1.Init.DataTimeSeg2 = 5; + hfdcan1.Init.StdFiltersNbr = 0; + hfdcan1.Init.ExtFiltersNbr = 2; + hfdcan1.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; + if (HAL_FDCAN_Init(&hfdcan1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN FDCAN1_Init 2 */ + + /* USER CODE END FDCAN1_Init 2 */ + } /* FDCAN2 init function */ void MX_FDCAN2_Init(void) { - /* USER CODE BEGIN FDCAN2_Init 0 */ - - /* USER CODE END FDCAN2_Init 0 */ - - /* USER CODE BEGIN FDCAN2_Init 1 */ - - /* USER CODE END FDCAN2_Init 1 */ - hfdcan2.Instance = FDCAN2; - hfdcan2.Init.ClockDivider = FDCAN_CLOCK_DIV1; - hfdcan2.Init.FrameFormat = FDCAN_FRAME_CLASSIC; - hfdcan2.Init.Mode = FDCAN_MODE_INTERNAL_LOOPBACK; - hfdcan2.Init.AutoRetransmission = ENABLE; - hfdcan2.Init.TransmitPause = DISABLE; - hfdcan2.Init.ProtocolException = ENABLE; - hfdcan2.Init.NominalPrescaler = 1; - hfdcan2.Init.NominalSyncJumpWidth = 16; - hfdcan2.Init.NominalTimeSeg1 = 119; - hfdcan2.Init.NominalTimeSeg2 = 40; - hfdcan2.Init.DataPrescaler = 8; - hfdcan2.Init.DataSyncJumpWidth = 16; - hfdcan2.Init.DataTimeSeg1 = 14; - hfdcan2.Init.DataTimeSeg2 = 5; - hfdcan2.Init.StdFiltersNbr = 0; - hfdcan2.Init.ExtFiltersNbr = 2; - hfdcan2.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; - if (HAL_FDCAN_Init(&hfdcan2) != HAL_OK) { - Error_Handler(); - } - /* USER CODE BEGIN FDCAN2_Init 2 */ - - /* USER CODE END FDCAN2_Init 2 */ + /* USER CODE BEGIN FDCAN2_Init 0 */ + + /* USER CODE END FDCAN2_Init 0 */ + + /* USER CODE BEGIN FDCAN2_Init 1 */ + + /* USER CODE END FDCAN2_Init 1 */ + hfdcan2.Instance = FDCAN2; + hfdcan2.Init.ClockDivider = FDCAN_CLOCK_DIV1; + hfdcan2.Init.FrameFormat = FDCAN_FRAME_CLASSIC; + hfdcan2.Init.Mode = FDCAN_MODE_INTERNAL_LOOPBACK; + hfdcan2.Init.AutoRetransmission = ENABLE; + hfdcan2.Init.TransmitPause = DISABLE; + hfdcan2.Init.ProtocolException = ENABLE; + hfdcan2.Init.NominalPrescaler = 1; + hfdcan2.Init.NominalSyncJumpWidth = 16; + hfdcan2.Init.NominalTimeSeg1 = 119; + hfdcan2.Init.NominalTimeSeg2 = 40; + hfdcan2.Init.DataPrescaler = 8; + hfdcan2.Init.DataSyncJumpWidth = 16; + hfdcan2.Init.DataTimeSeg1 = 14; + hfdcan2.Init.DataTimeSeg2 = 5; + hfdcan2.Init.StdFiltersNbr = 0; + hfdcan2.Init.ExtFiltersNbr = 2; + hfdcan2.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; + if (HAL_FDCAN_Init(&hfdcan2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN FDCAN2_Init 2 */ + + /* USER CODE END FDCAN2_Init 2 */ + } /* FDCAN3 init function */ void MX_FDCAN3_Init(void) { - /* USER CODE BEGIN FDCAN3_Init 0 */ - - /* USER CODE END FDCAN3_Init 0 */ - - /* USER CODE BEGIN FDCAN3_Init 1 */ - - /* USER CODE END FDCAN3_Init 1 */ - hfdcan3.Instance = FDCAN3; - hfdcan3.Init.ClockDivider = FDCAN_CLOCK_DIV1; - hfdcan3.Init.FrameFormat = FDCAN_FRAME_CLASSIC; - hfdcan3.Init.Mode = FDCAN_MODE_INTERNAL_LOOPBACK; - hfdcan3.Init.AutoRetransmission = DISABLE; - hfdcan3.Init.TransmitPause = DISABLE; - hfdcan3.Init.ProtocolException = DISABLE; - hfdcan3.Init.NominalPrescaler = 16; - hfdcan3.Init.NominalSyncJumpWidth = 1; - hfdcan3.Init.NominalTimeSeg1 = 1; - hfdcan3.Init.NominalTimeSeg2 = 1; - hfdcan3.Init.DataPrescaler = 1; - hfdcan3.Init.DataSyncJumpWidth = 1; - hfdcan3.Init.DataTimeSeg1 = 1; - hfdcan3.Init.DataTimeSeg2 = 1; - hfdcan3.Init.StdFiltersNbr = 0; - hfdcan3.Init.ExtFiltersNbr = 0; - hfdcan3.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; - if (HAL_FDCAN_Init(&hfdcan3) != HAL_OK) { - Error_Handler(); - } - /* USER CODE BEGIN FDCAN3_Init 2 */ - - /* USER CODE END FDCAN3_Init 2 */ + /* USER CODE BEGIN FDCAN3_Init 0 */ + + /* USER CODE END FDCAN3_Init 0 */ + + /* USER CODE BEGIN FDCAN3_Init 1 */ + + /* USER CODE END FDCAN3_Init 1 */ + hfdcan3.Instance = FDCAN3; + hfdcan3.Init.ClockDivider = FDCAN_CLOCK_DIV1; + hfdcan3.Init.FrameFormat = FDCAN_FRAME_CLASSIC; + hfdcan3.Init.Mode = FDCAN_MODE_INTERNAL_LOOPBACK; + hfdcan3.Init.AutoRetransmission = DISABLE; + hfdcan3.Init.TransmitPause = DISABLE; + hfdcan3.Init.ProtocolException = DISABLE; + hfdcan3.Init.NominalPrescaler = 16; + hfdcan3.Init.NominalSyncJumpWidth = 1; + hfdcan3.Init.NominalTimeSeg1 = 1; + hfdcan3.Init.NominalTimeSeg2 = 1; + hfdcan3.Init.DataPrescaler = 1; + hfdcan3.Init.DataSyncJumpWidth = 1; + hfdcan3.Init.DataTimeSeg1 = 1; + hfdcan3.Init.DataTimeSeg2 = 1; + hfdcan3.Init.StdFiltersNbr = 0; + hfdcan3.Init.ExtFiltersNbr = 0; + hfdcan3.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; + if (HAL_FDCAN_Init(&hfdcan3) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN FDCAN3_Init 2 */ + + /* USER CODE END FDCAN3_Init 2 */ + } -static uint32_t HAL_RCC_FDCAN_CLK_ENABLED = 0; +static uint32_t HAL_RCC_FDCAN_CLK_ENABLED=0; -void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *fdcanHandle) +void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* fdcanHandle) { - GPIO_InitTypeDef GPIO_InitStruct = {0}; - if (fdcanHandle->Instance == FDCAN1) { - /* USER CODE BEGIN FDCAN1_MspInit 0 */ - - /* USER CODE END FDCAN1_MspInit 0 */ - LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_PCLK1); - - /* FDCAN1 clock enable */ - HAL_RCC_FDCAN_CLK_ENABLED++; - if (HAL_RCC_FDCAN_CLK_ENABLED == 1) { - __HAL_RCC_FDCAN_CLK_ENABLE(); - } - - __HAL_RCC_GPIOB_CLK_ENABLE(); - /**FDCAN1 GPIO Configuration - PB8-BOOT0 ------> FDCAN1_RX - PB9 ------> FDCAN1_TX - */ - GPIO_InitStruct.Pin = GPIO_PIN_8 | GPIO_PIN_9; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN1; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /* FDCAN1 interrupt Init */ - HAL_NVIC_SetPriority(FDCAN1_IT0_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(FDCAN1_IT0_IRQn); - /* USER CODE BEGIN FDCAN1_MspInit 1 */ - - /* USER CODE END FDCAN1_MspInit 1 */ - } else if (fdcanHandle->Instance == FDCAN2) { - /* USER CODE BEGIN FDCAN2_MspInit 0 */ - - /* USER CODE END FDCAN2_MspInit 0 */ - - LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_PCLK1); - - /* FDCAN2 clock enable */ - HAL_RCC_FDCAN_CLK_ENABLED++; - if (HAL_RCC_FDCAN_CLK_ENABLED == 1) { - __HAL_RCC_FDCAN_CLK_ENABLE(); - } - - __HAL_RCC_GPIOB_CLK_ENABLE(); - /**FDCAN2 GPIO Configuration - PB12 ------> FDCAN2_RX - PB13 ------> FDCAN2_TX - */ - GPIO_InitStruct.Pin = GPIO_PIN_12 | GPIO_PIN_13; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN2; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /* FDCAN2 interrupt Init */ - HAL_NVIC_SetPriority(FDCAN2_IT0_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(FDCAN2_IT0_IRQn); - /* USER CODE BEGIN FDCAN2_MspInit 1 */ - - /* USER CODE END FDCAN2_MspInit 1 */ - } else if (fdcanHandle->Instance == FDCAN3) { - /* USER CODE BEGIN FDCAN3_MspInit 0 */ - - /* USER CODE END FDCAN3_MspInit 0 */ - - LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_PCLK1); - - /* FDCAN3 clock enable */ - HAL_RCC_FDCAN_CLK_ENABLED++; - if (HAL_RCC_FDCAN_CLK_ENABLED == 1) { - __HAL_RCC_FDCAN_CLK_ENABLE(); - } - - __HAL_RCC_GPIOA_CLK_ENABLE(); - /**FDCAN3 GPIO Configuration - PA8 ------> FDCAN3_RX - PA15 ------> FDCAN3_TX - */ - GPIO_InitStruct.Pin = GPIO_PIN_8 | GPIO_PIN_15; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF11_FDCAN3; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /* FDCAN3 interrupt Init */ - HAL_NVIC_SetPriority(FDCAN3_IT0_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(FDCAN3_IT0_IRQn); - /* USER CODE BEGIN FDCAN3_MspInit 1 */ - - /* USER CODE END FDCAN3_MspInit 1 */ - } + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(fdcanHandle->Instance==FDCAN1) + { + /* USER CODE BEGIN FDCAN1_MspInit 0 */ + + /* USER CODE END FDCAN1_MspInit 0 */ + LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_PCLK1); + + /* FDCAN1 clock enable */ + HAL_RCC_FDCAN_CLK_ENABLED++; + if(HAL_RCC_FDCAN_CLK_ENABLED==1){ + __HAL_RCC_FDCAN_CLK_ENABLE(); + } + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**FDCAN1 GPIO Configuration + PB8-BOOT0 ------> FDCAN1_RX + PB9 ------> FDCAN1_TX + */ + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN1; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* FDCAN1 interrupt Init */ + HAL_NVIC_SetPriority(FDCAN1_IT0_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(FDCAN1_IT0_IRQn); + /* USER CODE BEGIN FDCAN1_MspInit 1 */ + + /* USER CODE END FDCAN1_MspInit 1 */ + } + else if(fdcanHandle->Instance==FDCAN2) + { + /* USER CODE BEGIN FDCAN2_MspInit 0 */ + + /* USER CODE END FDCAN2_MspInit 0 */ + + LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_PCLK1); + + /* FDCAN2 clock enable */ + HAL_RCC_FDCAN_CLK_ENABLED++; + if(HAL_RCC_FDCAN_CLK_ENABLED==1){ + __HAL_RCC_FDCAN_CLK_ENABLE(); + } + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**FDCAN2 GPIO Configuration + PB12 ------> FDCAN2_RX + PB13 ------> FDCAN2_TX + */ + GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_13; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN2; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* FDCAN2 interrupt Init */ + HAL_NVIC_SetPriority(FDCAN2_IT0_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(FDCAN2_IT0_IRQn); + /* USER CODE BEGIN FDCAN2_MspInit 1 */ + + /* USER CODE END FDCAN2_MspInit 1 */ + } + else if(fdcanHandle->Instance==FDCAN3) + { + /* USER CODE BEGIN FDCAN3_MspInit 0 */ + + /* USER CODE END FDCAN3_MspInit 0 */ + + LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_PCLK1); + + /* FDCAN3 clock enable */ + HAL_RCC_FDCAN_CLK_ENABLED++; + if(HAL_RCC_FDCAN_CLK_ENABLED==1){ + __HAL_RCC_FDCAN_CLK_ENABLE(); + } + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**FDCAN3 GPIO Configuration + PA8 ------> FDCAN3_RX + PA15 ------> FDCAN3_TX + */ + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF11_FDCAN3; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* FDCAN3 interrupt Init */ + HAL_NVIC_SetPriority(FDCAN3_IT0_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(FDCAN3_IT0_IRQn); + /* USER CODE BEGIN FDCAN3_MspInit 1 */ + + /* USER CODE END FDCAN3_MspInit 1 */ + } } -void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *fdcanHandle) +void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef* fdcanHandle) { - if (fdcanHandle->Instance == FDCAN1) { - /* USER CODE BEGIN FDCAN1_MspDeInit 0 */ - - /* USER CODE END FDCAN1_MspDeInit 0 */ - /* Peripheral clock disable */ - HAL_RCC_FDCAN_CLK_ENABLED--; - if (HAL_RCC_FDCAN_CLK_ENABLED == 0) { - __HAL_RCC_FDCAN_CLK_DISABLE(); - } - - /**FDCAN1 GPIO Configuration - PB8-BOOT0 ------> FDCAN1_RX - PB9 ------> FDCAN1_TX - */ - HAL_GPIO_DeInit(GPIOB, GPIO_PIN_8 | GPIO_PIN_9); - - /* FDCAN1 interrupt Deinit */ - HAL_NVIC_DisableIRQ(FDCAN1_IT0_IRQn); - /* USER CODE BEGIN FDCAN1_MspDeInit 1 */ - - /* USER CODE END FDCAN1_MspDeInit 1 */ - } else if (fdcanHandle->Instance == FDCAN2) { - /* USER CODE BEGIN FDCAN2_MspDeInit 0 */ - - /* USER CODE END FDCAN2_MspDeInit 0 */ - /* Peripheral clock disable */ - HAL_RCC_FDCAN_CLK_ENABLED--; - if (HAL_RCC_FDCAN_CLK_ENABLED == 0) { - __HAL_RCC_FDCAN_CLK_DISABLE(); - } - - /**FDCAN2 GPIO Configuration - PB12 ------> FDCAN2_RX - PB13 ------> FDCAN2_TX - */ - HAL_GPIO_DeInit(GPIOB, GPIO_PIN_12 | GPIO_PIN_13); - - /* FDCAN2 interrupt Deinit */ - HAL_NVIC_DisableIRQ(FDCAN2_IT0_IRQn); - /* USER CODE BEGIN FDCAN2_MspDeInit 1 */ - - /* USER CODE END FDCAN2_MspDeInit 1 */ - } else if (fdcanHandle->Instance == FDCAN3) { - /* USER CODE BEGIN FDCAN3_MspDeInit 0 */ - - /* USER CODE END FDCAN3_MspDeInit 0 */ - /* Peripheral clock disable */ - HAL_RCC_FDCAN_CLK_ENABLED--; - if (HAL_RCC_FDCAN_CLK_ENABLED == 0) { - __HAL_RCC_FDCAN_CLK_DISABLE(); - } - - /**FDCAN3 GPIO Configuration - PA8 ------> FDCAN3_RX - PA15 ------> FDCAN3_TX - */ - HAL_GPIO_DeInit(GPIOA, GPIO_PIN_8 | GPIO_PIN_15); - - /* FDCAN3 interrupt Deinit */ - HAL_NVIC_DisableIRQ(FDCAN3_IT0_IRQn); - /* USER CODE BEGIN FDCAN3_MspDeInit 1 */ - - /* USER CODE END FDCAN3_MspDeInit 1 */ - } + if(fdcanHandle->Instance==FDCAN1) + { + /* USER CODE BEGIN FDCAN1_MspDeInit 0 */ + + /* USER CODE END FDCAN1_MspDeInit 0 */ + /* Peripheral clock disable */ + HAL_RCC_FDCAN_CLK_ENABLED--; + if(HAL_RCC_FDCAN_CLK_ENABLED==0){ + __HAL_RCC_FDCAN_CLK_DISABLE(); + } + + /**FDCAN1 GPIO Configuration + PB8-BOOT0 ------> FDCAN1_RX + PB9 ------> FDCAN1_TX + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_8|GPIO_PIN_9); + + /* FDCAN1 interrupt Deinit */ + HAL_NVIC_DisableIRQ(FDCAN1_IT0_IRQn); + /* USER CODE BEGIN FDCAN1_MspDeInit 1 */ + + /* USER CODE END FDCAN1_MspDeInit 1 */ + } + else if(fdcanHandle->Instance==FDCAN2) + { + /* USER CODE BEGIN FDCAN2_MspDeInit 0 */ + + /* USER CODE END FDCAN2_MspDeInit 0 */ + /* Peripheral clock disable */ + HAL_RCC_FDCAN_CLK_ENABLED--; + if(HAL_RCC_FDCAN_CLK_ENABLED==0){ + __HAL_RCC_FDCAN_CLK_DISABLE(); + } + + /**FDCAN2 GPIO Configuration + PB12 ------> FDCAN2_RX + PB13 ------> FDCAN2_TX + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_12|GPIO_PIN_13); + + /* FDCAN2 interrupt Deinit */ + HAL_NVIC_DisableIRQ(FDCAN2_IT0_IRQn); + /* USER CODE BEGIN FDCAN2_MspDeInit 1 */ + + /* USER CODE END FDCAN2_MspDeInit 1 */ + } + else if(fdcanHandle->Instance==FDCAN3) + { + /* USER CODE BEGIN FDCAN3_MspDeInit 0 */ + + /* USER CODE END FDCAN3_MspDeInit 0 */ + /* Peripheral clock disable */ + HAL_RCC_FDCAN_CLK_ENABLED--; + if(HAL_RCC_FDCAN_CLK_ENABLED==0){ + __HAL_RCC_FDCAN_CLK_DISABLE(); + } + + /**FDCAN3 GPIO Configuration + PA8 ------> FDCAN3_RX + PA15 ------> FDCAN3_TX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_8|GPIO_PIN_15); + + /* FDCAN3 interrupt Deinit */ + HAL_NVIC_DisableIRQ(FDCAN3_IT0_IRQn); + /* USER CODE BEGIN FDCAN3_MspDeInit 1 */ + + /* USER CODE END FDCAN3_MspDeInit 1 */ + } } /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ + diff --git a/Testbench/CUBEMXTESTING/Core/Src/gpio.c b/Testbench/CUBEMXTESTING/Core/Src/gpio.c index 4d07c7993..96b5c07ab 100644 --- a/Testbench/CUBEMXTESTING/Core/Src/gpio.c +++ b/Testbench/CUBEMXTESTING/Core/Src/gpio.c @@ -33,277 +33,278 @@ /* USER CODE END 1 */ /** Configure pins as - * Analog - * Input - * Output - * EVENT_OUT - * EXTI - * Free pins are configured automatically as Analog (this feature is enabled through - * the Code Generation settings) - */ + * Analog + * Input + * Output + * EVENT_OUT + * EXTI + * Free pins are configured automatically as Analog (this feature is enabled through + * the Code Generation settings) +*/ void MX_GPIO_Init(void) { - LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; - - /* GPIO Ports Clock Enable */ - LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOC); - LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOF); - LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOG); - LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA); - LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB); - LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOD); - - /**/ - LL_GPIO_ResetOutputPin(USER_LED_GPIO_Port, USER_LED_Pin); - - /**/ - GPIO_InitStruct.Pin = USER_BUTTON_Pin; - GPIO_InitStruct.Mode = LL_GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(USER_BUTTON_GPIO_Port, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_14; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_15; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_0; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOF, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_1; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOF, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_10; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOG, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_0; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_1; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_2; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_3; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_0; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_1; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_4; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = USER_LED_Pin; - GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT; - GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(USER_LED_GPIO_Port, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_6; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_7; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_4; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_5; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_0; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_1; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_2; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_10; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_11; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_14; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_15; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_6; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_7; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_8; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_9; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_9; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_10; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_11; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_12; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_10; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_11; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_12; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_2; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOD, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_4; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_5; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_6; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_7; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* GPIO Ports Clock Enable */ + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOC); + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOF); + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOG); + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA); + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB); + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOD); + + /**/ + LL_GPIO_ResetOutputPin(USER_LED_GPIO_Port, USER_LED_Pin); + + /**/ + GPIO_InitStruct.Pin = USER_BUTTON_Pin; + GPIO_InitStruct.Mode = LL_GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(USER_BUTTON_GPIO_Port, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_14; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_15; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_0; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_1; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_10; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_0; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_1; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_2; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_3; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_0; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_1; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_4; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = USER_LED_Pin; + GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(USER_LED_GPIO_Port, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_6; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_7; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_4; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_5; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_0; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_1; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_2; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_10; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_11; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_14; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_15; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_6; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_7; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_8; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_9; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_9; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_10; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_11; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_12; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_10; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_11; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_12; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_2; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_4; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_5; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_6; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_7; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + } /* USER CODE BEGIN 2 */ diff --git a/Testbench/CUBEMXTESTING/Core/Src/main.c b/Testbench/CUBEMXTESTING/Core/Src/main.c index 7344dd05d..d201e4a35 100644 --- a/Testbench/CUBEMXTESTING/Core/Src/main.c +++ b/Testbench/CUBEMXTESTING/Core/Src/main.c @@ -18,11 +18,10 @@ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "main.h" - #include "fdcan.h" -#include "gpio.h" -#include "tim.h" #include "usart.h" +#include "tim.h" +#include "gpio.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ @@ -73,40 +72,40 @@ void SystemClock_Config(void); /* USER CODE END 0 */ /** - * @brief The application entry point. - * @retval int - */ + * @brief The application entry point. + * @retval int + */ int main(void) { - /* USER CODE BEGIN 1 */ + /* USER CODE BEGIN 1 */ - /* USER CODE END 1 */ + /* USER CODE END 1 */ - /* MCU Configuration--------------------------------------------------------*/ + /* MCU Configuration--------------------------------------------------------*/ - /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ - HAL_Init(); + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); - /* USER CODE BEGIN Init */ + /* USER CODE BEGIN Init */ - /* USER CODE END Init */ + /* USER CODE END Init */ - /* Configure the system clock */ - SystemClock_Config(); + /* Configure the system clock */ + SystemClock_Config(); - /* USER CODE BEGIN SysInit */ + /* USER CODE BEGIN SysInit */ Logomatic_SetLogLevel(LogLevel_Debug); - /* USER CODE END SysInit */ - - /* Initialize all configured peripherals */ - MX_GPIO_Init(); - MX_FDCAN1_Init(); - MX_FDCAN2_Init(); - MX_TIM5_Init(); - MX_FDCAN3_Init(); - MX_LPUART1_UART_Init(); - /* USER CODE BEGIN 2 */ + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_FDCAN1_Init(); + MX_FDCAN2_Init(); + MX_TIM5_Init(); + MX_FDCAN3_Init(); + MX_LPUART1_UART_Init(); + /* USER CODE BEGIN 2 */ CubeCAN_Config primaryCanConfig = {.rx_callback = CANdler_Callback, .context.busid_user_context = GRCAN_BUS_PRIMARY, .sending_node_id = GRCAN_Debugger}; CubeCAN_Config dataCanConfig = {.rx_callback = CANdler_Callback, .context.busid_user_context = GRCAN_BUS_DATA, .sending_node_id = GRCAN_Debugger}; CubeCAN_Config chargerCanConfig = {.rx_callback = CANdler_Callback, .context.busid_user_context = GRCAN_BUS_CHARGER, .sending_node_id = GRCAN_Debugger}; @@ -133,59 +132,67 @@ int main(void) CubeVCP_Setup(&hlpuart1); CubeVCP_EnableRx(CANdler_VCP_Callback); CubeVCP_SendString("Hello World!\n", sizeof("Hello World!\n") - 1); - /* USER CODE END 2 */ + /* USER CODE END 2 */ - /* Infinite loop */ - /* USER CODE BEGIN WHILE */ + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ while (1) { - /* USER CODE END WHILE */ + /* USER CODE END WHILE */ - /* USER CODE BEGIN 3 */ + /* USER CODE BEGIN 3 */ MainLoop(); HAL_Delay(100); } - /* USER CODE END 3 */ + /* USER CODE END 3 */ } /** - * @brief System Clock Configuration - * @retval None - */ + * @brief System Clock Configuration + * @retval None + */ void SystemClock_Config(void) { - LL_FLASH_SetLatency(LL_FLASH_LATENCY_4); - while (LL_FLASH_GetLatency() != LL_FLASH_LATENCY_4) {} - LL_PWR_EnableRange1BoostMode(); - LL_RCC_HSI_Enable(); - /* Wait till HSI is ready */ - while (LL_RCC_HSI_IsReady() != 1) {} - - LL_RCC_HSI_SetCalibTrimming(64); - LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, LL_RCC_PLLM_DIV_1, 20, LL_RCC_PLLR_DIV_2); - LL_RCC_PLL_EnableDomain_SYS(); - LL_RCC_PLL_Enable(); - /* Wait till PLL is ready */ - while (LL_RCC_PLL_IsReady() != 1) {} - - LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); - LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_2); - /* Wait till System clock is ready */ - while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) {} - - /* Insure 1us transition state at intermediate medium speed clock*/ - for (__IO uint32_t i = (170 >> 1); i != 0; i--) - ; - - /* Set AHB prescaler*/ - LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1); - LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1); - LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1); - LL_SetSystemCoreClock(160000000); - - /* Update the time base */ - if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) { - Error_Handler(); - } + LL_FLASH_SetLatency(LL_FLASH_LATENCY_4); + while(LL_FLASH_GetLatency() != LL_FLASH_LATENCY_4) + { + } + LL_PWR_EnableRange1BoostMode(); + LL_RCC_HSI_Enable(); + /* Wait till HSI is ready */ + while(LL_RCC_HSI_IsReady() != 1) + { + } + + LL_RCC_HSI_SetCalibTrimming(64); + LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, LL_RCC_PLLM_DIV_1, 20, LL_RCC_PLLR_DIV_2); + LL_RCC_PLL_EnableDomain_SYS(); + LL_RCC_PLL_Enable(); + /* Wait till PLL is ready */ + while(LL_RCC_PLL_IsReady() != 1) + { + } + + LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); + LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_2); + /* Wait till System clock is ready */ + while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) + { + } + + /* Insure 1us transition state at intermediate medium speed clock*/ + for (__IO uint32_t i = (170 >> 1); i !=0; i--); + + /* Set AHB prescaler*/ + LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1); + LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1); + LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1); + LL_SetSystemCoreClock(160000000); + + /* Update the time base */ + if (HAL_InitTick (TICK_INT_PRIORITY) != HAL_OK) + { + Error_Handler(); + } } /* USER CODE BEGIN 4 */ @@ -204,29 +211,29 @@ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) /* USER CODE END 4 */ /** - * @brief This function is executed in case of error occurrence. - * @retval None - */ + * @brief This function is executed in case of error occurrence. + * @retval None + */ void Error_Handler(void) { - /* USER CODE BEGIN Error_Handler_Debug */ + /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) {} - /* USER CODE END Error_Handler_Debug */ + /* USER CODE END Error_Handler_Debug */ } #ifdef USE_FULL_ASSERT /** - * @brief Reports the name of the source file and the source line number - * where the assert_param error has occurred. - * @param file: pointer to the source file name - * @param line: assert_param error line source number - * @retval None - */ + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ void assert_failed(uint8_t *file, uint32_t line) { - /* USER CODE BEGIN 6 */ + /* USER CODE BEGIN 6 */ LOGOMATIC_CRITICAL("Assert failed! File %s on line %" PRIu32 "\n", file, line); - /* USER CODE END 6 */ + /* USER CODE END 6 */ } #endif /* USE_FULL_ASSERT */ diff --git a/Testbench/CUBEMXTESTING/Core/Src/stm32g4xx_hal_msp.c b/Testbench/CUBEMXTESTING/Core/Src/stm32g4xx_hal_msp.c index 4668755ab..2cc7d8296 100644 --- a/Testbench/CUBEMXTESTING/Core/Src/stm32g4xx_hal_msp.c +++ b/Testbench/CUBEMXTESTING/Core/Src/stm32g4xx_hal_msp.c @@ -57,27 +57,27 @@ /* USER CODE END 0 */ /** - * Initializes the Global MSP. - */ + * Initializes the Global MSP. + */ void HAL_MspInit(void) { - /* USER CODE BEGIN MspInit 0 */ + /* USER CODE BEGIN MspInit 0 */ - /* USER CODE END MspInit 0 */ + /* USER CODE END MspInit 0 */ - __HAL_RCC_SYSCFG_CLK_ENABLE(); - __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_RCC_SYSCFG_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); - /* System interrupt init*/ + /* System interrupt init*/ - /** Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral - */ - HAL_PWREx_DisableUCPDDeadBattery(); + /** Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral + */ + HAL_PWREx_DisableUCPDDeadBattery(); - /* USER CODE BEGIN MspInit 1 */ + /* USER CODE BEGIN MspInit 1 */ - /* USER CODE END MspInit 1 */ + /* USER CODE END MspInit 1 */ } /* USER CODE BEGIN 1 */ diff --git a/Testbench/CUBEMXTESTING/Core/Src/stm32g4xx_it.c b/Testbench/CUBEMXTESTING/Core/Src/stm32g4xx_it.c index 77f85d385..f02085e66 100644 --- a/Testbench/CUBEMXTESTING/Core/Src/stm32g4xx_it.c +++ b/Testbench/CUBEMXTESTING/Core/Src/stm32g4xx_it.c @@ -18,9 +18,8 @@ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ -#include "stm32g4xx_it.h" - #include "main.h" +#include "stm32g4xx_it.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ /* USER CODE END Includes */ @@ -69,125 +68,129 @@ extern TIM_HandleTypeDef htim5; /* Cortex-M4 Processor Interruption and Exception Handlers */ /******************************************************************************/ /** - * @brief This function handles Non maskable interrupt. - */ + * @brief This function handles Non maskable interrupt. + */ void NMI_Handler(void) { - /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ - /* USER CODE END NonMaskableInt_IRQn 0 */ - /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) {} - /* USER CODE END NonMaskableInt_IRQn 1 */ + /* USER CODE END NonMaskableInt_IRQn 1 */ } /** - * @brief This function handles Hard fault interrupt. - */ + * @brief This function handles Hard fault interrupt. + */ void HardFault_Handler(void) { - /* USER CODE BEGIN HardFault_IRQn 0 */ - - /* USER CODE END HardFault_IRQn 0 */ - while (1) { - /* USER CODE BEGIN W1_HardFault_IRQn 0 */ - /* USER CODE END W1_HardFault_IRQn 0 */ - } + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } } /** - * @brief This function handles Memory management fault. - */ + * @brief This function handles Memory management fault. + */ void MemManage_Handler(void) { - /* USER CODE BEGIN MemoryManagement_IRQn 0 */ - - /* USER CODE END MemoryManagement_IRQn 0 */ - while (1) { - /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ - /* USER CODE END W1_MemoryManagement_IRQn 0 */ - } + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } } /** - * @brief This function handles Prefetch fault, memory access fault. - */ + * @brief This function handles Prefetch fault, memory access fault. + */ void BusFault_Handler(void) { - /* USER CODE BEGIN BusFault_IRQn 0 */ - - /* USER CODE END BusFault_IRQn 0 */ - while (1) { - /* USER CODE BEGIN W1_BusFault_IRQn 0 */ - /* USER CODE END W1_BusFault_IRQn 0 */ - } + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } } /** - * @brief This function handles Undefined instruction or illegal state. - */ + * @brief This function handles Undefined instruction or illegal state. + */ void UsageFault_Handler(void) { - /* USER CODE BEGIN UsageFault_IRQn 0 */ - - /* USER CODE END UsageFault_IRQn 0 */ - while (1) { - /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ - /* USER CODE END W1_UsageFault_IRQn 0 */ - } + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } } /** - * @brief This function handles System service call via SWI instruction. - */ + * @brief This function handles System service call via SWI instruction. + */ void SVC_Handler(void) { - /* USER CODE BEGIN SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 0 */ - /* USER CODE END SVCall_IRQn 0 */ - /* USER CODE BEGIN SVCall_IRQn 1 */ + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ - /* USER CODE END SVCall_IRQn 1 */ + /* USER CODE END SVCall_IRQn 1 */ } /** - * @brief This function handles Debug monitor. - */ + * @brief This function handles Debug monitor. + */ void DebugMon_Handler(void) { - /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ - /* USER CODE END DebugMonitor_IRQn 0 */ - /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ - /* USER CODE END DebugMonitor_IRQn 1 */ + /* USER CODE END DebugMonitor_IRQn 1 */ } /** - * @brief This function handles Pendable request for system service. - */ + * @brief This function handles Pendable request for system service. + */ void PendSV_Handler(void) { - /* USER CODE BEGIN PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 0 */ - /* USER CODE END PendSV_IRQn 0 */ - /* USER CODE BEGIN PendSV_IRQn 1 */ + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ - /* USER CODE END PendSV_IRQn 1 */ + /* USER CODE END PendSV_IRQn 1 */ } /** - * @brief This function handles System tick timer. - */ + * @brief This function handles System tick timer. + */ void SysTick_Handler(void) { - /* USER CODE BEGIN SysTick_IRQn 0 */ + /* USER CODE BEGIN SysTick_IRQn 0 */ - /* USER CODE END SysTick_IRQn 0 */ - HAL_IncTick(); - /* USER CODE BEGIN SysTick_IRQn 1 */ + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ - /* USER CODE END SysTick_IRQn 1 */ + /* USER CODE END SysTick_IRQn 1 */ } /******************************************************************************/ @@ -198,73 +201,73 @@ void SysTick_Handler(void) /******************************************************************************/ /** - * @brief This function handles FDCAN1 interrupt 0. - */ + * @brief This function handles FDCAN1 interrupt 0. + */ void FDCAN1_IT0_IRQHandler(void) { - /* USER CODE BEGIN FDCAN1_IT0_IRQn 0 */ + /* USER CODE BEGIN FDCAN1_IT0_IRQn 0 */ - /* USER CODE END FDCAN1_IT0_IRQn 0 */ - HAL_FDCAN_IRQHandler(&hfdcan1); - /* USER CODE BEGIN FDCAN1_IT0_IRQn 1 */ + /* USER CODE END FDCAN1_IT0_IRQn 0 */ + HAL_FDCAN_IRQHandler(&hfdcan1); + /* USER CODE BEGIN FDCAN1_IT0_IRQn 1 */ - /* USER CODE END FDCAN1_IT0_IRQn 1 */ + /* USER CODE END FDCAN1_IT0_IRQn 1 */ } /** - * @brief This function handles TIM5 global interrupt. - */ + * @brief This function handles TIM5 global interrupt. + */ void TIM5_IRQHandler(void) { - /* USER CODE BEGIN TIM5_IRQn 0 */ + /* USER CODE BEGIN TIM5_IRQn 0 */ - /* USER CODE END TIM5_IRQn 0 */ - HAL_TIM_IRQHandler(&htim5); - /* USER CODE BEGIN TIM5_IRQn 1 */ + /* USER CODE END TIM5_IRQn 0 */ + HAL_TIM_IRQHandler(&htim5); + /* USER CODE BEGIN TIM5_IRQn 1 */ - /* USER CODE END TIM5_IRQn 1 */ + /* USER CODE END TIM5_IRQn 1 */ } /** - * @brief This function handles FDCAN2 interrupt 0. - */ + * @brief This function handles FDCAN2 interrupt 0. + */ void FDCAN2_IT0_IRQHandler(void) { - /* USER CODE BEGIN FDCAN2_IT0_IRQn 0 */ + /* USER CODE BEGIN FDCAN2_IT0_IRQn 0 */ - /* USER CODE END FDCAN2_IT0_IRQn 0 */ - HAL_FDCAN_IRQHandler(&hfdcan2); - /* USER CODE BEGIN FDCAN2_IT0_IRQn 1 */ + /* USER CODE END FDCAN2_IT0_IRQn 0 */ + HAL_FDCAN_IRQHandler(&hfdcan2); + /* USER CODE BEGIN FDCAN2_IT0_IRQn 1 */ - /* USER CODE END FDCAN2_IT0_IRQn 1 */ + /* USER CODE END FDCAN2_IT0_IRQn 1 */ } /** - * @brief This function handles FDCAN3 interrupt 0. - */ + * @brief This function handles FDCAN3 interrupt 0. + */ void FDCAN3_IT0_IRQHandler(void) { - /* USER CODE BEGIN FDCAN3_IT0_IRQn 0 */ + /* USER CODE BEGIN FDCAN3_IT0_IRQn 0 */ - /* USER CODE END FDCAN3_IT0_IRQn 0 */ - HAL_FDCAN_IRQHandler(&hfdcan3); - /* USER CODE BEGIN FDCAN3_IT0_IRQn 1 */ + /* USER CODE END FDCAN3_IT0_IRQn 0 */ + HAL_FDCAN_IRQHandler(&hfdcan3); + /* USER CODE BEGIN FDCAN3_IT0_IRQn 1 */ - /* USER CODE END FDCAN3_IT0_IRQn 1 */ + /* USER CODE END FDCAN3_IT0_IRQn 1 */ } /** - * @brief This function handles LPUART1 global interrupt. - */ + * @brief This function handles LPUART1 global interrupt. + */ void LPUART1_IRQHandler(void) { - /* USER CODE BEGIN LPUART1_IRQn 0 */ + /* USER CODE BEGIN LPUART1_IRQn 0 */ - /* USER CODE END LPUART1_IRQn 0 */ - HAL_UART_IRQHandler(&hlpuart1); - /* USER CODE BEGIN LPUART1_IRQn 1 */ + /* USER CODE END LPUART1_IRQn 0 */ + HAL_UART_IRQHandler(&hlpuart1); + /* USER CODE BEGIN LPUART1_IRQn 1 */ - /* USER CODE END LPUART1_IRQn 1 */ + /* USER CODE END LPUART1_IRQn 1 */ } /* USER CODE BEGIN 1 */ diff --git a/Testbench/CUBEMXTESTING/Core/Src/syscalls.c b/Testbench/CUBEMXTESTING/Core/Src/syscalls.c new file mode 100644 index 000000000..e10d76fa2 --- /dev/null +++ b/Testbench/CUBEMXTESTING/Core/Src/syscalls.c @@ -0,0 +1,244 @@ +/** + ****************************************************************************** + * @file syscalls.c + * @author Auto-generated by STM32CubeMX + * @brief Minimal System calls file + * + * For more information about which c-functions + * need which of these lowlevel functions + * please consult the Newlib or Picolibc libc-manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2020-2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include +#include +#include +#include +#include +#include +#include + + +/* Variables */ +extern int __io_putchar(int ch) __attribute__((weak)); +extern int __io_getchar(void) __attribute__((weak)); + + +char *__env[1] = { 0 }; +char **environ = __env; + + +/* Functions */ +void initialise_monitor_handles() +{ +} + +int _getpid(void) +{ + return 1; +} + +int _kill(int pid, int sig) +{ + (void)pid; + (void)sig; + errno = EINVAL; + return -1; +} + +void _exit (int status) +{ + _kill(status, -1); + while (1) {} /* Make sure we hang here */ +} + +__attribute__((weak)) int _read(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + *ptr++ = __io_getchar(); + } + + return len; +} + +__attribute__((weak)) int _write(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + __io_putchar(*ptr++); + } + return len; +} + +int _close(int file) +{ + (void)file; + return -1; +} + + +int _fstat(int file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _isatty(int file) +{ + (void)file; + return 1; +} + +int _lseek(int file, int ptr, int dir) +{ + (void)file; + (void)ptr; + (void)dir; + return 0; +} + +int _open(char *path, int flags, ...) +{ + (void)path; + (void)flags; + /* Pretend like we always fail */ + return -1; +} + +int _wait(int *status) +{ + (void)status; + errno = ECHILD; + return -1; +} + +int _unlink(char *name) +{ + (void)name; + errno = ENOENT; + return -1; +} + +clock_t _times(struct tms *buf) +{ + (void)buf; + return -1; +} + +int _stat(const char *file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _link(char *old, char *new) +{ + (void)old; + (void)new; + errno = EMLINK; + return -1; +} + +int _fork(void) +{ + errno = EAGAIN; + return -1; +} + +int _execve(char *name, char **argv, char **env) +{ + (void)name; + (void)argv; + (void)env; + errno = ENOMEM; + return -1; +} + +// --- Picolibc Specific Section --- +#if defined(__PICOLIBC__) + +/** + * @brief Picolibc helper function to output a character to a FILE stream. + * This redirects the output to the low-level __io_putchar function. + * @param c Character to write. + * @param file FILE stream pointer (ignored). + * @retval int The character written. + */ +static int starm_putc(char c, FILE *file) +{ + (void) file; + __io_putchar(c); + return c; +} + +/** + * @brief Picolibc helper function to input a character from a FILE stream. + * This redirects the input from the low-level __io_getchar function. + * @param file FILE stream pointer (ignored). + * @retval int The character read, cast to an unsigned char then int. + */ +static int starm_getc(FILE *file) +{ + unsigned char c; + (void) file; + c = __io_getchar(); + return c; +} + +// Define and initialize the standard I/O streams for Picolibc. +// FDEV_SETUP_STREAM connects the starm_putc and starm_getc helper functions to a FILE structure. +// _FDEV_SETUP_RW indicates the stream is for reading and writing. +static FILE __stdio = FDEV_SETUP_STREAM(starm_putc, + starm_getc, + NULL, + _FDEV_SETUP_RW); + +// Assign the standard stream pointers (stdin, stdout, stderr) to the initialized stream. +// Picolibc uses these pointers for standard I/O operations (printf, scanf, etc.). +FILE *const stdin = &__stdio; +__strong_reference(stdin, stdout); +__strong_reference(stdin, stderr); + +// Create strong aliases mapping standard C library function names (without underscore) +// to the implemented system call stubs (with underscore). Picolibc uses these +// standard names internally, so this linking is required. +__strong_reference(_read, read); +__strong_reference(_write, write); +__strong_reference(_times, times); +__strong_reference(_execve, execve); +__strong_reference(_fork, fork); +__strong_reference(_link, link); +__strong_reference(_unlink, unlink); +__strong_reference(_stat, stat); +__strong_reference(_wait, wait); +__strong_reference(_open, open); +__strong_reference(_close, close); +__strong_reference(_lseek, lseek); +__strong_reference(_isatty, isatty); +__strong_reference(_fstat, fstat); +__strong_reference(_exit, exit); +__strong_reference(_kill, kill); +__strong_reference(_getpid, getpid); + +#endif //__PICOLIBC__ diff --git a/Testbench/CUBEMXTESTING/Core/Src/sysmem.c b/Testbench/CUBEMXTESTING/Core/Src/sysmem.c new file mode 100644 index 000000000..a875d42c0 --- /dev/null +++ b/Testbench/CUBEMXTESTING/Core/Src/sysmem.c @@ -0,0 +1,87 @@ +/** + ****************************************************************************** + * @file sysmem.c + * @author Generated by STM32CubeMX + * @brief System Memory calls file + * + * For more information about which C functions + * need which of these lowlevel functions + * please consult the Newlib or Picolibc libc manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include +#include + +/** + * Pointer to the current high watermark of the heap usage + */ +static uint8_t *__sbrk_heap_end = NULL; + +/** + * @brief _sbrk() allocates memory to the newlib heap and is used by malloc + * and others from the C library + * + * @verbatim + * ############################################################################ + * # .data # .bss # newlib heap # MSP stack # + * # # # # Reserved by _Min_Stack_Size # + * ############################################################################ + * ^-- RAM start ^-- _end _estack, RAM end --^ + * @endverbatim + * + * This implementation starts allocating at the '_end' linker symbol + * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack + * The implementation considers '_estack' linker symbol to be RAM end + * NOTE: If the MSP stack, at any point during execution, grows larger than the + * reserved size, please increase the '_Min_Stack_Size'. + * + * @param incr Memory size + * @return Pointer to allocated memory + */ +void *_sbrk(ptrdiff_t incr) +{ + extern uint8_t _end; /* Symbol defined in the linker script */ + extern uint8_t _estack; /* Symbol defined in the linker script */ + extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + const uint8_t *max_heap = (uint8_t *)stack_limit; + uint8_t *prev_heap_end; + + /* Initialize heap end at first call */ + if (NULL == __sbrk_heap_end) + { + __sbrk_heap_end = &_end; + } + + /* Protect heap from growing into the reserved MSP stack */ + if (__sbrk_heap_end + incr > max_heap) + { + errno = ENOMEM; + return (void *)-1; + } + + prev_heap_end = __sbrk_heap_end; + __sbrk_heap_end += incr; + + return (void *)prev_heap_end; +} + +#if defined(__PICOLIBC__) + // Picolibc expects syscalls without the leading underscore. + // This creates a strong alias so that + // calls to `sbrk()` are resolved to our `_sbrk()` implementation. + __strong_reference(_sbrk, sbrk); +#endif diff --git a/Testbench/CUBEMXTESTING/Core/Src/system_stm32g4xx.c b/Testbench/CUBEMXTESTING/Core/Src/system_stm32g4xx.c new file mode 100644 index 000000000..2cd914e7b --- /dev/null +++ b/Testbench/CUBEMXTESTING/Core/Src/system_stm32g4xx.c @@ -0,0 +1,287 @@ +/** + ****************************************************************************** + * @file system_stm32g4xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32g4xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32g4xx.s" file, to + * configure the system clock before to branch to main program. + * + * This file configures the system clock as follows: + *============================================================================= + *----------------------------------------------------------------------------- + * System Clock source | HSI + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 16000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 16000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 1 + *----------------------------------------------------------------------------- + * PLL_M | 1 + *----------------------------------------------------------------------------- + * PLL_N | 16 + *----------------------------------------------------------------------------- + * PLL_P | 7 + *----------------------------------------------------------------------------- + * PLL_Q | 2 + *----------------------------------------------------------------------------- + * PLL_R | 2 + *----------------------------------------------------------------------------- + * Require 48MHz for RNG | Disabled + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32g4xx_system + * @{ + */ + +/** @addtogroup STM32G4xx_System_Private_Includes + * @{ + */ + +#include "stm32g4xx.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE 24000000U /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32G4xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32G4xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in Flash or Sram, else the vector table is kept at the automatic + remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +/*!< Uncomment the following line if you need to relocate your vector Table + in Sram else user remap will be done in Flash. */ +/* #define VECT_TAB_SRAM */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_SRAM */ + +#if !defined(VECT_TAB_OFFSET) +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_OFFSET */ + +#endif /* USER_VECT_TAB_ADDRESS */ +/******************************************************************************/ +/** + * @} + */ + +/** @addtogroup STM32G4xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32G4xx_System_Private_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = HSI_VALUE; + + const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; + const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; + +/** + * @} + */ + +/** @addtogroup STM32G4xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32G4xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ + +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ + #endif + + /* Configure the Vector Table location add offset address ------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (**) HSI_VALUE is a constant defined in stm32g4xx_hal.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in stm32g4xx_hal.h file (default value + * 24 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp, pllvco, pllr, pllsource, pllm; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case 0x04: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + + case 0x08: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + + case 0x0C: /* PLL used as system clock source */ + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); + pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1U ; + if (pllsource == 0x02UL) /* HSI used as PLL clock source */ + { + pllvco = (HSI_VALUE / pllm); + } + else /* HSE used as PLL clock source */ + { + pllvco = (HSE_VALUE / pllm); + } + pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8); + pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U; + SystemCoreClock = pllvco/pllr; + break; + + default: + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + diff --git a/Testbench/CUBEMXTESTING/Core/Src/tim.c b/Testbench/CUBEMXTESTING/Core/Src/tim.c index 1f6110e86..cc6e6a92e 100644 --- a/Testbench/CUBEMXTESTING/Core/Src/tim.c +++ b/Testbench/CUBEMXTESTING/Core/Src/tim.c @@ -30,76 +30,83 @@ TIM_HandleTypeDef htim5; void MX_TIM5_Init(void) { - /* USER CODE BEGIN TIM5_Init 0 */ - - /* USER CODE END TIM5_Init 0 */ - - TIM_ClockConfigTypeDef sClockSourceConfig = {0}; - TIM_MasterConfigTypeDef sMasterConfig = {0}; - - /* USER CODE BEGIN TIM5_Init 1 */ - - /* USER CODE END TIM5_Init 1 */ - htim5.Instance = TIM5; - htim5.Init.Prescaler = 159; - htim5.Init.CounterMode = TIM_COUNTERMODE_UP; - htim5.Init.Period = 499; - htim5.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; - htim5.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; - if (HAL_TIM_Base_Init(&htim5) != HAL_OK) { - Error_Handler(); - } - sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; - if (HAL_TIM_ConfigClockSource(&htim5, &sClockSourceConfig) != HAL_OK) { - Error_Handler(); - } - sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; - sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; - if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig) != HAL_OK) { - Error_Handler(); - } - /* USER CODE BEGIN TIM5_Init 2 */ + /* USER CODE BEGIN TIM5_Init 0 */ + + /* USER CODE END TIM5_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; + + /* USER CODE BEGIN TIM5_Init 1 */ + + /* USER CODE END TIM5_Init 1 */ + htim5.Instance = TIM5; + htim5.Init.Prescaler = 159; + htim5.Init.CounterMode = TIM_COUNTERMODE_UP; + htim5.Init.Period = 499; + htim5.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim5.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim5) != HAL_OK) + { + Error_Handler(); + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(&htim5, &sClockSourceConfig) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM5_Init 2 */ HAL_TIM_Base_Start_IT(&htim5); - /* USER CODE END TIM5_Init 2 */ + /* USER CODE END TIM5_Init 2 */ + } -void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *tim_baseHandle) +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) { - if (tim_baseHandle->Instance == TIM5) { - /* USER CODE BEGIN TIM5_MspInit 0 */ + if(tim_baseHandle->Instance==TIM5) + { + /* USER CODE BEGIN TIM5_MspInit 0 */ - /* USER CODE END TIM5_MspInit 0 */ - /* TIM5 clock enable */ - __HAL_RCC_TIM5_CLK_ENABLE(); + /* USER CODE END TIM5_MspInit 0 */ + /* TIM5 clock enable */ + __HAL_RCC_TIM5_CLK_ENABLE(); - /* TIM5 interrupt Init */ - HAL_NVIC_SetPriority(TIM5_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(TIM5_IRQn); - /* USER CODE BEGIN TIM5_MspInit 1 */ + /* TIM5 interrupt Init */ + HAL_NVIC_SetPriority(TIM5_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(TIM5_IRQn); + /* USER CODE BEGIN TIM5_MspInit 1 */ - /* USER CODE END TIM5_MspInit 1 */ - } + /* USER CODE END TIM5_MspInit 1 */ + } } -void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *tim_baseHandle) +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* tim_baseHandle) { - if (tim_baseHandle->Instance == TIM5) { - /* USER CODE BEGIN TIM5_MspDeInit 0 */ + if(tim_baseHandle->Instance==TIM5) + { + /* USER CODE BEGIN TIM5_MspDeInit 0 */ - /* USER CODE END TIM5_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_TIM5_CLK_DISABLE(); + /* USER CODE END TIM5_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM5_CLK_DISABLE(); - /* TIM5 interrupt Deinit */ - HAL_NVIC_DisableIRQ(TIM5_IRQn); - /* USER CODE BEGIN TIM5_MspDeInit 1 */ + /* TIM5 interrupt Deinit */ + HAL_NVIC_DisableIRQ(TIM5_IRQn); + /* USER CODE BEGIN TIM5_MspDeInit 1 */ - /* USER CODE END TIM5_MspDeInit 1 */ - } + /* USER CODE END TIM5_MspDeInit 1 */ + } } /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ + diff --git a/Testbench/CUBEMXTESTING/Core/Src/usart.c b/Testbench/CUBEMXTESTING/Core/Src/usart.c index a14deb76c..836ce8d48 100644 --- a/Testbench/CUBEMXTESTING/Core/Src/usart.c +++ b/Testbench/CUBEMXTESTING/Core/Src/usart.c @@ -31,98 +31,106 @@ UART_HandleTypeDef hlpuart1; void MX_LPUART1_UART_Init(void) { - /* USER CODE BEGIN LPUART1_Init 0 */ - - /* USER CODE END LPUART1_Init 0 */ - - /* USER CODE BEGIN LPUART1_Init 1 */ - - /* USER CODE END LPUART1_Init 1 */ - hlpuart1.Instance = LPUART1; - hlpuart1.Init.BaudRate = 115200; - hlpuart1.Init.WordLength = UART_WORDLENGTH_8B; - hlpuart1.Init.StopBits = UART_STOPBITS_1; - hlpuart1.Init.Parity = UART_PARITY_NONE; - hlpuart1.Init.Mode = UART_MODE_TX_RX; - hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; - hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; - hlpuart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; - hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; - if (HAL_UART_Init(&hlpuart1) != HAL_OK) { - Error_Handler(); - } - if (HAL_UARTEx_SetTxFifoThreshold(&hlpuart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) { - Error_Handler(); - } - if (HAL_UARTEx_SetRxFifoThreshold(&hlpuart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) { - Error_Handler(); - } - if (HAL_UARTEx_DisableFifoMode(&hlpuart1) != HAL_OK) { - Error_Handler(); - } - /* USER CODE BEGIN LPUART1_Init 2 */ - - /* USER CODE END LPUART1_Init 2 */ + /* USER CODE BEGIN LPUART1_Init 0 */ + + /* USER CODE END LPUART1_Init 0 */ + + /* USER CODE BEGIN LPUART1_Init 1 */ + + /* USER CODE END LPUART1_Init 1 */ + hlpuart1.Instance = LPUART1; + hlpuart1.Init.BaudRate = 115200; + hlpuart1.Init.WordLength = UART_WORDLENGTH_8B; + hlpuart1.Init.StopBits = UART_STOPBITS_1; + hlpuart1.Init.Parity = UART_PARITY_NONE; + hlpuart1.Init.Mode = UART_MODE_TX_RX; + hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + hlpuart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; + hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&hlpuart1) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetTxFifoThreshold(&hlpuart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetRxFifoThreshold(&hlpuart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_DisableFifoMode(&hlpuart1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN LPUART1_Init 2 */ + + /* USER CODE END LPUART1_Init 2 */ + } -void HAL_UART_MspInit(UART_HandleTypeDef *uartHandle) +void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { - GPIO_InitTypeDef GPIO_InitStruct = {0}; - if (uartHandle->Instance == LPUART1) { - /* USER CODE BEGIN LPUART1_MspInit 0 */ - - /* USER CODE END LPUART1_MspInit 0 */ - LL_RCC_SetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE_PCLK1); - - /* LPUART1 clock enable */ - __HAL_RCC_LPUART1_CLK_ENABLE(); - - __HAL_RCC_GPIOA_CLK_ENABLE(); - /**LPUART1 GPIO Configuration - PA2 ------> LPUART1_TX - PA3 ------> LPUART1_RX - */ - GPIO_InitStruct.Pin = GPIO_PIN_2 | GPIO_PIN_3; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF12_LPUART1; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /* LPUART1 interrupt Init */ - HAL_NVIC_SetPriority(LPUART1_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(LPUART1_IRQn); - /* USER CODE BEGIN LPUART1_MspInit 1 */ - - /* USER CODE END LPUART1_MspInit 1 */ - } + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(uartHandle->Instance==LPUART1) + { + /* USER CODE BEGIN LPUART1_MspInit 0 */ + + /* USER CODE END LPUART1_MspInit 0 */ + LL_RCC_SetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE_PCLK1); + + /* LPUART1 clock enable */ + __HAL_RCC_LPUART1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**LPUART1 GPIO Configuration + PA2 ------> LPUART1_TX + PA3 ------> LPUART1_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF12_LPUART1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* LPUART1 interrupt Init */ + HAL_NVIC_SetPriority(LPUART1_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(LPUART1_IRQn); + /* USER CODE BEGIN LPUART1_MspInit 1 */ + + /* USER CODE END LPUART1_MspInit 1 */ + } } -void HAL_UART_MspDeInit(UART_HandleTypeDef *uartHandle) +void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle) { - if (uartHandle->Instance == LPUART1) { - /* USER CODE BEGIN LPUART1_MspDeInit 0 */ + if(uartHandle->Instance==LPUART1) + { + /* USER CODE BEGIN LPUART1_MspDeInit 0 */ - /* USER CODE END LPUART1_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_LPUART1_CLK_DISABLE(); + /* USER CODE END LPUART1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_LPUART1_CLK_DISABLE(); - /**LPUART1 GPIO Configuration - PA2 ------> LPUART1_TX - PA3 ------> LPUART1_RX - */ - HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2 | GPIO_PIN_3); + /**LPUART1 GPIO Configuration + PA2 ------> LPUART1_TX + PA3 ------> LPUART1_RX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); - /* LPUART1 interrupt Deinit */ - HAL_NVIC_DisableIRQ(LPUART1_IRQn); - /* USER CODE BEGIN LPUART1_MspDeInit 1 */ + /* LPUART1 interrupt Deinit */ + HAL_NVIC_DisableIRQ(LPUART1_IRQn); + /* USER CODE BEGIN LPUART1_MspDeInit 1 */ - /* USER CODE END LPUART1_MspDeInit 1 */ - } + /* USER CODE END LPUART1_MspDeInit 1 */ + } } /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ + diff --git a/Testbench/CUBEMXTESTING/STM32G474xx_FLASH.ld b/Testbench/CUBEMXTESTING/STM32G474xx_FLASH.ld new file mode 100644 index 000000000..2c518a14a --- /dev/null +++ b/Testbench/CUBEMXTESTING/STM32G474xx_FLASH.ld @@ -0,0 +1,250 @@ +/* +****************************************************************************** +** + +** File : LinkerScript.ld +** +** Author : STM32CubeMX +** +** Abstract : Linker script for STM32G474RETx series +** 512Kbytes FLASH and 128Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed “as is,” without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +**

© COPYRIGHT(c) 2025 STMicroelectronics

+** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** 1. Redistributions of source code must retain the above copyright notice, +** this list of conditions and the following disclaimer. +** 2. Redistributions in binary form must reproduce the above copyright notice, +** this list of conditions and the following disclaimer in the documentation +** and/or other materials provided with the distribution. +** 3. Neither the name of STMicroelectronics nor the names of its contributors +** may be used to endorse or promote products derived from this software +** without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K +FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 512K +} + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of RAM */ +_sstack = _estack - _Min_Stack_Size; +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + } >RAM AT> FLASH + + /* Initialized TLS data section */ + .tdata : ALIGN(4) + { + *(.tdata .tdata.* .gnu.linkonce.td.*) + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + PROVIDE(__data_end = .); + PROVIDE(__tdata_end = .); + } >RAM AT> FLASH + + PROVIDE( __tdata_start = ADDR(.tdata) ); + PROVIDE( __tdata_size = __tdata_end - __tdata_start ); + + PROVIDE( __data_start = ADDR(.data) ); + PROVIDE( __data_size = __data_end - __data_start ); + + PROVIDE( __tdata_source = LOADADDR(.tdata) ); + PROVIDE( __tdata_source_end = LOADADDR(.tdata) + SIZEOF(.tdata) ); + PROVIDE( __tdata_source_size = __tdata_source_end - __tdata_source ); + + PROVIDE( __data_source = LOADADDR(.data) ); + PROVIDE( __data_source_end = __tdata_source_end ); + PROVIDE( __data_source_size = __data_source_end - __data_source ); + /* Uninitialized data section */ + .tbss (NOLOAD) : ALIGN(4) + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.tbss .tbss.*) + . = ALIGN(4); + PROVIDE( __tbss_end = . ); + } >RAM + + PROVIDE( __tbss_start = ADDR(.tbss) ); + PROVIDE( __tbss_size = __tbss_end - __tbss_start ); + PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); + + PROVIDE( __tls_base = __tdata_start ); + PROVIDE( __tls_end = __tbss_end ); + PROVIDE( __tls_size = __tls_end - __tls_base ); + PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); + PROVIDE( __tls_size_align = (__tls_size + __tls_align - 1) & ~(__tls_align - 1) ); + PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); + PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); + + .bss (NOLOAD) : ALIGN(4) + { + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + PROVIDE( __bss_end = .); + } >RAM + PROVIDE( __non_tls_bss_start = ADDR(.bss) ); + + PROVIDE( __bss_start = __tbss_start ); + PROVIDE( __bss_size = __bss_end - __bss_start ); + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack (NOLOAD) : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a:* ( * ) + libm.a:* ( * ) + libgcc.a:* ( * ) + } + +} diff --git a/Testbench/CUBEMXTESTING/startup_stm32g474xx.s b/Testbench/CUBEMXTESTING/startup_stm32g474xx.s new file mode 100644 index 000000000..e7a2c61fc --- /dev/null +++ b/Testbench/CUBEMXTESTING/startup_stm32g474xx.s @@ -0,0 +1,592 @@ +/** + ****************************************************************************** + * @file startup_stm32g474xx.s + * @author MCD Application Team + * @brief STM32G474xx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex-M4. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_PVM_IRQHandler + .word RTC_TAMP_LSECSS_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_IRQHandler + .word USB_LP_IRQHandler + .word FDCAN1_IT0_IRQHandler + .word FDCAN1_IT1_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word USBWakeUp_IRQHandler + .word TIM8_BRK_IRQHandler + .word TIM8_UP_IRQHandler + .word TIM8_TRG_COM_IRQHandler + .word TIM8_CC_IRQHandler + .word ADC3_IRQHandler + .word FMC_IRQHandler + .word LPTIM1_IRQHandler + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_DAC_IRQHandler + .word TIM7_DAC_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word ADC4_IRQHandler + .word ADC5_IRQHandler + .word UCPD1_IRQHandler + .word COMP1_2_3_IRQHandler + .word COMP4_5_6_IRQHandler + .word COMP7_IRQHandler + .word HRTIM1_Master_IRQHandler + .word HRTIM1_TIMA_IRQHandler + .word HRTIM1_TIMB_IRQHandler + .word HRTIM1_TIMC_IRQHandler + .word HRTIM1_TIMD_IRQHandler + .word HRTIM1_TIME_IRQHandler + .word HRTIM1_FLT_IRQHandler + .word HRTIM1_TIMF_IRQHandler + .word CRS_IRQHandler + .word SAI1_IRQHandler + .word TIM20_BRK_IRQHandler + .word TIM20_UP_IRQHandler + .word TIM20_TRG_COM_IRQHandler + .word TIM20_CC_IRQHandler + .word FPU_IRQHandler + .word I2C4_EV_IRQHandler + .word I2C4_ER_IRQHandler + .word SPI4_IRQHandler + .word 0 + .word FDCAN2_IT0_IRQHandler + .word FDCAN2_IT1_IRQHandler + .word FDCAN3_IT0_IRQHandler + .word FDCAN3_IT1_IRQHandler + .word RNG_IRQHandler + .word LPUART1_IRQHandler + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word DMAMUX_OVR_IRQHandler + .word QUADSPI_IRQHandler + .word DMA1_Channel8_IRQHandler + .word DMA2_Channel6_IRQHandler + .word DMA2_Channel7_IRQHandler + .word DMA2_Channel8_IRQHandler + .word CORDIC_IRQHandler + .word FMAC_IRQHandler + + .size g_pfnVectors, .-g_pfnVectors + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak RTC_TAMP_LSECSS_IRQHandler + .thumb_set RTC_TAMP_LSECSS_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_IRQHandler + .thumb_set USB_HP_IRQHandler,Default_Handler + + .weak USB_LP_IRQHandler + .thumb_set USB_LP_IRQHandler,Default_Handler + + .weak FDCAN1_IT0_IRQHandler + .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler + + .weak FDCAN1_IT1_IRQHandler + .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_DAC_IRQHandler + .thumb_set TIM7_DAC_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak ADC4_IRQHandler + .thumb_set ADC4_IRQHandler,Default_Handler + + .weak ADC5_IRQHandler + .thumb_set ADC5_IRQHandler,Default_Handler + + .weak UCPD1_IRQHandler + .thumb_set UCPD1_IRQHandler,Default_Handler + + .weak COMP1_2_3_IRQHandler + .thumb_set COMP1_2_3_IRQHandler,Default_Handler + + .weak COMP4_5_6_IRQHandler + .thumb_set COMP4_5_6_IRQHandler,Default_Handler + + .weak COMP7_IRQHandler + .thumb_set COMP7_IRQHandler,Default_Handler + + .weak HRTIM1_Master_IRQHandler + .thumb_set HRTIM1_Master_IRQHandler,Default_Handler + + .weak HRTIM1_TIMA_IRQHandler + .thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler + + .weak HRTIM1_TIMB_IRQHandler + .thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler + + .weak HRTIM1_TIMC_IRQHandler + .thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler + + .weak HRTIM1_TIMD_IRQHandler + .thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler + + .weak HRTIM1_TIME_IRQHandler + .thumb_set HRTIM1_TIME_IRQHandler,Default_Handler + + .weak HRTIM1_FLT_IRQHandler + .thumb_set HRTIM1_FLT_IRQHandler,Default_Handler + + .weak HRTIM1_TIMF_IRQHandler + .thumb_set HRTIM1_TIMF_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak TIM20_BRK_IRQHandler + .thumb_set TIM20_BRK_IRQHandler,Default_Handler + + .weak TIM20_UP_IRQHandler + .thumb_set TIM20_UP_IRQHandler,Default_Handler + + .weak TIM20_TRG_COM_IRQHandler + .thumb_set TIM20_TRG_COM_IRQHandler,Default_Handler + + .weak TIM20_CC_IRQHandler + .thumb_set TIM20_CC_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak I2C4_EV_IRQHandler + .thumb_set I2C4_EV_IRQHandler,Default_Handler + + .weak I2C4_ER_IRQHandler + .thumb_set I2C4_ER_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak FDCAN2_IT0_IRQHandler + .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler + + .weak FDCAN2_IT1_IRQHandler + .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler + + .weak FDCAN3_IT0_IRQHandler + .thumb_set FDCAN3_IT0_IRQHandler,Default_Handler + + .weak FDCAN3_IT1_IRQHandler + .thumb_set FDCAN3_IT1_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak DMAMUX_OVR_IRQHandler + .thumb_set DMAMUX_OVR_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak DMA1_Channel8_IRQHandler + .thumb_set DMA1_Channel8_IRQHandler,Default_Handler + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak DMA2_Channel7_IRQHandler + .thumb_set DMA2_Channel7_IRQHandler,Default_Handler + + .weak DMA2_Channel8_IRQHandler + .thumb_set DMA2_Channel8_IRQHandler,Default_Handler + + .weak CORDIC_IRQHandler + .thumb_set CORDIC_IRQHandler,Default_Handler + + .weak FMAC_IRQHandler + .thumb_set FMAC_IRQHandler,Default_Handler + From aacd8e2e6c6b6ec505c3e8716b4104b5b6c66ed4 Mon Sep 17 00:00:00 2001 From: github-actions <41898282+github-actions[bot]@users.noreply.github.com> Date: Sun, 23 Aug 2026 09:53:43 +0000 Subject: [PATCH 03/17] Automatic CMake Format: Standardized formatting automatically --- CMakeLists.txt | 148 +++---- Lib/Vendor/TargetFlags/stm32g4xx.cmake | 24 +- Lib/Vendor/TargetFlags/stm32h5xx.cmake | 12 +- Lib/Vendor/TargetFlags/stm32l4xx.cmake | 12 +- Lib/Vendor/TargetFlags/stm32u5xx.cmake | 12 +- Lib/cmake/cube.cmake | 592 ++++++++++++++----------- 6 files changed, 448 insertions(+), 352 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 6d4fb866a..b384bc343 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1,8 +1,8 @@ cmake_minimum_required(VERSION 3.25) project(Firmware) enable_language( - C - ASM + C + ASM ) # Setup compiler settings @@ -13,99 +13,99 @@ set(CMAKE_EXPORT_COMPILE_COMMANDS TRUE) # Messages if(NOT DEFINED CMAKE_PRESET_NAME) - message( - FATAL_ERROR - "This project requires configuration using a CMake preset. Please use 'cmake --preset ' or select a preset in your IDE." - ) + message( + FATAL_ERROR + "This project requires configuration using a CMake preset. Please use 'cmake --preset ' or select a preset in your IDE." + ) endif() message( - STATUS - "Build type: " - ${CMAKE_BUILD_TYPE} + STATUS + "Build type: " + ${CMAKE_BUILD_TYPE} ) message(STATUS "Target type: ${TARGET_TYPE}") message( - STATUS - "Active CMake Preset: " - ${CMAKE_PRESET_NAME} + STATUS + "Active CMake Preset: " + ${CMAKE_PRESET_NAME} ) # Shared Compiler Cache Configuration find_program(SCCACHE_PROGRAM sccache) if( - SCCACHE_PROGRAM - AND - NOT - CMAKE_C_COMPILER_LAUNCHER - AND - NOT - CMAKE_ASM_COMPILER_LAUNCHER + SCCACHE_PROGRAM + AND + NOT + CMAKE_C_COMPILER_LAUNCHER + AND + NOT + CMAKE_ASM_COMPILER_LAUNCHER ) - message(STATUS "Found sccache: ${SCCACHE_PROGRAM}") - set(SCCACHE_DIR_PATH "${CMAKE_SOURCE_DIR}/sccache") - set( - CMAKE_C_COMPILER_LAUNCHER - "${CMAKE_COMMAND}" - -E - env - "SCCACHE_DIR=${SCCACHE_DIR_PATH}" - "${SCCACHE_PROGRAM}" - ) - set( - CMAKE_ASM_COMPILER_LAUNCHER - "${CMAKE_COMMAND}" - -E - env - "SCCACHE_DIR=${SCCACHE_DIR_PATH}" - "${SCCACHE_PROGRAM}" - ) - message(STATUS "sccache directory: ${SCCACHE_DIR_PATH}") + message(STATUS "Found sccache: ${SCCACHE_PROGRAM}") + set(SCCACHE_DIR_PATH "${CMAKE_SOURCE_DIR}/sccache") + set( + CMAKE_C_COMPILER_LAUNCHER + "${CMAKE_COMMAND}" + -E + env + "SCCACHE_DIR=${SCCACHE_DIR_PATH}" + "${SCCACHE_PROGRAM}" + ) + set( + CMAKE_ASM_COMPILER_LAUNCHER + "${CMAKE_COMMAND}" + -E + env + "SCCACHE_DIR=${SCCACHE_DIR_PATH}" + "${SCCACHE_PROGRAM}" + ) + message(STATUS "sccache directory: ${SCCACHE_DIR_PATH}") elseif(CMAKE_C_COMPILER_LAUNCHER OR CMAKE_ASM_COMPILER_LAUNCHER) - message( - STATUS - "Not using sccache: CMAKE_C_COMPILER_LAUNCHER already set to '${CMAKE_C_COMPILER_LAUNCHER}' or CMAKE_ASM_COMPILER_LAUNCHER already set to '${CMAKE_ASM_COMPILER_LAUNCHER}'" - ) + message( + STATUS + "Not using sccache: CMAKE_C_COMPILER_LAUNCHER already set to '${CMAKE_C_COMPILER_LAUNCHER}' or CMAKE_ASM_COMPILER_LAUNCHER already set to '${CMAKE_ASM_COMPILER_LAUNCHER}'" + ) else() - message(STATUS "Not using sccache: sccache not found in PATH") + message(STATUS "Not using sccache: sccache not found in PATH") endif() # Compiler Cache Configuration find_program(CCACHE_PROGRAM ccache) if( - CCACHE_PROGRAM - AND - NOT - CMAKE_C_COMPILER_LAUNCHER - AND - NOT - CMAKE_ASM_COMPILER_LAUNCHER + CCACHE_PROGRAM + AND + NOT + CMAKE_C_COMPILER_LAUNCHER + AND + NOT + CMAKE_ASM_COMPILER_LAUNCHER ) - message(STATUS "Found ccache: ${CCACHE_PROGRAM}") - set(CCACHE_DIR_PATH "${CMAKE_SOURCE_DIR}/ccache") - set( - CMAKE_C_COMPILER_LAUNCHER - "${CMAKE_COMMAND}" - -E - env - "CCACHE_DIR=${CCACHE_DIR_PATH}" - "${CCACHE_PROGRAM}" - ) - set( - CMAKE_ASM_COMPILER_LAUNCHER - "${CMAKE_COMMAND}" - -E - env - "CCACHE_DIR=${CCACHE_DIR_PATH}" - "${CCACHE_PROGRAM}" - ) - message(STATUS "ccache directory: ${CCACHE_DIR_PATH}") + message(STATUS "Found ccache: ${CCACHE_PROGRAM}") + set(CCACHE_DIR_PATH "${CMAKE_SOURCE_DIR}/ccache") + set( + CMAKE_C_COMPILER_LAUNCHER + "${CMAKE_COMMAND}" + -E + env + "CCACHE_DIR=${CCACHE_DIR_PATH}" + "${CCACHE_PROGRAM}" + ) + set( + CMAKE_ASM_COMPILER_LAUNCHER + "${CMAKE_COMMAND}" + -E + env + "CCACHE_DIR=${CCACHE_DIR_PATH}" + "${CCACHE_PROGRAM}" + ) + message(STATUS "ccache directory: ${CCACHE_DIR_PATH}") elseif(CMAKE_C_COMPILER_LAUNCHER OR CMAKE_ASM_COMPILER_LAUNCHER) - message( - STATUS - "Not using ccache: CMAKE_C_COMPILER_LAUNCHER already set to '${CMAKE_C_COMPILER_LAUNCHER}' or CMAKE_ASM_COMPILER_LAUNCHER already set to '${CMAKE_ASM_COMPILER_LAUNCHER}'" - ) + message( + STATUS + "Not using ccache: CMAKE_C_COMPILER_LAUNCHER already set to '${CMAKE_C_COMPILER_LAUNCHER}' or CMAKE_ASM_COMPILER_LAUNCHER already set to '${CMAKE_ASM_COMPILER_LAUNCHER}'" + ) else() - message(STATUS "Not using ccache: ccache not found in PATH") + message(STATUS "Not using ccache: ccache not found in PATH") endif() # Globals diff --git a/Lib/Vendor/TargetFlags/stm32g4xx.cmake b/Lib/Vendor/TargetFlags/stm32g4xx.cmake index 89405f61f..020b59e5d 100644 --- a/Lib/Vendor/TargetFlags/stm32g4xx.cmake +++ b/Lib/Vendor/TargetFlags/stm32g4xx.cmake @@ -1,17 +1,17 @@ target_compile_options( - ${TARGET_NAME} - PRIVATE - -mcpu=cortex-m4 - -mfpu=fpv4-sp-d16 - -mfloat-abi=hard - -mthumb + ${TARGET_NAME} + PRIVATE + -mcpu=cortex-m4 + -mfpu=fpv4-sp-d16 + -mfloat-abi=hard + -mthumb ) target_link_options( - ${TARGET_NAME} - PRIVATE - -mcpu=cortex-m4 - -mfpu=fpv4-sp-d16 - -mfloat-abi=hard - -mthumb + ${TARGET_NAME} + PRIVATE + -mcpu=cortex-m4 + -mfpu=fpv4-sp-d16 + -mfloat-abi=hard + -mthumb ) diff --git a/Lib/Vendor/TargetFlags/stm32h5xx.cmake b/Lib/Vendor/TargetFlags/stm32h5xx.cmake index 372a7a537..e8ade8126 100644 --- a/Lib/Vendor/TargetFlags/stm32h5xx.cmake +++ b/Lib/Vendor/TargetFlags/stm32h5xx.cmake @@ -1,8 +1,8 @@ target_compile_options( - ${TARGET_NAME} - PRIVATE - -mcpu=cortex-m33 - -mfpu=fpv5-sp-d16 - -mfloat-abi=hard - -mthumb + ${TARGET_NAME} + PRIVATE + -mcpu=cortex-m33 + -mfpu=fpv5-sp-d16 + -mfloat-abi=hard + -mthumb ) diff --git a/Lib/Vendor/TargetFlags/stm32l4xx.cmake b/Lib/Vendor/TargetFlags/stm32l4xx.cmake index 0f074d3d0..587463c17 100644 --- a/Lib/Vendor/TargetFlags/stm32l4xx.cmake +++ b/Lib/Vendor/TargetFlags/stm32l4xx.cmake @@ -1,8 +1,8 @@ target_compile_options( - ${TARGET_NAME} - PRIVATE - -mcpu=cortex-m4 - -mfpu=fpv4-sp-d16 - -mfloat-abi=hard - -mthumb + ${TARGET_NAME} + PRIVATE + -mcpu=cortex-m4 + -mfpu=fpv4-sp-d16 + -mfloat-abi=hard + -mthumb ) diff --git a/Lib/Vendor/TargetFlags/stm32u5xx.cmake b/Lib/Vendor/TargetFlags/stm32u5xx.cmake index 3f127fcf2..263580b13 100644 --- a/Lib/Vendor/TargetFlags/stm32u5xx.cmake +++ b/Lib/Vendor/TargetFlags/stm32u5xx.cmake @@ -1,8 +1,8 @@ target_compile_options( - ${TARGET_NAME} - PRIVATE - -mcpu=cortex-m33 - -mfpu=fpv4-sp-d16 - -mfloat-abi=hard - -mthumb + ${TARGET_NAME} + PRIVATE + -mcpu=cortex-m33 + -mfpu=fpv4-sp-d16 + -mfloat-abi=hard + -mthumb ) diff --git a/Lib/cmake/cube.cmake b/Lib/cmake/cube.cmake index a8caf1b4f..bb3afee52 100644 --- a/Lib/cmake/cube.cmake +++ b/Lib/cmake/cube.cmake @@ -12,55 +12,84 @@ include(FetchContent) @remark Prefer calling add_project() instead of this function directly ]] function(download_git) - if(NOT ${ARGC} EQUAL 10) - message( - FATAL_ERROR - "You called download_git with an unsupported number of inputs/arguments! Do better please :)" - ) - endif() - - set(one_value_args NAME GIT_REPOSITORY GIT_TAG OUTPUT_PATH_VAR) - set(multi_value_args TARGET_FOLDER) - unset(DOWNLOAD_GIT_ARG_NAME) - unset(DOWNLOAD_GIT_ARG_GIT_REPOSITORY) - unset(DOWNLOAD_GIT_ARG_GIT_TAG) - unset(DOWNLOAD_GIT_ARG_OUTPUT_PATH_VAR) - unset(DOWNLOAD_GIT_ARG_TARGET_FOLDER) - cmake_parse_arguments("DOWNLOAD_GIT_ARG" "" "${one_value_args}" "${multi_value_args}" ${ARGN}) - - message(STATUS "This may take a moment, fetching content for ${DOWNLOAD_GIT_ARG_NAME} from ${DOWNLOAD_GIT_ARG_GIT_REPOSITORY} at tag ${DOWNLOAD_GIT_ARG_GIT_TAG}") - - FetchContent_Declare( - "${DOWNLOAD_GIT_ARG_NAME}" - GIT_REPOSITORY "${DOWNLOAD_GIT_ARG_GIT_REPOSITORY}" - GIT_TAG "${DOWNLOAD_GIT_ARG_GIT_TAG}" - GIT_SHALLOW ON - GIT_SUBMODULES "" - UPDATE_DISCONNECTED TRUE - GIT_CONFIG "core.sparseCheckout=true" - ) - - string(TOLOWER "${DOWNLOAD_GIT_ARG_NAME}" NAME_LOWER) - - FetchContent_GetProperties(${NAME_LOWER}) - - if(NOT ${NAME_LOWER}_POPULATED) - FetchContent_Populate(${NAME_LOWER}) - separate_arguments(TARGET_FOLDER_LIST NATIVE_COMMAND "${DOWNLOAD_GIT_ARG_TARGET_FOLDER}") - execute_process( - COMMAND git sparse-checkout set ${TARGET_FOLDER_LIST} - WORKING_DIRECTORY "${${NAME_LOWER}_SOURCE_DIR}" - ) - execute_process( - COMMAND git checkout - WORKING_DIRECTORY "${${NAME_LOWER}_SOURCE_DIR}" - ) - endif() - - message(STATUS "Successfully fetched content for ${DOWNLOAD_GIT_ARG_NAME} from ${DOWNLOAD_GIT_ARG_GIT_REPOSITORY} at tag ${DOWNLOAD_GIT_ARG_GIT_TAG} to ${${DOWNLOAD_GIT_ARG_NAME}_SOURCE_DIR}") - - set("${DOWNLOAD_GIT_ARG_OUTPUT_PATH_VAR}" "${${DOWNLOAD_GIT_ARG_NAME}_SOURCE_DIR}") - return(PROPAGATE "${DOWNLOAD_GIT_ARG_OUTPUT_PATH_VAR}") + if(NOT ${ARGC} EQUAL 10) + message( + FATAL_ERROR + "You called download_git with an unsupported number of inputs/arguments! Do better please :)" + ) + endif() + + set( + one_value_args + NAME + GIT_REPOSITORY + GIT_TAG + OUTPUT_PATH_VAR + ) + set(multi_value_args TARGET_FOLDER) + unset(DOWNLOAD_GIT_ARG_NAME) + unset(DOWNLOAD_GIT_ARG_GIT_REPOSITORY) + unset(DOWNLOAD_GIT_ARG_GIT_TAG) + unset(DOWNLOAD_GIT_ARG_OUTPUT_PATH_VAR) + unset(DOWNLOAD_GIT_ARG_TARGET_FOLDER) + cmake_parse_arguments( + "DOWNLOAD_GIT_ARG" + "" + "${one_value_args}" + "${multi_value_args}" + ${ARGN} + ) + + message( + STATUS + "This may take a moment, fetching content for ${DOWNLOAD_GIT_ARG_NAME} from ${DOWNLOAD_GIT_ARG_GIT_REPOSITORY} at tag ${DOWNLOAD_GIT_ARG_GIT_TAG}" + ) + + FetchContent_Declare( + "${DOWNLOAD_GIT_ARG_NAME}" + GIT_REPOSITORY "${DOWNLOAD_GIT_ARG_GIT_REPOSITORY}" + GIT_TAG "${DOWNLOAD_GIT_ARG_GIT_TAG}" + GIT_SHALLOW ON + GIT_SUBMODULES + "" + UPDATE_DISCONNECTED TRUE + GIT_CONFIG + "core.sparseCheckout=true" + ) + + string(TOLOWER "${DOWNLOAD_GIT_ARG_NAME}" NAME_LOWER) + + FetchContent_GetProperties(${NAME_LOWER}) + + if(NOT ${NAME_LOWER}_POPULATED) + FetchContent_Populate(${NAME_LOWER}) + separate_arguments( + TARGET_FOLDER_LIST + NATIVE_COMMAND + "${DOWNLOAD_GIT_ARG_TARGET_FOLDER}" + ) + execute_process( + COMMAND + git sparse-checkout set ${TARGET_FOLDER_LIST} + WORKING_DIRECTORY "${${NAME_LOWER}_SOURCE_DIR}" + ) + execute_process( + COMMAND + git checkout + WORKING_DIRECTORY "${${NAME_LOWER}_SOURCE_DIR}" + ) + endif() + + message( + STATUS + "Successfully fetched content for ${DOWNLOAD_GIT_ARG_NAME} from ${DOWNLOAD_GIT_ARG_GIT_REPOSITORY} at tag ${DOWNLOAD_GIT_ARG_GIT_TAG} to ${${DOWNLOAD_GIT_ARG_NAME}_SOURCE_DIR}" + ) + + set( + "${DOWNLOAD_GIT_ARG_OUTPUT_PATH_VAR}" + "${${DOWNLOAD_GIT_ARG_NAME}_SOURCE_DIR}" + ) + return(PROPAGATE "${DOWNLOAD_GIT_ARG_OUTPUT_PATH_VAR}") endfunction() #[[ @@ -71,36 +100,46 @@ endfunction() @remark Prefer calling add_project() instead of this function directly ]] function(add_arm_cmsis_core) - if(NOT ${ARGC} EQUAL 4) - message( - FATAL_ERROR - "You called add_arm_cmsis_core with an unsupported number of inputs/arguments! Do better please :)" - ) - endif() - - set(one_value_args MAJOR GIT_TAG) - unset(ARM_CMSIS_CORE_ARG_MAJOR) - unset(ARM_CMSIS_CORE_ARG_GIT_TAG) - cmake_parse_arguments("ARM_CMSIS_CORE_ARG" "" "${one_value_args}" "" ${ARGN}) - - if(NOT ARM_CMSIS_CORE_ARG_MAJOR MATCHES "^[0-9]$") - message(FATAL_ERROR "MAJOR '${ARM_CMSIS_CORE_ARG_MAJOR}' is not a valid version number (ie '5')") - endif() - - download_git( - NAME "arm_cmsis_${ARM_CMSIS_CORE_ARG_MAJOR}" - GIT_REPOSITORY "https://github.com/arm-software/cmsis_${ARM_CMSIS_CORE_ARG_MAJOR}.git" - GIT_TAG "${ARM_CMSIS_CORE_ARG_GIT_TAG}" - OUTPUT_PATH_VAR ARM_CMSIS_CORE_PATH - TARGET_FOLDER "CMSIS/Core/Include" - ) - message(STATUS "Successfully fetched content for ARM CMSIS core version ${ARM_CMSIS_CORE_ARG_MAJOR} from ${ARM_CMSIS_CORE_ARG_GIT_TAG} to ${ARM_CMSIS_CORE_PATH}") - add_library(CMSIS_${ARM_CMSIS_CORE_ARG_MAJOR}_Core INTERFACE) - target_include_directories( - CMSIS_${ARM_CMSIS_CORE_ARG_MAJOR}_Core - INTERFACE - $ - ) + if(NOT ${ARGC} EQUAL 4) + message( + FATAL_ERROR + "You called add_arm_cmsis_core with an unsupported number of inputs/arguments! Do better please :)" + ) + endif() + + set( + one_value_args + MAJOR + GIT_TAG + ) + unset(ARM_CMSIS_CORE_ARG_MAJOR) + unset(ARM_CMSIS_CORE_ARG_GIT_TAG) + cmake_parse_arguments("ARM_CMSIS_CORE_ARG" "" "${one_value_args}" "" ${ARGN}) + + if(NOT ARM_CMSIS_CORE_ARG_MAJOR MATCHES "^[0-9]$") + message( + FATAL_ERROR + "MAJOR '${ARM_CMSIS_CORE_ARG_MAJOR}' is not a valid version number (ie '5')" + ) + endif() + + download_git( + NAME "arm_cmsis_${ARM_CMSIS_CORE_ARG_MAJOR}" + GIT_REPOSITORY "https://github.com/arm-software/cmsis_${ARM_CMSIS_CORE_ARG_MAJOR}.git" + GIT_TAG "${ARM_CMSIS_CORE_ARG_GIT_TAG}" + OUTPUT_PATH_VAR ARM_CMSIS_CORE_PATH + TARGET_FOLDER "CMSIS/Core/Include" + ) + message( + STATUS + "Successfully fetched content for ARM CMSIS core version ${ARM_CMSIS_CORE_ARG_MAJOR} from ${ARM_CMSIS_CORE_ARG_GIT_TAG} to ${ARM_CMSIS_CORE_PATH}" + ) + add_library(CMSIS_${ARM_CMSIS_CORE_ARG_MAJOR}_Core INTERFACE) + target_include_directories( + CMSIS_${ARM_CMSIS_CORE_ARG_MAJOR}_Core + INTERFACE + $ + ) endfunction() #[[ @@ -112,59 +151,89 @@ endfunction() @remark Prefer calling add_project() instead of this function directly ]] function(add_arm_cmsis_interface) - if(NOT ${ARGC} EQUAL 6) - message( - FATAL_ERROR - "You called add_arm_cmsis_interface with an unsupported number of inputs/arguments! Do better please :)" - ) - endif() - - set(one_value_args SERIES SPECIFIER GIT_TAG) - unset(ARM_CMSIS_INTERFACE_ARG_SERIES) - unset(ARM_CMSIS_INTERFACE_ARG_SPECIFIER) - unset(ARM_CMSIS_INTERFACE_ARG_GIT_TAG) - cmake_parse_arguments("ARM_CMSIS_INTERFACE_ARG" "" "${one_value_args}" "" ${ARGN}) - - message(VERBOSE "Adding ARM CMSIS device interface for SERIES '${ARM_CMSIS_INTERFACE_ARG_SERIES}', SPECIFIER '${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}', and GIT_TAG '${ARM_CMSIS_INTERFACE_ARG_GIT_TAG}'") - - string(LENGTH "${ARM_CMSIS_INTERFACE_ARG_SERIES}" SERIES_LENGTH) - if(NOT SERIES_LENGTH EQUAL 2) - message(FATAL_ERROR "SERIES '${ARM_CMSIS_INTERFACE_ARG_SERIES}' must be 2 characters long (ie 'g4')") - endif() - string(TOLOWER "${ARM_CMSIS_INTERFACE_ARG_SERIES}" SERIES_LOWER) - - string(LENGTH "${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}" SPECIFIER_LENGTH) - if(SPECIFIER_LENGTH LESS 6) - message(FATAL_ERROR "SPECIFIER '${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}' must be at least 6 characters long (ie 'g474re' or 'g474ret6')") - endif() - string(TOLOWER "${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}" SPECIFIER_LOWER) - string(TOUPPER "${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}" SPECIFIER_UPPER) - - string(FIND "${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}" "${ARM_CMSIS_INTERFACE_ARG_SERIES}" SERIES_POSITION_IN_SPECIFIER) - if(NOT SERIES_POSITION_IN_SPECIFIER EQUAL 0) - message(FATAL_ERROR "SPECIFIER '${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}' must start with SERIES '${ARM_CMSIS_INTERFACE_ARG_SERIES}' at the beginning (eg 'g4' and 'g474ret6')") - endif() - - download_git( - NAME "cmsis_device_${SERIES_LOWER}" - GIT_REPOSITORY "https://github.com/STMicroelectronics/cmsis-device-${SERIES_LOWER}.git" - GIT_TAG ${ARM_CMSIS_INTERFACE_ARG_GIT_TAG} - TARGET_FOLDER "Include" - OUTPUT_PATH_VAR CMSIS_DEVICE_PATH - ) - message(STATUS "Successfully fetched content for ARM CMSIS device ${SPECIFIER_UPPER} from ${ARM_CMSIS_INTERFACE_ARG_GIT_TAG} to ${CMSIS_DEVICE_PATH}") - add_library("CMSIS_Device_${SPECIFIER_UPPER}" INTERFACE) - target_include_directories( - "CMSIS_Device_${SPECIFIER_UPPER}" - INTERFACE - $ - ) - target_compile_definitions( - "CMSIS_Device_${SPECIFIER_UPPER}" - INTERFACE - "STM32${SERIES_UPPER}xx" - "USE_HAL_DRIVER" - ) + if(NOT ${ARGC} EQUAL 6) + message( + FATAL_ERROR + "You called add_arm_cmsis_interface with an unsupported number of inputs/arguments! Do better please :)" + ) + endif() + + set( + one_value_args + SERIES + SPECIFIER + GIT_TAG + ) + unset(ARM_CMSIS_INTERFACE_ARG_SERIES) + unset(ARM_CMSIS_INTERFACE_ARG_SPECIFIER) + unset(ARM_CMSIS_INTERFACE_ARG_GIT_TAG) + cmake_parse_arguments( + "ARM_CMSIS_INTERFACE_ARG" + "" + "${one_value_args}" + "" + ${ARGN} + ) + + message( + VERBOSE + "Adding ARM CMSIS device interface for SERIES '${ARM_CMSIS_INTERFACE_ARG_SERIES}', SPECIFIER '${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}', and GIT_TAG '${ARM_CMSIS_INTERFACE_ARG_GIT_TAG}'" + ) + + string(LENGTH "${ARM_CMSIS_INTERFACE_ARG_SERIES}" SERIES_LENGTH) + if(NOT SERIES_LENGTH EQUAL 2) + message( + FATAL_ERROR + "SERIES '${ARM_CMSIS_INTERFACE_ARG_SERIES}' must be 2 characters long (ie 'g4')" + ) + endif() + string(TOLOWER "${ARM_CMSIS_INTERFACE_ARG_SERIES}" SERIES_LOWER) + + string(LENGTH "${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}" SPECIFIER_LENGTH) + if(SPECIFIER_LENGTH LESS 6) + message( + FATAL_ERROR + "SPECIFIER '${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}' must be at least 6 characters long (ie 'g474re' or 'g474ret6')" + ) + endif() + string(TOLOWER "${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}" SPECIFIER_LOWER) + string(TOUPPER "${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}" SPECIFIER_UPPER) + + string( + FIND "${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}" + "${ARM_CMSIS_INTERFACE_ARG_SERIES}" + SERIES_POSITION_IN_SPECIFIER + ) + if(NOT SERIES_POSITION_IN_SPECIFIER EQUAL 0) + message( + FATAL_ERROR + "SPECIFIER '${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}' must start with SERIES '${ARM_CMSIS_INTERFACE_ARG_SERIES}' at the beginning (eg 'g4' and 'g474ret6')" + ) + endif() + + download_git( + NAME "cmsis_device_${SERIES_LOWER}" + GIT_REPOSITORY "https://github.com/STMicroelectronics/cmsis-device-${SERIES_LOWER}.git" + GIT_TAG ${ARM_CMSIS_INTERFACE_ARG_GIT_TAG} + TARGET_FOLDER "Include" + OUTPUT_PATH_VAR CMSIS_DEVICE_PATH + ) + message( + STATUS + "Successfully fetched content for ARM CMSIS device ${SPECIFIER_UPPER} from ${ARM_CMSIS_INTERFACE_ARG_GIT_TAG} to ${CMSIS_DEVICE_PATH}" + ) + add_library("CMSIS_Device_${SPECIFIER_UPPER}" INTERFACE) + target_include_directories( + "CMSIS_Device_${SPECIFIER_UPPER}" + INTERFACE + $ + ) + target_compile_definitions( + "CMSIS_Device_${SPECIFIER_UPPER}" + INTERFACE + "STM32${SERIES_UPPER}xx" + "USE_HAL_DRIVER" + ) endfunction() #[[ @@ -175,50 +244,63 @@ endfunction() @remark Prefer calling add_project() instead of this function directly ]] function(add_stm32_hal_interface) - if(NOT ${ARGC} EQUAL 4) - message( - FATAL_ERROR - "You called add_stm32_hal_interface with an unsupported number of inputs/arguments! Do better please :)" - ) - endif() - - set(one_value_args SERIES GIT_TAG) - cmake_parse_arguments("STM32_HAL_ARG" "" "${one_value_args}" "" ${ARGN}) - - message(VERBOSE "Adding STM32 HAL driver interface for SERIES '${STM32_HAL_ARG_SERIES}' with GIT_TAG '${STM32_HAL_ARG_GIT_TAG}'") - - string(LENGTH "${STM32_HAL_ARG_SERIES}" SERIES_LENGTH) - if(NOT SERIES_LENGTH EQUAL 2) - message(FATAL_ERROR "SERIES '${STM32_HAL_ARG_SERIES}' must be 2 characters long (ie 'g4')") - endif() - - string(TOLOWER "${STM32_HAL_ARG_SERIES}" SERIES_LOWER) - string(TOUPPER "${STM32_HAL_ARG_SERIES}" SERIES_UPPER) - - download_git( - NAME "stm32_hal_driver_${SERIES_LOWER}" - GIT_REPOSITORY "https://github.com/STMicroelectronics/stm32${SERIES_LOWER}xx-hal-driver.git" - GIT_TAG ${STM32_HAL_ARG_GIT_TAG} - TARGET_FOLDER "Inc Src" - OUTPUT_PATH_VAR STM32_HAL_DRIVER_PATH - ) - message(STATUS "Successfully fetched content for STM32 HAL driver ${SERIES_UPPER} from ${STM32_HAL_ARG_GIT_TAG} to ${STM32_HAL_DRIVER_PATH}") - add_library("STM32HAL_${SERIES_UPPER}" INTERFACE) - - target_include_directories( - "STM32HAL_${SERIES_UPPER}" - INTERFACE - $ - $ - ) - - file(GLOB_RECURSE HAL_SOURCES CONFIGURE_DEPENDS "${STM32_HAL_DRIVER_PATH}/Src/*.c") - list(FILTER HAL_SOURCES EXCLUDE REGEX ".*_template\.c$") - target_sources( - "STM32HAL_${SERIES_UPPER}" - INTERFACE - ${HAL_SOURCES} - ) + if(NOT ${ARGC} EQUAL 4) + message( + FATAL_ERROR + "You called add_stm32_hal_interface with an unsupported number of inputs/arguments! Do better please :)" + ) + endif() + + set( + one_value_args + SERIES + GIT_TAG + ) + cmake_parse_arguments("STM32_HAL_ARG" "" "${one_value_args}" "" ${ARGN}) + + message( + VERBOSE + "Adding STM32 HAL driver interface for SERIES '${STM32_HAL_ARG_SERIES}' with GIT_TAG '${STM32_HAL_ARG_GIT_TAG}'" + ) + + string(LENGTH "${STM32_HAL_ARG_SERIES}" SERIES_LENGTH) + if(NOT SERIES_LENGTH EQUAL 2) + message( + FATAL_ERROR + "SERIES '${STM32_HAL_ARG_SERIES}' must be 2 characters long (ie 'g4')" + ) + endif() + + string(TOLOWER "${STM32_HAL_ARG_SERIES}" SERIES_LOWER) + string(TOUPPER "${STM32_HAL_ARG_SERIES}" SERIES_UPPER) + + download_git( + NAME "stm32_hal_driver_${SERIES_LOWER}" + GIT_REPOSITORY "https://github.com/STMicroelectronics/stm32${SERIES_LOWER}xx-hal-driver.git" + GIT_TAG ${STM32_HAL_ARG_GIT_TAG} + TARGET_FOLDER "Inc Src" + OUTPUT_PATH_VAR STM32_HAL_DRIVER_PATH + ) + message( + STATUS + "Successfully fetched content for STM32 HAL driver ${SERIES_UPPER} from ${STM32_HAL_ARG_GIT_TAG} to ${STM32_HAL_DRIVER_PATH}" + ) + add_library("STM32HAL_${SERIES_UPPER}" INTERFACE) + + target_include_directories( + "STM32HAL_${SERIES_UPPER}" + INTERFACE + $ + $ + ) + + file( + GLOB_RECURSE HAL_SOURCES + CONFIGURE_DEPENDS + "${STM32_HAL_DRIVER_PATH}/Src/*.c" + ) + list(FILTER HAL_SOURCES EXCLUDE REGEX ".*_template\.c$") + target_sources("STM32HAL_${SERIES_UPPER}" INTERFACE ${HAL_SOURCES}) endfunction() #[[ @@ -233,76 +315,90 @@ endfunction() @note Link your user code against "${NAME}_USER_CODE" to ensure proper linking with the STM32 HAL and CMSIS libraries ]] function(add_project) - if(NOT ${ARGC} EQUAL 14) - message( - FATAL_ERROR - "You called add_project with an unsupported number of inputs/arguments! Do better please :)" - ) - endif() - - set(one_value_args NAME PATH SERIES SPECIFIER HAL_GIT_TAG CMSIS_GIT_TAG CMSIS_MAJOR) - cmake_parse_arguments("ARG" "" "${one_value_args}" "" ${ARGN}) - string(TOUPPER "${ARG_SERIES}" SERIES_UPPER) - string(TOLOWER "${ARG_SERIES}" SERIES_LOWER) - string(TOUPPER "${ARG_SPECIFIER}" SPECIFIER_UPPER) - - message(DEBUG "Adding project '${ARG_NAME}' at path '${ARG_PATH}' with SERIES '${ARG_SERIES}', SPECIFIER '${ARG_SPECIFIER}', HAL_GIT_TAG '${ARG_HAL_GIT_TAG}', CMSIS_GIT_TAG '${ARG_CMSIS_GIT_TAG}', and CMSIS_MAJOR '${ARG_CMSIS_MAJOR}'") - - add_arm_cmsis_interface( - SERIES ${ARG_SERIES} - SPECIFIER ${ARG_SPECIFIER} - GIT_TAG ${ARG_CMSIS_GIT_TAG} - ) - - add_stm32_hal_interface( - SERIES ${ARG_SERIES} - GIT_TAG ${ARG_HAL_GIT_TAG} - ) - - if(CMAKE_PRESET_NAME STREQUAL "HOOTLTest") - # TODO Later, out of scope for now - else() - set(TARGET_NAME "${ARG_NAME}") - message(STATUS "Adding project '${TARGET_NAME}'") - add_executable("${TARGET_NAME}") - - include("${PROJECT_SOURCE_DIR}/Lib/Vendor/TargetFlags/stm32${SERIES_LOWER}xx.cmake") - - target_compile_options( - "${TARGET_NAME}" - PRIVATE - "${stm32${SERIES_LOWER}xx_flags}" - ) - - target_link_libraries( - "${TARGET_NAME}" - PRIVATE - "CMSIS_Device_${SPECIFIER_UPPER}" - "CMSIS_${ARG_CMSIS_MAJOR}_Core" - "STM32HAL_${SERIES_UPPER}" - # "stm32${SERIES_LOWER}xx_flags" - GLOBALSHARE_LIB - m - ) - - target_link_options( - "${TARGET_NAME}" - PRIVATE - "LINKER:-Map=$/$.map" - ) - - target_compile_definitions( - "${TARGET_NAME}" - PRIVATE - USE_HAL_DRIVER - USE_FULL_LL_DRIVER - STM32${SERIES_UPPER}xx - ) - endif() - - if(DEFINED NODE) - target_compile_definitions("${ARG_NAME}" PRIVATE NODE=${NODE}) - endif() - - add_subdirectory("${PROJECT_SOURCE_DIR}/${ARG_PATH}") + if(NOT ${ARGC} EQUAL 14) + message( + FATAL_ERROR + "You called add_project with an unsupported number of inputs/arguments! Do better please :)" + ) + endif() + + set( + one_value_args + NAME + PATH + SERIES + SPECIFIER + HAL_GIT_TAG + CMSIS_GIT_TAG + CMSIS_MAJOR + ) + cmake_parse_arguments("ARG" "" "${one_value_args}" "" ${ARGN}) + string(TOUPPER "${ARG_SERIES}" SERIES_UPPER) + string(TOLOWER "${ARG_SERIES}" SERIES_LOWER) + string(TOUPPER "${ARG_SPECIFIER}" SPECIFIER_UPPER) + + message( + DEBUG + "Adding project '${ARG_NAME}' at path '${ARG_PATH}' with SERIES '${ARG_SERIES}', SPECIFIER '${ARG_SPECIFIER}', HAL_GIT_TAG '${ARG_HAL_GIT_TAG}', CMSIS_GIT_TAG '${ARG_CMSIS_GIT_TAG}', and CMSIS_MAJOR '${ARG_CMSIS_MAJOR}'" + ) + + add_arm_cmsis_interface( + SERIES ${ARG_SERIES} + SPECIFIER ${ARG_SPECIFIER} + GIT_TAG ${ARG_CMSIS_GIT_TAG} + ) + + add_stm32_hal_interface( + SERIES ${ARG_SERIES} + GIT_TAG ${ARG_HAL_GIT_TAG} + ) + + if(CMAKE_PRESET_NAME STREQUAL "HOOTLTest") + # TODO Later, out of scope for now + else() + set(TARGET_NAME "${ARG_NAME}") + message(STATUS "Adding project '${TARGET_NAME}'") + add_executable("${TARGET_NAME}") + + include( + "${PROJECT_SOURCE_DIR}/Lib/Vendor/TargetFlags/stm32${SERIES_LOWER}xx.cmake" + ) + + target_compile_options( + "${TARGET_NAME}" + PRIVATE + "${stm32${SERIES_LOWER}xx_flags}" + ) + + target_link_libraries( + "${TARGET_NAME}" + PRIVATE + "CMSIS_Device_${SPECIFIER_UPPER}" + "CMSIS_${ARG_CMSIS_MAJOR}_Core" + "STM32HAL_${SERIES_UPPER}" + # "stm32${SERIES_LOWER}xx_flags" + GLOBALSHARE_LIB + m + ) + + target_link_options( + "${TARGET_NAME}" + PRIVATE + "LINKER:-Map=$/$.map" + ) + + target_compile_definitions( + "${TARGET_NAME}" + PRIVATE + USE_HAL_DRIVER + USE_FULL_LL_DRIVER + STM32${SERIES_UPPER}xx + ) + endif() + + if(DEFINED NODE) + target_compile_definitions("${ARG_NAME}" PRIVATE NODE=${NODE}) + endif() + + add_subdirectory("${PROJECT_SOURCE_DIR}/${ARG_PATH}") endfunction() From 8e06886ca5868752cd3180d9b7c77b6bc4077c71 Mon Sep 17 00:00:00 2001 From: github-actions <41898282+github-actions[bot]@users.noreply.github.com> Date: Sun, 23 Aug 2026 09:55:02 +0000 Subject: [PATCH 04/17] Automatic Assembly Format: Standardized formatting automatically --- Testbench/CUBEMXTESTING/startup_stm32g474xx.s | 676 +++++++++--------- 1 file changed, 340 insertions(+), 336 deletions(-) diff --git a/Testbench/CUBEMXTESTING/startup_stm32g474xx.s b/Testbench/CUBEMXTESTING/startup_stm32g474xx.s index e7a2c61fc..31cf98b7f 100644 --- a/Testbench/CUBEMXTESTING/startup_stm32g474xx.s +++ b/Testbench/CUBEMXTESTING/startup_stm32g474xx.s @@ -1,592 +1,596 @@ -/** - ****************************************************************************** - * @file startup_stm32g474xx.s - * @author MCD Application Team - * @brief STM32G474xx devices vector table GCC toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address, - * - Configure the clock system - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M4 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - * Copyright (c) 2019 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m4 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler +/* * + ****************************************************************************** + * @file startup_stm32g474xx.s + * @author MCD Application Team + * @brief STM32G474xx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +.syntax unified +.cpu cortex-m4 +.fpu softvfp +.thumb + +.global g_pfnVectors +.global Default_Handler /* start address for the initialization values of the .data section. defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss - -.equ BootRAM, 0xF1E0F85F -/** +.word _sidata + +// start address for the .data section. defined in linker script +.word _sdata + +// end address for the .data section. defined in linker script +.word _edata + +// start address for the .bss section. defined in linker script +.word _sbss + +// end address for the .bss section. defined in linker script +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/* * * @brief This is the code that gets called when the processor first * starts execution following a reset event. Only the absolutely * necessary set is performed, after which the application * supplied main() routine is called. * @param None * @retval : None -*/ + */ + +.section .text.Reset_Handler +.weak Reset_Handler +.type Reset_Handler, %function - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function Reset_Handler: - ldr r0, =_estack - mov sp, r0 /* set stack pointer */ + ldr r0, =_estack + mov sp, r0 // set stack pointer -/* Call the clock system initialization function.*/ - bl SystemInit + // Call the clock system initialization function. + bl SystemInit -/* Copy the data segment initializers from flash to SRAM */ - ldr r0, =_sdata - ldr r1, =_edata - ldr r2, =_sidata - movs r3, #0 - b LoopCopyDataInit + // Copy the data segment initializers from flash to SRAM + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit CopyDataInit: - ldr r4, [r2, r3] - str r4, [r0, r3] - adds r3, r3, #4 + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 LoopCopyDataInit: - adds r4, r0, r3 - cmp r4, r1 - bcc CopyDataInit - -/* Zero fill the bss segment. */ - ldr r2, =_sbss - ldr r4, =_ebss - movs r3, #0 - b LoopFillZerobss + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + + // Zero fill the bss segment. + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss FillZerobss: - str r3, [r2] - adds r2, r2, #4 + str r3, [r2] + adds r2, r2, #4 LoopFillZerobss: - cmp r2, r4 - bcc FillZerobss + cmp r2, r4 + bcc FillZerobss + + // Call static constructors + bl __libc_init_array -/* Call static constructors */ - bl __libc_init_array -/* Call the application's entry point.*/ - bl main + // Call the application's entry point. + bl main LoopForever: - b LoopForever + b LoopForever -.size Reset_Handler, .-Reset_Handler + .size Reset_Handler, .-Reset_Handler -/** +/* * * @brief This is the code that gets called when the processor receives an * unexpected interrupt. This simply enters an infinite loop, preserving * the system state for examination by a debugger. * * @param None * @retval : None -*/ - .section .text.Default_Handler,"ax",%progbits + */ + .section .text.Default_Handler, "ax", %progbits + Default_Handler: Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex-M4. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/* ***************************************************************************** + * + * The minimal vector table for a Cortex-M4. Note that the proper constructs + * must be placed on this to ensure that it ends up at physical address + * 0x0000.0000. + * +***************************************************************************** */ + .section .isr_vector, "a", %progbits + .type g_pfnVectors, %object g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler - .word PVD_PVM_IRQHandler - .word RTC_TAMP_LSECSS_IRQHandler - .word RTC_WKUP_IRQHandler - .word FLASH_IRQHandler - .word RCC_IRQHandler - .word EXTI0_IRQHandler - .word EXTI1_IRQHandler - .word EXTI2_IRQHandler - .word EXTI3_IRQHandler - .word EXTI4_IRQHandler - .word DMA1_Channel1_IRQHandler - .word DMA1_Channel2_IRQHandler - .word DMA1_Channel3_IRQHandler - .word DMA1_Channel4_IRQHandler - .word DMA1_Channel5_IRQHandler - .word DMA1_Channel6_IRQHandler - .word DMA1_Channel7_IRQHandler - .word ADC1_2_IRQHandler - .word USB_HP_IRQHandler - .word USB_LP_IRQHandler - .word FDCAN1_IT0_IRQHandler - .word FDCAN1_IT1_IRQHandler - .word EXTI9_5_IRQHandler - .word TIM1_BRK_TIM15_IRQHandler - .word TIM1_UP_TIM16_IRQHandler - .word TIM1_TRG_COM_TIM17_IRQHandler - .word TIM1_CC_IRQHandler - .word TIM2_IRQHandler - .word TIM3_IRQHandler - .word TIM4_IRQHandler - .word I2C1_EV_IRQHandler - .word I2C1_ER_IRQHandler - .word I2C2_EV_IRQHandler - .word I2C2_ER_IRQHandler - .word SPI1_IRQHandler - .word SPI2_IRQHandler - .word USART1_IRQHandler - .word USART2_IRQHandler - .word USART3_IRQHandler - .word EXTI15_10_IRQHandler - .word RTC_Alarm_IRQHandler - .word USBWakeUp_IRQHandler - .word TIM8_BRK_IRQHandler - .word TIM8_UP_IRQHandler - .word TIM8_TRG_COM_IRQHandler - .word TIM8_CC_IRQHandler - .word ADC3_IRQHandler - .word FMC_IRQHandler - .word LPTIM1_IRQHandler - .word TIM5_IRQHandler - .word SPI3_IRQHandler - .word UART4_IRQHandler - .word UART5_IRQHandler - .word TIM6_DAC_IRQHandler - .word TIM7_DAC_IRQHandler - .word DMA2_Channel1_IRQHandler - .word DMA2_Channel2_IRQHandler - .word DMA2_Channel3_IRQHandler - .word DMA2_Channel4_IRQHandler - .word DMA2_Channel5_IRQHandler - .word ADC4_IRQHandler - .word ADC5_IRQHandler - .word UCPD1_IRQHandler - .word COMP1_2_3_IRQHandler - .word COMP4_5_6_IRQHandler - .word COMP7_IRQHandler - .word HRTIM1_Master_IRQHandler - .word HRTIM1_TIMA_IRQHandler - .word HRTIM1_TIMB_IRQHandler - .word HRTIM1_TIMC_IRQHandler - .word HRTIM1_TIMD_IRQHandler - .word HRTIM1_TIME_IRQHandler - .word HRTIM1_FLT_IRQHandler - .word HRTIM1_TIMF_IRQHandler - .word CRS_IRQHandler - .word SAI1_IRQHandler - .word TIM20_BRK_IRQHandler - .word TIM20_UP_IRQHandler - .word TIM20_TRG_COM_IRQHandler - .word TIM20_CC_IRQHandler - .word FPU_IRQHandler - .word I2C4_EV_IRQHandler - .word I2C4_ER_IRQHandler - .word SPI4_IRQHandler - .word 0 - .word FDCAN2_IT0_IRQHandler - .word FDCAN2_IT1_IRQHandler - .word FDCAN3_IT0_IRQHandler - .word FDCAN3_IT1_IRQHandler - .word RNG_IRQHandler - .word LPUART1_IRQHandler - .word I2C3_EV_IRQHandler - .word I2C3_ER_IRQHandler - .word DMAMUX_OVR_IRQHandler - .word QUADSPI_IRQHandler - .word DMA1_Channel8_IRQHandler - .word DMA2_Channel6_IRQHandler - .word DMA2_Channel7_IRQHandler - .word DMA2_Channel8_IRQHandler - .word CORDIC_IRQHandler - .word FMAC_IRQHandler - - .size g_pfnVectors, .-g_pfnVectors - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - .weak NMI_Handler + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_PVM_IRQHandler + .word RTC_TAMP_LSECSS_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_IRQHandler + .word USB_LP_IRQHandler + .word FDCAN1_IT0_IRQHandler + .word FDCAN1_IT1_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word USBWakeUp_IRQHandler + .word TIM8_BRK_IRQHandler + .word TIM8_UP_IRQHandler + .word TIM8_TRG_COM_IRQHandler + .word TIM8_CC_IRQHandler + .word ADC3_IRQHandler + .word FMC_IRQHandler + .word LPTIM1_IRQHandler + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_DAC_IRQHandler + .word TIM7_DAC_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word ADC4_IRQHandler + .word ADC5_IRQHandler + .word UCPD1_IRQHandler + .word COMP1_2_3_IRQHandler + .word COMP4_5_6_IRQHandler + .word COMP7_IRQHandler + .word HRTIM1_Master_IRQHandler + .word HRTIM1_TIMA_IRQHandler + .word HRTIM1_TIMB_IRQHandler + .word HRTIM1_TIMC_IRQHandler + .word HRTIM1_TIMD_IRQHandler + .word HRTIM1_TIME_IRQHandler + .word HRTIM1_FLT_IRQHandler + .word HRTIM1_TIMF_IRQHandler + .word CRS_IRQHandler + .word SAI1_IRQHandler + .word TIM20_BRK_IRQHandler + .word TIM20_UP_IRQHandler + .word TIM20_TRG_COM_IRQHandler + .word TIM20_CC_IRQHandler + .word FPU_IRQHandler + .word I2C4_EV_IRQHandler + .word I2C4_ER_IRQHandler + .word SPI4_IRQHandler + .word 0 + .word FDCAN2_IT0_IRQHandler + .word FDCAN2_IT1_IRQHandler + .word FDCAN3_IT0_IRQHandler + .word FDCAN3_IT1_IRQHandler + .word RNG_IRQHandler + .word LPUART1_IRQHandler + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word DMAMUX_OVR_IRQHandler + .word QUADSPI_IRQHandler + .word DMA1_Channel8_IRQHandler + .word DMA2_Channel6_IRQHandler + .word DMA2_Channel7_IRQHandler + .word DMA2_Channel8_IRQHandler + .word CORDIC_IRQHandler + .word FMAC_IRQHandler + + .size g_pfnVectors, .-g_pfnVectors + +/* ****************************************************************************** + * + * Provide weak aliases for each Exception handler to the Default_Handler. + * As they are weak aliases, any function with the same name will override + * this definition. + * +****************************************************************************** */ + .weak NMI_Handler .thumb_set NMI_Handler,Default_Handler - .weak HardFault_Handler + .weak HardFault_Handler .thumb_set HardFault_Handler,Default_Handler - .weak MemManage_Handler + .weak MemManage_Handler .thumb_set MemManage_Handler,Default_Handler - .weak BusFault_Handler + .weak BusFault_Handler .thumb_set BusFault_Handler,Default_Handler - .weak UsageFault_Handler + .weak UsageFault_Handler .thumb_set UsageFault_Handler,Default_Handler - .weak SVC_Handler + .weak SVC_Handler .thumb_set SVC_Handler,Default_Handler - .weak DebugMon_Handler + .weak DebugMon_Handler .thumb_set DebugMon_Handler,Default_Handler - .weak PendSV_Handler + .weak PendSV_Handler .thumb_set PendSV_Handler,Default_Handler - .weak SysTick_Handler + .weak SysTick_Handler .thumb_set SysTick_Handler,Default_Handler - .weak WWDG_IRQHandler + .weak WWDG_IRQHandler .thumb_set WWDG_IRQHandler,Default_Handler - .weak PVD_PVM_IRQHandler + .weak PVD_PVM_IRQHandler .thumb_set PVD_PVM_IRQHandler,Default_Handler - .weak RTC_TAMP_LSECSS_IRQHandler + .weak RTC_TAMP_LSECSS_IRQHandler .thumb_set RTC_TAMP_LSECSS_IRQHandler,Default_Handler - .weak RTC_WKUP_IRQHandler + .weak RTC_WKUP_IRQHandler .thumb_set RTC_WKUP_IRQHandler,Default_Handler - .weak FLASH_IRQHandler + .weak FLASH_IRQHandler .thumb_set FLASH_IRQHandler,Default_Handler - .weak RCC_IRQHandler + .weak RCC_IRQHandler .thumb_set RCC_IRQHandler,Default_Handler - .weak EXTI0_IRQHandler + .weak EXTI0_IRQHandler .thumb_set EXTI0_IRQHandler,Default_Handler - .weak EXTI1_IRQHandler + .weak EXTI1_IRQHandler .thumb_set EXTI1_IRQHandler,Default_Handler - .weak EXTI2_IRQHandler + .weak EXTI2_IRQHandler .thumb_set EXTI2_IRQHandler,Default_Handler - .weak EXTI3_IRQHandler + .weak EXTI3_IRQHandler .thumb_set EXTI3_IRQHandler,Default_Handler - .weak EXTI4_IRQHandler + .weak EXTI4_IRQHandler .thumb_set EXTI4_IRQHandler,Default_Handler - .weak DMA1_Channel1_IRQHandler + .weak DMA1_Channel1_IRQHandler .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - .weak DMA1_Channel2_IRQHandler + .weak DMA1_Channel2_IRQHandler .thumb_set DMA1_Channel2_IRQHandler,Default_Handler - .weak DMA1_Channel3_IRQHandler + .weak DMA1_Channel3_IRQHandler .thumb_set DMA1_Channel3_IRQHandler,Default_Handler - .weak DMA1_Channel4_IRQHandler + .weak DMA1_Channel4_IRQHandler .thumb_set DMA1_Channel4_IRQHandler,Default_Handler - .weak DMA1_Channel5_IRQHandler + .weak DMA1_Channel5_IRQHandler .thumb_set DMA1_Channel5_IRQHandler,Default_Handler - .weak DMA1_Channel6_IRQHandler + .weak DMA1_Channel6_IRQHandler .thumb_set DMA1_Channel6_IRQHandler,Default_Handler - .weak DMA1_Channel7_IRQHandler + .weak DMA1_Channel7_IRQHandler .thumb_set DMA1_Channel7_IRQHandler,Default_Handler - .weak ADC1_2_IRQHandler + .weak ADC1_2_IRQHandler .thumb_set ADC1_2_IRQHandler,Default_Handler - .weak USB_HP_IRQHandler + .weak USB_HP_IRQHandler .thumb_set USB_HP_IRQHandler,Default_Handler - .weak USB_LP_IRQHandler + .weak USB_LP_IRQHandler .thumb_set USB_LP_IRQHandler,Default_Handler - .weak FDCAN1_IT0_IRQHandler + .weak FDCAN1_IT0_IRQHandler .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler - .weak FDCAN1_IT1_IRQHandler + .weak FDCAN1_IT1_IRQHandler .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler - .weak EXTI9_5_IRQHandler + .weak EXTI9_5_IRQHandler .thumb_set EXTI9_5_IRQHandler,Default_Handler - .weak TIM1_BRK_TIM15_IRQHandler + .weak TIM1_BRK_TIM15_IRQHandler .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler - .weak TIM1_UP_TIM16_IRQHandler + .weak TIM1_UP_TIM16_IRQHandler .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler - .weak TIM1_TRG_COM_TIM17_IRQHandler + .weak TIM1_TRG_COM_TIM17_IRQHandler .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler - .weak TIM1_CC_IRQHandler + .weak TIM1_CC_IRQHandler .thumb_set TIM1_CC_IRQHandler,Default_Handler - .weak TIM2_IRQHandler + .weak TIM2_IRQHandler .thumb_set TIM2_IRQHandler,Default_Handler - .weak TIM3_IRQHandler + .weak TIM3_IRQHandler .thumb_set TIM3_IRQHandler,Default_Handler - .weak TIM4_IRQHandler + .weak TIM4_IRQHandler .thumb_set TIM4_IRQHandler,Default_Handler - .weak I2C1_EV_IRQHandler + .weak I2C1_EV_IRQHandler .thumb_set I2C1_EV_IRQHandler,Default_Handler - .weak I2C1_ER_IRQHandler + .weak I2C1_ER_IRQHandler .thumb_set I2C1_ER_IRQHandler,Default_Handler - .weak I2C2_EV_IRQHandler + .weak I2C2_EV_IRQHandler .thumb_set I2C2_EV_IRQHandler,Default_Handler - .weak I2C2_ER_IRQHandler + .weak I2C2_ER_IRQHandler .thumb_set I2C2_ER_IRQHandler,Default_Handler - .weak SPI1_IRQHandler + .weak SPI1_IRQHandler .thumb_set SPI1_IRQHandler,Default_Handler - .weak SPI2_IRQHandler + .weak SPI2_IRQHandler .thumb_set SPI2_IRQHandler,Default_Handler - .weak USART1_IRQHandler + .weak USART1_IRQHandler .thumb_set USART1_IRQHandler,Default_Handler - .weak USART2_IRQHandler + .weak USART2_IRQHandler .thumb_set USART2_IRQHandler,Default_Handler - .weak USART3_IRQHandler + .weak USART3_IRQHandler .thumb_set USART3_IRQHandler,Default_Handler - .weak EXTI15_10_IRQHandler + .weak EXTI15_10_IRQHandler .thumb_set EXTI15_10_IRQHandler,Default_Handler - .weak RTC_Alarm_IRQHandler + .weak RTC_Alarm_IRQHandler .thumb_set RTC_Alarm_IRQHandler,Default_Handler - .weak USBWakeUp_IRQHandler + .weak USBWakeUp_IRQHandler .thumb_set USBWakeUp_IRQHandler,Default_Handler - .weak TIM8_BRK_IRQHandler + .weak TIM8_BRK_IRQHandler .thumb_set TIM8_BRK_IRQHandler,Default_Handler - .weak TIM8_UP_IRQHandler + .weak TIM8_UP_IRQHandler .thumb_set TIM8_UP_IRQHandler,Default_Handler - .weak TIM8_TRG_COM_IRQHandler + .weak TIM8_TRG_COM_IRQHandler .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler - .weak TIM8_CC_IRQHandler + .weak TIM8_CC_IRQHandler .thumb_set TIM8_CC_IRQHandler,Default_Handler - .weak ADC3_IRQHandler + .weak ADC3_IRQHandler .thumb_set ADC3_IRQHandler,Default_Handler - .weak FMC_IRQHandler + .weak FMC_IRQHandler .thumb_set FMC_IRQHandler,Default_Handler - .weak LPTIM1_IRQHandler + .weak LPTIM1_IRQHandler .thumb_set LPTIM1_IRQHandler,Default_Handler - .weak TIM5_IRQHandler + .weak TIM5_IRQHandler .thumb_set TIM5_IRQHandler,Default_Handler - .weak SPI3_IRQHandler + .weak SPI3_IRQHandler .thumb_set SPI3_IRQHandler,Default_Handler - .weak UART4_IRQHandler + .weak UART4_IRQHandler .thumb_set UART4_IRQHandler,Default_Handler - .weak UART5_IRQHandler + .weak UART5_IRQHandler .thumb_set UART5_IRQHandler,Default_Handler - .weak TIM6_DAC_IRQHandler + .weak TIM6_DAC_IRQHandler .thumb_set TIM6_DAC_IRQHandler,Default_Handler - .weak TIM7_DAC_IRQHandler + .weak TIM7_DAC_IRQHandler .thumb_set TIM7_DAC_IRQHandler,Default_Handler - .weak DMA2_Channel1_IRQHandler + .weak DMA2_Channel1_IRQHandler .thumb_set DMA2_Channel1_IRQHandler,Default_Handler - .weak DMA2_Channel2_IRQHandler + .weak DMA2_Channel2_IRQHandler .thumb_set DMA2_Channel2_IRQHandler,Default_Handler - .weak DMA2_Channel3_IRQHandler + .weak DMA2_Channel3_IRQHandler .thumb_set DMA2_Channel3_IRQHandler,Default_Handler - .weak DMA2_Channel4_IRQHandler + .weak DMA2_Channel4_IRQHandler .thumb_set DMA2_Channel4_IRQHandler,Default_Handler - .weak DMA2_Channel5_IRQHandler + .weak DMA2_Channel5_IRQHandler .thumb_set DMA2_Channel5_IRQHandler,Default_Handler - .weak ADC4_IRQHandler + .weak ADC4_IRQHandler .thumb_set ADC4_IRQHandler,Default_Handler - .weak ADC5_IRQHandler + .weak ADC5_IRQHandler .thumb_set ADC5_IRQHandler,Default_Handler - .weak UCPD1_IRQHandler + .weak UCPD1_IRQHandler .thumb_set UCPD1_IRQHandler,Default_Handler - .weak COMP1_2_3_IRQHandler + .weak COMP1_2_3_IRQHandler .thumb_set COMP1_2_3_IRQHandler,Default_Handler - .weak COMP4_5_6_IRQHandler + .weak COMP4_5_6_IRQHandler .thumb_set COMP4_5_6_IRQHandler,Default_Handler - .weak COMP7_IRQHandler + .weak COMP7_IRQHandler .thumb_set COMP7_IRQHandler,Default_Handler - .weak HRTIM1_Master_IRQHandler + .weak HRTIM1_Master_IRQHandler .thumb_set HRTIM1_Master_IRQHandler,Default_Handler - .weak HRTIM1_TIMA_IRQHandler + .weak HRTIM1_TIMA_IRQHandler .thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler - .weak HRTIM1_TIMB_IRQHandler + .weak HRTIM1_TIMB_IRQHandler .thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler - .weak HRTIM1_TIMC_IRQHandler + .weak HRTIM1_TIMC_IRQHandler .thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler - .weak HRTIM1_TIMD_IRQHandler + .weak HRTIM1_TIMD_IRQHandler .thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler - .weak HRTIM1_TIME_IRQHandler + .weak HRTIM1_TIME_IRQHandler .thumb_set HRTIM1_TIME_IRQHandler,Default_Handler - .weak HRTIM1_FLT_IRQHandler + .weak HRTIM1_FLT_IRQHandler .thumb_set HRTIM1_FLT_IRQHandler,Default_Handler - .weak HRTIM1_TIMF_IRQHandler + .weak HRTIM1_TIMF_IRQHandler .thumb_set HRTIM1_TIMF_IRQHandler,Default_Handler - .weak CRS_IRQHandler + .weak CRS_IRQHandler .thumb_set CRS_IRQHandler,Default_Handler - .weak SAI1_IRQHandler + .weak SAI1_IRQHandler .thumb_set SAI1_IRQHandler,Default_Handler - .weak TIM20_BRK_IRQHandler + .weak TIM20_BRK_IRQHandler .thumb_set TIM20_BRK_IRQHandler,Default_Handler - .weak TIM20_UP_IRQHandler + .weak TIM20_UP_IRQHandler .thumb_set TIM20_UP_IRQHandler,Default_Handler - .weak TIM20_TRG_COM_IRQHandler + .weak TIM20_TRG_COM_IRQHandler .thumb_set TIM20_TRG_COM_IRQHandler,Default_Handler - .weak TIM20_CC_IRQHandler + .weak TIM20_CC_IRQHandler .thumb_set TIM20_CC_IRQHandler,Default_Handler - .weak FPU_IRQHandler + .weak FPU_IRQHandler .thumb_set FPU_IRQHandler,Default_Handler - .weak I2C4_EV_IRQHandler + .weak I2C4_EV_IRQHandler .thumb_set I2C4_EV_IRQHandler,Default_Handler - .weak I2C4_ER_IRQHandler + .weak I2C4_ER_IRQHandler .thumb_set I2C4_ER_IRQHandler,Default_Handler - .weak SPI4_IRQHandler + .weak SPI4_IRQHandler .thumb_set SPI4_IRQHandler,Default_Handler - .weak FDCAN2_IT0_IRQHandler + .weak FDCAN2_IT0_IRQHandler .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler - .weak FDCAN2_IT1_IRQHandler + .weak FDCAN2_IT1_IRQHandler .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler - .weak FDCAN3_IT0_IRQHandler + .weak FDCAN3_IT0_IRQHandler .thumb_set FDCAN3_IT0_IRQHandler,Default_Handler - .weak FDCAN3_IT1_IRQHandler + .weak FDCAN3_IT1_IRQHandler .thumb_set FDCAN3_IT1_IRQHandler,Default_Handler - .weak RNG_IRQHandler + .weak RNG_IRQHandler .thumb_set RNG_IRQHandler,Default_Handler - .weak LPUART1_IRQHandler + .weak LPUART1_IRQHandler .thumb_set LPUART1_IRQHandler,Default_Handler - .weak I2C3_EV_IRQHandler + .weak I2C3_EV_IRQHandler .thumb_set I2C3_EV_IRQHandler,Default_Handler - .weak I2C3_ER_IRQHandler + .weak I2C3_ER_IRQHandler .thumb_set I2C3_ER_IRQHandler,Default_Handler - .weak DMAMUX_OVR_IRQHandler + .weak DMAMUX_OVR_IRQHandler .thumb_set DMAMUX_OVR_IRQHandler,Default_Handler - .weak QUADSPI_IRQHandler + .weak QUADSPI_IRQHandler .thumb_set QUADSPI_IRQHandler,Default_Handler - .weak DMA1_Channel8_IRQHandler + .weak DMA1_Channel8_IRQHandler .thumb_set DMA1_Channel8_IRQHandler,Default_Handler - .weak DMA2_Channel6_IRQHandler + .weak DMA2_Channel6_IRQHandler .thumb_set DMA2_Channel6_IRQHandler,Default_Handler - .weak DMA2_Channel7_IRQHandler + .weak DMA2_Channel7_IRQHandler .thumb_set DMA2_Channel7_IRQHandler,Default_Handler - .weak DMA2_Channel8_IRQHandler + .weak DMA2_Channel8_IRQHandler .thumb_set DMA2_Channel8_IRQHandler,Default_Handler - .weak CORDIC_IRQHandler + .weak CORDIC_IRQHandler .thumb_set CORDIC_IRQHandler,Default_Handler - .weak FMAC_IRQHandler + .weak FMAC_IRQHandler .thumb_set FMAC_IRQHandler,Default_Handler From fc2d7dc5e079adcb1d8ed68a3d2167eacb38b7a0 Mon Sep 17 00:00:00 2001 From: github-actions <41898282+github-actions[bot]@users.noreply.github.com> Date: Sun, 23 Aug 2026 09:56:08 +0000 Subject: [PATCH 05/17] Automatic Clang-Format: Standardized formatting automatically --- Testbench/CUBEMXTESTING/Core/Inc/fdcan.h | 1 - Testbench/CUBEMXTESTING/Core/Inc/gpio.h | 1 - Testbench/CUBEMXTESTING/Core/Inc/main.h | 13 +- .../CUBEMXTESTING/Core/Inc/stm32_assert.h | 49 +- .../Core/Inc/stm32g4xx_hal_conf.h | 215 +++---- Testbench/CUBEMXTESTING/Core/Inc/tim.h | 1 - Testbench/CUBEMXTESTING/Core/Inc/usart.h | 1 - Testbench/CUBEMXTESTING/Core/Src/fdcan.c | 525 +++++++++-------- Testbench/CUBEMXTESTING/Core/Src/gpio.c | 537 +++++++++--------- Testbench/CUBEMXTESTING/Core/Src/main.c | 169 +++--- .../Core/Src/stm32g4xx_hal_msp.c | 24 +- .../CUBEMXTESTING/Core/Src/stm32g4xx_it.c | 211 ++++--- Testbench/CUBEMXTESTING/Core/Src/syscalls.c | 147 +++-- Testbench/CUBEMXTESTING/Core/Src/sysmem.c | 48 +- .../CUBEMXTESTING/Core/Src/system_stm32g4xx.c | 432 +++++++------- Testbench/CUBEMXTESTING/Core/Src/tim.c | 113 ++-- Testbench/CUBEMXTESTING/Core/Src/usart.c | 164 +++--- 17 files changed, 1294 insertions(+), 1357 deletions(-) diff --git a/Testbench/CUBEMXTESTING/Core/Inc/fdcan.h b/Testbench/CUBEMXTESTING/Core/Inc/fdcan.h index 21271cf64..3597c6476 100644 --- a/Testbench/CUBEMXTESTING/Core/Inc/fdcan.h +++ b/Testbench/CUBEMXTESTING/Core/Inc/fdcan.h @@ -55,4 +55,3 @@ void MX_FDCAN3_Init(void); #endif #endif /* __FDCAN_H__ */ - diff --git a/Testbench/CUBEMXTESTING/Core/Inc/gpio.h b/Testbench/CUBEMXTESTING/Core/Inc/gpio.h index 03c2faca5..37dcc0a5c 100644 --- a/Testbench/CUBEMXTESTING/Core/Inc/gpio.h +++ b/Testbench/CUBEMXTESTING/Core/Inc/gpio.h @@ -46,4 +46,3 @@ void MX_GPIO_Init(void); } #endif #endif /*__ GPIO_H__ */ - diff --git a/Testbench/CUBEMXTESTING/Core/Inc/main.h b/Testbench/CUBEMXTESTING/Core/Inc/main.h index 2b50abc31..cbeced83f 100644 --- a/Testbench/CUBEMXTESTING/Core/Inc/main.h +++ b/Testbench/CUBEMXTESTING/Core/Inc/main.h @@ -28,17 +28,16 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" - -#include "stm32g4xx_ll_rcc.h" #include "stm32g4xx_ll_bus.h" -#include "stm32g4xx_ll_crs.h" -#include "stm32g4xx_ll_system.h" -#include "stm32g4xx_ll_exti.h" #include "stm32g4xx_ll_cortex.h" -#include "stm32g4xx_ll_utils.h" -#include "stm32g4xx_ll_pwr.h" +#include "stm32g4xx_ll_crs.h" #include "stm32g4xx_ll_dma.h" +#include "stm32g4xx_ll_exti.h" #include "stm32g4xx_ll_gpio.h" +#include "stm32g4xx_ll_pwr.h" +#include "stm32g4xx_ll_rcc.h" +#include "stm32g4xx_ll_system.h" +#include "stm32g4xx_ll_utils.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ diff --git a/Testbench/CUBEMXTESTING/Core/Inc/stm32_assert.h b/Testbench/CUBEMXTESTING/Core/Inc/stm32_assert.h index 61631c41e..92460620f 100644 --- a/Testbench/CUBEMXTESTING/Core/Inc/stm32_assert.h +++ b/Testbench/CUBEMXTESTING/Core/Inc/stm32_assert.h @@ -1,21 +1,21 @@ /* USER CODE BEGIN Header */ /** - ****************************************************************************** - * @file stm32_assert.h - * @author MCD Application Team - * @brief STM32 assert file. - ****************************************************************************** - * @attention - * - * Copyright (c) 2019 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ + ****************************************************************************** + * @file stm32_assert.h + * @author MCD Application Team + * @brief STM32 assert file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ /* USER CODE END Header */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32_ASSERT_H @@ -29,15 +29,15 @@ extern "C" { /* Exported constants --------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT +#ifdef USE_FULL_ASSERT /** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) /* Exported functions ------------------------------------------------------- */ void assert_failed(uint8_t *file, uint32_t line); @@ -50,4 +50,3 @@ void assert_failed(uint8_t *file, uint32_t line); #endif #endif /* __STM32_ASSERT_H */ - diff --git a/Testbench/CUBEMXTESTING/Core/Inc/stm32g4xx_hal_conf.h b/Testbench/CUBEMXTESTING/Core/Inc/stm32g4xx_hal_conf.h index e4db34d37..d12d585bd 100644 --- a/Testbench/CUBEMXTESTING/Core/Inc/stm32g4xx_hal_conf.h +++ b/Testbench/CUBEMXTESTING/Core/Inc/stm32g4xx_hal_conf.h @@ -23,7 +23,7 @@ #define STM32G4xx_HAL_CONF_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Exported types ------------------------------------------------------------*/ @@ -31,12 +31,12 @@ /* ########################## Module Selection ############################## */ /** - * @brief This is the list of modules to be used in the HAL driver - */ + * @brief This is the list of modules to be used in the HAL driver + */ #define HAL_MODULE_ENABLED - /*#define HAL_ADC_MODULE_ENABLED */ +/*#define HAL_ADC_MODULE_ENABLED */ /*#define HAL_COMP_MODULE_ENABLED */ /*#define HAL_CORDIC_MODULE_ENABLED */ /*#define HAL_CRC_MODULE_ENABLED */ @@ -76,123 +76,124 @@ /* ########################## Register Callbacks selection ############################## */ /** - * @brief This is the list of modules where register callback can be used - */ -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U -#define USE_HAL_COMP_REGISTER_CALLBACKS 0U -#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U -#define USE_HAL_EXTI_REGISTER_CALLBACKS 0U -#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U -#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U -#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U -#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U -#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U -#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U -#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U -#define USE_HAL_UART_REGISTER_CALLBACKS 0U -#define USE_HAL_USART_REGISTER_CALLBACKS 0U -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U + * @brief This is the list of modules where register callback can be used + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U +#define USE_HAL_COMP_REGISTER_CALLBACKS 0U +#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U +#define USE_HAL_EXTI_REGISTER_CALLBACKS 0U +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U +#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U +#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U +#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U +#define USE_HAL_UART_REGISTER_CALLBACKS 0U +#define USE_HAL_USART_REGISTER_CALLBACKS 0U +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* ########################## Oscillator Values adaptation ####################*/ /** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE (16000000UL) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined(HSE_VALUE) +#define HSE_VALUE (16000000UL) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined(HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ /** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined(HSI_VALUE) +#define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ /** - * @brief Internal High Speed oscillator (HSI48) value for USB FS and RNG. - * This internal oscillator is mainly dedicated to provide a high precision clock to - * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. - * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency - * which is subject to manufacturing process variations. - */ -#if !defined (HSI48_VALUE) - #define HSI48_VALUE (48000000UL) /*!< Value of the Internal High Speed oscillator for USB FS/RNG in Hz. - The real value my vary depending on manufacturing process variations.*/ -#endif /* HSI48_VALUE */ + * @brief Internal High Speed oscillator (HSI48) value for USB FS and RNG. + * This internal oscillator is mainly dedicated to provide a high precision clock to + * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. + * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency + * which is subject to manufacturing process variations. + */ +#if !defined(HSI48_VALUE) +#define HSI48_VALUE \ + (48000000UL) /*!< Value of the Internal High Speed oscillator for USB FS/RNG in Hz. \ + The real value my vary depending on manufacturing process variations.*/ +#endif /* HSI48_VALUE */ /** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined(LSI_VALUE) /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature.*/ -#define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/ -#endif /* LSI_VALUE */ +#define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /** - * @brief External Low Speed oscillator (LSE) value. - * This value is used by the UART, RTC HAL module to compute the system frequency - */ -#if !defined (LSE_VALUE) -#define LSE_VALUE (32768UL) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined(LSE_VALUE) +#define LSE_VALUE (32768UL) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ -#if !defined (LSE_STARTUP_TIMEOUT) -#define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ +#if !defined(LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ /** - * @brief External clock source for I2S and SAI peripherals - * This value is used by the I2S and SAI HAL modules to compute the I2S and SAI clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined (EXTERNAL_CLOCK_VALUE) -#define EXTERNAL_CLOCK_VALUE (12288000UL) /*!< Value of the External oscillator in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ + * @brief External clock source for I2S and SAI peripherals + * This value is used by the I2S and SAI HAL modules to compute the I2S and SAI clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined(EXTERNAL_CLOCK_VALUE) +#define EXTERNAL_CLOCK_VALUE (12288000UL) /*!< Value of the External oscillator in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ /* Tip: To avoid modifying this file each time you need to use different HSE, === you can define the HSE value in your toolchain compiler preprocessor. */ /* ########################### System Configuration ######################### */ /** - * @brief This is the HAL system configuration section - */ + * @brief This is the HAL system configuration section + */ -#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority (lowest by default) */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 0U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U +#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority (lowest by default) */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 0U +#define INSTRUCTION_CACHE_ENABLE 1U +#define DATA_CACHE_ENABLE 1U /* ########################## Assert Selection ############################## */ /** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ - #define USE_FULL_ASSERT 1U + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +#define USE_FULL_ASSERT 1U /* ################## SPI peripheral configuration ########################## */ @@ -201,12 +202,12 @@ The real value may vary depending on the variations in voltage and temperature.* * Deactivated: CRC code cleaned from driver */ -#define USE_SPI_CRC 0U +#define USE_SPI_CRC 0U /* Includes ------------------------------------------------------------------*/ /** - * @brief Include module's header file - */ + * @brief Include module's header file + */ #ifdef HAL_RCC_MODULE_ENABLED #include "stm32g4xx_hal_rcc.h" @@ -357,15 +358,15 @@ The real value may vary depending on the variations in voltage and temperature.* #endif /* HAL_WWDG_MODULE_ENABLED */ /* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT +#ifdef USE_FULL_ASSERT /** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) /* Exported functions ------------------------------------------------------- */ void assert_failed(uint8_t *file, uint32_t line); diff --git a/Testbench/CUBEMXTESTING/Core/Inc/tim.h b/Testbench/CUBEMXTESTING/Core/Inc/tim.h index b90657cf4..2d20bd560 100644 --- a/Testbench/CUBEMXTESTING/Core/Inc/tim.h +++ b/Testbench/CUBEMXTESTING/Core/Inc/tim.h @@ -49,4 +49,3 @@ void MX_TIM5_Init(void); #endif #endif /* __TIM_H__ */ - diff --git a/Testbench/CUBEMXTESTING/Core/Inc/usart.h b/Testbench/CUBEMXTESTING/Core/Inc/usart.h index 49dd0cccc..bdec0c9cb 100644 --- a/Testbench/CUBEMXTESTING/Core/Inc/usart.h +++ b/Testbench/CUBEMXTESTING/Core/Inc/usart.h @@ -49,4 +49,3 @@ void MX_LPUART1_UART_Init(void); #endif #endif /* __USART_H__ */ - diff --git a/Testbench/CUBEMXTESTING/Core/Src/fdcan.c b/Testbench/CUBEMXTESTING/Core/Src/fdcan.c index 08b2a1b8a..30b3c9dc1 100644 --- a/Testbench/CUBEMXTESTING/Core/Src/fdcan.c +++ b/Testbench/CUBEMXTESTING/Core/Src/fdcan.c @@ -32,298 +32,281 @@ FDCAN_HandleTypeDef hfdcan3; void MX_FDCAN1_Init(void) { - /* USER CODE BEGIN FDCAN1_Init 0 */ - - /* USER CODE END FDCAN1_Init 0 */ - - /* USER CODE BEGIN FDCAN1_Init 1 */ - - /* USER CODE END FDCAN1_Init 1 */ - hfdcan1.Instance = FDCAN1; - hfdcan1.Init.ClockDivider = FDCAN_CLOCK_DIV1; - hfdcan1.Init.FrameFormat = FDCAN_FRAME_CLASSIC; - hfdcan1.Init.Mode = FDCAN_MODE_INTERNAL_LOOPBACK; - hfdcan1.Init.AutoRetransmission = ENABLE; - hfdcan1.Init.TransmitPause = DISABLE; - hfdcan1.Init.ProtocolException = ENABLE; - hfdcan1.Init.NominalPrescaler = 1; - hfdcan1.Init.NominalSyncJumpWidth = 16; - hfdcan1.Init.NominalTimeSeg1 = 119; - hfdcan1.Init.NominalTimeSeg2 = 40; - hfdcan1.Init.DataPrescaler = 8; - hfdcan1.Init.DataSyncJumpWidth = 16; - hfdcan1.Init.DataTimeSeg1 = 14; - hfdcan1.Init.DataTimeSeg2 = 5; - hfdcan1.Init.StdFiltersNbr = 0; - hfdcan1.Init.ExtFiltersNbr = 2; - hfdcan1.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; - if (HAL_FDCAN_Init(&hfdcan1) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN FDCAN1_Init 2 */ - - /* USER CODE END FDCAN1_Init 2 */ - + /* USER CODE BEGIN FDCAN1_Init 0 */ + + /* USER CODE END FDCAN1_Init 0 */ + + /* USER CODE BEGIN FDCAN1_Init 1 */ + + /* USER CODE END FDCAN1_Init 1 */ + hfdcan1.Instance = FDCAN1; + hfdcan1.Init.ClockDivider = FDCAN_CLOCK_DIV1; + hfdcan1.Init.FrameFormat = FDCAN_FRAME_CLASSIC; + hfdcan1.Init.Mode = FDCAN_MODE_INTERNAL_LOOPBACK; + hfdcan1.Init.AutoRetransmission = ENABLE; + hfdcan1.Init.TransmitPause = DISABLE; + hfdcan1.Init.ProtocolException = ENABLE; + hfdcan1.Init.NominalPrescaler = 1; + hfdcan1.Init.NominalSyncJumpWidth = 16; + hfdcan1.Init.NominalTimeSeg1 = 119; + hfdcan1.Init.NominalTimeSeg2 = 40; + hfdcan1.Init.DataPrescaler = 8; + hfdcan1.Init.DataSyncJumpWidth = 16; + hfdcan1.Init.DataTimeSeg1 = 14; + hfdcan1.Init.DataTimeSeg2 = 5; + hfdcan1.Init.StdFiltersNbr = 0; + hfdcan1.Init.ExtFiltersNbr = 2; + hfdcan1.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; + if (HAL_FDCAN_Init(&hfdcan1) != HAL_OK) { + Error_Handler(); + } + /* USER CODE BEGIN FDCAN1_Init 2 */ + + /* USER CODE END FDCAN1_Init 2 */ } /* FDCAN2 init function */ void MX_FDCAN2_Init(void) { - /* USER CODE BEGIN FDCAN2_Init 0 */ - - /* USER CODE END FDCAN2_Init 0 */ - - /* USER CODE BEGIN FDCAN2_Init 1 */ - - /* USER CODE END FDCAN2_Init 1 */ - hfdcan2.Instance = FDCAN2; - hfdcan2.Init.ClockDivider = FDCAN_CLOCK_DIV1; - hfdcan2.Init.FrameFormat = FDCAN_FRAME_CLASSIC; - hfdcan2.Init.Mode = FDCAN_MODE_INTERNAL_LOOPBACK; - hfdcan2.Init.AutoRetransmission = ENABLE; - hfdcan2.Init.TransmitPause = DISABLE; - hfdcan2.Init.ProtocolException = ENABLE; - hfdcan2.Init.NominalPrescaler = 1; - hfdcan2.Init.NominalSyncJumpWidth = 16; - hfdcan2.Init.NominalTimeSeg1 = 119; - hfdcan2.Init.NominalTimeSeg2 = 40; - hfdcan2.Init.DataPrescaler = 8; - hfdcan2.Init.DataSyncJumpWidth = 16; - hfdcan2.Init.DataTimeSeg1 = 14; - hfdcan2.Init.DataTimeSeg2 = 5; - hfdcan2.Init.StdFiltersNbr = 0; - hfdcan2.Init.ExtFiltersNbr = 2; - hfdcan2.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; - if (HAL_FDCAN_Init(&hfdcan2) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN FDCAN2_Init 2 */ - - /* USER CODE END FDCAN2_Init 2 */ - + /* USER CODE BEGIN FDCAN2_Init 0 */ + + /* USER CODE END FDCAN2_Init 0 */ + + /* USER CODE BEGIN FDCAN2_Init 1 */ + + /* USER CODE END FDCAN2_Init 1 */ + hfdcan2.Instance = FDCAN2; + hfdcan2.Init.ClockDivider = FDCAN_CLOCK_DIV1; + hfdcan2.Init.FrameFormat = FDCAN_FRAME_CLASSIC; + hfdcan2.Init.Mode = FDCAN_MODE_INTERNAL_LOOPBACK; + hfdcan2.Init.AutoRetransmission = ENABLE; + hfdcan2.Init.TransmitPause = DISABLE; + hfdcan2.Init.ProtocolException = ENABLE; + hfdcan2.Init.NominalPrescaler = 1; + hfdcan2.Init.NominalSyncJumpWidth = 16; + hfdcan2.Init.NominalTimeSeg1 = 119; + hfdcan2.Init.NominalTimeSeg2 = 40; + hfdcan2.Init.DataPrescaler = 8; + hfdcan2.Init.DataSyncJumpWidth = 16; + hfdcan2.Init.DataTimeSeg1 = 14; + hfdcan2.Init.DataTimeSeg2 = 5; + hfdcan2.Init.StdFiltersNbr = 0; + hfdcan2.Init.ExtFiltersNbr = 2; + hfdcan2.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; + if (HAL_FDCAN_Init(&hfdcan2) != HAL_OK) { + Error_Handler(); + } + /* USER CODE BEGIN FDCAN2_Init 2 */ + + /* USER CODE END FDCAN2_Init 2 */ } /* FDCAN3 init function */ void MX_FDCAN3_Init(void) { - /* USER CODE BEGIN FDCAN3_Init 0 */ - - /* USER CODE END FDCAN3_Init 0 */ - - /* USER CODE BEGIN FDCAN3_Init 1 */ - - /* USER CODE END FDCAN3_Init 1 */ - hfdcan3.Instance = FDCAN3; - hfdcan3.Init.ClockDivider = FDCAN_CLOCK_DIV1; - hfdcan3.Init.FrameFormat = FDCAN_FRAME_CLASSIC; - hfdcan3.Init.Mode = FDCAN_MODE_INTERNAL_LOOPBACK; - hfdcan3.Init.AutoRetransmission = DISABLE; - hfdcan3.Init.TransmitPause = DISABLE; - hfdcan3.Init.ProtocolException = DISABLE; - hfdcan3.Init.NominalPrescaler = 16; - hfdcan3.Init.NominalSyncJumpWidth = 1; - hfdcan3.Init.NominalTimeSeg1 = 1; - hfdcan3.Init.NominalTimeSeg2 = 1; - hfdcan3.Init.DataPrescaler = 1; - hfdcan3.Init.DataSyncJumpWidth = 1; - hfdcan3.Init.DataTimeSeg1 = 1; - hfdcan3.Init.DataTimeSeg2 = 1; - hfdcan3.Init.StdFiltersNbr = 0; - hfdcan3.Init.ExtFiltersNbr = 0; - hfdcan3.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; - if (HAL_FDCAN_Init(&hfdcan3) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN FDCAN3_Init 2 */ - - /* USER CODE END FDCAN3_Init 2 */ - + /* USER CODE BEGIN FDCAN3_Init 0 */ + + /* USER CODE END FDCAN3_Init 0 */ + + /* USER CODE BEGIN FDCAN3_Init 1 */ + + /* USER CODE END FDCAN3_Init 1 */ + hfdcan3.Instance = FDCAN3; + hfdcan3.Init.ClockDivider = FDCAN_CLOCK_DIV1; + hfdcan3.Init.FrameFormat = FDCAN_FRAME_CLASSIC; + hfdcan3.Init.Mode = FDCAN_MODE_INTERNAL_LOOPBACK; + hfdcan3.Init.AutoRetransmission = DISABLE; + hfdcan3.Init.TransmitPause = DISABLE; + hfdcan3.Init.ProtocolException = DISABLE; + hfdcan3.Init.NominalPrescaler = 16; + hfdcan3.Init.NominalSyncJumpWidth = 1; + hfdcan3.Init.NominalTimeSeg1 = 1; + hfdcan3.Init.NominalTimeSeg2 = 1; + hfdcan3.Init.DataPrescaler = 1; + hfdcan3.Init.DataSyncJumpWidth = 1; + hfdcan3.Init.DataTimeSeg1 = 1; + hfdcan3.Init.DataTimeSeg2 = 1; + hfdcan3.Init.StdFiltersNbr = 0; + hfdcan3.Init.ExtFiltersNbr = 0; + hfdcan3.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; + if (HAL_FDCAN_Init(&hfdcan3) != HAL_OK) { + Error_Handler(); + } + /* USER CODE BEGIN FDCAN3_Init 2 */ + + /* USER CODE END FDCAN3_Init 2 */ } -static uint32_t HAL_RCC_FDCAN_CLK_ENABLED=0; +static uint32_t HAL_RCC_FDCAN_CLK_ENABLED = 0; -void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* fdcanHandle) +void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *fdcanHandle) { - GPIO_InitTypeDef GPIO_InitStruct = {0}; - if(fdcanHandle->Instance==FDCAN1) - { - /* USER CODE BEGIN FDCAN1_MspInit 0 */ - - /* USER CODE END FDCAN1_MspInit 0 */ - LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_PCLK1); - - /* FDCAN1 clock enable */ - HAL_RCC_FDCAN_CLK_ENABLED++; - if(HAL_RCC_FDCAN_CLK_ENABLED==1){ - __HAL_RCC_FDCAN_CLK_ENABLE(); - } - - __HAL_RCC_GPIOB_CLK_ENABLE(); - /**FDCAN1 GPIO Configuration - PB8-BOOT0 ------> FDCAN1_RX - PB9 ------> FDCAN1_TX - */ - GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN1; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /* FDCAN1 interrupt Init */ - HAL_NVIC_SetPriority(FDCAN1_IT0_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(FDCAN1_IT0_IRQn); - /* USER CODE BEGIN FDCAN1_MspInit 1 */ - - /* USER CODE END FDCAN1_MspInit 1 */ - } - else if(fdcanHandle->Instance==FDCAN2) - { - /* USER CODE BEGIN FDCAN2_MspInit 0 */ - - /* USER CODE END FDCAN2_MspInit 0 */ - - LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_PCLK1); - - /* FDCAN2 clock enable */ - HAL_RCC_FDCAN_CLK_ENABLED++; - if(HAL_RCC_FDCAN_CLK_ENABLED==1){ - __HAL_RCC_FDCAN_CLK_ENABLE(); - } - - __HAL_RCC_GPIOB_CLK_ENABLE(); - /**FDCAN2 GPIO Configuration - PB12 ------> FDCAN2_RX - PB13 ------> FDCAN2_TX - */ - GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_13; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN2; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /* FDCAN2 interrupt Init */ - HAL_NVIC_SetPriority(FDCAN2_IT0_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(FDCAN2_IT0_IRQn); - /* USER CODE BEGIN FDCAN2_MspInit 1 */ - - /* USER CODE END FDCAN2_MspInit 1 */ - } - else if(fdcanHandle->Instance==FDCAN3) - { - /* USER CODE BEGIN FDCAN3_MspInit 0 */ - - /* USER CODE END FDCAN3_MspInit 0 */ - - LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_PCLK1); - - /* FDCAN3 clock enable */ - HAL_RCC_FDCAN_CLK_ENABLED++; - if(HAL_RCC_FDCAN_CLK_ENABLED==1){ - __HAL_RCC_FDCAN_CLK_ENABLE(); - } - - __HAL_RCC_GPIOA_CLK_ENABLE(); - /**FDCAN3 GPIO Configuration - PA8 ------> FDCAN3_RX - PA15 ------> FDCAN3_TX - */ - GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_15; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF11_FDCAN3; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /* FDCAN3 interrupt Init */ - HAL_NVIC_SetPriority(FDCAN3_IT0_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(FDCAN3_IT0_IRQn); - /* USER CODE BEGIN FDCAN3_MspInit 1 */ - - /* USER CODE END FDCAN3_MspInit 1 */ - } + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if (fdcanHandle->Instance == FDCAN1) { + /* USER CODE BEGIN FDCAN1_MspInit 0 */ + + /* USER CODE END FDCAN1_MspInit 0 */ + LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_PCLK1); + + /* FDCAN1 clock enable */ + HAL_RCC_FDCAN_CLK_ENABLED++; + if (HAL_RCC_FDCAN_CLK_ENABLED == 1) { + __HAL_RCC_FDCAN_CLK_ENABLE(); + } + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**FDCAN1 GPIO Configuration + PB8-BOOT0 ------> FDCAN1_RX + PB9 ------> FDCAN1_TX + */ + GPIO_InitStruct.Pin = GPIO_PIN_8 | GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN1; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* FDCAN1 interrupt Init */ + HAL_NVIC_SetPriority(FDCAN1_IT0_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(FDCAN1_IT0_IRQn); + /* USER CODE BEGIN FDCAN1_MspInit 1 */ + + /* USER CODE END FDCAN1_MspInit 1 */ + } else if (fdcanHandle->Instance == FDCAN2) { + /* USER CODE BEGIN FDCAN2_MspInit 0 */ + + /* USER CODE END FDCAN2_MspInit 0 */ + + LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_PCLK1); + + /* FDCAN2 clock enable */ + HAL_RCC_FDCAN_CLK_ENABLED++; + if (HAL_RCC_FDCAN_CLK_ENABLED == 1) { + __HAL_RCC_FDCAN_CLK_ENABLE(); + } + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**FDCAN2 GPIO Configuration + PB12 ------> FDCAN2_RX + PB13 ------> FDCAN2_TX + */ + GPIO_InitStruct.Pin = GPIO_PIN_12 | GPIO_PIN_13; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN2; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* FDCAN2 interrupt Init */ + HAL_NVIC_SetPriority(FDCAN2_IT0_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(FDCAN2_IT0_IRQn); + /* USER CODE BEGIN FDCAN2_MspInit 1 */ + + /* USER CODE END FDCAN2_MspInit 1 */ + } else if (fdcanHandle->Instance == FDCAN3) { + /* USER CODE BEGIN FDCAN3_MspInit 0 */ + + /* USER CODE END FDCAN3_MspInit 0 */ + + LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_PCLK1); + + /* FDCAN3 clock enable */ + HAL_RCC_FDCAN_CLK_ENABLED++; + if (HAL_RCC_FDCAN_CLK_ENABLED == 1) { + __HAL_RCC_FDCAN_CLK_ENABLE(); + } + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**FDCAN3 GPIO Configuration + PA8 ------> FDCAN3_RX + PA15 ------> FDCAN3_TX + */ + GPIO_InitStruct.Pin = GPIO_PIN_8 | GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF11_FDCAN3; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* FDCAN3 interrupt Init */ + HAL_NVIC_SetPriority(FDCAN3_IT0_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(FDCAN3_IT0_IRQn); + /* USER CODE BEGIN FDCAN3_MspInit 1 */ + + /* USER CODE END FDCAN3_MspInit 1 */ + } } -void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef* fdcanHandle) +void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *fdcanHandle) { - if(fdcanHandle->Instance==FDCAN1) - { - /* USER CODE BEGIN FDCAN1_MspDeInit 0 */ - - /* USER CODE END FDCAN1_MspDeInit 0 */ - /* Peripheral clock disable */ - HAL_RCC_FDCAN_CLK_ENABLED--; - if(HAL_RCC_FDCAN_CLK_ENABLED==0){ - __HAL_RCC_FDCAN_CLK_DISABLE(); - } - - /**FDCAN1 GPIO Configuration - PB8-BOOT0 ------> FDCAN1_RX - PB9 ------> FDCAN1_TX - */ - HAL_GPIO_DeInit(GPIOB, GPIO_PIN_8|GPIO_PIN_9); - - /* FDCAN1 interrupt Deinit */ - HAL_NVIC_DisableIRQ(FDCAN1_IT0_IRQn); - /* USER CODE BEGIN FDCAN1_MspDeInit 1 */ - - /* USER CODE END FDCAN1_MspDeInit 1 */ - } - else if(fdcanHandle->Instance==FDCAN2) - { - /* USER CODE BEGIN FDCAN2_MspDeInit 0 */ - - /* USER CODE END FDCAN2_MspDeInit 0 */ - /* Peripheral clock disable */ - HAL_RCC_FDCAN_CLK_ENABLED--; - if(HAL_RCC_FDCAN_CLK_ENABLED==0){ - __HAL_RCC_FDCAN_CLK_DISABLE(); - } - - /**FDCAN2 GPIO Configuration - PB12 ------> FDCAN2_RX - PB13 ------> FDCAN2_TX - */ - HAL_GPIO_DeInit(GPIOB, GPIO_PIN_12|GPIO_PIN_13); - - /* FDCAN2 interrupt Deinit */ - HAL_NVIC_DisableIRQ(FDCAN2_IT0_IRQn); - /* USER CODE BEGIN FDCAN2_MspDeInit 1 */ - - /* USER CODE END FDCAN2_MspDeInit 1 */ - } - else if(fdcanHandle->Instance==FDCAN3) - { - /* USER CODE BEGIN FDCAN3_MspDeInit 0 */ - - /* USER CODE END FDCAN3_MspDeInit 0 */ - /* Peripheral clock disable */ - HAL_RCC_FDCAN_CLK_ENABLED--; - if(HAL_RCC_FDCAN_CLK_ENABLED==0){ - __HAL_RCC_FDCAN_CLK_DISABLE(); - } - - /**FDCAN3 GPIO Configuration - PA8 ------> FDCAN3_RX - PA15 ------> FDCAN3_TX - */ - HAL_GPIO_DeInit(GPIOA, GPIO_PIN_8|GPIO_PIN_15); - - /* FDCAN3 interrupt Deinit */ - HAL_NVIC_DisableIRQ(FDCAN3_IT0_IRQn); - /* USER CODE BEGIN FDCAN3_MspDeInit 1 */ - - /* USER CODE END FDCAN3_MspDeInit 1 */ - } + if (fdcanHandle->Instance == FDCAN1) { + /* USER CODE BEGIN FDCAN1_MspDeInit 0 */ + + /* USER CODE END FDCAN1_MspDeInit 0 */ + /* Peripheral clock disable */ + HAL_RCC_FDCAN_CLK_ENABLED--; + if (HAL_RCC_FDCAN_CLK_ENABLED == 0) { + __HAL_RCC_FDCAN_CLK_DISABLE(); + } + + /**FDCAN1 GPIO Configuration + PB8-BOOT0 ------> FDCAN1_RX + PB9 ------> FDCAN1_TX + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_8 | GPIO_PIN_9); + + /* FDCAN1 interrupt Deinit */ + HAL_NVIC_DisableIRQ(FDCAN1_IT0_IRQn); + /* USER CODE BEGIN FDCAN1_MspDeInit 1 */ + + /* USER CODE END FDCAN1_MspDeInit 1 */ + } else if (fdcanHandle->Instance == FDCAN2) { + /* USER CODE BEGIN FDCAN2_MspDeInit 0 */ + + /* USER CODE END FDCAN2_MspDeInit 0 */ + /* Peripheral clock disable */ + HAL_RCC_FDCAN_CLK_ENABLED--; + if (HAL_RCC_FDCAN_CLK_ENABLED == 0) { + __HAL_RCC_FDCAN_CLK_DISABLE(); + } + + /**FDCAN2 GPIO Configuration + PB12 ------> FDCAN2_RX + PB13 ------> FDCAN2_TX + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_12 | GPIO_PIN_13); + + /* FDCAN2 interrupt Deinit */ + HAL_NVIC_DisableIRQ(FDCAN2_IT0_IRQn); + /* USER CODE BEGIN FDCAN2_MspDeInit 1 */ + + /* USER CODE END FDCAN2_MspDeInit 1 */ + } else if (fdcanHandle->Instance == FDCAN3) { + /* USER CODE BEGIN FDCAN3_MspDeInit 0 */ + + /* USER CODE END FDCAN3_MspDeInit 0 */ + /* Peripheral clock disable */ + HAL_RCC_FDCAN_CLK_ENABLED--; + if (HAL_RCC_FDCAN_CLK_ENABLED == 0) { + __HAL_RCC_FDCAN_CLK_DISABLE(); + } + + /**FDCAN3 GPIO Configuration + PA8 ------> FDCAN3_RX + PA15 ------> FDCAN3_TX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_8 | GPIO_PIN_15); + + /* FDCAN3 interrupt Deinit */ + HAL_NVIC_DisableIRQ(FDCAN3_IT0_IRQn); + /* USER CODE BEGIN FDCAN3_MspDeInit 1 */ + + /* USER CODE END FDCAN3_MspDeInit 1 */ + } } /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ - diff --git a/Testbench/CUBEMXTESTING/Core/Src/gpio.c b/Testbench/CUBEMXTESTING/Core/Src/gpio.c index 96b5c07ab..4d07c7993 100644 --- a/Testbench/CUBEMXTESTING/Core/Src/gpio.c +++ b/Testbench/CUBEMXTESTING/Core/Src/gpio.c @@ -33,278 +33,277 @@ /* USER CODE END 1 */ /** Configure pins as - * Analog - * Input - * Output - * EVENT_OUT - * EXTI - * Free pins are configured automatically as Analog (this feature is enabled through - * the Code Generation settings) -*/ + * Analog + * Input + * Output + * EVENT_OUT + * EXTI + * Free pins are configured automatically as Analog (this feature is enabled through + * the Code Generation settings) + */ void MX_GPIO_Init(void) { - LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; - - /* GPIO Ports Clock Enable */ - LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOC); - LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOF); - LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOG); - LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA); - LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB); - LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOD); - - /**/ - LL_GPIO_ResetOutputPin(USER_LED_GPIO_Port, USER_LED_Pin); - - /**/ - GPIO_InitStruct.Pin = USER_BUTTON_Pin; - GPIO_InitStruct.Mode = LL_GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(USER_BUTTON_GPIO_Port, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_14; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_15; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_0; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOF, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_1; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOF, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_10; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOG, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_0; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_1; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_2; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_3; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_0; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_1; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_4; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = USER_LED_Pin; - GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT; - GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(USER_LED_GPIO_Port, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_6; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_7; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_4; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_5; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_0; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_1; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_2; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_10; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_11; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_14; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_15; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_6; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_7; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_8; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_9; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_9; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_10; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_11; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_12; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_10; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_11; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_12; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_2; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOD, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_4; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_5; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_6; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_7; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - + LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* GPIO Ports Clock Enable */ + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOC); + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOF); + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOG); + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA); + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB); + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOD); + + /**/ + LL_GPIO_ResetOutputPin(USER_LED_GPIO_Port, USER_LED_Pin); + + /**/ + GPIO_InitStruct.Pin = USER_BUTTON_Pin; + GPIO_InitStruct.Mode = LL_GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(USER_BUTTON_GPIO_Port, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_14; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_15; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_0; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_1; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_10; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_0; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_1; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_2; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_3; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_0; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_1; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_4; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = USER_LED_Pin; + GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(USER_LED_GPIO_Port, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_6; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_7; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_4; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_5; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_0; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_1; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_2; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_10; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_11; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_14; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_15; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_6; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_7; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_8; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_9; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_9; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_10; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_11; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_12; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_10; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_11; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_12; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_2; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_4; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_5; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_6; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_7; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); } /* USER CODE BEGIN 2 */ diff --git a/Testbench/CUBEMXTESTING/Core/Src/main.c b/Testbench/CUBEMXTESTING/Core/Src/main.c index d201e4a35..7344dd05d 100644 --- a/Testbench/CUBEMXTESTING/Core/Src/main.c +++ b/Testbench/CUBEMXTESTING/Core/Src/main.c @@ -18,10 +18,11 @@ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "main.h" + #include "fdcan.h" -#include "usart.h" -#include "tim.h" #include "gpio.h" +#include "tim.h" +#include "usart.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ @@ -72,40 +73,40 @@ void SystemClock_Config(void); /* USER CODE END 0 */ /** - * @brief The application entry point. - * @retval int - */ + * @brief The application entry point. + * @retval int + */ int main(void) { - /* USER CODE BEGIN 1 */ + /* USER CODE BEGIN 1 */ - /* USER CODE END 1 */ + /* USER CODE END 1 */ - /* MCU Configuration--------------------------------------------------------*/ + /* MCU Configuration--------------------------------------------------------*/ - /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ - HAL_Init(); + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); - /* USER CODE BEGIN Init */ + /* USER CODE BEGIN Init */ - /* USER CODE END Init */ + /* USER CODE END Init */ - /* Configure the system clock */ - SystemClock_Config(); + /* Configure the system clock */ + SystemClock_Config(); - /* USER CODE BEGIN SysInit */ + /* USER CODE BEGIN SysInit */ Logomatic_SetLogLevel(LogLevel_Debug); - /* USER CODE END SysInit */ - - /* Initialize all configured peripherals */ - MX_GPIO_Init(); - MX_FDCAN1_Init(); - MX_FDCAN2_Init(); - MX_TIM5_Init(); - MX_FDCAN3_Init(); - MX_LPUART1_UART_Init(); - /* USER CODE BEGIN 2 */ + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_FDCAN1_Init(); + MX_FDCAN2_Init(); + MX_TIM5_Init(); + MX_FDCAN3_Init(); + MX_LPUART1_UART_Init(); + /* USER CODE BEGIN 2 */ CubeCAN_Config primaryCanConfig = {.rx_callback = CANdler_Callback, .context.busid_user_context = GRCAN_BUS_PRIMARY, .sending_node_id = GRCAN_Debugger}; CubeCAN_Config dataCanConfig = {.rx_callback = CANdler_Callback, .context.busid_user_context = GRCAN_BUS_DATA, .sending_node_id = GRCAN_Debugger}; CubeCAN_Config chargerCanConfig = {.rx_callback = CANdler_Callback, .context.busid_user_context = GRCAN_BUS_CHARGER, .sending_node_id = GRCAN_Debugger}; @@ -132,67 +133,59 @@ int main(void) CubeVCP_Setup(&hlpuart1); CubeVCP_EnableRx(CANdler_VCP_Callback); CubeVCP_SendString("Hello World!\n", sizeof("Hello World!\n") - 1); - /* USER CODE END 2 */ + /* USER CODE END 2 */ - /* Infinite loop */ - /* USER CODE BEGIN WHILE */ + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ while (1) { - /* USER CODE END WHILE */ + /* USER CODE END WHILE */ - /* USER CODE BEGIN 3 */ + /* USER CODE BEGIN 3 */ MainLoop(); HAL_Delay(100); } - /* USER CODE END 3 */ + /* USER CODE END 3 */ } /** - * @brief System Clock Configuration - * @retval None - */ + * @brief System Clock Configuration + * @retval None + */ void SystemClock_Config(void) { - LL_FLASH_SetLatency(LL_FLASH_LATENCY_4); - while(LL_FLASH_GetLatency() != LL_FLASH_LATENCY_4) - { - } - LL_PWR_EnableRange1BoostMode(); - LL_RCC_HSI_Enable(); - /* Wait till HSI is ready */ - while(LL_RCC_HSI_IsReady() != 1) - { - } - - LL_RCC_HSI_SetCalibTrimming(64); - LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, LL_RCC_PLLM_DIV_1, 20, LL_RCC_PLLR_DIV_2); - LL_RCC_PLL_EnableDomain_SYS(); - LL_RCC_PLL_Enable(); - /* Wait till PLL is ready */ - while(LL_RCC_PLL_IsReady() != 1) - { - } - - LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); - LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_2); - /* Wait till System clock is ready */ - while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) - { - } - - /* Insure 1us transition state at intermediate medium speed clock*/ - for (__IO uint32_t i = (170 >> 1); i !=0; i--); - - /* Set AHB prescaler*/ - LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1); - LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1); - LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1); - LL_SetSystemCoreClock(160000000); - - /* Update the time base */ - if (HAL_InitTick (TICK_INT_PRIORITY) != HAL_OK) - { - Error_Handler(); - } + LL_FLASH_SetLatency(LL_FLASH_LATENCY_4); + while (LL_FLASH_GetLatency() != LL_FLASH_LATENCY_4) {} + LL_PWR_EnableRange1BoostMode(); + LL_RCC_HSI_Enable(); + /* Wait till HSI is ready */ + while (LL_RCC_HSI_IsReady() != 1) {} + + LL_RCC_HSI_SetCalibTrimming(64); + LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, LL_RCC_PLLM_DIV_1, 20, LL_RCC_PLLR_DIV_2); + LL_RCC_PLL_EnableDomain_SYS(); + LL_RCC_PLL_Enable(); + /* Wait till PLL is ready */ + while (LL_RCC_PLL_IsReady() != 1) {} + + LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); + LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_2); + /* Wait till System clock is ready */ + while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) {} + + /* Insure 1us transition state at intermediate medium speed clock*/ + for (__IO uint32_t i = (170 >> 1); i != 0; i--) + ; + + /* Set AHB prescaler*/ + LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1); + LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1); + LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1); + LL_SetSystemCoreClock(160000000); + + /* Update the time base */ + if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) { + Error_Handler(); + } } /* USER CODE BEGIN 4 */ @@ -211,29 +204,29 @@ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) /* USER CODE END 4 */ /** - * @brief This function is executed in case of error occurrence. - * @retval None - */ + * @brief This function is executed in case of error occurrence. + * @retval None + */ void Error_Handler(void) { - /* USER CODE BEGIN Error_Handler_Debug */ + /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) {} - /* USER CODE END Error_Handler_Debug */ + /* USER CODE END Error_Handler_Debug */ } #ifdef USE_FULL_ASSERT /** - * @brief Reports the name of the source file and the source line number - * where the assert_param error has occurred. - * @param file: pointer to the source file name - * @param line: assert_param error line source number - * @retval None - */ + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ void assert_failed(uint8_t *file, uint32_t line) { - /* USER CODE BEGIN 6 */ + /* USER CODE BEGIN 6 */ LOGOMATIC_CRITICAL("Assert failed! File %s on line %" PRIu32 "\n", file, line); - /* USER CODE END 6 */ + /* USER CODE END 6 */ } #endif /* USE_FULL_ASSERT */ diff --git a/Testbench/CUBEMXTESTING/Core/Src/stm32g4xx_hal_msp.c b/Testbench/CUBEMXTESTING/Core/Src/stm32g4xx_hal_msp.c index 2cc7d8296..4668755ab 100644 --- a/Testbench/CUBEMXTESTING/Core/Src/stm32g4xx_hal_msp.c +++ b/Testbench/CUBEMXTESTING/Core/Src/stm32g4xx_hal_msp.c @@ -57,27 +57,27 @@ /* USER CODE END 0 */ /** - * Initializes the Global MSP. - */ + * Initializes the Global MSP. + */ void HAL_MspInit(void) { - /* USER CODE BEGIN MspInit 0 */ + /* USER CODE BEGIN MspInit 0 */ - /* USER CODE END MspInit 0 */ + /* USER CODE END MspInit 0 */ - __HAL_RCC_SYSCFG_CLK_ENABLE(); - __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_RCC_SYSCFG_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); - /* System interrupt init*/ + /* System interrupt init*/ - /** Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral - */ - HAL_PWREx_DisableUCPDDeadBattery(); + /** Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral + */ + HAL_PWREx_DisableUCPDDeadBattery(); - /* USER CODE BEGIN MspInit 1 */ + /* USER CODE BEGIN MspInit 1 */ - /* USER CODE END MspInit 1 */ + /* USER CODE END MspInit 1 */ } /* USER CODE BEGIN 1 */ diff --git a/Testbench/CUBEMXTESTING/Core/Src/stm32g4xx_it.c b/Testbench/CUBEMXTESTING/Core/Src/stm32g4xx_it.c index f02085e66..77f85d385 100644 --- a/Testbench/CUBEMXTESTING/Core/Src/stm32g4xx_it.c +++ b/Testbench/CUBEMXTESTING/Core/Src/stm32g4xx_it.c @@ -18,8 +18,9 @@ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ -#include "main.h" #include "stm32g4xx_it.h" + +#include "main.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ /* USER CODE END Includes */ @@ -68,129 +69,125 @@ extern TIM_HandleTypeDef htim5; /* Cortex-M4 Processor Interruption and Exception Handlers */ /******************************************************************************/ /** - * @brief This function handles Non maskable interrupt. - */ + * @brief This function handles Non maskable interrupt. + */ void NMI_Handler(void) { - /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ - /* USER CODE END NonMaskableInt_IRQn 0 */ - /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) {} - /* USER CODE END NonMaskableInt_IRQn 1 */ + /* USER CODE END NonMaskableInt_IRQn 1 */ } /** - * @brief This function handles Hard fault interrupt. - */ + * @brief This function handles Hard fault interrupt. + */ void HardFault_Handler(void) { - /* USER CODE BEGIN HardFault_IRQn 0 */ - - /* USER CODE END HardFault_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_HardFault_IRQn 0 */ - /* USER CODE END W1_HardFault_IRQn 0 */ - } + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } } /** - * @brief This function handles Memory management fault. - */ + * @brief This function handles Memory management fault. + */ void MemManage_Handler(void) { - /* USER CODE BEGIN MemoryManagement_IRQn 0 */ - - /* USER CODE END MemoryManagement_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ - /* USER CODE END W1_MemoryManagement_IRQn 0 */ - } + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } } /** - * @brief This function handles Prefetch fault, memory access fault. - */ + * @brief This function handles Prefetch fault, memory access fault. + */ void BusFault_Handler(void) { - /* USER CODE BEGIN BusFault_IRQn 0 */ - - /* USER CODE END BusFault_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_BusFault_IRQn 0 */ - /* USER CODE END W1_BusFault_IRQn 0 */ - } + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } } /** - * @brief This function handles Undefined instruction or illegal state. - */ + * @brief This function handles Undefined instruction or illegal state. + */ void UsageFault_Handler(void) { - /* USER CODE BEGIN UsageFault_IRQn 0 */ - - /* USER CODE END UsageFault_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ - /* USER CODE END W1_UsageFault_IRQn 0 */ - } + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } } /** - * @brief This function handles System service call via SWI instruction. - */ + * @brief This function handles System service call via SWI instruction. + */ void SVC_Handler(void) { - /* USER CODE BEGIN SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 0 */ - /* USER CODE END SVCall_IRQn 0 */ - /* USER CODE BEGIN SVCall_IRQn 1 */ + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ - /* USER CODE END SVCall_IRQn 1 */ + /* USER CODE END SVCall_IRQn 1 */ } /** - * @brief This function handles Debug monitor. - */ + * @brief This function handles Debug monitor. + */ void DebugMon_Handler(void) { - /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ - /* USER CODE END DebugMonitor_IRQn 0 */ - /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ - /* USER CODE END DebugMonitor_IRQn 1 */ + /* USER CODE END DebugMonitor_IRQn 1 */ } /** - * @brief This function handles Pendable request for system service. - */ + * @brief This function handles Pendable request for system service. + */ void PendSV_Handler(void) { - /* USER CODE BEGIN PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 0 */ - /* USER CODE END PendSV_IRQn 0 */ - /* USER CODE BEGIN PendSV_IRQn 1 */ + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ - /* USER CODE END PendSV_IRQn 1 */ + /* USER CODE END PendSV_IRQn 1 */ } /** - * @brief This function handles System tick timer. - */ + * @brief This function handles System tick timer. + */ void SysTick_Handler(void) { - /* USER CODE BEGIN SysTick_IRQn 0 */ + /* USER CODE BEGIN SysTick_IRQn 0 */ - /* USER CODE END SysTick_IRQn 0 */ - HAL_IncTick(); - /* USER CODE BEGIN SysTick_IRQn 1 */ + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ - /* USER CODE END SysTick_IRQn 1 */ + /* USER CODE END SysTick_IRQn 1 */ } /******************************************************************************/ @@ -201,73 +198,73 @@ void SysTick_Handler(void) /******************************************************************************/ /** - * @brief This function handles FDCAN1 interrupt 0. - */ + * @brief This function handles FDCAN1 interrupt 0. + */ void FDCAN1_IT0_IRQHandler(void) { - /* USER CODE BEGIN FDCAN1_IT0_IRQn 0 */ + /* USER CODE BEGIN FDCAN1_IT0_IRQn 0 */ - /* USER CODE END FDCAN1_IT0_IRQn 0 */ - HAL_FDCAN_IRQHandler(&hfdcan1); - /* USER CODE BEGIN FDCAN1_IT0_IRQn 1 */ + /* USER CODE END FDCAN1_IT0_IRQn 0 */ + HAL_FDCAN_IRQHandler(&hfdcan1); + /* USER CODE BEGIN FDCAN1_IT0_IRQn 1 */ - /* USER CODE END FDCAN1_IT0_IRQn 1 */ + /* USER CODE END FDCAN1_IT0_IRQn 1 */ } /** - * @brief This function handles TIM5 global interrupt. - */ + * @brief This function handles TIM5 global interrupt. + */ void TIM5_IRQHandler(void) { - /* USER CODE BEGIN TIM5_IRQn 0 */ + /* USER CODE BEGIN TIM5_IRQn 0 */ - /* USER CODE END TIM5_IRQn 0 */ - HAL_TIM_IRQHandler(&htim5); - /* USER CODE BEGIN TIM5_IRQn 1 */ + /* USER CODE END TIM5_IRQn 0 */ + HAL_TIM_IRQHandler(&htim5); + /* USER CODE BEGIN TIM5_IRQn 1 */ - /* USER CODE END TIM5_IRQn 1 */ + /* USER CODE END TIM5_IRQn 1 */ } /** - * @brief This function handles FDCAN2 interrupt 0. - */ + * @brief This function handles FDCAN2 interrupt 0. + */ void FDCAN2_IT0_IRQHandler(void) { - /* USER CODE BEGIN FDCAN2_IT0_IRQn 0 */ + /* USER CODE BEGIN FDCAN2_IT0_IRQn 0 */ - /* USER CODE END FDCAN2_IT0_IRQn 0 */ - HAL_FDCAN_IRQHandler(&hfdcan2); - /* USER CODE BEGIN FDCAN2_IT0_IRQn 1 */ + /* USER CODE END FDCAN2_IT0_IRQn 0 */ + HAL_FDCAN_IRQHandler(&hfdcan2); + /* USER CODE BEGIN FDCAN2_IT0_IRQn 1 */ - /* USER CODE END FDCAN2_IT0_IRQn 1 */ + /* USER CODE END FDCAN2_IT0_IRQn 1 */ } /** - * @brief This function handles FDCAN3 interrupt 0. - */ + * @brief This function handles FDCAN3 interrupt 0. + */ void FDCAN3_IT0_IRQHandler(void) { - /* USER CODE BEGIN FDCAN3_IT0_IRQn 0 */ + /* USER CODE BEGIN FDCAN3_IT0_IRQn 0 */ - /* USER CODE END FDCAN3_IT0_IRQn 0 */ - HAL_FDCAN_IRQHandler(&hfdcan3); - /* USER CODE BEGIN FDCAN3_IT0_IRQn 1 */ + /* USER CODE END FDCAN3_IT0_IRQn 0 */ + HAL_FDCAN_IRQHandler(&hfdcan3); + /* USER CODE BEGIN FDCAN3_IT0_IRQn 1 */ - /* USER CODE END FDCAN3_IT0_IRQn 1 */ + /* USER CODE END FDCAN3_IT0_IRQn 1 */ } /** - * @brief This function handles LPUART1 global interrupt. - */ + * @brief This function handles LPUART1 global interrupt. + */ void LPUART1_IRQHandler(void) { - /* USER CODE BEGIN LPUART1_IRQn 0 */ + /* USER CODE BEGIN LPUART1_IRQn 0 */ - /* USER CODE END LPUART1_IRQn 0 */ - HAL_UART_IRQHandler(&hlpuart1); - /* USER CODE BEGIN LPUART1_IRQn 1 */ + /* USER CODE END LPUART1_IRQn 0 */ + HAL_UART_IRQHandler(&hlpuart1); + /* USER CODE BEGIN LPUART1_IRQn 1 */ - /* USER CODE END LPUART1_IRQn 1 */ + /* USER CODE END LPUART1_IRQn 1 */ } /* USER CODE BEGIN 1 */ diff --git a/Testbench/CUBEMXTESTING/Core/Src/syscalls.c b/Testbench/CUBEMXTESTING/Core/Src/syscalls.c index e10d76fa2..d2b217993 100644 --- a/Testbench/CUBEMXTESTING/Core/Src/syscalls.c +++ b/Testbench/CUBEMXTESTING/Core/Src/syscalls.c @@ -21,158 +21,150 @@ */ /* Includes */ -#include -#include #include -#include #include -#include +#include +#include +#include #include #include - +#include /* Variables */ extern int __io_putchar(int ch) __attribute__((weak)); extern int __io_getchar(void) __attribute__((weak)); - -char *__env[1] = { 0 }; +char *__env[1] = {0}; char **environ = __env; - /* Functions */ -void initialise_monitor_handles() -{ -} +void initialise_monitor_handles() {} int _getpid(void) { - return 1; + return 1; } int _kill(int pid, int sig) { - (void)pid; - (void)sig; - errno = EINVAL; - return -1; + (void)pid; + (void)sig; + errno = EINVAL; + return -1; } -void _exit (int status) +void _exit(int status) { - _kill(status, -1); - while (1) {} /* Make sure we hang here */ + _kill(status, -1); + while (1) {} /* Make sure we hang here */ } __attribute__((weak)) int _read(int file, char *ptr, int len) { - (void)file; - int DataIdx; + (void)file; + int DataIdx; - for (DataIdx = 0; DataIdx < len; DataIdx++) - { - *ptr++ = __io_getchar(); - } + for (DataIdx = 0; DataIdx < len; DataIdx++) { + *ptr++ = __io_getchar(); + } - return len; + return len; } __attribute__((weak)) int _write(int file, char *ptr, int len) { - (void)file; - int DataIdx; + (void)file; + int DataIdx; - for (DataIdx = 0; DataIdx < len; DataIdx++) - { - __io_putchar(*ptr++); - } - return len; + for (DataIdx = 0; DataIdx < len; DataIdx++) { + __io_putchar(*ptr++); + } + return len; } int _close(int file) { - (void)file; - return -1; + (void)file; + return -1; } - int _fstat(int file, struct stat *st) { - (void)file; - st->st_mode = S_IFCHR; - return 0; + (void)file; + st->st_mode = S_IFCHR; + return 0; } int _isatty(int file) { - (void)file; - return 1; + (void)file; + return 1; } int _lseek(int file, int ptr, int dir) { - (void)file; - (void)ptr; - (void)dir; - return 0; + (void)file; + (void)ptr; + (void)dir; + return 0; } int _open(char *path, int flags, ...) { - (void)path; - (void)flags; - /* Pretend like we always fail */ - return -1; + (void)path; + (void)flags; + /* Pretend like we always fail */ + return -1; } int _wait(int *status) { - (void)status; - errno = ECHILD; - return -1; + (void)status; + errno = ECHILD; + return -1; } int _unlink(char *name) { - (void)name; - errno = ENOENT; - return -1; + (void)name; + errno = ENOENT; + return -1; } clock_t _times(struct tms *buf) { - (void)buf; - return -1; + (void)buf; + return -1; } int _stat(const char *file, struct stat *st) { - (void)file; - st->st_mode = S_IFCHR; - return 0; + (void)file; + st->st_mode = S_IFCHR; + return 0; } int _link(char *old, char *new) { - (void)old; - (void)new; - errno = EMLINK; - return -1; + (void)old; + (void)new; + errno = EMLINK; + return -1; } int _fork(void) { - errno = EAGAIN; - return -1; + errno = EAGAIN; + return -1; } int _execve(char *name, char **argv, char **env) { - (void)name; - (void)argv; - (void)env; - errno = ENOMEM; - return -1; + (void)name; + (void)argv; + (void)env; + errno = ENOMEM; + return -1; } // --- Picolibc Specific Section --- @@ -187,8 +179,8 @@ int _execve(char *name, char **argv, char **env) */ static int starm_putc(char c, FILE *file) { - (void) file; - __io_putchar(c); + (void)file; + __io_putchar(c); return c; } @@ -201,18 +193,15 @@ static int starm_putc(char c, FILE *file) static int starm_getc(FILE *file) { unsigned char c; - (void) file; - c = __io_getchar(); + (void)file; + c = __io_getchar(); return c; } // Define and initialize the standard I/O streams for Picolibc. // FDEV_SETUP_STREAM connects the starm_putc and starm_getc helper functions to a FILE structure. // _FDEV_SETUP_RW indicates the stream is for reading and writing. -static FILE __stdio = FDEV_SETUP_STREAM(starm_putc, - starm_getc, - NULL, - _FDEV_SETUP_RW); +static FILE __stdio = FDEV_SETUP_STREAM(starm_putc, starm_getc, NULL, _FDEV_SETUP_RW); // Assign the standard stream pointers (stdin, stdout, stderr) to the initialized stream. // Picolibc uses these pointers for standard I/O operations (printf, scanf, etc.). diff --git a/Testbench/CUBEMXTESTING/Core/Src/sysmem.c b/Testbench/CUBEMXTESTING/Core/Src/sysmem.c index a875d42c0..3a092d114 100644 --- a/Testbench/CUBEMXTESTING/Core/Src/sysmem.c +++ b/Testbench/CUBEMXTESTING/Core/Src/sysmem.c @@ -22,8 +22,8 @@ /* Includes */ #include -#include #include +#include /** * Pointer to the current high watermark of the heap usage @@ -53,35 +53,33 @@ static uint8_t *__sbrk_heap_end = NULL; */ void *_sbrk(ptrdiff_t incr) { - extern uint8_t _end; /* Symbol defined in the linker script */ - extern uint8_t _estack; /* Symbol defined in the linker script */ - extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ - const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; - const uint8_t *max_heap = (uint8_t *)stack_limit; - uint8_t *prev_heap_end; + extern uint8_t _end; /* Symbol defined in the linker script */ + extern uint8_t _estack; /* Symbol defined in the linker script */ + extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + const uint8_t *max_heap = (uint8_t *)stack_limit; + uint8_t *prev_heap_end; - /* Initialize heap end at first call */ - if (NULL == __sbrk_heap_end) - { - __sbrk_heap_end = &_end; - } + /* Initialize heap end at first call */ + if (NULL == __sbrk_heap_end) { + __sbrk_heap_end = &_end; + } - /* Protect heap from growing into the reserved MSP stack */ - if (__sbrk_heap_end + incr > max_heap) - { - errno = ENOMEM; - return (void *)-1; - } + /* Protect heap from growing into the reserved MSP stack */ + if (__sbrk_heap_end + incr > max_heap) { + errno = ENOMEM; + return (void *)-1; + } - prev_heap_end = __sbrk_heap_end; - __sbrk_heap_end += incr; + prev_heap_end = __sbrk_heap_end; + __sbrk_heap_end += incr; - return (void *)prev_heap_end; + return (void *)prev_heap_end; } #if defined(__PICOLIBC__) - // Picolibc expects syscalls without the leading underscore. - // This creates a strong alias so that - // calls to `sbrk()` are resolved to our `_sbrk()` implementation. - __strong_reference(_sbrk, sbrk); +// Picolibc expects syscalls without the leading underscore. +// This creates a strong alias so that +// calls to `sbrk()` are resolved to our `_sbrk()` implementation. +__strong_reference(_sbrk, sbrk); #endif diff --git a/Testbench/CUBEMXTESTING/Core/Src/system_stm32g4xx.c b/Testbench/CUBEMXTESTING/Core/Src/system_stm32g4xx.c index 2cd914e7b..414c5339c 100644 --- a/Testbench/CUBEMXTESTING/Core/Src/system_stm32g4xx.c +++ b/Testbench/CUBEMXTESTING/Core/Src/system_stm32g4xx.c @@ -1,109 +1,109 @@ /** - ****************************************************************************** - * @file system_stm32g4xx.c - * @author MCD Application Team - * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File - * - * This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32g4xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * After each device reset the HSI (16 MHz) is used as system clock source. - * Then SystemInit() function is called, in "startup_stm32g4xx.s" file, to - * configure the system clock before to branch to main program. - * - * This file configures the system clock as follows: - *============================================================================= - *----------------------------------------------------------------------------- - * System Clock source | HSI - *----------------------------------------------------------------------------- - * SYSCLK(Hz) | 16000000 - *----------------------------------------------------------------------------- - * HCLK(Hz) | 16000000 - *----------------------------------------------------------------------------- - * AHB Prescaler | 1 - *----------------------------------------------------------------------------- - * APB1 Prescaler | 1 - *----------------------------------------------------------------------------- - * APB2 Prescaler | 1 - *----------------------------------------------------------------------------- - * PLL_M | 1 - *----------------------------------------------------------------------------- - * PLL_N | 16 - *----------------------------------------------------------------------------- - * PLL_P | 7 - *----------------------------------------------------------------------------- - * PLL_Q | 2 - *----------------------------------------------------------------------------- - * PLL_R | 2 - *----------------------------------------------------------------------------- - * Require 48MHz for RNG | Disabled - *----------------------------------------------------------------------------- - *============================================================================= - ****************************************************************************** - * @attention - * - * Copyright (c) 2019 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ + ****************************************************************************** + * @file system_stm32g4xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32g4xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32g4xx.s" file, to + * configure the system clock before to branch to main program. + * + * This file configures the system clock as follows: + *============================================================================= + *----------------------------------------------------------------------------- + * System Clock source | HSI + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 16000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 16000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 1 + *----------------------------------------------------------------------------- + * PLL_M | 1 + *----------------------------------------------------------------------------- + * PLL_N | 16 + *----------------------------------------------------------------------------- + * PLL_P | 7 + *----------------------------------------------------------------------------- + * PLL_Q | 2 + *----------------------------------------------------------------------------- + * PLL_R | 2 + *----------------------------------------------------------------------------- + * Require 48MHz for RNG | Disabled + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ /** @addtogroup CMSIS - * @{ - */ + * @{ + */ /** @addtogroup stm32g4xx_system - * @{ - */ + * @{ + */ /** @addtogroup STM32G4xx_System_Private_Includes - * @{ - */ + * @{ + */ #include "stm32g4xx.h" -#if !defined (HSE_VALUE) - #define HSE_VALUE 24000000U /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ +#if !defined(HSE_VALUE) +#define HSE_VALUE 24000000U /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ -#if !defined (HSI_VALUE) - #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ +#if !defined(HSI_VALUE) +#define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ /** - * @} - */ + * @} + */ /** @addtogroup STM32G4xx_System_Private_TypesDefinitions - * @{ - */ + * @{ + */ /** - * @} - */ + * @} + */ /** @addtogroup STM32G4xx_System_Private_Defines - * @{ - */ + * @{ + */ /************************* Miscellaneous Configuration ************************/ /* Note: Following vector table addresses must be defined in line with linker - configuration. */ + configuration. */ /*!< Uncomment the following line if you need to relocate the vector table anywhere in Flash or Sram, else the vector table is kept at the automatic remap of boot address selected */ @@ -114,174 +114,172 @@ in Sram else user remap will be done in Flash. */ /* #define VECT_TAB_SRAM */ #if defined(VECT_TAB_SRAM) -#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x200. */ +#define VECT_TAB_BASE_ADDRESS \ + SRAM_BASE /*!< Vector Table base address field. \ + This value must be a multiple of 0x200. */ #else -#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x200. */ -#endif /* VECT_TAB_SRAM */ +#define VECT_TAB_BASE_ADDRESS \ + FLASH_BASE /*!< Vector Table base address field. \ + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_SRAM */ #if !defined(VECT_TAB_OFFSET) -#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table offset field. - This value must be a multiple of 0x200. */ -#endif /* VECT_TAB_OFFSET */ +#define VECT_TAB_OFFSET \ + 0x00000000U /*!< Vector Table offset field. \ + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_OFFSET */ #endif /* USER_VECT_TAB_ADDRESS */ -/******************************************************************************/ -/** - * @} - */ + /******************************************************************************/ + /** + * @} + */ /** @addtogroup STM32G4xx_System_Private_Macros - * @{ - */ + * @{ + */ /** - * @} - */ + * @} + */ /** @addtogroup STM32G4xx_System_Private_Variables - * @{ - */ - /* The SystemCoreClock variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetHCLKFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ - uint32_t SystemCoreClock = HSI_VALUE; - - const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; - const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; + * @{ + */ +/* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. +*/ +uint32_t SystemCoreClock = HSI_VALUE; + +const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; +const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; /** - * @} - */ + * @} + */ /** @addtogroup STM32G4xx_System_Private_FunctionPrototypes - * @{ - */ + * @{ + */ /** - * @} - */ + * @} + */ /** @addtogroup STM32G4xx_System_Private_Functions - * @{ - */ + * @{ + */ /** - * @brief Setup the microcontroller system. - * @param None - * @retval None - */ + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ void SystemInit(void) { - /* FPU settings ------------------------------------------------------------*/ - #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ - #endif +/* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << (10 * 2)) | (3UL << (11 * 2))); /* set CP10 and CP11 Full Access */ +#endif - /* Configure the Vector Table location add offset address ------------------*/ + /* Configure the Vector Table location add offset address ------------------*/ #if defined(USER_VECT_TAB_ADDRESS) - SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#endif /* USER_VECT_TAB_ADDRESS */ + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ } /** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * - * (**) HSI_VALUE is a constant defined in stm32g4xx_hal.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (***) HSE_VALUE is a constant defined in stm32g4xx_hal.h file (default value - * 24 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param None - * @retval None - */ + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (**) HSI_VALUE is a constant defined in stm32g4xx_hal.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in stm32g4xx_hal.h file (default value + * 24 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ void SystemCoreClockUpdate(void) { - uint32_t tmp, pllvco, pllr, pllsource, pllm; - - /* Get SYSCLK source -------------------------------------------------------*/ - switch (RCC->CFGR & RCC_CFGR_SWS) - { - case 0x04: /* HSI used as system clock source */ - SystemCoreClock = HSI_VALUE; - break; - - case 0x08: /* HSE used as system clock source */ - SystemCoreClock = HSE_VALUE; - break; - - case 0x0C: /* PLL used as system clock source */ - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN - SYSCLK = PLL_VCO / PLLR - */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); - pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1U ; - if (pllsource == 0x02UL) /* HSI used as PLL clock source */ - { - pllvco = (HSI_VALUE / pllm); - } - else /* HSE used as PLL clock source */ - { - pllvco = (HSE_VALUE / pllm); - } - pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8); - pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U; - SystemCoreClock = pllvco/pllr; - break; - - default: - break; - } - /* Compute HCLK clock frequency --------------------------------------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK clock frequency */ - SystemCoreClock >>= tmp; + uint32_t tmp, pllvco, pllr, pllsource, pllm; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) { + case 0x04: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + + case 0x08: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + + case 0x0C: /* PLL used as system clock source */ + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); + pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1U; + if (pllsource == 0x02UL) /* HSI used as PLL clock source */ + { + pllvco = (HSI_VALUE / pllm); + } else /* HSE used as PLL clock source */ + { + pllvco = (HSE_VALUE / pllm); + } + pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8); + pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U; + SystemCoreClock = pllvco / pllr; + break; + + default: + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; } - /** - * @} - */ + * @} + */ /** - * @} - */ + * @} + */ /** - * @} - */ - - + * @} + */ diff --git a/Testbench/CUBEMXTESTING/Core/Src/tim.c b/Testbench/CUBEMXTESTING/Core/Src/tim.c index cc6e6a92e..1f6110e86 100644 --- a/Testbench/CUBEMXTESTING/Core/Src/tim.c +++ b/Testbench/CUBEMXTESTING/Core/Src/tim.c @@ -30,83 +30,76 @@ TIM_HandleTypeDef htim5; void MX_TIM5_Init(void) { - /* USER CODE BEGIN TIM5_Init 0 */ - - /* USER CODE END TIM5_Init 0 */ - - TIM_ClockConfigTypeDef sClockSourceConfig = {0}; - TIM_MasterConfigTypeDef sMasterConfig = {0}; - - /* USER CODE BEGIN TIM5_Init 1 */ - - /* USER CODE END TIM5_Init 1 */ - htim5.Instance = TIM5; - htim5.Init.Prescaler = 159; - htim5.Init.CounterMode = TIM_COUNTERMODE_UP; - htim5.Init.Period = 499; - htim5.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; - htim5.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; - if (HAL_TIM_Base_Init(&htim5) != HAL_OK) - { - Error_Handler(); - } - sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; - if (HAL_TIM_ConfigClockSource(&htim5, &sClockSourceConfig) != HAL_OK) - { - Error_Handler(); - } - sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; - sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; - if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN TIM5_Init 2 */ + /* USER CODE BEGIN TIM5_Init 0 */ + + /* USER CODE END TIM5_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; + + /* USER CODE BEGIN TIM5_Init 1 */ + + /* USER CODE END TIM5_Init 1 */ + htim5.Instance = TIM5; + htim5.Init.Prescaler = 159; + htim5.Init.CounterMode = TIM_COUNTERMODE_UP; + htim5.Init.Period = 499; + htim5.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim5.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim5) != HAL_OK) { + Error_Handler(); + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(&htim5, &sClockSourceConfig) != HAL_OK) { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig) != HAL_OK) { + Error_Handler(); + } + /* USER CODE BEGIN TIM5_Init 2 */ HAL_TIM_Base_Start_IT(&htim5); - /* USER CODE END TIM5_Init 2 */ - + /* USER CODE END TIM5_Init 2 */ } -void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *tim_baseHandle) { - if(tim_baseHandle->Instance==TIM5) - { - /* USER CODE BEGIN TIM5_MspInit 0 */ + if (tim_baseHandle->Instance == TIM5) { + /* USER CODE BEGIN TIM5_MspInit 0 */ - /* USER CODE END TIM5_MspInit 0 */ - /* TIM5 clock enable */ - __HAL_RCC_TIM5_CLK_ENABLE(); + /* USER CODE END TIM5_MspInit 0 */ + /* TIM5 clock enable */ + __HAL_RCC_TIM5_CLK_ENABLE(); - /* TIM5 interrupt Init */ - HAL_NVIC_SetPriority(TIM5_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(TIM5_IRQn); - /* USER CODE BEGIN TIM5_MspInit 1 */ + /* TIM5 interrupt Init */ + HAL_NVIC_SetPriority(TIM5_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(TIM5_IRQn); + /* USER CODE BEGIN TIM5_MspInit 1 */ - /* USER CODE END TIM5_MspInit 1 */ - } + /* USER CODE END TIM5_MspInit 1 */ + } } -void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* tim_baseHandle) +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *tim_baseHandle) { - if(tim_baseHandle->Instance==TIM5) - { - /* USER CODE BEGIN TIM5_MspDeInit 0 */ + if (tim_baseHandle->Instance == TIM5) { + /* USER CODE BEGIN TIM5_MspDeInit 0 */ - /* USER CODE END TIM5_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_TIM5_CLK_DISABLE(); + /* USER CODE END TIM5_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM5_CLK_DISABLE(); - /* TIM5 interrupt Deinit */ - HAL_NVIC_DisableIRQ(TIM5_IRQn); - /* USER CODE BEGIN TIM5_MspDeInit 1 */ + /* TIM5 interrupt Deinit */ + HAL_NVIC_DisableIRQ(TIM5_IRQn); + /* USER CODE BEGIN TIM5_MspDeInit 1 */ - /* USER CODE END TIM5_MspDeInit 1 */ - } + /* USER CODE END TIM5_MspDeInit 1 */ + } } /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ - diff --git a/Testbench/CUBEMXTESTING/Core/Src/usart.c b/Testbench/CUBEMXTESTING/Core/Src/usart.c index 836ce8d48..a14deb76c 100644 --- a/Testbench/CUBEMXTESTING/Core/Src/usart.c +++ b/Testbench/CUBEMXTESTING/Core/Src/usart.c @@ -31,106 +31,98 @@ UART_HandleTypeDef hlpuart1; void MX_LPUART1_UART_Init(void) { - /* USER CODE BEGIN LPUART1_Init 0 */ - - /* USER CODE END LPUART1_Init 0 */ - - /* USER CODE BEGIN LPUART1_Init 1 */ - - /* USER CODE END LPUART1_Init 1 */ - hlpuart1.Instance = LPUART1; - hlpuart1.Init.BaudRate = 115200; - hlpuart1.Init.WordLength = UART_WORDLENGTH_8B; - hlpuart1.Init.StopBits = UART_STOPBITS_1; - hlpuart1.Init.Parity = UART_PARITY_NONE; - hlpuart1.Init.Mode = UART_MODE_TX_RX; - hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; - hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; - hlpuart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; - hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; - if (HAL_UART_Init(&hlpuart1) != HAL_OK) - { - Error_Handler(); - } - if (HAL_UARTEx_SetTxFifoThreshold(&hlpuart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) - { - Error_Handler(); - } - if (HAL_UARTEx_SetRxFifoThreshold(&hlpuart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) - { - Error_Handler(); - } - if (HAL_UARTEx_DisableFifoMode(&hlpuart1) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN LPUART1_Init 2 */ - - /* USER CODE END LPUART1_Init 2 */ - + /* USER CODE BEGIN LPUART1_Init 0 */ + + /* USER CODE END LPUART1_Init 0 */ + + /* USER CODE BEGIN LPUART1_Init 1 */ + + /* USER CODE END LPUART1_Init 1 */ + hlpuart1.Instance = LPUART1; + hlpuart1.Init.BaudRate = 115200; + hlpuart1.Init.WordLength = UART_WORDLENGTH_8B; + hlpuart1.Init.StopBits = UART_STOPBITS_1; + hlpuart1.Init.Parity = UART_PARITY_NONE; + hlpuart1.Init.Mode = UART_MODE_TX_RX; + hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + hlpuart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; + hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&hlpuart1) != HAL_OK) { + Error_Handler(); + } + if (HAL_UARTEx_SetTxFifoThreshold(&hlpuart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) { + Error_Handler(); + } + if (HAL_UARTEx_SetRxFifoThreshold(&hlpuart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) { + Error_Handler(); + } + if (HAL_UARTEx_DisableFifoMode(&hlpuart1) != HAL_OK) { + Error_Handler(); + } + /* USER CODE BEGIN LPUART1_Init 2 */ + + /* USER CODE END LPUART1_Init 2 */ } -void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) +void HAL_UART_MspInit(UART_HandleTypeDef *uartHandle) { - GPIO_InitTypeDef GPIO_InitStruct = {0}; - if(uartHandle->Instance==LPUART1) - { - /* USER CODE BEGIN LPUART1_MspInit 0 */ - - /* USER CODE END LPUART1_MspInit 0 */ - LL_RCC_SetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE_PCLK1); - - /* LPUART1 clock enable */ - __HAL_RCC_LPUART1_CLK_ENABLE(); - - __HAL_RCC_GPIOA_CLK_ENABLE(); - /**LPUART1 GPIO Configuration - PA2 ------> LPUART1_TX - PA3 ------> LPUART1_RX - */ - GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF12_LPUART1; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /* LPUART1 interrupt Init */ - HAL_NVIC_SetPriority(LPUART1_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(LPUART1_IRQn); - /* USER CODE BEGIN LPUART1_MspInit 1 */ - - /* USER CODE END LPUART1_MspInit 1 */ - } + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if (uartHandle->Instance == LPUART1) { + /* USER CODE BEGIN LPUART1_MspInit 0 */ + + /* USER CODE END LPUART1_MspInit 0 */ + LL_RCC_SetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE_PCLK1); + + /* LPUART1 clock enable */ + __HAL_RCC_LPUART1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**LPUART1 GPIO Configuration + PA2 ------> LPUART1_TX + PA3 ------> LPUART1_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_2 | GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF12_LPUART1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* LPUART1 interrupt Init */ + HAL_NVIC_SetPriority(LPUART1_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(LPUART1_IRQn); + /* USER CODE BEGIN LPUART1_MspInit 1 */ + + /* USER CODE END LPUART1_MspInit 1 */ + } } -void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle) +void HAL_UART_MspDeInit(UART_HandleTypeDef *uartHandle) { - if(uartHandle->Instance==LPUART1) - { - /* USER CODE BEGIN LPUART1_MspDeInit 0 */ + if (uartHandle->Instance == LPUART1) { + /* USER CODE BEGIN LPUART1_MspDeInit 0 */ - /* USER CODE END LPUART1_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_LPUART1_CLK_DISABLE(); + /* USER CODE END LPUART1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_LPUART1_CLK_DISABLE(); - /**LPUART1 GPIO Configuration - PA2 ------> LPUART1_TX - PA3 ------> LPUART1_RX - */ - HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); + /**LPUART1 GPIO Configuration + PA2 ------> LPUART1_TX + PA3 ------> LPUART1_RX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2 | GPIO_PIN_3); - /* LPUART1 interrupt Deinit */ - HAL_NVIC_DisableIRQ(LPUART1_IRQn); - /* USER CODE BEGIN LPUART1_MspDeInit 1 */ + /* LPUART1 interrupt Deinit */ + HAL_NVIC_DisableIRQ(LPUART1_IRQn); + /* USER CODE BEGIN LPUART1_MspDeInit 1 */ - /* USER CODE END LPUART1_MspDeInit 1 */ - } + /* USER CODE END LPUART1_MspDeInit 1 */ + } } /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ - From c8a3d2e5c203516dbf7d57eb904d38aa03030c2b Mon Sep 17 00:00:00 2001 From: Daniel Hansen Date: Sun, 23 Aug 2026 16:05:16 -0700 Subject: [PATCH 06/17] Adding a project (format) Signed-off-by: Daniel Hansen --- BLINKY/blinky.cmake | 59 ++ CMakeLists.txt | 277 +++---- CUBEMX.md | 6 +- Lib/Peripherals/CAN/TESTING.md | 6 +- Lib/Vendor/TargetFlags/README.md | 38 +- Lib/Vendor/TargetFlags/stm32g4xx.cmake | 22 +- Lib/Vendor/TargetFlags/stm32h5xx.cmake | 19 +- Lib/Vendor/TargetFlags/stm32l4xx.cmake | 19 +- Lib/Vendor/TargetFlags/stm32u5xx.cmake | 19 +- Lib/cmake/cube.cmake | 688 +++++++++--------- Lib/cmake/gcc-arm-none-eabi.cmake | 4 +- Testbench/CUBEMXTESTING/Core/Inc/fdcan.h | 1 + Testbench/CUBEMXTESTING/Core/Inc/gpio.h | 1 + Testbench/CUBEMXTESTING/Core/Inc/main.h | 13 +- .../CUBEMXTESTING/Core/Inc/stm32_assert.h | 17 +- .../Core/Inc/stm32g4xx_hal_conf.h | 215 +++--- Testbench/CUBEMXTESTING/Core/Inc/tim.h | 1 + Testbench/CUBEMXTESTING/Core/Inc/usart.h | 1 + Testbench/CUBEMXTESTING/Core/Src/fdcan.c | 525 ++++++------- Testbench/CUBEMXTESTING/Core/Src/gpio.c | 537 +++++++------- Testbench/CUBEMXTESTING/Core/Src/main.c | 169 ++--- .../Core/Src/stm32g4xx_hal_msp.c | 24 +- .../CUBEMXTESTING/Core/Src/stm32g4xx_it.c | 211 +++--- Testbench/CUBEMXTESTING/Core/Src/tim.c | 113 +-- Testbench/CUBEMXTESTING/Core/Src/usart.c | 164 +++-- Testbench/testbench.cmake | 9 + 26 files changed, 1676 insertions(+), 1482 deletions(-) create mode 100644 BLINKY/blinky.cmake create mode 100644 Testbench/testbench.cmake diff --git a/BLINKY/blinky.cmake b/BLINKY/blinky.cmake new file mode 100644 index 000000000..f11af746e --- /dev/null +++ b/BLINKY/blinky.cmake @@ -0,0 +1,59 @@ +add_project( + NAME "G4BLINKY" + PATH "G4BLINKY" + SERIES "g4" + SPECIFIER "g474re" + HAL_GIT_TAG "v1.2.7" # https://github.com/STMicroelectronics/stm32g4xx-hal-driver/tree/v1.2.7 + CMSIS_GIT_TAG "v1.2.6" # https://github.com/STMicroelectronics/cmsis-device-g4/tree/v1.2.6 + CMSIS_MAJOR "5" +) + +add_project( + NAME "G4ECHO" + PATH "G4ECHO" + SERIES "g4" + SPECIFIER "g474re" + HAL_GIT_TAG "v1.2.7" # https://github.com/STMicroelectronics/stm32g4xx-hal-driver/tree/v1.2.7 + CMSIS_GIT_TAG "v1.2.6" # https://github.com/STMicroelectronics/cmsis-device-g4/tree/v1.2.6 + CMSIS_MAJOR "5" +) + +add_project( + NAME "G4HELLO" + PATH "G4HELLO" + SERIES "g4" + SPECIFIER "g474re" + HAL_GIT_TAG "v1.2.7" # https://github.com/STMicroelectronics/stm32g4xx-hal-driver/tree/v1.2.7 + CMSIS_GIT_TAG "v1.2.6" # https://github.com/STMicroelectronics/cmsis-device-g4/tree/v1.2.6 + CMSIS_MAJOR "5" +) + +add_project( + NAME "U5BLINKY" + PATH "U5BLINKY" + SERIES "u5" + SPECIFIER "u5a9nj" + HAL_GIT_TAG "v1.6.3" # https://github.com/STMicroelectronics/stm32u5xx-hal-driver/tree/v1.6.3 + CMSIS_GIT_TAG "v1.4.3" # https://github.com/STMicroelectronics/cmsis-device-u5/tree/v1.4.3 + CMSIS_MAJOR "5" +) + +# add_project( +# NAME "L4HELLO" +# PATH "L4HELLO" +# SERIES "l4" +# SPECIFIER "l476rg" +# HAL_GIT_TAG "v1.13.6" # https://github.com/STMicroelectronics/stm32l4xx-hal-driver/tree/v1.13.6 +# CMSIS_GIT_TAG "v1.7.5" # https://github.com/STMicroelectronics/cmsis-device-l4/tree/v1.7.5 +# CMSIS_MAJOR "5" +# ) + +# add_project( +# NAME "L4BLINKY" +# PATH "L4BLINKY" +# SERIES "l4" +# SPECIFIER "l476rg" +# HAL_GIT_TAG "v1.13.6" # https://github.com/STMicroelectronics/stm32l4xx-hal-driver/tree/v1.13.6 +# CMSIS_GIT_TAG "v1.7.5" # https://github.com/STMicroelectronics/cmsis-device-l4/tree/v1.7.5 +# CMSIS_MAJOR "5" +# ) diff --git a/CMakeLists.txt b/CMakeLists.txt index b384bc343..5915fd75d 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1,11 +1,6 @@ cmake_minimum_required(VERSION 3.25) project(Firmware) -enable_language( - C - ASM -) - -# Setup compiler settings +enable_language(C ASM) set(CMAKE_C_STANDARD 11) set(CMAKE_C_STANDARD_REQUIRED ON) set(CMAKE_C_EXTENSIONS ON) @@ -13,128 +8,119 @@ set(CMAKE_EXPORT_COMPILE_COMMANDS TRUE) # Messages if(NOT DEFINED CMAKE_PRESET_NAME) - message( - FATAL_ERROR - "This project requires configuration using a CMake preset. Please use 'cmake --preset ' or select a preset in your IDE." - ) + message( + FATAL_ERROR + "This project requires configuration using a CMake preset. Please use 'cmake --preset ' or select a preset in your IDE." + ) endif() message( - STATUS - "Build type: " - ${CMAKE_BUILD_TYPE} + STATUS + "Build type: " + ${CMAKE_BUILD_TYPE} ) message(STATUS "Target type: ${TARGET_TYPE}") message( - STATUS - "Active CMake Preset: " - ${CMAKE_PRESET_NAME} + STATUS + "Active CMake Preset: " + ${CMAKE_PRESET_NAME} ) # Shared Compiler Cache Configuration find_program(SCCACHE_PROGRAM sccache) if( - SCCACHE_PROGRAM - AND - NOT - CMAKE_C_COMPILER_LAUNCHER - AND - NOT - CMAKE_ASM_COMPILER_LAUNCHER + SCCACHE_PROGRAM + AND + NOT + CMAKE_C_COMPILER_LAUNCHER + AND + NOT + CMAKE_ASM_COMPILER_LAUNCHER ) - message(STATUS "Found sccache: ${SCCACHE_PROGRAM}") - set(SCCACHE_DIR_PATH "${CMAKE_SOURCE_DIR}/sccache") - set( - CMAKE_C_COMPILER_LAUNCHER - "${CMAKE_COMMAND}" - -E - env - "SCCACHE_DIR=${SCCACHE_DIR_PATH}" - "${SCCACHE_PROGRAM}" - ) - set( - CMAKE_ASM_COMPILER_LAUNCHER - "${CMAKE_COMMAND}" - -E - env - "SCCACHE_DIR=${SCCACHE_DIR_PATH}" - "${SCCACHE_PROGRAM}" - ) - message(STATUS "sccache directory: ${SCCACHE_DIR_PATH}") + message(STATUS "Found sccache: ${SCCACHE_PROGRAM}") + set(SCCACHE_DIR_PATH "${CMAKE_SOURCE_DIR}/sccache") + set( + CMAKE_C_COMPILER_LAUNCHER + "${CMAKE_COMMAND}" + -E + env + "SCCACHE_DIR=${SCCACHE_DIR_PATH}" + "${SCCACHE_PROGRAM}" + ) + set( + CMAKE_ASM_COMPILER_LAUNCHER + "${CMAKE_COMMAND}" + -E + env + "SCCACHE_DIR=${SCCACHE_DIR_PATH}" + "${SCCACHE_PROGRAM}" + ) + message(STATUS "sccache directory: ${SCCACHE_DIR_PATH}") elseif(CMAKE_C_COMPILER_LAUNCHER OR CMAKE_ASM_COMPILER_LAUNCHER) - message( - STATUS - "Not using sccache: CMAKE_C_COMPILER_LAUNCHER already set to '${CMAKE_C_COMPILER_LAUNCHER}' or CMAKE_ASM_COMPILER_LAUNCHER already set to '${CMAKE_ASM_COMPILER_LAUNCHER}'" - ) + message( + STATUS + "Not using sccache: CMAKE_C_COMPILER_LAUNCHER already set to '${CMAKE_C_COMPILER_LAUNCHER}' or CMAKE_ASM_COMPILER_LAUNCHER already set to '${CMAKE_ASM_COMPILER_LAUNCHER}'" + ) else() - message(STATUS "Not using sccache: sccache not found in PATH") + message(STATUS "Not using sccache: sccache not found in PATH") endif() # Compiler Cache Configuration find_program(CCACHE_PROGRAM ccache) if( - CCACHE_PROGRAM - AND - NOT - CMAKE_C_COMPILER_LAUNCHER - AND - NOT - CMAKE_ASM_COMPILER_LAUNCHER + CCACHE_PROGRAM + AND + NOT + CMAKE_C_COMPILER_LAUNCHER + AND + NOT + CMAKE_ASM_COMPILER_LAUNCHER ) - message(STATUS "Found ccache: ${CCACHE_PROGRAM}") - set(CCACHE_DIR_PATH "${CMAKE_SOURCE_DIR}/ccache") - set( - CMAKE_C_COMPILER_LAUNCHER - "${CMAKE_COMMAND}" - -E - env - "CCACHE_DIR=${CCACHE_DIR_PATH}" - "${CCACHE_PROGRAM}" - ) - set( - CMAKE_ASM_COMPILER_LAUNCHER - "${CMAKE_COMMAND}" - -E - env - "CCACHE_DIR=${CCACHE_DIR_PATH}" - "${CCACHE_PROGRAM}" - ) - message(STATUS "ccache directory: ${CCACHE_DIR_PATH}") + message(STATUS "Found ccache: ${CCACHE_PROGRAM}") + set(CCACHE_DIR_PATH "${CMAKE_SOURCE_DIR}/ccache") + set( + CMAKE_C_COMPILER_LAUNCHER + "${CMAKE_COMMAND}" + -E + env + "CCACHE_DIR=${CCACHE_DIR_PATH}" + "${CCACHE_PROGRAM}" + ) + set( + CMAKE_ASM_COMPILER_LAUNCHER + "${CMAKE_COMMAND}" + -E + env + "CCACHE_DIR=${CCACHE_DIR_PATH}" + "${CCACHE_PROGRAM}" + ) + message(STATUS "ccache directory: ${CCACHE_DIR_PATH}") elseif(CMAKE_C_COMPILER_LAUNCHER OR CMAKE_ASM_COMPILER_LAUNCHER) - message( - STATUS - "Not using ccache: CMAKE_C_COMPILER_LAUNCHER already set to '${CMAKE_C_COMPILER_LAUNCHER}' or CMAKE_ASM_COMPILER_LAUNCHER already set to '${CMAKE_ASM_COMPILER_LAUNCHER}'" - ) + message( + STATUS + "Not using ccache: CMAKE_C_COMPILER_LAUNCHER already set to '${CMAKE_C_COMPILER_LAUNCHER}' or CMAKE_ASM_COMPILER_LAUNCHER already set to '${CMAKE_ASM_COMPILER_LAUNCHER}'" + ) else() - message(STATUS "Not using ccache: ccache not found in PATH") + message(STATUS "Not using ccache: ccache not found in PATH") endif() # Globals -set(lib_path "Lib") -set(platform_path "${lib_path}/Platform") +set(LIB_PATH "Lib") +set(platform_path "${LIB_PATH}/Platform") -include("${lib_path}/cmake/cube.cmake") +include("${LIB_PATH}/cmake/cube.cmake") add_arm_cmsis_core( MAJOR "5" GIT_TAG "5.9.0" # https://github.com/ARM-software/CMSIS_5/tree/5.9.0 ) -add_project( - NAME "CUBEMXTESTING" - PATH "Testbench/CUBEMXTESTING" - SERIES "g4" - SPECIFIER "g474re" - HAL_GIT_TAG "v1.2.7" # https://github.com/STMicroelectronics/stm32g4xx-hal-driver/tree/v1.2.7 - CMSIS_GIT_TAG "v1.2.6" # https://github.com/STMicroelectronics/cmsis-device-g4/tree/v1.2.6 - CMSIS_MAJOR "5" -) # Vendor -include("${lib_path}/Vendor/CMSIS_5/cmsis_5.cmake") -include("${lib_path}/Vendor/STM32_HAL_LL/cube.cmake") -add_subdirectory("${lib_path}/Vendor/BCC") -include("${lib_path}/Vendor/MLX90640/combined.cmake") -include("${lib_path}/Vendor/MLX90614/combined.cmake") +include("${LIB_PATH}/Vendor/CMSIS_5/cmsis_5.cmake") +include("${LIB_PATH}/Vendor/STM32_HAL_LL/cube.cmake") +add_subdirectory("${LIB_PATH}/Vendor/BCC") +include("${LIB_PATH}/Vendor/MLX90640/combined.cmake") +include("${LIB_PATH}/Vendor/MLX90614/combined.cmake") # Platforms include("${platform_path}/STM32G474xE/chip.cmake") @@ -144,51 +130,88 @@ include("${platform_path}/STM32L476xG/chip.cmake") include("${platform_path}/STM32H523xE/chip.cmake") # Utils -include("${lib_path}/GlobalShare/common.cmake") -include("${lib_path}/Utils/OldLogomatic/logomatic.cmake") -include("${lib_path}/Utils/Logomatic/log.cmake") -include("${lib_path}/Utils/CubeVCP/vcp.cmake") -include("${lib_path}/Utils/VirtualComPort/vcp.cmake") -include("${lib_path}/Utils/CircularBuffer/circular-buffer-lib.cmake") -include("${lib_path}/Utils/MsgBuffer/msg-buffer-lib.cmake") -include("${lib_path}/cmake/gr-lib.cmake") -include("${lib_path}/Utils/BitManipulations/bit-utils.cmake") +include("${LIB_PATH}/GlobalShare/common.cmake") +include("${LIB_PATH}/Utils/OldLogomatic/logomatic.cmake") +include("${LIB_PATH}/Utils/Logomatic/log.cmake") +include("${LIB_PATH}/Utils/CubeVCP/vcp.cmake") +include("${LIB_PATH}/Utils/VirtualComPort/vcp.cmake") +include("${LIB_PATH}/Utils/CircularBuffer/circular-buffer-lib.cmake") +include("${LIB_PATH}/Utils/MsgBuffer/msg-buffer-lib.cmake") +include("${LIB_PATH}/cmake/gr-lib.cmake") +include("${LIB_PATH}/Utils/BitManipulations/bit-utils.cmake") # Autogen include("Autogen/CAN/CANfigurator.cmake") # Peripherals -include("${lib_path}/Peripherals/USART/common.cmake") -include("${lib_path}/Peripherals/TimedCAN/common.cmake") -include("${lib_path}/Peripherals/CAN/common.cmake") -include("${lib_path}/Peripherals/CubeCAN/cube_can.cmake") +include("${LIB_PATH}/Peripherals/USART/common.cmake") +include("${LIB_PATH}/Peripherals/TimedCAN/common.cmake") +include("${LIB_PATH}/Peripherals/CAN/common.cmake") +include("${LIB_PATH}/Peripherals/CubeCAN/cube_can.cmake") -include("${lib_path}/FancyLayers-RENAME/GRCAN/grcan_fancylayer.cmake") -include("${lib_path}/FancyLayers-RENAME/ADC/adc.cmake") -include("${lib_path}/FancyLayers-RENAME/SPI/spi.cmake") -include("${lib_path}/FancyLayers-RENAME/NeoPixel/neopixel.cmake") +include("${LIB_PATH}/FancyLayers-RENAME/GRCAN/grcan_fancylayer.cmake") +include("${LIB_PATH}/FancyLayers-RENAME/ADC/adc.cmake") +include("${LIB_PATH}/FancyLayers-RENAME/SPI/spi.cmake") +include("${LIB_PATH}/FancyLayers-RENAME/NeoPixel/neopixel.cmake") # Projects +include(BLINKY/blinky.cmake) +include(Testbench/testbench.cmake) + add_gr_project(STM32G474xE ECU) add_gr_project(STM32G474xE CCU) -# add_gr_project(STM32G474xE DashPanel) add_gr_project(STM32G474xE CANine) add_gr_project(STM32G431x8 OutboardSensors TireTemp) add_gr_project(STM32G431x8 OutboardSensors BrakeTemp) - -# Development -add_gr_project(STM32G474xE Testbench G4NEOTESTING) -# add_gr_project(STM32G474xE Testbench CUBEMXTESTING) - -# BLINKY Demos -add_gr_project(STM32G474xE BLINKY G4BLINKY) -add_gr_project(STM32U5A9xJ BLINKY U5BLINKY) add_gr_project(STM32L476xG BLINKY L4BLINKY) - add_gr_project(STM32L476xG BLINKY L4HELLO) -add_gr_project(STM32G474xE BLINKY G4HELLO) -add_gr_project(STM32G474xE BLINKY G4ECHO) -# Onboarding Workshops -add_gr_project(STM32G474xE Onboarding W3_G4SPI_Receive) -add_gr_project(STM32G474xE Onboarding W3_G4SPI_Transmit) +# add_project( +# NAME "ECU" +# PATH "ECU" +# SERIES "g4" +# SPECIFIER "g474re" +# HAL_GIT_TAG "v1.2.7" # https://github.com/STMicroelectronics/stm32g4xx-hal-driver/tree/v1.2.7 +# CMSIS_GIT_TAG "v1.2.6" # https://github.com/STMicroelectronics/cmsis-device-g4/tree/v1.2.6 +# CMSIS_MAJOR "5" +# ) + +# add_project( +# NAME "CCU" +# PATH "CCU" +# SERIES "g4" +# SPECIFIER "g474re" +# HAL_GIT_TAG "v1.2.7" # https://github.com/STMicroelectronics/stm32g4xx-hal-driver/tree/v1.2.7 +# CMSIS_GIT_TAG "v1.2.6" # https://github.com/STMicroelectronics/cmsis-device-g4/tree/v1.2.6 +# CMSIS_MAJOR "5" +# ) + +# add_project( +# NAME "CANine" +# PATH "CANine" +# SERIES "g4" +# SPECIFIER "g474re" +# HAL_GIT_TAG "v1.2.7" # https://github.com/STMicroelectronics/stm32g4xx-hal-driver/tree/v1.2.7 +# CMSIS_GIT_TAG "v1.2.6" # https://github.com/STMicroelectronics/cmsis-device-g4/tree/v1.2.6 +# CMSIS_MAJOR "5" +# ) + +# add_project( +# NAME "TireTemp" +# PATH "OutboardSensors/TireTemp" +# SERIES "g4" +# SPECIFIER "g474re" +# HAL_GIT_TAG "v1.2.7" # https://github.com/STMicroelectronics/stm32g4xx-hal-driver/tree/v1.2.7 +# CMSIS_GIT_TAG "v1.2.6" # https://github.com/STMicroelectronics/cmsis-device-g4/tree/v1.2.6 +# CMSIS_MAJOR "5" +# ) + +# add_project( +# NAME "BrakeTemp" +# PATH "OutboardSensors/BrakeTemp" +# SERIES "g4" +# SPECIFIER "g474re" +# HAL_GIT_TAG "v1.2.7" # https://github.com/STMicroelectronics/stm32g4xx-hal-driver/tree/v1.2.7 +# CMSIS_GIT_TAG "v1.2.6" # https://github.com/STMicroelectronics/cmsis-device-g4/tree/v1.2.6 +# CMSIS_MAJOR "5" +# ) diff --git a/CUBEMX.md b/CUBEMX.md index 7c8f81390..61f9e6902 100644 --- a/CUBEMX.md +++ b/CUBEMX.md @@ -1,9 +1,7 @@ -> [!IMPORTANT] -> Note that using a peripheral abstraction (eg our version of CAN) means it will no longer be compatible with CubeMX. As a result please **disable** the peripheral within CubeMX and let the peripheral abstraction handle it. - # STM32CubeMX -This was last verified on version `6.18.0` +> [!IMPORTANT] +> Note that using a peripheral abstraction (eg our old version of CAN) means it will no longer be compatible with CubeMX. As a result please **disable** the peripheral within CubeMX and let the peripheral abstraction handle it. STM32CubeMX2 is a different product that coexists with STM32CubeMX and (as of now) cannot be used. diff --git a/Lib/Peripherals/CAN/TESTING.md b/Lib/Peripherals/CAN/TESTING.md index c6a0acb23..537eac8de 100644 --- a/Lib/Peripherals/CAN/TESTING.md +++ b/Lib/Peripherals/CAN/TESTING.md @@ -43,7 +43,7 @@ These targets allow different test scenarios to be compiled independently. The CAN API and related utilities are included through CMake modules: ``` -include("${lib_path}/Peripherals/CAN/common.cmake") +include("${LIB_PATH}/Peripherals/CAN/common.cmake") ``` These modules provide: @@ -197,10 +197,8 @@ To initialize and run a CAN test: can_stress_test(); ``` -5. Results and diagnostics are printed through `LOGOMATIC`. +1. Results and diagnostics are printed through `LOGOMATIC`. This design allows each CAN test to run as a standalone firmware target while sharing the same CAN API implementation. - - --- diff --git a/Lib/Vendor/TargetFlags/README.md b/Lib/Vendor/TargetFlags/README.md index e714aca70..8967099b5 100644 --- a/Lib/Vendor/TargetFlags/README.md +++ b/Lib/Vendor/TargetFlags/README.md @@ -1,3 +1,39 @@ # Vendor Target Flags -TODO +Each file should be named `stm32**xx.cmake` where `**` is the lowercase series, eg `g4`. + +## Contents + +Each file should have a `target_compile_options` and `target_link_options` targetting `"${TARGET_NAME}"` + +Ensure that each defines at least the following machine dependent options (`-m` flags) + +| Machine Option | Type | Meaning | Preference | +| --- | --- | --- | --- | +| `cpu` | Hardware identifier | Defines the specific CPU and sets `arch` and `tune` automatically | Varies | +| `fpu` | Hardware identifier | Defines the exact FPU, vector extension, percision, register count | Varies | +| `float-abi` | `soft` / `softfp` / `hard` | Floating-point calling convention and ops on hardware or software | `hard` | + +## Advanced + +Set the CPU and FPU flags to match your hardware, and if you have a FPU make sure you use it by specifiying your floating-point ABI to use hardware, and if you are compiling for a Cortex-M microcontroller then you must use the `T32` instruction set + +### CPU and FPU + +CPU and FPU should always be exactly what the chip actually has, you can grab this trivially from the datasheet or look in the git-ignored `cmake` file after CubeMX generates its own (note that we do not use that `cmake` as it is not setup for the monorepo) + +Note that almost all STM32 chips FPUs only support 32-bit floats, this is why we have compiler warnings for double promotion since `double` must use software while `float` can use dedicated hardware. + +### Float ABI + +Determines the application binary interface (ABI) to generate floating point instructions in + +> | ABI Option | Description | +> | --- | --- | +> | `soft` | Soft ABI without FPU hardare: All floating-point operations are handled by the runtime library functions. Values are passed through integer register bank | +> | `softfp` | Soft ABI with FPU hardware: This allows the compiled code to generate codes that directly access the FPU. But, if a calculation needs to use a runtime library function, a soft-float calling convention is used. Values are passed through integer register bank | +> | `hard` | Hard ABI: This allows the compiled code to generate codes that directly accesss the FPU and use FPU-specific calling conventions when calling runtime library functions | + +See [ABI Options](https://support.arm.com/documentation/107656/0101/Registers/Floating-point-registers/Using-Floating-point-extension/ABI-options) from which the above table was approximately copied + +When possible, we always use `hard` because it uses the included FPU which means floating point operations are signficiantly faster. diff --git a/Lib/Vendor/TargetFlags/stm32g4xx.cmake b/Lib/Vendor/TargetFlags/stm32g4xx.cmake index 020b59e5d..1a7cdf773 100644 --- a/Lib/Vendor/TargetFlags/stm32g4xx.cmake +++ b/Lib/Vendor/TargetFlags/stm32g4xx.cmake @@ -1,17 +1,15 @@ target_compile_options( - ${TARGET_NAME} - PRIVATE - -mcpu=cortex-m4 - -mfpu=fpv4-sp-d16 - -mfloat-abi=hard - -mthumb + "${TARGET_NAME}" + PRIVATE + -mcpu=cortex-m4 + -mfpu=fpv4-sp-d16 + -mfloat-abi=hard ) target_link_options( - ${TARGET_NAME} - PRIVATE - -mcpu=cortex-m4 - -mfpu=fpv4-sp-d16 - -mfloat-abi=hard - -mthumb + "${TARGET_NAME}" + PRIVATE + -mcpu=cortex-m4 + -mfpu=fpv4-sp-d16 + -mfloat-abi=hard ) diff --git a/Lib/Vendor/TargetFlags/stm32h5xx.cmake b/Lib/Vendor/TargetFlags/stm32h5xx.cmake index e8ade8126..f7e85a490 100644 --- a/Lib/Vendor/TargetFlags/stm32h5xx.cmake +++ b/Lib/Vendor/TargetFlags/stm32h5xx.cmake @@ -1,8 +1,15 @@ target_compile_options( - ${TARGET_NAME} - PRIVATE - -mcpu=cortex-m33 - -mfpu=fpv5-sp-d16 - -mfloat-abi=hard - -mthumb + "${TARGET_NAME}" + PRIVATE + -mcpu=cortex-m33 + -mfpu=fpv5-sp-d16 + -mfloat-abi=hard +) + +target_link_options( + "${TARGET_NAME}" + PRIVATE + -mcpu=cortex-m33 + -mfpu=fpv5-sp-d16 + -mfloat-abi=hard ) diff --git a/Lib/Vendor/TargetFlags/stm32l4xx.cmake b/Lib/Vendor/TargetFlags/stm32l4xx.cmake index 587463c17..1a7cdf773 100644 --- a/Lib/Vendor/TargetFlags/stm32l4xx.cmake +++ b/Lib/Vendor/TargetFlags/stm32l4xx.cmake @@ -1,8 +1,15 @@ target_compile_options( - ${TARGET_NAME} - PRIVATE - -mcpu=cortex-m4 - -mfpu=fpv4-sp-d16 - -mfloat-abi=hard - -mthumb + "${TARGET_NAME}" + PRIVATE + -mcpu=cortex-m4 + -mfpu=fpv4-sp-d16 + -mfloat-abi=hard +) + +target_link_options( + "${TARGET_NAME}" + PRIVATE + -mcpu=cortex-m4 + -mfpu=fpv4-sp-d16 + -mfloat-abi=hard ) diff --git a/Lib/Vendor/TargetFlags/stm32u5xx.cmake b/Lib/Vendor/TargetFlags/stm32u5xx.cmake index 263580b13..6619b4fa8 100644 --- a/Lib/Vendor/TargetFlags/stm32u5xx.cmake +++ b/Lib/Vendor/TargetFlags/stm32u5xx.cmake @@ -1,8 +1,15 @@ target_compile_options( - ${TARGET_NAME} - PRIVATE - -mcpu=cortex-m33 - -mfpu=fpv4-sp-d16 - -mfloat-abi=hard - -mthumb + "${TARGET_NAME}" + PRIVATE + -mcpu=cortex-m33 + -mfpu=fpv4-sp-d16 + -mfloat-abi=hard +) + +target_link_options( + "${TARGET_NAME}" + PRIVATE + -mcpu=cortex-m33 + -mfpu=fpv4-sp-d16 + -mfloat-abi=hard ) diff --git a/Lib/cmake/cube.cmake b/Lib/cmake/cube.cmake index bb3afee52..65398a48c 100644 --- a/Lib/cmake/cube.cmake +++ b/Lib/cmake/cube.cmake @@ -12,84 +12,84 @@ include(FetchContent) @remark Prefer calling add_project() instead of this function directly ]] function(download_git) - if(NOT ${ARGC} EQUAL 10) - message( - FATAL_ERROR - "You called download_git with an unsupported number of inputs/arguments! Do better please :)" - ) - endif() - - set( - one_value_args - NAME - GIT_REPOSITORY - GIT_TAG - OUTPUT_PATH_VAR - ) - set(multi_value_args TARGET_FOLDER) - unset(DOWNLOAD_GIT_ARG_NAME) - unset(DOWNLOAD_GIT_ARG_GIT_REPOSITORY) - unset(DOWNLOAD_GIT_ARG_GIT_TAG) - unset(DOWNLOAD_GIT_ARG_OUTPUT_PATH_VAR) - unset(DOWNLOAD_GIT_ARG_TARGET_FOLDER) - cmake_parse_arguments( - "DOWNLOAD_GIT_ARG" - "" - "${one_value_args}" - "${multi_value_args}" - ${ARGN} - ) - - message( - STATUS - "This may take a moment, fetching content for ${DOWNLOAD_GIT_ARG_NAME} from ${DOWNLOAD_GIT_ARG_GIT_REPOSITORY} at tag ${DOWNLOAD_GIT_ARG_GIT_TAG}" - ) - - FetchContent_Declare( - "${DOWNLOAD_GIT_ARG_NAME}" - GIT_REPOSITORY "${DOWNLOAD_GIT_ARG_GIT_REPOSITORY}" - GIT_TAG "${DOWNLOAD_GIT_ARG_GIT_TAG}" - GIT_SHALLOW ON - GIT_SUBMODULES - "" - UPDATE_DISCONNECTED TRUE - GIT_CONFIG - "core.sparseCheckout=true" - ) - - string(TOLOWER "${DOWNLOAD_GIT_ARG_NAME}" NAME_LOWER) - - FetchContent_GetProperties(${NAME_LOWER}) - - if(NOT ${NAME_LOWER}_POPULATED) - FetchContent_Populate(${NAME_LOWER}) - separate_arguments( - TARGET_FOLDER_LIST - NATIVE_COMMAND - "${DOWNLOAD_GIT_ARG_TARGET_FOLDER}" - ) - execute_process( - COMMAND - git sparse-checkout set ${TARGET_FOLDER_LIST} - WORKING_DIRECTORY "${${NAME_LOWER}_SOURCE_DIR}" - ) - execute_process( - COMMAND - git checkout - WORKING_DIRECTORY "${${NAME_LOWER}_SOURCE_DIR}" - ) - endif() - - message( - STATUS - "Successfully fetched content for ${DOWNLOAD_GIT_ARG_NAME} from ${DOWNLOAD_GIT_ARG_GIT_REPOSITORY} at tag ${DOWNLOAD_GIT_ARG_GIT_TAG} to ${${DOWNLOAD_GIT_ARG_NAME}_SOURCE_DIR}" - ) - - set( - "${DOWNLOAD_GIT_ARG_OUTPUT_PATH_VAR}" - "${${DOWNLOAD_GIT_ARG_NAME}_SOURCE_DIR}" - ) - return(PROPAGATE "${DOWNLOAD_GIT_ARG_OUTPUT_PATH_VAR}") + if(NOT ${ARGC} EQUAL 10) + message( + FATAL_ERROR + "You called download_git with an unsupported number of inputs/arguments! Do better please :)" + ) + endif() + + set( + one_value_args + NAME + GIT_REPOSITORY + GIT_TAG + OUTPUT_PATH_VAR + ) + set(multi_value_args TARGET_FOLDER) + unset(DOWNLOAD_GIT_ARG_NAME) + unset(DOWNLOAD_GIT_ARG_GIT_REPOSITORY) + unset(DOWNLOAD_GIT_ARG_GIT_TAG) + unset(DOWNLOAD_GIT_ARG_OUTPUT_PATH_VAR) + unset(DOWNLOAD_GIT_ARG_TARGET_FOLDER) + cmake_parse_arguments( + "DOWNLOAD_GIT_ARG" + "" + "${one_value_args}" + "${multi_value_args}" + ${ARGN} + ) + + message( + STATUS + "This may take a moment, fetching content for ${DOWNLOAD_GIT_ARG_NAME} from ${DOWNLOAD_GIT_ARG_GIT_REPOSITORY} at tag ${DOWNLOAD_GIT_ARG_GIT_TAG}" + ) + + FetchContent_Declare( + "${DOWNLOAD_GIT_ARG_NAME}" + GIT_REPOSITORY "${DOWNLOAD_GIT_ARG_GIT_REPOSITORY}" + GIT_TAG "${DOWNLOAD_GIT_ARG_GIT_TAG}" + GIT_SHALLOW ON + GIT_SUBMODULES + "" + UPDATE_DISCONNECTED TRUE + GIT_CONFIG + "core.sparseCheckout=true" + ) + + string(TOLOWER "${DOWNLOAD_GIT_ARG_NAME}" NAME_LOWER) + + FetchContent_GetProperties(${NAME_LOWER}) + + if(NOT ${NAME_LOWER}_POPULATED) + FetchContent_Populate(${NAME_LOWER}) + separate_arguments( + TARGET_FOLDER_LIST + NATIVE_COMMAND + "${DOWNLOAD_GIT_ARG_TARGET_FOLDER}" + ) + execute_process( + COMMAND + git sparse-checkout set ${TARGET_FOLDER_LIST} + WORKING_DIRECTORY "${${NAME_LOWER}_SOURCE_DIR}" + ) + execute_process( + COMMAND + git checkout + WORKING_DIRECTORY "${${NAME_LOWER}_SOURCE_DIR}" + ) + endif() + + message( + STATUS + "Successfully fetched content for ${DOWNLOAD_GIT_ARG_NAME} from ${DOWNLOAD_GIT_ARG_GIT_REPOSITORY} at tag ${DOWNLOAD_GIT_ARG_GIT_TAG} to ${${DOWNLOAD_GIT_ARG_NAME}_SOURCE_DIR}" + ) + + set( + "${DOWNLOAD_GIT_ARG_OUTPUT_PATH_VAR}" + "${${DOWNLOAD_GIT_ARG_NAME}_SOURCE_DIR}" + ) + return(PROPAGATE "${DOWNLOAD_GIT_ARG_OUTPUT_PATH_VAR}") endfunction() #[[ @@ -100,46 +100,50 @@ endfunction() @remark Prefer calling add_project() instead of this function directly ]] function(add_arm_cmsis_core) - if(NOT ${ARGC} EQUAL 4) - message( - FATAL_ERROR - "You called add_arm_cmsis_core with an unsupported number of inputs/arguments! Do better please :)" - ) - endif() - - set( - one_value_args - MAJOR - GIT_TAG - ) - unset(ARM_CMSIS_CORE_ARG_MAJOR) - unset(ARM_CMSIS_CORE_ARG_GIT_TAG) - cmake_parse_arguments("ARM_CMSIS_CORE_ARG" "" "${one_value_args}" "" ${ARGN}) - - if(NOT ARM_CMSIS_CORE_ARG_MAJOR MATCHES "^[0-9]$") - message( - FATAL_ERROR - "MAJOR '${ARM_CMSIS_CORE_ARG_MAJOR}' is not a valid version number (ie '5')" - ) - endif() - - download_git( - NAME "arm_cmsis_${ARM_CMSIS_CORE_ARG_MAJOR}" - GIT_REPOSITORY "https://github.com/arm-software/cmsis_${ARM_CMSIS_CORE_ARG_MAJOR}.git" - GIT_TAG "${ARM_CMSIS_CORE_ARG_GIT_TAG}" - OUTPUT_PATH_VAR ARM_CMSIS_CORE_PATH - TARGET_FOLDER "CMSIS/Core/Include" - ) - message( - STATUS - "Successfully fetched content for ARM CMSIS core version ${ARM_CMSIS_CORE_ARG_MAJOR} from ${ARM_CMSIS_CORE_ARG_GIT_TAG} to ${ARM_CMSIS_CORE_PATH}" - ) - add_library(CMSIS_${ARM_CMSIS_CORE_ARG_MAJOR}_Core INTERFACE) - target_include_directories( - CMSIS_${ARM_CMSIS_CORE_ARG_MAJOR}_Core - INTERFACE - $ - ) + if(NOT ${ARGC} EQUAL 4) + message( + FATAL_ERROR + "You called add_arm_cmsis_core with an unsupported number of inputs/arguments! Do better please :)" + ) + endif() + + set( + one_value_args + MAJOR + GIT_TAG + ) + unset(ARM_CMSIS_CORE_ARG_MAJOR) + unset(ARM_CMSIS_CORE_ARG_GIT_TAG) + cmake_parse_arguments("ARM_CMSIS_CORE_ARG" "" "${one_value_args}" "" ${ARGN}) + + if(NOT ARM_CMSIS_CORE_ARG_MAJOR MATCHES "^[0-9]$") + message( + FATAL_ERROR + "MAJOR '${ARM_CMSIS_CORE_ARG_MAJOR}' is not a valid version number (ie '5')" + ) + endif() + + if(TARGET CMSIS_${ARM_CMSIS_CORE_ARG_MAJOR}_Core) + return() + endif() + + download_git( + NAME "arm_cmsis_${ARM_CMSIS_CORE_ARG_MAJOR}" + GIT_REPOSITORY "https://github.com/arm-software/cmsis_${ARM_CMSIS_CORE_ARG_MAJOR}.git" + GIT_TAG "${ARM_CMSIS_CORE_ARG_GIT_TAG}" + OUTPUT_PATH_VAR ARM_CMSIS_CORE_PATH + TARGET_FOLDER "CMSIS/Core/Include" + ) + message( + STATUS + "Successfully fetched content for ARM CMSIS core version ${ARM_CMSIS_CORE_ARG_MAJOR} from ${ARM_CMSIS_CORE_ARG_GIT_TAG} to ${ARM_CMSIS_CORE_PATH}" + ) + add_library(CMSIS_${ARM_CMSIS_CORE_ARG_MAJOR}_Core INTERFACE) + target_include_directories( + CMSIS_${ARM_CMSIS_CORE_ARG_MAJOR}_Core + INTERFACE + $ + ) endfunction() #[[ @@ -151,89 +155,88 @@ endfunction() @remark Prefer calling add_project() instead of this function directly ]] function(add_arm_cmsis_interface) - if(NOT ${ARGC} EQUAL 6) - message( - FATAL_ERROR - "You called add_arm_cmsis_interface with an unsupported number of inputs/arguments! Do better please :)" - ) - endif() - - set( - one_value_args - SERIES - SPECIFIER - GIT_TAG - ) - unset(ARM_CMSIS_INTERFACE_ARG_SERIES) - unset(ARM_CMSIS_INTERFACE_ARG_SPECIFIER) - unset(ARM_CMSIS_INTERFACE_ARG_GIT_TAG) - cmake_parse_arguments( - "ARM_CMSIS_INTERFACE_ARG" - "" - "${one_value_args}" - "" - ${ARGN} - ) - - message( - VERBOSE - "Adding ARM CMSIS device interface for SERIES '${ARM_CMSIS_INTERFACE_ARG_SERIES}', SPECIFIER '${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}', and GIT_TAG '${ARM_CMSIS_INTERFACE_ARG_GIT_TAG}'" - ) - - string(LENGTH "${ARM_CMSIS_INTERFACE_ARG_SERIES}" SERIES_LENGTH) - if(NOT SERIES_LENGTH EQUAL 2) - message( - FATAL_ERROR - "SERIES '${ARM_CMSIS_INTERFACE_ARG_SERIES}' must be 2 characters long (ie 'g4')" - ) - endif() - string(TOLOWER "${ARM_CMSIS_INTERFACE_ARG_SERIES}" SERIES_LOWER) - - string(LENGTH "${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}" SPECIFIER_LENGTH) - if(SPECIFIER_LENGTH LESS 6) - message( - FATAL_ERROR - "SPECIFIER '${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}' must be at least 6 characters long (ie 'g474re' or 'g474ret6')" - ) - endif() - string(TOLOWER "${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}" SPECIFIER_LOWER) - string(TOUPPER "${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}" SPECIFIER_UPPER) - - string( - FIND "${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}" - "${ARM_CMSIS_INTERFACE_ARG_SERIES}" - SERIES_POSITION_IN_SPECIFIER - ) - if(NOT SERIES_POSITION_IN_SPECIFIER EQUAL 0) - message( - FATAL_ERROR - "SPECIFIER '${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}' must start with SERIES '${ARM_CMSIS_INTERFACE_ARG_SERIES}' at the beginning (eg 'g4' and 'g474ret6')" - ) - endif() - - download_git( - NAME "cmsis_device_${SERIES_LOWER}" - GIT_REPOSITORY "https://github.com/STMicroelectronics/cmsis-device-${SERIES_LOWER}.git" - GIT_TAG ${ARM_CMSIS_INTERFACE_ARG_GIT_TAG} - TARGET_FOLDER "Include" - OUTPUT_PATH_VAR CMSIS_DEVICE_PATH - ) - message( - STATUS - "Successfully fetched content for ARM CMSIS device ${SPECIFIER_UPPER} from ${ARM_CMSIS_INTERFACE_ARG_GIT_TAG} to ${CMSIS_DEVICE_PATH}" - ) - add_library("CMSIS_Device_${SPECIFIER_UPPER}" INTERFACE) - target_include_directories( - "CMSIS_Device_${SPECIFIER_UPPER}" - INTERFACE - $ - ) - target_compile_definitions( - "CMSIS_Device_${SPECIFIER_UPPER}" - INTERFACE - "STM32${SERIES_UPPER}xx" - "USE_HAL_DRIVER" - ) + if(NOT ${ARGC} EQUAL 6) + message( + FATAL_ERROR + "You called add_arm_cmsis_interface with an unsupported number of inputs/arguments! Do better please :)" + ) + endif() + + set( + one_value_args + SERIES + SPECIFIER + GIT_TAG + ) + unset(ARM_CMSIS_INTERFACE_ARG_SERIES) + unset(ARM_CMSIS_INTERFACE_ARG_SPECIFIER) + unset(ARM_CMSIS_INTERFACE_ARG_GIT_TAG) + cmake_parse_arguments( + "ARM_CMSIS_INTERFACE_ARG" + "" + "${one_value_args}" + "" + ${ARGN} + ) + + string(LENGTH "${ARM_CMSIS_INTERFACE_ARG_SERIES}" SERIES_LENGTH) + if(NOT SERIES_LENGTH EQUAL 2) + message( + FATAL_ERROR + "SERIES '${ARM_CMSIS_INTERFACE_ARG_SERIES}' must be 2 characters long (ie 'g4')" + ) + endif() + string(TOLOWER "${ARM_CMSIS_INTERFACE_ARG_SERIES}" SERIES_LOWER) + + string(LENGTH "${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}" SPECIFIER_LENGTH) + if(SPECIFIER_LENGTH LESS 6) + message( + FATAL_ERROR + "SPECIFIER '${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}' must be at least 6 characters long (ie 'g474re' or 'g474ret6')" + ) + endif() + string(TOLOWER "${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}" SPECIFIER_LOWER) + string(TOUPPER "${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}" SPECIFIER_UPPER) + + string( + FIND "${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}" + "${ARM_CMSIS_INTERFACE_ARG_SERIES}" + SERIES_POSITION_IN_SPECIFIER + ) + if(NOT SERIES_POSITION_IN_SPECIFIER EQUAL 0) + message( + FATAL_ERROR + "SPECIFIER '${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}' must start with SERIES '${ARM_CMSIS_INTERFACE_ARG_SERIES}' at the beginning (eg 'g4' and 'g474ret6')" + ) + endif() + + if(TARGET CMSIS_Device_${SPECIFIER_UPPER}) + return() + endif() + + download_git( + NAME "cmsis_device_${SERIES_LOWER}" + GIT_REPOSITORY "https://github.com/STMicroelectronics/cmsis-device-${SERIES_LOWER}.git" + GIT_TAG ${ARM_CMSIS_INTERFACE_ARG_GIT_TAG} + TARGET_FOLDER "Include" + OUTPUT_PATH_VAR CMSIS_DEVICE_PATH + ) + message( + STATUS + "Successfully fetched content for ARM CMSIS device ${SPECIFIER_UPPER} from ${ARM_CMSIS_INTERFACE_ARG_GIT_TAG} to ${CMSIS_DEVICE_PATH}" + ) + add_library("CMSIS_Device_${SPECIFIER_UPPER}" INTERFACE) + target_include_directories( + "CMSIS_Device_${SPECIFIER_UPPER}" + INTERFACE + $ + ) + target_compile_definitions( + "CMSIS_Device_${SPECIFIER_UPPER}" + INTERFACE + "STM32${SERIES_UPPER}xx" + "USE_HAL_DRIVER" + ) endfunction() #[[ @@ -244,63 +247,67 @@ endfunction() @remark Prefer calling add_project() instead of this function directly ]] function(add_stm32_hal_interface) - if(NOT ${ARGC} EQUAL 4) - message( - FATAL_ERROR - "You called add_stm32_hal_interface with an unsupported number of inputs/arguments! Do better please :)" - ) - endif() - - set( - one_value_args - SERIES - GIT_TAG - ) - cmake_parse_arguments("STM32_HAL_ARG" "" "${one_value_args}" "" ${ARGN}) - - message( - VERBOSE - "Adding STM32 HAL driver interface for SERIES '${STM32_HAL_ARG_SERIES}' with GIT_TAG '${STM32_HAL_ARG_GIT_TAG}'" - ) - - string(LENGTH "${STM32_HAL_ARG_SERIES}" SERIES_LENGTH) - if(NOT SERIES_LENGTH EQUAL 2) - message( - FATAL_ERROR - "SERIES '${STM32_HAL_ARG_SERIES}' must be 2 characters long (ie 'g4')" - ) - endif() - - string(TOLOWER "${STM32_HAL_ARG_SERIES}" SERIES_LOWER) - string(TOUPPER "${STM32_HAL_ARG_SERIES}" SERIES_UPPER) - - download_git( - NAME "stm32_hal_driver_${SERIES_LOWER}" - GIT_REPOSITORY "https://github.com/STMicroelectronics/stm32${SERIES_LOWER}xx-hal-driver.git" - GIT_TAG ${STM32_HAL_ARG_GIT_TAG} - TARGET_FOLDER "Inc Src" - OUTPUT_PATH_VAR STM32_HAL_DRIVER_PATH - ) - message( - STATUS - "Successfully fetched content for STM32 HAL driver ${SERIES_UPPER} from ${STM32_HAL_ARG_GIT_TAG} to ${STM32_HAL_DRIVER_PATH}" - ) - add_library("STM32HAL_${SERIES_UPPER}" INTERFACE) - - target_include_directories( - "STM32HAL_${SERIES_UPPER}" - INTERFACE - $ - $ - ) - - file( - GLOB_RECURSE HAL_SOURCES - CONFIGURE_DEPENDS - "${STM32_HAL_DRIVER_PATH}/Src/*.c" - ) - list(FILTER HAL_SOURCES EXCLUDE REGEX ".*_template\.c$") - target_sources("STM32HAL_${SERIES_UPPER}" INTERFACE ${HAL_SOURCES}) + if(NOT ${ARGC} EQUAL 4) + message( + FATAL_ERROR + "You called add_stm32_hal_interface with an unsupported number of inputs/arguments! Do better please :)" + ) + endif() + + set( + one_value_args + SERIES + GIT_TAG + ) + cmake_parse_arguments("STM32_HAL_ARG" "" "${one_value_args}" "" ${ARGN}) + + message( + VERBOSE + "Adding STM32 HAL driver interface for SERIES '${STM32_HAL_ARG_SERIES}' with GIT_TAG '${STM32_HAL_ARG_GIT_TAG}'" + ) + + string(LENGTH "${STM32_HAL_ARG_SERIES}" SERIES_LENGTH) + if(NOT SERIES_LENGTH EQUAL 2) + message( + FATAL_ERROR + "SERIES '${STM32_HAL_ARG_SERIES}' must be 2 characters long (ie 'g4')" + ) + endif() + + string(TOLOWER "${STM32_HAL_ARG_SERIES}" SERIES_LOWER) + string(TOUPPER "${STM32_HAL_ARG_SERIES}" SERIES_UPPER) + + if(TARGET STM32HAL_${SERIES_UPPER}) + return() + endif() + + download_git( + NAME "stm32_hal_driver_${SERIES_LOWER}" + GIT_REPOSITORY "https://github.com/STMicroelectronics/stm32${SERIES_LOWER}xx-hal-driver.git" + GIT_TAG ${STM32_HAL_ARG_GIT_TAG} + TARGET_FOLDER "Inc Src" + OUTPUT_PATH_VAR STM32_HAL_DRIVER_PATH + ) + message( + STATUS + "Successfully fetched content for STM32 HAL driver ${SERIES_UPPER} from ${STM32_HAL_ARG_GIT_TAG} to ${STM32_HAL_DRIVER_PATH}" + ) + add_library("STM32HAL_${SERIES_UPPER}" INTERFACE) + + target_include_directories( + "STM32HAL_${SERIES_UPPER}" + INTERFACE + $ + $ + ) + + file( + GLOB_RECURSE HAL_SOURCES + CONFIGURE_DEPENDS + "${STM32_HAL_DRIVER_PATH}/Src/*.c" + ) + list(FILTER HAL_SOURCES EXCLUDE REGEX ".*_template\.c$") + target_sources("STM32HAL_${SERIES_UPPER}" INTERFACE ${HAL_SOURCES}) endfunction() #[[ @@ -315,90 +322,87 @@ endfunction() @note Link your user code against "${NAME}_USER_CODE" to ensure proper linking with the STM32 HAL and CMSIS libraries ]] function(add_project) - if(NOT ${ARGC} EQUAL 14) - message( - FATAL_ERROR - "You called add_project with an unsupported number of inputs/arguments! Do better please :)" - ) - endif() - - set( - one_value_args - NAME - PATH - SERIES - SPECIFIER - HAL_GIT_TAG - CMSIS_GIT_TAG - CMSIS_MAJOR - ) - cmake_parse_arguments("ARG" "" "${one_value_args}" "" ${ARGN}) - string(TOUPPER "${ARG_SERIES}" SERIES_UPPER) - string(TOLOWER "${ARG_SERIES}" SERIES_LOWER) - string(TOUPPER "${ARG_SPECIFIER}" SPECIFIER_UPPER) - - message( - DEBUG - "Adding project '${ARG_NAME}' at path '${ARG_PATH}' with SERIES '${ARG_SERIES}', SPECIFIER '${ARG_SPECIFIER}', HAL_GIT_TAG '${ARG_HAL_GIT_TAG}', CMSIS_GIT_TAG '${ARG_CMSIS_GIT_TAG}', and CMSIS_MAJOR '${ARG_CMSIS_MAJOR}'" - ) - - add_arm_cmsis_interface( - SERIES ${ARG_SERIES} - SPECIFIER ${ARG_SPECIFIER} - GIT_TAG ${ARG_CMSIS_GIT_TAG} - ) - - add_stm32_hal_interface( - SERIES ${ARG_SERIES} - GIT_TAG ${ARG_HAL_GIT_TAG} - ) - - if(CMAKE_PRESET_NAME STREQUAL "HOOTLTest") - # TODO Later, out of scope for now + if(NOT ${ARGC} EQUAL 14) + message( + FATAL_ERROR + "You called add_project with an unsupported number of inputs/arguments! Do better please :)" + ) + endif() + + set( + one_value_args + NAME + PATH + SERIES + SPECIFIER + HAL_GIT_TAG + CMSIS_GIT_TAG + CMSIS_MAJOR + ) + cmake_parse_arguments("ARG" "" "${one_value_args}" "" ${ARGN}) + string(TOUPPER "${ARG_SERIES}" SERIES_UPPER) + string(TOLOWER "${ARG_SERIES}" SERIES_LOWER) + string(TOUPPER "${ARG_SPECIFIER}" SPECIFIER_UPPER) + + message( + DEBUG + "Adding project '${ARG_NAME}' at path '${ARG_PATH}' with SERIES '${ARG_SERIES}', SPECIFIER '${ARG_SPECIFIER}', HAL_GIT_TAG '${ARG_HAL_GIT_TAG}', CMSIS_GIT_TAG '${ARG_CMSIS_GIT_TAG}', and CMSIS_MAJOR '${ARG_CMSIS_MAJOR}'" + ) + + add_arm_cmsis_interface( + SERIES ${ARG_SERIES} + SPECIFIER ${ARG_SPECIFIER} + GIT_TAG ${ARG_CMSIS_GIT_TAG} + ) + + add_stm32_hal_interface( + SERIES ${ARG_SERIES} + GIT_TAG ${ARG_HAL_GIT_TAG} + ) + + if(CMAKE_PRESET_NAME STREQUAL "HOOTLTest") + # TODO Later, out of scope for now + else() + set(TARGET_NAME "${ARG_NAME}") + message(STATUS "Adding project '${TARGET_NAME}'") + add_executable("${TARGET_NAME}") + + include( + "${PROJECT_SOURCE_DIR}/Lib/Vendor/TargetFlags/stm32${SERIES_LOWER}xx.cmake" + ) + + target_link_libraries( + "${TARGET_NAME}" + PRIVATE + "CMSIS_Device_${SPECIFIER_UPPER}" + "CMSIS_${ARG_CMSIS_MAJOR}_Core" + "STM32HAL_${SERIES_UPPER}" + GLOBALSHARE_LIB + m + ) + + target_link_options( + "${TARGET_NAME}" + PRIVATE + "LINKER:-Map=$/$.map" + ) + + target_compile_definitions( + "${TARGET_NAME}" + PRIVATE + USE_HAL_DRIVER + USE_FULL_LL_DRIVER + STM32${SERIES_UPPER}xx + ) + endif() + + if(DEFINED NODE) + target_compile_definitions("${ARG_NAME}" PRIVATE NODE=${NODE}) + endif() + + if(IS_ABSOLUTE "${ARG_PATH}") + add_subdirectory("${ARG_PATH}") else() - set(TARGET_NAME "${ARG_NAME}") - message(STATUS "Adding project '${TARGET_NAME}'") - add_executable("${TARGET_NAME}") - - include( - "${PROJECT_SOURCE_DIR}/Lib/Vendor/TargetFlags/stm32${SERIES_LOWER}xx.cmake" - ) - - target_compile_options( - "${TARGET_NAME}" - PRIVATE - "${stm32${SERIES_LOWER}xx_flags}" - ) - - target_link_libraries( - "${TARGET_NAME}" - PRIVATE - "CMSIS_Device_${SPECIFIER_UPPER}" - "CMSIS_${ARG_CMSIS_MAJOR}_Core" - "STM32HAL_${SERIES_UPPER}" - # "stm32${SERIES_LOWER}xx_flags" - GLOBALSHARE_LIB - m - ) - - target_link_options( - "${TARGET_NAME}" - PRIVATE - "LINKER:-Map=$/$.map" - ) - - target_compile_definitions( - "${TARGET_NAME}" - PRIVATE - USE_HAL_DRIVER - USE_FULL_LL_DRIVER - STM32${SERIES_UPPER}xx - ) + add_subdirectory("${CMAKE_CURRENT_LIST_DIR}/${ARG_PATH}") endif() - - if(DEFINED NODE) - target_compile_definitions("${ARG_NAME}" PRIVATE NODE=${NODE}) - endif() - - add_subdirectory("${PROJECT_SOURCE_DIR}/${ARG_PATH}") endfunction() diff --git a/Lib/cmake/gcc-arm-none-eabi.cmake b/Lib/cmake/gcc-arm-none-eabi.cmake index 3ab3c4ed1..609036931 100644 --- a/Lib/cmake/gcc-arm-none-eabi.cmake +++ b/Lib/cmake/gcc-arm-none-eabi.cmake @@ -20,11 +20,11 @@ set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) # Linker, Compiler, and Assembler Flags set( CMAKE_C_LINK_FLAGS - "${TARGET_FLAGS} --specs=nano.specs -Wl,--gc-sections -Wl,--start-group -lc -lm -Wl,--end-group -Wl,--print-memory-usage" + "${TARGET_FLAGS} -mthumb --specs=nano.specs -Wl,--gc-sections -Wl,--start-group -lc -lm -Wl,--end-group -Wl,--print-memory-usage" ) set( CMAKE_C_FLAGS - "${TARGET_FLAGS} -Wall -Wextra -Wpedantic -Wvla -Wdouble-promotion -Wmissing-field-initializers -fshort-enums -fdata-sections -ffunction-sections -fstack-usage" + "${TARGET_FLAGS} -mthumb -Wall -Wextra -Wpedantic -Wvla -Wdouble-promotion -Wmissing-field-initializers -fshort-enums -fdata-sections -ffunction-sections -fstack-usage" ) set(CMAKE_ASM_FLAGS "${CMAKE_C_FLAGS} -x assembler-with-cpp -MMD -MP") diff --git a/Testbench/CUBEMXTESTING/Core/Inc/fdcan.h b/Testbench/CUBEMXTESTING/Core/Inc/fdcan.h index 3597c6476..21271cf64 100644 --- a/Testbench/CUBEMXTESTING/Core/Inc/fdcan.h +++ b/Testbench/CUBEMXTESTING/Core/Inc/fdcan.h @@ -55,3 +55,4 @@ void MX_FDCAN3_Init(void); #endif #endif /* __FDCAN_H__ */ + diff --git a/Testbench/CUBEMXTESTING/Core/Inc/gpio.h b/Testbench/CUBEMXTESTING/Core/Inc/gpio.h index 37dcc0a5c..03c2faca5 100644 --- a/Testbench/CUBEMXTESTING/Core/Inc/gpio.h +++ b/Testbench/CUBEMXTESTING/Core/Inc/gpio.h @@ -46,3 +46,4 @@ void MX_GPIO_Init(void); } #endif #endif /*__ GPIO_H__ */ + diff --git a/Testbench/CUBEMXTESTING/Core/Inc/main.h b/Testbench/CUBEMXTESTING/Core/Inc/main.h index cbeced83f..2b50abc31 100644 --- a/Testbench/CUBEMXTESTING/Core/Inc/main.h +++ b/Testbench/CUBEMXTESTING/Core/Inc/main.h @@ -28,16 +28,17 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" + +#include "stm32g4xx_ll_rcc.h" #include "stm32g4xx_ll_bus.h" -#include "stm32g4xx_ll_cortex.h" #include "stm32g4xx_ll_crs.h" -#include "stm32g4xx_ll_dma.h" -#include "stm32g4xx_ll_exti.h" -#include "stm32g4xx_ll_gpio.h" -#include "stm32g4xx_ll_pwr.h" -#include "stm32g4xx_ll_rcc.h" #include "stm32g4xx_ll_system.h" +#include "stm32g4xx_ll_exti.h" +#include "stm32g4xx_ll_cortex.h" #include "stm32g4xx_ll_utils.h" +#include "stm32g4xx_ll_pwr.h" +#include "stm32g4xx_ll_dma.h" +#include "stm32g4xx_ll_gpio.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ diff --git a/Testbench/CUBEMXTESTING/Core/Inc/stm32_assert.h b/Testbench/CUBEMXTESTING/Core/Inc/stm32_assert.h index 92460620f..e645b21ee 100644 --- a/Testbench/CUBEMXTESTING/Core/Inc/stm32_assert.h +++ b/Testbench/CUBEMXTESTING/Core/Inc/stm32_assert.h @@ -29,15 +29,15 @@ extern "C" { /* Exported constants --------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT +#ifdef USE_FULL_ASSERT /** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) /* Exported functions ------------------------------------------------------- */ void assert_failed(uint8_t *file, uint32_t line); @@ -50,3 +50,4 @@ void assert_failed(uint8_t *file, uint32_t line); #endif #endif /* __STM32_ASSERT_H */ + diff --git a/Testbench/CUBEMXTESTING/Core/Inc/stm32g4xx_hal_conf.h b/Testbench/CUBEMXTESTING/Core/Inc/stm32g4xx_hal_conf.h index d12d585bd..e4db34d37 100644 --- a/Testbench/CUBEMXTESTING/Core/Inc/stm32g4xx_hal_conf.h +++ b/Testbench/CUBEMXTESTING/Core/Inc/stm32g4xx_hal_conf.h @@ -23,7 +23,7 @@ #define STM32G4xx_HAL_CONF_H #ifdef __cplusplus -extern "C" { + extern "C" { #endif /* Exported types ------------------------------------------------------------*/ @@ -31,12 +31,12 @@ extern "C" { /* ########################## Module Selection ############################## */ /** - * @brief This is the list of modules to be used in the HAL driver - */ + * @brief This is the list of modules to be used in the HAL driver + */ #define HAL_MODULE_ENABLED -/*#define HAL_ADC_MODULE_ENABLED */ + /*#define HAL_ADC_MODULE_ENABLED */ /*#define HAL_COMP_MODULE_ENABLED */ /*#define HAL_CORDIC_MODULE_ENABLED */ /*#define HAL_CRC_MODULE_ENABLED */ @@ -76,124 +76,123 @@ extern "C" { /* ########################## Register Callbacks selection ############################## */ /** - * @brief This is the list of modules where register callback can be used - */ -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U -#define USE_HAL_COMP_REGISTER_CALLBACKS 0U -#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U -#define USE_HAL_EXTI_REGISTER_CALLBACKS 0U -#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U -#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U -#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U -#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U -#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U -#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U -#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U -#define USE_HAL_UART_REGISTER_CALLBACKS 0U -#define USE_HAL_USART_REGISTER_CALLBACKS 0U -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U + * @brief This is the list of modules where register callback can be used + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U +#define USE_HAL_COMP_REGISTER_CALLBACKS 0U +#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U +#define USE_HAL_EXTI_REGISTER_CALLBACKS 0U +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U +#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U +#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U +#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U +#define USE_HAL_UART_REGISTER_CALLBACKS 0U +#define USE_HAL_USART_REGISTER_CALLBACKS 0U +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* ########################## Oscillator Values adaptation ####################*/ /** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined(HSE_VALUE) -#define HSE_VALUE (16000000UL) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined(HSE_STARTUP_TIMEOUT) -#define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE (16000000UL) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ /** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined(HSI_VALUE) -#define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ /** - * @brief Internal High Speed oscillator (HSI48) value for USB FS and RNG. - * This internal oscillator is mainly dedicated to provide a high precision clock to - * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. - * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency - * which is subject to manufacturing process variations. - */ -#if !defined(HSI48_VALUE) -#define HSI48_VALUE \ - (48000000UL) /*!< Value of the Internal High Speed oscillator for USB FS/RNG in Hz. \ - The real value my vary depending on manufacturing process variations.*/ -#endif /* HSI48_VALUE */ + * @brief Internal High Speed oscillator (HSI48) value for USB FS and RNG. + * This internal oscillator is mainly dedicated to provide a high precision clock to + * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. + * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency + * which is subject to manufacturing process variations. + */ +#if !defined (HSI48_VALUE) + #define HSI48_VALUE (48000000UL) /*!< Value of the Internal High Speed oscillator for USB FS/RNG in Hz. + The real value my vary depending on manufacturing process variations.*/ +#endif /* HSI48_VALUE */ /** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined(LSI_VALUE) + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature.*/ -#define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/ -#endif /* LSI_VALUE */ +#define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /** - * @brief External Low Speed oscillator (LSE) value. - * This value is used by the UART, RTC HAL module to compute the system frequency - */ -#if !defined(LSE_VALUE) -#define LSE_VALUE (32768UL) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) +#define LSE_VALUE (32768UL) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ -#if !defined(LSE_STARTUP_TIMEOUT) -#define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ +#if !defined (LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ /** - * @brief External clock source for I2S and SAI peripherals - * This value is used by the I2S and SAI HAL modules to compute the I2S and SAI clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined(EXTERNAL_CLOCK_VALUE) -#define EXTERNAL_CLOCK_VALUE (12288000UL) /*!< Value of the External oscillator in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ + * @brief External clock source for I2S and SAI peripherals + * This value is used by the I2S and SAI HAL modules to compute the I2S and SAI clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) +#define EXTERNAL_CLOCK_VALUE (12288000UL) /*!< Value of the External oscillator in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ /* Tip: To avoid modifying this file each time you need to use different HSE, === you can define the HSE value in your toolchain compiler preprocessor. */ /* ########################### System Configuration ######################### */ /** - * @brief This is the HAL system configuration section - */ + * @brief This is the HAL system configuration section + */ -#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority (lowest by default) */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 0U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U +#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority (lowest by default) */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 0U +#define INSTRUCTION_CACHE_ENABLE 1U +#define DATA_CACHE_ENABLE 1U /* ########################## Assert Selection ############################## */ /** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -#define USE_FULL_ASSERT 1U + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ + #define USE_FULL_ASSERT 1U /* ################## SPI peripheral configuration ########################## */ @@ -202,12 +201,12 @@ The real value may vary depending on the variations in voltage and temperature.* * Deactivated: CRC code cleaned from driver */ -#define USE_SPI_CRC 0U +#define USE_SPI_CRC 0U /* Includes ------------------------------------------------------------------*/ /** - * @brief Include module's header file - */ + * @brief Include module's header file + */ #ifdef HAL_RCC_MODULE_ENABLED #include "stm32g4xx_hal_rcc.h" @@ -358,15 +357,15 @@ The real value may vary depending on the variations in voltage and temperature.* #endif /* HAL_WWDG_MODULE_ENABLED */ /* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT +#ifdef USE_FULL_ASSERT /** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) /* Exported functions ------------------------------------------------------- */ void assert_failed(uint8_t *file, uint32_t line); diff --git a/Testbench/CUBEMXTESTING/Core/Inc/tim.h b/Testbench/CUBEMXTESTING/Core/Inc/tim.h index 2d20bd560..b90657cf4 100644 --- a/Testbench/CUBEMXTESTING/Core/Inc/tim.h +++ b/Testbench/CUBEMXTESTING/Core/Inc/tim.h @@ -49,3 +49,4 @@ void MX_TIM5_Init(void); #endif #endif /* __TIM_H__ */ + diff --git a/Testbench/CUBEMXTESTING/Core/Inc/usart.h b/Testbench/CUBEMXTESTING/Core/Inc/usart.h index bdec0c9cb..49dd0cccc 100644 --- a/Testbench/CUBEMXTESTING/Core/Inc/usart.h +++ b/Testbench/CUBEMXTESTING/Core/Inc/usart.h @@ -49,3 +49,4 @@ void MX_LPUART1_UART_Init(void); #endif #endif /* __USART_H__ */ + diff --git a/Testbench/CUBEMXTESTING/Core/Src/fdcan.c b/Testbench/CUBEMXTESTING/Core/Src/fdcan.c index 30b3c9dc1..08b2a1b8a 100644 --- a/Testbench/CUBEMXTESTING/Core/Src/fdcan.c +++ b/Testbench/CUBEMXTESTING/Core/Src/fdcan.c @@ -32,281 +32,298 @@ FDCAN_HandleTypeDef hfdcan3; void MX_FDCAN1_Init(void) { - /* USER CODE BEGIN FDCAN1_Init 0 */ - - /* USER CODE END FDCAN1_Init 0 */ - - /* USER CODE BEGIN FDCAN1_Init 1 */ - - /* USER CODE END FDCAN1_Init 1 */ - hfdcan1.Instance = FDCAN1; - hfdcan1.Init.ClockDivider = FDCAN_CLOCK_DIV1; - hfdcan1.Init.FrameFormat = FDCAN_FRAME_CLASSIC; - hfdcan1.Init.Mode = FDCAN_MODE_INTERNAL_LOOPBACK; - hfdcan1.Init.AutoRetransmission = ENABLE; - hfdcan1.Init.TransmitPause = DISABLE; - hfdcan1.Init.ProtocolException = ENABLE; - hfdcan1.Init.NominalPrescaler = 1; - hfdcan1.Init.NominalSyncJumpWidth = 16; - hfdcan1.Init.NominalTimeSeg1 = 119; - hfdcan1.Init.NominalTimeSeg2 = 40; - hfdcan1.Init.DataPrescaler = 8; - hfdcan1.Init.DataSyncJumpWidth = 16; - hfdcan1.Init.DataTimeSeg1 = 14; - hfdcan1.Init.DataTimeSeg2 = 5; - hfdcan1.Init.StdFiltersNbr = 0; - hfdcan1.Init.ExtFiltersNbr = 2; - hfdcan1.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; - if (HAL_FDCAN_Init(&hfdcan1) != HAL_OK) { - Error_Handler(); - } - /* USER CODE BEGIN FDCAN1_Init 2 */ - - /* USER CODE END FDCAN1_Init 2 */ + /* USER CODE BEGIN FDCAN1_Init 0 */ + + /* USER CODE END FDCAN1_Init 0 */ + + /* USER CODE BEGIN FDCAN1_Init 1 */ + + /* USER CODE END FDCAN1_Init 1 */ + hfdcan1.Instance = FDCAN1; + hfdcan1.Init.ClockDivider = FDCAN_CLOCK_DIV1; + hfdcan1.Init.FrameFormat = FDCAN_FRAME_CLASSIC; + hfdcan1.Init.Mode = FDCAN_MODE_INTERNAL_LOOPBACK; + hfdcan1.Init.AutoRetransmission = ENABLE; + hfdcan1.Init.TransmitPause = DISABLE; + hfdcan1.Init.ProtocolException = ENABLE; + hfdcan1.Init.NominalPrescaler = 1; + hfdcan1.Init.NominalSyncJumpWidth = 16; + hfdcan1.Init.NominalTimeSeg1 = 119; + hfdcan1.Init.NominalTimeSeg2 = 40; + hfdcan1.Init.DataPrescaler = 8; + hfdcan1.Init.DataSyncJumpWidth = 16; + hfdcan1.Init.DataTimeSeg1 = 14; + hfdcan1.Init.DataTimeSeg2 = 5; + hfdcan1.Init.StdFiltersNbr = 0; + hfdcan1.Init.ExtFiltersNbr = 2; + hfdcan1.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; + if (HAL_FDCAN_Init(&hfdcan1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN FDCAN1_Init 2 */ + + /* USER CODE END FDCAN1_Init 2 */ + } /* FDCAN2 init function */ void MX_FDCAN2_Init(void) { - /* USER CODE BEGIN FDCAN2_Init 0 */ - - /* USER CODE END FDCAN2_Init 0 */ - - /* USER CODE BEGIN FDCAN2_Init 1 */ - - /* USER CODE END FDCAN2_Init 1 */ - hfdcan2.Instance = FDCAN2; - hfdcan2.Init.ClockDivider = FDCAN_CLOCK_DIV1; - hfdcan2.Init.FrameFormat = FDCAN_FRAME_CLASSIC; - hfdcan2.Init.Mode = FDCAN_MODE_INTERNAL_LOOPBACK; - hfdcan2.Init.AutoRetransmission = ENABLE; - hfdcan2.Init.TransmitPause = DISABLE; - hfdcan2.Init.ProtocolException = ENABLE; - hfdcan2.Init.NominalPrescaler = 1; - hfdcan2.Init.NominalSyncJumpWidth = 16; - hfdcan2.Init.NominalTimeSeg1 = 119; - hfdcan2.Init.NominalTimeSeg2 = 40; - hfdcan2.Init.DataPrescaler = 8; - hfdcan2.Init.DataSyncJumpWidth = 16; - hfdcan2.Init.DataTimeSeg1 = 14; - hfdcan2.Init.DataTimeSeg2 = 5; - hfdcan2.Init.StdFiltersNbr = 0; - hfdcan2.Init.ExtFiltersNbr = 2; - hfdcan2.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; - if (HAL_FDCAN_Init(&hfdcan2) != HAL_OK) { - Error_Handler(); - } - /* USER CODE BEGIN FDCAN2_Init 2 */ - - /* USER CODE END FDCAN2_Init 2 */ + /* USER CODE BEGIN FDCAN2_Init 0 */ + + /* USER CODE END FDCAN2_Init 0 */ + + /* USER CODE BEGIN FDCAN2_Init 1 */ + + /* USER CODE END FDCAN2_Init 1 */ + hfdcan2.Instance = FDCAN2; + hfdcan2.Init.ClockDivider = FDCAN_CLOCK_DIV1; + hfdcan2.Init.FrameFormat = FDCAN_FRAME_CLASSIC; + hfdcan2.Init.Mode = FDCAN_MODE_INTERNAL_LOOPBACK; + hfdcan2.Init.AutoRetransmission = ENABLE; + hfdcan2.Init.TransmitPause = DISABLE; + hfdcan2.Init.ProtocolException = ENABLE; + hfdcan2.Init.NominalPrescaler = 1; + hfdcan2.Init.NominalSyncJumpWidth = 16; + hfdcan2.Init.NominalTimeSeg1 = 119; + hfdcan2.Init.NominalTimeSeg2 = 40; + hfdcan2.Init.DataPrescaler = 8; + hfdcan2.Init.DataSyncJumpWidth = 16; + hfdcan2.Init.DataTimeSeg1 = 14; + hfdcan2.Init.DataTimeSeg2 = 5; + hfdcan2.Init.StdFiltersNbr = 0; + hfdcan2.Init.ExtFiltersNbr = 2; + hfdcan2.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; + if (HAL_FDCAN_Init(&hfdcan2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN FDCAN2_Init 2 */ + + /* USER CODE END FDCAN2_Init 2 */ + } /* FDCAN3 init function */ void MX_FDCAN3_Init(void) { - /* USER CODE BEGIN FDCAN3_Init 0 */ - - /* USER CODE END FDCAN3_Init 0 */ - - /* USER CODE BEGIN FDCAN3_Init 1 */ - - /* USER CODE END FDCAN3_Init 1 */ - hfdcan3.Instance = FDCAN3; - hfdcan3.Init.ClockDivider = FDCAN_CLOCK_DIV1; - hfdcan3.Init.FrameFormat = FDCAN_FRAME_CLASSIC; - hfdcan3.Init.Mode = FDCAN_MODE_INTERNAL_LOOPBACK; - hfdcan3.Init.AutoRetransmission = DISABLE; - hfdcan3.Init.TransmitPause = DISABLE; - hfdcan3.Init.ProtocolException = DISABLE; - hfdcan3.Init.NominalPrescaler = 16; - hfdcan3.Init.NominalSyncJumpWidth = 1; - hfdcan3.Init.NominalTimeSeg1 = 1; - hfdcan3.Init.NominalTimeSeg2 = 1; - hfdcan3.Init.DataPrescaler = 1; - hfdcan3.Init.DataSyncJumpWidth = 1; - hfdcan3.Init.DataTimeSeg1 = 1; - hfdcan3.Init.DataTimeSeg2 = 1; - hfdcan3.Init.StdFiltersNbr = 0; - hfdcan3.Init.ExtFiltersNbr = 0; - hfdcan3.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; - if (HAL_FDCAN_Init(&hfdcan3) != HAL_OK) { - Error_Handler(); - } - /* USER CODE BEGIN FDCAN3_Init 2 */ - - /* USER CODE END FDCAN3_Init 2 */ + /* USER CODE BEGIN FDCAN3_Init 0 */ + + /* USER CODE END FDCAN3_Init 0 */ + + /* USER CODE BEGIN FDCAN3_Init 1 */ + + /* USER CODE END FDCAN3_Init 1 */ + hfdcan3.Instance = FDCAN3; + hfdcan3.Init.ClockDivider = FDCAN_CLOCK_DIV1; + hfdcan3.Init.FrameFormat = FDCAN_FRAME_CLASSIC; + hfdcan3.Init.Mode = FDCAN_MODE_INTERNAL_LOOPBACK; + hfdcan3.Init.AutoRetransmission = DISABLE; + hfdcan3.Init.TransmitPause = DISABLE; + hfdcan3.Init.ProtocolException = DISABLE; + hfdcan3.Init.NominalPrescaler = 16; + hfdcan3.Init.NominalSyncJumpWidth = 1; + hfdcan3.Init.NominalTimeSeg1 = 1; + hfdcan3.Init.NominalTimeSeg2 = 1; + hfdcan3.Init.DataPrescaler = 1; + hfdcan3.Init.DataSyncJumpWidth = 1; + hfdcan3.Init.DataTimeSeg1 = 1; + hfdcan3.Init.DataTimeSeg2 = 1; + hfdcan3.Init.StdFiltersNbr = 0; + hfdcan3.Init.ExtFiltersNbr = 0; + hfdcan3.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; + if (HAL_FDCAN_Init(&hfdcan3) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN FDCAN3_Init 2 */ + + /* USER CODE END FDCAN3_Init 2 */ + } -static uint32_t HAL_RCC_FDCAN_CLK_ENABLED = 0; +static uint32_t HAL_RCC_FDCAN_CLK_ENABLED=0; -void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *fdcanHandle) +void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* fdcanHandle) { - GPIO_InitTypeDef GPIO_InitStruct = {0}; - if (fdcanHandle->Instance == FDCAN1) { - /* USER CODE BEGIN FDCAN1_MspInit 0 */ - - /* USER CODE END FDCAN1_MspInit 0 */ - LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_PCLK1); - - /* FDCAN1 clock enable */ - HAL_RCC_FDCAN_CLK_ENABLED++; - if (HAL_RCC_FDCAN_CLK_ENABLED == 1) { - __HAL_RCC_FDCAN_CLK_ENABLE(); - } - - __HAL_RCC_GPIOB_CLK_ENABLE(); - /**FDCAN1 GPIO Configuration - PB8-BOOT0 ------> FDCAN1_RX - PB9 ------> FDCAN1_TX - */ - GPIO_InitStruct.Pin = GPIO_PIN_8 | GPIO_PIN_9; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN1; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /* FDCAN1 interrupt Init */ - HAL_NVIC_SetPriority(FDCAN1_IT0_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(FDCAN1_IT0_IRQn); - /* USER CODE BEGIN FDCAN1_MspInit 1 */ - - /* USER CODE END FDCAN1_MspInit 1 */ - } else if (fdcanHandle->Instance == FDCAN2) { - /* USER CODE BEGIN FDCAN2_MspInit 0 */ - - /* USER CODE END FDCAN2_MspInit 0 */ - - LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_PCLK1); - - /* FDCAN2 clock enable */ - HAL_RCC_FDCAN_CLK_ENABLED++; - if (HAL_RCC_FDCAN_CLK_ENABLED == 1) { - __HAL_RCC_FDCAN_CLK_ENABLE(); - } - - __HAL_RCC_GPIOB_CLK_ENABLE(); - /**FDCAN2 GPIO Configuration - PB12 ------> FDCAN2_RX - PB13 ------> FDCAN2_TX - */ - GPIO_InitStruct.Pin = GPIO_PIN_12 | GPIO_PIN_13; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN2; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /* FDCAN2 interrupt Init */ - HAL_NVIC_SetPriority(FDCAN2_IT0_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(FDCAN2_IT0_IRQn); - /* USER CODE BEGIN FDCAN2_MspInit 1 */ - - /* USER CODE END FDCAN2_MspInit 1 */ - } else if (fdcanHandle->Instance == FDCAN3) { - /* USER CODE BEGIN FDCAN3_MspInit 0 */ - - /* USER CODE END FDCAN3_MspInit 0 */ - - LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_PCLK1); - - /* FDCAN3 clock enable */ - HAL_RCC_FDCAN_CLK_ENABLED++; - if (HAL_RCC_FDCAN_CLK_ENABLED == 1) { - __HAL_RCC_FDCAN_CLK_ENABLE(); - } - - __HAL_RCC_GPIOA_CLK_ENABLE(); - /**FDCAN3 GPIO Configuration - PA8 ------> FDCAN3_RX - PA15 ------> FDCAN3_TX - */ - GPIO_InitStruct.Pin = GPIO_PIN_8 | GPIO_PIN_15; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF11_FDCAN3; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /* FDCAN3 interrupt Init */ - HAL_NVIC_SetPriority(FDCAN3_IT0_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(FDCAN3_IT0_IRQn); - /* USER CODE BEGIN FDCAN3_MspInit 1 */ - - /* USER CODE END FDCAN3_MspInit 1 */ - } + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(fdcanHandle->Instance==FDCAN1) + { + /* USER CODE BEGIN FDCAN1_MspInit 0 */ + + /* USER CODE END FDCAN1_MspInit 0 */ + LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_PCLK1); + + /* FDCAN1 clock enable */ + HAL_RCC_FDCAN_CLK_ENABLED++; + if(HAL_RCC_FDCAN_CLK_ENABLED==1){ + __HAL_RCC_FDCAN_CLK_ENABLE(); + } + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**FDCAN1 GPIO Configuration + PB8-BOOT0 ------> FDCAN1_RX + PB9 ------> FDCAN1_TX + */ + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN1; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* FDCAN1 interrupt Init */ + HAL_NVIC_SetPriority(FDCAN1_IT0_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(FDCAN1_IT0_IRQn); + /* USER CODE BEGIN FDCAN1_MspInit 1 */ + + /* USER CODE END FDCAN1_MspInit 1 */ + } + else if(fdcanHandle->Instance==FDCAN2) + { + /* USER CODE BEGIN FDCAN2_MspInit 0 */ + + /* USER CODE END FDCAN2_MspInit 0 */ + + LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_PCLK1); + + /* FDCAN2 clock enable */ + HAL_RCC_FDCAN_CLK_ENABLED++; + if(HAL_RCC_FDCAN_CLK_ENABLED==1){ + __HAL_RCC_FDCAN_CLK_ENABLE(); + } + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**FDCAN2 GPIO Configuration + PB12 ------> FDCAN2_RX + PB13 ------> FDCAN2_TX + */ + GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_13; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN2; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* FDCAN2 interrupt Init */ + HAL_NVIC_SetPriority(FDCAN2_IT0_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(FDCAN2_IT0_IRQn); + /* USER CODE BEGIN FDCAN2_MspInit 1 */ + + /* USER CODE END FDCAN2_MspInit 1 */ + } + else if(fdcanHandle->Instance==FDCAN3) + { + /* USER CODE BEGIN FDCAN3_MspInit 0 */ + + /* USER CODE END FDCAN3_MspInit 0 */ + + LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_PCLK1); + + /* FDCAN3 clock enable */ + HAL_RCC_FDCAN_CLK_ENABLED++; + if(HAL_RCC_FDCAN_CLK_ENABLED==1){ + __HAL_RCC_FDCAN_CLK_ENABLE(); + } + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**FDCAN3 GPIO Configuration + PA8 ------> FDCAN3_RX + PA15 ------> FDCAN3_TX + */ + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF11_FDCAN3; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* FDCAN3 interrupt Init */ + HAL_NVIC_SetPriority(FDCAN3_IT0_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(FDCAN3_IT0_IRQn); + /* USER CODE BEGIN FDCAN3_MspInit 1 */ + + /* USER CODE END FDCAN3_MspInit 1 */ + } } -void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *fdcanHandle) +void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef* fdcanHandle) { - if (fdcanHandle->Instance == FDCAN1) { - /* USER CODE BEGIN FDCAN1_MspDeInit 0 */ - - /* USER CODE END FDCAN1_MspDeInit 0 */ - /* Peripheral clock disable */ - HAL_RCC_FDCAN_CLK_ENABLED--; - if (HAL_RCC_FDCAN_CLK_ENABLED == 0) { - __HAL_RCC_FDCAN_CLK_DISABLE(); - } - - /**FDCAN1 GPIO Configuration - PB8-BOOT0 ------> FDCAN1_RX - PB9 ------> FDCAN1_TX - */ - HAL_GPIO_DeInit(GPIOB, GPIO_PIN_8 | GPIO_PIN_9); - - /* FDCAN1 interrupt Deinit */ - HAL_NVIC_DisableIRQ(FDCAN1_IT0_IRQn); - /* USER CODE BEGIN FDCAN1_MspDeInit 1 */ - - /* USER CODE END FDCAN1_MspDeInit 1 */ - } else if (fdcanHandle->Instance == FDCAN2) { - /* USER CODE BEGIN FDCAN2_MspDeInit 0 */ - - /* USER CODE END FDCAN2_MspDeInit 0 */ - /* Peripheral clock disable */ - HAL_RCC_FDCAN_CLK_ENABLED--; - if (HAL_RCC_FDCAN_CLK_ENABLED == 0) { - __HAL_RCC_FDCAN_CLK_DISABLE(); - } - - /**FDCAN2 GPIO Configuration - PB12 ------> FDCAN2_RX - PB13 ------> FDCAN2_TX - */ - HAL_GPIO_DeInit(GPIOB, GPIO_PIN_12 | GPIO_PIN_13); - - /* FDCAN2 interrupt Deinit */ - HAL_NVIC_DisableIRQ(FDCAN2_IT0_IRQn); - /* USER CODE BEGIN FDCAN2_MspDeInit 1 */ - - /* USER CODE END FDCAN2_MspDeInit 1 */ - } else if (fdcanHandle->Instance == FDCAN3) { - /* USER CODE BEGIN FDCAN3_MspDeInit 0 */ - - /* USER CODE END FDCAN3_MspDeInit 0 */ - /* Peripheral clock disable */ - HAL_RCC_FDCAN_CLK_ENABLED--; - if (HAL_RCC_FDCAN_CLK_ENABLED == 0) { - __HAL_RCC_FDCAN_CLK_DISABLE(); - } - - /**FDCAN3 GPIO Configuration - PA8 ------> FDCAN3_RX - PA15 ------> FDCAN3_TX - */ - HAL_GPIO_DeInit(GPIOA, GPIO_PIN_8 | GPIO_PIN_15); - - /* FDCAN3 interrupt Deinit */ - HAL_NVIC_DisableIRQ(FDCAN3_IT0_IRQn); - /* USER CODE BEGIN FDCAN3_MspDeInit 1 */ - - /* USER CODE END FDCAN3_MspDeInit 1 */ - } + if(fdcanHandle->Instance==FDCAN1) + { + /* USER CODE BEGIN FDCAN1_MspDeInit 0 */ + + /* USER CODE END FDCAN1_MspDeInit 0 */ + /* Peripheral clock disable */ + HAL_RCC_FDCAN_CLK_ENABLED--; + if(HAL_RCC_FDCAN_CLK_ENABLED==0){ + __HAL_RCC_FDCAN_CLK_DISABLE(); + } + + /**FDCAN1 GPIO Configuration + PB8-BOOT0 ------> FDCAN1_RX + PB9 ------> FDCAN1_TX + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_8|GPIO_PIN_9); + + /* FDCAN1 interrupt Deinit */ + HAL_NVIC_DisableIRQ(FDCAN1_IT0_IRQn); + /* USER CODE BEGIN FDCAN1_MspDeInit 1 */ + + /* USER CODE END FDCAN1_MspDeInit 1 */ + } + else if(fdcanHandle->Instance==FDCAN2) + { + /* USER CODE BEGIN FDCAN2_MspDeInit 0 */ + + /* USER CODE END FDCAN2_MspDeInit 0 */ + /* Peripheral clock disable */ + HAL_RCC_FDCAN_CLK_ENABLED--; + if(HAL_RCC_FDCAN_CLK_ENABLED==0){ + __HAL_RCC_FDCAN_CLK_DISABLE(); + } + + /**FDCAN2 GPIO Configuration + PB12 ------> FDCAN2_RX + PB13 ------> FDCAN2_TX + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_12|GPIO_PIN_13); + + /* FDCAN2 interrupt Deinit */ + HAL_NVIC_DisableIRQ(FDCAN2_IT0_IRQn); + /* USER CODE BEGIN FDCAN2_MspDeInit 1 */ + + /* USER CODE END FDCAN2_MspDeInit 1 */ + } + else if(fdcanHandle->Instance==FDCAN3) + { + /* USER CODE BEGIN FDCAN3_MspDeInit 0 */ + + /* USER CODE END FDCAN3_MspDeInit 0 */ + /* Peripheral clock disable */ + HAL_RCC_FDCAN_CLK_ENABLED--; + if(HAL_RCC_FDCAN_CLK_ENABLED==0){ + __HAL_RCC_FDCAN_CLK_DISABLE(); + } + + /**FDCAN3 GPIO Configuration + PA8 ------> FDCAN3_RX + PA15 ------> FDCAN3_TX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_8|GPIO_PIN_15); + + /* FDCAN3 interrupt Deinit */ + HAL_NVIC_DisableIRQ(FDCAN3_IT0_IRQn); + /* USER CODE BEGIN FDCAN3_MspDeInit 1 */ + + /* USER CODE END FDCAN3_MspDeInit 1 */ + } } /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ + diff --git a/Testbench/CUBEMXTESTING/Core/Src/gpio.c b/Testbench/CUBEMXTESTING/Core/Src/gpio.c index 4d07c7993..96b5c07ab 100644 --- a/Testbench/CUBEMXTESTING/Core/Src/gpio.c +++ b/Testbench/CUBEMXTESTING/Core/Src/gpio.c @@ -33,277 +33,278 @@ /* USER CODE END 1 */ /** Configure pins as - * Analog - * Input - * Output - * EVENT_OUT - * EXTI - * Free pins are configured automatically as Analog (this feature is enabled through - * the Code Generation settings) - */ + * Analog + * Input + * Output + * EVENT_OUT + * EXTI + * Free pins are configured automatically as Analog (this feature is enabled through + * the Code Generation settings) +*/ void MX_GPIO_Init(void) { - LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; - - /* GPIO Ports Clock Enable */ - LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOC); - LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOF); - LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOG); - LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA); - LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB); - LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOD); - - /**/ - LL_GPIO_ResetOutputPin(USER_LED_GPIO_Port, USER_LED_Pin); - - /**/ - GPIO_InitStruct.Pin = USER_BUTTON_Pin; - GPIO_InitStruct.Mode = LL_GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(USER_BUTTON_GPIO_Port, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_14; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_15; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_0; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOF, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_1; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOF, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_10; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOG, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_0; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_1; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_2; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_3; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_0; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_1; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_4; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = USER_LED_Pin; - GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT; - GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(USER_LED_GPIO_Port, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_6; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_7; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_4; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_5; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_0; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_1; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_2; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_10; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_11; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_14; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_15; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_6; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_7; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_8; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_9; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_9; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_10; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_11; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_12; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_10; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_11; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_12; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_2; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOD, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_4; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_5; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_6; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_7; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* GPIO Ports Clock Enable */ + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOC); + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOF); + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOG); + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA); + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB); + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOD); + + /**/ + LL_GPIO_ResetOutputPin(USER_LED_GPIO_Port, USER_LED_Pin); + + /**/ + GPIO_InitStruct.Pin = USER_BUTTON_Pin; + GPIO_InitStruct.Mode = LL_GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(USER_BUTTON_GPIO_Port, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_14; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_15; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_0; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_1; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_10; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_0; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_1; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_2; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_3; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_0; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_1; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_4; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = USER_LED_Pin; + GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(USER_LED_GPIO_Port, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_6; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_7; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_4; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_5; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_0; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_1; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_2; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_10; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_11; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_14; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_15; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_6; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_7; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_8; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_9; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_9; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_10; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_11; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_12; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_10; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_11; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_12; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_2; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_4; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_5; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_6; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_7; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + } /* USER CODE BEGIN 2 */ diff --git a/Testbench/CUBEMXTESTING/Core/Src/main.c b/Testbench/CUBEMXTESTING/Core/Src/main.c index 7344dd05d..d201e4a35 100644 --- a/Testbench/CUBEMXTESTING/Core/Src/main.c +++ b/Testbench/CUBEMXTESTING/Core/Src/main.c @@ -18,11 +18,10 @@ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "main.h" - #include "fdcan.h" -#include "gpio.h" -#include "tim.h" #include "usart.h" +#include "tim.h" +#include "gpio.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ @@ -73,40 +72,40 @@ void SystemClock_Config(void); /* USER CODE END 0 */ /** - * @brief The application entry point. - * @retval int - */ + * @brief The application entry point. + * @retval int + */ int main(void) { - /* USER CODE BEGIN 1 */ + /* USER CODE BEGIN 1 */ - /* USER CODE END 1 */ + /* USER CODE END 1 */ - /* MCU Configuration--------------------------------------------------------*/ + /* MCU Configuration--------------------------------------------------------*/ - /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ - HAL_Init(); + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); - /* USER CODE BEGIN Init */ + /* USER CODE BEGIN Init */ - /* USER CODE END Init */ + /* USER CODE END Init */ - /* Configure the system clock */ - SystemClock_Config(); + /* Configure the system clock */ + SystemClock_Config(); - /* USER CODE BEGIN SysInit */ + /* USER CODE BEGIN SysInit */ Logomatic_SetLogLevel(LogLevel_Debug); - /* USER CODE END SysInit */ - - /* Initialize all configured peripherals */ - MX_GPIO_Init(); - MX_FDCAN1_Init(); - MX_FDCAN2_Init(); - MX_TIM5_Init(); - MX_FDCAN3_Init(); - MX_LPUART1_UART_Init(); - /* USER CODE BEGIN 2 */ + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_FDCAN1_Init(); + MX_FDCAN2_Init(); + MX_TIM5_Init(); + MX_FDCAN3_Init(); + MX_LPUART1_UART_Init(); + /* USER CODE BEGIN 2 */ CubeCAN_Config primaryCanConfig = {.rx_callback = CANdler_Callback, .context.busid_user_context = GRCAN_BUS_PRIMARY, .sending_node_id = GRCAN_Debugger}; CubeCAN_Config dataCanConfig = {.rx_callback = CANdler_Callback, .context.busid_user_context = GRCAN_BUS_DATA, .sending_node_id = GRCAN_Debugger}; CubeCAN_Config chargerCanConfig = {.rx_callback = CANdler_Callback, .context.busid_user_context = GRCAN_BUS_CHARGER, .sending_node_id = GRCAN_Debugger}; @@ -133,59 +132,67 @@ int main(void) CubeVCP_Setup(&hlpuart1); CubeVCP_EnableRx(CANdler_VCP_Callback); CubeVCP_SendString("Hello World!\n", sizeof("Hello World!\n") - 1); - /* USER CODE END 2 */ + /* USER CODE END 2 */ - /* Infinite loop */ - /* USER CODE BEGIN WHILE */ + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ while (1) { - /* USER CODE END WHILE */ + /* USER CODE END WHILE */ - /* USER CODE BEGIN 3 */ + /* USER CODE BEGIN 3 */ MainLoop(); HAL_Delay(100); } - /* USER CODE END 3 */ + /* USER CODE END 3 */ } /** - * @brief System Clock Configuration - * @retval None - */ + * @brief System Clock Configuration + * @retval None + */ void SystemClock_Config(void) { - LL_FLASH_SetLatency(LL_FLASH_LATENCY_4); - while (LL_FLASH_GetLatency() != LL_FLASH_LATENCY_4) {} - LL_PWR_EnableRange1BoostMode(); - LL_RCC_HSI_Enable(); - /* Wait till HSI is ready */ - while (LL_RCC_HSI_IsReady() != 1) {} - - LL_RCC_HSI_SetCalibTrimming(64); - LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, LL_RCC_PLLM_DIV_1, 20, LL_RCC_PLLR_DIV_2); - LL_RCC_PLL_EnableDomain_SYS(); - LL_RCC_PLL_Enable(); - /* Wait till PLL is ready */ - while (LL_RCC_PLL_IsReady() != 1) {} - - LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); - LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_2); - /* Wait till System clock is ready */ - while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) {} - - /* Insure 1us transition state at intermediate medium speed clock*/ - for (__IO uint32_t i = (170 >> 1); i != 0; i--) - ; - - /* Set AHB prescaler*/ - LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1); - LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1); - LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1); - LL_SetSystemCoreClock(160000000); - - /* Update the time base */ - if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) { - Error_Handler(); - } + LL_FLASH_SetLatency(LL_FLASH_LATENCY_4); + while(LL_FLASH_GetLatency() != LL_FLASH_LATENCY_4) + { + } + LL_PWR_EnableRange1BoostMode(); + LL_RCC_HSI_Enable(); + /* Wait till HSI is ready */ + while(LL_RCC_HSI_IsReady() != 1) + { + } + + LL_RCC_HSI_SetCalibTrimming(64); + LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, LL_RCC_PLLM_DIV_1, 20, LL_RCC_PLLR_DIV_2); + LL_RCC_PLL_EnableDomain_SYS(); + LL_RCC_PLL_Enable(); + /* Wait till PLL is ready */ + while(LL_RCC_PLL_IsReady() != 1) + { + } + + LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); + LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_2); + /* Wait till System clock is ready */ + while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) + { + } + + /* Insure 1us transition state at intermediate medium speed clock*/ + for (__IO uint32_t i = (170 >> 1); i !=0; i--); + + /* Set AHB prescaler*/ + LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1); + LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1); + LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1); + LL_SetSystemCoreClock(160000000); + + /* Update the time base */ + if (HAL_InitTick (TICK_INT_PRIORITY) != HAL_OK) + { + Error_Handler(); + } } /* USER CODE BEGIN 4 */ @@ -204,29 +211,29 @@ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) /* USER CODE END 4 */ /** - * @brief This function is executed in case of error occurrence. - * @retval None - */ + * @brief This function is executed in case of error occurrence. + * @retval None + */ void Error_Handler(void) { - /* USER CODE BEGIN Error_Handler_Debug */ + /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) {} - /* USER CODE END Error_Handler_Debug */ + /* USER CODE END Error_Handler_Debug */ } #ifdef USE_FULL_ASSERT /** - * @brief Reports the name of the source file and the source line number - * where the assert_param error has occurred. - * @param file: pointer to the source file name - * @param line: assert_param error line source number - * @retval None - */ + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ void assert_failed(uint8_t *file, uint32_t line) { - /* USER CODE BEGIN 6 */ + /* USER CODE BEGIN 6 */ LOGOMATIC_CRITICAL("Assert failed! File %s on line %" PRIu32 "\n", file, line); - /* USER CODE END 6 */ + /* USER CODE END 6 */ } #endif /* USE_FULL_ASSERT */ diff --git a/Testbench/CUBEMXTESTING/Core/Src/stm32g4xx_hal_msp.c b/Testbench/CUBEMXTESTING/Core/Src/stm32g4xx_hal_msp.c index 4668755ab..2cc7d8296 100644 --- a/Testbench/CUBEMXTESTING/Core/Src/stm32g4xx_hal_msp.c +++ b/Testbench/CUBEMXTESTING/Core/Src/stm32g4xx_hal_msp.c @@ -57,27 +57,27 @@ /* USER CODE END 0 */ /** - * Initializes the Global MSP. - */ + * Initializes the Global MSP. + */ void HAL_MspInit(void) { - /* USER CODE BEGIN MspInit 0 */ + /* USER CODE BEGIN MspInit 0 */ - /* USER CODE END MspInit 0 */ + /* USER CODE END MspInit 0 */ - __HAL_RCC_SYSCFG_CLK_ENABLE(); - __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_RCC_SYSCFG_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); - /* System interrupt init*/ + /* System interrupt init*/ - /** Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral - */ - HAL_PWREx_DisableUCPDDeadBattery(); + /** Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral + */ + HAL_PWREx_DisableUCPDDeadBattery(); - /* USER CODE BEGIN MspInit 1 */ + /* USER CODE BEGIN MspInit 1 */ - /* USER CODE END MspInit 1 */ + /* USER CODE END MspInit 1 */ } /* USER CODE BEGIN 1 */ diff --git a/Testbench/CUBEMXTESTING/Core/Src/stm32g4xx_it.c b/Testbench/CUBEMXTESTING/Core/Src/stm32g4xx_it.c index 77f85d385..f02085e66 100644 --- a/Testbench/CUBEMXTESTING/Core/Src/stm32g4xx_it.c +++ b/Testbench/CUBEMXTESTING/Core/Src/stm32g4xx_it.c @@ -18,9 +18,8 @@ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ -#include "stm32g4xx_it.h" - #include "main.h" +#include "stm32g4xx_it.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ /* USER CODE END Includes */ @@ -69,125 +68,129 @@ extern TIM_HandleTypeDef htim5; /* Cortex-M4 Processor Interruption and Exception Handlers */ /******************************************************************************/ /** - * @brief This function handles Non maskable interrupt. - */ + * @brief This function handles Non maskable interrupt. + */ void NMI_Handler(void) { - /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ - /* USER CODE END NonMaskableInt_IRQn 0 */ - /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) {} - /* USER CODE END NonMaskableInt_IRQn 1 */ + /* USER CODE END NonMaskableInt_IRQn 1 */ } /** - * @brief This function handles Hard fault interrupt. - */ + * @brief This function handles Hard fault interrupt. + */ void HardFault_Handler(void) { - /* USER CODE BEGIN HardFault_IRQn 0 */ - - /* USER CODE END HardFault_IRQn 0 */ - while (1) { - /* USER CODE BEGIN W1_HardFault_IRQn 0 */ - /* USER CODE END W1_HardFault_IRQn 0 */ - } + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } } /** - * @brief This function handles Memory management fault. - */ + * @brief This function handles Memory management fault. + */ void MemManage_Handler(void) { - /* USER CODE BEGIN MemoryManagement_IRQn 0 */ - - /* USER CODE END MemoryManagement_IRQn 0 */ - while (1) { - /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ - /* USER CODE END W1_MemoryManagement_IRQn 0 */ - } + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } } /** - * @brief This function handles Prefetch fault, memory access fault. - */ + * @brief This function handles Prefetch fault, memory access fault. + */ void BusFault_Handler(void) { - /* USER CODE BEGIN BusFault_IRQn 0 */ - - /* USER CODE END BusFault_IRQn 0 */ - while (1) { - /* USER CODE BEGIN W1_BusFault_IRQn 0 */ - /* USER CODE END W1_BusFault_IRQn 0 */ - } + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } } /** - * @brief This function handles Undefined instruction or illegal state. - */ + * @brief This function handles Undefined instruction or illegal state. + */ void UsageFault_Handler(void) { - /* USER CODE BEGIN UsageFault_IRQn 0 */ - - /* USER CODE END UsageFault_IRQn 0 */ - while (1) { - /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ - /* USER CODE END W1_UsageFault_IRQn 0 */ - } + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } } /** - * @brief This function handles System service call via SWI instruction. - */ + * @brief This function handles System service call via SWI instruction. + */ void SVC_Handler(void) { - /* USER CODE BEGIN SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 0 */ - /* USER CODE END SVCall_IRQn 0 */ - /* USER CODE BEGIN SVCall_IRQn 1 */ + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ - /* USER CODE END SVCall_IRQn 1 */ + /* USER CODE END SVCall_IRQn 1 */ } /** - * @brief This function handles Debug monitor. - */ + * @brief This function handles Debug monitor. + */ void DebugMon_Handler(void) { - /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ - /* USER CODE END DebugMonitor_IRQn 0 */ - /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ - /* USER CODE END DebugMonitor_IRQn 1 */ + /* USER CODE END DebugMonitor_IRQn 1 */ } /** - * @brief This function handles Pendable request for system service. - */ + * @brief This function handles Pendable request for system service. + */ void PendSV_Handler(void) { - /* USER CODE BEGIN PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 0 */ - /* USER CODE END PendSV_IRQn 0 */ - /* USER CODE BEGIN PendSV_IRQn 1 */ + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ - /* USER CODE END PendSV_IRQn 1 */ + /* USER CODE END PendSV_IRQn 1 */ } /** - * @brief This function handles System tick timer. - */ + * @brief This function handles System tick timer. + */ void SysTick_Handler(void) { - /* USER CODE BEGIN SysTick_IRQn 0 */ + /* USER CODE BEGIN SysTick_IRQn 0 */ - /* USER CODE END SysTick_IRQn 0 */ - HAL_IncTick(); - /* USER CODE BEGIN SysTick_IRQn 1 */ + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ - /* USER CODE END SysTick_IRQn 1 */ + /* USER CODE END SysTick_IRQn 1 */ } /******************************************************************************/ @@ -198,73 +201,73 @@ void SysTick_Handler(void) /******************************************************************************/ /** - * @brief This function handles FDCAN1 interrupt 0. - */ + * @brief This function handles FDCAN1 interrupt 0. + */ void FDCAN1_IT0_IRQHandler(void) { - /* USER CODE BEGIN FDCAN1_IT0_IRQn 0 */ + /* USER CODE BEGIN FDCAN1_IT0_IRQn 0 */ - /* USER CODE END FDCAN1_IT0_IRQn 0 */ - HAL_FDCAN_IRQHandler(&hfdcan1); - /* USER CODE BEGIN FDCAN1_IT0_IRQn 1 */ + /* USER CODE END FDCAN1_IT0_IRQn 0 */ + HAL_FDCAN_IRQHandler(&hfdcan1); + /* USER CODE BEGIN FDCAN1_IT0_IRQn 1 */ - /* USER CODE END FDCAN1_IT0_IRQn 1 */ + /* USER CODE END FDCAN1_IT0_IRQn 1 */ } /** - * @brief This function handles TIM5 global interrupt. - */ + * @brief This function handles TIM5 global interrupt. + */ void TIM5_IRQHandler(void) { - /* USER CODE BEGIN TIM5_IRQn 0 */ + /* USER CODE BEGIN TIM5_IRQn 0 */ - /* USER CODE END TIM5_IRQn 0 */ - HAL_TIM_IRQHandler(&htim5); - /* USER CODE BEGIN TIM5_IRQn 1 */ + /* USER CODE END TIM5_IRQn 0 */ + HAL_TIM_IRQHandler(&htim5); + /* USER CODE BEGIN TIM5_IRQn 1 */ - /* USER CODE END TIM5_IRQn 1 */ + /* USER CODE END TIM5_IRQn 1 */ } /** - * @brief This function handles FDCAN2 interrupt 0. - */ + * @brief This function handles FDCAN2 interrupt 0. + */ void FDCAN2_IT0_IRQHandler(void) { - /* USER CODE BEGIN FDCAN2_IT0_IRQn 0 */ + /* USER CODE BEGIN FDCAN2_IT0_IRQn 0 */ - /* USER CODE END FDCAN2_IT0_IRQn 0 */ - HAL_FDCAN_IRQHandler(&hfdcan2); - /* USER CODE BEGIN FDCAN2_IT0_IRQn 1 */ + /* USER CODE END FDCAN2_IT0_IRQn 0 */ + HAL_FDCAN_IRQHandler(&hfdcan2); + /* USER CODE BEGIN FDCAN2_IT0_IRQn 1 */ - /* USER CODE END FDCAN2_IT0_IRQn 1 */ + /* USER CODE END FDCAN2_IT0_IRQn 1 */ } /** - * @brief This function handles FDCAN3 interrupt 0. - */ + * @brief This function handles FDCAN3 interrupt 0. + */ void FDCAN3_IT0_IRQHandler(void) { - /* USER CODE BEGIN FDCAN3_IT0_IRQn 0 */ + /* USER CODE BEGIN FDCAN3_IT0_IRQn 0 */ - /* USER CODE END FDCAN3_IT0_IRQn 0 */ - HAL_FDCAN_IRQHandler(&hfdcan3); - /* USER CODE BEGIN FDCAN3_IT0_IRQn 1 */ + /* USER CODE END FDCAN3_IT0_IRQn 0 */ + HAL_FDCAN_IRQHandler(&hfdcan3); + /* USER CODE BEGIN FDCAN3_IT0_IRQn 1 */ - /* USER CODE END FDCAN3_IT0_IRQn 1 */ + /* USER CODE END FDCAN3_IT0_IRQn 1 */ } /** - * @brief This function handles LPUART1 global interrupt. - */ + * @brief This function handles LPUART1 global interrupt. + */ void LPUART1_IRQHandler(void) { - /* USER CODE BEGIN LPUART1_IRQn 0 */ + /* USER CODE BEGIN LPUART1_IRQn 0 */ - /* USER CODE END LPUART1_IRQn 0 */ - HAL_UART_IRQHandler(&hlpuart1); - /* USER CODE BEGIN LPUART1_IRQn 1 */ + /* USER CODE END LPUART1_IRQn 0 */ + HAL_UART_IRQHandler(&hlpuart1); + /* USER CODE BEGIN LPUART1_IRQn 1 */ - /* USER CODE END LPUART1_IRQn 1 */ + /* USER CODE END LPUART1_IRQn 1 */ } /* USER CODE BEGIN 1 */ diff --git a/Testbench/CUBEMXTESTING/Core/Src/tim.c b/Testbench/CUBEMXTESTING/Core/Src/tim.c index 1f6110e86..cc6e6a92e 100644 --- a/Testbench/CUBEMXTESTING/Core/Src/tim.c +++ b/Testbench/CUBEMXTESTING/Core/Src/tim.c @@ -30,76 +30,83 @@ TIM_HandleTypeDef htim5; void MX_TIM5_Init(void) { - /* USER CODE BEGIN TIM5_Init 0 */ - - /* USER CODE END TIM5_Init 0 */ - - TIM_ClockConfigTypeDef sClockSourceConfig = {0}; - TIM_MasterConfigTypeDef sMasterConfig = {0}; - - /* USER CODE BEGIN TIM5_Init 1 */ - - /* USER CODE END TIM5_Init 1 */ - htim5.Instance = TIM5; - htim5.Init.Prescaler = 159; - htim5.Init.CounterMode = TIM_COUNTERMODE_UP; - htim5.Init.Period = 499; - htim5.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; - htim5.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; - if (HAL_TIM_Base_Init(&htim5) != HAL_OK) { - Error_Handler(); - } - sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; - if (HAL_TIM_ConfigClockSource(&htim5, &sClockSourceConfig) != HAL_OK) { - Error_Handler(); - } - sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; - sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; - if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig) != HAL_OK) { - Error_Handler(); - } - /* USER CODE BEGIN TIM5_Init 2 */ + /* USER CODE BEGIN TIM5_Init 0 */ + + /* USER CODE END TIM5_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; + + /* USER CODE BEGIN TIM5_Init 1 */ + + /* USER CODE END TIM5_Init 1 */ + htim5.Instance = TIM5; + htim5.Init.Prescaler = 159; + htim5.Init.CounterMode = TIM_COUNTERMODE_UP; + htim5.Init.Period = 499; + htim5.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim5.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim5) != HAL_OK) + { + Error_Handler(); + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(&htim5, &sClockSourceConfig) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM5_Init 2 */ HAL_TIM_Base_Start_IT(&htim5); - /* USER CODE END TIM5_Init 2 */ + /* USER CODE END TIM5_Init 2 */ + } -void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *tim_baseHandle) +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) { - if (tim_baseHandle->Instance == TIM5) { - /* USER CODE BEGIN TIM5_MspInit 0 */ + if(tim_baseHandle->Instance==TIM5) + { + /* USER CODE BEGIN TIM5_MspInit 0 */ - /* USER CODE END TIM5_MspInit 0 */ - /* TIM5 clock enable */ - __HAL_RCC_TIM5_CLK_ENABLE(); + /* USER CODE END TIM5_MspInit 0 */ + /* TIM5 clock enable */ + __HAL_RCC_TIM5_CLK_ENABLE(); - /* TIM5 interrupt Init */ - HAL_NVIC_SetPriority(TIM5_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(TIM5_IRQn); - /* USER CODE BEGIN TIM5_MspInit 1 */ + /* TIM5 interrupt Init */ + HAL_NVIC_SetPriority(TIM5_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(TIM5_IRQn); + /* USER CODE BEGIN TIM5_MspInit 1 */ - /* USER CODE END TIM5_MspInit 1 */ - } + /* USER CODE END TIM5_MspInit 1 */ + } } -void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *tim_baseHandle) +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* tim_baseHandle) { - if (tim_baseHandle->Instance == TIM5) { - /* USER CODE BEGIN TIM5_MspDeInit 0 */ + if(tim_baseHandle->Instance==TIM5) + { + /* USER CODE BEGIN TIM5_MspDeInit 0 */ - /* USER CODE END TIM5_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_TIM5_CLK_DISABLE(); + /* USER CODE END TIM5_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM5_CLK_DISABLE(); - /* TIM5 interrupt Deinit */ - HAL_NVIC_DisableIRQ(TIM5_IRQn); - /* USER CODE BEGIN TIM5_MspDeInit 1 */ + /* TIM5 interrupt Deinit */ + HAL_NVIC_DisableIRQ(TIM5_IRQn); + /* USER CODE BEGIN TIM5_MspDeInit 1 */ - /* USER CODE END TIM5_MspDeInit 1 */ - } + /* USER CODE END TIM5_MspDeInit 1 */ + } } /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ + diff --git a/Testbench/CUBEMXTESTING/Core/Src/usart.c b/Testbench/CUBEMXTESTING/Core/Src/usart.c index a14deb76c..836ce8d48 100644 --- a/Testbench/CUBEMXTESTING/Core/Src/usart.c +++ b/Testbench/CUBEMXTESTING/Core/Src/usart.c @@ -31,98 +31,106 @@ UART_HandleTypeDef hlpuart1; void MX_LPUART1_UART_Init(void) { - /* USER CODE BEGIN LPUART1_Init 0 */ - - /* USER CODE END LPUART1_Init 0 */ - - /* USER CODE BEGIN LPUART1_Init 1 */ - - /* USER CODE END LPUART1_Init 1 */ - hlpuart1.Instance = LPUART1; - hlpuart1.Init.BaudRate = 115200; - hlpuart1.Init.WordLength = UART_WORDLENGTH_8B; - hlpuart1.Init.StopBits = UART_STOPBITS_1; - hlpuart1.Init.Parity = UART_PARITY_NONE; - hlpuart1.Init.Mode = UART_MODE_TX_RX; - hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; - hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; - hlpuart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; - hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; - if (HAL_UART_Init(&hlpuart1) != HAL_OK) { - Error_Handler(); - } - if (HAL_UARTEx_SetTxFifoThreshold(&hlpuart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) { - Error_Handler(); - } - if (HAL_UARTEx_SetRxFifoThreshold(&hlpuart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) { - Error_Handler(); - } - if (HAL_UARTEx_DisableFifoMode(&hlpuart1) != HAL_OK) { - Error_Handler(); - } - /* USER CODE BEGIN LPUART1_Init 2 */ - - /* USER CODE END LPUART1_Init 2 */ + /* USER CODE BEGIN LPUART1_Init 0 */ + + /* USER CODE END LPUART1_Init 0 */ + + /* USER CODE BEGIN LPUART1_Init 1 */ + + /* USER CODE END LPUART1_Init 1 */ + hlpuart1.Instance = LPUART1; + hlpuart1.Init.BaudRate = 115200; + hlpuart1.Init.WordLength = UART_WORDLENGTH_8B; + hlpuart1.Init.StopBits = UART_STOPBITS_1; + hlpuart1.Init.Parity = UART_PARITY_NONE; + hlpuart1.Init.Mode = UART_MODE_TX_RX; + hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + hlpuart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; + hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&hlpuart1) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetTxFifoThreshold(&hlpuart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetRxFifoThreshold(&hlpuart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_DisableFifoMode(&hlpuart1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN LPUART1_Init 2 */ + + /* USER CODE END LPUART1_Init 2 */ + } -void HAL_UART_MspInit(UART_HandleTypeDef *uartHandle) +void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { - GPIO_InitTypeDef GPIO_InitStruct = {0}; - if (uartHandle->Instance == LPUART1) { - /* USER CODE BEGIN LPUART1_MspInit 0 */ - - /* USER CODE END LPUART1_MspInit 0 */ - LL_RCC_SetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE_PCLK1); - - /* LPUART1 clock enable */ - __HAL_RCC_LPUART1_CLK_ENABLE(); - - __HAL_RCC_GPIOA_CLK_ENABLE(); - /**LPUART1 GPIO Configuration - PA2 ------> LPUART1_TX - PA3 ------> LPUART1_RX - */ - GPIO_InitStruct.Pin = GPIO_PIN_2 | GPIO_PIN_3; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF12_LPUART1; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /* LPUART1 interrupt Init */ - HAL_NVIC_SetPriority(LPUART1_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(LPUART1_IRQn); - /* USER CODE BEGIN LPUART1_MspInit 1 */ - - /* USER CODE END LPUART1_MspInit 1 */ - } + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(uartHandle->Instance==LPUART1) + { + /* USER CODE BEGIN LPUART1_MspInit 0 */ + + /* USER CODE END LPUART1_MspInit 0 */ + LL_RCC_SetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE_PCLK1); + + /* LPUART1 clock enable */ + __HAL_RCC_LPUART1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**LPUART1 GPIO Configuration + PA2 ------> LPUART1_TX + PA3 ------> LPUART1_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF12_LPUART1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* LPUART1 interrupt Init */ + HAL_NVIC_SetPriority(LPUART1_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(LPUART1_IRQn); + /* USER CODE BEGIN LPUART1_MspInit 1 */ + + /* USER CODE END LPUART1_MspInit 1 */ + } } -void HAL_UART_MspDeInit(UART_HandleTypeDef *uartHandle) +void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle) { - if (uartHandle->Instance == LPUART1) { - /* USER CODE BEGIN LPUART1_MspDeInit 0 */ + if(uartHandle->Instance==LPUART1) + { + /* USER CODE BEGIN LPUART1_MspDeInit 0 */ - /* USER CODE END LPUART1_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_LPUART1_CLK_DISABLE(); + /* USER CODE END LPUART1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_LPUART1_CLK_DISABLE(); - /**LPUART1 GPIO Configuration - PA2 ------> LPUART1_TX - PA3 ------> LPUART1_RX - */ - HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2 | GPIO_PIN_3); + /**LPUART1 GPIO Configuration + PA2 ------> LPUART1_TX + PA3 ------> LPUART1_RX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); - /* LPUART1 interrupt Deinit */ - HAL_NVIC_DisableIRQ(LPUART1_IRQn); - /* USER CODE BEGIN LPUART1_MspDeInit 1 */ + /* LPUART1 interrupt Deinit */ + HAL_NVIC_DisableIRQ(LPUART1_IRQn); + /* USER CODE BEGIN LPUART1_MspDeInit 1 */ - /* USER CODE END LPUART1_MspDeInit 1 */ - } + /* USER CODE END LPUART1_MspDeInit 1 */ + } } /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ + diff --git a/Testbench/testbench.cmake b/Testbench/testbench.cmake new file mode 100644 index 000000000..6f02b074e --- /dev/null +++ b/Testbench/testbench.cmake @@ -0,0 +1,9 @@ +add_project( + NAME "CUBEMXTESTING" + PATH "CUBEMXTESTING" + SERIES "g4" + SPECIFIER "g474re" + HAL_GIT_TAG "v1.2.7" # https://github.com/STMicroelectronics/stm32g4xx-hal-driver/tree/v1.2.7 + CMSIS_GIT_TAG "v1.2.6" # https://github.com/STMicroelectronics/cmsis-device-g4/tree/v1.2.6 + CMSIS_MAJOR "5" +) From 24a39e042f46867a87e58b762de5910193278f88 Mon Sep 17 00:00:00 2001 From: github-actions <41898282+github-actions[bot]@users.noreply.github.com> Date: Sun, 23 Aug 2026 23:05:49 +0000 Subject: [PATCH 07/17] Automatic CMake Format: Standardized formatting automatically --- CMakeLists.txt | 150 +++--- Lib/Vendor/TargetFlags/stm32g4xx.cmake | 20 +- Lib/Vendor/TargetFlags/stm32h5xx.cmake | 20 +- Lib/Vendor/TargetFlags/stm32l4xx.cmake | 20 +- Lib/Vendor/TargetFlags/stm32u5xx.cmake | 20 +- Lib/cmake/cube.cmake | 684 ++++++++++++------------- 6 files changed, 458 insertions(+), 456 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 5915fd75d..6b8517123 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1,6 +1,9 @@ cmake_minimum_required(VERSION 3.25) project(Firmware) -enable_language(C ASM) +enable_language( + C + ASM +) set(CMAKE_C_STANDARD 11) set(CMAKE_C_STANDARD_REQUIRED ON) set(CMAKE_C_EXTENSIONS ON) @@ -8,99 +11,99 @@ set(CMAKE_EXPORT_COMPILE_COMMANDS TRUE) # Messages if(NOT DEFINED CMAKE_PRESET_NAME) - message( - FATAL_ERROR - "This project requires configuration using a CMake preset. Please use 'cmake --preset ' or select a preset in your IDE." - ) + message( + FATAL_ERROR + "This project requires configuration using a CMake preset. Please use 'cmake --preset ' or select a preset in your IDE." + ) endif() message( - STATUS - "Build type: " - ${CMAKE_BUILD_TYPE} + STATUS + "Build type: " + ${CMAKE_BUILD_TYPE} ) message(STATUS "Target type: ${TARGET_TYPE}") message( - STATUS - "Active CMake Preset: " - ${CMAKE_PRESET_NAME} + STATUS + "Active CMake Preset: " + ${CMAKE_PRESET_NAME} ) # Shared Compiler Cache Configuration find_program(SCCACHE_PROGRAM sccache) if( - SCCACHE_PROGRAM - AND - NOT - CMAKE_C_COMPILER_LAUNCHER - AND - NOT - CMAKE_ASM_COMPILER_LAUNCHER + SCCACHE_PROGRAM + AND + NOT + CMAKE_C_COMPILER_LAUNCHER + AND + NOT + CMAKE_ASM_COMPILER_LAUNCHER ) - message(STATUS "Found sccache: ${SCCACHE_PROGRAM}") - set(SCCACHE_DIR_PATH "${CMAKE_SOURCE_DIR}/sccache") - set( - CMAKE_C_COMPILER_LAUNCHER - "${CMAKE_COMMAND}" - -E - env - "SCCACHE_DIR=${SCCACHE_DIR_PATH}" - "${SCCACHE_PROGRAM}" - ) - set( - CMAKE_ASM_COMPILER_LAUNCHER - "${CMAKE_COMMAND}" - -E - env - "SCCACHE_DIR=${SCCACHE_DIR_PATH}" - "${SCCACHE_PROGRAM}" - ) - message(STATUS "sccache directory: ${SCCACHE_DIR_PATH}") + message(STATUS "Found sccache: ${SCCACHE_PROGRAM}") + set(SCCACHE_DIR_PATH "${CMAKE_SOURCE_DIR}/sccache") + set( + CMAKE_C_COMPILER_LAUNCHER + "${CMAKE_COMMAND}" + -E + env + "SCCACHE_DIR=${SCCACHE_DIR_PATH}" + "${SCCACHE_PROGRAM}" + ) + set( + CMAKE_ASM_COMPILER_LAUNCHER + "${CMAKE_COMMAND}" + -E + env + "SCCACHE_DIR=${SCCACHE_DIR_PATH}" + "${SCCACHE_PROGRAM}" + ) + message(STATUS "sccache directory: ${SCCACHE_DIR_PATH}") elseif(CMAKE_C_COMPILER_LAUNCHER OR CMAKE_ASM_COMPILER_LAUNCHER) - message( - STATUS - "Not using sccache: CMAKE_C_COMPILER_LAUNCHER already set to '${CMAKE_C_COMPILER_LAUNCHER}' or CMAKE_ASM_COMPILER_LAUNCHER already set to '${CMAKE_ASM_COMPILER_LAUNCHER}'" - ) + message( + STATUS + "Not using sccache: CMAKE_C_COMPILER_LAUNCHER already set to '${CMAKE_C_COMPILER_LAUNCHER}' or CMAKE_ASM_COMPILER_LAUNCHER already set to '${CMAKE_ASM_COMPILER_LAUNCHER}'" + ) else() - message(STATUS "Not using sccache: sccache not found in PATH") + message(STATUS "Not using sccache: sccache not found in PATH") endif() # Compiler Cache Configuration find_program(CCACHE_PROGRAM ccache) if( - CCACHE_PROGRAM - AND - NOT - CMAKE_C_COMPILER_LAUNCHER - AND - NOT - CMAKE_ASM_COMPILER_LAUNCHER + CCACHE_PROGRAM + AND + NOT + CMAKE_C_COMPILER_LAUNCHER + AND + NOT + CMAKE_ASM_COMPILER_LAUNCHER ) - message(STATUS "Found ccache: ${CCACHE_PROGRAM}") - set(CCACHE_DIR_PATH "${CMAKE_SOURCE_DIR}/ccache") - set( - CMAKE_C_COMPILER_LAUNCHER - "${CMAKE_COMMAND}" - -E - env - "CCACHE_DIR=${CCACHE_DIR_PATH}" - "${CCACHE_PROGRAM}" - ) - set( - CMAKE_ASM_COMPILER_LAUNCHER - "${CMAKE_COMMAND}" - -E - env - "CCACHE_DIR=${CCACHE_DIR_PATH}" - "${CCACHE_PROGRAM}" - ) - message(STATUS "ccache directory: ${CCACHE_DIR_PATH}") + message(STATUS "Found ccache: ${CCACHE_PROGRAM}") + set(CCACHE_DIR_PATH "${CMAKE_SOURCE_DIR}/ccache") + set( + CMAKE_C_COMPILER_LAUNCHER + "${CMAKE_COMMAND}" + -E + env + "CCACHE_DIR=${CCACHE_DIR_PATH}" + "${CCACHE_PROGRAM}" + ) + set( + CMAKE_ASM_COMPILER_LAUNCHER + "${CMAKE_COMMAND}" + -E + env + "CCACHE_DIR=${CCACHE_DIR_PATH}" + "${CCACHE_PROGRAM}" + ) + message(STATUS "ccache directory: ${CCACHE_DIR_PATH}") elseif(CMAKE_C_COMPILER_LAUNCHER OR CMAKE_ASM_COMPILER_LAUNCHER) - message( - STATUS - "Not using ccache: CMAKE_C_COMPILER_LAUNCHER already set to '${CMAKE_C_COMPILER_LAUNCHER}' or CMAKE_ASM_COMPILER_LAUNCHER already set to '${CMAKE_ASM_COMPILER_LAUNCHER}'" - ) + message( + STATUS + "Not using ccache: CMAKE_C_COMPILER_LAUNCHER already set to '${CMAKE_C_COMPILER_LAUNCHER}' or CMAKE_ASM_COMPILER_LAUNCHER already set to '${CMAKE_ASM_COMPILER_LAUNCHER}'" + ) else() - message(STATUS "Not using ccache: ccache not found in PATH") + message(STATUS "Not using ccache: ccache not found in PATH") endif() # Globals @@ -114,7 +117,6 @@ add_arm_cmsis_core( GIT_TAG "5.9.0" # https://github.com/ARM-software/CMSIS_5/tree/5.9.0 ) - # Vendor include("${LIB_PATH}/Vendor/CMSIS_5/cmsis_5.cmake") include("${LIB_PATH}/Vendor/STM32_HAL_LL/cube.cmake") diff --git a/Lib/Vendor/TargetFlags/stm32g4xx.cmake b/Lib/Vendor/TargetFlags/stm32g4xx.cmake index 1a7cdf773..a2e3c83f4 100644 --- a/Lib/Vendor/TargetFlags/stm32g4xx.cmake +++ b/Lib/Vendor/TargetFlags/stm32g4xx.cmake @@ -1,15 +1,15 @@ target_compile_options( - "${TARGET_NAME}" - PRIVATE - -mcpu=cortex-m4 - -mfpu=fpv4-sp-d16 - -mfloat-abi=hard + "${TARGET_NAME}" + PRIVATE + -mcpu=cortex-m4 + -mfpu=fpv4-sp-d16 + -mfloat-abi=hard ) target_link_options( - "${TARGET_NAME}" - PRIVATE - -mcpu=cortex-m4 - -mfpu=fpv4-sp-d16 - -mfloat-abi=hard + "${TARGET_NAME}" + PRIVATE + -mcpu=cortex-m4 + -mfpu=fpv4-sp-d16 + -mfloat-abi=hard ) diff --git a/Lib/Vendor/TargetFlags/stm32h5xx.cmake b/Lib/Vendor/TargetFlags/stm32h5xx.cmake index f7e85a490..13eb3cd24 100644 --- a/Lib/Vendor/TargetFlags/stm32h5xx.cmake +++ b/Lib/Vendor/TargetFlags/stm32h5xx.cmake @@ -1,15 +1,15 @@ target_compile_options( - "${TARGET_NAME}" - PRIVATE - -mcpu=cortex-m33 - -mfpu=fpv5-sp-d16 - -mfloat-abi=hard + "${TARGET_NAME}" + PRIVATE + -mcpu=cortex-m33 + -mfpu=fpv5-sp-d16 + -mfloat-abi=hard ) target_link_options( - "${TARGET_NAME}" - PRIVATE - -mcpu=cortex-m33 - -mfpu=fpv5-sp-d16 - -mfloat-abi=hard + "${TARGET_NAME}" + PRIVATE + -mcpu=cortex-m33 + -mfpu=fpv5-sp-d16 + -mfloat-abi=hard ) diff --git a/Lib/Vendor/TargetFlags/stm32l4xx.cmake b/Lib/Vendor/TargetFlags/stm32l4xx.cmake index 1a7cdf773..a2e3c83f4 100644 --- a/Lib/Vendor/TargetFlags/stm32l4xx.cmake +++ b/Lib/Vendor/TargetFlags/stm32l4xx.cmake @@ -1,15 +1,15 @@ target_compile_options( - "${TARGET_NAME}" - PRIVATE - -mcpu=cortex-m4 - -mfpu=fpv4-sp-d16 - -mfloat-abi=hard + "${TARGET_NAME}" + PRIVATE + -mcpu=cortex-m4 + -mfpu=fpv4-sp-d16 + -mfloat-abi=hard ) target_link_options( - "${TARGET_NAME}" - PRIVATE - -mcpu=cortex-m4 - -mfpu=fpv4-sp-d16 - -mfloat-abi=hard + "${TARGET_NAME}" + PRIVATE + -mcpu=cortex-m4 + -mfpu=fpv4-sp-d16 + -mfloat-abi=hard ) diff --git a/Lib/Vendor/TargetFlags/stm32u5xx.cmake b/Lib/Vendor/TargetFlags/stm32u5xx.cmake index 6619b4fa8..521077ce1 100644 --- a/Lib/Vendor/TargetFlags/stm32u5xx.cmake +++ b/Lib/Vendor/TargetFlags/stm32u5xx.cmake @@ -1,15 +1,15 @@ target_compile_options( - "${TARGET_NAME}" - PRIVATE - -mcpu=cortex-m33 - -mfpu=fpv4-sp-d16 - -mfloat-abi=hard + "${TARGET_NAME}" + PRIVATE + -mcpu=cortex-m33 + -mfpu=fpv4-sp-d16 + -mfloat-abi=hard ) target_link_options( - "${TARGET_NAME}" - PRIVATE - -mcpu=cortex-m33 - -mfpu=fpv4-sp-d16 - -mfloat-abi=hard + "${TARGET_NAME}" + PRIVATE + -mcpu=cortex-m33 + -mfpu=fpv4-sp-d16 + -mfloat-abi=hard ) diff --git a/Lib/cmake/cube.cmake b/Lib/cmake/cube.cmake index 65398a48c..9de7c142d 100644 --- a/Lib/cmake/cube.cmake +++ b/Lib/cmake/cube.cmake @@ -12,84 +12,84 @@ include(FetchContent) @remark Prefer calling add_project() instead of this function directly ]] function(download_git) - if(NOT ${ARGC} EQUAL 10) - message( - FATAL_ERROR - "You called download_git with an unsupported number of inputs/arguments! Do better please :)" - ) - endif() - - set( - one_value_args - NAME - GIT_REPOSITORY - GIT_TAG - OUTPUT_PATH_VAR - ) - set(multi_value_args TARGET_FOLDER) - unset(DOWNLOAD_GIT_ARG_NAME) - unset(DOWNLOAD_GIT_ARG_GIT_REPOSITORY) - unset(DOWNLOAD_GIT_ARG_GIT_TAG) - unset(DOWNLOAD_GIT_ARG_OUTPUT_PATH_VAR) - unset(DOWNLOAD_GIT_ARG_TARGET_FOLDER) - cmake_parse_arguments( - "DOWNLOAD_GIT_ARG" - "" - "${one_value_args}" - "${multi_value_args}" - ${ARGN} - ) - - message( - STATUS - "This may take a moment, fetching content for ${DOWNLOAD_GIT_ARG_NAME} from ${DOWNLOAD_GIT_ARG_GIT_REPOSITORY} at tag ${DOWNLOAD_GIT_ARG_GIT_TAG}" - ) - - FetchContent_Declare( - "${DOWNLOAD_GIT_ARG_NAME}" - GIT_REPOSITORY "${DOWNLOAD_GIT_ARG_GIT_REPOSITORY}" - GIT_TAG "${DOWNLOAD_GIT_ARG_GIT_TAG}" - GIT_SHALLOW ON - GIT_SUBMODULES - "" - UPDATE_DISCONNECTED TRUE - GIT_CONFIG - "core.sparseCheckout=true" - ) - - string(TOLOWER "${DOWNLOAD_GIT_ARG_NAME}" NAME_LOWER) - - FetchContent_GetProperties(${NAME_LOWER}) - - if(NOT ${NAME_LOWER}_POPULATED) - FetchContent_Populate(${NAME_LOWER}) - separate_arguments( - TARGET_FOLDER_LIST - NATIVE_COMMAND - "${DOWNLOAD_GIT_ARG_TARGET_FOLDER}" - ) - execute_process( - COMMAND - git sparse-checkout set ${TARGET_FOLDER_LIST} - WORKING_DIRECTORY "${${NAME_LOWER}_SOURCE_DIR}" - ) - execute_process( - COMMAND - git checkout - WORKING_DIRECTORY "${${NAME_LOWER}_SOURCE_DIR}" - ) - endif() - - message( - STATUS - "Successfully fetched content for ${DOWNLOAD_GIT_ARG_NAME} from ${DOWNLOAD_GIT_ARG_GIT_REPOSITORY} at tag ${DOWNLOAD_GIT_ARG_GIT_TAG} to ${${DOWNLOAD_GIT_ARG_NAME}_SOURCE_DIR}" - ) - - set( - "${DOWNLOAD_GIT_ARG_OUTPUT_PATH_VAR}" - "${${DOWNLOAD_GIT_ARG_NAME}_SOURCE_DIR}" - ) - return(PROPAGATE "${DOWNLOAD_GIT_ARG_OUTPUT_PATH_VAR}") + if(NOT ${ARGC} EQUAL 10) + message( + FATAL_ERROR + "You called download_git with an unsupported number of inputs/arguments! Do better please :)" + ) + endif() + + set( + one_value_args + NAME + GIT_REPOSITORY + GIT_TAG + OUTPUT_PATH_VAR + ) + set(multi_value_args TARGET_FOLDER) + unset(DOWNLOAD_GIT_ARG_NAME) + unset(DOWNLOAD_GIT_ARG_GIT_REPOSITORY) + unset(DOWNLOAD_GIT_ARG_GIT_TAG) + unset(DOWNLOAD_GIT_ARG_OUTPUT_PATH_VAR) + unset(DOWNLOAD_GIT_ARG_TARGET_FOLDER) + cmake_parse_arguments( + "DOWNLOAD_GIT_ARG" + "" + "${one_value_args}" + "${multi_value_args}" + ${ARGN} + ) + + message( + STATUS + "This may take a moment, fetching content for ${DOWNLOAD_GIT_ARG_NAME} from ${DOWNLOAD_GIT_ARG_GIT_REPOSITORY} at tag ${DOWNLOAD_GIT_ARG_GIT_TAG}" + ) + + FetchContent_Declare( + "${DOWNLOAD_GIT_ARG_NAME}" + GIT_REPOSITORY "${DOWNLOAD_GIT_ARG_GIT_REPOSITORY}" + GIT_TAG "${DOWNLOAD_GIT_ARG_GIT_TAG}" + GIT_SHALLOW ON + GIT_SUBMODULES + "" + UPDATE_DISCONNECTED TRUE + GIT_CONFIG + "core.sparseCheckout=true" + ) + + string(TOLOWER "${DOWNLOAD_GIT_ARG_NAME}" NAME_LOWER) + + FetchContent_GetProperties(${NAME_LOWER}) + + if(NOT ${NAME_LOWER}_POPULATED) + FetchContent_Populate(${NAME_LOWER}) + separate_arguments( + TARGET_FOLDER_LIST + NATIVE_COMMAND + "${DOWNLOAD_GIT_ARG_TARGET_FOLDER}" + ) + execute_process( + COMMAND + git sparse-checkout set ${TARGET_FOLDER_LIST} + WORKING_DIRECTORY "${${NAME_LOWER}_SOURCE_DIR}" + ) + execute_process( + COMMAND + git checkout + WORKING_DIRECTORY "${${NAME_LOWER}_SOURCE_DIR}" + ) + endif() + + message( + STATUS + "Successfully fetched content for ${DOWNLOAD_GIT_ARG_NAME} from ${DOWNLOAD_GIT_ARG_GIT_REPOSITORY} at tag ${DOWNLOAD_GIT_ARG_GIT_TAG} to ${${DOWNLOAD_GIT_ARG_NAME}_SOURCE_DIR}" + ) + + set( + "${DOWNLOAD_GIT_ARG_OUTPUT_PATH_VAR}" + "${${DOWNLOAD_GIT_ARG_NAME}_SOURCE_DIR}" + ) + return(PROPAGATE "${DOWNLOAD_GIT_ARG_OUTPUT_PATH_VAR}") endfunction() #[[ @@ -100,50 +100,50 @@ endfunction() @remark Prefer calling add_project() instead of this function directly ]] function(add_arm_cmsis_core) - if(NOT ${ARGC} EQUAL 4) - message( - FATAL_ERROR - "You called add_arm_cmsis_core with an unsupported number of inputs/arguments! Do better please :)" - ) - endif() - - set( - one_value_args - MAJOR - GIT_TAG - ) - unset(ARM_CMSIS_CORE_ARG_MAJOR) - unset(ARM_CMSIS_CORE_ARG_GIT_TAG) - cmake_parse_arguments("ARM_CMSIS_CORE_ARG" "" "${one_value_args}" "" ${ARGN}) - - if(NOT ARM_CMSIS_CORE_ARG_MAJOR MATCHES "^[0-9]$") - message( - FATAL_ERROR - "MAJOR '${ARM_CMSIS_CORE_ARG_MAJOR}' is not a valid version number (ie '5')" - ) - endif() - - if(TARGET CMSIS_${ARM_CMSIS_CORE_ARG_MAJOR}_Core) - return() - endif() - - download_git( - NAME "arm_cmsis_${ARM_CMSIS_CORE_ARG_MAJOR}" - GIT_REPOSITORY "https://github.com/arm-software/cmsis_${ARM_CMSIS_CORE_ARG_MAJOR}.git" - GIT_TAG "${ARM_CMSIS_CORE_ARG_GIT_TAG}" - OUTPUT_PATH_VAR ARM_CMSIS_CORE_PATH - TARGET_FOLDER "CMSIS/Core/Include" - ) - message( - STATUS - "Successfully fetched content for ARM CMSIS core version ${ARM_CMSIS_CORE_ARG_MAJOR} from ${ARM_CMSIS_CORE_ARG_GIT_TAG} to ${ARM_CMSIS_CORE_PATH}" - ) - add_library(CMSIS_${ARM_CMSIS_CORE_ARG_MAJOR}_Core INTERFACE) - target_include_directories( - CMSIS_${ARM_CMSIS_CORE_ARG_MAJOR}_Core - INTERFACE - $ - ) + if(NOT ${ARGC} EQUAL 4) + message( + FATAL_ERROR + "You called add_arm_cmsis_core with an unsupported number of inputs/arguments! Do better please :)" + ) + endif() + + set( + one_value_args + MAJOR + GIT_TAG + ) + unset(ARM_CMSIS_CORE_ARG_MAJOR) + unset(ARM_CMSIS_CORE_ARG_GIT_TAG) + cmake_parse_arguments("ARM_CMSIS_CORE_ARG" "" "${one_value_args}" "" ${ARGN}) + + if(NOT ARM_CMSIS_CORE_ARG_MAJOR MATCHES "^[0-9]$") + message( + FATAL_ERROR + "MAJOR '${ARM_CMSIS_CORE_ARG_MAJOR}' is not a valid version number (ie '5')" + ) + endif() + + if(TARGET CMSIS_${ARM_CMSIS_CORE_ARG_MAJOR}_Core) + return() + endif() + + download_git( + NAME "arm_cmsis_${ARM_CMSIS_CORE_ARG_MAJOR}" + GIT_REPOSITORY "https://github.com/arm-software/cmsis_${ARM_CMSIS_CORE_ARG_MAJOR}.git" + GIT_TAG "${ARM_CMSIS_CORE_ARG_GIT_TAG}" + OUTPUT_PATH_VAR ARM_CMSIS_CORE_PATH + TARGET_FOLDER "CMSIS/Core/Include" + ) + message( + STATUS + "Successfully fetched content for ARM CMSIS core version ${ARM_CMSIS_CORE_ARG_MAJOR} from ${ARM_CMSIS_CORE_ARG_GIT_TAG} to ${ARM_CMSIS_CORE_PATH}" + ) + add_library(CMSIS_${ARM_CMSIS_CORE_ARG_MAJOR}_Core INTERFACE) + target_include_directories( + CMSIS_${ARM_CMSIS_CORE_ARG_MAJOR}_Core + INTERFACE + $ + ) endfunction() #[[ @@ -155,88 +155,88 @@ endfunction() @remark Prefer calling add_project() instead of this function directly ]] function(add_arm_cmsis_interface) - if(NOT ${ARGC} EQUAL 6) - message( - FATAL_ERROR - "You called add_arm_cmsis_interface with an unsupported number of inputs/arguments! Do better please :)" - ) - endif() - - set( - one_value_args - SERIES - SPECIFIER - GIT_TAG - ) - unset(ARM_CMSIS_INTERFACE_ARG_SERIES) - unset(ARM_CMSIS_INTERFACE_ARG_SPECIFIER) - unset(ARM_CMSIS_INTERFACE_ARG_GIT_TAG) - cmake_parse_arguments( - "ARM_CMSIS_INTERFACE_ARG" - "" - "${one_value_args}" - "" - ${ARGN} - ) - - string(LENGTH "${ARM_CMSIS_INTERFACE_ARG_SERIES}" SERIES_LENGTH) - if(NOT SERIES_LENGTH EQUAL 2) - message( - FATAL_ERROR - "SERIES '${ARM_CMSIS_INTERFACE_ARG_SERIES}' must be 2 characters long (ie 'g4')" - ) - endif() - string(TOLOWER "${ARM_CMSIS_INTERFACE_ARG_SERIES}" SERIES_LOWER) - - string(LENGTH "${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}" SPECIFIER_LENGTH) - if(SPECIFIER_LENGTH LESS 6) - message( - FATAL_ERROR - "SPECIFIER '${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}' must be at least 6 characters long (ie 'g474re' or 'g474ret6')" - ) - endif() - string(TOLOWER "${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}" SPECIFIER_LOWER) - string(TOUPPER "${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}" SPECIFIER_UPPER) - - string( - FIND "${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}" - "${ARM_CMSIS_INTERFACE_ARG_SERIES}" - SERIES_POSITION_IN_SPECIFIER - ) - if(NOT SERIES_POSITION_IN_SPECIFIER EQUAL 0) - message( - FATAL_ERROR - "SPECIFIER '${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}' must start with SERIES '${ARM_CMSIS_INTERFACE_ARG_SERIES}' at the beginning (eg 'g4' and 'g474ret6')" - ) - endif() - - if(TARGET CMSIS_Device_${SPECIFIER_UPPER}) - return() - endif() - - download_git( - NAME "cmsis_device_${SERIES_LOWER}" - GIT_REPOSITORY "https://github.com/STMicroelectronics/cmsis-device-${SERIES_LOWER}.git" - GIT_TAG ${ARM_CMSIS_INTERFACE_ARG_GIT_TAG} - TARGET_FOLDER "Include" - OUTPUT_PATH_VAR CMSIS_DEVICE_PATH - ) - message( - STATUS - "Successfully fetched content for ARM CMSIS device ${SPECIFIER_UPPER} from ${ARM_CMSIS_INTERFACE_ARG_GIT_TAG} to ${CMSIS_DEVICE_PATH}" - ) - add_library("CMSIS_Device_${SPECIFIER_UPPER}" INTERFACE) - target_include_directories( - "CMSIS_Device_${SPECIFIER_UPPER}" - INTERFACE - $ - ) - target_compile_definitions( - "CMSIS_Device_${SPECIFIER_UPPER}" - INTERFACE - "STM32${SERIES_UPPER}xx" - "USE_HAL_DRIVER" - ) + if(NOT ${ARGC} EQUAL 6) + message( + FATAL_ERROR + "You called add_arm_cmsis_interface with an unsupported number of inputs/arguments! Do better please :)" + ) + endif() + + set( + one_value_args + SERIES + SPECIFIER + GIT_TAG + ) + unset(ARM_CMSIS_INTERFACE_ARG_SERIES) + unset(ARM_CMSIS_INTERFACE_ARG_SPECIFIER) + unset(ARM_CMSIS_INTERFACE_ARG_GIT_TAG) + cmake_parse_arguments( + "ARM_CMSIS_INTERFACE_ARG" + "" + "${one_value_args}" + "" + ${ARGN} + ) + + string(LENGTH "${ARM_CMSIS_INTERFACE_ARG_SERIES}" SERIES_LENGTH) + if(NOT SERIES_LENGTH EQUAL 2) + message( + FATAL_ERROR + "SERIES '${ARM_CMSIS_INTERFACE_ARG_SERIES}' must be 2 characters long (ie 'g4')" + ) + endif() + string(TOLOWER "${ARM_CMSIS_INTERFACE_ARG_SERIES}" SERIES_LOWER) + + string(LENGTH "${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}" SPECIFIER_LENGTH) + if(SPECIFIER_LENGTH LESS 6) + message( + FATAL_ERROR + "SPECIFIER '${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}' must be at least 6 characters long (ie 'g474re' or 'g474ret6')" + ) + endif() + string(TOLOWER "${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}" SPECIFIER_LOWER) + string(TOUPPER "${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}" SPECIFIER_UPPER) + + string( + FIND "${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}" + "${ARM_CMSIS_INTERFACE_ARG_SERIES}" + SERIES_POSITION_IN_SPECIFIER + ) + if(NOT SERIES_POSITION_IN_SPECIFIER EQUAL 0) + message( + FATAL_ERROR + "SPECIFIER '${ARM_CMSIS_INTERFACE_ARG_SPECIFIER}' must start with SERIES '${ARM_CMSIS_INTERFACE_ARG_SERIES}' at the beginning (eg 'g4' and 'g474ret6')" + ) + endif() + + if(TARGET CMSIS_Device_${SPECIFIER_UPPER}) + return() + endif() + + download_git( + NAME "cmsis_device_${SERIES_LOWER}" + GIT_REPOSITORY "https://github.com/STMicroelectronics/cmsis-device-${SERIES_LOWER}.git" + GIT_TAG ${ARM_CMSIS_INTERFACE_ARG_GIT_TAG} + TARGET_FOLDER "Include" + OUTPUT_PATH_VAR CMSIS_DEVICE_PATH + ) + message( + STATUS + "Successfully fetched content for ARM CMSIS device ${SPECIFIER_UPPER} from ${ARM_CMSIS_INTERFACE_ARG_GIT_TAG} to ${CMSIS_DEVICE_PATH}" + ) + add_library("CMSIS_Device_${SPECIFIER_UPPER}" INTERFACE) + target_include_directories( + "CMSIS_Device_${SPECIFIER_UPPER}" + INTERFACE + $ + ) + target_compile_definitions( + "CMSIS_Device_${SPECIFIER_UPPER}" + INTERFACE + "STM32${SERIES_UPPER}xx" + "USE_HAL_DRIVER" + ) endfunction() #[[ @@ -247,67 +247,67 @@ endfunction() @remark Prefer calling add_project() instead of this function directly ]] function(add_stm32_hal_interface) - if(NOT ${ARGC} EQUAL 4) - message( - FATAL_ERROR - "You called add_stm32_hal_interface with an unsupported number of inputs/arguments! Do better please :)" - ) - endif() - - set( - one_value_args - SERIES - GIT_TAG - ) - cmake_parse_arguments("STM32_HAL_ARG" "" "${one_value_args}" "" ${ARGN}) - - message( - VERBOSE - "Adding STM32 HAL driver interface for SERIES '${STM32_HAL_ARG_SERIES}' with GIT_TAG '${STM32_HAL_ARG_GIT_TAG}'" - ) - - string(LENGTH "${STM32_HAL_ARG_SERIES}" SERIES_LENGTH) - if(NOT SERIES_LENGTH EQUAL 2) - message( - FATAL_ERROR - "SERIES '${STM32_HAL_ARG_SERIES}' must be 2 characters long (ie 'g4')" - ) - endif() - - string(TOLOWER "${STM32_HAL_ARG_SERIES}" SERIES_LOWER) - string(TOUPPER "${STM32_HAL_ARG_SERIES}" SERIES_UPPER) - - if(TARGET STM32HAL_${SERIES_UPPER}) - return() - endif() - - download_git( - NAME "stm32_hal_driver_${SERIES_LOWER}" - GIT_REPOSITORY "https://github.com/STMicroelectronics/stm32${SERIES_LOWER}xx-hal-driver.git" - GIT_TAG ${STM32_HAL_ARG_GIT_TAG} - TARGET_FOLDER "Inc Src" - OUTPUT_PATH_VAR STM32_HAL_DRIVER_PATH - ) - message( - STATUS - "Successfully fetched content for STM32 HAL driver ${SERIES_UPPER} from ${STM32_HAL_ARG_GIT_TAG} to ${STM32_HAL_DRIVER_PATH}" - ) - add_library("STM32HAL_${SERIES_UPPER}" INTERFACE) - - target_include_directories( - "STM32HAL_${SERIES_UPPER}" - INTERFACE - $ - $ - ) - - file( - GLOB_RECURSE HAL_SOURCES - CONFIGURE_DEPENDS - "${STM32_HAL_DRIVER_PATH}/Src/*.c" - ) - list(FILTER HAL_SOURCES EXCLUDE REGEX ".*_template\.c$") - target_sources("STM32HAL_${SERIES_UPPER}" INTERFACE ${HAL_SOURCES}) + if(NOT ${ARGC} EQUAL 4) + message( + FATAL_ERROR + "You called add_stm32_hal_interface with an unsupported number of inputs/arguments! Do better please :)" + ) + endif() + + set( + one_value_args + SERIES + GIT_TAG + ) + cmake_parse_arguments("STM32_HAL_ARG" "" "${one_value_args}" "" ${ARGN}) + + message( + VERBOSE + "Adding STM32 HAL driver interface for SERIES '${STM32_HAL_ARG_SERIES}' with GIT_TAG '${STM32_HAL_ARG_GIT_TAG}'" + ) + + string(LENGTH "${STM32_HAL_ARG_SERIES}" SERIES_LENGTH) + if(NOT SERIES_LENGTH EQUAL 2) + message( + FATAL_ERROR + "SERIES '${STM32_HAL_ARG_SERIES}' must be 2 characters long (ie 'g4')" + ) + endif() + + string(TOLOWER "${STM32_HAL_ARG_SERIES}" SERIES_LOWER) + string(TOUPPER "${STM32_HAL_ARG_SERIES}" SERIES_UPPER) + + if(TARGET STM32HAL_${SERIES_UPPER}) + return() + endif() + + download_git( + NAME "stm32_hal_driver_${SERIES_LOWER}" + GIT_REPOSITORY "https://github.com/STMicroelectronics/stm32${SERIES_LOWER}xx-hal-driver.git" + GIT_TAG ${STM32_HAL_ARG_GIT_TAG} + TARGET_FOLDER "Inc Src" + OUTPUT_PATH_VAR STM32_HAL_DRIVER_PATH + ) + message( + STATUS + "Successfully fetched content for STM32 HAL driver ${SERIES_UPPER} from ${STM32_HAL_ARG_GIT_TAG} to ${STM32_HAL_DRIVER_PATH}" + ) + add_library("STM32HAL_${SERIES_UPPER}" INTERFACE) + + target_include_directories( + "STM32HAL_${SERIES_UPPER}" + INTERFACE + $ + $ + ) + + file( + GLOB_RECURSE HAL_SOURCES + CONFIGURE_DEPENDS + "${STM32_HAL_DRIVER_PATH}/Src/*.c" + ) + list(FILTER HAL_SOURCES EXCLUDE REGEX ".*_template\.c$") + target_sources("STM32HAL_${SERIES_UPPER}" INTERFACE ${HAL_SOURCES}) endfunction() #[[ @@ -322,83 +322,83 @@ endfunction() @note Link your user code against "${NAME}_USER_CODE" to ensure proper linking with the STM32 HAL and CMSIS libraries ]] function(add_project) - if(NOT ${ARGC} EQUAL 14) - message( - FATAL_ERROR - "You called add_project with an unsupported number of inputs/arguments! Do better please :)" - ) - endif() - - set( - one_value_args - NAME - PATH - SERIES - SPECIFIER - HAL_GIT_TAG - CMSIS_GIT_TAG - CMSIS_MAJOR - ) - cmake_parse_arguments("ARG" "" "${one_value_args}" "" ${ARGN}) - string(TOUPPER "${ARG_SERIES}" SERIES_UPPER) - string(TOLOWER "${ARG_SERIES}" SERIES_LOWER) - string(TOUPPER "${ARG_SPECIFIER}" SPECIFIER_UPPER) - - message( - DEBUG - "Adding project '${ARG_NAME}' at path '${ARG_PATH}' with SERIES '${ARG_SERIES}', SPECIFIER '${ARG_SPECIFIER}', HAL_GIT_TAG '${ARG_HAL_GIT_TAG}', CMSIS_GIT_TAG '${ARG_CMSIS_GIT_TAG}', and CMSIS_MAJOR '${ARG_CMSIS_MAJOR}'" - ) - - add_arm_cmsis_interface( - SERIES ${ARG_SERIES} - SPECIFIER ${ARG_SPECIFIER} - GIT_TAG ${ARG_CMSIS_GIT_TAG} - ) - - add_stm32_hal_interface( - SERIES ${ARG_SERIES} - GIT_TAG ${ARG_HAL_GIT_TAG} - ) - - if(CMAKE_PRESET_NAME STREQUAL "HOOTLTest") - # TODO Later, out of scope for now - else() - set(TARGET_NAME "${ARG_NAME}") - message(STATUS "Adding project '${TARGET_NAME}'") - add_executable("${TARGET_NAME}") - - include( - "${PROJECT_SOURCE_DIR}/Lib/Vendor/TargetFlags/stm32${SERIES_LOWER}xx.cmake" - ) - - target_link_libraries( - "${TARGET_NAME}" - PRIVATE - "CMSIS_Device_${SPECIFIER_UPPER}" - "CMSIS_${ARG_CMSIS_MAJOR}_Core" - "STM32HAL_${SERIES_UPPER}" - GLOBALSHARE_LIB - m - ) - - target_link_options( - "${TARGET_NAME}" - PRIVATE - "LINKER:-Map=$/$.map" - ) - - target_compile_definitions( - "${TARGET_NAME}" - PRIVATE - USE_HAL_DRIVER - USE_FULL_LL_DRIVER - STM32${SERIES_UPPER}xx - ) - endif() - - if(DEFINED NODE) - target_compile_definitions("${ARG_NAME}" PRIVATE NODE=${NODE}) - endif() + if(NOT ${ARGC} EQUAL 14) + message( + FATAL_ERROR + "You called add_project with an unsupported number of inputs/arguments! Do better please :)" + ) + endif() + + set( + one_value_args + NAME + PATH + SERIES + SPECIFIER + HAL_GIT_TAG + CMSIS_GIT_TAG + CMSIS_MAJOR + ) + cmake_parse_arguments("ARG" "" "${one_value_args}" "" ${ARGN}) + string(TOUPPER "${ARG_SERIES}" SERIES_UPPER) + string(TOLOWER "${ARG_SERIES}" SERIES_LOWER) + string(TOUPPER "${ARG_SPECIFIER}" SPECIFIER_UPPER) + + message( + DEBUG + "Adding project '${ARG_NAME}' at path '${ARG_PATH}' with SERIES '${ARG_SERIES}', SPECIFIER '${ARG_SPECIFIER}', HAL_GIT_TAG '${ARG_HAL_GIT_TAG}', CMSIS_GIT_TAG '${ARG_CMSIS_GIT_TAG}', and CMSIS_MAJOR '${ARG_CMSIS_MAJOR}'" + ) + + add_arm_cmsis_interface( + SERIES ${ARG_SERIES} + SPECIFIER ${ARG_SPECIFIER} + GIT_TAG ${ARG_CMSIS_GIT_TAG} + ) + + add_stm32_hal_interface( + SERIES ${ARG_SERIES} + GIT_TAG ${ARG_HAL_GIT_TAG} + ) + + if(CMAKE_PRESET_NAME STREQUAL "HOOTLTest") + # TODO Later, out of scope for now + else() + set(TARGET_NAME "${ARG_NAME}") + message(STATUS "Adding project '${TARGET_NAME}'") + add_executable("${TARGET_NAME}") + + include( + "${PROJECT_SOURCE_DIR}/Lib/Vendor/TargetFlags/stm32${SERIES_LOWER}xx.cmake" + ) + + target_link_libraries( + "${TARGET_NAME}" + PRIVATE + "CMSIS_Device_${SPECIFIER_UPPER}" + "CMSIS_${ARG_CMSIS_MAJOR}_Core" + "STM32HAL_${SERIES_UPPER}" + GLOBALSHARE_LIB + m + ) + + target_link_options( + "${TARGET_NAME}" + PRIVATE + "LINKER:-Map=$/$.map" + ) + + target_compile_definitions( + "${TARGET_NAME}" + PRIVATE + USE_HAL_DRIVER + USE_FULL_LL_DRIVER + STM32${SERIES_UPPER}xx + ) + endif() + + if(DEFINED NODE) + target_compile_definitions("${ARG_NAME}" PRIVATE NODE=${NODE}) + endif() if(IS_ABSOLUTE "${ARG_PATH}") add_subdirectory("${ARG_PATH}") From 25b43e25460ed26740ae71bc31f4aa3e1dc9fcf5 Mon Sep 17 00:00:00 2001 From: github-actions <41898282+github-actions[bot]@users.noreply.github.com> Date: Sun, 23 Aug 2026 23:07:06 +0000 Subject: [PATCH 08/17] Automatic Clang-Format: Standardized formatting automatically --- Testbench/CUBEMXTESTING/Core/Inc/fdcan.h | 1 - Testbench/CUBEMXTESTING/Core/Inc/gpio.h | 1 - Testbench/CUBEMXTESTING/Core/Inc/main.h | 13 +- .../CUBEMXTESTING/Core/Inc/stm32_assert.h | 17 +- .../Core/Inc/stm32g4xx_hal_conf.h | 215 +++---- Testbench/CUBEMXTESTING/Core/Inc/tim.h | 1 - Testbench/CUBEMXTESTING/Core/Inc/usart.h | 1 - Testbench/CUBEMXTESTING/Core/Src/fdcan.c | 525 +++++++++-------- Testbench/CUBEMXTESTING/Core/Src/gpio.c | 537 +++++++++--------- Testbench/CUBEMXTESTING/Core/Src/main.c | 169 +++--- .../Core/Src/stm32g4xx_hal_msp.c | 24 +- .../CUBEMXTESTING/Core/Src/stm32g4xx_it.c | 211 ++++--- Testbench/CUBEMXTESTING/Core/Src/tim.c | 113 ++-- Testbench/CUBEMXTESTING/Core/Src/usart.c | 164 +++--- 14 files changed, 972 insertions(+), 1020 deletions(-) diff --git a/Testbench/CUBEMXTESTING/Core/Inc/fdcan.h b/Testbench/CUBEMXTESTING/Core/Inc/fdcan.h index 21271cf64..3597c6476 100644 --- a/Testbench/CUBEMXTESTING/Core/Inc/fdcan.h +++ b/Testbench/CUBEMXTESTING/Core/Inc/fdcan.h @@ -55,4 +55,3 @@ void MX_FDCAN3_Init(void); #endif #endif /* __FDCAN_H__ */ - diff --git a/Testbench/CUBEMXTESTING/Core/Inc/gpio.h b/Testbench/CUBEMXTESTING/Core/Inc/gpio.h index 03c2faca5..37dcc0a5c 100644 --- a/Testbench/CUBEMXTESTING/Core/Inc/gpio.h +++ b/Testbench/CUBEMXTESTING/Core/Inc/gpio.h @@ -46,4 +46,3 @@ void MX_GPIO_Init(void); } #endif #endif /*__ GPIO_H__ */ - diff --git a/Testbench/CUBEMXTESTING/Core/Inc/main.h b/Testbench/CUBEMXTESTING/Core/Inc/main.h index 2b50abc31..cbeced83f 100644 --- a/Testbench/CUBEMXTESTING/Core/Inc/main.h +++ b/Testbench/CUBEMXTESTING/Core/Inc/main.h @@ -28,17 +28,16 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" - -#include "stm32g4xx_ll_rcc.h" #include "stm32g4xx_ll_bus.h" -#include "stm32g4xx_ll_crs.h" -#include "stm32g4xx_ll_system.h" -#include "stm32g4xx_ll_exti.h" #include "stm32g4xx_ll_cortex.h" -#include "stm32g4xx_ll_utils.h" -#include "stm32g4xx_ll_pwr.h" +#include "stm32g4xx_ll_crs.h" #include "stm32g4xx_ll_dma.h" +#include "stm32g4xx_ll_exti.h" #include "stm32g4xx_ll_gpio.h" +#include "stm32g4xx_ll_pwr.h" +#include "stm32g4xx_ll_rcc.h" +#include "stm32g4xx_ll_system.h" +#include "stm32g4xx_ll_utils.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ diff --git a/Testbench/CUBEMXTESTING/Core/Inc/stm32_assert.h b/Testbench/CUBEMXTESTING/Core/Inc/stm32_assert.h index e645b21ee..92460620f 100644 --- a/Testbench/CUBEMXTESTING/Core/Inc/stm32_assert.h +++ b/Testbench/CUBEMXTESTING/Core/Inc/stm32_assert.h @@ -29,15 +29,15 @@ extern "C" { /* Exported constants --------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT +#ifdef USE_FULL_ASSERT /** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) /* Exported functions ------------------------------------------------------- */ void assert_failed(uint8_t *file, uint32_t line); @@ -50,4 +50,3 @@ void assert_failed(uint8_t *file, uint32_t line); #endif #endif /* __STM32_ASSERT_H */ - diff --git a/Testbench/CUBEMXTESTING/Core/Inc/stm32g4xx_hal_conf.h b/Testbench/CUBEMXTESTING/Core/Inc/stm32g4xx_hal_conf.h index e4db34d37..d12d585bd 100644 --- a/Testbench/CUBEMXTESTING/Core/Inc/stm32g4xx_hal_conf.h +++ b/Testbench/CUBEMXTESTING/Core/Inc/stm32g4xx_hal_conf.h @@ -23,7 +23,7 @@ #define STM32G4xx_HAL_CONF_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Exported types ------------------------------------------------------------*/ @@ -31,12 +31,12 @@ /* ########################## Module Selection ############################## */ /** - * @brief This is the list of modules to be used in the HAL driver - */ + * @brief This is the list of modules to be used in the HAL driver + */ #define HAL_MODULE_ENABLED - /*#define HAL_ADC_MODULE_ENABLED */ +/*#define HAL_ADC_MODULE_ENABLED */ /*#define HAL_COMP_MODULE_ENABLED */ /*#define HAL_CORDIC_MODULE_ENABLED */ /*#define HAL_CRC_MODULE_ENABLED */ @@ -76,123 +76,124 @@ /* ########################## Register Callbacks selection ############################## */ /** - * @brief This is the list of modules where register callback can be used - */ -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U -#define USE_HAL_COMP_REGISTER_CALLBACKS 0U -#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U -#define USE_HAL_EXTI_REGISTER_CALLBACKS 0U -#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U -#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U -#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U -#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U -#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U -#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U -#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U -#define USE_HAL_UART_REGISTER_CALLBACKS 0U -#define USE_HAL_USART_REGISTER_CALLBACKS 0U -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U + * @brief This is the list of modules where register callback can be used + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U +#define USE_HAL_COMP_REGISTER_CALLBACKS 0U +#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U +#define USE_HAL_EXTI_REGISTER_CALLBACKS 0U +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U +#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U +#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U +#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U +#define USE_HAL_UART_REGISTER_CALLBACKS 0U +#define USE_HAL_USART_REGISTER_CALLBACKS 0U +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* ########################## Oscillator Values adaptation ####################*/ /** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE (16000000UL) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined(HSE_VALUE) +#define HSE_VALUE (16000000UL) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined(HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ /** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined(HSI_VALUE) +#define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ /** - * @brief Internal High Speed oscillator (HSI48) value for USB FS and RNG. - * This internal oscillator is mainly dedicated to provide a high precision clock to - * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. - * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency - * which is subject to manufacturing process variations. - */ -#if !defined (HSI48_VALUE) - #define HSI48_VALUE (48000000UL) /*!< Value of the Internal High Speed oscillator for USB FS/RNG in Hz. - The real value my vary depending on manufacturing process variations.*/ -#endif /* HSI48_VALUE */ + * @brief Internal High Speed oscillator (HSI48) value for USB FS and RNG. + * This internal oscillator is mainly dedicated to provide a high precision clock to + * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. + * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency + * which is subject to manufacturing process variations. + */ +#if !defined(HSI48_VALUE) +#define HSI48_VALUE \ + (48000000UL) /*!< Value of the Internal High Speed oscillator for USB FS/RNG in Hz. \ + The real value my vary depending on manufacturing process variations.*/ +#endif /* HSI48_VALUE */ /** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined(LSI_VALUE) /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature.*/ -#define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/ -#endif /* LSI_VALUE */ +#define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /** - * @brief External Low Speed oscillator (LSE) value. - * This value is used by the UART, RTC HAL module to compute the system frequency - */ -#if !defined (LSE_VALUE) -#define LSE_VALUE (32768UL) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined(LSE_VALUE) +#define LSE_VALUE (32768UL) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ -#if !defined (LSE_STARTUP_TIMEOUT) -#define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ +#if !defined(LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ /** - * @brief External clock source for I2S and SAI peripherals - * This value is used by the I2S and SAI HAL modules to compute the I2S and SAI clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined (EXTERNAL_CLOCK_VALUE) -#define EXTERNAL_CLOCK_VALUE (12288000UL) /*!< Value of the External oscillator in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ + * @brief External clock source for I2S and SAI peripherals + * This value is used by the I2S and SAI HAL modules to compute the I2S and SAI clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined(EXTERNAL_CLOCK_VALUE) +#define EXTERNAL_CLOCK_VALUE (12288000UL) /*!< Value of the External oscillator in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ /* Tip: To avoid modifying this file each time you need to use different HSE, === you can define the HSE value in your toolchain compiler preprocessor. */ /* ########################### System Configuration ######################### */ /** - * @brief This is the HAL system configuration section - */ + * @brief This is the HAL system configuration section + */ -#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority (lowest by default) */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 0U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U +#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority (lowest by default) */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 0U +#define INSTRUCTION_CACHE_ENABLE 1U +#define DATA_CACHE_ENABLE 1U /* ########################## Assert Selection ############################## */ /** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ - #define USE_FULL_ASSERT 1U + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +#define USE_FULL_ASSERT 1U /* ################## SPI peripheral configuration ########################## */ @@ -201,12 +202,12 @@ The real value may vary depending on the variations in voltage and temperature.* * Deactivated: CRC code cleaned from driver */ -#define USE_SPI_CRC 0U +#define USE_SPI_CRC 0U /* Includes ------------------------------------------------------------------*/ /** - * @brief Include module's header file - */ + * @brief Include module's header file + */ #ifdef HAL_RCC_MODULE_ENABLED #include "stm32g4xx_hal_rcc.h" @@ -357,15 +358,15 @@ The real value may vary depending on the variations in voltage and temperature.* #endif /* HAL_WWDG_MODULE_ENABLED */ /* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT +#ifdef USE_FULL_ASSERT /** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) /* Exported functions ------------------------------------------------------- */ void assert_failed(uint8_t *file, uint32_t line); diff --git a/Testbench/CUBEMXTESTING/Core/Inc/tim.h b/Testbench/CUBEMXTESTING/Core/Inc/tim.h index b90657cf4..2d20bd560 100644 --- a/Testbench/CUBEMXTESTING/Core/Inc/tim.h +++ b/Testbench/CUBEMXTESTING/Core/Inc/tim.h @@ -49,4 +49,3 @@ void MX_TIM5_Init(void); #endif #endif /* __TIM_H__ */ - diff --git a/Testbench/CUBEMXTESTING/Core/Inc/usart.h b/Testbench/CUBEMXTESTING/Core/Inc/usart.h index 49dd0cccc..bdec0c9cb 100644 --- a/Testbench/CUBEMXTESTING/Core/Inc/usart.h +++ b/Testbench/CUBEMXTESTING/Core/Inc/usart.h @@ -49,4 +49,3 @@ void MX_LPUART1_UART_Init(void); #endif #endif /* __USART_H__ */ - diff --git a/Testbench/CUBEMXTESTING/Core/Src/fdcan.c b/Testbench/CUBEMXTESTING/Core/Src/fdcan.c index 08b2a1b8a..30b3c9dc1 100644 --- a/Testbench/CUBEMXTESTING/Core/Src/fdcan.c +++ b/Testbench/CUBEMXTESTING/Core/Src/fdcan.c @@ -32,298 +32,281 @@ FDCAN_HandleTypeDef hfdcan3; void MX_FDCAN1_Init(void) { - /* USER CODE BEGIN FDCAN1_Init 0 */ - - /* USER CODE END FDCAN1_Init 0 */ - - /* USER CODE BEGIN FDCAN1_Init 1 */ - - /* USER CODE END FDCAN1_Init 1 */ - hfdcan1.Instance = FDCAN1; - hfdcan1.Init.ClockDivider = FDCAN_CLOCK_DIV1; - hfdcan1.Init.FrameFormat = FDCAN_FRAME_CLASSIC; - hfdcan1.Init.Mode = FDCAN_MODE_INTERNAL_LOOPBACK; - hfdcan1.Init.AutoRetransmission = ENABLE; - hfdcan1.Init.TransmitPause = DISABLE; - hfdcan1.Init.ProtocolException = ENABLE; - hfdcan1.Init.NominalPrescaler = 1; - hfdcan1.Init.NominalSyncJumpWidth = 16; - hfdcan1.Init.NominalTimeSeg1 = 119; - hfdcan1.Init.NominalTimeSeg2 = 40; - hfdcan1.Init.DataPrescaler = 8; - hfdcan1.Init.DataSyncJumpWidth = 16; - hfdcan1.Init.DataTimeSeg1 = 14; - hfdcan1.Init.DataTimeSeg2 = 5; - hfdcan1.Init.StdFiltersNbr = 0; - hfdcan1.Init.ExtFiltersNbr = 2; - hfdcan1.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; - if (HAL_FDCAN_Init(&hfdcan1) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN FDCAN1_Init 2 */ - - /* USER CODE END FDCAN1_Init 2 */ - + /* USER CODE BEGIN FDCAN1_Init 0 */ + + /* USER CODE END FDCAN1_Init 0 */ + + /* USER CODE BEGIN FDCAN1_Init 1 */ + + /* USER CODE END FDCAN1_Init 1 */ + hfdcan1.Instance = FDCAN1; + hfdcan1.Init.ClockDivider = FDCAN_CLOCK_DIV1; + hfdcan1.Init.FrameFormat = FDCAN_FRAME_CLASSIC; + hfdcan1.Init.Mode = FDCAN_MODE_INTERNAL_LOOPBACK; + hfdcan1.Init.AutoRetransmission = ENABLE; + hfdcan1.Init.TransmitPause = DISABLE; + hfdcan1.Init.ProtocolException = ENABLE; + hfdcan1.Init.NominalPrescaler = 1; + hfdcan1.Init.NominalSyncJumpWidth = 16; + hfdcan1.Init.NominalTimeSeg1 = 119; + hfdcan1.Init.NominalTimeSeg2 = 40; + hfdcan1.Init.DataPrescaler = 8; + hfdcan1.Init.DataSyncJumpWidth = 16; + hfdcan1.Init.DataTimeSeg1 = 14; + hfdcan1.Init.DataTimeSeg2 = 5; + hfdcan1.Init.StdFiltersNbr = 0; + hfdcan1.Init.ExtFiltersNbr = 2; + hfdcan1.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; + if (HAL_FDCAN_Init(&hfdcan1) != HAL_OK) { + Error_Handler(); + } + /* USER CODE BEGIN FDCAN1_Init 2 */ + + /* USER CODE END FDCAN1_Init 2 */ } /* FDCAN2 init function */ void MX_FDCAN2_Init(void) { - /* USER CODE BEGIN FDCAN2_Init 0 */ - - /* USER CODE END FDCAN2_Init 0 */ - - /* USER CODE BEGIN FDCAN2_Init 1 */ - - /* USER CODE END FDCAN2_Init 1 */ - hfdcan2.Instance = FDCAN2; - hfdcan2.Init.ClockDivider = FDCAN_CLOCK_DIV1; - hfdcan2.Init.FrameFormat = FDCAN_FRAME_CLASSIC; - hfdcan2.Init.Mode = FDCAN_MODE_INTERNAL_LOOPBACK; - hfdcan2.Init.AutoRetransmission = ENABLE; - hfdcan2.Init.TransmitPause = DISABLE; - hfdcan2.Init.ProtocolException = ENABLE; - hfdcan2.Init.NominalPrescaler = 1; - hfdcan2.Init.NominalSyncJumpWidth = 16; - hfdcan2.Init.NominalTimeSeg1 = 119; - hfdcan2.Init.NominalTimeSeg2 = 40; - hfdcan2.Init.DataPrescaler = 8; - hfdcan2.Init.DataSyncJumpWidth = 16; - hfdcan2.Init.DataTimeSeg1 = 14; - hfdcan2.Init.DataTimeSeg2 = 5; - hfdcan2.Init.StdFiltersNbr = 0; - hfdcan2.Init.ExtFiltersNbr = 2; - hfdcan2.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; - if (HAL_FDCAN_Init(&hfdcan2) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN FDCAN2_Init 2 */ - - /* USER CODE END FDCAN2_Init 2 */ - + /* USER CODE BEGIN FDCAN2_Init 0 */ + + /* USER CODE END FDCAN2_Init 0 */ + + /* USER CODE BEGIN FDCAN2_Init 1 */ + + /* USER CODE END FDCAN2_Init 1 */ + hfdcan2.Instance = FDCAN2; + hfdcan2.Init.ClockDivider = FDCAN_CLOCK_DIV1; + hfdcan2.Init.FrameFormat = FDCAN_FRAME_CLASSIC; + hfdcan2.Init.Mode = FDCAN_MODE_INTERNAL_LOOPBACK; + hfdcan2.Init.AutoRetransmission = ENABLE; + hfdcan2.Init.TransmitPause = DISABLE; + hfdcan2.Init.ProtocolException = ENABLE; + hfdcan2.Init.NominalPrescaler = 1; + hfdcan2.Init.NominalSyncJumpWidth = 16; + hfdcan2.Init.NominalTimeSeg1 = 119; + hfdcan2.Init.NominalTimeSeg2 = 40; + hfdcan2.Init.DataPrescaler = 8; + hfdcan2.Init.DataSyncJumpWidth = 16; + hfdcan2.Init.DataTimeSeg1 = 14; + hfdcan2.Init.DataTimeSeg2 = 5; + hfdcan2.Init.StdFiltersNbr = 0; + hfdcan2.Init.ExtFiltersNbr = 2; + hfdcan2.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; + if (HAL_FDCAN_Init(&hfdcan2) != HAL_OK) { + Error_Handler(); + } + /* USER CODE BEGIN FDCAN2_Init 2 */ + + /* USER CODE END FDCAN2_Init 2 */ } /* FDCAN3 init function */ void MX_FDCAN3_Init(void) { - /* USER CODE BEGIN FDCAN3_Init 0 */ - - /* USER CODE END FDCAN3_Init 0 */ - - /* USER CODE BEGIN FDCAN3_Init 1 */ - - /* USER CODE END FDCAN3_Init 1 */ - hfdcan3.Instance = FDCAN3; - hfdcan3.Init.ClockDivider = FDCAN_CLOCK_DIV1; - hfdcan3.Init.FrameFormat = FDCAN_FRAME_CLASSIC; - hfdcan3.Init.Mode = FDCAN_MODE_INTERNAL_LOOPBACK; - hfdcan3.Init.AutoRetransmission = DISABLE; - hfdcan3.Init.TransmitPause = DISABLE; - hfdcan3.Init.ProtocolException = DISABLE; - hfdcan3.Init.NominalPrescaler = 16; - hfdcan3.Init.NominalSyncJumpWidth = 1; - hfdcan3.Init.NominalTimeSeg1 = 1; - hfdcan3.Init.NominalTimeSeg2 = 1; - hfdcan3.Init.DataPrescaler = 1; - hfdcan3.Init.DataSyncJumpWidth = 1; - hfdcan3.Init.DataTimeSeg1 = 1; - hfdcan3.Init.DataTimeSeg2 = 1; - hfdcan3.Init.StdFiltersNbr = 0; - hfdcan3.Init.ExtFiltersNbr = 0; - hfdcan3.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; - if (HAL_FDCAN_Init(&hfdcan3) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN FDCAN3_Init 2 */ - - /* USER CODE END FDCAN3_Init 2 */ - + /* USER CODE BEGIN FDCAN3_Init 0 */ + + /* USER CODE END FDCAN3_Init 0 */ + + /* USER CODE BEGIN FDCAN3_Init 1 */ + + /* USER CODE END FDCAN3_Init 1 */ + hfdcan3.Instance = FDCAN3; + hfdcan3.Init.ClockDivider = FDCAN_CLOCK_DIV1; + hfdcan3.Init.FrameFormat = FDCAN_FRAME_CLASSIC; + hfdcan3.Init.Mode = FDCAN_MODE_INTERNAL_LOOPBACK; + hfdcan3.Init.AutoRetransmission = DISABLE; + hfdcan3.Init.TransmitPause = DISABLE; + hfdcan3.Init.ProtocolException = DISABLE; + hfdcan3.Init.NominalPrescaler = 16; + hfdcan3.Init.NominalSyncJumpWidth = 1; + hfdcan3.Init.NominalTimeSeg1 = 1; + hfdcan3.Init.NominalTimeSeg2 = 1; + hfdcan3.Init.DataPrescaler = 1; + hfdcan3.Init.DataSyncJumpWidth = 1; + hfdcan3.Init.DataTimeSeg1 = 1; + hfdcan3.Init.DataTimeSeg2 = 1; + hfdcan3.Init.StdFiltersNbr = 0; + hfdcan3.Init.ExtFiltersNbr = 0; + hfdcan3.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; + if (HAL_FDCAN_Init(&hfdcan3) != HAL_OK) { + Error_Handler(); + } + /* USER CODE BEGIN FDCAN3_Init 2 */ + + /* USER CODE END FDCAN3_Init 2 */ } -static uint32_t HAL_RCC_FDCAN_CLK_ENABLED=0; +static uint32_t HAL_RCC_FDCAN_CLK_ENABLED = 0; -void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* fdcanHandle) +void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *fdcanHandle) { - GPIO_InitTypeDef GPIO_InitStruct = {0}; - if(fdcanHandle->Instance==FDCAN1) - { - /* USER CODE BEGIN FDCAN1_MspInit 0 */ - - /* USER CODE END FDCAN1_MspInit 0 */ - LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_PCLK1); - - /* FDCAN1 clock enable */ - HAL_RCC_FDCAN_CLK_ENABLED++; - if(HAL_RCC_FDCAN_CLK_ENABLED==1){ - __HAL_RCC_FDCAN_CLK_ENABLE(); - } - - __HAL_RCC_GPIOB_CLK_ENABLE(); - /**FDCAN1 GPIO Configuration - PB8-BOOT0 ------> FDCAN1_RX - PB9 ------> FDCAN1_TX - */ - GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN1; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /* FDCAN1 interrupt Init */ - HAL_NVIC_SetPriority(FDCAN1_IT0_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(FDCAN1_IT0_IRQn); - /* USER CODE BEGIN FDCAN1_MspInit 1 */ - - /* USER CODE END FDCAN1_MspInit 1 */ - } - else if(fdcanHandle->Instance==FDCAN2) - { - /* USER CODE BEGIN FDCAN2_MspInit 0 */ - - /* USER CODE END FDCAN2_MspInit 0 */ - - LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_PCLK1); - - /* FDCAN2 clock enable */ - HAL_RCC_FDCAN_CLK_ENABLED++; - if(HAL_RCC_FDCAN_CLK_ENABLED==1){ - __HAL_RCC_FDCAN_CLK_ENABLE(); - } - - __HAL_RCC_GPIOB_CLK_ENABLE(); - /**FDCAN2 GPIO Configuration - PB12 ------> FDCAN2_RX - PB13 ------> FDCAN2_TX - */ - GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_13; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN2; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /* FDCAN2 interrupt Init */ - HAL_NVIC_SetPriority(FDCAN2_IT0_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(FDCAN2_IT0_IRQn); - /* USER CODE BEGIN FDCAN2_MspInit 1 */ - - /* USER CODE END FDCAN2_MspInit 1 */ - } - else if(fdcanHandle->Instance==FDCAN3) - { - /* USER CODE BEGIN FDCAN3_MspInit 0 */ - - /* USER CODE END FDCAN3_MspInit 0 */ - - LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_PCLK1); - - /* FDCAN3 clock enable */ - HAL_RCC_FDCAN_CLK_ENABLED++; - if(HAL_RCC_FDCAN_CLK_ENABLED==1){ - __HAL_RCC_FDCAN_CLK_ENABLE(); - } - - __HAL_RCC_GPIOA_CLK_ENABLE(); - /**FDCAN3 GPIO Configuration - PA8 ------> FDCAN3_RX - PA15 ------> FDCAN3_TX - */ - GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_15; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF11_FDCAN3; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /* FDCAN3 interrupt Init */ - HAL_NVIC_SetPriority(FDCAN3_IT0_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(FDCAN3_IT0_IRQn); - /* USER CODE BEGIN FDCAN3_MspInit 1 */ - - /* USER CODE END FDCAN3_MspInit 1 */ - } + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if (fdcanHandle->Instance == FDCAN1) { + /* USER CODE BEGIN FDCAN1_MspInit 0 */ + + /* USER CODE END FDCAN1_MspInit 0 */ + LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_PCLK1); + + /* FDCAN1 clock enable */ + HAL_RCC_FDCAN_CLK_ENABLED++; + if (HAL_RCC_FDCAN_CLK_ENABLED == 1) { + __HAL_RCC_FDCAN_CLK_ENABLE(); + } + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**FDCAN1 GPIO Configuration + PB8-BOOT0 ------> FDCAN1_RX + PB9 ------> FDCAN1_TX + */ + GPIO_InitStruct.Pin = GPIO_PIN_8 | GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN1; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* FDCAN1 interrupt Init */ + HAL_NVIC_SetPriority(FDCAN1_IT0_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(FDCAN1_IT0_IRQn); + /* USER CODE BEGIN FDCAN1_MspInit 1 */ + + /* USER CODE END FDCAN1_MspInit 1 */ + } else if (fdcanHandle->Instance == FDCAN2) { + /* USER CODE BEGIN FDCAN2_MspInit 0 */ + + /* USER CODE END FDCAN2_MspInit 0 */ + + LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_PCLK1); + + /* FDCAN2 clock enable */ + HAL_RCC_FDCAN_CLK_ENABLED++; + if (HAL_RCC_FDCAN_CLK_ENABLED == 1) { + __HAL_RCC_FDCAN_CLK_ENABLE(); + } + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**FDCAN2 GPIO Configuration + PB12 ------> FDCAN2_RX + PB13 ------> FDCAN2_TX + */ + GPIO_InitStruct.Pin = GPIO_PIN_12 | GPIO_PIN_13; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN2; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* FDCAN2 interrupt Init */ + HAL_NVIC_SetPriority(FDCAN2_IT0_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(FDCAN2_IT0_IRQn); + /* USER CODE BEGIN FDCAN2_MspInit 1 */ + + /* USER CODE END FDCAN2_MspInit 1 */ + } else if (fdcanHandle->Instance == FDCAN3) { + /* USER CODE BEGIN FDCAN3_MspInit 0 */ + + /* USER CODE END FDCAN3_MspInit 0 */ + + LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_PCLK1); + + /* FDCAN3 clock enable */ + HAL_RCC_FDCAN_CLK_ENABLED++; + if (HAL_RCC_FDCAN_CLK_ENABLED == 1) { + __HAL_RCC_FDCAN_CLK_ENABLE(); + } + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**FDCAN3 GPIO Configuration + PA8 ------> FDCAN3_RX + PA15 ------> FDCAN3_TX + */ + GPIO_InitStruct.Pin = GPIO_PIN_8 | GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF11_FDCAN3; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* FDCAN3 interrupt Init */ + HAL_NVIC_SetPriority(FDCAN3_IT0_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(FDCAN3_IT0_IRQn); + /* USER CODE BEGIN FDCAN3_MspInit 1 */ + + /* USER CODE END FDCAN3_MspInit 1 */ + } } -void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef* fdcanHandle) +void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *fdcanHandle) { - if(fdcanHandle->Instance==FDCAN1) - { - /* USER CODE BEGIN FDCAN1_MspDeInit 0 */ - - /* USER CODE END FDCAN1_MspDeInit 0 */ - /* Peripheral clock disable */ - HAL_RCC_FDCAN_CLK_ENABLED--; - if(HAL_RCC_FDCAN_CLK_ENABLED==0){ - __HAL_RCC_FDCAN_CLK_DISABLE(); - } - - /**FDCAN1 GPIO Configuration - PB8-BOOT0 ------> FDCAN1_RX - PB9 ------> FDCAN1_TX - */ - HAL_GPIO_DeInit(GPIOB, GPIO_PIN_8|GPIO_PIN_9); - - /* FDCAN1 interrupt Deinit */ - HAL_NVIC_DisableIRQ(FDCAN1_IT0_IRQn); - /* USER CODE BEGIN FDCAN1_MspDeInit 1 */ - - /* USER CODE END FDCAN1_MspDeInit 1 */ - } - else if(fdcanHandle->Instance==FDCAN2) - { - /* USER CODE BEGIN FDCAN2_MspDeInit 0 */ - - /* USER CODE END FDCAN2_MspDeInit 0 */ - /* Peripheral clock disable */ - HAL_RCC_FDCAN_CLK_ENABLED--; - if(HAL_RCC_FDCAN_CLK_ENABLED==0){ - __HAL_RCC_FDCAN_CLK_DISABLE(); - } - - /**FDCAN2 GPIO Configuration - PB12 ------> FDCAN2_RX - PB13 ------> FDCAN2_TX - */ - HAL_GPIO_DeInit(GPIOB, GPIO_PIN_12|GPIO_PIN_13); - - /* FDCAN2 interrupt Deinit */ - HAL_NVIC_DisableIRQ(FDCAN2_IT0_IRQn); - /* USER CODE BEGIN FDCAN2_MspDeInit 1 */ - - /* USER CODE END FDCAN2_MspDeInit 1 */ - } - else if(fdcanHandle->Instance==FDCAN3) - { - /* USER CODE BEGIN FDCAN3_MspDeInit 0 */ - - /* USER CODE END FDCAN3_MspDeInit 0 */ - /* Peripheral clock disable */ - HAL_RCC_FDCAN_CLK_ENABLED--; - if(HAL_RCC_FDCAN_CLK_ENABLED==0){ - __HAL_RCC_FDCAN_CLK_DISABLE(); - } - - /**FDCAN3 GPIO Configuration - PA8 ------> FDCAN3_RX - PA15 ------> FDCAN3_TX - */ - HAL_GPIO_DeInit(GPIOA, GPIO_PIN_8|GPIO_PIN_15); - - /* FDCAN3 interrupt Deinit */ - HAL_NVIC_DisableIRQ(FDCAN3_IT0_IRQn); - /* USER CODE BEGIN FDCAN3_MspDeInit 1 */ - - /* USER CODE END FDCAN3_MspDeInit 1 */ - } + if (fdcanHandle->Instance == FDCAN1) { + /* USER CODE BEGIN FDCAN1_MspDeInit 0 */ + + /* USER CODE END FDCAN1_MspDeInit 0 */ + /* Peripheral clock disable */ + HAL_RCC_FDCAN_CLK_ENABLED--; + if (HAL_RCC_FDCAN_CLK_ENABLED == 0) { + __HAL_RCC_FDCAN_CLK_DISABLE(); + } + + /**FDCAN1 GPIO Configuration + PB8-BOOT0 ------> FDCAN1_RX + PB9 ------> FDCAN1_TX + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_8 | GPIO_PIN_9); + + /* FDCAN1 interrupt Deinit */ + HAL_NVIC_DisableIRQ(FDCAN1_IT0_IRQn); + /* USER CODE BEGIN FDCAN1_MspDeInit 1 */ + + /* USER CODE END FDCAN1_MspDeInit 1 */ + } else if (fdcanHandle->Instance == FDCAN2) { + /* USER CODE BEGIN FDCAN2_MspDeInit 0 */ + + /* USER CODE END FDCAN2_MspDeInit 0 */ + /* Peripheral clock disable */ + HAL_RCC_FDCAN_CLK_ENABLED--; + if (HAL_RCC_FDCAN_CLK_ENABLED == 0) { + __HAL_RCC_FDCAN_CLK_DISABLE(); + } + + /**FDCAN2 GPIO Configuration + PB12 ------> FDCAN2_RX + PB13 ------> FDCAN2_TX + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_12 | GPIO_PIN_13); + + /* FDCAN2 interrupt Deinit */ + HAL_NVIC_DisableIRQ(FDCAN2_IT0_IRQn); + /* USER CODE BEGIN FDCAN2_MspDeInit 1 */ + + /* USER CODE END FDCAN2_MspDeInit 1 */ + } else if (fdcanHandle->Instance == FDCAN3) { + /* USER CODE BEGIN FDCAN3_MspDeInit 0 */ + + /* USER CODE END FDCAN3_MspDeInit 0 */ + /* Peripheral clock disable */ + HAL_RCC_FDCAN_CLK_ENABLED--; + if (HAL_RCC_FDCAN_CLK_ENABLED == 0) { + __HAL_RCC_FDCAN_CLK_DISABLE(); + } + + /**FDCAN3 GPIO Configuration + PA8 ------> FDCAN3_RX + PA15 ------> FDCAN3_TX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_8 | GPIO_PIN_15); + + /* FDCAN3 interrupt Deinit */ + HAL_NVIC_DisableIRQ(FDCAN3_IT0_IRQn); + /* USER CODE BEGIN FDCAN3_MspDeInit 1 */ + + /* USER CODE END FDCAN3_MspDeInit 1 */ + } } /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ - diff --git a/Testbench/CUBEMXTESTING/Core/Src/gpio.c b/Testbench/CUBEMXTESTING/Core/Src/gpio.c index 96b5c07ab..4d07c7993 100644 --- a/Testbench/CUBEMXTESTING/Core/Src/gpio.c +++ b/Testbench/CUBEMXTESTING/Core/Src/gpio.c @@ -33,278 +33,277 @@ /* USER CODE END 1 */ /** Configure pins as - * Analog - * Input - * Output - * EVENT_OUT - * EXTI - * Free pins are configured automatically as Analog (this feature is enabled through - * the Code Generation settings) -*/ + * Analog + * Input + * Output + * EVENT_OUT + * EXTI + * Free pins are configured automatically as Analog (this feature is enabled through + * the Code Generation settings) + */ void MX_GPIO_Init(void) { - LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; - - /* GPIO Ports Clock Enable */ - LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOC); - LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOF); - LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOG); - LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA); - LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB); - LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOD); - - /**/ - LL_GPIO_ResetOutputPin(USER_LED_GPIO_Port, USER_LED_Pin); - - /**/ - GPIO_InitStruct.Pin = USER_BUTTON_Pin; - GPIO_InitStruct.Mode = LL_GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(USER_BUTTON_GPIO_Port, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_14; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_15; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_0; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOF, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_1; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOF, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_10; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOG, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_0; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_1; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_2; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_3; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_0; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_1; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_4; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = USER_LED_Pin; - GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT; - GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(USER_LED_GPIO_Port, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_6; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_7; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_4; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_5; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_0; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_1; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_2; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_10; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_11; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_14; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_15; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_6; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_7; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_8; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_9; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_9; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_10; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_11; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_12; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_10; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_11; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_12; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_2; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOD, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_4; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_5; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_6; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /**/ - GPIO_InitStruct.Pin = LL_GPIO_PIN_7; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - + LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* GPIO Ports Clock Enable */ + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOC); + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOF); + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOG); + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA); + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB); + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOD); + + /**/ + LL_GPIO_ResetOutputPin(USER_LED_GPIO_Port, USER_LED_Pin); + + /**/ + GPIO_InitStruct.Pin = USER_BUTTON_Pin; + GPIO_InitStruct.Mode = LL_GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(USER_BUTTON_GPIO_Port, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_14; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_15; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_0; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_1; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_10; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_0; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_1; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_2; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_3; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_0; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_1; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_4; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = USER_LED_Pin; + GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(USER_LED_GPIO_Port, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_6; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_7; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_4; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_5; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_0; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_1; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_2; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_10; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_11; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_14; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_15; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_6; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_7; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_8; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_9; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_9; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_10; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_11; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_12; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_10; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_11; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_12; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_2; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_4; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_5; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_6; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_7; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); } /* USER CODE BEGIN 2 */ diff --git a/Testbench/CUBEMXTESTING/Core/Src/main.c b/Testbench/CUBEMXTESTING/Core/Src/main.c index d201e4a35..7344dd05d 100644 --- a/Testbench/CUBEMXTESTING/Core/Src/main.c +++ b/Testbench/CUBEMXTESTING/Core/Src/main.c @@ -18,10 +18,11 @@ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "main.h" + #include "fdcan.h" -#include "usart.h" -#include "tim.h" #include "gpio.h" +#include "tim.h" +#include "usart.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ @@ -72,40 +73,40 @@ void SystemClock_Config(void); /* USER CODE END 0 */ /** - * @brief The application entry point. - * @retval int - */ + * @brief The application entry point. + * @retval int + */ int main(void) { - /* USER CODE BEGIN 1 */ + /* USER CODE BEGIN 1 */ - /* USER CODE END 1 */ + /* USER CODE END 1 */ - /* MCU Configuration--------------------------------------------------------*/ + /* MCU Configuration--------------------------------------------------------*/ - /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ - HAL_Init(); + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); - /* USER CODE BEGIN Init */ + /* USER CODE BEGIN Init */ - /* USER CODE END Init */ + /* USER CODE END Init */ - /* Configure the system clock */ - SystemClock_Config(); + /* Configure the system clock */ + SystemClock_Config(); - /* USER CODE BEGIN SysInit */ + /* USER CODE BEGIN SysInit */ Logomatic_SetLogLevel(LogLevel_Debug); - /* USER CODE END SysInit */ - - /* Initialize all configured peripherals */ - MX_GPIO_Init(); - MX_FDCAN1_Init(); - MX_FDCAN2_Init(); - MX_TIM5_Init(); - MX_FDCAN3_Init(); - MX_LPUART1_UART_Init(); - /* USER CODE BEGIN 2 */ + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_FDCAN1_Init(); + MX_FDCAN2_Init(); + MX_TIM5_Init(); + MX_FDCAN3_Init(); + MX_LPUART1_UART_Init(); + /* USER CODE BEGIN 2 */ CubeCAN_Config primaryCanConfig = {.rx_callback = CANdler_Callback, .context.busid_user_context = GRCAN_BUS_PRIMARY, .sending_node_id = GRCAN_Debugger}; CubeCAN_Config dataCanConfig = {.rx_callback = CANdler_Callback, .context.busid_user_context = GRCAN_BUS_DATA, .sending_node_id = GRCAN_Debugger}; CubeCAN_Config chargerCanConfig = {.rx_callback = CANdler_Callback, .context.busid_user_context = GRCAN_BUS_CHARGER, .sending_node_id = GRCAN_Debugger}; @@ -132,67 +133,59 @@ int main(void) CubeVCP_Setup(&hlpuart1); CubeVCP_EnableRx(CANdler_VCP_Callback); CubeVCP_SendString("Hello World!\n", sizeof("Hello World!\n") - 1); - /* USER CODE END 2 */ + /* USER CODE END 2 */ - /* Infinite loop */ - /* USER CODE BEGIN WHILE */ + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ while (1) { - /* USER CODE END WHILE */ + /* USER CODE END WHILE */ - /* USER CODE BEGIN 3 */ + /* USER CODE BEGIN 3 */ MainLoop(); HAL_Delay(100); } - /* USER CODE END 3 */ + /* USER CODE END 3 */ } /** - * @brief System Clock Configuration - * @retval None - */ + * @brief System Clock Configuration + * @retval None + */ void SystemClock_Config(void) { - LL_FLASH_SetLatency(LL_FLASH_LATENCY_4); - while(LL_FLASH_GetLatency() != LL_FLASH_LATENCY_4) - { - } - LL_PWR_EnableRange1BoostMode(); - LL_RCC_HSI_Enable(); - /* Wait till HSI is ready */ - while(LL_RCC_HSI_IsReady() != 1) - { - } - - LL_RCC_HSI_SetCalibTrimming(64); - LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, LL_RCC_PLLM_DIV_1, 20, LL_RCC_PLLR_DIV_2); - LL_RCC_PLL_EnableDomain_SYS(); - LL_RCC_PLL_Enable(); - /* Wait till PLL is ready */ - while(LL_RCC_PLL_IsReady() != 1) - { - } - - LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); - LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_2); - /* Wait till System clock is ready */ - while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) - { - } - - /* Insure 1us transition state at intermediate medium speed clock*/ - for (__IO uint32_t i = (170 >> 1); i !=0; i--); - - /* Set AHB prescaler*/ - LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1); - LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1); - LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1); - LL_SetSystemCoreClock(160000000); - - /* Update the time base */ - if (HAL_InitTick (TICK_INT_PRIORITY) != HAL_OK) - { - Error_Handler(); - } + LL_FLASH_SetLatency(LL_FLASH_LATENCY_4); + while (LL_FLASH_GetLatency() != LL_FLASH_LATENCY_4) {} + LL_PWR_EnableRange1BoostMode(); + LL_RCC_HSI_Enable(); + /* Wait till HSI is ready */ + while (LL_RCC_HSI_IsReady() != 1) {} + + LL_RCC_HSI_SetCalibTrimming(64); + LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, LL_RCC_PLLM_DIV_1, 20, LL_RCC_PLLR_DIV_2); + LL_RCC_PLL_EnableDomain_SYS(); + LL_RCC_PLL_Enable(); + /* Wait till PLL is ready */ + while (LL_RCC_PLL_IsReady() != 1) {} + + LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); + LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_2); + /* Wait till System clock is ready */ + while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) {} + + /* Insure 1us transition state at intermediate medium speed clock*/ + for (__IO uint32_t i = (170 >> 1); i != 0; i--) + ; + + /* Set AHB prescaler*/ + LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1); + LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1); + LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1); + LL_SetSystemCoreClock(160000000); + + /* Update the time base */ + if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) { + Error_Handler(); + } } /* USER CODE BEGIN 4 */ @@ -211,29 +204,29 @@ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) /* USER CODE END 4 */ /** - * @brief This function is executed in case of error occurrence. - * @retval None - */ + * @brief This function is executed in case of error occurrence. + * @retval None + */ void Error_Handler(void) { - /* USER CODE BEGIN Error_Handler_Debug */ + /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) {} - /* USER CODE END Error_Handler_Debug */ + /* USER CODE END Error_Handler_Debug */ } #ifdef USE_FULL_ASSERT /** - * @brief Reports the name of the source file and the source line number - * where the assert_param error has occurred. - * @param file: pointer to the source file name - * @param line: assert_param error line source number - * @retval None - */ + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ void assert_failed(uint8_t *file, uint32_t line) { - /* USER CODE BEGIN 6 */ + /* USER CODE BEGIN 6 */ LOGOMATIC_CRITICAL("Assert failed! File %s on line %" PRIu32 "\n", file, line); - /* USER CODE END 6 */ + /* USER CODE END 6 */ } #endif /* USE_FULL_ASSERT */ diff --git a/Testbench/CUBEMXTESTING/Core/Src/stm32g4xx_hal_msp.c b/Testbench/CUBEMXTESTING/Core/Src/stm32g4xx_hal_msp.c index 2cc7d8296..4668755ab 100644 --- a/Testbench/CUBEMXTESTING/Core/Src/stm32g4xx_hal_msp.c +++ b/Testbench/CUBEMXTESTING/Core/Src/stm32g4xx_hal_msp.c @@ -57,27 +57,27 @@ /* USER CODE END 0 */ /** - * Initializes the Global MSP. - */ + * Initializes the Global MSP. + */ void HAL_MspInit(void) { - /* USER CODE BEGIN MspInit 0 */ + /* USER CODE BEGIN MspInit 0 */ - /* USER CODE END MspInit 0 */ + /* USER CODE END MspInit 0 */ - __HAL_RCC_SYSCFG_CLK_ENABLE(); - __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_RCC_SYSCFG_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); - /* System interrupt init*/ + /* System interrupt init*/ - /** Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral - */ - HAL_PWREx_DisableUCPDDeadBattery(); + /** Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral + */ + HAL_PWREx_DisableUCPDDeadBattery(); - /* USER CODE BEGIN MspInit 1 */ + /* USER CODE BEGIN MspInit 1 */ - /* USER CODE END MspInit 1 */ + /* USER CODE END MspInit 1 */ } /* USER CODE BEGIN 1 */ diff --git a/Testbench/CUBEMXTESTING/Core/Src/stm32g4xx_it.c b/Testbench/CUBEMXTESTING/Core/Src/stm32g4xx_it.c index f02085e66..77f85d385 100644 --- a/Testbench/CUBEMXTESTING/Core/Src/stm32g4xx_it.c +++ b/Testbench/CUBEMXTESTING/Core/Src/stm32g4xx_it.c @@ -18,8 +18,9 @@ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ -#include "main.h" #include "stm32g4xx_it.h" + +#include "main.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ /* USER CODE END Includes */ @@ -68,129 +69,125 @@ extern TIM_HandleTypeDef htim5; /* Cortex-M4 Processor Interruption and Exception Handlers */ /******************************************************************************/ /** - * @brief This function handles Non maskable interrupt. - */ + * @brief This function handles Non maskable interrupt. + */ void NMI_Handler(void) { - /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ - /* USER CODE END NonMaskableInt_IRQn 0 */ - /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) {} - /* USER CODE END NonMaskableInt_IRQn 1 */ + /* USER CODE END NonMaskableInt_IRQn 1 */ } /** - * @brief This function handles Hard fault interrupt. - */ + * @brief This function handles Hard fault interrupt. + */ void HardFault_Handler(void) { - /* USER CODE BEGIN HardFault_IRQn 0 */ - - /* USER CODE END HardFault_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_HardFault_IRQn 0 */ - /* USER CODE END W1_HardFault_IRQn 0 */ - } + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } } /** - * @brief This function handles Memory management fault. - */ + * @brief This function handles Memory management fault. + */ void MemManage_Handler(void) { - /* USER CODE BEGIN MemoryManagement_IRQn 0 */ - - /* USER CODE END MemoryManagement_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ - /* USER CODE END W1_MemoryManagement_IRQn 0 */ - } + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } } /** - * @brief This function handles Prefetch fault, memory access fault. - */ + * @brief This function handles Prefetch fault, memory access fault. + */ void BusFault_Handler(void) { - /* USER CODE BEGIN BusFault_IRQn 0 */ - - /* USER CODE END BusFault_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_BusFault_IRQn 0 */ - /* USER CODE END W1_BusFault_IRQn 0 */ - } + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } } /** - * @brief This function handles Undefined instruction or illegal state. - */ + * @brief This function handles Undefined instruction or illegal state. + */ void UsageFault_Handler(void) { - /* USER CODE BEGIN UsageFault_IRQn 0 */ - - /* USER CODE END UsageFault_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ - /* USER CODE END W1_UsageFault_IRQn 0 */ - } + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } } /** - * @brief This function handles System service call via SWI instruction. - */ + * @brief This function handles System service call via SWI instruction. + */ void SVC_Handler(void) { - /* USER CODE BEGIN SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 0 */ - /* USER CODE END SVCall_IRQn 0 */ - /* USER CODE BEGIN SVCall_IRQn 1 */ + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ - /* USER CODE END SVCall_IRQn 1 */ + /* USER CODE END SVCall_IRQn 1 */ } /** - * @brief This function handles Debug monitor. - */ + * @brief This function handles Debug monitor. + */ void DebugMon_Handler(void) { - /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ - /* USER CODE END DebugMonitor_IRQn 0 */ - /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ - /* USER CODE END DebugMonitor_IRQn 1 */ + /* USER CODE END DebugMonitor_IRQn 1 */ } /** - * @brief This function handles Pendable request for system service. - */ + * @brief This function handles Pendable request for system service. + */ void PendSV_Handler(void) { - /* USER CODE BEGIN PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 0 */ - /* USER CODE END PendSV_IRQn 0 */ - /* USER CODE BEGIN PendSV_IRQn 1 */ + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ - /* USER CODE END PendSV_IRQn 1 */ + /* USER CODE END PendSV_IRQn 1 */ } /** - * @brief This function handles System tick timer. - */ + * @brief This function handles System tick timer. + */ void SysTick_Handler(void) { - /* USER CODE BEGIN SysTick_IRQn 0 */ + /* USER CODE BEGIN SysTick_IRQn 0 */ - /* USER CODE END SysTick_IRQn 0 */ - HAL_IncTick(); - /* USER CODE BEGIN SysTick_IRQn 1 */ + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ - /* USER CODE END SysTick_IRQn 1 */ + /* USER CODE END SysTick_IRQn 1 */ } /******************************************************************************/ @@ -201,73 +198,73 @@ void SysTick_Handler(void) /******************************************************************************/ /** - * @brief This function handles FDCAN1 interrupt 0. - */ + * @brief This function handles FDCAN1 interrupt 0. + */ void FDCAN1_IT0_IRQHandler(void) { - /* USER CODE BEGIN FDCAN1_IT0_IRQn 0 */ + /* USER CODE BEGIN FDCAN1_IT0_IRQn 0 */ - /* USER CODE END FDCAN1_IT0_IRQn 0 */ - HAL_FDCAN_IRQHandler(&hfdcan1); - /* USER CODE BEGIN FDCAN1_IT0_IRQn 1 */ + /* USER CODE END FDCAN1_IT0_IRQn 0 */ + HAL_FDCAN_IRQHandler(&hfdcan1); + /* USER CODE BEGIN FDCAN1_IT0_IRQn 1 */ - /* USER CODE END FDCAN1_IT0_IRQn 1 */ + /* USER CODE END FDCAN1_IT0_IRQn 1 */ } /** - * @brief This function handles TIM5 global interrupt. - */ + * @brief This function handles TIM5 global interrupt. + */ void TIM5_IRQHandler(void) { - /* USER CODE BEGIN TIM5_IRQn 0 */ + /* USER CODE BEGIN TIM5_IRQn 0 */ - /* USER CODE END TIM5_IRQn 0 */ - HAL_TIM_IRQHandler(&htim5); - /* USER CODE BEGIN TIM5_IRQn 1 */ + /* USER CODE END TIM5_IRQn 0 */ + HAL_TIM_IRQHandler(&htim5); + /* USER CODE BEGIN TIM5_IRQn 1 */ - /* USER CODE END TIM5_IRQn 1 */ + /* USER CODE END TIM5_IRQn 1 */ } /** - * @brief This function handles FDCAN2 interrupt 0. - */ + * @brief This function handles FDCAN2 interrupt 0. + */ void FDCAN2_IT0_IRQHandler(void) { - /* USER CODE BEGIN FDCAN2_IT0_IRQn 0 */ + /* USER CODE BEGIN FDCAN2_IT0_IRQn 0 */ - /* USER CODE END FDCAN2_IT0_IRQn 0 */ - HAL_FDCAN_IRQHandler(&hfdcan2); - /* USER CODE BEGIN FDCAN2_IT0_IRQn 1 */ + /* USER CODE END FDCAN2_IT0_IRQn 0 */ + HAL_FDCAN_IRQHandler(&hfdcan2); + /* USER CODE BEGIN FDCAN2_IT0_IRQn 1 */ - /* USER CODE END FDCAN2_IT0_IRQn 1 */ + /* USER CODE END FDCAN2_IT0_IRQn 1 */ } /** - * @brief This function handles FDCAN3 interrupt 0. - */ + * @brief This function handles FDCAN3 interrupt 0. + */ void FDCAN3_IT0_IRQHandler(void) { - /* USER CODE BEGIN FDCAN3_IT0_IRQn 0 */ + /* USER CODE BEGIN FDCAN3_IT0_IRQn 0 */ - /* USER CODE END FDCAN3_IT0_IRQn 0 */ - HAL_FDCAN_IRQHandler(&hfdcan3); - /* USER CODE BEGIN FDCAN3_IT0_IRQn 1 */ + /* USER CODE END FDCAN3_IT0_IRQn 0 */ + HAL_FDCAN_IRQHandler(&hfdcan3); + /* USER CODE BEGIN FDCAN3_IT0_IRQn 1 */ - /* USER CODE END FDCAN3_IT0_IRQn 1 */ + /* USER CODE END FDCAN3_IT0_IRQn 1 */ } /** - * @brief This function handles LPUART1 global interrupt. - */ + * @brief This function handles LPUART1 global interrupt. + */ void LPUART1_IRQHandler(void) { - /* USER CODE BEGIN LPUART1_IRQn 0 */ + /* USER CODE BEGIN LPUART1_IRQn 0 */ - /* USER CODE END LPUART1_IRQn 0 */ - HAL_UART_IRQHandler(&hlpuart1); - /* USER CODE BEGIN LPUART1_IRQn 1 */ + /* USER CODE END LPUART1_IRQn 0 */ + HAL_UART_IRQHandler(&hlpuart1); + /* USER CODE BEGIN LPUART1_IRQn 1 */ - /* USER CODE END LPUART1_IRQn 1 */ + /* USER CODE END LPUART1_IRQn 1 */ } /* USER CODE BEGIN 1 */ diff --git a/Testbench/CUBEMXTESTING/Core/Src/tim.c b/Testbench/CUBEMXTESTING/Core/Src/tim.c index cc6e6a92e..1f6110e86 100644 --- a/Testbench/CUBEMXTESTING/Core/Src/tim.c +++ b/Testbench/CUBEMXTESTING/Core/Src/tim.c @@ -30,83 +30,76 @@ TIM_HandleTypeDef htim5; void MX_TIM5_Init(void) { - /* USER CODE BEGIN TIM5_Init 0 */ - - /* USER CODE END TIM5_Init 0 */ - - TIM_ClockConfigTypeDef sClockSourceConfig = {0}; - TIM_MasterConfigTypeDef sMasterConfig = {0}; - - /* USER CODE BEGIN TIM5_Init 1 */ - - /* USER CODE END TIM5_Init 1 */ - htim5.Instance = TIM5; - htim5.Init.Prescaler = 159; - htim5.Init.CounterMode = TIM_COUNTERMODE_UP; - htim5.Init.Period = 499; - htim5.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; - htim5.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; - if (HAL_TIM_Base_Init(&htim5) != HAL_OK) - { - Error_Handler(); - } - sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; - if (HAL_TIM_ConfigClockSource(&htim5, &sClockSourceConfig) != HAL_OK) - { - Error_Handler(); - } - sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; - sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; - if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN TIM5_Init 2 */ + /* USER CODE BEGIN TIM5_Init 0 */ + + /* USER CODE END TIM5_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; + + /* USER CODE BEGIN TIM5_Init 1 */ + + /* USER CODE END TIM5_Init 1 */ + htim5.Instance = TIM5; + htim5.Init.Prescaler = 159; + htim5.Init.CounterMode = TIM_COUNTERMODE_UP; + htim5.Init.Period = 499; + htim5.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim5.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim5) != HAL_OK) { + Error_Handler(); + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(&htim5, &sClockSourceConfig) != HAL_OK) { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig) != HAL_OK) { + Error_Handler(); + } + /* USER CODE BEGIN TIM5_Init 2 */ HAL_TIM_Base_Start_IT(&htim5); - /* USER CODE END TIM5_Init 2 */ - + /* USER CODE END TIM5_Init 2 */ } -void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *tim_baseHandle) { - if(tim_baseHandle->Instance==TIM5) - { - /* USER CODE BEGIN TIM5_MspInit 0 */ + if (tim_baseHandle->Instance == TIM5) { + /* USER CODE BEGIN TIM5_MspInit 0 */ - /* USER CODE END TIM5_MspInit 0 */ - /* TIM5 clock enable */ - __HAL_RCC_TIM5_CLK_ENABLE(); + /* USER CODE END TIM5_MspInit 0 */ + /* TIM5 clock enable */ + __HAL_RCC_TIM5_CLK_ENABLE(); - /* TIM5 interrupt Init */ - HAL_NVIC_SetPriority(TIM5_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(TIM5_IRQn); - /* USER CODE BEGIN TIM5_MspInit 1 */ + /* TIM5 interrupt Init */ + HAL_NVIC_SetPriority(TIM5_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(TIM5_IRQn); + /* USER CODE BEGIN TIM5_MspInit 1 */ - /* USER CODE END TIM5_MspInit 1 */ - } + /* USER CODE END TIM5_MspInit 1 */ + } } -void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* tim_baseHandle) +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *tim_baseHandle) { - if(tim_baseHandle->Instance==TIM5) - { - /* USER CODE BEGIN TIM5_MspDeInit 0 */ + if (tim_baseHandle->Instance == TIM5) { + /* USER CODE BEGIN TIM5_MspDeInit 0 */ - /* USER CODE END TIM5_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_TIM5_CLK_DISABLE(); + /* USER CODE END TIM5_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM5_CLK_DISABLE(); - /* TIM5 interrupt Deinit */ - HAL_NVIC_DisableIRQ(TIM5_IRQn); - /* USER CODE BEGIN TIM5_MspDeInit 1 */ + /* TIM5 interrupt Deinit */ + HAL_NVIC_DisableIRQ(TIM5_IRQn); + /* USER CODE BEGIN TIM5_MspDeInit 1 */ - /* USER CODE END TIM5_MspDeInit 1 */ - } + /* USER CODE END TIM5_MspDeInit 1 */ + } } /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ - diff --git a/Testbench/CUBEMXTESTING/Core/Src/usart.c b/Testbench/CUBEMXTESTING/Core/Src/usart.c index 836ce8d48..a14deb76c 100644 --- a/Testbench/CUBEMXTESTING/Core/Src/usart.c +++ b/Testbench/CUBEMXTESTING/Core/Src/usart.c @@ -31,106 +31,98 @@ UART_HandleTypeDef hlpuart1; void MX_LPUART1_UART_Init(void) { - /* USER CODE BEGIN LPUART1_Init 0 */ - - /* USER CODE END LPUART1_Init 0 */ - - /* USER CODE BEGIN LPUART1_Init 1 */ - - /* USER CODE END LPUART1_Init 1 */ - hlpuart1.Instance = LPUART1; - hlpuart1.Init.BaudRate = 115200; - hlpuart1.Init.WordLength = UART_WORDLENGTH_8B; - hlpuart1.Init.StopBits = UART_STOPBITS_1; - hlpuart1.Init.Parity = UART_PARITY_NONE; - hlpuart1.Init.Mode = UART_MODE_TX_RX; - hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; - hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; - hlpuart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; - hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; - if (HAL_UART_Init(&hlpuart1) != HAL_OK) - { - Error_Handler(); - } - if (HAL_UARTEx_SetTxFifoThreshold(&hlpuart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) - { - Error_Handler(); - } - if (HAL_UARTEx_SetRxFifoThreshold(&hlpuart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) - { - Error_Handler(); - } - if (HAL_UARTEx_DisableFifoMode(&hlpuart1) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN LPUART1_Init 2 */ - - /* USER CODE END LPUART1_Init 2 */ - + /* USER CODE BEGIN LPUART1_Init 0 */ + + /* USER CODE END LPUART1_Init 0 */ + + /* USER CODE BEGIN LPUART1_Init 1 */ + + /* USER CODE END LPUART1_Init 1 */ + hlpuart1.Instance = LPUART1; + hlpuart1.Init.BaudRate = 115200; + hlpuart1.Init.WordLength = UART_WORDLENGTH_8B; + hlpuart1.Init.StopBits = UART_STOPBITS_1; + hlpuart1.Init.Parity = UART_PARITY_NONE; + hlpuart1.Init.Mode = UART_MODE_TX_RX; + hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + hlpuart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; + hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&hlpuart1) != HAL_OK) { + Error_Handler(); + } + if (HAL_UARTEx_SetTxFifoThreshold(&hlpuart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) { + Error_Handler(); + } + if (HAL_UARTEx_SetRxFifoThreshold(&hlpuart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) { + Error_Handler(); + } + if (HAL_UARTEx_DisableFifoMode(&hlpuart1) != HAL_OK) { + Error_Handler(); + } + /* USER CODE BEGIN LPUART1_Init 2 */ + + /* USER CODE END LPUART1_Init 2 */ } -void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) +void HAL_UART_MspInit(UART_HandleTypeDef *uartHandle) { - GPIO_InitTypeDef GPIO_InitStruct = {0}; - if(uartHandle->Instance==LPUART1) - { - /* USER CODE BEGIN LPUART1_MspInit 0 */ - - /* USER CODE END LPUART1_MspInit 0 */ - LL_RCC_SetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE_PCLK1); - - /* LPUART1 clock enable */ - __HAL_RCC_LPUART1_CLK_ENABLE(); - - __HAL_RCC_GPIOA_CLK_ENABLE(); - /**LPUART1 GPIO Configuration - PA2 ------> LPUART1_TX - PA3 ------> LPUART1_RX - */ - GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF12_LPUART1; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /* LPUART1 interrupt Init */ - HAL_NVIC_SetPriority(LPUART1_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(LPUART1_IRQn); - /* USER CODE BEGIN LPUART1_MspInit 1 */ - - /* USER CODE END LPUART1_MspInit 1 */ - } + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if (uartHandle->Instance == LPUART1) { + /* USER CODE BEGIN LPUART1_MspInit 0 */ + + /* USER CODE END LPUART1_MspInit 0 */ + LL_RCC_SetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE_PCLK1); + + /* LPUART1 clock enable */ + __HAL_RCC_LPUART1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**LPUART1 GPIO Configuration + PA2 ------> LPUART1_TX + PA3 ------> LPUART1_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_2 | GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF12_LPUART1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* LPUART1 interrupt Init */ + HAL_NVIC_SetPriority(LPUART1_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(LPUART1_IRQn); + /* USER CODE BEGIN LPUART1_MspInit 1 */ + + /* USER CODE END LPUART1_MspInit 1 */ + } } -void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle) +void HAL_UART_MspDeInit(UART_HandleTypeDef *uartHandle) { - if(uartHandle->Instance==LPUART1) - { - /* USER CODE BEGIN LPUART1_MspDeInit 0 */ + if (uartHandle->Instance == LPUART1) { + /* USER CODE BEGIN LPUART1_MspDeInit 0 */ - /* USER CODE END LPUART1_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_LPUART1_CLK_DISABLE(); + /* USER CODE END LPUART1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_LPUART1_CLK_DISABLE(); - /**LPUART1 GPIO Configuration - PA2 ------> LPUART1_TX - PA3 ------> LPUART1_RX - */ - HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); + /**LPUART1 GPIO Configuration + PA2 ------> LPUART1_TX + PA3 ------> LPUART1_RX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2 | GPIO_PIN_3); - /* LPUART1 interrupt Deinit */ - HAL_NVIC_DisableIRQ(LPUART1_IRQn); - /* USER CODE BEGIN LPUART1_MspDeInit 1 */ + /* LPUART1 interrupt Deinit */ + HAL_NVIC_DisableIRQ(LPUART1_IRQn); + /* USER CODE BEGIN LPUART1_MspDeInit 1 */ - /* USER CODE END LPUART1_MspDeInit 1 */ - } + /* USER CODE END LPUART1_MspDeInit 1 */ + } } /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ - From ba3c8f0d57f9369fc9da82b6f605e4d01a34ca64 Mon Sep 17 00:00:00 2001 From: Daniel Hansen Date: Sun, 23 Aug 2026 16:41:57 -0700 Subject: [PATCH 09/17] Add G4Blinky (format) Signed-off-by: Daniel Hansen --- .gitignore | 2 - .../NucleoG4-Blinky/Application/Inc/morse.h | 16 + .../NucleoG4-Blinky/Application/Src/morse.c | 46 ++ Testbench/NucleoG4-Blinky/CMakeLists.txt | 45 ++ Testbench/NucleoG4-Blinky/Core/Inc/gpio.h | 49 ++ Testbench/NucleoG4-Blinky/Core/Inc/main.h | 82 +++ .../NucleoG4-Blinky/Core/Inc/stm32_assert.h | 53 ++ .../Core/Inc/stm32g4xx_hal_conf.h | 380 +++++++++++ .../NucleoG4-Blinky/Core/Inc/stm32g4xx_it.h | 66 ++ Testbench/NucleoG4-Blinky/Core/Src/gpio.c | 118 ++++ Testbench/NucleoG4-Blinky/Core/Src/main.c | 178 ++++++ .../NucleoG4-Blinky/Core/Src/stm32g4xx_it.c | 203 ++++++ Testbench/NucleoG4-Blinky/Core/Src/syscalls.c | 244 ++++++++ Testbench/NucleoG4-Blinky/Core/Src/sysmem.c | 87 +++ .../Core/Src/system_stm32g4xx.c | 287 +++++++++ Testbench/NucleoG4-Blinky/NucleoG4-Blinky.ioc | 122 ++++ .../NucleoG4-Blinky/STM32G474xx_FLASH.ld | 250 ++++++++ .../NucleoG4-Blinky/startup_stm32g474xx.s | 592 ++++++++++++++++++ Testbench/testbench.cmake | 10 + 19 files changed, 2828 insertions(+), 2 deletions(-) create mode 100644 Testbench/NucleoG4-Blinky/Application/Inc/morse.h create mode 100644 Testbench/NucleoG4-Blinky/Application/Src/morse.c create mode 100644 Testbench/NucleoG4-Blinky/CMakeLists.txt create mode 100644 Testbench/NucleoG4-Blinky/Core/Inc/gpio.h create mode 100644 Testbench/NucleoG4-Blinky/Core/Inc/main.h create mode 100644 Testbench/NucleoG4-Blinky/Core/Inc/stm32_assert.h create mode 100644 Testbench/NucleoG4-Blinky/Core/Inc/stm32g4xx_hal_conf.h create mode 100644 Testbench/NucleoG4-Blinky/Core/Inc/stm32g4xx_it.h create mode 100644 Testbench/NucleoG4-Blinky/Core/Src/gpio.c create mode 100644 Testbench/NucleoG4-Blinky/Core/Src/main.c create mode 100644 Testbench/NucleoG4-Blinky/Core/Src/stm32g4xx_it.c create mode 100644 Testbench/NucleoG4-Blinky/Core/Src/syscalls.c create mode 100644 Testbench/NucleoG4-Blinky/Core/Src/sysmem.c create mode 100644 Testbench/NucleoG4-Blinky/Core/Src/system_stm32g4xx.c create mode 100644 Testbench/NucleoG4-Blinky/NucleoG4-Blinky.ioc create mode 100644 Testbench/NucleoG4-Blinky/STM32G474xx_FLASH.ld create mode 100644 Testbench/NucleoG4-Blinky/startup_stm32g474xx.s diff --git a/.gitignore b/.gitignore index 531012429..487149f09 100644 --- a/.gitignore +++ b/.gitignore @@ -95,7 +95,5 @@ EWARM */*/cmake/starm-clang.cmake */Drivers */*/Drivers -*/CMakeLists.txt -*/*/CMakeLists.txt */CMakePresets.json */*/CMakePresets.json diff --git a/Testbench/NucleoG4-Blinky/Application/Inc/morse.h b/Testbench/NucleoG4-Blinky/Application/Inc/morse.h new file mode 100644 index 000000000..040fef088 --- /dev/null +++ b/Testbench/NucleoG4-Blinky/Application/Inc/morse.h @@ -0,0 +1,16 @@ +#include + +#include "main.h" + +#ifndef MORSE_H +#define MORSE_H + +#define morse_code_dot_delay (100U) +#define morse_code_intra_element_delay (morse_code_dot_delay) +#define morse_code_dash_delay (morse_code_dot_delay * 3U) +#define morse_code_letter_space_delay (morse_code_dot_delay * 3U) +#define morse_code_word_space_delay (morse_code_dot_delay * 7U) + +HAL_StatusTypeDef morse_code_send(const char *message, uint8_t length); + +#endif diff --git a/Testbench/NucleoG4-Blinky/Application/Src/morse.c b/Testbench/NucleoG4-Blinky/Application/Src/morse.c new file mode 100644 index 000000000..244eace03 --- /dev/null +++ b/Testbench/NucleoG4-Blinky/Application/Src/morse.c @@ -0,0 +1,46 @@ +#include "morse.h" + +#include + +#include "main.h" + +HAL_StatusTypeDef morse_code_send(const char *message, uint8_t length) +{ + if (message == NULL || length == 0) { + return HAL_ERROR; + } + + for (uint8_t i = 0; i < length; i++) { + if (message[i] == '\0') { + break; + } + + switch (message[i]) { + case '.': + HAL_GPIO_WritePin(USER_LED_GPIO_Port, USER_LED_Pin, GPIO_PIN_SET); + HAL_Delay(morse_code_dot_delay); + HAL_GPIO_WritePin(USER_LED_GPIO_Port, USER_LED_Pin, GPIO_PIN_RESET); + HAL_Delay(morse_code_intra_element_delay); + break; + + case '-': + HAL_GPIO_WritePin(USER_LED_GPIO_Port, USER_LED_Pin, GPIO_PIN_SET); + HAL_Delay(morse_code_dash_delay); + HAL_GPIO_WritePin(USER_LED_GPIO_Port, USER_LED_Pin, GPIO_PIN_RESET); + HAL_Delay(morse_code_intra_element_delay); + break; + + case ' ': + HAL_Delay(morse_code_letter_space_delay); + break; + + case '/': + HAL_Delay(morse_code_word_space_delay); + break; + + default: + return HAL_ERROR; + } + } + return HAL_OK; +} diff --git a/Testbench/NucleoG4-Blinky/CMakeLists.txt b/Testbench/NucleoG4-Blinky/CMakeLists.txt new file mode 100644 index 000000000..1d8144aae --- /dev/null +++ b/Testbench/NucleoG4-Blinky/CMakeLists.txt @@ -0,0 +1,45 @@ +#[[ +Required components (orderless) +- Link options for the GCC linker script +- Compile definitions for the chip subfamily +- Includes for the project +- Sources for the project +- Additional link libraries for the project +]] + +target_link_options( + ${TARGET_NAME} + PRIVATE + -T "${CMAKE_CURRENT_SOURCE_DIR}/STM32G474xx_FLASH.ld" +) + +target_compile_definitions( + ${TARGET_NAME} + PRIVATE + STM32G474xx +) + +target_include_directories( + ${TARGET_NAME} + PRIVATE + Core/Inc + Application/Inc +) + +target_sources( + ${TARGET_NAME} + PRIVATE + Application/Src/morse.c + Core/Src/gpio.c + Core/Src/main.c + Core/Src/stm32g4xx_it.c + Core/Src/syscalls.c + Core/Src/sysmem.c + Core/Src/system_stm32g4xx.c + startup_stm32g474xx.s +) + +target_link_libraries( + ${TARGET_NAME} + PRIVATE +) diff --git a/Testbench/NucleoG4-Blinky/Core/Inc/gpio.h b/Testbench/NucleoG4-Blinky/Core/Inc/gpio.h new file mode 100644 index 000000000..3c91c4dd6 --- /dev/null +++ b/Testbench/NucleoG4-Blinky/Core/Inc/gpio.h @@ -0,0 +1,49 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file gpio.h + * @brief This file contains all the function prototypes for + * the gpio.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __GPIO_H__ +#define __GPIO_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_GPIO_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif +#endif /*__ GPIO_H__ */ + diff --git a/Testbench/NucleoG4-Blinky/Core/Inc/main.h b/Testbench/NucleoG4-Blinky/Core/Inc/main.h new file mode 100644 index 000000000..1e2c763d8 --- /dev/null +++ b/Testbench/NucleoG4-Blinky/Core/Inc/main.h @@ -0,0 +1,82 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g4xx_hal.h" + +#include "stm32g4xx_ll_rcc.h" +#include "stm32g4xx_ll_bus.h" +#include "stm32g4xx_ll_crs.h" +#include "stm32g4xx_ll_system.h" +#include "stm32g4xx_ll_exti.h" +#include "stm32g4xx_ll_cortex.h" +#include "stm32g4xx_ll_utils.h" +#include "stm32g4xx_ll_pwr.h" +#include "stm32g4xx_ll_dma.h" +#include "stm32g4xx_ll_gpio.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +#define USER_LED_Pin GPIO_PIN_5 +#define USER_LED_GPIO_Port GPIOA + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ diff --git a/Testbench/NucleoG4-Blinky/Core/Inc/stm32_assert.h b/Testbench/NucleoG4-Blinky/Core/Inc/stm32_assert.h new file mode 100644 index 000000000..61631c41e --- /dev/null +++ b/Testbench/NucleoG4-Blinky/Core/Inc/stm32_assert.h @@ -0,0 +1,53 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32_assert.h + * @author MCD Application Team + * @brief STM32 assert file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_ASSERT_H +#define __STM32_ASSERT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Includes ------------------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ +void assert_failed(uint8_t *file, uint32_t line); +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_ASSERT_H */ + diff --git a/Testbench/NucleoG4-Blinky/Core/Inc/stm32g4xx_hal_conf.h b/Testbench/NucleoG4-Blinky/Core/Inc/stm32g4xx_hal_conf.h new file mode 100644 index 000000000..90adf393c --- /dev/null +++ b/Testbench/NucleoG4-Blinky/Core/Inc/stm32g4xx_hal_conf.h @@ -0,0 +1,380 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32g4xx_hal_conf.h + * @author MCD Application Team + * @brief HAL configuration file + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G4xx_HAL_CONF_H +#define STM32G4xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ + +#define HAL_MODULE_ENABLED + + /*#define HAL_ADC_MODULE_ENABLED */ +/*#define HAL_COMP_MODULE_ENABLED */ +/*#define HAL_CORDIC_MODULE_ENABLED */ +/*#define HAL_CRC_MODULE_ENABLED */ +/*#define HAL_CRYP_MODULE_ENABLED */ +/*#define HAL_DAC_MODULE_ENABLED */ +/*#define HAL_FDCAN_MODULE_ENABLED */ +/*#define HAL_FMAC_MODULE_ENABLED */ +/*#define HAL_HRTIM_MODULE_ENABLED */ +/*#define HAL_IRDA_MODULE_ENABLED */ +/*#define HAL_IWDG_MODULE_ENABLED */ +/*#define HAL_I2C_MODULE_ENABLED */ +/*#define HAL_I2S_MODULE_ENABLED */ +/*#define HAL_LPTIM_MODULE_ENABLED */ +/*#define HAL_NAND_MODULE_ENABLED */ +/*#define HAL_NOR_MODULE_ENABLED */ +/*#define HAL_OPAMP_MODULE_ENABLED */ +/*#define HAL_PCD_MODULE_ENABLED */ +/*#define HAL_QSPI_MODULE_ENABLED */ +/*#define HAL_RNG_MODULE_ENABLED */ +/*#define HAL_RTC_MODULE_ENABLED */ +/*#define HAL_SAI_MODULE_ENABLED */ +/*#define HAL_SMARTCARD_MODULE_ENABLED */ +/*#define HAL_SMBUS_MODULE_ENABLED */ +/*#define HAL_SPI_MODULE_ENABLED */ +/*#define HAL_SRAM_MODULE_ENABLED */ +/*#define HAL_TIM_MODULE_ENABLED */ +/*#define HAL_UART_MODULE_ENABLED */ +/*#define HAL_USART_MODULE_ENABLED */ +/*#define HAL_WWDG_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## Register Callbacks selection ############################## */ +/** + * @brief This is the list of modules where register callback can be used + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U +#define USE_HAL_COMP_REGISTER_CALLBACKS 0U +#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U +#define USE_HAL_EXTI_REGISTER_CALLBACKS 0U +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U +#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U +#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U +#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U +#define USE_HAL_UART_REGISTER_CALLBACKS 0U +#define USE_HAL_USART_REGISTER_CALLBACKS 0U +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI48) value for USB FS and RNG. + * This internal oscillator is mainly dedicated to provide a high precision clock to + * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. + * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency + * which is subject to manufacturing process variations. + */ +#if !defined (HSI48_VALUE) + #define HSI48_VALUE (48000000UL) /*!< Value of the Internal High Speed oscillator for USB FS/RNG in Hz. + The real value my vary depending on manufacturing process variations.*/ +#endif /* HSI48_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) +/*!< Value of the Internal Low Speed oscillator in Hz +The real value may vary depending on the variations in voltage and temperature.*/ +#define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) +#define LSE_VALUE (32768UL) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S and SAI peripherals + * This value is used by the I2S and SAI HAL modules to compute the I2S and SAI clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) +#define EXTERNAL_CLOCK_VALUE (12288000UL) /*!< Value of the External oscillator in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ + +#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority (lowest by default) */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 0U +#define INSTRUCTION_CACHE_ENABLE 1U +#define DATA_CACHE_ENABLE 1U + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ + #define USE_FULL_ASSERT 1U + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver + * Activated: CRC code is present inside driver + * Deactivated: CRC code cleaned from driver + */ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED +#include "stm32g4xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED +#include "stm32g4xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED +#include "stm32g4xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED +#include "stm32g4xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED +#include "stm32g4xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED +#include "stm32g4xx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CORDIC_MODULE_ENABLED +#include "stm32g4xx_hal_cordic.h" +#endif /* HAL_CORDIC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED +#include "stm32g4xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED +#include "stm32g4xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED +#include "stm32g4xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED +#include "stm32g4xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_FDCAN_MODULE_ENABLED +#include "stm32g4xx_hal_fdcan.h" +#endif /* HAL_FDCAN_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED +#include "stm32g4xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_FMAC_MODULE_ENABLED +#include "stm32g4xx_hal_fmac.h" +#endif /* HAL_FMAC_MODULE_ENABLED */ + +#ifdef HAL_HRTIM_MODULE_ENABLED +#include "stm32g4xx_hal_hrtim.h" +#endif /* HAL_HRTIM_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED +#include "stm32g4xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED +#include "stm32g4xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED +#include "stm32g4xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED +#include "stm32g4xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED +#include "stm32g4xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED +#include "stm32g4xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED +#include "stm32g4xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_OPAMP_MODULE_ENABLED +#include "stm32g4xx_hal_opamp.h" +#endif /* HAL_OPAMP_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED +#include "stm32g4xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED +#include "stm32g4xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED +#include "stm32g4xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED +#include "stm32g4xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED +#include "stm32g4xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED +#include "stm32g4xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED +#include "stm32g4xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED +#include "stm32g4xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED +#include "stm32g4xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED +#include "stm32g4xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED +#include "stm32g4xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED +#include "stm32g4xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED +#include "stm32g4xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED +#include "stm32g4xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ +void assert_failed(uint8_t *file, uint32_t line); +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G4xx_HAL_CONF_H */ diff --git a/Testbench/NucleoG4-Blinky/Core/Inc/stm32g4xx_it.h b/Testbench/NucleoG4-Blinky/Core/Inc/stm32g4xx_it.h new file mode 100644 index 000000000..1a144ad22 --- /dev/null +++ b/Testbench/NucleoG4-Blinky/Core/Inc/stm32g4xx_it.h @@ -0,0 +1,66 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32g4xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32G4xx_IT_H +#define __STM32G4xx_IT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32G4xx_IT_H */ diff --git a/Testbench/NucleoG4-Blinky/Core/Src/gpio.c b/Testbench/NucleoG4-Blinky/Core/Src/gpio.c new file mode 100644 index 000000000..7f64369d4 --- /dev/null +++ b/Testbench/NucleoG4-Blinky/Core/Src/gpio.c @@ -0,0 +1,118 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file gpio.c + * @brief This file provides code for the configuration + * of all used GPIO pins. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "gpio.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/*----------------------------------------------------------------------------*/ +/* Configure GPIO */ +/*----------------------------------------------------------------------------*/ +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/** Configure pins +*/ +void MX_GPIO_Init(void) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(USER_LED_GPIO_Port, USER_LED_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pins : PC13 PC14 PC15 PC0 + PC1 PC2 PC3 PC4 + PC5 PC6 PC7 PC8 + PC9 PC10 PC11 PC12 */ + GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15|GPIO_PIN_0 + |GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4 + |GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8 + |GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /*Configure GPIO pins : PF0 PF1 */ + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + /*Configure GPIO pin : PG10 */ + GPIO_InitStruct.Pin = GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + /*Configure GPIO pins : PA0 PA1 PA2 PA3 + PA4 PA6 PA7 PA8 + PA9 PA10 PA11 PA12 + PA13 PA14 PA15 */ + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8 + |GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12 + |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /*Configure GPIO pin : USER_LED_Pin */ + GPIO_InitStruct.Pin = USER_LED_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(USER_LED_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pins : PB0 PB1 PB2 PB10 + PB11 PB12 PB13 PB14 + PB15 PB3 PB4 PB5 + PB6 PB7 PB8 PB9 */ + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_10 + |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 + |GPIO_PIN_15|GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5 + |GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /*Configure GPIO pin : PD2 */ + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + +} + +/* USER CODE BEGIN 2 */ + +/* USER CODE END 2 */ diff --git a/Testbench/NucleoG4-Blinky/Core/Src/main.c b/Testbench/NucleoG4-Blinky/Core/Src/main.c new file mode 100644 index 000000000..ff8b65b47 --- /dev/null +++ b/Testbench/NucleoG4-Blinky/Core/Src/main.c @@ -0,0 +1,178 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "gpio.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +#include "morse.h" +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ + +/* USER CODE BEGIN PV */ +const char message[] = "--. .- ..- -.-. .... ---/.-. .- -.-. .. -. --."; +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + /* USER CODE BEGIN 2 */ + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + if (morse_code_send(message, sizeof(message) / sizeof(message[0])) != HAL_OK) { + Error_Handler(); + } + HAL_Delay(500); + } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + LL_FLASH_SetLatency(LL_FLASH_LATENCY_0); + while(LL_FLASH_GetLatency() != LL_FLASH_LATENCY_0) + { + } + LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1); + LL_RCC_HSI_Enable(); + /* Wait till HSI is ready */ + while(LL_RCC_HSI_IsReady() != 1) + { + } + + LL_RCC_HSI_SetCalibTrimming(64); + LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI); + /* Wait till System clock is ready */ + while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI) + { + } + + /* Set AHB prescaler*/ + LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1); + LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1); + LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1); + LL_SetSystemCoreClock(16000000); + + /* Update the time base */ + if (HAL_InitTick (TICK_INT_PRIORITY) != HAL_OK) + { + Error_Handler(); + } +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ +} +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + UNUSED(file); + UNUSED(line); + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/Testbench/NucleoG4-Blinky/Core/Src/stm32g4xx_it.c b/Testbench/NucleoG4-Blinky/Core/Src/stm32g4xx_it.c new file mode 100644 index 000000000..13e0f0c20 --- /dev/null +++ b/Testbench/NucleoG4-Blinky/Core/Src/stm32g4xx_it.c @@ -0,0 +1,203 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32g4xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32g4xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ + +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M4 Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + { + } + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Prefetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn 0 */ + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32G4xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32g4xx.s). */ +/******************************************************************************/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/Testbench/NucleoG4-Blinky/Core/Src/syscalls.c b/Testbench/NucleoG4-Blinky/Core/Src/syscalls.c new file mode 100644 index 000000000..e10d76fa2 --- /dev/null +++ b/Testbench/NucleoG4-Blinky/Core/Src/syscalls.c @@ -0,0 +1,244 @@ +/** + ****************************************************************************** + * @file syscalls.c + * @author Auto-generated by STM32CubeMX + * @brief Minimal System calls file + * + * For more information about which c-functions + * need which of these lowlevel functions + * please consult the Newlib or Picolibc libc-manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2020-2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include +#include +#include +#include +#include +#include +#include + + +/* Variables */ +extern int __io_putchar(int ch) __attribute__((weak)); +extern int __io_getchar(void) __attribute__((weak)); + + +char *__env[1] = { 0 }; +char **environ = __env; + + +/* Functions */ +void initialise_monitor_handles() +{ +} + +int _getpid(void) +{ + return 1; +} + +int _kill(int pid, int sig) +{ + (void)pid; + (void)sig; + errno = EINVAL; + return -1; +} + +void _exit (int status) +{ + _kill(status, -1); + while (1) {} /* Make sure we hang here */ +} + +__attribute__((weak)) int _read(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + *ptr++ = __io_getchar(); + } + + return len; +} + +__attribute__((weak)) int _write(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + __io_putchar(*ptr++); + } + return len; +} + +int _close(int file) +{ + (void)file; + return -1; +} + + +int _fstat(int file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _isatty(int file) +{ + (void)file; + return 1; +} + +int _lseek(int file, int ptr, int dir) +{ + (void)file; + (void)ptr; + (void)dir; + return 0; +} + +int _open(char *path, int flags, ...) +{ + (void)path; + (void)flags; + /* Pretend like we always fail */ + return -1; +} + +int _wait(int *status) +{ + (void)status; + errno = ECHILD; + return -1; +} + +int _unlink(char *name) +{ + (void)name; + errno = ENOENT; + return -1; +} + +clock_t _times(struct tms *buf) +{ + (void)buf; + return -1; +} + +int _stat(const char *file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _link(char *old, char *new) +{ + (void)old; + (void)new; + errno = EMLINK; + return -1; +} + +int _fork(void) +{ + errno = EAGAIN; + return -1; +} + +int _execve(char *name, char **argv, char **env) +{ + (void)name; + (void)argv; + (void)env; + errno = ENOMEM; + return -1; +} + +// --- Picolibc Specific Section --- +#if defined(__PICOLIBC__) + +/** + * @brief Picolibc helper function to output a character to a FILE stream. + * This redirects the output to the low-level __io_putchar function. + * @param c Character to write. + * @param file FILE stream pointer (ignored). + * @retval int The character written. + */ +static int starm_putc(char c, FILE *file) +{ + (void) file; + __io_putchar(c); + return c; +} + +/** + * @brief Picolibc helper function to input a character from a FILE stream. + * This redirects the input from the low-level __io_getchar function. + * @param file FILE stream pointer (ignored). + * @retval int The character read, cast to an unsigned char then int. + */ +static int starm_getc(FILE *file) +{ + unsigned char c; + (void) file; + c = __io_getchar(); + return c; +} + +// Define and initialize the standard I/O streams for Picolibc. +// FDEV_SETUP_STREAM connects the starm_putc and starm_getc helper functions to a FILE structure. +// _FDEV_SETUP_RW indicates the stream is for reading and writing. +static FILE __stdio = FDEV_SETUP_STREAM(starm_putc, + starm_getc, + NULL, + _FDEV_SETUP_RW); + +// Assign the standard stream pointers (stdin, stdout, stderr) to the initialized stream. +// Picolibc uses these pointers for standard I/O operations (printf, scanf, etc.). +FILE *const stdin = &__stdio; +__strong_reference(stdin, stdout); +__strong_reference(stdin, stderr); + +// Create strong aliases mapping standard C library function names (without underscore) +// to the implemented system call stubs (with underscore). Picolibc uses these +// standard names internally, so this linking is required. +__strong_reference(_read, read); +__strong_reference(_write, write); +__strong_reference(_times, times); +__strong_reference(_execve, execve); +__strong_reference(_fork, fork); +__strong_reference(_link, link); +__strong_reference(_unlink, unlink); +__strong_reference(_stat, stat); +__strong_reference(_wait, wait); +__strong_reference(_open, open); +__strong_reference(_close, close); +__strong_reference(_lseek, lseek); +__strong_reference(_isatty, isatty); +__strong_reference(_fstat, fstat); +__strong_reference(_exit, exit); +__strong_reference(_kill, kill); +__strong_reference(_getpid, getpid); + +#endif //__PICOLIBC__ diff --git a/Testbench/NucleoG4-Blinky/Core/Src/sysmem.c b/Testbench/NucleoG4-Blinky/Core/Src/sysmem.c new file mode 100644 index 000000000..a875d42c0 --- /dev/null +++ b/Testbench/NucleoG4-Blinky/Core/Src/sysmem.c @@ -0,0 +1,87 @@ +/** + ****************************************************************************** + * @file sysmem.c + * @author Generated by STM32CubeMX + * @brief System Memory calls file + * + * For more information about which C functions + * need which of these lowlevel functions + * please consult the Newlib or Picolibc libc manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include +#include + +/** + * Pointer to the current high watermark of the heap usage + */ +static uint8_t *__sbrk_heap_end = NULL; + +/** + * @brief _sbrk() allocates memory to the newlib heap and is used by malloc + * and others from the C library + * + * @verbatim + * ############################################################################ + * # .data # .bss # newlib heap # MSP stack # + * # # # # Reserved by _Min_Stack_Size # + * ############################################################################ + * ^-- RAM start ^-- _end _estack, RAM end --^ + * @endverbatim + * + * This implementation starts allocating at the '_end' linker symbol + * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack + * The implementation considers '_estack' linker symbol to be RAM end + * NOTE: If the MSP stack, at any point during execution, grows larger than the + * reserved size, please increase the '_Min_Stack_Size'. + * + * @param incr Memory size + * @return Pointer to allocated memory + */ +void *_sbrk(ptrdiff_t incr) +{ + extern uint8_t _end; /* Symbol defined in the linker script */ + extern uint8_t _estack; /* Symbol defined in the linker script */ + extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + const uint8_t *max_heap = (uint8_t *)stack_limit; + uint8_t *prev_heap_end; + + /* Initialize heap end at first call */ + if (NULL == __sbrk_heap_end) + { + __sbrk_heap_end = &_end; + } + + /* Protect heap from growing into the reserved MSP stack */ + if (__sbrk_heap_end + incr > max_heap) + { + errno = ENOMEM; + return (void *)-1; + } + + prev_heap_end = __sbrk_heap_end; + __sbrk_heap_end += incr; + + return (void *)prev_heap_end; +} + +#if defined(__PICOLIBC__) + // Picolibc expects syscalls without the leading underscore. + // This creates a strong alias so that + // calls to `sbrk()` are resolved to our `_sbrk()` implementation. + __strong_reference(_sbrk, sbrk); +#endif diff --git a/Testbench/NucleoG4-Blinky/Core/Src/system_stm32g4xx.c b/Testbench/NucleoG4-Blinky/Core/Src/system_stm32g4xx.c new file mode 100644 index 000000000..2cd914e7b --- /dev/null +++ b/Testbench/NucleoG4-Blinky/Core/Src/system_stm32g4xx.c @@ -0,0 +1,287 @@ +/** + ****************************************************************************** + * @file system_stm32g4xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32g4xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32g4xx.s" file, to + * configure the system clock before to branch to main program. + * + * This file configures the system clock as follows: + *============================================================================= + *----------------------------------------------------------------------------- + * System Clock source | HSI + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 16000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 16000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 1 + *----------------------------------------------------------------------------- + * PLL_M | 1 + *----------------------------------------------------------------------------- + * PLL_N | 16 + *----------------------------------------------------------------------------- + * PLL_P | 7 + *----------------------------------------------------------------------------- + * PLL_Q | 2 + *----------------------------------------------------------------------------- + * PLL_R | 2 + *----------------------------------------------------------------------------- + * Require 48MHz for RNG | Disabled + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32g4xx_system + * @{ + */ + +/** @addtogroup STM32G4xx_System_Private_Includes + * @{ + */ + +#include "stm32g4xx.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE 24000000U /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32G4xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32G4xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in Flash or Sram, else the vector table is kept at the automatic + remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +/*!< Uncomment the following line if you need to relocate your vector Table + in Sram else user remap will be done in Flash. */ +/* #define VECT_TAB_SRAM */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_SRAM */ + +#if !defined(VECT_TAB_OFFSET) +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_OFFSET */ + +#endif /* USER_VECT_TAB_ADDRESS */ +/******************************************************************************/ +/** + * @} + */ + +/** @addtogroup STM32G4xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32G4xx_System_Private_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = HSI_VALUE; + + const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; + const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; + +/** + * @} + */ + +/** @addtogroup STM32G4xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32G4xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ + +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ + #endif + + /* Configure the Vector Table location add offset address ------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (**) HSI_VALUE is a constant defined in stm32g4xx_hal.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in stm32g4xx_hal.h file (default value + * 24 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp, pllvco, pllr, pllsource, pllm; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case 0x04: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + + case 0x08: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + + case 0x0C: /* PLL used as system clock source */ + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); + pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1U ; + if (pllsource == 0x02UL) /* HSI used as PLL clock source */ + { + pllvco = (HSI_VALUE / pllm); + } + else /* HSE used as PLL clock source */ + { + pllvco = (HSE_VALUE / pllm); + } + pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8); + pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U; + SystemCoreClock = pllvco/pllr; + break; + + default: + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + diff --git a/Testbench/NucleoG4-Blinky/NucleoG4-Blinky.ioc b/Testbench/NucleoG4-Blinky/NucleoG4-Blinky.ioc new file mode 100644 index 000000000..3bb4b9c03 --- /dev/null +++ b/Testbench/NucleoG4-Blinky/NucleoG4-Blinky.ioc @@ -0,0 +1,122 @@ +#MicroXplorer Configuration settings - do not modify +CAD.formats= +CAD.pinconfig= +CAD.provider= +File.Version=6 +GPIO.groupedBy= +KeepUserPlacement=false +Mcu.CPN=STM32G474RET6 +Mcu.Family=STM32G4 +Mcu.IP0=NVIC +Mcu.IP1=RCC +Mcu.IP2=SYS +Mcu.IPNb=3 +Mcu.Name=STM32G474R(B-C-E)Tx +Mcu.Package=LQFP64 +Mcu.Pin0=PA5 +Mcu.Pin1=VP_SYS_VS_Systick +Mcu.Pin2=VP_SYS_VS_DBSignals +Mcu.PinsNb=3 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32G474RETx +MxCube.Version=6.18.1 +MxDb.Version=DB.6.0.181 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +PA5.GPIOParameters=GPIO_Label +PA5.GPIO_Label=USER_LED +PA5.Locked=true +PA5.Signal=GPIO_Output +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerLinker=GCC +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=true +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32G474RETx +ProjectManager.FirmwarePackage=STM32Cube FW_G4 V1.6.3 +ProjectManager.FreePins=true +ProjectManager.FreePinsContext= +ProjectManager.HalAssertFull=true +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=2 +ProjectManager.MainLocation=Core/Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=NucleoG4-Blinky.ioc +ProjectManager.ProjectName=NucleoG4-Blinky +ProjectManager.ProjectStructure= +ProjectManager.RegisterCallBack= +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=CMake +ProjectManager.ToolChainLocation= +ProjectManager.UAScriptAfterPath= +ProjectManager.UAScriptBeforePath= +ProjectManager.UnderRoot=false +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-LL-false,2-MX_GPIO_Init-GPIO-false-HAL-true +RCC.AHBFreq_Value=16000000 +RCC.APB1Freq_Value=16000000 +RCC.APB1TimFreq_Value=16000000 +RCC.APB2Freq_Value=16000000 +RCC.APB2TimFreq_Value=16000000 +RCC.CRSFreq_Value=48000000 +RCC.CortexFreq_Value=16000000 +RCC.EXTERNAL_CLOCK_VALUE=12288000 +RCC.FCLKCortexFreq_Value=16000000 +RCC.FDCANFreq_Value=16000000 +RCC.FamilyName=M +RCC.HCLKFreq_Value=16000000 +RCC.HRTIM1Freq_Value=16000000 +RCC.HSE_VALUE=8000000 +RCC.HSI48_VALUE=48000000 +RCC.HSI_VALUE=16000000 +RCC.I2C1Freq_Value=16000000 +RCC.I2C2Freq_Value=16000000 +RCC.I2C3Freq_Value=16000000 +RCC.I2C4Freq_Value=16000000 +RCC.I2SFreq_Value=16000000 +RCC.IPParameters=AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CRSFreq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLKCortexFreq_Value,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HRTIM1Freq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I2SFreq_Value,LPTIM1Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,QSPIFreq_Value,RNGFreq_Value,SAI1Freq_Value,SYSCLKFreq_VALUE,UART4Freq_Value,UART5Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value +RCC.LPTIM1Freq_Value=16000000 +RCC.LPUART1Freq_Value=16000000 +RCC.LSCOPinFreq_Value=32000 +RCC.LSE_VALUE=32768 +RCC.LSI_VALUE=32000 +RCC.MCO1PinFreq_Value=16000000 +RCC.PLLPoutputFreq_Value=64000000 +RCC.PLLQoutputFreq_Value=64000000 +RCC.PLLRCLKFreq_Value=64000000 +RCC.PWRFreq_Value=16000000 +RCC.QSPIFreq_Value=16000000 +RCC.RNGFreq_Value=64000000 +RCC.SAI1Freq_Value=16000000 +RCC.SYSCLKFreq_VALUE=16000000 +RCC.UART4Freq_Value=16000000 +RCC.UART5Freq_Value=16000000 +RCC.USART1Freq_Value=16000000 +RCC.USART2Freq_Value=16000000 +RCC.USART3Freq_Value=16000000 +RCC.USBFreq_Value=64000000 +RCC.VCOInputFreq_Value=16000000 +RCC.VCOOutputFreq_Value=128000000 +VP_SYS_VS_DBSignals.Mode=DisableDeadBatterySignals +VP_SYS_VS_DBSignals.Signal=SYS_VS_DBSignals +VP_SYS_VS_Systick.Mode=SysTick +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +board=custom diff --git a/Testbench/NucleoG4-Blinky/STM32G474xx_FLASH.ld b/Testbench/NucleoG4-Blinky/STM32G474xx_FLASH.ld new file mode 100644 index 000000000..2c518a14a --- /dev/null +++ b/Testbench/NucleoG4-Blinky/STM32G474xx_FLASH.ld @@ -0,0 +1,250 @@ +/* +****************************************************************************** +** + +** File : LinkerScript.ld +** +** Author : STM32CubeMX +** +** Abstract : Linker script for STM32G474RETx series +** 512Kbytes FLASH and 128Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed “as is,” without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +**

© COPYRIGHT(c) 2025 STMicroelectronics

+** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** 1. Redistributions of source code must retain the above copyright notice, +** this list of conditions and the following disclaimer. +** 2. Redistributions in binary form must reproduce the above copyright notice, +** this list of conditions and the following disclaimer in the documentation +** and/or other materials provided with the distribution. +** 3. Neither the name of STMicroelectronics nor the names of its contributors +** may be used to endorse or promote products derived from this software +** without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K +FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 512K +} + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of RAM */ +_sstack = _estack - _Min_Stack_Size; +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + } >RAM AT> FLASH + + /* Initialized TLS data section */ + .tdata : ALIGN(4) + { + *(.tdata .tdata.* .gnu.linkonce.td.*) + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + PROVIDE(__data_end = .); + PROVIDE(__tdata_end = .); + } >RAM AT> FLASH + + PROVIDE( __tdata_start = ADDR(.tdata) ); + PROVIDE( __tdata_size = __tdata_end - __tdata_start ); + + PROVIDE( __data_start = ADDR(.data) ); + PROVIDE( __data_size = __data_end - __data_start ); + + PROVIDE( __tdata_source = LOADADDR(.tdata) ); + PROVIDE( __tdata_source_end = LOADADDR(.tdata) + SIZEOF(.tdata) ); + PROVIDE( __tdata_source_size = __tdata_source_end - __tdata_source ); + + PROVIDE( __data_source = LOADADDR(.data) ); + PROVIDE( __data_source_end = __tdata_source_end ); + PROVIDE( __data_source_size = __data_source_end - __data_source ); + /* Uninitialized data section */ + .tbss (NOLOAD) : ALIGN(4) + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.tbss .tbss.*) + . = ALIGN(4); + PROVIDE( __tbss_end = . ); + } >RAM + + PROVIDE( __tbss_start = ADDR(.tbss) ); + PROVIDE( __tbss_size = __tbss_end - __tbss_start ); + PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); + + PROVIDE( __tls_base = __tdata_start ); + PROVIDE( __tls_end = __tbss_end ); + PROVIDE( __tls_size = __tls_end - __tls_base ); + PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); + PROVIDE( __tls_size_align = (__tls_size + __tls_align - 1) & ~(__tls_align - 1) ); + PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); + PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); + + .bss (NOLOAD) : ALIGN(4) + { + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + PROVIDE( __bss_end = .); + } >RAM + PROVIDE( __non_tls_bss_start = ADDR(.bss) ); + + PROVIDE( __bss_start = __tbss_start ); + PROVIDE( __bss_size = __bss_end - __bss_start ); + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack (NOLOAD) : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a:* ( * ) + libm.a:* ( * ) + libgcc.a:* ( * ) + } + +} diff --git a/Testbench/NucleoG4-Blinky/startup_stm32g474xx.s b/Testbench/NucleoG4-Blinky/startup_stm32g474xx.s new file mode 100644 index 000000000..e7a2c61fc --- /dev/null +++ b/Testbench/NucleoG4-Blinky/startup_stm32g474xx.s @@ -0,0 +1,592 @@ +/** + ****************************************************************************** + * @file startup_stm32g474xx.s + * @author MCD Application Team + * @brief STM32G474xx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex-M4. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_PVM_IRQHandler + .word RTC_TAMP_LSECSS_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_IRQHandler + .word USB_LP_IRQHandler + .word FDCAN1_IT0_IRQHandler + .word FDCAN1_IT1_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word USBWakeUp_IRQHandler + .word TIM8_BRK_IRQHandler + .word TIM8_UP_IRQHandler + .word TIM8_TRG_COM_IRQHandler + .word TIM8_CC_IRQHandler + .word ADC3_IRQHandler + .word FMC_IRQHandler + .word LPTIM1_IRQHandler + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_DAC_IRQHandler + .word TIM7_DAC_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word ADC4_IRQHandler + .word ADC5_IRQHandler + .word UCPD1_IRQHandler + .word COMP1_2_3_IRQHandler + .word COMP4_5_6_IRQHandler + .word COMP7_IRQHandler + .word HRTIM1_Master_IRQHandler + .word HRTIM1_TIMA_IRQHandler + .word HRTIM1_TIMB_IRQHandler + .word HRTIM1_TIMC_IRQHandler + .word HRTIM1_TIMD_IRQHandler + .word HRTIM1_TIME_IRQHandler + .word HRTIM1_FLT_IRQHandler + .word HRTIM1_TIMF_IRQHandler + .word CRS_IRQHandler + .word SAI1_IRQHandler + .word TIM20_BRK_IRQHandler + .word TIM20_UP_IRQHandler + .word TIM20_TRG_COM_IRQHandler + .word TIM20_CC_IRQHandler + .word FPU_IRQHandler + .word I2C4_EV_IRQHandler + .word I2C4_ER_IRQHandler + .word SPI4_IRQHandler + .word 0 + .word FDCAN2_IT0_IRQHandler + .word FDCAN2_IT1_IRQHandler + .word FDCAN3_IT0_IRQHandler + .word FDCAN3_IT1_IRQHandler + .word RNG_IRQHandler + .word LPUART1_IRQHandler + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word DMAMUX_OVR_IRQHandler + .word QUADSPI_IRQHandler + .word DMA1_Channel8_IRQHandler + .word DMA2_Channel6_IRQHandler + .word DMA2_Channel7_IRQHandler + .word DMA2_Channel8_IRQHandler + .word CORDIC_IRQHandler + .word FMAC_IRQHandler + + .size g_pfnVectors, .-g_pfnVectors + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak RTC_TAMP_LSECSS_IRQHandler + .thumb_set RTC_TAMP_LSECSS_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_IRQHandler + .thumb_set USB_HP_IRQHandler,Default_Handler + + .weak USB_LP_IRQHandler + .thumb_set USB_LP_IRQHandler,Default_Handler + + .weak FDCAN1_IT0_IRQHandler + .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler + + .weak FDCAN1_IT1_IRQHandler + .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_DAC_IRQHandler + .thumb_set TIM7_DAC_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak ADC4_IRQHandler + .thumb_set ADC4_IRQHandler,Default_Handler + + .weak ADC5_IRQHandler + .thumb_set ADC5_IRQHandler,Default_Handler + + .weak UCPD1_IRQHandler + .thumb_set UCPD1_IRQHandler,Default_Handler + + .weak COMP1_2_3_IRQHandler + .thumb_set COMP1_2_3_IRQHandler,Default_Handler + + .weak COMP4_5_6_IRQHandler + .thumb_set COMP4_5_6_IRQHandler,Default_Handler + + .weak COMP7_IRQHandler + .thumb_set COMP7_IRQHandler,Default_Handler + + .weak HRTIM1_Master_IRQHandler + .thumb_set HRTIM1_Master_IRQHandler,Default_Handler + + .weak HRTIM1_TIMA_IRQHandler + .thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler + + .weak HRTIM1_TIMB_IRQHandler + .thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler + + .weak HRTIM1_TIMC_IRQHandler + .thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler + + .weak HRTIM1_TIMD_IRQHandler + .thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler + + .weak HRTIM1_TIME_IRQHandler + .thumb_set HRTIM1_TIME_IRQHandler,Default_Handler + + .weak HRTIM1_FLT_IRQHandler + .thumb_set HRTIM1_FLT_IRQHandler,Default_Handler + + .weak HRTIM1_TIMF_IRQHandler + .thumb_set HRTIM1_TIMF_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak TIM20_BRK_IRQHandler + .thumb_set TIM20_BRK_IRQHandler,Default_Handler + + .weak TIM20_UP_IRQHandler + .thumb_set TIM20_UP_IRQHandler,Default_Handler + + .weak TIM20_TRG_COM_IRQHandler + .thumb_set TIM20_TRG_COM_IRQHandler,Default_Handler + + .weak TIM20_CC_IRQHandler + .thumb_set TIM20_CC_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak I2C4_EV_IRQHandler + .thumb_set I2C4_EV_IRQHandler,Default_Handler + + .weak I2C4_ER_IRQHandler + .thumb_set I2C4_ER_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak FDCAN2_IT0_IRQHandler + .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler + + .weak FDCAN2_IT1_IRQHandler + .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler + + .weak FDCAN3_IT0_IRQHandler + .thumb_set FDCAN3_IT0_IRQHandler,Default_Handler + + .weak FDCAN3_IT1_IRQHandler + .thumb_set FDCAN3_IT1_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak DMAMUX_OVR_IRQHandler + .thumb_set DMAMUX_OVR_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak DMA1_Channel8_IRQHandler + .thumb_set DMA1_Channel8_IRQHandler,Default_Handler + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak DMA2_Channel7_IRQHandler + .thumb_set DMA2_Channel7_IRQHandler,Default_Handler + + .weak DMA2_Channel8_IRQHandler + .thumb_set DMA2_Channel8_IRQHandler,Default_Handler + + .weak CORDIC_IRQHandler + .thumb_set CORDIC_IRQHandler,Default_Handler + + .weak FMAC_IRQHandler + .thumb_set FMAC_IRQHandler,Default_Handler + diff --git a/Testbench/testbench.cmake b/Testbench/testbench.cmake index 6f02b074e..a3b8c6714 100644 --- a/Testbench/testbench.cmake +++ b/Testbench/testbench.cmake @@ -7,3 +7,13 @@ add_project( CMSIS_GIT_TAG "v1.2.6" # https://github.com/STMicroelectronics/cmsis-device-g4/tree/v1.2.6 CMSIS_MAJOR "5" ) + +add_project( + NAME "NucleoG4-Blinky" + PATH "NucleoG4-Blinky" + SERIES "g4" + SPECIFIER "g474re" + HAL_GIT_TAG "v1.2.7" # https://github.com/STMicroelectronics/stm32g4xx-hal-driver/tree/v1.2.7 + CMSIS_GIT_TAG "v1.2.6" # https://github.com/STMicroelectronics/cmsis-device-g4/tree/v1.2.6 + CMSIS_MAJOR "5" +) From 844f8a2b4dd6e26ab7c6d770234f10ca6317f471 Mon Sep 17 00:00:00 2001 From: github-actions <41898282+github-actions[bot]@users.noreply.github.com> Date: Sun, 23 Aug 2026 23:42:31 +0000 Subject: [PATCH 10/17] Automatic CMake Format: Standardized formatting automatically --- Testbench/CUBEMXTESTING/CMakeLists.txt | 59 +++++++++++------------- Testbench/NucleoG4-Blinky/CMakeLists.txt | 46 ++++++++---------- 2 files changed, 48 insertions(+), 57 deletions(-) diff --git a/Testbench/CUBEMXTESTING/CMakeLists.txt b/Testbench/CUBEMXTESTING/CMakeLists.txt index a3c82d523..63b34f327 100644 --- a/Testbench/CUBEMXTESTING/CMakeLists.txt +++ b/Testbench/CUBEMXTESTING/CMakeLists.txt @@ -8,45 +8,42 @@ Required components (orderless) ]] target_link_options( - ${TARGET_NAME} - PRIVATE - -T "${CMAKE_CURRENT_SOURCE_DIR}/STM32G474xx_FLASH.ld" + ${TARGET_NAME} + PRIVATE + -T + "${CMAKE_CURRENT_SOURCE_DIR}/STM32G474xx_FLASH.ld" ) -target_compile_definitions( - ${TARGET_NAME} - PRIVATE - STM32G474xx -) +target_compile_definitions(${TARGET_NAME} PRIVATE STM32G474xx) target_include_directories( - ${TARGET_NAME} - PRIVATE - Core/Inc - Application/Inc + ${TARGET_NAME} + PRIVATE + Core/Inc + Application/Inc ) target_sources( - ${TARGET_NAME} - PRIVATE - Application/Src/CANdler.c - Application/Src/Loop.c - Core/Src/fdcan.c - Core/Src/gpio.c - Core/Src/main.c - Core/Src/stm32g4xx_it.c - Core/Src/syscalls.c - Core/Src/sysmem.c - Core/Src/system_stm32g4xx.c - Core/Src/tim.c - Core/Src/usart.c - startup_stm32g474xx.s + ${TARGET_NAME} + PRIVATE + Application/Src/CANdler.c + Application/Src/Loop.c + Core/Src/fdcan.c + Core/Src/gpio.c + Core/Src/main.c + Core/Src/stm32g4xx_it.c + Core/Src/syscalls.c + Core/Src/sysmem.c + Core/Src/system_stm32g4xx.c + Core/Src/tim.c + Core/Src/usart.c + startup_stm32g474xx.s ) target_link_libraries( - ${TARGET_NAME} - PRIVATE - CUBE_CAN_LIB - CUBE_VCP_LIB - LOGOMATIC_LIB + ${TARGET_NAME} + PRIVATE + CUBE_CAN_LIB + CUBE_VCP_LIB + LOGOMATIC_LIB ) diff --git a/Testbench/NucleoG4-Blinky/CMakeLists.txt b/Testbench/NucleoG4-Blinky/CMakeLists.txt index 1d8144aae..8261094a0 100644 --- a/Testbench/NucleoG4-Blinky/CMakeLists.txt +++ b/Testbench/NucleoG4-Blinky/CMakeLists.txt @@ -8,38 +8,32 @@ Required components (orderless) ]] target_link_options( - ${TARGET_NAME} - PRIVATE - -T "${CMAKE_CURRENT_SOURCE_DIR}/STM32G474xx_FLASH.ld" + ${TARGET_NAME} + PRIVATE + -T + "${CMAKE_CURRENT_SOURCE_DIR}/STM32G474xx_FLASH.ld" ) -target_compile_definitions( - ${TARGET_NAME} - PRIVATE - STM32G474xx -) +target_compile_definitions(${TARGET_NAME} PRIVATE STM32G474xx) target_include_directories( - ${TARGET_NAME} - PRIVATE - Core/Inc - Application/Inc + ${TARGET_NAME} + PRIVATE + Core/Inc + Application/Inc ) target_sources( - ${TARGET_NAME} - PRIVATE - Application/Src/morse.c - Core/Src/gpio.c - Core/Src/main.c - Core/Src/stm32g4xx_it.c - Core/Src/syscalls.c - Core/Src/sysmem.c - Core/Src/system_stm32g4xx.c - startup_stm32g474xx.s + ${TARGET_NAME} + PRIVATE + Application/Src/morse.c + Core/Src/gpio.c + Core/Src/main.c + Core/Src/stm32g4xx_it.c + Core/Src/syscalls.c + Core/Src/sysmem.c + Core/Src/system_stm32g4xx.c + startup_stm32g474xx.s ) -target_link_libraries( - ${TARGET_NAME} - PRIVATE -) +target_link_libraries(${TARGET_NAME} PRIVATE) From 109103543c181bb5ae2e74373af30c6ea54d3d69 Mon Sep 17 00:00:00 2001 From: github-actions <41898282+github-actions[bot]@users.noreply.github.com> Date: Sun, 23 Aug 2026 23:43:58 +0000 Subject: [PATCH 11/17] Automatic Clang-Format: Standardized formatting automatically --- Testbench/NucleoG4-Blinky/Core/Inc/gpio.h | 33 +- Testbench/NucleoG4-Blinky/Core/Inc/main.h | 45 +- .../NucleoG4-Blinky/Core/Inc/stm32_assert.h | 49 +- .../Core/Inc/stm32g4xx_hal_conf.h | 245 +++++----- .../NucleoG4-Blinky/Core/Inc/stm32g4xx_it.h | 30 +- Testbench/NucleoG4-Blinky/Core/Src/gpio.c | 175 ++++--- Testbench/NucleoG4-Blinky/Core/Src/main.c | 185 ++++---- .../NucleoG4-Blinky/Core/Src/stm32g4xx_it.c | 177 ++++--- Testbench/NucleoG4-Blinky/Core/Src/syscalls.c | 147 +++--- Testbench/NucleoG4-Blinky/Core/Src/sysmem.c | 48 +- .../Core/Src/system_stm32g4xx.c | 432 +++++++++--------- 11 files changed, 764 insertions(+), 802 deletions(-) diff --git a/Testbench/NucleoG4-Blinky/Core/Inc/gpio.h b/Testbench/NucleoG4-Blinky/Core/Inc/gpio.h index 3c91c4dd6..37dcc0a5c 100644 --- a/Testbench/NucleoG4-Blinky/Core/Inc/gpio.h +++ b/Testbench/NucleoG4-Blinky/Core/Inc/gpio.h @@ -1,21 +1,21 @@ /* USER CODE BEGIN Header */ /** - ****************************************************************************** - * @file gpio.h - * @brief This file contains all the function prototypes for - * the gpio.c file - ****************************************************************************** - * @attention - * - * Copyright (c) 2026 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ + ****************************************************************************** + * @file gpio.h + * @brief This file contains all the function prototypes for + * the gpio.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ /* USER CODE END Header */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __GPIO_H__ @@ -46,4 +46,3 @@ void MX_GPIO_Init(void); } #endif #endif /*__ GPIO_H__ */ - diff --git a/Testbench/NucleoG4-Blinky/Core/Inc/main.h b/Testbench/NucleoG4-Blinky/Core/Inc/main.h index 1e2c763d8..07f5c4299 100644 --- a/Testbench/NucleoG4-Blinky/Core/Inc/main.h +++ b/Testbench/NucleoG4-Blinky/Core/Inc/main.h @@ -1,21 +1,21 @@ /* USER CODE BEGIN Header */ /** - ****************************************************************************** - * @file : main.h - * @brief : Header for main.c file. - * This file contains the common defines of the application. - ****************************************************************************** - * @attention - * - * Copyright (c) 2026 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ /* USER CODE END Header */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -28,17 +28,16 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" - -#include "stm32g4xx_ll_rcc.h" #include "stm32g4xx_ll_bus.h" -#include "stm32g4xx_ll_crs.h" -#include "stm32g4xx_ll_system.h" -#include "stm32g4xx_ll_exti.h" #include "stm32g4xx_ll_cortex.h" -#include "stm32g4xx_ll_utils.h" -#include "stm32g4xx_ll_pwr.h" +#include "stm32g4xx_ll_crs.h" #include "stm32g4xx_ll_dma.h" +#include "stm32g4xx_ll_exti.h" #include "stm32g4xx_ll_gpio.h" +#include "stm32g4xx_ll_pwr.h" +#include "stm32g4xx_ll_rcc.h" +#include "stm32g4xx_ll_system.h" +#include "stm32g4xx_ll_utils.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ diff --git a/Testbench/NucleoG4-Blinky/Core/Inc/stm32_assert.h b/Testbench/NucleoG4-Blinky/Core/Inc/stm32_assert.h index 61631c41e..92460620f 100644 --- a/Testbench/NucleoG4-Blinky/Core/Inc/stm32_assert.h +++ b/Testbench/NucleoG4-Blinky/Core/Inc/stm32_assert.h @@ -1,21 +1,21 @@ /* USER CODE BEGIN Header */ /** - ****************************************************************************** - * @file stm32_assert.h - * @author MCD Application Team - * @brief STM32 assert file. - ****************************************************************************** - * @attention - * - * Copyright (c) 2019 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ + ****************************************************************************** + * @file stm32_assert.h + * @author MCD Application Team + * @brief STM32 assert file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ /* USER CODE END Header */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32_ASSERT_H @@ -29,15 +29,15 @@ extern "C" { /* Exported constants --------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT +#ifdef USE_FULL_ASSERT /** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) /* Exported functions ------------------------------------------------------- */ void assert_failed(uint8_t *file, uint32_t line); @@ -50,4 +50,3 @@ void assert_failed(uint8_t *file, uint32_t line); #endif #endif /* __STM32_ASSERT_H */ - diff --git a/Testbench/NucleoG4-Blinky/Core/Inc/stm32g4xx_hal_conf.h b/Testbench/NucleoG4-Blinky/Core/Inc/stm32g4xx_hal_conf.h index 90adf393c..b56f22666 100644 --- a/Testbench/NucleoG4-Blinky/Core/Inc/stm32g4xx_hal_conf.h +++ b/Testbench/NucleoG4-Blinky/Core/Inc/stm32g4xx_hal_conf.h @@ -1,21 +1,21 @@ /* USER CODE BEGIN Header */ /** - ****************************************************************************** - * @file stm32g4xx_hal_conf.h - * @author MCD Application Team - * @brief HAL configuration file - ****************************************************************************** + ****************************************************************************** + * @file stm32g4xx_hal_conf.h + * @author MCD Application Team + * @brief HAL configuration file + ****************************************************************************** * @attention - * - * Copyright (c) 2019 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ /* USER CODE END Header */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -23,7 +23,7 @@ #define STM32G4xx_HAL_CONF_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Exported types ------------------------------------------------------------*/ @@ -31,12 +31,12 @@ /* ########################## Module Selection ############################## */ /** - * @brief This is the list of modules to be used in the HAL driver - */ + * @brief This is the list of modules to be used in the HAL driver + */ #define HAL_MODULE_ENABLED - /*#define HAL_ADC_MODULE_ENABLED */ +/*#define HAL_ADC_MODULE_ENABLED */ /*#define HAL_COMP_MODULE_ENABLED */ /*#define HAL_CORDIC_MODULE_ENABLED */ /*#define HAL_CRC_MODULE_ENABLED */ @@ -76,123 +76,124 @@ /* ########################## Register Callbacks selection ############################## */ /** - * @brief This is the list of modules where register callback can be used - */ -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U -#define USE_HAL_COMP_REGISTER_CALLBACKS 0U -#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U -#define USE_HAL_EXTI_REGISTER_CALLBACKS 0U -#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U -#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U -#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U -#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U -#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U -#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U -#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U -#define USE_HAL_UART_REGISTER_CALLBACKS 0U -#define USE_HAL_USART_REGISTER_CALLBACKS 0U -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U + * @brief This is the list of modules where register callback can be used + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U +#define USE_HAL_COMP_REGISTER_CALLBACKS 0U +#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U +#define USE_HAL_EXTI_REGISTER_CALLBACKS 0U +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U +#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U +#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U +#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U +#define USE_HAL_UART_REGISTER_CALLBACKS 0U +#define USE_HAL_USART_REGISTER_CALLBACKS 0U +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* ########################## Oscillator Values adaptation ####################*/ /** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined(HSE_VALUE) +#define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined(HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ /** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined(HSI_VALUE) +#define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ /** - * @brief Internal High Speed oscillator (HSI48) value for USB FS and RNG. - * This internal oscillator is mainly dedicated to provide a high precision clock to - * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. - * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency - * which is subject to manufacturing process variations. - */ -#if !defined (HSI48_VALUE) - #define HSI48_VALUE (48000000UL) /*!< Value of the Internal High Speed oscillator for USB FS/RNG in Hz. - The real value my vary depending on manufacturing process variations.*/ -#endif /* HSI48_VALUE */ + * @brief Internal High Speed oscillator (HSI48) value for USB FS and RNG. + * This internal oscillator is mainly dedicated to provide a high precision clock to + * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. + * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency + * which is subject to manufacturing process variations. + */ +#if !defined(HSI48_VALUE) +#define HSI48_VALUE \ + (48000000UL) /*!< Value of the Internal High Speed oscillator for USB FS/RNG in Hz. \ + The real value my vary depending on manufacturing process variations.*/ +#endif /* HSI48_VALUE */ /** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined(LSI_VALUE) /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature.*/ -#define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/ -#endif /* LSI_VALUE */ +#define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /** - * @brief External Low Speed oscillator (LSE) value. - * This value is used by the UART, RTC HAL module to compute the system frequency - */ -#if !defined (LSE_VALUE) -#define LSE_VALUE (32768UL) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined(LSE_VALUE) +#define LSE_VALUE (32768UL) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ -#if !defined (LSE_STARTUP_TIMEOUT) -#define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ +#if !defined(LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ /** - * @brief External clock source for I2S and SAI peripherals - * This value is used by the I2S and SAI HAL modules to compute the I2S and SAI clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined (EXTERNAL_CLOCK_VALUE) -#define EXTERNAL_CLOCK_VALUE (12288000UL) /*!< Value of the External oscillator in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ + * @brief External clock source for I2S and SAI peripherals + * This value is used by the I2S and SAI HAL modules to compute the I2S and SAI clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined(EXTERNAL_CLOCK_VALUE) +#define EXTERNAL_CLOCK_VALUE (12288000UL) /*!< Value of the External oscillator in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ /* Tip: To avoid modifying this file each time you need to use different HSE, === you can define the HSE value in your toolchain compiler preprocessor. */ /* ########################### System Configuration ######################### */ /** - * @brief This is the HAL system configuration section - */ + * @brief This is the HAL system configuration section + */ -#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority (lowest by default) */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 0U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U +#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority (lowest by default) */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 0U +#define INSTRUCTION_CACHE_ENABLE 1U +#define DATA_CACHE_ENABLE 1U /* ########################## Assert Selection ############################## */ /** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ - #define USE_FULL_ASSERT 1U + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +#define USE_FULL_ASSERT 1U /* ################## SPI peripheral configuration ########################## */ @@ -201,12 +202,12 @@ The real value may vary depending on the variations in voltage and temperature.* * Deactivated: CRC code cleaned from driver */ -#define USE_SPI_CRC 0U +#define USE_SPI_CRC 0U /* Includes ------------------------------------------------------------------*/ /** - * @brief Include module's header file - */ + * @brief Include module's header file + */ #ifdef HAL_RCC_MODULE_ENABLED #include "stm32g4xx_hal_rcc.h" @@ -357,15 +358,15 @@ The real value may vary depending on the variations in voltage and temperature.* #endif /* HAL_WWDG_MODULE_ENABLED */ /* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT +#ifdef USE_FULL_ASSERT /** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) /* Exported functions ------------------------------------------------------- */ void assert_failed(uint8_t *file, uint32_t line); diff --git a/Testbench/NucleoG4-Blinky/Core/Inc/stm32g4xx_it.h b/Testbench/NucleoG4-Blinky/Core/Inc/stm32g4xx_it.h index 1a144ad22..3cfc1aa5a 100644 --- a/Testbench/NucleoG4-Blinky/Core/Inc/stm32g4xx_it.h +++ b/Testbench/NucleoG4-Blinky/Core/Inc/stm32g4xx_it.h @@ -1,20 +1,20 @@ /* USER CODE BEGIN Header */ /** - ****************************************************************************** - * @file stm32g4xx_it.h - * @brief This file contains the headers of the interrupt handlers. - ****************************************************************************** - * @attention - * - * Copyright (c) 2026 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ + ****************************************************************************** + * @file stm32g4xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ /* USER CODE END Header */ /* Define to prevent recursive inclusion -------------------------------------*/ diff --git a/Testbench/NucleoG4-Blinky/Core/Src/gpio.c b/Testbench/NucleoG4-Blinky/Core/Src/gpio.c index 7f64369d4..d41fa2e7c 100644 --- a/Testbench/NucleoG4-Blinky/Core/Src/gpio.c +++ b/Testbench/NucleoG4-Blinky/Core/Src/gpio.c @@ -1,21 +1,21 @@ /* USER CODE BEGIN Header */ /** - ****************************************************************************** - * @file gpio.c - * @brief This file provides code for the configuration - * of all used GPIO pins. - ****************************************************************************** - * @attention - * - * Copyright (c) 2026 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ + ****************************************************************************** + * @file gpio.c + * @brief This file provides code for the configuration + * of all used GPIO pins. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ @@ -33,84 +33,77 @@ /* USER CODE END 1 */ /** Configure pins -*/ + */ void MX_GPIO_Init(void) { - GPIO_InitTypeDef GPIO_InitStruct = {0}; - - /* GPIO Ports Clock Enable */ - __HAL_RCC_GPIOC_CLK_ENABLE(); - __HAL_RCC_GPIOF_CLK_ENABLE(); - __HAL_RCC_GPIOG_CLK_ENABLE(); - __HAL_RCC_GPIOA_CLK_ENABLE(); - __HAL_RCC_GPIOB_CLK_ENABLE(); - __HAL_RCC_GPIOD_CLK_ENABLE(); - - /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(USER_LED_GPIO_Port, USER_LED_Pin, GPIO_PIN_RESET); - - /*Configure GPIO pins : PC13 PC14 PC15 PC0 - PC1 PC2 PC3 PC4 - PC5 PC6 PC7 PC8 - PC9 PC10 PC11 PC12 */ - GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15|GPIO_PIN_0 - |GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4 - |GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8 - |GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /*Configure GPIO pins : PF0 PF1 */ - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); - - /*Configure GPIO pin : PG10 */ - GPIO_InitStruct.Pin = GPIO_PIN_10; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); - - /*Configure GPIO pins : PA0 PA1 PA2 PA3 - PA4 PA6 PA7 PA8 - PA9 PA10 PA11 PA12 - PA13 PA14 PA15 */ - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 - |GPIO_PIN_4|GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8 - |GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12 - |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /*Configure GPIO pin : USER_LED_Pin */ - GPIO_InitStruct.Pin = USER_LED_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - HAL_GPIO_Init(USER_LED_GPIO_Port, &GPIO_InitStruct); - - /*Configure GPIO pins : PB0 PB1 PB2 PB10 - PB11 PB12 PB13 PB14 - PB15 PB3 PB4 PB5 - PB6 PB7 PB8 PB9 */ - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_10 - |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 - |GPIO_PIN_15|GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5 - |GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /*Configure GPIO pin : PD2 */ - GPIO_InitStruct.Pin = GPIO_PIN_2; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); - + GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(USER_LED_GPIO_Port, USER_LED_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pins : PC13 PC14 PC15 PC0 + PC1 PC2 PC3 PC4 + PC5 PC6 PC7 PC8 + PC9 PC10 PC11 PC12 */ + GPIO_InitStruct.Pin = GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15 | GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | + GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /*Configure GPIO pins : PF0 PF1 */ + GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + /*Configure GPIO pin : PG10 */ + GPIO_InitStruct.Pin = GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + /*Configure GPIO pins : PA0 PA1 PA2 PA3 + PA4 PA6 PA7 PA8 + PA9 PA10 PA11 PA12 + PA13 PA14 PA15 */ + GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | + GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /*Configure GPIO pin : USER_LED_Pin */ + GPIO_InitStruct.Pin = USER_LED_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(USER_LED_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pins : PB0 PB1 PB2 PB10 + PB11 PB12 PB13 PB14 + PB15 PB3 PB4 PB5 + PB6 PB7 PB8 PB9 */ + GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | + GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /*Configure GPIO pin : PD2 */ + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); } /* USER CODE BEGIN 2 */ diff --git a/Testbench/NucleoG4-Blinky/Core/Src/main.c b/Testbench/NucleoG4-Blinky/Core/Src/main.c index ff8b65b47..d7782e301 100644 --- a/Testbench/NucleoG4-Blinky/Core/Src/main.c +++ b/Testbench/NucleoG4-Blinky/Core/Src/main.c @@ -1,23 +1,24 @@ /* USER CODE BEGIN Header */ /** - ****************************************************************************** - * @file : main.c - * @brief : Main program body - ****************************************************************************** - * @attention - * - * Copyright (c) 2026 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "main.h" + #include "gpio.h" /* Private includes ----------------------------------------------------------*/ @@ -58,88 +59,80 @@ void SystemClock_Config(void); /* USER CODE END 0 */ /** - * @brief The application entry point. - * @retval int - */ + * @brief The application entry point. + * @retval int + */ int main(void) { - /* USER CODE BEGIN 1 */ + /* USER CODE BEGIN 1 */ - /* USER CODE END 1 */ + /* USER CODE END 1 */ - /* MCU Configuration--------------------------------------------------------*/ + /* MCU Configuration--------------------------------------------------------*/ - /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ - HAL_Init(); + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); - /* USER CODE BEGIN Init */ + /* USER CODE BEGIN Init */ - /* USER CODE END Init */ + /* USER CODE END Init */ - /* Configure the system clock */ - SystemClock_Config(); + /* Configure the system clock */ + SystemClock_Config(); - /* USER CODE BEGIN SysInit */ + /* USER CODE BEGIN SysInit */ - /* USER CODE END SysInit */ + /* USER CODE END SysInit */ - /* Initialize all configured peripherals */ - MX_GPIO_Init(); - /* USER CODE BEGIN 2 */ + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + /* USER CODE BEGIN 2 */ - /* USER CODE END 2 */ + /* USER CODE END 2 */ - /* Infinite loop */ - /* USER CODE BEGIN WHILE */ - while (1) - { - /* USER CODE END WHILE */ + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) { + /* USER CODE END WHILE */ - /* USER CODE BEGIN 3 */ - if (morse_code_send(message, sizeof(message) / sizeof(message[0])) != HAL_OK) { - Error_Handler(); - } - HAL_Delay(500); - } - /* USER CODE END 3 */ + /* USER CODE BEGIN 3 */ + if (morse_code_send(message, sizeof(message) / sizeof(message[0])) != HAL_OK) { + Error_Handler(); + } + HAL_Delay(500); + } + /* USER CODE END 3 */ } /** - * @brief System Clock Configuration - * @retval None - */ + * @brief System Clock Configuration + * @retval None + */ void SystemClock_Config(void) { - LL_FLASH_SetLatency(LL_FLASH_LATENCY_0); - while(LL_FLASH_GetLatency() != LL_FLASH_LATENCY_0) - { - } - LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1); - LL_RCC_HSI_Enable(); - /* Wait till HSI is ready */ - while(LL_RCC_HSI_IsReady() != 1) - { - } - - LL_RCC_HSI_SetCalibTrimming(64); - LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI); - /* Wait till System clock is ready */ - while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI) - { - } - - /* Set AHB prescaler*/ - LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1); - LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1); - LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1); - LL_SetSystemCoreClock(16000000); - - /* Update the time base */ - if (HAL_InitTick (TICK_INT_PRIORITY) != HAL_OK) - { - Error_Handler(); - } + LL_FLASH_SetLatency(LL_FLASH_LATENCY_0); + while (LL_FLASH_GetLatency() != LL_FLASH_LATENCY_0) {} + LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1); + LL_RCC_HSI_Enable(); + /* Wait till HSI is ready */ + while (LL_RCC_HSI_IsReady() != 1) {} + + LL_RCC_HSI_SetCalibTrimming(64); + LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI); + /* Wait till System clock is ready */ + while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI) {} + + /* Set AHB prescaler*/ + LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1); + LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1); + LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1); + LL_SetSystemCoreClock(16000000); + + /* Update the time base */ + if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) { + Error_Handler(); + } } /* USER CODE BEGIN 4 */ @@ -147,32 +140,30 @@ void SystemClock_Config(void) /* USER CODE END 4 */ /** - * @brief This function is executed in case of error occurrence. - * @retval None - */ + * @brief This function is executed in case of error occurrence. + * @retval None + */ void Error_Handler(void) { - /* USER CODE BEGIN Error_Handler_Debug */ - /* User can add his own implementation to report the HAL error return state */ - __disable_irq(); - while (1) - { - } - /* USER CODE END Error_Handler_Debug */ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) {} + /* USER CODE END Error_Handler_Debug */ } #ifdef USE_FULL_ASSERT /** - * @brief Reports the name of the source file and the source line number - * where the assert_param error has occurred. - * @param file: pointer to the source file name - * @param line: assert_param error line source number - * @retval None - */ + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ void assert_failed(uint8_t *file, uint32_t line) { - /* USER CODE BEGIN 6 */ - UNUSED(file); - UNUSED(line); - /* USER CODE END 6 */ + /* USER CODE BEGIN 6 */ + UNUSED(file); + UNUSED(line); + /* USER CODE END 6 */ } #endif /* USE_FULL_ASSERT */ diff --git a/Testbench/NucleoG4-Blinky/Core/Src/stm32g4xx_it.c b/Testbench/NucleoG4-Blinky/Core/Src/stm32g4xx_it.c index 13e0f0c20..22ab0ab23 100644 --- a/Testbench/NucleoG4-Blinky/Core/Src/stm32g4xx_it.c +++ b/Testbench/NucleoG4-Blinky/Core/Src/stm32g4xx_it.c @@ -1,25 +1,26 @@ /* USER CODE BEGIN Header */ /** - ****************************************************************************** - * @file stm32g4xx_it.c - * @brief Interrupt Service Routines. - ****************************************************************************** - * @attention - * - * Copyright (c) 2026 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ + ****************************************************************************** + * @file stm32g4xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ -#include "main.h" #include "stm32g4xx_it.h" + +#include "main.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ /* USER CODE END Includes */ @@ -64,131 +65,125 @@ /* Cortex-M4 Processor Interruption and Exception Handlers */ /******************************************************************************/ /** - * @brief This function handles Non maskable interrupt. - */ + * @brief This function handles Non maskable interrupt. + */ void NMI_Handler(void) { - /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ - - /* USER CODE END NonMaskableInt_IRQn 0 */ - /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ - while (1) - { - } - /* USER CODE END NonMaskableInt_IRQn 1 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) {} + /* USER CODE END NonMaskableInt_IRQn 1 */ } /** - * @brief This function handles Hard fault interrupt. - */ + * @brief This function handles Hard fault interrupt. + */ void HardFault_Handler(void) { - /* USER CODE BEGIN HardFault_IRQn 0 */ - - /* USER CODE END HardFault_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_HardFault_IRQn 0 */ - /* USER CODE END W1_HardFault_IRQn 0 */ - } + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } } /** - * @brief This function handles Memory management fault. - */ + * @brief This function handles Memory management fault. + */ void MemManage_Handler(void) { - /* USER CODE BEGIN MemoryManagement_IRQn 0 */ - - /* USER CODE END MemoryManagement_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ - /* USER CODE END W1_MemoryManagement_IRQn 0 */ - } + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } } /** - * @brief This function handles Prefetch fault, memory access fault. - */ + * @brief This function handles Prefetch fault, memory access fault. + */ void BusFault_Handler(void) { - /* USER CODE BEGIN BusFault_IRQn 0 */ - - /* USER CODE END BusFault_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_BusFault_IRQn 0 */ - /* USER CODE END W1_BusFault_IRQn 0 */ - } + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } } /** - * @brief This function handles Undefined instruction or illegal state. - */ + * @brief This function handles Undefined instruction or illegal state. + */ void UsageFault_Handler(void) { - /* USER CODE BEGIN UsageFault_IRQn 0 */ - - /* USER CODE END UsageFault_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ - /* USER CODE END W1_UsageFault_IRQn 0 */ - } + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } } /** - * @brief This function handles System service call via SWI instruction. - */ + * @brief This function handles System service call via SWI instruction. + */ void SVC_Handler(void) { - /* USER CODE BEGIN SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 0 */ - /* USER CODE END SVCall_IRQn 0 */ - /* USER CODE BEGIN SVCall_IRQn 1 */ + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ - /* USER CODE END SVCall_IRQn 1 */ + /* USER CODE END SVCall_IRQn 1 */ } /** - * @brief This function handles Debug monitor. - */ + * @brief This function handles Debug monitor. + */ void DebugMon_Handler(void) { - /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ - /* USER CODE END DebugMonitor_IRQn 0 */ - /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ - /* USER CODE END DebugMonitor_IRQn 1 */ + /* USER CODE END DebugMonitor_IRQn 1 */ } /** - * @brief This function handles Pendable request for system service. - */ + * @brief This function handles Pendable request for system service. + */ void PendSV_Handler(void) { - /* USER CODE BEGIN PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 0 */ - /* USER CODE END PendSV_IRQn 0 */ - /* USER CODE BEGIN PendSV_IRQn 1 */ + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ - /* USER CODE END PendSV_IRQn 1 */ + /* USER CODE END PendSV_IRQn 1 */ } /** - * @brief This function handles System tick timer. - */ + * @brief This function handles System tick timer. + */ void SysTick_Handler(void) { - /* USER CODE BEGIN SysTick_IRQn 0 */ + /* USER CODE BEGIN SysTick_IRQn 0 */ - /* USER CODE END SysTick_IRQn 0 */ - HAL_IncTick(); - /* USER CODE BEGIN SysTick_IRQn 1 */ + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ - /* USER CODE END SysTick_IRQn 1 */ + /* USER CODE END SysTick_IRQn 1 */ } /******************************************************************************/ diff --git a/Testbench/NucleoG4-Blinky/Core/Src/syscalls.c b/Testbench/NucleoG4-Blinky/Core/Src/syscalls.c index e10d76fa2..d2b217993 100644 --- a/Testbench/NucleoG4-Blinky/Core/Src/syscalls.c +++ b/Testbench/NucleoG4-Blinky/Core/Src/syscalls.c @@ -21,158 +21,150 @@ */ /* Includes */ -#include -#include #include -#include #include -#include +#include +#include +#include #include #include - +#include /* Variables */ extern int __io_putchar(int ch) __attribute__((weak)); extern int __io_getchar(void) __attribute__((weak)); - -char *__env[1] = { 0 }; +char *__env[1] = {0}; char **environ = __env; - /* Functions */ -void initialise_monitor_handles() -{ -} +void initialise_monitor_handles() {} int _getpid(void) { - return 1; + return 1; } int _kill(int pid, int sig) { - (void)pid; - (void)sig; - errno = EINVAL; - return -1; + (void)pid; + (void)sig; + errno = EINVAL; + return -1; } -void _exit (int status) +void _exit(int status) { - _kill(status, -1); - while (1) {} /* Make sure we hang here */ + _kill(status, -1); + while (1) {} /* Make sure we hang here */ } __attribute__((weak)) int _read(int file, char *ptr, int len) { - (void)file; - int DataIdx; + (void)file; + int DataIdx; - for (DataIdx = 0; DataIdx < len; DataIdx++) - { - *ptr++ = __io_getchar(); - } + for (DataIdx = 0; DataIdx < len; DataIdx++) { + *ptr++ = __io_getchar(); + } - return len; + return len; } __attribute__((weak)) int _write(int file, char *ptr, int len) { - (void)file; - int DataIdx; + (void)file; + int DataIdx; - for (DataIdx = 0; DataIdx < len; DataIdx++) - { - __io_putchar(*ptr++); - } - return len; + for (DataIdx = 0; DataIdx < len; DataIdx++) { + __io_putchar(*ptr++); + } + return len; } int _close(int file) { - (void)file; - return -1; + (void)file; + return -1; } - int _fstat(int file, struct stat *st) { - (void)file; - st->st_mode = S_IFCHR; - return 0; + (void)file; + st->st_mode = S_IFCHR; + return 0; } int _isatty(int file) { - (void)file; - return 1; + (void)file; + return 1; } int _lseek(int file, int ptr, int dir) { - (void)file; - (void)ptr; - (void)dir; - return 0; + (void)file; + (void)ptr; + (void)dir; + return 0; } int _open(char *path, int flags, ...) { - (void)path; - (void)flags; - /* Pretend like we always fail */ - return -1; + (void)path; + (void)flags; + /* Pretend like we always fail */ + return -1; } int _wait(int *status) { - (void)status; - errno = ECHILD; - return -1; + (void)status; + errno = ECHILD; + return -1; } int _unlink(char *name) { - (void)name; - errno = ENOENT; - return -1; + (void)name; + errno = ENOENT; + return -1; } clock_t _times(struct tms *buf) { - (void)buf; - return -1; + (void)buf; + return -1; } int _stat(const char *file, struct stat *st) { - (void)file; - st->st_mode = S_IFCHR; - return 0; + (void)file; + st->st_mode = S_IFCHR; + return 0; } int _link(char *old, char *new) { - (void)old; - (void)new; - errno = EMLINK; - return -1; + (void)old; + (void)new; + errno = EMLINK; + return -1; } int _fork(void) { - errno = EAGAIN; - return -1; + errno = EAGAIN; + return -1; } int _execve(char *name, char **argv, char **env) { - (void)name; - (void)argv; - (void)env; - errno = ENOMEM; - return -1; + (void)name; + (void)argv; + (void)env; + errno = ENOMEM; + return -1; } // --- Picolibc Specific Section --- @@ -187,8 +179,8 @@ int _execve(char *name, char **argv, char **env) */ static int starm_putc(char c, FILE *file) { - (void) file; - __io_putchar(c); + (void)file; + __io_putchar(c); return c; } @@ -201,18 +193,15 @@ static int starm_putc(char c, FILE *file) static int starm_getc(FILE *file) { unsigned char c; - (void) file; - c = __io_getchar(); + (void)file; + c = __io_getchar(); return c; } // Define and initialize the standard I/O streams for Picolibc. // FDEV_SETUP_STREAM connects the starm_putc and starm_getc helper functions to a FILE structure. // _FDEV_SETUP_RW indicates the stream is for reading and writing. -static FILE __stdio = FDEV_SETUP_STREAM(starm_putc, - starm_getc, - NULL, - _FDEV_SETUP_RW); +static FILE __stdio = FDEV_SETUP_STREAM(starm_putc, starm_getc, NULL, _FDEV_SETUP_RW); // Assign the standard stream pointers (stdin, stdout, stderr) to the initialized stream. // Picolibc uses these pointers for standard I/O operations (printf, scanf, etc.). diff --git a/Testbench/NucleoG4-Blinky/Core/Src/sysmem.c b/Testbench/NucleoG4-Blinky/Core/Src/sysmem.c index a875d42c0..3a092d114 100644 --- a/Testbench/NucleoG4-Blinky/Core/Src/sysmem.c +++ b/Testbench/NucleoG4-Blinky/Core/Src/sysmem.c @@ -22,8 +22,8 @@ /* Includes */ #include -#include #include +#include /** * Pointer to the current high watermark of the heap usage @@ -53,35 +53,33 @@ static uint8_t *__sbrk_heap_end = NULL; */ void *_sbrk(ptrdiff_t incr) { - extern uint8_t _end; /* Symbol defined in the linker script */ - extern uint8_t _estack; /* Symbol defined in the linker script */ - extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ - const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; - const uint8_t *max_heap = (uint8_t *)stack_limit; - uint8_t *prev_heap_end; + extern uint8_t _end; /* Symbol defined in the linker script */ + extern uint8_t _estack; /* Symbol defined in the linker script */ + extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + const uint8_t *max_heap = (uint8_t *)stack_limit; + uint8_t *prev_heap_end; - /* Initialize heap end at first call */ - if (NULL == __sbrk_heap_end) - { - __sbrk_heap_end = &_end; - } + /* Initialize heap end at first call */ + if (NULL == __sbrk_heap_end) { + __sbrk_heap_end = &_end; + } - /* Protect heap from growing into the reserved MSP stack */ - if (__sbrk_heap_end + incr > max_heap) - { - errno = ENOMEM; - return (void *)-1; - } + /* Protect heap from growing into the reserved MSP stack */ + if (__sbrk_heap_end + incr > max_heap) { + errno = ENOMEM; + return (void *)-1; + } - prev_heap_end = __sbrk_heap_end; - __sbrk_heap_end += incr; + prev_heap_end = __sbrk_heap_end; + __sbrk_heap_end += incr; - return (void *)prev_heap_end; + return (void *)prev_heap_end; } #if defined(__PICOLIBC__) - // Picolibc expects syscalls without the leading underscore. - // This creates a strong alias so that - // calls to `sbrk()` are resolved to our `_sbrk()` implementation. - __strong_reference(_sbrk, sbrk); +// Picolibc expects syscalls without the leading underscore. +// This creates a strong alias so that +// calls to `sbrk()` are resolved to our `_sbrk()` implementation. +__strong_reference(_sbrk, sbrk); #endif diff --git a/Testbench/NucleoG4-Blinky/Core/Src/system_stm32g4xx.c b/Testbench/NucleoG4-Blinky/Core/Src/system_stm32g4xx.c index 2cd914e7b..414c5339c 100644 --- a/Testbench/NucleoG4-Blinky/Core/Src/system_stm32g4xx.c +++ b/Testbench/NucleoG4-Blinky/Core/Src/system_stm32g4xx.c @@ -1,109 +1,109 @@ /** - ****************************************************************************** - * @file system_stm32g4xx.c - * @author MCD Application Team - * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File - * - * This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32g4xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * After each device reset the HSI (16 MHz) is used as system clock source. - * Then SystemInit() function is called, in "startup_stm32g4xx.s" file, to - * configure the system clock before to branch to main program. - * - * This file configures the system clock as follows: - *============================================================================= - *----------------------------------------------------------------------------- - * System Clock source | HSI - *----------------------------------------------------------------------------- - * SYSCLK(Hz) | 16000000 - *----------------------------------------------------------------------------- - * HCLK(Hz) | 16000000 - *----------------------------------------------------------------------------- - * AHB Prescaler | 1 - *----------------------------------------------------------------------------- - * APB1 Prescaler | 1 - *----------------------------------------------------------------------------- - * APB2 Prescaler | 1 - *----------------------------------------------------------------------------- - * PLL_M | 1 - *----------------------------------------------------------------------------- - * PLL_N | 16 - *----------------------------------------------------------------------------- - * PLL_P | 7 - *----------------------------------------------------------------------------- - * PLL_Q | 2 - *----------------------------------------------------------------------------- - * PLL_R | 2 - *----------------------------------------------------------------------------- - * Require 48MHz for RNG | Disabled - *----------------------------------------------------------------------------- - *============================================================================= - ****************************************************************************** - * @attention - * - * Copyright (c) 2019 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ + ****************************************************************************** + * @file system_stm32g4xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32g4xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32g4xx.s" file, to + * configure the system clock before to branch to main program. + * + * This file configures the system clock as follows: + *============================================================================= + *----------------------------------------------------------------------------- + * System Clock source | HSI + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 16000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 16000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 1 + *----------------------------------------------------------------------------- + * PLL_M | 1 + *----------------------------------------------------------------------------- + * PLL_N | 16 + *----------------------------------------------------------------------------- + * PLL_P | 7 + *----------------------------------------------------------------------------- + * PLL_Q | 2 + *----------------------------------------------------------------------------- + * PLL_R | 2 + *----------------------------------------------------------------------------- + * Require 48MHz for RNG | Disabled + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ /** @addtogroup CMSIS - * @{ - */ + * @{ + */ /** @addtogroup stm32g4xx_system - * @{ - */ + * @{ + */ /** @addtogroup STM32G4xx_System_Private_Includes - * @{ - */ + * @{ + */ #include "stm32g4xx.h" -#if !defined (HSE_VALUE) - #define HSE_VALUE 24000000U /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ +#if !defined(HSE_VALUE) +#define HSE_VALUE 24000000U /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ -#if !defined (HSI_VALUE) - #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ +#if !defined(HSI_VALUE) +#define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ /** - * @} - */ + * @} + */ /** @addtogroup STM32G4xx_System_Private_TypesDefinitions - * @{ - */ + * @{ + */ /** - * @} - */ + * @} + */ /** @addtogroup STM32G4xx_System_Private_Defines - * @{ - */ + * @{ + */ /************************* Miscellaneous Configuration ************************/ /* Note: Following vector table addresses must be defined in line with linker - configuration. */ + configuration. */ /*!< Uncomment the following line if you need to relocate the vector table anywhere in Flash or Sram, else the vector table is kept at the automatic remap of boot address selected */ @@ -114,174 +114,172 @@ in Sram else user remap will be done in Flash. */ /* #define VECT_TAB_SRAM */ #if defined(VECT_TAB_SRAM) -#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x200. */ +#define VECT_TAB_BASE_ADDRESS \ + SRAM_BASE /*!< Vector Table base address field. \ + This value must be a multiple of 0x200. */ #else -#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x200. */ -#endif /* VECT_TAB_SRAM */ +#define VECT_TAB_BASE_ADDRESS \ + FLASH_BASE /*!< Vector Table base address field. \ + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_SRAM */ #if !defined(VECT_TAB_OFFSET) -#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table offset field. - This value must be a multiple of 0x200. */ -#endif /* VECT_TAB_OFFSET */ +#define VECT_TAB_OFFSET \ + 0x00000000U /*!< Vector Table offset field. \ + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_OFFSET */ #endif /* USER_VECT_TAB_ADDRESS */ -/******************************************************************************/ -/** - * @} - */ + /******************************************************************************/ + /** + * @} + */ /** @addtogroup STM32G4xx_System_Private_Macros - * @{ - */ + * @{ + */ /** - * @} - */ + * @} + */ /** @addtogroup STM32G4xx_System_Private_Variables - * @{ - */ - /* The SystemCoreClock variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetHCLKFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ - uint32_t SystemCoreClock = HSI_VALUE; - - const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; - const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; + * @{ + */ +/* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. +*/ +uint32_t SystemCoreClock = HSI_VALUE; + +const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; +const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; /** - * @} - */ + * @} + */ /** @addtogroup STM32G4xx_System_Private_FunctionPrototypes - * @{ - */ + * @{ + */ /** - * @} - */ + * @} + */ /** @addtogroup STM32G4xx_System_Private_Functions - * @{ - */ + * @{ + */ /** - * @brief Setup the microcontroller system. - * @param None - * @retval None - */ + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ void SystemInit(void) { - /* FPU settings ------------------------------------------------------------*/ - #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ - #endif +/* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << (10 * 2)) | (3UL << (11 * 2))); /* set CP10 and CP11 Full Access */ +#endif - /* Configure the Vector Table location add offset address ------------------*/ + /* Configure the Vector Table location add offset address ------------------*/ #if defined(USER_VECT_TAB_ADDRESS) - SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#endif /* USER_VECT_TAB_ADDRESS */ + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ } /** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * - * (**) HSI_VALUE is a constant defined in stm32g4xx_hal.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (***) HSE_VALUE is a constant defined in stm32g4xx_hal.h file (default value - * 24 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param None - * @retval None - */ + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (**) HSI_VALUE is a constant defined in stm32g4xx_hal.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in stm32g4xx_hal.h file (default value + * 24 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ void SystemCoreClockUpdate(void) { - uint32_t tmp, pllvco, pllr, pllsource, pllm; - - /* Get SYSCLK source -------------------------------------------------------*/ - switch (RCC->CFGR & RCC_CFGR_SWS) - { - case 0x04: /* HSI used as system clock source */ - SystemCoreClock = HSI_VALUE; - break; - - case 0x08: /* HSE used as system clock source */ - SystemCoreClock = HSE_VALUE; - break; - - case 0x0C: /* PLL used as system clock source */ - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN - SYSCLK = PLL_VCO / PLLR - */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); - pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1U ; - if (pllsource == 0x02UL) /* HSI used as PLL clock source */ - { - pllvco = (HSI_VALUE / pllm); - } - else /* HSE used as PLL clock source */ - { - pllvco = (HSE_VALUE / pllm); - } - pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8); - pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U; - SystemCoreClock = pllvco/pllr; - break; - - default: - break; - } - /* Compute HCLK clock frequency --------------------------------------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK clock frequency */ - SystemCoreClock >>= tmp; + uint32_t tmp, pllvco, pllr, pllsource, pllm; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) { + case 0x04: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + + case 0x08: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + + case 0x0C: /* PLL used as system clock source */ + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); + pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1U; + if (pllsource == 0x02UL) /* HSI used as PLL clock source */ + { + pllvco = (HSI_VALUE / pllm); + } else /* HSE used as PLL clock source */ + { + pllvco = (HSE_VALUE / pllm); + } + pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8); + pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U; + SystemCoreClock = pllvco / pllr; + break; + + default: + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; } - /** - * @} - */ + * @} + */ /** - * @} - */ + * @} + */ /** - * @} - */ - - + * @} + */ From 5e80c3985a50653ae8ea646390dec6cda6eae11f Mon Sep 17 00:00:00 2001 From: github-actions <41898282+github-actions[bot]@users.noreply.github.com> Date: Sun, 23 Aug 2026 23:44:57 +0000 Subject: [PATCH 12/17] Automatic Assembly Format: Standardized formatting automatically --- .../NucleoG4-Blinky/startup_stm32g474xx.s | 676 +++++++++--------- 1 file changed, 340 insertions(+), 336 deletions(-) diff --git a/Testbench/NucleoG4-Blinky/startup_stm32g474xx.s b/Testbench/NucleoG4-Blinky/startup_stm32g474xx.s index e7a2c61fc..31cf98b7f 100644 --- a/Testbench/NucleoG4-Blinky/startup_stm32g474xx.s +++ b/Testbench/NucleoG4-Blinky/startup_stm32g474xx.s @@ -1,592 +1,596 @@ -/** - ****************************************************************************** - * @file startup_stm32g474xx.s - * @author MCD Application Team - * @brief STM32G474xx devices vector table GCC toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address, - * - Configure the clock system - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M4 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - * Copyright (c) 2019 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m4 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler +/* * + ****************************************************************************** + * @file startup_stm32g474xx.s + * @author MCD Application Team + * @brief STM32G474xx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +.syntax unified +.cpu cortex-m4 +.fpu softvfp +.thumb + +.global g_pfnVectors +.global Default_Handler /* start address for the initialization values of the .data section. defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss - -.equ BootRAM, 0xF1E0F85F -/** +.word _sidata + +// start address for the .data section. defined in linker script +.word _sdata + +// end address for the .data section. defined in linker script +.word _edata + +// start address for the .bss section. defined in linker script +.word _sbss + +// end address for the .bss section. defined in linker script +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/* * * @brief This is the code that gets called when the processor first * starts execution following a reset event. Only the absolutely * necessary set is performed, after which the application * supplied main() routine is called. * @param None * @retval : None -*/ + */ + +.section .text.Reset_Handler +.weak Reset_Handler +.type Reset_Handler, %function - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function Reset_Handler: - ldr r0, =_estack - mov sp, r0 /* set stack pointer */ + ldr r0, =_estack + mov sp, r0 // set stack pointer -/* Call the clock system initialization function.*/ - bl SystemInit + // Call the clock system initialization function. + bl SystemInit -/* Copy the data segment initializers from flash to SRAM */ - ldr r0, =_sdata - ldr r1, =_edata - ldr r2, =_sidata - movs r3, #0 - b LoopCopyDataInit + // Copy the data segment initializers from flash to SRAM + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit CopyDataInit: - ldr r4, [r2, r3] - str r4, [r0, r3] - adds r3, r3, #4 + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 LoopCopyDataInit: - adds r4, r0, r3 - cmp r4, r1 - bcc CopyDataInit - -/* Zero fill the bss segment. */ - ldr r2, =_sbss - ldr r4, =_ebss - movs r3, #0 - b LoopFillZerobss + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + + // Zero fill the bss segment. + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss FillZerobss: - str r3, [r2] - adds r2, r2, #4 + str r3, [r2] + adds r2, r2, #4 LoopFillZerobss: - cmp r2, r4 - bcc FillZerobss + cmp r2, r4 + bcc FillZerobss + + // Call static constructors + bl __libc_init_array -/* Call static constructors */ - bl __libc_init_array -/* Call the application's entry point.*/ - bl main + // Call the application's entry point. + bl main LoopForever: - b LoopForever + b LoopForever -.size Reset_Handler, .-Reset_Handler + .size Reset_Handler, .-Reset_Handler -/** +/* * * @brief This is the code that gets called when the processor receives an * unexpected interrupt. This simply enters an infinite loop, preserving * the system state for examination by a debugger. * * @param None * @retval : None -*/ - .section .text.Default_Handler,"ax",%progbits + */ + .section .text.Default_Handler, "ax", %progbits + Default_Handler: Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex-M4. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/* ***************************************************************************** + * + * The minimal vector table for a Cortex-M4. Note that the proper constructs + * must be placed on this to ensure that it ends up at physical address + * 0x0000.0000. + * +***************************************************************************** */ + .section .isr_vector, "a", %progbits + .type g_pfnVectors, %object g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler - .word PVD_PVM_IRQHandler - .word RTC_TAMP_LSECSS_IRQHandler - .word RTC_WKUP_IRQHandler - .word FLASH_IRQHandler - .word RCC_IRQHandler - .word EXTI0_IRQHandler - .word EXTI1_IRQHandler - .word EXTI2_IRQHandler - .word EXTI3_IRQHandler - .word EXTI4_IRQHandler - .word DMA1_Channel1_IRQHandler - .word DMA1_Channel2_IRQHandler - .word DMA1_Channel3_IRQHandler - .word DMA1_Channel4_IRQHandler - .word DMA1_Channel5_IRQHandler - .word DMA1_Channel6_IRQHandler - .word DMA1_Channel7_IRQHandler - .word ADC1_2_IRQHandler - .word USB_HP_IRQHandler - .word USB_LP_IRQHandler - .word FDCAN1_IT0_IRQHandler - .word FDCAN1_IT1_IRQHandler - .word EXTI9_5_IRQHandler - .word TIM1_BRK_TIM15_IRQHandler - .word TIM1_UP_TIM16_IRQHandler - .word TIM1_TRG_COM_TIM17_IRQHandler - .word TIM1_CC_IRQHandler - .word TIM2_IRQHandler - .word TIM3_IRQHandler - .word TIM4_IRQHandler - .word I2C1_EV_IRQHandler - .word I2C1_ER_IRQHandler - .word I2C2_EV_IRQHandler - .word I2C2_ER_IRQHandler - .word SPI1_IRQHandler - .word SPI2_IRQHandler - .word USART1_IRQHandler - .word USART2_IRQHandler - .word USART3_IRQHandler - .word EXTI15_10_IRQHandler - .word RTC_Alarm_IRQHandler - .word USBWakeUp_IRQHandler - .word TIM8_BRK_IRQHandler - .word TIM8_UP_IRQHandler - .word TIM8_TRG_COM_IRQHandler - .word TIM8_CC_IRQHandler - .word ADC3_IRQHandler - .word FMC_IRQHandler - .word LPTIM1_IRQHandler - .word TIM5_IRQHandler - .word SPI3_IRQHandler - .word UART4_IRQHandler - .word UART5_IRQHandler - .word TIM6_DAC_IRQHandler - .word TIM7_DAC_IRQHandler - .word DMA2_Channel1_IRQHandler - .word DMA2_Channel2_IRQHandler - .word DMA2_Channel3_IRQHandler - .word DMA2_Channel4_IRQHandler - .word DMA2_Channel5_IRQHandler - .word ADC4_IRQHandler - .word ADC5_IRQHandler - .word UCPD1_IRQHandler - .word COMP1_2_3_IRQHandler - .word COMP4_5_6_IRQHandler - .word COMP7_IRQHandler - .word HRTIM1_Master_IRQHandler - .word HRTIM1_TIMA_IRQHandler - .word HRTIM1_TIMB_IRQHandler - .word HRTIM1_TIMC_IRQHandler - .word HRTIM1_TIMD_IRQHandler - .word HRTIM1_TIME_IRQHandler - .word HRTIM1_FLT_IRQHandler - .word HRTIM1_TIMF_IRQHandler - .word CRS_IRQHandler - .word SAI1_IRQHandler - .word TIM20_BRK_IRQHandler - .word TIM20_UP_IRQHandler - .word TIM20_TRG_COM_IRQHandler - .word TIM20_CC_IRQHandler - .word FPU_IRQHandler - .word I2C4_EV_IRQHandler - .word I2C4_ER_IRQHandler - .word SPI4_IRQHandler - .word 0 - .word FDCAN2_IT0_IRQHandler - .word FDCAN2_IT1_IRQHandler - .word FDCAN3_IT0_IRQHandler - .word FDCAN3_IT1_IRQHandler - .word RNG_IRQHandler - .word LPUART1_IRQHandler - .word I2C3_EV_IRQHandler - .word I2C3_ER_IRQHandler - .word DMAMUX_OVR_IRQHandler - .word QUADSPI_IRQHandler - .word DMA1_Channel8_IRQHandler - .word DMA2_Channel6_IRQHandler - .word DMA2_Channel7_IRQHandler - .word DMA2_Channel8_IRQHandler - .word CORDIC_IRQHandler - .word FMAC_IRQHandler - - .size g_pfnVectors, .-g_pfnVectors - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - .weak NMI_Handler + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_PVM_IRQHandler + .word RTC_TAMP_LSECSS_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_IRQHandler + .word USB_LP_IRQHandler + .word FDCAN1_IT0_IRQHandler + .word FDCAN1_IT1_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word USBWakeUp_IRQHandler + .word TIM8_BRK_IRQHandler + .word TIM8_UP_IRQHandler + .word TIM8_TRG_COM_IRQHandler + .word TIM8_CC_IRQHandler + .word ADC3_IRQHandler + .word FMC_IRQHandler + .word LPTIM1_IRQHandler + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_DAC_IRQHandler + .word TIM7_DAC_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word ADC4_IRQHandler + .word ADC5_IRQHandler + .word UCPD1_IRQHandler + .word COMP1_2_3_IRQHandler + .word COMP4_5_6_IRQHandler + .word COMP7_IRQHandler + .word HRTIM1_Master_IRQHandler + .word HRTIM1_TIMA_IRQHandler + .word HRTIM1_TIMB_IRQHandler + .word HRTIM1_TIMC_IRQHandler + .word HRTIM1_TIMD_IRQHandler + .word HRTIM1_TIME_IRQHandler + .word HRTIM1_FLT_IRQHandler + .word HRTIM1_TIMF_IRQHandler + .word CRS_IRQHandler + .word SAI1_IRQHandler + .word TIM20_BRK_IRQHandler + .word TIM20_UP_IRQHandler + .word TIM20_TRG_COM_IRQHandler + .word TIM20_CC_IRQHandler + .word FPU_IRQHandler + .word I2C4_EV_IRQHandler + .word I2C4_ER_IRQHandler + .word SPI4_IRQHandler + .word 0 + .word FDCAN2_IT0_IRQHandler + .word FDCAN2_IT1_IRQHandler + .word FDCAN3_IT0_IRQHandler + .word FDCAN3_IT1_IRQHandler + .word RNG_IRQHandler + .word LPUART1_IRQHandler + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word DMAMUX_OVR_IRQHandler + .word QUADSPI_IRQHandler + .word DMA1_Channel8_IRQHandler + .word DMA2_Channel6_IRQHandler + .word DMA2_Channel7_IRQHandler + .word DMA2_Channel8_IRQHandler + .word CORDIC_IRQHandler + .word FMAC_IRQHandler + + .size g_pfnVectors, .-g_pfnVectors + +/* ****************************************************************************** + * + * Provide weak aliases for each Exception handler to the Default_Handler. + * As they are weak aliases, any function with the same name will override + * this definition. + * +****************************************************************************** */ + .weak NMI_Handler .thumb_set NMI_Handler,Default_Handler - .weak HardFault_Handler + .weak HardFault_Handler .thumb_set HardFault_Handler,Default_Handler - .weak MemManage_Handler + .weak MemManage_Handler .thumb_set MemManage_Handler,Default_Handler - .weak BusFault_Handler + .weak BusFault_Handler .thumb_set BusFault_Handler,Default_Handler - .weak UsageFault_Handler + .weak UsageFault_Handler .thumb_set UsageFault_Handler,Default_Handler - .weak SVC_Handler + .weak SVC_Handler .thumb_set SVC_Handler,Default_Handler - .weak DebugMon_Handler + .weak DebugMon_Handler .thumb_set DebugMon_Handler,Default_Handler - .weak PendSV_Handler + .weak PendSV_Handler .thumb_set PendSV_Handler,Default_Handler - .weak SysTick_Handler + .weak SysTick_Handler .thumb_set SysTick_Handler,Default_Handler - .weak WWDG_IRQHandler + .weak WWDG_IRQHandler .thumb_set WWDG_IRQHandler,Default_Handler - .weak PVD_PVM_IRQHandler + .weak PVD_PVM_IRQHandler .thumb_set PVD_PVM_IRQHandler,Default_Handler - .weak RTC_TAMP_LSECSS_IRQHandler + .weak RTC_TAMP_LSECSS_IRQHandler .thumb_set RTC_TAMP_LSECSS_IRQHandler,Default_Handler - .weak RTC_WKUP_IRQHandler + .weak RTC_WKUP_IRQHandler .thumb_set RTC_WKUP_IRQHandler,Default_Handler - .weak FLASH_IRQHandler + .weak FLASH_IRQHandler .thumb_set FLASH_IRQHandler,Default_Handler - .weak RCC_IRQHandler + .weak RCC_IRQHandler .thumb_set RCC_IRQHandler,Default_Handler - .weak EXTI0_IRQHandler + .weak EXTI0_IRQHandler .thumb_set EXTI0_IRQHandler,Default_Handler - .weak EXTI1_IRQHandler + .weak EXTI1_IRQHandler .thumb_set EXTI1_IRQHandler,Default_Handler - .weak EXTI2_IRQHandler + .weak EXTI2_IRQHandler .thumb_set EXTI2_IRQHandler,Default_Handler - .weak EXTI3_IRQHandler + .weak EXTI3_IRQHandler .thumb_set EXTI3_IRQHandler,Default_Handler - .weak EXTI4_IRQHandler + .weak EXTI4_IRQHandler .thumb_set EXTI4_IRQHandler,Default_Handler - .weak DMA1_Channel1_IRQHandler + .weak DMA1_Channel1_IRQHandler .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - .weak DMA1_Channel2_IRQHandler + .weak DMA1_Channel2_IRQHandler .thumb_set DMA1_Channel2_IRQHandler,Default_Handler - .weak DMA1_Channel3_IRQHandler + .weak DMA1_Channel3_IRQHandler .thumb_set DMA1_Channel3_IRQHandler,Default_Handler - .weak DMA1_Channel4_IRQHandler + .weak DMA1_Channel4_IRQHandler .thumb_set DMA1_Channel4_IRQHandler,Default_Handler - .weak DMA1_Channel5_IRQHandler + .weak DMA1_Channel5_IRQHandler .thumb_set DMA1_Channel5_IRQHandler,Default_Handler - .weak DMA1_Channel6_IRQHandler + .weak DMA1_Channel6_IRQHandler .thumb_set DMA1_Channel6_IRQHandler,Default_Handler - .weak DMA1_Channel7_IRQHandler + .weak DMA1_Channel7_IRQHandler .thumb_set DMA1_Channel7_IRQHandler,Default_Handler - .weak ADC1_2_IRQHandler + .weak ADC1_2_IRQHandler .thumb_set ADC1_2_IRQHandler,Default_Handler - .weak USB_HP_IRQHandler + .weak USB_HP_IRQHandler .thumb_set USB_HP_IRQHandler,Default_Handler - .weak USB_LP_IRQHandler + .weak USB_LP_IRQHandler .thumb_set USB_LP_IRQHandler,Default_Handler - .weak FDCAN1_IT0_IRQHandler + .weak FDCAN1_IT0_IRQHandler .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler - .weak FDCAN1_IT1_IRQHandler + .weak FDCAN1_IT1_IRQHandler .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler - .weak EXTI9_5_IRQHandler + .weak EXTI9_5_IRQHandler .thumb_set EXTI9_5_IRQHandler,Default_Handler - .weak TIM1_BRK_TIM15_IRQHandler + .weak TIM1_BRK_TIM15_IRQHandler .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler - .weak TIM1_UP_TIM16_IRQHandler + .weak TIM1_UP_TIM16_IRQHandler .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler - .weak TIM1_TRG_COM_TIM17_IRQHandler + .weak TIM1_TRG_COM_TIM17_IRQHandler .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler - .weak TIM1_CC_IRQHandler + .weak TIM1_CC_IRQHandler .thumb_set TIM1_CC_IRQHandler,Default_Handler - .weak TIM2_IRQHandler + .weak TIM2_IRQHandler .thumb_set TIM2_IRQHandler,Default_Handler - .weak TIM3_IRQHandler + .weak TIM3_IRQHandler .thumb_set TIM3_IRQHandler,Default_Handler - .weak TIM4_IRQHandler + .weak TIM4_IRQHandler .thumb_set TIM4_IRQHandler,Default_Handler - .weak I2C1_EV_IRQHandler + .weak I2C1_EV_IRQHandler .thumb_set I2C1_EV_IRQHandler,Default_Handler - .weak I2C1_ER_IRQHandler + .weak I2C1_ER_IRQHandler .thumb_set I2C1_ER_IRQHandler,Default_Handler - .weak I2C2_EV_IRQHandler + .weak I2C2_EV_IRQHandler .thumb_set I2C2_EV_IRQHandler,Default_Handler - .weak I2C2_ER_IRQHandler + .weak I2C2_ER_IRQHandler .thumb_set I2C2_ER_IRQHandler,Default_Handler - .weak SPI1_IRQHandler + .weak SPI1_IRQHandler .thumb_set SPI1_IRQHandler,Default_Handler - .weak SPI2_IRQHandler + .weak SPI2_IRQHandler .thumb_set SPI2_IRQHandler,Default_Handler - .weak USART1_IRQHandler + .weak USART1_IRQHandler .thumb_set USART1_IRQHandler,Default_Handler - .weak USART2_IRQHandler + .weak USART2_IRQHandler .thumb_set USART2_IRQHandler,Default_Handler - .weak USART3_IRQHandler + .weak USART3_IRQHandler .thumb_set USART3_IRQHandler,Default_Handler - .weak EXTI15_10_IRQHandler + .weak EXTI15_10_IRQHandler .thumb_set EXTI15_10_IRQHandler,Default_Handler - .weak RTC_Alarm_IRQHandler + .weak RTC_Alarm_IRQHandler .thumb_set RTC_Alarm_IRQHandler,Default_Handler - .weak USBWakeUp_IRQHandler + .weak USBWakeUp_IRQHandler .thumb_set USBWakeUp_IRQHandler,Default_Handler - .weak TIM8_BRK_IRQHandler + .weak TIM8_BRK_IRQHandler .thumb_set TIM8_BRK_IRQHandler,Default_Handler - .weak TIM8_UP_IRQHandler + .weak TIM8_UP_IRQHandler .thumb_set TIM8_UP_IRQHandler,Default_Handler - .weak TIM8_TRG_COM_IRQHandler + .weak TIM8_TRG_COM_IRQHandler .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler - .weak TIM8_CC_IRQHandler + .weak TIM8_CC_IRQHandler .thumb_set TIM8_CC_IRQHandler,Default_Handler - .weak ADC3_IRQHandler + .weak ADC3_IRQHandler .thumb_set ADC3_IRQHandler,Default_Handler - .weak FMC_IRQHandler + .weak FMC_IRQHandler .thumb_set FMC_IRQHandler,Default_Handler - .weak LPTIM1_IRQHandler + .weak LPTIM1_IRQHandler .thumb_set LPTIM1_IRQHandler,Default_Handler - .weak TIM5_IRQHandler + .weak TIM5_IRQHandler .thumb_set TIM5_IRQHandler,Default_Handler - .weak SPI3_IRQHandler + .weak SPI3_IRQHandler .thumb_set SPI3_IRQHandler,Default_Handler - .weak UART4_IRQHandler + .weak UART4_IRQHandler .thumb_set UART4_IRQHandler,Default_Handler - .weak UART5_IRQHandler + .weak UART5_IRQHandler .thumb_set UART5_IRQHandler,Default_Handler - .weak TIM6_DAC_IRQHandler + .weak TIM6_DAC_IRQHandler .thumb_set TIM6_DAC_IRQHandler,Default_Handler - .weak TIM7_DAC_IRQHandler + .weak TIM7_DAC_IRQHandler .thumb_set TIM7_DAC_IRQHandler,Default_Handler - .weak DMA2_Channel1_IRQHandler + .weak DMA2_Channel1_IRQHandler .thumb_set DMA2_Channel1_IRQHandler,Default_Handler - .weak DMA2_Channel2_IRQHandler + .weak DMA2_Channel2_IRQHandler .thumb_set DMA2_Channel2_IRQHandler,Default_Handler - .weak DMA2_Channel3_IRQHandler + .weak DMA2_Channel3_IRQHandler .thumb_set DMA2_Channel3_IRQHandler,Default_Handler - .weak DMA2_Channel4_IRQHandler + .weak DMA2_Channel4_IRQHandler .thumb_set DMA2_Channel4_IRQHandler,Default_Handler - .weak DMA2_Channel5_IRQHandler + .weak DMA2_Channel5_IRQHandler .thumb_set DMA2_Channel5_IRQHandler,Default_Handler - .weak ADC4_IRQHandler + .weak ADC4_IRQHandler .thumb_set ADC4_IRQHandler,Default_Handler - .weak ADC5_IRQHandler + .weak ADC5_IRQHandler .thumb_set ADC5_IRQHandler,Default_Handler - .weak UCPD1_IRQHandler + .weak UCPD1_IRQHandler .thumb_set UCPD1_IRQHandler,Default_Handler - .weak COMP1_2_3_IRQHandler + .weak COMP1_2_3_IRQHandler .thumb_set COMP1_2_3_IRQHandler,Default_Handler - .weak COMP4_5_6_IRQHandler + .weak COMP4_5_6_IRQHandler .thumb_set COMP4_5_6_IRQHandler,Default_Handler - .weak COMP7_IRQHandler + .weak COMP7_IRQHandler .thumb_set COMP7_IRQHandler,Default_Handler - .weak HRTIM1_Master_IRQHandler + .weak HRTIM1_Master_IRQHandler .thumb_set HRTIM1_Master_IRQHandler,Default_Handler - .weak HRTIM1_TIMA_IRQHandler + .weak HRTIM1_TIMA_IRQHandler .thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler - .weak HRTIM1_TIMB_IRQHandler + .weak HRTIM1_TIMB_IRQHandler .thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler - .weak HRTIM1_TIMC_IRQHandler + .weak HRTIM1_TIMC_IRQHandler .thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler - .weak HRTIM1_TIMD_IRQHandler + .weak HRTIM1_TIMD_IRQHandler .thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler - .weak HRTIM1_TIME_IRQHandler + .weak HRTIM1_TIME_IRQHandler .thumb_set HRTIM1_TIME_IRQHandler,Default_Handler - .weak HRTIM1_FLT_IRQHandler + .weak HRTIM1_FLT_IRQHandler .thumb_set HRTIM1_FLT_IRQHandler,Default_Handler - .weak HRTIM1_TIMF_IRQHandler + .weak HRTIM1_TIMF_IRQHandler .thumb_set HRTIM1_TIMF_IRQHandler,Default_Handler - .weak CRS_IRQHandler + .weak CRS_IRQHandler .thumb_set CRS_IRQHandler,Default_Handler - .weak SAI1_IRQHandler + .weak SAI1_IRQHandler .thumb_set SAI1_IRQHandler,Default_Handler - .weak TIM20_BRK_IRQHandler + .weak TIM20_BRK_IRQHandler .thumb_set TIM20_BRK_IRQHandler,Default_Handler - .weak TIM20_UP_IRQHandler + .weak TIM20_UP_IRQHandler .thumb_set TIM20_UP_IRQHandler,Default_Handler - .weak TIM20_TRG_COM_IRQHandler + .weak TIM20_TRG_COM_IRQHandler .thumb_set TIM20_TRG_COM_IRQHandler,Default_Handler - .weak TIM20_CC_IRQHandler + .weak TIM20_CC_IRQHandler .thumb_set TIM20_CC_IRQHandler,Default_Handler - .weak FPU_IRQHandler + .weak FPU_IRQHandler .thumb_set FPU_IRQHandler,Default_Handler - .weak I2C4_EV_IRQHandler + .weak I2C4_EV_IRQHandler .thumb_set I2C4_EV_IRQHandler,Default_Handler - .weak I2C4_ER_IRQHandler + .weak I2C4_ER_IRQHandler .thumb_set I2C4_ER_IRQHandler,Default_Handler - .weak SPI4_IRQHandler + .weak SPI4_IRQHandler .thumb_set SPI4_IRQHandler,Default_Handler - .weak FDCAN2_IT0_IRQHandler + .weak FDCAN2_IT0_IRQHandler .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler - .weak FDCAN2_IT1_IRQHandler + .weak FDCAN2_IT1_IRQHandler .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler - .weak FDCAN3_IT0_IRQHandler + .weak FDCAN3_IT0_IRQHandler .thumb_set FDCAN3_IT0_IRQHandler,Default_Handler - .weak FDCAN3_IT1_IRQHandler + .weak FDCAN3_IT1_IRQHandler .thumb_set FDCAN3_IT1_IRQHandler,Default_Handler - .weak RNG_IRQHandler + .weak RNG_IRQHandler .thumb_set RNG_IRQHandler,Default_Handler - .weak LPUART1_IRQHandler + .weak LPUART1_IRQHandler .thumb_set LPUART1_IRQHandler,Default_Handler - .weak I2C3_EV_IRQHandler + .weak I2C3_EV_IRQHandler .thumb_set I2C3_EV_IRQHandler,Default_Handler - .weak I2C3_ER_IRQHandler + .weak I2C3_ER_IRQHandler .thumb_set I2C3_ER_IRQHandler,Default_Handler - .weak DMAMUX_OVR_IRQHandler + .weak DMAMUX_OVR_IRQHandler .thumb_set DMAMUX_OVR_IRQHandler,Default_Handler - .weak QUADSPI_IRQHandler + .weak QUADSPI_IRQHandler .thumb_set QUADSPI_IRQHandler,Default_Handler - .weak DMA1_Channel8_IRQHandler + .weak DMA1_Channel8_IRQHandler .thumb_set DMA1_Channel8_IRQHandler,Default_Handler - .weak DMA2_Channel6_IRQHandler + .weak DMA2_Channel6_IRQHandler .thumb_set DMA2_Channel6_IRQHandler,Default_Handler - .weak DMA2_Channel7_IRQHandler + .weak DMA2_Channel7_IRQHandler .thumb_set DMA2_Channel7_IRQHandler,Default_Handler - .weak DMA2_Channel8_IRQHandler + .weak DMA2_Channel8_IRQHandler .thumb_set DMA2_Channel8_IRQHandler,Default_Handler - .weak CORDIC_IRQHandler + .weak CORDIC_IRQHandler .thumb_set CORDIC_IRQHandler,Default_Handler - .weak FMAC_IRQHandler + .weak FMAC_IRQHandler .thumb_set FMAC_IRQHandler,Default_Handler From b026fe8f4046e95fbcd83022a652dcdd1a17c792 Mon Sep 17 00:00:00 2001 From: Daniel Hansen Date: Sun, 23 Aug 2026 16:49:49 -0700 Subject: [PATCH 13/17] Add G4Hello (format) Signed-off-by: Daniel Hansen --- .../NucleoG4-Hello/Application/Inc/hello.h | 0 .../NucleoG4-Hello/Application/Src/hello.c | 19 + Testbench/NucleoG4-Hello/CMakeLists.txt | 46 ++ Testbench/NucleoG4-Hello/Core/Inc/gpio.h | 49 ++ Testbench/NucleoG4-Hello/Core/Inc/main.h | 71 +++ .../NucleoG4-Hello/Core/Inc/stm32_assert.h | 52 ++ .../Core/Inc/stm32g4xx_hal_conf.h | 380 +++++++++++ .../NucleoG4-Hello/Core/Inc/stm32g4xx_it.h | 66 ++ Testbench/NucleoG4-Hello/Core/Src/gpio.c | 125 ++++ Testbench/NucleoG4-Hello/Core/Src/main.c | 183 ++++++ .../Core/Src/stm32g4xx_hal_msp.c | 85 +++ .../NucleoG4-Hello/Core/Src/stm32g4xx_it.c | 203 ++++++ Testbench/NucleoG4-Hello/Core/Src/syscalls.c | 244 ++++++++ Testbench/NucleoG4-Hello/Core/Src/sysmem.c | 87 +++ .../Core/Src/system_stm32g4xx.c | 287 +++++++++ Testbench/NucleoG4-Hello/NucleoG4-Hello.ioc | 135 ++++ Testbench/NucleoG4-Hello/STM32G474xx_FLASH.ld | 250 ++++++++ .../NucleoG4-Hello/startup_stm32g474xx.s | 592 ++++++++++++++++++ Testbench/testbench.cmake | 10 + 19 files changed, 2884 insertions(+) create mode 100644 Testbench/NucleoG4-Hello/Application/Inc/hello.h create mode 100644 Testbench/NucleoG4-Hello/Application/Src/hello.c create mode 100644 Testbench/NucleoG4-Hello/CMakeLists.txt create mode 100644 Testbench/NucleoG4-Hello/Core/Inc/gpio.h create mode 100644 Testbench/NucleoG4-Hello/Core/Inc/main.h create mode 100644 Testbench/NucleoG4-Hello/Core/Inc/stm32_assert.h create mode 100644 Testbench/NucleoG4-Hello/Core/Inc/stm32g4xx_hal_conf.h create mode 100644 Testbench/NucleoG4-Hello/Core/Inc/stm32g4xx_it.h create mode 100644 Testbench/NucleoG4-Hello/Core/Src/gpio.c create mode 100644 Testbench/NucleoG4-Hello/Core/Src/main.c create mode 100644 Testbench/NucleoG4-Hello/Core/Src/stm32g4xx_hal_msp.c create mode 100644 Testbench/NucleoG4-Hello/Core/Src/stm32g4xx_it.c create mode 100644 Testbench/NucleoG4-Hello/Core/Src/syscalls.c create mode 100644 Testbench/NucleoG4-Hello/Core/Src/sysmem.c create mode 100644 Testbench/NucleoG4-Hello/Core/Src/system_stm32g4xx.c create mode 100644 Testbench/NucleoG4-Hello/NucleoG4-Hello.ioc create mode 100644 Testbench/NucleoG4-Hello/STM32G474xx_FLASH.ld create mode 100644 Testbench/NucleoG4-Hello/startup_stm32g474xx.s diff --git a/Testbench/NucleoG4-Hello/Application/Inc/hello.h b/Testbench/NucleoG4-Hello/Application/Inc/hello.h new file mode 100644 index 000000000..e69de29bb diff --git a/Testbench/NucleoG4-Hello/Application/Src/hello.c b/Testbench/NucleoG4-Hello/Application/Src/hello.c new file mode 100644 index 000000000..837639fcd --- /dev/null +++ b/Testbench/NucleoG4-Hello/Application/Src/hello.c @@ -0,0 +1,19 @@ +#include "hello.h" + +#include + +#include "main.h" +#include "Logomatic.h" + +HAL_StatusTypeDef say_hello(uint8_t count) +{ + if (count == 0) { + return HAL_ERROR; + } + + for (uint8_t i = 0; i < count; i++) { + LOGOMATIC_INFO("Hello, World!\n"); + HAL_Delay(1000); + } + return HAL_OK; +} diff --git a/Testbench/NucleoG4-Hello/CMakeLists.txt b/Testbench/NucleoG4-Hello/CMakeLists.txt new file mode 100644 index 000000000..a372d6963 --- /dev/null +++ b/Testbench/NucleoG4-Hello/CMakeLists.txt @@ -0,0 +1,46 @@ +#[[ +Required components (orderless) +- Link options for the GCC linker script +- Compile definitions for the chip subfamily +- Includes for the project +- Sources for the project +- Additional link libraries for the project +]] + +target_link_options( + ${TARGET_NAME} + PRIVATE + -T "${CMAKE_CURRENT_SOURCE_DIR}/STM32G474xx_FLASH.ld" +) + +target_compile_definitions( + ${TARGET_NAME} + PRIVATE + STM32G474xx +) + +target_include_directories( + ${TARGET_NAME} + PRIVATE + Core/Inc + Application/Inc +) + +target_sources( + ${TARGET_NAME} + PRIVATE + Application/Src/hello.c + Core/Src/gpio.c + Core/Src/main.c + Core/Src/stm32g4xx_it.c + Core/Src/syscalls.c + Core/Src/sysmem.c + Core/Src/system_stm32g4xx.c + startup_stm32g474xx.s +) + +target_link_libraries( + ${TARGET_NAME} + PRIVATE + LOGOMATIC_LIB +) diff --git a/Testbench/NucleoG4-Hello/Core/Inc/gpio.h b/Testbench/NucleoG4-Hello/Core/Inc/gpio.h new file mode 100644 index 000000000..3c91c4dd6 --- /dev/null +++ b/Testbench/NucleoG4-Hello/Core/Inc/gpio.h @@ -0,0 +1,49 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file gpio.h + * @brief This file contains all the function prototypes for + * the gpio.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __GPIO_H__ +#define __GPIO_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_GPIO_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif +#endif /*__ GPIO_H__ */ + diff --git a/Testbench/NucleoG4-Hello/Core/Inc/main.h b/Testbench/NucleoG4-Hello/Core/Inc/main.h new file mode 100644 index 000000000..e2752149c --- /dev/null +++ b/Testbench/NucleoG4-Hello/Core/Inc/main.h @@ -0,0 +1,71 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g4xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +#define USER_LED_Pin GPIO_PIN_5 +#define USER_LED_GPIO_Port GPIOA + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ diff --git a/Testbench/NucleoG4-Hello/Core/Inc/stm32_assert.h b/Testbench/NucleoG4-Hello/Core/Inc/stm32_assert.h new file mode 100644 index 000000000..92460620f --- /dev/null +++ b/Testbench/NucleoG4-Hello/Core/Inc/stm32_assert.h @@ -0,0 +1,52 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32_assert.h + * @author MCD Application Team + * @brief STM32 assert file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_ASSERT_H +#define __STM32_ASSERT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Includes ------------------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ +void assert_failed(uint8_t *file, uint32_t line); +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_ASSERT_H */ diff --git a/Testbench/NucleoG4-Hello/Core/Inc/stm32g4xx_hal_conf.h b/Testbench/NucleoG4-Hello/Core/Inc/stm32g4xx_hal_conf.h new file mode 100644 index 000000000..90adf393c --- /dev/null +++ b/Testbench/NucleoG4-Hello/Core/Inc/stm32g4xx_hal_conf.h @@ -0,0 +1,380 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32g4xx_hal_conf.h + * @author MCD Application Team + * @brief HAL configuration file + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G4xx_HAL_CONF_H +#define STM32G4xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ + +#define HAL_MODULE_ENABLED + + /*#define HAL_ADC_MODULE_ENABLED */ +/*#define HAL_COMP_MODULE_ENABLED */ +/*#define HAL_CORDIC_MODULE_ENABLED */ +/*#define HAL_CRC_MODULE_ENABLED */ +/*#define HAL_CRYP_MODULE_ENABLED */ +/*#define HAL_DAC_MODULE_ENABLED */ +/*#define HAL_FDCAN_MODULE_ENABLED */ +/*#define HAL_FMAC_MODULE_ENABLED */ +/*#define HAL_HRTIM_MODULE_ENABLED */ +/*#define HAL_IRDA_MODULE_ENABLED */ +/*#define HAL_IWDG_MODULE_ENABLED */ +/*#define HAL_I2C_MODULE_ENABLED */ +/*#define HAL_I2S_MODULE_ENABLED */ +/*#define HAL_LPTIM_MODULE_ENABLED */ +/*#define HAL_NAND_MODULE_ENABLED */ +/*#define HAL_NOR_MODULE_ENABLED */ +/*#define HAL_OPAMP_MODULE_ENABLED */ +/*#define HAL_PCD_MODULE_ENABLED */ +/*#define HAL_QSPI_MODULE_ENABLED */ +/*#define HAL_RNG_MODULE_ENABLED */ +/*#define HAL_RTC_MODULE_ENABLED */ +/*#define HAL_SAI_MODULE_ENABLED */ +/*#define HAL_SMARTCARD_MODULE_ENABLED */ +/*#define HAL_SMBUS_MODULE_ENABLED */ +/*#define HAL_SPI_MODULE_ENABLED */ +/*#define HAL_SRAM_MODULE_ENABLED */ +/*#define HAL_TIM_MODULE_ENABLED */ +/*#define HAL_UART_MODULE_ENABLED */ +/*#define HAL_USART_MODULE_ENABLED */ +/*#define HAL_WWDG_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## Register Callbacks selection ############################## */ +/** + * @brief This is the list of modules where register callback can be used + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U +#define USE_HAL_COMP_REGISTER_CALLBACKS 0U +#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U +#define USE_HAL_EXTI_REGISTER_CALLBACKS 0U +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U +#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U +#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U +#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U +#define USE_HAL_UART_REGISTER_CALLBACKS 0U +#define USE_HAL_USART_REGISTER_CALLBACKS 0U +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI48) value for USB FS and RNG. + * This internal oscillator is mainly dedicated to provide a high precision clock to + * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. + * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency + * which is subject to manufacturing process variations. + */ +#if !defined (HSI48_VALUE) + #define HSI48_VALUE (48000000UL) /*!< Value of the Internal High Speed oscillator for USB FS/RNG in Hz. + The real value my vary depending on manufacturing process variations.*/ +#endif /* HSI48_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) +/*!< Value of the Internal Low Speed oscillator in Hz +The real value may vary depending on the variations in voltage and temperature.*/ +#define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) +#define LSE_VALUE (32768UL) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S and SAI peripherals + * This value is used by the I2S and SAI HAL modules to compute the I2S and SAI clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) +#define EXTERNAL_CLOCK_VALUE (12288000UL) /*!< Value of the External oscillator in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ + +#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority (lowest by default) */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 0U +#define INSTRUCTION_CACHE_ENABLE 1U +#define DATA_CACHE_ENABLE 1U + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ + #define USE_FULL_ASSERT 1U + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver + * Activated: CRC code is present inside driver + * Deactivated: CRC code cleaned from driver + */ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED +#include "stm32g4xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED +#include "stm32g4xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED +#include "stm32g4xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED +#include "stm32g4xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED +#include "stm32g4xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED +#include "stm32g4xx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CORDIC_MODULE_ENABLED +#include "stm32g4xx_hal_cordic.h" +#endif /* HAL_CORDIC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED +#include "stm32g4xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED +#include "stm32g4xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED +#include "stm32g4xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED +#include "stm32g4xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_FDCAN_MODULE_ENABLED +#include "stm32g4xx_hal_fdcan.h" +#endif /* HAL_FDCAN_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED +#include "stm32g4xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_FMAC_MODULE_ENABLED +#include "stm32g4xx_hal_fmac.h" +#endif /* HAL_FMAC_MODULE_ENABLED */ + +#ifdef HAL_HRTIM_MODULE_ENABLED +#include "stm32g4xx_hal_hrtim.h" +#endif /* HAL_HRTIM_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED +#include "stm32g4xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED +#include "stm32g4xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED +#include "stm32g4xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED +#include "stm32g4xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED +#include "stm32g4xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED +#include "stm32g4xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED +#include "stm32g4xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_OPAMP_MODULE_ENABLED +#include "stm32g4xx_hal_opamp.h" +#endif /* HAL_OPAMP_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED +#include "stm32g4xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED +#include "stm32g4xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED +#include "stm32g4xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED +#include "stm32g4xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED +#include "stm32g4xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED +#include "stm32g4xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED +#include "stm32g4xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED +#include "stm32g4xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED +#include "stm32g4xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED +#include "stm32g4xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED +#include "stm32g4xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED +#include "stm32g4xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED +#include "stm32g4xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED +#include "stm32g4xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ +void assert_failed(uint8_t *file, uint32_t line); +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G4xx_HAL_CONF_H */ diff --git a/Testbench/NucleoG4-Hello/Core/Inc/stm32g4xx_it.h b/Testbench/NucleoG4-Hello/Core/Inc/stm32g4xx_it.h new file mode 100644 index 000000000..1a144ad22 --- /dev/null +++ b/Testbench/NucleoG4-Hello/Core/Inc/stm32g4xx_it.h @@ -0,0 +1,66 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32g4xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32G4xx_IT_H +#define __STM32G4xx_IT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32G4xx_IT_H */ diff --git a/Testbench/NucleoG4-Hello/Core/Src/gpio.c b/Testbench/NucleoG4-Hello/Core/Src/gpio.c new file mode 100644 index 000000000..252155711 --- /dev/null +++ b/Testbench/NucleoG4-Hello/Core/Src/gpio.c @@ -0,0 +1,125 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file gpio.c + * @brief This file provides code for the configuration + * of all used GPIO pins. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "gpio.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/*----------------------------------------------------------------------------*/ +/* Configure GPIO */ +/*----------------------------------------------------------------------------*/ +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/** Configure pins as + * Analog + * Input + * Output + * EVENT_OUT + * EXTI + * Free pins are configured automatically as Analog (this feature is enabled through + * the Code Generation settings) +*/ +void MX_GPIO_Init(void) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(USER_LED_GPIO_Port, USER_LED_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pins : PC13 PC14 PC15 PC0 + PC1 PC2 PC3 PC4 + PC5 PC6 PC7 PC8 + PC9 PC10 PC11 PC12 */ + GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15|GPIO_PIN_0 + |GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4 + |GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8 + |GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /*Configure GPIO pins : PF0 PF1 */ + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + /*Configure GPIO pin : PG10 */ + GPIO_InitStruct.Pin = GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + /*Configure GPIO pins : PA0 PA1 PA2 PA3 + PA4 PA6 PA7 PA8 + PA9 PA10 PA11 PA12 + PA15 */ + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8 + |GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12 + |GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /*Configure GPIO pin : USER_LED_Pin */ + GPIO_InitStruct.Pin = USER_LED_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(USER_LED_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pins : PB0 PB1 PB2 PB10 + PB11 PB12 PB13 PB14 + PB15 PB4 PB5 PB6 + PB7 PB8 PB9 */ + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_10 + |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 + |GPIO_PIN_15|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6 + |GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /*Configure GPIO pin : PD2 */ + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + +} + +/* USER CODE BEGIN 2 */ + +/* USER CODE END 2 */ diff --git a/Testbench/NucleoG4-Hello/Core/Src/main.c b/Testbench/NucleoG4-Hello/Core/Src/main.c new file mode 100644 index 000000000..074f2482f --- /dev/null +++ b/Testbench/NucleoG4-Hello/Core/Src/main.c @@ -0,0 +1,183 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "gpio.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + /* USER CODE BEGIN 2 */ + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /** Configure the main internal regulator output voltage + */ + HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST); + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1; + RCC_OscInitStruct.PLL.PLLN = 20; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; + RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) + { + Error_Handler(); + } +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ +} +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + UNUSED(file); + UNUSED(line); + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/Testbench/NucleoG4-Hello/Core/Src/stm32g4xx_hal_msp.c b/Testbench/NucleoG4-Hello/Core/Src/stm32g4xx_hal_msp.c new file mode 100644 index 000000000..d908bd772 --- /dev/null +++ b/Testbench/NucleoG4-Hello/Core/Src/stm32g4xx_hal_msp.c @@ -0,0 +1,85 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32g4xx_hal_msp.c + * @brief This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); + + /* System interrupt init*/ + + /** Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral + */ + HAL_PWREx_DisableUCPDDeadBattery(); + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/Testbench/NucleoG4-Hello/Core/Src/stm32g4xx_it.c b/Testbench/NucleoG4-Hello/Core/Src/stm32g4xx_it.c new file mode 100644 index 000000000..13e0f0c20 --- /dev/null +++ b/Testbench/NucleoG4-Hello/Core/Src/stm32g4xx_it.c @@ -0,0 +1,203 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32g4xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32g4xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ + +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M4 Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + { + } + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Prefetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn 0 */ + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32G4xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32g4xx.s). */ +/******************************************************************************/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/Testbench/NucleoG4-Hello/Core/Src/syscalls.c b/Testbench/NucleoG4-Hello/Core/Src/syscalls.c new file mode 100644 index 000000000..e10d76fa2 --- /dev/null +++ b/Testbench/NucleoG4-Hello/Core/Src/syscalls.c @@ -0,0 +1,244 @@ +/** + ****************************************************************************** + * @file syscalls.c + * @author Auto-generated by STM32CubeMX + * @brief Minimal System calls file + * + * For more information about which c-functions + * need which of these lowlevel functions + * please consult the Newlib or Picolibc libc-manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2020-2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include +#include +#include +#include +#include +#include +#include + + +/* Variables */ +extern int __io_putchar(int ch) __attribute__((weak)); +extern int __io_getchar(void) __attribute__((weak)); + + +char *__env[1] = { 0 }; +char **environ = __env; + + +/* Functions */ +void initialise_monitor_handles() +{ +} + +int _getpid(void) +{ + return 1; +} + +int _kill(int pid, int sig) +{ + (void)pid; + (void)sig; + errno = EINVAL; + return -1; +} + +void _exit (int status) +{ + _kill(status, -1); + while (1) {} /* Make sure we hang here */ +} + +__attribute__((weak)) int _read(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + *ptr++ = __io_getchar(); + } + + return len; +} + +__attribute__((weak)) int _write(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + __io_putchar(*ptr++); + } + return len; +} + +int _close(int file) +{ + (void)file; + return -1; +} + + +int _fstat(int file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _isatty(int file) +{ + (void)file; + return 1; +} + +int _lseek(int file, int ptr, int dir) +{ + (void)file; + (void)ptr; + (void)dir; + return 0; +} + +int _open(char *path, int flags, ...) +{ + (void)path; + (void)flags; + /* Pretend like we always fail */ + return -1; +} + +int _wait(int *status) +{ + (void)status; + errno = ECHILD; + return -1; +} + +int _unlink(char *name) +{ + (void)name; + errno = ENOENT; + return -1; +} + +clock_t _times(struct tms *buf) +{ + (void)buf; + return -1; +} + +int _stat(const char *file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _link(char *old, char *new) +{ + (void)old; + (void)new; + errno = EMLINK; + return -1; +} + +int _fork(void) +{ + errno = EAGAIN; + return -1; +} + +int _execve(char *name, char **argv, char **env) +{ + (void)name; + (void)argv; + (void)env; + errno = ENOMEM; + return -1; +} + +// --- Picolibc Specific Section --- +#if defined(__PICOLIBC__) + +/** + * @brief Picolibc helper function to output a character to a FILE stream. + * This redirects the output to the low-level __io_putchar function. + * @param c Character to write. + * @param file FILE stream pointer (ignored). + * @retval int The character written. + */ +static int starm_putc(char c, FILE *file) +{ + (void) file; + __io_putchar(c); + return c; +} + +/** + * @brief Picolibc helper function to input a character from a FILE stream. + * This redirects the input from the low-level __io_getchar function. + * @param file FILE stream pointer (ignored). + * @retval int The character read, cast to an unsigned char then int. + */ +static int starm_getc(FILE *file) +{ + unsigned char c; + (void) file; + c = __io_getchar(); + return c; +} + +// Define and initialize the standard I/O streams for Picolibc. +// FDEV_SETUP_STREAM connects the starm_putc and starm_getc helper functions to a FILE structure. +// _FDEV_SETUP_RW indicates the stream is for reading and writing. +static FILE __stdio = FDEV_SETUP_STREAM(starm_putc, + starm_getc, + NULL, + _FDEV_SETUP_RW); + +// Assign the standard stream pointers (stdin, stdout, stderr) to the initialized stream. +// Picolibc uses these pointers for standard I/O operations (printf, scanf, etc.). +FILE *const stdin = &__stdio; +__strong_reference(stdin, stdout); +__strong_reference(stdin, stderr); + +// Create strong aliases mapping standard C library function names (without underscore) +// to the implemented system call stubs (with underscore). Picolibc uses these +// standard names internally, so this linking is required. +__strong_reference(_read, read); +__strong_reference(_write, write); +__strong_reference(_times, times); +__strong_reference(_execve, execve); +__strong_reference(_fork, fork); +__strong_reference(_link, link); +__strong_reference(_unlink, unlink); +__strong_reference(_stat, stat); +__strong_reference(_wait, wait); +__strong_reference(_open, open); +__strong_reference(_close, close); +__strong_reference(_lseek, lseek); +__strong_reference(_isatty, isatty); +__strong_reference(_fstat, fstat); +__strong_reference(_exit, exit); +__strong_reference(_kill, kill); +__strong_reference(_getpid, getpid); + +#endif //__PICOLIBC__ diff --git a/Testbench/NucleoG4-Hello/Core/Src/sysmem.c b/Testbench/NucleoG4-Hello/Core/Src/sysmem.c new file mode 100644 index 000000000..a875d42c0 --- /dev/null +++ b/Testbench/NucleoG4-Hello/Core/Src/sysmem.c @@ -0,0 +1,87 @@ +/** + ****************************************************************************** + * @file sysmem.c + * @author Generated by STM32CubeMX + * @brief System Memory calls file + * + * For more information about which C functions + * need which of these lowlevel functions + * please consult the Newlib or Picolibc libc manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include +#include + +/** + * Pointer to the current high watermark of the heap usage + */ +static uint8_t *__sbrk_heap_end = NULL; + +/** + * @brief _sbrk() allocates memory to the newlib heap and is used by malloc + * and others from the C library + * + * @verbatim + * ############################################################################ + * # .data # .bss # newlib heap # MSP stack # + * # # # # Reserved by _Min_Stack_Size # + * ############################################################################ + * ^-- RAM start ^-- _end _estack, RAM end --^ + * @endverbatim + * + * This implementation starts allocating at the '_end' linker symbol + * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack + * The implementation considers '_estack' linker symbol to be RAM end + * NOTE: If the MSP stack, at any point during execution, grows larger than the + * reserved size, please increase the '_Min_Stack_Size'. + * + * @param incr Memory size + * @return Pointer to allocated memory + */ +void *_sbrk(ptrdiff_t incr) +{ + extern uint8_t _end; /* Symbol defined in the linker script */ + extern uint8_t _estack; /* Symbol defined in the linker script */ + extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + const uint8_t *max_heap = (uint8_t *)stack_limit; + uint8_t *prev_heap_end; + + /* Initialize heap end at first call */ + if (NULL == __sbrk_heap_end) + { + __sbrk_heap_end = &_end; + } + + /* Protect heap from growing into the reserved MSP stack */ + if (__sbrk_heap_end + incr > max_heap) + { + errno = ENOMEM; + return (void *)-1; + } + + prev_heap_end = __sbrk_heap_end; + __sbrk_heap_end += incr; + + return (void *)prev_heap_end; +} + +#if defined(__PICOLIBC__) + // Picolibc expects syscalls without the leading underscore. + // This creates a strong alias so that + // calls to `sbrk()` are resolved to our `_sbrk()` implementation. + __strong_reference(_sbrk, sbrk); +#endif diff --git a/Testbench/NucleoG4-Hello/Core/Src/system_stm32g4xx.c b/Testbench/NucleoG4-Hello/Core/Src/system_stm32g4xx.c new file mode 100644 index 000000000..2cd914e7b --- /dev/null +++ b/Testbench/NucleoG4-Hello/Core/Src/system_stm32g4xx.c @@ -0,0 +1,287 @@ +/** + ****************************************************************************** + * @file system_stm32g4xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32g4xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32g4xx.s" file, to + * configure the system clock before to branch to main program. + * + * This file configures the system clock as follows: + *============================================================================= + *----------------------------------------------------------------------------- + * System Clock source | HSI + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 16000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 16000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 1 + *----------------------------------------------------------------------------- + * PLL_M | 1 + *----------------------------------------------------------------------------- + * PLL_N | 16 + *----------------------------------------------------------------------------- + * PLL_P | 7 + *----------------------------------------------------------------------------- + * PLL_Q | 2 + *----------------------------------------------------------------------------- + * PLL_R | 2 + *----------------------------------------------------------------------------- + * Require 48MHz for RNG | Disabled + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32g4xx_system + * @{ + */ + +/** @addtogroup STM32G4xx_System_Private_Includes + * @{ + */ + +#include "stm32g4xx.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE 24000000U /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32G4xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32G4xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in Flash or Sram, else the vector table is kept at the automatic + remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +/*!< Uncomment the following line if you need to relocate your vector Table + in Sram else user remap will be done in Flash. */ +/* #define VECT_TAB_SRAM */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_SRAM */ + +#if !defined(VECT_TAB_OFFSET) +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_OFFSET */ + +#endif /* USER_VECT_TAB_ADDRESS */ +/******************************************************************************/ +/** + * @} + */ + +/** @addtogroup STM32G4xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32G4xx_System_Private_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = HSI_VALUE; + + const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; + const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; + +/** + * @} + */ + +/** @addtogroup STM32G4xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32G4xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ + +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ + #endif + + /* Configure the Vector Table location add offset address ------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (**) HSI_VALUE is a constant defined in stm32g4xx_hal.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in stm32g4xx_hal.h file (default value + * 24 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp, pllvco, pllr, pllsource, pllm; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case 0x04: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + + case 0x08: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + + case 0x0C: /* PLL used as system clock source */ + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); + pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1U ; + if (pllsource == 0x02UL) /* HSI used as PLL clock source */ + { + pllvco = (HSI_VALUE / pllm); + } + else /* HSE used as PLL clock source */ + { + pllvco = (HSE_VALUE / pllm); + } + pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8); + pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U; + SystemCoreClock = pllvco/pllr; + break; + + default: + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + diff --git a/Testbench/NucleoG4-Hello/NucleoG4-Hello.ioc b/Testbench/NucleoG4-Hello/NucleoG4-Hello.ioc new file mode 100644 index 000000000..80665e2b5 --- /dev/null +++ b/Testbench/NucleoG4-Hello/NucleoG4-Hello.ioc @@ -0,0 +1,135 @@ +#MicroXplorer Configuration settings - do not modify +CAD.formats= +CAD.pinconfig= +CAD.provider= +File.Version=6 +GPIO.groupedBy= +KeepUserPlacement=false +Mcu.CPN=STM32G474RET6 +Mcu.Family=STM32G4 +Mcu.IP0=NVIC +Mcu.IP1=RCC +Mcu.IP2=SYS +Mcu.IPNb=3 +Mcu.Name=STM32G474R(B-C-E)Tx +Mcu.Package=LQFP64 +Mcu.Pin0=PA5 +Mcu.Pin1=PA13 +Mcu.Pin2=PA14 +Mcu.Pin3=PB3 +Mcu.Pin4=VP_SYS_VS_Systick +Mcu.Pin5=VP_SYS_VS_DBSignals +Mcu.PinsNb=6 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32G474RETx +MxCube.Version=6.18.1 +MxDb.Version=DB.6.0.181 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +PA13.Mode=Trace_Asynchronous_SW +PA13.Signal=SYS_JTMS-SWDIO +PA14.Mode=Trace_Asynchronous_SW +PA14.Signal=SYS_JTCK-SWCLK +PA5.GPIOParameters=GPIO_Label +PA5.GPIO_Label=USER_LED +PA5.Locked=true +PA5.Signal=GPIO_Output +PB3.Mode=Trace_Asynchronous_SW +PB3.Signal=SYS_JTDO-SWO +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerLinker=GCC +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=true +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32G474RETx +ProjectManager.FirmwarePackage=STM32Cube FW_G4 V1.6.3 +ProjectManager.FreePins=true +ProjectManager.FreePinsContext= +ProjectManager.HalAssertFull=true +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=2 +ProjectManager.MainLocation=Core/Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=NucleoG4-Hello.ioc +ProjectManager.ProjectName=NucleoG4-Hello +ProjectManager.ProjectStructure= +ProjectManager.RegisterCallBack= +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=CMake +ProjectManager.ToolChainLocation= +ProjectManager.UAScriptAfterPath= +ProjectManager.UAScriptBeforePath= +ProjectManager.UnderRoot=false +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true +RCC.ADC12Freq_Value=160000000 +RCC.ADC345Freq_Value=160000000 +RCC.AHBFreq_Value=160000000 +RCC.APB1Freq_Value=160000000 +RCC.APB1TimFreq_Value=160000000 +RCC.APB2Freq_Value=160000000 +RCC.APB2TimFreq_Value=160000000 +RCC.CRSFreq_Value=48000000 +RCC.CortexFreq_Value=160000000 +RCC.EXTERNAL_CLOCK_VALUE=12288000 +RCC.FCLKCortexFreq_Value=160000000 +RCC.FDCANFreq_Value=160000000 +RCC.FamilyName=M +RCC.HCLKFreq_Value=160000000 +RCC.HRTIM1Freq_Value=160000000 +RCC.HSE_VALUE=8000000 +RCC.HSI48_VALUE=48000000 +RCC.HSI_VALUE=16000000 +RCC.I2C1Freq_Value=160000000 +RCC.I2C2Freq_Value=160000000 +RCC.I2C3Freq_Value=160000000 +RCC.I2C4Freq_Value=160000000 +RCC.I2SFreq_Value=160000000 +RCC.IPParameters=ADC12Freq_Value,ADC345Freq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CRSFreq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLKCortexFreq_Value,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HRTIM1Freq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I2SFreq_Value,LPTIM1Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,QSPIFreq_Value,RNGFreq_Value,SAI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value +RCC.LPTIM1Freq_Value=160000000 +RCC.LPUART1Freq_Value=160000000 +RCC.LSCOPinFreq_Value=32000 +RCC.LSE_VALUE=32768 +RCC.LSI_VALUE=32000 +RCC.MCO1PinFreq_Value=16000000 +RCC.PLLN=20 +RCC.PLLPoutputFreq_Value=160000000 +RCC.PLLQoutputFreq_Value=160000000 +RCC.PLLRCLKFreq_Value=160000000 +RCC.PWRFreq_Value=160000000 +RCC.QSPIFreq_Value=160000000 +RCC.RNGFreq_Value=160000000 +RCC.SAI1Freq_Value=160000000 +RCC.SYSCLKFreq_VALUE=160000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +RCC.UART4Freq_Value=160000000 +RCC.UART5Freq_Value=160000000 +RCC.USART1Freq_Value=160000000 +RCC.USART2Freq_Value=160000000 +RCC.USART3Freq_Value=160000000 +RCC.USBFreq_Value=160000000 +RCC.VCOInputFreq_Value=16000000 +RCC.VCOOutputFreq_Value=320000000 +VP_SYS_VS_DBSignals.Mode=DisableDeadBatterySignals +VP_SYS_VS_DBSignals.Signal=SYS_VS_DBSignals +VP_SYS_VS_Systick.Mode=SysTick +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +board=custom diff --git a/Testbench/NucleoG4-Hello/STM32G474xx_FLASH.ld b/Testbench/NucleoG4-Hello/STM32G474xx_FLASH.ld new file mode 100644 index 000000000..2c518a14a --- /dev/null +++ b/Testbench/NucleoG4-Hello/STM32G474xx_FLASH.ld @@ -0,0 +1,250 @@ +/* +****************************************************************************** +** + +** File : LinkerScript.ld +** +** Author : STM32CubeMX +** +** Abstract : Linker script for STM32G474RETx series +** 512Kbytes FLASH and 128Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed “as is,” without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +**

© COPYRIGHT(c) 2025 STMicroelectronics

+** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** 1. Redistributions of source code must retain the above copyright notice, +** this list of conditions and the following disclaimer. +** 2. Redistributions in binary form must reproduce the above copyright notice, +** this list of conditions and the following disclaimer in the documentation +** and/or other materials provided with the distribution. +** 3. Neither the name of STMicroelectronics nor the names of its contributors +** may be used to endorse or promote products derived from this software +** without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K +FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 512K +} + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of RAM */ +_sstack = _estack - _Min_Stack_Size; +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + } >RAM AT> FLASH + + /* Initialized TLS data section */ + .tdata : ALIGN(4) + { + *(.tdata .tdata.* .gnu.linkonce.td.*) + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + PROVIDE(__data_end = .); + PROVIDE(__tdata_end = .); + } >RAM AT> FLASH + + PROVIDE( __tdata_start = ADDR(.tdata) ); + PROVIDE( __tdata_size = __tdata_end - __tdata_start ); + + PROVIDE( __data_start = ADDR(.data) ); + PROVIDE( __data_size = __data_end - __data_start ); + + PROVIDE( __tdata_source = LOADADDR(.tdata) ); + PROVIDE( __tdata_source_end = LOADADDR(.tdata) + SIZEOF(.tdata) ); + PROVIDE( __tdata_source_size = __tdata_source_end - __tdata_source ); + + PROVIDE( __data_source = LOADADDR(.data) ); + PROVIDE( __data_source_end = __tdata_source_end ); + PROVIDE( __data_source_size = __data_source_end - __data_source ); + /* Uninitialized data section */ + .tbss (NOLOAD) : ALIGN(4) + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.tbss .tbss.*) + . = ALIGN(4); + PROVIDE( __tbss_end = . ); + } >RAM + + PROVIDE( __tbss_start = ADDR(.tbss) ); + PROVIDE( __tbss_size = __tbss_end - __tbss_start ); + PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); + + PROVIDE( __tls_base = __tdata_start ); + PROVIDE( __tls_end = __tbss_end ); + PROVIDE( __tls_size = __tls_end - __tls_base ); + PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); + PROVIDE( __tls_size_align = (__tls_size + __tls_align - 1) & ~(__tls_align - 1) ); + PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); + PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); + + .bss (NOLOAD) : ALIGN(4) + { + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + PROVIDE( __bss_end = .); + } >RAM + PROVIDE( __non_tls_bss_start = ADDR(.bss) ); + + PROVIDE( __bss_start = __tbss_start ); + PROVIDE( __bss_size = __bss_end - __bss_start ); + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack (NOLOAD) : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a:* ( * ) + libm.a:* ( * ) + libgcc.a:* ( * ) + } + +} diff --git a/Testbench/NucleoG4-Hello/startup_stm32g474xx.s b/Testbench/NucleoG4-Hello/startup_stm32g474xx.s new file mode 100644 index 000000000..e7a2c61fc --- /dev/null +++ b/Testbench/NucleoG4-Hello/startup_stm32g474xx.s @@ -0,0 +1,592 @@ +/** + ****************************************************************************** + * @file startup_stm32g474xx.s + * @author MCD Application Team + * @brief STM32G474xx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex-M4. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_PVM_IRQHandler + .word RTC_TAMP_LSECSS_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_IRQHandler + .word USB_LP_IRQHandler + .word FDCAN1_IT0_IRQHandler + .word FDCAN1_IT1_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word USBWakeUp_IRQHandler + .word TIM8_BRK_IRQHandler + .word TIM8_UP_IRQHandler + .word TIM8_TRG_COM_IRQHandler + .word TIM8_CC_IRQHandler + .word ADC3_IRQHandler + .word FMC_IRQHandler + .word LPTIM1_IRQHandler + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_DAC_IRQHandler + .word TIM7_DAC_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word ADC4_IRQHandler + .word ADC5_IRQHandler + .word UCPD1_IRQHandler + .word COMP1_2_3_IRQHandler + .word COMP4_5_6_IRQHandler + .word COMP7_IRQHandler + .word HRTIM1_Master_IRQHandler + .word HRTIM1_TIMA_IRQHandler + .word HRTIM1_TIMB_IRQHandler + .word HRTIM1_TIMC_IRQHandler + .word HRTIM1_TIMD_IRQHandler + .word HRTIM1_TIME_IRQHandler + .word HRTIM1_FLT_IRQHandler + .word HRTIM1_TIMF_IRQHandler + .word CRS_IRQHandler + .word SAI1_IRQHandler + .word TIM20_BRK_IRQHandler + .word TIM20_UP_IRQHandler + .word TIM20_TRG_COM_IRQHandler + .word TIM20_CC_IRQHandler + .word FPU_IRQHandler + .word I2C4_EV_IRQHandler + .word I2C4_ER_IRQHandler + .word SPI4_IRQHandler + .word 0 + .word FDCAN2_IT0_IRQHandler + .word FDCAN2_IT1_IRQHandler + .word FDCAN3_IT0_IRQHandler + .word FDCAN3_IT1_IRQHandler + .word RNG_IRQHandler + .word LPUART1_IRQHandler + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word DMAMUX_OVR_IRQHandler + .word QUADSPI_IRQHandler + .word DMA1_Channel8_IRQHandler + .word DMA2_Channel6_IRQHandler + .word DMA2_Channel7_IRQHandler + .word DMA2_Channel8_IRQHandler + .word CORDIC_IRQHandler + .word FMAC_IRQHandler + + .size g_pfnVectors, .-g_pfnVectors + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak RTC_TAMP_LSECSS_IRQHandler + .thumb_set RTC_TAMP_LSECSS_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_IRQHandler + .thumb_set USB_HP_IRQHandler,Default_Handler + + .weak USB_LP_IRQHandler + .thumb_set USB_LP_IRQHandler,Default_Handler + + .weak FDCAN1_IT0_IRQHandler + .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler + + .weak FDCAN1_IT1_IRQHandler + .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_DAC_IRQHandler + .thumb_set TIM7_DAC_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak ADC4_IRQHandler + .thumb_set ADC4_IRQHandler,Default_Handler + + .weak ADC5_IRQHandler + .thumb_set ADC5_IRQHandler,Default_Handler + + .weak UCPD1_IRQHandler + .thumb_set UCPD1_IRQHandler,Default_Handler + + .weak COMP1_2_3_IRQHandler + .thumb_set COMP1_2_3_IRQHandler,Default_Handler + + .weak COMP4_5_6_IRQHandler + .thumb_set COMP4_5_6_IRQHandler,Default_Handler + + .weak COMP7_IRQHandler + .thumb_set COMP7_IRQHandler,Default_Handler + + .weak HRTIM1_Master_IRQHandler + .thumb_set HRTIM1_Master_IRQHandler,Default_Handler + + .weak HRTIM1_TIMA_IRQHandler + .thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler + + .weak HRTIM1_TIMB_IRQHandler + .thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler + + .weak HRTIM1_TIMC_IRQHandler + .thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler + + .weak HRTIM1_TIMD_IRQHandler + .thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler + + .weak HRTIM1_TIME_IRQHandler + .thumb_set HRTIM1_TIME_IRQHandler,Default_Handler + + .weak HRTIM1_FLT_IRQHandler + .thumb_set HRTIM1_FLT_IRQHandler,Default_Handler + + .weak HRTIM1_TIMF_IRQHandler + .thumb_set HRTIM1_TIMF_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak TIM20_BRK_IRQHandler + .thumb_set TIM20_BRK_IRQHandler,Default_Handler + + .weak TIM20_UP_IRQHandler + .thumb_set TIM20_UP_IRQHandler,Default_Handler + + .weak TIM20_TRG_COM_IRQHandler + .thumb_set TIM20_TRG_COM_IRQHandler,Default_Handler + + .weak TIM20_CC_IRQHandler + .thumb_set TIM20_CC_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak I2C4_EV_IRQHandler + .thumb_set I2C4_EV_IRQHandler,Default_Handler + + .weak I2C4_ER_IRQHandler + .thumb_set I2C4_ER_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak FDCAN2_IT0_IRQHandler + .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler + + .weak FDCAN2_IT1_IRQHandler + .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler + + .weak FDCAN3_IT0_IRQHandler + .thumb_set FDCAN3_IT0_IRQHandler,Default_Handler + + .weak FDCAN3_IT1_IRQHandler + .thumb_set FDCAN3_IT1_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak DMAMUX_OVR_IRQHandler + .thumb_set DMAMUX_OVR_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak DMA1_Channel8_IRQHandler + .thumb_set DMA1_Channel8_IRQHandler,Default_Handler + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak DMA2_Channel7_IRQHandler + .thumb_set DMA2_Channel7_IRQHandler,Default_Handler + + .weak DMA2_Channel8_IRQHandler + .thumb_set DMA2_Channel8_IRQHandler,Default_Handler + + .weak CORDIC_IRQHandler + .thumb_set CORDIC_IRQHandler,Default_Handler + + .weak FMAC_IRQHandler + .thumb_set FMAC_IRQHandler,Default_Handler + diff --git a/Testbench/testbench.cmake b/Testbench/testbench.cmake index a3b8c6714..52a4f20a2 100644 --- a/Testbench/testbench.cmake +++ b/Testbench/testbench.cmake @@ -17,3 +17,13 @@ add_project( CMSIS_GIT_TAG "v1.2.6" # https://github.com/STMicroelectronics/cmsis-device-g4/tree/v1.2.6 CMSIS_MAJOR "5" ) + +add_project( + NAME "NucleoG4-Hello" + PATH "NucleoG4-Hello" + SERIES "g4" + SPECIFIER "g474re" + HAL_GIT_TAG "v1.2.7" # https://github.com/STMicroelectronics/stm32g4xx-hal-driver/tree/v1.2.7 + CMSIS_GIT_TAG "v1.2.6" # https://github.com/STMicroelectronics/cmsis-device-g4/tree/v1.2.6 + CMSIS_MAJOR "5" +) From ba73fa8e195aaeaaadc981431fe62f6f9c77e038 Mon Sep 17 00:00:00 2001 From: github-actions <41898282+github-actions[bot]@users.noreply.github.com> Date: Sun, 23 Aug 2026 23:50:28 +0000 Subject: [PATCH 14/17] Automatic CMake Format: Standardized formatting automatically --- Testbench/NucleoG4-Hello/CMakeLists.txt | 47 +++++++++++-------------- 1 file changed, 20 insertions(+), 27 deletions(-) diff --git a/Testbench/NucleoG4-Hello/CMakeLists.txt b/Testbench/NucleoG4-Hello/CMakeLists.txt index a372d6963..a95a6919a 100644 --- a/Testbench/NucleoG4-Hello/CMakeLists.txt +++ b/Testbench/NucleoG4-Hello/CMakeLists.txt @@ -8,39 +8,32 @@ Required components (orderless) ]] target_link_options( - ${TARGET_NAME} - PRIVATE - -T "${CMAKE_CURRENT_SOURCE_DIR}/STM32G474xx_FLASH.ld" + ${TARGET_NAME} + PRIVATE + -T + "${CMAKE_CURRENT_SOURCE_DIR}/STM32G474xx_FLASH.ld" ) -target_compile_definitions( - ${TARGET_NAME} - PRIVATE - STM32G474xx -) +target_compile_definitions(${TARGET_NAME} PRIVATE STM32G474xx) target_include_directories( - ${TARGET_NAME} - PRIVATE - Core/Inc - Application/Inc + ${TARGET_NAME} + PRIVATE + Core/Inc + Application/Inc ) target_sources( - ${TARGET_NAME} - PRIVATE - Application/Src/hello.c - Core/Src/gpio.c - Core/Src/main.c - Core/Src/stm32g4xx_it.c - Core/Src/syscalls.c - Core/Src/sysmem.c - Core/Src/system_stm32g4xx.c - startup_stm32g474xx.s + ${TARGET_NAME} + PRIVATE + Application/Src/hello.c + Core/Src/gpio.c + Core/Src/main.c + Core/Src/stm32g4xx_it.c + Core/Src/syscalls.c + Core/Src/sysmem.c + Core/Src/system_stm32g4xx.c + startup_stm32g474xx.s ) -target_link_libraries( - ${TARGET_NAME} - PRIVATE - LOGOMATIC_LIB -) +target_link_libraries(${TARGET_NAME} PRIVATE LOGOMATIC_LIB) From f55cc7cb00705b98e34647ef778c2579f96f882b Mon Sep 17 00:00:00 2001 From: github-actions <41898282+github-actions[bot]@users.noreply.github.com> Date: Sun, 23 Aug 2026 23:51:42 +0000 Subject: [PATCH 15/17] Automatic Clang-Format: Standardized formatting automatically --- .../NucleoG4-Hello/Application/Src/hello.c | 2 +- Testbench/NucleoG4-Hello/Core/Inc/gpio.h | 33 +- Testbench/NucleoG4-Hello/Core/Inc/main.h | 32 +- .../Core/Inc/stm32g4xx_hal_conf.h | 245 +++++----- .../NucleoG4-Hello/Core/Inc/stm32g4xx_it.h | 30 +- Testbench/NucleoG4-Hello/Core/Src/gpio.c | 189 ++++---- Testbench/NucleoG4-Hello/Core/Src/main.c | 199 ++++---- .../Core/Src/stm32g4xx_hal_msp.c | 56 +-- .../NucleoG4-Hello/Core/Src/stm32g4xx_it.c | 177 ++++--- Testbench/NucleoG4-Hello/Core/Src/syscalls.c | 147 +++--- Testbench/NucleoG4-Hello/Core/Src/sysmem.c | 48 +- .../Core/Src/system_stm32g4xx.c | 432 +++++++++--------- 12 files changed, 779 insertions(+), 811 deletions(-) diff --git a/Testbench/NucleoG4-Hello/Application/Src/hello.c b/Testbench/NucleoG4-Hello/Application/Src/hello.c index 837639fcd..ef415e173 100644 --- a/Testbench/NucleoG4-Hello/Application/Src/hello.c +++ b/Testbench/NucleoG4-Hello/Application/Src/hello.c @@ -2,8 +2,8 @@ #include -#include "main.h" #include "Logomatic.h" +#include "main.h" HAL_StatusTypeDef say_hello(uint8_t count) { diff --git a/Testbench/NucleoG4-Hello/Core/Inc/gpio.h b/Testbench/NucleoG4-Hello/Core/Inc/gpio.h index 3c91c4dd6..37dcc0a5c 100644 --- a/Testbench/NucleoG4-Hello/Core/Inc/gpio.h +++ b/Testbench/NucleoG4-Hello/Core/Inc/gpio.h @@ -1,21 +1,21 @@ /* USER CODE BEGIN Header */ /** - ****************************************************************************** - * @file gpio.h - * @brief This file contains all the function prototypes for - * the gpio.c file - ****************************************************************************** - * @attention - * - * Copyright (c) 2026 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ + ****************************************************************************** + * @file gpio.h + * @brief This file contains all the function prototypes for + * the gpio.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ /* USER CODE END Header */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __GPIO_H__ @@ -46,4 +46,3 @@ void MX_GPIO_Init(void); } #endif #endif /*__ GPIO_H__ */ - diff --git a/Testbench/NucleoG4-Hello/Core/Inc/main.h b/Testbench/NucleoG4-Hello/Core/Inc/main.h index e2752149c..2beba28d2 100644 --- a/Testbench/NucleoG4-Hello/Core/Inc/main.h +++ b/Testbench/NucleoG4-Hello/Core/Inc/main.h @@ -1,21 +1,21 @@ /* USER CODE BEGIN Header */ /** - ****************************************************************************** - * @file : main.h - * @brief : Header for main.c file. - * This file contains the common defines of the application. - ****************************************************************************** - * @attention - * - * Copyright (c) 2026 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ /* USER CODE END Header */ /* Define to prevent recursive inclusion -------------------------------------*/ diff --git a/Testbench/NucleoG4-Hello/Core/Inc/stm32g4xx_hal_conf.h b/Testbench/NucleoG4-Hello/Core/Inc/stm32g4xx_hal_conf.h index 90adf393c..b56f22666 100644 --- a/Testbench/NucleoG4-Hello/Core/Inc/stm32g4xx_hal_conf.h +++ b/Testbench/NucleoG4-Hello/Core/Inc/stm32g4xx_hal_conf.h @@ -1,21 +1,21 @@ /* USER CODE BEGIN Header */ /** - ****************************************************************************** - * @file stm32g4xx_hal_conf.h - * @author MCD Application Team - * @brief HAL configuration file - ****************************************************************************** + ****************************************************************************** + * @file stm32g4xx_hal_conf.h + * @author MCD Application Team + * @brief HAL configuration file + ****************************************************************************** * @attention - * - * Copyright (c) 2019 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ /* USER CODE END Header */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -23,7 +23,7 @@ #define STM32G4xx_HAL_CONF_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Exported types ------------------------------------------------------------*/ @@ -31,12 +31,12 @@ /* ########################## Module Selection ############################## */ /** - * @brief This is the list of modules to be used in the HAL driver - */ + * @brief This is the list of modules to be used in the HAL driver + */ #define HAL_MODULE_ENABLED - /*#define HAL_ADC_MODULE_ENABLED */ +/*#define HAL_ADC_MODULE_ENABLED */ /*#define HAL_COMP_MODULE_ENABLED */ /*#define HAL_CORDIC_MODULE_ENABLED */ /*#define HAL_CRC_MODULE_ENABLED */ @@ -76,123 +76,124 @@ /* ########################## Register Callbacks selection ############################## */ /** - * @brief This is the list of modules where register callback can be used - */ -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U -#define USE_HAL_COMP_REGISTER_CALLBACKS 0U -#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U -#define USE_HAL_EXTI_REGISTER_CALLBACKS 0U -#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U -#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U -#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U -#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U -#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U -#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U -#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U -#define USE_HAL_UART_REGISTER_CALLBACKS 0U -#define USE_HAL_USART_REGISTER_CALLBACKS 0U -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U + * @brief This is the list of modules where register callback can be used + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U +#define USE_HAL_COMP_REGISTER_CALLBACKS 0U +#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U +#define USE_HAL_EXTI_REGISTER_CALLBACKS 0U +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U +#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U +#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U +#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U +#define USE_HAL_UART_REGISTER_CALLBACKS 0U +#define USE_HAL_USART_REGISTER_CALLBACKS 0U +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* ########################## Oscillator Values adaptation ####################*/ /** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined(HSE_VALUE) +#define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined(HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ /** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined(HSI_VALUE) +#define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ /** - * @brief Internal High Speed oscillator (HSI48) value for USB FS and RNG. - * This internal oscillator is mainly dedicated to provide a high precision clock to - * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. - * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency - * which is subject to manufacturing process variations. - */ -#if !defined (HSI48_VALUE) - #define HSI48_VALUE (48000000UL) /*!< Value of the Internal High Speed oscillator for USB FS/RNG in Hz. - The real value my vary depending on manufacturing process variations.*/ -#endif /* HSI48_VALUE */ + * @brief Internal High Speed oscillator (HSI48) value for USB FS and RNG. + * This internal oscillator is mainly dedicated to provide a high precision clock to + * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. + * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency + * which is subject to manufacturing process variations. + */ +#if !defined(HSI48_VALUE) +#define HSI48_VALUE \ + (48000000UL) /*!< Value of the Internal High Speed oscillator for USB FS/RNG in Hz. \ + The real value my vary depending on manufacturing process variations.*/ +#endif /* HSI48_VALUE */ /** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined(LSI_VALUE) /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature.*/ -#define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/ -#endif /* LSI_VALUE */ +#define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /** - * @brief External Low Speed oscillator (LSE) value. - * This value is used by the UART, RTC HAL module to compute the system frequency - */ -#if !defined (LSE_VALUE) -#define LSE_VALUE (32768UL) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined(LSE_VALUE) +#define LSE_VALUE (32768UL) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ -#if !defined (LSE_STARTUP_TIMEOUT) -#define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ +#if !defined(LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ /** - * @brief External clock source for I2S and SAI peripherals - * This value is used by the I2S and SAI HAL modules to compute the I2S and SAI clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined (EXTERNAL_CLOCK_VALUE) -#define EXTERNAL_CLOCK_VALUE (12288000UL) /*!< Value of the External oscillator in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ + * @brief External clock source for I2S and SAI peripherals + * This value is used by the I2S and SAI HAL modules to compute the I2S and SAI clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined(EXTERNAL_CLOCK_VALUE) +#define EXTERNAL_CLOCK_VALUE (12288000UL) /*!< Value of the External oscillator in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ /* Tip: To avoid modifying this file each time you need to use different HSE, === you can define the HSE value in your toolchain compiler preprocessor. */ /* ########################### System Configuration ######################### */ /** - * @brief This is the HAL system configuration section - */ + * @brief This is the HAL system configuration section + */ -#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority (lowest by default) */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 0U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U +#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority (lowest by default) */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 0U +#define INSTRUCTION_CACHE_ENABLE 1U +#define DATA_CACHE_ENABLE 1U /* ########################## Assert Selection ############################## */ /** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ - #define USE_FULL_ASSERT 1U + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +#define USE_FULL_ASSERT 1U /* ################## SPI peripheral configuration ########################## */ @@ -201,12 +202,12 @@ The real value may vary depending on the variations in voltage and temperature.* * Deactivated: CRC code cleaned from driver */ -#define USE_SPI_CRC 0U +#define USE_SPI_CRC 0U /* Includes ------------------------------------------------------------------*/ /** - * @brief Include module's header file - */ + * @brief Include module's header file + */ #ifdef HAL_RCC_MODULE_ENABLED #include "stm32g4xx_hal_rcc.h" @@ -357,15 +358,15 @@ The real value may vary depending on the variations in voltage and temperature.* #endif /* HAL_WWDG_MODULE_ENABLED */ /* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT +#ifdef USE_FULL_ASSERT /** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) /* Exported functions ------------------------------------------------------- */ void assert_failed(uint8_t *file, uint32_t line); diff --git a/Testbench/NucleoG4-Hello/Core/Inc/stm32g4xx_it.h b/Testbench/NucleoG4-Hello/Core/Inc/stm32g4xx_it.h index 1a144ad22..3cfc1aa5a 100644 --- a/Testbench/NucleoG4-Hello/Core/Inc/stm32g4xx_it.h +++ b/Testbench/NucleoG4-Hello/Core/Inc/stm32g4xx_it.h @@ -1,20 +1,20 @@ /* USER CODE BEGIN Header */ /** - ****************************************************************************** - * @file stm32g4xx_it.h - * @brief This file contains the headers of the interrupt handlers. - ****************************************************************************** - * @attention - * - * Copyright (c) 2026 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ + ****************************************************************************** + * @file stm32g4xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ /* USER CODE END Header */ /* Define to prevent recursive inclusion -------------------------------------*/ diff --git a/Testbench/NucleoG4-Hello/Core/Src/gpio.c b/Testbench/NucleoG4-Hello/Core/Src/gpio.c index 252155711..4b59572f4 100644 --- a/Testbench/NucleoG4-Hello/Core/Src/gpio.c +++ b/Testbench/NucleoG4-Hello/Core/Src/gpio.c @@ -1,21 +1,21 @@ /* USER CODE BEGIN Header */ /** - ****************************************************************************** - * @file gpio.c - * @brief This file provides code for the configuration - * of all used GPIO pins. - ****************************************************************************** - * @attention - * - * Copyright (c) 2026 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ + ****************************************************************************** + * @file gpio.c + * @brief This file provides code for the configuration + * of all used GPIO pins. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ @@ -33,91 +33,84 @@ /* USER CODE END 1 */ /** Configure pins as - * Analog - * Input - * Output - * EVENT_OUT - * EXTI - * Free pins are configured automatically as Analog (this feature is enabled through - * the Code Generation settings) -*/ + * Analog + * Input + * Output + * EVENT_OUT + * EXTI + * Free pins are configured automatically as Analog (this feature is enabled through + * the Code Generation settings) + */ void MX_GPIO_Init(void) { - GPIO_InitTypeDef GPIO_InitStruct = {0}; - - /* GPIO Ports Clock Enable */ - __HAL_RCC_GPIOC_CLK_ENABLE(); - __HAL_RCC_GPIOF_CLK_ENABLE(); - __HAL_RCC_GPIOG_CLK_ENABLE(); - __HAL_RCC_GPIOA_CLK_ENABLE(); - __HAL_RCC_GPIOB_CLK_ENABLE(); - __HAL_RCC_GPIOD_CLK_ENABLE(); - - /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(USER_LED_GPIO_Port, USER_LED_Pin, GPIO_PIN_RESET); - - /*Configure GPIO pins : PC13 PC14 PC15 PC0 - PC1 PC2 PC3 PC4 - PC5 PC6 PC7 PC8 - PC9 PC10 PC11 PC12 */ - GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15|GPIO_PIN_0 - |GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4 - |GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8 - |GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /*Configure GPIO pins : PF0 PF1 */ - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); - - /*Configure GPIO pin : PG10 */ - GPIO_InitStruct.Pin = GPIO_PIN_10; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); - - /*Configure GPIO pins : PA0 PA1 PA2 PA3 - PA4 PA6 PA7 PA8 - PA9 PA10 PA11 PA12 - PA15 */ - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 - |GPIO_PIN_4|GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8 - |GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12 - |GPIO_PIN_15; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /*Configure GPIO pin : USER_LED_Pin */ - GPIO_InitStruct.Pin = USER_LED_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - HAL_GPIO_Init(USER_LED_GPIO_Port, &GPIO_InitStruct); - - /*Configure GPIO pins : PB0 PB1 PB2 PB10 - PB11 PB12 PB13 PB14 - PB15 PB4 PB5 PB6 - PB7 PB8 PB9 */ - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_10 - |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 - |GPIO_PIN_15|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6 - |GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /*Configure GPIO pin : PD2 */ - GPIO_InitStruct.Pin = GPIO_PIN_2; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); - + GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(USER_LED_GPIO_Port, USER_LED_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pins : PC13 PC14 PC15 PC0 + PC1 PC2 PC3 PC4 + PC5 PC6 PC7 PC8 + PC9 PC10 PC11 PC12 */ + GPIO_InitStruct.Pin = GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15 | GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | + GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /*Configure GPIO pins : PF0 PF1 */ + GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + /*Configure GPIO pin : PG10 */ + GPIO_InitStruct.Pin = GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + /*Configure GPIO pins : PA0 PA1 PA2 PA3 + PA4 PA6 PA7 PA8 + PA9 PA10 PA11 PA12 + PA15 */ + GPIO_InitStruct.Pin = + GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /*Configure GPIO pin : USER_LED_Pin */ + GPIO_InitStruct.Pin = USER_LED_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(USER_LED_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pins : PB0 PB1 PB2 PB10 + PB11 PB12 PB13 PB14 + PB15 PB4 PB5 PB6 + PB7 PB8 PB9 */ + GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | + GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /*Configure GPIO pin : PD2 */ + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); } /* USER CODE BEGIN 2 */ diff --git a/Testbench/NucleoG4-Hello/Core/Src/main.c b/Testbench/NucleoG4-Hello/Core/Src/main.c index 074f2482f..fd7d90b5b 100644 --- a/Testbench/NucleoG4-Hello/Core/Src/main.c +++ b/Testbench/NucleoG4-Hello/Core/Src/main.c @@ -1,23 +1,24 @@ /* USER CODE BEGIN Header */ /** - ****************************************************************************** - * @file : main.c - * @brief : Main program body - ****************************************************************************** - * @attention - * - * Copyright (c) 2026 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "main.h" + #include "gpio.h" /* Private includes ----------------------------------------------------------*/ @@ -58,93 +59,89 @@ void SystemClock_Config(void); /* USER CODE END 0 */ /** - * @brief The application entry point. - * @retval int - */ + * @brief The application entry point. + * @retval int + */ int main(void) { - /* USER CODE BEGIN 1 */ + /* USER CODE BEGIN 1 */ - /* USER CODE END 1 */ + /* USER CODE END 1 */ - /* MCU Configuration--------------------------------------------------------*/ + /* MCU Configuration--------------------------------------------------------*/ - /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ - HAL_Init(); + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); - /* USER CODE BEGIN Init */ + /* USER CODE BEGIN Init */ - /* USER CODE END Init */ + /* USER CODE END Init */ - /* Configure the system clock */ - SystemClock_Config(); + /* Configure the system clock */ + SystemClock_Config(); - /* USER CODE BEGIN SysInit */ + /* USER CODE BEGIN SysInit */ - /* USER CODE END SysInit */ + /* USER CODE END SysInit */ - /* Initialize all configured peripherals */ - MX_GPIO_Init(); - /* USER CODE BEGIN 2 */ + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + /* USER CODE BEGIN 2 */ - /* USER CODE END 2 */ + /* USER CODE END 2 */ - /* Infinite loop */ - /* USER CODE BEGIN WHILE */ - while (1) - { - /* USER CODE END WHILE */ + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) { + /* USER CODE END WHILE */ - /* USER CODE BEGIN 3 */ - } - /* USER CODE END 3 */ + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ } /** - * @brief System Clock Configuration - * @retval None - */ + * @brief System Clock Configuration + * @retval None + */ void SystemClock_Config(void) { - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - - /** Configure the main internal regulator output voltage - */ - HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST); - - /** Initializes the RCC Oscillators according to the specified parameters - * in the RCC_OscInitTypeDef structure. - */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; - RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1; - RCC_OscInitStruct.PLL.PLLN = 20; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; - RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - { - Error_Handler(); - } - - /** Initializes the CPU, AHB and APB buses clocks - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) - { - Error_Handler(); - } + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /** Configure the main internal regulator output voltage + */ + HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST); + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1; + RCC_OscInitStruct.PLL.PLLN = 20; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; + RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + Error_Handler(); + } } /* USER CODE BEGIN 4 */ @@ -152,32 +149,30 @@ void SystemClock_Config(void) /* USER CODE END 4 */ /** - * @brief This function is executed in case of error occurrence. - * @retval None - */ + * @brief This function is executed in case of error occurrence. + * @retval None + */ void Error_Handler(void) { - /* USER CODE BEGIN Error_Handler_Debug */ - /* User can add his own implementation to report the HAL error return state */ - __disable_irq(); - while (1) - { - } - /* USER CODE END Error_Handler_Debug */ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) {} + /* USER CODE END Error_Handler_Debug */ } #ifdef USE_FULL_ASSERT /** - * @brief Reports the name of the source file and the source line number - * where the assert_param error has occurred. - * @param file: pointer to the source file name - * @param line: assert_param error line source number - * @retval None - */ + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ void assert_failed(uint8_t *file, uint32_t line) { - /* USER CODE BEGIN 6 */ - UNUSED(file); - UNUSED(line); - /* USER CODE END 6 */ + /* USER CODE BEGIN 6 */ + UNUSED(file); + UNUSED(line); + /* USER CODE END 6 */ } #endif /* USE_FULL_ASSERT */ diff --git a/Testbench/NucleoG4-Hello/Core/Src/stm32g4xx_hal_msp.c b/Testbench/NucleoG4-Hello/Core/Src/stm32g4xx_hal_msp.c index d908bd772..4668755ab 100644 --- a/Testbench/NucleoG4-Hello/Core/Src/stm32g4xx_hal_msp.c +++ b/Testbench/NucleoG4-Hello/Core/Src/stm32g4xx_hal_msp.c @@ -1,21 +1,21 @@ /* USER CODE BEGIN Header */ /** - ****************************************************************************** - * @file stm32g4xx_hal_msp.c - * @brief This file provides code for the MSP Initialization - * and de-Initialization codes. - ****************************************************************************** - * @attention - * - * Copyright (c) 2026 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ + ****************************************************************************** + * @file stm32g4xx_hal_msp.c + * @brief This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "main.h" @@ -57,27 +57,27 @@ /* USER CODE END 0 */ /** - * Initializes the Global MSP. - */ + * Initializes the Global MSP. + */ void HAL_MspInit(void) { - /* USER CODE BEGIN MspInit 0 */ + /* USER CODE BEGIN MspInit 0 */ - /* USER CODE END MspInit 0 */ + /* USER CODE END MspInit 0 */ - __HAL_RCC_SYSCFG_CLK_ENABLE(); - __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_RCC_SYSCFG_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); - /* System interrupt init*/ + /* System interrupt init*/ - /** Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral - */ - HAL_PWREx_DisableUCPDDeadBattery(); + /** Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral + */ + HAL_PWREx_DisableUCPDDeadBattery(); - /* USER CODE BEGIN MspInit 1 */ + /* USER CODE BEGIN MspInit 1 */ - /* USER CODE END MspInit 1 */ + /* USER CODE END MspInit 1 */ } /* USER CODE BEGIN 1 */ diff --git a/Testbench/NucleoG4-Hello/Core/Src/stm32g4xx_it.c b/Testbench/NucleoG4-Hello/Core/Src/stm32g4xx_it.c index 13e0f0c20..22ab0ab23 100644 --- a/Testbench/NucleoG4-Hello/Core/Src/stm32g4xx_it.c +++ b/Testbench/NucleoG4-Hello/Core/Src/stm32g4xx_it.c @@ -1,25 +1,26 @@ /* USER CODE BEGIN Header */ /** - ****************************************************************************** - * @file stm32g4xx_it.c - * @brief Interrupt Service Routines. - ****************************************************************************** - * @attention - * - * Copyright (c) 2026 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ + ****************************************************************************** + * @file stm32g4xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ -#include "main.h" #include "stm32g4xx_it.h" + +#include "main.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ /* USER CODE END Includes */ @@ -64,131 +65,125 @@ /* Cortex-M4 Processor Interruption and Exception Handlers */ /******************************************************************************/ /** - * @brief This function handles Non maskable interrupt. - */ + * @brief This function handles Non maskable interrupt. + */ void NMI_Handler(void) { - /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ - - /* USER CODE END NonMaskableInt_IRQn 0 */ - /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ - while (1) - { - } - /* USER CODE END NonMaskableInt_IRQn 1 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) {} + /* USER CODE END NonMaskableInt_IRQn 1 */ } /** - * @brief This function handles Hard fault interrupt. - */ + * @brief This function handles Hard fault interrupt. + */ void HardFault_Handler(void) { - /* USER CODE BEGIN HardFault_IRQn 0 */ - - /* USER CODE END HardFault_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_HardFault_IRQn 0 */ - /* USER CODE END W1_HardFault_IRQn 0 */ - } + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } } /** - * @brief This function handles Memory management fault. - */ + * @brief This function handles Memory management fault. + */ void MemManage_Handler(void) { - /* USER CODE BEGIN MemoryManagement_IRQn 0 */ - - /* USER CODE END MemoryManagement_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ - /* USER CODE END W1_MemoryManagement_IRQn 0 */ - } + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } } /** - * @brief This function handles Prefetch fault, memory access fault. - */ + * @brief This function handles Prefetch fault, memory access fault. + */ void BusFault_Handler(void) { - /* USER CODE BEGIN BusFault_IRQn 0 */ - - /* USER CODE END BusFault_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_BusFault_IRQn 0 */ - /* USER CODE END W1_BusFault_IRQn 0 */ - } + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } } /** - * @brief This function handles Undefined instruction or illegal state. - */ + * @brief This function handles Undefined instruction or illegal state. + */ void UsageFault_Handler(void) { - /* USER CODE BEGIN UsageFault_IRQn 0 */ - - /* USER CODE END UsageFault_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ - /* USER CODE END W1_UsageFault_IRQn 0 */ - } + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } } /** - * @brief This function handles System service call via SWI instruction. - */ + * @brief This function handles System service call via SWI instruction. + */ void SVC_Handler(void) { - /* USER CODE BEGIN SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 0 */ - /* USER CODE END SVCall_IRQn 0 */ - /* USER CODE BEGIN SVCall_IRQn 1 */ + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ - /* USER CODE END SVCall_IRQn 1 */ + /* USER CODE END SVCall_IRQn 1 */ } /** - * @brief This function handles Debug monitor. - */ + * @brief This function handles Debug monitor. + */ void DebugMon_Handler(void) { - /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ - /* USER CODE END DebugMonitor_IRQn 0 */ - /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ - /* USER CODE END DebugMonitor_IRQn 1 */ + /* USER CODE END DebugMonitor_IRQn 1 */ } /** - * @brief This function handles Pendable request for system service. - */ + * @brief This function handles Pendable request for system service. + */ void PendSV_Handler(void) { - /* USER CODE BEGIN PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 0 */ - /* USER CODE END PendSV_IRQn 0 */ - /* USER CODE BEGIN PendSV_IRQn 1 */ + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ - /* USER CODE END PendSV_IRQn 1 */ + /* USER CODE END PendSV_IRQn 1 */ } /** - * @brief This function handles System tick timer. - */ + * @brief This function handles System tick timer. + */ void SysTick_Handler(void) { - /* USER CODE BEGIN SysTick_IRQn 0 */ + /* USER CODE BEGIN SysTick_IRQn 0 */ - /* USER CODE END SysTick_IRQn 0 */ - HAL_IncTick(); - /* USER CODE BEGIN SysTick_IRQn 1 */ + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ - /* USER CODE END SysTick_IRQn 1 */ + /* USER CODE END SysTick_IRQn 1 */ } /******************************************************************************/ diff --git a/Testbench/NucleoG4-Hello/Core/Src/syscalls.c b/Testbench/NucleoG4-Hello/Core/Src/syscalls.c index e10d76fa2..d2b217993 100644 --- a/Testbench/NucleoG4-Hello/Core/Src/syscalls.c +++ b/Testbench/NucleoG4-Hello/Core/Src/syscalls.c @@ -21,158 +21,150 @@ */ /* Includes */ -#include -#include #include -#include #include -#include +#include +#include +#include #include #include - +#include /* Variables */ extern int __io_putchar(int ch) __attribute__((weak)); extern int __io_getchar(void) __attribute__((weak)); - -char *__env[1] = { 0 }; +char *__env[1] = {0}; char **environ = __env; - /* Functions */ -void initialise_monitor_handles() -{ -} +void initialise_monitor_handles() {} int _getpid(void) { - return 1; + return 1; } int _kill(int pid, int sig) { - (void)pid; - (void)sig; - errno = EINVAL; - return -1; + (void)pid; + (void)sig; + errno = EINVAL; + return -1; } -void _exit (int status) +void _exit(int status) { - _kill(status, -1); - while (1) {} /* Make sure we hang here */ + _kill(status, -1); + while (1) {} /* Make sure we hang here */ } __attribute__((weak)) int _read(int file, char *ptr, int len) { - (void)file; - int DataIdx; + (void)file; + int DataIdx; - for (DataIdx = 0; DataIdx < len; DataIdx++) - { - *ptr++ = __io_getchar(); - } + for (DataIdx = 0; DataIdx < len; DataIdx++) { + *ptr++ = __io_getchar(); + } - return len; + return len; } __attribute__((weak)) int _write(int file, char *ptr, int len) { - (void)file; - int DataIdx; + (void)file; + int DataIdx; - for (DataIdx = 0; DataIdx < len; DataIdx++) - { - __io_putchar(*ptr++); - } - return len; + for (DataIdx = 0; DataIdx < len; DataIdx++) { + __io_putchar(*ptr++); + } + return len; } int _close(int file) { - (void)file; - return -1; + (void)file; + return -1; } - int _fstat(int file, struct stat *st) { - (void)file; - st->st_mode = S_IFCHR; - return 0; + (void)file; + st->st_mode = S_IFCHR; + return 0; } int _isatty(int file) { - (void)file; - return 1; + (void)file; + return 1; } int _lseek(int file, int ptr, int dir) { - (void)file; - (void)ptr; - (void)dir; - return 0; + (void)file; + (void)ptr; + (void)dir; + return 0; } int _open(char *path, int flags, ...) { - (void)path; - (void)flags; - /* Pretend like we always fail */ - return -1; + (void)path; + (void)flags; + /* Pretend like we always fail */ + return -1; } int _wait(int *status) { - (void)status; - errno = ECHILD; - return -1; + (void)status; + errno = ECHILD; + return -1; } int _unlink(char *name) { - (void)name; - errno = ENOENT; - return -1; + (void)name; + errno = ENOENT; + return -1; } clock_t _times(struct tms *buf) { - (void)buf; - return -1; + (void)buf; + return -1; } int _stat(const char *file, struct stat *st) { - (void)file; - st->st_mode = S_IFCHR; - return 0; + (void)file; + st->st_mode = S_IFCHR; + return 0; } int _link(char *old, char *new) { - (void)old; - (void)new; - errno = EMLINK; - return -1; + (void)old; + (void)new; + errno = EMLINK; + return -1; } int _fork(void) { - errno = EAGAIN; - return -1; + errno = EAGAIN; + return -1; } int _execve(char *name, char **argv, char **env) { - (void)name; - (void)argv; - (void)env; - errno = ENOMEM; - return -1; + (void)name; + (void)argv; + (void)env; + errno = ENOMEM; + return -1; } // --- Picolibc Specific Section --- @@ -187,8 +179,8 @@ int _execve(char *name, char **argv, char **env) */ static int starm_putc(char c, FILE *file) { - (void) file; - __io_putchar(c); + (void)file; + __io_putchar(c); return c; } @@ -201,18 +193,15 @@ static int starm_putc(char c, FILE *file) static int starm_getc(FILE *file) { unsigned char c; - (void) file; - c = __io_getchar(); + (void)file; + c = __io_getchar(); return c; } // Define and initialize the standard I/O streams for Picolibc. // FDEV_SETUP_STREAM connects the starm_putc and starm_getc helper functions to a FILE structure. // _FDEV_SETUP_RW indicates the stream is for reading and writing. -static FILE __stdio = FDEV_SETUP_STREAM(starm_putc, - starm_getc, - NULL, - _FDEV_SETUP_RW); +static FILE __stdio = FDEV_SETUP_STREAM(starm_putc, starm_getc, NULL, _FDEV_SETUP_RW); // Assign the standard stream pointers (stdin, stdout, stderr) to the initialized stream. // Picolibc uses these pointers for standard I/O operations (printf, scanf, etc.). diff --git a/Testbench/NucleoG4-Hello/Core/Src/sysmem.c b/Testbench/NucleoG4-Hello/Core/Src/sysmem.c index a875d42c0..3a092d114 100644 --- a/Testbench/NucleoG4-Hello/Core/Src/sysmem.c +++ b/Testbench/NucleoG4-Hello/Core/Src/sysmem.c @@ -22,8 +22,8 @@ /* Includes */ #include -#include #include +#include /** * Pointer to the current high watermark of the heap usage @@ -53,35 +53,33 @@ static uint8_t *__sbrk_heap_end = NULL; */ void *_sbrk(ptrdiff_t incr) { - extern uint8_t _end; /* Symbol defined in the linker script */ - extern uint8_t _estack; /* Symbol defined in the linker script */ - extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ - const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; - const uint8_t *max_heap = (uint8_t *)stack_limit; - uint8_t *prev_heap_end; + extern uint8_t _end; /* Symbol defined in the linker script */ + extern uint8_t _estack; /* Symbol defined in the linker script */ + extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + const uint8_t *max_heap = (uint8_t *)stack_limit; + uint8_t *prev_heap_end; - /* Initialize heap end at first call */ - if (NULL == __sbrk_heap_end) - { - __sbrk_heap_end = &_end; - } + /* Initialize heap end at first call */ + if (NULL == __sbrk_heap_end) { + __sbrk_heap_end = &_end; + } - /* Protect heap from growing into the reserved MSP stack */ - if (__sbrk_heap_end + incr > max_heap) - { - errno = ENOMEM; - return (void *)-1; - } + /* Protect heap from growing into the reserved MSP stack */ + if (__sbrk_heap_end + incr > max_heap) { + errno = ENOMEM; + return (void *)-1; + } - prev_heap_end = __sbrk_heap_end; - __sbrk_heap_end += incr; + prev_heap_end = __sbrk_heap_end; + __sbrk_heap_end += incr; - return (void *)prev_heap_end; + return (void *)prev_heap_end; } #if defined(__PICOLIBC__) - // Picolibc expects syscalls without the leading underscore. - // This creates a strong alias so that - // calls to `sbrk()` are resolved to our `_sbrk()` implementation. - __strong_reference(_sbrk, sbrk); +// Picolibc expects syscalls without the leading underscore. +// This creates a strong alias so that +// calls to `sbrk()` are resolved to our `_sbrk()` implementation. +__strong_reference(_sbrk, sbrk); #endif diff --git a/Testbench/NucleoG4-Hello/Core/Src/system_stm32g4xx.c b/Testbench/NucleoG4-Hello/Core/Src/system_stm32g4xx.c index 2cd914e7b..414c5339c 100644 --- a/Testbench/NucleoG4-Hello/Core/Src/system_stm32g4xx.c +++ b/Testbench/NucleoG4-Hello/Core/Src/system_stm32g4xx.c @@ -1,109 +1,109 @@ /** - ****************************************************************************** - * @file system_stm32g4xx.c - * @author MCD Application Team - * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File - * - * This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32g4xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * After each device reset the HSI (16 MHz) is used as system clock source. - * Then SystemInit() function is called, in "startup_stm32g4xx.s" file, to - * configure the system clock before to branch to main program. - * - * This file configures the system clock as follows: - *============================================================================= - *----------------------------------------------------------------------------- - * System Clock source | HSI - *----------------------------------------------------------------------------- - * SYSCLK(Hz) | 16000000 - *----------------------------------------------------------------------------- - * HCLK(Hz) | 16000000 - *----------------------------------------------------------------------------- - * AHB Prescaler | 1 - *----------------------------------------------------------------------------- - * APB1 Prescaler | 1 - *----------------------------------------------------------------------------- - * APB2 Prescaler | 1 - *----------------------------------------------------------------------------- - * PLL_M | 1 - *----------------------------------------------------------------------------- - * PLL_N | 16 - *----------------------------------------------------------------------------- - * PLL_P | 7 - *----------------------------------------------------------------------------- - * PLL_Q | 2 - *----------------------------------------------------------------------------- - * PLL_R | 2 - *----------------------------------------------------------------------------- - * Require 48MHz for RNG | Disabled - *----------------------------------------------------------------------------- - *============================================================================= - ****************************************************************************** - * @attention - * - * Copyright (c) 2019 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ + ****************************************************************************** + * @file system_stm32g4xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32g4xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32g4xx.s" file, to + * configure the system clock before to branch to main program. + * + * This file configures the system clock as follows: + *============================================================================= + *----------------------------------------------------------------------------- + * System Clock source | HSI + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 16000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 16000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 1 + *----------------------------------------------------------------------------- + * PLL_M | 1 + *----------------------------------------------------------------------------- + * PLL_N | 16 + *----------------------------------------------------------------------------- + * PLL_P | 7 + *----------------------------------------------------------------------------- + * PLL_Q | 2 + *----------------------------------------------------------------------------- + * PLL_R | 2 + *----------------------------------------------------------------------------- + * Require 48MHz for RNG | Disabled + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ /** @addtogroup CMSIS - * @{ - */ + * @{ + */ /** @addtogroup stm32g4xx_system - * @{ - */ + * @{ + */ /** @addtogroup STM32G4xx_System_Private_Includes - * @{ - */ + * @{ + */ #include "stm32g4xx.h" -#if !defined (HSE_VALUE) - #define HSE_VALUE 24000000U /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ +#if !defined(HSE_VALUE) +#define HSE_VALUE 24000000U /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ -#if !defined (HSI_VALUE) - #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ +#if !defined(HSI_VALUE) +#define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ /** - * @} - */ + * @} + */ /** @addtogroup STM32G4xx_System_Private_TypesDefinitions - * @{ - */ + * @{ + */ /** - * @} - */ + * @} + */ /** @addtogroup STM32G4xx_System_Private_Defines - * @{ - */ + * @{ + */ /************************* Miscellaneous Configuration ************************/ /* Note: Following vector table addresses must be defined in line with linker - configuration. */ + configuration. */ /*!< Uncomment the following line if you need to relocate the vector table anywhere in Flash or Sram, else the vector table is kept at the automatic remap of boot address selected */ @@ -114,174 +114,172 @@ in Sram else user remap will be done in Flash. */ /* #define VECT_TAB_SRAM */ #if defined(VECT_TAB_SRAM) -#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x200. */ +#define VECT_TAB_BASE_ADDRESS \ + SRAM_BASE /*!< Vector Table base address field. \ + This value must be a multiple of 0x200. */ #else -#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x200. */ -#endif /* VECT_TAB_SRAM */ +#define VECT_TAB_BASE_ADDRESS \ + FLASH_BASE /*!< Vector Table base address field. \ + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_SRAM */ #if !defined(VECT_TAB_OFFSET) -#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table offset field. - This value must be a multiple of 0x200. */ -#endif /* VECT_TAB_OFFSET */ +#define VECT_TAB_OFFSET \ + 0x00000000U /*!< Vector Table offset field. \ + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_OFFSET */ #endif /* USER_VECT_TAB_ADDRESS */ -/******************************************************************************/ -/** - * @} - */ + /******************************************************************************/ + /** + * @} + */ /** @addtogroup STM32G4xx_System_Private_Macros - * @{ - */ + * @{ + */ /** - * @} - */ + * @} + */ /** @addtogroup STM32G4xx_System_Private_Variables - * @{ - */ - /* The SystemCoreClock variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetHCLKFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ - uint32_t SystemCoreClock = HSI_VALUE; - - const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; - const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; + * @{ + */ +/* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. +*/ +uint32_t SystemCoreClock = HSI_VALUE; + +const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; +const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; /** - * @} - */ + * @} + */ /** @addtogroup STM32G4xx_System_Private_FunctionPrototypes - * @{ - */ + * @{ + */ /** - * @} - */ + * @} + */ /** @addtogroup STM32G4xx_System_Private_Functions - * @{ - */ + * @{ + */ /** - * @brief Setup the microcontroller system. - * @param None - * @retval None - */ + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ void SystemInit(void) { - /* FPU settings ------------------------------------------------------------*/ - #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ - #endif +/* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << (10 * 2)) | (3UL << (11 * 2))); /* set CP10 and CP11 Full Access */ +#endif - /* Configure the Vector Table location add offset address ------------------*/ + /* Configure the Vector Table location add offset address ------------------*/ #if defined(USER_VECT_TAB_ADDRESS) - SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#endif /* USER_VECT_TAB_ADDRESS */ + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ } /** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * - * (**) HSI_VALUE is a constant defined in stm32g4xx_hal.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (***) HSE_VALUE is a constant defined in stm32g4xx_hal.h file (default value - * 24 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param None - * @retval None - */ + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (**) HSI_VALUE is a constant defined in stm32g4xx_hal.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in stm32g4xx_hal.h file (default value + * 24 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ void SystemCoreClockUpdate(void) { - uint32_t tmp, pllvco, pllr, pllsource, pllm; - - /* Get SYSCLK source -------------------------------------------------------*/ - switch (RCC->CFGR & RCC_CFGR_SWS) - { - case 0x04: /* HSI used as system clock source */ - SystemCoreClock = HSI_VALUE; - break; - - case 0x08: /* HSE used as system clock source */ - SystemCoreClock = HSE_VALUE; - break; - - case 0x0C: /* PLL used as system clock source */ - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN - SYSCLK = PLL_VCO / PLLR - */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); - pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1U ; - if (pllsource == 0x02UL) /* HSI used as PLL clock source */ - { - pllvco = (HSI_VALUE / pllm); - } - else /* HSE used as PLL clock source */ - { - pllvco = (HSE_VALUE / pllm); - } - pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8); - pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U; - SystemCoreClock = pllvco/pllr; - break; - - default: - break; - } - /* Compute HCLK clock frequency --------------------------------------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK clock frequency */ - SystemCoreClock >>= tmp; + uint32_t tmp, pllvco, pllr, pllsource, pllm; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) { + case 0x04: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + + case 0x08: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + + case 0x0C: /* PLL used as system clock source */ + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); + pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1U; + if (pllsource == 0x02UL) /* HSI used as PLL clock source */ + { + pllvco = (HSI_VALUE / pllm); + } else /* HSE used as PLL clock source */ + { + pllvco = (HSE_VALUE / pllm); + } + pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8); + pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U; + SystemCoreClock = pllvco / pllr; + break; + + default: + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; } - /** - * @} - */ + * @} + */ /** - * @} - */ + * @} + */ /** - * @} - */ - - + * @} + */ From d987b58619c1e6ac5fb9f1e0a216242fe061aeaa Mon Sep 17 00:00:00 2001 From: github-actions <41898282+github-actions[bot]@users.noreply.github.com> Date: Sun, 23 Aug 2026 23:53:10 +0000 Subject: [PATCH 16/17] Automatic Assembly Format: Standardized formatting automatically --- .../NucleoG4-Hello/startup_stm32g474xx.s | 676 +++++++++--------- 1 file changed, 340 insertions(+), 336 deletions(-) diff --git a/Testbench/NucleoG4-Hello/startup_stm32g474xx.s b/Testbench/NucleoG4-Hello/startup_stm32g474xx.s index e7a2c61fc..31cf98b7f 100644 --- a/Testbench/NucleoG4-Hello/startup_stm32g474xx.s +++ b/Testbench/NucleoG4-Hello/startup_stm32g474xx.s @@ -1,592 +1,596 @@ -/** - ****************************************************************************** - * @file startup_stm32g474xx.s - * @author MCD Application Team - * @brief STM32G474xx devices vector table GCC toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address, - * - Configure the clock system - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M4 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - * Copyright (c) 2019 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m4 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler +/* * + ****************************************************************************** + * @file startup_stm32g474xx.s + * @author MCD Application Team + * @brief STM32G474xx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +.syntax unified +.cpu cortex-m4 +.fpu softvfp +.thumb + +.global g_pfnVectors +.global Default_Handler /* start address for the initialization values of the .data section. defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss - -.equ BootRAM, 0xF1E0F85F -/** +.word _sidata + +// start address for the .data section. defined in linker script +.word _sdata + +// end address for the .data section. defined in linker script +.word _edata + +// start address for the .bss section. defined in linker script +.word _sbss + +// end address for the .bss section. defined in linker script +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/* * * @brief This is the code that gets called when the processor first * starts execution following a reset event. Only the absolutely * necessary set is performed, after which the application * supplied main() routine is called. * @param None * @retval : None -*/ + */ + +.section .text.Reset_Handler +.weak Reset_Handler +.type Reset_Handler, %function - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function Reset_Handler: - ldr r0, =_estack - mov sp, r0 /* set stack pointer */ + ldr r0, =_estack + mov sp, r0 // set stack pointer -/* Call the clock system initialization function.*/ - bl SystemInit + // Call the clock system initialization function. + bl SystemInit -/* Copy the data segment initializers from flash to SRAM */ - ldr r0, =_sdata - ldr r1, =_edata - ldr r2, =_sidata - movs r3, #0 - b LoopCopyDataInit + // Copy the data segment initializers from flash to SRAM + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit CopyDataInit: - ldr r4, [r2, r3] - str r4, [r0, r3] - adds r3, r3, #4 + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 LoopCopyDataInit: - adds r4, r0, r3 - cmp r4, r1 - bcc CopyDataInit - -/* Zero fill the bss segment. */ - ldr r2, =_sbss - ldr r4, =_ebss - movs r3, #0 - b LoopFillZerobss + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + + // Zero fill the bss segment. + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss FillZerobss: - str r3, [r2] - adds r2, r2, #4 + str r3, [r2] + adds r2, r2, #4 LoopFillZerobss: - cmp r2, r4 - bcc FillZerobss + cmp r2, r4 + bcc FillZerobss + + // Call static constructors + bl __libc_init_array -/* Call static constructors */ - bl __libc_init_array -/* Call the application's entry point.*/ - bl main + // Call the application's entry point. + bl main LoopForever: - b LoopForever + b LoopForever -.size Reset_Handler, .-Reset_Handler + .size Reset_Handler, .-Reset_Handler -/** +/* * * @brief This is the code that gets called when the processor receives an * unexpected interrupt. This simply enters an infinite loop, preserving * the system state for examination by a debugger. * * @param None * @retval : None -*/ - .section .text.Default_Handler,"ax",%progbits + */ + .section .text.Default_Handler, "ax", %progbits + Default_Handler: Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex-M4. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/* ***************************************************************************** + * + * The minimal vector table for a Cortex-M4. Note that the proper constructs + * must be placed on this to ensure that it ends up at physical address + * 0x0000.0000. + * +***************************************************************************** */ + .section .isr_vector, "a", %progbits + .type g_pfnVectors, %object g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler - .word PVD_PVM_IRQHandler - .word RTC_TAMP_LSECSS_IRQHandler - .word RTC_WKUP_IRQHandler - .word FLASH_IRQHandler - .word RCC_IRQHandler - .word EXTI0_IRQHandler - .word EXTI1_IRQHandler - .word EXTI2_IRQHandler - .word EXTI3_IRQHandler - .word EXTI4_IRQHandler - .word DMA1_Channel1_IRQHandler - .word DMA1_Channel2_IRQHandler - .word DMA1_Channel3_IRQHandler - .word DMA1_Channel4_IRQHandler - .word DMA1_Channel5_IRQHandler - .word DMA1_Channel6_IRQHandler - .word DMA1_Channel7_IRQHandler - .word ADC1_2_IRQHandler - .word USB_HP_IRQHandler - .word USB_LP_IRQHandler - .word FDCAN1_IT0_IRQHandler - .word FDCAN1_IT1_IRQHandler - .word EXTI9_5_IRQHandler - .word TIM1_BRK_TIM15_IRQHandler - .word TIM1_UP_TIM16_IRQHandler - .word TIM1_TRG_COM_TIM17_IRQHandler - .word TIM1_CC_IRQHandler - .word TIM2_IRQHandler - .word TIM3_IRQHandler - .word TIM4_IRQHandler - .word I2C1_EV_IRQHandler - .word I2C1_ER_IRQHandler - .word I2C2_EV_IRQHandler - .word I2C2_ER_IRQHandler - .word SPI1_IRQHandler - .word SPI2_IRQHandler - .word USART1_IRQHandler - .word USART2_IRQHandler - .word USART3_IRQHandler - .word EXTI15_10_IRQHandler - .word RTC_Alarm_IRQHandler - .word USBWakeUp_IRQHandler - .word TIM8_BRK_IRQHandler - .word TIM8_UP_IRQHandler - .word TIM8_TRG_COM_IRQHandler - .word TIM8_CC_IRQHandler - .word ADC3_IRQHandler - .word FMC_IRQHandler - .word LPTIM1_IRQHandler - .word TIM5_IRQHandler - .word SPI3_IRQHandler - .word UART4_IRQHandler - .word UART5_IRQHandler - .word TIM6_DAC_IRQHandler - .word TIM7_DAC_IRQHandler - .word DMA2_Channel1_IRQHandler - .word DMA2_Channel2_IRQHandler - .word DMA2_Channel3_IRQHandler - .word DMA2_Channel4_IRQHandler - .word DMA2_Channel5_IRQHandler - .word ADC4_IRQHandler - .word ADC5_IRQHandler - .word UCPD1_IRQHandler - .word COMP1_2_3_IRQHandler - .word COMP4_5_6_IRQHandler - .word COMP7_IRQHandler - .word HRTIM1_Master_IRQHandler - .word HRTIM1_TIMA_IRQHandler - .word HRTIM1_TIMB_IRQHandler - .word HRTIM1_TIMC_IRQHandler - .word HRTIM1_TIMD_IRQHandler - .word HRTIM1_TIME_IRQHandler - .word HRTIM1_FLT_IRQHandler - .word HRTIM1_TIMF_IRQHandler - .word CRS_IRQHandler - .word SAI1_IRQHandler - .word TIM20_BRK_IRQHandler - .word TIM20_UP_IRQHandler - .word TIM20_TRG_COM_IRQHandler - .word TIM20_CC_IRQHandler - .word FPU_IRQHandler - .word I2C4_EV_IRQHandler - .word I2C4_ER_IRQHandler - .word SPI4_IRQHandler - .word 0 - .word FDCAN2_IT0_IRQHandler - .word FDCAN2_IT1_IRQHandler - .word FDCAN3_IT0_IRQHandler - .word FDCAN3_IT1_IRQHandler - .word RNG_IRQHandler - .word LPUART1_IRQHandler - .word I2C3_EV_IRQHandler - .word I2C3_ER_IRQHandler - .word DMAMUX_OVR_IRQHandler - .word QUADSPI_IRQHandler - .word DMA1_Channel8_IRQHandler - .word DMA2_Channel6_IRQHandler - .word DMA2_Channel7_IRQHandler - .word DMA2_Channel8_IRQHandler - .word CORDIC_IRQHandler - .word FMAC_IRQHandler - - .size g_pfnVectors, .-g_pfnVectors - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - .weak NMI_Handler + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_PVM_IRQHandler + .word RTC_TAMP_LSECSS_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_IRQHandler + .word USB_LP_IRQHandler + .word FDCAN1_IT0_IRQHandler + .word FDCAN1_IT1_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word USBWakeUp_IRQHandler + .word TIM8_BRK_IRQHandler + .word TIM8_UP_IRQHandler + .word TIM8_TRG_COM_IRQHandler + .word TIM8_CC_IRQHandler + .word ADC3_IRQHandler + .word FMC_IRQHandler + .word LPTIM1_IRQHandler + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_DAC_IRQHandler + .word TIM7_DAC_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word ADC4_IRQHandler + .word ADC5_IRQHandler + .word UCPD1_IRQHandler + .word COMP1_2_3_IRQHandler + .word COMP4_5_6_IRQHandler + .word COMP7_IRQHandler + .word HRTIM1_Master_IRQHandler + .word HRTIM1_TIMA_IRQHandler + .word HRTIM1_TIMB_IRQHandler + .word HRTIM1_TIMC_IRQHandler + .word HRTIM1_TIMD_IRQHandler + .word HRTIM1_TIME_IRQHandler + .word HRTIM1_FLT_IRQHandler + .word HRTIM1_TIMF_IRQHandler + .word CRS_IRQHandler + .word SAI1_IRQHandler + .word TIM20_BRK_IRQHandler + .word TIM20_UP_IRQHandler + .word TIM20_TRG_COM_IRQHandler + .word TIM20_CC_IRQHandler + .word FPU_IRQHandler + .word I2C4_EV_IRQHandler + .word I2C4_ER_IRQHandler + .word SPI4_IRQHandler + .word 0 + .word FDCAN2_IT0_IRQHandler + .word FDCAN2_IT1_IRQHandler + .word FDCAN3_IT0_IRQHandler + .word FDCAN3_IT1_IRQHandler + .word RNG_IRQHandler + .word LPUART1_IRQHandler + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word DMAMUX_OVR_IRQHandler + .word QUADSPI_IRQHandler + .word DMA1_Channel8_IRQHandler + .word DMA2_Channel6_IRQHandler + .word DMA2_Channel7_IRQHandler + .word DMA2_Channel8_IRQHandler + .word CORDIC_IRQHandler + .word FMAC_IRQHandler + + .size g_pfnVectors, .-g_pfnVectors + +/* ****************************************************************************** + * + * Provide weak aliases for each Exception handler to the Default_Handler. + * As they are weak aliases, any function with the same name will override + * this definition. + * +****************************************************************************** */ + .weak NMI_Handler .thumb_set NMI_Handler,Default_Handler - .weak HardFault_Handler + .weak HardFault_Handler .thumb_set HardFault_Handler,Default_Handler - .weak MemManage_Handler + .weak MemManage_Handler .thumb_set MemManage_Handler,Default_Handler - .weak BusFault_Handler + .weak BusFault_Handler .thumb_set BusFault_Handler,Default_Handler - .weak UsageFault_Handler + .weak UsageFault_Handler .thumb_set UsageFault_Handler,Default_Handler - .weak SVC_Handler + .weak SVC_Handler .thumb_set SVC_Handler,Default_Handler - .weak DebugMon_Handler + .weak DebugMon_Handler .thumb_set DebugMon_Handler,Default_Handler - .weak PendSV_Handler + .weak PendSV_Handler .thumb_set PendSV_Handler,Default_Handler - .weak SysTick_Handler + .weak SysTick_Handler .thumb_set SysTick_Handler,Default_Handler - .weak WWDG_IRQHandler + .weak WWDG_IRQHandler .thumb_set WWDG_IRQHandler,Default_Handler - .weak PVD_PVM_IRQHandler + .weak PVD_PVM_IRQHandler .thumb_set PVD_PVM_IRQHandler,Default_Handler - .weak RTC_TAMP_LSECSS_IRQHandler + .weak RTC_TAMP_LSECSS_IRQHandler .thumb_set RTC_TAMP_LSECSS_IRQHandler,Default_Handler - .weak RTC_WKUP_IRQHandler + .weak RTC_WKUP_IRQHandler .thumb_set RTC_WKUP_IRQHandler,Default_Handler - .weak FLASH_IRQHandler + .weak FLASH_IRQHandler .thumb_set FLASH_IRQHandler,Default_Handler - .weak RCC_IRQHandler + .weak RCC_IRQHandler .thumb_set RCC_IRQHandler,Default_Handler - .weak EXTI0_IRQHandler + .weak EXTI0_IRQHandler .thumb_set EXTI0_IRQHandler,Default_Handler - .weak EXTI1_IRQHandler + .weak EXTI1_IRQHandler .thumb_set EXTI1_IRQHandler,Default_Handler - .weak EXTI2_IRQHandler + .weak EXTI2_IRQHandler .thumb_set EXTI2_IRQHandler,Default_Handler - .weak EXTI3_IRQHandler + .weak EXTI3_IRQHandler .thumb_set EXTI3_IRQHandler,Default_Handler - .weak EXTI4_IRQHandler + .weak EXTI4_IRQHandler .thumb_set EXTI4_IRQHandler,Default_Handler - .weak DMA1_Channel1_IRQHandler + .weak DMA1_Channel1_IRQHandler .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - .weak DMA1_Channel2_IRQHandler + .weak DMA1_Channel2_IRQHandler .thumb_set DMA1_Channel2_IRQHandler,Default_Handler - .weak DMA1_Channel3_IRQHandler + .weak DMA1_Channel3_IRQHandler .thumb_set DMA1_Channel3_IRQHandler,Default_Handler - .weak DMA1_Channel4_IRQHandler + .weak DMA1_Channel4_IRQHandler .thumb_set DMA1_Channel4_IRQHandler,Default_Handler - .weak DMA1_Channel5_IRQHandler + .weak DMA1_Channel5_IRQHandler .thumb_set DMA1_Channel5_IRQHandler,Default_Handler - .weak DMA1_Channel6_IRQHandler + .weak DMA1_Channel6_IRQHandler .thumb_set DMA1_Channel6_IRQHandler,Default_Handler - .weak DMA1_Channel7_IRQHandler + .weak DMA1_Channel7_IRQHandler .thumb_set DMA1_Channel7_IRQHandler,Default_Handler - .weak ADC1_2_IRQHandler + .weak ADC1_2_IRQHandler .thumb_set ADC1_2_IRQHandler,Default_Handler - .weak USB_HP_IRQHandler + .weak USB_HP_IRQHandler .thumb_set USB_HP_IRQHandler,Default_Handler - .weak USB_LP_IRQHandler + .weak USB_LP_IRQHandler .thumb_set USB_LP_IRQHandler,Default_Handler - .weak FDCAN1_IT0_IRQHandler + .weak FDCAN1_IT0_IRQHandler .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler - .weak FDCAN1_IT1_IRQHandler + .weak FDCAN1_IT1_IRQHandler .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler - .weak EXTI9_5_IRQHandler + .weak EXTI9_5_IRQHandler .thumb_set EXTI9_5_IRQHandler,Default_Handler - .weak TIM1_BRK_TIM15_IRQHandler + .weak TIM1_BRK_TIM15_IRQHandler .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler - .weak TIM1_UP_TIM16_IRQHandler + .weak TIM1_UP_TIM16_IRQHandler .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler - .weak TIM1_TRG_COM_TIM17_IRQHandler + .weak TIM1_TRG_COM_TIM17_IRQHandler .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler - .weak TIM1_CC_IRQHandler + .weak TIM1_CC_IRQHandler .thumb_set TIM1_CC_IRQHandler,Default_Handler - .weak TIM2_IRQHandler + .weak TIM2_IRQHandler .thumb_set TIM2_IRQHandler,Default_Handler - .weak TIM3_IRQHandler + .weak TIM3_IRQHandler .thumb_set TIM3_IRQHandler,Default_Handler - .weak TIM4_IRQHandler + .weak TIM4_IRQHandler .thumb_set TIM4_IRQHandler,Default_Handler - .weak I2C1_EV_IRQHandler + .weak I2C1_EV_IRQHandler .thumb_set I2C1_EV_IRQHandler,Default_Handler - .weak I2C1_ER_IRQHandler + .weak I2C1_ER_IRQHandler .thumb_set I2C1_ER_IRQHandler,Default_Handler - .weak I2C2_EV_IRQHandler + .weak I2C2_EV_IRQHandler .thumb_set I2C2_EV_IRQHandler,Default_Handler - .weak I2C2_ER_IRQHandler + .weak I2C2_ER_IRQHandler .thumb_set I2C2_ER_IRQHandler,Default_Handler - .weak SPI1_IRQHandler + .weak SPI1_IRQHandler .thumb_set SPI1_IRQHandler,Default_Handler - .weak SPI2_IRQHandler + .weak SPI2_IRQHandler .thumb_set SPI2_IRQHandler,Default_Handler - .weak USART1_IRQHandler + .weak USART1_IRQHandler .thumb_set USART1_IRQHandler,Default_Handler - .weak USART2_IRQHandler + .weak USART2_IRQHandler .thumb_set USART2_IRQHandler,Default_Handler - .weak USART3_IRQHandler + .weak USART3_IRQHandler .thumb_set USART3_IRQHandler,Default_Handler - .weak EXTI15_10_IRQHandler + .weak EXTI15_10_IRQHandler .thumb_set EXTI15_10_IRQHandler,Default_Handler - .weak RTC_Alarm_IRQHandler + .weak RTC_Alarm_IRQHandler .thumb_set RTC_Alarm_IRQHandler,Default_Handler - .weak USBWakeUp_IRQHandler + .weak USBWakeUp_IRQHandler .thumb_set USBWakeUp_IRQHandler,Default_Handler - .weak TIM8_BRK_IRQHandler + .weak TIM8_BRK_IRQHandler .thumb_set TIM8_BRK_IRQHandler,Default_Handler - .weak TIM8_UP_IRQHandler + .weak TIM8_UP_IRQHandler .thumb_set TIM8_UP_IRQHandler,Default_Handler - .weak TIM8_TRG_COM_IRQHandler + .weak TIM8_TRG_COM_IRQHandler .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler - .weak TIM8_CC_IRQHandler + .weak TIM8_CC_IRQHandler .thumb_set TIM8_CC_IRQHandler,Default_Handler - .weak ADC3_IRQHandler + .weak ADC3_IRQHandler .thumb_set ADC3_IRQHandler,Default_Handler - .weak FMC_IRQHandler + .weak FMC_IRQHandler .thumb_set FMC_IRQHandler,Default_Handler - .weak LPTIM1_IRQHandler + .weak LPTIM1_IRQHandler .thumb_set LPTIM1_IRQHandler,Default_Handler - .weak TIM5_IRQHandler + .weak TIM5_IRQHandler .thumb_set TIM5_IRQHandler,Default_Handler - .weak SPI3_IRQHandler + .weak SPI3_IRQHandler .thumb_set SPI3_IRQHandler,Default_Handler - .weak UART4_IRQHandler + .weak UART4_IRQHandler .thumb_set UART4_IRQHandler,Default_Handler - .weak UART5_IRQHandler + .weak UART5_IRQHandler .thumb_set UART5_IRQHandler,Default_Handler - .weak TIM6_DAC_IRQHandler + .weak TIM6_DAC_IRQHandler .thumb_set TIM6_DAC_IRQHandler,Default_Handler - .weak TIM7_DAC_IRQHandler + .weak TIM7_DAC_IRQHandler .thumb_set TIM7_DAC_IRQHandler,Default_Handler - .weak DMA2_Channel1_IRQHandler + .weak DMA2_Channel1_IRQHandler .thumb_set DMA2_Channel1_IRQHandler,Default_Handler - .weak DMA2_Channel2_IRQHandler + .weak DMA2_Channel2_IRQHandler .thumb_set DMA2_Channel2_IRQHandler,Default_Handler - .weak DMA2_Channel3_IRQHandler + .weak DMA2_Channel3_IRQHandler .thumb_set DMA2_Channel3_IRQHandler,Default_Handler - .weak DMA2_Channel4_IRQHandler + .weak DMA2_Channel4_IRQHandler .thumb_set DMA2_Channel4_IRQHandler,Default_Handler - .weak DMA2_Channel5_IRQHandler + .weak DMA2_Channel5_IRQHandler .thumb_set DMA2_Channel5_IRQHandler,Default_Handler - .weak ADC4_IRQHandler + .weak ADC4_IRQHandler .thumb_set ADC4_IRQHandler,Default_Handler - .weak ADC5_IRQHandler + .weak ADC5_IRQHandler .thumb_set ADC5_IRQHandler,Default_Handler - .weak UCPD1_IRQHandler + .weak UCPD1_IRQHandler .thumb_set UCPD1_IRQHandler,Default_Handler - .weak COMP1_2_3_IRQHandler + .weak COMP1_2_3_IRQHandler .thumb_set COMP1_2_3_IRQHandler,Default_Handler - .weak COMP4_5_6_IRQHandler + .weak COMP4_5_6_IRQHandler .thumb_set COMP4_5_6_IRQHandler,Default_Handler - .weak COMP7_IRQHandler + .weak COMP7_IRQHandler .thumb_set COMP7_IRQHandler,Default_Handler - .weak HRTIM1_Master_IRQHandler + .weak HRTIM1_Master_IRQHandler .thumb_set HRTIM1_Master_IRQHandler,Default_Handler - .weak HRTIM1_TIMA_IRQHandler + .weak HRTIM1_TIMA_IRQHandler .thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler - .weak HRTIM1_TIMB_IRQHandler + .weak HRTIM1_TIMB_IRQHandler .thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler - .weak HRTIM1_TIMC_IRQHandler + .weak HRTIM1_TIMC_IRQHandler .thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler - .weak HRTIM1_TIMD_IRQHandler + .weak HRTIM1_TIMD_IRQHandler .thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler - .weak HRTIM1_TIME_IRQHandler + .weak HRTIM1_TIME_IRQHandler .thumb_set HRTIM1_TIME_IRQHandler,Default_Handler - .weak HRTIM1_FLT_IRQHandler + .weak HRTIM1_FLT_IRQHandler .thumb_set HRTIM1_FLT_IRQHandler,Default_Handler - .weak HRTIM1_TIMF_IRQHandler + .weak HRTIM1_TIMF_IRQHandler .thumb_set HRTIM1_TIMF_IRQHandler,Default_Handler - .weak CRS_IRQHandler + .weak CRS_IRQHandler .thumb_set CRS_IRQHandler,Default_Handler - .weak SAI1_IRQHandler + .weak SAI1_IRQHandler .thumb_set SAI1_IRQHandler,Default_Handler - .weak TIM20_BRK_IRQHandler + .weak TIM20_BRK_IRQHandler .thumb_set TIM20_BRK_IRQHandler,Default_Handler - .weak TIM20_UP_IRQHandler + .weak TIM20_UP_IRQHandler .thumb_set TIM20_UP_IRQHandler,Default_Handler - .weak TIM20_TRG_COM_IRQHandler + .weak TIM20_TRG_COM_IRQHandler .thumb_set TIM20_TRG_COM_IRQHandler,Default_Handler - .weak TIM20_CC_IRQHandler + .weak TIM20_CC_IRQHandler .thumb_set TIM20_CC_IRQHandler,Default_Handler - .weak FPU_IRQHandler + .weak FPU_IRQHandler .thumb_set FPU_IRQHandler,Default_Handler - .weak I2C4_EV_IRQHandler + .weak I2C4_EV_IRQHandler .thumb_set I2C4_EV_IRQHandler,Default_Handler - .weak I2C4_ER_IRQHandler + .weak I2C4_ER_IRQHandler .thumb_set I2C4_ER_IRQHandler,Default_Handler - .weak SPI4_IRQHandler + .weak SPI4_IRQHandler .thumb_set SPI4_IRQHandler,Default_Handler - .weak FDCAN2_IT0_IRQHandler + .weak FDCAN2_IT0_IRQHandler .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler - .weak FDCAN2_IT1_IRQHandler + .weak FDCAN2_IT1_IRQHandler .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler - .weak FDCAN3_IT0_IRQHandler + .weak FDCAN3_IT0_IRQHandler .thumb_set FDCAN3_IT0_IRQHandler,Default_Handler - .weak FDCAN3_IT1_IRQHandler + .weak FDCAN3_IT1_IRQHandler .thumb_set FDCAN3_IT1_IRQHandler,Default_Handler - .weak RNG_IRQHandler + .weak RNG_IRQHandler .thumb_set RNG_IRQHandler,Default_Handler - .weak LPUART1_IRQHandler + .weak LPUART1_IRQHandler .thumb_set LPUART1_IRQHandler,Default_Handler - .weak I2C3_EV_IRQHandler + .weak I2C3_EV_IRQHandler .thumb_set I2C3_EV_IRQHandler,Default_Handler - .weak I2C3_ER_IRQHandler + .weak I2C3_ER_IRQHandler .thumb_set I2C3_ER_IRQHandler,Default_Handler - .weak DMAMUX_OVR_IRQHandler + .weak DMAMUX_OVR_IRQHandler .thumb_set DMAMUX_OVR_IRQHandler,Default_Handler - .weak QUADSPI_IRQHandler + .weak QUADSPI_IRQHandler .thumb_set QUADSPI_IRQHandler,Default_Handler - .weak DMA1_Channel8_IRQHandler + .weak DMA1_Channel8_IRQHandler .thumb_set DMA1_Channel8_IRQHandler,Default_Handler - .weak DMA2_Channel6_IRQHandler + .weak DMA2_Channel6_IRQHandler .thumb_set DMA2_Channel6_IRQHandler,Default_Handler - .weak DMA2_Channel7_IRQHandler + .weak DMA2_Channel7_IRQHandler .thumb_set DMA2_Channel7_IRQHandler,Default_Handler - .weak DMA2_Channel8_IRQHandler + .weak DMA2_Channel8_IRQHandler .thumb_set DMA2_Channel8_IRQHandler,Default_Handler - .weak CORDIC_IRQHandler + .weak CORDIC_IRQHandler .thumb_set CORDIC_IRQHandler,Default_Handler - .weak FMAC_IRQHandler + .weak FMAC_IRQHandler .thumb_set FMAC_IRQHandler,Default_Handler From 3866243e3a42b2a2b99666c2d629c0c11c1bbd73 Mon Sep 17 00:00:00 2001 From: Daniel Hansen Date: Tue, 25 Aug 2026 00:45:14 -0700 Subject: [PATCH 17/17] Checkpoint in progress Signed-off-by: Daniel Hansen --- .vscode/launch.json | 151 +- .vscode/settings.json | 2 +- .vscode/tasks.json | 27 + Lib/Vendor/SVD/README.md | 13 + Lib/Vendor/SVD/STM32G431.svd | 50458 ++++++ Lib/Vendor/SVD/STM32G474.svd | 63342 +++++++ Lib/Vendor/SVD/STM32H523.svd | 175071 +++++++++++++++++++ Lib/Vendor/SVD/STM32L476.svd | 56176 ++++++ Lib/Vendor/SVD/STM32U5A9.svd | 295938 ++++++++++++++++++++++++++++++++ 9 files changed, 641155 insertions(+), 23 deletions(-) create mode 100644 Lib/Vendor/SVD/README.md create mode 100644 Lib/Vendor/SVD/STM32G431.svd create mode 100644 Lib/Vendor/SVD/STM32G474.svd create mode 100644 Lib/Vendor/SVD/STM32H523.svd create mode 100644 Lib/Vendor/SVD/STM32L476.svd create mode 100644 Lib/Vendor/SVD/STM32U5A9.svd diff --git a/.vscode/launch.json b/.vscode/launch.json index 101ae7491..d5559fff1 100644 --- a/.vscode/launch.json +++ b/.vscode/launch.json @@ -1,6 +1,89 @@ { "version": "0.2.0", "configurations": [ + { + "cwd": "${workspaceFolder}", + "executable": "${command:cmake.buildDirectory}/NucleoG4-Blinky.elf", + "name": "NucleoG4-Blinky", + "request": "launch", + "type": "cortex-debug", + "servertype": "openocd", + "configFiles": [ + "interface/stlink.cfg", + "target/stm32g4x.cfg" + ], + "searchDir": [], + "preLaunchTask": "CMake: configure and build NucleoG4-Blinky", + "showDevDebugOutput": "raw", + "svdPath": "${workspaceFolder}/Lib/Vendor/SVD/STM32G474.svd", + "openOCDLaunchCommands": [ + "reset_config srst_only separate connect_assert_srst", + ], + "runToEntryPoint": "main", + "showDevDebugTimestamps": true + }, + { + "cwd": "${workspaceFolder}", + "executable": "${command:cmake.buildDirectory}/NucleoG4-Hello.elf", + "name": "NucleoG4-Hello", + "request": "launch", + "type": "cortex-debug", + "servertype": "openocd", + "configFiles": [ + "interface/stlink.cfg", + "target/stm32g4x.cfg" + ], + "searchDir": [], + "preLaunchTask": "CMake: configure and build NucleoG4-Hello", + "showDevDebugOutput": "raw", + "svdPath": "${workspaceFolder}/Lib/Vendor/SVD/STM32G474.svd", + "swoConfig": { + "enabled": true, + "cpuFrequency": 160000000, + "swoFrequency": 2000000, + "source": "probe", + "decoders": [ + { + "type": "console", + "label": "ITM", + "showOnStartup": true, + "port": 0, + "encoding": "ascii" + } + ] + } + }, + { + "cwd": "${workspaceFolder}", + "executable": "${command:cmake.buildDirectory}/NucleoG4-Echo.elf", + "name": "NucleoG4-Echo", + "request": "launch", + "type": "cortex-debug", + "servertype": "openocd", + "configFiles": [ + "interface/stlink.cfg", + "target/stm32g4x.cfg" + ], + "searchDir": [], + "preLaunchTask": "CMake: configure and build NucleoG4-Echo", + "showDevDebugOutput": "raw", + "svdPath": "${workspaceFolder}/Lib/Vendor/SVD/STM32G474.svd", + "swoConfig": { + "enabled": true, + "cpuFrequency": 160000000, + "swoFrequency": 2000000, + "source": "probe", + "decoders": [ + { + "type": "console", + "label": "ITM", + "showOnStartup": true, + "port": 0, + "encoding": "ascii" + } + ] + } + }, { "cwd": "${workspaceFolder}", "executable": "${command:cmake.buildDirectory}/ECU.elf", @@ -15,7 +98,7 @@ "searchDir": [], "preLaunchTask": "CMake: configure and build ECU", "showDevDebugOutput": "raw", - "svdPath": "${workspaceFolder}/Lib/Vendor/CMSIS_5/SVD/STM32G474.svd", + "svdPath": "${workspaceFolder}/Lib/Vendor/SVD/STM32G474.svd", "swoConfig": { "enabled": true, "cpuFrequency": 160000000, @@ -46,7 +129,7 @@ "searchDir": [], "preLaunchTask": "CMake: configure and build CUBEMXTESTING", "showDevDebugOutput": "raw", - "svdPath": "${workspaceFolder}/Lib/Vendor/CMSIS_5/SVD/STM32G474.svd", + "svdPath": "${workspaceFolder}/Lib/Vendor/SVD/STM32G474.svd", "swoConfig": { "enabled": true, "cpuFrequency": 160000000, @@ -77,7 +160,7 @@ "searchDir": [], "preLaunchTask": "CMake: configure and build CCU", "showDevDebugOutput": "raw", - "svdPath": "${workspaceFolder}/Lib/Vendor/CMSIS_5/SVD/STM32G474.svd", + "svdPath": "${workspaceFolder}/Lib/Vendor/SVD/STM32G474.svd", "swoConfig": { "enabled": true, "cpuFrequency": 170000000, @@ -108,7 +191,7 @@ "searchDir": [], "preLaunchTask": "CMake: configure and build DashPanel", "showDevDebugOutput": "raw", - "svdPath": "${workspaceFolder}/Lib/Vendor/CMSIS_5/SVD/STM32G474.svd", + "svdPath": "${workspaceFolder}/Lib/Vendor/SVD/STM32G474.svd", "swoConfig": { "enabled": true, "cpuFrequency": 170000000, @@ -139,7 +222,7 @@ "searchDir": [], "preLaunchTask": "CMake: configure and build CANine", "showDevDebugOutput": "raw", - "svdPath": "${workspaceFolder}/Lib/Vendor/CMSIS_5/SVD/STM32G474.svd", + "svdPath": "${workspaceFolder}/Lib/Vendor/SVD/STM32G474.svd", "swoConfig": { "enabled": true, "cpuFrequency": 170000000, @@ -170,7 +253,7 @@ "searchDir": [], "preLaunchTask": "CMake: configure and build TireTemp FL", "showDevDebugOutput": "raw", - "svdPath": "${workspaceFolder}/Lib/Vendor/CMSIS_5/SVD/STM32G431.svd", + "svdPath": "${workspaceFolder}/Lib/Vendor/SVD/STM32G431.svd", "swoConfig": { "enabled": true, "cpuFrequency": 160000000, @@ -201,7 +284,7 @@ "searchDir": [], "preLaunchTask": "CMake: configure and build TireTemp FR", "showDevDebugOutput": "raw", - "svdPath": "${workspaceFolder}/Lib/Vendor/CMSIS_5/SVD/STM32G431.svd", + "svdPath": "${workspaceFolder}/Lib/Vendor/SVD/STM32G431.svd", "swoConfig": { "enabled": true, "cpuFrequency": 160000000, @@ -232,7 +315,7 @@ "searchDir": [], "preLaunchTask": "CMake: configure and build TireTemp RL", "showDevDebugOutput": "raw", - "svdPath": "${workspaceFolder}/Lib/Vendor/CMSIS_5/SVD/STM32G431.svd", + "svdPath": "${workspaceFolder}/Lib/Vendor/SVD/STM32G431.svd", "swoConfig": { "enabled": true, "cpuFrequency": 160000000, @@ -263,7 +346,7 @@ "searchDir": [], "preLaunchTask": "CMake: configure and build TireTemp RR", "showDevDebugOutput": "raw", - "svdPath": "${workspaceFolder}/Lib/Vendor/CMSIS_5/SVD/STM32G431.svd", + "svdPath": "${workspaceFolder}/Lib/Vendor/SVD/STM32G431.svd", "swoConfig": { "enabled": true, "cpuFrequency": 160000000, @@ -294,7 +377,7 @@ "searchDir": [], "preLaunchTask": "CMake: configure and build BrakeTemp FL", "showDevDebugOutput": "raw", - "svdPath": "${workspaceFolder}/Lib/Vendor/CMSIS_5/SVD/STM32G431.svd", + "svdPath": "${workspaceFolder}/Lib/Vendor/SVD/STM32G431.svd", "swoConfig": { "enabled": true, "cpuFrequency": 160000000, @@ -325,7 +408,7 @@ "searchDir": [], "preLaunchTask": "CMake: configure and build BrakeTemp FR", "showDevDebugOutput": "raw", - "svdPath": "${workspaceFolder}/Lib/Vendor/CMSIS_5/SVD/STM32G431.svd", + "svdPath": "${workspaceFolder}/Lib/Vendor/SVD/STM32G431.svd", "swoConfig": { "enabled": true, "cpuFrequency": 160000000, @@ -356,7 +439,7 @@ "searchDir": [], "preLaunchTask": "CMake: configure and build BrakeTemp RL", "showDevDebugOutput": "raw", - "svdPath": "${workspaceFolder}/Lib/Vendor/CMSIS_5/SVD/STM32G431.svd", + "svdPath": "${workspaceFolder}/Lib/Vendor/SVD/STM32G431.svd", "swoConfig": { "enabled": true, "cpuFrequency": 160000000, @@ -387,7 +470,7 @@ "searchDir": [], "preLaunchTask": "CMake: configure and build BrakeTemp RR", "showDevDebugOutput": "raw", - "svdPath": "${workspaceFolder}/Lib/Vendor/CMSIS_5/SVD/STM32G431.svd", + "svdPath": "${workspaceFolder}/Lib/Vendor/SVD/STM32G431.svd", "swoConfig": { "enabled": true, "cpuFrequency": 160000000, @@ -418,7 +501,7 @@ "searchDir": [], "preLaunchTask": "CMake: configure and build G4HELLO", "showDevDebugOutput": "raw", - "svdPath": "${workspaceFolder}/Lib/Vendor/CMSIS_5/SVD/STM32G474.svd", + "svdPath": "${workspaceFolder}/Lib/Vendor/SVD/STM32G474.svd", "swoConfig": { "enabled": true, "cpuFrequency": 170000000, @@ -449,7 +532,7 @@ "searchDir": [], "preLaunchTask": "CMake: configure and build G4ECHO", "showDevDebugOutput": "raw", - "svdPath": "${workspaceFolder}/Lib/Vendor/CMSIS_5/SVD/STM32G474.svd", + "svdPath": "${workspaceFolder}/Lib/Vendor/SVD/STM32G474.svd", "swoConfig": { "enabled": true, "cpuFrequency": 170000000, @@ -480,7 +563,7 @@ "searchDir": [], "preLaunchTask": "CMake: configure and build G4BLINKY", "showDevDebugOutput": "raw", - "svdPath": "${workspaceFolder}/Lib/Vendor/CMSIS_5/SVD/STM32G474.svd", + "svdPath": "${workspaceFolder}/Lib/Vendor/SVD/STM32G474.svd", "swoConfig": { "enabled": true, "cpuFrequency": 170000000, @@ -511,7 +594,7 @@ "searchDir": [], "preLaunchTask": "CMake: configure and build U5BLINKY", "showDevDebugOutput": "raw", - "svdPath": "${workspaceFolder}/Lib/Vendor/CMSIS_5/SVD/STM32U5A9.svd" + "svdPath": "${workspaceFolder}/Lib/Vendor/SVD/STM32U5A9.svd" }, { "cwd": "${workspaceFolder}", @@ -527,7 +610,7 @@ "searchDir": [], "preLaunchTask": "CMake: configure and build L4BLINKY", "showDevDebugOutput": "raw", - "svdPath": "${workspaceFolder}/Lib/Vendor/CMSIS_5/SVD/STM32L476.svd" + "svdPath": "${workspaceFolder}/Lib/Vendor/SVD/STM32L476.svd" }, { "cwd": "${workspaceFolder}", @@ -558,7 +641,7 @@ } ] }, - "svdPath": "${workspaceFolder}/Lib/Vendor/CMSIS_5/SVD/STM32L476.svd" + "svdPath": "${workspaceFolder}/Lib/Vendor/SVD/STM32L476.svd" }, { "cwd": "${workspaceFolder}", @@ -574,7 +657,7 @@ "searchDir": [], "preLaunchTask": "CMake: configure and build W3_G4SPI_Receive", "showDevDebugOutput": "raw", - "svdPath": "${workspaceFolder}/Lib/Vendor/CMSIS_5/SVD/STM32G474.svd" + "svdPath": "${workspaceFolder}/Lib/Vendor/SVD/STM32G474.svd" }, { "cwd": "${workspaceFolder}", @@ -590,7 +673,7 @@ "searchDir": [], "preLaunchTask": "CMake: configure and build W3_G4SPI_Transmit", "showDevDebugOutput": "raw", - "svdPath": "${workspaceFolder}/Lib/Vendor/CMSIS_5/SVD/STM32G474.svd" + "svdPath": "${workspaceFolder}/Lib/Vendor/SVD/STM32G474.svd" }, { "cwd": "${workspaceFolder}", @@ -606,7 +689,7 @@ "searchDir": [], "preLaunchTask": "CMake: configure and build G4NEOTESTING", "showDevDebugOutput": "raw", - "svdPath": "${workspaceFolder}/Lib/Vendor/CMSIS_5/SVD/STM32G474.svd", + "svdPath": "${workspaceFolder}/Lib/Vendor/SVD/STM32G474.svd", "swoConfig": { "enabled": true, "cpuFrequency": 170000000, @@ -623,5 +706,29 @@ ] } } + ], + "inputs": [ + { + "id": "pickSeries", + "description": "Pick the series of the STM32 device to debug", + "type": "pickString", + "options": [ + "stm32g4x", + "stm32l4x", + "stm32u5x" + ], + }, + { + "id": "pickSvd", + "description": "Pick the SVD file for the STM32 device to debug", + "type": "pickString", + "options": [ + "STM32G431", + "STM32G474", + "STM32H523", + "STM32L476", + "STM32U5A9" + ], + } ] } diff --git a/.vscode/settings.json b/.vscode/settings.json index 90857164e..973827be5 100644 --- a/.vscode/settings.json +++ b/.vscode/settings.json @@ -24,5 +24,5 @@ "files.trimTrailingWhitespace": true, "files.eol": "\n", "cmake.useCMakePresets": "always", - "cortex-debug.variableUseNaturalFormat": true + "cortex-debug.variableUseNaturalFormat": false } diff --git a/.vscode/tasks.json b/.vscode/tasks.json index d3cb13330..482511eb7 100644 --- a/.vscode/tasks.json +++ b/.vscode/tasks.json @@ -29,6 +29,33 @@ "type": "shell", "command": "cmake --preset ${command:cmake.activeConfigurePresetName} -DNODE:STRING=RR" }, + { + "label": "CMake: configure and build NucleoG4-Blinky", + "type": "shell", + "dependsOrder": "sequence", + "dependsOn": [ + "CMake: configure" + ], + "command": "cmake --build --preset ${command:cmake.activeBuildPresetName} --target NucleoG4-Blinky" + }, + { + "label": "CMake: configure and build NucleoG4-Hello", + "type": "shell", + "dependsOrder": "sequence", + "dependsOn": [ + "CMake: configure" + ], + "command": "cmake --build --preset ${command:cmake.activeBuildPresetName} --target NucleoG4-Hello" + }, + { + "label": "CMake: configure and build NucleoG4-Echo", + "type": "shell", + "dependsOrder": "sequence", + "dependsOn": [ + "CMake: configure" + ], + "command": "cmake --build --preset ${command:cmake.activeBuildPresetName} --target NucleoG4-Echo" + }, { "label": "CMake: configure and build ECU", "type": "shell", diff --git a/Lib/Vendor/SVD/README.md b/Lib/Vendor/SVD/README.md new file mode 100644 index 000000000..e855b502e --- /dev/null +++ b/Lib/Vendor/SVD/README.md @@ -0,0 +1,13 @@ +# CMSIS System View Description + +Grab from where needed and copy unchanged into this directory + +Set the path as appropriate inside of [`.vscode/launch.json`](/.vscode/launch.json) + +## Version + +Version information is contained in the top of each `svd` file. + +## License + +License information is contained in the top of each `svd` file. diff --git a/Lib/Vendor/SVD/STM32G431.svd b/Lib/Vendor/SVD/STM32G431.svd new file mode 100644 index 000000000..62c7d1afd --- /dev/null +++ b/Lib/Vendor/SVD/STM32G431.svd @@ -0,0 +1,50458 @@ + + + + STM32G431 + 2.8 + Description for STM32G431 + + CM4 + r0p1 + little + true + true + 4 + false + + 8 + 32 + 0x20 + 0x0 + 0xFFFFFFFF + + + ADC1 + Analog-to-Digital Converter + ADC + 0x50000000 + + 0x0 + 0xD0 + registers + + + ADC1_2 + ADC1 and ADC2 global interrupt + 18 + + + + ISR + ISR + interrupt and status register + 0x0 + 0x20 + read-write + 0x00000000 + + + JQOVF + JQOVF + 10 + 1 + + + AWD3 + AWD3 + 9 + 1 + + + AWD2 + AWD2 + 8 + 1 + + + AWD1 + AWD1 + 7 + 1 + + + JEOS + JEOS + 6 + 1 + + + JEOC + JEOC + 5 + 1 + + + OVR + OVR + 4 + 1 + + + EOS + EOS + 3 + 1 + + + EOC + EOC + 2 + 1 + + + EOSMP + EOSMP + 1 + 1 + + + ADRDY + ADRDY + 0 + 1 + + + + + IER + IER + interrupt enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + JQOVFIE + JQOVFIE + 10 + 1 + + + AWD3IE + AWD3IE + 9 + 1 + + + AWD2IE + AWD2IE + 8 + 1 + + + AWD1IE + AWD1IE + 7 + 1 + + + JEOSIE + JEOSIE + 6 + 1 + + + JEOCIE + JEOCIE + 5 + 1 + + + OVRIE + OVRIE + 4 + 1 + + + EOSIE + EOSIE + 3 + 1 + + + EOCIE + EOCIE + 2 + 1 + + + EOSMPIE + EOSMPIE + 1 + 1 + + + ADRDYIE + ADRDYIE + 0 + 1 + + + + + CR + CR + control register + 0x8 + 0x20 + read-write + 0x20000000 + + + ADCAL + ADCAL + 31 + 1 + + + ADCALDIF + ADCALDIF + 30 + 1 + + + DEEPPWD + DEEPPWD + 29 + 1 + + + ADVREGEN + ADVREGEN + 28 + 1 + + + JADSTP + JADSTP + 5 + 1 + + + ADSTP + ADSTP + 4 + 1 + + + JADSTART + JADSTART + 3 + 1 + + + ADSTART + ADSTART + 2 + 1 + + + ADDIS + ADDIS + 1 + 1 + + + ADEN + ADEN + 0 + 1 + + + + + CFGR + CFGR + configuration register + 0xC + 0x20 + read-write + 0x80000000 + + + JQDIS + Injected Queue disable + 31 + 1 + + + AWD1CH + Analog watchdog 1 channel selection + 26 + 5 + + + JAUTO + JAUTO + 25 + 1 + + + JAWD1EN + JAWD1EN + 24 + 1 + + + AWD1EN + AWD1EN + 23 + 1 + + + AWD1SGL + AWD1SGL + 22 + 1 + + + JQM + JQM + 21 + 1 + + + JDISCEN + JDISCEN + 20 + 1 + + + DISCNUM + DISCNUM + 17 + 3 + + + DISCEN + DISCEN + 16 + 1 + + + ALIGN + ALIGN + 15 + 1 + + + AUTDLY + AUTDLY + 14 + 1 + + + CONT + CONT + 13 + 1 + + + OVRMOD + OVRMOD + 12 + 1 + + + EXTEN + EXTEN + 10 + 2 + + + EXTSEL + External trigger selection for regular group + 5 + 5 + + + RES + RES + 3 + 2 + + + DMACFG + DMACFG + 1 + 1 + + + DMAEN + DMAEN + 0 + 1 + + + + + CFGR2 + CFGR2 + configuration register + 0x10 + 0x20 + read-write + 0x00000000 + + + SMPTRIG + SMPTRIG + 27 + 1 + + + BULB + BULB + 26 + 1 + + + SWTRIG + SWTRIG + 25 + 1 + + + GCOMP + GCOMP + 16 + 1 + + + ROVSM + EXTEN + 10 + 1 + + + TROVS + Triggered Regular Oversampling + 9 + 1 + + + OVSS + ALIGN + 5 + 4 + + + OVSR + RES + 2 + 3 + + + JOVSE + DMACFG + 1 + 1 + + + ROVSE + DMAEN + 0 + 1 + + + + + SMPR1 + SMPR1 + sample time register 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + SMP9 + SMP9 + 27 + 3 + + + SMP8 + SMP8 + 24 + 3 + + + SMP7 + SMP7 + 21 + 3 + + + SMP6 + SMP6 + 18 + 3 + + + SMP5 + SMP5 + 15 + 3 + + + SMP4 + SMP4 + 12 + 3 + + + SMP3 + SMP3 + 9 + 3 + + + SMP2 + SMP2 + 6 + 3 + + + SMP1 + SMP1 + 3 + 3 + + + SMPPLUS + Addition of one clock cycle to the sampling time + 31 + 1 + + + SMP0 + SMP0 + 0 + 3 + + + + + SMPR2 + SMPR2 + sample time register 2 + 0x18 + 0x20 + read-write + 0x00000000 + + + SMP18 + SMP18 + 24 + 3 + + + SMP17 + SMP17 + 21 + 3 + + + SMP16 + SMP16 + 18 + 3 + + + SMP15 + SMP15 + 15 + 3 + + + SMP14 + SMP14 + 12 + 3 + + + SMP13 + SMP13 + 9 + 3 + + + SMP12 + SMP12 + 6 + 3 + + + SMP11 + SMP11 + 3 + 3 + + + SMP10 + SMP10 + 0 + 3 + + + + + TR1 + TR1 + watchdog threshold register 1 + 0x20 + 0x20 + read-write + 0x0FFF0000 + + + HT1 + HT1 + 16 + 12 + + + AWDFILT + AWDFILT + 12 + 3 + + + LT1 + LT1 + 0 + 12 + + + + + TR2 + TR2 + watchdog threshold register + 0x24 + 0x20 + read-write + 0x00FF0000 + + + HT2 + HT2 + 16 + 8 + + + LT2 + LT2 + 0 + 8 + + + + + TR3 + TR3 + watchdog threshold register 3 + 0x28 + 0x20 + read-write + 0x00FF0000 + + + HT3 + HT3 + 16 + 8 + + + LT3 + LT3 + 0 + 8 + + + + + SQR1 + SQR1 + regular sequence register 1 + 0x30 + 0x20 + read-write + 0x00000000 + + + SQ4 + SQ4 + 24 + 5 + + + SQ3 + SQ3 + 18 + 5 + + + SQ2 + SQ2 + 12 + 5 + + + SQ1 + SQ1 + 6 + 5 + + + L + Regular channel sequence length + 0 + 4 + + + + + SQR2 + SQR2 + regular sequence register 2 + 0x34 + 0x20 + read-write + 0x00000000 + + + SQ9 + SQ9 + 24 + 5 + + + SQ8 + SQ8 + 18 + 5 + + + SQ7 + SQ7 + 12 + 5 + + + SQ6 + SQ6 + 6 + 5 + + + SQ5 + SQ5 + 0 + 5 + + + + + SQR3 + SQR3 + regular sequence register 3 + 0x38 + 0x20 + read-write + 0x00000000 + + + SQ14 + SQ14 + 24 + 5 + + + SQ13 + SQ13 + 18 + 5 + + + SQ12 + SQ12 + 12 + 5 + + + SQ11 + SQ11 + 6 + 5 + + + SQ10 + SQ10 + 0 + 5 + + + + + SQR4 + SQR4 + regular sequence register 4 + 0x3C + 0x20 + read-write + 0x00000000 + + + SQ16 + SQ16 + 6 + 5 + + + SQ15 + SQ15 + 0 + 5 + + + + + DR + DR + regular Data Register + 0x40 + 0x20 + read-only + 0x00000000 + + + RDATA + Regular Data converted + 0 + 16 + + + + + JSQR + JSQR + injected sequence register + 0x4C + 0x20 + read-write + 0x00000000 + + + JSQ4 + JSQ4 + 27 + 5 + + + JSQ3 + JSQ3 + 21 + 5 + + + JSQ2 + JSQ2 + 15 + 5 + + + JSQ1 + JSQ1 + 9 + 5 + + + JEXTEN + JEXTEN + 7 + 2 + + + JEXTSEL + JEXTSEL + 2 + 5 + + + JL + JL + 0 + 2 + + + + + OFR1 + OFR1 + offset register 1 + 0x60 + 0x20 + read-write + 0x00000000 + + + OFFSET1_EN + OFFSET1_EN + 31 + 1 + + + OFFSET1_CH + OFFSET1_CH + 26 + 5 + + + SATEN + SATEN + 25 + 1 + + + OFFSETPOS + OFFSETPOS + 24 + 1 + + + OFFSET1 + OFFSET1 + 0 + 12 + + + + + OFR2 + OFR2 + offset register 2 + 0x64 + 0x20 + read-write + 0x00000000 + + + OFFSET1_EN + OFFSET1_EN + 31 + 1 + + + OFFSET1_CH + OFFSET1_CH + 26 + 5 + + + SATEN + SATEN + 25 + 1 + + + OFFSETPOS + OFFSETPOS + 24 + 1 + + + OFFSET1 + OFFSET1 + 0 + 12 + + + + + OFR3 + OFR3 + offset register 3 + 0x68 + 0x20 + read-write + 0x00000000 + + + OFFSET1_EN + OFFSET1_EN + 31 + 1 + + + OFFSET1_CH + OFFSET1_CH + 26 + 5 + + + SATEN + SATEN + 25 + 1 + + + OFFSETPOS + OFFSETPOS + 24 + 1 + + + OFFSET1 + OFFSET1 + 0 + 12 + + + + + OFR4 + OFR4 + offset register 4 + 0x6C + 0x20 + read-write + 0x00000000 + + + OFFSET1_EN + OFFSET1_EN + 31 + 1 + + + OFFSET1_CH + OFFSET1_CH + 26 + 5 + + + SATEN + SATEN + 25 + 1 + + + OFFSETPOS + OFFSETPOS + 24 + 1 + + + OFFSET1 + OFFSET1 + 0 + 12 + + + + + JDR1 + JDR1 + injected data register 1 + 0x80 + 0x20 + read-only + 0x00000000 + + + JDATA1 + JDATA1 + 0 + 16 + + + + + JDR2 + JDR2 + injected data register 2 + 0x84 + 0x20 + read-only + 0x00000000 + + + JDATA2 + JDATA2 + 0 + 16 + + + + + JDR3 + JDR3 + injected data register 3 + 0x88 + 0x20 + read-only + 0x00000000 + + + JDATA3 + JDATA3 + 0 + 16 + + + + + JDR4 + JDR4 + injected data register 4 + 0x8C + 0x20 + read-only + 0x00000000 + + + JDATA4 + JDATA4 + 0 + 16 + + + + + AWD2CR + AWD2CR + Analog Watchdog 2 Configuration Register + 0xA0 + 0x20 + read-write + 0x00000000 + + + AWD2CH + AWD2CH + 0 + 19 + + + + + AWD3CR + AWD3CR + Analog Watchdog 3 Configuration Register + 0xA4 + 0x20 + read-write + 0x00000000 + + + AWD3CH + AWD3CH + 0 + 19 + + + + + DIFSEL + DIFSEL + Differential Mode Selection Register 2 + 0xB0 + 0x20 + 0x00000000 + + + DIFSEL_0 + Differential mode for channels 0 + 0 + 1 + read-only + + + DIFSEL_1_18 + Differential mode for channels 15 to 1 + 1 + 18 + read-write + + + + + CALFACT + CALFACT + Calibration Factors + 0xB4 + 0x20 + read-write + 0x00000000 + + + CALFACT_D + CALFACT_D + 16 + 7 + + + CALFACT_S + CALFACT_S + 0 + 7 + + + + + GCOMP + GCOMP + Gain compensation Register + 0xC0 + 0x20 + read-write + 0x00000000 + + + GCOMPCOEFF + GCOMPCOEFF + 0 + 14 + + + + + + + ADC2 + 0x50000100 + + + ADC12_Common + Analog-to-Digital Converter + ADC + 0x50000300 + + 0x0 + 0x11 + registers + + + + CSR + CSR + ADC Common status register + 0x0 + 0x20 + read-only + 0x00000000 + + + ADDRDY_MST + ADDRDY_MST + 0 + 1 + + + EOSMP_MST + EOSMP_MST + 1 + 1 + + + EOC_MST + EOC_MST + 2 + 1 + + + EOS_MST + EOS_MST + 3 + 1 + + + OVR_MST + OVR_MST + 4 + 1 + + + JEOC_MST + JEOC_MST + 5 + 1 + + + JEOS_MST + JEOS_MST + 6 + 1 + + + AWD1_MST + AWD1_MST + 7 + 1 + + + AWD2_MST + AWD2_MST + 8 + 1 + + + AWD3_MST + AWD3_MST + 9 + 1 + + + JQOVF_MST + JQOVF_MST + 10 + 1 + + + ADRDY_SLV + ADRDY_SLV + 16 + 1 + + + EOSMP_SLV + EOSMP_SLV + 17 + 1 + + + EOC_SLV + End of regular conversion of the slave ADC + 18 + 1 + + + EOS_SLV + End of regular sequence flag of the slave ADC + 19 + 1 + + + OVR_SLV + Overrun flag of the slave ADC + 20 + 1 + + + JEOC_SLV + End of injected conversion flag of the slave ADC + 21 + 1 + + + JEOS_SLV + End of injected sequence flag of the slave ADC + 22 + 1 + + + AWD1_SLV + Analog watchdog 1 flag of the slave ADC + 23 + 1 + + + AWD2_SLV + Analog watchdog 2 flag of the slave ADC + 24 + 1 + + + AWD3_SLV + Analog watchdog 3 flag of the slave ADC + 25 + 1 + + + JQOVF_SLV + Injected Context Queue Overflow flag of the slave ADC + 26 + 1 + + + + + CCR + CCR + ADC common control register + 0x8 + 0x20 + read-write + 0x00000000 + + + DUAL + Dual ADC mode selection + 0 + 5 + + + DELAY + Delay between 2 sampling phases + 8 + 4 + + + DMACFG + DMA configuration (for multi-ADC mode) + 13 + 1 + + + MDMA + Direct memory access mode for multi ADC mode + 14 + 2 + + + CKMODE + ADC clock mode + 16 + 2 + + + VREFEN + VREFINT enable + 22 + 1 + + + VSENSESEL + VTS selection + 23 + 1 + + + VBATSEL + VBAT selection + 24 + 1 + + + PRESC + ADC prescaler + 18 + 4 + + + + + CDR + CDR + ADC common regular data register for dual and triple modes + 0xC + 0x20 + read-only + 0x00000000 + + + RDATA_SLV + Regular data of the slave ADC + 16 + 16 + + + RDATA_MST + Regular data of the master ADC + 0 + 16 + + + + + + + ADC345_Common + 0x50000700 + + + AES + Advanced encryption standard hardware accelerator + AES + 0x50060000 + + 0x0 + 0x400 + registers + + + AES + AES + 85 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + NPBLB + NPBLB + 20 + 4 + + + KEYSIZE + KEYSIZE + 18 + 1 + + + CHMOD_2 + CHMOD_2 + 16 + 1 + + + GCMPH + GCMPH + 13 + 2 + + + DMAOUTEN + Enable DMA management of data output phase + 12 + 1 + + + DMAINEN + Enable DMA management of data input phase + 11 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + CCFIE + CCF flag interrupt enable + 9 + 1 + + + ERRC + Error clear + 8 + 1 + + + CCFC + Computation Complete Flag Clear + 7 + 1 + + + CHMOD + AES chaining mode + 5 + 2 + + + MODE + AES operating mode + 3 + 2 + + + DATATYPE + Data type selection (for data in and data out to/from the cryptographic block) + 1 + 2 + + + EN + AES enable + 0 + 1 + + + + + SR + SR + status register + 0x4 + 0x20 + read-only + 0x00000000 + + + BUSY + BUSY + 3 + 1 + + + WRERR + Write error flag + 2 + 1 + + + RDERR + Read error flag + 1 + 1 + + + CCF + Computation complete flag + 0 + 1 + + + + + DINR + DINR + data input register + 0x8 + 0x20 + read-write + 0x00000000 + + + AES_DINR + Data Input Register + 0 + 32 + + + + + DOUTR + DOUTR + data output register + 0xC + 0x20 + read-only + 0x00000000 + + + AES_DOUTR + Data output register + 0 + 32 + + + + + KEYR0 + KEYR0 + key register 0 + 0x10 + 0x20 + read-write + 0x00000000 + + + AES_KEYR0 + Data Output Register (LSB key [31:0]) + 0 + 32 + + + + + KEYR1 + KEYR1 + key register 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + AES_KEYR1 + AES key register (key [63:32]) + 0 + 32 + + + + + KEYR2 + KEYR2 + key register 2 + 0x18 + 0x20 + read-write + 0x00000000 + + + AES_KEYR2 + AES key register (key [95:64]) + 0 + 32 + + + + + KEYR3 + KEYR3 + key register 3 + 0x1C + 0x20 + read-write + 0x00000000 + + + AES_KEYR3 + AES key register (MSB key [127:96]) + 0 + 32 + + + + + IVR0 + IVR0 + initialization vector register 0 + 0x20 + 0x20 + read-write + 0x00000000 + + + AES_IVR0 + initialization vector register (LSB IVR [31:0]) + 0 + 32 + + + + + IVR1 + IVR1 + initialization vector register 1 + 0x24 + 0x20 + read-write + 0x00000000 + + + AES_IVR1 + Initialization Vector Register (IVR [63:32]) + 0 + 32 + + + + + IVR2 + IVR2 + initialization vector register 2 + 0x28 + 0x20 + read-write + 0x00000000 + + + AES_IVR2 + Initialization Vector Register (IVR [95:64]) + 0 + 32 + + + + + IVR3 + IVR3 + initialization vector register 3 + 0x2C + 0x20 + read-write + 0x00000000 + + + AES_IVR3 + Initialization Vector Register (MSB IVR [127:96]) + 0 + 32 + + + + + KEYR4 + KEYR4 + key register 4 + 0x30 + 0x20 + read-write + 0x00000000 + + + KEY + AES key + 0 + 32 + + + + + KEYR5 + KEYR5 + key register 5 + 0x34 + 0x20 + read-write + 0x00000000 + + + KEY + AES key + 0 + 32 + + + + + KEYR6 + KEYR6 + key register 6 + 0x38 + 0x20 + read-write + 0x00000000 + + + KEY + AES key + 0 + 32 + + + + + KEYR7 + KEYR7 + key register 7 + 0x3C + 0x20 + read-write + 0x00000000 + + + KEY + AES key + 0 + 32 + + + + + SUSP0R + SUSP0R + suspend registers + 0x40 + 0x20 + read-write + 0x00000000 + + + SUSP + AES suspend + 0 + 32 + + + + + SUSP1R + SUSP1R + suspend registers + 0x44 + 0x20 + read-write + 0x00000000 + + + SUSP + AES suspend + 0 + 32 + + + + + SUSP2R + SUSP2R + suspend registers + 0x48 + 0x20 + read-write + 0x00000000 + + + SUSP + AES suspend + 0 + 32 + + + + + SUSP3R + SUSP3R + suspend registers + 0x4C + 0x20 + read-write + 0x00000000 + + + SUSP + AES suspend + 0 + 32 + + + + + SUSP4R + SUSP4R + suspend registers + 0x50 + 0x20 + read-write + 0x00000000 + + + SUSP + AES suspend + 0 + 32 + + + + + SUSP5R + SUSP5R + suspend registers + 0x54 + 0x20 + read-write + 0x00000000 + + + SUSP + AES suspend + 0 + 32 + + + + + SUSP6R + SUSP6R + suspend registers + 0x58 + 0x20 + read-write + 0x00000000 + + + SUSP + AES suspend + 0 + 32 + + + + + SUSP7R + SUSP7R + suspend registers + 0x5C + 0x20 + read-write + 0x00000000 + + + SUSP + AES suspend + 0 + 32 + + + + + + + COMP + Comparator control and status register + COMP + 0x40010200 + + 0x0 + 0x100 + registers + + + COMP1_2_3 + COMP1_2_3 + 64 + + + COMP4_5_6 + COMP4_5_6 + 65 + + + COMP7 + COMP7 + 66 + + + + COMP_C1CSR + COMP_C1CSR + Comparator control/status register + 0x0 + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + INMSEL + INMSEL + 4 + 3 + read-write + + + INPSEL + INPSEL + 8 + 1 + read-write + + + POL + POL + 15 + 1 + read-write + + + HYST + HYST + 16 + 3 + read-write + + + BLANKSEL + BLANKSEL + 19 + 3 + read-write + + + BRGEN + BRGEN + 22 + 1 + read-write + + + SCALEN + SCALEN + 23 + 1 + read-write + + + VALUE + VALUE + 30 + 1 + read-only + + + LOCK + LOCK + 31 + 1 + read-write + + + + + COMP_C2CSR + COMP_C2CSR + Comparator control/status register + 0x4 + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + INMSEL + INMSEL + 4 + 3 + read-write + + + INPSEL + INPSEL + 8 + 1 + read-write + + + POL + POL + 15 + 1 + read-write + + + HYST + HYST + 16 + 3 + read-write + + + BLANKSEL + BLANKSEL + 19 + 3 + read-write + + + BRGEN + BRGEN + 22 + 1 + read-write + + + SCALEN + SCALEN + 23 + 1 + read-write + + + VALUE + VALUE + 30 + 1 + read-only + + + LOCK + LOCK + 31 + 1 + read-write + + + + + COMP_C3CSR + COMP_C3CSR + Comparator control/status register + 0x8 + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + INMSEL + INMSEL + 4 + 3 + read-write + + + INPSEL + INPSEL + 8 + 1 + read-write + + + POL + POL + 15 + 1 + read-write + + + HYST + HYST + 16 + 3 + read-write + + + BLANKSEL + BLANKSEL + 19 + 3 + read-write + + + BRGEN + BRGEN + 22 + 1 + read-write + + + SCALEN + SCALEN + 23 + 1 + read-write + + + VALUE + VALUE + 30 + 1 + read-only + + + LOCK + LOCK + 31 + 1 + read-write + + + + + COMP_C4CSR + COMP_C4CSR + Comparator control/status register + 0x0C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + INMSEL + INMSEL + 4 + 3 + read-write + + + INPSEL + INPSEL + 8 + 1 + read-write + + + POL + POL + 15 + 1 + read-write + + + HYST + HYST + 16 + 3 + read-write + + + BLANKSEL + BLANKSEL + 19 + 3 + read-write + + + BRGEN + BRGEN + 22 + 1 + read-write + + + SCALEN + SCALEN + 23 + 1 + read-write + + + VALUE + VALUE + 30 + 1 + read-only + + + LOCK + LOCK + 31 + 1 + read-write + + + + + + + CORDIC + CORDIC Co-processor + CORDIC + 0x40020C00 + + 0x0 + 0x400 + registers + + + Cordic + Cordic + 100 + + + + CSR + CSR + CORDIC Control Status register + 0x0 + 0x20 + read-write + 0x00000000 + + + FUNC + FUNC + 0 + 4 + + + PRECISION + PRECISION + 4 + 4 + + + SCALE + SCALE + 8 + 3 + + + IEN + IEN + 16 + 1 + + + DMAREN + DMAREN + 17 + 1 + + + DMAWEN + DMAWEN + 18 + 1 + + + NRES + NRES + 19 + 1 + + + NARGS + NARGS + 20 + 1 + + + RESSIZE + RESSIZE + 21 + 1 + + + ARGSIZE + ARGSIZE + 22 + 1 + + + RRDY + RRDY + 31 + 1 + + + + + WDATA + WDATA + FMAC Write Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + ARG + ARG + 0 + 32 + + + + + RDATA + RDATA + FMAC Read Data register + 0x8 + 0x20 + read-only + 0x00000000 + + + RES + RES + 0 + 32 + + + + + + + CRC + Cyclic redundancy check calculation unit + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DR + DR + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DR + Data register bits + 0 + 32 + + + + + IDR + IDR + Independent data register + 0x4 + 0x20 + read-write + 0x00000000 + + + IDR + General-purpose 8-bit data register bits + 0 + 32 + + + + + CR + CR + Control register + 0x8 + 0x20 + 0x00000000 + + + REV_OUT + Reverse output data + 7 + 1 + read-write + + + REV_IN + Reverse input data + 5 + 2 + read-write + + + POLYSIZE + Polynomial size + 3 + 2 + read-write + + + RESET + RESET bit + 0 + 1 + write-only + + + + + INIT + INIT + Initial CRC value + 0x10 + 0x20 + read-write + 0xFFFFFFFF + + + CRC_INIT + Programmable initial CRC value + 0 + 32 + + + + + POL + POL + polynomial + 0x14 + 0x20 + read-write + 0x04C11DB7 + + + POL + Programmable polynomial + 0 + 32 + + + + + + + CRS + CRS + CRS + 0x40002000 + + 0x0 + 0x400 + registers + + + CRS + CRS + 75 + + + + CR + CR + CRS control register + 0x0 + 0x20 + 0x00004000 + + + SYNCOKIE + SYNC event OK interrupt enable + 0 + 1 + read-write + + + SYNCWARNIE + SYNC warning interrupt enable + 1 + 1 + read-write + + + ERRIE + Synchronization or trimming error interrupt enable + 2 + 1 + read-write + + + ESYNCIE + Expected SYNC interrupt enable + 3 + 1 + read-write + + + CEN + Frequency error counter enable This bit enables the oscillator clock for the frequency error counter. When this bit is set, the CRS_CFGR register is write-protected and cannot be modified. + 5 + 1 + read-write + + + AUTOTRIMEN + Automatic trimming enable This bit enables the automatic hardware adjustment of TRIM bits according to the measured frequency error between two SYNC events. If this bit is set, the TRIM bits are read-only. The TRIM value can be adjusted by hardware by one or two steps at a time, depending on the measured frequency error value. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details. + 6 + 1 + read-write + + + SWSYNC + Generate software SYNC event This bit is set by software in order to generate a software SYNC event. It is automatically cleared by hardware. + 7 + 1 + read-write + + + TRIM + HSI48 oscillator smooth trimming These bits provide a user-programmable trimming value to the HSI48 oscillator. They can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI48. The default value is 32, which corresponds to the middle of the trimming interval. The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value corresponds to a higher output frequency. When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only. + 8 + 7 + read-write + + + + + CFGR + CFGR + This register can be written only when the frequency error counter is disabled (CEN bit is cleared in CRS_CR). When the counter is enabled, this register is write-protected. + 0x4 + 0x20 + read-write + 0x2022BB7F + + + RELOAD + Counter reload value RELOAD is the value to be loaded in the frequency error counter with each SYNC event. Refer to Section7.3.3: Frequency error measurement for more details about counter behavior. + 0 + 16 + + + FELIM + Frequency error limit FELIM contains the value to be used to evaluate the captured frequency error value latched in the FECAP[15:0] bits of the CRS_ISR register. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details about FECAP evaluation. + 16 + 8 + + + SYNCDIV + SYNC divider These bits are set and cleared by software to control the division factor of the SYNC signal. + 24 + 3 + + + SYNCSRC + SYNC signal source selection These bits are set and cleared by software to select the SYNC signal source. Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the periodic USB SOF will not be generated by the host. No SYNC signal will therefore be provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs should be used as SYNC signal. + 28 + 2 + + + SYNCPOL + SYNC polarity selection This bit is set and cleared by software to select the input polarity for the SYNC signal source. + 31 + 1 + + + + + ISR + ISR + CRS interrupt and status register + 0x8 + 0x20 + read-only + 0x00000000 + + + SYNCOKF + SYNC event OK flag This flag is set by hardware when the measured frequency error is smaller than FELIM * 3. This means that either no adjustment of the TRIM value is needed or that an adjustment by one trimming step is enough to compensate the frequency error. An interrupt is generated if the SYNCOKIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCOKC bit in the CRS_ICR register. + 0 + 1 + + + SYNCWARNF + SYNC warning flag This flag is set by hardware when the measured frequency error is greater than or equal to FELIM * 3, but smaller than FELIM * 128. This means that to compensate the frequency error, the TRIM value must be adjusted by two steps or more. An interrupt is generated if the SYNCWARNIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCWARNC bit in the CRS_ICR register. + 1 + 1 + + + ERRF + Error flag This flag is set by hardware in case of any synchronization or trimming error. It is the logical OR of the TRIMOVF, SYNCMISS and SYNCERR bits. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software in reaction to setting the ERRC bit in the CRS_ICR register, which clears the TRIMOVF, SYNCMISS and SYNCERR bits. + 2 + 1 + + + ESYNCF + Expected SYNC flag This flag is set by hardware when the frequency error counter reached a zero value. An interrupt is generated if the ESYNCIE bit is set in the CRS_CR register. It is cleared by software by setting the ESYNCC bit in the CRS_ICR register. + 3 + 1 + + + SYNCERR + SYNC error This flag is set by hardware when the SYNC pulse arrives before the ESYNC event and the measured frequency error is greater than or equal to FELIM * 128. This means that the frequency error is too big (internal frequency too low) to be compensated by adjusting the TRIM value, and that some other action should be taken. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. + 8 + 1 + + + SYNCMISS + SYNC missed This flag is set by hardware when the frequency error counter reached value FELIM * 128 and no SYNC was detected, meaning either that a SYNC pulse was missed or that the frequency error is too big (internal frequency too high) to be compensated by adjusting the TRIM value, and that some other action should be taken. At this point, the frequency error counter is stopped (waiting for a next SYNC) and an interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. + 9 + 1 + + + TRIMOVF + Trimming overflow or underflow This flag is set by hardware when the automatic trimming tries to over- or under-flow the TRIM value. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. + 10 + 1 + + + FEDIR + Frequency error direction FEDIR is the counting direction of the frequency error counter latched in the time of the last SYNC event. It shows whether the actual frequency is below or above the target. + 15 + 1 + + + FECAP + Frequency error capture FECAP is the frequency error counter value latched in the time ofthe last SYNC event. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details about FECAP usage. + 16 + 16 + + + + + ICR + ICR + CRS interrupt flag clear register + 0xC + 0x20 + read-write + 0x00000000 + + + SYNCOKC + SYNC event OK clear flag Writing 1 to this bit clears the SYNCOKF flag in the CRS_ISR register. + 0 + 1 + + + SYNCWARNC + SYNC warning clear flag Writing 1 to this bit clears the SYNCWARNF flag in the CRS_ISR register. + 1 + 1 + + + ERRC + Error clear flag Writing 1 to this bit clears TRIMOVF, SYNCMISS and SYNCERR bits and consequently also the ERRF flag in the CRS_ISR register. + 2 + 1 + + + ESYNCC + Expected SYNC clear flag Writing 1 to this bit clears the ESYNCF flag in the CRS_ISR register. + 3 + 1 + + + + + + + DAC1 + Digital-to-analog converter + DAC + 0x50000800 + + 0x0 + 0x400 + registers + + + + DAC_CR + DAC_CR + DAC control register + 0x0 + 0x20 + read-write + 0x00000000 + + + EN1 + DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1. + 0 + 1 + + + TEN1 + DAC channel1 trigger enable + 1 + 1 + + + TSEL1 + DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled). + 2 + 4 + + + WAVE1 + DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled). + 6 + 2 + + + MAMP1 + DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 + 8 + 4 + + + DMAEN1 + DAC channel1 DMA enable This bit is set and cleared by software. + 12 + 1 + + + DMAUDRIE1 + DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software. + 13 + 1 + + + CEN1 + DAC Channel 1 calibration enable This bit is set and cleared by software to enable/disable DAC channel 1 calibration, it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored. + 14 + 1 + + + EN2 + DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2. + 16 + 1 + + + TEN2 + DAC channel2 trigger enable + 17 + 1 + + + TSEL2 + DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled). + 18 + 4 + + + WAVE2 + DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled) + 22 + 2 + + + MAMP2 + DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 + 24 + 4 + + + DMAEN2 + DAC channel2 DMA enable This bit is set and cleared by software. + 28 + 1 + + + DMAUDRIE2 + DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software. + 29 + 1 + + + CEN2 + DAC Channel 2 calibration enable This bit is set and cleared by software to enable/disable DAC channel 2 calibration, it can be written only if bit EN2=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored. + 30 + 1 + + + + + DAC_SWTRGR + DAC_SWTRGR + DAC software trigger register + 0x4 + 0x20 + write-only + 0x00000000 + + + SWTRIG1 + DAC channel1 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR1 register value has been loaded into the DAC_DOR1 register. + 0 + 1 + + + SWTRIG2 + DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2 register value has been loaded into the DAC_DOR2 register. + 1 + 1 + + + SWTRIGB1 + DAC channel1 software trigger B + 16 + 1 + + + SWTRIGB2 + DAC channel2 software trigger B + 17 + 1 + + + + + DAC_DHR12R1 + DAC_DHR12R1 + DAC channel1 12-bit right-aligned data holding register + 0x8 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. + 0 + 12 + + + DACC1DHRB + DAC channel1 12-bit right-aligned data B + 16 + 12 + + + + + DAC_DHR12L1 + DAC_DHR12L1 + DAC channel1 12-bit left aligned data holding register + 0xC + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. + 4 + 12 + + + DACC1DHRB + DAC channel1 12-bit left-aligned data B + 20 + 12 + + + + + DAC_DHR8R1 + DAC_DHR8R1 + DAC channel1 8-bit right aligned data holding register + 0x10 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1. + 0 + 8 + + + DACC1DHRB + DAC channel1 8-bit right-aligned data + 8 + 8 + + + + + DAC_DHR12R2 + DAC_DHR12R2 + DAC channel2 12-bit right aligned data holding register + 0x14 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. + 0 + 12 + + + DACC2DHRB + DAC channel2 12-bit right-aligned data + 16 + 12 + + + + + DAC_DHR12L2 + DAC_DHR12L2 + DAC channel2 12-bit left aligned data holding register + 0x18 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2. + 4 + 12 + + + DACC2DHRB + DAC channel2 12-bit left-aligned data B + 20 + 12 + + + + + DAC_DHR8R2 + DAC_DHR8R2 + DAC channel2 8-bit right-aligned data holding register + 0x1C + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2. + 0 + 8 + + + DACC2DHRB + DAC channel2 8-bit right-aligned data + 8 + 8 + + + + + DAC_DHR12RD + DAC_DHR12RD + Dual DAC 12-bit right-aligned data holding register + 0x20 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. + 0 + 12 + + + DACC2DHR + DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. + 16 + 12 + + + + + DAC_DHR12LD + DAC_DHR12LD + DUAL DAC 12-bit left aligned data holding register + 0x24 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. + 4 + 12 + + + DACC2DHR + DAC channel2 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. + 20 + 12 + + + + + DAC_DHR8RD + DAC_DHR8RD + DUAL DAC 8-bit right aligned data holding register + 0x28 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1. + 0 + 8 + + + DACC2DHR + DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2. + 8 + 8 + + + + + DAC_DOR1 + DAC_DOR1 + DAC channel1 data output register + 0x2C + 0x20 + read-only + 0x00000000 + + + DACC1DOR + DAC channel1 data output These bits are read-only, they contain data output for DAC channel1. + 0 + 12 + + + DACC1DORB + DAC channel1 data output + 16 + 12 + + + + + DAC_DOR2 + DAC_DOR2 + DAC channel2 data output register + 0x30 + 0x20 + read-only + 0x00000000 + + + DACC2DOR + DAC channel2 data output These bits are read-only, they contain data output for DAC channel2. + 0 + 12 + + + DACC2DORB + DAC channel2 data output + 16 + 12 + + + + + DAC_SR + DAC_SR + DAC status register + 0x34 + 0x20 + 0x00000000 + + + DAC1RDY + DAC channel1 ready status bit + 11 + 1 + read-write + + + DORSTAT1 + DAC channel1 output register status bit + 12 + 1 + read-write + + + DMAUDR1 + DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). + 13 + 1 + read-write + + + CAL_FLAG1 + DAC Channel 1 calibration offset status This bit is set and cleared by hardware + 14 + 1 + read-only + + + BWST1 + DAC Channel 1 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete. (It takes about 3LSI periods of synchronization). + 15 + 1 + read-only + + + DAC2RDY + DAC channel 2 ready status bit + 27 + 1 + read-write + + + DORSTAT2 + DAC channel 2 output register status bit + 28 + 1 + read-write + + + DMAUDR2 + DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). + 29 + 1 + read-write + + + CAL_FLAG2 + DAC Channel 2 calibration offset status This bit is set and cleared by hardware + 30 + 1 + read-only + + + BWST2 + DAC Channel 2 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR2, It is cleared by hardware when the write operation of DAC_SHSR2 is complete. (It takes about 3 LSI periods of synchronization). + 31 + 1 + read-only + + + + + DAC_CCR + DAC_CCR + DAC calibration control register + 0x38 + 0x20 + read-write + 0x00000000 + + + OTRIM1 + DAC Channel 1 offset trimming value + 0 + 5 + + + OTRIM2 + DAC Channel 2 offset trimming value + 16 + 5 + + + + + DAC_MCR + DAC_MCR + DAC mode control register + 0x3C + 0x20 + read-write + 0x00000000 + + + MODE1 + DAC Channel 1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1=0 and bit CEN1 =0 in the DAC_CR register). If EN1=1 or CEN1 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 1 mode: DAC Channel 1 in normal Mode DAC Channel 1 in sample &amp; hold mode + 0 + 3 + + + DMADOUBLE1 + DAC Channel1 DMA double data mode + 8 + 1 + + + SINFORMAT1 + Enable signed format for DAC channel1 + 9 + 1 + + + HFSEL + High frequency interface mode selection + 14 + 2 + + + MODE2 + DAC Channel 2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 2 mode: DAC Channel 2 in normal Mode DAC Channel 2 in sample &amp; hold mode + 16 + 3 + + + DMADOUBLE2 + DAC Channel2 DMA double data mode + 24 + 1 + + + SINFORMAT2 + Enable signed format for DAC channel2 + 25 + 1 + + + + + DAC_SHSR1 + DAC_SHSR1 + DAC Sample and Hold sample time register 1 + 0x40 + 0x20 + read-write + 0x00000000 + + + TSAMPLE1 + DAC Channel 1 sample Time (only valid in sample &amp; hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored. + 0 + 10 + + + + + DAC_SHSR2 + DAC_SHSR2 + DAC Sample and Hold sample time register 2 + 0x44 + 0x20 + read-write + 0x00000000 + + + TSAMPLE2 + DAC Channel 2 sample Time (only valid in sample &amp; hold mode) These bits can be written when the DAC channel2 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, if BWSTx=1, the write operation is ignored. + 0 + 10 + + + + + DAC_SHHR + DAC_SHHR + DAC Sample and Hold hold time register + 0x48 + 0x20 + read-write + 0x00010001 + + + THOLD1 + DAC Channel 1 hold Time (only valid in sample &amp; hold mode) Hold time= (THOLD[9:0]) x T LSI + 0 + 10 + + + THOLD2 + DAC Channel 2 hold time (only valid in sample &amp; hold mode). Hold time= (THOLD[9:0]) x T LSI + 16 + 10 + + + + + DAC_SHRR + DAC_SHRR + DAC Sample and Hold refresh time register + 0x4C + 0x20 + read-write + 0x00010001 + + + TREFRESH1 + DAC Channel 1 refresh Time (only valid in sample &amp; hold mode) Refresh time= (TREFRESH[7:0]) x T LSI + 0 + 8 + + + TREFRESH2 + DAC Channel 2 refresh Time (only valid in sample &amp; hold mode) Refresh time= (TREFRESH[7:0]) x T LSI + 16 + 8 + + + + + DAC_STR1 + DAC_STR1 + Sawtooth register + 0x58 + 0x20 + read-write + 0x00000000 + + + STRSTDATA1 + DAC Channel 1 Sawtooth reset value + 0 + 12 + + + STDIR1 + DAC Channel1 Sawtooth direction setting + 12 + 1 + + + STINCDATA1 + DAC CH1 Sawtooth increment value (12.4 bit format) + 16 + 16 + + + + + DAC_STR2 + DAC_STR2 + Sawtooth register + 0x5C + 0x20 + read-write + 0x00000000 + + + STRSTDATA2 + DAC Channel 2 Sawtooth reset value + 0 + 12 + + + STDIR2 + DAC Channel2 Sawtooth direction setting + 12 + 1 + + + STINCDATA2 + DAC CH2 Sawtooth increment value (12.4 bit format) + 16 + 16 + + + + + DAC_STMODR + DAC_STMODR + Sawtooth Mode register + 0x60 + 0x20 + read-write + 0x00000000 + + + STRSTTRIGSEL1 + DAC Channel 1 Sawtooth Reset trigger selection + 0 + 4 + + + STINCTRIGSEL1 + DAC Channel 1 Sawtooth Increment trigger selection + 8 + 4 + + + STRSTTRIGSEL2 + DAC Channel 1 Sawtooth Reset trigger selection + 16 + 4 + + + STINCTRIGSEL2 + DAC Channel 2 Sawtooth Increment trigger selection + 24 + 4 + + + + + + + DAC2 + 0x50000C00 + + + DAC3 + 0x50001000 + + + DAC4 + 0x50001400 + + + DBGMCU + Debug support + DBGMCU + 0xE0042000 + + 0x0 + 0x400 + registers + + + + IDCODE + IDCODE + MCU Device ID Code Register + 0x0 + 0x20 + read-only + 0x0 + + + DEV_ID + Device Identifier + 0 + 16 + + + REV_ID + Revision Identifier + 16 + 16 + + + + + CR + CR + Debug MCU Configuration Register + 0x4 + 0x20 + read-write + 0x0 + + + DBG_SLEEP + Debug Sleep Mode + 0 + 1 + + + DBG_STOP + Debug Stop Mode + 1 + 1 + + + DBG_STANDBY + Debug Standby Mode + 2 + 1 + + + TRACE_IOEN + Trace pin assignment control + 5 + 1 + + + TRACE_MODE + Trace pin assignment control + 6 + 2 + + + + + APB1L_FZ + APB1L_FZ + APB Low Freeze Register 1 + 0x8 + 0x20 + read-write + 0x0 + + + DBG_TIMER2_STOP + Debug Timer 2 stopped when Core is halted + 0 + 1 + + + DBG_TIM3_STOP + TIM3 counter stopped when core is halted + 1 + 1 + + + DBG_TIM4_STOP + TIM4 counter stopped when core is halted + 2 + 1 + + + DBG_TIM5_STOP + TIM5 counter stopped when core is halted + 3 + 1 + + + DBG_TIMER6_STOP + Debug Timer 6 stopped when Core is halted + 4 + 1 + + + DBG_TIM7_STOP + TIM7 counter stopped when core is halted + 5 + 1 + + + DBG_RTC_STOP + Debug RTC stopped when Core is halted + 10 + 1 + + + DBG_WWDG_STOP + Debug Window Wachdog stopped when Core is halted + 11 + 1 + + + DBG_IWDG_STOP + Debug Independent Wachdog stopped when Core is halted + 12 + 1 + + + DBG_I2C1_STOP + I2C1 SMBUS timeout mode stopped when core is halted + 21 + 1 + + + DBG_I2C2_STOP + I2C2 SMBUS timeout mode stopped when core is halted + 22 + 1 + + + DBG_I2C3_STOP + I2C3 SMBUS timeout mode stopped when core is halted + 30 + 1 + + + DBG_LPTIMER_STOP + LPTIM1 counter stopped when core is halted + 31 + 1 + + + + + APB1H_FZ + APB1H_FZ + APB Low Freeze Register 2 + 0xC + 0x20 + read-write + 0x0 + + + DBG_I2C4_STOP + DBG_I2C4_STOP + 1 + 1 + + + + + APB2_FZ + APB2_FZ + APB High Freeze Register + 0x10 + 0x20 + read-write + 0x0 + + + DBG_TIM1_STOP + TIM1 counter stopped when core is halted + 11 + 1 + + + DBG_TIM8_STOP + TIM8 counter stopped when core is halted + 13 + 1 + + + DBG_TIM15_STOP + TIM15 counter stopped when core is halted + 16 + 1 + + + DBG_TIM16_STOP + TIM16 counter stopped when core is halted + 17 + 1 + + + DBG_TIM17_STOP + TIM17 counter stopped when core is halted + 18 + 1 + + + DBG_TIM20_STOP + TIM20counter stopped when core is halted + 20 + 1 + + + DBG_HRTIM0_STOP + DBG_HRTIM0_STOP + 26 + 1 + + + DBG_HRTIM1_STOP + DBG_HRTIM0_STOP + 27 + 1 + + + DBG_HRTIM2_STOP + DBG_HRTIM0_STOP + 28 + 1 + + + DBG_HRTIM3_STOP + DBG_HRTIM0_STOP + 29 + 1 + + + + + + + DMA1 + DMA controller + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA1_CH1 + DMA1 channel 1 interrupt + 11 + + + DMA1_CH2 + DMA1 channel 2 interrupt + 12 + + + DMA1_CH3 + DMA1 channel 3 interrupt + 13 + + + DMA1_CH4 + DMA1 channel 4 interrupt + 14 + + + DMA1_CH5 + DMA1 channel 5 interrupt + 15 + + + DMA1_CH6 + DMA1 channel 6 interrupt + 16 + + + + ISR + ISR + interrupt status register + 0x0 + 0x20 + read-only + 0x00000000 + + + TEIF8 + TEIF8 + 31 + 1 + + + HTIF8 + HTIF8 + 30 + 1 + + + TCIF8 + TCIF8 + 29 + 1 + + + GIF8 + GIF8 + 28 + 1 + + + TEIF7 + TEIF7 + 27 + 1 + + + HTIF7 + HTIF7 + 26 + 1 + + + TCIF7 + TCIF7 + 25 + 1 + + + GIF7 + GIF7 + 24 + 1 + + + TEIF6 + TEIF6 + 23 + 1 + + + HTIF6 + HTIF6 + 22 + 1 + + + TCIF6 + TCIF6 + 21 + 1 + + + GIF6 + GIF6 + 20 + 1 + + + TEIF5 + TEIF5 + 19 + 1 + + + HTIF5 + HTIF5 + 18 + 1 + + + TCIF5 + TCIF5 + 17 + 1 + + + GIF5 + GIF5 + 16 + 1 + + + TEIF4 + TEIF4 + 15 + 1 + + + HTIF4 + HTIF4 + 14 + 1 + + + TCIF4 + TCIF4 + 13 + 1 + + + GIF4 + GIF4 + 12 + 1 + + + TEIF3 + TEIF3 + 11 + 1 + + + HTIF3 + HTIF3 + 10 + 1 + + + TCIF3 + TCIF3 + 9 + 1 + + + GIF3 + GIF3 + 8 + 1 + + + TEIF2 + TEIF2 + 7 + 1 + + + HTIF2 + HTIF2 + 6 + 1 + + + TCIF2 + TCIF2 + 5 + 1 + + + GIF2 + GIF2 + 4 + 1 + + + TEIF1 + TEIF1 + 3 + 1 + + + HTIF1 + HTIF1 + 2 + 1 + + + TCIF1 + TCIF1 + 1 + 1 + + + GIF1 + GIF1 + 0 + 1 + + + + + IFCR + IFCR + DMA interrupt flag clear register + 0x4 + 0x20 + write-only + 0x00000000 + + + TEIF8 + TEIF8 + 31 + 1 + + + HTIF8 + HTIF8 + 30 + 1 + + + TCIF8 + TCIF8 + 29 + 1 + + + GIF8 + GIF8 + 28 + 1 + + + TEIF7 + TEIF7 + 27 + 1 + + + HTIF7 + HTIF7 + 26 + 1 + + + TCIF7 + TCIF7 + 25 + 1 + + + GIF7 + GIF7 + 24 + 1 + + + TEIF6 + TEIF6 + 23 + 1 + + + HTIF6 + HTIF6 + 22 + 1 + + + TCIF6 + TCIF6 + 21 + 1 + + + GIF6 + GIF6 + 20 + 1 + + + TEIF5 + TEIF5 + 19 + 1 + + + HTIF5 + HTIF5 + 18 + 1 + + + TCIF5 + TCIF5 + 17 + 1 + + + GIF5 + GIF5 + 16 + 1 + + + TEIF4 + TEIF4 + 15 + 1 + + + HTIF4 + HTIF4 + 14 + 1 + + + TCIF4 + TCIF4 + 13 + 1 + + + GIF4 + GIF4 + 12 + 1 + + + TEIF3 + TEIF3 + 11 + 1 + + + HTIF3 + HTIF3 + 10 + 1 + + + TCIF3 + TCIF3 + 9 + 1 + + + GIF3 + GIF3 + 8 + 1 + + + TEIF2 + TEIF2 + 7 + 1 + + + HTIF2 + HTIF2 + 6 + 1 + + + TCIF2 + TCIF2 + 5 + 1 + + + GIF2 + GIF2 + 4 + 1 + + + TEIF1 + TEIF1 + 3 + 1 + + + HTIF1 + HTIF1 + 2 + 1 + + + TCIF1 + TCIF1 + 1 + 1 + + + GIF1 + GIF1 + 0 + 1 + + + + + CCR1 + CCR1 + DMA channel 1 configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + EN + channel enable + 0 + 1 + + + TCIE + TCIE + 1 + 1 + + + HTIE + HTIE + 2 + 1 + + + TEIE + TEIE + 3 + 1 + + + DIR + DIR + 4 + 1 + + + CIRC + CIRC + 5 + 1 + + + PINC + PINC + 6 + 1 + + + MINC + MINC + 7 + 1 + + + PSIZE + PSIZE + 8 + 2 + + + MSIZE + MSIZE + 10 + 2 + + + PL + PL + 12 + 2 + + + MEM2MEM + MEM2MEM + 14 + 1 + + + + + CCR2 + CCR2 + DMA channel 2 configuration register + 0x1C + 0x20 + read-write + 0x00000000 + + + EN + channel enable + 0 + 1 + + + TCIE + TCIE + 1 + 1 + + + HTIE + HTIE + 2 + 1 + + + TEIE + TEIE + 3 + 1 + + + DIR + DIR + 4 + 1 + + + CIRC + CIRC + 5 + 1 + + + PINC + PINC + 6 + 1 + + + MINC + MINC + 7 + 1 + + + PSIZE + PSIZE + 8 + 2 + + + MSIZE + MSIZE + 10 + 2 + + + PL + PL + 12 + 2 + + + MEM2MEM + MEM2MEM + 14 + 1 + + + + + CCR3 + CCR3 + DMA channel 3 configuration register + 0x30 + 0x20 + read-write + 0x00000000 + + + EN + channel enable + 0 + 1 + + + TCIE + TCIE + 1 + 1 + + + HTIE + HTIE + 2 + 1 + + + TEIE + TEIE + 3 + 1 + + + DIR + DIR + 4 + 1 + + + CIRC + CIRC + 5 + 1 + + + PINC + PINC + 6 + 1 + + + MINC + MINC + 7 + 1 + + + PSIZE + PSIZE + 8 + 2 + + + MSIZE + MSIZE + 10 + 2 + + + PL + PL + 12 + 2 + + + MEM2MEM + MEM2MEM + 14 + 1 + + + + + CCR4 + CCR4 + DMA channel 3 configuration register + 0x44 + 0x20 + read-write + 0x00000000 + + + EN + channel enable + 0 + 1 + + + TCIE + TCIE + 1 + 1 + + + HTIE + HTIE + 2 + 1 + + + TEIE + TEIE + 3 + 1 + + + DIR + DIR + 4 + 1 + + + CIRC + CIRC + 5 + 1 + + + PINC + PINC + 6 + 1 + + + MINC + MINC + 7 + 1 + + + PSIZE + PSIZE + 8 + 2 + + + MSIZE + MSIZE + 10 + 2 + + + PL + PL + 12 + 2 + + + MEM2MEM + MEM2MEM + 14 + 1 + + + + + CCR5 + CCR5 + DMA channel 4 configuration register + 0x58 + 0x20 + read-write + 0x00000000 + + + EN + channel enable + 0 + 1 + + + TCIE + TCIE + 1 + 1 + + + HTIE + HTIE + 2 + 1 + + + TEIE + TEIE + 3 + 1 + + + DIR + DIR + 4 + 1 + + + CIRC + CIRC + 5 + 1 + + + PINC + PINC + 6 + 1 + + + MINC + MINC + 7 + 1 + + + PSIZE + PSIZE + 8 + 2 + + + MSIZE + MSIZE + 10 + 2 + + + PL + PL + 12 + 2 + + + MEM2MEM + MEM2MEM + 14 + 1 + + + + + CCR6 + CCR6 + DMA channel 5 configuration register + 0x6C + 0x20 + read-write + 0x00000000 + + + EN + channel enable + 0 + 1 + + + TCIE + TCIE + 1 + 1 + + + HTIE + HTIE + 2 + 1 + + + TEIE + TEIE + 3 + 1 + + + DIR + DIR + 4 + 1 + + + CIRC + CIRC + 5 + 1 + + + PINC + PINC + 6 + 1 + + + MINC + MINC + 7 + 1 + + + PSIZE + PSIZE + 8 + 2 + + + MSIZE + MSIZE + 10 + 2 + + + PL + PL + 12 + 2 + + + MEM2MEM + MEM2MEM + 14 + 1 + + + + + CCR7 + CCR7 + DMA channel 6 configuration register + 0x80 + 0x20 + read-write + 0x00000000 + + + EN + channel enable + 0 + 1 + + + TCIE + TCIE + 1 + 1 + + + HTIE + HTIE + 2 + 1 + + + TEIE + TEIE + 3 + 1 + + + DIR + DIR + 4 + 1 + + + CIRC + CIRC + 5 + 1 + + + PINC + PINC + 6 + 1 + + + MINC + MINC + 7 + 1 + + + PSIZE + PSIZE + 8 + 2 + + + MSIZE + MSIZE + 10 + 2 + + + PL + PL + 12 + 2 + + + MEM2MEM + MEM2MEM + 14 + 1 + + + + + CCR8 + CCR8 + DMA channel 7 configuration register + 0x94 + 0x20 + read-write + 0x00000000 + + + EN + channel enable + 0 + 1 + + + TCIE + TCIE + 1 + 1 + + + HTIE + HTIE + 2 + 1 + + + TEIE + TEIE + 3 + 1 + + + DIR + DIR + 4 + 1 + + + CIRC + CIRC + 5 + 1 + + + PINC + PINC + 6 + 1 + + + MINC + MINC + 7 + 1 + + + PSIZE + PSIZE + 8 + 2 + + + MSIZE + MSIZE + 10 + 2 + + + PL + PL + 12 + 2 + + + MEM2MEM + MEM2MEM + 14 + 1 + + + + + CNDTR1 + CNDTR1 + channel x number of data to transfer register + 0xC + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to transfer + 0 + 16 + + + + + CNDTR2 + CNDTR2 + channel x number of data to transfer register + 0x20 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to transfer + 0 + 16 + + + + + CNDTR3 + CNDTR3 + channel x number of data to transfer register + 0x34 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to transfer + 0 + 16 + + + + + CNDTR4 + CNDTR4 + channel x number of data to transfer register + 0x48 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to transfer + 0 + 16 + + + + + CNDTR5 + CNDTR5 + channel x number of data to transfer register + 0x5C + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to transfer + 0 + 16 + + + + + CNDTR6 + CNDTR6 + channel x number of data to transfer register + 0x70 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to transfer + 0 + 16 + + + + + CNDTR7 + CNDTR7 + channel x number of data to transfer register + 0x84 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to transfer + 0 + 16 + + + + + CNDTR8 + CNDTR8 + channel x number of data to transfer register + 0x98 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to transfer + 0 + 16 + + + + + CPAR1 + CPAR1 + DMA channel x peripheral address register + 0x10 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CPAR2 + CPAR2 + DMA channel x peripheral address register + 0x24 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CPAR3 + CPAR3 + DMA channel x peripheral address register + 0x38 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CPAR4 + CPAR4 + DMA channel x peripheral address register + 0x4C + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CPAR5 + CPAR5 + DMA channel x peripheral address register + 0x60 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CPAR6 + CPAR6 + DMA channel x peripheral address register + 0x74 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CPAR7 + CPAR7 + DMA channel x peripheral address register + 0x88 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CPAR8 + CPAR8 + DMA channel x peripheral address register + 0x9C + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR1 + CMAR1 + DMA channel x memory address register + 0x14 + 0x20 + read-write + 0x00000000 + + + MA + Memory 1 address (used in case of Double buffer mode) + 0 + 32 + + + + + CMAR2 + CMAR2 + DMA channel x memory address register + 0x28 + 0x20 + read-write + 0x00000000 + + + MA + Memory 1 address (used in case of Double buffer mode) + 0 + 32 + + + + + CMAR3 + CMAR3 + DMA channel x memory address register + 0x3C + 0x20 + read-write + 0x00000000 + + + MA + Memory 1 address (used in case of Double buffer mode) + 0 + 32 + + + + + CMAR4 + CMAR4 + DMA channel x memory address register + 0x50 + 0x20 + read-write + 0x00000000 + + + MA + Memory 1 address (used in case of Double buffer mode) + 0 + 32 + + + + + CMAR5 + CMAR5 + DMA channel x memory address register + 0x64 + 0x20 + read-write + 0x00000000 + + + MA + Memory 1 address (used in case of Double buffer mode) + 0 + 32 + + + + + CMAR6 + CMAR6 + DMA channel x memory address register + 0x78 + 0x20 + read-write + 0x00000000 + + + MA + Memory 1 address (used in case of Double buffer mode) + 0 + 32 + + + + + CMAR7 + CMAR7 + DMA channel x memory address register + 0x8C + 0x20 + read-write + 0x00000000 + + + MA + Memory 1 address (used in case of Double buffer mode) + 0 + 32 + + + + + CMAR8 + CMAR8 + DMA channel x memory address register + 0xA0 + 0x20 + read-write + 0x00000000 + + + MA + Memory 1 address (used in case of Double buffer mode) + 0 + 32 + + + + + + + DMA2 + 0x40020400 + + DMA2_CH1 + DMA2_CH1 + 56 + + + DMA2_CH2 + DMA2_CH2 + 57 + + + DMA2_CH3 + DMA2_CH3 + 58 + + + DMA2_CH4 + DMA2_CH4 + 59 + + + DMA2_CH5 + DMA2_CH5 + 60 + + + DMA2_CH6 + DMA2_CH6 + 97 + + + + DMAMUX + DMAMUX + DMAMUX + 0x40020800 + + 0x0 + 0x400 + registers + + + DMAMUX_OVR + DMAMUX_OVR + 94 + + + + C0CR + C0CR + DMAMux - DMA request line multiplexer channel x control register + 0x0 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C1CR + C1CR + DMAMux - DMA request line multiplexer channel x control register + 0x4 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C2CR + C2CR + DMAMux - DMA request line multiplexer channel x control register + 0x8 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C3CR + C3CR + DMAMux - DMA request line multiplexer channel x control register + 0xC + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C4CR + C4CR + DMAMux - DMA request line multiplexer channel x control register + 0x10 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C5CR + C5CR + DMAMux - DMA request line multiplexer channel x control register + 0x14 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C6CR + C6CR + DMAMux - DMA request line multiplexer channel x control register + 0x18 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C7CR + C7CR + DMAMux - DMA request line multiplexer channel x control register + 0x1C + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C8CR + C8CR + DMAMux - DMA request line multiplexer channel x control register + 0x20 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C9CR + C9CR + DMAMux - DMA request line multiplexer channel x control register + 0x24 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C10CR + C10CR + DMAMux - DMA request line multiplexer channel x control register + 0x28 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C11CR + C11CR + DMAMux - DMA request line multiplexer channel x control register + 0x2C + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C12CR + C12CR + DMAMux - DMA request line multiplexer channel x control register + 0x30 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C13CR + C13CR + DMAMux - DMA request line multiplexer channel x control register + 0x34 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C14CR + C14CR + DMAMux - DMA request line multiplexer channel x control register + 0x38 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C15CR + C15CR + DMAMux - DMA request line multiplexer channel x control register + 0x3C + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + RG0CR + RG0CR + DMAMux - DMA request generator channel x control register + 0x100 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input selected + 0 + 5 + + + OIE + Interrupt enable at trigger event overrun + 8 + 1 + + + GE + DMA request generator channel enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset. + 19 + 5 + + + + + RG1CR + RG1CR + DMAMux - DMA request generator channel x control register + 0x104 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input selected + 0 + 5 + + + OIE + Interrupt enable at trigger event overrun + 8 + 1 + + + GE + DMA request generator channel enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset. + 19 + 5 + + + + + RG2CR + RG2CR + DMAMux - DMA request generator channel x control register + 0x108 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input selected + 0 + 5 + + + OIE + Interrupt enable at trigger event overrun + 8 + 1 + + + GE + DMA request generator channel enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset. + 19 + 5 + + + + + RG3CR + RG3CR + DMAMux - DMA request generator channel x control register + 0x10C + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input selected + 0 + 5 + + + OIE + Interrupt enable at trigger event overrun + 8 + 1 + + + GE + DMA request generator channel enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset. + 19 + 5 + + + + + RGSR + RGSR + DMAMux - DMA request generator status register + 0x140 + 0x20 + read-only + 0x00000000 + + + OF + Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register. + 0 + 4 + + + + + RGCFR + RGCFR + DMAMux - DMA request generator clear flag register + 0x144 + 0x20 + write-only + 0x00000000 + + + COF + Clear trigger event overrun flag Upon setting, this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register. + 0 + 4 + + + + + CSR + CSR + DMAMUX request line multiplexer interrupt channel status register + 0x80 + 0x20 + read-only + 0x00000000 + + + SOF + Synchronization overrun event flag + 0 + 16 + + + + + CFR + CFR + DMAMUX request line multiplexer interrupt clear flag register + 0x84 + 0x20 + write-only + 0x00000000 + + + CSOF + Clear synchronization overrun event flag + 0 + 16 + + + + + + + EXTI + External interrupt/event controller + EXTI + 0x40010400 + + 0x0 + 0x400 + registers + + + PVD_PVM + PVD through EXTI line detection + 1 + + + EXTI0 + EXTI Line0 interrupt + 6 + + + EXTI1 + EXTI Line1 interrupt + 7 + + + EXTI2 + EXTI Line2 interrupt + 8 + + + EXTI3 + EXTI Line3 interrupt + 9 + + + EXTI4 + EXTI Line4 interrupt + 10 + + + EXTI9_5 + EXTI9_5 + 23 + + + EXTI15_10 + EXTI15_10 + 40 + + + FPU + Floating point interrupt + 81 + + + + IMR1 + IMR1 + Interrupt mask register + 0x0 + 0x20 + read-write + 0xFF820000 + + + IM0 + Interrupt Mask on line 0 + 0 + 1 + + + IM1 + Interrupt Mask on line 1 + 1 + 1 + + + IM2 + Interrupt Mask on line 2 + 2 + 1 + + + IM3 + Interrupt Mask on line 3 + 3 + 1 + + + IM4 + Interrupt Mask on line 4 + 4 + 1 + + + IM5 + Interrupt Mask on line 5 + 5 + 1 + + + IM6 + Interrupt Mask on line 6 + 6 + 1 + + + IM7 + Interrupt Mask on line 7 + 7 + 1 + + + IM8 + Interrupt Mask on line 8 + 8 + 1 + + + IM9 + Interrupt Mask on line 9 + 9 + 1 + + + IM10 + Interrupt Mask on line 10 + 10 + 1 + + + IM11 + Interrupt Mask on line 11 + 11 + 1 + + + IM12 + Interrupt Mask on line 12 + 12 + 1 + + + IM13 + Interrupt Mask on line 13 + 13 + 1 + + + IM14 + Interrupt Mask on line 14 + 14 + 1 + + + IM15 + Interrupt Mask on line 15 + 15 + 1 + + + IM16 + Interrupt Mask on line 16 + 16 + 1 + + + IM17 + Interrupt Mask on line 17 + 17 + 1 + + + IM18 + Interrupt Mask on line 18 + 18 + 1 + + + IM19 + Interrupt Mask on line 19 + 19 + 1 + + + IM20 + Interrupt Mask on line 20 + 20 + 1 + + + IM21 + Interrupt Mask on line 21 + 21 + 1 + + + IM22 + Interrupt Mask on line 22 + 22 + 1 + + + IM23 + Interrupt Mask on line 23 + 23 + 1 + + + IM24 + Interrupt Mask on line 24 + 24 + 1 + + + IM25 + Interrupt Mask on line 25 + 25 + 1 + + + IM26 + Interrupt Mask on line 26 + 26 + 1 + + + IM27 + Interrupt Mask on line 27 + 27 + 1 + + + IM28 + Interrupt Mask on line 28 + 28 + 1 + + + IM29 + Interrupt Mask on line 29 + 29 + 1 + + + IM30 + Interrupt Mask on line 30 + 30 + 1 + + + IM31 + Interrupt Mask on line 31 + 31 + 1 + + + + + EMR1 + EMR1 + Event mask register + 0x4 + 0x20 + read-write + 0x00000000 + + + EM0 + Event Mask on line 0 + 0 + 1 + + + EM1 + Event Mask on line 1 + 1 + 1 + + + EM2 + Event Mask on line 2 + 2 + 1 + + + EM3 + Event Mask on line 3 + 3 + 1 + + + EM4 + Event Mask on line 4 + 4 + 1 + + + EM5 + Event Mask on line 5 + 5 + 1 + + + EM6 + Event Mask on line 6 + 6 + 1 + + + EM7 + Event Mask on line 7 + 7 + 1 + + + EM8 + Event Mask on line 8 + 8 + 1 + + + EM9 + Event Mask on line 9 + 9 + 1 + + + EM10 + Event Mask on line 10 + 10 + 1 + + + EM11 + Event Mask on line 11 + 11 + 1 + + + EM12 + Event Mask on line 12 + 12 + 1 + + + EM13 + Event Mask on line 13 + 13 + 1 + + + EM14 + Event Mask on line 14 + 14 + 1 + + + EM15 + Event Mask on line 15 + 15 + 1 + + + EM16 + Event Mask on line 16 + 16 + 1 + + + EM17 + Event Mask on line 17 + 17 + 1 + + + EM18 + Event Mask on line 18 + 18 + 1 + + + EM19 + Event Mask on line 19 + 19 + 1 + + + EM20 + Event Mask on line 20 + 20 + 1 + + + EM21 + Event Mask on line 21 + 21 + 1 + + + EM22 + Event Mask on line 22 + 22 + 1 + + + EM23 + Event Mask on line 23 + 23 + 1 + + + EM24 + Event Mask on line 24 + 24 + 1 + + + EM25 + Event Mask on line 25 + 25 + 1 + + + EM26 + Event Mask on line 26 + 26 + 1 + + + EM27 + Event Mask on line 27 + 27 + 1 + + + EM28 + Event Mask on line 28 + 28 + 1 + + + EM29 + Event Mask on line 29 + 29 + 1 + + + EM30 + Event Mask on line 30 + 30 + 1 + + + EM31 + Event Mask on line 31 + 31 + 1 + + + + + RTSR1 + RTSR1 + Rising Trigger selection register + 0x8 + 0x20 + read-write + 0x00000000 + + + RT0 + Rising trigger event configuration of line 0 + 0 + 1 + + + RT1 + Rising trigger event configuration of line 1 + 1 + 1 + + + RT2 + Rising trigger event configuration of line 2 + 2 + 1 + + + RT3 + Rising trigger event configuration of line 3 + 3 + 1 + + + RT4 + Rising trigger event configuration of line 4 + 4 + 1 + + + RT5 + Rising trigger event configuration of line 5 + 5 + 1 + + + RT6 + Rising trigger event configuration of line 6 + 6 + 1 + + + RT7 + Rising trigger event configuration of line 7 + 7 + 1 + + + RT8 + Rising trigger event configuration of line 8 + 8 + 1 + + + RT9 + Rising trigger event configuration of line 9 + 9 + 1 + + + RT10 + Rising trigger event configuration of line 10 + 10 + 1 + + + RT11 + Rising trigger event configuration of line 11 + 11 + 1 + + + RT12 + Rising trigger event configuration of line 12 + 12 + 1 + + + RT13 + Rising trigger event configuration of line 13 + 13 + 1 + + + RT14 + Rising trigger event configuration of line 14 + 14 + 1 + + + RT15 + Rising trigger event configuration of line 15 + 15 + 1 + + + RT16 + Rising trigger event configuration of line 16 + 16 + 1 + + + RT18 + Rising trigger event configuration of line 18 + 18 + 1 + + + RT19 + Rising trigger event configuration of line 19 + 19 + 1 + + + RT20 + Rising trigger event configuration of line 20 + 20 + 1 + + + RT21 + Rising trigger event configuration of line 21 + 21 + 1 + + + RT22 + Rising trigger event configuration of line 22 + 22 + 1 + + + RT + RT + 29 + 3 + + + + + FTSR1 + FTSR1 + Falling Trigger selection register + 0xC + 0x20 + read-write + 0x00000000 + + + FT0 + Falling trigger event configuration of line 0 + 0 + 1 + + + FT1 + Falling trigger event configuration of line 1 + 1 + 1 + + + FT2 + Falling trigger event configuration of line 2 + 2 + 1 + + + FT3 + Falling trigger event configuration of line 3 + 3 + 1 + + + FT4 + Falling trigger event configuration of line 4 + 4 + 1 + + + FT5 + Falling trigger event configuration of line 5 + 5 + 1 + + + FT6 + Falling trigger event configuration of line 6 + 6 + 1 + + + FT7 + Falling trigger event configuration of line 7 + 7 + 1 + + + FT8 + Falling trigger event configuration of line 8 + 8 + 1 + + + FT9 + Falling trigger event configuration of line 9 + 9 + 1 + + + FT10 + Falling trigger event configuration of line 10 + 10 + 1 + + + FT11 + Falling trigger event configuration of line 11 + 11 + 1 + + + FT12 + Falling trigger event configuration of line 12 + 12 + 1 + + + FT13 + Falling trigger event configuration of line 13 + 13 + 1 + + + FT14 + Falling trigger event configuration of line 14 + 14 + 1 + + + FT15 + Falling trigger event configuration of line 15 + 15 + 1 + + + FT16 + Falling trigger event configuration of line 16 + 16 + 1 + + + FT18 + Falling trigger event configuration of line 18 + 18 + 1 + + + FT19 + Falling trigger event configuration of line 19 + 19 + 1 + + + FT20 + Falling trigger event configuration of line 20 + 20 + 1 + + + FT21 + Falling trigger event configuration of line 21 + 21 + 1 + + + FT22 + Falling trigger event configuration of line 22 + 22 + 1 + + + + + SWIER1 + SWIER1 + Software interrupt event register + 0x10 + 0x20 + read-write + 0x00000000 + + + SWI0 + Software Interrupt on line 0 + 0 + 1 + + + SWI1 + Software Interrupt on line 1 + 1 + 1 + + + SWI2 + Software Interrupt on line 2 + 2 + 1 + + + SWI3 + Software Interrupt on line 3 + 3 + 1 + + + SWI4 + Software Interrupt on line 4 + 4 + 1 + + + SWI5 + Software Interrupt on line 5 + 5 + 1 + + + SWI6 + Software Interrupt on line 6 + 6 + 1 + + + SWI7 + Software Interrupt on line 7 + 7 + 1 + + + SWI8 + Software Interrupt on line 8 + 8 + 1 + + + SWI9 + Software Interrupt on line 9 + 9 + 1 + + + SWI10 + Software Interrupt on line 10 + 10 + 1 + + + SWI11 + Software Interrupt on line 11 + 11 + 1 + + + SWI12 + Software Interrupt on line 12 + 12 + 1 + + + SWI13 + Software Interrupt on line 13 + 13 + 1 + + + SWI14 + Software Interrupt on line 14 + 14 + 1 + + + SWI15 + Software Interrupt on line 15 + 15 + 1 + + + SWI16 + Software Interrupt on line 16 + 16 + 1 + + + SWI18 + Software Interrupt on line 18 + 18 + 1 + + + SWI19 + Software Interrupt on line 19 + 19 + 1 + + + SWI20 + Software Interrupt on line 20 + 20 + 1 + + + SWI21 + Software Interrupt on line 21 + 21 + 1 + + + SWI22 + Software Interrupt on line 22 + 22 + 1 + + + + + PR1 + PR1 + Pending register + 0x14 + 0x20 + read-write + 0x00000000 + + + PIF0 + Pending bit 0 + 0 + 1 + + + PIF1 + Pending bit 1 + 1 + 1 + + + PIF2 + Pending bit 2 + 2 + 1 + + + PIF3 + Pending bit 3 + 3 + 1 + + + PIF4 + Pending bit 4 + 4 + 1 + + + PIF5 + Pending bit 5 + 5 + 1 + + + PIF6 + Pending bit 6 + 6 + 1 + + + PIF7 + Pending bit 7 + 7 + 1 + + + PIF8 + Pending bit 8 + 8 + 1 + + + PIF9 + Pending bit 9 + 9 + 1 + + + PIF10 + Pending bit 10 + 10 + 1 + + + PIF11 + Pending bit 11 + 11 + 1 + + + PIF12 + Pending bit 12 + 12 + 1 + + + PIF13 + Pending bit 13 + 13 + 1 + + + PIF14 + Pending bit 14 + 14 + 1 + + + PIF15 + Pending bit 15 + 15 + 1 + + + PIF16 + Pending bit 16 + 16 + 1 + + + PIF17 + Pending bit 17 + 17 + 1 + + + PIF18 + Pending bit 18 + 18 + 1 + + + PIF19 + Pending bit 19 + 19 + 1 + + + PIF20 + Pending bit 20 + 20 + 1 + + + PIF21 + Pending bit 21 + 21 + 1 + + + PIF22 + Pending bit 22 + 22 + 1 + + + PIF29 + Pending bit 29 + 29 + 1 + + + PIF30 + Pending bit 30 + 30 + 1 + + + PIF31 + Pending bit 31 + 31 + 1 + + + + + IMR2 + IMR2 + Interrupt mask register + 0x20 + 0x20 + read-write + 0xFFFFFF87 + + + IM32 + Interrupt Mask on external/internal line 32 + 0 + 1 + + + IM33 + Interrupt Mask on external/internal line 33 + 1 + 1 + + + IM34 + Interrupt Mask on external/internal line 34 + 2 + 1 + + + IM35 + Interrupt Mask on external/internal line 35 + 3 + 1 + + + IM36 + Interrupt Mask on external/internal line 36 + 4 + 1 + + + IM37 + Interrupt Mask on external/internal line 37 + 5 + 1 + + + IM38 + Interrupt Mask on external/internal line 38 + 6 + 1 + + + IM39 + Interrupt Mask on external/internal line 39 + 7 + 1 + + + IM40 + Interrupt Mask on external/internal line 40 + 8 + 1 + + + IM41 + Interrupt Mask on external/internal line 41 + 9 + 1 + + + IM42 + Interrupt Mask on external/internal line 42 + 10 + 1 + + + IM43 + Interrupt Mask on external/internal line 43 + 11 + 1 + + + + + EMR2 + EMR2 + Event mask register + 0x24 + 0x20 + read-write + 0x00000000 + + + EM32 + Event mask on external/internal line 32 + 0 + 1 + + + EM33 + Event mask on external/internal line 33 + 1 + 1 + + + EM34 + Event mask on external/internal line 34 + 2 + 1 + + + EM35 + Event mask on external/internal line 35 + 3 + 1 + + + EM36 + Event mask on external/internal line 36 + 4 + 1 + + + EM37 + Event mask on external/internal line 37 + 5 + 1 + + + EM38 + Event mask on external/internal line 38 + 6 + 1 + + + EM39 + Event mask on external/internal line 39 + 7 + 1 + + + EM40 + Event mask on external/internal line 40 + 8 + 1 + + + + + RTSR2 + RTSR2 + Rising Trigger selection register + 0x28 + 0x20 + read-write + 0x00000000 + + + RT32 + Rising trigger event configuration bit of line 32 + 0 + 1 + + + RT33 + Rising trigger event configuration bit of line 32 + 1 + 1 + + + RT38 + Rising trigger event configuration bit of line 38 + 6 + 1 + + + RT39 + Rising trigger event configuration bit of line 39 + 7 + 1 + + + RT40 + Rising trigger event configuration bit of line 40 + 8 + 1 + + + RT41 + Rising trigger event configuration bit of line 41 + 9 + 1 + + + + + FTSR2 + FTSR2 + Falling Trigger selection register + 0x2C + 0x20 + read-write + 0x00000000 + + + FT35 + Falling trigger event configuration bit of line 35 + 3 + 1 + + + FT36 + Falling trigger event configuration bit of line 36 + 4 + 1 + + + FT37 + Falling trigger event configuration bit of line 37 + 5 + 1 + + + FT38 + Falling trigger event configuration bit of line 38 + 6 + 1 + + + + + SWIER2 + SWIER2 + Software interrupt event register + 0x30 + 0x20 + read-write + 0x00000000 + + + SWI35 + Software interrupt on line 35 + 3 + 1 + + + SWI36 + Software interrupt on line 36 + 4 + 1 + + + SWI37 + Software interrupt on line 37 + 5 + 1 + + + SWI38 + Software interrupt on line 38 + 6 + 1 + + + + + PR2 + PR2 + Pending register + 0x34 + 0x20 + read-write + 0x00000000 + + + PIF35 + Pending interrupt flag on line 35 + 3 + 1 + + + PIF36 + Pending interrupt flag on line 36 + 4 + 1 + + + PIF37 + Pending interrupt flag on line 37 + 5 + 1 + + + PIF38 + Pending interrupt flag on line 38 + 6 + 1 + + + + + + + FDCAN + FDCAN + FDCAN + 0x4000A400 + + 0x0 + 0x400 + registers + + + + FDCAN_CREL + FDCAN_CREL + FDCAN core release register + 0x0000 + 0x20 + 0x32141218 + 0xFFFFFFFF + + + DAY + 18 + 0 + 8 + read-only + + + MON + 12 + 8 + 8 + read-only + + + YEAR + 4 + 16 + 4 + read-only + + + SUBSTEP + 1 + 20 + 4 + read-only + + + STEP + 2 + 24 + 4 + read-only + + + REL + 3 + 28 + 4 + read-only + + + + + FDCAN_ENDN + FDCAN_ENDN + FDCAN endian register + 0x0004 + 0x20 + 0x87654321 + 0xFFFFFFFF + + + ETV + Endianness test value + + 0 + 32 + read-only + + + + + FDCAN_DBTP + FDCAN_DBTP + FDCAN data bit timing and prescaler register + 0x000C + 0x20 + 0x00000A33 + 0xFFFFFFFF + + + DSJW + Synchronization jump width + + 0 + 4 + read-write + + + DTSEG2 + Data time segment after sample point + + 4 + 4 + read-write + + + DTSEG1 + Data time segment before sample point + + 8 + 5 + read-write + + + DBRP + Data bit rate prescaler + + 16 + 5 + read-write + + + TDC + Transceiver delay compensation + 23 + 1 + read-write + + + B_0x0 + Transceiver delay compensation disabled + 0x0 + + + B_0x1 + Transceiver delay compensation enabled + 0x1 + + + + + + + FDCAN_TEST + FDCAN_TEST + FDCAN test register + 0x0010 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LBCK + Loop back mode + 4 + 1 + read-write + + + B_0x0 + Reset value, Loop Back mode is disabled + 0x0 + + + B_0x1 + Loop Back mode is enabled (see Power down (Sleep mode)) + 0x1 + + + + + TX + Control of transmit pin + 5 + 2 + read-write + + + B_0x0 + Reset value, FDCANx_TX TX is controlled by the CAN core, updated at the end of the CAN bit time + 0x0 + + + B_0x1 + Sample point can be monitored at pin FDCANx_TX + 0x1 + + + B_0x2 + Dominant (0) level at pin FDCANx_TX + 0x2 + + + B_0x3 + Recessive (1) at pin FDCANx_TX + 0x3 + + + + + RX + Receive pin + + 7 + 1 + read-only + + + B_0x0 + The CAN bus is dominant (FDCANx_RX = 0) + 0x0 + + + B_0x1 + The CAN bus is recessive (FDCANx_RX = 1) + 0x1 + + + + + + + FDCAN_RWD + FDCAN_RWD + FDCAN RAM watchdog register + 0x0014 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WDC + Watchdog configuration + + 0 + 8 + read-write + + + WDV + Watchdog value + + 8 + 8 + read-only + + + + + FDCAN_CCCR + FDCAN_CCCR + FDCAN CC control register + 0x0018 + 0x20 + 0x00000001 + 0xFFFFFFFF + + + INIT + Initialization + 0 + 1 + read-write + + + B_0x0 + Normal operation + 0x0 + + + B_0x1 + Initialization started + 0x1 + + + + + CCE + Configuration change enable + 1 + 1 + read-write + + + B_0x0 + The CPU has no write access to the protected configuration registers. + 0x0 + + + B_0x1 + The CPU has write access to the protected configuration registers (while CCCR.INIT = 1). + 0x1 + + + + + ASM + ASM restricted operation mode + + 2 + 1 + read-write + + + B_0x0 + Normal CAN operation + 0x0 + + + B_0x1 + Restricted operation Mode active + 0x1 + + + + + CSA + Clock stop acknowledge + 3 + 1 + read-only + + + B_0x0 + No clock stop acknowledged + 0x0 + + + B_0x1 + FDCAN may be set in power down by stopping APB clock and kernel clock. + 0x1 + + + + + CSR + Clock stop request + 4 + 1 + read-write + + + B_0x0 + No clock stop requested + 0x0 + + + B_0x1 + Clock stop requested. When clock stop is requested, first INIT and then CSA is set after all pending transfer requests have been completed and the CAN bus reached idle. + 0x1 + + + + + MON + Bus monitoring mode + + 5 + 1 + read-write + + + B_0x0 + Bus monitoring mode disabled + 0x0 + + + B_0x1 + Bus monitoring mode enabled + 0x1 + + + + + DAR + Disable automatic retransmission + 6 + 1 + read-write + + + B_0x0 + Automatic retransmission of messages not transmitted successfully enabled + 0x0 + + + B_0x1 + Automatic retransmission disabled + 0x1 + + + + + TEST + Test mode enable + 7 + 1 + read-write + + + B_0x0 + Normal operation, register TEST holds reset values + 0x0 + + + B_0x1 + Test Mode, write access to register TEST enabled + 0x1 + + + + + FDOE + FD operation enable + 8 + 1 + read-write + + + B_0x0 + FD operation disabled + 0x0 + + + B_0x1 + FD operation enabled + 0x1 + + + + + BRSE + FDCAN bit rate switching + 9 + 1 + read-write + + + B_0x0 + Bit rate switching for transmissions disabled + 0x0 + + + B_0x1 + Bit rate switching for transmissions enabled + 0x1 + + + + + PXHD + Protocol exception handling disable + 12 + 1 + read-write + + + B_0x0 + Protocol exception handling enabled + 0x0 + + + B_0x1 + Protocol exception handling disabled + 0x1 + + + + + EFBI + Edge filtering during bus integration + 13 + 1 + read-write + + + B_0x0 + Edge filtering disabled + 0x0 + + + B_0x1 + Two consecutive dominant tq required to detect an edge for hard synchronization + 0x1 + + + + + TXP + If this bit is set, the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame. + 14 + 1 + read-write + + + B_0x0 + disabled + 0x0 + + + B_0x1 + enabled + 0x1 + + + + + NISO + Non ISO operation + + 15 + 1 + read-write + + + B_0x0 + CAN FD frame format according to ISO11898-1 + 0x0 + + + B_0x1 + CAN FD frame format according to Bosch CAN FD Specification V1.0 + 0x1 + + + + + + + FDCAN_NBTP + FDCAN_NBTP + FDCAN nominal bit timing and prescaler register + 0x001C + 0x20 + 0x06000A03 + 0xFFFFFFFF + + + NTSEG2 + Nominal time segment after sample point + + 0 + 7 + read-write + + + NTSEG1 + Nominal time segment before sample point + + 8 + 8 + read-write + + + NBRP + Bit rate prescaler + + 16 + 9 + read-write + + + NSJW + Nominal (re)synchronization jump width + + 25 + 7 + read-write + + + + + FDCAN_TSCC + FDCAN_TSCC + FDCAN timestamp counter configuration register + 0x0020 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TSS + Timestamp select + + 0 + 2 + read-write + + + B_0x0 + Timestamp counter value always 0x0000 + 0x0 + + + B_0x1 + Timestamp counter value incremented according to TCP + 0x1 + + + B_0x2 + External timestamp counter from TIM3 value (tim3_cnt[0:15]) + 0x2 + + + B_0x3 + Same as 00. + 0x3 + + + + + TCP + Timestamp counter prescaler + 16 + 4 + read-write + + + + + FDCAN_TSCV + FDCAN_TSCV + FDCAN timestamp counter value register + 0x0024 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TSC + Timestamp counter + 0 + 16 + read-write + + + + + FDCAN_TOCC + FDCAN_TOCC + FDCAN timeout counter configuration register + 0x0028 + 0x20 + 0xFFFF0000 + 0xFFFFFFFF + + + ETOC + Timeout counter enable + + 0 + 1 + read-write + + + B_0x0 + Timeout counter disabled + 0x0 + + + B_0x1 + Timeout counter enabled + 0x1 + + + + + TOS + Timeout select + + 1 + 2 + read-write + + + B_0x0 + Continuous operation + 0x0 + + + B_0x1 + Timeout controlled by Tx event FIFO + 0x1 + + + B_0x2 + Timeout controlled by Rx FIFO 0 + 0x2 + + + B_0x3 + Timeout controlled by Rx FIFO 1 + 0x3 + + + + + TOP + Timeout period + + 16 + 16 + read-write + + + + + FDCAN_TOCV + FDCAN_TOCV + FDCAN timeout counter value register + 0x002C + 0x20 + 0x0000FFFF + 0xFFFFFFFF + + + TOC + Timeout counter + 0 + 16 + read-write + + + + + FDCAN_ECR + FDCAN_ECR + FDCAN error counter register + 0x0040 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TEC + Transmit error counter + + 0 + 8 + read-only + + + REC + Receive error counter + + 8 + 7 + read-only + + + RP + Receive error passive + 15 + 1 + read-only + + + B_0x0 + The receive error counter is below the error passive level of 128. + 0x0 + + + B_0x1 + The receive error counter has reached the error passive level of 128. + 0x1 + + + + + CEL + CAN error logging + + 16 + 8 + read-write + + + + + FDCAN_PSR + FDCAN_PSR + FDCAN protocol status register + 0x0044 + 0x20 + 0x00000707 + 0xFFFFFFFF + + + LEC + Last error code + + 0 + 3 + read-write + + + B_0x0 + No Error: No error occurred since LEC has been reset by successful reception or transmission. + 0x0 + + + B_0x1 + Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. + 0x1 + + + B_0x2 + Form Error: A fixed format part of a received frame has the wrong format. + 0x2 + + + B_0x3 + AckError: The message transmitted by the FDCAN was not acknowledged by another node. + 0x3 + + + B_0x4 + Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value 1), but the monitored bus value was dominant. + 0x4 + + + B_0x5 + Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value 0), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). + 0x5 + + + B_0x6 + CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. + 0x6 + + + B_0x7 + NoChange: Any read access to the Protocol status register re-initializes the LEC to 7. When the LEC shows the value 7, no CAN bus event was detected since the last CPU read access to the Protocol status register. + 0x7 + + + + + ACT + Activity + + 3 + 2 + read-only + + + B_0x0 + Synchronizing: node is synchronizing on CAN communication. + 0x0 + + + B_0x1 + Idle: node is neither receiver nor transmitter. + 0x1 + + + B_0x2 + Receiver: node is operating as receiver. + 0x2 + + + B_0x3 + Transmitter: node is operating as transmitter. + 0x3 + + + + + EP + Error passive + 5 + 1 + read-only + + + B_0x0 + The FDCAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected. + 0x0 + + + B_0x1 + The FDCAN is in the Error_Passive state. + 0x1 + + + + + EW + Warning Sstatus + 6 + 1 + read-only + + + B_0x0 + Both error counters are below the Error_Warning limit of 96. + 0x0 + + + B_0x1 + At least one of error counter has reached the Error_Warning limit of 96. + 0x1 + + + + + BO + Bus_Off status + 7 + 1 + read-only + + + B_0x0 + The FDCAN is not Bus_Off. + 0x0 + + + B_0x1 + The FDCAN is in Bus_Off state. + 0x1 + + + + + DLEC + Data last error code + + 8 + 3 + read-write + + + RESI + ESI flag of last received FDCAN message + + 11 + 1 + read-write + + + B_0x0 + Last received FDCAN message did not have its ESI flag set. + 0x0 + + + B_0x1 + Last received FDCAN message had its ESI flag set. + 0x1 + + + + + RBRS + BRS flag of last received FDCAN message + + 12 + 1 + read-write + + + B_0x0 + Last received FDCAN message did not have its BRS flag set. + 0x0 + + + B_0x1 + Last received FDCAN message had its BRS flag set. + 0x1 + + + + + REDL + Received FDCAN message + + 13 + 1 + read-write + + + B_0x0 + Since this bit was reset by the CPU, no FDCAN message has been received. + 0x0 + + + B_0x1 + Message in FDCAN format with EDL flag set has been received. + 0x1 + + + + + PXE + Protocol exception event + 14 + 1 + read-write + + + B_0x0 + No protocol exception event occurred since last read access + 0x0 + + + B_0x1 + Protocol exception event occurred + 0x1 + + + + + TDCV + Transmitter delay compensation value + + 16 + 7 + read-only + + + + + FDCAN_TDCR + FDCAN_TDCR + FDCAN transmitter delay compensation register + 0x0048 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TDCF + Transmitter delay compensation filter window length + + 0 + 7 + read-write + + + TDCO + Transmitter delay compensation offset + + 8 + 7 + read-write + + + + + FDCAN_IR + FDCAN_IR + FDCAN interrupt register + 0x0050 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RF0N + Rx FIFO 0 new message + 0 + 1 + read-write + + + B_0x0 + No new message written to Rx FIFO 0 + 0x0 + + + B_0x1 + New message written to Rx FIFO 0 + 0x1 + + + + + RF0F + Rx FIFO 0 full + 1 + 1 + read-write + + + B_0x0 + Rx FIFO 0 not full + 0x0 + + + B_0x1 + Rx FIFO 0 full + 0x1 + + + + + RF0L + Rx FIFO 0 message lost + 2 + 1 + read-write + + + B_0x0 + No Rx FIFO 0 message lost + 0x0 + + + B_0x1 + Rx FIFO 0 message lost + 0x1 + + + + + RF1N + Rx FIFO 1 new message + 3 + 1 + read-write + + + B_0x0 + No new message written to Rx FIFO 1 + 0x0 + + + B_0x1 + New message written to Rx FIFO 1 + 0x1 + + + + + RF1F + Rx FIFO 1 full + 4 + 1 + read-write + + + B_0x0 + Rx FIFO 1 not full + 0x0 + + + B_0x1 + Rx FIFO 1 full + 0x1 + + + + + RF1L + Rx FIFO 1 message lost + 5 + 1 + read-write + + + B_0x0 + No Rx FIFO 1 message lost + 0x0 + + + B_0x1 + Rx FIFO 1 message lost + 0x1 + + + + + HPM + High-priority message + 6 + 1 + read-write + + + B_0x0 + No high-priority message received + 0x0 + + + B_0x1 + High-priority message received + 0x1 + + + + + TC + Transmission completed + 7 + 1 + read-write + + + B_0x0 + No transmission completed + 0x0 + + + B_0x1 + Transmission completed + 0x1 + + + + + TCF + Transmission cancellation finished + 8 + 1 + read-write + + + B_0x0 + No transmission cancellation finished + 0x0 + + + B_0x1 + Transmission cancellation finished + 0x1 + + + + + TFE + Tx FIFO empty + 9 + 1 + read-write + + + B_0x0 + Tx FIFO non-empty + 0x0 + + + B_0x1 + Tx FIFO empty + 0x1 + + + + + TEFN + Tx event FIFO New Entry + 10 + 1 + read-write + + + B_0x0 + Tx event FIFO unchanged + 0x0 + + + B_0x1 + Tx handler wrote Tx event FIFO element. + 0x1 + + + + + TEFF + Tx event FIFO full + 11 + 1 + read-write + + + B_0x0 + Tx event FIFO Not full + 0x0 + + + B_0x1 + Tx event FIFO full + 0x1 + + + + + TEFL + Tx event FIFO element lost + 12 + 1 + read-write + + + B_0x0 + No Tx event FIFO element lost + 0x0 + + + B_0x1 + Tx event FIFO element lost + 0x1 + + + + + TSW + Timestamp wraparound + 13 + 1 + read-write + + + B_0x0 + No timestamp counter wrap-around + 0x0 + + + B_0x1 + Timestamp counter wrapped around + 0x1 + + + + + MRAF + Message RAM access failure + + 14 + 1 + read-write + + + B_0x0 + No Message RAM access failure occurred + 0x0 + + + B_0x1 + Message RAM access failure occurred + 0x1 + + + + + TOO + Timeout occurred + 15 + 1 + read-write + + + B_0x0 + No timeout + 0x0 + + + B_0x1 + Timeout reached + 0x1 + + + + + ELO + Error logging overflow + 16 + 1 + read-write + + + B_0x0 + CAN error logging counter did not overflow. + 0x0 + + + B_0x1 + Overflow of CAN error logging counter occurred. + 0x1 + + + + + EP + Error passive + 17 + 1 + read-write + + + B_0x0 + Error_Passive status unchanged + 0x0 + + + B_0x1 + Error_Passive status changed + 0x1 + + + + + EW + Warning status + 18 + 1 + read-write + + + B_0x0 + Error_Warning status unchanged + 0x0 + + + B_0x1 + Error_Warning status changed + 0x1 + + + + + BO + Bus_Off status + 19 + 1 + read-write + + + B_0x0 + Bus_Off status unchanged + 0x0 + + + B_0x1 + Bus_Off status changed + 0x1 + + + + + WDI + Watchdog interrupt + 20 + 1 + read-write + + + B_0x0 + No message RAM watchdog event occurred + 0x0 + + + B_0x1 + Message RAM watchdog event due to missing READY + 0x1 + + + + + PEA + Protocol error in arbitration phase (nominal bit time is used) + 21 + 1 + read-write + + + B_0x0 + No protocol error in arbitration phase + 0x0 + + + B_0x1 + Protocol error in arbitration phase detected (PSR.LEC different from 0,7) + 0x1 + + + + + PED + Protocol error in data phase (data bit time is used) + 22 + 1 + read-write + + + B_0x0 + No protocol error in data phase + 0x0 + + + B_0x1 + Protocol error in data phase detected (PSR.DLEC different from 0,7) + 0x1 + + + + + ARA + Access to reserved address + 23 + 1 + read-write + + + B_0x0 + No access to reserved address occurred + 0x0 + + + B_0x1 + Access to reserved address occurred + 0x1 + + + + + + + FDCAN_IE + FDCAN_IE + FDCAN interrupt enable register + 0x0054 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RF0NE + Rx FIFO 0 new message interrupt enable + 0 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + RF0FE + Rx FIFO 0 full interrupt enable + 1 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + RF0LE + Rx FIFO 0 message lost interrupt enable + 2 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + RF1NE + Rx FIFO 1 new message interrupt enable + 3 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + RF1FE + Rx FIFO 1 full interrupt enable + 4 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + RF1LE + Rx FIFO 1 message lost interrupt enable + 5 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + HPME + High-priority message interrupt enable + 6 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + TCE + Transmission completed interrupt enable + 7 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + TCFE + Transmission cancellation finished interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + TFEE + Tx FIFO empty interrupt enable + 9 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + TEFNE + Tx event FIFO new entry interrupt enable + 10 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + TEFFE + Tx event FIFO full interrupt enable + 11 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + TEFLE + Tx event FIFO element lost interrupt enable + 12 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + TSWE + Timestamp wraparound interrupt enable + 13 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + MRAFE + Message RAM access failure interrupt enable + 14 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + TOOE + Timeout occurred interrupt enable + 15 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + ELOE + Error logging overflow interrupt enable + 16 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EPE + Error passive interrupt enable + 17 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EWE + Warning status interrupt enable + 18 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + BOE + Bus_Off status + 19 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + WDIE + Watchdog interrupt enable + 20 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + PEAE + Protocol error in arbitration phase enable + 21 + 1 + read-write + + + PEDE + Protocol error in data phase enable + 22 + 1 + read-write + + + ARAE + Access to reserved address enable + 23 + 1 + read-write + + + + + FDCAN_ILS + FDCAN_ILS + FDCAN interrupt line select register + 0x0058 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RXFIFO0 + RX FIFO bit grouping the following interruption + + 0 + 1 + read-write + + + RXFIFO1 + RX FIFO bit grouping the following interruption + + 1 + 1 + read-write + + + SMSG + Status message bit grouping the following interruption + + 2 + 1 + read-write + + + TFERR + Tx FIFO ERROR grouping the following interruption + + 3 + 1 + read-write + + + MISC + Interrupt regrouping the following interruption + + 4 + 1 + read-write + + + BERR + Bit and line error grouping the following interruption + + 5 + 1 + read-write + + + PERR + Protocol error grouping the following interruption + + 6 + 1 + read-write + + + + + FDCAN_ILE + FDCAN_ILE + FDCAN interrupt line enable register + 0x005C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EINT0 + Enable interrupt line 0 + 0 + 1 + read-write + + + B_0x0 + Interrupt line fdcan_intr1_it disabled + 0x0 + + + B_0x1 + Interrupt line fdcan_intr1_it enabled + 0x1 + + + + + EINT1 + Enable interrupt line 1 + 1 + 1 + read-write + + + B_0x0 + Interrupt line fdcan_intr0_it disabled + 0x0 + + + B_0x1 + Interrupt line fdcan_intr0_it enabled + 0x1 + + + + + + + FDCAN_RXGFC + FDCAN_RXGFC + FDCAN global filter configuration register + 0x0080 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RRFE + Reject remote frames extended + + 0 + 1 + read-write + + + B_0x0 + Filter remote frames with 29-bit standard IDs + 0x0 + + + B_0x1 + Reject all remote frames with 29-bit standard IDs + 0x1 + + + + + RRFS + Reject remote frames standard + + 1 + 1 + read-write + + + B_0x0 + Filter remote frames with 11-bit standard IDs + 0x0 + + + B_0x1 + Reject all remote frames with 11-bit standard IDs + 0x1 + + + + + ANFE + Accept non-matching frames extended + + 2 + 2 + read-write + + + B_0x0 + Accept in Rx FIFO 0 + 0x0 + + + B_0x1 + Accept in Rx FIFO 1 + 0x1 + + + B_0x2 + Reject + 0x2 + + + B_0x3 + Reject + 0x3 + + + + + ANFS + Accept Non-matching frames standard + + 4 + 2 + read-write + + + B_0x0 + Accept in Rx FIFO 0 + 0x0 + + + B_0x1 + Accept in Rx FIFO 1 + 0x1 + + + B_0x2 + Reject + 0x2 + + + B_0x3 + Reject + 0x3 + + + + + F1OM + FIFO 1 operation mode (overwrite or blocking) + + 8 + 1 + read-write + + + F0OM + FIFO 0 operation mode (overwrite or blocking) + + 9 + 1 + read-write + + + LSS + List size standard + + 16 + 5 + read-write + + + B_0x0 + No standard message ID filter + 0x0 + + + + + LSE + List size extended + + 24 + 4 + read-write + + + B_0x0 + No extended message ID filter + 0x0 + + + + + + + FDCAN_XIDAM + FDCAN_XIDAM + FDCAN extended ID and mask register + 0x0084 + 0x20 + 0x1FFFFFFF + 0xFFFFFFFF + + + EIDM + Extended ID mask + + 0 + 29 + read-write + + + + + FDCAN_HPMS + FDCAN_HPMS + FDCAN high-priority message status register + 0x0088 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BIDX + Buffer index + + 0 + 3 + read-only + + + MSI + Message storage indicator + 6 + 2 + read-only + + + B_0x0 + No FIFO selected + 0x0 + + + B_0x1 + FIFO overrun + 0x1 + + + B_0x2 + Message stored in FIFO 0 + 0x2 + + + B_0x3 + Message stored in FIFO 1 + 0x3 + + + + + FIDX + Filter index + + 8 + 5 + read-only + + + FLST + Filter list + + 15 + 1 + read-only + + + B_0x0 + Standard filter list + 0x0 + + + B_0x1 + Extended filter list + 0x1 + + + + + + + FDCAN_RXF0S + FDCAN_RXF0S + FDCAN Rx FIFO 0 status register + 0x0090 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + F0FL + Rx FIFO 0 fill level + + 0 + 4 + read-only + + + F0GI + Rx FIFO 0 get index + + 8 + 2 + read-only + + + F0PI + Rx FIFO 0 put index + + 16 + 2 + read-only + + + F0F + Rx FIFO 0 full + 24 + 1 + read-only + + + B_0x0 + Rx FIFO 0 not full + 0x0 + + + B_0x1 + Rx FIFO 0 full + 0x1 + + + + + RF0L + Rx FIFO 0 message lost + + 25 + 1 + read-only + + + B_0x0 + No Rx FIFO 0 message lost + 0x0 + + + B_0x1 + Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size 0 + 0x1 + + + + + + + FDCAN_RXF0A + FDCAN_RXF0A + CAN Rx FIFO 0 acknowledge register + 0x0094 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + F0AI + Rx FIFO 0 acknowledge index + + 0 + 3 + read-write + + + + + FDCAN_RXF1S + FDCAN_RXF1S + FDCAN Rx FIFO 1 status register + 0x0098 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + F1FL + Rx FIFO 1 fill level + + 0 + 4 + read-only + + + F1GI + Rx FIFO 1 get index + + 8 + 2 + read-only + + + F1PI + Rx FIFO 1 put index + + 16 + 2 + read-only + + + F1F + Rx FIFO 1 full + 24 + 1 + read-only + + + B_0x0 + Rx FIFO 1 not full + 0x0 + + + B_0x1 + Rx FIFO 1 full + 0x1 + + + + + RF1L + Rx FIFO 1 message lost + + 25 + 1 + read-only + + + B_0x0 + No Rx FIFO 1 message lost + 0x0 + + + B_0x1 + Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size 0 + 0x1 + + + + + + + FDCAN_RXF1A + FDCAN_RXF1A + FDCAN Rx FIFO 1 acknowledge register + 0x009C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + F1AI + Rx FIFO 1 acknowledge index + + 0 + 3 + read-write + + + + + FDCAN_TXBC + FDCAN_TXBC + FDCAN Tx buffer configuration register + 0x00C0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TFQM + Tx FIFO/queue mode + + 24 + 1 + read-write + + + B_0x0 + Tx FIFO operation + 0x0 + + + B_0x1 + Tx queue operation. + 0x1 + + + + + + + FDCAN_TXFQS + FDCAN_TXFQS + FDCAN Tx FIFO/queue status register + 0x00C4 + 0x20 + 0x00000003 + 0xFFFFFFFF + + + TFFL + Tx FIFO free level + + 0 + 3 + read-only + + + TFGI + Tx FIFO get index + + 8 + 2 + read-only + + + TFQPI + Tx FIFO/queue put index + + 16 + 2 + read-only + + + TFQF + Tx FIFO/queue full + 21 + 1 + read-only + + + B_0x0 + Tx FIFO/queue not full + 0x0 + + + B_0x1 + Tx FIFO/queue full + 0x1 + + + + + + + FDCAN_TXBRP + FDCAN_TXBRP + FDCAN Tx buffer request pending register + 0x00C8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TRP + Transmission request pending + + 0 + 3 + read-only + + + B_0x0 + No transmission request pending + 0x0 + + + B_0x1 + Transmission request pending + 0x1 + + + + + + + FDCAN_TXBAR + FDCAN_TXBAR + FDCAN Tx buffer add request register + 0x00CC + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AR + Add request + + 0 + 3 + read-write + + + B_0x0 + No transmission request added + 0x0 + + + B_0x1 + Transmission requested added. + 0x1 + + + + + + + FDCAN_TXBCR + FDCAN_TXBCR + FDCAN Tx buffer cancellation request register + 0x00D0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CR + Cancellation request + + 0 + 3 + read-write + + + B_0x0 + No cancellation pending + 0x0 + + + B_0x1 + Cancellation pending + 0x1 + + + + + + + FDCAN_TXBTO + FDCAN_TXBTO + FDCAN Tx buffer transmission occurred register + 0x00D4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TO + Transmission occurred. + + 0 + 3 + read-only + + + B_0x0 + No transmission occurred + 0x0 + + + B_0x1 + Transmission occurred + 0x1 + + + + + + + FDCAN_TXBCF + FDCAN_TXBCF + FDCAN Tx buffer cancellation finished register + 0x00D8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CF + Cancellation finished + + 0 + 3 + read-only + + + B_0x0 + No transmit buffer cancellation + 0x0 + + + B_0x1 + Transmit buffer cancellation finished + 0x1 + + + + + + + FDCAN_TXBTIE + FDCAN_TXBTIE + FDCAN Tx buffer transmission interrupt enable register + 0x00DC + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIE + Transmission interrupt enable + + 0 + 3 + read-write + + + B_0x0 + Transmission interrupt disabled + 0x0 + + + B_0x1 + Transmission interrupt enable + 0x1 + + + + + + + FDCAN_TXBCIE + FDCAN_TXBCIE + FDCAN Tx buffer cancellation finished interrupt enable register + 0x00E0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CFIE + Cancellation finished interrupt enable. + + 0 + 3 + read-write + + + B_0x0 + Cancellation finished interrupt disabled + 0x0 + + + B_0x1 + Cancellation finished interrupt enabled + 0x1 + + + + + + + FDCAN_TXEFS + FDCAN_TXEFS + FDCAN Tx event FIFO status register + 0x00E4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EFFL + Event FIFO fill level + + 0 + 3 + read-only + + + EFGI + Event FIFO get index + + 8 + 2 + read-only + + + EFPI + Event FIFO put index + + 16 + 2 + read-only + + + EFF + Event FIFO full + 24 + 1 + read-only + + + B_0x0 + Tx event FIFO not full + 0x0 + + + B_0x1 + Tx event FIFO full + 0x1 + + + + + TEFL + Tx event FIFO element lost + + 25 + 1 + read-only + + + + + FDCAN_TXEFA + FDCAN_TXEFA + FDCAN Tx event FIFO acknowledge register + 0x00E8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EFAI + Event FIFO acknowledge index + + 0 + 2 + read-write + + + + + FDCAN_CKDIV + FDCAN_CKDIV + FDCAN CFG clock divider register + 0x0100 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PDIV + input clock divider + + 0 + 4 + read-write + + + B_0x0 + Divide by 1 + 0x0 + + + B_0x1 + Divide by 2 + 0x1 + + + B_0x2 + Divide by 4 + 0x2 + + + B_0x3 + Divide by 6 + 0x3 + + + B_0x4 + Divide by 8 + 0x4 + + + B_0x5 + Divide by 10 + 0x5 + + + B_0x6 + Divide by 12 + 0x6 + + + B_0x7 + Divide by 14 + 0x7 + + + B_0x8 + Divide by 16 + 0x8 + + + B_0x9 + Divide by 18 + 0x9 + + + B_0xA + Divide by 20 + 0xA + + + B_0xB + Divide by 22 + 0xB + + + B_0xC + Divide by 24 + 0xC + + + B_0xD + Divide by 26 + 0xD + + + B_0xE + Divide by 28 + 0xE + + + B_0xF + Divide by 30 + 0xF + + + + + + + + + FDCAN1 + 0x40006400 + + FDCAN1_IT0 + FDCAN1 interrupt 0 + 21 + + + FDCAN1_IT1 + FDCAN1 interrupt 1 + 22 + + + + FLASH + Flash + Flash + 0x40022000 + + 0x0 + 0x400 + registers + + + FLASH + FLASH + 4 + + + + FLASH_ACR + FLASH_ACR + Flash access control register + 0x00 + 0x20 + read-write + 0x00040601 + 0xFFFFFFFF + + + LATENCY + Latency + + 0 + 4 + read-write + + + B_0x0 + Zero wait state + 0x0 + + + B_0x1 + One wait state + 0x1 + + + B_0x2 + Two wait states + 0x2 + + + B_0x3 + Three wait states + 0x3 + + + B_0x4 + Four wait states + 0x4 + + + + + PRFTEN + Prefetch enable + 8 + 1 + read-write + + + B_0x0 + Prefetch disabled + 0x0 + + + B_0x1 + Prefetch enabled + 0x1 + + + + + ICEN + Instruction cache enable + 9 + 1 + read-write + + + B_0x0 + Instruction cache is disabled + 0x0 + + + B_0x1 + Instruction cache is enabled + 0x1 + + + + + DCEN + Data cache enable + 10 + 1 + read-write + + + B_0x0 + Data cache is disabled + 0x0 + + + B_0x1 + Data cache is enabled + 0x1 + + + + + ICRST + Instruction cache reset + + 11 + 1 + read-write + + + B_0x0 + Instruction cache is not reset + 0x0 + + + B_0x1 + Instruction cache is reset + 0x1 + + + + + DCRST + Data cache reset + + 12 + 1 + read-write + + + B_0x0 + Data cache is not reset + 0x0 + + + B_0x1 + Data cache is reset + 0x1 + + + + + RUN_PD + Flash Power-down mode during Run or Low-power run mode + + 13 + 1 + read-write + + + B_0x0 + Flash in Idle mode + 0x0 + + + B_0x1 + Flash in Power-down mode + 0x1 + + + + + SLEEP_PD + Flash Power-down mode during Sleep or Low-power sleep mode + + 14 + 1 + read-write + + + B_0x0 + Flash in Idle mode during Sleep and Low-power sleep modes + 0x0 + + + B_0x1 + Flash in Power-down mode during Sleep and Low-power sleep modes + 0x1 + + + + + DBG_SWEN + Debug software enable + + 18 + 1 + read-write + + + B_0x0 + Debugger disabled + 0x0 + + + B_0x1 + Debugger enabled + 0x1 + + + + + + + FLASH_PDKEYR + FLASH_PDKEYR + Flash Power-down key register + 0x04 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + PDKEYR + Power-down in Run mode Flash key + + 0 + 32 + write-only + + + + + FLASH_KEYR + FLASH_KEYR + Flash key register + 0x08 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + KEYR + Flash key + + 0 + 32 + write-only + + + + + FLASH_OPTKEYR + FLASH_OPTKEYR + Flash option key register + 0x0C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + OPTKEYR + Option byte key + + 0 + 32 + write-only + + + + + FLASH_SR + FLASH_SR + Flash status register + 0x10 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EOP + End of operation + + 0 + 1 + read-write + + + OPERR + Operation error + + 1 + 1 + read-write + + + PROGERR + Programming error + + 3 + 1 + read-write + + + WRPERR + Write protection error + + 4 + 1 + read-write + + + PGAERR + Programming alignment error + + 5 + 1 + read-write + + + SIZERR + Size error + + 6 + 1 + read-write + + + PGSERR + Programming sequence error + + 7 + 1 + read-write + + + MISSERR + Fast programming data miss error + + 8 + 1 + read-write + + + FASTERR + Fast programming error + + 9 + 1 + read-write + + + RDERR + PCROP read error + + 14 + 1 + read-write + + + OPTVERR + Option validity error + + 15 + 1 + read-write + + + BSY + Busy + + 16 + 1 + read-only + + + + + FLASH_CR + FLASH_CR + Flash control register + 0x14 + 0x20 + read-write + 0xC0000000 + 0xFFFFFFFF + + + PG + Programming + 0 + 1 + read-write + + + B_0x0 + Flash programming disabled + 0x0 + + + B_0x1 + Flash programming enabled + 0x1 + + + + + PER + Page erase + 1 + 1 + read-write + + + B_0x0 + page erase disabled + 0x0 + + + B_0x1 + page erase enabled + 0x1 + + + + + MER1 + Mass erase + + 2 + 1 + read-write + + + PNB + Page number selection + + 3 + 6 + read-write + + + B_0x0 + page 0 + 0x0 + + + B_0x1 + page 1 + 0x1 + + + + + STRT + None + 16 + 1 + read-write + + + OPTSTRT + Options modification start + + 17 + 1 + read-write + + + FSTPG + Fast programming + 18 + 1 + read-write + + + B_0x0 + Fast programming disabled + 0x0 + + + B_0x1 + Fast programming enabled + 0x1 + + + + + EOPIE + End of operation interrupt enable + + 24 + 1 + read-write + + + B_0x0 + EOP Interrupt disabled + 0x0 + + + B_0x1 + EOP Interrupt enabled + 0x1 + + + + + ERRIE + Error interrupt enable + + 25 + 1 + read-write + + + B_0x0 + OPERR error interrupt disabled + 0x0 + + + B_0x1 + OPERR error interrupt enabled + 0x1 + + + + + RDERRIE + PCROP read error interrupt enable + + 26 + 1 + read-write + + + B_0x0 + PCROP read error interrupt disabled + 0x0 + + + B_0x1 + PCROP read error interrupt enabled + 0x1 + + + + + OBL_LAUNCH + Force the option byte loading + + 27 + 1 + read-write + + + B_0x0 + Option byte loading complete + 0x0 + + + B_0x1 + Option byte loading requested + 0x1 + + + + + SEC_PROT1 + Securable memory area protection bit. + + 28 + 1 + read-write + + + OPTLOCK + Options Lock + + 30 + 1 + read-write + + + LOCK + FLASH_CR Lock + + 31 + 1 + read-write + + + + + FLASH_ECCR + FLASH_ECCR + Flash ECC register + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ADDR_ECC + ECC fail address + + 0 + 19 + read-only + + + SYSF_ECC + System Flash ECC fail + + 22 + 1 + read-only + + + ECCCIE + None + 24 + 1 + read-write + + + ECCC + ECC correction + + 30 + 1 + read-write + + + ECCD + ECC detection + + 31 + 1 + read-write + + + + + FLASH_OPTR + FLASH_OPTR + 0x20 + 0x20 + read-write + + + RDP + Read protection level + + 0 + 8 + read-write + + + B_0xAA + Level 0, read protection not active + 0xAA + + + B_0xCC + Level 2, chip read protection active + 0xCC + + + + + BOR_LEV + BOR reset Level + + 8 + 3 + read-write + + + B_0x0 + BOR Level 0. Reset level threshold is around 1.7 V + 0x0 + + + B_0x1 + BOR Level 1. Reset level threshold is around 2.0 V + 0x1 + + + B_0x2 + BOR Level 2. Reset level threshold is around 2.2 V + 0x2 + + + B_0x3 + BOR Level 3. Reset level threshold is around 2.5 V + 0x3 + + + B_0x4 + BOR Level 4. Reset level threshold is around 2.8 V + 0x4 + + + + + nRST_STOP + None + 12 + 1 + read-write + + + nRST_STDBY + None + 13 + 1 + read-write + + + nRST_SHDW + None + 14 + 1 + read-write + + + IWDG_SW + Independent watchdog selection + 16 + 1 + read-write + + + B_0x0 + Hardware independent watchdog + 0x0 + + + B_0x1 + Software independent watchdog + 0x1 + + + + + IWDG_STOP + Independent watchdog counter freeze in Stop mode + 17 + 1 + read-write + + + B_0x0 + Independent watchdog counter is frozen in Stop mode + 0x0 + + + B_0x1 + Independent watchdog counter is running in Stop mode + 0x1 + + + + + IWGD_STDBY + None + 18 + 1 + read-write + + + WWDG_SW + Window watchdog selection + 19 + 1 + read-write + + + B_0x0 + Hardware window watchdog + 0x0 + + + B_0x1 + Software window watchdog + 0x1 + + + + + nBOOT1 + Boot configuration + + 23 + 1 + read-write + + + SRAM_PE + SRAM1 and CCM SRAM parity check enable + 24 + 1 + read-write + + + B_0x0 + SRAM1 and CCM SRAM parity check enable + 0x0 + + + B_0x1 + SRAM1 and CCM SRAM parity check disable + 0x1 + + + + + CCMSRAM_RST + None + 25 + 1 + read-write + + + nSWBOOT0 + Software BOOT0 + 26 + 1 + read-write + + + B_0x0 + BOOT0 taken from the option bit nBOOT0 + 0x0 + + + B_0x1 + BOOT0 taken from PB8/BOOT0 pin + 0x1 + + + + + nBOOT0 + nBOOT0 option bit + 27 + 1 + read-write + + + B_0x0 + nBOOT0 = 0 + 0x0 + + + B_0x1 + nBOOT0 = 1 + 0x1 + + + + + NRST_MODE + None + 28 + 2 + read-write + + + B_0x1 + Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin + 0x1 + + + B_0x2 + GPIO: standard GPIO pad functionality, only internal RESET possible + 0x2 + + + B_0x3 + Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode) + 0x3 + + + + + IRHEN + Internal reset holder enable bit + 30 + 1 + read-write + + + B_0x0 + Internal resets are propagated as simple pulse on NRST pin + 0x0 + + + B_0x1 + Internal resets drives NRST pin low until it is seen as low level + 0x1 + + + + + + + FLASH_PCROP1SR + FLASH_PCROP1SR + Flash PCROP1 Start address register + 0x24 + 0x20 + read-write + 0xFFFF0000 + 0xFFFF0000 + + + PCROP1_STRT + PCROP area start offset + + 0 + 15 + read-write + + + + + FLASH_PCROP1ER + FLASH_PCROP1ER + Flash PCROP1 End address register + 0x28 + 0x20 + read-write + 0x00000000 + 0x0FFF0000 + + + PCROP1_END + PCROP area end offset + + 0 + 15 + read-write + + + PCROP_RDP + PCROP area preserved when RDP level decreased + + 31 + 1 + read-write + + + B_0x0 + PCROP area is not erased when the RDP level is decreased from Level 1 to Level 0. + 0x0 + + + B_0x1 + PCROP area is erased when the RDP level is decreased from Level 1 to Level 0 (full mass erase). + 0x1 + + + + + + + FLASH_WRP1AR + FLASH_WRP1AR + Flash WRP area A address register + 0x2C + 0x20 + read-write + 0x00000000 + 0xFF00FF00 + + + WRP1A_STRT + WRP first area A start offset + + 0 + 6 + read-write + + + WRP1A_END + WRP first area A end offset + + 16 + 6 + read-write + + + + + FLASH_WRP1BR + FLASH_WRP1BR + Flash WRP area B address register + 0x30 + 0x20 + read-write + 0x00000000 + 0xFF00FF00 + + + WRP1B_STRT + WRP second area B start offset + + 0 + 6 + read-write + + + WRP1B_END + WRP second area B end offset + + 16 + 6 + read-write + + + + + FLASH_SEC1R + FLASH_SEC1R + Flash Securable area register + 0x70 + 0x20 + read-write + 0xFFF0FF00 + 0xFFF0FF00 + + + SEC_SIZE1 + sets the number of pages used in the Securable area. + + 0 + 7 + read-write + + + BOOT_LOCK + used to force boot from user Flash area + 16 + 1 + read-write + + + B_0x0 + Boot based on the pad/option bit configuration + 0x0 + + + B_0x1 + Boot forced from Main Flash memory + 0x1 + + + + + + + + + FMAC + Filter Math Accelerator + FMAC + 0x40021400 + + 0x0 + 0xC00 + registers + + + FMAC + FMAC + 101 + + + + X1BUFCFG + X1BUFCFG + FMAC X1 Buffer Configuration register + 0x0 + 0x20 + read-write + 0x00000000 + + + X1_BASE + X1_BASE + 0 + 8 + + + X1_BUF_SIZE + X1_BUF_SIZE + 8 + 8 + + + FULL_WM + FULL_WM + 24 + 2 + + + + + X2BUFCFG + X2BUFCFG + FMAC X2 Buffer Configuration register + 0x4 + 0x20 + read-write + 0x00000000 + + + X2_BASE + X1_BASE + 0 + 8 + + + X2_BUF_SIZE + X1_BUF_SIZE + 8 + 8 + + + + + YBUFCFG + YBUFCFG + FMAC Y Buffer Configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + Y_BASE + X1_BASE + 0 + 8 + + + Y_BUF_SIZE + X1_BUF_SIZE + 8 + 8 + + + EMPTY_WM + EMPTY_WM + 24 + 2 + + + + + PARAM + PARAM + FMAC Parameter register + 0xC + 0x20 + read-write + 0x00000000 + + + START + START + 31 + 1 + + + FUNC + FUNC + 24 + 7 + + + R + R + 16 + 8 + + + Q + Q + 8 + 8 + + + P + P + 0 + 8 + + + + + CR + CR + FMAC Control register + 0x10 + 0x20 + read-write + 0x00000000 + + + RESET + RESET + 16 + 1 + + + CLIPEN + CLIPEN + 15 + 1 + + + DMAWEN + DMAWEN + 9 + 1 + + + DMAREN + DMAREN + 8 + 1 + + + SATIEN + SATIEN + 4 + 1 + + + UNFLIEN + UNFLIEN + 3 + 1 + + + OVFLIEN + OVFLIEN + 2 + 1 + + + WIEN + WIEN + 1 + 1 + + + RIEN + RIEN + 0 + 1 + + + + + SR + SR + FMAC Status register + 0x14 + 0x20 + read-only + 0x00000000 + + + YEMPTY + YEMPTY + 0 + 1 + + + X1FULL + X1FULL + 1 + 1 + + + OVFL + OVFL + 8 + 1 + + + UNFL + UNFL + 9 + 1 + + + SAT + SAT + 10 + 1 + + + + + WDATA + WDATA + FMAC Write Data register + 0x18 + 0x20 + write-only + 0x00000000 + + + WDATA + WDATA + 0 + 16 + + + + + RDATA + RDATA + FMAC Read Data register + 0x1C + 0x20 + read-only + 0x00000000 + + + RDATA + RDATA + 0 + 16 + + + + + + + GPIOA + General-purpose I/Os + GPIO + 0x48000000 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xABFFFFFF + + + MODER15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + MODER14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + MODER13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + MODER12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + MODER11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + MODER10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + MODER9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + MODER8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + MODER7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + MODER6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + MODER5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + MODER4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + MODER3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + MODER2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + MODER1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + MODER0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT15 + Port x configuration bits (y = 0..15) + 15 + 1 + + + OT14 + Port x configuration bits (y = 0..15) + 14 + 1 + + + OT13 + Port x configuration bits (y = 0..15) + 13 + 1 + + + OT12 + Port x configuration bits (y = 0..15) + 12 + 1 + + + OT11 + Port x configuration bits (y = 0..15) + 11 + 1 + + + OT10 + Port x configuration bits (y = 0..15) + 10 + 1 + + + OT9 + Port x configuration bits (y = 0..15) + 9 + 1 + + + OT8 + Port x configuration bits (y = 0..15) + 8 + 1 + + + OT7 + Port x configuration bits (y = 0..15) + 7 + 1 + + + OT6 + Port x configuration bits (y = 0..15) + 6 + 1 + + + OT5 + Port x configuration bits (y = 0..15) + 5 + 1 + + + OT4 + Port x configuration bits (y = 0..15) + 4 + 1 + + + OT3 + Port x configuration bits (y = 0..15) + 3 + 1 + + + OT2 + Port x configuration bits (y = 0..15) + 2 + 1 + + + OT1 + Port x configuration bits (y = 0..15) + 1 + 1 + + + OT0 + Port x configuration bits (y = 0..15) + 0 + 1 + + + + + OSPEEDR + OSPEEDR + GPIO port output speed register + 0x8 + 0x20 + read-write + 0x0C000000 + + + OSPEEDR15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + OSPEEDR14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + OSPEEDR13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + OSPEEDR12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + OSPEEDR11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + OSPEEDR10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + OSPEEDR9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + OSPEEDR8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + OSPEEDR7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + OSPEEDR6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + OSPEEDR5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + OSPEEDR4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + OSPEEDR3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + OSPEEDR2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + OSPEEDR1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + OSPEEDR0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down register + 0xC + 0x20 + read-write + 0x64000000 + + + PUPDR15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + PUPDR14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + PUPDR13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + PUPDR12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + PUPDR11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + PUPDR10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + PUPDR9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + PUPDR8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + PUPDR7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + PUPDR6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + PUPDR5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + PUPDR4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + PUPDR3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + PUPDR2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + PUPDR1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + PUPDR0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR15 + Port input data (y = 0..15) + 15 + 1 + + + IDR14 + Port input data (y = 0..15) + 14 + 1 + + + IDR13 + Port input data (y = 0..15) + 13 + 1 + + + IDR12 + Port input data (y = 0..15) + 12 + 1 + + + IDR11 + Port input data (y = 0..15) + 11 + 1 + + + IDR10 + Port input data (y = 0..15) + 10 + 1 + + + IDR9 + Port input data (y = 0..15) + 9 + 1 + + + IDR8 + Port input data (y = 0..15) + 8 + 1 + + + IDR7 + Port input data (y = 0..15) + 7 + 1 + + + IDR6 + Port input data (y = 0..15) + 6 + 1 + + + IDR5 + Port input data (y = 0..15) + 5 + 1 + + + IDR4 + Port input data (y = 0..15) + 4 + 1 + + + IDR3 + Port input data (y = 0..15) + 3 + 1 + + + IDR2 + Port input data (y = 0..15) + 2 + 1 + + + IDR1 + Port input data (y = 0..15) + 1 + 1 + + + IDR0 + Port input data (y = 0..15) + 0 + 1 + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR15 + Port output data (y = 0..15) + 15 + 1 + + + ODR14 + Port output data (y = 0..15) + 14 + 1 + + + ODR13 + Port output data (y = 0..15) + 13 + 1 + + + ODR12 + Port output data (y = 0..15) + 12 + 1 + + + ODR11 + Port output data (y = 0..15) + 11 + 1 + + + ODR10 + Port output data (y = 0..15) + 10 + 1 + + + ODR9 + Port output data (y = 0..15) + 9 + 1 + + + ODR8 + Port output data (y = 0..15) + 8 + 1 + + + ODR7 + Port output data (y = 0..15) + 7 + 1 + + + ODR6 + Port output data (y = 0..15) + 6 + 1 + + + ODR5 + Port output data (y = 0..15) + 5 + 1 + + + ODR4 + Port output data (y = 0..15) + 4 + 1 + + + ODR3 + Port output data (y = 0..15) + 3 + 1 + + + ODR2 + Port output data (y = 0..15) + 2 + 1 + + + ODR1 + Port output data (y = 0..15) + 1 + 1 + + + ODR0 + Port output data (y = 0..15) + 0 + 1 + + + + + BSRR + BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + + + BR15 + Port x reset bit y (y = 0..15) + 31 + 1 + + + BR14 + Port x reset bit y (y = 0..15) + 30 + 1 + + + BR13 + Port x reset bit y (y = 0..15) + 29 + 1 + + + BR12 + Port x reset bit y (y = 0..15) + 28 + 1 + + + BR11 + Port x reset bit y (y = 0..15) + 27 + 1 + + + BR10 + Port x reset bit y (y = 0..15) + 26 + 1 + + + BR9 + Port x reset bit y (y = 0..15) + 25 + 1 + + + BR8 + Port x reset bit y (y = 0..15) + 24 + 1 + + + BR7 + Port x reset bit y (y = 0..15) + 23 + 1 + + + BR6 + Port x reset bit y (y = 0..15) + 22 + 1 + + + BR5 + Port x reset bit y (y = 0..15) + 21 + 1 + + + BR4 + Port x reset bit y (y = 0..15) + 20 + 1 + + + BR3 + Port x reset bit y (y = 0..15) + 19 + 1 + + + BR2 + Port x reset bit y (y = 0..15) + 18 + 1 + + + BR1 + Port x reset bit y (y = 0..15) + 17 + 1 + + + BR0 + Port x set bit y (y= 0..15) + 16 + 1 + + + BS15 + Port x set bit y (y= 0..15) + 15 + 1 + + + BS14 + Port x set bit y (y= 0..15) + 14 + 1 + + + BS13 + Port x set bit y (y= 0..15) + 13 + 1 + + + BS12 + Port x set bit y (y= 0..15) + 12 + 1 + + + BS11 + Port x set bit y (y= 0..15) + 11 + 1 + + + BS10 + Port x set bit y (y= 0..15) + 10 + 1 + + + BS9 + Port x set bit y (y= 0..15) + 9 + 1 + + + BS8 + Port x set bit y (y= 0..15) + 8 + 1 + + + BS7 + Port x set bit y (y= 0..15) + 7 + 1 + + + BS6 + Port x set bit y (y= 0..15) + 6 + 1 + + + BS5 + Port x set bit y (y= 0..15) + 5 + 1 + + + BS4 + Port x set bit y (y= 0..15) + 4 + 1 + + + BS3 + Port x set bit y (y= 0..15) + 3 + 1 + + + BS2 + Port x set bit y (y= 0..15) + 2 + 1 + + + BS1 + Port x set bit y (y= 0..15) + 1 + 1 + + + BS0 + Port x set bit y (y= 0..15) + 0 + 1 + + + + + LCKR + LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y (y= 0..15) + 16 + 1 + + + LCK15 + Port x lock bit y (y= 0..15) + 15 + 1 + + + LCK14 + Port x lock bit y (y= 0..15) + 14 + 1 + + + LCK13 + Port x lock bit y (y= 0..15) + 13 + 1 + + + LCK12 + Port x lock bit y (y= 0..15) + 12 + 1 + + + LCK11 + Port x lock bit y (y= 0..15) + 11 + 1 + + + LCK10 + Port x lock bit y (y= 0..15) + 10 + 1 + + + LCK9 + Port x lock bit y (y= 0..15) + 9 + 1 + + + LCK8 + Port x lock bit y (y= 0..15) + 8 + 1 + + + LCK7 + Port x lock bit y (y= 0..15) + 7 + 1 + + + LCK6 + Port x lock bit y (y= 0..15) + 6 + 1 + + + LCK5 + Port x lock bit y (y= 0..15) + 5 + 1 + + + LCK4 + Port x lock bit y (y= 0..15) + 4 + 1 + + + LCK3 + Port x lock bit y (y= 0..15) + 3 + 1 + + + LCK2 + Port x lock bit y (y= 0..15) + 2 + 1 + + + LCK1 + Port x lock bit y (y= 0..15) + 1 + 1 + + + LCK0 + Port x lock bit y (y= 0..15) + 0 + 1 + + + + + AFRL + AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFRL7 + Alternate function selection for port x bit y (y = 0..7) + 28 + 4 + + + AFRL6 + Alternate function selection for port x bit y (y = 0..7) + 24 + 4 + + + AFRL5 + Alternate function selection for port x bit y (y = 0..7) + 20 + 4 + + + AFRL4 + Alternate function selection for port x bit y (y = 0..7) + 16 + 4 + + + AFRL3 + Alternate function selection for port x bit y (y = 0..7) + 12 + 4 + + + AFRL2 + Alternate function selection for port x bit y (y = 0..7) + 8 + 4 + + + AFRL1 + Alternate function selection for port x bit y (y = 0..7) + 4 + 4 + + + AFRL0 + Alternate function selection for port x bit y (y = 0..7) + 0 + 4 + + + + + AFRH + AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFRH15 + Alternate function selection for port x bit y (y = 8..15) + 28 + 4 + + + AFRH14 + Alternate function selection for port x bit y (y = 8..15) + 24 + 4 + + + AFRH13 + Alternate function selection for port x bit y (y = 8..15) + 20 + 4 + + + AFRH12 + Alternate function selection for port x bit y (y = 8..15) + 16 + 4 + + + AFRH11 + Alternate function selection for port x bit y (y = 8..15) + 12 + 4 + + + AFRH10 + Alternate function selection for port x bit y (y = 8..15) + 8 + 4 + + + AFRH9 + Alternate function selection for port x bit y (y = 8..15) + 4 + 4 + + + AFRH8 + Alternate function selection for port x bit y (y = 8..15) + 0 + 4 + + + + + BRR + BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + Port Reset bit + 0 + 1 + + + BR1 + Port Reset bit + 1 + 1 + + + BR2 + Port Reset bit + 2 + 1 + + + BR3 + Port Reset bit + 3 + 1 + + + BR4 + Port Reset bit + 4 + 1 + + + BR5 + Port Reset bit + 5 + 1 + + + BR6 + Port Reset bit + 6 + 1 + + + BR7 + Port Reset bit + 7 + 1 + + + BR8 + Port Reset bit + 8 + 1 + + + BR9 + Port Reset bit + 9 + 1 + + + BR10 + Port Reset bit + 10 + 1 + + + BR11 + Port Reset bit + 11 + 1 + + + BR12 + Port Reset bit + 12 + 1 + + + BR13 + Port Reset bit + 13 + 1 + + + BR14 + Port Reset bit + 14 + 1 + + + BR15 + Port Reset bit + 15 + 1 + + + + + + + GPIOB + General-purpose I/Os + GPIO + 0x48000400 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xFFFFFEBF + + + MODER15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + MODER14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + MODER13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + MODER12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + MODER11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + MODER10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + MODER9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + MODER8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + MODER7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + MODER6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + MODER5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + MODER4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + MODER3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + MODER2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + MODER1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + MODER0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT15 + Port x configuration bits (y = 0..15) + 15 + 1 + + + OT14 + Port x configuration bits (y = 0..15) + 14 + 1 + + + OT13 + Port x configuration bits (y = 0..15) + 13 + 1 + + + OT12 + Port x configuration bits (y = 0..15) + 12 + 1 + + + OT11 + Port x configuration bits (y = 0..15) + 11 + 1 + + + OT10 + Port x configuration bits (y = 0..15) + 10 + 1 + + + OT9 + Port x configuration bits (y = 0..15) + 9 + 1 + + + OT8 + Port x configuration bits (y = 0..15) + 8 + 1 + + + OT7 + Port x configuration bits (y = 0..15) + 7 + 1 + + + OT6 + Port x configuration bits (y = 0..15) + 6 + 1 + + + OT5 + Port x configuration bits (y = 0..15) + 5 + 1 + + + OT4 + Port x configuration bits (y = 0..15) + 4 + 1 + + + OT3 + Port x configuration bits (y = 0..15) + 3 + 1 + + + OT2 + Port x configuration bits (y = 0..15) + 2 + 1 + + + OT1 + Port x configuration bits (y = 0..15) + 1 + 1 + + + OT0 + Port x configuration bits (y = 0..15) + 0 + 1 + + + + + OSPEEDR + OSPEEDR + GPIO port output speed register + 0x8 + 0x20 + read-write + 0x000000C0 + + + OSPEEDR15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + OSPEEDR14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + OSPEEDR13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + OSPEEDR12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + OSPEEDR11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + OSPEEDR10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + OSPEEDR9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + OSPEEDR8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + OSPEEDR7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + OSPEEDR6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + OSPEEDR5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + OSPEEDR4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + OSPEEDR3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + OSPEEDR2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + OSPEEDR1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + OSPEEDR0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000100 + + + PUPDR15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + PUPDR14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + PUPDR13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + PUPDR12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + PUPDR11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + PUPDR10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + PUPDR9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + PUPDR8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + PUPDR7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + PUPDR6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + PUPDR5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + PUPDR4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + PUPDR3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + PUPDR2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + PUPDR1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + PUPDR0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR15 + Port input data (y = 0..15) + 15 + 1 + + + IDR14 + Port input data (y = 0..15) + 14 + 1 + + + IDR13 + Port input data (y = 0..15) + 13 + 1 + + + IDR12 + Port input data (y = 0..15) + 12 + 1 + + + IDR11 + Port input data (y = 0..15) + 11 + 1 + + + IDR10 + Port input data (y = 0..15) + 10 + 1 + + + IDR9 + Port input data (y = 0..15) + 9 + 1 + + + IDR8 + Port input data (y = 0..15) + 8 + 1 + + + IDR7 + Port input data (y = 0..15) + 7 + 1 + + + IDR6 + Port input data (y = 0..15) + 6 + 1 + + + IDR5 + Port input data (y = 0..15) + 5 + 1 + + + IDR4 + Port input data (y = 0..15) + 4 + 1 + + + IDR3 + Port input data (y = 0..15) + 3 + 1 + + + IDR2 + Port input data (y = 0..15) + 2 + 1 + + + IDR1 + Port input data (y = 0..15) + 1 + 1 + + + IDR0 + Port input data (y = 0..15) + 0 + 1 + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR15 + Port output data (y = 0..15) + 15 + 1 + + + ODR14 + Port output data (y = 0..15) + 14 + 1 + + + ODR13 + Port output data (y = 0..15) + 13 + 1 + + + ODR12 + Port output data (y = 0..15) + 12 + 1 + + + ODR11 + Port output data (y = 0..15) + 11 + 1 + + + ODR10 + Port output data (y = 0..15) + 10 + 1 + + + ODR9 + Port output data (y = 0..15) + 9 + 1 + + + ODR8 + Port output data (y = 0..15) + 8 + 1 + + + ODR7 + Port output data (y = 0..15) + 7 + 1 + + + ODR6 + Port output data (y = 0..15) + 6 + 1 + + + ODR5 + Port output data (y = 0..15) + 5 + 1 + + + ODR4 + Port output data (y = 0..15) + 4 + 1 + + + ODR3 + Port output data (y = 0..15) + 3 + 1 + + + ODR2 + Port output data (y = 0..15) + 2 + 1 + + + ODR1 + Port output data (y = 0..15) + 1 + 1 + + + ODR0 + Port output data (y = 0..15) + 0 + 1 + + + + + BSRR + BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + + + BR15 + Port x reset bit y (y = 0..15) + 31 + 1 + + + BR14 + Port x reset bit y (y = 0..15) + 30 + 1 + + + BR13 + Port x reset bit y (y = 0..15) + 29 + 1 + + + BR12 + Port x reset bit y (y = 0..15) + 28 + 1 + + + BR11 + Port x reset bit y (y = 0..15) + 27 + 1 + + + BR10 + Port x reset bit y (y = 0..15) + 26 + 1 + + + BR9 + Port x reset bit y (y = 0..15) + 25 + 1 + + + BR8 + Port x reset bit y (y = 0..15) + 24 + 1 + + + BR7 + Port x reset bit y (y = 0..15) + 23 + 1 + + + BR6 + Port x reset bit y (y = 0..15) + 22 + 1 + + + BR5 + Port x reset bit y (y = 0..15) + 21 + 1 + + + BR4 + Port x reset bit y (y = 0..15) + 20 + 1 + + + BR3 + Port x reset bit y (y = 0..15) + 19 + 1 + + + BR2 + Port x reset bit y (y = 0..15) + 18 + 1 + + + BR1 + Port x reset bit y (y = 0..15) + 17 + 1 + + + BR0 + Port x set bit y (y= 0..15) + 16 + 1 + + + BS15 + Port x set bit y (y= 0..15) + 15 + 1 + + + BS14 + Port x set bit y (y= 0..15) + 14 + 1 + + + BS13 + Port x set bit y (y= 0..15) + 13 + 1 + + + BS12 + Port x set bit y (y= 0..15) + 12 + 1 + + + BS11 + Port x set bit y (y= 0..15) + 11 + 1 + + + BS10 + Port x set bit y (y= 0..15) + 10 + 1 + + + BS9 + Port x set bit y (y= 0..15) + 9 + 1 + + + BS8 + Port x set bit y (y= 0..15) + 8 + 1 + + + BS7 + Port x set bit y (y= 0..15) + 7 + 1 + + + BS6 + Port x set bit y (y= 0..15) + 6 + 1 + + + BS5 + Port x set bit y (y= 0..15) + 5 + 1 + + + BS4 + Port x set bit y (y= 0..15) + 4 + 1 + + + BS3 + Port x set bit y (y= 0..15) + 3 + 1 + + + BS2 + Port x set bit y (y= 0..15) + 2 + 1 + + + BS1 + Port x set bit y (y= 0..15) + 1 + 1 + + + BS0 + Port x set bit y (y= 0..15) + 0 + 1 + + + + + LCKR + LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y (y= 0..15) + 16 + 1 + + + LCK15 + Port x lock bit y (y= 0..15) + 15 + 1 + + + LCK14 + Port x lock bit y (y= 0..15) + 14 + 1 + + + LCK13 + Port x lock bit y (y= 0..15) + 13 + 1 + + + LCK12 + Port x lock bit y (y= 0..15) + 12 + 1 + + + LCK11 + Port x lock bit y (y= 0..15) + 11 + 1 + + + LCK10 + Port x lock bit y (y= 0..15) + 10 + 1 + + + LCK9 + Port x lock bit y (y= 0..15) + 9 + 1 + + + LCK8 + Port x lock bit y (y= 0..15) + 8 + 1 + + + LCK7 + Port x lock bit y (y= 0..15) + 7 + 1 + + + LCK6 + Port x lock bit y (y= 0..15) + 6 + 1 + + + LCK5 + Port x lock bit y (y= 0..15) + 5 + 1 + + + LCK4 + Port x lock bit y (y= 0..15) + 4 + 1 + + + LCK3 + Port x lock bit y (y= 0..15) + 3 + 1 + + + LCK2 + Port x lock bit y (y= 0..15) + 2 + 1 + + + LCK1 + Port x lock bit y (y= 0..15) + 1 + 1 + + + LCK0 + Port x lock bit y (y= 0..15) + 0 + 1 + + + + + AFRL + AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFRL7 + Alternate function selection for port x bit y (y = 0..7) + 28 + 4 + + + AFRL6 + Alternate function selection for port x bit y (y = 0..7) + 24 + 4 + + + AFRL5 + Alternate function selection for port x bit y (y = 0..7) + 20 + 4 + + + AFRL4 + Alternate function selection for port x bit y (y = 0..7) + 16 + 4 + + + AFRL3 + Alternate function selection for port x bit y (y = 0..7) + 12 + 4 + + + AFRL2 + Alternate function selection for port x bit y (y = 0..7) + 8 + 4 + + + AFRL1 + Alternate function selection for port x bit y (y = 0..7) + 4 + 4 + + + AFRL0 + Alternate function selection for port x bit y (y = 0..7) + 0 + 4 + + + + + AFRH + AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFRH15 + Alternate function selection for port x bit y (y = 8..15) + 28 + 4 + + + AFRH14 + Alternate function selection for port x bit y (y = 8..15) + 24 + 4 + + + AFRH13 + Alternate function selection for port x bit y (y = 8..15) + 20 + 4 + + + AFRH12 + Alternate function selection for port x bit y (y = 8..15) + 16 + 4 + + + AFRH11 + Alternate function selection for port x bit y (y = 8..15) + 12 + 4 + + + AFRH10 + Alternate function selection for port x bit y (y = 8..15) + 8 + 4 + + + AFRH9 + Alternate function selection for port x bit y (y = 8..15) + 4 + 4 + + + AFRH8 + Alternate function selection for port x bit y (y = 8..15) + 0 + 4 + + + + + BRR + BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + Port Reset bit + 0 + 1 + + + BR1 + Port Reset bit + 1 + 1 + + + BR2 + Port Reset bit + 2 + 1 + + + BR3 + Port Reset bit + 3 + 1 + + + BR4 + Port Reset bit + 4 + 1 + + + BR5 + Port Reset bit + 5 + 1 + + + BR6 + Port Reset bit + 6 + 1 + + + BR7 + Port Reset bit + 7 + 1 + + + BR8 + Port Reset bit + 8 + 1 + + + BR9 + Port Reset bit + 9 + 1 + + + BR10 + Port Reset bit + 10 + 1 + + + BR11 + Port Reset bit + 11 + 1 + + + BR12 + Port Reset bit + 12 + 1 + + + BR13 + Port Reset bit + 13 + 1 + + + BR14 + Port Reset bit + 14 + 1 + + + BR15 + Port Reset bit + 15 + 1 + + + + + + + GPIOC + General-purpose I/Os + GPIO + 0x48000800 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + MODER15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + MODER14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + MODER13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + MODER12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + MODER11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + MODER10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + MODER9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + MODER8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + MODER7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + MODER6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + MODER5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + MODER4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + MODER3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + MODER2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + MODER1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + MODER0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT15 + Port x configuration bits (y = 0..15) + 15 + 1 + + + OT14 + Port x configuration bits (y = 0..15) + 14 + 1 + + + OT13 + Port x configuration bits (y = 0..15) + 13 + 1 + + + OT12 + Port x configuration bits (y = 0..15) + 12 + 1 + + + OT11 + Port x configuration bits (y = 0..15) + 11 + 1 + + + OT10 + Port x configuration bits (y = 0..15) + 10 + 1 + + + OT9 + Port x configuration bits (y = 0..15) + 9 + 1 + + + OT8 + Port x configuration bits (y = 0..15) + 8 + 1 + + + OT7 + Port x configuration bits (y = 0..15) + 7 + 1 + + + OT6 + Port x configuration bits (y = 0..15) + 6 + 1 + + + OT5 + Port x configuration bits (y = 0..15) + 5 + 1 + + + OT4 + Port x configuration bits (y = 0..15) + 4 + 1 + + + OT3 + Port x configuration bits (y = 0..15) + 3 + 1 + + + OT2 + Port x configuration bits (y = 0..15) + 2 + 1 + + + OT1 + Port x configuration bits (y = 0..15) + 1 + 1 + + + OT0 + Port x configuration bits (y = 0..15) + 0 + 1 + + + + + OSPEEDR + OSPEEDR + GPIO port output speed register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEEDR15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + OSPEEDR14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + OSPEEDR13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + OSPEEDR12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + OSPEEDR11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + OSPEEDR10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + OSPEEDR9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + OSPEEDR8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + OSPEEDR7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + OSPEEDR6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + OSPEEDR5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + OSPEEDR4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + OSPEEDR3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + OSPEEDR2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + OSPEEDR1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + OSPEEDR0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000000 + + + PUPDR15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + PUPDR14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + PUPDR13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + PUPDR12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + PUPDR11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + PUPDR10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + PUPDR9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + PUPDR8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + PUPDR7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + PUPDR6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + PUPDR5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + PUPDR4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + PUPDR3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + PUPDR2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + PUPDR1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + PUPDR0 + Port x configuration bits (y = 0..15) + 0 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Port output data (y = 0..15) + 15 + 1 + + + ODR14 + Port output data (y = 0..15) + 14 + 1 + + + ODR13 + Port output data (y = 0..15) + 13 + 1 + + + ODR12 + Port output data (y = 0..15) + 12 + 1 + + + ODR11 + Port output data (y = 0..15) + 11 + 1 + + + ODR10 + Port output data (y = 0..15) + 10 + 1 + + + ODR9 + Port output data (y = 0..15) + 9 + 1 + + + ODR8 + Port output data (y = 0..15) + 8 + 1 + + + ODR7 + Port output data (y = 0..15) + 7 + 1 + + + ODR6 + Port output data (y = 0..15) + 6 + 1 + + + ODR5 + Port output data (y = 0..15) + 5 + 1 + + + ODR4 + Port output data (y = 0..15) + 4 + 1 + + + ODR3 + Port output data (y = 0..15) + 3 + 1 + + + ODR2 + Port output data (y = 0..15) + 2 + 1 + + + ODR1 + Port output data (y = 0..15) + 1 + 1 + + + ODR0 + Port output data (y = 0..15) + 0 + 1 + + + + + BSRR + BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + + + BR15 + Port x reset bit y (y = 0..15) + 31 + 1 + + + BR14 + Port x reset bit y (y = 0..15) + 30 + 1 + + + BR13 + Port x reset bit y (y = 0..15) + 29 + 1 + + + BR12 + Port x reset bit y (y = 0..15) + 28 + 1 + + + BR11 + Port x reset bit y (y = 0..15) + 27 + 1 + + + BR10 + Port x reset bit y (y = 0..15) + 26 + 1 + + + BR9 + Port x reset bit y (y = 0..15) + 25 + 1 + + + BR8 + Port x reset bit y (y = 0..15) + 24 + 1 + + + BR7 + Port x reset bit y (y = 0..15) + 23 + 1 + + + BR6 + Port x reset bit y (y = 0..15) + 22 + 1 + + + BR5 + Port x reset bit y (y = 0..15) + 21 + 1 + + + BR4 + Port x reset bit y (y = 0..15) + 20 + 1 + + + BR3 + Port x reset bit y (y = 0..15) + 19 + 1 + + + BR2 + Port x reset bit y (y = 0..15) + 18 + 1 + + + BR1 + Port x reset bit y (y = 0..15) + 17 + 1 + + + BR0 + Port x set bit y (y= 0..15) + 16 + 1 + + + BS15 + Port x set bit y (y= 0..15) + 15 + 1 + + + BS14 + Port x set bit y (y= 0..15) + 14 + 1 + + + BS13 + Port x set bit y (y= 0..15) + 13 + 1 + + + BS12 + Port x set bit y (y= 0..15) + 12 + 1 + + + BS11 + Port x set bit y (y= 0..15) + 11 + 1 + + + BS10 + Port x set bit y (y= 0..15) + 10 + 1 + + + BS9 + Port x set bit y (y= 0..15) + 9 + 1 + + + BS8 + Port x set bit y (y= 0..15) + 8 + 1 + + + BS7 + Port x set bit y (y= 0..15) + 7 + 1 + + + BS6 + Port x set bit y (y= 0..15) + 6 + 1 + + + BS5 + Port x set bit y (y= 0..15) + 5 + 1 + + + BS4 + Port x set bit y (y= 0..15) + 4 + 1 + + + BS3 + Port x set bit y (y= 0..15) + 3 + 1 + + + BS2 + Port x set bit y (y= 0..15) + 2 + 1 + + + BS1 + Port x set bit y (y= 0..15) + 1 + 1 + + + BS0 + Port x set bit y (y= 0..15) + 0 + 1 + + + + + LCKR + LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y (y= 0..15) + 16 + 1 + + + LCK15 + Port x lock bit y (y= 0..15) + 15 + 1 + + + LCK14 + Port x lock bit y (y= 0..15) + 14 + 1 + + + LCK13 + Port x lock bit y (y= 0..15) + 13 + 1 + + + LCK12 + Port x lock bit y (y= 0..15) + 12 + 1 + + + LCK11 + Port x lock bit y (y= 0..15) + 11 + 1 + + + LCK10 + Port x lock bit y (y= 0..15) + 10 + 1 + + + LCK9 + Port x lock bit y (y= 0..15) + 9 + 1 + + + LCK8 + Port x lock bit y (y= 0..15) + 8 + 1 + + + LCK7 + Port x lock bit y (y= 0..15) + 7 + 1 + + + LCK6 + Port x lock bit y (y= 0..15) + 6 + 1 + + + LCK5 + Port x lock bit y (y= 0..15) + 5 + 1 + + + LCK4 + Port x lock bit y (y= 0..15) + 4 + 1 + + + LCK3 + Port x lock bit y (y= 0..15) + 3 + 1 + + + LCK2 + Port x lock bit y (y= 0..15) + 2 + 1 + + + LCK1 + Port x lock bit y (y= 0..15) + 1 + 1 + + + LCK0 + Port x lock bit y (y= 0..15) + 0 + 1 + + + + + AFRL + AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFRL7 + Alternate function selection for port x bit y (y = 0..7) + 28 + 4 + + + AFRL6 + Alternate function selection for port x bit y (y = 0..7) + 24 + 4 + + + AFRL5 + Alternate function selection for port x bit y (y = 0..7) + 20 + 4 + + + AFRL4 + Alternate function selection for port x bit y (y = 0..7) + 16 + 4 + + + AFRL3 + Alternate function selection for port x bit y (y = 0..7) + 12 + 4 + + + AFRL2 + Alternate function selection for port x bit y (y = 0..7) + 8 + 4 + + + AFRL1 + Alternate function selection for port x bit y (y = 0..7) + 4 + 4 + + + AFRL0 + Alternate function selection for port x bit y (y = 0..7) + 0 + 4 + + + + + AFRH + AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFRH15 + Alternate function selection for port x bit y (y = 8..15) + 28 + 4 + + + AFRH14 + Alternate function selection for port x bit y (y = 8..15) + 24 + 4 + + + AFRH13 + Alternate function selection for port x bit y (y = 8..15) + 20 + 4 + + + AFRH12 + Alternate function selection for port x bit y (y = 8..15) + 16 + 4 + + + AFRH11 + Alternate function selection for port x bit y (y = 8..15) + 12 + 4 + + + AFRH10 + Alternate function selection for port x bit y (y = 8..15) + 8 + 4 + + + AFRH9 + Alternate function selection for port x bit y (y = 8..15) + 4 + 4 + + + AFRH8 + Alternate function selection for port x bit y (y = 8..15) + 0 + 4 + + + + + BRR + BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + Port Reset bit + 0 + 1 + + + BR1 + Port Reset bit + 1 + 1 + + + BR2 + Port Reset bit + 2 + 1 + + + BR3 + Port Reset bit + 3 + 1 + + + BR4 + Port Reset bit + 4 + 1 + + + BR5 + Port Reset bit + 5 + 1 + + + BR6 + Port Reset bit + 6 + 1 + + + BR7 + Port Reset bit + 7 + 1 + + + BR8 + Port Reset bit + 8 + 1 + + + BR9 + Port Reset bit + 9 + 1 + + + BR10 + Port Reset bit + 10 + 1 + + + BR11 + Port Reset bit + 11 + 1 + + + BR12 + Port Reset bit + 12 + 1 + + + BR13 + Port Reset bit + 13 + 1 + + + BR14 + Port Reset bit + 14 + 1 + + + BR15 + Port Reset bit + 15 + 1 + + + + + + + GPIOD + 0x48000C00 + + + GPIOE + 0x48001000 + + + GPIOF + 0x48001400 + + + GPIOG + 0x48001800 + + + I2C1 + Inter-integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1_EV + I2C1_EV + 31 + + + I2C1_ER + I2C1_ER + 32 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + PE + Peripheral enable + 0 + 1 + + + TXIE + TX Interrupt enable + 1 + 1 + + + RXIE + RX Interrupt enable + 2 + 1 + + + ADDRIE + Address match interrupt enable (slave only) + 3 + 1 + + + NACKIE + Not acknowledge received interrupt enable + 4 + 1 + + + STOPIE + STOP detection Interrupt enable + 5 + 1 + + + TCIE + Transfer Complete interrupt enable + 6 + 1 + + + ERRIE + Error interrupts enable + 7 + 1 + + + DNF + Digital noise filter + 8 + 4 + + + ANFOFF + Analog noise filter OFF + 12 + 1 + + + TXDMAEN + DMA transmission requests enable + 14 + 1 + + + RXDMAEN + DMA reception requests enable + 15 + 1 + + + SBC + Slave byte control + 16 + 1 + + + NOSTRETCH + Clock stretching disable + 17 + 1 + + + WUPEN + Wakeup from STOP enable + 18 + 1 + + + GCEN + General call enable + 19 + 1 + + + SMBHEN + SMBus Host address enable + 20 + 1 + + + SMBDEN + SMBus Device Default address enable + 21 + 1 + + + ALERTEN + SMBUS alert enable + 22 + 1 + + + PECEN + PEC enable + 23 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + PECBYTE + Packet error checking byte + 26 + 1 + + + AUTOEND + Automatic end mode (master mode) + 25 + 1 + + + RELOAD + NBYTES reload mode + 24 + 1 + + + NBYTES + Number of bytes + 16 + 8 + + + NACK + NACK generation (slave mode) + 15 + 1 + + + STOP + Stop generation (master mode) + 14 + 1 + + + START + Start generation + 13 + 1 + + + HEAD10R + 10-bit address header only read direction (master receiver mode) + 12 + 1 + + + ADD10 + 10-bit addressing mode (master mode) + 11 + 1 + + + RD_WRN + Transfer direction (master mode) + 10 + 1 + + + SADD + Slave address bit (master mode) + 0 + 10 + + + + + OAR1 + OAR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x00000000 + + + OA1 + Interface address + 0 + 10 + + + OA1MODE + Own Address 1 10-bit mode + 10 + 1 + + + OA1EN + Own Address 1 enable + 15 + 1 + + + + + OAR2 + OAR2 + Own address register 2 + 0xC + 0x20 + read-write + 0x00000000 + + + OA2 + Interface address + 1 + 7 + + + OA2MSK + Own Address 2 masks + 8 + 3 + + + OA2EN + Own Address 2 enable + 15 + 1 + + + + + TIMINGR + TIMINGR + Timing register + 0x10 + 0x20 + read-write + 0x00000000 + + + SCLL + SCL low period (master mode) + 0 + 8 + + + SCLH + SCL high period (master mode) + 8 + 8 + + + SDADEL + Data hold time + 16 + 4 + + + SCLDEL + Data setup time + 20 + 4 + + + PRESC + Timing prescaler + 28 + 4 + + + + + TIMEOUTR + TIMEOUTR + Status register 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + TIMEOUTA + Bus timeout A + 0 + 12 + + + TIDLE + Idle clock timeout detection + 12 + 1 + + + TIMOUTEN + Clock timeout enable + 15 + 1 + + + TIMEOUTB + Bus timeout B + 16 + 12 + + + TEXTEN + Extended clock timeout enable + 31 + 1 + + + + + ISR + ISR + Interrupt and Status register + 0x18 + 0x20 + 0x00000001 + + + ADDCODE + Address match code (Slave mode) + 17 + 7 + read-only + + + DIR + Transfer direction (Slave mode) + 16 + 1 + read-only + + + BUSY + Bus busy + 15 + 1 + read-only + + + ALERT + SMBus alert + 13 + 1 + read-only + + + TIMEOUT + Timeout or t_low detection flag + 12 + 1 + read-only + + + PECERR + PEC Error in reception + 11 + 1 + read-only + + + OVR + Overrun/Underrun (slave mode) + 10 + 1 + read-only + + + ARLO + Arbitration lost + 9 + 1 + read-only + + + BERR + Bus error + 8 + 1 + read-only + + + TCR + Transfer Complete Reload + 7 + 1 + read-only + + + TC + Transfer Complete (master mode) + 6 + 1 + read-only + + + STOPF + Stop detection flag + 5 + 1 + read-only + + + NACKF + Not acknowledge received flag + 4 + 1 + read-only + + + ADDR + Address matched (slave mode) + 3 + 1 + read-only + + + RXNE + Receive data register not empty (receivers) + 2 + 1 + read-only + + + TXIS + Transmit interrupt status (transmitters) + 1 + 1 + read-write + + + TXE + Transmit data register empty (transmitters) + 0 + 1 + read-write + + + + + ICR + ICR + Interrupt clear register + 0x1C + 0x20 + write-only + 0x00000000 + + + ALERTCF + Alert flag clear + 13 + 1 + + + TIMOUTCF + Timeout detection flag clear + 12 + 1 + + + PECCF + PEC Error flag clear + 11 + 1 + + + OVRCF + Overrun/Underrun flag clear + 10 + 1 + + + ARLOCF + Arbitration lost flag clear + 9 + 1 + + + BERRCF + Bus error flag clear + 8 + 1 + + + STOPCF + Stop detection flag clear + 5 + 1 + + + NACKCF + Not Acknowledge flag clear + 4 + 1 + + + ADDRCF + Address Matched flag clear + 3 + 1 + + + + + PECR + PECR + PEC register + 0x20 + 0x20 + read-only + 0x00000000 + + + PEC + Packet error checking register + 0 + 8 + + + + + RXDR + RXDR + Receive data register + 0x24 + 0x20 + read-only + 0x00000000 + + + RXDATA + 8-bit receive data + 0 + 8 + + + + + TXDR + TXDR + Transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + + + TXDATA + 8-bit transmit data + 0 + 8 + + + + + + + I2C2 + 0x40005800 + + I2C2_EV + I2C2_EV + 33 + + + I2C2_ER + I2C2_ER + 34 + + + + I2C3 + 0x40007800 + + I2C3_EV + I2C3_EV + 92 + + + I2C3_ER + I2C3_ER + 93 + + + + IWDG + WinWATCHDOG + IWDG + 0x40003000 + + 0x0 + 0x400 + registers + + + + KR + KR + Key register + 0x0 + 0x20 + write-only + 0x00000000 + + + KEY + Key value (write only, read 0x0000) + 0 + 16 + + + + + PR + PR + Prescaler register + 0x4 + 0x20 + read-write + 0x00000000 + + + PR + Prescaler divider + 0 + 3 + + + + + RLR + RLR + Reload register + 0x8 + 0x20 + read-write + 0x00000FFF + + + RL + Watchdog counter reload value + 0 + 12 + + + + + SR + SR + Status register + 0xC + 0x20 + read-only + 0x00000000 + + + WVU + Watchdog counter window value update + 2 + 1 + + + RVU + Watchdog counter reload value update + 1 + 1 + + + PVU + Watchdog prescaler value update + 0 + 1 + + + + + WINR + WINR + Window register + 0x10 + 0x20 + read-write + 0x00000FFF + + + WIN + Watchdog counter window value + 0 + 12 + + + + + + + LPTIM1 + Low power timer + LPTIM + 0x40007C00 + + 0x0 + 0x400 + registers + + + LPTIM1 + LPTIM1 + 49 + + + + ISR + ISR + Interrupt and Status Register + 0x0 + 0x20 + read-only + 0x00000000 + + + DOWN + Counter direction change up to down + 6 + 1 + + + UP + Counter direction change down to up + 5 + 1 + + + ARROK + Autoreload register update OK + 4 + 1 + + + CMPOK + Compare register update OK + 3 + 1 + + + EXTTRIG + External trigger edge event + 2 + 1 + + + ARRM + Autoreload match + 1 + 1 + + + CMPM + Compare match + 0 + 1 + + + + + ICR + ICR + Interrupt Clear Register + 0x4 + 0x20 + write-only + 0x00000000 + + + DOWNCF + Direction change to down Clear Flag + 6 + 1 + + + UPCF + Direction change to UP Clear Flag + 5 + 1 + + + ARROKCF + Autoreload register update OK Clear Flag + 4 + 1 + + + CMPOKCF + Compare register update OK Clear Flag + 3 + 1 + + + EXTTRIGCF + External trigger valid edge Clear Flag + 2 + 1 + + + ARRMCF + Autoreload match Clear Flag + 1 + 1 + + + CMPMCF + compare match Clear Flag + 0 + 1 + + + + + IER + IER + Interrupt Enable Register + 0x8 + 0x20 + read-write + 0x00000000 + + + DOWNIE + Direction change to down Interrupt Enable + 6 + 1 + + + UPIE + Direction change to UP Interrupt Enable + 5 + 1 + + + ARROKIE + Autoreload register update OK Interrupt Enable + 4 + 1 + + + CMPOKIE + Compare register update OK Interrupt Enable + 3 + 1 + + + EXTTRIGIE + External trigger valid edge Interrupt Enable + 2 + 1 + + + ARRMIE + Autoreload match Interrupt Enable + 1 + 1 + + + CMPMIE + Compare match Interrupt Enable + 0 + 1 + + + + + CFGR + CFGR + Configuration Register + 0xC + 0x20 + read-write + 0x00000000 + + + ENC + Encoder mode enable + 24 + 1 + + + COUNTMODE + counter mode enabled + 23 + 1 + + + PRELOAD + Registers update mode + 22 + 1 + + + WAVPOL + Waveform shape polarity + 21 + 1 + + + WAVE + Waveform shape + 20 + 1 + + + TIMOUT + Timeout enable + 19 + 1 + + + TRIGEN + Trigger enable and polarity + 17 + 2 + + + TRIGSEL + Trigger selector + 13 + 4 + + + PRESC + Clock prescaler + 9 + 3 + + + TRGFLT + Configurable digital filter for trigger + 6 + 2 + + + CKFLT + Configurable digital filter for external clock + 3 + 2 + + + CKPOL + Clock Polarity + 1 + 2 + + + CKSEL + Clock selector + 0 + 1 + + + + + CR + CR + Control Register + 0x10 + 0x20 + read-write + 0x00000000 + + + RSTARE + RSTARE + 4 + 1 + + + COUNTRST + COUNTRST + 3 + 1 + + + CNTSTRT + Timer start in continuous mode + 2 + 1 + + + SNGSTRT + LPTIM start in single mode + 1 + 1 + + + ENABLE + LPTIM Enable + 0 + 1 + + + + + CMP + CMP + Compare Register + 0x14 + 0x20 + read-write + 0x00000000 + + + CMP + Compare value + 0 + 16 + + + + + ARR + ARR + Autoreload Register + 0x18 + 0x20 + read-write + 0x00000001 + + + ARR + Auto reload value + 0 + 16 + + + + + CNT + CNT + Counter Register + 0x1C + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 16 + + + + + OR + OR + option register + 0x20 + 0x20 + read-write + 0x00000000 + + + IN1 + IN1 + 0 + 1 + + + IN2 + IN2 + 1 + 1 + + + IN1_2_1 + IN1_2_1 + 2 + 2 + + + IN2_2_1 + IN2_2_1 + 4 + 2 + + + + + + + LPUART1 + Universal synchronous asynchronous receiver transmitter + USART + 0x40008000 + + 0x0 + 0x400 + registers + + + LPUART + LPUART + 91 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + RXFFIE + RXFFIE + 31 + 1 + + + TXFEIE + TXFEIE + 30 + 1 + + + FIFOEN + FIFOEN + 29 + 1 + + + M1 + Word length + 28 + 1 + + + DEAT4 + Driver Enable assertion time + 25 + 1 + + + DEAT3 + DEAT3 + 24 + 1 + + + DEAT2 + DEAT2 + 23 + 1 + + + DEAT1 + DEAT1 + 22 + 1 + + + DEAT0 + DEAT0 + 21 + 1 + + + DEDT4 + Driver Enable de-assertion time + 20 + 1 + + + DEDT3 + DEDT3 + 19 + 1 + + + DEDT2 + DEDT2 + 18 + 1 + + + DEDT1 + DEDT1 + 17 + 1 + + + DEDT0 + DEDT0 + 16 + 1 + + + CMIE + Character match interrupt enable + 14 + 1 + + + MME + Mute mode enable + 13 + 1 + + + M0 + Word length + 12 + 1 + + + WAKE + Receiver wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXEIE + interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt enable + 6 + 1 + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + UESM + USART enable in Stop mode + 1 + 1 + + + UE + USART enable + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + ADD4_7 + Address of the USART node + 28 + 4 + + + ADD0_3 + Address of the USART node + 24 + 4 + + + MSBFIRST + Most significant bit first + 19 + 1 + + + TAINV + Binary data inversion + 18 + 1 + + + TXINV + TX pin active level inversion + 17 + 1 + + + RXINV + RX pin active level inversion + 16 + 1 + + + SWAP + Swap TX/RX pins + 15 + 1 + + + STOP + STOP bits + 12 + 2 + + + ADDM7 + 7-bit Address Detection/4-bit Address Detection + 4 + 1 + + + + + CR3 + CR3 + Control register 3 + 0x8 + 0x20 + read-write + 0x0000 + + + TXFTCFG + TXFTCFG + 29 + 3 + + + RXFTIE + RXFTIE + 28 + 1 + + + RXFTCFG + RXFTCFG + 25 + 3 + + + TXFTIE + TXFTIE + 23 + 1 + + + WUFIE + Wakeup from Stop mode interrupt enable + 22 + 1 + + + WUS + Wakeup from Stop mode interrupt flag selection + 20 + 2 + + + DEP + Driver enable polarity selection + 15 + 1 + + + DEM + Driver enable mode + 14 + 1 + + + DDRE + DMA Disable on Reception Error + 13 + 1 + + + OVRDIS + Overrun Disable + 12 + 1 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSE + CTS enable + 9 + 1 + + + RTSE + RTS enable + 8 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + DMAR + DMA enable receiver + 6 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + + + BRR + BRR + Baud rate register + 0xC + 0x20 + read-write + 0x0000 + + + BRR + BRR + 0 + 20 + + + + + RQR + RQR + Request register + 0x18 + 0x20 + write-only + 0x0000 + + + TXFRQ + TXFRQ + 4 + 1 + + + RXFRQ + Receive data flush request + 3 + 1 + + + MMRQ + Mute mode request + 2 + 1 + + + SBKRQ + Send break request + 1 + 1 + + + + + ISR + ISR + Interrupt & status register + 0x1C + 0x20 + read-only + 0x00C0 + + + TXFT + TXFT + 27 + 1 + + + RXFT + RXFT + 26 + 1 + + + RXFF + RXFF + 24 + 1 + + + TXFE + TXFE + 23 + 1 + + + REACK + REACK + 22 + 1 + + + TEACK + TEACK + 21 + 1 + + + WUF + WUF + 20 + 1 + + + RWU + RWU + 19 + 1 + + + SBKF + SBKF + 18 + 1 + + + CMF + CMF + 17 + 1 + + + BUSY + BUSY + 16 + 1 + + + CTS + CTS + 10 + 1 + + + CTSIF + CTSIF + 9 + 1 + + + TXE + TXE + 7 + 1 + + + TC + TC + 6 + 1 + + + RXNE + RXNE + 5 + 1 + + + IDLE + IDLE + 4 + 1 + + + ORE + ORE + 3 + 1 + + + NF + NF + 2 + 1 + + + FE + FE + 1 + 1 + + + PE + PE + 0 + 1 + + + + + ICR + ICR + Interrupt flag clear register + 0x20 + 0x20 + write-only + 0x0000 + + + WUCF + Wakeup from Stop mode clear flag + 20 + 1 + + + CMCF + Character match clear flag + 17 + 1 + + + CTSCF + CTS clear flag + 9 + 1 + + + TCCF + Transmission complete clear flag + 6 + 1 + + + IDLECF + Idle line detected clear flag + 4 + 1 + + + ORECF + Overrun error clear flag + 3 + 1 + + + NCF + Noise detected clear flag + 2 + 1 + + + FECF + Framing error clear flag + 1 + 1 + + + PECF + Parity error clear flag + 0 + 1 + + + + + RDR + RDR + Receive data register + 0x24 + 0x20 + read-only + 0x0000 + + + RDR + Receive data value + 0 + 9 + + + + + TDR + TDR + Transmit data register + 0x28 + 0x20 + read-write + 0x0000 + + + TDR + Transmit data value + 0 + 9 + + + + + PRESC + PRESC + Prescaler register + 0x2C + 0x20 + read-write + 0x0000 + + + PRESCALER + PRESCALER + 0 + 4 + + + + + + + OPAMP + Operational amplifiers + OPAMP + 0x40010300 + + 0x0 + 0x100 + registers + + + + OPAMP1_CSR + OPAMP1_CSR + OPAMP1 control/status register + 0x0 + 0x20 + read-write + 0x00000000 + + + OPAEN + Operational amplifier Enable + 0 + 1 + + + FORCE_VP + FORCE_VP + 1 + 1 + + + VP_SEL + VP_SEL + 2 + 2 + + + USERTRIM + USERTRIM + 4 + 1 + + + VM_SEL + VM_SEL + 5 + 2 + + + OPAHSM + OPAHSM + 7 + 1 + + + OPAINTOEN + OPAINTOEN + 8 + 1 + + + CALON + CALON + 11 + 1 + + + CALSEL + CALSEL + 12 + 2 + + + PGA_GAIN + PGA_GAIN + 14 + 5 + + + TRIMOFFSETP + TRIMOFFSETP + 19 + 5 + + + TRIMOFFSETN + TRIMOFFSETN + 24 + 5 + + + CALOUT + CALOUT + 30 + 1 + + + LOCK + LOCK + 31 + 1 + + + + + OPAMP2_CSR + OPAMP2_CSR + OPAMP2 control/status register + 0x4 + 0x20 + read-write + 0x00000000 + + + OPAEN + Operational amplifier Enable + 0 + 1 + + + FORCE_VP + FORCE_VP + 1 + 1 + + + VP_SEL + VP_SEL + 2 + 2 + + + USERTRIM + USERTRIM + 4 + 1 + + + VM_SEL + VM_SEL + 5 + 2 + + + OPAHSM + OPAHSM + 7 + 1 + + + OPAINTOEN + OPAINTOEN + 8 + 1 + + + CALON + CALON + 11 + 1 + + + CALSEL + CALSEL + 12 + 2 + + + PGA_GAIN + PGA_GAIN + 14 + 5 + + + TRIMOFFSETP + TRIMOFFSETP + 19 + 5 + + + TRIMOFFSETN + TRIMOFFSETN + 24 + 5 + + + CALOUT + CALOUT + 30 + 1 + + + LOCK + LOCK + 31 + 1 + + + + + OPAMP3_CSR + OPAMP3_CSR + OPAMP3 control/status register + 0x8 + 0x20 + read-write + 0x00000000 + + + OPAEN + Operational amplifier Enable + 0 + 1 + + + FORCE_VP + FORCE_VP + 1 + 1 + + + VP_SEL + VP_SEL + 2 + 2 + + + USERTRIM + USERTRIM + 4 + 1 + + + VM_SEL + VM_SEL + 5 + 2 + + + OPAHSM + OPAHSM + 7 + 1 + + + OPAINTOEN + OPAINTOEN + 8 + 1 + + + CALON + CALON + 11 + 1 + + + CALSEL + CALSEL + 12 + 2 + + + PGA_GAIN + PGA_GAIN + 14 + 5 + + + TRIMOFFSETP + TRIMOFFSETP + 19 + 5 + + + TRIMOFFSETN + TRIMOFFSETN + 24 + 5 + + + CALOUT + CALOUT + 30 + 1 + + + LOCK + LOCK + 31 + 1 + + + + + OPAMP4_CSR + OPAMP4_CSR + OPAMP4 control/status register + 0xC + 0x20 + read-write + 0x00000000 + + + OPAEN + Operational amplifier Enable + 0 + 1 + + + FORCE_VP + FORCE_VP + 1 + 1 + + + VP_SEL + VP_SEL + 2 + 2 + + + USERTRIM + USERTRIM + 4 + 1 + + + VM_SEL + VM_SEL + 5 + 2 + + + OPAHSM + OPAHSM + 7 + 1 + + + OPAINTOEN + OPAINTOEN + 8 + 1 + + + CALON + CALON + 11 + 1 + + + CALSEL + CALSEL + 12 + 2 + + + PGA_GAIN + PGA_GAIN + 14 + 5 + + + TRIMOFFSETP + TRIMOFFSETP + 19 + 5 + + + TRIMOFFSETN + TRIMOFFSETN + 24 + 5 + + + CALOUT + CALOUT + 30 + 1 + + + LOCK + LOCK + 31 + 1 + + + + + OPAMP5_CSR + OPAMP5_CSR + OPAMP5 control/status register + 0x10 + 0x20 + read-write + 0x00000000 + + + OPAEN + Operational amplifier Enable + 0 + 1 + + + FORCE_VP + FORCE_VP + 1 + 1 + + + VP_SEL + VP_SEL + 2 + 2 + + + USERTRIM + USERTRIM + 4 + 1 + + + VM_SEL + VM_SEL + 5 + 2 + + + OPAHSM + OPAHSM + 7 + 1 + + + OPAINTOEN + OPAINTOEN + 8 + 1 + + + CALON + CALON + 11 + 1 + + + CALSEL + CALSEL + 12 + 2 + + + PGA_GAIN + PGA_GAIN + 14 + 5 + + + TRIMOFFSETP + TRIMOFFSETP + 19 + 5 + + + TRIMOFFSETN + TRIMOFFSETN + 24 + 5 + + + CALOUT + CALOUT + 30 + 1 + + + LOCK + LOCK + 31 + 1 + + + + + OPAMP6_CSR + OPAMP6_CSR + OPAMP6 control/status register + 0x14 + 0x20 + read-write + 0x00000000 + + + OPAEN + Operational amplifier Enable + 0 + 1 + + + FORCE_VP + FORCE_VP + 1 + 1 + + + VP_SEL + VP_SEL + 2 + 2 + + + USERTRIM + USERTRIM + 4 + 1 + + + VM_SEL + VM_SEL + 5 + 2 + + + OPAHSM + OPAHSM + 7 + 1 + + + OPAINTOEN + OPAINTOEN + 8 + 1 + + + CALON + CALON + 11 + 1 + + + CALSEL + CALSEL + 12 + 2 + + + PGA_GAIN + PGA_GAIN + 14 + 5 + + + TRIMOFFSETP + TRIMOFFSETP + 19 + 5 + + + TRIMOFFSETN + TRIMOFFSETN + 24 + 5 + + + CALOUT + CALOUT + 30 + 1 + + + LOCK + LOCK + 31 + 1 + + + + + OPAMP1_TCMR + OPAMP1_TCMR + OPAMP1 control/status register + 0x18 + 0x20 + read-write + 0x00000000 + + + VMS_SEL + VMS_SEL + 0 + 1 + + + VPS_SEL + VPS_SEL + 1 + 2 + + + T1CM_EN + T1CM_EN + 3 + 1 + + + T8CM_EN + T8CM_EN + 4 + 1 + + + T20CM_EN + T20CM_EN + 5 + 1 + + + LOCK + LOCK + 31 + 1 + + + + + OPAMP2_TCMR + OPAMP2_TCMR + OPAMP2 control/status register + 0x1C + 0x20 + read-write + 0x00000000 + + + VMS_SEL + VMS_SEL + 0 + 1 + + + VPS_SEL + VPS_SEL + 1 + 2 + + + T1CM_EN + T1CM_EN + 3 + 1 + + + T8CM_EN + T8CM_EN + 4 + 1 + + + T20CM_EN + T20CM_EN + 5 + 1 + + + LOCK + LOCK + 31 + 1 + + + + + OPAMP3_TCMR + OPAMP3_TCMR + OPAMP3 control/status register + 0x20 + 0x20 + read-write + 0x00000000 + + + VMS_SEL + VMS_SEL + 0 + 1 + + + VPS_SEL + VPS_SEL + 1 + 2 + + + T1CM_EN + T1CM_EN + 3 + 1 + + + T8CM_EN + T8CM_EN + 4 + 1 + + + T20CM_EN + T20CM_EN + 5 + 1 + + + LOCK + LOCK + 31 + 1 + + + + + OPAMP4_TCMR + OPAMP4_TCMR + OPAMP4 control/status register + 0x24 + 0x20 + read-write + 0x00000000 + + + VMS_SEL + VMS_SEL + 0 + 1 + + + VPS_SEL + VPS_SEL + 1 + 2 + + + T1CM_EN + T1CM_EN + 3 + 1 + + + T8CM_EN + T8CM_EN + 4 + 1 + + + T20CM_EN + T20CM_EN + 5 + 1 + + + LOCK + LOCK + 31 + 1 + + + + + OPAMP5_TCMR + OPAMP5_TCMR + OPAMP5 control/status register + 0x28 + 0x20 + read-write + 0x00000000 + + + VMS_SEL + VMS_SEL + 0 + 1 + + + VPS_SEL + VPS_SEL + 1 + 2 + + + T1CM_EN + T1CM_EN + 3 + 1 + + + T8CM_EN + T8CM_EN + 4 + 1 + + + T20CM_EN + T20CM_EN + 5 + 1 + + + LOCK + LOCK + 31 + 1 + + + + + OPAMP6_TCMR + OPAMP6_TCMR + OPAMP6 control/status register + 0x2C + 0x20 + read-write + 0x00000000 + + + VMS_SEL + VMS_SEL + 0 + 1 + + + VPS_SEL + VPS_SEL + 1 + 2 + + + T1CM_EN + T1CM_EN + 3 + 1 + + + T8CM_EN + T8CM_EN + 4 + 1 + + + T20CM_EN + T20CM_EN + 5 + 1 + + + LOCK + LOCK + 31 + 1 + + + + + + + PWR + Power control + PWR + 0x40007000 + + 0x0 + 0x400 + registers + + + + PWR_CR1 + PWR_CR1 + Power control register 1 + 0x00 + 0x20 + 0x00000200 + 0xFFFFFFFF + + + LPMS + Low-power mode selection + + 0 + 3 + read-write + + + B_0x0 + Stop 0 mode + 0x0 + + + B_0x1 + Stop 1 mode + 0x1 + + + B_0x3 + Standby mode + 0x3 + + + + + FPD_STOP + FPD_STOP + 3 + 1 + read-write + + + DBP + Disable backup domain write protection + + 8 + 1 + read-write + + + B_0x0 + Access to RTC and Backup registers disabled + 0x0 + + + B_0x1 + Access to RTC and Backup registers enabled + 0x1 + + + + + VOS + Voltage scaling range selection + 9 + 2 + read-write + + + B_0x0 + Cannot be written (forbidden by hardware) + 0x0 + + + B_0x1 + Range 1 + 0x1 + + + B_0x2 + Range 2 + 0x2 + + + B_0x3 + Cannot be written (forbidden by hardware) + 0x3 + + + + + LPR + Low-power run + + 14 + 1 + read-write + + + + + PWR_CR2 + PWR_CR2 + Power control register 2 + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PVDE + Programmable voltage detector enable + + 0 + 1 + read-write + + + B_0x0 + Programmable voltage detector disable. + 0x0 + + + B_0x1 + Programmable voltage detector enable. + 0x1 + + + + + PVDLS + Programmable voltage detector level selection. + + 1 + 3 + read-write + + + B_0x0 + V<sub>PVD0</sub> PVD threshold 0 + 0x0 + + + B_0x1 + V<sub>PVD1</sub> PVD threshold 1 + 0x1 + + + B_0x2 + V<sub>PVD2</sub> PVD threshold 2 + 0x2 + + + B_0x3 + V<sub>PVD3</sub> PVD threshold 3 + 0x3 + + + B_0x4 + V<sub>PVD4</sub> PVD threshold 4 + 0x4 + + + B_0x5 + V<sub>PVD5</sub> PVD threshold 5 + 0x5 + + + B_0x6 + V<sub>PVD6</sub> PVD threshold 6 + 0x6 + + + B_0x7 + External input analog voltage PVD_IN (compared internally to V<sub>REFINT</sub>) + 0x7 + + + + + PVMEN1 + Peripheral voltage monitoring 3 enable: V<sub>DDA</sub> vs. ADC/COMP min voltage 1.62V + 6 + 1 + read-write + + + B_0x0 + PVM1 (V<sub>DDA</sub> monitoring vs. 1.62V threshold) disable. + 0x0 + + + B_0x1 + PVM1 (V<sub>DDA</sub> monitoring vs. 1.62V threshold) enable. + 0x1 + + + + + PVMEN2 + Peripheral voltage monitoring 4 enable: V<sub>DDA</sub> vs. DAC 1MSPS /DAC 15MSPS min voltage. + 7 + 1 + read-write + + + B_0x0 + PVM2 (V<sub>DDA</sub> monitoring vs. 1.8 V threshold) disable. + 0x0 + + + B_0x1 + PVM2 (V<sub>DDA</sub> monitoring vs. 1.8 V threshold) enable. + 0x1 + + + + + + + PWR_CR3 + PWR_CR3 + Power control register 3 + 0x08 + 0x20 + 0x00008000 + 0xFFFFFFFF + + + EWUP1 + Enable Wakeup pin WKUP1 + + 0 + 1 + read-write + + + EWUP2 + Enable Wakeup pin WKUP2 + + 1 + 1 + read-write + + + EWUP3 + Enable Wakeup pin WKUP3 + + 2 + 1 + read-write + + + EWUP4 + Enable Wakeup pin WKUP4 + + 3 + 1 + read-write + + + EWUP5 + Enable Wakeup pin WKUP5 + + 4 + 1 + read-write + + + RRS + SRAM2 retention in Standby mode + 8 + 1 + read-write + + + B_0x0 + SRAM2 is powered off in Standby mode (SRAM2 content is lost). + 0x0 + + + B_0x1 + SRAM2 is powered by the low-power regulator in Standby mode (SRAM2 content is kept). + 0x1 + + + + + APC + Apply pull-up and pull-down configuration + + 10 + 1 + read-write + + + UCPD1_STDBY + UCPD1_STDBY USB Type-C and Power Delivery standby mode. + 13 + 1 + read-write + + + B_0x0 + Write 0 immediately after standby exit when using UCPD1, (and before writing any UCPD1 registers). + 0x0 + + + B_0x1 + Write 1 just before entering standby when using UCPD1. + 0x1 + + + + + UCPD1_DBDIS + USB Type-C and Power Delivery Dead Battery disable. + + 14 + 1 + read-write + + + B_0x0 + Enable USB Type-C dead battery pull-down behavior on UCPD1_CC1 and UCPD1_CC2 pins. + 0x0 + + + B_0x1 + Disable USB Type-C dead battery pull-down behavior on UCPD1_CC1 and UCPD1_CC2 pins. + 0x1 + + + + + EIWUL + Enable internal wakeup line + 15 + 1 + read-write + + + B_0x0 + Internal wakeup line disable. + 0x0 + + + B_0x1 + Internal wakeup line enable. + 0x1 + + + + + + + PWR_CR4 + PWR_CR4 + Power control register 4 + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WP1 + Wakeup pin WKUP1 polarity + + 0 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WP2 + Wakeup pin WKUP2 polarity + + 1 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WP3 + Wakeup pin WKUP3 polarity + + 2 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WP4 + Wakeup pin WKUP4 polarity + + 3 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WP5 + Wakeup pin WKUP5 polarity + + 4 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + VBE + V<sub>BAT</sub> battery charging enable + 8 + 1 + read-write + + + B_0x0 + V<sub>BAT</sub> battery charging disable + 0x0 + + + B_0x1 + V<sub>BAT</sub> battery charging enable + 0x1 + + + + + VBRS + V<sub>BAT</sub> battery charging resistor selection + 9 + 1 + read-write + + + B_0x0 + Charge V<sub>BAT</sub> through a 5 kOhms resistor + 0x0 + + + B_0x1 + Charge V<sub>BAT</sub> through a 1.5 kOhms resistor + 0x1 + + + + + + + PWR_SR1 + PWR_SR1 + Power status register 1 + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WUF1 + Wakeup flag 1 + + 0 + 1 + read-only + + + WUF2 + Wakeup flag 2 + + 1 + 1 + read-only + + + WUF3 + Wakeup flag 3 + + 2 + 1 + read-only + + + WUF4 + Wakeup flag 4 + + 3 + 1 + read-only + + + WUF5 + Wakeup flag 5 + + 4 + 1 + read-only + + + SBF + Standby flag + + 8 + 1 + read-only + + + B_0x0 + The device did not enter the Standby mode + 0x0 + + + B_0x1 + The device entered the Standby mode + 0x1 + + + + + WUFI + Wakeup flag internal + + 15 + 1 + read-only + + + + + PWR_SR2 + PWR_SR2 + Power status register 2 + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + REGLPS + Low-power regulator started + + 8 + 1 + read-only + + + B_0x0 + The low-power regulator is not ready + 0x0 + + + B_0x1 + The low-power regulator is ready + 0x1 + + + + + REGLPF + Low-power regulator flag + + 9 + 1 + read-only + + + B_0x0 + The regulator is ready in main mode (MR) + 0x0 + + + B_0x1 + The regulator is in low-power mode (LPR) + 0x1 + + + + + VOSF + Voltage scaling flag + + 10 + 1 + read-only + + + B_0x0 + The regulator is ready in the selected voltage range + 0x0 + + + B_0x1 + The regulator output voltage is changing to the required voltage level + 0x1 + + + + + PVDO + Programmable voltage detector output + 11 + 1 + read-only + + + B_0x0 + V<sub>DD</sub> is above the selected PVD threshold + 0x0 + + + B_0x1 + V<sub>DD</sub> is below the selected PVD threshold + 0x1 + + + + + PVMO1 + Peripheral voltage monitoring output: V<sub>DDA</sub> vs. 1.62 V + + 14 + 1 + read-only + + + B_0x0 + V<sub>DDA</sub> voltage is above PVM1 threshold (around 1.62 V). + 0x0 + + + B_0x1 + V<sub>DDA</sub> voltage is below PVM1 threshold (around 1.62 V). + 0x1 + + + + + PVMO2 + Peripheral voltage monitoring output: V<sub>DDA</sub> vs. 1.8 V + + 15 + 1 + read-only + + + B_0x0 + V<sub>DDA</sub> voltage is above PVM2 threshold (around 1.8 V). + 0x0 + + + B_0x1 + V<sub>DDA</sub> voltage is below PVM2 threshold (around 1.8 V). + 0x1 + + + + + + + PWR_SCR + PWR_SCR + Power status clear register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CWUF1 + Clear wakeup flag 1 + + 0 + 1 + write-only + + + CWUF2 + Clear wakeup flag 2 + + 1 + 1 + write-only + + + CWUF3 + Clear wakeup flag 3 + + 2 + 1 + write-only + + + CWUF4 + Clear wakeup flag 4 + + 3 + 1 + write-only + + + CWUF5 + Clear wakeup flag 5 + + 4 + 1 + write-only + + + CSBF + Clear standby flag + + 8 + 1 + write-only + + + + + PWR_PUCRA + PWR_PUCRA + Power Port A pull-up control register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PU0 + Port A pull-up bit y (y=0..13) + + 0 + 1 + read-write + + + PU1 + Port A pull-up bit y (y=0..13) + + 1 + 1 + read-write + + + PU2 + Port A pull-up bit y (y=0..13) + + 2 + 1 + read-write + + + PU3 + Port A pull-up bit y (y=0..13) + + 3 + 1 + read-write + + + PU4 + Port A pull-up bit y (y=0..13) + + 4 + 1 + read-write + + + PU5 + Port A pull-up bit y (y=0..13) + + 5 + 1 + read-write + + + PU6 + Port A pull-up bit y (y=0..13) + + 6 + 1 + read-write + + + PU7 + Port A pull-up bit y (y=0..13) + + 7 + 1 + read-write + + + PU8 + Port A pull-up bit y (y=0..13) + + 8 + 1 + read-write + + + PU9 + Port A pull-up bit y (y=0..13) + + 9 + 1 + read-write + + + PU10 + Port A pull-up bit y (y=0..13) + + 10 + 1 + read-write + + + PU11 + Port A pull-up bit y (y=0..13) + + 11 + 1 + read-write + + + PU12 + Port A pull-up bit y (y=0..13) + + 12 + 1 + read-write + + + PU13 + Port A pull-up bit y (y=0..13) + + 13 + 1 + read-write + + + PU15 + Port A pull-up bit 15 + + 15 + 1 + read-write + + + + + PWR_PDCRA + PWR_PDCRA + Power Port A pull-down control register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PD0 + Port A pull-down bit y (y=0..12) + + 0 + 1 + read-write + + + PD1 + Port A pull-down bit y (y=0..12) + + 1 + 1 + read-write + + + PD2 + Port A pull-down bit y (y=0..12) + + 2 + 1 + read-write + + + PD3 + Port A pull-down bit y (y=0..12) + + 3 + 1 + read-write + + + PD4 + Port A pull-down bit y (y=0..12) + + 4 + 1 + read-write + + + PD5 + Port A pull-down bit y (y=0..12) + + 5 + 1 + read-write + + + PD6 + Port A pull-down bit y (y=0..12) + + 6 + 1 + read-write + + + PD7 + Port A pull-down bit y (y=0..12) + + 7 + 1 + read-write + + + PD8 + Port A pull-down bit y (y=0..12) + + 8 + 1 + read-write + + + PD9 + Port A pull-down bit y (y=0..12) + + 9 + 1 + read-write + + + PD10 + Port A pull-down bit y (y=0..12) + + 10 + 1 + read-write + + + PD11 + Port A pull-down bit y (y=0..12) + + 11 + 1 + read-write + + + PD12 + Port A pull-down bit y (y=0..12) + + 12 + 1 + read-write + + + PD14 + Port A pull-down bit 14 + + 14 + 1 + read-write + + + + + PWR_PUCRB + PWR_PUCRB + Power Port B pull-up control register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PU0 + Port B pull-up bit y (y=0..15) + + 0 + 1 + read-write + + + PU1 + Port B pull-up bit y (y=0..15) + + 1 + 1 + read-write + + + PU2 + Port B pull-up bit y (y=0..15) + + 2 + 1 + read-write + + + PU3 + Port B pull-up bit y (y=0..15) + + 3 + 1 + read-write + + + PU4 + Port B pull-up bit y (y=0..15) + + 4 + 1 + read-write + + + PU5 + Port B pull-up bit y (y=0..15) + + 5 + 1 + read-write + + + PU6 + Port B pull-up bit y (y=0..15) + + 6 + 1 + read-write + + + PU7 + Port B pull-up bit y (y=0..15) + + 7 + 1 + read-write + + + PU8 + Port B pull-up bit y (y=0..15) + + 8 + 1 + read-write + + + PU9 + Port B pull-up bit y (y=0..15) + + 9 + 1 + read-write + + + PU10 + Port B pull-up bit y (y=0..15) + + 10 + 1 + read-write + + + PU11 + Port B pull-up bit y (y=0..15) + + 11 + 1 + read-write + + + PU12 + Port B pull-up bit y (y=0..15) + + 12 + 1 + read-write + + + PU13 + Port B pull-up bit y (y=0..15) + + 13 + 1 + read-write + + + PU14 + Port B pull-up bit y (y=0..15) + + 14 + 1 + read-write + + + PU15 + Port B pull-up bit y (y=0..15) + + 15 + 1 + read-write + + + + + PWR_PDCRB + PWR_PDCRB + Power Port B pull-down control register + 0x2C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PD0 + Port B pull-down bit y (y=0..3) + + 0 + 1 + read-write + + + PD1 + Port B pull-down bit y (y=0..3) + + 1 + 1 + read-write + + + PD2 + Port B pull-down bit y (y=0..3) + + 2 + 1 + read-write + + + PD3 + Port B pull-down bit y (y=0..3) + + 3 + 1 + read-write + + + PD5 + Port B pull-down bit y (y=5..15) + + 5 + 1 + read-write + + + PD6 + Port B pull-down bit y (y=5..15) + + 6 + 1 + read-write + + + PD7 + Port B pull-down bit y (y=5..15) + + 7 + 1 + read-write + + + PD8 + Port B pull-down bit y (y=5..15) + + 8 + 1 + read-write + + + PD9 + Port B pull-down bit y (y=5..15) + + 9 + 1 + read-write + + + PD10 + Port B pull-down bit y (y=5..15) + + 10 + 1 + read-write + + + PD11 + Port B pull-down bit y (y=5..15) + + 11 + 1 + read-write + + + PD12 + Port B pull-down bit y (y=5..15) + + 12 + 1 + read-write + + + PD13 + Port B pull-down bit y (y=5..15) + + 13 + 1 + read-write + + + PD14 + Port B pull-down bit y (y=5..15) + + 14 + 1 + read-write + + + PD15 + Port B pull-down bit y (y=5..15) + + 15 + 1 + read-write + + + + + PWR_PUCRC + PWR_PUCRC + Power Port C pull-up control register + 0x30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PU0 + Port C pull-up bit y (y=0..15) + + 0 + 1 + read-write + + + PU1 + Port C pull-up bit y (y=0..15) + + 1 + 1 + read-write + + + PU2 + Port C pull-up bit y (y=0..15) + + 2 + 1 + read-write + + + PU3 + Port C pull-up bit y (y=0..15) + + 3 + 1 + read-write + + + PU4 + Port C pull-up bit y (y=0..15) + + 4 + 1 + read-write + + + PU5 + Port C pull-up bit y (y=0..15) + + 5 + 1 + read-write + + + PU6 + Port C pull-up bit y (y=0..15) + + 6 + 1 + read-write + + + PU7 + Port C pull-up bit y (y=0..15) + + 7 + 1 + read-write + + + PU8 + Port C pull-up bit y (y=0..15) + + 8 + 1 + read-write + + + PU9 + Port C pull-up bit y (y=0..15) + + 9 + 1 + read-write + + + PU10 + Port C pull-up bit y (y=0..15) + + 10 + 1 + read-write + + + PU11 + Port C pull-up bit y (y=0..15) + + 11 + 1 + read-write + + + PU12 + Port C pull-up bit y (y=0..15) + + 12 + 1 + read-write + + + PU13 + Port C pull-up bit y (y=0..15) + + 13 + 1 + read-write + + + PU14 + Port C pull-up bit y (y=0..15) + + 14 + 1 + read-write + + + PU15 + Port C pull-up bit y (y=0..15) + + 15 + 1 + read-write + + + + + PWR_PDCRC + PWR_PDCRC + Power Port C pull-down control register + 0x34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PD0 + Port C pull-down bit y (y=0..15) + + 0 + 1 + read-write + + + PD1 + Port C pull-down bit y (y=0..15) + + 1 + 1 + read-write + + + PD2 + Port C pull-down bit y (y=0..15) + + 2 + 1 + read-write + + + PD3 + Port C pull-down bit y (y=0..15) + + 3 + 1 + read-write + + + PD4 + Port C pull-down bit y (y=0..15) + + 4 + 1 + read-write + + + PD5 + Port C pull-down bit y (y=0..15) + + 5 + 1 + read-write + + + PD6 + Port C pull-down bit y (y=0..15) + + 6 + 1 + read-write + + + PD7 + Port C pull-down bit y (y=0..15) + + 7 + 1 + read-write + + + PD8 + Port C pull-down bit y (y=0..15) + + 8 + 1 + read-write + + + PD9 + Port C pull-down bit y (y=0..15) + + 9 + 1 + read-write + + + PD10 + Port C pull-down bit y (y=0..15) + + 10 + 1 + read-write + + + PD11 + Port C pull-down bit y (y=0..15) + + 11 + 1 + read-write + + + PD12 + Port C pull-down bit y (y=0..15) + + 12 + 1 + read-write + + + PD13 + Port C pull-down bit y (y=0..15) + + 13 + 1 + read-write + + + PD14 + Port C pull-down bit y (y=0..15) + + 14 + 1 + read-write + + + PD15 + Port C pull-down bit y (y=0..15) + + 15 + 1 + read-write + + + + + PWR_PUCRD + PWR_PUCRD + Power Port D pull-up control register + 0x38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PU0 + Port D pull-up bit y (y=0..15) + + 0 + 1 + read-write + + + PU1 + Port D pull-up bit y (y=0..15) + + 1 + 1 + read-write + + + PU2 + Port D pull-up bit y (y=0..15) + + 2 + 1 + read-write + + + PU3 + Port D pull-up bit y (y=0..15) + + 3 + 1 + read-write + + + PU4 + Port D pull-up bit y (y=0..15) + + 4 + 1 + read-write + + + PU5 + Port D pull-up bit y (y=0..15) + + 5 + 1 + read-write + + + PU6 + Port D pull-up bit y (y=0..15) + + 6 + 1 + read-write + + + PU7 + Port D pull-up bit y (y=0..15) + + 7 + 1 + read-write + + + PU8 + Port D pull-up bit y (y=0..15) + + 8 + 1 + read-write + + + PU9 + Port D pull-up bit y (y=0..15) + + 9 + 1 + read-write + + + PU10 + Port D pull-up bit y (y=0..15) + + 10 + 1 + read-write + + + PU11 + Port D pull-up bit y (y=0..15) + + 11 + 1 + read-write + + + PU12 + Port D pull-up bit y (y=0..15) + + 12 + 1 + read-write + + + PU13 + Port D pull-up bit y (y=0..15) + + 13 + 1 + read-write + + + PU14 + Port D pull-up bit y (y=0..15) + + 14 + 1 + read-write + + + PU15 + Port D pull-up bit y (y=0..15) + + 15 + 1 + read-write + + + + + PWR_PDCRD + PWR_PDCRD + Power Port D pull-down control register + 0x3C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PD0 + Port D pull-down bit y (y=0..15) + + 0 + 1 + read-write + + + PD1 + Port D pull-down bit y (y=0..15) + + 1 + 1 + read-write + + + PD2 + Port D pull-down bit y (y=0..15) + + 2 + 1 + read-write + + + PD3 + Port D pull-down bit y (y=0..15) + + 3 + 1 + read-write + + + PD4 + Port D pull-down bit y (y=0..15) + + 4 + 1 + read-write + + + PD5 + Port D pull-down bit y (y=0..15) + + 5 + 1 + read-write + + + PD6 + Port D pull-down bit y (y=0..15) + + 6 + 1 + read-write + + + PD7 + Port D pull-down bit y (y=0..15) + + 7 + 1 + read-write + + + PD8 + Port D pull-down bit y (y=0..15) + + 8 + 1 + read-write + + + PD9 + Port D pull-down bit y (y=0..15) + + 9 + 1 + read-write + + + PD10 + Port D pull-down bit y (y=0..15) + + 10 + 1 + read-write + + + PD11 + Port D pull-down bit y (y=0..15) + + 11 + 1 + read-write + + + PD12 + Port D pull-down bit y (y=0..15) + + 12 + 1 + read-write + + + PD13 + Port D pull-down bit y (y=0..15) + + 13 + 1 + read-write + + + PD14 + Port D pull-down bit y (y=0..15) + + 14 + 1 + read-write + + + PD15 + Port D pull-down bit y (y=0..15) + + 15 + 1 + read-write + + + + + PWR_PUCRE + PWR_PUCRE + Power Port E pull-up control register + 0x40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PU0 + Port E pull-up bit y (y=0..15) + + 0 + 1 + read-write + + + PU1 + Port E pull-up bit y (y=0..15) + + 1 + 1 + read-write + + + PU2 + Port E pull-up bit y (y=0..15) + + 2 + 1 + read-write + + + PU3 + Port E pull-up bit y (y=0..15) + + 3 + 1 + read-write + + + PU4 + Port E pull-up bit y (y=0..15) + + 4 + 1 + read-write + + + PU5 + Port E pull-up bit y (y=0..15) + + 5 + 1 + read-write + + + PU6 + Port E pull-up bit y (y=0..15) + + 6 + 1 + read-write + + + PU7 + Port E pull-up bit y (y=0..15) + + 7 + 1 + read-write + + + PU8 + Port E pull-up bit y (y=0..15) + + 8 + 1 + read-write + + + PU9 + Port E pull-up bit y (y=0..15) + + 9 + 1 + read-write + + + PU10 + Port E pull-up bit y (y=0..15) + + 10 + 1 + read-write + + + PU11 + Port E pull-up bit y (y=0..15) + + 11 + 1 + read-write + + + PU12 + Port E pull-up bit y (y=0..15) + + 12 + 1 + read-write + + + PU13 + Port E pull-up bit y (y=0..15) + + 13 + 1 + read-write + + + PU14 + Port E pull-up bit y (y=0..15) + + 14 + 1 + read-write + + + PU15 + Port E pull-up bit y (y=0..15) + + 15 + 1 + read-write + + + + + PWR_PDCRE + PWR_PDCRE + Power Port E pull-down control register + 0x44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PD0 + Port E pull-down bit y (y=0..15) + + 0 + 1 + read-write + + + PD1 + Port E pull-down bit y (y=0..15) + + 1 + 1 + read-write + + + PD2 + Port E pull-down bit y (y=0..15) + + 2 + 1 + read-write + + + PD3 + Port E pull-down bit y (y=0..15) + + 3 + 1 + read-write + + + PD4 + Port E pull-down bit y (y=0..15) + + 4 + 1 + read-write + + + PD5 + Port E pull-down bit y (y=0..15) + + 5 + 1 + read-write + + + PD6 + Port E pull-down bit y (y=0..15) + + 6 + 1 + read-write + + + PD7 + Port E pull-down bit y (y=0..15) + + 7 + 1 + read-write + + + PD8 + Port E pull-down bit y (y=0..15) + + 8 + 1 + read-write + + + PD9 + Port E pull-down bit y (y=0..15) + + 9 + 1 + read-write + + + PD10 + Port E pull-down bit y (y=0..15) + + 10 + 1 + read-write + + + PD11 + Port E pull-down bit y (y=0..15) + + 11 + 1 + read-write + + + PD12 + Port E pull-down bit y (y=0..15) + + 12 + 1 + read-write + + + PD13 + Port E pull-down bit y (y=0..15) + + 13 + 1 + read-write + + + PD14 + Port E pull-down bit y (y=0..15) + + 14 + 1 + read-write + + + PD15 + Port E pull-down bit y (y=0..15) + + 15 + 1 + read-write + + + + + PWR_PUCRF + PWR_PUCRF + Power Port F pull-up control register + 0x48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PU0 + Port F pull-up bit y (y=0..15) + + 0 + 1 + read-write + + + PU1 + Port F pull-up bit y (y=0..15) + + 1 + 1 + read-write + + + PU2 + Port F pull-up bit y (y=0..15) + + 2 + 1 + read-write + + + PU3 + Port F pull-up bit y (y=0..15) + + 3 + 1 + read-write + + + PU4 + Port F pull-up bit y (y=0..15) + + 4 + 1 + read-write + + + PU5 + Port F pull-up bit y (y=0..15) + + 5 + 1 + read-write + + + PU6 + Port F pull-up bit y (y=0..15) + + 6 + 1 + read-write + + + PU7 + Port F pull-up bit y (y=0..15) + + 7 + 1 + read-write + + + PU8 + Port F pull-up bit y (y=0..15) + + 8 + 1 + read-write + + + PU9 + Port F pull-up bit y (y=0..15) + + 9 + 1 + read-write + + + PU10 + Port F pull-up bit y (y=0..15) + + 10 + 1 + read-write + + + PU11 + Port F pull-up bit y (y=0..15) + + 11 + 1 + read-write + + + PU12 + Port F pull-up bit y (y=0..15) + + 12 + 1 + read-write + + + PU13 + Port F pull-up bit y (y=0..15) + + 13 + 1 + read-write + + + PU14 + Port F pull-up bit y (y=0..15) + + 14 + 1 + read-write + + + PU15 + Port F pull-up bit y (y=0..15) + + 15 + 1 + read-write + + + + + PWR_PDCRF + PWR_PDCRF + Power Port F pull-down control register + 0x4C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PD0 + Port F pull-down bit y (y=0..15) + + 0 + 1 + read-write + + + PD1 + Port F pull-down bit y (y=0..15) + + 1 + 1 + read-write + + + PD2 + Port F pull-down bit y (y=0..15) + + 2 + 1 + read-write + + + PD3 + Port F pull-down bit y (y=0..15) + + 3 + 1 + read-write + + + PD4 + Port F pull-down bit y (y=0..15) + + 4 + 1 + read-write + + + PD5 + Port F pull-down bit y (y=0..15) + + 5 + 1 + read-write + + + PD6 + Port F pull-down bit y (y=0..15) + + 6 + 1 + read-write + + + PD7 + Port F pull-down bit y (y=0..15) + + 7 + 1 + read-write + + + PD8 + Port F pull-down bit y (y=0..15) + + 8 + 1 + read-write + + + PD9 + Port F pull-down bit y (y=0..15) + + 9 + 1 + read-write + + + PD10 + Port F pull-down bit y (y=0..15) + + 10 + 1 + read-write + + + PD11 + Port F pull-down bit y (y=0..15) + + 11 + 1 + read-write + + + PD12 + Port F pull-down bit y (y=0..15) + + 12 + 1 + read-write + + + PD13 + Port F pull-down bit y (y=0..15) + + 13 + 1 + read-write + + + PD14 + Port F pull-down bit y (y=0..15) + + 14 + 1 + read-write + + + PD15 + Port F pull-down bit y (y=0..15) + + 15 + 1 + read-write + + + + + PWR_PUCRG + PWR_PUCRG + Power Port G pull-up control register + 0x50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PU0 + Port G pull-up bit y (y=0..10) + + 0 + 1 + read-write + + + PU1 + Port G pull-up bit y (y=0..10) + + 1 + 1 + read-write + + + PU2 + Port G pull-up bit y (y=0..10) + + 2 + 1 + read-write + + + PU3 + Port G pull-up bit y (y=0..10) + + 3 + 1 + read-write + + + PU4 + Port G pull-up bit y (y=0..10) + + 4 + 1 + read-write + + + PU5 + Port G pull-up bit y (y=0..10) + + 5 + 1 + read-write + + + PU6 + Port G pull-up bit y (y=0..10) + + 6 + 1 + read-write + + + PU7 + Port G pull-up bit y (y=0..10) + + 7 + 1 + read-write + + + PU8 + Port G pull-up bit y (y=0..10) + + 8 + 1 + read-write + + + PU9 + Port G pull-up bit y (y=0..10) + + 9 + 1 + read-write + + + PU10 + Port G pull-up bit y (y=0..10) + + 10 + 1 + read-write + + + + + PWR_PDCRG + PWR_PDCRG + Power Port G pull-down control register + 0x54 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PD0 + Port G pull-down bit y (y=0..10) + + 0 + 1 + read-write + + + PD1 + Port G pull-down bit y (y=0..10) + + 1 + 1 + read-write + + + PD2 + Port G pull-down bit y (y=0..10) + + 2 + 1 + read-write + + + PD3 + Port G pull-down bit y (y=0..10) + + 3 + 1 + read-write + + + PD4 + Port G pull-down bit y (y=0..10) + + 4 + 1 + read-write + + + PD5 + Port G pull-down bit y (y=0..10) + + 5 + 1 + read-write + + + PD6 + Port G pull-down bit y (y=0..10) + + 6 + 1 + read-write + + + PD7 + Port G pull-down bit y (y=0..10) + + 7 + 1 + read-write + + + PD8 + Port G pull-down bit y (y=0..10) + + 8 + 1 + read-write + + + PD9 + Port G pull-down bit y (y=0..10) + + 9 + 1 + read-write + + + PD10 + Port G pull-down bit y (y=0..10) + + 10 + 1 + read-write + + + + + PWR_CR5 + PWR_CR5 + Power control register + 0x80 + 0x20 + 0x00000100 + 0xFFFFFFFF + + + R1MODE + Main regular range 1 mode + + 8 + 1 + read-write + + + B_0x0 + Main regulator in range 1 boost mode. + 0x0 + + + B_0x1 + Main regulator in range 1 normal mode. + 0x1 + + + + + + + + + RCC + Reset and clock control + RCC + 0x40021000 + + 0x0 + 0x400 + registers + + + RCC + RCC global interrupt + 5 + + + + RCC_CR + RCC_CR + Clock control register + 0x00 + 0x20 + 0x00000063 + 0xFFFFFFFF + + + HSION + HSI16 clock enable + + 8 + 1 + read-write + + + B_0x0 + HSI16 oscillator OFF + 0x0 + + + B_0x1 + HSI16 oscillator ON + 0x1 + + + + + HSIKERON + HSI16 always enable for peripheral kernels. + + 9 + 1 + read-write + + + B_0x0 + No effect on HSI16 oscillator. + 0x0 + + + B_0x1 + HSI16 oscillator is forced ON even in Stop mode. + 0x1 + + + + + HSIRDY + HSI16 clock ready flag + + 10 + 1 + read-only + + + B_0x0 + HSI16 oscillator not ready + 0x0 + + + B_0x1 + HSI16 oscillator ready + 0x1 + + + + + HSEON + HSE clock enable + + 16 + 1 + read-write + + + B_0x0 + HSE oscillator OFF + 0x0 + + + B_0x1 + HSE oscillator ON + 0x1 + + + + + HSERDY + HSE clock ready flag + + 17 + 1 + read-only + + + B_0x0 + HSE oscillator not ready + 0x0 + + + B_0x1 + HSE oscillator ready + 0x1 + + + + + HSEBYP + HSE crystal oscillator bypass + + 18 + 1 + read-write + + + B_0x0 + HSE crystal oscillator not bypassed + 0x0 + + + B_0x1 + HSE crystal oscillator bypassed with external clock + 0x1 + + + + + CSSON + Clock security system enable + + 19 + 1 + read-write + + + B_0x0 + Clock security system OFF (clock detector OFF) + 0x0 + + + B_0x1 + Clock security system ON (Clock detector ON if the HSE oscillator is stable, OFF if not). + 0x1 + + + + + PLLON + Main PLL enable + + 24 + 1 + read-write + + + B_0x0 + PLL OFF + 0x0 + + + B_0x1 + PLL ON + 0x1 + + + + + PLLRDY + Main PLL clock ready flag + + 25 + 1 + read-only + + + B_0x0 + PLL unlocked + 0x0 + + + B_0x1 + PLL locked + 0x1 + + + + + + + RCC_ICSCR + RCC_ICSCR + Internal clock sources calibration register + 0x04 + 0x20 + 0x40000000 + 0xFFFFFFFF + + + HSICAL + HSI16 clock calibration + + 16 + 8 + read-only + + + HSITRIM + HSI16 clock trimming + + 24 + 7 + read-write + + + + + RCC_CFGR + RCC_CFGR + Clock configuration register + 0x08 + 0x20 + 0x00000005 + 0xFFFFFFFF + + + SW + System clock switch + + 0 + 2 + read-write + + + B_0x0 + Reserved, must be kept at reset value + 0x0 + + + B_0x1 + HSI16 selected as system clock + 0x1 + + + B_0x2 + HSE selected as system clock + 0x2 + + + B_0x3 + PLL selected as system clock + 0x3 + + + + + SWS + System clock switch status + + 2 + 2 + read-only + + + B_0x0 + Reserved, must be kept at reset value + 0x0 + + + B_0x1 + HSI16 oscillator used as system clock + 0x1 + + + B_0x2 + HSE used as system clock + 0x2 + + + B_0x3 + PLL used as system clock + 0x3 + + + + + HPRE + AHB prescaler + + 4 + 4 + read-write + + + B_0x8 + SYSCLK divided by 2 + 0x8 + + + B_0x9 + SYSCLK divided by 4 + 0x9 + + + B_0xA + SYSCLK divided by 8 + 0xA + + + B_0xB + SYSCLK divided by 16 + 0xB + + + B_0xC + SYSCLK divided by 64 + 0xC + + + B_0xD + SYSCLK divided by 128 + 0xD + + + B_0xE + SYSCLK divided by 256 + 0xE + + + B_0xF + SYSCLK divided by 512 + 0xF + + + + + PPRE1 + APB1 prescaler + + 8 + 3 + read-write + + + B_0x4 + HCLK divided by 2 + 0x4 + + + B_0x5 + HCLK divided by 4 + 0x5 + + + B_0x6 + HCLK divided by 8 + 0x6 + + + B_0x7 + HCLK divided by 16 + 0x7 + + + + + PPRE2 + APB2 prescaler + + 11 + 3 + read-write + + + B_0x4 + HCLK divided by 2 + 0x4 + + + B_0x5 + HCLK divided by 4 + 0x5 + + + B_0x6 + HCLK divided by 8 + 0x6 + + + B_0x7 + HCLK divided by 16 + 0x7 + + + + + MCOSEL + Microcontroller clock output + + 24 + 4 + read-write + + + B_0x0 + MCO output disabled, no clock on MCO + 0x0 + + + B_0x1 + SYSCLK system clock selected + 0x1 + + + B_0x2 + Reserved, must be kept at reset value + 0x2 + + + B_0x3 + HSI16 clock selected + 0x3 + + + B_0x4 + HSE clock selected + 0x4 + + + B_0x5 + Main PLL clock selected + 0x5 + + + B_0x6 + LSI clock selected + 0x6 + + + B_0x7 + LSE clock selected + 0x7 + + + B_0x8 + Internal HSI48 clock selected + 0x8 + + + + + MCOPRE + Microcontroller clock output prescaler + + 28 + 3 + read-write + + + B_0x0 + MCO is divided by 1 + 0x0 + + + B_0x1 + MCO is divided by 2 + 0x1 + + + B_0x2 + MCO is divided by 4 + 0x2 + + + B_0x3 + MCO is divided by 8 + 0x3 + + + B_0x4 + MCO is divided by 16 + 0x4 + + + + + + + RCC_PLLCFGR + RCC_PLLCFGR + PLL configuration register + 0x0C + 0x20 + 0x00001000 + 0xFFFFFFFF + + + PLLSRC + Main PLL entry clock source + + 0 + 2 + read-write + + + B_0x0 + No clock sent to PLL + 0x0 + + + B_0x1 + No clock sent to PLL + 0x1 + + + B_0x2 + HSI16 clock selected as PLL clock entry + 0x2 + + + B_0x3 + HSE clock selected as PLL clock entry + 0x3 + + + + + PLLM + Division factor for the main PLL input clock + + 4 + 4 + read-write + + + B_0x0 + PLLM = 1 + 0x0 + + + B_0x1 + PLLM = 2 + 0x1 + + + B_0x2 + PLLM = 3 + 0x2 + + + B_0x3 + PLLM = 4 + 0x3 + + + B_0x4 + PLLM = 5 + 0x4 + + + B_0x5 + PLLM = 6 + 0x5 + + + B_0x6 + PLLM = 7 + 0x6 + + + B_0x7 + PLLM = 8 + 0x7 + + + B_0x8 + PLLSYSM = 9 + 0x8 + + + B_0xF + PLLSYSM= 16 + 0xF + + + + + PLLN + Main PLL multiplication factor for VCO + + 8 + 7 + read-write + + + B_0x0 + PLLN = 0 wrong configuration + 0x0 + + + B_0x1 + PLLN = 1 wrong configuration + 0x1 + + + B_0x7 + PLLN = 7 wrong configuration + 0x7 + + + B_0x8 + PLLN = 8 + 0x8 + + + B_0x9 + PLLN = 9 + 0x9 + + + B_0x7F + PLLN = 127 + 0x7F + + + + + PLLPEN + Main PLL PLL P clock output enable + + 16 + 1 + read-write + + + B_0x0 + PLL P clock output disable + 0x0 + + + B_0x1 + PLL P clock output enable + 0x1 + + + + + PLLP + Main PLL division factor for PLL P clock. + + 17 + 1 + read-write + + + B_0x0 + PLLP = 7 + 0x0 + + + B_0x1 + PLLP = 17 + 0x1 + + + + + PLLQEN + Main PLL Q clock output enable + + 20 + 1 + read-write + + + B_0x0 + PLL Q clock output disable + 0x0 + + + B_0x1 + PLL Q clock output enable + 0x1 + + + + + PLLQ + Main PLL division factor for PLL Q clock. + + 21 + 2 + read-write + + + B_0x0 + PLLQ = 2 + 0x0 + + + B_0x1 + PLLQ = 4 + 0x1 + + + B_0x2 + PLLQ = 6 + 0x2 + + + B_0x3 + PLLQ = 8 + 0x3 + + + + + PLLREN + PLL R clock output enable + + 24 + 1 + read-write + + + B_0x0 + PLL R clock output disable + 0x0 + + + B_0x1 + PLL R clock output enable + 0x1 + + + + + PLLR + Main PLL division factor for PLL R clock (system clock) + + 25 + 2 + read-write + + + B_0x0 + PLLR = 2 + 0x0 + + + B_0x1 + PLLR = 4 + 0x1 + + + B_0x2 + PLLR = 6 + 0x2 + + + B_0x3 + PLLR = 8 + 0x3 + + + + + PLLPDIV + Main PLLP division factor + + 27 + 5 + read-write + + + B_0x0 + PLL P clock is controlled by the bit PLLP + 0x0 + + + B_0x1 + Reserved. + 0x1 + + + B_0x2 + PLL P clock = VCO / 2 + 0x2 + + + B_0x1F + PLL P clock = VCO / 31 + 0x1F + + + + + + + RCC_CIER + RCC_CIER + Clock interrupt enable register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LSIRDYIE + LSI ready interrupt enable + + 0 + 1 + read-write + + + B_0x0 + LSI ready interrupt disabled + 0x0 + + + B_0x1 + LSI ready interrupt enabled + 0x1 + + + + + LSERDYIE + LSE ready interrupt enable + + 1 + 1 + read-write + + + B_0x0 + LSE ready interrupt disabled + 0x0 + + + B_0x1 + LSE ready interrupt enabled + 0x1 + + + + + HSIRDYIE + HSI16 ready interrupt enable + + 3 + 1 + read-write + + + B_0x0 + HSI16 ready interrupt disabled + 0x0 + + + B_0x1 + HSI16 ready interrupt enabled + 0x1 + + + + + HSERDYIE + HSE ready interrupt enable + + 4 + 1 + read-write + + + B_0x0 + HSE ready interrupt disabled + 0x0 + + + B_0x1 + HSE ready interrupt enabled + 0x1 + + + + + PLLRDYIE + PLL ready interrupt enable + + 5 + 1 + read-write + + + B_0x0 + PLL lock interrupt disabled + 0x0 + + + B_0x1 + PLL lock interrupt enabled + 0x1 + + + + + LSECSSIE + LSE clock security system interrupt enable + + 9 + 1 + read-write + + + B_0x0 + Clock security interrupt caused by LSE clock failure disabled + 0x0 + + + B_0x1 + Clock security interrupt caused by LSE clock failure enabled + 0x1 + + + + + HSI48RDYIE + HSI48 ready interrupt enable + + 10 + 1 + read-write + + + B_0x0 + HSI48 ready interrupt disabled + 0x0 + + + B_0x1 + HSI48 ready interrupt enabled + 0x1 + + + + + + + RCC_CIFR + RCC_CIFR + Clock interrupt flag register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LSIRDYF + LSI ready interrupt flag + + 0 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by the LSI oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the LSI oscillator + 0x1 + + + + + LSERDYF + LSE ready interrupt flag + + 1 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by the LSE oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the LSE oscillator + 0x1 + + + + + HSIRDYF + HSI16 ready interrupt flag + + 3 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by the HSI16 oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the HSI16 oscillator + 0x1 + + + + + HSERDYF + HSE ready interrupt flag + + 4 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by the HSE oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the HSE oscillator + 0x1 + + + + + PLLRDYF + PLL ready interrupt flag + + 5 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by PLL lock + 0x0 + + + B_0x1 + Clock ready interrupt caused by PLL lock + 0x1 + + + + + CSSF + Clock security system interrupt flag + + 8 + 1 + read-only + + + B_0x0 + No clock security interrupt caused by HSE clock failure + 0x0 + + + B_0x1 + Clock security interrupt caused by HSE clock failure + 0x1 + + + + + LSECSSF + LSE Clock security system interrupt flag + + 9 + 1 + read-only + + + B_0x0 + No clock security interrupt caused by LSE clock failure + 0x0 + + + B_0x1 + Clock security interrupt caused by LSE clock failure + 0x1 + + + + + HSI48RDYF + HSI48 ready interrupt flag + + 10 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by the HSI48 oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the HSI48 oscillator + 0x1 + + + + + + + RCC_CICR + RCC_CICR + Clock interrupt clear register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LSIRDYC + LSI ready interrupt clear + + 0 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + LSIRDYF cleared + 0x1 + + + + + LSERDYC + LSE ready interrupt clear + + 1 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + LSERDYF cleared + 0x1 + + + + + HSIRDYC + HSI16 ready interrupt clear + + 3 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear HSIRDYF flag + 0x1 + + + + + HSERDYC + HSE ready interrupt clear + + 4 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear HSERDYF flag + 0x1 + + + + + PLLRDYC + PLL ready interrupt clear + + 5 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear PLLRDYF flag + 0x1 + + + + + CSSC + Clock security system interrupt clear + + 8 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear CSSF flag + 0x1 + + + + + LSECSSC + LSE Clock security system interrupt clear + + 9 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear LSECSSF flag + 0x1 + + + + + HSI48RDYC + HSI48 oscillator ready interrupt clear + + 10 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear the HSI48RDYC flag + 0x1 + + + + + + + RCC_AHB1RSTR + RCC_AHB1RSTR + AHB1 peripheral reset register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMA1RST + DMA1 reset + + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset DMA1 + 0x1 + + + + + DMA2RST + DMA2 reset + + 1 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset DMA2 + 0x1 + + + + + DMAMUX1RST + Set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset DMAMUX1 + 0x1 + + + + + CORDICRST + Set and cleared by software + 3 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset CORDIC + 0x1 + + + + + FMACRST + Set and cleared by software + 4 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset FMAC + 0x1 + + + + + FLASHRST + Flash memory interface reset + + 8 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset Flash memory interface + 0x1 + + + + + CRCRST + CRC reset + + 12 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset CRC + 0x1 + + + + + + + RCC_AHB2RSTR + RCC_AHB2RSTR + AHB2 peripheral reset register + 0x2C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + GPIOARST + IO port A reset + + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset IO port A + 0x1 + + + + + GPIOBRST + IO port B reset + + 1 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset IO port B + 0x1 + + + + + GPIOCRST + IO port C reset + + 2 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset IO port C + 0x1 + + + + + GPIODRST + IO port D reset + + 3 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset IO port D + 0x1 + + + + + GPIOERST + IO port E reset + + 4 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset IO port E + 0x1 + + + + + GPIOFRST + IO port F reset + + 5 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset IO port F + 0x1 + + + + + GPIOGRST + IO port G reset + + 6 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset IO port G + 0x1 + + + + + ADC12RST + ADC12 reset + + 13 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset ADC12 interface + 0x1 + + + + + ADC345RST + ADC345 reset + + 14 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset ADC345 + 0x1 + + + + + DAC1RST + DAC1 reset + + 16 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset DAC1 + 0x1 + + + + + DAC2RST + DAC2 reset + + 17 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset DAC2 + 0x1 + + + + + DAC3RST + DAC3 reset + + 18 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset DAC3 + 0x1 + + + + + DAC4RST + DAC4 reset + + 19 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset DAC4 + 0x1 + + + + + AESRST + AESRST reset + + 24 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset AES + 0x1 + + + + + RNGRST + RNG reset + + 26 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset RNG + 0x1 + + + + + + + RCC_AHB3RSTR + RCC_AHB3RSTR + AHB3 peripheral reset register + 0x30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FMCRST + Flexible static memory controller reset + + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset FSMC + 0x1 + + + + + QSPIRST + QUADSPI reset + + 8 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset QUADSPI + 0x1 + + + + + + + RCC_APB1RSTR1 + RCC_APB1RSTR1 + APB1 peripheral reset register 1 + 0x38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIM2RST + TIM2 timer reset + + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM2 + 0x1 + + + + + TIM3RST + TIM3 timer reset + + 1 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM3 + 0x1 + + + + + TIM4RST + TIM3 timer reset + + 2 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM3 + 0x1 + + + + + TIM5RST + TIM5 timer reset + + 3 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM5 + 0x1 + + + + + TIM6RST + TIM6 timer reset + + 4 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM7 + 0x1 + + + + + TIM7RST + TIM7 timer reset + + 5 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM7 + 0x1 + + + + + CRSRST + CRS reset + + 8 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset CRS + 0x1 + + + + + SPI2RST + SPI2 reset + + 14 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset SPI2 + 0x1 + + + + + SPI3RST + SPI3 reset + + 15 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset SPI3 + 0x1 + + + + + USART2RST + USART2 reset + + 17 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset USART2 + 0x1 + + + + + USART3RST + USART3 reset + + 18 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset USART3 + 0x1 + + + + + UART4RST + UART4 reset + + 19 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset UART4 + 0x1 + + + + + UART5RST + UART5 reset + + 20 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset UART5 + 0x1 + + + + + I2C1RST + I2C1 reset + + 21 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset I2C1 + 0x1 + + + + + I2C2RST + I2C2 reset + + 22 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset I2C2 + 0x1 + + + + + USBRST + USB device reset + + 23 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset USB device + 0x1 + + + + + FDCANRST + FDCAN reset + + 25 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the FDCAN + 0x1 + + + + + PWRRST + Power interface reset + + 28 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset PWR + 0x1 + + + + + I2C3RST + I2C3 reset + + 30 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset I2C3 interface + 0x1 + + + + + LPTIM1RST + Low Power Timer 1 reset + + 31 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset LPTIM1 + 0x1 + + + + + + + RCC_APB1RSTR2 + RCC_APB1RSTR2 + APB1 peripheral reset register 2 + 0x3C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LPUART1RST + Low-power UART 1 reset + + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset LPUART1 + 0x1 + + + + + I2C4RST + I2C4 reset + + 1 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset I2C4 + 0x1 + + + + + UCPD1RST + UCPD1 reset + + 8 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset UCPD1 + 0x1 + + + + + + + RCC_APB2RSTR + RCC_APB2RSTR + APB2 peripheral reset register + 0x40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SYSCFGRST + SYSCFG + COMP + OPAMP + VREFBUF reset + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset SYSCFG + COMP + OPAMP + VREFBUF + 0x1 + + + + + TIM1RST + TIM1 timer reset + + 11 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM1 timer + 0x1 + + + + + SPI1RST + SPI1 reset + + 12 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset SPI1 + 0x1 + + + + + TIM8RST + TIM8 timer reset + + 13 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM8 timer + 0x1 + + + + + USART1RST + USART1 reset + + 14 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset USART1 + 0x1 + + + + + SPI4RST + SPI4 reset + + 15 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset SPI4 + 0x1 + + + + + TIM15RST + TIM15 timer reset + + 16 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM15 timer + 0x1 + + + + + TIM16RST + TIM16 timer reset + + 17 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM16 timer + 0x1 + + + + + TIM17RST + TIM17 timer reset + + 18 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM17 timer + 0x1 + + + + + TIM20RST + TIM20 reset + + 20 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM20 + 0x1 + + + + + SAI1RST + Serial audio interface 1 (SAI1) reset + + 21 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset SAI1 + 0x1 + + + + + HRTIM1RST + HRTIM1 reset + + 26 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset HRTIM1 + 0x1 + + + + + + + RCC_AHB1ENR + RCC_AHB1ENR + AHB1 peripheral clock enable register + 0x48 + 0x20 + 0x00000100 + 0xFFFFFFFF + + + DMA1EN + DMA1 clock enable + + 0 + 1 + read-write + + + B_0x0 + DMA1 clock disable + 0x0 + + + B_0x1 + DMA1 clock enable + 0x1 + + + + + DMA2EN + DMA2 clock enable + + 1 + 1 + read-write + + + B_0x0 + DMA2 clock disable + 0x0 + + + B_0x1 + DMA2 clock enable + 0x1 + + + + + DMAMUX1EN + DMAMUX1 clock enable + + 2 + 1 + read-write + + + B_0x0 + DMAMUX1 clock disabled + 0x0 + + + B_0x1 + DMAMUX1 clock enabled + 0x1 + + + + + CORDICEN + CORDIC clock enable + + 3 + 1 + read-write + + + B_0x0 + CORDIC clock disabled + 0x0 + + + B_0x1 + CORDIC clock enabled + 0x1 + + + + + FMACEN + FMAC enable + + 4 + 1 + read-write + + + B_0x0 + FMAC clock disabled + 0x0 + + + B_0x1 + FMAC clock enabled + 0x1 + + + + + FLASHEN + Flash memory interface clock enable + + 8 + 1 + read-write + + + B_0x0 + Flash memory interface clock disable + 0x0 + + + B_0x1 + Flash memory interface clock enable + 0x1 + + + + + CRCEN + CRC clock enable + + 12 + 1 + read-write + + + B_0x0 + CRC clock disable + 0x0 + + + B_0x1 + CRC clock enable + 0x1 + + + + + + + RCC_AHB2ENR + RCC_AHB2ENR + AHB2 peripheral clock enable register + 0x4C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + GPIOAEN + IO port A clock enable + + 0 + 1 + read-write + + + B_0x0 + IO port A clock disabled + 0x0 + + + B_0x1 + IO port A clock enabled + 0x1 + + + + + GPIOBEN + IO port B clock enable + + 1 + 1 + read-write + + + B_0x0 + IO port B clock disabled + 0x0 + + + B_0x1 + IO port B clock enabled + 0x1 + + + + + GPIOCEN + IO port C clock enable + + 2 + 1 + read-write + + + B_0x0 + IO port C clock disabled + 0x0 + + + B_0x1 + IO port C clock enabled + 0x1 + + + + + GPIODEN + IO port D clock enable + + 3 + 1 + read-write + + + B_0x0 + IO port D clock disabled + 0x0 + + + B_0x1 + IO port D clock enabled + 0x1 + + + + + GPIOEEN + IO port E clock enable + + 4 + 1 + read-write + + + B_0x0 + IO port E clock disabled + 0x0 + + + B_0x1 + IO port E clock enabled + 0x1 + + + + + GPIOFEN + IO port F clock enable + + 5 + 1 + read-write + + + B_0x0 + IO port F clock disabled + 0x0 + + + B_0x1 + IO port F clock enabled + 0x1 + + + + + GPIOGEN + IO port G clock enable + + 6 + 1 + read-write + + + B_0x0 + IO port G clock disabled + 0x0 + + + B_0x1 + IO port G clock enabled + 0x1 + + + + + ADC12EN + ADC12 clock enable + + 13 + 1 + read-write + + + B_0x0 + ADC12 clock disabled + 0x0 + + + B_0x1 + ADC12 clock enabled + 0x1 + + + + + ADC345EN + ADC345 clock enable + + 14 + 1 + read-write + + + B_0x0 + ADC345 clock disabled + 0x0 + + + B_0x1 + ADC345 clock enabled + 0x1 + + + + + DAC1EN + DAC1 clock enable + + 16 + 1 + read-write + + + B_0x0 + DAC1 clock disabled + 0x0 + + + B_0x1 + DAC1 clock enabled + 0x1 + + + + + DAC2EN + DAC2 clock enable + + 17 + 1 + read-write + + + B_0x0 + DAC2 clock disabled + 0x0 + + + B_0x1 + DAC2 clock enabled + 0x1 + + + + + DAC3EN + DAC3 clock enable + + 18 + 1 + read-write + + + B_0x0 + DAC3 clock disabled + 0x0 + + + B_0x1 + DAC3 clock enabled + 0x1 + + + + + DAC4EN + DAC4 clock enable + + 19 + 1 + read-write + + + B_0x0 + DAC4 clock disabled + 0x0 + + + B_0x1 + DAC4 clock enabled + 0x1 + + + + + AESEN + AES clock enable + + 24 + 1 + read-write + + + B_0x0 + AES clock disabled + 0x0 + + + B_0x1 + AES clock enabled + 0x1 + + + + + RNGEN + RNG enable + + 26 + 1 + read-write + + + B_0x0 + RNG disabled + 0x0 + + + B_0x1 + RNG enabled + 0x1 + + + + + + + RCC_AHB3ENR + RCC_AHB3ENR + AHB3 peripheral clock enable register + 0x50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FMCEN + Flexible static memory controller clock enable + + 0 + 1 + read-write + + + B_0x0 + FSMC clock disable + 0x0 + + + B_0x1 + FSMC clock enable + 0x1 + + + + + QSPIEN + QUADSPI memory interface clock enable + + 8 + 1 + read-write + + + B_0x0 + QUADSPI clock disable + 0x0 + + + B_0x1 + QUADSPI clock enable + 0x1 + + + + + + + RCC_APB1ENR1 + RCC_APB1ENR1 + APB1 peripheral clock enable register 1 + 0x58 + 0x20 + 0x00000400 + 0xFFFFFFFF + + + TIM2EN + TIM2 timer clock enable + + 0 + 1 + read-write + + + B_0x0 + TIM2 clock disabled + 0x0 + + + B_0x1 + TIM2 clock enabled + 0x1 + + + + + TIM3EN + TIM3 timer clock enable + + 1 + 1 + read-write + + + B_0x0 + TIM3 clock disabled + 0x0 + + + B_0x1 + TIM3 clock enabled + 0x1 + + + + + TIM4EN + TIM4 timer clock enable + + 2 + 1 + read-write + + + B_0x0 + TIM4 clock disabled + 0x0 + + + B_0x1 + TIM4 clock enabled + 0x1 + + + + + TIM5EN + TIM5 timer clock enable + + 3 + 1 + read-write + + + B_0x0 + TIM5 clock disabled + 0x0 + + + B_0x1 + TIM5 clock enabled + 0x1 + + + + + TIM6EN + TIM6 timer clock enable + + 4 + 1 + read-write + + + B_0x0 + TIM6 clock disabled + 0x0 + + + B_0x1 + TIM6 clock enabled + 0x1 + + + + + TIM7EN + TIM7 timer clock enable + + 5 + 1 + read-write + + + B_0x0 + TIM7 clock disabled + 0x0 + + + B_0x1 + TIM7 clock enabled + 0x1 + + + + + CRSEN + CRS Recovery System clock enable + + 8 + 1 + read-write + + + B_0x0 + CRS clock disabled + 0x0 + + + B_0x1 + CRS clock enabled + 0x1 + + + + + RTCAPBEN + RTC APB clock enable + + 10 + 1 + read-write + + + B_0x0 + RTC APB clock disabled + 0x0 + + + B_0x1 + RTC APB clock enabled + 0x1 + + + + + WWDGEN + Window watchdog clock enable + + 11 + 1 + read-write + + + B_0x0 + Window watchdog clock disabled + 0x0 + + + B_0x1 + Window watchdog clock enabled + 0x1 + + + + + SPI2EN + SPI2 clock enable + + 14 + 1 + read-write + + + B_0x0 + SPI2 clock disabled + 0x0 + + + B_0x1 + SPI2 clock enabled + 0x1 + + + + + SPI3EN + SPI3 clock enable + + 15 + 1 + read-write + + + B_0x0 + SPI3 clock disabled + 0x0 + + + B_0x1 + SPI3 clock enabled + 0x1 + + + + + USART2EN + USART2 clock enable + + 17 + 1 + read-write + + + B_0x0 + USART2 clock disabled + 0x0 + + + B_0x1 + USART2 clock enabled + 0x1 + + + + + USART3EN + USART3 clock enable + + 18 + 1 + read-write + + + B_0x0 + USART3 clock disabled + 0x0 + + + B_0x1 + USART3 clock enabled + 0x1 + + + + + UART4EN + UART4 clock enable + + 19 + 1 + read-write + + + B_0x0 + UART4 clock disabled + 0x0 + + + B_0x1 + UART4 clock enabled + 0x1 + + + + + UART5EN + UART5 clock enable + + 20 + 1 + read-write + + + B_0x0 + UART5 clock disabled + 0x0 + + + B_0x1 + UART5 clock enabled + 0x1 + + + + + I2C1EN + I2C1 clock enable + + 21 + 1 + read-write + + + B_0x0 + I2C1 clock disabled + 0x0 + + + B_0x1 + I2C1 clock enabled + 0x1 + + + + + I2C2EN + I2C2 clock enable + + 22 + 1 + read-write + + + B_0x0 + I2C2 clock disabled + 0x0 + + + B_0x1 + I2C2 clock enabled + 0x1 + + + + + USBEN + USB device clock enable + + 23 + 1 + read-write + + + B_0x0 + USB device clock disabled + 0x0 + + + B_0x1 + USB device clock enabled + 0x1 + + + + + FDCANEN + FDCAN clock enable + + 25 + 1 + read-write + + + B_0x0 + FDCAN clock disabled + 0x0 + + + B_0x1 + FDCAN clock enabled + 0x1 + + + + + PWREN + Power interface clock enable + + 28 + 1 + read-write + + + B_0x0 + Power interface clock disabled + 0x0 + + + B_0x1 + Power interface clock enabled + 0x1 + + + + + I2C3EN + I2C3 clock enable + + 30 + 1 + read-write + + + B_0x0 + I2C3 clock disabled + 0x0 + + + B_0x1 + I2C3 clock enabled + 0x1 + + + + + LPTIM1EN + Low power timer 1 clock enable + + 31 + 1 + read-write + + + B_0x0 + LPTIM1 clock disabled + 0x0 + + + B_0x1 + LPTIM1 clock enabled + 0x1 + + + + + + + RCC_APB1ENR2 + RCC_APB1ENR2 + APB1 peripheral clock enable register 2 + 0x5C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LPUART1EN + Low power UART 1 clock enable + + 0 + 1 + read-write + + + B_0x0 + LPUART1 clock disable + 0x0 + + + B_0x1 + LPUART1 clock enable + 0x1 + + + + + I2C4EN + I2C4 clock enable + + 1 + 1 + read-write + + + B_0x0 + I2C4 clock disabled + 0x0 + + + B_0x1 + I2C4 clock enabled + 0x1 + + + + + UCPD1EN + UCPD1 clock enable + + 8 + 1 + read-write + + + B_0x0 + UCPD1 clock disable + 0x0 + + + B_0x1 + UCPD1 clock enable + 0x1 + + + + + + + RCC_APB2ENR + RCC_APB2ENR + APB2 peripheral clock enable register + 0x60 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SYSCFGEN + SYSCFG + COMP + VREFBUF + OPAMP clock enable + + 0 + 1 + read-write + + + B_0x0 + SYSCFG + COMP + VREFBUF + OPAMP clock disabled + 0x0 + + + B_0x1 + SYSCFG + COMP + VREFBUF + OPAMP clock enabled + 0x1 + + + + + TIM1EN + TIM1 timer clock enable + + 11 + 1 + read-write + + + B_0x0 + TIM1 timer clock disabled + 0x0 + + + B_0x1 + TIM1P timer clock enabled + 0x1 + + + + + SPI1EN + SPI1 clock enable + + 12 + 1 + read-write + + + B_0x0 + SPI1 clock disabled + 0x0 + + + B_0x1 + SPI1 clock enabled + 0x1 + + + + + TIM8EN + TIM8 timer clock enable + + 13 + 1 + read-write + + + B_0x0 + TIM8 timer clock disabled + 0x0 + + + B_0x1 + TIM8 timer clock enabled + 0x1 + + + + + USART1EN + USART1clock enable + + 14 + 1 + read-write + + + B_0x0 + USART1clock disabled + 0x0 + + + B_0x1 + USART1clock enabled + 0x1 + + + + + SPI4EN + SPI4 clock enable + + 15 + 1 + read-write + + + B_0x0 + SPI4 clock disabled + 0x0 + + + B_0x1 + SPI4 clock enabled + 0x1 + + + + + TIM15EN + TIM15 timer clock enable + + 16 + 1 + read-write + + + B_0x0 + TIM15 timer clock disabled + 0x0 + + + B_0x1 + TIM15 timer clock enabled + 0x1 + + + + + TIM16EN + TIM16 timer clock enable + + 17 + 1 + read-write + + + B_0x0 + TIM16 timer clock disabled + 0x0 + + + B_0x1 + TIM16 timer clock enabled + 0x1 + + + + + TIM17EN + TIM17 timer clock enable + + 18 + 1 + read-write + + + B_0x0 + TIM17 timer clock disabled + 0x0 + + + B_0x1 + TIM17 timer clock enabled + 0x1 + + + + + TIM20EN + TIM20 timer clock enable + + 20 + 1 + read-write + + + B_0x0 + TIM20 clock disabled + 0x0 + + + B_0x1 + TIM20 clock enabled + 0x1 + + + + + SAI1EN + SAI1 clock enable + + 21 + 1 + read-write + + + B_0x0 + SAI1 clock disabled + 0x0 + + + B_0x1 + SAI1 clock enabled + 0x1 + + + + + HRTIM1EN + HRTIM1 clock enable + + 26 + 1 + read-write + + + B_0x0 + HRTIM1 clock disabled + 0x0 + + + B_0x1 + HRTIM1 clock enable + 0x1 + + + + + + + RCC_AHB1SMENR + RCC_AHB1SMENR + AHB1 peripheral clocks enable in Sleep and Stop modes register + 0x68 + 0x20 + 0x0000130F + 0xFFFFFFFF + + + DMA1SMEN + DMA1 clocks enable during Sleep and Stop modes + + 0 + 1 + read-write + + + B_0x0 + DMA1 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + DMA1 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + DMA2SMEN + DMA2 clocks enable during Sleep and Stop modes + + 1 + 1 + read-write + + + B_0x0 + DMA2 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + DMA2 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + DMAMUX1SMEN + DMAMUX1 clock enable during Sleep and Stop modes. + + 2 + 1 + read-write + + + B_0x0 + DMAMUX1 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + DMAMUX1 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + CORDICSMEN + CORDICSM clock enable. + + 3 + 1 + read-write + + + B_0x0 + CORDICSM clocks disabled. + 0x0 + + + B_0x1 + CORDICSM clocks enabled. + 0x1 + + + + + FMACSMEN + FMACSM clock enable. + + 4 + 1 + read-write + + + B_0x0 + FMACSM clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + FMACSM clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + FLASHSMEN + Flash memory interface clocks enable during Sleep and Stop modes + + 8 + 1 + read-write + + + B_0x0 + Flash memory interface clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + Flash memory interface clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + SRAM1SMEN + SRAM1 interface clocks enable during Sleep and Stop modes + + 9 + 1 + read-write + + + B_0x0 + SRAM1 interface clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + SRAM1 interface clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + CRCSMEN + CRC clocks enable during Sleep and Stop modes + + 12 + 1 + read-write + + + B_0x0 + CRC clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + CRC clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + + + RCC_AHB2SMENR + RCC_AHB2SMENR + AHB2 peripheral clocks enable in Sleep and Stop modes register + 0x6C + 0x20 + 0x050F667F + 0xFFFFFFFF + + + GPIOASMEN + IO port A clocks enable during Sleep and Stop modes + + 0 + 1 + read-write + + + B_0x0 + IO port A clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + IO port A clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + GPIOBSMEN + IO port B clocks enable during Sleep and Stop modes + + 1 + 1 + read-write + + + B_0x0 + IO port B clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + IO port B clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + GPIOCSMEN + IO port C clocks enable during Sleep and Stop modes + + 2 + 1 + read-write + + + B_0x0 + IO port C clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + IO port C clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + GPIODSMEN + IO port D clocks enable during Sleep and Stop modes + + 3 + 1 + read-write + + + B_0x0 + IO port D clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + IO port D clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + GPIOESMEN + IO port E clocks enable during Sleep and Stop modes + + 4 + 1 + read-write + + + B_0x0 + IO port E clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + IO port E clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + GPIOFSMEN + IO port F clocks enable during Sleep and Stop modes + + 5 + 1 + read-write + + + B_0x0 + IO port F clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + IO port F clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + GPIOGSMEN + IO port G clocks enable during Sleep and Stop modes + + 6 + 1 + read-write + + + B_0x0 + IO port G clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + IO port G clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + CCMSRAMSMEN + CCM SRAM interface clocks enable during Sleep and Stop modes + + 9 + 1 + read-write + + + B_0x0 + CCM SRAM interface clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + CCM SRAM interface clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + SRAM2SMEN + SRAM2 interface clocks enable during Sleep and Stop modes + + 10 + 1 + read-write + + + B_0x0 + SRAM2 interface clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + SRAM2 interface clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + ADC12SMEN + ADC12 clocks enable during Sleep and Stop modes + + 13 + 1 + read-write + + + B_0x0 + ADC12 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + ADC12 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + ADC345SMEN + ADC345 clock enable + + 14 + 1 + read-write + + + B_0x0 + ADC345 clock disabled + 0x0 + + + B_0x1 + ADC345 clock enabled + 0x1 + + + + + DAC1SMEN + DAC1 clock enable + + 16 + 1 + read-write + + + B_0x0 + DAC1 clock disabled + 0x0 + + + B_0x1 + DAC1 clock enabled during sleep and stop modes + 0x1 + + + + + DAC2SMEN + DAC2 clock enable + + 17 + 1 + read-write + + + B_0x0 + DAC2 clock disabled + 0x0 + + + B_0x1 + DAC2 clock enabled during sleep and stop modes + 0x1 + + + + + DAC3SMEN + DAC3 clock enable + + 18 + 1 + read-write + + + B_0x0 + DAC3 clock disabled + 0x0 + + + B_0x1 + DAC3 clock enabled during sleep and stop modes + 0x1 + + + + + DAC4SMEN + DAC4 clock enable + + 19 + 1 + read-write + + + B_0x0 + DAC4 clock disabled + 0x0 + + + B_0x1 + DAC4 clock enabled during sleep and stop modes + 0x1 + + + + + AESSMEN + AESM clocks enable + + 24 + 1 + read-write + + + B_0x0 + AESM clocks disabled + 0x0 + + + B_0x1 + AESM clocks enabled + 0x1 + + + + + RNGEN + RNG enable + + 26 + 1 + read-write + + + B_0x0 + RNG disabled + 0x0 + + + B_0x1 + RNG enabled + 0x1 + + + + + + + RCC_AHB3SMENR + RCC_AHB3SMENR + AHB3 peripheral clocks enable in Sleep and Stop modes register + 0x70 + 0x20 + 0x00000101 + 0xFFFFFFFF + + + FMCSMEN + Flexible static memory controller clocks enable during Sleep and Stop modes + + 0 + 1 + read-write + + + B_0x0 + FSMC clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + FSMC clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + QSPISMEN + QUADSPI memory interface clock enable during Sleep and Stop modes + + 8 + 1 + read-write + + + B_0x0 + QUADSPI clock disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + QUADSPI clock enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + + + RCC_APB1SMENR1 + RCC_APB1SMENR1 + APB1 peripheral clocks enable in Sleep and Stop modes register 1 + 0x78 + 0x20 + 0xD2FECD3F + 0xFFFFFFFF + + + TIM2SMEN + TIM2 timer clocks enable during Sleep and Stop modes + + 0 + 1 + read-write + + + B_0x0 + TIM2 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM2 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + TIM3SMEN + TIM3 timer clocks enable during Sleep and Stop modes + + 1 + 1 + read-write + + + B_0x0 + TIM3 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM3 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + TIM4SMEN + TIM4 timer clocks enable during Sleep and Stop modes + + 2 + 1 + read-write + + + B_0x0 + TIM4 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM4 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + TIM5SMEN + TIM5 timer clocks enable during Sleep and Stop modes + + 3 + 1 + read-write + + + B_0x0 + TIM5 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM5 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + TIM6SMEN + TIM6 timer clocks enable during Sleep and Stop modes + + 4 + 1 + read-write + + + B_0x0 + TIM6 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM6 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + TIM7SMEN + TIM7 timer clocks enable during Sleep and Stop modes + + 5 + 1 + read-write + + + B_0x0 + TIM7 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM7 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + CRSSMEN + CRS timer clocks enable during Sleep and Stop modes + + 8 + 1 + read-write + + + B_0x0 + CRS clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + CRS clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + RTCAPBSMEN + RTC APB clock enable during Sleep and Stop modes + + 10 + 1 + read-write + + + B_0x0 + RTC APB clock disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + RTC APB clock enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + WWDGSMEN + Window watchdog clocks enable during Sleep and Stop modes + + 11 + 1 + read-write + + + B_0x0 + Window watchdog clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + Window watchdog clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + SPI2SMEN + SPI2 clocks enable during Sleep and Stop modes + + 14 + 1 + read-write + + + B_0x0 + SPI2 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + SPI2 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + SPI3SMEN + SPI3 clocks enable during Sleep and Stop modes + + 15 + 1 + read-write + + + B_0x0 + SPI3 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + SPI3 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + USART2SMEN + USART2 clocks enable during Sleep and Stop modes + + 17 + 1 + read-write + + + B_0x0 + USART2 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + USART2 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + USART3SMEN + USART3 clocks enable during Sleep and Stop modes + + 18 + 1 + read-write + + + B_0x0 + USART3 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + USART3 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + UART4SMEN + UART4 clocks enable during Sleep and Stop modes + + 19 + 1 + read-write + + + B_0x0 + UART4 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + UART4 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + UART5SMEN + UART5 clocks enable during Sleep and Stop modes + + 20 + 1 + read-write + + + B_0x0 + UART5 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + UART5 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + I2C1SMEN + I2C1 clocks enable during Sleep and Stop modes + + 21 + 1 + read-write + + + B_0x0 + I2C1 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + I2C1 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + I2C2SMEN + I2C2 clocks enable during Sleep and Stop modes + + 22 + 1 + read-write + + + B_0x0 + I2C2 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + I2C2 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + USBSMEN + USB device clocks enable during Sleep and Stop modes + + 23 + 1 + read-write + + + B_0x0 + USB device clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + USB device clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + FDCANSMEN + FDCAN clocks enable during Sleep and Stop modes + + 25 + 1 + read-write + + + B_0x0 + FDCAN clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + FDCAN clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + PWRSMEN + Power interface clocks enable during Sleep and Stop modes + + 28 + 1 + read-write + + + B_0x0 + Power interface clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + Power interface clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + I2C3SMEN + I2C3 clocks enable during Sleep and Stop modes + + 30 + 1 + read-write + + + B_0x0 + I2C3 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + I2C3 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + LPTIM1SMEN + Low power timer 1 clocks enable during Sleep and Stop modes + + 31 + 1 + read-write + + + B_0x0 + LPTIM1 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + LPTIM1 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + + + RCC_APB1SMENR2 + RCC_APB1SMENR2 + APB1 peripheral clocks enable in Sleep and Stop modes register 2 + 0x7C + 0x20 + 0x00000103 + 0xFFFFFFFF + + + LPUART1SMEN + Low power UART 1 clocks enable during Sleep and Stop modes + + 0 + 1 + read-write + + + B_0x0 + LPUART1 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + LPUART1 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + I2C4SMEN + I2C4 clocks enable during Sleep and Stop modes + + 1 + 1 + read-write + + + B_0x0 + I2C4 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + I2C4 clock enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + UCPD1SMEN + UCPD1 clocks enable during Sleep and Stop modes + + 8 + 1 + read-write + + + B_0x0 + UCPD1 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + UCPD1 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + + + RCC_APB2SMENR + RCC_APB2SMENR + APB2 peripheral clocks enable in Sleep and Stop modes register + 0x80 + 0x20 + 0x0437F801 + 0xFFFFFFFF + + + SYSCFGSMEN + SYSCFG + COMP + VREFBUF + OPAMP clocks enable during Sleep and Stop modes + + 0 + 1 + read-write + + + B_0x0 + SYSCFG + COMP + VREFBUF + OPAMP clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + SYSCFG + COMP + VREFBUF + OPAMP clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + TIM1SMEN + TIM1 timer clocks enable during Sleep and Stop modes + + 11 + 1 + read-write + + + B_0x0 + TIM1 timer clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM1P timer clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + SPI1SMEN + SPI1 clocks enable during Sleep and Stop modes + + 12 + 1 + read-write + + + B_0x0 + SPI1 clocks disabled by the clock gating during<sup>(1)</sup> Sleep and Stop modes + 0x0 + + + B_0x1 + SPI1 clocks enabled by the clock gating during<sup>(1)</sup> Sleep and Stop modes + 0x1 + + + + + TIM8SMEN + TIM8 timer clocks enable during Sleep and Stop modes + + 13 + 1 + read-write + + + B_0x0 + TIM8 timer clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM8 timer clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + USART1SMEN + USART1clocks enable during Sleep and Stop modes + + 14 + 1 + read-write + + + B_0x0 + USART1clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + USART1clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + SPI4SMEN + SPI4 timer clocks enable during Sleep and Stop modes + + 15 + 1 + read-write + + + B_0x0 + SPI4 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + SPI4 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop mode + 0x1 + + + + + TIM15SMEN + TIM15 timer clocks enable during Sleep and Stop modes + + 16 + 1 + read-write + + + B_0x0 + TIM15 timer clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM15 timer clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop mode + 0x1 + + + + + TIM16SMEN + TIM16 timer clocks enable during Sleep and Stop modes + + 17 + 1 + read-write + + + B_0x0 + TIM16 timer clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM16 timer clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + TIM17SMEN + TIM17 timer clocks enable during Sleep and Stop modes + + 18 + 1 + read-write + + + B_0x0 + TIM17 timer clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM17 timer clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + TIM20SMEN + TIM20 timer clocks enable during Sleep and Stop modes + + 20 + 1 + read-write + + + B_0x0 + TIM20 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM20 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + SAI1SMEN + SAI1 clocks enable during Sleep and Stop modes + + 21 + 1 + read-write + + + B_0x0 + SAI1 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + SAI1 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + HRTIM1SMEN + HRTIM1 timer clocks enable during Sleep and Stop modes + + 26 + 1 + read-write + + + B_0x0 + HRTIM1 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + HRTIM1 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + + + RCC_CCIPR + RCC_CCIPR + Peripherals independent clock configuration register + 0x88 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + USART1SEL + USART1 clock source selection + + 0 + 2 + read-write + + + B_0x0 + PCLK selected as USART1 clock + 0x0 + + + B_0x1 + System clock (SYSCLK) selected as USART1 clock + 0x1 + + + B_0x2 + HSI16 clock selected as USART1 clock + 0x2 + + + B_0x3 + LSE clock selected as USART1 clock + 0x3 + + + + + USART2SEL + USART2 clock source selection + + 2 + 2 + read-write + + + B_0x0 + PCLK selected as USART2 clock + 0x0 + + + B_0x1 + System clock (SYSCLK) selected as USART2 clock + 0x1 + + + B_0x2 + HSI16 clock selected as USART2 clock + 0x2 + + + B_0x3 + LSE clock selected as USART2 clock + 0x3 + + + + + USART3SEL + USART3 clock source selection + + 4 + 2 + read-write + + + B_0x0 + PCLK selected as USART3 clock + 0x0 + + + B_0x1 + System clock (SYSCLK) selected as USART3 clock + 0x1 + + + B_0x2 + HSI16 clock selected as USART3 clock + 0x2 + + + B_0x3 + LSE clock selected as USART3 clock + 0x3 + + + + + UART4SEL + UART4 clock source selection + + 6 + 2 + read-write + + + B_0x0 + PCLK selected as UART4 clock + 0x0 + + + B_0x1 + System clock (SYSCLK) selected as UART4 clock + 0x1 + + + B_0x2 + HSI16 clock selected as UART4 clock + 0x2 + + + B_0x3 + LSE clock selected as UART4 clock + 0x3 + + + + + UART5SEL + UART5 clock source selection + + 8 + 2 + read-write + + + B_0x0 + PCLK selected as UART5 clock + 0x0 + + + B_0x1 + System clock (SYSCLK) selected as UART5 clock + 0x1 + + + B_0x2 + HSI16 clock selected as UART5 clock + 0x2 + + + B_0x3 + LSE clock selected as UART5 clock + 0x3 + + + + + LPUART1SEL + LPUART1 clock source selection + + 10 + 2 + read-write + + + B_0x0 + PCLK selected as LPUART1 clock + 0x0 + + + B_0x1 + System clock (SYSCLK) selected as LPUART1 clock + 0x1 + + + B_0x2 + HSI16 clock selected as LPUART1 clock + 0x2 + + + B_0x3 + LSE clock selected as LPUART1 clock + 0x3 + + + + + I2C1SEL + I2C1 clock source selection + + 12 + 2 + read-write + + + B_0x0 + PCLK selected as I2C1 clock + 0x0 + + + B_0x1 + System clock (SYSCLK) selected as I2C1 clock + 0x1 + + + B_0x2 + HSI16 clock selected as I2C1 clock + 0x2 + + + + + I2C2SEL + I2C2 clock source selection + + 14 + 2 + read-write + + + B_0x0 + PCLK selected as I2C2 clock + 0x0 + + + B_0x1 + System clock (SYSCLK) selected as I2C2 clock + 0x1 + + + B_0x2 + HSI16 clock selected as I2C2 clock + 0x2 + + + + + I2C3SEL + I2C3 clock source selection + + 16 + 2 + read-write + + + B_0x0 + PCLK selected as I2C3 clock + 0x0 + + + B_0x1 + System clock (SYSCLK) selected as I2C3 clock + 0x1 + + + B_0x2 + HSI16 clock selected as I2C3 clock + 0x2 + + + + + LPTIM1SEL + Low power timer 1 clock source selection + + 18 + 2 + read-write + + + B_0x0 + PCLK selected as LPTIM1 clock + 0x0 + + + B_0x1 + LSI clock selected as LPTIM1 clock + 0x1 + + + B_0x2 + HSI16 clock selected as LPTIM1 clock + 0x2 + + + B_0x3 + LSE clock selected as LPTIM1 clock + 0x3 + + + + + SAI1SEL + clock source selection + + 20 + 2 + read-write + + + B_0x0 + System clock selected as SAI clock + 0x0 + + + B_0x1 + PLL Q clock selected as SAI clock + 0x1 + + + B_0x2 + Clock provided on I2S_CKIN pin selected as SAI clock + 0x2 + + + B_0x3 + HSI16 clock selected as SAI clock + 0x3 + + + + + I2S23SEL + clock source selection + + 22 + 2 + read-write + + + B_0x0 + System clock selected as I2S23 clock + 0x0 + + + B_0x1 + PLL Q clock selected as I2S23 clock + 0x1 + + + B_0x2 + Clock provided on I2S_CKIN pin is selected as I2S23 clock + 0x2 + + + B_0x3 + HSI16 clock selected as I2S23 clock. + 0x3 + + + + + FDCANSEL + None + 24 + 2 + read-write + + + CLK48SEL + 48 MHz clock source selection + + 26 + 2 + read-write + + + B_0x0 + HSI48 clock selected as 48 MHz clock + 0x0 + + + B_0x2 + PLL Q clock (PLL48M1CLK) selected as 48 MHz clock + 0x2 + + + B_0x3 + Reserved, must be kept at reset value + 0x3 + + + + + ADC12SEL + ADC1/2 clock source selection + + 28 + 2 + read-write + + + B_0x0 + No clock selected + 0x0 + + + B_0x1 + PLL P clock selected as ADC1/2 clock + 0x1 + + + B_0x2 + System clock selected as ADC1/2 clock + 0x2 + + + + + ADC345SEL + ADC3/4/5 clock source selection + + 30 + 2 + read-write + + + B_0x0 + No clock selected + 0x0 + + + B_0x1 + PLL P clock selected as ADC345 clock + 0x1 + + + B_0x2 + System clock selected as ADC3/4/5 clock + 0x2 + + + B_0x3 + Reserved. + 0x3 + + + + + + + RCC_BDCR + RCC_BDCR + RTC domain control register + 0x90 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LSEON + LSE oscillator enable + + 0 + 1 + read-write + + + B_0x0 + LSE oscillator OFF + 0x0 + + + B_0x1 + LSE oscillator ON + 0x1 + + + + + LSERDY + LSE oscillator ready + + 1 + 1 + read-only + + + B_0x0 + LSE oscillator not ready + 0x0 + + + B_0x1 + LSE oscillator ready + 0x1 + + + + + LSEBYP + LSE oscillator bypass + + 2 + 1 + read-write + + + B_0x0 + LSE oscillator not bypassed + 0x0 + + + B_0x1 + LSE oscillator bypassed + 0x1 + + + + + LSEDRV + LSE oscillator drive capability + + 3 + 2 + read-write + + + B_0x0 + Xtal mode lower driving capability + 0x0 + + + B_0x1 + Xtal mode medium low driving capability + 0x1 + + + B_0x2 + Xtal mode medium high driving capability + 0x2 + + + B_0x3 + Xtal mode higher driving capability + 0x3 + + + + + LSECSSON + CSS on LSE enable + + 5 + 1 + read-write + + + B_0x0 + CSS on LSE (32 kHz external oscillator) OFF + 0x0 + + + B_0x1 + CSS on LSE (32 kHz external oscillator) ON + 0x1 + + + + + LSECSSD + CSS on LSE failure Detection + + 6 + 1 + read-only + + + B_0x0 + No failure detected on LSE (32 kHz oscillator) + 0x0 + + + B_0x1 + Failure detected on LSE (32 kHz oscillator) + 0x1 + + + + + RTCSEL + RTC clock source selection + + 8 + 2 + read-write + + + B_0x0 + No clock + 0x0 + + + B_0x1 + LSE oscillator clock used as RTC clock + 0x1 + + + B_0x2 + LSI oscillator clock used as RTC clock + 0x2 + + + B_0x3 + HSE oscillator clock divided by 32 used as RTC clock + 0x3 + + + + + RTCEN + RTC clock enable + + 15 + 1 + read-write + + + B_0x0 + RTC clock disabled + 0x0 + + + B_0x1 + RTC clock enabled + 0x1 + + + + + BDRST + RTC domain software reset + + 16 + 1 + read-write + + + B_0x0 + Reset not activated + 0x0 + + + B_0x1 + Reset the entire RTC domain + 0x1 + + + + + LSCOEN + Low speed clock output enable + + 24 + 1 + read-write + + + B_0x0 + Low speed clock output (LSCO) disable + 0x0 + + + B_0x1 + Low speed clock output (LSCO) enable + 0x1 + + + + + LSCOSEL + Low speed clock output selection + + 25 + 1 + read-write + + + B_0x0 + LSI clock selected + 0x0 + + + B_0x1 + LSE clock selected + 0x1 + + + + + + + RCC_CSR + RCC_CSR + Control/status register + 0x94 + 0x20 + 0x0C000000 + 0xFFFFFFFF + + + LSION + LSI oscillator enable + + 0 + 1 + read-write + + + B_0x0 + LSI oscillator OFF + 0x0 + + + B_0x1 + LSI oscillator ON + 0x1 + + + + + LSIRDY + LSI oscillator ready + + 1 + 1 + read-only + + + B_0x0 + LSI oscillator not ready + 0x0 + + + B_0x1 + LSI oscillator ready + 0x1 + + + + + RMVF + Remove reset flag + + 23 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear the reset flags + 0x1 + + + + + OBLRSTF + Option byte loader reset flag + + 25 + 1 + read-only + + + B_0x0 + No reset from Option Byte loading occurred + 0x0 + + + B_0x1 + Reset from Option Byte loading occurred + 0x1 + + + + + PINRSTF + Pin reset flag + + 26 + 1 + read-only + + + B_0x0 + No reset from NRST pin occurred + 0x0 + + + B_0x1 + Reset from NRST pin occurred + 0x1 + + + + + BORRSTF + BOR flag + + 27 + 1 + read-only + + + B_0x0 + No BOR occurred + 0x0 + + + B_0x1 + BOR occurred + 0x1 + + + + + SFTRSTF + Software reset flag + + 28 + 1 + read-only + + + B_0x0 + No software reset occurred + 0x0 + + + B_0x1 + Software reset occurred + 0x1 + + + + + IWDGRSTF + Independent window watchdog reset flag + + 29 + 1 + read-only + + + B_0x0 + No independent watchdog reset occurred + 0x0 + + + B_0x1 + Independent watchdog reset occurred + 0x1 + + + + + WWDGRSTF + Window watchdog reset flag + + 30 + 1 + read-only + + + B_0x0 + No window watchdog reset occurred + 0x0 + + + B_0x1 + Window watchdog reset occurred + 0x1 + + + + + LPWRRSTF + Low-power reset flag + + 31 + 1 + read-only + + + B_0x0 + No illegal mode reset occurred + 0x0 + + + B_0x1 + Illegal mode reset occurred + 0x1 + + + + + + + RCC_CRRCR + RCC_CRRCR + Clock recovery RC register + 0x98 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + HSI48ON + HSI48 clock enable + + 0 + 1 + read-write + + + B_0x0 + HSI48 oscillator OFF + 0x0 + + + B_0x1 + HSI48 oscillator ON + 0x1 + + + + + HSI48RDY + HSI48 clock ready flag + + 1 + 1 + read-only + + + B_0x0 + HSI48 oscillator not ready + 0x0 + + + B_0x1 + HSI48 oscillator ready + 0x1 + + + + + HSI48CAL + HSI48 clock calibration + + 7 + 9 + read-only + + + + + RCC_CCIPR2 + RCC_CCIPR2 + Peripherals independent clock configuration register + 0x9C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + I2C4SEL + I2C4 clock source selection + + 0 + 2 + read-write + + + B_0x0 + PCLK selected as I2C4 clock + 0x0 + + + B_0x1 + System clock (SYSCLK) selected as I2C4 clock + 0x1 + + + B_0x2 + HSI16 clock selected as I2C4 clock + 0x2 + + + + + QSPISEL + QUADSPI clock source selection + + 20 + 2 + read-write + + + B_0x0 + system clock selected as QUADSPI kernel clock + 0x0 + + + B_0x1 + HSI16 clock selected as QUADSPI kernel clock + 0x1 + + + B_0x2 + PLL Q clock selected as QUADSPI kernel clock + 0x2 + + + + + + + + + RNG + Random number generator + RNG + 0x50060800 + + 0x0 + 0x400 + registers + + + RNG + RNG + 90 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + CED + Clock error detection + 5 + 1 + + + IE + Interrupt enable + 3 + 1 + + + RNGEN + Random number generator enable + 2 + 1 + + + + + SR + SR + status register + 0x4 + 0x20 + 0x00000000 + + + SEIS + Seed error interrupt status + 6 + 1 + read-write + + + CEIS + Clock error interrupt status + 5 + 1 + read-write + + + SECS + Seed error current status + 2 + 1 + read-only + + + CECS + Clock error current status + 1 + 1 + read-only + + + DRDY + Data ready + 0 + 1 + read-only + + + + + DR + DR + data register + 0x8 + 0x20 + read-only + 0x00000000 + + + RNDATA + Random data + 0 + 32 + + + + + + + RTC + Real-time clock + RTC + 0x40002800 + + 0x0 + 0x400 + registers + + + RTC_TAMP_CSS_LSE + RTC_TAMP_CSS_LSE + 2 + + + RTC_WKUP + RTC Wakeup timer + 3 + + + RTC_ALARM + RTC_ALARM + 41 + + + + TR + TR + time register + 0x0 + 0x20 + read-write + 0x00000000 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + DR + DR + date register + 0x4 + 0x20 + read-write + 0x00002101 + + + YT + Year tens in BCD format + 20 + 4 + + + YU + Year units in BCD format + 16 + 4 + + + WDU + Week day units + 13 + 3 + + + MT + Month tens in BCD format + 12 + 1 + + + MU + Month units in BCD format + 8 + 4 + + + DT + Date tens in BCD format + 4 + 2 + + + DU + Date units in BCD format + 0 + 4 + + + + + SSR + SSR + sub second register + 0x8 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value + 0 + 16 + + + + + ICSR + ICSR + initialization and status register + 0xC + 0x20 + 0x00000007 + + + ALRAWF + Alarm A write flag + 0 + 1 + read-only + + + ALRBWF + Alarm B write flag + 1 + 1 + read-only + + + WUTWF + Wakeup timer write flag + 2 + 1 + read-only + + + SHPF + Shift operation pending + 3 + 1 + read-write + + + INITS + Initialization status flag + 4 + 1 + read-only + + + RSF + Registers synchronization flag + 5 + 1 + read-write + + + INITF + Initialization flag + 6 + 1 + read-only + + + INIT + Initialization mode + 7 + 1 + read-write + + + RECALPF + Recalibration pending Flag + 16 + 1 + read-only + + + + + PRER + PRER + prescaler register + 0x10 + 0x20 + read-write + 0x007F00FF + + + PREDIV_A + Asynchronous prescaler factor + 16 + 7 + + + PREDIV_S + Synchronous prescaler factor + 0 + 15 + + + + + WUTR + WUTR + wakeup timer register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + WUT + Wakeup auto-reload value bits + 0 + 16 + + + + + CR + CR + control register + 0x18 + 0x20 + read-write + 0x00000000 + + + WCKSEL + Wakeup clock selection + 0 + 3 + + + TSEDGE + Time-stamp event active edge + 3 + 1 + + + REFCKON + Reference clock detection enable (50 or 60 Hz) + 4 + 1 + + + BYPSHAD + Bypass the shadow registers + 5 + 1 + + + FMT + Hour format + 6 + 1 + + + ALRAE + Alarm A enable + 8 + 1 + + + ALRBE + Alarm B enable + 9 + 1 + + + WUTE + Wakeup timer enable + 10 + 1 + + + TSE + Time stamp enable + 11 + 1 + + + ALRAIE + Alarm A interrupt enable + 12 + 1 + + + ALRBIE + Alarm B interrupt enable + 13 + 1 + + + WUTIE + Wakeup timer interrupt enable + 14 + 1 + + + TSIE + Time-stamp interrupt enable + 15 + 1 + + + ADD1H + Add 1 hour (summer time change) + 16 + 1 + + + SUB1H + Subtract 1 hour (winter time change) + 17 + 1 + + + BKP + Backup + 18 + 1 + + + COSEL + Calibration output selection + 19 + 1 + + + POL + Output polarity + 20 + 1 + + + OSEL + Output selection + 21 + 2 + + + COE + Calibration output enable + 23 + 1 + + + ITSE + timestamp on internal event enable + 24 + 1 + + + TAMPTS + TAMPTS + 25 + 1 + + + TAMPOE + TAMPOE + 26 + 1 + + + TAMPALRM_PU + TAMPALRM_PU + 29 + 1 + + + TAMPALRM_TYPE + TAMPALRM_TYPE + 30 + 1 + + + OUT2EN + OUT2EN + 31 + 1 + + + + + WPR + WPR + write protection register + 0x24 + 0x20 + write-only + 0x00000000 + + + KEY + Write protection key + 0 + 8 + + + + + CALR + CALR + calibration register + 0x28 + 0x20 + read-write + 0x00000000 + + + CALP + Increase frequency of RTC by 488.5 ppm + 15 + 1 + + + CALW8 + Use an 8-second calibration cycle period + 14 + 1 + + + CALW16 + Use a 16-second calibration cycle period + 13 + 1 + + + CALM + Calibration minus + 0 + 9 + + + + + SHIFTR + SHIFTR + shift control register + 0x2C + 0x20 + write-only + 0x00000000 + + + ADD1S + Add one second + 31 + 1 + + + SUBFS + Subtract a fraction of a second + 0 + 15 + + + + + TSTR + TSTR + time stamp time register + 0x30 + 0x20 + read-only + 0x00000000 + + + SU + Second units in BCD format + 0 + 4 + + + ST + Second tens in BCD format + 4 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + MNT + Minute tens in BCD format + 12 + 3 + + + HU + Hour units in BCD format + 16 + 4 + + + HT + Hour tens in BCD format + 20 + 2 + + + PM + AM/PM notation + 22 + 1 + + + + + TSDR + TSDR + time stamp date register + 0x34 + 0x20 + read-only + 0x00000000 + + + WDU + Week day units + 13 + 3 + + + MT + Month tens in BCD format + 12 + 1 + + + MU + Month units in BCD format + 8 + 4 + + + DT + Date tens in BCD format + 4 + 2 + + + DU + Date units in BCD format + 0 + 4 + + + + + TSSSR + TSSSR + timestamp sub second register + 0x38 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value + 0 + 16 + + + + + ALRMAR + ALRMAR + alarm A register + 0x40 + 0x20 + read-write + 0x00000000 + + + MSK4 + Alarm A date mask + 31 + 1 + + + WDSEL + Week day selection + 30 + 1 + + + DT + Date tens in BCD format + 28 + 2 + + + DU + Date units or day in BCD format + 24 + 4 + + + MSK3 + Alarm A hours mask + 23 + 1 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MSK2 + Alarm A minutes mask + 15 + 1 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + MSK1 + Alarm A seconds mask + 7 + 1 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + ALRMASSR + ALRMASSR + alarm A sub second register + 0x44 + 0x20 + read-write + 0x00000000 + + + MASKSS + Mask the most-significant bits starting at this bit + 24 + 4 + + + SS + Sub seconds value + 0 + 15 + + + + + ALRMBR + ALRMBR + alarm B register + 0x48 + 0x20 + read-write + 0x00000000 + + + MSK4 + Alarm B date mask + 31 + 1 + + + WDSEL + Week day selection + 30 + 1 + + + DT + Date tens in BCD format + 28 + 2 + + + DU + Date units or day in BCD format + 24 + 4 + + + MSK3 + Alarm B hours mask + 23 + 1 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MSK2 + Alarm B minutes mask + 15 + 1 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + MSK1 + Alarm B seconds mask + 7 + 1 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + ALRMBSSR + ALRMBSSR + alarm B sub second register + 0x4C + 0x20 + read-write + 0x00000000 + + + MASKSS + Mask the most-significant bits starting at this bit + 24 + 4 + + + SS + Sub seconds value + 0 + 15 + + + + + SR + SR + status register + 0x50 + 0x20 + read-only + 0x00000000 + + + ALRAF + ALRAF + 0 + 1 + + + ALRBF + ALRBF + 1 + 1 + + + WUTF + WUTF + 2 + 1 + + + TSF + TSF + 3 + 1 + + + TSOVF + TSOVF + 4 + 1 + + + ITSF + ITSF + 5 + 1 + + + + + MISR + MISR + status register + 0x54 + 0x20 + read-only + 0x00000000 + + + ALRAMF + ALRAMF + 0 + 1 + + + ALRBMF + ALRBMF + 1 + 1 + + + WUTMF + WUTMF + 2 + 1 + + + TSMF + TSMF + 3 + 1 + + + TSOVMF + TSOVMF + 4 + 1 + + + ITSMF + ITSMF + 5 + 1 + + + + + SCR + SCR + status register + 0x5C + 0x20 + write-only + 0x00000000 + + + CALRAF + CALRAF + 0 + 1 + + + CALRBF + CALRBF + 1 + 1 + + + CWUTF + CWUTF + 2 + 1 + + + CTSF + CTSF + 3 + 1 + + + CTSOVF + CTSOVF + 4 + 1 + + + CITSF + CITSF + 5 + 1 + + + + + + + SAI + Serial audio interface + SAI + 0x40015400 + + 0x0 + 0x400 + registers + + + SAI + SAI + 76 + + + + BCR1 + BCR1 + BConfiguration register 1 + 0x24 + 0x20 + read-write + 0x00000040 + + + MCKEN + MCKEN + 27 + 1 + + + OSR + OSR + 26 + 1 + + + MCJDIV + Master clock divider + 20 + 6 + + + NODIV + No divider + 19 + 1 + + + DMAEN + DMA enable + 17 + 1 + + + SAIBEN + Audio block B enable + 16 + 1 + + + OutDri + Output drive + 13 + 1 + + + MONO + Mono mode + 12 + 1 + + + SYNCEN + Synchronization enable + 10 + 2 + + + CKSTR + Clock strobing edge + 9 + 1 + + + LSBFIRST + Least significant bit first + 8 + 1 + + + DS + Data size + 5 + 3 + + + PRTCFG + Protocol configuration + 2 + 2 + + + MODE + Audio block mode + 0 + 2 + + + + + BCR2 + BCR2 + BConfiguration register 2 + 0x28 + 0x20 + read-write + 0x00000000 + + + COMP + Companding mode + 14 + 2 + + + CPL + Complement bit + 13 + 1 + + + MUTECN + Mute counter + 7 + 6 + + + MUTEVAL + Mute value + 6 + 1 + + + MUTE + Mute + 5 + 1 + + + TRIS + Tristate management on data line + 4 + 1 + + + FFLUS + FIFO flush + 3 + 1 + + + FTH + FIFO threshold + 0 + 3 + + + + + BFRCR + BFRCR + BFRCR + 0x2C + 0x20 + read-write + 0x00000007 + + + FSOFF + Frame synchronization offset + 18 + 1 + + + FSPOL + Frame synchronization polarity + 17 + 1 + + + FSDEF + Frame synchronization definition + 16 + 1 + + + FSALL + Frame synchronization active level length + 8 + 7 + + + FRL + Frame length + 0 + 8 + + + + + BSLOTR + BSLOTR + BSlot register + 0x30 + 0x20 + read-write + 0x00000000 + + + SLOTEN + Slot enable + 16 + 16 + + + NBSLOT + Number of slots in an audio frame + 8 + 4 + + + SLOTSZ + Slot size + 6 + 2 + + + FBOFF + First bit offset + 0 + 5 + + + + + BIM + BIM + BInterrupt mask register2 + 0x34 + 0x20 + read-write + 0x00000000 + + + LFSDETIE + Late frame synchronization detection interrupt enable + 6 + 1 + + + AFSDETIE + Anticipated frame synchronization detection interrupt enable + 5 + 1 + + + CNRDYIE + Codec not ready interrupt enable + 4 + 1 + + + FREQIE + FIFO request interrupt enable + 3 + 1 + + + WCKCFG + Wrong clock configuration interrupt enable + 2 + 1 + + + MUTEDET + Mute detection interrupt enable + 1 + 1 + + + OVRUDRIE + Overrun/underrun interrupt enable + 0 + 1 + + + + + BSR + BSR + BStatus register + 0x38 + 0x20 + read-only + 0x00000000 + + + FLVL + FIFO level threshold + 16 + 3 + + + LFSDET + Late frame synchronization detection + 6 + 1 + + + AFSDET + Anticipated frame synchronization detection + 5 + 1 + + + CNRDY + Codec not ready + 4 + 1 + + + FREQ + FIFO request + 3 + 1 + + + WCKCFG + Wrong clock configuration flag + 2 + 1 + + + MUTEDET + Mute detection + 1 + 1 + + + OVRUDR + Overrun / underrun + 0 + 1 + + + + + BCLRFR + BCLRFR + BClear flag register + 0x3C + 0x20 + write-only + 0x00000000 + + + LFSDET + Clear late frame synchronization detection flag + 6 + 1 + + + CAFSDET + Clear anticipated frame synchronization detection flag + 5 + 1 + + + CNRDY + Clear codec not ready flag + 4 + 1 + + + WCKCFG + Clear wrong clock configuration flag + 2 + 1 + + + MUTEDET + Mute detection flag + 1 + 1 + + + OVRUDR + Clear overrun / underrun + 0 + 1 + + + + + BDR + BDR + BData register + 0x40 + 0x20 + read-write + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + ACR1 + ACR1 + AConfiguration register 1 + 0x4 + 0x20 + read-write + 0x00000040 + + + MCKEN + MCKEN + 27 + 1 + + + OSR + OSR + 26 + 1 + + + MCJDIV + Master clock divider + 20 + 6 + + + NODIV + No divider + 19 + 1 + + + DMAEN + DMA enable + 17 + 1 + + + SAIAEN + Audio block A enable + 16 + 1 + + + OutDri + Output drive + 13 + 1 + + + MONO + Mono mode + 12 + 1 + + + SYNCEN + Synchronization enable + 10 + 2 + + + CKSTR + Clock strobing edge + 9 + 1 + + + LSBFIRST + Least significant bit first + 8 + 1 + + + DS + Data size + 5 + 3 + + + PRTCFG + Protocol configuration + 2 + 2 + + + MODE + Audio block mode + 0 + 2 + + + + + ACR2 + ACR2 + AConfiguration register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + COMP + Companding mode + 14 + 2 + + + CPL + Complement bit + 13 + 1 + + + MUTECN + Mute counter + 7 + 6 + + + MUTEVAL + Mute value + 6 + 1 + + + MUTE + Mute + 5 + 1 + + + TRIS + Tristate management on data line + 4 + 1 + + + FFLUS + FIFO flush + 3 + 1 + + + FTH + FIFO threshold + 0 + 3 + + + + + AFRCR + AFRCR + AFRCR + 0xC + 0x20 + read-write + 0x00000007 + + + FSOFF + Frame synchronization offset + 18 + 1 + + + FSPOL + Frame synchronization polarity + 17 + 1 + + + FSDEF + Frame synchronization definition + 16 + 1 + + + FSALL + Frame synchronization active level length + 8 + 7 + + + FRL + Frame length + 0 + 8 + + + + + ASLOTR + ASLOTR + ASlot register + 0x10 + 0x20 + read-write + 0x00000000 + + + SLOTEN + Slot enable + 16 + 16 + + + NBSLOT + Number of slots in an audio frame + 8 + 4 + + + SLOTSZ + Slot size + 6 + 2 + + + FBOFF + First bit offset + 0 + 5 + + + + + AIM + AIM + AInterrupt mask register2 + 0x14 + 0x20 + read-write + 0x00000000 + + + LFSDET + Late frame synchronization detection interrupt enable + 6 + 1 + + + AFSDETIE + Anticipated frame synchronization detection interrupt enable + 5 + 1 + + + CNRDYIE + Codec not ready interrupt enable + 4 + 1 + + + FREQIE + FIFO request interrupt enable + 3 + 1 + + + WCKCFG + Wrong clock configuration interrupt enable + 2 + 1 + + + MUTEDET + Mute detection interrupt enable + 1 + 1 + + + OVRUDRIE + Overrun/underrun interrupt enable + 0 + 1 + + + + + ASR + ASR + AStatus register + 0x18 + 0x20 + read-write + 0x00000000 + + + FLVL + FIFO level threshold + 16 + 3 + + + LFSDET + Late frame synchronization detection + 6 + 1 + + + AFSDET + Anticipated frame synchronization detection + 5 + 1 + + + CNRDY + Codec not ready + 4 + 1 + + + FREQ + FIFO request + 3 + 1 + + + WCKCFG + Wrong clock configuration flag. This bit is read only + 2 + 1 + + + MUTEDET + Mute detection + 1 + 1 + + + OVRUDR + Overrun / underrun + 0 + 1 + + + + + ACLRFR + ACLRFR + AClear flag register + 0x1C + 0x20 + read-write + 0x00000000 + + + LFSDET + Clear late frame synchronization detection flag + 6 + 1 + + + CAFSDET + Clear anticipated frame synchronization detection flag + 5 + 1 + + + CNRDY + Clear codec not ready flag + 4 + 1 + + + WCKCFG + Clear wrong clock configuration flag + 2 + 1 + + + MUTEDET + Mute detection flag + 1 + 1 + + + OVRUDR + Clear overrun / underrun + 0 + 1 + + + + + ADR + ADR + AData register + 0x20 + 0x20 + read-write + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + PDMCR + PDMCR + PDM control register + 0x44 + 0x20 + read-write + 0x00000000 + + + PDMEN + PDMEN + 0 + 1 + + + MICNBR + MICNBR + 4 + 2 + + + CKEN1 + CKEN1 + 8 + 1 + + + CKEN2 + CKEN2 + 9 + 1 + + + CKEN3 + CKEN3 + 10 + 1 + + + CKEN4 + CKEN4 + 11 + 1 + + + + + PDMDLY + PDMDLY + PDM delay register + 0x48 + 0x20 + read-write + 0x00000000 + + + DLYM1L + DLYM1L + 0 + 3 + + + DLYM1R + DLYM1R + 4 + 3 + + + DLYM2L + DLYM2L + 8 + 3 + + + DLYM2R + DLYM2R + 12 + 3 + + + DLYM3L + DLYM3L + 16 + 3 + + + DLYM3R + DLYM3R + 20 + 3 + + + DLYM4L + DLYM4L + 24 + 3 + + + DLYM4R + DLYM4R + 28 + 3 + + + + + + + SPI1 + Serial peripheral interface/Inter-IC sound + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 + 35 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + BIDIMODE + Bidirectional data mode enable + 15 + 1 + + + BIDIOE + Output enable in bidirectional mode + 14 + 1 + + + CRCEN + Hardware CRC calculation enable + 13 + 1 + + + CRCNEXT + CRC transfer next + 12 + 1 + + + DFF + Data frame format + 11 + 1 + + + RXONLY + Receive only + 10 + 1 + + + SSM + Software slave management + 9 + 1 + + + SSI + Internal slave select + 8 + 1 + + + LSBFIRST + Frame format + 7 + 1 + + + SPE + SPI enable + 6 + 1 + + + BR + Baud rate control + 3 + 3 + + + MSTR + Master selection + 2 + 1 + + + CPOL + Clock polarity + 1 + 1 + + + CPHA + Clock phase + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x00000700 + + + RXDMAEN + Rx buffer DMA enable + 0 + 1 + + + TXDMAEN + Tx buffer DMA enable + 1 + 1 + + + SSOE + SS output enable + 2 + 1 + + + NSSP + NSS pulse management + 3 + 1 + + + FRF + Frame format + 4 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + RXNEIE + RX buffer not empty interrupt enable + 6 + 1 + + + TXEIE + Tx buffer empty interrupt enable + 7 + 1 + + + DS + Data size + 8 + 4 + + + FRXTH + FIFO reception threshold + 12 + 1 + + + LDMA_RX + Last DMA transfer for reception + 13 + 1 + + + LDMA_TX + Last DMA transfer for transmission + 14 + 1 + + + + + SR + SR + status register + 0x8 + 0x20 + 0x00000002 + + + RXNE + Receive buffer not empty + 0 + 1 + read-only + + + TXE + Transmit buffer empty + 1 + 1 + read-only + + + CRCERR + CRC error flag + 4 + 1 + read-write + + + MODF + Mode fault + 5 + 1 + read-only + + + OVR + Overrun flag + 6 + 1 + read-only + + + BSY + Busy flag + 7 + 1 + read-only + + + TIFRFE + TI frame format error + 8 + 1 + read-only + + + FRLVL + FIFO reception level + 9 + 2 + read-only + + + FTLVL + FIFO transmission level + 11 + 2 + read-only + + + + + DR + DR + data register + 0xC + 0x20 + read-write + 0x00000000 + + + DR + Data register + 0 + 16 + + + + + CRCPR + CRCPR + CRC polynomial register + 0x10 + 0x20 + read-write + 0x00000007 + + + CRCPOLY + CRC polynomial register + 0 + 16 + + + + + RXCRCR + RXCRCR + RX CRC register + 0x14 + 0x20 + read-only + 0x00000000 + + + RxCRC + Rx CRC register + 0 + 16 + + + + + TXCRCR + TXCRCR + TX CRC register + 0x18 + 0x20 + read-only + 0x00000000 + + + TxCRC + Tx CRC register + 0 + 16 + + + + + I2SCFGR + I2SCFGR + configuration register + 0x1C + 0x20 + read-write + 0x00000000 + + + CHLEN + CHLEN + 0 + 1 + + + DATLEN + DATLEN + 1 + 2 + + + CKPOL + CKPOL + 3 + 1 + + + I2SSTD + I2SSTD + 4 + 2 + + + PCMSYNC + PCMSYNC + 7 + 1 + + + I2SCFG + I2SCFG + 8 + 2 + + + I2SE + I2SE + 10 + 1 + + + I2SMOD + I2SMOD + 11 + 1 + + + + + I2SPR + I2SPR + prescaler register + 0x20 + 0x20 + read-write + 0x00000002 + + + I2SDIV + I2SDIV + 0 + 8 + + + ODD + ODD + 8 + 1 + + + MCKOE + MCKOE + 9 + 1 + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 + 36 + + + + SPI3 + 0x40003C00 + + SPI3 + SPI3 + 51 + + + + SYSCFG + System configuration controller + SYSCFG + 0x40010000 + + 0x0 + 0x2A + registers + + + + MEMRMP + MEMRMP + Remap Memory register + 0x0 + 0x20 + read-write + 0x00000000 + + + MEM_MODE + Memory mapping selection + 0 + 3 + + + FB_mode + User Flash Bank mode + 8 + 1 + + + + + CFGR1 + CFGR1 + peripheral mode configuration register + 0x4 + 0x20 + read-write + 0x7C000001 + + + BOOSTEN + BOOSTEN + 8 + 1 + + + ANASWVDD + GPIO analog switch control voltage selection + 9 + 1 + + + I2C_PB6_FMP + FM+ drive capability on PB6 + 16 + 1 + + + I2C_PB7_FMP + FM+ drive capability on PB6 + 17 + 1 + + + I2C_PB8_FMP + FM+ drive capability on PB6 + 18 + 1 + + + I2C_PB9_FMP + FM+ drive capability on PB6 + 19 + 1 + + + I2C1_FMP + I2C1 FM+ drive capability enable + 20 + 1 + + + I2C2_FMP + I2C1 FM+ drive capability enable + 21 + 1 + + + I2C3_FMP + I2C1 FM+ drive capability enable + 22 + 1 + + + I2C4_FMP + I2C1 FM+ drive capability enable + 23 + 1 + + + FPU_IE + FPU Interrupts Enable + 26 + 6 + + + + + EXTICR1 + EXTICR1 + external interrupt configuration register 1 + 0x8 + 0x20 + read-write + 0x0000 + + + EXTI3 + EXTI x configuration (x = 0 to 3) + 12 + 4 + + + EXTI2 + EXTI x configuration (x = 0 to 3) + 8 + 4 + + + EXTI1 + EXTI x configuration (x = 0 to 3) + 4 + 4 + + + EXTI0 + EXTI x configuration (x = 0 to 3) + 0 + 4 + + + + + EXTICR2 + EXTICR2 + external interrupt configuration register 2 + 0xC + 0x20 + read-write + 0x0000 + + + EXTI7 + EXTI x configuration (x = 4 to 7) + 12 + 4 + + + EXTI6 + EXTI x configuration (x = 4 to 7) + 8 + 4 + + + EXTI5 + EXTI x configuration (x = 4 to 7) + 4 + 4 + + + EXTI4 + EXTI x configuration (x = 4 to 7) + 0 + 4 + + + + + EXTICR3 + EXTICR3 + external interrupt configuration register 3 + 0x10 + 0x20 + read-write + 0x0000 + + + EXTI11 + EXTI x configuration (x = 8 to 11) + 12 + 4 + + + EXTI10 + EXTI10 + 8 + 4 + + + EXTI9 + EXTI x configuration (x = 8 to 11) + 4 + 4 + + + EXTI8 + EXTI x configuration (x = 8 to 11) + 0 + 4 + + + + + EXTICR4 + EXTICR4 + external interrupt configuration register 4 + 0x14 + 0x20 + read-write + 0x0000 + + + EXTI15 + EXTI x configuration (x = 12 to 15) + 12 + 4 + + + EXTI14 + EXTI x configuration (x = 12 to 15) + 8 + 4 + + + EXTI13 + EXTI x configuration (x = 12 to 15) + 4 + 4 + + + EXTI12 + EXTI x configuration (x = 12 to 15) + 0 + 4 + + + + + SCSR + SCSR + CCM SRAM control and status register + 0x18 + 0x20 + 0x00000000 + + + CCMER + CCM SRAM Erase + 0 + 1 + read-write + + + CCMBSY + CCM SRAM busy by erase operation + 1 + 1 + read-only + + + + + CFGR2 + CFGR2 + configuration register 2 + 0x1C + 0x20 + read-write + 0x00000000 + + + CLL + Core Lockup Lock + 0 + 1 + + + SPL + SRAM Parity Lock + 1 + 1 + + + PVDL + PVD Lock + 2 + 1 + + + ECCL + ECC Lock + 3 + 1 + + + SPF + SRAM Parity Flag + 8 + 1 + + + + + SWPR + SWPR + SRAM Write protection register 1 + 0x20 + 0x20 + read-write + 0x00000000 + + + Page0_WP + Write protection + 0 + 1 + + + Page1_WP + Write protection + 1 + 1 + + + Page2_WP + Write protection + 2 + 1 + + + Page3_WP + Write protection + 3 + 1 + + + Page4_WP + Write protection + 4 + 1 + + + Page5_WP + Write protection + 5 + 1 + + + Page6_WP + Write protection + 6 + 1 + + + Page7_WP + Write protection + 7 + 1 + + + Page8_WP + Write protection + 8 + 1 + + + Page9_WP + Write protection + 9 + 1 + + + Page10_WP + Write protection + 10 + 1 + + + Page11_WP + Write protection + 11 + 1 + + + Page12_WP + Write protection + 12 + 1 + + + Page13_WP + Write protection + 13 + 1 + + + Page14_WP + Write protection + 14 + 1 + + + Page15_WP + Write protection + 15 + 1 + + + Page16_WP + Write protection + 16 + 1 + + + Page17_WP + Write protection + 17 + 1 + + + Page18_WP + Write protection + 18 + 1 + + + Page19_WP + Write protection + 19 + 1 + + + Page20_WP + Write protection + 20 + 1 + + + Page21_WP + Write protection + 21 + 1 + + + Page22_WP + Write protection + 22 + 1 + + + Page23_WP + Write protection + 23 + 1 + + + Page24_WP + Write protection + 24 + 1 + + + Page25_WP + Write protection + 25 + 1 + + + Page26_WP + Write protection + 26 + 1 + + + Page27_WP + Write protection + 27 + 1 + + + Page28_WP + Write protection + 28 + 1 + + + Page29_WP + Write protection + 29 + 1 + + + Page30_WP + Write protection + 30 + 1 + + + Page31_WP + Write protection + 31 + 1 + + + + + SKR + SKR + SRAM2 Key Register + 0x24 + 0x20 + write-only + 0x00000000 + + + KEY + SRAM2 Key for software erase + 0 + 8 + + + + + + + TAMP + Tamper and backup registers + TAMP + 0x40002400 + + 0x0 + 0x400 + registers + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0xFFFF0000 + + + TAMP1E + TAMP1E + 0 + 1 + + + TAMP2E + TAMP2E + 1 + 1 + + + TAMP3E + TAMP2E + 2 + 1 + + + ITAMP3E + ITAMP3E + 18 + 1 + + + ITAMP4E + ITAMP4E + 19 + 1 + + + ITAMP5E + ITAMP5E + 20 + 1 + + + ITAMP6E + ITAMP6E + 21 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + TAMP1NOER + TAMP1NOER + 0 + 1 + + + TAMP2NOER + TAMP2NOER + 1 + 1 + + + TAMP3NOER + TAMP3NOER + 2 + 1 + + + TAMP1MSK + TAMP1MSK + 16 + 1 + + + TAMP2MSK + TAMP2MSK + 17 + 1 + + + TAMP3MSK + TAMP3MSK + 18 + 1 + + + TAMP1TRG + TAMP1TRG + 24 + 1 + + + TAMP2TRG + TAMP2TRG + 25 + 1 + + + TAMP3TRG + TAMP3TRG + 26 + 1 + + + + + FLTCR + FLTCR + TAMP filter control register + 0xC + 0x20 + read-write + 0x00000000 + + + TAMPFREQ + TAMPFREQ + 0 + 3 + + + TAMPFLT + TAMPFLT + 3 + 2 + + + TAMPPRCH + TAMPPRCH + 5 + 2 + + + TAMPPUDIS + TAMPPUDIS + 7 + 1 + + + + + IER + IER + TAMP interrupt enable register + 0x2C + 0x20 + read-write + 0x00000000 + + + TAMP1IE + TAMP1IE + 0 + 1 + + + TAMP2IE + TAMP2IE + 1 + 1 + + + TAMP3IE + TAMP3IE + 2 + 1 + + + ITAMP3IE + ITAMP3IE + 18 + 1 + + + ITAMP4IE + ITAMP4IE + 19 + 1 + + + ITAMP5IE + ITAMP5IE + 20 + 1 + + + ITAMP6IE + ITAMP6IE + 21 + 1 + + + + + SR + SR + TAMP status register + 0x30 + 0x20 + read-only + 0x00000000 + + + TAMP1F + TAMP1F + 0 + 1 + + + TAMP2F + TAMP2F + 1 + 1 + + + TAMP3F + TAMP3F + 2 + 1 + + + ITAMP3F + ITAMP3F + 18 + 1 + + + ITAMP4F + ITAMP4F + 19 + 1 + + + ITAMP5F + ITAMP5F + 20 + 1 + + + ITAMP6F + ITAMP6F + 21 + 1 + + + + + MISR + MISR + TAMP masked interrupt status register + 0x34 + 0x20 + read-only + 0x00000000 + + + TAMP1MF + TAMP1MF: + 0 + 1 + + + TAMP2MF + TAMP2MF + 1 + 1 + + + TAMP3MF + TAMP3MF + 2 + 1 + + + ITAMP3MF + ITAMP3MF + 18 + 1 + + + ITAMP4MF + ITAMP4MF + 19 + 1 + + + ITAMP5MF + ITAMP5MF + 20 + 1 + + + ITAMP6MF + ITAMP6MF + 21 + 1 + + + + + SCR + SCR + TAMP status clear register + 0x3C + 0x20 + read-write + 0x00000000 + + + CTAMP1F + CTAMP1F + 0 + 1 + + + CTAMP2F + CTAMP2F + 1 + 1 + + + CTAMP3F + CTAMP3F + 2 + 1 + + + CITAMP3F + CITAMP3F + 18 + 1 + + + CITAMP4F + CITAMP4F + 19 + 1 + + + CITAMP5F + CITAMP5F + 20 + 1 + + + CITAMP6F + CITAMP6F + 21 + 1 + + + + + BKP0R + BKP0R + TAMP backup register + 0x100 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP1R + BKP1R + TAMP backup register + 0x104 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP2R + BKP2R + TAMP backup register + 0x108 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP3R + BKP3R + TAMP backup register + 0x10C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP4R + BKP4R + TAMP backup register + 0x110 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP5R + BKP5R + TAMP backup register + 0x114 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP6R + BKP6R + TAMP backup register + 0x118 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP7R + BKP7R + TAMP backup register + 0x11C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP8R + BKP8R + TAMP backup register + 0x120 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP9R + BKP9R + TAMP backup register + 0x124 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP10R + BKP10R + TAMP backup register + 0x128 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP11R + BKP11R + TAMP backup register + 0x12C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP12R + BKP12R + TAMP backup register + 0x130 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP13R + BKP13R + TAMP backup register + 0x134 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP14R + BKP14R + TAMP backup register + 0x138 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP15R + BKP15R + TAMP backup register + 0x13C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP16R + BKP16R + TAMP backup register + 0x140 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP17R + BKP17R + TAMP backup register + 0x144 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP18R + BKP18R + TAMP backup register + 0x148 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP19R + BKP19R + TAMP backup register + 0x14C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP20R + BKP20R + TAMP backup register + 0x150 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP21R + BKP21R + TAMP backup register + 0x154 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP22R + BKP22R + TAMP backup register + 0x158 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP23R + BKP23R + TAMP backup register + 0x15C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP24R + BKP24R + TAMP backup register + 0x160 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP25R + BKP25R + TAMP backup register + 0x164 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP26R + BKP26R + TAMP backup register + 0x168 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP27R + BKP27R + TAMP backup register + 0x16C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP28R + BKP28R + TAMP backup register + 0x170 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP29R + BKP29R + TAMP backup register + 0x174 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP30R + BKP30R + TAMP backup register + 0x178 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP31R + BKP31R + TAMP backup register + 0x17C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + + + TIM1 + Advanced-timers + TIM + 0x40012C00 + + 0x0 + 0x400 + registers + + + TIM1_BRK_TIM15 + TIM1_BRK_TIM15 + 24 + + + TIM1_UP_TIM16 + TIM1_UP_TIM16 + 25 + + + TIM1_TRG_COM + TIM1_TRG_COM/ + 26 + + + TIM1_CC + TIM1 capture compare interrupt + 27 + + + + TIM1_CR1 + TIM1_CR1 + TIM1 control register 1 + 0x000 + 16 + read-write + 0x00000000 + 0x0000FFFF + + + CEN + Counter enable + + + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable + + + 1 + 1 + read-write + + + B_0x0 + UEV enabled. + 0x0 + + + B_0x1 + UEV disabled. + 0x1 + + + + + URS + Update request source + + + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt or DMA request if enabled. + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + DIR + Direction + + + 4 + 1 + read-write + + + B_0x0 + Counter used as upcounter + 0x0 + + + B_0x1 + Counter used as downcounter + 0x1 + + + + + CMS + Center-aligned mode selection + + + 5 + 2 + read-write + + + B_0x0 + Edge-aligned mode. + 0x0 + + + B_0x1 + Center-aligned mode 1. + 0x1 + + + B_0x2 + Center-aligned mode 2. + 0x2 + + + B_0x3 + Center-aligned mode 3. + 0x3 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division + + + 8 + 2 + read-write + + + B_0x0 + tless thansub>DTSless than/sub>=tless thansub>tim_ker_ckless than/sub> + 0x0 + + + B_0x1 + tless thansub>DTSless than/sub>=2*tless thansub>tim_ker_ckless than/sub> + 0x1 + + + B_0x2 + tless thansub>DTSless than/sub>=4*tless thansub>tim_ker_ckless than/sub> + 0x2 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. + 0x0 + + + B_0x1 + Remapping enabled. + 0x1 + + + + + DITHEN + Dithering enable + + + 12 + 1 + read-write + + + B_0x0 + Dithering disabled + 0x0 + + + B_0x1 + Dithering enabled + 0x1 + + + + + + + TIM1_CR2 + TIM1_CR2 + TIM1 control register 2 + 0x004 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCPC + Capture/compare preloaded control + + + 0 + 1 + read-write + + + B_0x0 + CCxE, CCxNE and OCxM bits are not preloaded + 0x0 + + + B_0x1 + CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on tim_trgi, depending on the CCUS bit). + 0x1 + + + + + CCUS + Capture/compare control update selection + + + 2 + 1 + read-write + + + B_0x0 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only + 0x0 + + + B_0x1 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on tim_trgi + 0x1 + + + + + CCDS + Capture/compare DMA selection + 3 + 1 + read-write + + + B_0x0 + CCx DMA request sent when CCx event occurs + 0x0 + + + B_0x1 + CCx DMA requests sent when update event occurs + 0x1 + + + + + MMS + MMS[2:0]: Master mode selection + + + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo). + 0x0 + + + B_0x1 + Enable - the Counter Enable signal CNT_EN is used as trigger output (tim_trgo). + 0x1 + + + B_0x2 + Update - The update event is selected as trigger output (tim_trgo). + 0x2 + + + B_0x3 + Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. + 0x3 + + + B_0x4 + Compare - tim_oc1refc signal is used as trigger output (tim_trgo) + 0x4 + + + B_0x5 + Compare - tim_oc2refc signal is used as trigger output (tim_trgo) + 0x5 + + + B_0x6 + Compare - tim_oc3refc signal is used as trigger output (tim_trgo) + 0x6 + + + B_0x7 + Compare - tim_oc4refc signal is used as trigger output (tim_trgo) + 0x7 + + + + + TI1S + tim_ti1 selection + 7 + 1 + read-write + + + B_0x0 + The tim_ti1_in[15:0] multiplexer output is connected to tim_ti1 input + 0x0 + + + B_0x1 + tim_ti1_in[15:0], tim_ti2_in[15:0] and tim_ti3_in[15:0] multiplexers outputs are XORed and connected to the tim_ti1 input + 0x1 + + + + + OIS1 + Output idle state 1 (tim_oc1 output) + + + 8 + 1 + read-write + + + B_0x0 + tim_oc1=0 (after a dead-time) when MOE=0 + 0x0 + + + B_0x1 + tim_oc1=1 (after a dead-time) when MOE=0 + 0x1 + + + + + OIS1N + Output idle state 1 (tim_oc1n output) + + + 9 + 1 + read-write + + + B_0x0 + tim_oc1n=0 after a dead-time when MOE=0 + 0x0 + + + B_0x1 + tim_oc1n=1 after a dead-time when MOE=0 + 0x1 + + + + + OIS2 + Output idle state 2 (tim_oc2 output) + + + 10 + 1 + read-write + + + OIS2N + Output idle state 2 (tim_oc2n output) + + + 11 + 1 + read-write + + + OIS3 + Output idle state 3 (tim_oc3n output) + + + 12 + 1 + read-write + + + OIS3N + Output idle state 3 (tim_oc3n output) + + + 13 + 1 + read-write + + + OIS4 + Output idle state 4 (tim_oc4 output) + + + 14 + 1 + read-write + + + OIS4N + Output idle state 4 (tim_oc4n output) + + + 15 + 1 + read-write + + + OIS5 + Output idle state 5 (tim_oc5 output) + + + 16 + 1 + read-write + + + OIS6 + Output idle state 6 (tim_oc6 output) + + + 18 + 1 + read-write + + + MMS2 + Master mode selection 2 + + + 20 + 4 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo2). + 0x0 + + + B_0x1 + Enable - the Counter Enable signal CNT_EN is used as trigger output (tim_trgo2). + 0x1 + + + B_0x2 + Update - the update event is selected as trigger output (tim_trgo2). + 0x2 + + + B_0x3 + Compare pulse - the trigger output sends a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or compare match occurs (tim_trgo2). + 0x3 + + + B_0x4 + Compare - tim_oc1refc signal is used as trigger output (tim_trgo2) + 0x4 + + + B_0x5 + Compare - tim_oc2refc signal is used as trigger output (tim_trgo2) + 0x5 + + + B_0x6 + Compare - tim_oc3refc signal is used as trigger output (tim_trgo2) + 0x6 + + + B_0x7 + Compare - tim_oc4refc signal is used as trigger output (tim_trgo2) + 0x7 + + + B_0x8 + Compare - tim_oc5refc signal is used as trigger output (tim_trgo2) + 0x8 + + + B_0x9 + Compare - tim_oc6refc signal is used as trigger output (tim_trgo2) + 0x9 + + + B_0xA + Compare Pulse - tim_oc4refc rising or falling edges generate pulses on tim_trgo2 + 0xA + + + B_0xB + Compare pulse - tim_oc6refc rising or falling edges generate pulses on tim_trgo2 + 0xB + + + B_0xC + Compare pulse - tim_oc4refc or tim_oc6refc rising edges generate pulses on tim_trgo2 + 0xC + + + B_0xD + Compare pulse - tim_oc4refc rising or tim_oc6refc falling edges generate pulses on tim_trgo2 + 0xD + + + B_0xE + Compare pulse - tim_oc5refc or tim_oc6refc rising edges generate pulses on tim_trgo2 + 0xE + + + B_0xF + Compare pulse - tim_oc5refc rising or tim_oc6refc falling edges generate pulses on tim_trgo2 + 0xF + + + + + MMS_1 + MMS[3] + 25 + 1 + read-write + + + + + TIM1_SMCR + TIM1_SMCR + TIM1 slave mode control register + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SMS + SMS[2:0]: Slave mode selection + + + 0 + 3 + read-write + + + B_0x0 + Slave mode disabled - if CEN = 1' then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Quadrature encoder mode 1, x2 mode- Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level. + 0x1 + + + B_0x2 + Quadrature encoder mode 2, x2 mode - Counter counts up/down on tim_ti2fp2 edge depending on tim_ti1fp1 level. + 0x2 + + + B_0x3 + Quadrature encoder mode 3, x4 mode - Counter counts up/down on both tim_ti1fp1 and tim_ti2fp2 edges depending on the level of the other input. + 0x3 + + + B_0x4 + Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers. + 0x4 + + + B_0x5 + Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high. + 0x5 + + + B_0x6 + Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). + 0x6 + + + B_0x7 + External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter. + 0x7 + + + + + OCCS + OCREF clear selection + + + 3 + 1 + read-write + + + B_0x0 + tim_ocref_clr_int is connected to the tim_ocref_clr input + 0x0 + + + B_0x1 + tim_ocref_clr_int is connected to tim_etrf + 0x1 + + + + + TS + TS[2:0]: Trigger selection + + + 4 + 3 + read-write + + + B_0x0 + Internal Trigger 0 (tim_itr0) + 0x0 + + + B_0x1 + Internal Trigger 1 (tim_itr1) + 0x1 + + + B_0x2 + Internal Trigger 2 (tim_itr2) + 0x2 + + + B_0x3 + Internal Trigger 3 (tim_itr3) + 0x3 + + + B_0x4 + tim_ti1 Edge Detector (tim_ti1f_ed) + 0x4 + + + B_0x5 + Filtered Timer Input 1 (tim_ti1fp1) + 0x5 + + + B_0x6 + Filtered Timer Input 2 (tim_ti2fp2) + 0x6 + + + B_0x7 + External Trigger input (tim_etrf) + 0x7 + + + + + MSM + Master/slave mode + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). + 0x1 + + + + + ETF + External trigger filter + + + 8 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + ETPS + External trigger prescaler + + + 12 + 2 + read-write + + + B_0x0 + Prescaler OFF + 0x0 + + + B_0x1 + tim_etr_in frequency divided by 2 + 0x1 + + + B_0x2 + tim_etr_in frequency divided by 4 + 0x2 + + + B_0x3 + tim_etr_in frequency divided by 8 + 0x3 + + + + + ECE + External clock enable + + + 14 + 1 + read-write + + + B_0x0 + External clock mode 2 disabled + 0x0 + + + B_0x1 + External clock mode 2 enabled. + 0x1 + + + + + ETP + External trigger polarity + + + 15 + 1 + read-write + + + B_0x0 + tim_etr_in is non-inverted, active at high level or rising edge. + 0x0 + + + B_0x1 + tim_etr_in is inverted, active at low level or falling edge. + 0x1 + + + + + SMS_1 + SMS[3] + 16 + 1 + read-write + + + TS_1 + TS[4:3] + 20 + 2 + read-write + + + SMSPE + SMS preload enable + + + 24 + 1 + read-write + + + B_0x0 + SMS[3:0] bitfield is not preloaded + 0x0 + + + B_0x1 + SMS[3:0] preload is enabled + 0x1 + + + + + SMSPS + SMS preload source + + + 25 + 1 + read-write + + + B_0x0 + The transfer is triggered by the Timer's Update event + 0x0 + + + B_0x1 + The transfer is triggered by the Index event + 0x1 + + + + + + + TIM1_DIER + TIM1_DIER + TIM1 DMA/interrupt enable register + 0x00C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled + 0x0 + + + B_0x1 + Update interrupt enabled + 0x1 + + + + + CC1IE + Capture/compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled + 0x0 + + + B_0x1 + CC1 interrupt enabled + 0x1 + + + + + CC2IE + Capture/compare 2 interrupt enable + 2 + 1 + read-write + + + B_0x0 + CC2 interrupt disabled + 0x0 + + + B_0x1 + CC2 interrupt enabled + 0x1 + + + + + CC3IE + Capture/compare 3 interrupt enable + 3 + 1 + read-write + + + B_0x0 + CC3 interrupt disabled + 0x0 + + + B_0x1 + CC3 interrupt enabled + 0x1 + + + + + CC4IE + Capture/compare 4 interrupt enable + 4 + 1 + read-write + + + B_0x0 + CC4 interrupt disabled + 0x0 + + + B_0x1 + CC4 interrupt enabled + 0x1 + + + + + COMIE + COM interrupt enable + 5 + 1 + read-write + + + B_0x0 + COM interrupt disabled + 0x0 + + + B_0x1 + COM interrupt enabled + 0x1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + read-write + + + B_0x0 + Trigger interrupt disabled + 0x0 + + + B_0x1 + Trigger interrupt enabled + 0x1 + + + + + BIE + Break interrupt enable + 7 + 1 + read-write + + + B_0x0 + Break interrupt disabled + 0x0 + + + B_0x1 + Break interrupt enabled + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled + 0x0 + + + B_0x1 + Update DMA request enabled + 0x1 + + + + + CC1DE + Capture/compare 1 DMA request enable + 9 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled + 0x0 + + + B_0x1 + CC1 DMA request enabled + 0x1 + + + + + CC2DE + Capture/compare 2 DMA request enable + 10 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled + 0x0 + + + B_0x1 + CC2 DMA request enabled + 0x1 + + + + + CC3DE + Capture/compare 3 DMA request enable + 11 + 1 + read-write + + + B_0x0 + CC3 DMA request disabled + 0x0 + + + B_0x1 + CC3 DMA request enabled + 0x1 + + + + + CC4DE + Capture/compare 4 DMA request enable + 12 + 1 + read-write + + + B_0x0 + CC4 DMA request disabled + 0x0 + + + B_0x1 + CC4 DMA request enabled + 0x1 + + + + + COMDE + COM DMA request enable + 13 + 1 + read-write + + + B_0x0 + COM DMA request disabled + 0x0 + + + B_0x1 + COM DMA request enabled + 0x1 + + + + + TDE + Trigger DMA request enable + 14 + 1 + read-write + + + B_0x0 + Trigger DMA request disabled + 0x0 + + + B_0x1 + Trigger DMA request enabled + 0x1 + + + + + IDXIE + Index interrupt enable + 20 + 1 + read-write + + + B_0x0 + Index interrupt disabled + 0x0 + + + B_0x1 + Index Change interrupt enabled + 0x1 + + + + + DIRIE + Direction change interrupt enable + 21 + 1 + read-write + + + B_0x0 + Direction Change interrupt disabled + 0x0 + + + B_0x1 + Direction Change interrupt enabled + 0x1 + + + + + IERRIE + Index error interrupt enable + 22 + 1 + read-write + + + B_0x0 + Index error interrupt disabled + 0x0 + + + B_0x1 + Index error interrupt enabled + 0x1 + + + + + TERRIE + Transition error interrupt enable + 23 + 1 + read-write + + + B_0x0 + Transition error interrupt disabled + 0x0 + + + B_0x1 + Transition error interrupt enabled + 0x1 + + + + + + + TIM1_SR + TIM1_SR + TIM1 status register + 0x010 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UIF + Update interrupt flag + + + 0 + 1 + read-write + + + B_0x0 + No update occurred. + 0x0 + + + B_0x1 + Update interrupt pending. + 0x1 + + + + + CC1IF + Capture/compare 1 interrupt flag + + + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred + 0x1 + + + + + CC2IF + Capture/compare 2 interrupt flag + + + 2 + 1 + read-write + + + CC3IF + Capture/compare 3 interrupt flag + + + 3 + 1 + read-write + + + CC4IF + Capture/compare 4 interrupt flag + + + 4 + 1 + read-write + + + COMIF + COM interrupt flag + + + 5 + 1 + read-write + + + B_0x0 + No COM event occurred. + 0x0 + + + B_0x1 + COM interrupt pending. + 0x1 + + + + + TIF + Trigger interrupt flag + + + 6 + 1 + read-write + + + B_0x0 + No trigger event occurred. + 0x0 + + + B_0x1 + Trigger interrupt pending. + 0x1 + + + + + BIF + Break interrupt flag + + + 7 + 1 + read-write + + + B_0x0 + No break event occurred. + 0x0 + + + B_0x1 + An active level has been detected on the break input. + 0x1 + + + + + B2IF + Break 2 interrupt flag + + + 8 + 1 + read-write + + + B_0x0 + No break event occurred. + 0x0 + + + B_0x1 + An active level has been detected on the break 2 input. + 0x1 + + + + + CC1OF + Capture/compare 1 overcapture flag + + + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + CC2OF + Capture/compare 2 overcapture flag + + + 10 + 1 + read-write + + + CC3OF + Capture/compare 3 overcapture flag + + + 11 + 1 + read-write + + + CC4OF + Capture/compare 4 overcapture flag + + + 12 + 1 + read-write + + + SBIF + System break interrupt flag + + + 13 + 1 + read-write + + + B_0x0 + No break event occurred. + 0x0 + + + B_0x1 + An active level has been detected on the system break input. + 0x1 + + + + + CC5IF + Compare 5 interrupt flag + + + 16 + 1 + read-write + + + CC6IF + Compare 6 interrupt flag + + + 17 + 1 + read-write + + + IDXF + Index interrupt flag + + + 20 + 1 + read-write + + + B_0x0 + No index event occurred. + 0x0 + + + B_0x1 + An index event has occurred + 0x1 + + + + + DIRF + Direction change interrupt flag + + + 21 + 1 + read-write + + + B_0x0 + No direction change + 0x0 + + + B_0x1 + Direction change + 0x1 + + + + + IERRF + Index error interrupt flag + + + 22 + 1 + read-write + + + B_0x0 + No index error has been detected. + 0x0 + + + B_0x1 + An index error has been detected + 0x1 + + + + + TERRF + Transition error interrupt flag + + + 23 + 1 + read-write + + + B_0x0 + No encoder transition error has been detected. + 0x0 + + + B_0x1 + An encoder transition error has been detected + 0x1 + + + + + + + TIM1_EGR + TIM1_EGR + TIM1 event generation register + 0x014 + 16 + write-only + 0x00000000 + 0x0000FFFF + + + UG + Update generation + + + 0 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Reinitialize the counter and generates an update of the registers. + 0x1 + + + + + CC1G + Capture/compare 1 generation + + + 1 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + CC2G + Capture/compare 2 generation + + + 2 + 1 + write-only + + + CC3G + Capture/compare 3 generation + + + 3 + 1 + write-only + + + CC4G + Capture/compare 4 generation + + + 4 + 1 + write-only + + + COMG + Capture/compare control update generation + + + 5 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + When CCPC bit is set, it allows to update CCxE, CCxNE and OCxM bits + 0x1 + + + + + TG + Trigger generation + + + 6 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + The TIF flag is set in TIMx_SR register. + 0x1 + + + + + BG + Break generation + + + 7 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A break event is generated. + 0x1 + + + + + B2G + Break 2 generation + + + 8 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A break 2 event is generated. + 0x1 + + + + + + + TIM1_CCMR1 + TIM1_CCMR1 + TIM1 capture/compare mode register 1 [alternate] + 0x018 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/compare 1 Selection + + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. + 0x3 + + + + + IC1PSC + Input capture 1 prescaler + + + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter + + + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + CC2S + Capture/compare 2 selection + + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. + 0x3 + + + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + read-write + + + IC2F + Input capture 2 filter + 12 + 4 + read-write + + + + + TIM1_CCMR1_Alternate + TIM1_CCMR1_Alternate + TIM1 capture/compare mode register 1 + TIM1_CCMR1 + 0x018 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/compare 1 selection + + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. + 0x3 + + + + + OC1FE + Output compare 1 fast enable + + + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. + 0x1 + + + + + OC1PE + Output compare 1 preload enable + + + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. + 0x1 + + + + + OC1M + OC1M[2:0]: Output compare 1 mode + + + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. + 0x2 + + + B_0x3 + Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - tim_oc1ref is forced low. + 0x4 + + + B_0x5 + Force active level - tim_oc1ref is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. + 0x6 + + + B_0x7 + PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. + 0x7 + + + + + OC1CE + Output compare 1 clear enable + 7 + 1 + read-write + + + B_0x0 + tim_oc1ref is not affected by the tim_ocref_clr_int signal + 0x0 + + + B_0x1 + tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr_int signal (tim_ocref_clr input or tim_etrf input) + 0x1 + + + + + CC2S + Capture/compare 2 selection + + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. + 0x3 + + + + + OC2FE + Output compare 2 fast enable + 10 + 1 + read-write + + + OC2PE + Output compare 2 preload enable + 11 + 1 + read-write + + + OC2M + OC2M[2:0]: Output compare 2 mode + 12 + 3 + read-write + + + OC2CE + Output compare 2 clear enable + 15 + 1 + read-write + + + OC1M_1 + OC1M[3] + 16 + 1 + read-write + + + OC2M_1 + OC2M[3] + 24 + 1 + read-write + + + + + TIM1_CCMR2 + TIM1_CCMR2 + TIM1 capture/compare mode register 2 [alternate] + 0x01C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/compare 3 selection + + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. + 0x3 + + + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + read-write + + + IC3F + Input capture 3 filter + 4 + 4 + read-write + + + CC4S + Capture/compare 4 selection + + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. + 0x3 + + + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + read-write + + + IC4F + Input capture 4 filter + 12 + 4 + read-write + + + + + TIM1_CCMR2_Alternate + TIM1_CCMR2_Alternate + TIM1 capture/compare mode register 2 + TIM1_CCMR2 + 0x01C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/compare 3 selection + + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. + 0x3 + + + + + OC3FE + Output compare 3 fast enable + 2 + 1 + read-write + + + OC3PE + Output compare 3 preload enable + 3 + 1 + read-write + + + OC3M + OC3M[2:0]: Output compare 3 mode + + + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR3 and the counter TIMx_CNT has no effect on the outputs. + 0x0 + + + B_0x1 + Set channel 3 to active level on match. + 0x1 + + + B_0x2 + Set channel 3 to inactive level on match. + 0x2 + + + B_0x3 + Toggle - tim_oc3ref toggles when TIMx_CNT=TIMx_CCR3. + 0x3 + + + B_0x4 + Force inactive level - tim_oc3ref is forced low. + 0x4 + + + B_0x5 + Force active level - tim_oc3ref is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - In upcounting, channel 3 is active as long as TIMx_CNTless thanTIMx_CCR3 else inactive. + 0x6 + + + B_0x7 + PWM mode 2 - In upcounting, channel 3 is inactive as long as TIMx_CNTless thanTIMx_CCR3 else active. + 0x7 + + + + + OC3CE + Output compare 3 clear enable + 7 + 1 + read-write + + + CC4S + Capture/compare 4 selection + + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. + 0x3 + + + + + OC4FE + Output compare 4 fast enable + 10 + 1 + read-write + + + OC4PE + Output compare 4 preload enable + 11 + 1 + read-write + + + OC4M + OC4M[2:0]: Output compare 4 mode + + + 12 + 3 + read-write + + + OC4CE + Output compare 4 clear enable + 15 + 1 + read-write + + + OC3M_1 + OC3M[3] + 16 + 1 + read-write + + + OC4M_1 + OC4M[3] + 24 + 1 + read-write + + + + + TIM1_CCER + TIM1_CCER + TIM1 capture/compare enable register + 0x020 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1E + Capture/compare 1 output enable + + + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active (see below) + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/compare 1 output polarity + + + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NE + Capture/compare 1 complementary output enable + + + 2 + 1 + read-write + + + B_0x0 + Off - tim_oc1n is not active. + 0x0 + + + B_0x1 + On - tim_oc1n signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. + 0x1 + + + + + CC1NP + Capture/compare 1 complementary output polarity + + + 3 + 1 + read-write + + + B_0x0 + tim_oc1n active high. + 0x0 + + + B_0x1 + tim_oc1n active low. + 0x1 + + + + + CC2E + Capture/compare 2 output enable + + + 4 + 1 + read-write + + + CC2P + Capture/compare 2 output polarity + + + 5 + 1 + read-write + + + CC2NE + Capture/compare 2 complementary output enable + + + 6 + 1 + read-write + + + CC2NP + Capture/compare 2 complementary output polarity + + + 7 + 1 + read-write + + + CC3E + Capture/compare 3 output enable + + + 8 + 1 + read-write + + + CC3P + Capture/compare 3 output polarity + + + 9 + 1 + read-write + + + CC3NE + Capture/compare 3 complementary output enable + + + 10 + 1 + read-write + + + CC3NP + Capture/compare 3 complementary output polarity + + + 11 + 1 + read-write + + + CC4E + Capture/compare 4 output enable + + + 12 + 1 + read-write + + + CC4P + Capture/compare 4 output polarity + + + 13 + 1 + read-write + + + CC4NE + Capture/compare 4 complementary output enable + + + 14 + 1 + read-write + + + CC4NP + Capture/compare 4 complementary output polarity + + + 15 + 1 + read-write + + + CC5E + Capture/compare 5 output enable + + + 16 + 1 + read-write + + + CC5P + Capture/compare 5 output polarity + + + 17 + 1 + read-write + + + CC6E + Capture/compare 6 output enable + + + 20 + 1 + read-write + + + CC6P + Capture/compare 6 output polarity + + + 21 + 1 + read-write + + + + + TIM1_CNT + TIM1_CNT + TIM1 counter + 0x024 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + + + 0 + 16 + read-write + + + UIFCPY + UIF copy + + + 31 + 1 + read-only + + + + + TIM1_PSC + TIM1_PSC + TIM1 prescaler + 0x028 + 16 + read-write + 0x00000000 + 0x0000FFFF + + + PSC + Prescaler value + + + 0 + 16 + read-write + + + + + TIM1_ARR + TIM1_ARR + TIM1 auto-reload register + 0x02C + 0x20 + read-write + 0x0000FFFF + 0xFFFFFFFF + + + ARR + Auto-reload value + + + 0 + 20 + read-write + + + + + TIM1_RCR + TIM1_RCR + TIM1 repetition counter register + 0x030 + 16 + read-write + 0x00000000 + 0x0000FFFF + + + REP + Repetition counter reload value + + + 0 + 16 + read-write + + + + + TIM1_CCR1 + TIM1_CCR1 + TIM1 capture/compare register 1 + 0x034 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR1 + Capture/compare 1 value + + + 0 + 20 + read-write + + + + + TIM1_CCR2 + TIM1_CCR2 + TIM1 capture/compare register 2 + 0x038 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR2 + Capture/compare 2 value + + + 0 + 20 + read-write + + + + + TIM1_CCR3 + TIM1_CCR3 + TIM1 capture/compare register 3 + 0x03C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR3 + Capture/compare value + + + 0 + 20 + read-write + + + + + TIM1_CCR4 + TIM1_CCR4 + TIM1 capture/compare register 4 + 0x040 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR4 + Capture/compare value + + + 0 + 20 + read-write + + + + + TIM1_BDTR + TIM1_BDTR + TIM1 break and dead-time register + 0x044 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DTG + Dead-time generator setup + + + 0 + 8 + read-write + + + LOCK + Lock configuration + + + 8 + 2 + read-write + + + B_0x0 + LOCK OFF - No bit is write protected. + 0x0 + + + B_0x1 + LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BK2BID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written. + 0x1 + + + B_0x2 + LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. + 0x2 + + + B_0x3 + LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. + 0x3 + + + + + OSSI + Off-state selection for idle mode + + + 10 + 1 + read-write + + + B_0x0 + When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic and which imposes a Hi-Z state). + 0x0 + + + B_0x1 + When inactive, OC/OCN outputs are first forced with their inactive level then forced to their idle level after the deadtime. + 0x1 + + + + + OSSR + Off-state selection for Run mode + + + 11 + 1 + read-write + + + B_0x0 + When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic, which forces a Hi-Z state). + 0x0 + + + B_0x1 + When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer). + 0x1 + + + + + BKE + Break enable + + + 12 + 1 + read-write + + + B_0x0 + Break function disabled + 0x0 + + + B_0x1 + Break function enabled + 0x1 + + + + + BKP + Break polarity + + + 13 + 1 + read-write + + + B_0x0 + Break input tim_brk is active low + 0x0 + + + B_0x1 + Break input tim_brk is active high + 0x1 + + + + + AOE + Automatic output enable + + + 14 + 1 + read-write + + + B_0x0 + MOE can be set only by software + 0x0 + + + B_0x1 + MOE can be set by software or automatically at the next update event (if none of the break inputs tim_brk and tim_brk2 is active) + 0x1 + + + + + MOE + Main output enable + + + 15 + 1 + read-write + + + B_0x0 + In response to a break 2 event. + 0x0 + + + B_0x1 + OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register). + 0x1 + + + + + BKF + Break filter + + + 16 + 4 + read-write + + + B_0x0 + No filter, tim_brk acts asynchronously + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + BK2F + Break 2 filter + + + 20 + 4 + read-write + + + B_0x0 + No filter, tim_brk2 acts asynchronously + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + BK2E + Break 2 enable + + + 24 + 1 + read-write + + + B_0x0 + Break2 function disabled + 0x0 + + + B_0x1 + Break2 function enabled + 0x1 + + + + + BK2P + Break 2 polarity + + + 25 + 1 + read-write + + + B_0x0 + Break input tim_brk2 is active low + 0x0 + + + B_0x1 + Break input tim_brk2 is active high + 0x1 + + + + + BKDSRM + Break disarm + + + 26 + 1 + read-write + + + B_0x0 + Break input tim_brk is armed + 0x0 + + + B_0x1 + Break input tim_brk is disarmed + 0x1 + + + + + BK2DSRM + Break2 disarm + + + 27 + 1 + read-write + + + BKBID + Break bidirectional + + + 28 + 1 + read-write + + + B_0x0 + Break input tim_brk in input mode + 0x0 + + + B_0x1 + Break input tim_brk in bidirectional mode + 0x1 + + + + + BK2BID + Break2 bidirectional + + + 29 + 1 + read-write + + + + + TIM1_CCR5 + TIM1_CCR5 + TIM1 capture/compare register 5 + 0x048 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR5 + Capture/compare 5 value + + + 0 + 20 + read-write + + + GC5C1 + Group channel 5 and channel 1 + + + 29 + 1 + read-write + + + B_0x0 + No effect of oc5ref on oc1refc + 0x0 + + + B_0x1 + oc1refc is the logical AND of oc1ref and oc5ref + 0x1 + + + + + GC5C2 + Group channel 5 and channel 2 + + + 30 + 1 + read-write + + + B_0x0 + No effect of tim_oc5ref on tim_oc2refc + 0x0 + + + B_0x1 + tim_oc2refc is the logical AND of tim_oc2ref and tim_oc5ref + 0x1 + + + + + GC5C3 + Group channel 5 and channel 3 + + + 31 + 1 + read-write + + + B_0x0 + No effect of tim_oc5ref on tim_oc3refc + 0x0 + + + B_0x1 + tim_oc3refc is the logical AND of tim_oc3ref and tim_oc5ref + 0x1 + + + + + + + TIM1_CCR6 + TIM1_CCR6 + TIM1 capture/compare register 6 + 0x04C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR6 + Capture/compare 6 value + + + 0 + 20 + read-write + + + + + TIM1_CCMR3 + TIM1_CCMR3 + TIM1 capture/compare mode register 3 + 0x050 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OC5FE + Output compare 5 fast enable + 2 + 1 + read-write + + + OC5PE + Output compare 5 preload enable + 3 + 1 + read-write + + + OC5M + OC5M[2:0]: Output compare 5 mode + 4 + 3 + read-write + + + OC5CE + Output compare 5 clear enable + 7 + 1 + read-write + + + OC6FE + Output compare 6 fast enable + 10 + 1 + read-write + + + OC6PE + Output compare 6 preload enable + 11 + 1 + read-write + + + OC6M + OC6M[2:0]: Output compare 6 mode + 12 + 3 + read-write + + + OC6CE + Output compare 6 clear enable + 15 + 1 + read-write + + + OC5M_1 + OC5M[3] + 16 + 1 + read-write + + + OC6M_1 + OC6M[3] + 24 + 1 + read-write + + + + + TIM1_DTR2 + TIM1_DTR2 + TIM1 timer deadtime register 2 + 0x054 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DTGF + Dead-time falling edge generator setup + + + 0 + 8 + read-write + + + DTAE + Deadtime asymmetric enable + + + 16 + 1 + read-write + + + B_0x0 + Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register + 0x0 + + + B_0x1 + Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits. + 0x1 + + + + + DTPE + Deadtime preload enable + + + 17 + 1 + read-write + + + B_0x0 + Deadtime value is not preloaded + 0x0 + + + B_0x1 + Deadtime value preload is enabled + 0x1 + + + + + + + TIM1_ECR + TIM1_ECR + TIM1 timer encoder control register + 0x058 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IE + Index enable + + + 0 + 1 + read-write + + + B_0x0 + Index disabled + 0x0 + + + B_0x1 + Index enabled + 0x1 + + + + + IDIR + Index direction + + + 1 + 2 + read-write + + + B_0x0 + Index resets the counter whatever the direction + 0x0 + + + B_0x1 + Index resets the counter when up-counting only + 0x1 + + + B_0x2 + Index resets the counter when down-counting only + 0x2 + + + + + FIDX + First index + + + 5 + 1 + read-write + + + B_0x0 + Index is always active + 0x0 + + + B_0x1 + the first Index only resets the counter + 0x1 + + + + + IPOS + Index positioning + + + 6 + 2 + read-write + + + B_0x0 + Index resets the counter when AB = 00 + 0x0 + + + B_0x1 + Index resets the counter when AB = 01 + 0x1 + + + B_0x2 + Index resets the counter when AB = 10 + 0x2 + + + B_0x3 + Index resets the counter when AB = 11 + 0x3 + + + + + PW + Pulse width + + + 16 + 8 + read-write + + + PWPRSC + Pulse width prescaler + + + 24 + 3 + read-write + + + + + TIM1_TISEL + TIM1_TISEL + TIM1 timer input selection register + 0x05C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + Selects tim_ti1[15:0] input + + + 0 + 4 + read-write + + + B_0x0 + tim_ti1_in0: TIMx_CH1 + 0x0 + + + B_0x1 + tim_ti1_in1 + 0x1 + + + B_0xF + tim_ti1_in15 + 0xF + + + + + TI2SEL + Selects tim_ti2[15:0] input + + + 8 + 4 + read-write + + + B_0x0 + tim_ti2_in0: TIMx_CH2 + 0x0 + + + B_0x1 + tim_ti2_in1 + 0x1 + + + B_0xF + tim_ti2_in15 + 0xF + + + + + TI3SEL + Selects tim_ti3[15:0] input + + + 16 + 4 + read-write + + + B_0x0 + tim_ti3_in0: TIMx_CH2 + 0x0 + + + B_0x1 + tim_ti3_in1 + 0x1 + + + B_0xF + tim_ti3_in15 + 0xF + + + + + TI4SEL + Selects tim_ti4[15:0] input + + + 24 + 4 + read-write + + + B_0x0 + tim_ti4_in0: TIMx_CH4 + 0x0 + + + B_0x1 + tim_ti4_in1 + 0x1 + + + B_0xF + tim_ti4_in15 + 0xF + + + + + + + TIM1_AF1 + TIM1_AF1 + TIM1 alternate function option register 1 + 0x060 + 0x20 + read-write + 0x00000001 + 0xFFFFFFFF + + + BKINE + TIMx_BKIN input enable + + + 0 + 1 + read-write + + + B_0x0 + TIMx_BKIN input disabled + 0x0 + + + B_0x1 + TIMx_BKIN input enabled + 0x1 + + + + + BKCMP1E + tim_brk_cmp1 enable + + + 1 + 1 + read-write + + + B_0x0 + tim_brk_cmp1 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp1 input enabled + 0x1 + + + + + BKCMP2E + tim_brk_cmp2 enable + + + 2 + 1 + read-write + + + B_0x0 + tim_brk_cmp2 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp2 input enabled + 0x1 + + + + + BKCMP3E + tim_brk_cmp3 enable + + + 3 + 1 + read-write + + + B_0x0 + tim_brk_cmp3 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp3 input enabled + 0x1 + + + + + BKCMP4E + tim_brk_cmp4 enable + + + 4 + 1 + read-write + + + B_0x0 + tim_brk_cmp4 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp4 input enabled + 0x1 + + + + + BKCMP5E + tim_brk_cmp5 enable + + + 5 + 1 + read-write + + + B_0x0 + tim_brk_cmp5 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp5 input enabled + 0x1 + + + + + BKCMP6E + tim_brk_cmp6 enable + + + 6 + 1 + read-write + + + B_0x0 + tim_brk_cmp6 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp6 input enabled + 0x1 + + + + + BKCMP7E + tim_brk_cmp7 enable + + + 7 + 1 + read-write + + + B_0x0 + tim_brk_cmp7 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp7 input enabled + 0x1 + + + + + BKCMP8E + tim_brk_cmp8 enable + + + 8 + 1 + read-write + + + B_0x0 + tim_brk_cmp8 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp8 input enabled + 0x1 + + + + + BKINP + TIMx_BKIN input polarity + + + 9 + 1 + read-write + + + B_0x0 + TIMx_BKIN input polarity is not inverted (active low if BKP = 0, active high if BKP = 1) + 0x0 + + + B_0x1 + TIMx_BKIN input polarity is inverted (active high if BKP = 0, active low if BKP = 1) + 0x1 + + + + + BKCMP1P + tim_brk_cmp1 input polarity + + + 10 + 1 + read-write + + + B_0x0 + tim_brk_cmp1 input polarity is not inverted (active low if BKP = 0, active high if BKP = 1) + 0x0 + + + B_0x1 + tim_brk_cmp1 input polarity is inverted (active high if BKP = 0, active low if BKP = 1) + 0x1 + + + + + BKCMP2P + tim_brk_cmp2 input polarity + + + 11 + 1 + read-write + + + B_0x0 + tim_brk_cmp2 input polarity is not inverted (active low if BKP = 0, active high if BKP = 1) + 0x0 + + + B_0x1 + tim_brk_cmp2 input polarity is inverted (active high if BKP = 0, active low if BKP = 1) + 0x1 + + + + + BKCMP3P + tim_brk_cmp3 input polarity + + + 12 + 1 + read-write + + + B_0x0 + tim_brk_cmp3 input polarity is not inverted (active low if BKP = 0, active high if BKP = 1) + 0x0 + + + B_0x1 + tim_brk_cmp3 input polarity is inverted (active high if BKP = 0, active low if BKP = 1) + 0x1 + + + + + BKCMP4P + tim_brk_cmp4 input polarity + + + 13 + 1 + read-write + + + B_0x0 + tim_brk_cmp4 input polarity is not inverted (active low if BKP = 0, active high if BKP = 1) + 0x0 + + + B_0x1 + tim_brk_cmp4 input polarity is inverted (active high if BKP = 0, active low if BKP = 1) + 0x1 + + + + + ETRSEL + etr_in source selection + + + 14 + 4 + read-write + + + B_0x0 + tim_etr0: TIMx_ETR input + 0x0 + + + B_0x1 + tim_etr1 + 0x1 + + + B_0xF + tim_etr15 + 0xF + + + + + + + TIM1_AF2 + TIM1_AF2 + TIM1 alternate function register 2 + 0x064 + 0x20 + read-write + 0x00000001 + 0xFFFFFFFF + + + BK2INE + TIMx_BKIN2 input enable + + + 0 + 1 + read-write + + + B_0x0 + TIMx_BKIN2 input disabled + 0x0 + + + B_0x1 + TIMx_BKIN2 input enabled + 0x1 + + + + + BK2CMP1E + tim_brk2_cmp1 enable + + + 1 + 1 + read-write + + + B_0x0 + tim_brk2_cmp1 input disabled + 0x0 + + + B_0x1 + tim_brk2_cmp1 input enabled + 0x1 + + + + + BK2CMP2E + tim_brk2_cmp2 enable + + + 2 + 1 + read-write + + + B_0x0 + tim_brk2_cmp2 input disabled + 0x0 + + + B_0x1 + tim_brk2_cmp2 input enabled + 0x1 + + + + + BK2CMP3E + tim_brk2_cmp3 enable + + + 3 + 1 + read-write + + + B_0x0 + tim_brk2_cmp3 input disabled + 0x0 + + + B_0x1 + tim_brk2_cmp3 input enabled + 0x1 + + + + + BK2CMP4E + tim_brk2_cmp4 enable + + + 4 + 1 + read-write + + + B_0x0 + tim_brk2_cmp4 input disabled + 0x0 + + + B_0x1 + tim_brk2_cmp4 input enabled + 0x1 + + + + + BK2CMP5E + tim_brk2_cmp5 enable + + + 5 + 1 + read-write + + + B_0x0 + tim_brk2_cmp5 input disabled + 0x0 + + + B_0x1 + tim_brk2_cmp5 input enabled + 0x1 + + + + + BK2CMP6E + tim_brk2_cmp6 enable + + + 6 + 1 + read-write + + + B_0x0 + tim_brk2_cmp6 input disabled + 0x0 + + + B_0x1 + tim_brk2_cmp6 input enabled + 0x1 + + + + + BK2CMP7E + tim_brk2_cmp7 enable + + + 7 + 1 + read-write + + + B_0x0 + tim_brk2_cmp7 input disabled + 0x0 + + + B_0x1 + tim_brk2_cmp7 input enabled + 0x1 + + + + + BK2CMP8E + tim_brk2_cmp8 enable + + + 8 + 1 + read-write + + + B_0x0 + tim_brk2_cmp8 input disabled + 0x0 + + + B_0x1 + tim_brk2_cmp8 input enabled + 0x1 + + + + + BK2INP + TIMx_BKIN2 input polarity + + + 9 + 1 + read-write + + + B_0x0 + TIMx_BKIN2 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1) + 0x0 + + + B_0x1 + TIMx_BKIN2 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1) + 0x1 + + + + + BK2CMP1P + tim_brk2_cmp1 input polarity + + + 10 + 1 + read-write + + + B_0x0 + tim_brk2_cmp1 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1) + 0x0 + + + B_0x1 + tim_brk2_cmp1 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1) + 0x1 + + + + + BK2CMP2P + tim_brk2_cmp2 input polarity + + + 11 + 1 + read-write + + + B_0x0 + tim_brk2_cmp2 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1) + 0x0 + + + B_0x1 + tim_brk2_cmp2 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1) + 0x1 + + + + + BK2CMP3P + tim_brk2_cmp3 input polarity + + + 12 + 1 + read-write + + + B_0x0 + tim_brk2_cmp3 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1) + 0x0 + + + B_0x1 + tim_brk2_cmp3 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1) + 0x1 + + + + + BK2CMP4P + tim_brk2_cmp4 input polarity + + + 13 + 1 + read-write + + + B_0x0 + tim_brk2_cmp4 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1) + 0x0 + + + B_0x1 + tim_brk2_cmp4 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1) + 0x1 + + + + + OCRSEL + ocref_clr source selection + + + 16 + 3 + read-write + + + B_0x0 + tim_ocref_clr0 + 0x0 + + + B_0x1 + tim_ocref_clr1 + 0x1 + + + B_0x7 + tim_ocref_clr7 + 0x7 + + + + + + + TIM1_DCR + TIM1_DCR + TIM1 DMA control register + 0x3DC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DBA + DMA base address + + + 0 + 5 + read-write + + + B_0x0 + TIMx_CR1 + 0x0 + + + B_0x1 + TIMx_CR2 + 0x1 + + + B_0x2 + TIMx_SMCR + 0x2 + + + + + DBL + DMA burst length + + + 8 + 5 + read-write + + + B_0x0 + 1 transfer + 0x0 + + + B_0x1 + 2 transfers + 0x1 + + + B_0x2 + 3 transfers + 0x2 + + + B_0x1A + 26 transfers + 0x1A + + + + + + + TIM1_DMAR + TIM1_DMAR + TIM1 DMA address for full transfer + 0x3E0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DMAB + DMA register for burst accesses + + + 0 + 32 + read-write + + + + + + + TIM2 + Advanced-timers + TIM + 0x40000000 + + 0x0 + 0x400 + registers + + + TIM2 + TIM2 + 28 + + + + TIM2_CR1 + TIM2_CR1 + TIM2 control register 1 + 0x000 + 16 + read-write + 0x00000000 + 0x0000FFFF + + + CEN + Counter enable + + + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable + + + 1 + 1 + read-write + + + B_0x0 + UEV enabled. + 0x0 + + + B_0x1 + UEV disabled. + 0x1 + + + + + URS + Update request source + + + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt or DMA request if enabled. + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + DIR + Direction + + + 4 + 1 + read-write + + + B_0x0 + Counter used as upcounter + 0x0 + + + B_0x1 + Counter used as downcounter + 0x1 + + + + + CMS + Center-aligned mode selection + + + 5 + 2 + read-write + + + B_0x0 + Edge-aligned mode. + 0x0 + + + B_0x1 + Center-aligned mode 1. + 0x1 + + + B_0x2 + Center-aligned mode 2. + 0x2 + + + B_0x3 + Center-aligned mode 3. + 0x3 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division + + + 8 + 2 + read-write + + + B_0x0 + tless thansub>DTSless than/sub> = tless thansub>tim_ker_ckless than/sub> + 0x0 + + + B_0x1 + tless thansub>DTSless than/sub> = 2 tless thansub>tim_ker_ckless than/sub> + 0x1 + + + B_0x2 + tless thansub>DTSless than/sub> = 4 tless thansub>tim_ker_ckless than/sub> + 0x2 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. + 0x0 + + + B_0x1 + Remapping enabled. + 0x1 + + + + + DITHEN + Dithering Enable + + + 12 + 1 + read-write + + + B_0x0 + Dithering disabled + 0x0 + + + B_0x1 + Dithering enabled + 0x1 + + + + + + + TIM2_CR2 + TIM2_CR2 + TIM2 control register 2 + 0x004 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCDS + Capture/compare DMA selection + 3 + 1 + read-write + + + B_0x0 + CCx DMA request sent when CCx event occurs + 0x0 + + + B_0x1 + CCx DMA requests sent when update event occurs + 0x1 + + + + + MMS + MMS[0]: Master mode selection + + + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo). + 0x0 + + + B_0x1 + Enable - the Counter enable signal, CNT_EN, is used as trigger output (tim_trgo). + 0x1 + + + B_0x2 + Update - The update event is selected as trigger output (tim_trgo). + 0x2 + + + B_0x3 + Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred (tim_trgo). + 0x3 + + + B_0x4 + Compare - tim_oc1refc signal is used as trigger output (tim_trgo) + 0x4 + + + B_0x5 + Compare - tim_oc2refc signal is used as trigger output (tim_trgo) + 0x5 + + + B_0x6 + Compare - tim_oc3refc signal is used as trigger output (tim_trgo) + 0x6 + + + B_0x7 + Compare - tim_oc4refc signal is used as trigger output (tim_trgo) + 0x7 + + + + + TI1S + tim_ti1 selection + 7 + 1 + read-write + + + B_0x0 + The tim_ti1_in[15:0] multiplexer output is to tim_ti1 input + 0x0 + + + B_0x1 + The tim_ti1_in[15:0], tim_ti2_in[15:0] and tim_ti3_in[15:0] multiplexers outputs are XORed and connected to the tim_ti1 input. + 0x1 + + + + + MMS_1 + MMS[3] + 25 + 1 + read-write + + + + + TIM2_SMCR + TIM2_SMCR + TIM2 slave mode control register + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SMS + SMS[0]: Slave mode selection + + + 0 + 3 + read-write + + + B_0x0 + Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level. + 0x1 + + + B_0x2 + Encoder mode 2 - Counter counts up/down on tim_ti2fp2 edge depending on tim_ti1fp1 level. + 0x2 + + + B_0x3 + Encoder mode 3 - Counter counts up/down on both tim_ti1fp1 and tim_ti2fp2 edges depending on the level of the other input. + 0x3 + + + B_0x4 + Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers. + 0x4 + + + B_0x5 + Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high. + 0x5 + + + B_0x6 + Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). + 0x6 + + + B_0x7 + External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter. + 0x7 + + + + + OCCS + OCREF clear selection + + + 3 + 1 + read-write + + + B_0x0 + tim_ocref_clr_int is connected to the tim_ocref_clr input + 0x0 + + + B_0x1 + tim_ocref_clr_int is connected to tim_etrf + 0x1 + + + + + TS + TS[0]: Trigger selection + + + 4 + 3 + read-write + + + B_0x0 + Internal trigger 0 (tim_itr0) + 0x0 + + + B_0x1 + Internal trigger 1 (tim_itr1) + 0x1 + + + B_0x2 + Internal trigger 2 (tim_itr2) + 0x2 + + + B_0x3 + Internal trigger 3 (tim_itr3) + 0x3 + + + B_0x4 + tim_ti1 edge detector (tim_ti1f_ed) + 0x4 + + + B_0x5 + Filtered timer input 1 (tim_ti1fp1) + 0x5 + + + B_0x6 + Filtered timer input 2 (tim_ti2fp2) + 0x6 + + + B_0x7 + External trigger input (tim_etrf) + 0x7 + + + + + MSM + Master/Slave mode + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). + 0x1 + + + + + ETF + External trigger filter + + + 8 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + ETPS + External trigger prescaler + + + 12 + 2 + read-write + + + B_0x0 + Prescaler OFF + 0x0 + + + B_0x1 + tim_etrp frequency divided by 2 + 0x1 + + + B_0x2 + tim_etrp frequency divided by 4 + 0x2 + + + B_0x3 + tim_etrp frequency divided by 8 + 0x3 + + + + + ECE + External clock enable + + + 14 + 1 + read-write + + + B_0x0 + External clock mode 2 disabled + 0x0 + + + B_0x1 + External clock mode 2 enabled. + 0x1 + + + + + ETP + External trigger polarity + + + 15 + 1 + read-write + + + B_0x0 + tim_etr_in is non-inverted, active at high level or rising edge + 0x0 + + + B_0x1 + tim_etr_in is inverted, active at low level or falling edge + 0x1 + + + + + SMS_1 + SMS[3] + 16 + 1 + read-write + + + TS_1 + TS[4:3] + 20 + 2 + read-write + + + SMSPE + SMS preload enable + + + 24 + 1 + read-write + + + B_0x0 + SMS[3:0] bitfield is not preloaded + 0x0 + + + B_0x1 + SMS[3:0] preload is enabled + 0x1 + + + + + SMSPS + SMS preload source + + + 25 + 1 + read-write + + + B_0x0 + The transfer is triggered by the Timer's Update event + 0x0 + + + B_0x1 + The transfer is triggered by the Index event + 0x1 + + + + + + + TIM2_DIER + TIM2_DIER + TIM2 DMA/Interrupt enable register + 0x00C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled. + 0x0 + + + B_0x1 + Update interrupt enabled. + 0x1 + + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled. + 0x0 + + + B_0x1 + CC1 interrupt enabled. + 0x1 + + + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + read-write + + + B_0x0 + CC2 interrupt disabled. + 0x0 + + + B_0x1 + CC2 interrupt enabled. + 0x1 + + + + + CC3IE + Capture/Compare 3 interrupt enable + 3 + 1 + read-write + + + B_0x0 + CC3 interrupt disabled. + 0x0 + + + B_0x1 + CC3 interrupt enabled. + 0x1 + + + + + CC4IE + Capture/Compare 4 interrupt enable + 4 + 1 + read-write + + + B_0x0 + CC4 interrupt disabled. + 0x0 + + + B_0x1 + CC4 interrupt enabled. + 0x1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + read-write + + + B_0x0 + Trigger interrupt disabled. + 0x0 + + + B_0x1 + Trigger interrupt enabled. + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled. + 0x0 + + + B_0x1 + Update DMA request enabled. + 0x1 + + + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled. + 0x0 + + + B_0x1 + CC1 DMA request enabled. + 0x1 + + + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled. + 0x0 + + + B_0x1 + CC2 DMA request enabled. + 0x1 + + + + + CC3DE + Capture/Compare 3 DMA request enable + 11 + 1 + read-write + + + B_0x0 + CC3 DMA request disabled. + 0x0 + + + B_0x1 + CC3 DMA request enabled. + 0x1 + + + + + CC4DE + Capture/Compare 4 DMA request enable + 12 + 1 + read-write + + + B_0x0 + CC4 DMA request disabled. + 0x0 + + + B_0x1 + CC4 DMA request enabled. + 0x1 + + + + + TDE + Trigger DMA request enable + 14 + 1 + read-write + + + B_0x0 + Trigger DMA request disabled. + 0x0 + + + B_0x1 + Trigger DMA request enabled. + 0x1 + + + + + IDXIE + Index interrupt enable + 20 + 1 + read-write + + + B_0x0 + Index interrupt disabled + 0x0 + + + B_0x1 + Index interrupt enabled + 0x1 + + + + + DIRIE + Direction change interrupt enable + 21 + 1 + read-write + + + B_0x0 + Direction change interrupt disabled + 0x0 + + + B_0x1 + Direction change interrupt enabled + 0x1 + + + + + IERRIE + Index error interrupt enable + 22 + 1 + read-write + + + B_0x0 + Index error interrupt disabled + 0x0 + + + B_0x1 + Index error interrupt enabled + 0x1 + + + + + TERRIE + Transition error interrupt enable + 23 + 1 + read-write + + + B_0x0 + Transition error interrupt disabled + 0x0 + + + B_0x1 + Transition error interrupt enabled + 0x1 + + + + + + + TIM2_SR + TIM2_SR + TIM2 status register + 0x010 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UIF + Update interrupt flag + + + 0 + 1 + read-write + + + B_0x0 + No update occurred + 0x0 + + + B_0x1 + Update interrupt pending. + 0x1 + + + + + CC1IF + Capture/compare 1 interrupt flag + + + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred + 0x1 + + + + + CC2IF + Capture/Compare 2 interrupt flag + + + 2 + 1 + read-write + + + CC3IF + Capture/Compare 3 interrupt flag + + + 3 + 1 + read-write + + + CC4IF + Capture/Compare 4 interrupt flag + + + 4 + 1 + read-write + + + TIF + Trigger interrupt flag + + + 6 + 1 + read-write + + + B_0x0 + No trigger event occurred. + 0x0 + + + B_0x1 + Trigger interrupt pending. + 0x1 + + + + + CC1OF + Capture/Compare 1 overcapture flag + + + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + CC2OF + Capture/compare 2 overcapture flag + + + 10 + 1 + read-write + + + CC3OF + Capture/Compare 3 overcapture flag + + + 11 + 1 + read-write + + + CC4OF + Capture/Compare 4 overcapture flag + + + 12 + 1 + read-write + + + IDXF + Index interrupt flag + + + 20 + 1 + read-write + + + B_0x0 + No index event occurred. + 0x0 + + + B_0x1 + An index event has occurred + 0x1 + + + + + DIRF + Direction change interrupt flag + + + 21 + 1 + read-write + + + B_0x0 + No direction change + 0x0 + + + B_0x1 + Direction change + 0x1 + + + + + IERRF + Index error interrupt flag + + + 22 + 1 + read-write + + + B_0x0 + No index error has been detected. + 0x0 + + + B_0x1 + An index error has been detected + 0x1 + + + + + TERRF + Transition error interrupt flag + + + 23 + 1 + read-write + + + B_0x0 + No encoder transition error has been detected. + 0x0 + + + B_0x1 + An encoder transition error has been detected + 0x1 + + + + + + + TIM2_EGR + TIM2_EGR + TIM2 event generation register + 0x014 + 16 + write-only + 0x00000000 + 0x0000FFFF + + + UG + Update generation + + + 0 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Re-initialize the counter and generates an update of the registers. + 0x1 + + + + + CC1G + Capture/compare 1 generation + + + 1 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + CC2G + Capture/compare 2 generation + + + 2 + 1 + write-only + + + CC3G + Capture/compare 3 generation + + + 3 + 1 + write-only + + + CC4G + Capture/compare 4 generation + + + 4 + 1 + write-only + + + TG + Trigger generation + + + 6 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + The TIF flag is set in TIMx_SR register. + 0x1 + + + + + + + TIM2_CCMR1 + TIM2_CCMR1 + TIM2 capture/compare mode register 1 [alternate] + 0x018 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. + 0x3 + + + + + IC1PSC + Input capture 1 prescaler + + + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter + + + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + CC2S + Capture/compare 2 selection + + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output. + 0x0 + + + B_0x1 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2. + 0x1 + + + B_0x2 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1. + 0x2 + + + B_0x3 + CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. + 0x3 + + + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + read-write + + + IC2F + Input capture 2 filter + 12 + 4 + read-write + + + + + TIM2_CCMR1_Alternate + TIM2_CCMR1_Alternate + TIM2 capture/compare mode register 1 + TIM2_CCMR1 + 0x018 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output. + 0x0 + + + B_0x1 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1. + 0x1 + + + B_0x2 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2. + 0x2 + + + B_0x3 + CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. + 0x3 + + + + + OC1FE + Output compare 1 fast enable + + + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. + 0x1 + + + + + OC1PE + Output compare 1 preload enable + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. + 0x1 + + + + + OC1M + OC1M[2:0]: Output compare 1 mode + + + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. + 0x2 + + + B_0x3 + Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - tim_oc1ref is forced low. + 0x4 + + + B_0x5 + Force active level - tim_oc1ref is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. + 0x6 + + + B_0x7 + PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. + 0x7 + + + + + OC1CE + Output compare 1 clear enable + 7 + 1 + read-write + + + B_0x0 + tim_oc1ref is not affected by the tim_ocref_clr_int input + 0x0 + + + B_0x1 + tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr_int input + 0x1 + + + + + CC2S + Capture/Compare 2 selection + + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. + 0x3 + + + + + OC2FE + Output compare 2 fast enable + 10 + 1 + read-write + + + OC2PE + Output compare 2 preload enable + 11 + 1 + read-write + + + OC2M + OC2M[2:0]: Output compare 2 mode + + + 12 + 3 + read-write + + + OC2CE + Output compare 2 clear enable + 15 + 1 + read-write + + + OC1M_1 + OC1M[3] + 16 + 1 + read-write + + + OC2M_1 + OC2M[3] + 24 + 1 + read-write + + + + + TIM2_CCMR2 + TIM2_CCMR2 + TIM2 capture/compare mode register 2 [alternate] + 0x01C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection + + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. + 0x3 + + + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + read-write + + + IC3F + Input capture 3 filter + 4 + 4 + read-write + + + CC4S + Capture/Compare 4 selection + + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. + 0x3 + + + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + read-write + + + IC4F + Input capture 4 filter + 12 + 4 + read-write + + + + + TIM2_CCMR2_Alternate + TIM2_CCMR2_Alternate + TIM2 capture/compare mode register 2 + TIM2_CCMR2 + 0x01C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection + + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. + 0x3 + + + + + OC3FE + Output compare 3 fast enable + 2 + 1 + read-write + + + OC3PE + Output compare 3 preload enable + 3 + 1 + read-write + + + OC3M + OC3M[2:0]: Output compare 3 mode + + + 4 + 3 + read-write + + + OC3CE + Output compare 3 clear enable + 7 + 1 + read-write + + + CC4S + Capture/Compare 4 selection + + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. + 0x3 + + + + + OC4FE + Output compare 4 fast enable + 10 + 1 + read-write + + + OC4PE + Output compare 4 preload enable + 11 + 1 + read-write + + + OC4M + OC4M[2:0]: Output compare 4 mode + + + 12 + 3 + read-write + + + OC4CE + Output compare 4 clear enable + 15 + 1 + read-write + + + OC3M_1 + OC3M[3] + 16 + 1 + read-write + + + OC4M_1 + OC4M[3] + 24 + 1 + read-write + + + + + TIM2_CCER + TIM2_CCER + TIM2 capture/compare enable register + 0x020 + 16 + read-write + 0x00000000 + 0x0000FFFF + + + CC1E + Capture/Compare 1 output enable. + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/Compare 1 output Polarity. + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NP + Capture/Compare 1 output Polarity. + 3 + 1 + read-write + + + CC2E + Capture/Compare 2 output enable. + 4 + 1 + read-write + + + CC2P + Capture/Compare 2 output Polarity. + 5 + 1 + read-write + + + CC2NP + Capture/Compare 2 output Polarity. + 7 + 1 + read-write + + + CC3E + Capture/Compare 3 output enable. + 8 + 1 + read-write + + + CC3P + Capture/Compare 3 output Polarity. + 9 + 1 + read-write + + + CC3NP + Capture/Compare 3 output Polarity. + 11 + 1 + read-write + + + CC4E + Capture/Compare 4 output enable. + 12 + 1 + read-write + + + CC4P + Capture/Compare 4 output Polarity. + 13 + 1 + read-write + + + CC4NP + Capture/Compare 4 output Polarity. + 15 + 1 + read-write + + + + + TIM2_CNT + TIM2_CNT + TIM2 counter + 0x024 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Least significant part of counter value + + + 0 + 31 + read-write + + + UIFCPY_CNT + Value depends on IUFREMAP in TIMx_CR1. + 31 + 1 + read-write + + + + + TIM2_PSC + TIM2_PSC + TIM2 prescaler + 0x028 + 16 + read-write + 0x00000000 + 0x0000FFFF + + + PSC + Prescaler value + + + 0 + 16 + read-write + + + + + TIM2_ARR + TIM2_ARR + TIM2 auto-reload register + 0x02C + 0x20 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + ARR + Auto-reload value + + + 0 + 32 + read-write + + + + + TIM2_CCR1 + TIM2_CCR1 + TIM2 capture/compare register 1 + 0x034 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR1 + Capture/compare 1 value + + + 0 + 32 + read-write + + + + + TIM2_CCR2 + TIM2_CCR2 + TIM2 capture/compare register 2 + 0x038 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR2 + Capture/compare 2 value + + + 0 + 32 + read-write + + + + + TIM2_CCR3 + TIM2_CCR3 + TIM2 capture/compare register 3 + 0x03C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR3 + Capture/compare 3 value + + + 0 + 32 + read-write + + + + + TIM2_CCR4 + TIM2_CCR4 + TIM2 capture/compare register 4 + 0x040 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR4 + Capture/compare 4 value + + + 0 + 32 + read-write + + + + + TIM2_ECR + TIM2_ECR + TIM2 timer encoder control register + 0x058 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IE + Index enable + + + 0 + 1 + read-write + + + B_0x0 + Index disabled + 0x0 + + + B_0x1 + Index enabled + 0x1 + + + + + IDIR + Index direction + + + 1 + 2 + read-write + + + B_0x0 + Index resets the counter whatever the direction + 0x0 + + + B_0x1 + Index resets the counter when up-counting only + 0x1 + + + B_0x2 + Index resets the counter when down-counting only + 0x2 + + + + + FIDX + First index + + + 5 + 1 + read-write + + + B_0x0 + Index is always active + 0x0 + + + B_0x1 + the first Index only resets the counter + 0x1 + + + + + IPOS + Index positioning + + + 6 + 2 + read-write + + + B_0x0 + Index resets the counter when AB = 00 + 0x0 + + + B_0x1 + Index resets the counter when AB = 01 + 0x1 + + + B_0x2 + Index resets the counter when AB = 10 + 0x2 + + + B_0x3 + Index resets the counter when AB = 11 + 0x3 + + + + + PW + Pulse width + + + 16 + 8 + read-write + + + PWPRSC + Pulse width prescaler + + + 24 + 3 + read-write + + + + + TIM2_TISEL + TIM2_TISEL + TIM2 timer input selection register + 0x05C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + Selects tim_ti1[15:0] input + + + 0 + 4 + read-write + + + B_0x0 + tim_ti1_in0: TIMx_CH1 + 0x0 + + + B_0x1 + tim_ti1_in1 + 0x1 + + + B_0xF + tim_ti1_in15 + 0xF + + + + + TI2SEL + Selects tim_ti2[15:0] input + + + 8 + 4 + read-write + + + B_0x0 + tim_ti2_in0: TIMx_CH2 + 0x0 + + + B_0x1 + tim_ti2_in1 + 0x1 + + + B_0xF + tim_ti2_in15 + 0xF + + + + + TI3SEL + Selects tim_ti3[15:0] input + + + 16 + 4 + read-write + + + B_0x0 + tim_ti3_in0: TIMx_CH3 + 0x0 + + + B_0x1 + tim_ti3_in1 + 0x1 + + + B_0xF + tim_ti3_in15 + 0xF + + + + + TI4SEL + Selects tim_ti4[15:0] input + + + 24 + 4 + read-write + + + B_0x0 + tim_ti4_in0: TIMx_CH4 + 0x0 + + + B_0x1 + tim_ti4_in1 + 0x1 + + + B_0xF + tim_ti4_in15 + 0xF + + + + + + + TIM2_AF1 + TIM2_AF1 + TIM2 alternate function register 1 + 0x060 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ETRSEL + etr_in source selection + + + 14 + 4 + read-write + + + B_0x0 + tim_etr0: TIMx_ETR input + 0x0 + + + B_0x1 + tim_etr1 + 0x1 + + + B_0xF + tim_etr15 + 0xF + + + + + + + TIM2_AF2 + TIM2_AF2 + TIM2 alternate function register 2 + 0x064 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OCRSEL + ocref_clr source selection + + + 16 + 3 + read-write + + + B_0x0 + tim_ocref_clr0 + 0x0 + + + B_0x1 + tim_ocref_clr1 + 0x1 + + + B_0x7 + tim_ocref_clr7 + 0x7 + + + + + + + TIM2_DCR + TIM2_DCR + TIM2 DMA control register + 0x3DC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DBA + DMA base address + + + 0 + 5 + read-write + + + B_0x0 + TIMx_CR1, + 0x0 + + + B_0x1 + TIMx_CR2, + 0x1 + + + B_0x2 + TIMx_SMCR, + 0x2 + + + + + DBL + DMA burst length + + + 8 + 5 + read-write + + + B_0x0 + 1 transfer + 0x0 + + + B_0x1 + 2 transfers + 0x1 + + + B_0x2 + 3 transfers + 0x2 + + + B_0x1A + 26 transfers + 0x1A + + + + + + + TIM2_DMAR + TIM2_DMAR + TIM2 DMA address for full transfer + 0x3E0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DMAB + DMA register for burst accesses + + + 0 + 32 + read-write + + + + + + + TIM3 + Advanced-timers + TIM + 0x40000400 + + 0x0 + 0x400 + registers + + + TIM3 + TIM3 + 29 + + + + TIM3_CR1 + TIM3_CR1 + TIM3 control register 1 + 0x000 + 16 + read-write + 0x00000000 + 0x0000FFFF + + + CEN + Counter enable + + + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable + + + 1 + 1 + read-write + + + B_0x0 + UEV enabled. + 0x0 + + + B_0x1 + UEV disabled. + 0x1 + + + + + URS + Update request source + + + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt or DMA request if enabled. + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + DIR + Direction + + + 4 + 1 + read-write + + + B_0x0 + Counter used as upcounter + 0x0 + + + B_0x1 + Counter used as downcounter + 0x1 + + + + + CMS + Center-aligned mode selection + + + 5 + 2 + read-write + + + B_0x0 + Edge-aligned mode. + 0x0 + + + B_0x1 + Center-aligned mode 1. + 0x1 + + + B_0x2 + Center-aligned mode 2. + 0x2 + + + B_0x3 + Center-aligned mode 3. + 0x3 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division + + + 8 + 2 + read-write + + + B_0x0 + tless thansub>DTSless than/sub> = tless thansub>tim_ker_ckless than/sub> + 0x0 + + + B_0x1 + tless thansub>DTSless than/sub> = 2 tless thansub>tim_ker_ckless than/sub> + 0x1 + + + B_0x2 + tless thansub>DTSless than/sub> = 4 tless thansub>tim_ker_ckless than/sub> + 0x2 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. + 0x0 + + + B_0x1 + Remapping enabled. + 0x1 + + + + + DITHEN + Dithering Enable + + + 12 + 1 + read-write + + + B_0x0 + Dithering disabled + 0x0 + + + B_0x1 + Dithering enabled + 0x1 + + + + + + + TIM3_CR2 + TIM3_CR2 + TIM3 control register 2 + 0x004 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCDS + Capture/compare DMA selection + 3 + 1 + read-write + + + B_0x0 + CCx DMA request sent when CCx event occurs + 0x0 + + + B_0x1 + CCx DMA requests sent when update event occurs + 0x1 + + + + + MMS + MMS[0]: Master mode selection + + + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo). + 0x0 + + + B_0x1 + Enable - the Counter enable signal, CNT_EN, is used as trigger output (tim_trgo). + 0x1 + + + B_0x2 + Update - The update event is selected as trigger output (tim_trgo). + 0x2 + + + B_0x3 + Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred (tim_trgo). + 0x3 + + + B_0x4 + Compare - tim_oc1refc signal is used as trigger output (tim_trgo) + 0x4 + + + B_0x5 + Compare - tim_oc2refc signal is used as trigger output (tim_trgo) + 0x5 + + + B_0x6 + Compare - tim_oc3refc signal is used as trigger output (tim_trgo) + 0x6 + + + B_0x7 + Compare - tim_oc4refc signal is used as trigger output (tim_trgo) + 0x7 + + + + + TI1S + tim_ti1 selection + 7 + 1 + read-write + + + B_0x0 + The tim_ti1_in[15:0] multiplexer output is to tim_ti1 input + 0x0 + + + B_0x1 + The tim_ti1_in[15:0], tim_ti2_in[15:0] and tim_ti3_in[15:0] multiplexers outputs are XORed and connected to the tim_ti1 input. + 0x1 + + + + + MMS_1 + MMS[3] + 25 + 1 + read-write + + + + + TIM3_SMCR + TIM3_SMCR + TIM3 slave mode control register + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SMS + SMS[0]: Slave mode selection + + + 0 + 3 + read-write + + + B_0x0 + Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level. + 0x1 + + + B_0x2 + Encoder mode 2 - Counter counts up/down on tim_ti2fp2 edge depending on tim_ti1fp1 level. + 0x2 + + + B_0x3 + Encoder mode 3 - Counter counts up/down on both tim_ti1fp1 and tim_ti2fp2 edges depending on the level of the other input. + 0x3 + + + B_0x4 + Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers. + 0x4 + + + B_0x5 + Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high. + 0x5 + + + B_0x6 + Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). + 0x6 + + + B_0x7 + External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter. + 0x7 + + + + + OCCS + OCREF clear selection + + + 3 + 1 + read-write + + + B_0x0 + tim_ocref_clr_int is connected to the tim_ocref_clr input + 0x0 + + + B_0x1 + tim_ocref_clr_int is connected to tim_etrf + 0x1 + + + + + TS + TS[0]: Trigger selection + + + 4 + 3 + read-write + + + B_0x0 + Internal trigger 0 (tim_itr0) + 0x0 + + + B_0x1 + Internal trigger 1 (tim_itr1) + 0x1 + + + B_0x2 + Internal trigger 2 (tim_itr2) + 0x2 + + + B_0x3 + Internal trigger 3 (tim_itr3) + 0x3 + + + B_0x4 + tim_ti1 edge detector (tim_ti1f_ed) + 0x4 + + + B_0x5 + Filtered timer input 1 (tim_ti1fp1) + 0x5 + + + B_0x6 + Filtered timer input 2 (tim_ti2fp2) + 0x6 + + + B_0x7 + External trigger input (tim_etrf) + 0x7 + + + + + MSM + Master/Slave mode + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). + 0x1 + + + + + ETF + External trigger filter + + + 8 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + ETPS + External trigger prescaler + + + 12 + 2 + read-write + + + B_0x0 + Prescaler OFF + 0x0 + + + B_0x1 + tim_etrp frequency divided by 2 + 0x1 + + + B_0x2 + tim_etrp frequency divided by 4 + 0x2 + + + B_0x3 + tim_etrp frequency divided by 8 + 0x3 + + + + + ECE + External clock enable + + + 14 + 1 + read-write + + + B_0x0 + External clock mode 2 disabled + 0x0 + + + B_0x1 + External clock mode 2 enabled. + 0x1 + + + + + ETP + External trigger polarity + + + 15 + 1 + read-write + + + B_0x0 + tim_etr_in is non-inverted, active at high level or rising edge + 0x0 + + + B_0x1 + tim_etr_in is inverted, active at low level or falling edge + 0x1 + + + + + SMS_1 + SMS[3] + 16 + 1 + read-write + + + TS_1 + TS[4:3] + 20 + 2 + read-write + + + SMSPE + SMS preload enable + + + 24 + 1 + read-write + + + B_0x0 + SMS[3:0] bitfield is not preloaded + 0x0 + + + B_0x1 + SMS[3:0] preload is enabled + 0x1 + + + + + SMSPS + SMS preload source + + + 25 + 1 + read-write + + + B_0x0 + The transfer is triggered by the Timer's Update event + 0x0 + + + B_0x1 + The transfer is triggered by the Index event + 0x1 + + + + + + + TIM3_DIER + TIM3_DIER + TIM3 DMA/Interrupt enable register + 0x00C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled. + 0x0 + + + B_0x1 + Update interrupt enabled. + 0x1 + + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled. + 0x0 + + + B_0x1 + CC1 interrupt enabled. + 0x1 + + + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + read-write + + + B_0x0 + CC2 interrupt disabled. + 0x0 + + + B_0x1 + CC2 interrupt enabled. + 0x1 + + + + + CC3IE + Capture/Compare 3 interrupt enable + 3 + 1 + read-write + + + B_0x0 + CC3 interrupt disabled. + 0x0 + + + B_0x1 + CC3 interrupt enabled. + 0x1 + + + + + CC4IE + Capture/Compare 4 interrupt enable + 4 + 1 + read-write + + + B_0x0 + CC4 interrupt disabled. + 0x0 + + + B_0x1 + CC4 interrupt enabled. + 0x1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + read-write + + + B_0x0 + Trigger interrupt disabled. + 0x0 + + + B_0x1 + Trigger interrupt enabled. + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled. + 0x0 + + + B_0x1 + Update DMA request enabled. + 0x1 + + + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled. + 0x0 + + + B_0x1 + CC1 DMA request enabled. + 0x1 + + + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled. + 0x0 + + + B_0x1 + CC2 DMA request enabled. + 0x1 + + + + + CC3DE + Capture/Compare 3 DMA request enable + 11 + 1 + read-write + + + B_0x0 + CC3 DMA request disabled. + 0x0 + + + B_0x1 + CC3 DMA request enabled. + 0x1 + + + + + CC4DE + Capture/Compare 4 DMA request enable + 12 + 1 + read-write + + + B_0x0 + CC4 DMA request disabled. + 0x0 + + + B_0x1 + CC4 DMA request enabled. + 0x1 + + + + + TDE + Trigger DMA request enable + 14 + 1 + read-write + + + B_0x0 + Trigger DMA request disabled. + 0x0 + + + B_0x1 + Trigger DMA request enabled. + 0x1 + + + + + IDXIE + Index interrupt enable + 20 + 1 + read-write + + + B_0x0 + Index interrupt disabled + 0x0 + + + B_0x1 + Index interrupt enabled + 0x1 + + + + + DIRIE + Direction change interrupt enable + 21 + 1 + read-write + + + B_0x0 + Direction change interrupt disabled + 0x0 + + + B_0x1 + Direction change interrupt enabled + 0x1 + + + + + IERRIE + Index error interrupt enable + 22 + 1 + read-write + + + B_0x0 + Index error interrupt disabled + 0x0 + + + B_0x1 + Index error interrupt enabled + 0x1 + + + + + TERRIE + Transition error interrupt enable + 23 + 1 + read-write + + + B_0x0 + Transition error interrupt disabled + 0x0 + + + B_0x1 + Transition error interrupt enabled + 0x1 + + + + + + + TIM3_SR + TIM3_SR + TIM3 status register + 0x010 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UIF + Update interrupt flag + + + 0 + 1 + read-write + + + B_0x0 + No update occurred + 0x0 + + + B_0x1 + Update interrupt pending. + 0x1 + + + + + CC1IF + Capture/compare 1 interrupt flag + + + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred + 0x1 + + + + + CC2IF + Capture/Compare 2 interrupt flag + + + 2 + 1 + read-write + + + CC3IF + Capture/Compare 3 interrupt flag + + + 3 + 1 + read-write + + + CC4IF + Capture/Compare 4 interrupt flag + + + 4 + 1 + read-write + + + TIF + Trigger interrupt flag + + + 6 + 1 + read-write + + + B_0x0 + No trigger event occurred. + 0x0 + + + B_0x1 + Trigger interrupt pending. + 0x1 + + + + + CC1OF + Capture/Compare 1 overcapture flag + + + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + CC2OF + Capture/compare 2 overcapture flag + + + 10 + 1 + read-write + + + CC3OF + Capture/Compare 3 overcapture flag + + + 11 + 1 + read-write + + + CC4OF + Capture/Compare 4 overcapture flag + + + 12 + 1 + read-write + + + IDXF + Index interrupt flag + + + 20 + 1 + read-write + + + B_0x0 + No index event occurred. + 0x0 + + + B_0x1 + An index event has occurred + 0x1 + + + + + DIRF + Direction change interrupt flag + + + 21 + 1 + read-write + + + B_0x0 + No direction change + 0x0 + + + B_0x1 + Direction change + 0x1 + + + + + IERRF + Index error interrupt flag + + + 22 + 1 + read-write + + + B_0x0 + No index error has been detected. + 0x0 + + + B_0x1 + An index error has been detected + 0x1 + + + + + TERRF + Transition error interrupt flag + + + 23 + 1 + read-write + + + B_0x0 + No encoder transition error has been detected. + 0x0 + + + B_0x1 + An encoder transition error has been detected + 0x1 + + + + + + + TIM3_EGR + TIM3_EGR + TIM3 event generation register + 0x014 + 16 + write-only + 0x00000000 + 0x0000FFFF + + + UG + Update generation + + + 0 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Re-initialize the counter and generates an update of the registers. + 0x1 + + + + + CC1G + Capture/compare 1 generation + + + 1 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + CC2G + Capture/compare 2 generation + + + 2 + 1 + write-only + + + CC3G + Capture/compare 3 generation + + + 3 + 1 + write-only + + + CC4G + Capture/compare 4 generation + + + 4 + 1 + write-only + + + TG + Trigger generation + + + 6 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + The TIF flag is set in TIMx_SR register. + 0x1 + + + + + + + TIM3_CCMR1 + TIM3_CCMR1 + TIM3 capture/compare mode register 1 [alternate] + 0x018 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. + 0x3 + + + + + IC1PSC + Input capture 1 prescaler + + + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter + + + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + CC2S + Capture/compare 2 selection + + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output. + 0x0 + + + B_0x1 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2. + 0x1 + + + B_0x2 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1. + 0x2 + + + B_0x3 + CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. + 0x3 + + + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + read-write + + + IC2F + Input capture 2 filter + 12 + 4 + read-write + + + + + TIM3_CCMR1_Alternate + TIM3_CCMR1_Alternate + TIM3 capture/compare mode register 1 + TIM3_CCMR1 + 0x018 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output. + 0x0 + + + B_0x1 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1. + 0x1 + + + B_0x2 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2. + 0x2 + + + B_0x3 + CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. + 0x3 + + + + + OC1FE + Output compare 1 fast enable + + + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. + 0x1 + + + + + OC1PE + Output compare 1 preload enable + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. + 0x1 + + + + + OC1M + OC1M[2:0]: Output compare 1 mode + + + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. + 0x2 + + + B_0x3 + Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - tim_oc1ref is forced low. + 0x4 + + + B_0x5 + Force active level - tim_oc1ref is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. + 0x6 + + + B_0x7 + PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. + 0x7 + + + + + OC1CE + Output compare 1 clear enable + 7 + 1 + read-write + + + B_0x0 + tim_oc1ref is not affected by the tim_ocref_clr_int input + 0x0 + + + B_0x1 + tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr_int input + 0x1 + + + + + CC2S + Capture/Compare 2 selection + + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. + 0x3 + + + + + OC2FE + Output compare 2 fast enable + 10 + 1 + read-write + + + OC2PE + Output compare 2 preload enable + 11 + 1 + read-write + + + OC2M + OC2M[2:0]: Output compare 2 mode + + + 12 + 3 + read-write + + + OC2CE + Output compare 2 clear enable + 15 + 1 + read-write + + + OC1M_1 + OC1M[3] + 16 + 1 + read-write + + + OC2M_1 + OC2M[3] + 24 + 1 + read-write + + + + + TIM3_CCMR2 + TIM3_CCMR2 + TIM3 capture/compare mode register 2 [alternate] + 0x01C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection + + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. + 0x3 + + + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + read-write + + + IC3F + Input capture 3 filter + 4 + 4 + read-write + + + CC4S + Capture/Compare 4 selection + + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. + 0x3 + + + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + read-write + + + IC4F + Input capture 4 filter + 12 + 4 + read-write + + + + + TIM3_CCMR2_Alternate + TIM3_CCMR2_Alternate + TIM3 capture/compare mode register 2 + TIM3_CCMR2 + 0x01C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection + + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. + 0x3 + + + + + OC3FE + Output compare 3 fast enable + 2 + 1 + read-write + + + OC3PE + Output compare 3 preload enable + 3 + 1 + read-write + + + OC3M + OC3M[2:0]: Output compare 3 mode + + + 4 + 3 + read-write + + + OC3CE + Output compare 3 clear enable + 7 + 1 + read-write + + + CC4S + Capture/Compare 4 selection + + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. + 0x3 + + + + + OC4FE + Output compare 4 fast enable + 10 + 1 + read-write + + + OC4PE + Output compare 4 preload enable + 11 + 1 + read-write + + + OC4M + OC4M[2:0]: Output compare 4 mode + + + 12 + 3 + read-write + + + OC4CE + Output compare 4 clear enable + 15 + 1 + read-write + + + OC3M_1 + OC3M[3] + 16 + 1 + read-write + + + OC4M_1 + OC4M[3] + 24 + 1 + read-write + + + + + TIM3_CCER + TIM3_CCER + TIM3 capture/compare enable register + 0x020 + 16 + read-write + 0x00000000 + 0x0000FFFF + + + CC1E + Capture/Compare 1 output enable. + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/Compare 1 output Polarity. + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NP + Capture/Compare 1 output Polarity. + 3 + 1 + read-write + + + CC2E + Capture/Compare 2 output enable. + 4 + 1 + read-write + + + CC2P + Capture/Compare 2 output Polarity. + 5 + 1 + read-write + + + CC2NP + Capture/Compare 2 output Polarity. + 7 + 1 + read-write + + + CC3E + Capture/Compare 3 output enable. + 8 + 1 + read-write + + + CC3P + Capture/Compare 3 output Polarity. + 9 + 1 + read-write + + + CC3NP + Capture/Compare 3 output Polarity. + 11 + 1 + read-write + + + CC4E + Capture/Compare 4 output enable. + 12 + 1 + read-write + + + CC4P + Capture/Compare 4 output Polarity. + 13 + 1 + read-write + + + CC4NP + Capture/Compare 4 output Polarity. + 15 + 1 + read-write + + + + + TIM3_CNT + TIM3_CNT + TIM3 counter + 0x024 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + + + 0 + 16 + read-write + + + UIFCPY + Value depends on IUFREMAP in TIMx_CR1. + 31 + 1 + read-write + + + + + TIM3_PSC + TIM3_PSC + TIM3 prescaler + 0x028 + 16 + read-write + 0x00000000 + 0x0000FFFF + + + PSC + Prescaler value + + + 0 + 16 + read-write + + + + + TIM3_ARR + TIM3_ARR + TIM3 auto-reload register + 0x02C + 0x20 + read-write + 0x0000FFFF + 0xFFFFFFFF + + + ARR + Low Auto-reload value + + + 0 + 20 + read-write + + + + + TIM3_CCR1 + TIM3_CCR1 + TIM3 capture/compare register 1 + 0x034 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR1 + Capture/compare 1 value + + + 0 + 20 + read-write + + + + + TIM3_CCR2 + TIM3_CCR2 + TIM3 capture/compare register 2 + 0x038 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR2 + Capture/compare 1 value + + + 0 + 20 + read-write + + + + + TIM3_CCR3 + TIM3_CCR3 + TIM3 capture/compare register 3 + 0x03C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR3 + Capture/compare 3 value + + + 0 + 20 + read-write + + + + + TIM3_CCR4 + TIM3_CCR4 + TIM3 capture/compare register 4 + 0x040 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR4 + Capture/compare 4 value + + + 0 + 20 + read-write + + + + + TIM3_ECR + TIM3_ECR + TIM3 timer encoder control register + 0x058 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IE + Index enable + + + 0 + 1 + read-write + + + B_0x0 + Index disabled + 0x0 + + + B_0x1 + Index enabled + 0x1 + + + + + IDIR + Index direction + + + 1 + 2 + read-write + + + B_0x0 + Index resets the counter whatever the direction + 0x0 + + + B_0x1 + Index resets the counter when up-counting only + 0x1 + + + B_0x2 + Index resets the counter when down-counting only + 0x2 + + + + + FIDX + First index + + + 5 + 1 + read-write + + + B_0x0 + Index is always active + 0x0 + + + B_0x1 + the first Index only resets the counter + 0x1 + + + + + IPOS + Index positioning + + + 6 + 2 + read-write + + + B_0x0 + Index resets the counter when AB = 00 + 0x0 + + + B_0x1 + Index resets the counter when AB = 01 + 0x1 + + + B_0x2 + Index resets the counter when AB = 10 + 0x2 + + + B_0x3 + Index resets the counter when AB = 11 + 0x3 + + + + + PW + Pulse width + + + 16 + 8 + read-write + + + PWPRSC + Pulse width prescaler + + + 24 + 3 + read-write + + + + + TIM3_TISEL + TIM3_TISEL + TIM3 timer input selection register + 0x05C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + Selects tim_ti1[15:0] input + + + 0 + 4 + read-write + + + B_0x0 + tim_ti1_in0: TIMx_CH1 + 0x0 + + + B_0x1 + tim_ti1_in1 + 0x1 + + + B_0xF + tim_ti1_in15 + 0xF + + + + + TI2SEL + Selects tim_ti2[15:0] input + + + 8 + 4 + read-write + + + B_0x0 + tim_ti2_in0: TIMx_CH2 + 0x0 + + + B_0x1 + tim_ti2_in1 + 0x1 + + + B_0xF + tim_ti2_in15 + 0xF + + + + + TI3SEL + Selects tim_ti3[15:0] input + + + 16 + 4 + read-write + + + B_0x0 + tim_ti3_in0: TIMx_CH3 + 0x0 + + + B_0x1 + tim_ti3_in1 + 0x1 + + + B_0xF + tim_ti3_in15 + 0xF + + + + + TI4SEL + Selects tim_ti4[15:0] input + + + 24 + 4 + read-write + + + B_0x0 + tim_ti4_in0: TIMx_CH4 + 0x0 + + + B_0x1 + tim_ti4_in1 + 0x1 + + + B_0xF + tim_ti4_in15 + 0xF + + + + + + + TIM3_AF1 + TIM3_AF1 + TIM3 alternate function register 1 + 0x060 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ETRSEL + etr_in source selection + + + 14 + 4 + read-write + + + B_0x0 + tim_etr0: TIMx_ETR input + 0x0 + + + B_0x1 + tim_etr1 + 0x1 + + + B_0xF + tim_etr15 + 0xF + + + + + + + TIM3_AF2 + TIM3_AF2 + TIM3 alternate function register 2 + 0x064 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OCRSEL + ocref_clr source selection + + + 16 + 3 + read-write + + + B_0x0 + tim_ocref_clr0 + 0x0 + + + B_0x1 + tim_ocref_clr1 + 0x1 + + + B_0x7 + tim_ocref_clr7 + 0x7 + + + + + + + TIM3_DCR + TIM3_DCR + TIM3 DMA control register + 0x3DC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DBA + DMA base address + + + 0 + 5 + read-write + + + B_0x0 + TIMx_CR1, + 0x0 + + + B_0x1 + TIMx_CR2, + 0x1 + + + B_0x2 + TIMx_SMCR, + 0x2 + + + + + DBL + DMA burst length + + + 8 + 5 + read-write + + + B_0x0 + 1 transfer + 0x0 + + + B_0x1 + 2 transfers + 0x1 + + + B_0x2 + 3 transfers + 0x2 + + + B_0x1A + 26 transfers + 0x1A + + + + + + + TIM3_DMAR + TIM3_DMAR + TIM3 DMA address for full transfer + 0x3E0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DMAB + DMA register for burst accesses + + + 0 + 32 + read-write + + + + + + + TIM4 + 0x40000800 + + TIM4 + TIM4 + 30 + + + + TIM6 + Basic-timers + TIM + 0x40001000 + + 0x0 + 0x400 + registers + + + TIM6_DACUNDER + TIM6_DACUNDER + 54 + + + + TIM6_CR1 + TIM6_CR1 + TIM6 control register 1 + 0x00 + 16 + read-write + 0x00000000 + 0x0000FFFF + + + CEN + Counter enable + + + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable + + + 1 + 1 + read-write + + + B_0x0 + UEV enabled. + 0x0 + + + B_0x1 + UEV disabled. + 0x1 + + + + + URS + Update request source + + + 2 + 1 + read-write + + + B_0x0 + Any of the following events generates an update interrupt or DMA request if enabled. + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the CEN bit). + 0x1 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered. + 0x0 + + + B_0x1 + TIMx_ARR register is buffered. + 0x1 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. + 0x0 + + + B_0x1 + Remapping enabled. + 0x1 + + + + + DITHEN + Dithering enable + + + 12 + 1 + read-write + + + B_0x0 + Dithering disabled + 0x0 + + + B_0x1 + Dithering enabled + 0x1 + + + + + + + TIM6_CR2 + TIM6_CR2 + TIM6 control register 2 + 0x04 + 16 + read-write + 0x00000000 + 0x0000FFFF + + + MMS + Master mode selection + + + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as a trigger output (tim_trgo). + 0x0 + + + B_0x1 + Enable - the Counter enable signal, tim_cnt_en, is used as a trigger output (tim_trgo). + 0x1 + + + B_0x2 + Update - The update event is selected as a trigger output (tim_trgo). + 0x2 + + + + + + + TIM6_DIER + TIM6_DIER + TIM6 DMA/Interrupt enable register + 0x0C + 16 + read-write + 0x00000000 + 0x0000FFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled. + 0x0 + + + B_0x1 + Update interrupt enabled. + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled. + 0x0 + + + B_0x1 + Update DMA request enabled. + 0x1 + + + + + + + TIM6_SR + TIM6_SR + TIM6 status register + 0x10 + 16 + read-write + 0x00000000 + 0x0000FFFF + + + UIF + Update interrupt flag + + + 0 + 1 + read-write + + + B_0x0 + No update occurred. + 0x0 + + + B_0x1 + Update interrupt pending. + 0x1 + + + + + + + TIM6_EGR + TIM6_EGR + TIM6 event generation register + 0x14 + 16 + write-only + 0x00000000 + 0x0000FFFF + + + UG + Update generation + + + 0 + 1 + write-only + + + B_0x0 + No action. + 0x0 + + + B_0x1 + Re-initializes the timer counter and generates an update of the registers. + 0x1 + + + + + + + TIM6_CNT + TIM6_CNT + TIM6 counter + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + + + 0 + 16 + read-write + + + UIFCPY + UIF copy + + + 31 + 1 + read-only + + + + + TIM6_PSC + TIM6_PSC + TIM6 prescaler + 0x28 + 16 + read-write + 0x00000000 + 0x0000FFFF + + + PSC + Prescaler value + + + 0 + 16 + read-write + + + + + TIM6_ARR + TIM6_ARR + TIM6 auto-reload register + 0x2C + 0x20 + read-write + 0x0000FFFF + 0xFFFFFFFF + + + ARR + Auto-reload value + + + 0 + 20 + read-write + + + + + + + TIM7 + 0x40001400 + + TIM7 + TIM7 + 55 + + + + TIM8 + 0x40013400 + + TIM8_BRK + TIM8_BRK + 43 + + + TIM8_UP + TIM8_UP + 44 + + + TIM8_TRG_COM + TIM8_TRG_COM + 45 + + + TIM8_CC + TIM8_CC + 46 + + + + TIM15 + General purpose timers + TIM + 0x40014000 + + 0x0 + 0x400 + registers + + + + TIM5_CR1 + TIM5_CR1 + TIM5 control register 1 + 0x000 + 16 + read-write + 0x00000000 + 0x0000FFFF + + + CEN + Counter enable + + + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable + + + 1 + 1 + read-write + + + B_0x0 + UEV enabled. + 0x0 + + + B_0x1 + UEV disabled. + 0x1 + + + + + URS + Update request source + + + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt or DMA request if enabled. + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + DIR + Direction + + + 4 + 1 + read-write + + + B_0x0 + Counter used as upcounter + 0x0 + + + B_0x1 + Counter used as downcounter + 0x1 + + + + + CMS + Center-aligned mode selection + + + 5 + 2 + read-write + + + B_0x0 + Edge-aligned mode. + 0x0 + + + B_0x1 + Center-aligned mode 1. + 0x1 + + + B_0x2 + Center-aligned mode 2. + 0x2 + + + B_0x3 + Center-aligned mode 3. + 0x3 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division + + + 8 + 2 + read-write + + + B_0x0 + tless thansub>DTSless than/sub> = tless thansub>tim_ker_ckless than/sub> + 0x0 + + + B_0x1 + tless thansub>DTSless than/sub> = 2 tless thansub>tim_ker_ckless than/sub> + 0x1 + + + B_0x2 + tless thansub>DTSless than/sub> = 4 tless thansub>tim_ker_ckless than/sub> + 0x2 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. + 0x0 + + + B_0x1 + Remapping enabled. + 0x1 + + + + + DITHEN + Dithering Enable + + + 12 + 1 + read-write + + + B_0x0 + Dithering disabled + 0x0 + + + B_0x1 + Dithering enabled + 0x1 + + + + + + + TIM5_CR2 + TIM5_CR2 + TIM5 control register 2 + 0x004 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCDS + Capture/compare DMA selection + 3 + 1 + read-write + + + B_0x0 + CCx DMA request sent when CCx event occurs + 0x0 + + + B_0x1 + CCx DMA requests sent when update event occurs + 0x1 + + + + + MMS + MMS[0]: Master mode selection + + + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo). + 0x0 + + + B_0x1 + Enable - the Counter enable signal, CNT_EN, is used as trigger output (tim_trgo). + 0x1 + + + B_0x2 + Update - The update event is selected as trigger output (tim_trgo). + 0x2 + + + B_0x3 + Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred (tim_trgo). + 0x3 + + + B_0x4 + Compare - tim_oc1refc signal is used as trigger output (tim_trgo) + 0x4 + + + B_0x5 + Compare - tim_oc2refc signal is used as trigger output (tim_trgo) + 0x5 + + + B_0x6 + Compare - tim_oc3refc signal is used as trigger output (tim_trgo) + 0x6 + + + B_0x7 + Compare - tim_oc4refc signal is used as trigger output (tim_trgo) + 0x7 + + + + + TI1S + tim_ti1 selection + 7 + 1 + read-write + + + B_0x0 + The tim_ti1_in[15:0] multiplexer output is to tim_ti1 input + 0x0 + + + B_0x1 + The tim_ti1_in[15:0], tim_ti2_in[15:0] and tim_ti3_in[15:0] multiplexers outputs are XORed and connected to the tim_ti1 input. + 0x1 + + + + + MMS_1 + MMS[3] + 25 + 1 + read-write + + + + + TIM5_SMCR + TIM5_SMCR + TIM5 slave mode control register + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SMS + SMS[0]: Slave mode selection + + + 0 + 3 + read-write + + + B_0x0 + Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level. + 0x1 + + + B_0x2 + Encoder mode 2 - Counter counts up/down on tim_ti2fp2 edge depending on tim_ti1fp1 level. + 0x2 + + + B_0x3 + Encoder mode 3 - Counter counts up/down on both tim_ti1fp1 and tim_ti2fp2 edges depending on the level of the other input. + 0x3 + + + B_0x4 + Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers. + 0x4 + + + B_0x5 + Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high. + 0x5 + + + B_0x6 + Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). + 0x6 + + + B_0x7 + External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter. + 0x7 + + + + + OCCS + OCREF clear selection + + + 3 + 1 + read-write + + + B_0x0 + tim_ocref_clr_int is connected to the tim_ocref_clr input + 0x0 + + + B_0x1 + tim_ocref_clr_int is connected to tim_etrf + 0x1 + + + + + TS + TS[0]: Trigger selection + + + 4 + 3 + read-write + + + B_0x0 + Internal trigger 0 (tim_itr0) + 0x0 + + + B_0x1 + Internal trigger 1 (tim_itr1) + 0x1 + + + B_0x2 + Internal trigger 2 (tim_itr2) + 0x2 + + + B_0x3 + Internal trigger 3 (tim_itr3) + 0x3 + + + B_0x4 + tim_ti1 edge detector (tim_ti1f_ed) + 0x4 + + + B_0x5 + Filtered timer input 1 (tim_ti1fp1) + 0x5 + + + B_0x6 + Filtered timer input 2 (tim_ti2fp2) + 0x6 + + + B_0x7 + External trigger input (tim_etrf) + 0x7 + + + + + MSM + Master/Slave mode + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). + 0x1 + + + + + ETF + External trigger filter + + + 8 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + ETPS + External trigger prescaler + + + 12 + 2 + read-write + + + B_0x0 + Prescaler OFF + 0x0 + + + B_0x1 + tim_etrp frequency divided by 2 + 0x1 + + + B_0x2 + tim_etrp frequency divided by 4 + 0x2 + + + B_0x3 + tim_etrp frequency divided by 8 + 0x3 + + + + + ECE + External clock enable + + + 14 + 1 + read-write + + + B_0x0 + External clock mode 2 disabled + 0x0 + + + B_0x1 + External clock mode 2 enabled. + 0x1 + + + + + ETP + External trigger polarity + + + 15 + 1 + read-write + + + B_0x0 + tim_etr_in is non-inverted, active at high level or rising edge + 0x0 + + + B_0x1 + tim_etr_in is inverted, active at low level or falling edge + 0x1 + + + + + SMS_1 + SMS[3] + 16 + 1 + read-write + + + TS_1 + TS[4:3] + 20 + 2 + read-write + + + SMSPE + SMS preload enable + + + 24 + 1 + read-write + + + B_0x0 + SMS[3:0] bitfield is not preloaded + 0x0 + + + B_0x1 + SMS[3:0] preload is enabled + 0x1 + + + + + SMSPS + SMS preload source + + + 25 + 1 + read-write + + + B_0x0 + The transfer is triggered by the Timer's Update event + 0x0 + + + B_0x1 + The transfer is triggered by the Index event + 0x1 + + + + + + + TIM5_DIER + TIM5_DIER + TIM5 DMA/Interrupt enable register + 0x00C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled. + 0x0 + + + B_0x1 + Update interrupt enabled. + 0x1 + + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled. + 0x0 + + + B_0x1 + CC1 interrupt enabled. + 0x1 + + + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + read-write + + + B_0x0 + CC2 interrupt disabled. + 0x0 + + + B_0x1 + CC2 interrupt enabled. + 0x1 + + + + + CC3IE + Capture/Compare 3 interrupt enable + 3 + 1 + read-write + + + B_0x0 + CC3 interrupt disabled. + 0x0 + + + B_0x1 + CC3 interrupt enabled. + 0x1 + + + + + CC4IE + Capture/Compare 4 interrupt enable + 4 + 1 + read-write + + + B_0x0 + CC4 interrupt disabled. + 0x0 + + + B_0x1 + CC4 interrupt enabled. + 0x1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + read-write + + + B_0x0 + Trigger interrupt disabled. + 0x0 + + + B_0x1 + Trigger interrupt enabled. + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled. + 0x0 + + + B_0x1 + Update DMA request enabled. + 0x1 + + + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled. + 0x0 + + + B_0x1 + CC1 DMA request enabled. + 0x1 + + + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled. + 0x0 + + + B_0x1 + CC2 DMA request enabled. + 0x1 + + + + + CC3DE + Capture/Compare 3 DMA request enable + 11 + 1 + read-write + + + B_0x0 + CC3 DMA request disabled. + 0x0 + + + B_0x1 + CC3 DMA request enabled. + 0x1 + + + + + CC4DE + Capture/Compare 4 DMA request enable + 12 + 1 + read-write + + + B_0x0 + CC4 DMA request disabled. + 0x0 + + + B_0x1 + CC4 DMA request enabled. + 0x1 + + + + + TDE + Trigger DMA request enable + 14 + 1 + read-write + + + B_0x0 + Trigger DMA request disabled. + 0x0 + + + B_0x1 + Trigger DMA request enabled. + 0x1 + + + + + IDXIE + Index interrupt enable + 20 + 1 + read-write + + + B_0x0 + Index interrupt disabled + 0x0 + + + B_0x1 + Index interrupt enabled + 0x1 + + + + + DIRIE + Direction change interrupt enable + 21 + 1 + read-write + + + B_0x0 + Direction change interrupt disabled + 0x0 + + + B_0x1 + Direction change interrupt enabled + 0x1 + + + + + IERRIE + Index error interrupt enable + 22 + 1 + read-write + + + B_0x0 + Index error interrupt disabled + 0x0 + + + B_0x1 + Index error interrupt enabled + 0x1 + + + + + TERRIE + Transition error interrupt enable + 23 + 1 + read-write + + + B_0x0 + Transition error interrupt disabled + 0x0 + + + B_0x1 + Transition error interrupt enabled + 0x1 + + + + + + + TIM5_SR + TIM5_SR + TIM5 status register + 0x010 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UIF + Update interrupt flag + + + 0 + 1 + read-write + + + B_0x0 + No update occurred + 0x0 + + + B_0x1 + Update interrupt pending. + 0x1 + + + + + CC1IF + Capture/compare 1 interrupt flag + + + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred + 0x1 + + + + + CC2IF + Capture/Compare 2 interrupt flag + + + 2 + 1 + read-write + + + CC3IF + Capture/Compare 3 interrupt flag + + + 3 + 1 + read-write + + + CC4IF + Capture/Compare 4 interrupt flag + + + 4 + 1 + read-write + + + TIF + Trigger interrupt flag + + + 6 + 1 + read-write + + + B_0x0 + No trigger event occurred. + 0x0 + + + B_0x1 + Trigger interrupt pending. + 0x1 + + + + + CC1OF + Capture/Compare 1 overcapture flag + + + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + CC2OF + Capture/compare 2 overcapture flag + + + 10 + 1 + read-write + + + CC3OF + Capture/Compare 3 overcapture flag + + + 11 + 1 + read-write + + + CC4OF + Capture/Compare 4 overcapture flag + + + 12 + 1 + read-write + + + IDXF + Index interrupt flag + + + 20 + 1 + read-write + + + B_0x0 + No index event occurred. + 0x0 + + + B_0x1 + An index event has occurred + 0x1 + + + + + DIRF + Direction change interrupt flag + + + 21 + 1 + read-write + + + B_0x0 + No direction change + 0x0 + + + B_0x1 + Direction change + 0x1 + + + + + IERRF + Index error interrupt flag + + + 22 + 1 + read-write + + + B_0x0 + No index error has been detected. + 0x0 + + + B_0x1 + An index error has been detected + 0x1 + + + + + TERRF + Transition error interrupt flag + + + 23 + 1 + read-write + + + B_0x0 + No encoder transition error has been detected. + 0x0 + + + B_0x1 + An encoder transition error has been detected + 0x1 + + + + + + + TIM5_EGR + TIM5_EGR + TIM5 event generation register + 0x014 + 16 + write-only + 0x00000000 + 0x0000FFFF + + + UG + Update generation + + + 0 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Re-initialize the counter and generates an update of the registers. + 0x1 + + + + + CC1G + Capture/compare 1 generation + + + 1 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + CC2G + Capture/compare 2 generation + + + 2 + 1 + write-only + + + CC3G + Capture/compare 3 generation + + + 3 + 1 + write-only + + + CC4G + Capture/compare 4 generation + + + 4 + 1 + write-only + + + TG + Trigger generation + + + 6 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + The TIF flag is set in TIMx_SR register. + 0x1 + + + + + + + TIM5_CCMR1 + TIM5_CCMR1 + TIM5 capture/compare mode register 1 [alternate] + 0x018 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. + 0x3 + + + + + IC1PSC + Input capture 1 prescaler + + + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter + + + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + CC2S + Capture/compare 2 selection + + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output. + 0x0 + + + B_0x1 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2. + 0x1 + + + B_0x2 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1. + 0x2 + + + B_0x3 + CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. + 0x3 + + + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + read-write + + + IC2F + Input capture 2 filter + 12 + 4 + read-write + + + + + TIM5_CCMR1_Alternate + TIM5_CCMR1_Alternate + TIM5 capture/compare mode register 1 + TIM5_CCMR1 + 0x018 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output. + 0x0 + + + B_0x1 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1. + 0x1 + + + B_0x2 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2. + 0x2 + + + B_0x3 + CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. + 0x3 + + + + + OC1FE + Output compare 1 fast enable + + + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. + 0x1 + + + + + OC1PE + Output compare 1 preload enable + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. + 0x1 + + + + + OC1M + OC1M[2:0]: Output compare 1 mode + + + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. + 0x2 + + + B_0x3 + Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - tim_oc1ref is forced low. + 0x4 + + + B_0x5 + Force active level - tim_oc1ref is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. + 0x6 + + + B_0x7 + PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. + 0x7 + + + + + OC1CE + Output compare 1 clear enable + 7 + 1 + read-write + + + B_0x0 + tim_oc1ref is not affected by the tim_ocref_clr_int input + 0x0 + + + B_0x1 + tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr_int input + 0x1 + + + + + CC2S + Capture/Compare 2 selection + + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. + 0x3 + + + + + OC2FE + Output compare 2 fast enable + 10 + 1 + read-write + + + OC2PE + Output compare 2 preload enable + 11 + 1 + read-write + + + OC2M + OC2M[2:0]: Output compare 2 mode + + + 12 + 3 + read-write + + + OC2CE + Output compare 2 clear enable + 15 + 1 + read-write + + + OC1M_1 + OC1M[3] + 16 + 1 + read-write + + + OC2M_1 + OC2M[3] + 24 + 1 + read-write + + + + + TIM5_CCMR2 + TIM5_CCMR2 + TIM5 capture/compare mode register 2 [alternate] + 0x01C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection + + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. + 0x3 + + + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + read-write + + + IC3F + Input capture 3 filter + 4 + 4 + read-write + + + CC4S + Capture/Compare 4 selection + + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. + 0x3 + + + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + read-write + + + IC4F + Input capture 4 filter + 12 + 4 + read-write + + + + + TIM5_CCMR2_Alternate + TIM5_CCMR2_Alternate + TIM5 capture/compare mode register 2 + TIM5_CCMR2 + 0x01C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection + + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. + 0x3 + + + + + OC3FE + Output compare 3 fast enable + 2 + 1 + read-write + + + OC3PE + Output compare 3 preload enable + 3 + 1 + read-write + + + OC3M + OC3M[2:0]: Output compare 3 mode + + + 4 + 3 + read-write + + + OC3CE + Output compare 3 clear enable + 7 + 1 + read-write + + + CC4S + Capture/Compare 4 selection + + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. + 0x3 + + + + + OC4FE + Output compare 4 fast enable + 10 + 1 + read-write + + + OC4PE + Output compare 4 preload enable + 11 + 1 + read-write + + + OC4M + OC4M[2:0]: Output compare 4 mode + + + 12 + 3 + read-write + + + OC4CE + Output compare 4 clear enable + 15 + 1 + read-write + + + OC3M_1 + OC3M[3] + 16 + 1 + read-write + + + OC4M_1 + OC4M[3] + 24 + 1 + read-write + + + + + TIM5_CCER + TIM5_CCER + TIM5 capture/compare enable register + 0x020 + 16 + read-write + 0x00000000 + 0x0000FFFF + + + CC1E + Capture/Compare 1 output enable. + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/Compare 1 output Polarity. + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NP + Capture/Compare 1 output Polarity. + 3 + 1 + read-write + + + CC2E + Capture/Compare 2 output enable. + 4 + 1 + read-write + + + CC2P + Capture/Compare 2 output Polarity. + 5 + 1 + read-write + + + CC2NP + Capture/Compare 2 output Polarity. + 7 + 1 + read-write + + + CC3E + Capture/Compare 3 output enable. + 8 + 1 + read-write + + + CC3P + Capture/Compare 3 output Polarity. + 9 + 1 + read-write + + + CC3NP + Capture/Compare 3 output Polarity. + 11 + 1 + read-write + + + CC4E + Capture/Compare 4 output enable. + 12 + 1 + read-write + + + CC4P + Capture/Compare 4 output Polarity. + 13 + 1 + read-write + + + CC4NP + Capture/Compare 4 output Polarity. + 15 + 1 + read-write + + + + + TIM5_CNT + TIM5_CNT + TIM5 counter + 0x024 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Least significant part of counter value + + + 0 + 31 + read-write + + + UIFCPY_CNT + Value depends on IUFREMAP in TIMx_CR1. + 31 + 1 + read-write + + + + + TIM5_PSC + TIM5_PSC + TIM5 prescaler + 0x028 + 16 + read-write + 0x00000000 + 0x0000FFFF + + + PSC + Prescaler value + + + 0 + 16 + read-write + + + + + TIM5_ARR + TIM5_ARR + TIM5 auto-reload register + 0x02C + 0x20 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + ARR + Auto-reload value + + + 0 + 32 + read-write + + + + + TIM5_CCR1 + TIM5_CCR1 + TIM5 capture/compare register 1 + 0x034 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR1 + Capture/compare 1 value + + + 0 + 32 + read-write + + + + + TIM5_CCR2 + TIM5_CCR2 + TIM5 capture/compare register 2 + 0x038 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR2 + Capture/compare 2 value + + + 0 + 32 + read-write + + + + + TIM5_CCR3 + TIM5_CCR3 + TIM5 capture/compare register 3 + 0x03C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR3 + Capture/compare 3 value + + + 0 + 32 + read-write + + + + + TIM5_CCR4 + TIM5_CCR4 + TIM5 capture/compare register 4 + 0x040 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR4 + Capture/compare 4 value + + + 0 + 32 + read-write + + + + + TIM5_ECR + TIM5_ECR + TIM5 timer encoder control register + 0x058 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IE + Index enable + + + 0 + 1 + read-write + + + B_0x0 + Index disabled + 0x0 + + + B_0x1 + Index enabled + 0x1 + + + + + IDIR + Index direction + + + 1 + 2 + read-write + + + B_0x0 + Index resets the counter whatever the direction + 0x0 + + + B_0x1 + Index resets the counter when up-counting only + 0x1 + + + B_0x2 + Index resets the counter when down-counting only + 0x2 + + + + + FIDX + First index + + + 5 + 1 + read-write + + + B_0x0 + Index is always active + 0x0 + + + B_0x1 + the first Index only resets the counter + 0x1 + + + + + IPOS + Index positioning + + + 6 + 2 + read-write + + + B_0x0 + Index resets the counter when AB = 00 + 0x0 + + + B_0x1 + Index resets the counter when AB = 01 + 0x1 + + + B_0x2 + Index resets the counter when AB = 10 + 0x2 + + + B_0x3 + Index resets the counter when AB = 11 + 0x3 + + + + + PW + Pulse width + + + 16 + 8 + read-write + + + PWPRSC + Pulse width prescaler + + + 24 + 3 + read-write + + + + + TIM5_TISEL + TIM5_TISEL + TIM5 timer input selection register + 0x05C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + Selects tim_ti1[15:0] input + + + 0 + 4 + read-write + + + B_0x0 + tim_ti1_in0: TIMx_CH1 + 0x0 + + + B_0x1 + tim_ti1_in1 + 0x1 + + + B_0xF + tim_ti1_in15 + 0xF + + + + + TI2SEL + Selects tim_ti2[15:0] input + + + 8 + 4 + read-write + + + B_0x0 + tim_ti2_in0: TIMx_CH2 + 0x0 + + + B_0x1 + tim_ti2_in1 + 0x1 + + + B_0xF + tim_ti2_in15 + 0xF + + + + + TI3SEL + Selects tim_ti3[15:0] input + + + 16 + 4 + read-write + + + B_0x0 + tim_ti3_in0: TIMx_CH3 + 0x0 + + + B_0x1 + tim_ti3_in1 + 0x1 + + + B_0xF + tim_ti3_in15 + 0xF + + + + + TI4SEL + Selects tim_ti4[15:0] input + + + 24 + 4 + read-write + + + B_0x0 + tim_ti4_in0: TIMx_CH4 + 0x0 + + + B_0x1 + tim_ti4_in1 + 0x1 + + + B_0xF + tim_ti4_in15 + 0xF + + + + + + + TIM5_AF1 + TIM5_AF1 + TIM5 alternate function register 1 + 0x060 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ETRSEL + etr_in source selection + + + 14 + 4 + read-write + + + B_0x0 + tim_etr0: TIMx_ETR input + 0x0 + + + B_0x1 + tim_etr1 + 0x1 + + + B_0xF + tim_etr15 + 0xF + + + + + + + TIM5_AF2 + TIM5_AF2 + TIM5 alternate function register 2 + 0x064 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OCRSEL + ocref_clr source selection + + + 16 + 3 + read-write + + + B_0x0 + tim_ocref_clr0 + 0x0 + + + B_0x1 + tim_ocref_clr1 + 0x1 + + + B_0x7 + tim_ocref_clr7 + 0x7 + + + + + + + TIM5_DCR + TIM5_DCR + TIM5 DMA control register + 0x3DC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DBA + DMA base address + + + 0 + 5 + read-write + + + B_0x0 + TIMx_CR1, + 0x0 + + + B_0x1 + TIMx_CR2, + 0x1 + + + B_0x2 + TIMx_SMCR, + 0x2 + + + + + DBL + DMA burst length + + + 8 + 5 + read-write + + + B_0x0 + 1 transfer + 0x0 + + + B_0x1 + 2 transfers + 0x1 + + + B_0x2 + 3 transfers + 0x2 + + + B_0x1A + 26 transfers + 0x1A + + + + + + + TIM5_DMAR + TIM5_DMAR + TIM5 DMA address for full transfer + 0x3E0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DMAB + DMA register for burst accesses + + + 0 + 32 + read-write + + + + + + + TIM16 + General purpose timers + TIM + 0x40014400 + + 0x0 + 0x400 + registers + + + + TIM16_CR1 + TIM16_CR1 + TIM16 control register 1 + 0x00 + 16 + read-write + 0x00000000 + 0x0000FFFF + + + CEN + Counter enable + + + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable + + + 1 + 1 + read-write + + + B_0x0 + UEV enabled. + 0x0 + + + B_0x1 + UEV disabled. + 0x1 + + + + + URS + Update request source + + + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt or DMA request if enabled. + 0x0 + + + B_0x1 + nly counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division + + + 8 + 2 + read-write + + + B_0x0 + tless thansub>DTSless than/sub>=tless thansub>tim_ker_ckless than/sub> + 0x0 + + + B_0x1 + tless thansub>DTSless than/sub>=2*tless thansub>tim_ker_ckless than/sub> + 0x1 + + + B_0x2 + tless thansub>DTSless than/sub>=4*tless thansub>tim_ker_ckless than/sub> + 0x2 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. + 0x0 + + + B_0x1 + Remapping enabled. + 0x1 + + + + + DITHEN + Dithering enable + + + 12 + 1 + read-write + + + B_0x0 + Dithering disabled + 0x0 + + + B_0x1 + Dithering enabled + 0x1 + + + + + + + TIM16_CR2 + TIM16_CR2 + TIM16 control register 2 + 0x04 + 16 + read-write + 0x00000000 + 0x0000FFFF + + + CCPC + Capture/compare preloaded control + + + 0 + 1 + read-write + + + B_0x0 + CCxE, CCxNE and OCxM bits are not preloaded + 0x0 + + + B_0x1 + CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when COM bit is set. + 0x1 + + + + + CCUS + Capture/compare control update selection + + + 2 + 1 + read-write + + + B_0x0 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only. + 0x0 + + + B_0x1 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when a rising edge occurs on tim_trgi (if available). + 0x1 + + + + + CCDS + Capture/compare DMA selection + 3 + 1 + read-write + + + B_0x0 + CCx DMA request sent when CCx event occurs + 0x0 + + + B_0x1 + CCx DMA requests sent when update event occurs + 0x1 + + + + + OIS1 + Output Idle state 1 (tim_oc1 output) + + + 8 + 1 + read-write + + + B_0x0 + tim_oc1=0 after a dead-time when MOE=0 + 0x0 + + + B_0x1 + tim_oc1=1 after a dead-time when MOE=0 + 0x1 + + + + + OIS1N + Output Idle state 1 (tim_oc1n output) + + + 9 + 1 + read-write + + + B_0x0 + tim_oc1n=0 after a dead-time when MOE=0 + 0x0 + + + B_0x1 + tim_oc1n=1 after a dead-time when MOE=0 + 0x1 + + + + + + + TIM16_DIER + TIM16_DIER + TIM16 DMA/interrupt enable register + 0x0C + 16 + read-write + 0x00000000 + 0x0000FFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled + 0x0 + + + B_0x1 + Update interrupt enabled + 0x1 + + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled + 0x0 + + + B_0x1 + CC1 interrupt enabled + 0x1 + + + + + COMIE + COM interrupt enable + 5 + 1 + read-write + + + B_0x0 + COM interrupt disabled + 0x0 + + + B_0x1 + COM interrupt enabled + 0x1 + + + + + BIE + Break interrupt enable + 7 + 1 + read-write + + + B_0x0 + Break interrupt disabled + 0x0 + + + B_0x1 + Break interrupt enabled + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled + 0x0 + + + B_0x1 + Update DMA request enabled + 0x1 + + + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled + 0x0 + + + B_0x1 + CC1 DMA request enabled + 0x1 + + + + + + + TIM16_SR + TIM16_SR + TIM16 status register + 0x10 + 16 + read-write + 0x00000000 + 0x0000FFFF + + + UIF + Update interrupt flag + + + 0 + 1 + read-write + + + B_0x0 + No update occurred. + 0x0 + + + B_0x1 + Update interrupt pending. + 0x1 + + + + + CC1IF + Capture/Compare 1 interrupt flag + + + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred + 0x1 + + + + + COMIF + COM interrupt flag + + + 5 + 1 + read-write + + + B_0x0 + No COM event occurred + 0x0 + + + B_0x1 + COM interrupt pending + 0x1 + + + + + BIF + Break interrupt flag + + + 7 + 1 + read-write + + + B_0x0 + No break event occurred + 0x0 + + + B_0x1 + An active level has been detected on the break input + 0x1 + + + + + CC1OF + Capture/Compare 1 overcapture flag + + + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + + + TIM16_EGR + TIM16_EGR + TIM16 event generation register + 0x14 + 16 + write-only + 0x00000000 + 0x0000FFFF + + + UG + Update generation + + + 0 + 1 + write-only + + + B_0x0 + No action. + 0x0 + + + B_0x1 + Reinitialize the counter and generates an update of the registers. + 0x1 + + + + + CC1G + Capture/Compare 1 generation + + + 1 + 1 + write-only + + + B_0x0 + No action. + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + COMG + Capture/Compare control update generation + + + 5 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits + 0x1 + + + + + BG + Break generation + + + 7 + 1 + write-only + + + B_0x0 + No action. + 0x0 + + + B_0x1 + A break event is generated. + 0x1 + + + + + + + TIM16_CCMR1 + TIM16_CCMR1 + TIM16 capture/compare mode register 1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1 + 0x1 + + + + + IC1PSC + Input capture 1 prescaler + + + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input. + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter + + + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N= + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + + + TIM16_CCMR1_Alternate + TIM16_CCMR1_Alternate + TIM16 capture/compare mode register 1 + TIM16_CCMR1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1 + 0x1 + + + + + OC1FE + Output Compare 1 fast enable + + + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. + 0x1 + + + + + OC1PE + Output Compare 1 preload enable + + + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. + 0x1 + + + + + OC1M + OC1M[2:0]: Output Compare 1 mode + + + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. + 0x2 + + + B_0x3 + Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - tim_oc1ref is forced low. + 0x4 + + + B_0x5 + Force active level - tim_oc1ref is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - Channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. + 0x6 + + + B_0x7 + PWM mode 2 - Channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. + 0x7 + + + + + OC1CE + Output Compare 1 clear enable + 7 + 1 + read-write + + + B_0x0 + tim_oc1ref is not affected by the tim_ocref_clr input. + 0x0 + + + B_0x1 + tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr input. + 0x1 + + + + + OC1M_1 + OC1M[3] + 16 + 1 + read-write + + + + + TIM16_CCER + TIM16_CCER + TIM16 capture/compare enable register + 0x20 + 16 + read-write + 0x00000000 + 0x0000FFFF + + + CC1E + Capture/Compare 1 output enable + + + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active (see below) + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/Compare 1 output polarity + + + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NE + Capture/Compare 1 complementary output enable + 2 + 1 + read-write + + + B_0x0 + Off - tim_oc1n is not active. + 0x0 + + + B_0x1 + On - tim_oc1n signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. + 0x1 + + + + + CC1NP + Capture/Compare 1 complementary output polarity + + + 3 + 1 + read-write + + + B_0x0 + tim_oc1n active high + 0x0 + + + B_0x1 + tim_oc1n active low + 0x1 + + + + + + + TIM16_CNT + TIM16_CNT + TIM16 counter + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + + + 0 + 16 + read-write + + + UIFCPY + UIF Copy + + + 31 + 1 + read-only + + + + + TIM16_PSC + TIM16_PSC + TIM16 prescaler + 0x28 + 16 + read-write + 0x00000000 + 0x0000FFFF + + + PSC + Prescaler value + + + 0 + 16 + read-write + + + + + TIM16_ARR + TIM16_ARR + TIM16 auto-reload register + 0x2C + 0x20 + read-write + 0x0000FFFF + 0xFFFFFFFF + + + ARR + Auto-reload value + + + 0 + 20 + read-write + + + + + TIM16_RCR + TIM16_RCR + TIM16 repetition counter register + 0x30 + 16 + read-write + 0x00000000 + 0x0000FFFF + + + REP + Repetition counter reload value + + + 0 + 8 + read-write + + + + + TIM16_CCR1 + TIM16_CCR1 + TIM16 capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR1 + Capture/Compare 1 value + + + 0 + 20 + read-write + + + + + TIM16_BDTR + TIM16_BDTR + TIM16 break and dead-time register + 0x44 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DTG + Dead-time generator setup + + + 0 + 8 + read-write + + + LOCK + Lock configuration + + + 8 + 2 + read-write + + + B_0x0 + LOCK OFF - No bit is write protected + 0x0 + + + B_0x1 + LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written. + 0x1 + + + B_0x2 + LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. + 0x2 + + + B_0x3 + LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. + 0x3 + + + + + OSSI + Off-state selection for Idle mode + + + 10 + 1 + read-write + + + B_0x0 + When inactive, tim_oc1/tim_oc1n outputs are disabled (tim_oc1/tim_oc1n enable output signal=0) + 0x0 + + + B_0x1 + When inactive, tim_oc1/tim_oc1n outputs are forced first with their idle level as soon as CC1E=1 or CC1NE=1. + 0x1 + + + + + OSSR + Off-state selection for Run mode + + + 11 + 1 + read-write + + + B_0x0 + When inactive, tim_oc1/tim_oc1n outputs are disabled (the timer releases the output control which is taken over by the GPIO, which forces a Hi-Z state) + 0x0 + + + B_0x1 + When inactive, tim_oc1/tim_oc1n outputs are enabled with their inactive level as soon as CC1E=1 or CC1NE=1 (the output is still controlled by the timer). + 0x1 + + + + + BKE + Break enable + + + 12 + 1 + read-write + + + B_0x0 + Break inputs (tim_brk and tim_sys_brk event) disabled + 0x0 + + + + + BKP + Break polarity + + + 13 + 1 + read-write + + + B_0x0 + Break input tim_brk is active low + 0x0 + + + B_0x1 + Break input tim_brk is active high + 0x1 + + + + + AOE + Automatic output enable + + + 14 + 1 + read-write + + + B_0x0 + MOE can be set only by software + 0x0 + + + B_0x1 + MOE can be set by software or automatically at the next update event (if the tim_brk input is not active) + 0x1 + + + + + MOE + Main output enable + + + 15 + 1 + read-write + + + B_0x0 + tim_oc1 and tim_oc1n outputs are disabled or forced to idle state depending on the OSSI bit. + 0x0 + + + B_0x1 + tim_oc1 and tim_oc1n outputs are enabled if their respective enable bits are set (CC1E, CC1NE in TIMx_CCER register) + 0x1 + + + + + BKF + Break filter + + + 16 + 4 + read-write + + + B_0x0 + No filter, tim_brk acts asynchronously + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + BKDSRM + Break Disarm + + + 26 + 1 + read-write + + + B_0x0 + Break input tim_brk is armed + 0x0 + + + B_0x1 + Break input tim_brk is disarmed + 0x1 + + + + + BKBID + Break Bidirectional + + + 28 + 1 + read-write + + + B_0x0 + Break input tim_brk in input mode + 0x0 + + + B_0x1 + Break input tim_brk in bidirectional mode + 0x1 + + + + + + + TIM16_DTR2 + TIM16_DTR2 + TIM16 timer deadtime register 2 + 0x054 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DTGF + Dead-time falling edge generator setup + + + 0 + 8 + read-write + + + DTAE + Deadtime asymmetric enable + + + 16 + 1 + read-write + + + B_0x0 + Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register + 0x0 + + + B_0x1 + Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits. + 0x1 + + + + + DTPE + Deadtime preload enable + + + 17 + 1 + read-write + + + B_0x0 + Deadtime value is not preloaded + 0x0 + + + B_0x1 + Deadtime value preload is enabled + 0x1 + + + + + + + TIM16_TISEL + TIM16_TISEL + TIM16 input selection register + 0x5C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + selects tim_ti1_in[15:0] input + + + 0 + 4 + read-write + + + B_0x0 + TIMx_CH1 input (tim_ti1_in0) + 0x0 + + + B_0x1 + tim_ti1_in1 + 0x1 + + + B_0xF + tim_ti1_in15 + 0xF + + + + + + + TIM16_AF1 + TIM16_AF1 + TIM16 alternate function register 1 + 0x060 + 0x20 + read-write + 0x00000001 + 0xFFFFFFFF + + + BKINE + TIMx_BKIN input enable + + + 0 + 1 + read-write + + + B_0x0 + TIMx_BKIN input disabled + 0x0 + + + B_0x1 + TIMx_BKIN input enabled + 0x1 + + + + + BKCMP1E + tim_brk_cmp1 enable + + + 1 + 1 + read-write + + + B_0x0 + tim_brk_cmp1 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp1 input enabled + 0x1 + + + + + BKCMP2E + tim_brk_cmp2 enable + + + 2 + 1 + read-write + + + B_0x0 + tim_brk_cmp2 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp2 input enabled + 0x1 + + + + + BKCMP3E + tim_brk_cmp3 enable + + + 3 + 1 + read-write + + + B_0x0 + tim_brk_cmp3 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp3 input enabled + 0x1 + + + + + BKCMP4E + tim_brk_cmp4 enable + + + 4 + 1 + read-write + + + B_0x0 + tim_brk_cmp4 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp4 input enabled + 0x1 + + + + + BKCMP5E + tim_brk_cmp5 enable + + + 5 + 1 + read-write + + + B_0x0 + tim_brk_cmp5 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp5 input enabled + 0x1 + + + + + BKCMP6E + tim_brk_cmp6 enable + + + 6 + 1 + read-write + + + B_0x0 + tim_brk_cmp6 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp6 input enabled + 0x1 + + + + + BKCMP7E + tim_brk_cmp7 enable + + + 7 + 1 + read-write + + + B_0x0 + tim_brk_cmp7 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp7 input enabled + 0x1 + + + + + BKCMP8E + tim_brk_cmp8 enable + + + 8 + 1 + read-write + + + B_0x0 + tim_brk_cmp8 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp8 input enabled + 0x1 + + + + + BKINP + TIMx_BKIN input polarity + + + 9 + 1 + read-write + + + B_0x0 + TIMx_BKIN input is active high + 0x0 + + + B_0x1 + TIMx_BKIN input is active low + 0x1 + + + + + BKCMP1P + tim_brk_cmp1 input polarity + + + 10 + 1 + read-write + + + B_0x0 + tim_brk_cmp1 input is active high + 0x0 + + + B_0x1 + tim_brk_cmp1 input is active low + 0x1 + + + + + BKCMP2P + tim_brk_cmp2 input polarity + + + 11 + 1 + read-write + + + B_0x0 + tim_brk_cmp2 input is active high + 0x0 + + + B_0x1 + tim_brk_cmp2 input is active low + 0x1 + + + + + BKCMP3P + tim_brk_cmp3 input polarity + + + 12 + 1 + read-write + + + B_0x0 + tim_brk_cmp3 input is active high + 0x0 + + + B_0x1 + tim_brk_cmp3 input is active low + 0x1 + + + + + BKCMP4P + tim_brk_cmp4 input polarity + + + 13 + 1 + read-write + + + B_0x0 + tim_brk_cmp4 input is active high + 0x0 + + + B_0x1 + tim_brk_cmp4 input is active low + 0x1 + + + + + + + TIM16_AF2 + TIM16_AF2 + TIM16 alternate function register 2 + 0x064 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OCRSEL + tim_ocref_clr source selection + + + 16 + 3 + read-write + + + B_0x0 + tim_ocref_clr0 + 0x0 + + + B_0x1 + tim_ocref_clr1 + 0x1 + + + B_0x2 + tim_ocref_clr2 + 0x2 + + + B_0x3 + tim_ocref_clr3 + 0x3 + + + B_0x4 + tim_ocref_clr4 + 0x4 + + + B_0x5 + tim_ocref_clr5 + 0x5 + + + B_0x6 + tim_ocref_clr6 + 0x6 + + + B_0x7 + tim_ocref_clr7 + 0x7 + + + + + + + TIM16_OR1 + TIM16_OR1 + TIM16 option register 1 + 0x68 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + HSE32EN + HSE Divided by 32 enable + + + 0 + 1 + read-write + + + B_0x0 + HSE divided by 32 disabled + 0x0 + + + B_0x1 + HSE divided by 32 enabled + 0x1 + + + + + + + TIM16_DCR + TIM16_DCR + TIM16 DMA control register + 0x3DC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DBA + DMA base address + + + 0 + 5 + read-write + + + B_0x0 + TIMx_CR1, + 0x0 + + + B_0x1 + TIMx_CR2, + 0x1 + + + B_0x2 + TIMx_SMCR, + 0x2 + + + + + DBL + DMA burst length + + + 8 + 5 + read-write + + + B_0x0 + 1 transfer, + 0x0 + + + B_0x1 + 2 transfers, + 0x1 + + + B_0x2 + 3 transfers, + 0x2 + + + B_0x11 + 18 transfers. + 0x11 + + + + + + + TIM16_DMAR + TIM16_DMAR + TIM16/TIM17 DMA address for full transfer + 0x3E0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DMAB + DMA register for burst accesses + + + 0 + 32 + read-write + + + + + + + TIM17 + 0x40014800 + + + TIM20 + 0x40015000 + + TIM20_BRK + TIM20_BRK + 77 + + + TIM20_UP + TIM20_UP + 78 + + + TIM20_TRG_COM + TIM20_TRG_COM + 79 + + + TIM20_CC + TIM20_CC + 80 + + + + UART4 + Universal synchronous asynchronous receiver transmitter + USART + 0x40004C00 + + 0x0 + 0x400 + registers + + + UART4 + UART4 + 52 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + RXFFIE + RXFFIE + 31 + 1 + + + TXFEIE + TXFEIE + 30 + 1 + + + FIFOEN + FIFOEN + 29 + 1 + + + M1 + M1 + 28 + 1 + + + EOBIE + End of Block interrupt enable + 27 + 1 + + + RTOIE + Receiver timeout interrupt enable + 26 + 1 + + + DEAT4 + Driver Enable assertion time + 25 + 1 + + + DEAT3 + DEAT3 + 24 + 1 + + + DEAT2 + DEAT2 + 23 + 1 + + + DEAT1 + DEAT1 + 22 + 1 + + + DEAT0 + DEAT0 + 21 + 1 + + + DEDT4 + Driver Enable de-assertion time + 20 + 1 + + + DEDT3 + DEDT3 + 19 + 1 + + + DEDT2 + DEDT2 + 18 + 1 + + + DEDT1 + DEDT1 + 17 + 1 + + + DEDT0 + DEDT0 + 16 + 1 + + + OVER8 + Oversampling mode + 15 + 1 + + + CMIE + Character match interrupt enable + 14 + 1 + + + MME + Mute mode enable + 13 + 1 + + + M0 + Word length + 12 + 1 + + + WAKE + Receiver wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXEIE + interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt enable + 6 + 1 + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + UESM + USART enable in Stop mode + 1 + 1 + + + UE + USART enable + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + ADD4_7 + Address of the USART node + 28 + 4 + + + ADD0_3 + Address of the USART node + 24 + 4 + + + RTOEN + Receiver timeout enable + 23 + 1 + + + ABRMOD1 + Auto baud rate mode + 22 + 1 + + + ABRMOD0 + ABRMOD0 + 21 + 1 + + + ABREN + Auto baud rate enable + 20 + 1 + + + MSBFIRST + Most significant bit first + 19 + 1 + + + TAINV + Binary data inversion + 18 + 1 + + + TXINV + TX pin active level inversion + 17 + 1 + + + RXINV + RX pin active level inversion + 16 + 1 + + + SWAP + Swap TX/RX pins + 15 + 1 + + + LINEN + LIN mode enable + 14 + 1 + + + STOP + STOP bits + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CPOL + Clock polarity + 10 + 1 + + + CPHA + Clock phase + 9 + 1 + + + LBCL + Last bit clock pulse + 8 + 1 + + + LBDIE + LIN break detection interrupt enable + 6 + 1 + + + LBDL + LIN break detection length + 5 + 1 + + + ADDM7 + 7-bit Address Detection/4-bit Address Detection + 4 + 1 + + + DIS_NSS + DIS_NSS + 3 + 1 + + + SLVEN + SLVEN + 0 + 1 + + + + + CR3 + CR3 + Control register 3 + 0x8 + 0x20 + read-write + 0x00000000 + + + TXFTCFG + TXFTCFG + 29 + 3 + + + RXFTIE + RXFTIE + 28 + 1 + + + RXFTCFG + RXFTCFG + 25 + 3 + + + TCBGTIE + TCBGTIE + 24 + 1 + + + TXFTIE + TXFTIE + 23 + 1 + + + WUFIE + Wakeup from Stop mode interrupt enable + 22 + 1 + + + WUS + Wakeup from Stop mode interrupt flag selection + 20 + 2 + + + SCARCNT + Smartcard auto-retry count + 17 + 3 + + + DEP + Driver enable polarity selection + 15 + 1 + + + DEM + Driver enable mode + 14 + 1 + + + DDRE + DMA Disable on Reception Error + 13 + 1 + + + OVRDIS + Overrun Disable + 12 + 1 + + + ONEBIT + One sample bit method enable + 11 + 1 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSE + CTS enable + 9 + 1 + + + RTSE + RTS enable + 8 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + DMAR + DMA enable receiver + 6 + 1 + + + SCEN + Smartcard mode enable + 5 + 1 + + + NACK + Smartcard NACK enable + 4 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + IRLP + Ir low-power + 2 + 1 + + + IREN + Ir mode enable + 1 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + + + BRR + BRR + Baud rate register + 0xC + 0x20 + read-write + 0x00000000 + + + DIV_Mantissa + DIV_Mantissa + 4 + 12 + + + DIV_Fraction + DIV_Fraction + 0 + 4 + + + + + GTPR + GTPR + Guard time and prescaler register + 0x10 + 0x20 + read-write + 0x00000000 + + + GT + Guard time value + 8 + 8 + + + PSC + Prescaler value + 0 + 8 + + + + + RTOR + RTOR + Receiver timeout register + 0x14 + 0x20 + read-write + 0x00000000 + + + BLEN + Block Length + 24 + 8 + + + RTO + Receiver timeout value + 0 + 24 + + + + + RQR + RQR + Request register + 0x18 + 0x20 + write-only + 0x00000000 + + + TXFRQ + Transmit data flush request + 4 + 1 + + + RXFRQ + Receive data flush request + 3 + 1 + + + MMRQ + Mute mode request + 2 + 1 + + + SBKRQ + Send break request + 1 + 1 + + + ABRRQ + Auto baud rate request + 0 + 1 + + + + + ISR + ISR + Interrupt & status register + 0x1C + 0x20 + read-only + 0x000000C0 + + + TXFT + TXFT + 27 + 1 + + + RXFT + RXFT + 26 + 1 + + + TCBGT + TCBGT + 25 + 1 + + + RXFF + RXFF + 24 + 1 + + + TXFE + TXFE + 23 + 1 + + + REACK + REACK + 22 + 1 + + + TEACK + TEACK + 21 + 1 + + + WUF + WUF + 20 + 1 + + + RWU + RWU + 19 + 1 + + + SBKF + SBKF + 18 + 1 + + + CMF + CMF + 17 + 1 + + + BUSY + BUSY + 16 + 1 + + + ABRF + ABRF + 15 + 1 + + + ABRE + ABRE + 14 + 1 + + + UDR + UDR + 13 + 1 + + + EOBF + EOBF + 12 + 1 + + + RTOF + RTOF + 11 + 1 + + + CTS + CTS + 10 + 1 + + + CTSIF + CTSIF + 9 + 1 + + + LBDF + LBDF + 8 + 1 + + + TXE + TXE + 7 + 1 + + + TC + TC + 6 + 1 + + + RXNE + RXNE + 5 + 1 + + + IDLE + IDLE + 4 + 1 + + + ORE + ORE + 3 + 1 + + + NF + NF + 2 + 1 + + + FE + FE + 1 + 1 + + + PE + PE + 0 + 1 + + + + + ICR + ICR + Interrupt flag clear register + 0x20 + 0x20 + write-only + 0x00000000 + + + WUCF + Wakeup from Stop mode clear flag + 20 + 1 + + + CMCF + Character match clear flag + 17 + 1 + + + UDRCF + UDRCF + 13 + 1 + + + EOBCF + End of block clear flag + 12 + 1 + + + RTOCF + Receiver timeout clear flag + 11 + 1 + + + CTSCF + CTS clear flag + 9 + 1 + + + LBDCF + LIN break detection clear flag + 8 + 1 + + + TCBGTCF + TCBGTCF + 7 + 1 + + + TCCF + Transmission complete clear flag + 6 + 1 + + + TXFECF + TXFECF + 5 + 1 + + + IDLECF + Idle line detected clear flag + 4 + 1 + + + ORECF + Overrun error clear flag + 3 + 1 + + + NCF + Noise detected clear flag + 2 + 1 + + + FECF + Framing error clear flag + 1 + 1 + + + PECF + Parity error clear flag + 0 + 1 + + + + + RDR + RDR + Receive data register + 0x24 + 0x20 + read-only + 0x00000000 + + + RDR + Receive data value + 0 + 9 + + + + + TDR + TDR + Transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + + + TDR + Transmit data value + 0 + 9 + + + + + PRESC + PRESC + USART prescaler register + 0x2C + 0x20 + read-write + 0x00000000 + + + PRESCALER + PRESCALER + 0 + 4 + + + + + + + UCPD1 + UCPD1 + UCPD + 0x4000A000 + + 0x0 + 0x400 + registers + + + UCPD1 + UCPD1 + 63 + + + + CFG1 + CFG1 + UCPD configuration register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + HBITCLKDIV + HBITCLKDIV + 0 + 6 + + + IFRGAP + IFRGAP + 6 + 5 + + + TRANSWIN + TRANSWIN + 11 + 5 + + + PSC_USBPDCLK + PSC_USBPDCLK + 17 + 3 + + + RXORDSETEN + RXORDSETEN + 20 + 9 + + + TXDMAEN + TXDMAEN + 29 + 1 + + + RXDMAEN + RXDMAEN + 30 + 1 + + + UCPDEN + UCPDEN + 31 + 1 + + + + + CFG2 + CFG2 + UCPD configuration register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + RXFILTDIS + RXFILTDIS + 0 + 1 + + + RXFILT2N3 + RXFILT2N3 + 1 + 1 + + + FORCECLK + FORCECLK + 2 + 1 + + + WUPEN + WUPEN + 3 + 1 + + + + + CR + CR + UCPD configuration register 2 + 0xC + 0x20 + read-write + 0x00000000 + + + TXMODE + TXMODE + 0 + 2 + + + TXSEND + TXSEND + 2 + 1 + + + TXHRST + TXHRST + 3 + 1 + + + RXMODE + RXMODE + 4 + 1 + + + PHYRXEN + PHYRXEN + 5 + 1 + + + PHYCCSEL + PHYCCSEL + 6 + 1 + + + ANASUBMODE + ANASUBMODE + 7 + 2 + + + ANAMODE + ANAMODE + 9 + 1 + + + CCENABLE + CCENABLE + 10 + 2 + + + FRSRXEN + FRSRXEN + 16 + 1 + + + FRSTX + FRSTX + 17 + 1 + + + RDCH + RDCH + 18 + 1 + + + CC1TCDIS + CC1TCDIS + 20 + 1 + + + CC2TCDIS + CC2TCDIS + 21 + 1 + + + + + IMR + IMR + UCPD Interrupt Mask Register + 0x10 + 0x20 + read-write + 0x00000000 + + + TXISIE + TXISIE + 0 + 1 + + + TXMSGDISCIE + TXMSGDISCIE + 1 + 1 + + + TXMSGSENTIE + TXMSGSENTIE + 2 + 1 + + + TXMSGABTIE + TXMSGABTIE + 3 + 1 + + + HRSTDISCIE + HRSTDISCIE + 4 + 1 + + + HRSTSENTIE + HRSTSENTIE + 5 + 1 + + + TXUNDIE + TXUNDIE + 6 + 1 + + + RXNEIE + RXNEIE + 8 + 1 + + + RXORDDETIE + RXORDDETIE + 9 + 1 + + + RXHRSTDETIE + RXHRSTDETIE + 10 + 1 + + + RXOVRIE + RXOVRIE + 11 + 1 + + + RXMSGENDIE + RXMSGENDIE + 12 + 1 + + + TYPECEVT1IE + TYPECEVT1IE + 14 + 1 + + + TYPECEVT2IE + TYPECEVT2IE + 15 + 1 + + + FRSEVTIE + FRSEVTIE + 20 + 1 + + + + + SR + SR + UCPD Status Register + 0x14 + 0x20 + read-write + 0x00000000 + + + TXIS + TXIS + 0 + 1 + + + TXMSGDISC + TXMSGDISC + 1 + 1 + + + TXMSGSENT + TXMSGSENT + 2 + 1 + + + TXMSGABT + TXMSGABT + 3 + 1 + + + HRSTDISC + HRSTDISC + 4 + 1 + + + HRSTSENT + HRSTSENT + 5 + 1 + + + TXUND + TXUND + 6 + 1 + + + RXNE + RXNE + 8 + 1 + + + RXORDDET + RXORDDET + 9 + 1 + + + RXHRSTDET + RXHRSTDET + 10 + 1 + + + RXOVR + RXOVR + 11 + 1 + + + RXMSGEND + RXMSGEND + 12 + 1 + + + RXERR + RXERR + 13 + 1 + + + TYPECEVT1 + TYPECEVT1 + 14 + 1 + + + TYPECEVT2 + TYPECEVT2 + 15 + 1 + + + TYPEC_VSTATE_CC1 + TYPEC_VSTATE_CC1 + 16 + 2 + + + TYPEC_VSTATE_CC2 + TYPEC_VSTATE_CC2 + 18 + 2 + + + FRSEVT + FRSEVT + 20 + 1 + + + + + ICR + ICR + UCPD Interrupt Clear Register + 0x18 + 0x20 + read-write + 0x00000000 + + + TXMSGDISCCF + TXMSGDISCCF + 1 + 1 + + + TXMSGSENTCF + TXMSGSENTCF + 2 + 1 + + + TXMSGABTCF + TXMSGABTCF + 3 + 1 + + + HRSTDISCCF + HRSTDISCCF + 4 + 1 + + + HRSTSENTCF + HRSTSENTCF + 5 + 1 + + + TXUNDCF + TXUNDCF + 6 + 1 + + + RXORDDETCF + RXORDDETCF + 9 + 1 + + + RXHRSTDETCF + RXHRSTDETCF + 10 + 1 + + + RXOVRCF + RXOVRCF + 11 + 1 + + + RXMSGENDCF + RXMSGENDCF + 12 + 1 + + + TYPECEVT1CF + TYPECEVT1CF + 14 + 1 + + + TYPECEVT2CF + TYPECEVT2CF + 15 + 1 + + + FRSEVTCF + FRSEVTCF + 20 + 1 + + + + + TX_ORDSET + TX_ORDSET + UCPD Tx Ordered Set Type Register + 0x1C + 0x20 + read-write + 0x00000000 + + + TXORDSET + TXORDSET + 0 + 20 + + + + + TX_PAYSZ + TX_PAYSZ + UCPD Tx Paysize Register + 0x20 + 0x20 + read-write + 0x00000000 + + + TXPAYSZ + TXPAYSZ + 0 + 10 + + + + + TXDR + TXDR + UCPD Tx Data Register + 0x24 + 0x20 + read-write + 0x00000000 + + + TXDATA + TXDATA + 0 + 8 + + + + + RX_ORDSET + RX_ORDSET + UCPD Rx Ordered Set Register + 0x28 + 0x20 + read-only + 0x00000000 + + + RXORDSET + RXORDSET + 0 + 3 + + + RXSOP3OF4 + RXSOP3OF4 + 3 + 1 + + + RXSOPKINVALID + RXSOPKINVALID + 4 + 3 + + + + + RX_PAYSZ + RX_PAYSZ + UCPD Rx Paysize Register + 0x2C + 0x20 + read-only + 0x00000000 + + + RXPAYSZ + RXPAYSZ + 0 + 10 + + + + + RXDR + RXDR + UCPD Rx Data Register + 0x30 + 0x20 + read-only + 0x00000000 + + + RXDATA + RXDATA + 0 + 8 + + + + + RX_ORDEXT1 + RX_ORDEXT1 + UCPD Rx Ordered Set Extension Register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + RXSOPX1 + RXSOPX1 + 0 + 20 + + + + + RX_ORDEXT2 + RX_ORDEXT2 + UCPD Rx Ordered Set Extension Register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + RXSOPX2 + RXSOPX2 + 0 + 20 + + + + + + + USART1 + Universal synchronous asynchronous receiver transmitter + USART + 0x40013800 + + 0x0 + 0x400 + registers + + + USART1 + USART1 + 37 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + RXFFIE + RXFFIE + 31 + 1 + + + TXFEIE + TXFEIE + 30 + 1 + + + FIFOEN + FIFOEN + 29 + 1 + + + M1 + M1 + 28 + 1 + + + EOBIE + End of Block interrupt enable + 27 + 1 + + + RTOIE + Receiver timeout interrupt enable + 26 + 1 + + + DEAT4 + Driver Enable assertion time + 25 + 1 + + + DEAT3 + DEAT3 + 24 + 1 + + + DEAT2 + DEAT2 + 23 + 1 + + + DEAT1 + DEAT1 + 22 + 1 + + + DEAT0 + DEAT0 + 21 + 1 + + + DEDT4 + Driver Enable de-assertion time + 20 + 1 + + + DEDT3 + DEDT3 + 19 + 1 + + + DEDT2 + DEDT2 + 18 + 1 + + + DEDT1 + DEDT1 + 17 + 1 + + + DEDT0 + DEDT0 + 16 + 1 + + + OVER8 + Oversampling mode + 15 + 1 + + + CMIE + Character match interrupt enable + 14 + 1 + + + MME + Mute mode enable + 13 + 1 + + + M0 + Word length + 12 + 1 + + + WAKE + Receiver wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXEIE + interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt enable + 6 + 1 + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + UESM + USART enable in Stop mode + 1 + 1 + + + UE + USART enable + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + ADD4_7 + Address of the USART node + 28 + 4 + + + ADD0_3 + Address of the USART node + 24 + 4 + + + RTOEN + Receiver timeout enable + 23 + 1 + + + ABRMOD1 + Auto baud rate mode + 22 + 1 + + + ABRMOD0 + ABRMOD0 + 21 + 1 + + + ABREN + Auto baud rate enable + 20 + 1 + + + MSBFIRST + Most significant bit first + 19 + 1 + + + TAINV + Binary data inversion + 18 + 1 + + + TXINV + TX pin active level inversion + 17 + 1 + + + RXINV + RX pin active level inversion + 16 + 1 + + + SWAP + Swap TX/RX pins + 15 + 1 + + + LINEN + LIN mode enable + 14 + 1 + + + STOP + STOP bits + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CPOL + Clock polarity + 10 + 1 + + + CPHA + Clock phase + 9 + 1 + + + LBCL + Last bit clock pulse + 8 + 1 + + + LBDIE + LIN break detection interrupt enable + 6 + 1 + + + LBDL + LIN break detection length + 5 + 1 + + + ADDM7 + 7-bit Address Detection/4-bit Address Detection + 4 + 1 + + + DIS_NSS + DIS_NSS + 3 + 1 + + + SLVEN + SLVEN + 0 + 1 + + + + + CR3 + CR3 + Control register 3 + 0x8 + 0x20 + read-write + 0x00000000 + + + TXFTCFG + TXFTCFG + 29 + 3 + + + RXFTIE + RXFTIE + 28 + 1 + + + RXFTCFG + RXFTCFG + 25 + 3 + + + TCBGTIE + TCBGTIE + 24 + 1 + + + TXFTIE + TXFTIE + 23 + 1 + + + WUFIE + Wakeup from Stop mode interrupt enable + 22 + 1 + + + WUS + Wakeup from Stop mode interrupt flag selection + 20 + 2 + + + SCARCNT + Smartcard auto-retry count + 17 + 3 + + + DEP + Driver enable polarity selection + 15 + 1 + + + DEM + Driver enable mode + 14 + 1 + + + DDRE + DMA Disable on Reception Error + 13 + 1 + + + OVRDIS + Overrun Disable + 12 + 1 + + + ONEBIT + One sample bit method enable + 11 + 1 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSE + CTS enable + 9 + 1 + + + RTSE + RTS enable + 8 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + DMAR + DMA enable receiver + 6 + 1 + + + SCEN + Smartcard mode enable + 5 + 1 + + + NACK + Smartcard NACK enable + 4 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + IRLP + Ir low-power + 2 + 1 + + + IREN + Ir mode enable + 1 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + + + BRR + BRR + Baud rate register + 0xC + 0x20 + read-write + 0x00000000 + + + DIV_Mantissa + DIV_Mantissa + 4 + 12 + + + DIV_Fraction + DIV_Fraction + 0 + 4 + + + + + GTPR + GTPR + Guard time and prescaler register + 0x10 + 0x20 + read-write + 0x00000000 + + + GT + Guard time value + 8 + 8 + + + PSC + Prescaler value + 0 + 8 + + + + + RTOR + RTOR + Receiver timeout register + 0x14 + 0x20 + read-write + 0x00000000 + + + BLEN + Block Length + 24 + 8 + + + RTO + Receiver timeout value + 0 + 24 + + + + + RQR + RQR + Request register + 0x18 + 0x20 + write-only + 0x00000000 + + + TXFRQ + Transmit data flush request + 4 + 1 + + + RXFRQ + Receive data flush request + 3 + 1 + + + MMRQ + Mute mode request + 2 + 1 + + + SBKRQ + Send break request + 1 + 1 + + + ABRRQ + Auto baud rate request + 0 + 1 + + + + + ISR + ISR + Interrupt & status register + 0x1C + 0x20 + read-only + 0x00000000 + + + TXFT + TXFT + 27 + 1 + + + RXFT + RXFT + 26 + 1 + + + TCBGT + TCBGT + 25 + 1 + + + RXFF + RXFF + 24 + 1 + + + TXFE + TXFE + 23 + 1 + + + REACK + REACK + 22 + 1 + + + TEACK + TEACK + 21 + 1 + + + WUF + WUF + 20 + 1 + + + RWU + RWU + 19 + 1 + + + SBKF + SBKF + 18 + 1 + + + CMF + CMF + 17 + 1 + + + BUSY + BUSY + 16 + 1 + + + ABRF + ABRF + 15 + 1 + + + ABRE + ABRE + 14 + 1 + + + UDR + UDR + 13 + 1 + + + EOBF + EOBF + 12 + 1 + + + RTOF + RTOF + 11 + 1 + + + CTS + CTS + 10 + 1 + + + CTSIF + CTSIF + 9 + 1 + + + LBDF + LBDF + 8 + 1 + + + TXE + TXE + 7 + 1 + + + TC + TC + 6 + 1 + + + RXNE + RXNE + 5 + 1 + + + IDLE + IDLE + 4 + 1 + + + ORE + ORE + 3 + 1 + + + NF + NF + 2 + 1 + + + FE + FE + 1 + 1 + + + PE + PE + 0 + 1 + + + + + ICR + ICR + Interrupt flag clear register + 0x20 + 0x20 + write-only + 0x00000000 + + + WUCF + Wakeup from Stop mode clear flag + 20 + 1 + + + CMCF + Character match clear flag + 17 + 1 + + + UDRCF + UDRCF + 13 + 1 + + + EOBCF + End of block clear flag + 12 + 1 + + + RTOCF + Receiver timeout clear flag + 11 + 1 + + + CTSCF + CTS clear flag + 9 + 1 + + + LBDCF + LIN break detection clear flag + 8 + 1 + + + TCBGTCF + TCBGTCF + 7 + 1 + + + TCCF + Transmission complete clear flag + 6 + 1 + + + TXFECF + TXFECF + 5 + 1 + + + IDLECF + Idle line detected clear flag + 4 + 1 + + + ORECF + Overrun error clear flag + 3 + 1 + + + NCF + Noise detected clear flag + 2 + 1 + + + FECF + Framing error clear flag + 1 + 1 + + + PECF + Parity error clear flag + 0 + 1 + + + + + RDR + RDR + Receive data register + 0x24 + 0x20 + read-only + 0x00000000 + + + RDR + Receive data value + 0 + 9 + + + + + TDR + TDR + Transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + + + TDR + Transmit data value + 0 + 9 + + + + + PRESC + PRESC + USART prescaler register + 0x2C + 0x20 + read-write + 0x00000000 + + + PRESCALER + PRESCALER + 0 + 4 + + + + + + + USART2 + 0x40004400 + + USART2 + USART2 + 38 + + + + USART3 + 0x40004800 + + USART3 + USART3 + 39 + + + + USB_FS_device + USB_FS_device + USB + 0x40005C00 + + 0x0 + 0x400 + registers + + + USB_HP + USB_HP + 19 + + + USB_LP + USB_LP + 20 + + + USBWakeUP + USBWakeUP + 42 + + + + EP0R + EP0R + USB endpoint n register + 0x0 + 0x20 + read-write + 0x00000000 + + + EA + EA + 0 + 4 + + + STAT_TX + STAT_TX + 4 + 2 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + EP_KIND + EP_KIND + 8 + 1 + + + EP_TYPE + EP_TYPE + 9 + 2 + + + SETUP + SETUP + 11 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + CTR_RX + CTR_RX + 15 + 1 + + + + + EP1R + EP1R + USB endpoint n register + 0x4 + 0x20 + read-write + 0x00000000 + + + EA + EA + 0 + 4 + + + STAT_TX + STAT_TX + 4 + 2 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + EP_KIND + EP_KIND + 8 + 1 + + + EP_TYPE + EP_TYPE + 9 + 2 + + + SETUP + SETUP + 11 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + CTR_RX + CTR_RX + 15 + 1 + + + + + EP2R + EP2R + USB endpoint n register + 0x8 + 0x20 + read-write + 0x00000000 + + + EA + EA + 0 + 4 + + + STAT_TX + STAT_TX + 4 + 2 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + EP_KIND + EP_KIND + 8 + 1 + + + EP_TYPE + EP_TYPE + 9 + 2 + + + SETUP + SETUP + 11 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + CTR_RX + CTR_RX + 15 + 1 + + + + + EP3R + EP3R + USB endpoint n register + 0xC + 0x20 + read-write + 0x00000000 + + + EA + EA + 0 + 4 + + + STAT_TX + STAT_TX + 4 + 2 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + EP_KIND + EP_KIND + 8 + 1 + + + EP_TYPE + EP_TYPE + 9 + 2 + + + SETUP + SETUP + 11 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + CTR_RX + CTR_RX + 15 + 1 + + + + + EP4R + EP4R + USB endpoint n register + 0x10 + 0x20 + read-write + 0x00000000 + + + EA + EA + 0 + 4 + + + STAT_TX + STAT_TX + 4 + 2 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + EP_KIND + EP_KIND + 8 + 1 + + + EP_TYPE + EP_TYPE + 9 + 2 + + + SETUP + SETUP + 11 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + CTR_RX + CTR_RX + 15 + 1 + + + + + EP5R + EP5R + USB endpoint n register + 0x14 + 0x20 + read-write + 0x00000000 + + + EA + EA + 0 + 4 + + + STAT_TX + STAT_TX + 4 + 2 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + EP_KIND + EP_KIND + 8 + 1 + + + EP_TYPE + EP_TYPE + 9 + 2 + + + SETUP + SETUP + 11 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + CTR_RX + CTR_RX + 15 + 1 + + + + + EP6R + EP6R + USB endpoint n register + 0x18 + 0x20 + read-write + 0x00000000 + + + EA + EA + 0 + 4 + + + STAT_TX + STAT_TX + 4 + 2 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + EP_KIND + EP_KIND + 8 + 1 + + + EP_TYPE + EP_TYPE + 9 + 2 + + + SETUP + SETUP + 11 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + CTR_RX + CTR_RX + 15 + 1 + + + + + EP7R + EP7R + USB endpoint n register + 0x1C + 0x20 + read-write + 0x00000000 + + + EA + EA + 0 + 4 + + + STAT_TX + STAT_TX + 4 + 2 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + EP_KIND + EP_KIND + 8 + 1 + + + EP_TYPE + EP_TYPE + 9 + 2 + + + SETUP + SETUP + 11 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + CTR_RX + CTR_RX + 15 + 1 + + + + + CNTR + CNTR + USB control register + 0x40 + 0x20 + read-write + 0x00000000 + + + FRES + FRES + 0 + 1 + + + PDWN + PDWN + 1 + 1 + + + LP_MODE + LP_MODE + 2 + 1 + + + FSUSP + FSUSP + 3 + 1 + + + RESUME + RESUME + 4 + 1 + + + L1RESUME + L1RESUME + 5 + 1 + + + L1REQM + L1REQM + 7 + 1 + + + ESOFM + ESOFM + 8 + 1 + + + SOFM + SOFM + 9 + 1 + + + RESETM + RESETM + 10 + 1 + + + SUSPM + SUSPM + 11 + 1 + + + WKUPM + WKUPM + 12 + 1 + + + ERRM + ERRM + 13 + 1 + + + PMAOVRM + PMAOVRM + 14 + 1 + + + CTRM + CTRM + 15 + 1 + + + + + ISTR + ISTR + USB interrupt status register + 0x44 + 0x20 + read-write + 0x00000000 + + + EP_ID + EP_ID + 0 + 4 + + + DIR + DIR + 4 + 1 + + + L1REQ + L1REQ + 7 + 1 + + + ESOF + ESOF + 8 + 1 + + + SOF + SOF + 9 + 1 + + + RESET + RESET + 10 + 1 + + + SUSP + SUSP + 11 + 1 + + + WKUP + WKUP + 12 + 1 + + + ERR + ERR + 13 + 1 + + + PMAOVR + PMAOVR + 14 + 1 + + + CTR + CTR + 15 + 1 + + + + + FNR + FNR + USB frame number register + 0x48 + 0x20 + read-only + 0x00000000 + + + FN + FN + 0 + 11 + + + LSOF + LSOF + 11 + 2 + + + LCK + LCK + 13 + 1 + + + RXDM + RXDM + 14 + 1 + + + RXDP + RXDP + 15 + 1 + + + + + DADDR + DADDR + USB device address + 0x4C + 0x20 + read-write + 0x00000000 + + + ADD + ADD + 0 + 7 + + + EF + EF + 7 + 1 + + + + + BTABLE + BTABLE + Buffer table address + 0x50 + 0x20 + read-write + 0x00000000 + + + BTABLE + BTABLE + 3 + 13 + + + + + + + VREFBUF + Voltage reference buffer + VREFBUF + 0x40010030 + + 0x0 + 0x1D0 + registers + + + + VREFBUF_CSR + VREFBUF_CSR + VREF_BUF Control and Status Register + 0x0 + 0x20 + 0x00000002 + + + ENVR + Enable Voltage Reference + 0 + 1 + read-write + + + HIZ + High impedence mode for the VREF_BUF + 1 + 1 + read-write + + + VRR + Voltage reference buffer ready + 3 + 1 + read-only + + + VRS + Voltage reference scale + 4 + 2 + read-write + + + + + VREFBUF_CCR + VREFBUF_CCR + VREF_BUF Calibration Control Register + 0x04 + 0x20 + read-write + 0x00000000 + + + TRIM + Trimming code + 0 + 6 + + + + + + + WWDG + System window watchdog + WWDG + 0x40002C00 + + 0x0 + 0x400 + registers + + + WWDG + Window Watchdog interrupt + 0 + + + + CR + CR + Control register + 0x0 + 0x20 + read-write + 0x0000007F + + + WDGA + Activation bit + 7 + 1 + + + T + 7-bit counter (MSB to LSB) + 0 + 7 + + + + + CFR + CFR + Configuration register + 0x4 + 0x20 + read-write + 0x0000007F + + + WDGTB + Timer base + 11 + 3 + + + EWI + Early wakeup interrupt + 9 + 1 + + + W + 7-bit window value + 0 + 7 + + + + + SR + SR + Status register + 0x8 + 0x20 + read-write + 0x00000000 + + + EWIF + Early wakeup interrupt flag + 0 + 1 + + + + + + + diff --git a/Lib/Vendor/SVD/STM32G474.svd b/Lib/Vendor/SVD/STM32G474.svd new file mode 100644 index 000000000..b9db130f6 --- /dev/null +++ b/Lib/Vendor/SVD/STM32G474.svd @@ -0,0 +1,63342 @@ + + + + STM32G474 + 2.1 + STM32G474 + + CM4 + r0p1 + little + true + true + 4 + false + + 8 + 32 + 0x20 + 0x0 + 0xFFFFFFFF + + + CRC + Cyclic redundancy check calculation unit + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DR + DR + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DR + Data register bits + 0 + 32 + + + + + IDR + IDR + Independent data register + 0x4 + 0x20 + read-write + 0x00000000 + + + IDR + General-purpose 8-bit data register bits + 0 + 32 + + + + + CR + CR + Control register + 0x8 + 0x20 + 0x00000000 + + + REV_OUT + Reverse output data + 7 + 1 + read-write + + + REV_IN + Reverse input data + 5 + 2 + read-write + + + POLYSIZE + Polynomial size + 3 + 2 + read-write + + + RESET + RESET bit + 0 + 1 + write-only + + + + + INIT + INIT + Initial CRC value + 0x10 + 0x20 + read-write + 0xFFFFFFFF + + + CRC_INIT + Programmable initial CRC value + 0 + 32 + + + + + POL + POL + polynomial + 0x14 + 0x20 + read-write + 0x04C11DB7 + + + POL + Programmable polynomial + 0 + 32 + + + + + + + IWDG + WinWATCHDOG + IWDG + 0x40003000 + + 0x0 + 0x400 + registers + + + + KR + KR + Key register + 0x0 + 0x20 + write-only + 0x00000000 + + + KEY + Key value (write only, read 0x0000) + 0 + 16 + + + + + PR + PR + Prescaler register + 0x4 + 0x20 + read-write + 0x00000000 + + + PR + Prescaler divider + 0 + 3 + + + + + RLR + RLR + Reload register + 0x8 + 0x20 + read-write + 0x00000FFF + + + RL + Watchdog counter reload value + 0 + 12 + + + + + SR + SR + Status register + 0xC + 0x20 + read-only + 0x00000000 + + + WVU + Watchdog counter window value update + 2 + 1 + + + RVU + Watchdog counter reload value update + 1 + 1 + + + PVU + Watchdog prescaler value update + 0 + 1 + + + + + WINR + WINR + Window register + 0x10 + 0x20 + read-write + 0x00000FFF + + + WIN + Watchdog counter window value + 0 + 12 + + + + + + + WWDG + System window watchdog + WWDG + 0x40002C00 + + 0x0 + 0x400 + registers + + + + CR + CR + Control register + 0x0 + 0x20 + read-write + 0x0000007F + + + WDGA + Activation bit + 7 + 1 + + + T + 7-bit counter (MSB to LSB) + 0 + 7 + + + + + CFR + CFR + Configuration register + 0x4 + 0x20 + read-write + 0x0000007F + + + WDGTB + Timer base + 11 + 3 + + + EWI + Early wakeup interrupt + 9 + 1 + + + W + 7-bit window value + 0 + 7 + + + + + SR + SR + Status register + 0x8 + 0x20 + read-write + 0x00000000 + + + EWIF + Early wakeup interrupt flag + 0 + 1 + + + + + + + I2C1 + Inter-integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1_EV + I2C1_EV + 31 + + + I2C1_ER + I2C1_ER + 32 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + PE + Peripheral enable + 0 + 1 + + + TXIE + TX Interrupt enable + 1 + 1 + + + RXIE + RX Interrupt enable + 2 + 1 + + + ADDRIE + Address match interrupt enable (slave only) + 3 + 1 + + + NACKIE + Not acknowledge received interrupt enable + 4 + 1 + + + STOPIE + STOP detection Interrupt enable + 5 + 1 + + + TCIE + Transfer Complete interrupt enable + 6 + 1 + + + ERRIE + Error interrupts enable + 7 + 1 + + + DNF + Digital noise filter + 8 + 4 + + + ANFOFF + Analog noise filter OFF + 12 + 1 + + + TXDMAEN + DMA transmission requests enable + 14 + 1 + + + RXDMAEN + DMA reception requests enable + 15 + 1 + + + SBC + Slave byte control + 16 + 1 + + + NOSTRETCH + Clock stretching disable + 17 + 1 + + + WUPEN + Wakeup from STOP enable + 18 + 1 + + + GCEN + General call enable + 19 + 1 + + + SMBHEN + SMBus Host address enable + 20 + 1 + + + SMBDEN + SMBus Device Default address enable + 21 + 1 + + + ALERTEN + SMBUS alert enable + 22 + 1 + + + PECEN + PEC enable + 23 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + PECBYTE + Packet error checking byte + 26 + 1 + + + AUTOEND + Automatic end mode (master mode) + 25 + 1 + + + RELOAD + NBYTES reload mode + 24 + 1 + + + NBYTES + Number of bytes + 16 + 8 + + + NACK + NACK generation (slave mode) + 15 + 1 + + + STOP + Stop generation (master mode) + 14 + 1 + + + START + Start generation + 13 + 1 + + + HEAD10R + 10-bit address header only read direction (master receiver mode) + 12 + 1 + + + ADD10 + 10-bit addressing mode (master mode) + 11 + 1 + + + RD_WRN + Transfer direction (master mode) + 10 + 1 + + + SADD + Slave address bit (master mode) + 0 + 10 + + + + + OAR1 + OAR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x00000000 + + + OA1 + Interface address + 0 + 10 + + + OA1MODE + Own Address 1 10-bit mode + 10 + 1 + + + OA1EN + Own Address 1 enable + 15 + 1 + + + + + OAR2 + OAR2 + Own address register 2 + 0xC + 0x20 + read-write + 0x00000000 + + + OA2 + Interface address + 1 + 7 + + + OA2MSK + Own Address 2 masks + 8 + 3 + + + OA2EN + Own Address 2 enable + 15 + 1 + + + + + TIMINGR + TIMINGR + Timing register + 0x10 + 0x20 + read-write + 0x00000000 + + + SCLL + SCL low period (master mode) + 0 + 8 + + + SCLH + SCL high period (master mode) + 8 + 8 + + + SDADEL + Data hold time + 16 + 4 + + + SCLDEL + Data setup time + 20 + 4 + + + PRESC + Timing prescaler + 28 + 4 + + + + + TIMEOUTR + TIMEOUTR + Status register 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + TIMEOUTA + Bus timeout A + 0 + 12 + + + TIDLE + Idle clock timeout detection + 12 + 1 + + + TIMOUTEN + Clock timeout enable + 15 + 1 + + + TIMEOUTB + Bus timeout B + 16 + 12 + + + TEXTEN + Extended clock timeout enable + 31 + 1 + + + + + ISR + ISR + Interrupt and Status register + 0x18 + 0x20 + 0x00000001 + + + ADDCODE + Address match code (Slave mode) + 17 + 7 + read-only + + + DIR + Transfer direction (Slave mode) + 16 + 1 + read-only + + + BUSY + Bus busy + 15 + 1 + read-only + + + ALERT + SMBus alert + 13 + 1 + read-only + + + TIMEOUT + Timeout or t_low detection flag + 12 + 1 + read-only + + + PECERR + PEC Error in reception + 11 + 1 + read-only + + + OVR + Overrun/Underrun (slave mode) + 10 + 1 + read-only + + + ARLO + Arbitration lost + 9 + 1 + read-only + + + BERR + Bus error + 8 + 1 + read-only + + + TCR + Transfer Complete Reload + 7 + 1 + read-only + + + TC + Transfer Complete (master mode) + 6 + 1 + read-only + + + STOPF + Stop detection flag + 5 + 1 + read-only + + + NACKF + Not acknowledge received flag + 4 + 1 + read-only + + + ADDR + Address matched (slave mode) + 3 + 1 + read-only + + + RXNE + Receive data register not empty (receivers) + 2 + 1 + read-only + + + TXIS + Transmit interrupt status (transmitters) + 1 + 1 + read-write + + + TXE + Transmit data register empty (transmitters) + 0 + 1 + read-write + + + + + ICR + ICR + Interrupt clear register + 0x1C + 0x20 + write-only + 0x00000000 + + + ALERTCF + Alert flag clear + 13 + 1 + + + TIMOUTCF + Timeout detection flag clear + 12 + 1 + + + PECCF + PEC Error flag clear + 11 + 1 + + + OVRCF + Overrun/Underrun flag clear + 10 + 1 + + + ARLOCF + Arbitration lost flag clear + 9 + 1 + + + BERRCF + Bus error flag clear + 8 + 1 + + + STOPCF + Stop detection flag clear + 5 + 1 + + + NACKCF + Not Acknowledge flag clear + 4 + 1 + + + ADDRCF + Address Matched flag clear + 3 + 1 + + + + + PECR + PECR + PEC register + 0x20 + 0x20 + read-only + 0x00000000 + + + PEC + Packet error checking register + 0 + 8 + + + + + RXDR + RXDR + Receive data register + 0x24 + 0x20 + read-only + 0x00000000 + + + RXDATA + 8-bit receive data + 0 + 8 + + + + + TXDR + TXDR + Transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + + + TXDATA + 8-bit transmit data + 0 + 8 + + + + + + + I2C2 + 0x40005800 + + WWDG + Window Watchdog interrupt + 0 + + + I2C2_EV + I2C2_EV + 33 + + + I2C2_ER + I2C2_ER + 34 + + + + I2C3 + 0x40007800 + + I2C3_EV + I2C3_EV + 92 + + + I2C3_ER + I2C3_ER + 93 + + + + I2C4 + 0x40008400 + + I2C4_EV + I2C4_EV + 82 + + + I2C4_ER + I2C4_ER + 83 + + + + FLASH + Flash + Flash + 0x40022000 + + 0x0 + 0x400 + registers + + + FLASH + FLASH + 4 + + + + ACR + ACR + Access control register + 0x0 + 0x20 + read-write + 0x00000600 + + + LATENCY + Latency + 0 + 4 + + + PRFTEN + Prefetch enable + 8 + 1 + + + ICEN + Instruction cache enable + 9 + 1 + + + DCEN + Data cache enable + 10 + 1 + + + ICRST + Instruction cache reset + 11 + 1 + + + DCRST + Data cache reset + 12 + 1 + + + RUN_PD + Flash Power-down mode during Low-power run mode + 13 + 1 + + + SLEEP_PD + Flash Power-down mode during Low-power sleep mode + 14 + 1 + + + DBG_SWEN + Debug software enable + 18 + 1 + + + + + PDKEYR + PDKEYR + Power down key register + 0x4 + 0x20 + write-only + 0x00000000 + + + PDKEYR + RUN_PD in FLASH_ACR key + 0 + 32 + + + + + KEYR + KEYR + Flash key register + 0x8 + 0x20 + write-only + 0x00000000 + + + KEYR + KEYR + 0 + 32 + + + + + OPTKEYR + OPTKEYR + Option byte key register + 0xC + 0x20 + write-only + 0x00000000 + + + OPTKEYR + Option byte key + 0 + 32 + + + + + SR + SR + Status register + 0x10 + 0x20 + 0x00000000 + + + EOP + End of operation + 0 + 1 + read-write + + + OPERR + Operation error + 1 + 1 + read-write + + + PROGERR + Programming error + 3 + 1 + read-write + + + WRPERR + Write protected error + 4 + 1 + read-write + + + PGAERR + Programming alignment error + 5 + 1 + read-write + + + SIZERR + Size error + 6 + 1 + read-write + + + PGSERR + Programming sequence error + 7 + 1 + read-write + + + MISERR + Fast programming data miss error + 8 + 1 + read-write + + + FASTERR + Fast programming error + 9 + 1 + read-write + + + RDERR + PCROP read error + 14 + 1 + read-write + + + OPTVERR + Option validity error + 15 + 1 + read-write + + + BSY + Busy + 16 + 1 + read-only + + + + + CR + CR + Flash control register + 0x14 + 0x20 + read-write + 0xC0000000 + + + PG + Programming + 0 + 1 + + + PER + Page erase + 1 + 1 + + + MER1 + Bank 1 Mass erase + 2 + 1 + + + PNB + Page number + 3 + 7 + + + STRT + Start + 16 + 1 + + + OPTSTRT + Options modification start + 17 + 1 + + + FSTPG + Fast programming + 18 + 1 + + + EOPIE + End of operation interrupt enable + 24 + 1 + + + ERRIE + Error interrupt enable + 25 + 1 + + + RDERRIE + PCROP read error interrupt enable + 26 + 1 + + + OBL_LAUNCH + Force the option byte loading + 27 + 1 + + + SEC_PROT1 + SEC_PROT1 + 28 + 1 + + + OPTLOCK + Options Lock + 30 + 1 + + + LOCK + FLASH_CR Lock + 31 + 1 + + + + + ECCR + ECCR + Flash ECC register + 0x18 + 0x20 + 0x00000000 + + + ADDR_ECC + ECC fail address + 0 + 19 + read-only + + + BK_ECC + BK_ECC + 21 + 1 + read-only + + + SYSF_ECC + SYSF_ECC + 22 + 1 + read-only + + + ECCIE + ECCIE + 24 + 1 + read-write + + + ECCC2 + ECC correction + 28 + 1 + read-write + + + ECCD2 + ECC2 detection + 29 + 1 + read-write + + + ECCC + ECC correction + 30 + 1 + read-write + + + ECCD + ECC detection + 31 + 1 + read-write + + + + + OPTR + OPTR + Flash option register + 0x20 + 0x20 + read-write + 0xF0000000 + + + RDP + Read protection level + 0 + 8 + + + BOR_LEV + BOR reset Level + 8 + 3 + + + nRST_STOP + nRST_STOP + 12 + 1 + + + nRST_STDBY + nRST_STDBY + 13 + 1 + + + nRST_SHDW + nRST_SHDW + 14 + 1 + + + IDWG_SW + Independent watchdog selection + 16 + 1 + + + IWDG_STOP + Independent watchdog counter freeze in Stop mode + 17 + 1 + + + IWDG_STDBY + Independent watchdog counter freeze in Standby mode + 18 + 1 + + + WWDG_SW + Window watchdog selection + 19 + 1 + + + nBOOT1 + Boot configuration + 23 + 1 + + + SRAM2_PE + SRAM2 parity check enable + 24 + 1 + + + SRAM2_RST + SRAM2 Erase when system reset + 25 + 1 + + + nSWBOOT0 + nSWBOOT0 + 26 + 1 + + + nBOOT0 + nBOOT0 + 27 + 1 + + + NRST_MODE + NRST_MODE + 28 + 2 + + + IRHEN + IRHEN + 30 + 1 + + + + + PCROP1SR + PCROP1SR + Flash Bank 1 PCROP Start address register + 0x24 + 0x20 + read-write + 0xFFFF0000 + + + PCROP1_STRT + Bank 1 PCROP area start offset + 0 + 15 + + + + + PCROP1ER + PCROP1ER + Flash Bank 1 PCROP End address register + 0x28 + 0x20 + read-write + 0x0FFF0000 + + + PCROP1_END + Bank 1 PCROP area end offset + 0 + 15 + + + PCROP_RDP + PCROP area preserved when RDP level decreased + 31 + 1 + + + + + WRP1AR + WRP1AR + Flash Bank 1 WRP area A address register + 0x2C + 0x20 + read-write + 0x00000000 + + + WRP1A_STRT + Bank 1 WRP first area start offset + 0 + 7 + + + WRP1A_END + Bank 1 WRP first area A end offset + 16 + 7 + + + + + WRP1BR + WRP1BR + Flash Bank 1 WRP area B address register + 0x30 + 0x20 + read-write + 0x00000000 + + + WRP1B_STRT + Bank 1 WRP second area B end offset + 0 + 7 + + + WRP1B_END + Bank 1 WRP second area B start offset + 16 + 7 + + + + + SEC1R + SEC1R + securable area bank1 register + 0x70 + 0x20 + read-write + 0xFF00FF00 + + + BOOT_LOCK + BOOT_LOCK + 16 + 1 + + + SEC_SIZE1 + SEC_SIZE1 + 0 + 8 + + + + + + + DBGMCU + Debug support + DBGMCU + 0xE0042000 + + 0x0 + 0x400 + registers + + + + IDCODE + IDCODE + MCU Device ID Code Register + 0x0 + 0x20 + read-only + 0x0 + + + DEV_ID + Device Identifier + 0 + 16 + + + REV_ID + Revision Identifier + 16 + 16 + + + + + CR + CR + Debug MCU Configuration Register + 0x4 + 0x20 + read-write + 0x0 + + + DBG_SLEEP + Debug Sleep Mode + 0 + 1 + + + DBG_STOP + Debug Stop Mode + 1 + 1 + + + DBG_STANDBY + Debug Standby Mode + 2 + 1 + + + TRACE_IOEN + Trace pin assignment control + 5 + 1 + + + TRACE_MODE + Trace pin assignment control + 6 + 2 + + + + + APB1L_FZ + APB1L_FZ + APB Low Freeze Register 1 + 0x8 + 0x20 + read-write + 0x0 + + + DBG_TIMER2_STOP + Debug Timer 2 stopped when Core is halted + 0 + 1 + + + DBG_TIM3_STOP + TIM3 counter stopped when core is halted + 1 + 1 + + + DBG_TIM4_STOP + TIM4 counter stopped when core is halted + 2 + 1 + + + DBG_TIM5_STOP + TIM5 counter stopped when core is halted + 3 + 1 + + + DBG_TIMER6_STOP + Debug Timer 6 stopped when Core is halted + 4 + 1 + + + DBG_TIM7_STOP + TIM7 counter stopped when core is halted + 5 + 1 + + + DBG_RTC_STOP + Debug RTC stopped when Core is halted + 10 + 1 + + + DBG_WWDG_STOP + Debug Window Wachdog stopped when Core is halted + 11 + 1 + + + DBG_IWDG_STOP + Debug Independent Wachdog stopped when Core is halted + 12 + 1 + + + DBG_I2C1_STOP + I2C1 SMBUS timeout mode stopped when core is halted + 21 + 1 + + + DBG_I2C2_STOP + I2C2 SMBUS timeout mode stopped when core is halted + 22 + 1 + + + DBG_I2C3_STOP + I2C3 SMBUS timeout mode stopped when core is halted + 30 + 1 + + + DBG_LPTIMER_STOP + LPTIM1 counter stopped when core is halted + 31 + 1 + + + + + APB1H_FZ + APB1H_FZ + APB Low Freeze Register 2 + 0xC + 0x20 + read-write + 0x0 + + + DBG_I2C4_STOP + DBG_I2C4_STOP + 1 + 1 + + + + + APB2_FZ + APB2_FZ + APB High Freeze Register + 0x10 + 0x20 + read-write + 0x0 + + + DBG_TIM1_STOP + TIM1 counter stopped when core is halted + 11 + 1 + + + DBG_TIM8_STOP + TIM8 counter stopped when core is halted + 13 + 1 + + + DBG_TIM15_STOP + TIM15 counter stopped when core is halted + 16 + 1 + + + DBG_TIM16_STOP + TIM16 counter stopped when core is halted + 17 + 1 + + + DBG_TIM17_STOP + TIM17 counter stopped when core is halted + 18 + 1 + + + DBG_TIM20_STOP + TIM20counter stopped when core is halted + 20 + 1 + + + DBG_HRTIM0_STOP + DBG_HRTIM0_STOP + 26 + 1 + + + DBG_HRTIM1_STOP + DBG_HRTIM0_STOP + 27 + 1 + + + DBG_HRTIM2_STOP + DBG_HRTIM0_STOP + 28 + 1 + + + DBG_HRTIM3_STOP + DBG_HRTIM0_STOP + 29 + 1 + + + + + + + RCC + Reset and clock control + RCC + 0x40021000 + + 0x0 + 0x400 + registers + + + RCC + RCC global interrupt + 5 + + + + RCC_CR + RCC_CR + Clock control register + 0x00 + 0x20 + 0x00000063 + 0xFFFFFFFF + + + HSION + HSI16 clock enable +Set and cleared by software. +Cleared by hardware to stop the HSI16 oscillator when entering Stop, Standby or Shutdown mode. +Set by hardware to force the HSI16 oscillator ON when STOPWUCK=1 or HSIASFS = 1 when leaving Stop modes, or in case of failure of the HSE crystal oscillator. +This bit is set by hardware if the HSI16 is used directly or indirectly as system clock. + 8 + 1 + read-write + + + B_0x0 + HSI16 oscillator OFF + 0x0 + + + B_0x1 + HSI16 oscillator ON + 0x1 + + + + + HSIKERON + HSI16 always enable for peripheral kernels. +Set and cleared by software to force HSI16 ON even in Stop modes. The HSI16 can only feed USARTs and I<sup>2</sup>Cs peripherals configured with HSI16 as kernel clock. Keeping the HSI16 ON in Stop mode allows to avoid slowing down the communication speed because of the HSI16 startup time. This bit has no effect on HSION value. + 9 + 1 + read-write + + + B_0x0 + No effect on HSI16 oscillator. + 0x0 + + + B_0x1 + HSI16 oscillator is forced ON even in Stop mode. + 0x1 + + + + + HSIRDY + HSI16 clock ready flag +Set by hardware to indicate that HSI16 oscillator is stable. This bit is set only when HSI16 is enabled by software by setting HSION. +Note: Once the HSION bit is cleared, HSIRDY goes low after 6 HSI16 clock cycles. + 10 + 1 + read-only + + + B_0x0 + HSI16 oscillator not ready + 0x0 + + + B_0x1 + HSI16 oscillator ready + 0x1 + + + + + HSEON + HSE clock enable +Set and cleared by software. +Cleared by hardware to stop the HSE oscillator when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock. + 16 + 1 + read-write + + + B_0x0 + HSE oscillator OFF + 0x0 + + + B_0x1 + HSE oscillator ON + 0x1 + + + + + HSERDY + HSE clock ready flag +Set by hardware to indicate that the HSE oscillator is stable. +Note: Once the HSEON bit is cleared, HSERDY goes low after 6 HSE clock cycles. + 17 + 1 + read-only + + + B_0x0 + HSE oscillator not ready + 0x0 + + + B_0x1 + HSE oscillator ready + 0x1 + + + + + HSEBYP + HSE crystal oscillator bypass +Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled. + 18 + 1 + read-write + + + B_0x0 + HSE crystal oscillator not bypassed + 0x0 + + + B_0x1 + HSE crystal oscillator bypassed with external clock + 0x1 + + + + + CSSON + Clock security system enable +Set by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset. + 19 + 1 + read-write + + + B_0x0 + Clock security system OFF (clock detector OFF) + 0x0 + + + B_0x1 + Clock security system ON (Clock detector ON if the HSE oscillator is stable, OFF if not). + 0x1 + + + + + PLLON + Main PLL enable +Set and cleared by software to enable the main PLL. +Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the PLL clock is used as the system clock. + 24 + 1 + read-write + + + B_0x0 + PLL OFF + 0x0 + + + B_0x1 + PLL ON + 0x1 + + + + + PLLRDY + Main PLL clock ready flag +Set by hardware to indicate that the main PLL is locked. + 25 + 1 + read-only + + + B_0x0 + PLL unlocked + 0x0 + + + B_0x1 + PLL locked + 0x1 + + + + + + + RCC_ICSCR + RCC_ICSCR + Internal clock sources calibration register + 0x04 + 0x20 + 0x40000000 + 0xFFFFFFFF + + + HSICAL + HSI16 clock calibration +These bits are initialized at startup with the factory-programmed HSI16 calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value. + 16 + 8 + read-only + + + HSITRIM + HSI16 clock trimming +These bits provide an additional user-programmable trimming value that is added to the HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI16. +The default value is 16, which, when added to the HSICAL value, should trim the HSI16 to 16 MHz 1 %. + 24 + 7 + read-write + + + + + RCC_CFGR + RCC_CFGR + Clock configuration register + 0x08 + 0x20 + 0x00000005 + 0xFFFFFFFF + + + SW + System clock switch +Set and cleared by software to select system clock source (SYSCLK). +Configured by hardware to force HSI16 oscillator selection when exiting stop and standby modes or in case of failure of the HSE oscillator. + 0 + 2 + read-write + + + B_0x0 + Reserved, must be kept at reset value + 0x0 + + + B_0x1 + HSI16 selected as system clock + 0x1 + + + B_0x2 + HSE selected as system clock + 0x2 + + + B_0x3 + PLL selected as system clock + 0x3 + + + + + SWS + System clock switch status +Set and cleared by hardware to indicate which clock source is used as system clock. + 2 + 2 + read-only + + + B_0x0 + Reserved, must be kept at reset value + 0x0 + + + B_0x1 + HSI16 oscillator used as system clock + 0x1 + + + B_0x2 + HSE used as system clock + 0x2 + + + B_0x3 + PLL used as system clock + 0x3 + + + + + HPRE + AHB prescaler +Set and cleared by software to control the division factor of the AHB clock. +Note: Depending on the device voltage range, the software has to set correctly these bits to ensure that the system frequency does not exceed the maximum allowed frequency (for more details please refer to Section 6.1.5: Dynamic voltage scaling management). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value has been taken into account. +0xxx: SYSCLK not divided + 4 + 4 + read-write + + + B_0x8 + SYSCLK divided by 2 + 0x8 + + + B_0x9 + SYSCLK divided by 4 + 0x9 + + + B_0xA + SYSCLK divided by 8 + 0xA + + + B_0xB + SYSCLK divided by 16 + 0xB + + + B_0xC + SYSCLK divided by 64 + 0xC + + + B_0xD + SYSCLK divided by 128 + 0xD + + + B_0xE + SYSCLK divided by 256 + 0xE + + + B_0xF + SYSCLK divided by 512 + 0xF + + + + + PPRE1 + APB1 prescaler +Set and cleared by software to control the division factor of the APB1 clock (PCLK1). +0xx: HCLK not divided + 8 + 3 + read-write + + + B_0x4 + HCLK divided by 2 + 0x4 + + + B_0x5 + HCLK divided by 4 + 0x5 + + + B_0x6 + HCLK divided by 8 + 0x6 + + + B_0x7 + HCLK divided by 16 + 0x7 + + + + + PPRE2 + APB2 prescaler +Set and cleared by software to control the division factor of the APB2 clock (PCLK2). +0xx: HCLK not divided + 11 + 3 + read-write + + + B_0x4 + HCLK divided by 2 + 0x4 + + + B_0x5 + HCLK divided by 4 + 0x5 + + + B_0x6 + HCLK divided by 8 + 0x6 + + + B_0x7 + HCLK divided by 16 + 0x7 + + + + + MCOSEL + Microcontroller clock output +Set and cleared by software. +Others: Reserved +Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. + 24 + 4 + read-write + + + B_0x0 + MCO output disabled, no clock on MCO + 0x0 + + + B_0x1 + SYSCLK system clock selected + 0x1 + + + B_0x2 + Reserved, must be kept at reset value + 0x2 + + + B_0x3 + HSI16 clock selected + 0x3 + + + B_0x4 + HSE clock selected + 0x4 + + + B_0x5 + Main PLL clock selected + 0x5 + + + B_0x6 + LSI clock selected + 0x6 + + + B_0x7 + LSE clock selected + 0x7 + + + B_0x8 + Internal HSI48 clock selected + 0x8 + + + + + MCOPRE + Microcontroller clock output prescaler +These bits are set and cleared by software. +It is highly recommended to change this prescaler before MCO output is enabled. +Others: not allowed + 28 + 3 + read-write + + + B_0x0 + MCO is divided by 1 + 0x0 + + + B_0x1 + MCO is divided by 2 + 0x1 + + + B_0x2 + MCO is divided by 4 + 0x2 + + + B_0x3 + MCO is divided by 8 + 0x3 + + + B_0x4 + MCO is divided by 16 + 0x4 + + + + + + + RCC_PLLCFGR + RCC_PLLCFGR + PLL configuration register + 0x0C + 0x20 + 0x00001000 + 0xFFFFFFFF + + + PLLSRC + Main PLL entry clock source +Set and cleared by software to select PLL clock source. These bits can be written only when PLL is disabled. +In order to save power, when no PLL is used, the value of PLLSRC should be 00. + 0 + 2 + read-write + + + B_0x0 + No clock sent to PLL + 0x0 + + + B_0x1 + No clock sent to PLL + 0x1 + + + B_0x2 + HSI16 clock selected as PLL clock entry + 0x2 + + + B_0x3 + HSE clock selected as PLL clock entry + 0x3 + + + + + PLLM + Division factor for the main PLL input clock +Set and cleared by software to divide the PLL input clock before the VCO. These bits can be written only when all PLLs are disabled. +VCO input frequency = PLL input clock frequency / PLLM with 1 <= PLLM <= 16 +... +Note: The software has to set these bits correctly to ensure that the VCO input frequency is within the range defined in the device datasheet. + 4 + 4 + read-write + + + B_0x0 + PLLM = 1 + 0x0 + + + B_0x1 + PLLM = 2 + 0x1 + + + B_0x2 + PLLM = 3 + 0x2 + + + B_0x3 + PLLM = 4 + 0x3 + + + B_0x4 + PLLM = 5 + 0x4 + + + B_0x5 + PLLM = 6 + 0x5 + + + B_0x6 + PLLM = 7 + 0x6 + + + B_0x7 + PLLM = 8 + 0x7 + + + B_0x8 + PLLSYSM = 9 + 0x8 + + + B_0xF + PLLSYSM= 16 + 0xF + + + + + PLLN + Main PLL multiplication factor for VCO +Set and cleared by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled. +VCO output frequency = VCO input frequency x PLLN with 8 =< PLLN =< 127 +... +... +Note: The software has to set correctly these bits to assure that the VCO output frequency is within the range defined in the device datasheet. + 8 + 7 + read-write + + + B_0x0 + PLLN = 0 wrong configuration + 0x0 + + + B_0x1 + PLLN = 1 wrong configuration + 0x1 + + + B_0x7 + PLLN = 7 wrong configuration + 0x7 + + + B_0x8 + PLLN = 8 + 0x8 + + + B_0x9 + PLLN = 9 + 0x9 + + + B_0x7F + PLLN = 127 + 0x7F + + + + + PLLPEN + Main PLL PLL P clock output enable +Set and reset by software to enable the PLL P clock output of the PLL. +In order to save power, when the PLL P clock output of the PLL is not used, the value of PLLPEN should be 0. + 16 + 1 + read-write + + + B_0x0 + PLL P clock output disable + 0x0 + + + B_0x1 + PLL P clock output enable + 0x1 + + + + + PLLP + Main PLL division factor for PLL P clock. +Set and cleared by software to control the frequency of the main PLL output clock PLL P clock. These bits can be written only if PLL is disabled. +When the PLLPDIV[4:0] is set to 00000PLL P output clock frequency = VCO frequency / PLLP with PLLP =7, or 17 +Note: The software has to set these bits correctly not to exceed 170 MHz on this domain. + 17 + 1 + read-write + + + B_0x0 + PLLP = 7 + 0x0 + + + B_0x1 + PLLP = 17 + 0x1 + + + + + PLLQEN + Main PLL Q clock output enable +Set and reset by software to enable the PLL Q clock output of the PLL. +In order to save power, when the PLL Q clock output of the PLL is not used, the value of PLLQEN should be 0. + 20 + 1 + read-write + + + B_0x0 + PLL Q clock output disable + 0x0 + + + B_0x1 + PLL Q clock output enable + 0x1 + + + + + PLLQ + Main PLL division factor for PLL Q clock. +Set and cleared by software to control the frequency of the main PLL output clock PLL Q clock. This output can be selected for USB, RNG, SAI (48 MHz clock). These bits can be written only if PLL is disabled. +PLL Q output clock frequency = VCO frequency / PLLQ with PLLQ = 2, 4, 6, or 8 +Note: The software has to set these bits correctly not to exceed 170 MHz on this domain. + 21 + 2 + read-write + + + B_0x0 + PLLQ = 2 + 0x0 + + + B_0x1 + PLLQ = 4 + 0x1 + + + B_0x2 + PLLQ = 6 + 0x2 + + + B_0x3 + PLLQ = 8 + 0x3 + + + + + PLLREN + PLL R clock output enable +Set and reset by software to enable the PLL R clock output of the PLL (used as system clock). +This bit cannot be written when PLL R clock output of the PLL is used as System Clock. +In order to save power, when the PLL R clock output of the PLL is not used, the value of PLLREN should be 0. + 24 + 1 + read-write + + + B_0x0 + PLL R clock output disable + 0x0 + + + B_0x1 + PLL R clock output enable + 0x1 + + + + + PLLR + Main PLL division factor for PLL R clock (system clock) +Set and cleared by software to control the frequency of the main PLL output clock PLLCLK. This output can be selected as system clock. These bits can be written only if PLL is disabled. +PLL R output clock frequency = VCO frequency / PLLR with PLLR = 2, 4, 6, or 8 +Note: The software has to set these bits correctly not to exceed 170 MHz on this domain. + 25 + 2 + read-write + + + B_0x0 + PLLR = 2 + 0x0 + + + B_0x1 + PLLR = 4 + 0x1 + + + B_0x2 + PLLR = 6 + 0x2 + + + B_0x3 + PLLR = 8 + 0x3 + + + + + PLLPDIV + Main PLLP division factor +Set and cleared by software to control the PLL P frequency. PLL P output clock frequency = VCO frequency / PLLPDIV. +.... + 27 + 5 + read-write + + + B_0x0 + PLL P clock is controlled by the bit PLLP + 0x0 + + + B_0x1 + Reserved. + 0x1 + + + B_0x2 + PLL P clock = VCO / 2 + 0x2 + + + B_0x1F + PLL P clock = VCO / 31 + 0x1F + + + + + + + RCC_CIER + RCC_CIER + Clock interrupt enable register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LSIRDYIE + LSI ready interrupt enable +Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization. + 0 + 1 + read-write + + + B_0x0 + LSI ready interrupt disabled + 0x0 + + + B_0x1 + LSI ready interrupt enabled + 0x1 + + + + + LSERDYIE + LSE ready interrupt enable +Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization. + 1 + 1 + read-write + + + B_0x0 + LSE ready interrupt disabled + 0x0 + + + B_0x1 + LSE ready interrupt enabled + 0x1 + + + + + HSIRDYIE + HSI16 ready interrupt enable +Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization. + 3 + 1 + read-write + + + B_0x0 + HSI16 ready interrupt disabled + 0x0 + + + B_0x1 + HSI16 ready interrupt enabled + 0x1 + + + + + HSERDYIE + HSE ready interrupt enable +Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization. + 4 + 1 + read-write + + + B_0x0 + HSE ready interrupt disabled + 0x0 + + + B_0x1 + HSE ready interrupt enabled + 0x1 + + + + + PLLRDYIE + PLL ready interrupt enable +Set and cleared by software to enable/disable interrupt caused by PLL lock. + 5 + 1 + read-write + + + B_0x0 + PLL lock interrupt disabled + 0x0 + + + B_0x1 + PLL lock interrupt enabled + 0x1 + + + + + LSECSSIE + LSE clock security system interrupt enable +Set and cleared by software to enable/disable interrupt caused by the clock security system on LSE. + 9 + 1 + read-write + + + B_0x0 + Clock security interrupt caused by LSE clock failure disabled + 0x0 + + + B_0x1 + Clock security interrupt caused by LSE clock failure enabled + 0x1 + + + + + HSI48RDYIE + HSI48 ready interrupt enable +Set and cleared by software to enable/disable interrupt caused by the internal HSI48 oscillator. + 10 + 1 + read-write + + + B_0x0 + HSI48 ready interrupt disabled + 0x0 + + + B_0x1 + HSI48 ready interrupt enabled + 0x1 + + + + + + + RCC_CIFR + RCC_CIFR + Clock interrupt flag register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LSIRDYF + LSI ready interrupt flag +Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set. +Cleared by software setting the LSIRDYC bit. + 0 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by the LSI oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the LSI oscillator + 0x1 + + + + + LSERDYF + LSE ready interrupt flag +Set by hardware when the LSE clock becomes stable and LSERDYDIE is set. +Cleared by software setting the LSERDYC bit. + 1 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by the LSE oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the LSE oscillator + 0x1 + + + + + HSIRDYF + HSI16 ready interrupt flag +Set by hardware when the HSI16 clock becomes stable and HSIRDYDIE is set in a response to setting the HSION (refer to Clock control register (RCC_CR)). When HSION is not set but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. +Cleared by software setting the HSIRDYC bit. + 3 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by the HSI16 oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the HSI16 oscillator + 0x1 + + + + + HSERDYF + HSE ready interrupt flag +Set by hardware when the HSE clock becomes stable and HSERDYDIE is set. +Cleared by software setting the HSERDYC bit. + 4 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by the HSE oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the HSE oscillator + 0x1 + + + + + PLLRDYF + PLL ready interrupt flag +Set by hardware when the PLL locks and PLLRDYDIE is set. +Cleared by software setting the PLLRDYC bit. + 5 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by PLL lock + 0x0 + + + B_0x1 + Clock ready interrupt caused by PLL lock + 0x1 + + + + + CSSF + Clock security system interrupt flag +Set by hardware when a failure is detected in the HSE oscillator. +Cleared by software setting the CSSC bit. + 8 + 1 + read-only + + + B_0x0 + No clock security interrupt caused by HSE clock failure + 0x0 + + + B_0x1 + Clock security interrupt caused by HSE clock failure + 0x1 + + + + + LSECSSF + LSE Clock security system interrupt flag +Set by hardware when a failure is detected in the LSE oscillator. +Cleared by software setting the LSECSSC bit. + 9 + 1 + read-only + + + B_0x0 + No clock security interrupt caused by LSE clock failure + 0x0 + + + B_0x1 + Clock security interrupt caused by LSE clock failure + 0x1 + + + + + HSI48RDYF + HSI48 ready interrupt flag +Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set in a response to setting the HSI48ON (refer to Clock recovery RC register (RCC_CRRCR)). +Cleared by software setting the HSI48RDYC bit. + 10 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by the HSI48 oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the HSI48 oscillator + 0x1 + + + + + + + RCC_CICR + RCC_CICR + Clock interrupt clear register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LSIRDYC + LSI ready interrupt clear +This bit is set by software to clear the LSIRDYF flag. + 0 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + LSIRDYF cleared + 0x1 + + + + + LSERDYC + LSE ready interrupt clear +This bit is set by software to clear the LSERDYF flag. + 1 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + LSERDYF cleared + 0x1 + + + + + HSIRDYC + HSI16 ready interrupt clear +This bit is set software to clear the HSIRDYF flag. + 3 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear HSIRDYF flag + 0x1 + + + + + HSERDYC + HSE ready interrupt clear +This bit is set by software to clear the HSERDYF flag. + 4 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear HSERDYF flag + 0x1 + + + + + PLLRDYC + PLL ready interrupt clear +This bit is set by software to clear the PLLRDYF flag. + 5 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear PLLRDYF flag + 0x1 + + + + + CSSC + Clock security system interrupt clear +This bit is set by software to clear the CSSF flag. + 8 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear CSSF flag + 0x1 + + + + + LSECSSC + LSE Clock security system interrupt clear +This bit is set by software to clear the LSECSSF flag. + 9 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear LSECSSF flag + 0x1 + + + + + HSI48RDYC + HSI48 oscillator ready interrupt clear +This bit is set by software to clear the HSI48RDYF flag. + 10 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear the HSI48RDYC flag + 0x1 + + + + + + + RCC_AHB1RSTR + RCC_AHB1RSTR + AHB1 peripheral reset register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMA1RST + DMA1 reset +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset DMA1 + 0x1 + + + + + DMA2RST + DMA2 reset +Set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset DMA2 + 0x1 + + + + + DMAMUX1RST + Set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset DMAMUX1 + 0x1 + + + + + CORDICRST + Set and cleared by software + 3 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset CORDIC + 0x1 + + + + + FMACRST + Set and cleared by software + 4 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset FMAC + 0x1 + + + + + FLASHRST + Flash memory interface reset +Set and cleared by software. This bit can be activated only when the Flash memory is in power down mode. + 8 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset Flash memory interface + 0x1 + + + + + CRCRST + CRC reset +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset CRC + 0x1 + + + + + + + RCC_AHB2RSTR + RCC_AHB2RSTR + AHB2 peripheral reset register + 0x2C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + GPIOARST + IO port A reset +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset IO port A + 0x1 + + + + + GPIOBRST + IO port B reset +Set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset IO port B + 0x1 + + + + + GPIOCRST + IO port C reset +Set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset IO port C + 0x1 + + + + + GPIODRST + IO port D reset +Set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset IO port D + 0x1 + + + + + GPIOERST + IO port E reset +Set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset IO port E + 0x1 + + + + + GPIOFRST + IO port F reset +Set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset IO port F + 0x1 + + + + + GPIOGRST + IO port G reset +Set and cleared by software. + 6 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset IO port G + 0x1 + + + + + ADC12RST + ADC12 reset +Set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset ADC12 interface + 0x1 + + + + + ADC345RST + ADC345 reset +Set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset ADC345 + 0x1 + + + + + DAC1RST + DAC1 reset +Set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset DAC1 + 0x1 + + + + + DAC2RST + DAC2 reset +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset DAC2 + 0x1 + + + + + DAC3RST + DAC3 reset +Set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset DAC3 + 0x1 + + + + + DAC4RST + DAC4 reset +Set and cleared by software. + 19 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset DAC4 + 0x1 + + + + + AESRST + AESRST reset +Set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset AES + 0x1 + + + + + RNGRST + RNG reset +Set and cleared by software. + 26 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset RNG + 0x1 + + + + + + + RCC_AHB3RSTR + RCC_AHB3RSTR + AHB3 peripheral reset register + 0x30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FMCRST + Flexible static memory controller reset +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset FSMC + 0x1 + + + + + QSPIRST + QUADSPI reset +Set and cleared by software. + 8 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset QUADSPI + 0x1 + + + + + + + RCC_APB1RSTR1 + RCC_APB1RSTR1 + APB1 peripheral reset register 1 + 0x38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIM2RST + TIM2 timer reset +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM2 + 0x1 + + + + + TIM3RST + TIM3 timer reset +Set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM3 + 0x1 + + + + + TIM4RST + TIM3 timer reset +Set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM3 + 0x1 + + + + + TIM5RST + TIM5 timer reset +Set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM5 + 0x1 + + + + + TIM6RST + TIM6 timer reset +Set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM7 + 0x1 + + + + + TIM7RST + TIM7 timer reset +Set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM7 + 0x1 + + + + + CRSRST + CRS reset +Set and cleared by software. + 8 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset CRS + 0x1 + + + + + SPI2RST + SPI2 reset +Set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset SPI2 + 0x1 + + + + + SPI3RST + SPI3 reset +Set and cleared by software. + 15 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset SPI3 + 0x1 + + + + + USART2RST + USART2 reset +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset USART2 + 0x1 + + + + + USART3RST + USART3 reset +Set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset USART3 + 0x1 + + + + + UART4RST + UART4 reset +Set and cleared by software. + 19 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset UART4 + 0x1 + + + + + UART5RST + UART5 reset +Set and cleared by software. + 20 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset UART5 + 0x1 + + + + + I2C1RST + I2C1 reset +Set and cleared by software. + 21 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset I2C1 + 0x1 + + + + + I2C2RST + I2C2 reset +Set and cleared by software. + 22 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset I2C2 + 0x1 + + + + + USBRST + USB device reset +Set and reset by software. + 23 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset USB device + 0x1 + + + + + FDCANRST + FDCAN reset +Set and reset by software. + 25 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the FDCAN + 0x1 + + + + + PWRRST + Power interface reset +Set and cleared by software. + 28 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset PWR + 0x1 + + + + + I2C3RST + I2C3 reset +Set and cleared by software. + 30 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset I2C3 interface + 0x1 + + + + + LPTIM1RST + Low Power Timer 1 reset +Set and cleared by software. + 31 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset LPTIM1 + 0x1 + + + + + + + RCC_APB1RSTR2 + RCC_APB1RSTR2 + APB1 peripheral reset register 2 + 0x3C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LPUART1RST + Low-power UART 1 reset +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset LPUART1 + 0x1 + + + + + I2C4RST + I2C4 reset + Set and cleared by software + 1 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset I2C4 + 0x1 + + + + + UCPD1RST + UCPD1 reset +Set and cleared by software. + 8 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset UCPD1 + 0x1 + + + + + + + RCC_APB2RSTR + RCC_APB2RSTR + APB2 peripheral reset register + 0x40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SYSCFGRST + SYSCFG + COMP + OPAMP + VREFBUF reset + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset SYSCFG + COMP + OPAMP + VREFBUF + 0x1 + + + + + TIM1RST + TIM1 timer reset +Set and cleared by software. + 11 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM1 timer + 0x1 + + + + + SPI1RST + SPI1 reset +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset SPI1 + 0x1 + + + + + TIM8RST + TIM8 timer reset +Set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM8 timer + 0x1 + + + + + USART1RST + USART1 reset +Set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset USART1 + 0x1 + + + + + SPI4RST + SPI4 reset +Set and cleared by software. + 15 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset SPI4 + 0x1 + + + + + TIM15RST + TIM15 timer reset +Set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM15 timer + 0x1 + + + + + TIM16RST + TIM16 timer reset +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM16 timer + 0x1 + + + + + TIM17RST + TIM17 timer reset +Set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM17 timer + 0x1 + + + + + TIM20RST + TIM20 reset +Set and cleared by software. + 20 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM20 + 0x1 + + + + + SAI1RST + Serial audio interface 1 (SAI1) reset +Set and cleared by software. + 21 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset SAI1 + 0x1 + + + + + HRTIM1RST + HRTIM1 reset +Set and cleared by software. + 26 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset HRTIM1 + 0x1 + + + + + + + RCC_AHB1ENR + RCC_AHB1ENR + AHB1 peripheral clock enable register + 0x48 + 0x20 + 0x00000100 + 0xFFFFFFFF + + + DMA1EN + DMA1 clock enable +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + DMA1 clock disable + 0x0 + + + B_0x1 + DMA1 clock enable + 0x1 + + + + + DMA2EN + DMA2 clock enable +Set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + DMA2 clock disable + 0x0 + + + B_0x1 + DMA2 clock enable + 0x1 + + + + + DMAMUX1EN + DMAMUX1 clock enable +Set and reset by software. + 2 + 1 + read-write + + + B_0x0 + DMAMUX1 clock disabled + 0x0 + + + B_0x1 + DMAMUX1 clock enabled + 0x1 + + + + + CORDICEN + CORDIC clock enable +Set and reset by software. + 3 + 1 + read-write + + + B_0x0 + CORDIC clock disabled + 0x0 + + + B_0x1 + CORDIC clock enabled + 0x1 + + + + + FMACEN + FMAC enable +Set and reset by software. + 4 + 1 + read-write + + + B_0x0 + FMAC clock disabled + 0x0 + + + B_0x1 + FMAC clock enabled + 0x1 + + + + + FLASHEN + Flash memory interface clock enable +Set and cleared by software. This bit can be disabled only when the Flash is in power down mode. + 8 + 1 + read-write + + + B_0x0 + Flash memory interface clock disable + 0x0 + + + B_0x1 + Flash memory interface clock enable + 0x1 + + + + + CRCEN + CRC clock enable +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + CRC clock disable + 0x0 + + + B_0x1 + CRC clock enable + 0x1 + + + + + + + RCC_AHB2ENR + RCC_AHB2ENR + AHB2 peripheral clock enable register + 0x4C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + GPIOAEN + IO port A clock enable +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + IO port A clock disabled + 0x0 + + + B_0x1 + IO port A clock enabled + 0x1 + + + + + GPIOBEN + IO port B clock enable +Set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + IO port B clock disabled + 0x0 + + + B_0x1 + IO port B clock enabled + 0x1 + + + + + GPIOCEN + IO port C clock enable +Set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + IO port C clock disabled + 0x0 + + + B_0x1 + IO port C clock enabled + 0x1 + + + + + GPIODEN + IO port D clock enable +Set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + IO port D clock disabled + 0x0 + + + B_0x1 + IO port D clock enabled + 0x1 + + + + + GPIOEEN + IO port E clock enable +Set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + IO port E clock disabled + 0x0 + + + B_0x1 + IO port E clock enabled + 0x1 + + + + + GPIOFEN + IO port F clock enable +Set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + IO port F clock disabled + 0x0 + + + B_0x1 + IO port F clock enabled + 0x1 + + + + + GPIOGEN + IO port G clock enable +Set and cleared by software. + 6 + 1 + read-write + + + B_0x0 + IO port G clock disabled + 0x0 + + + B_0x1 + IO port G clock enabled + 0x1 + + + + + ADC12EN + ADC12 clock enable +Set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + ADC12 clock disabled + 0x0 + + + B_0x1 + ADC12 clock enabled + 0x1 + + + + + ADC345EN + ADC345 clock enable + Set and cleared by software + 14 + 1 + read-write + + + B_0x0 + ADC345 clock disabled + 0x0 + + + B_0x1 + ADC345 clock enabled + 0x1 + + + + + DAC1EN + DAC1 clock enable +Set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + DAC1 clock disabled + 0x0 + + + B_0x1 + DAC1 clock enabled + 0x1 + + + + + DAC2EN + DAC2 clock enable +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + DAC2 clock disabled + 0x0 + + + B_0x1 + DAC2 clock enabled + 0x1 + + + + + DAC3EN + DAC3 clock enable +Set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + DAC3 clock disabled + 0x0 + + + B_0x1 + DAC3 clock enabled + 0x1 + + + + + DAC4EN + DAC4 clock enable +Set and cleared by software. + 19 + 1 + read-write + + + B_0x0 + DAC4 clock disabled + 0x0 + + + B_0x1 + DAC4 clock enabled + 0x1 + + + + + AESEN + AES clock enable +Set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + AES clock disabled + 0x0 + + + B_0x1 + AES clock enabled + 0x1 + + + + + RNGEN + RNG enable +Set and cleared by software. + 26 + 1 + read-write + + + B_0x0 + RNG disabled + 0x0 + + + B_0x1 + RNG enabled + 0x1 + + + + + + + RCC_AHB3ENR + RCC_AHB3ENR + AHB3 peripheral clock enable register + 0x50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FMCEN + Flexible static memory controller clock enable +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + FSMC clock disable + 0x0 + + + B_0x1 + FSMC clock enable + 0x1 + + + + + QSPIEN + QUADSPI memory interface clock enable +Set and cleared by software. + 8 + 1 + read-write + + + B_0x0 + QUADSPI clock disable + 0x0 + + + B_0x1 + QUADSPI clock enable + 0x1 + + + + + + + RCC_APB1ENR1 + RCC_APB1ENR1 + APB1 peripheral clock enable register 1 + 0x58 + 0x20 + 0x00000400 + 0xFFFFFFFF + + + TIM2EN + TIM2 timer clock enable +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + TIM2 clock disabled + 0x0 + + + B_0x1 + TIM2 clock enabled + 0x1 + + + + + TIM3EN + TIM3 timer clock enable +Set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + TIM3 clock disabled + 0x0 + + + B_0x1 + TIM3 clock enabled + 0x1 + + + + + TIM4EN + TIM4 timer clock enable +Set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + TIM4 clock disabled + 0x0 + + + B_0x1 + TIM4 clock enabled + 0x1 + + + + + TIM5EN + TIM5 timer clock enable +Set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + TIM5 clock disabled + 0x0 + + + B_0x1 + TIM5 clock enabled + 0x1 + + + + + TIM6EN + TIM6 timer clock enable +Set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + TIM6 clock disabled + 0x0 + + + B_0x1 + TIM6 clock enabled + 0x1 + + + + + TIM7EN + TIM7 timer clock enable +Set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + TIM7 clock disabled + 0x0 + + + B_0x1 + TIM7 clock enabled + 0x1 + + + + + CRSEN + CRS Recovery System clock enable +Set and cleared by software. + 8 + 1 + read-write + + + B_0x0 + CRS clock disabled + 0x0 + + + B_0x1 + CRS clock enabled + 0x1 + + + + + RTCAPBEN + RTC APB clock enable +Set and cleared by software + 10 + 1 + read-write + + + B_0x0 + RTC APB clock disabled + 0x0 + + + B_0x1 + RTC APB clock enabled + 0x1 + + + + + WWDGEN + Window watchdog clock enable +Set by software to enable the window watchdog clock. Reset by hardware system reset. This bit can also be set by hardware if the WWDG_SW option bit is reset. + 11 + 1 + read-write + + + B_0x0 + Window watchdog clock disabled + 0x0 + + + B_0x1 + Window watchdog clock enabled + 0x1 + + + + + SPI2EN + SPI2 clock enable +Set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + SPI2 clock disabled + 0x0 + + + B_0x1 + SPI2 clock enabled + 0x1 + + + + + SPI3EN + SPI3 clock enable +Set and cleared by software. + 15 + 1 + read-write + + + B_0x0 + SPI3 clock disabled + 0x0 + + + B_0x1 + SPI3 clock enabled + 0x1 + + + + + USART2EN + USART2 clock enable +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + USART2 clock disabled + 0x0 + + + B_0x1 + USART2 clock enabled + 0x1 + + + + + USART3EN + USART3 clock enable +Set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + USART3 clock disabled + 0x0 + + + B_0x1 + USART3 clock enabled + 0x1 + + + + + UART4EN + UART4 clock enable +Set and cleared by software. + 19 + 1 + read-write + + + B_0x0 + UART4 clock disabled + 0x0 + + + B_0x1 + UART4 clock enabled + 0x1 + + + + + UART5EN + UART5 clock enable +Set and cleared by software. + 20 + 1 + read-write + + + B_0x0 + UART5 clock disabled + 0x0 + + + B_0x1 + UART5 clock enabled + 0x1 + + + + + I2C1EN + I2C1 clock enable +Set and cleared by software. + 21 + 1 + read-write + + + B_0x0 + I2C1 clock disabled + 0x0 + + + B_0x1 + I2C1 clock enabled + 0x1 + + + + + I2C2EN + I2C2 clock enable +Set and cleared by software. + 22 + 1 + read-write + + + B_0x0 + I2C2 clock disabled + 0x0 + + + B_0x1 + I2C2 clock enabled + 0x1 + + + + + USBEN + USB device clock enable +Set and cleared by software. + 23 + 1 + read-write + + + B_0x0 + USB device clock disabled + 0x0 + + + B_0x1 + USB device clock enabled + 0x1 + + + + + FDCANEN + FDCAN clock enable +Set and cleared by software. + 25 + 1 + read-write + + + B_0x0 + FDCAN clock disabled + 0x0 + + + B_0x1 + FDCAN clock enabled + 0x1 + + + + + PWREN + Power interface clock enable +Set and cleared by software. + 28 + 1 + read-write + + + B_0x0 + Power interface clock disabled + 0x0 + + + B_0x1 + Power interface clock enabled + 0x1 + + + + + I2C3EN + I2C3 clock enable +Set and cleared by software. + 30 + 1 + read-write + + + B_0x0 + I2C3 clock disabled + 0x0 + + + B_0x1 + I2C3 clock enabled + 0x1 + + + + + LPTIM1EN + Low power timer 1 clock enable +Set and cleared by software. + 31 + 1 + read-write + + + B_0x0 + LPTIM1 clock disabled + 0x0 + + + B_0x1 + LPTIM1 clock enabled + 0x1 + + + + + + + RCC_APB1ENR2 + RCC_APB1ENR2 + APB1 peripheral clock enable register 2 + 0x5C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LPUART1EN + Low power UART 1 clock enable +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + LPUART1 clock disable + 0x0 + + + B_0x1 + LPUART1 clock enable + 0x1 + + + + + I2C4EN + I2C4 clock enable +Set and cleared by software + 1 + 1 + read-write + + + B_0x0 + I2C4 clock disabled + 0x0 + + + B_0x1 + I2C4 clock enabled + 0x1 + + + + + UCPD1EN + UCPD1 clock enable +Set and cleared by software. + 8 + 1 + read-write + + + B_0x0 + UCPD1 clock disable + 0x0 + + + B_0x1 + UCPD1 clock enable + 0x1 + + + + + + + RCC_APB2ENR + RCC_APB2ENR + APB2 peripheral clock enable register + 0x60 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SYSCFGEN + SYSCFG + COMP + VREFBUF + OPAMP clock enable +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + SYSCFG + COMP + VREFBUF + OPAMP clock disabled + 0x0 + + + B_0x1 + SYSCFG + COMP + VREFBUF + OPAMP clock enabled + 0x1 + + + + + TIM1EN + TIM1 timer clock enable +Set and cleared by software. + 11 + 1 + read-write + + + B_0x0 + TIM1 timer clock disabled + 0x0 + + + B_0x1 + TIM1P timer clock enabled + 0x1 + + + + + SPI1EN + SPI1 clock enable +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + SPI1 clock disabled + 0x0 + + + B_0x1 + SPI1 clock enabled + 0x1 + + + + + TIM8EN + TIM8 timer clock enable +Set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + TIM8 timer clock disabled + 0x0 + + + B_0x1 + TIM8 timer clock enabled + 0x1 + + + + + USART1EN + USART1clock enable +Set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + USART1clock disabled + 0x0 + + + B_0x1 + USART1clock enabled + 0x1 + + + + + SPI4EN + SPI4 clock enable +Set and cleared by software. + 15 + 1 + read-write + + + B_0x0 + SPI4 clock disabled + 0x0 + + + B_0x1 + SPI4 clock enabled + 0x1 + + + + + TIM15EN + TIM15 timer clock enable +Set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + TIM15 timer clock disabled + 0x0 + + + B_0x1 + TIM15 timer clock enabled + 0x1 + + + + + TIM16EN + TIM16 timer clock enable +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + TIM16 timer clock disabled + 0x0 + + + B_0x1 + TIM16 timer clock enabled + 0x1 + + + + + TIM17EN + TIM17 timer clock enable +Set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + TIM17 timer clock disabled + 0x0 + + + B_0x1 + TIM17 timer clock enabled + 0x1 + + + + + TIM20EN + TIM20 timer clock enable +Set and cleared by software. + 20 + 1 + read-write + + + B_0x0 + TIM20 clock disabled + 0x0 + + + B_0x1 + TIM20 clock enabled + 0x1 + + + + + SAI1EN + SAI1 clock enable +Set and cleared by software. + 21 + 1 + read-write + + + B_0x0 + SAI1 clock disabled + 0x0 + + + B_0x1 + SAI1 clock enabled + 0x1 + + + + + HRTIM1EN + HRTIM1 clock enable +Set and cleared by software. + 26 + 1 + read-write + + + B_0x0 + HRTIM1 clock disabled + 0x0 + + + B_0x1 + HRTIM1 clock enable + 0x1 + + + + + + + RCC_AHB1SMENR + RCC_AHB1SMENR + AHB1 peripheral clocks enable in Sleep and Stop modes register + 0x68 + 0x20 + 0x0000130F + 0xFFFFFFFF + + + DMA1SMEN + DMA1 clocks enable during Sleep and Stop modes +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + DMA1 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + DMA1 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + DMA2SMEN + DMA2 clocks enable during Sleep and Stop modes +Set and cleared by software during Sleep mode. + 1 + 1 + read-write + + + B_0x0 + DMA2 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + DMA2 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + DMAMUX1SMEN + DMAMUX1 clock enable during Sleep and Stop modes. +Set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + DMAMUX1 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + DMAMUX1 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + CORDICSMEN + CORDICSM clock enable. +Set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + CORDICSM clocks disabled. + 0x0 + + + B_0x1 + CORDICSM clocks enabled. + 0x1 + + + + + FMACSMEN + FMACSM clock enable. +Set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + FMACSM clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + FMACSM clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + FLASHSMEN + Flash memory interface clocks enable during Sleep and Stop modes +Set and cleared by software. + 8 + 1 + read-write + + + B_0x0 + Flash memory interface clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + Flash memory interface clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + SRAM1SMEN + SRAM1 interface clocks enable during Sleep and Stop modes +Set and cleared by software. + 9 + 1 + read-write + + + B_0x0 + SRAM1 interface clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + SRAM1 interface clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + CRCSMEN + CRC clocks enable during Sleep and Stop modes +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + CRC clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + CRC clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + + + RCC_AHB2SMENR + RCC_AHB2SMENR + AHB2 peripheral clocks enable in Sleep and Stop modes register + 0x6C + 0x20 + 0x050F667F + 0xFFFFFFFF + + + GPIOASMEN + IO port A clocks enable during Sleep and Stop modes +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + IO port A clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + IO port A clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + GPIOBSMEN + IO port B clocks enable during Sleep and Stop modes +Set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + IO port B clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + IO port B clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + GPIOCSMEN + IO port C clocks enable during Sleep and Stop modes +Set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + IO port C clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + IO port C clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + GPIODSMEN + IO port D clocks enable during Sleep and Stop modes +Set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + IO port D clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + IO port D clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + GPIOESMEN + IO port E clocks enable during Sleep and Stop modes +Set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + IO port E clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + IO port E clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + GPIOFSMEN + IO port F clocks enable during Sleep and Stop modes +Set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + IO port F clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + IO port F clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + GPIOGSMEN + IO port G clocks enable during Sleep and Stop modes +Set and cleared by software. + 6 + 1 + read-write + + + B_0x0 + IO port G clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + IO port G clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + CCMSRAMSMEN + CCM SRAM interface clocks enable during Sleep and Stop modes +Set and cleared by software. + 9 + 1 + read-write + + + B_0x0 + CCM SRAM interface clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + CCM SRAM interface clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + SRAM2SMEN + SRAM2 interface clocks enable during Sleep and Stop modes +Set and cleared by software. + 10 + 1 + read-write + + + B_0x0 + SRAM2 interface clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + SRAM2 interface clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + ADC12SMEN + ADC12 clocks enable during Sleep and Stop modes +Set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + ADC12 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + ADC12 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + ADC345SMEN + ADC345 clock enable +Set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + ADC345 clock disabled + 0x0 + + + B_0x1 + ADC345 clock enabled + 0x1 + + + + + DAC1SMEN + DAC1 clock enable +Set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + DAC1 clock disabled + 0x0 + + + B_0x1 + DAC1 clock enabled during sleep and stop modes + 0x1 + + + + + DAC2SMEN + DAC2 clock enable +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + DAC2 clock disabled + 0x0 + + + B_0x1 + DAC2 clock enabled during sleep and stop modes + 0x1 + + + + + DAC3SMEN + DAC3 clock enable +Set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + DAC3 clock disabled + 0x0 + + + B_0x1 + DAC3 clock enabled during sleep and stop modes + 0x1 + + + + + DAC4SMEN + DAC4 clock enable +Set and cleared by software. + 19 + 1 + read-write + + + B_0x0 + DAC4 clock disabled + 0x0 + + + B_0x1 + DAC4 clock enabled during sleep and stop modes + 0x1 + + + + + AESSMEN + AESM clocks enable +Set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + AESM clocks disabled + 0x0 + + + B_0x1 + AESM clocks enabled + 0x1 + + + + + RNGEN + RNG enable +Set and cleared by software. + 26 + 1 + read-write + + + B_0x0 + RNG disabled + 0x0 + + + B_0x1 + RNG enabled + 0x1 + + + + + + + RCC_AHB3SMENR + RCC_AHB3SMENR + AHB3 peripheral clocks enable in Sleep and Stop modes register + 0x70 + 0x20 + 0x00000101 + 0xFFFFFFFF + + + FMCSMEN + Flexible static memory controller clocks enable during Sleep and Stop modes +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + FSMC clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + FSMC clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + QSPISMEN + QUADSPI memory interface clock enable during Sleep and Stop modes +Set and cleared by software. + 8 + 1 + read-write + + + B_0x0 + QUADSPI clock disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + QUADSPI clock enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + + + RCC_APB1SMENR1 + RCC_APB1SMENR1 + APB1 peripheral clocks enable in Sleep and Stop modes register 1 + 0x78 + 0x20 + 0xD2FECD3F + 0xFFFFFFFF + + + TIM2SMEN + TIM2 timer clocks enable during Sleep and Stop modes +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + TIM2 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM2 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + TIM3SMEN + TIM3 timer clocks enable during Sleep and Stop modes +Set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + TIM3 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM3 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + TIM4SMEN + TIM4 timer clocks enable during Sleep and Stop modes +Set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + TIM4 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM4 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + TIM5SMEN + TIM5 timer clocks enable during Sleep and Stop modes +Set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + TIM5 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM5 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + TIM6SMEN + TIM6 timer clocks enable during Sleep and Stop modes +Set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + TIM6 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM6 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + TIM7SMEN + TIM7 timer clocks enable during Sleep and Stop modes +Set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + TIM7 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM7 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + CRSSMEN + CRS timer clocks enable during Sleep and Stop modes +Set and cleared by software. + 8 + 1 + read-write + + + B_0x0 + CRS clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + CRS clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + RTCAPBSMEN + RTC APB clock enable during Sleep and Stop modes +Set and cleared by software + 10 + 1 + read-write + + + B_0x0 + RTC APB clock disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + RTC APB clock enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + WWDGSMEN + Window watchdog clocks enable during Sleep and Stop modes +Set and cleared by software. This bit is forced to 1 by hardware when the hardware WWDG option is activated. + 11 + 1 + read-write + + + B_0x0 + Window watchdog clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + Window watchdog clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + SPI2SMEN + SPI2 clocks enable during Sleep and Stop modes +Set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + SPI2 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + SPI2 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + SPI3SMEN + SPI3 clocks enable during Sleep and Stop modes +Set and cleared by software. + 15 + 1 + read-write + + + B_0x0 + SPI3 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + SPI3 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + USART2SMEN + USART2 clocks enable during Sleep and Stop modes +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + USART2 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + USART2 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + USART3SMEN + USART3 clocks enable during Sleep and Stop modes +Set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + USART3 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + USART3 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + UART4SMEN + UART4 clocks enable during Sleep and Stop modes +Set and cleared by software. + 19 + 1 + read-write + + + B_0x0 + UART4 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + UART4 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + UART5SMEN + UART5 clocks enable during Sleep and Stop modes +Set and cleared by software. + 20 + 1 + read-write + + + B_0x0 + UART5 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + UART5 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + I2C1SMEN + I2C1 clocks enable during Sleep and Stop modes +Set and cleared by software. + 21 + 1 + read-write + + + B_0x0 + I2C1 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + I2C1 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + I2C2SMEN + I2C2 clocks enable during Sleep and Stop modes +Set and cleared by software. + 22 + 1 + read-write + + + B_0x0 + I2C2 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + I2C2 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + USBSMEN + USB device clocks enable during Sleep and Stop modes +Set and cleared by software. + 23 + 1 + read-write + + + B_0x0 + USB device clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + USB device clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + FDCANSMEN + FDCAN clocks enable during Sleep and Stop modes +Set and cleared by software. + 25 + 1 + read-write + + + B_0x0 + FDCAN clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + FDCAN clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + PWRSMEN + Power interface clocks enable during Sleep and Stop modes +Set and cleared by software. + 28 + 1 + read-write + + + B_0x0 + Power interface clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + Power interface clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + I2C3SMEN + I2C3 clocks enable during Sleep and Stop modes +Set and cleared by software. + 30 + 1 + read-write + + + B_0x0 + I2C3 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + I2C3 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + LPTIM1SMEN + Low power timer 1 clocks enable during Sleep and Stop modes +Set and cleared by software. + 31 + 1 + read-write + + + B_0x0 + LPTIM1 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + LPTIM1 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + + + RCC_APB1SMENR2 + RCC_APB1SMENR2 + APB1 peripheral clocks enable in Sleep and Stop modes register 2 + 0x7C + 0x20 + 0x00000103 + 0xFFFFFFFF + + + LPUART1SMEN + Low power UART 1 clocks enable during Sleep and Stop modes +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + LPUART1 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + LPUART1 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + I2C4SMEN + I2C4 clocks enable during Sleep and Stop modes + Set and cleared by software + 1 + 1 + read-write + + + B_0x0 + I2C4 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + I2C4 clock enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + UCPD1SMEN + UCPD1 clocks enable during Sleep and Stop modes +Set and cleared by software. + 8 + 1 + read-write + + + B_0x0 + UCPD1 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + UCPD1 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + + + RCC_APB2SMENR + RCC_APB2SMENR + APB2 peripheral clocks enable in Sleep and Stop modes register + 0x80 + 0x20 + 0x0437F801 + 0xFFFFFFFF + + + SYSCFGSMEN + SYSCFG + COMP + VREFBUF + OPAMP clocks enable during Sleep and Stop modes +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + SYSCFG + COMP + VREFBUF + OPAMP clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + SYSCFG + COMP + VREFBUF + OPAMP clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + TIM1SMEN + TIM1 timer clocks enable during Sleep and Stop modes +Set and cleared by software. + 11 + 1 + read-write + + + B_0x0 + TIM1 timer clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM1P timer clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + SPI1SMEN + SPI1 clocks enable during Sleep and Stop modes +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + SPI1 clocks disabled by the clock gating during<sup>(1)</sup> Sleep and Stop modes + 0x0 + + + B_0x1 + SPI1 clocks enabled by the clock gating during<sup>(1)</sup> Sleep and Stop modes + 0x1 + + + + + TIM8SMEN + TIM8 timer clocks enable during Sleep and Stop modes +Set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + TIM8 timer clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM8 timer clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + USART1SMEN + USART1clocks enable during Sleep and Stop modes +Set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + USART1clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + USART1clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + SPI4SMEN + SPI4 timer clocks enable during Sleep and Stop modes +Set and cleared by software. + 15 + 1 + read-write + + + B_0x0 + SPI4 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + SPI4 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop mode + 0x1 + + + + + TIM15SMEN + TIM15 timer clocks enable during Sleep and Stop modes +Set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + TIM15 timer clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM15 timer clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop mode + 0x1 + + + + + TIM16SMEN + TIM16 timer clocks enable during Sleep and Stop modes +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + TIM16 timer clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM16 timer clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + TIM17SMEN + TIM17 timer clocks enable during Sleep and Stop modes +Set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + TIM17 timer clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM17 timer clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + TIM20SMEN + TIM20 timer clocks enable during Sleep and Stop modes +Set and cleared by software. + 20 + 1 + read-write + + + B_0x0 + TIM20 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM20 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + SAI1SMEN + SAI1 clocks enable during Sleep and Stop modes +Set and cleared by software. + 21 + 1 + read-write + + + B_0x0 + SAI1 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + SAI1 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + HRTIM1SMEN + HRTIM1 timer clocks enable during Sleep and Stop modes +Set and cleared by software. + 26 + 1 + read-write + + + B_0x0 + HRTIM1 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + HRTIM1 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + + + RCC_CCIPR + RCC_CCIPR + Peripherals independent clock configuration register + 0x88 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + USART1SEL + USART1 clock source selection +This bit is set and cleared by software to select the USART1 clock source. + 0 + 2 + read-write + + + B_0x0 + PCLK selected as USART1 clock + 0x0 + + + B_0x1 + System clock (SYSCLK) selected as USART1 clock + 0x1 + + + B_0x2 + HSI16 clock selected as USART1 clock + 0x2 + + + B_0x3 + LSE clock selected as USART1 clock + 0x3 + + + + + USART2SEL + USART2 clock source selection +This bit is set and cleared by software to select the USART2 clock source. + 2 + 2 + read-write + + + B_0x0 + PCLK selected as USART2 clock + 0x0 + + + B_0x1 + System clock (SYSCLK) selected as USART2 clock + 0x1 + + + B_0x2 + HSI16 clock selected as USART2 clock + 0x2 + + + B_0x3 + LSE clock selected as USART2 clock + 0x3 + + + + + USART3SEL + USART3 clock source selection +This bit is set and cleared by software to select the USART3 clock source. + 4 + 2 + read-write + + + B_0x0 + PCLK selected as USART3 clock + 0x0 + + + B_0x1 + System clock (SYSCLK) selected as USART3 clock + 0x1 + + + B_0x2 + HSI16 clock selected as USART3 clock + 0x2 + + + B_0x3 + LSE clock selected as USART3 clock + 0x3 + + + + + UART4SEL + UART4 clock source selection +This bit is set and cleared by software to select the UART4 clock source. + 6 + 2 + read-write + + + B_0x0 + PCLK selected as UART4 clock + 0x0 + + + B_0x1 + System clock (SYSCLK) selected as UART4 clock + 0x1 + + + B_0x2 + HSI16 clock selected as UART4 clock + 0x2 + + + B_0x3 + LSE clock selected as UART4 clock + 0x3 + + + + + UART5SEL + UART5 clock source selection +These bits are set and cleared by software to select the UART5 clock source. + 8 + 2 + read-write + + + B_0x0 + PCLK selected as UART5 clock + 0x0 + + + B_0x1 + System clock (SYSCLK) selected as UART5 clock + 0x1 + + + B_0x2 + HSI16 clock selected as UART5 clock + 0x2 + + + B_0x3 + LSE clock selected as UART5 clock + 0x3 + + + + + LPUART1SEL + LPUART1 clock source selection +These bits are set and cleared by software to select the LPUART1 clock source. + 10 + 2 + read-write + + + B_0x0 + PCLK selected as LPUART1 clock + 0x0 + + + B_0x1 + System clock (SYSCLK) selected as LPUART1 clock + 0x1 + + + B_0x2 + HSI16 clock selected as LPUART1 clock + 0x2 + + + B_0x3 + LSE clock selected as LPUART1 clock + 0x3 + + + + + I2C1SEL + I2C1 clock source selection +These bits are set and cleared by software to select the I2C1 clock source. + 12 + 2 + read-write + + + B_0x0 + PCLK selected as I2C1 clock + 0x0 + + + B_0x1 + System clock (SYSCLK) selected as I2C1 clock + 0x1 + + + B_0x2 + HSI16 clock selected as I2C1 clock + 0x2 + + + + + I2C2SEL + I2C2 clock source selection +These bits are set and cleared by software to select the I2C2 clock source. + 14 + 2 + read-write + + + B_0x0 + PCLK selected as I2C2 clock + 0x0 + + + B_0x1 + System clock (SYSCLK) selected as I2C2 clock + 0x1 + + + B_0x2 + HSI16 clock selected as I2C2 clock + 0x2 + + + + + I2C3SEL + I2C3 clock source selection +These bits are set and cleared by software to select the I2C3 clock source. + 16 + 2 + read-write + + + B_0x0 + PCLK selected as I2C3 clock + 0x0 + + + B_0x1 + System clock (SYSCLK) selected as I2C3 clock + 0x1 + + + B_0x2 + HSI16 clock selected as I2C3 clock + 0x2 + + + + + LPTIM1SEL + Low power timer 1 clock source selection +These bits are set and cleared by software to select the LPTIM1 clock source. + 18 + 2 + read-write + + + B_0x0 + PCLK selected as LPTIM1 clock + 0x0 + + + B_0x1 + LSI clock selected as LPTIM1 clock + 0x1 + + + B_0x2 + HSI16 clock selected as LPTIM1 clock + 0x2 + + + B_0x3 + LSE clock selected as LPTIM1 clock + 0x3 + + + + + SAI1SEL + clock source selection +These bits are set and cleared by software to select the SAI clock source. + 20 + 2 + read-write + + + B_0x0 + System clock selected as SAI clock + 0x0 + + + B_0x1 + PLL Q clock selected as SAI clock + 0x1 + + + B_0x2 + Clock provided on I2S_CKIN pin selected as SAI clock + 0x2 + + + B_0x3 + HSI16 clock selected as SAI clock + 0x3 + + + + + I2S23SEL + clock source selection +These bits are set and cleared by software to select the I2S23 clock source. + 22 + 2 + read-write + + + B_0x0 + System clock selected as I2S23 clock + 0x0 + + + B_0x1 + PLL Q clock selected as I2S23 clock + 0x1 + + + B_0x2 + Clock provided on I2S_CKIN pin is selected as I2S23 clock + 0x2 + + + B_0x3 + HSI16 clock selected as I2S23 clock. + 0x3 + + + + + FDCANSEL + None + 24 + 2 + read-write + + + CLK48SEL + 48 MHz clock source selection +These bits are set and cleared by software to select the 48 MHz clock source used by USB device FS and RNG. + 26 + 2 + read-write + + + B_0x0 + HSI48 clock selected as 48 MHz clock + 0x0 + + + B_0x2 + PLL Q clock (PLL48M1CLK) selected as 48 MHz clock + 0x2 + + + B_0x3 + Reserved, must be kept at reset value + 0x3 + + + + + ADC12SEL + ADC1/2 clock source selection +These bits are set and cleared by software to select the clock source used by the ADC interface. + 28 + 2 + read-write + + + B_0x0 + No clock selected + 0x0 + + + B_0x1 + PLL P clock selected as ADC1/2 clock + 0x1 + + + B_0x2 + System clock selected as ADC1/2 clock + 0x2 + + + + + ADC345SEL + ADC3/4/5 clock source selection +These bits are set and cleared by software to select the clock source used by the ADC345 interface. + 30 + 2 + read-write + + + B_0x0 + No clock selected + 0x0 + + + B_0x1 + PLL P clock selected as ADC345 clock + 0x1 + + + B_0x2 + System clock selected as ADC3/4/5 clock + 0x2 + + + B_0x3 + Reserved. + 0x3 + + + + + + + RCC_BDCR + RCC_BDCR + RTC domain control register + 0x90 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LSEON + LSE oscillator enable +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + LSE oscillator OFF + 0x0 + + + B_0x1 + LSE oscillator ON + 0x1 + + + + + LSERDY + LSE oscillator ready +Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles. + 1 + 1 + read-only + + + B_0x0 + LSE oscillator not ready + 0x0 + + + B_0x1 + LSE oscillator ready + 0x1 + + + + + LSEBYP + LSE oscillator bypass +Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32 kHz oscillator is disabled (LSEON=0 and LSERDY=0). + 2 + 1 + read-write + + + B_0x0 + LSE oscillator not bypassed + 0x0 + + + B_0x1 + LSE oscillator bypassed + 0x1 + + + + + LSEDRV + LSE oscillator drive capability +Set by software to modulate the LSE oscillators drive capability. +The oscillator is in Xtal mode when it is not in bypass mode. + 3 + 2 + read-write + + + B_0x0 + Xtal mode lower driving capability + 0x0 + + + B_0x1 + Xtal mode medium low driving capability + 0x1 + + + B_0x2 + Xtal mode medium high driving capability + 0x2 + + + B_0x3 + Xtal mode higher driving capability + 0x3 + + + + + LSECSSON + CSS on LSE enable +Set by software to enable the Clock Security System on LSE (32 kHz oscillator). +LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected. +Once enabled this bit cannot be disabled, except after a LSE failure detection (LSECSSD +=1). In that case the software MUST disable the LSECSSON bit. + 5 + 1 + read-write + + + B_0x0 + CSS on LSE (32 kHz external oscillator) OFF + 0x0 + + + B_0x1 + CSS on LSE (32 kHz external oscillator) ON + 0x1 + + + + + LSECSSD + CSS on LSE failure Detection +Set by hardware to indicate when a failure has been detected by the Clock Security System +on the external 32 kHz oscillator (LSE). + 6 + 1 + read-only + + + B_0x0 + No failure detected on LSE (32 kHz oscillator) + 0x0 + + + B_0x1 + Failure detected on LSE (32 kHz oscillator) + 0x1 + + + + + RTCSEL + RTC clock source selection +Set by software to select the clock source for the RTC. Once the RTC clock source has been selected, it cannot be changed anymore unless the RTC domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset them. + 8 + 2 + read-write + + + B_0x0 + No clock + 0x0 + + + B_0x1 + LSE oscillator clock used as RTC clock + 0x1 + + + B_0x2 + LSI oscillator clock used as RTC clock + 0x2 + + + B_0x3 + HSE oscillator clock divided by 32 used as RTC clock + 0x3 + + + + + RTCEN + RTC clock enable +Set and cleared by software. + 15 + 1 + read-write + + + B_0x0 + RTC clock disabled + 0x0 + + + B_0x1 + RTC clock enabled + 0x1 + + + + + BDRST + RTC domain software reset +Set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + Reset not activated + 0x0 + + + B_0x1 + Reset the entire RTC domain + 0x1 + + + + + LSCOEN + Low speed clock output enable +Set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + Low speed clock output (LSCO) disable + 0x0 + + + B_0x1 + Low speed clock output (LSCO) enable + 0x1 + + + + + LSCOSEL + Low speed clock output selection +Set and cleared by software. + 25 + 1 + read-write + + + B_0x0 + LSI clock selected + 0x0 + + + B_0x1 + LSE clock selected + 0x1 + + + + + + + RCC_CSR + RCC_CSR + Control/status register + 0x94 + 0x20 + 0x0C000000 + 0xFFFFFFFF + + + LSION + LSI oscillator enable +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + LSI oscillator OFF + 0x0 + + + B_0x1 + LSI oscillator ON + 0x1 + + + + + LSIRDY + LSI oscillator ready +Set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles. This bit can be set even if LSION = 0 if the LSI is requested by the Clock Security System on LSE, by the Independent Watchdog or by the RTC. + 1 + 1 + read-only + + + B_0x0 + LSI oscillator not ready + 0x0 + + + B_0x1 + LSI oscillator ready + 0x1 + + + + + RMVF + Remove reset flag +Set by software to clear the reset flags. + 23 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear the reset flags + 0x1 + + + + + OBLRSTF + Option byte loader reset flag +Set by hardware when a reset from the Option Byte loading occurs. +Cleared by writing to the RMVF bit. + 25 + 1 + read-only + + + B_0x0 + No reset from Option Byte loading occurred + 0x0 + + + B_0x1 + Reset from Option Byte loading occurred + 0x1 + + + + + PINRSTF + Pin reset flag +Set by hardware when a reset from the NRST pin occurs. +Cleared by writing to the RMVF bit. + 26 + 1 + read-only + + + B_0x0 + No reset from NRST pin occurred + 0x0 + + + B_0x1 + Reset from NRST pin occurred + 0x1 + + + + + BORRSTF + BOR flag +Set by hardware when a BOR occurs. +Cleared by writing to the RMVF bit. + 27 + 1 + read-only + + + B_0x0 + No BOR occurred + 0x0 + + + B_0x1 + BOR occurred + 0x1 + + + + + SFTRSTF + Software reset flag +Set by hardware when a software reset occurs. +Cleared by writing to the RMVF bit. + 28 + 1 + read-only + + + B_0x0 + No software reset occurred + 0x0 + + + B_0x1 + Software reset occurred + 0x1 + + + + + IWDGRSTF + Independent window watchdog reset flag +Set by hardware when an independent watchdog reset domain occurs. +Cleared by writing to the RMVF bit. + 29 + 1 + read-only + + + B_0x0 + No independent watchdog reset occurred + 0x0 + + + B_0x1 + Independent watchdog reset occurred + 0x1 + + + + + WWDGRSTF + Window watchdog reset flag +Set by hardware when a window watchdog reset occurs. +Cleared by writing to the RMVF bit. + 30 + 1 + read-only + + + B_0x0 + No window watchdog reset occurred + 0x0 + + + B_0x1 + Window watchdog reset occurred + 0x1 + + + + + LPWRRSTF + Low-power reset flag +Set by hardware when a reset occurs due to illegal Stop, Standby or Shutdown mode entry. +Cleared by writing to the RMVF bit. + 31 + 1 + read-only + + + B_0x0 + No illegal mode reset occurred + 0x0 + + + B_0x1 + Illegal mode reset occurred + 0x1 + + + + + + + RCC_CRRCR + RCC_CRRCR + Clock recovery RC register + 0x98 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + HSI48ON + HSI48 clock enable +Set and cleared by software. +Cleared by hardware to stop the HSI48 when entering in Stop, Standby or Shutdown modes. + 0 + 1 + read-write + + + B_0x0 + HSI48 oscillator OFF + 0x0 + + + B_0x1 + HSI48 oscillator ON + 0x1 + + + + + HSI48RDY + HSI48 clock ready flag +Set by hardware to indicate that HSI48 oscillator is stable. This bit is set only when HSI48 is enabled by software by setting HSI48ON. + 1 + 1 + read-only + + + B_0x0 + HSI48 oscillator not ready + 0x0 + + + B_0x1 + HSI48 oscillator ready + 0x1 + + + + + HSI48CAL + HSI48 clock calibration +These bits are initialized at startup with the factory-programmed HSI48 calibration trim value. +They are ready only. + 7 + 9 + read-only + + + + + RCC_CCIPR2 + RCC_CCIPR2 + Peripherals independent clock configuration register + 0x9C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + I2C4SEL + I2C4 clock source selection +These bits are set and cleared by software to select the I2C4 clock source. + 0 + 2 + read-write + + + B_0x0 + PCLK selected as I2C4 clock + 0x0 + + + B_0x1 + System clock (SYSCLK) selected as I2C4 clock + 0x1 + + + B_0x2 + HSI16 clock selected as I2C4 clock + 0x2 + + + + + QSPISEL + QUADSPI clock source selection +Set and reset by software. + 20 + 2 + read-write + + + B_0x0 + system clock selected as QUADSPI kernel clock + 0x0 + + + B_0x1 + HSI16 clock selected as QUADSPI kernel clock + 0x1 + + + B_0x2 + PLL Q clock selected as QUADSPI kernel clock + 0x2 + + + + + + + + + PWR + Power control + PWR + 0x40007000 + + 0x0 + 0x400 + registers + + + + PWR_CR1 + PWR_CR1 + Power control register 1 + 0x00 + 0x20 + 0x00000200 + 0xFFFFFFFF + + + LPMS + Low-power mode selection +These bits select the low-power mode entered when CPU enters the deepsleep mode. +1xx: Shutdown mode +Note: In Standby mode, SRAM2 can be preserved or not, depending on RRS bit configuration in PWR_CR3. + 0 + 3 + read-write + + + B_0x0 + Stop 0 mode + 0x0 + + + B_0x1 + Stop 1 mode + 0x1 + + + B_0x3 + Standby mode + 0x3 + + + + + FPD_STOP + FPD_STOP + 3 + 1 + read-write + + + DBP + Disable backup domain write protection +In reset state, the RTC and backup registers are protected against parasitic write access. This bit must be set to enable write access to these registers. + 8 + 1 + read-write + + + B_0x0 + Access to RTC and Backup registers disabled + 0x0 + + + B_0x1 + Access to RTC and Backup registers enabled + 0x1 + + + + + VOS + Voltage scaling range selection + 9 + 2 + read-write + + + B_0x0 + Cannot be written (forbidden by hardware) + 0x0 + + + B_0x1 + Range 1 + 0x1 + + + B_0x2 + Range 2 + 0x2 + + + B_0x3 + Cannot be written (forbidden by hardware) + 0x3 + + + + + LPR + Low-power run +When this bit is set, the regulator is switched from main mode (MR) to low-power mode (LPR). + 14 + 1 + read-write + + + + + PWR_CR2 + PWR_CR2 + Power control register 2 + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PVDE + Programmable voltage detector enable +Note: This bit is write-protected when the PVDL bit is set in the SYSCFG_CFGR2 register. The protection can be reset only by a system reset. + 0 + 1 + read-write + + + B_0x0 + Programmable voltage detector disable. + 0x0 + + + B_0x1 + Programmable voltage detector enable. + 0x1 + + + + + PVDLS + Programmable voltage detector level selection. +These bits select the PVD falling threshold: +Note: These bits are write-protected when the PVDL bit is set in the SYSCFG_CFGR2 register. The protection can be reset only by a system reset. + 1 + 3 + read-write + + + B_0x0 + V<sub>PVD0</sub> PVD threshold 0 + 0x0 + + + B_0x1 + V<sub>PVD1</sub> PVD threshold 1 + 0x1 + + + B_0x2 + V<sub>PVD2</sub> PVD threshold 2 + 0x2 + + + B_0x3 + V<sub>PVD3</sub> PVD threshold 3 + 0x3 + + + B_0x4 + V<sub>PVD4</sub> PVD threshold 4 + 0x4 + + + B_0x5 + V<sub>PVD5</sub> PVD threshold 5 + 0x5 + + + B_0x6 + V<sub>PVD6</sub> PVD threshold 6 + 0x6 + + + B_0x7 + External input analog voltage PVD_IN (compared internally to V<sub>REFINT</sub>) + 0x7 + + + + + PVMEN1 + Peripheral voltage monitoring 3 enable: V<sub>DDA</sub> vs. ADC/COMP min voltage 1.62V + 6 + 1 + read-write + + + B_0x0 + PVM1 (V<sub>DDA</sub> monitoring vs. 1.62V threshold) disable. + 0x0 + + + B_0x1 + PVM1 (V<sub>DDA</sub> monitoring vs. 1.62V threshold) enable. + 0x1 + + + + + PVMEN2 + Peripheral voltage monitoring 4 enable: V<sub>DDA</sub> vs. DAC 1MSPS /DAC 15MSPS min voltage. + 7 + 1 + read-write + + + B_0x0 + PVM2 (V<sub>DDA</sub> monitoring vs. 1.8 V threshold) disable. + 0x0 + + + B_0x1 + PVM2 (V<sub>DDA</sub> monitoring vs. 1.8 V threshold) enable. + 0x1 + + + + + + + PWR_CR3 + PWR_CR3 + Power control register 3 + 0x08 + 0x20 + 0x00008000 + 0xFFFFFFFF + + + EWUP1 + Enable Wakeup pin WKUP1 +When this bit is set, the external wakeup pin WKUP1 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP1 bit in the PWR_CR4 register. + 0 + 1 + read-write + + + EWUP2 + Enable Wakeup pin WKUP2 +When this bit is set, the external wakeup pin WKUP2 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP2 bit in the PWR_CR4 register. + 1 + 1 + read-write + + + EWUP3 + Enable Wakeup pin WKUP3 +When this bit is set, the external wakeup pin WKUP3 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP3 bit in the PWR_CR4 register. + 2 + 1 + read-write + + + EWUP4 + Enable Wakeup pin WKUP4 +When this bit is set, the external wakeup pin WKUP4 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP4 bit in the PWR_CR4 register. + 3 + 1 + read-write + + + EWUP5 + Enable Wakeup pin WKUP5 +When this bit is set, the external wakeup pin WKUP5 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs.The active edge is configured via the WP5 bit in the PWR_CR4 register. + 4 + 1 + read-write + + + RRS + SRAM2 retention in Standby mode + 8 + 1 + read-write + + + B_0x0 + SRAM2 is powered off in Standby mode (SRAM2 content is lost). + 0x0 + + + B_0x1 + SRAM2 is powered by the low-power regulator in Standby mode (SRAM2 content is kept). + 0x1 + + + + + APC + Apply pull-up and pull-down configuration +When this bit is set, the I/O pull-up and pull-down configurations defined in the PWR_PUCRx +and PWR_PDCRx registers are applied. When this bit is cleared, the PWR_PUCRx and +PWR_PDCRx registers are not applied to the I/Os. + 10 + 1 + read-write + + + UCPD1_STDBY + UCPD1_STDBY USB Type-C and Power Delivery standby mode. + 13 + 1 + read-write + + + B_0x0 + Write 0 immediately after standby exit when using UCPD1, (and before writing any UCPD1 registers). + 0x0 + + + B_0x1 + Write 1 just before entering standby when using UCPD1. + 0x1 + + + + + UCPD1_DBDIS + USB Type-C and Power Delivery Dead Battery disable. +After exiting reset, the USB Type-C dead battery behavior is enabled, which may have +a pull-down effect on CC1 and CC2 pins. It is recommended to disable it in all cases, either +to stop this pull-down or to hand over control to the UCPD1 (which should therefore be +initialized before doing the disable). + 14 + 1 + read-write + + + B_0x0 + Enable USB Type-C dead battery pull-down behavior on UCPD1_CC1 and UCPD1_CC2 pins. + 0x0 + + + B_0x1 + Disable USB Type-C dead battery pull-down behavior on UCPD1_CC1 and UCPD1_CC2 pins. + 0x1 + + + + + EIWUL + Enable internal wakeup line + 15 + 1 + read-write + + + B_0x0 + Internal wakeup line disable. + 0x0 + + + B_0x1 + Internal wakeup line enable. + 0x1 + + + + + + + PWR_CR4 + PWR_CR4 + Power control register 4 + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WP1 + Wakeup pin WKUP1 polarity +This bit defines the polarity used for an event detection on external wake-up pin, WKUP1 + 0 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WP2 + Wakeup pin WKUP2 polarity +This bit defines the polarity used for an event detection on external wake-up pin, WKUP2 + 1 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WP3 + Wakeup pin WKUP3 polarity +This bit defines the polarity used for an event detection on external wake-up pin, WKUP3 + 2 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WP4 + Wakeup pin WKUP4 polarity +This bit defines the polarity used for an event detection on external wake-up pin, WKUP4 + 3 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WP5 + Wakeup pin WKUP5 polarity +This bit defines the polarity used for an event detection on external wake-up pin, WKUP5 + 4 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + VBE + V<sub>BAT</sub> battery charging enable + 8 + 1 + read-write + + + B_0x0 + V<sub>BAT</sub> battery charging disable + 0x0 + + + B_0x1 + V<sub>BAT</sub> battery charging enable + 0x1 + + + + + VBRS + V<sub>BAT</sub> battery charging resistor selection + 9 + 1 + read-write + + + B_0x0 + Charge V<sub>BAT</sub> through a 5 kOhms resistor + 0x0 + + + B_0x1 + Charge V<sub>BAT</sub> through a 1.5 kOhms resistor + 0x1 + + + + + + + PWR_SR1 + PWR_SR1 + Power status register 1 + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WUF1 + Wakeup flag 1 +This bit is set when a wakeup event is detected on wakeup pin, WKUP1. It is cleared by writing 1 in the CWUF1 bit of the PWR_SCR register. + 0 + 1 + read-only + + + WUF2 + Wakeup flag 2 +This bit is set when a wakeup event is detected on wakeup pin, WKUP2. It is cleared by writing 1 in the CWUF2 bit of the PWR_SCR register. + 1 + 1 + read-only + + + WUF3 + Wakeup flag 3 +This bit is set when a wakeup event is detected on wakeup pin, WKUP3. It is cleared by writing 1 in the CWUF3 bit of the PWR_SCR register. + 2 + 1 + read-only + + + WUF4 + Wakeup flag 4 +This bit is set when a wakeup event is detected on wakeup pin,WKUP4. It is cleared by writing 1 in the CWUF4 bit of the PWR_SCR register. + 3 + 1 + read-only + + + WUF5 + Wakeup flag 5 +This bit is set when a wakeup event is detected on wakeup pin, WKUP5. It is cleared by writing 1 in the CWUF5 bit of the PWR_SCR register. + 4 + 1 + read-only + + + SBF + Standby flag +This bit is set by hardware when the device enters the Standby mode and is cleared by setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the system reset. + 8 + 1 + read-only + + + B_0x0 + The device did not enter the Standby mode + 0x0 + + + B_0x1 + The device entered the Standby mode + 0x1 + + + + + WUFI + Wakeup flag internal +This bit is set when a wakeup is detected on the internal wakeup line. It is cleared when all internal wakeup sources are cleared. + 15 + 1 + read-only + + + + + PWR_SR2 + PWR_SR2 + Power status register 2 + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + REGLPS + Low-power regulator started +This bit provides the information whether the low-power regulator is ready after a power-on +reset or a Standby/Shutdown. If the Standby mode is entered while REGLPS bit is still cleared, the wakeup from Standby mode time may be increased. + 8 + 1 + read-only + + + B_0x0 + The low-power regulator is not ready + 0x0 + + + B_0x1 + The low-power regulator is ready + 0x1 + + + + + REGLPF + Low-power regulator flag +This bit is set by hardware when the MCU is in Low-power run mode. When the MCU exits +the Low-power run mode, this bit remains at 1 until the regulator is ready in main mode. A polling on this bit must be done before increasing the product frequency. +This bit is cleared by hardware when the regulator is ready. + 9 + 1 + read-only + + + B_0x0 + The regulator is ready in main mode (MR) + 0x0 + + + B_0x1 + The regulator is in low-power mode (LPR) + 0x1 + + + + + VOSF + Voltage scaling flag +A delay is required for the internal regulator to be ready after the voltage scaling has been changed. VOSF indicates that the regulator reached the voltage level defined with VOS bits of the PWR_CR1 register. + 10 + 1 + read-only + + + B_0x0 + The regulator is ready in the selected voltage range + 0x0 + + + B_0x1 + The regulator output voltage is changing to the required voltage level + 0x1 + + + + + PVDO + Programmable voltage detector output + 11 + 1 + read-only + + + B_0x0 + V<sub>DD</sub> is above the selected PVD threshold + 0x0 + + + B_0x1 + V<sub>DD</sub> is below the selected PVD threshold + 0x1 + + + + + PVMO1 + Peripheral voltage monitoring output: V<sub>DDA</sub> vs. 1.62 V +Note: PVMO1 is cleared when PVM1 is disabled (PVME = 0). After enabling PVM1, the PVM1 output is valid after the PVM1 wakeup time. + 14 + 1 + read-only + + + B_0x0 + V<sub>DDA</sub> voltage is above PVM1 threshold (around 1.62 V). + 0x0 + + + B_0x1 + V<sub>DDA</sub> voltage is below PVM1 threshold (around 1.62 V). + 0x1 + + + + + PVMO2 + Peripheral voltage monitoring output: V<sub>DDA</sub> vs. 1.8 V +Note: PVMO2 is cleared when PVM2 is disabled (PVME = 0). After enabling PVM2, the PVM2 output is valid after the PVM2 wakeup time. + 15 + 1 + read-only + + + B_0x0 + V<sub>DDA</sub> voltage is above PVM2 threshold (around 1.8 V). + 0x0 + + + B_0x1 + V<sub>DDA</sub> voltage is below PVM2 threshold (around 1.8 V). + 0x1 + + + + + + + PWR_SCR + PWR_SCR + Power status clear register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CWUF1 + Clear wakeup flag 1 +Setting this bit clears the WUF1 flag in the PWR_SR1 register. + 0 + 1 + write-only + + + CWUF2 + Clear wakeup flag 2 +Setting this bit clears the WUF2 flag in the PWR_SR1 register. + 1 + 1 + write-only + + + CWUF3 + Clear wakeup flag 3 +Setting this bit clears the WUF3 flag in the PWR_SR1 register. + 2 + 1 + write-only + + + CWUF4 + Clear wakeup flag 4 +Setting this bit clears the WUF4 flag in the PWR_SR1 register. + 3 + 1 + write-only + + + CWUF5 + Clear wakeup flag 5 +Setting this bit clears the WUF5 flag in the PWR_SR1 register. + 4 + 1 + write-only + + + CSBF + Clear standby flag +Setting this bit clears the SBF flag in the PWR_SR1 register. + 8 + 1 + write-only + + + + + PWR_PUCRA + PWR_PUCRA + Power Port A pull-up control register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PU0 + Port A pull-up bit y (y=0..13) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 0 + 1 + read-write + + + PU1 + Port A pull-up bit y (y=0..13) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 1 + 1 + read-write + + + PU2 + Port A pull-up bit y (y=0..13) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 2 + 1 + read-write + + + PU3 + Port A pull-up bit y (y=0..13) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 3 + 1 + read-write + + + PU4 + Port A pull-up bit y (y=0..13) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 4 + 1 + read-write + + + PU5 + Port A pull-up bit y (y=0..13) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 5 + 1 + read-write + + + PU6 + Port A pull-up bit y (y=0..13) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 6 + 1 + read-write + + + PU7 + Port A pull-up bit y (y=0..13) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 7 + 1 + read-write + + + PU8 + Port A pull-up bit y (y=0..13) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 8 + 1 + read-write + + + PU9 + Port A pull-up bit y (y=0..13) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 9 + 1 + read-write + + + PU10 + Port A pull-up bit y (y=0..13) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 10 + 1 + read-write + + + PU11 + Port A pull-up bit y (y=0..13) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 11 + 1 + read-write + + + PU12 + Port A pull-up bit y (y=0..13) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 12 + 1 + read-write + + + PU13 + Port A pull-up bit y (y=0..13) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 13 + 1 + read-write + + + PU15 + Port A pull-up bit 15 +When set, this bit activates the pull-up on PA[15] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PD15 bit is also set. + 15 + 1 + read-write + + + + + PWR_PDCRA + PWR_PDCRA + Power Port A pull-down control register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PD0 + Port A pull-down bit y (y=0..12) +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 0 + 1 + read-write + + + PD1 + Port A pull-down bit y (y=0..12) +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 1 + 1 + read-write + + + PD2 + Port A pull-down bit y (y=0..12) +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 2 + 1 + read-write + + + PD3 + Port A pull-down bit y (y=0..12) +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 3 + 1 + read-write + + + PD4 + Port A pull-down bit y (y=0..12) +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 4 + 1 + read-write + + + PD5 + Port A pull-down bit y (y=0..12) +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 5 + 1 + read-write + + + PD6 + Port A pull-down bit y (y=0..12) +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 6 + 1 + read-write + + + PD7 + Port A pull-down bit y (y=0..12) +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 7 + 1 + read-write + + + PD8 + Port A pull-down bit y (y=0..12) +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 8 + 1 + read-write + + + PD9 + Port A pull-down bit y (y=0..12) +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 9 + 1 + read-write + + + PD10 + Port A pull-down bit y (y=0..12) +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 10 + 1 + read-write + + + PD11 + Port A pull-down bit y (y=0..12) +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 11 + 1 + read-write + + + PD12 + Port A pull-down bit y (y=0..12) +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 12 + 1 + read-write + + + PD14 + Port A pull-down bit 14 +When set, this bit activates the pull-down on PA[14] when APC bit is set in PWR_CR3 register. + 14 + 1 + read-write + + + + + PWR_PUCRB + PWR_PUCRB + Power Port B pull-up control register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PU0 + Port B pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 0 + 1 + read-write + + + PU1 + Port B pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 1 + 1 + read-write + + + PU2 + Port B pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 2 + 1 + read-write + + + PU3 + Port B pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 3 + 1 + read-write + + + PU4 + Port B pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 4 + 1 + read-write + + + PU5 + Port B pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 5 + 1 + read-write + + + PU6 + Port B pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 6 + 1 + read-write + + + PU7 + Port B pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 7 + 1 + read-write + + + PU8 + Port B pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 8 + 1 + read-write + + + PU9 + Port B pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 9 + 1 + read-write + + + PU10 + Port B pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 10 + 1 + read-write + + + PU11 + Port B pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 11 + 1 + read-write + + + PU12 + Port B pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 12 + 1 + read-write + + + PU13 + Port B pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 13 + 1 + read-write + + + PU14 + Port B pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 14 + 1 + read-write + + + PU15 + Port B pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 15 + 1 + read-write + + + + + PWR_PDCRB + PWR_PDCRB + Power Port B pull-down control register + 0x2C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PD0 + Port B pull-down bit y (y=0..3) +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 0 + 1 + read-write + + + PD1 + Port B pull-down bit y (y=0..3) +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 1 + 1 + read-write + + + PD2 + Port B pull-down bit y (y=0..3) +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 2 + 1 + read-write + + + PD3 + Port B pull-down bit y (y=0..3) +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 3 + 1 + read-write + + + PD5 + Port B pull-down bit y (y=5..15) +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 5 + 1 + read-write + + + PD6 + Port B pull-down bit y (y=5..15) +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 6 + 1 + read-write + + + PD7 + Port B pull-down bit y (y=5..15) +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 7 + 1 + read-write + + + PD8 + Port B pull-down bit y (y=5..15) +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 8 + 1 + read-write + + + PD9 + Port B pull-down bit y (y=5..15) +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 9 + 1 + read-write + + + PD10 + Port B pull-down bit y (y=5..15) +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 10 + 1 + read-write + + + PD11 + Port B pull-down bit y (y=5..15) +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 11 + 1 + read-write + + + PD12 + Port B pull-down bit y (y=5..15) +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 12 + 1 + read-write + + + PD13 + Port B pull-down bit y (y=5..15) +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 13 + 1 + read-write + + + PD14 + Port B pull-down bit y (y=5..15) +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 14 + 1 + read-write + + + PD15 + Port B pull-down bit y (y=5..15) +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 15 + 1 + read-write + + + + + PWR_PUCRC + PWR_PUCRC + Power Port C pull-up control register + 0x30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PU0 + Port C pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 0 + 1 + read-write + + + PU1 + Port C pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 1 + 1 + read-write + + + PU2 + Port C pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 2 + 1 + read-write + + + PU3 + Port C pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 3 + 1 + read-write + + + PU4 + Port C pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 4 + 1 + read-write + + + PU5 + Port C pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 5 + 1 + read-write + + + PU6 + Port C pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 6 + 1 + read-write + + + PU7 + Port C pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 7 + 1 + read-write + + + PU8 + Port C pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 8 + 1 + read-write + + + PU9 + Port C pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 9 + 1 + read-write + + + PU10 + Port C pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 10 + 1 + read-write + + + PU11 + Port C pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 11 + 1 + read-write + + + PU12 + Port C pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 12 + 1 + read-write + + + PU13 + Port C pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 13 + 1 + read-write + + + PU14 + Port C pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 14 + 1 + read-write + + + PU15 + Port C pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 15 + 1 + read-write + + + + + PWR_PDCRC + PWR_PDCRC + Power Port C pull-down control register + 0x34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PD0 + Port C pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 0 + 1 + read-write + + + PD1 + Port C pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 1 + 1 + read-write + + + PD2 + Port C pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 2 + 1 + read-write + + + PD3 + Port C pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 3 + 1 + read-write + + + PD4 + Port C pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 4 + 1 + read-write + + + PD5 + Port C pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 5 + 1 + read-write + + + PD6 + Port C pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 6 + 1 + read-write + + + PD7 + Port C pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 7 + 1 + read-write + + + PD8 + Port C pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 8 + 1 + read-write + + + PD9 + Port C pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 9 + 1 + read-write + + + PD10 + Port C pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 10 + 1 + read-write + + + PD11 + Port C pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 11 + 1 + read-write + + + PD12 + Port C pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 12 + 1 + read-write + + + PD13 + Port C pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 13 + 1 + read-write + + + PD14 + Port C pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 14 + 1 + read-write + + + PD15 + Port C pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 15 + 1 + read-write + + + + + PWR_PUCRD + PWR_PUCRD + Power Port D pull-up control register + 0x38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PU0 + Port D pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 0 + 1 + read-write + + + PU1 + Port D pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 1 + 1 + read-write + + + PU2 + Port D pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 2 + 1 + read-write + + + PU3 + Port D pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 3 + 1 + read-write + + + PU4 + Port D pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 4 + 1 + read-write + + + PU5 + Port D pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 5 + 1 + read-write + + + PU6 + Port D pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 6 + 1 + read-write + + + PU7 + Port D pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 7 + 1 + read-write + + + PU8 + Port D pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 8 + 1 + read-write + + + PU9 + Port D pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 9 + 1 + read-write + + + PU10 + Port D pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 10 + 1 + read-write + + + PU11 + Port D pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 11 + 1 + read-write + + + PU12 + Port D pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 12 + 1 + read-write + + + PU13 + Port D pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 13 + 1 + read-write + + + PU14 + Port D pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 14 + 1 + read-write + + + PU15 + Port D pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 15 + 1 + read-write + + + + + PWR_PDCRD + PWR_PDCRD + Power Port D pull-down control register + 0x3C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PD0 + Port D pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 0 + 1 + read-write + + + PD1 + Port D pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 1 + 1 + read-write + + + PD2 + Port D pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 2 + 1 + read-write + + + PD3 + Port D pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 3 + 1 + read-write + + + PD4 + Port D pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 4 + 1 + read-write + + + PD5 + Port D pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 5 + 1 + read-write + + + PD6 + Port D pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 6 + 1 + read-write + + + PD7 + Port D pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 7 + 1 + read-write + + + PD8 + Port D pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 8 + 1 + read-write + + + PD9 + Port D pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 9 + 1 + read-write + + + PD10 + Port D pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 10 + 1 + read-write + + + PD11 + Port D pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 11 + 1 + read-write + + + PD12 + Port D pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 12 + 1 + read-write + + + PD13 + Port D pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 13 + 1 + read-write + + + PD14 + Port D pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 14 + 1 + read-write + + + PD15 + Port D pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 15 + 1 + read-write + + + + + PWR_PUCRE + PWR_PUCRE + Power Port E pull-up control register + 0x40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PU0 + Port E pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 0 + 1 + read-write + + + PU1 + Port E pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 1 + 1 + read-write + + + PU2 + Port E pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 2 + 1 + read-write + + + PU3 + Port E pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 3 + 1 + read-write + + + PU4 + Port E pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 4 + 1 + read-write + + + PU5 + Port E pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 5 + 1 + read-write + + + PU6 + Port E pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 6 + 1 + read-write + + + PU7 + Port E pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 7 + 1 + read-write + + + PU8 + Port E pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 8 + 1 + read-write + + + PU9 + Port E pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 9 + 1 + read-write + + + PU10 + Port E pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 10 + 1 + read-write + + + PU11 + Port E pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 11 + 1 + read-write + + + PU12 + Port E pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 12 + 1 + read-write + + + PU13 + Port E pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 13 + 1 + read-write + + + PU14 + Port E pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 14 + 1 + read-write + + + PU15 + Port E pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 15 + 1 + read-write + + + + + PWR_PDCRE + PWR_PDCRE + Power Port E pull-down control register + 0x44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PD0 + Port E pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 0 + 1 + read-write + + + PD1 + Port E pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 1 + 1 + read-write + + + PD2 + Port E pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 2 + 1 + read-write + + + PD3 + Port E pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 3 + 1 + read-write + + + PD4 + Port E pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 4 + 1 + read-write + + + PD5 + Port E pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 5 + 1 + read-write + + + PD6 + Port E pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 6 + 1 + read-write + + + PD7 + Port E pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 7 + 1 + read-write + + + PD8 + Port E pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 8 + 1 + read-write + + + PD9 + Port E pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 9 + 1 + read-write + + + PD10 + Port E pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 10 + 1 + read-write + + + PD11 + Port E pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 11 + 1 + read-write + + + PD12 + Port E pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 12 + 1 + read-write + + + PD13 + Port E pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 13 + 1 + read-write + + + PD14 + Port E pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 14 + 1 + read-write + + + PD15 + Port E pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 15 + 1 + read-write + + + + + PWR_PUCRF + PWR_PUCRF + Power Port F pull-up control register + 0x48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PU0 + Port F pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 0 + 1 + read-write + + + PU1 + Port F pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 1 + 1 + read-write + + + PU2 + Port F pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 2 + 1 + read-write + + + PU3 + Port F pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 3 + 1 + read-write + + + PU4 + Port F pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 4 + 1 + read-write + + + PU5 + Port F pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 5 + 1 + read-write + + + PU6 + Port F pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 6 + 1 + read-write + + + PU7 + Port F pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 7 + 1 + read-write + + + PU8 + Port F pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 8 + 1 + read-write + + + PU9 + Port F pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 9 + 1 + read-write + + + PU10 + Port F pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 10 + 1 + read-write + + + PU11 + Port F pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 11 + 1 + read-write + + + PU12 + Port F pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 12 + 1 + read-write + + + PU13 + Port F pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 13 + 1 + read-write + + + PU14 + Port F pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 14 + 1 + read-write + + + PU15 + Port F pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 15 + 1 + read-write + + + + + PWR_PDCRF + PWR_PDCRF + Power Port F pull-down control register + 0x4C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PD0 + Port F pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. + 0 + 1 + read-write + + + PD1 + Port F pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. + 1 + 1 + read-write + + + PD2 + Port F pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. + 2 + 1 + read-write + + + PD3 + Port F pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. + 3 + 1 + read-write + + + PD4 + Port F pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. + 4 + 1 + read-write + + + PD5 + Port F pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. + 5 + 1 + read-write + + + PD6 + Port F pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. + 6 + 1 + read-write + + + PD7 + Port F pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. + 7 + 1 + read-write + + + PD8 + Port F pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. + 8 + 1 + read-write + + + PD9 + Port F pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. + 9 + 1 + read-write + + + PD10 + Port F pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. + 10 + 1 + read-write + + + PD11 + Port F pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. + 11 + 1 + read-write + + + PD12 + Port F pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. + 12 + 1 + read-write + + + PD13 + Port F pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. + 13 + 1 + read-write + + + PD14 + Port F pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. + 14 + 1 + read-write + + + PD15 + Port F pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. + 15 + 1 + read-write + + + + + PWR_PUCRG + PWR_PUCRG + Power Port G pull-up control register + 0x50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PU0 + Port G pull-up bit y (y=0..10) +When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 0 + 1 + read-write + + + PU1 + Port G pull-up bit y (y=0..10) +When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 1 + 1 + read-write + + + PU2 + Port G pull-up bit y (y=0..10) +When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 2 + 1 + read-write + + + PU3 + Port G pull-up bit y (y=0..10) +When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 3 + 1 + read-write + + + PU4 + Port G pull-up bit y (y=0..10) +When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 4 + 1 + read-write + + + PU5 + Port G pull-up bit y (y=0..10) +When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 5 + 1 + read-write + + + PU6 + Port G pull-up bit y (y=0..10) +When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 6 + 1 + read-write + + + PU7 + Port G pull-up bit y (y=0..10) +When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 7 + 1 + read-write + + + PU8 + Port G pull-up bit y (y=0..10) +When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 8 + 1 + read-write + + + PU9 + Port G pull-up bit y (y=0..10) +When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 9 + 1 + read-write + + + PU10 + Port G pull-up bit y (y=0..10) +When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 10 + 1 + read-write + + + + + PWR_PDCRG + PWR_PDCRG + Power Port G pull-down control register + 0x54 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PD0 + Port G pull-down bit y (y=0..10) +When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. + 0 + 1 + read-write + + + PD1 + Port G pull-down bit y (y=0..10) +When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. + 1 + 1 + read-write + + + PD2 + Port G pull-down bit y (y=0..10) +When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. + 2 + 1 + read-write + + + PD3 + Port G pull-down bit y (y=0..10) +When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. + 3 + 1 + read-write + + + PD4 + Port G pull-down bit y (y=0..10) +When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. + 4 + 1 + read-write + + + PD5 + Port G pull-down bit y (y=0..10) +When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. + 5 + 1 + read-write + + + PD6 + Port G pull-down bit y (y=0..10) +When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. + 6 + 1 + read-write + + + PD7 + Port G pull-down bit y (y=0..10) +When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. + 7 + 1 + read-write + + + PD8 + Port G pull-down bit y (y=0..10) +When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. + 8 + 1 + read-write + + + PD9 + Port G pull-down bit y (y=0..10) +When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. + 9 + 1 + read-write + + + PD10 + Port G pull-down bit y (y=0..10) +When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. + 10 + 1 + read-write + + + + + PWR_CR5 + PWR_CR5 + Power control register + 0x80 + 0x20 + 0x00000100 + 0xFFFFFFFF + + + R1MODE + Main regular range 1 mode +This bit is only valid for the main regulator in range 1 and has no effect on range 2. It is recommended to reset this bit when the system frequency is greater than 150 MHz. Refer to + 8 + 1 + read-write + + + B_0x0 + Main regulator in range 1 boost mode. + 0x0 + + + B_0x1 + Main regulator in range 1 normal mode. + 0x1 + + + + + + + + + RNG + Random number generator + RNG + 0x50060800 + + 0x0 + 0x400 + registers + + + RNG + RNG + 90 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + CED + Clock error detection + 5 + 1 + + + IE + Interrupt enable + 3 + 1 + + + RNGEN + Random number generator enable + 2 + 1 + + + + + SR + SR + status register + 0x4 + 0x20 + 0x00000000 + + + SEIS + Seed error interrupt status + 6 + 1 + read-write + + + CEIS + Clock error interrupt status + 5 + 1 + read-write + + + SECS + Seed error current status + 2 + 1 + read-only + + + CECS + Clock error current status + 1 + 1 + read-only + + + DRDY + Data ready + 0 + 1 + read-only + + + + + DR + DR + data register + 0x8 + 0x20 + read-only + 0x00000000 + + + RNDATA + Random data + 0 + 32 + + + + + + + GPIOA + General-purpose I/Os + GPIO + 0x48000000 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xABFFFFFF + + + MODER15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + MODER14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + MODER13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + MODER12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + MODER11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + MODER10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + MODER9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + MODER8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + MODER7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + MODER6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + MODER5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + MODER4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + MODER3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + MODER2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + MODER1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + MODER0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT15 + Port x configuration bits (y = 0..15) + 15 + 1 + + + OT14 + Port x configuration bits (y = 0..15) + 14 + 1 + + + OT13 + Port x configuration bits (y = 0..15) + 13 + 1 + + + OT12 + Port x configuration bits (y = 0..15) + 12 + 1 + + + OT11 + Port x configuration bits (y = 0..15) + 11 + 1 + + + OT10 + Port x configuration bits (y = 0..15) + 10 + 1 + + + OT9 + Port x configuration bits (y = 0..15) + 9 + 1 + + + OT8 + Port x configuration bits (y = 0..15) + 8 + 1 + + + OT7 + Port x configuration bits (y = 0..15) + 7 + 1 + + + OT6 + Port x configuration bits (y = 0..15) + 6 + 1 + + + OT5 + Port x configuration bits (y = 0..15) + 5 + 1 + + + OT4 + Port x configuration bits (y = 0..15) + 4 + 1 + + + OT3 + Port x configuration bits (y = 0..15) + 3 + 1 + + + OT2 + Port x configuration bits (y = 0..15) + 2 + 1 + + + OT1 + Port x configuration bits (y = 0..15) + 1 + 1 + + + OT0 + Port x configuration bits (y = 0..15) + 0 + 1 + + + + + OSPEEDR + OSPEEDR + GPIO port output speed register + 0x8 + 0x20 + read-write + 0x0C000000 + + + OSPEEDR15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + OSPEEDR14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + OSPEEDR13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + OSPEEDR12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + OSPEEDR11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + OSPEEDR10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + OSPEEDR9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + OSPEEDR8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + OSPEEDR7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + OSPEEDR6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + OSPEEDR5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + OSPEEDR4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + OSPEEDR3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + OSPEEDR2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + OSPEEDR1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + OSPEEDR0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down register + 0xC + 0x20 + read-write + 0x64000000 + + + PUPDR15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + PUPDR14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + PUPDR13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + PUPDR12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + PUPDR11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + PUPDR10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + PUPDR9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + PUPDR8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + PUPDR7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + PUPDR6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + PUPDR5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + PUPDR4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + PUPDR3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + PUPDR2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + PUPDR1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + PUPDR0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR15 + Port input data (y = 0..15) + 15 + 1 + + + IDR14 + Port input data (y = 0..15) + 14 + 1 + + + IDR13 + Port input data (y = 0..15) + 13 + 1 + + + IDR12 + Port input data (y = 0..15) + 12 + 1 + + + IDR11 + Port input data (y = 0..15) + 11 + 1 + + + IDR10 + Port input data (y = 0..15) + 10 + 1 + + + IDR9 + Port input data (y = 0..15) + 9 + 1 + + + IDR8 + Port input data (y = 0..15) + 8 + 1 + + + IDR7 + Port input data (y = 0..15) + 7 + 1 + + + IDR6 + Port input data (y = 0..15) + 6 + 1 + + + IDR5 + Port input data (y = 0..15) + 5 + 1 + + + IDR4 + Port input data (y = 0..15) + 4 + 1 + + + IDR3 + Port input data (y = 0..15) + 3 + 1 + + + IDR2 + Port input data (y = 0..15) + 2 + 1 + + + IDR1 + Port input data (y = 0..15) + 1 + 1 + + + IDR0 + Port input data (y = 0..15) + 0 + 1 + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR15 + Port output data (y = 0..15) + 15 + 1 + + + ODR14 + Port output data (y = 0..15) + 14 + 1 + + + ODR13 + Port output data (y = 0..15) + 13 + 1 + + + ODR12 + Port output data (y = 0..15) + 12 + 1 + + + ODR11 + Port output data (y = 0..15) + 11 + 1 + + + ODR10 + Port output data (y = 0..15) + 10 + 1 + + + ODR9 + Port output data (y = 0..15) + 9 + 1 + + + ODR8 + Port output data (y = 0..15) + 8 + 1 + + + ODR7 + Port output data (y = 0..15) + 7 + 1 + + + ODR6 + Port output data (y = 0..15) + 6 + 1 + + + ODR5 + Port output data (y = 0..15) + 5 + 1 + + + ODR4 + Port output data (y = 0..15) + 4 + 1 + + + ODR3 + Port output data (y = 0..15) + 3 + 1 + + + ODR2 + Port output data (y = 0..15) + 2 + 1 + + + ODR1 + Port output data (y = 0..15) + 1 + 1 + + + ODR0 + Port output data (y = 0..15) + 0 + 1 + + + + + BSRR + BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + + + BR15 + Port x reset bit y (y = 0..15) + 31 + 1 + + + BR14 + Port x reset bit y (y = 0..15) + 30 + 1 + + + BR13 + Port x reset bit y (y = 0..15) + 29 + 1 + + + BR12 + Port x reset bit y (y = 0..15) + 28 + 1 + + + BR11 + Port x reset bit y (y = 0..15) + 27 + 1 + + + BR10 + Port x reset bit y (y = 0..15) + 26 + 1 + + + BR9 + Port x reset bit y (y = 0..15) + 25 + 1 + + + BR8 + Port x reset bit y (y = 0..15) + 24 + 1 + + + BR7 + Port x reset bit y (y = 0..15) + 23 + 1 + + + BR6 + Port x reset bit y (y = 0..15) + 22 + 1 + + + BR5 + Port x reset bit y (y = 0..15) + 21 + 1 + + + BR4 + Port x reset bit y (y = 0..15) + 20 + 1 + + + BR3 + Port x reset bit y (y = 0..15) + 19 + 1 + + + BR2 + Port x reset bit y (y = 0..15) + 18 + 1 + + + BR1 + Port x reset bit y (y = 0..15) + 17 + 1 + + + BR0 + Port x set bit y (y= 0..15) + 16 + 1 + + + BS15 + Port x set bit y (y= 0..15) + 15 + 1 + + + BS14 + Port x set bit y (y= 0..15) + 14 + 1 + + + BS13 + Port x set bit y (y= 0..15) + 13 + 1 + + + BS12 + Port x set bit y (y= 0..15) + 12 + 1 + + + BS11 + Port x set bit y (y= 0..15) + 11 + 1 + + + BS10 + Port x set bit y (y= 0..15) + 10 + 1 + + + BS9 + Port x set bit y (y= 0..15) + 9 + 1 + + + BS8 + Port x set bit y (y= 0..15) + 8 + 1 + + + BS7 + Port x set bit y (y= 0..15) + 7 + 1 + + + BS6 + Port x set bit y (y= 0..15) + 6 + 1 + + + BS5 + Port x set bit y (y= 0..15) + 5 + 1 + + + BS4 + Port x set bit y (y= 0..15) + 4 + 1 + + + BS3 + Port x set bit y (y= 0..15) + 3 + 1 + + + BS2 + Port x set bit y (y= 0..15) + 2 + 1 + + + BS1 + Port x set bit y (y= 0..15) + 1 + 1 + + + BS0 + Port x set bit y (y= 0..15) + 0 + 1 + + + + + LCKR + LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y (y= 0..15) + 16 + 1 + + + LCK15 + Port x lock bit y (y= 0..15) + 15 + 1 + + + LCK14 + Port x lock bit y (y= 0..15) + 14 + 1 + + + LCK13 + Port x lock bit y (y= 0..15) + 13 + 1 + + + LCK12 + Port x lock bit y (y= 0..15) + 12 + 1 + + + LCK11 + Port x lock bit y (y= 0..15) + 11 + 1 + + + LCK10 + Port x lock bit y (y= 0..15) + 10 + 1 + + + LCK9 + Port x lock bit y (y= 0..15) + 9 + 1 + + + LCK8 + Port x lock bit y (y= 0..15) + 8 + 1 + + + LCK7 + Port x lock bit y (y= 0..15) + 7 + 1 + + + LCK6 + Port x lock bit y (y= 0..15) + 6 + 1 + + + LCK5 + Port x lock bit y (y= 0..15) + 5 + 1 + + + LCK4 + Port x lock bit y (y= 0..15) + 4 + 1 + + + LCK3 + Port x lock bit y (y= 0..15) + 3 + 1 + + + LCK2 + Port x lock bit y (y= 0..15) + 2 + 1 + + + LCK1 + Port x lock bit y (y= 0..15) + 1 + 1 + + + LCK0 + Port x lock bit y (y= 0..15) + 0 + 1 + + + + + AFRL + AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFRL7 + Alternate function selection for port x bit y (y = 0..7) + 28 + 4 + + + AFRL6 + Alternate function selection for port x bit y (y = 0..7) + 24 + 4 + + + AFRL5 + Alternate function selection for port x bit y (y = 0..7) + 20 + 4 + + + AFRL4 + Alternate function selection for port x bit y (y = 0..7) + 16 + 4 + + + AFRL3 + Alternate function selection for port x bit y (y = 0..7) + 12 + 4 + + + AFRL2 + Alternate function selection for port x bit y (y = 0..7) + 8 + 4 + + + AFRL1 + Alternate function selection for port x bit y (y = 0..7) + 4 + 4 + + + AFRL0 + Alternate function selection for port x bit y (y = 0..7) + 0 + 4 + + + + + AFRH + AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFRH15 + Alternate function selection for port x bit y (y = 8..15) + 28 + 4 + + + AFRH14 + Alternate function selection for port x bit y (y = 8..15) + 24 + 4 + + + AFRH13 + Alternate function selection for port x bit y (y = 8..15) + 20 + 4 + + + AFRH12 + Alternate function selection for port x bit y (y = 8..15) + 16 + 4 + + + AFRH11 + Alternate function selection for port x bit y (y = 8..15) + 12 + 4 + + + AFRH10 + Alternate function selection for port x bit y (y = 8..15) + 8 + 4 + + + AFRH9 + Alternate function selection for port x bit y (y = 8..15) + 4 + 4 + + + AFRH8 + Alternate function selection for port x bit y (y = 8..15) + 0 + 4 + + + + + BRR + BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + Port Reset bit + 0 + 1 + + + BR1 + Port Reset bit + 1 + 1 + + + BR2 + Port Reset bit + 2 + 1 + + + BR3 + Port Reset bit + 3 + 1 + + + BR4 + Port Reset bit + 4 + 1 + + + BR5 + Port Reset bit + 5 + 1 + + + BR6 + Port Reset bit + 6 + 1 + + + BR7 + Port Reset bit + 7 + 1 + + + BR8 + Port Reset bit + 8 + 1 + + + BR9 + Port Reset bit + 9 + 1 + + + BR10 + Port Reset bit + 10 + 1 + + + BR11 + Port Reset bit + 11 + 1 + + + BR12 + Port Reset bit + 12 + 1 + + + BR13 + Port Reset bit + 13 + 1 + + + BR14 + Port Reset bit + 14 + 1 + + + BR15 + Port Reset bit + 15 + 1 + + + + + + + GPIOB + General-purpose I/Os + GPIO + 0x48000400 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xFFFFFEBF + + + MODER15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + MODER14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + MODER13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + MODER12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + MODER11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + MODER10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + MODER9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + MODER8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + MODER7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + MODER6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + MODER5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + MODER4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + MODER3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + MODER2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + MODER1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + MODER0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT15 + Port x configuration bits (y = 0..15) + 15 + 1 + + + OT14 + Port x configuration bits (y = 0..15) + 14 + 1 + + + OT13 + Port x configuration bits (y = 0..15) + 13 + 1 + + + OT12 + Port x configuration bits (y = 0..15) + 12 + 1 + + + OT11 + Port x configuration bits (y = 0..15) + 11 + 1 + + + OT10 + Port x configuration bits (y = 0..15) + 10 + 1 + + + OT9 + Port x configuration bits (y = 0..15) + 9 + 1 + + + OT8 + Port x configuration bits (y = 0..15) + 8 + 1 + + + OT7 + Port x configuration bits (y = 0..15) + 7 + 1 + + + OT6 + Port x configuration bits (y = 0..15) + 6 + 1 + + + OT5 + Port x configuration bits (y = 0..15) + 5 + 1 + + + OT4 + Port x configuration bits (y = 0..15) + 4 + 1 + + + OT3 + Port x configuration bits (y = 0..15) + 3 + 1 + + + OT2 + Port x configuration bits (y = 0..15) + 2 + 1 + + + OT1 + Port x configuration bits (y = 0..15) + 1 + 1 + + + OT0 + Port x configuration bits (y = 0..15) + 0 + 1 + + + + + OSPEEDR + OSPEEDR + GPIO port output speed register + 0x8 + 0x20 + read-write + 0x000000C0 + + + OSPEEDR15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + OSPEEDR14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + OSPEEDR13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + OSPEEDR12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + OSPEEDR11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + OSPEEDR10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + OSPEEDR9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + OSPEEDR8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + OSPEEDR7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + OSPEEDR6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + OSPEEDR5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + OSPEEDR4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + OSPEEDR3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + OSPEEDR2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + OSPEEDR1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + OSPEEDR0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000100 + + + PUPDR15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + PUPDR14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + PUPDR13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + PUPDR12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + PUPDR11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + PUPDR10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + PUPDR9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + PUPDR8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + PUPDR7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + PUPDR6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + PUPDR5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + PUPDR4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + PUPDR3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + PUPDR2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + PUPDR1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + PUPDR0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR15 + Port input data (y = 0..15) + 15 + 1 + + + IDR14 + Port input data (y = 0..15) + 14 + 1 + + + IDR13 + Port input data (y = 0..15) + 13 + 1 + + + IDR12 + Port input data (y = 0..15) + 12 + 1 + + + IDR11 + Port input data (y = 0..15) + 11 + 1 + + + IDR10 + Port input data (y = 0..15) + 10 + 1 + + + IDR9 + Port input data (y = 0..15) + 9 + 1 + + + IDR8 + Port input data (y = 0..15) + 8 + 1 + + + IDR7 + Port input data (y = 0..15) + 7 + 1 + + + IDR6 + Port input data (y = 0..15) + 6 + 1 + + + IDR5 + Port input data (y = 0..15) + 5 + 1 + + + IDR4 + Port input data (y = 0..15) + 4 + 1 + + + IDR3 + Port input data (y = 0..15) + 3 + 1 + + + IDR2 + Port input data (y = 0..15) + 2 + 1 + + + IDR1 + Port input data (y = 0..15) + 1 + 1 + + + IDR0 + Port input data (y = 0..15) + 0 + 1 + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR15 + Port output data (y = 0..15) + 15 + 1 + + + ODR14 + Port output data (y = 0..15) + 14 + 1 + + + ODR13 + Port output data (y = 0..15) + 13 + 1 + + + ODR12 + Port output data (y = 0..15) + 12 + 1 + + + ODR11 + Port output data (y = 0..15) + 11 + 1 + + + ODR10 + Port output data (y = 0..15) + 10 + 1 + + + ODR9 + Port output data (y = 0..15) + 9 + 1 + + + ODR8 + Port output data (y = 0..15) + 8 + 1 + + + ODR7 + Port output data (y = 0..15) + 7 + 1 + + + ODR6 + Port output data (y = 0..15) + 6 + 1 + + + ODR5 + Port output data (y = 0..15) + 5 + 1 + + + ODR4 + Port output data (y = 0..15) + 4 + 1 + + + ODR3 + Port output data (y = 0..15) + 3 + 1 + + + ODR2 + Port output data (y = 0..15) + 2 + 1 + + + ODR1 + Port output data (y = 0..15) + 1 + 1 + + + ODR0 + Port output data (y = 0..15) + 0 + 1 + + + + + BSRR + BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + + + BR15 + Port x reset bit y (y = 0..15) + 31 + 1 + + + BR14 + Port x reset bit y (y = 0..15) + 30 + 1 + + + BR13 + Port x reset bit y (y = 0..15) + 29 + 1 + + + BR12 + Port x reset bit y (y = 0..15) + 28 + 1 + + + BR11 + Port x reset bit y (y = 0..15) + 27 + 1 + + + BR10 + Port x reset bit y (y = 0..15) + 26 + 1 + + + BR9 + Port x reset bit y (y = 0..15) + 25 + 1 + + + BR8 + Port x reset bit y (y = 0..15) + 24 + 1 + + + BR7 + Port x reset bit y (y = 0..15) + 23 + 1 + + + BR6 + Port x reset bit y (y = 0..15) + 22 + 1 + + + BR5 + Port x reset bit y (y = 0..15) + 21 + 1 + + + BR4 + Port x reset bit y (y = 0..15) + 20 + 1 + + + BR3 + Port x reset bit y (y = 0..15) + 19 + 1 + + + BR2 + Port x reset bit y (y = 0..15) + 18 + 1 + + + BR1 + Port x reset bit y (y = 0..15) + 17 + 1 + + + BR0 + Port x set bit y (y= 0..15) + 16 + 1 + + + BS15 + Port x set bit y (y= 0..15) + 15 + 1 + + + BS14 + Port x set bit y (y= 0..15) + 14 + 1 + + + BS13 + Port x set bit y (y= 0..15) + 13 + 1 + + + BS12 + Port x set bit y (y= 0..15) + 12 + 1 + + + BS11 + Port x set bit y (y= 0..15) + 11 + 1 + + + BS10 + Port x set bit y (y= 0..15) + 10 + 1 + + + BS9 + Port x set bit y (y= 0..15) + 9 + 1 + + + BS8 + Port x set bit y (y= 0..15) + 8 + 1 + + + BS7 + Port x set bit y (y= 0..15) + 7 + 1 + + + BS6 + Port x set bit y (y= 0..15) + 6 + 1 + + + BS5 + Port x set bit y (y= 0..15) + 5 + 1 + + + BS4 + Port x set bit y (y= 0..15) + 4 + 1 + + + BS3 + Port x set bit y (y= 0..15) + 3 + 1 + + + BS2 + Port x set bit y (y= 0..15) + 2 + 1 + + + BS1 + Port x set bit y (y= 0..15) + 1 + 1 + + + BS0 + Port x set bit y (y= 0..15) + 0 + 1 + + + + + LCKR + LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y (y= 0..15) + 16 + 1 + + + LCK15 + Port x lock bit y (y= 0..15) + 15 + 1 + + + LCK14 + Port x lock bit y (y= 0..15) + 14 + 1 + + + LCK13 + Port x lock bit y (y= 0..15) + 13 + 1 + + + LCK12 + Port x lock bit y (y= 0..15) + 12 + 1 + + + LCK11 + Port x lock bit y (y= 0..15) + 11 + 1 + + + LCK10 + Port x lock bit y (y= 0..15) + 10 + 1 + + + LCK9 + Port x lock bit y (y= 0..15) + 9 + 1 + + + LCK8 + Port x lock bit y (y= 0..15) + 8 + 1 + + + LCK7 + Port x lock bit y (y= 0..15) + 7 + 1 + + + LCK6 + Port x lock bit y (y= 0..15) + 6 + 1 + + + LCK5 + Port x lock bit y (y= 0..15) + 5 + 1 + + + LCK4 + Port x lock bit y (y= 0..15) + 4 + 1 + + + LCK3 + Port x lock bit y (y= 0..15) + 3 + 1 + + + LCK2 + Port x lock bit y (y= 0..15) + 2 + 1 + + + LCK1 + Port x lock bit y (y= 0..15) + 1 + 1 + + + LCK0 + Port x lock bit y (y= 0..15) + 0 + 1 + + + + + AFRL + AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFRL7 + Alternate function selection for port x bit y (y = 0..7) + 28 + 4 + + + AFRL6 + Alternate function selection for port x bit y (y = 0..7) + 24 + 4 + + + AFRL5 + Alternate function selection for port x bit y (y = 0..7) + 20 + 4 + + + AFRL4 + Alternate function selection for port x bit y (y = 0..7) + 16 + 4 + + + AFRL3 + Alternate function selection for port x bit y (y = 0..7) + 12 + 4 + + + AFRL2 + Alternate function selection for port x bit y (y = 0..7) + 8 + 4 + + + AFRL1 + Alternate function selection for port x bit y (y = 0..7) + 4 + 4 + + + AFRL0 + Alternate function selection for port x bit y (y = 0..7) + 0 + 4 + + + + + AFRH + AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFRH15 + Alternate function selection for port x bit y (y = 8..15) + 28 + 4 + + + AFRH14 + Alternate function selection for port x bit y (y = 8..15) + 24 + 4 + + + AFRH13 + Alternate function selection for port x bit y (y = 8..15) + 20 + 4 + + + AFRH12 + Alternate function selection for port x bit y (y = 8..15) + 16 + 4 + + + AFRH11 + Alternate function selection for port x bit y (y = 8..15) + 12 + 4 + + + AFRH10 + Alternate function selection for port x bit y (y = 8..15) + 8 + 4 + + + AFRH9 + Alternate function selection for port x bit y (y = 8..15) + 4 + 4 + + + AFRH8 + Alternate function selection for port x bit y (y = 8..15) + 0 + 4 + + + + + BRR + BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + Port Reset bit + 0 + 1 + + + BR1 + Port Reset bit + 1 + 1 + + + BR2 + Port Reset bit + 2 + 1 + + + BR3 + Port Reset bit + 3 + 1 + + + BR4 + Port Reset bit + 4 + 1 + + + BR5 + Port Reset bit + 5 + 1 + + + BR6 + Port Reset bit + 6 + 1 + + + BR7 + Port Reset bit + 7 + 1 + + + BR8 + Port Reset bit + 8 + 1 + + + BR9 + Port Reset bit + 9 + 1 + + + BR10 + Port Reset bit + 10 + 1 + + + BR11 + Port Reset bit + 11 + 1 + + + BR12 + Port Reset bit + 12 + 1 + + + BR13 + Port Reset bit + 13 + 1 + + + BR14 + Port Reset bit + 14 + 1 + + + BR15 + Port Reset bit + 15 + 1 + + + + + + + GPIOC + General-purpose I/Os + GPIO + 0x48000800 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + MODER15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + MODER14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + MODER13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + MODER12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + MODER11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + MODER10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + MODER9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + MODER8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + MODER7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + MODER6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + MODER5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + MODER4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + MODER3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + MODER2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + MODER1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + MODER0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT15 + Port x configuration bits (y = 0..15) + 15 + 1 + + + OT14 + Port x configuration bits (y = 0..15) + 14 + 1 + + + OT13 + Port x configuration bits (y = 0..15) + 13 + 1 + + + OT12 + Port x configuration bits (y = 0..15) + 12 + 1 + + + OT11 + Port x configuration bits (y = 0..15) + 11 + 1 + + + OT10 + Port x configuration bits (y = 0..15) + 10 + 1 + + + OT9 + Port x configuration bits (y = 0..15) + 9 + 1 + + + OT8 + Port x configuration bits (y = 0..15) + 8 + 1 + + + OT7 + Port x configuration bits (y = 0..15) + 7 + 1 + + + OT6 + Port x configuration bits (y = 0..15) + 6 + 1 + + + OT5 + Port x configuration bits (y = 0..15) + 5 + 1 + + + OT4 + Port x configuration bits (y = 0..15) + 4 + 1 + + + OT3 + Port x configuration bits (y = 0..15) + 3 + 1 + + + OT2 + Port x configuration bits (y = 0..15) + 2 + 1 + + + OT1 + Port x configuration bits (y = 0..15) + 1 + 1 + + + OT0 + Port x configuration bits (y = 0..15) + 0 + 1 + + + + + OSPEEDR + OSPEEDR + GPIO port output speed register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEEDR15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + OSPEEDR14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + OSPEEDR13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + OSPEEDR12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + OSPEEDR11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + OSPEEDR10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + OSPEEDR9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + OSPEEDR8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + OSPEEDR7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + OSPEEDR6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + OSPEEDR5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + OSPEEDR4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + OSPEEDR3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + OSPEEDR2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + OSPEEDR1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + OSPEEDR0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000000 + + + PUPDR15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + PUPDR14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + PUPDR13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + PUPDR12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + PUPDR11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + PUPDR10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + PUPDR9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + PUPDR8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + PUPDR7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + PUPDR6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + PUPDR5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + PUPDR4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + PUPDR3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + PUPDR2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + PUPDR1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + PUPDR0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR15 + Port input data (y = 0..15) + 15 + 1 + + + IDR14 + Port input data (y = 0..15) + 14 + 1 + + + IDR13 + Port input data (y = 0..15) + 13 + 1 + + + IDR12 + Port input data (y = 0..15) + 12 + 1 + + + IDR11 + Port input data (y = 0..15) + 11 + 1 + + + IDR10 + Port input data (y = 0..15) + 10 + 1 + + + IDR9 + Port input data (y = 0..15) + 9 + 1 + + + IDR8 + Port input data (y = 0..15) + 8 + 1 + + + IDR7 + Port input data (y = 0..15) + 7 + 1 + + + IDR6 + Port input data (y = 0..15) + 6 + 1 + + + IDR5 + Port input data (y = 0..15) + 5 + 1 + + + IDR4 + Port input data (y = 0..15) + 4 + 1 + + + IDR3 + Port input data (y = 0..15) + 3 + 1 + + + IDR2 + Port input data (y = 0..15) + 2 + 1 + + + IDR1 + Port input data (y = 0..15) + 1 + 1 + + + IDR0 + Port input data (y = 0..15) + 0 + 1 + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR15 + Port output data (y = 0..15) + 15 + 1 + + + ODR14 + Port output data (y = 0..15) + 14 + 1 + + + ODR13 + Port output data (y = 0..15) + 13 + 1 + + + ODR12 + Port output data (y = 0..15) + 12 + 1 + + + ODR11 + Port output data (y = 0..15) + 11 + 1 + + + ODR10 + Port output data (y = 0..15) + 10 + 1 + + + ODR9 + Port output data (y = 0..15) + 9 + 1 + + + ODR8 + Port output data (y = 0..15) + 8 + 1 + + + ODR7 + Port output data (y = 0..15) + 7 + 1 + + + ODR6 + Port output data (y = 0..15) + 6 + 1 + + + ODR5 + Port output data (y = 0..15) + 5 + 1 + + + ODR4 + Port output data (y = 0..15) + 4 + 1 + + + ODR3 + Port output data (y = 0..15) + 3 + 1 + + + ODR2 + Port output data (y = 0..15) + 2 + 1 + + + ODR1 + Port output data (y = 0..15) + 1 + 1 + + + ODR0 + Port output data (y = 0..15) + 0 + 1 + + + + + BSRR + BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + + + BR15 + Port x reset bit y (y = 0..15) + 31 + 1 + + + BR14 + Port x reset bit y (y = 0..15) + 30 + 1 + + + BR13 + Port x reset bit y (y = 0..15) + 29 + 1 + + + BR12 + Port x reset bit y (y = 0..15) + 28 + 1 + + + BR11 + Port x reset bit y (y = 0..15) + 27 + 1 + + + BR10 + Port x reset bit y (y = 0..15) + 26 + 1 + + + BR9 + Port x reset bit y (y = 0..15) + 25 + 1 + + + BR8 + Port x reset bit y (y = 0..15) + 24 + 1 + + + BR7 + Port x reset bit y (y = 0..15) + 23 + 1 + + + BR6 + Port x reset bit y (y = 0..15) + 22 + 1 + + + BR5 + Port x reset bit y (y = 0..15) + 21 + 1 + + + BR4 + Port x reset bit y (y = 0..15) + 20 + 1 + + + BR3 + Port x reset bit y (y = 0..15) + 19 + 1 + + + BR2 + Port x reset bit y (y = 0..15) + 18 + 1 + + + BR1 + Port x reset bit y (y = 0..15) + 17 + 1 + + + BR0 + Port x set bit y (y= 0..15) + 16 + 1 + + + BS15 + Port x set bit y (y= 0..15) + 15 + 1 + + + BS14 + Port x set bit y (y= 0..15) + 14 + 1 + + + BS13 + Port x set bit y (y= 0..15) + 13 + 1 + + + BS12 + Port x set bit y (y= 0..15) + 12 + 1 + + + BS11 + Port x set bit y (y= 0..15) + 11 + 1 + + + BS10 + Port x set bit y (y= 0..15) + 10 + 1 + + + BS9 + Port x set bit y (y= 0..15) + 9 + 1 + + + BS8 + Port x set bit y (y= 0..15) + 8 + 1 + + + BS7 + Port x set bit y (y= 0..15) + 7 + 1 + + + BS6 + Port x set bit y (y= 0..15) + 6 + 1 + + + BS5 + Port x set bit y (y= 0..15) + 5 + 1 + + + BS4 + Port x set bit y (y= 0..15) + 4 + 1 + + + BS3 + Port x set bit y (y= 0..15) + 3 + 1 + + + BS2 + Port x set bit y (y= 0..15) + 2 + 1 + + + BS1 + Port x set bit y (y= 0..15) + 1 + 1 + + + BS0 + Port x set bit y (y= 0..15) + 0 + 1 + + + + + LCKR + LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y (y= 0..15) + 16 + 1 + + + LCK15 + Port x lock bit y (y= 0..15) + 15 + 1 + + + LCK14 + Port x lock bit y (y= 0..15) + 14 + 1 + + + LCK13 + Port x lock bit y (y= 0..15) + 13 + 1 + + + LCK12 + Port x lock bit y (y= 0..15) + 12 + 1 + + + LCK11 + Port x lock bit y (y= 0..15) + 11 + 1 + + + LCK10 + Port x lock bit y (y= 0..15) + 10 + 1 + + + LCK9 + Port x lock bit y (y= 0..15) + 9 + 1 + + + LCK8 + Port x lock bit y (y= 0..15) + 8 + 1 + + + LCK7 + Port x lock bit y (y= 0..15) + 7 + 1 + + + LCK6 + Port x lock bit y (y= 0..15) + 6 + 1 + + + LCK5 + Port x lock bit y (y= 0..15) + 5 + 1 + + + LCK4 + Port x lock bit y (y= 0..15) + 4 + 1 + + + LCK3 + Port x lock bit y (y= 0..15) + 3 + 1 + + + LCK2 + Port x lock bit y (y= 0..15) + 2 + 1 + + + LCK1 + Port x lock bit y (y= 0..15) + 1 + 1 + + + LCK0 + Port x lock bit y (y= 0..15) + 0 + 1 + + + + + AFRL + AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFRL7 + Alternate function selection for port x bit y (y = 0..7) + 28 + 4 + + + AFRL6 + Alternate function selection for port x bit y (y = 0..7) + 24 + 4 + + + AFRL5 + Alternate function selection for port x bit y (y = 0..7) + 20 + 4 + + + AFRL4 + Alternate function selection for port x bit y (y = 0..7) + 16 + 4 + + + AFRL3 + Alternate function selection for port x bit y (y = 0..7) + 12 + 4 + + + AFRL2 + Alternate function selection for port x bit y (y = 0..7) + 8 + 4 + + + AFRL1 + Alternate function selection for port x bit y (y = 0..7) + 4 + 4 + + + AFRL0 + Alternate function selection for port x bit y (y = 0..7) + 0 + 4 + + + + + AFRH + AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFRH15 + Alternate function selection for port x bit y (y = 8..15) + 28 + 4 + + + AFRH14 + Alternate function selection for port x bit y (y = 8..15) + 24 + 4 + + + AFRH13 + Alternate function selection for port x bit y (y = 8..15) + 20 + 4 + + + AFRH12 + Alternate function selection for port x bit y (y = 8..15) + 16 + 4 + + + AFRH11 + Alternate function selection for port x bit y (y = 8..15) + 12 + 4 + + + AFRH10 + Alternate function selection for port x bit y (y = 8..15) + 8 + 4 + + + AFRH9 + Alternate function selection for port x bit y (y = 8..15) + 4 + 4 + + + AFRH8 + Alternate function selection for port x bit y (y = 8..15) + 0 + 4 + + + + + BRR + BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + Port Reset bit + 0 + 1 + + + BR1 + Port Reset bit + 1 + 1 + + + BR2 + Port Reset bit + 2 + 1 + + + BR3 + Port Reset bit + 3 + 1 + + + BR4 + Port Reset bit + 4 + 1 + + + BR5 + Port Reset bit + 5 + 1 + + + BR6 + Port Reset bit + 6 + 1 + + + BR7 + Port Reset bit + 7 + 1 + + + BR8 + Port Reset bit + 8 + 1 + + + BR9 + Port Reset bit + 9 + 1 + + + BR10 + Port Reset bit + 10 + 1 + + + BR11 + Port Reset bit + 11 + 1 + + + BR12 + Port Reset bit + 12 + 1 + + + BR13 + Port Reset bit + 13 + 1 + + + BR14 + Port Reset bit + 14 + 1 + + + BR15 + Port Reset bit + 15 + 1 + + + + + + + GPIOD + 0x48000C00 + + + GPIOE + 0x48001000 + + + GPIOF + 0x48001400 + + + GPIOG + 0x48001800 + + + TIM15 + General purpose timers + TIM + 0x40014000 + + 0x0 + 0x400 + registers + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + CEN + Counter enable + 0 + 1 + + + UDIS + Update disable + 1 + 1 + + + URS + Update request source + 2 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CKD + Clock division + 8 + 2 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + DITHEN + Dithering Enable + 12 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + OIS2 + Output idle state 2 (OC2 output) + 10 + 1 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + TI1S + TI1 selection + 7 + 1 + + + MMS + Master mode selection + 4 + 3 + + + CCDS + Capture/compare DMA selection + 3 + 1 + + + CCUS + Capture/compare control update selection + 2 + 1 + + + CCPC + Capture/compare preloaded control + 0 + 1 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x00000000 + + + TS_4_3 + Trigger selection - bit 4:3 + 20 + 2 + + + SMS_3 + Slave mode selection - bit 3 + 16 + 1 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + SMS + Slave mode selection + 0 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x00000000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + COMDE + COM DMA request enable + 13 + 1 + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x00000000 + + + CC2OF + Capture/Compare 2 overcapture flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture flag + 9 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + CC2IF + Capture/compare 2 interrupt flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x00000000 + + + BG + Break generation + 7 + 1 + + + TG + Trigger generation + 6 + 1 + + + COMG + Capture/Compare control update generation + 5 + 1 + + + CC2G + Capture/compare 2 generation + 2 + 1 + + + CC1G + Capture/compare 1 generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register (output mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2M_3 + Output Compare 2 mode - bit 3 + 24 + 1 + + + OC1M_3 + Output Compare 1 mode + 16 + 1 + + + OC2M + OC2M + 12 + 3 + + + OC2PE + OC2PE + 11 + 1 + + + OC2FE + OC2FE + 10 + 1 + + + CC2S + CC2S + 8 + 2 + + + OC1CE + OC1CE + 7 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload enable + 3 + 1 + + + OC1FE + Output Compare 1 fast enable + 2 + 1 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + IC2F + 12 + 4 + + + IC2PSC + IC2PSC + 10 + 2 + + + CC2S + CC2S + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable register + 0x20 + 0x20 + read-write + 0x00000000 + + + CC2NP + Capture/Compare 2 complementary output polarity + 7 + 1 + + + CC2P + Capture/Compare 2 output polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output enable + 2 + 1 + + + CC1P + Capture/Compare 1 output Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + 0x00000000 + + + CNT + counter value + 0 + 16 + read-write + + + UIFCPY + UIF Copy + 31 + 1 + read-only + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x00000000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x0000FFFF + + + ARR + Auto-reload value + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x00000000 + + + REP + Repetition counter value + 0 + 8 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/Compare 1 value + 0 + 16 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x00000000 + + + DTG + Dead-time generator setup + 0 + 8 + + + LOCK + Lock configuration + 8 + 2 + + + OSSI + Off-state selection for Idle mode + 10 + 1 + + + OSSR + Off-state selection for Run mode + 11 + 1 + + + BKE + Break enable + 12 + 1 + + + BKP + Break polarity + 13 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + MOE + Main output enable + 15 + 1 + + + BKF + Break filter + 16 + 4 + + + BKDSRM + BKDSRM + 26 + 1 + + + BKBID + BKBID + 28 + 1 + + + + + DTR2 + DTR2 + timer Deadtime Register 2 + 0x54 + 0x20 + read-write + 0x00000000 + + + DTGF + Dead-time generator setup + 0 + 8 + + + DTAE + Deadtime Asymmetric Enable + 16 + 1 + + + DTPE + Deadtime Preload Enable + 17 + 1 + + + + + TISEL + TISEL + TIM timer input selection register + 0x5C + 0x20 + read-write + 0x00000000 + + + TI1SEL + TI1[0] to TI1[15] input selection + 0 + 4 + + + TI2SEL + TI2[0] to TI2[15] input selection + 8 + 4 + + + + + AF1 + AF1 + TIM alternate function option register 1 + 0x60 + 0x20 + read-write + 0x00000000 + + + BKCMP4P + BRK COMP4 input polarity + 13 + 1 + + + BKCMP3P + BRK COMP3 input polarity + 12 + 1 + + + BKCMP2P + BRK COMP2 input polarity + 11 + 1 + + + BKCMP1P + BRK COMP1 input polarity + 10 + 1 + + + BKINP + BRK BKIN input polarity + 9 + 1 + + + BKCMP7E + BRK COMP7 enable + 7 + 1 + + + BKCMP6E + BRK COMP6 enable + 6 + 1 + + + BKCMP5E + BRK COMP5 enable + 5 + 1 + + + BKCMP4E + BRK COMP4 enable + 4 + 1 + + + BKCMP3E + BRK COMP3 enable + 3 + 1 + + + BKCMP2E + BRK COMP2 enable + 2 + 1 + + + BKCMP1E + BRK COMP1 enable + 1 + 1 + + + BKINE + BRK BKIN input enable + 0 + 1 + + + + + AF2 + AF2 + TIM alternate function option register 2 + 0x64 + 0x20 + read-write + 0x00000000 + + + OCRSEL + OCREF_CLR source selection + 16 + 3 + + + + + DCR + DCR + DMA control register + 0x3DC + 0x20 + read-write + 0x00000000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x3E0 + 0x20 + read-write + 0x00000000 + + + DMAB + DMA register for burst accesses + 0 + 32 + + + + + + + TIM16 + General purpose timers + TIM + 0x40014400 + + 0x0 + 0x400 + registers + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + CEN + Counter enable + 0 + 1 + + + UDIS + Update disable + 1 + 1 + + + URS + Update request source + 2 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CKD + Clock division + 8 + 2 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + DITHEN + Dithering Enable + 12 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + CCDS + Capture/compare DMA selection + 3 + 1 + + + CCUS + Capture/compare control update selection + 2 + 1 + + + CCPC + Capture/compare preloaded control + 0 + 1 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x00000000 + + + COMDE + COM DMA request enable + 13 + 1 + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x00000000 + + + CC1OF + Capture/Compare 1 overcapture flag + 9 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + CC1IF + Capture/compare 1 interrupt flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x00000000 + + + BG + Break generation + 7 + 1 + + + COMG + Capture/Compare control update generation + 5 + 1 + + + CC1G + Capture/compare 1 generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register (output mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC1M_3 + Output Compare 1 mode + 16 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload enable + 3 + 1 + + + OC1FE + Output Compare 1 fast enable + 2 + 1 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable register + 0x20 + 0x20 + read-write + 0x00000000 + + + CC1NP + Capture/Compare 1 output Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output enable + 2 + 1 + + + CC1P + Capture/Compare 1 output Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + 0x00000000 + + + CNT + counter value + 0 + 16 + read-write + + + UIFCPY + UIF Copy + 31 + 1 + read-only + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x00000000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x0000FFFF + + + ARR + Auto-reload value + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x00000000 + + + REP + Repetition counter value + 0 + 8 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x00000000 + + + DTG + Dead-time generator setup + 0 + 8 + + + LOCK + Lock configuration + 8 + 2 + + + OSSI + Off-state selection for Idle mode + 10 + 1 + + + OSSR + Off-state selection for Run mode + 11 + 1 + + + BKE + Break enable + 12 + 1 + + + BKP + Break polarity + 13 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + MOE + Main output enable + 15 + 1 + + + BKF + Break filter + 16 + 4 + + + BKDSRM + BKDSRM + 26 + 1 + + + BKBID + BKBID + 28 + 1 + + + + + DTR2 + DTR2 + timer Deadtime Register 2 + 0x54 + 0x20 + read-write + 0x00000000 + + + DTGF + Dead-time generator setup + 0 + 8 + + + DTAE + Deadtime Asymmetric Enable + 16 + 1 + + + DTPE + Deadtime Preload Enable + 17 + 1 + + + + + TISEL + TISEL + TIM timer input selection register + 0x5C + 0x20 + read-write + 0x00000000 + + + TI1SEL + TI1[0] to TI1[15] input selection + 0 + 4 + + + + + AF1 + AF1 + TIM alternate function option register 1 + 0x60 + 0x20 + read-write + 0x00000000 + + + BKCMP4P + BRK COMP4 input polarity + 13 + 1 + + + BKCMP3P + BRK COMP3 input polarity + 12 + 1 + + + BKCMP2P + BRK COMP2 input polarity + 11 + 1 + + + BKCMP1P + BRK COMP1 input polarity + 10 + 1 + + + BKINP + BRK BKIN input polarity + 9 + 1 + + + BKCMP7E + BRK COMP7 enable + 7 + 1 + + + BKCMP6E + BRK COMP6 enable + 6 + 1 + + + BKCMP5E + BRK COMP5 enable + 5 + 1 + + + BKCMP4E + BRK COMP4 enable + 4 + 1 + + + BKCMP3E + BRK COMP3 enable + 3 + 1 + + + BKCMP2E + BRK COMP2 enable + 2 + 1 + + + BKCMP1E + BRK COMP1 enable + 1 + 1 + + + BKINE + BRK BKIN input enable + 0 + 1 + + + + + AF2 + AF2 + TIM alternate function option register 2 + 0x64 + 0x20 + read-write + 0x00000000 + + + OCRSEL + OCREF_CLR source selection + 16 + 3 + + + + + OR1 + OR1 + TIM option register 1 + 0x68 + 0x20 + read-write + 0x00000000 + + + HSE32EN + HSE Divided by 32 enable + 0 + 1 + + + + + DCR + DCR + DMA control register + 0x3DC + 0x20 + read-write + 0x00000000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x3E0 + 0x20 + read-write + 0x00000000 + + + DMAB + DMA register for burst accesses + 0 + 32 + + + + + + + TIM17 + 0x40014800 + + + TIM1 + Advanced-timers + TIM + 0x40012C00 + + 0x0 + 0x400 + registers + + + TIM1_BRK_TIM15 + TIM1_BRK_TIM15 + 24 + + + TIM1_UP_TIM16 + TIM1_UP_TIM16 + 25 + + + TIM1_TRG_COM + TIM1_TRG_COM/ + 26 + + + TIM1_CC + TIM1 capture compare interrupt + 27 + + + TIM8_CC + TIM8_CC + 46 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + DITHEN + Dithering Enable + 12 + 1 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CMS + Center-aligned mode selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + MMS_3 + Master mode selection - bit 3 + 25 + 1 + + + MMS2 + Master mode selection 2 + 20 + 4 + + + OIS6 + Output Idle state 6 (OC6 output) + 18 + 1 + + + OIS5 + Output Idle state 5 (OC5 output) + 16 + 1 + + + OIS4N + Output Idle state 4 (OC4N output) + 15 + 1 + + + OIS4 + Output Idle state 4 + 14 + 1 + + + OIS3N + Output Idle state 3 + 13 + 1 + + + OIS3 + Output Idle state 3 + 12 + 1 + + + OIS2N + Output Idle state 2 + 11 + 1 + + + OIS2 + Output Idle state 2 + 10 + 1 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + TI1S + TI1 selection + 7 + 1 + + + MMS + Master mode selection + 4 + 3 + + + CCDS + Capture/compare DMA selection + 3 + 1 + + + CCUS + Capture/compare control update selection + 2 + 1 + + + CCPC + Capture/compare preloaded control + 0 + 1 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x00000000 + + + SMSPS + SMS Preload Source + 25 + 1 + + + SMSPE + SMS Preload Enable + 24 + 1 + + + TS_4_3 + Trigger selection - bit 4:3 + 20 + 2 + + + SMS_3 + Slave mode selection - bit 3 + 16 + 1 + + + ETP + External trigger polarity + 15 + 1 + + + ECE + External clock enable + 14 + 1 + + + ETPS + External trigger prescaler + 12 + 2 + + + ETF + External trigger filter + 8 + 4 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + OCCS + OCREF clear selection + 3 + 1 + + + SMS + Slave mode selection + 0 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x00000000 + + + TERRIE + Transition Error interrupt enable + 23 + 1 + + + IERRIE + Index Error interrupt enable + 22 + 1 + + + DIRIE + Direction Change interrupt enable + 21 + 1 + + + IDXIE + Index interrupt enable + 20 + 1 + + + TDE + Trigger DMA request enable + 14 + 1 + + + COMDE + COM DMA request enable + 13 + 1 + + + CC4DE + Capture/Compare 4 DMA request enable + 12 + 1 + + + CC3DE + Capture/Compare 3 DMA request enable + 11 + 1 + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + CC4IE + Capture/Compare 4 interrupt enable + 4 + 1 + + + CC3IE + Capture/Compare 3 interrupt enable + 3 + 1 + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x00000000 + + + TERRF + Transition Error interrupt flag + 23 + 1 + + + IERRF + Index Error interrupt flag + 22 + 1 + + + DIRF + Direction Change interrupt flag + 21 + 1 + + + IDXF + Index interrupt flag + 20 + 1 + + + CC6IF + Compare 6 interrupt flag + 17 + 1 + + + CC5IF + Compare 5 interrupt flag + 16 + 1 + + + SBIF + System Break interrupt flag + 13 + 1 + + + CC4OF + Capture/Compare 4 overcapture flag + 12 + 1 + + + CC3OF + Capture/Compare 3 overcapture flag + 11 + 1 + + + CC2OF + Capture/compare 2 overcapture flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture flag + 9 + 1 + + + B2IF + Break 2 interrupt flag + 8 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + CC4IF + Capture/Compare 4 interrupt flag + 4 + 1 + + + CC3IF + Capture/Compare 3 interrupt flag + 3 + 1 + + + CC2IF + Capture/Compare 2 interrupt flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x00000000 + + + B2G + Break 2 generation + 8 + 1 + + + BG + Break generation + 7 + 1 + + + TG + Trigger generation + 6 + 1 + + + COMG + Capture/Compare control update generation + 5 + 1 + + + CC4G + Capture/compare 4 generation + 4 + 1 + + + CC3G + Capture/compare 3 generation + 3 + 1 + + + CC2G + Capture/compare 2 generation + 2 + 1 + + + CC1G + Capture/compare 1 generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2M_3 + Output Compare 2 mode - bit 3 + 24 + 1 + + + OC1M_3 + Output Compare 1 mode - bit 3 + 16 + 1 + + + OC2CE + Output Compare 2 clear enable + 15 + 1 + + + OC2M + Output Compare 2 mode + 12 + 3 + + + OC2PE + Output Compare 2 preload enable + 11 + 1 + + + OC2FE + Output Compare 2 fast enable + 10 + 1 + + + CC2S + Capture/Compare 2 selection + 8 + 2 + + + OC1CE + Output Compare 1 clear enable + 7 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload enable + 3 + 1 + + + OC1FE + Output Compare 1 fast enable + 2 + 1 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + ICPCS + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCMR2_Output + CCMR2_Output + capture/compare mode register 2 (output mode) + 0x1C + 0x20 + read-write + 0x00000000 + + + OC4M_3 + Output Compare 4 mode - bit 3 + 24 + 1 + + + OC3M_3 + Output Compare 3 mode - bit 3 + 16 + 1 + + + OC4CE + Output compare 4 clear enable + 15 + 1 + + + OC4M + Output compare 4 mode + 12 + 3 + + + OC4PE + Output compare 4 preload enable + 11 + 1 + + + OC4FE + Output compare 4 fast enable + 10 + 1 + + + CC4S + Capture/Compare 4 selection + 8 + 2 + + + OC3CE + Output compare 3 clear enable + 7 + 1 + + + OC3M + Output compare 3 mode + 4 + 3 + + + OC3PE + Output compare 3 preload enable + 3 + 1 + + + OC3FE + Output compare 3 fast enable + 2 + 1 + + + CC3S + Capture/Compare 3 selection + 0 + 2 + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (input mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + CC4S + Capture/Compare 4 selection + 8 + 2 + + + IC3F + Input capture 3 filter + 4 + 4 + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + CC3S + Capture/compare 3 selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable register + 0x20 + 0x20 + read-write + 0x00000000 + + + CC6P + Capture/Compare 6 output polarity + 21 + 1 + + + CC6E + Capture/Compare 6 output enable + 20 + 1 + + + CC5P + Capture/Compare 5 output polarity + 17 + 1 + + + CC5E + Capture/Compare 5 output enable + 16 + 1 + + + CC4NP + Capture/Compare 4 complementary output polarity + 15 + 1 + + + CC4NE + Capture/Compare 4 complementary output enable + 14 + 1 + + + CC4P + Capture/Compare 3 output Polarity + 13 + 1 + + + CC4E + Capture/Compare 4 output enable + 12 + 1 + + + CC3NP + Capture/Compare 3 output Polarity + 11 + 1 + + + CC3NE + Capture/Compare 3 complementary output enable + 10 + 1 + + + CC3P + Capture/Compare 3 output Polarity + 9 + 1 + + + CC3E + Capture/Compare 3 output enable + 8 + 1 + + + CC2NP + Capture/Compare 2 output Polarity + 7 + 1 + + + CC2NE + Capture/Compare 2 complementary output enable + 6 + 1 + + + CC2P + Capture/Compare 2 output Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output enable + 2 + 1 + + + CC1P + Capture/Compare 1 output Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + 0x00000000 + + + UIFCPY + UIFCPY + 31 + 1 + read-only + + + CNT + counter value + 0 + 16 + read-write + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x00000000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x0000FFFF + + + ARR + Auto-reload value + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x00000000 + + + REP + Repetition counter value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/Compare 2 value + 0 + 16 + + + + + CCR3 + CCR3 + capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + CCR3 + Capture/Compare value + 0 + 16 + + + + + CCR4 + CCR4 + capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + + + CCR4 + Capture/Compare value + 0 + 16 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x00000000 + + + BK2ID + BK2ID + 29 + 1 + + + BKBID + BKBID + 28 + 1 + + + BK2DSRM + BK2DSRM + 27 + 1 + + + BKDSRM + BKDSRM + 26 + 1 + + + BK2P + Break 2 polarity + 25 + 1 + + + BK2E + Break 2 Enable + 24 + 1 + + + BK2F + Break 2 filter + 20 + 4 + + + BKF + Break filter + 16 + 4 + + + MOE + Main output enable + 15 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + BKP + Break polarity + 13 + 1 + + + BKE + Break enable + 12 + 1 + + + OSSR + Off-state selection for Run mode + 11 + 1 + + + OSSI + Off-state selection for Idle mode + 10 + 1 + + + LOCK + Lock configuration + 8 + 2 + + + DTG + Dead-time generator setup + 0 + 8 + + + + + CCR5 + CCR5 + capture/compare register 4 + 0x48 + 0x20 + read-write + 0x00000000 + + + CCR5 + Capture/Compare value + 0 + 16 + + + GC5C1 + Group Channel 5 and Channel 1 + 29 + 1 + + + GC5C2 + Group Channel 5 and Channel 2 + 30 + 1 + + + GC5C3 + Group Channel 5 and Channel 3 + 31 + 1 + + + + + CCR6 + CCR6 + capture/compare register 4 + 0x4C + 0x20 + read-write + 0x00000000 + + + CCR6 + Capture/Compare value + 0 + 16 + + + + + CCMR3_Output + CCMR3_Output + capture/compare mode register 2 (output mode) + 0x50 + 0x20 + read-write + 0x00000000 + + + OC6M_bit3 + Output Compare 6 mode bit 3 + 24 + 1 + + + OC5M_bit3 + Output Compare 5 mode bit 3 + 16 + 3 + + + OC6CE + Output compare 6 clear enable + 15 + 1 + + + OC6M + Output compare 6 mode + 12 + 3 + + + OC6PE + Output compare 6 preload enable + 11 + 1 + + + OC6FE + Output compare 6 fast enable + 10 + 1 + + + OC5CE + Output compare 5 clear enable + 7 + 1 + + + OC5M + Output compare 5 mode + 4 + 3 + + + OC5PE + Output compare 5 preload enable + 3 + 1 + + + OC5FE + Output compare 5 fast enable + 2 + 1 + + + + + DTR2 + DTR2 + timer Deadtime Register 2 + 0x54 + 0x20 + read-write + 0x00000000 + + + DTPE + Deadtime Preload Enable + 17 + 1 + + + DTAE + Deadtime Asymmetric Enable + 16 + 1 + + + DTGF + Dead-time falling edge generator setup + 0 + 8 + + + + + ECR + ECR + DMA control register + 0x58 + 0x20 + read-write + 0x00000000 + + + IE + Index Enable + 0 + 1 + + + IDIR + Index Direction + 1 + 2 + + + IBLK + Index Blanking + 3 + 2 + + + FIDX + First Index + 5 + 1 + + + IPOS + Index Positioning + 6 + 2 + + + PW + Pulse width + 16 + 8 + + + PWPRSC + Pulse Width prescaler + 24 + 3 + + + + + TISEL + TISEL + TIM timer input selection register + 0x5C + 0x20 + read-write + 0x00000000 + + + TI1SEL + TI1[0] to TI1[15] input selection + 0 + 4 + + + TI2SEL + TI2[0] to TI2[15] input selection + 8 + 4 + + + TI3SEL + TI3[0] to TI3[15] input selection + 16 + 4 + + + TI4SEL + TI4[0] to TI4[15] input selection + 24 + 4 + + + + + AF1 + AF1 + TIM alternate function option register 1 + 0x60 + 0x20 + read-write + 0x00000000 + + + ETRSEL + ETR source selection + 14 + 4 + + + BKCMP4P + BRK COMP4 input polarity + 13 + 1 + + + BKCMP3P + BRK COMP3 input polarity + 12 + 1 + + + BKCMP2P + BRK COMP2 input polarity + 11 + 1 + + + BKCMP1P + BRK COMP1 input polarity + 10 + 1 + + + BKINP + BRK BKIN input polarity + 9 + 1 + + + BKCMP7E + BRK COMP7 enable + 7 + 1 + + + BKCMP6E + BRK COMP6 enable + 6 + 1 + + + BKCMP5E + BRK COMP5 enable + 5 + 1 + + + BKCMP4E + BRK COMP4 enable + 4 + 1 + + + BKCMP3E + BRK COMP3 enable + 3 + 1 + + + BKCMP2E + BRK COMP2 enable + 2 + 1 + + + BKCMP1E + BRK COMP1 enable + 1 + 1 + + + BKINE + BRK BKIN input enable + 0 + 1 + + + + + AF2 + AF2 + TIM alternate function option register 2 + 0x64 + 0x20 + read-write + 0x00000000 + + + OCRSEL + OCREF_CLR source selection + 16 + 3 + + + BK2CMP4P + BRK2 COMP4 input polarity + 13 + 1 + + + BK2CMP3P + BRK2 COMP3 input polarity + 12 + 1 + + + BK2CMP2P + BRK2 COMP2 input polarity + 11 + 1 + + + BK2CMP1P + BRK2 COMP1 input polarity + 10 + 1 + + + BK2INP + BRK2 BKIN input polarity + 9 + 1 + + + BK2CMP7E + BRK2 COMP7 enable + 7 + 1 + + + BK2CMP6E + BRK2 COMP6 enable + 6 + 1 + + + BK2CMP5E + BRK2 COMP5 enable + 5 + 1 + + + BK2CMP4E + BRK2 COMP4 enable + 4 + 1 + + + BK2CMP3E + BRK2 COMP3 enable + 3 + 1 + + + BK2CMP2E + BRK2 COMP2 enable + 2 + 1 + + + BK2CMP1E + BRK2 COMP1 enable + 1 + 1 + + + BKINE + BRK BKIN input enable + 0 + 1 + + + + + DCR + DCR + control register + 0x3DC + 0x20 + read-write + 0x00000000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x3E0 + 0x20 + read-write + 0x00000000 + + + DMAB + DMA register for burst accesses + 0 + 32 + + + + + + + TIM20 + 0x40015000 + + TIM20_BRK + TIM20_BRK + 77 + + + TIM20_UP + TIM20_UP + 78 + + + TIM20_TRG_COM + TIM20_TRG_COM + 79 + + + TIM20_CC + TIM20_CC + 80 + + + + TIM8 + 0x40013400 + + TIM8_BRK + TIM8_BRK + 43 + + + TIM8_UP + TIM8_UP + 44 + + + TIM8_TRG_COM + TIM8_TRG_COM + 45 + + + + TIM2 + Advanced-timers + TIM + 0x40000000 + + 0x0 + 0x400 + registers + + + TIM2 + TIM2 + 28 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + DITHEN + Dithering Enable + 12 + 1 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CMS + Center-aligned mode selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + MMS_3 + Master mode selection - bit 3 + 25 + 1 + + + MMS2 + Master mode selection 2 + 20 + 4 + + + OIS6 + Output Idle state 6 (OC6 output) + 18 + 1 + + + OIS5 + Output Idle state 5 (OC5 output) + 16 + 1 + + + OIS4N + Output Idle state 4 (OC4N output) + 15 + 1 + + + OIS4 + Output Idle state 4 + 14 + 1 + + + OIS3N + Output Idle state 3 + 13 + 1 + + + OIS3 + Output Idle state 3 + 12 + 1 + + + OIS2N + Output Idle state 2 + 11 + 1 + + + OIS2 + Output Idle state 2 + 10 + 1 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + TI1S + TI1 selection + 7 + 1 + + + MMS + Master mode selection + 4 + 3 + + + CCDS + Capture/compare DMA selection + 3 + 1 + + + CCUS + Capture/compare control update selection + 2 + 1 + + + CCPC + Capture/compare preloaded control + 0 + 1 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x00000000 + + + SMSPS + SMS Preload Source + 25 + 1 + + + SMSPE + SMS Preload Enable + 24 + 1 + + + TS_4_3 + Trigger selection - bit 4:3 + 20 + 2 + + + SMS_3 + Slave mode selection - bit 3 + 16 + 1 + + + ETP + External trigger polarity + 15 + 1 + + + ECE + External clock enable + 14 + 1 + + + ETPS + External trigger prescaler + 12 + 2 + + + ETF + External trigger filter + 8 + 4 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + OCCS + OCREF clear selection + 3 + 1 + + + SMS + Slave mode selection + 0 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x00000000 + + + TERRIE + Transition Error interrupt enable + 23 + 1 + + + IERRIE + Index Error interrupt enable + 22 + 1 + + + DIRIE + Direction Change interrupt enable + 21 + 1 + + + IDXIE + Index interrupt enable + 20 + 1 + + + TDE + Trigger DMA request enable + 14 + 1 + + + COMDE + COM DMA request enable + 13 + 1 + + + CC4DE + Capture/Compare 4 DMA request enable + 12 + 1 + + + CC3DE + Capture/Compare 3 DMA request enable + 11 + 1 + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + CC4IE + Capture/Compare 4 interrupt enable + 4 + 1 + + + CC3IE + Capture/Compare 3 interrupt enable + 3 + 1 + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x00000000 + + + TERRF + Transition Error interrupt flag + 23 + 1 + + + IERRF + Index Error interrupt flag + 22 + 1 + + + DIRF + Direction Change interrupt flag + 21 + 1 + + + IDXF + Index interrupt flag + 20 + 1 + + + CC6IF + Compare 6 interrupt flag + 17 + 1 + + + CC5IF + Compare 5 interrupt flag + 16 + 1 + + + SBIF + System Break interrupt flag + 13 + 1 + + + CC4OF + Capture/Compare 4 overcapture flag + 12 + 1 + + + CC3OF + Capture/Compare 3 overcapture flag + 11 + 1 + + + CC2OF + Capture/compare 2 overcapture flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture flag + 9 + 1 + + + B2IF + Break 2 interrupt flag + 8 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + CC4IF + Capture/Compare 4 interrupt flag + 4 + 1 + + + CC3IF + Capture/Compare 3 interrupt flag + 3 + 1 + + + CC2IF + Capture/Compare 2 interrupt flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x00000000 + + + B2G + Break 2 generation + 8 + 1 + + + BG + Break generation + 7 + 1 + + + TG + Trigger generation + 6 + 1 + + + COMG + Capture/Compare control update generation + 5 + 1 + + + CC4G + Capture/compare 4 generation + 4 + 1 + + + CC3G + Capture/compare 3 generation + 3 + 1 + + + CC2G + Capture/compare 2 generation + 2 + 1 + + + CC1G + Capture/compare 1 generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2M_3 + Output Compare 2 mode - bit 3 + 24 + 1 + + + OC1M_3 + Output Compare 1 mode - bit 3 + 16 + 1 + + + OC2CE + Output Compare 2 clear enable + 15 + 1 + + + OC2M + Output Compare 2 mode + 12 + 3 + + + OC2PE + Output Compare 2 preload enable + 11 + 1 + + + OC2FE + Output Compare 2 fast enable + 10 + 1 + + + CC2S + Capture/Compare 2 selection + 8 + 2 + + + OC1CE + Output Compare 1 clear enable + 7 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload enable + 3 + 1 + + + OC1FE + Output Compare 1 fast enable + 2 + 1 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + ICPCS + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCMR2_Output + CCMR2_Output + capture/compare mode register 2 (output mode) + 0x1C + 0x20 + read-write + 0x00000000 + + + OC4M_3 + Output Compare 4 mode - bit 3 + 24 + 1 + + + OC3M_3 + Output Compare 3 mode - bit 3 + 16 + 1 + + + OC4CE + Output compare 4 clear enable + 15 + 1 + + + OC4M + Output compare 4 mode + 12 + 3 + + + OC4PE + Output compare 4 preload enable + 11 + 1 + + + OC4FE + Output compare 4 fast enable + 10 + 1 + + + CC4S + Capture/Compare 4 selection + 8 + 2 + + + OC3CE + Output compare 3 clear enable + 7 + 1 + + + OC3M + Output compare 3 mode + 4 + 3 + + + OC3PE + Output compare 3 preload enable + 3 + 1 + + + OC3FE + Output compare 3 fast enable + 2 + 1 + + + CC3S + Capture/Compare 3 selection + 0 + 2 + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (input mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + CC4S + Capture/Compare 4 selection + 8 + 2 + + + IC3F + Input capture 3 filter + 4 + 4 + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + CC3S + Capture/compare 3 selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable register + 0x20 + 0x20 + read-write + 0x00000000 + + + CC6P + Capture/Compare 6 output polarity + 21 + 1 + + + CC6E + Capture/Compare 6 output enable + 20 + 1 + + + CC5P + Capture/Compare 5 output polarity + 17 + 1 + + + CC5E + Capture/Compare 5 output enable + 16 + 1 + + + CC4NP + Capture/Compare 4 complementary output polarity + 15 + 1 + + + CC4NE + Capture/Compare 4 complementary output enable + 14 + 1 + + + CC4P + Capture/Compare 3 output Polarity + 13 + 1 + + + CC4E + Capture/Compare 4 output enable + 12 + 1 + + + CC3NP + Capture/Compare 3 output Polarity + 11 + 1 + + + CC3NE + Capture/Compare 3 complementary output enable + 10 + 1 + + + CC3P + Capture/Compare 3 output Polarity + 9 + 1 + + + CC3E + Capture/Compare 3 output enable + 8 + 1 + + + CC2NP + Capture/Compare 2 output Polarity + 7 + 1 + + + CC2NE + Capture/Compare 2 complementary output enable + 6 + 1 + + + CC2P + Capture/Compare 2 output Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output enable + 2 + 1 + + + CC1P + Capture/Compare 1 output Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + UIFCPY + UIFCPY + 31 + 1 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x00000000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0xFFFFFFFF + + + ARR + Auto-reload value + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x00000000 + + + REP + Repetition counter value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/Compare 2 value + 0 + 16 + + + + + CCR3 + CCR3 + capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + CCR3 + Capture/Compare value + 0 + 16 + + + + + CCR4 + CCR4 + capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + + + CCR4 + Capture/Compare value + 0 + 16 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x00000000 + + + BK2ID + BK2ID + 29 + 1 + + + BKBID + BKBID + 28 + 1 + + + BK2DSRM + BK2DSRM + 27 + 1 + + + BKDSRM + BKDSRM + 26 + 1 + + + BK2P + Break 2 polarity + 25 + 1 + + + BK2E + Break 2 Enable + 24 + 1 + + + BK2F + Break 2 filter + 20 + 4 + + + BKF + Break filter + 16 + 4 + + + MOE + Main output enable + 15 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + BKP + Break polarity + 13 + 1 + + + BKE + Break enable + 12 + 1 + + + OSSR + Off-state selection for Run mode + 11 + 1 + + + OSSI + Off-state selection for Idle mode + 10 + 1 + + + LOCK + Lock configuration + 8 + 2 + + + DTG + Dead-time generator setup + 0 + 8 + + + + + CCR5 + CCR5 + capture/compare register 4 + 0x48 + 0x20 + read-write + 0x00000000 + + + CCR5 + Capture/Compare value + 0 + 16 + + + GC5C1 + Group Channel 5 and Channel 1 + 29 + 1 + + + GC5C2 + Group Channel 5 and Channel 2 + 30 + 1 + + + GC5C3 + Group Channel 5 and Channel 3 + 31 + 1 + + + + + CCR6 + CCR6 + capture/compare register 4 + 0x4C + 0x20 + read-write + 0x00000000 + + + CCR6 + Capture/Compare value + 0 + 16 + + + + + CCMR3_Output + CCMR3_Output + capture/compare mode register 2 (output mode) + 0x50 + 0x20 + read-write + 0x00000000 + + + OC6M_bit3 + Output Compare 6 mode bit 3 + 24 + 1 + + + OC5M_bit3 + Output Compare 5 mode bit 3 + 16 + 3 + + + OC6CE + Output compare 6 clear enable + 15 + 1 + + + OC6M + Output compare 6 mode + 12 + 3 + + + OC6PE + Output compare 6 preload enable + 11 + 1 + + + OC6FE + Output compare 6 fast enable + 10 + 1 + + + OC5CE + Output compare 5 clear enable + 7 + 1 + + + OC5M + Output compare 5 mode + 4 + 3 + + + OC5PE + Output compare 5 preload enable + 3 + 1 + + + OC5FE + Output compare 5 fast enable + 2 + 1 + + + + + DTR2 + DTR2 + timer Deadtime Register 2 + 0x54 + 0x20 + read-write + 0x00000000 + + + DTPE + Deadtime Preload Enable + 17 + 1 + + + DTAE + Deadtime Asymmetric Enable + 16 + 1 + + + DTGF + Dead-time falling edge generator setup + 0 + 8 + + + + + ECR + ECR + DMA control register + 0x58 + 0x20 + read-write + 0x00000000 + + + IE + Index Enable + 0 + 1 + + + IDIR + Index Direction + 1 + 2 + + + IBLK + Index Blanking + 3 + 2 + + + FIDX + First Index + 5 + 1 + + + IPOS + Index Positioning + 6 + 2 + + + PW + Pulse width + 16 + 8 + + + PWPRSC + Pulse Width prescaler + 24 + 3 + + + + + TISEL + TISEL + TIM timer input selection register + 0x5C + 0x20 + read-write + 0x00000000 + + + TI1SEL + TI1[0] to TI1[15] input selection + 0 + 4 + + + TI2SEL + TI2[0] to TI2[15] input selection + 8 + 4 + + + TI3SEL + TI3[0] to TI3[15] input selection + 16 + 4 + + + TI4SEL + TI4[0] to TI4[15] input selection + 24 + 4 + + + + + AF1 + AF1 + TIM alternate function option register 1 + 0x60 + 0x20 + read-write + 0x00000000 + + + ETRSEL + ETR source selection + 14 + 4 + + + BKCMP4P + BRK COMP4 input polarity + 13 + 1 + + + BKCMP3P + BRK COMP3 input polarity + 12 + 1 + + + BKCMP2P + BRK COMP2 input polarity + 11 + 1 + + + BKCMP1P + BRK COMP1 input polarity + 10 + 1 + + + BKINP + BRK BKIN input polarity + 9 + 1 + + + BKCMP7E + BRK COMP7 enable + 7 + 1 + + + BKCMP6E + BRK COMP6 enable + 6 + 1 + + + BKCMP5E + BRK COMP5 enable + 5 + 1 + + + BKCMP4E + BRK COMP4 enable + 4 + 1 + + + BKCMP3E + BRK COMP3 enable + 3 + 1 + + + BKCMP2E + BRK COMP2 enable + 2 + 1 + + + BKCMP1E + BRK COMP1 enable + 1 + 1 + + + BKINE + BRK BKIN input enable + 0 + 1 + + + + + AF2 + AF2 + TIM alternate function option register 2 + 0x64 + 0x20 + read-write + 0x00000000 + + + OCRSEL + OCREF_CLR source selection + 16 + 3 + + + BK2CMP4P + BRK2 COMP4 input polarity + 13 + 1 + + + BK2CMP3P + BRK2 COMP3 input polarity + 12 + 1 + + + BK2CMP2P + BRK2 COMP2 input polarity + 11 + 1 + + + BK2CMP1P + BRK2 COMP1 input polarity + 10 + 1 + + + BK2INP + BRK2 BKIN input polarity + 9 + 1 + + + BK2CMP7E + BRK2 COMP7 enable + 7 + 1 + + + BK2CMP6E + BRK2 COMP6 enable + 6 + 1 + + + BK2CMP5E + BRK2 COMP5 enable + 5 + 1 + + + BK2CMP4E + BRK2 COMP4 enable + 4 + 1 + + + BK2CMP3E + BRK2 COMP3 enable + 3 + 1 + + + BK2CMP2E + BRK2 COMP2 enable + 2 + 1 + + + BK2CMP1E + BRK2 COMP1 enable + 1 + 1 + + + BKINE + BRK BKIN input enable + 0 + 1 + + + + + DCR + DCR + control register + 0x3DC + 0x20 + read-write + 0x00000000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x3E0 + 0x20 + read-write + 0x00000000 + + + DMAB + DMA register for burst accesses + 0 + 32 + + + + + + + TIM3 + 0x40000400 + + TIM3 + TIM3 + 29 + + + + TIM4 + 0x40000800 + + TIM4 + TIM4 + 30 + + + + TIM5 + 0x40000C00 + + TIM5 + TIM5 + 50 + + + + TIM6 + Basic-timers + TIM + 0x40001000 + + 0x0 + 0x400 + registers + + + TIM6_DACUNDER + TIM6_DACUNDER + 54 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + DITHEN + Dithering Enable + 12 + 1 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + MMS + Master mode selection + 4 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x00000000 + + + UDE + Update DMA request enable + 8 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x00000000 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x00000000 + + + UG + Update generation + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + 0x00000000 + + + UIFCPY + UIF Copy + 31 + 1 + read-only + + + CNT + Low counter value + 0 + 16 + read-write + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x00000000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x0000FFFF + + + ARR + Low Auto-reload value + 0 + 16 + + + + + + + TIM7 + 0x40001400 + + TIM7 + TIM7 + 55 + + + + LPTIMER1 + Low power timer + LPTIM + 0x40007C00 + + 0x0 + 0x400 + registers + + + + ISR + ISR + Interrupt and Status Register + 0x0 + 0x20 + read-only + 0x00000000 + + + DOWN + Counter direction change up to down + 6 + 1 + + + UP + Counter direction change down to up + 5 + 1 + + + ARROK + Autoreload register update OK + 4 + 1 + + + CMPOK + Compare register update OK + 3 + 1 + + + EXTTRIG + External trigger edge event + 2 + 1 + + + ARRM + Autoreload match + 1 + 1 + + + CMPM + Compare match + 0 + 1 + + + + + ICR + ICR + Interrupt Clear Register + 0x4 + 0x20 + write-only + 0x00000000 + + + DOWNCF + Direction change to down Clear Flag + 6 + 1 + + + UPCF + Direction change to UP Clear Flag + 5 + 1 + + + ARROKCF + Autoreload register update OK Clear Flag + 4 + 1 + + + CMPOKCF + Compare register update OK Clear Flag + 3 + 1 + + + EXTTRIGCF + External trigger valid edge Clear Flag + 2 + 1 + + + ARRMCF + Autoreload match Clear Flag + 1 + 1 + + + CMPMCF + compare match Clear Flag + 0 + 1 + + + + + IER + IER + Interrupt Enable Register + 0x8 + 0x20 + read-write + 0x00000000 + + + DOWNIE + Direction change to down Interrupt Enable + 6 + 1 + + + UPIE + Direction change to UP Interrupt Enable + 5 + 1 + + + ARROKIE + Autoreload register update OK Interrupt Enable + 4 + 1 + + + CMPOKIE + Compare register update OK Interrupt Enable + 3 + 1 + + + EXTTRIGIE + External trigger valid edge Interrupt Enable + 2 + 1 + + + ARRMIE + Autoreload match Interrupt Enable + 1 + 1 + + + CMPMIE + Compare match Interrupt Enable + 0 + 1 + + + + + CFGR + CFGR + Configuration Register + 0xC + 0x20 + read-write + 0x00000000 + + + ENC + Encoder mode enable + 24 + 1 + + + COUNTMODE + counter mode enabled + 23 + 1 + + + PRELOAD + Registers update mode + 22 + 1 + + + WAVPOL + Waveform shape polarity + 21 + 1 + + + WAVE + Waveform shape + 20 + 1 + + + TIMOUT + Timeout enable + 19 + 1 + + + TRIGEN + Trigger enable and polarity + 17 + 2 + + + TRIGSEL + Trigger selector + 13 + 4 + + + PRESC + Clock prescaler + 9 + 3 + + + TRGFLT + Configurable digital filter for trigger + 6 + 2 + + + CKFLT + Configurable digital filter for external clock + 3 + 2 + + + CKPOL + Clock Polarity + 1 + 2 + + + CKSEL + Clock selector + 0 + 1 + + + + + CR + CR + Control Register + 0x10 + 0x20 + read-write + 0x00000000 + + + RSTARE + RSTARE + 4 + 1 + + + COUNTRST + COUNTRST + 3 + 1 + + + CNTSTRT + Timer start in continuous mode + 2 + 1 + + + SNGSTRT + LPTIM start in single mode + 1 + 1 + + + ENABLE + LPTIM Enable + 0 + 1 + + + + + CMP + CMP + Compare Register + 0x14 + 0x20 + read-write + 0x00000000 + + + CMP + Compare value + 0 + 16 + + + + + ARR + ARR + Autoreload Register + 0x18 + 0x20 + read-write + 0x00000001 + + + ARR + Auto reload value + 0 + 16 + + + + + CNT + CNT + Counter Register + 0x1C + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 16 + + + + + OR + OR + option register + 0x20 + 0x20 + read-write + 0x00000000 + + + IN1 + IN1 + 0 + 1 + + + IN2 + IN2 + 1 + 1 + + + IN1_2_1 + IN1_2_1 + 2 + 2 + + + IN2_2_1 + IN2_2_1 + 4 + 2 + + + + + + + USART1 + Universal synchronous asynchronous receiver transmitter + USART + 0x40013800 + + 0x0 + 0x400 + registers + + + USART1 + USART1 + 37 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + RXFFIE + RXFFIE + 31 + 1 + + + TXFEIE + TXFEIE + 30 + 1 + + + FIFOEN + FIFOEN + 29 + 1 + + + M1 + M1 + 28 + 1 + + + EOBIE + End of Block interrupt enable + 27 + 1 + + + RTOIE + Receiver timeout interrupt enable + 26 + 1 + + + DEAT4 + Driver Enable assertion time + 25 + 1 + + + DEAT3 + DEAT3 + 24 + 1 + + + DEAT2 + DEAT2 + 23 + 1 + + + DEAT1 + DEAT1 + 22 + 1 + + + DEAT0 + DEAT0 + 21 + 1 + + + DEDT4 + Driver Enable de-assertion time + 20 + 1 + + + DEDT3 + DEDT3 + 19 + 1 + + + DEDT2 + DEDT2 + 18 + 1 + + + DEDT1 + DEDT1 + 17 + 1 + + + DEDT0 + DEDT0 + 16 + 1 + + + OVER8 + Oversampling mode + 15 + 1 + + + CMIE + Character match interrupt enable + 14 + 1 + + + MME + Mute mode enable + 13 + 1 + + + M0 + Word length + 12 + 1 + + + WAKE + Receiver wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXEIE + interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt enable + 6 + 1 + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + UESM + USART enable in Stop mode + 1 + 1 + + + UE + USART enable + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + ADD4_7 + Address of the USART node + 28 + 4 + + + ADD0_3 + Address of the USART node + 24 + 4 + + + RTOEN + Receiver timeout enable + 23 + 1 + + + ABRMOD1 + Auto baud rate mode + 22 + 1 + + + ABRMOD0 + ABRMOD0 + 21 + 1 + + + ABREN + Auto baud rate enable + 20 + 1 + + + MSBFIRST + Most significant bit first + 19 + 1 + + + TAINV + Binary data inversion + 18 + 1 + + + TXINV + TX pin active level inversion + 17 + 1 + + + RXINV + RX pin active level inversion + 16 + 1 + + + SWAP + Swap TX/RX pins + 15 + 1 + + + LINEN + LIN mode enable + 14 + 1 + + + STOP + STOP bits + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CPOL + Clock polarity + 10 + 1 + + + CPHA + Clock phase + 9 + 1 + + + LBCL + Last bit clock pulse + 8 + 1 + + + LBDIE + LIN break detection interrupt enable + 6 + 1 + + + LBDL + LIN break detection length + 5 + 1 + + + ADDM7 + 7-bit Address Detection/4-bit Address Detection + 4 + 1 + + + DIS_NSS + DIS_NSS + 3 + 1 + + + SLVEN + SLVEN + 0 + 1 + + + + + CR3 + CR3 + Control register 3 + 0x8 + 0x20 + read-write + 0x00000000 + + + TXFTCFG + TXFTCFG + 29 + 3 + + + RXFTIE + RXFTIE + 28 + 1 + + + RXFTCFG + RXFTCFG + 25 + 3 + + + TCBGTIE + TCBGTIE + 24 + 1 + + + TXFTIE + TXFTIE + 23 + 1 + + + WUFIE + Wakeup from Stop mode interrupt enable + 22 + 1 + + + WUS + Wakeup from Stop mode interrupt flag selection + 20 + 2 + + + SCARCNT + Smartcard auto-retry count + 17 + 3 + + + DEP + Driver enable polarity selection + 15 + 1 + + + DEM + Driver enable mode + 14 + 1 + + + DDRE + DMA Disable on Reception Error + 13 + 1 + + + OVRDIS + Overrun Disable + 12 + 1 + + + ONEBIT + One sample bit method enable + 11 + 1 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSE + CTS enable + 9 + 1 + + + RTSE + RTS enable + 8 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + DMAR + DMA enable receiver + 6 + 1 + + + SCEN + Smartcard mode enable + 5 + 1 + + + NACK + Smartcard NACK enable + 4 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + IRLP + Ir low-power + 2 + 1 + + + IREN + Ir mode enable + 1 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + + + BRR + BRR + Baud rate register + 0xC + 0x20 + read-write + 0x00000000 + + + DIV_Mantissa + DIV_Mantissa + 4 + 12 + + + DIV_Fraction + DIV_Fraction + 0 + 4 + + + + + GTPR + GTPR + Guard time and prescaler register + 0x10 + 0x20 + read-write + 0x00000000 + + + GT + Guard time value + 8 + 8 + + + PSC + Prescaler value + 0 + 8 + + + + + RTOR + RTOR + Receiver timeout register + 0x14 + 0x20 + read-write + 0x00000000 + + + BLEN + Block Length + 24 + 8 + + + RTO + Receiver timeout value + 0 + 24 + + + + + RQR + RQR + Request register + 0x18 + 0x20 + write-only + 0x00000000 + + + TXFRQ + Transmit data flush request + 4 + 1 + + + RXFRQ + Receive data flush request + 3 + 1 + + + MMRQ + Mute mode request + 2 + 1 + + + SBKRQ + Send break request + 1 + 1 + + + ABRRQ + Auto baud rate request + 0 + 1 + + + + + ISR + ISR + Interrupt & status register + 0x1C + 0x20 + read-only + 0x00000000 + + + TXFT + TXFT + 27 + 1 + + + RXFT + RXFT + 26 + 1 + + + TCBGT + TCBGT + 25 + 1 + + + RXFF + RXFF + 24 + 1 + + + TXFE + TXFE + 23 + 1 + + + REACK + REACK + 22 + 1 + + + TEACK + TEACK + 21 + 1 + + + WUF + WUF + 20 + 1 + + + RWU + RWU + 19 + 1 + + + SBKF + SBKF + 18 + 1 + + + CMF + CMF + 17 + 1 + + + BUSY + BUSY + 16 + 1 + + + ABRF + ABRF + 15 + 1 + + + ABRE + ABRE + 14 + 1 + + + UDR + UDR + 13 + 1 + + + EOBF + EOBF + 12 + 1 + + + RTOF + RTOF + 11 + 1 + + + CTS + CTS + 10 + 1 + + + CTSIF + CTSIF + 9 + 1 + + + LBDF + LBDF + 8 + 1 + + + TXE + TXE + 7 + 1 + + + TC + TC + 6 + 1 + + + RXNE + RXNE + 5 + 1 + + + IDLE + IDLE + 4 + 1 + + + ORE + ORE + 3 + 1 + + + NF + NF + 2 + 1 + + + FE + FE + 1 + 1 + + + PE + PE + 0 + 1 + + + + + ICR + ICR + Interrupt flag clear register + 0x20 + 0x20 + write-only + 0x00000000 + + + WUCF + Wakeup from Stop mode clear flag + 20 + 1 + + + CMCF + Character match clear flag + 17 + 1 + + + UDRCF + UDRCF + 13 + 1 + + + EOBCF + End of block clear flag + 12 + 1 + + + RTOCF + Receiver timeout clear flag + 11 + 1 + + + CTSCF + CTS clear flag + 9 + 1 + + + LBDCF + LIN break detection clear flag + 8 + 1 + + + TCBGTCF + TCBGTCF + 7 + 1 + + + TCCF + Transmission complete clear flag + 6 + 1 + + + TXFECF + TXFECF + 5 + 1 + + + IDLECF + Idle line detected clear flag + 4 + 1 + + + ORECF + Overrun error clear flag + 3 + 1 + + + NCF + Noise detected clear flag + 2 + 1 + + + FECF + Framing error clear flag + 1 + 1 + + + PECF + Parity error clear flag + 0 + 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+ 1 + + + EM9 + Event Mask on line 9 + 9 + 1 + + + EM10 + Event Mask on line 10 + 10 + 1 + + + EM11 + Event Mask on line 11 + 11 + 1 + + + EM12 + Event Mask on line 12 + 12 + 1 + + + EM13 + Event Mask on line 13 + 13 + 1 + + + EM14 + Event Mask on line 14 + 14 + 1 + + + EM15 + Event Mask on line 15 + 15 + 1 + + + EM16 + Event Mask on line 16 + 16 + 1 + + + EM17 + Event Mask on line 17 + 17 + 1 + + + EM18 + Event Mask on line 18 + 18 + 1 + + + EM19 + Event Mask on line 19 + 19 + 1 + + + EM20 + Event Mask on line 20 + 20 + 1 + + + EM21 + Event Mask on line 21 + 21 + 1 + + + EM22 + Event Mask on line 22 + 22 + 1 + + + EM23 + Event Mask on line 23 + 23 + 1 + + + EM24 + Event Mask on line 24 + 24 + 1 + + + EM25 + Event Mask on line 25 + 25 + 1 + + + EM26 + Event Mask on line 26 + 26 + 1 + + + EM27 + Event Mask on line 27 + 27 + 1 + + + EM28 + Event Mask on line 28 + 28 + 1 + + + EM29 + Event Mask on line 29 + 29 + 1 + + + EM30 + Event Mask on line 30 + 30 + 1 + + + EM31 + Event Mask on line 31 + 31 + 1 + + + + + RTSR1 + RTSR1 + Rising Trigger selection register + 0x8 + 0x20 + read-write + 0x00000000 + + + RT0 + Rising trigger event configuration of line 0 + 0 + 1 + + + RT1 + Rising trigger event configuration of line 1 + 1 + 1 + + + RT2 + Rising trigger event configuration of line 2 + 2 + 1 + + + RT3 + Rising trigger event configuration of line 3 + 3 + 1 + + + RT4 + Rising trigger event configuration of line 4 + 4 + 1 + + + RT5 + Rising trigger event configuration of line 5 + 5 + 1 + + + RT6 + Rising trigger event configuration of line 6 + 6 + 1 + + + RT7 + Rising trigger event configuration of line 7 + 7 + 1 + + + RT8 + Rising trigger event configuration of line 8 + 8 + 1 + + + RT9 + Rising trigger event configuration of line 9 + 9 + 1 + + + RT10 + Rising trigger event configuration of line 10 + 10 + 1 + + + RT11 + Rising trigger event configuration of line 11 + 11 + 1 + + + RT12 + Rising trigger event configuration of line 12 + 12 + 1 + + + RT13 + Rising trigger event configuration of line 13 + 13 + 1 + + + RT14 + Rising trigger event configuration of line 14 + 14 + 1 + + + RT15 + Rising trigger event configuration of line 15 + 15 + 1 + + + RT16 + Rising trigger event configuration of line 16 + 16 + 1 + + + RT18 + Rising trigger event configuration of line 18 + 18 + 1 + + + RT19 + Rising trigger event configuration of line 19 + 19 + 1 + + + RT20 + Rising trigger event configuration of line 20 + 20 + 1 + + + RT21 + Rising trigger event configuration of line 21 + 21 + 1 + + + RT22 + Rising trigger event configuration of line 22 + 22 + 1 + + + RT + RT + 29 + 3 + + + + + FTSR1 + FTSR1 + Falling Trigger selection register + 0xC + 0x20 + read-write + 0x00000000 + + + FT0 + Falling trigger event configuration of line 0 + 0 + 1 + + + FT1 + Falling trigger event configuration of line 1 + 1 + 1 + + + FT2 + Falling trigger event configuration of line 2 + 2 + 1 + + + FT3 + Falling trigger event configuration of line 3 + 3 + 1 + + + FT4 + Falling trigger event configuration of line 4 + 4 + 1 + + + FT5 + Falling trigger event configuration of line 5 + 5 + 1 + + + FT6 + Falling trigger event configuration of line 6 + 6 + 1 + + + FT7 + Falling trigger event configuration of line 7 + 7 + 1 + + + FT8 + Falling trigger event configuration of line 8 + 8 + 1 + + + FT9 + Falling trigger event configuration of line 9 + 9 + 1 + + + FT10 + Falling trigger event configuration of line 10 + 10 + 1 + + + FT11 + Falling trigger event configuration of line 11 + 11 + 1 + + + FT12 + Falling trigger event configuration of line 12 + 12 + 1 + + + FT13 + Falling trigger event configuration of line 13 + 13 + 1 + + + FT14 + Falling trigger event configuration of line 14 + 14 + 1 + + + FT15 + Falling trigger event configuration of line 15 + 15 + 1 + + + FT16 + Falling trigger event configuration of line 16 + 16 + 1 + + + FT18 + Falling trigger event configuration of line 18 + 18 + 1 + + + FT19 + Falling trigger event configuration of line 19 + 19 + 1 + + + FT20 + Falling trigger event configuration of line 20 + 20 + 1 + + + FT21 + Falling trigger event configuration of line 21 + 21 + 1 + + + FT22 + Falling trigger event configuration of line 22 + 22 + 1 + + + + + SWIER1 + SWIER1 + Software interrupt event register + 0x10 + 0x20 + read-write + 0x00000000 + + + SWI0 + Software Interrupt on line 0 + 0 + 1 + + + SWI1 + Software Interrupt on line 1 + 1 + 1 + + + SWI2 + Software Interrupt on line 2 + 2 + 1 + + + SWI3 + Software Interrupt on line 3 + 3 + 1 + + + SWI4 + Software Interrupt on line 4 + 4 + 1 + + + SWI5 + Software Interrupt on line 5 + 5 + 1 + + + SWI6 + Software Interrupt on line 6 + 6 + 1 + + + SWI7 + Software Interrupt on line 7 + 7 + 1 + + + SWI8 + Software Interrupt on line 8 + 8 + 1 + + + SWI9 + Software Interrupt on line 9 + 9 + 1 + + + SWI10 + Software Interrupt on line 10 + 10 + 1 + + + SWI11 + Software Interrupt on line 11 + 11 + 1 + + + SWI12 + Software Interrupt on line 12 + 12 + 1 + + + SWI13 + Software Interrupt on line 13 + 13 + 1 + + + SWI14 + Software Interrupt on line 14 + 14 + 1 + + + SWI15 + Software Interrupt on line 15 + 15 + 1 + + + SWI16 + Software Interrupt on line 16 + 16 + 1 + + + SWI18 + Software Interrupt on line 18 + 18 + 1 + + + SWI19 + Software Interrupt on line 19 + 19 + 1 + + + SWI20 + Software Interrupt on line 20 + 20 + 1 + + + SWI21 + Software Interrupt on line 21 + 21 + 1 + + + SWI22 + Software Interrupt on line 22 + 22 + 1 + + + + + PR1 + PR1 + Pending register + 0x14 + 0x20 + read-write + 0x00000000 + + + PIF0 + Pending bit 0 + 0 + 1 + + + PIF1 + Pending bit 1 + 1 + 1 + + + PIF2 + Pending bit 2 + 2 + 1 + + + PIF3 + Pending bit 3 + 3 + 1 + + + PIF4 + Pending bit 4 + 4 + 1 + + + PIF5 + Pending bit 5 + 5 + 1 + + + PIF6 + Pending bit 6 + 6 + 1 + + + PIF7 + Pending bit 7 + 7 + 1 + + + PIF8 + Pending bit 8 + 8 + 1 + + + PIF9 + Pending bit 9 + 9 + 1 + + + PIF10 + Pending bit 10 + 10 + 1 + + + PIF11 + Pending bit 11 + 11 + 1 + + + PIF12 + Pending bit 12 + 12 + 1 + + + PIF13 + Pending bit 13 + 13 + 1 + + + PIF14 + Pending bit 14 + 14 + 1 + + + PIF15 + Pending bit 15 + 15 + 1 + + + PIF16 + Pending bit 16 + 16 + 1 + + + PIF18 + Pending bit 18 + 18 + 1 + + + PIF19 + Pending bit 19 + 19 + 1 + + + PIF20 + Pending bit 20 + 20 + 1 + + + PIF21 + Pending bit 21 + 21 + 1 + + + PIF22 + Pending bit 22 + 22 + 1 + + + + + IMR2 + IMR2 + Interrupt mask register + 0x20 + 0x20 + read-write + 0xFFFFFF87 + + + IM32 + Interrupt Mask on external/internal line 32 + 0 + 1 + + + IM33 + Interrupt Mask on external/internal line 33 + 1 + 1 + + + IM34 + Interrupt Mask on external/internal line 34 + 2 + 1 + + + IM35 + Interrupt Mask on external/internal line 35 + 3 + 1 + + + IM36 + Interrupt Mask on external/internal line 36 + 4 + 1 + + + IM37 + Interrupt Mask on external/internal line 37 + 5 + 1 + + + IM38 + Interrupt Mask on external/internal line 38 + 6 + 1 + + + IM39 + Interrupt Mask on external/internal line 39 + 7 + 1 + + + IM40 + Interrupt Mask on external/internal line 40 + 8 + 1 + + + IM41 + Interrupt Mask on external/internal line 41 + 9 + 1 + + + IM42 + Interrupt Mask on external/internal line 42 + 10 + 1 + + + IM43 + Interrupt Mask on external/internal line 43 + 11 + 1 + + + + + EMR2 + EMR2 + Event mask register + 0x24 + 0x20 + read-write + 0x00000000 + + + EM32 + Event mask on external/internal line 32 + 0 + 1 + + + EM33 + Event mask on external/internal line 33 + 1 + 1 + + + EM34 + Event mask on external/internal line 34 + 2 + 1 + + + EM35 + Event mask on external/internal line 35 + 3 + 1 + + + EM36 + Event mask on external/internal line 36 + 4 + 1 + + + EM37 + Event mask on external/internal line 37 + 5 + 1 + + + EM38 + Event mask on external/internal line 38 + 6 + 1 + + + EM39 + Event mask on external/internal line 39 + 7 + 1 + + + EM40 + Event mask on external/internal line 40 + 8 + 1 + + + + + RTSR2 + RTSR2 + Rising Trigger selection register + 0x28 + 0x20 + read-write + 0x00000000 + + + RT32 + Rising trigger event configuration bit of line 32 + 0 + 1 + + + RT33 + Rising trigger event configuration bit of line 32 + 1 + 1 + + + RT38 + Rising trigger event configuration bit of line 38 + 6 + 1 + + + RT39 + Rising trigger event configuration bit of line 39 + 7 + 1 + + + RT40 + Rising trigger event configuration bit of line 40 + 8 + 1 + + + RT41 + Rising trigger event configuration bit of line 41 + 9 + 1 + + + + + FTSR2 + FTSR2 + Falling Trigger selection register + 0x2C + 0x20 + read-write + 0x00000000 + + + FT35 + Falling trigger event configuration bit of line 35 + 3 + 1 + + + FT36 + Falling trigger event configuration bit of line 36 + 4 + 1 + + + FT37 + Falling trigger event configuration bit of line 37 + 5 + 1 + + + FT38 + Falling trigger event configuration bit of line 38 + 6 + 1 + + + + + SWIER2 + SWIER2 + Software interrupt event register + 0x30 + 0x20 + read-write + 0x00000000 + + + SWI35 + Software interrupt on line 35 + 3 + 1 + + + SWI36 + Software interrupt on line 36 + 4 + 1 + + + SWI37 + Software interrupt on line 37 + 5 + 1 + + + SWI38 + Software interrupt on line 38 + 6 + 1 + + + + + PR2 + PR2 + Pending register + 0x34 + 0x20 + read-write + 0x00000000 + + + PIF35 + Pending interrupt flag on line 35 + 3 + 1 + + + PIF36 + Pending interrupt flag on line 36 + 4 + 1 + + + PIF37 + Pending interrupt flag on line 37 + 5 + 1 + + + PIF38 + Pending interrupt flag on line 38 + 6 + 1 + + + + + + + RTC + Real-time clock + RTC + 0x40002800 + + 0x0 + 0x400 + registers + + + RTC_TAMP_CSS_LSE + RTC_TAMP_CSS_LSE + 2 + + + RTC_WKUP + RTC Wakeup timer + 3 + + + RTC_ALARM + RTC_ALARM + 41 + + + + TR + TR + time register + 0x0 + 0x20 + read-write + 0x00000000 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + DR + DR + date register + 0x4 + 0x20 + read-write + 0x00002101 + + + YT + Year tens in BCD format + 20 + 4 + + + YU + Year units in BCD format + 16 + 4 + + + WDU + Week day units + 13 + 3 + + + MT + Month tens in BCD format + 12 + 1 + + + MU + Month units in BCD format + 8 + 4 + + + DT + Date tens in BCD format + 4 + 2 + + + DU + Date units in BCD format + 0 + 4 + + + + + SSR + SSR + sub second register + 0x8 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value + 0 + 16 + + + + + ICSR + ICSR + initialization and status register + 0xC + 0x20 + 0x00000007 + + + ALRAWF + Alarm A write flag + 0 + 1 + read-only + + + ALRBWF + Alarm B write flag + 1 + 1 + read-only + + + WUTWF + Wakeup timer write flag + 2 + 1 + read-only + + + SHPF + Shift operation pending + 3 + 1 + read-write + + + INITS + Initialization status flag + 4 + 1 + read-only + + + RSF + Registers synchronization flag + 5 + 1 + read-write + + + INITF + Initialization flag + 6 + 1 + read-only + + + INIT + Initialization mode + 7 + 1 + read-write + + + RECALPF + Recalibration pending Flag + 16 + 1 + read-only + + + + + PRER + PRER + prescaler register + 0x10 + 0x20 + read-write + 0x007F00FF + + + PREDIV_A + Asynchronous prescaler factor + 16 + 7 + + + PREDIV_S + Synchronous prescaler factor + 0 + 15 + + + + + WUTR + WUTR + wakeup timer register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + WUT + Wakeup auto-reload value bits + 0 + 16 + + + + + CR + CR + control register + 0x18 + 0x20 + read-write + 0x00000000 + + + WCKSEL + Wakeup clock selection + 0 + 3 + + + TSEDGE + Time-stamp event active edge + 3 + 1 + + + REFCKON + Reference clock detection enable (50 or 60 Hz) + 4 + 1 + + + BYPSHAD + Bypass the shadow registers + 5 + 1 + + + FMT + Hour format + 6 + 1 + + + ALRAE + Alarm A enable + 8 + 1 + + + ALRBE + Alarm B enable + 9 + 1 + + + WUTE + Wakeup timer enable + 10 + 1 + + + TSE + Time stamp enable + 11 + 1 + + + ALRAIE + Alarm A interrupt enable + 12 + 1 + + + ALRBIE + Alarm B interrupt enable + 13 + 1 + + + WUTIE + Wakeup timer interrupt enable + 14 + 1 + + + TSIE + Time-stamp interrupt enable + 15 + 1 + + + ADD1H + Add 1 hour (summer time change) + 16 + 1 + + + SUB1H + Subtract 1 hour (winter time change) + 17 + 1 + + + BKP + Backup + 18 + 1 + + + COSEL + Calibration output selection + 19 + 1 + + + POL + Output polarity + 20 + 1 + + + OSEL + Output selection + 21 + 2 + + + COE + Calibration output enable + 23 + 1 + + + ITSE + timestamp on internal event enable + 24 + 1 + + + TAMPTS + TAMPTS + 25 + 1 + + + TAMPOE + TAMPOE + 26 + 1 + + + TAMPALRM_PU + TAMPALRM_PU + 29 + 1 + + + TAMPALRM_TYPE + TAMPALRM_TYPE + 30 + 1 + + + OUT2EN + OUT2EN + 31 + 1 + + + + + WPR + WPR + write protection register + 0x24 + 0x20 + write-only + 0x00000000 + + + KEY + Write protection key + 0 + 8 + + + + + CALR + CALR + calibration register + 0x28 + 0x20 + read-write + 0x00000000 + + + CALP + Increase frequency of RTC by 488.5 ppm + 15 + 1 + + + CALW8 + Use an 8-second calibration cycle period + 14 + 1 + + + CALW16 + Use a 16-second calibration cycle period + 13 + 1 + + + CALM + Calibration minus + 0 + 9 + + + + + SHIFTR + SHIFTR + shift control register + 0x2C + 0x20 + write-only + 0x00000000 + + + ADD1S + Add one second + 31 + 1 + + + SUBFS + Subtract a fraction of a second + 0 + 15 + + + + + TSTR + TSTR + time stamp time register + 0x30 + 0x20 + read-only + 0x00000000 + + + SU + Second units in BCD format + 0 + 4 + + + ST + Second tens in BCD format + 4 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + MNT + Minute tens in BCD format + 12 + 3 + + + HU + Hour units in BCD format + 16 + 4 + + + HT + Hour tens in BCD format + 20 + 2 + + + PM + AM/PM notation + 22 + 1 + + + + + TSDR + TSDR + time stamp date register + 0x34 + 0x20 + read-only + 0x00000000 + + + WDU + Week day units + 13 + 3 + + + MT + Month tens in BCD format + 12 + 1 + + + MU + Month units in BCD format + 8 + 4 + + + DT + Date tens in BCD format + 4 + 2 + + + DU + Date units in BCD format + 0 + 4 + + + + + TSSSR + TSSSR + timestamp sub second register + 0x38 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value + 0 + 16 + + + + + ALRMAR + ALRMAR + alarm A register + 0x40 + 0x20 + read-write + 0x00000000 + + + MSK4 + Alarm A date mask + 31 + 1 + + + WDSEL + Week day selection + 30 + 1 + + + DT + Date tens in BCD format + 28 + 2 + + + DU + Date units or day in BCD format + 24 + 4 + + + MSK3 + Alarm A hours mask + 23 + 1 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MSK2 + Alarm A minutes mask + 15 + 1 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + MSK1 + Alarm A seconds mask + 7 + 1 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + ALRMASSR + ALRMASSR + alarm A sub second register + 0x44 + 0x20 + read-write + 0x00000000 + + + MASKSS + Mask the most-significant bits starting at this bit + 24 + 4 + + + SS + Sub seconds value + 0 + 15 + + + + + ALRMBR + ALRMBR + alarm B register + 0x48 + 0x20 + read-write + 0x00000000 + + + MSK4 + Alarm B date mask + 31 + 1 + + + WDSEL + Week day selection + 30 + 1 + + + DT + Date tens in BCD format + 28 + 2 + + + DU + Date units or day in BCD format + 24 + 4 + + + MSK3 + Alarm B hours mask + 23 + 1 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MSK2 + Alarm B minutes mask + 15 + 1 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + MSK1 + Alarm B seconds mask + 7 + 1 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + ALRMBSSR + ALRMBSSR + alarm B sub second register + 0x4C + 0x20 + read-write + 0x00000000 + + + MASKSS + Mask the most-significant bits starting at this bit + 24 + 4 + + + SS + Sub seconds value + 0 + 15 + + + + + SR + SR + status register + 0x50 + 0x20 + read-only + 0x00000000 + + + ALRAF + ALRAF + 0 + 1 + + + ALRBF + ALRBF + 1 + 1 + + + WUTF + WUTF + 2 + 1 + + + TSF + TSF + 3 + 1 + + + TSOVF + TSOVF + 4 + 1 + + + ITSF + ITSF + 5 + 1 + + + + + MISR + MISR + status register + 0x54 + 0x20 + read-only + 0x00000000 + + + ALRAMF + ALRAMF + 0 + 1 + + + ALRBMF + ALRBMF + 1 + 1 + + + WUTMF + WUTMF + 2 + 1 + + + TSMF + TSMF + 3 + 1 + + + TSOVMF + TSOVMF + 4 + 1 + + + ITSMF + ITSMF + 5 + 1 + + + + + SCR + SCR + status register + 0x5C + 0x20 + write-only + 0x00000000 + + + CALRAF + CALRAF + 0 + 1 + + + CALRBF + CALRBF + 1 + 1 + + + CWUTF + CWUTF + 2 + 1 + + + CTSF + CTSF + 3 + 1 + + + CTSOVF + CTSOVF + 4 + 1 + + + CITSF + CITSF + 5 + 1 + + + + + + + FMC + Flexible memory controller + FMC + 0xA0000000 + + 0x0 + 0x400 + registers + + + FMC + FMC + 48 + + + + BCR1 + BCR1 + SRAM/NOR-Flash chip-select control register 1 + 0x0 + 0x20 + read-write + 0x000030D0 + + + MBKEN + MBKEN + 0 + 1 + + + MUXEN + MUXEN + 1 + 1 + + + MTYP + MTYP + 2 + 2 + + + MWID + MWID + 4 + 2 + + + FACCEN + FACCEN + 6 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WREN + WREN + 12 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + CPSIZE + CPSIZE + 16 + 3 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + CCLKEN + CCLKEN + 20 + 1 + + + WFDIS + WFDIS + 21 + 1 + + + NBLSET + NBLSET + 22 + 2 + + + + + BTR1 + BTR1 + SRAM/NOR-Flash chip-select timing register 1 + 0x4 + 0x20 + read-write + 0xFFFFFFFF + + + DATAHLD + DATAHLD + 30 + 2 + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BCR2 + BCR2 + SRAM/NOR-Flash chip-select control register 2 + 0x8 + 0x20 + read-write + 0x000030D0 + + + MBKEN + MBKEN + 0 + 1 + + + MUXEN + MUXEN + 1 + 1 + + + MTYP + MTYP + 2 + 2 + + + MWID + MWID + 4 + 2 + + + FACCEN + FACCEN + 6 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WREN + WREN + 12 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + CPSIZE + CPSIZE + 16 + 3 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + CCLKEN + CCLKEN + 20 + 1 + + + WFDIS + WFDIS + 21 + 1 + + + NBLSET + NBLSET + 22 + 2 + + + + + BTR2 + BTR2 + SRAM/NOR-Flash chip-select timing register 2 + 0xC + 0x20 + read-write + 0xFFFFFFFF + + + DATAHLD + DATAHLD + 30 + 2 + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BCR3 + BCR3 + SRAM/NOR-Flash chip-select control register 3 + 0x10 + 0x20 + read-write + 0x000030D0 + + + MBKEN + MBKEN + 0 + 1 + + + MUXEN + MUXEN + 1 + 1 + + + MTYP + MTYP + 2 + 2 + + + MWID + MWID + 4 + 2 + + + FACCEN + FACCEN + 6 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WREN + WREN + 12 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + CPSIZE + CPSIZE + 16 + 3 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + CCLKEN + CCLKEN + 20 + 1 + + + WFDIS + WFDIS + 21 + 1 + + + NBLSET + NBLSET + 22 + 2 + + + + + BTR3 + BTR3 + SRAM/NOR-Flash chip-select timing register 3 + 0x14 + 0x20 + read-write + 0xFFFFFFFF + + + DATAHLD + DATAHLD + 30 + 2 + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BCR4 + BCR4 + SRAM/NOR-Flash chip-select control register 4 + 0x18 + 0x20 + read-write + 0x000030D0 + + + MBKEN + MBKEN + 0 + 1 + + + MUXEN + MUXEN + 1 + 1 + + + MTYP + MTYP + 2 + 2 + + + MWID + MWID + 4 + 2 + + + FACCEN + FACCEN + 6 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WREN + WREN + 12 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + CPSIZE + CPSIZE + 16 + 3 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + CCLKEN + CCLKEN + 20 + 1 + + + WFDIS + WFDIS + 21 + 1 + + + NBLSET + NBLSET + 22 + 2 + + + + + BTR4 + BTR4 + SRAM/NOR-Flash chip-select timing register 4 + 0x1C + 0x20 + read-write + 0xFFFFFFFF + + + DATAHLD + DATAHLD + 30 + 2 + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + PCSCNTR + PCSCNTR + PSRAM chip select counter register + 0x20 + 0x20 + read-write + 0x00000000 + + + CSCOUNT + CSCOUNT + 0 + 16 + + + CNTB1EN + CNTB1EN + 16 + 1 + + + CNTB2EN + CNTB2EN + 17 + 1 + + + CNTB3EN + CNTB3EN + 18 + 1 + + + CNTB4EN + CNTB4EN + 19 + 1 + + + + + PCR + PCR + PC Card/NAND Flash control register 3 + 0x80 + 0x20 + read-write + 0x00000018 + + + ECCPS + ECCPS + 17 + 3 + + + TAR + TAR + 13 + 4 + + + TCLR + TCLR + 9 + 4 + + + ECCEN + ECCEN + 6 + 1 + + + PWID + PWID + 4 + 2 + + + PTYP + PTYP + 3 + 1 + + + PBKEN + PBKEN + 2 + 1 + + + PWAITEN + PWAITEN + 1 + 1 + + + + + SR + SR + FIFO status and interrupt register 3 + 0x84 + 0x20 + 0x00000040 + + + FEMPT + FEMPT + 6 + 1 + read-only + + + IFEN + IFEN + 5 + 1 + read-write + + + ILEN + ILEN + 4 + 1 + read-write + + + IREN + IREN + 3 + 1 + read-write + + + IFS + IFS + 2 + 1 + read-write + + + ILS + ILS + 1 + 1 + read-write + + + IRS + IRS + 0 + 1 + read-write + + + + + PMEM + PMEM + Common memory space timing register 3 + 0x88 + 0x20 + read-write + 0xFCFCFCFC + + + MEMHIZx + MEMHIZx + 24 + 8 + + + MEMHOLDx + MEMHOLDx + 16 + 8 + + + MEMWAITx + MEMWAITx + 8 + 8 + + + MEMSETx + MEMSETx + 0 + 8 + + + + + PATT + PATT + Attribute memory space timing register 3 + 0x8C + 0x20 + read-write + 0xFCFCFCFC + + + ATTHIZx + ATTHIZx + 24 + 8 + + + ATTHOLDx + ATTHOLDx + 16 + 8 + + + ATTWAITx + ATTWAITx + 8 + 8 + + + ATTSETx + ATTSETx + 0 + 8 + + + + + ECCR + ECCR + ECC result register 3 + 0x94 + 0x20 + read-only + 0x00000000 + + + ECCx + ECCx + 0 + 32 + + + + + BWTR1 + BWTR1 + SRAM/NOR-Flash write timing registers 1 + 0x104 + 0x20 + read-write + 0x0FFFFFFF + + + DATAHLD + DATAHLD + 30 + 2 + + + ACCMOD + ACCMOD + 28 + 2 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BWTR2 + BWTR2 + SRAM/NOR-Flash write timing registers 2 + 0x10C + 0x20 + read-write + 0x0FFFFFFF + + + DATAHLD + DATAHLD + 30 + 2 + + + ACCMOD + ACCMOD + 28 + 2 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BWTR3 + BWTR3 + SRAM/NOR-Flash write timing registers 3 + 0x114 + 0x20 + read-write + 0x0FFFFFFF + + + DATAHLD + DATAHLD + 30 + 2 + + + ACCMOD + ACCMOD + 28 + 2 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BWTR4 + BWTR4 + SRAM/NOR-Flash write timing registers 4 + 0x11C + 0x20 + read-write + 0x0FFFFFFF + + + DATAHLD + DATAHLD + 30 + 2 + + + ACCMOD + ACCMOD + 28 + 2 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + + + DMA1 + DMA controller + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA1_CH1 + DMA1 channel 1 interrupt + 11 + + + DMA1_CH2 + DMA1 channel 2 interrupt + 12 + + + DMA1_CH3 + DMA1 channel 3 interrupt + 13 + + + DMA1_CH4 + DMA1 channel 4 interrupt + 14 + + + DMA1_CH5 + DMA1 channel 5 interrupt + 15 + + + DMA1_CH6 + DMA1 channel 6 interrupt + 16 + + + DMA1_CH8 + DMA1_CH8 + 96 + + + + ISR + ISR + interrupt status register + 0x0 + 0x20 + read-only + 0x00000000 + + + TEIF8 + TEIF8 + 31 + 1 + + + HTIF8 + HTIF8 + 30 + 1 + + + TCIF8 + TCIF8 + 29 + 1 + + + GIF8 + GIF8 + 28 + 1 + + + TEIF7 + TEIF7 + 27 + 1 + + + HTIF7 + HTIF7 + 26 + 1 + + + TCIF7 + TCIF7 + 25 + 1 + + + GIF7 + GIF7 + 24 + 1 + + + TEIF6 + TEIF6 + 23 + 1 + + + HTIF6 + HTIF6 + 22 + 1 + + + TCIF6 + TCIF6 + 21 + 1 + + + GIF6 + GIF6 + 20 + 1 + + + TEIF5 + TEIF5 + 19 + 1 + + + HTIF5 + HTIF5 + 18 + 1 + + + TCIF5 + TCIF5 + 17 + 1 + + + GIF5 + GIF5 + 16 + 1 + + + TEIF4 + TEIF4 + 15 + 1 + + + HTIF4 + HTIF4 + 14 + 1 + + + TCIF4 + TCIF4 + 13 + 1 + + + GIF4 + GIF4 + 12 + 1 + + + TEIF3 + TEIF3 + 11 + 1 + + + HTIF3 + HTIF3 + 10 + 1 + + + TCIF3 + TCIF3 + 9 + 1 + + + GIF3 + GIF3 + 8 + 1 + + + TEIF2 + TEIF2 + 7 + 1 + + + HTIF2 + HTIF2 + 6 + 1 + + + TCIF2 + TCIF2 + 5 + 1 + + + GIF2 + GIF2 + 4 + 1 + + + TEIF1 + TEIF1 + 3 + 1 + + + HTIF1 + HTIF1 + 2 + 1 + + + TCIF1 + TCIF1 + 1 + 1 + + + GIF1 + GIF1 + 0 + 1 + + + + + IFCR + IFCR + DMA interrupt flag clear register + 0x4 + 0x20 + write-only + 0x00000000 + + + TEIF8 + TEIF8 + 31 + 1 + + + HTIF8 + HTIF8 + 30 + 1 + + + TCIF8 + TCIF8 + 29 + 1 + + + GIF8 + GIF8 + 28 + 1 + + + TEIF7 + TEIF7 + 27 + 1 + + + HTIF7 + HTIF7 + 26 + 1 + + + TCIF7 + TCIF7 + 25 + 1 + + + GIF7 + GIF7 + 24 + 1 + + + TEIF6 + TEIF6 + 23 + 1 + + + HTIF6 + HTIF6 + 22 + 1 + + + TCIF6 + TCIF6 + 21 + 1 + + + GIF6 + GIF6 + 20 + 1 + + + TEIF5 + TEIF5 + 19 + 1 + + + HTIF5 + HTIF5 + 18 + 1 + + + TCIF5 + TCIF5 + 17 + 1 + + + GIF5 + GIF5 + 16 + 1 + + + TEIF4 + TEIF4 + 15 + 1 + + + HTIF4 + HTIF4 + 14 + 1 + + + TCIF4 + TCIF4 + 13 + 1 + + + GIF4 + GIF4 + 12 + 1 + + + TEIF3 + TEIF3 + 11 + 1 + + + HTIF3 + HTIF3 + 10 + 1 + + + TCIF3 + TCIF3 + 9 + 1 + + + GIF3 + GIF3 + 8 + 1 + + + TEIF2 + TEIF2 + 7 + 1 + + + HTIF2 + HTIF2 + 6 + 1 + + + TCIF2 + TCIF2 + 5 + 1 + + + GIF2 + GIF2 + 4 + 1 + + + TEIF1 + TEIF1 + 3 + 1 + + + HTIF1 + HTIF1 + 2 + 1 + + + TCIF1 + TCIF1 + 1 + 1 + + + GIF1 + GIF1 + 0 + 1 + + + + + CCR1 + CCR1 + DMA channel 1 configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + EN + channel enable + 0 + 1 + + + TCIE + TCIE + 1 + 1 + + + HTIE + HTIE + 2 + 1 + + + TEIE + TEIE + 3 + 1 + + + DIR + DIR + 4 + 1 + + + CIRC + CIRC + 5 + 1 + + + PINC + PINC + 6 + 1 + + + MINC + MINC + 7 + 1 + + + PSIZE + PSIZE + 8 + 2 + + + MSIZE + MSIZE + 10 + 2 + + + PL + PL + 12 + 2 + + + MEM2MEM + MEM2MEM + 14 + 1 + + + + + CCR2 + CCR2 + DMA channel 2 configuration register + 0x1C + 0x20 + read-write + 0x00000000 + + + EN + channel enable + 0 + 1 + + + TCIE + TCIE + 1 + 1 + + + HTIE + HTIE + 2 + 1 + + + TEIE + TEIE + 3 + 1 + + + DIR + DIR + 4 + 1 + + + CIRC + CIRC + 5 + 1 + + + PINC + PINC + 6 + 1 + + + MINC + MINC + 7 + 1 + + + PSIZE + PSIZE + 8 + 2 + + + MSIZE + MSIZE + 10 + 2 + + + PL + PL + 12 + 2 + + + MEM2MEM + MEM2MEM + 14 + 1 + + + + + CCR3 + CCR3 + DMA channel 3 configuration register + 0x30 + 0x20 + read-write + 0x00000000 + + + EN + channel enable + 0 + 1 + + + TCIE + TCIE + 1 + 1 + + + HTIE + HTIE + 2 + 1 + + + TEIE + TEIE + 3 + 1 + + + DIR + DIR + 4 + 1 + + + CIRC + CIRC + 5 + 1 + + + PINC + PINC + 6 + 1 + + + MINC + MINC + 7 + 1 + + + PSIZE + PSIZE + 8 + 2 + + + MSIZE + MSIZE + 10 + 2 + + + PL + PL + 12 + 2 + + + MEM2MEM + MEM2MEM + 14 + 1 + + + + + CCR4 + CCR4 + DMA channel 3 configuration register + 0x44 + 0x20 + read-write + 0x00000000 + + + EN + channel enable + 0 + 1 + + + TCIE + TCIE + 1 + 1 + + + HTIE + HTIE + 2 + 1 + + + TEIE + TEIE + 3 + 1 + + + DIR + DIR + 4 + 1 + + + CIRC + CIRC + 5 + 1 + + + PINC + PINC + 6 + 1 + + + MINC + MINC + 7 + 1 + + + PSIZE + PSIZE + 8 + 2 + + + MSIZE + MSIZE + 10 + 2 + + + PL + PL + 12 + 2 + + + MEM2MEM + MEM2MEM + 14 + 1 + + + + + CCR5 + CCR5 + DMA channel 4 configuration register + 0x58 + 0x20 + read-write + 0x00000000 + + + EN + channel enable + 0 + 1 + + + TCIE + TCIE + 1 + 1 + + + HTIE + HTIE + 2 + 1 + + + TEIE + TEIE + 3 + 1 + + + DIR + DIR + 4 + 1 + + + CIRC + CIRC + 5 + 1 + + + PINC + PINC + 6 + 1 + + + MINC + MINC + 7 + 1 + + + PSIZE + PSIZE + 8 + 2 + + + MSIZE + MSIZE + 10 + 2 + + + PL + PL + 12 + 2 + + + MEM2MEM + MEM2MEM + 14 + 1 + + + + + CCR6 + CCR6 + DMA channel 5 configuration register + 0x6C + 0x20 + read-write + 0x00000000 + + + EN + channel enable + 0 + 1 + + + TCIE + TCIE + 1 + 1 + + + HTIE + HTIE + 2 + 1 + + + TEIE + TEIE + 3 + 1 + + + DIR + DIR + 4 + 1 + + + CIRC + CIRC + 5 + 1 + + + PINC + PINC + 6 + 1 + + + MINC + MINC + 7 + 1 + + + PSIZE + PSIZE + 8 + 2 + + + MSIZE + MSIZE + 10 + 2 + + + PL + PL + 12 + 2 + + + MEM2MEM + MEM2MEM + 14 + 1 + + + + + CCR7 + CCR7 + DMA channel 6 configuration register + 0x80 + 0x20 + read-write + 0x00000000 + + + EN + channel enable + 0 + 1 + + + TCIE + TCIE + 1 + 1 + + + HTIE + HTIE + 2 + 1 + + + TEIE + TEIE + 3 + 1 + + + DIR + DIR + 4 + 1 + + + CIRC + CIRC + 5 + 1 + + + PINC + PINC + 6 + 1 + + + MINC + MINC + 7 + 1 + + + PSIZE + PSIZE + 8 + 2 + + + MSIZE + MSIZE + 10 + 2 + + + PL + PL + 12 + 2 + + + MEM2MEM + MEM2MEM + 14 + 1 + + + + + CCR8 + CCR8 + DMA channel 7 configuration register + 0x94 + 0x20 + read-write + 0x00000000 + + + EN + channel enable + 0 + 1 + + + TCIE + TCIE + 1 + 1 + + + HTIE + HTIE + 2 + 1 + + + TEIE + TEIE + 3 + 1 + + + DIR + DIR + 4 + 1 + + + CIRC + CIRC + 5 + 1 + + + PINC + PINC + 6 + 1 + + + MINC + MINC + 7 + 1 + + + PSIZE + PSIZE + 8 + 2 + + + MSIZE + MSIZE + 10 + 2 + + + PL + PL + 12 + 2 + + + MEM2MEM + MEM2MEM + 14 + 1 + + + + + CNDTR1 + CNDTR1 + channel x number of data to transfer register + 0xC + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to transfer + 0 + 16 + + + + + CNDTR2 + CNDTR2 + channel x number of data to transfer register + 0x20 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to transfer + 0 + 16 + + + + + CNDTR3 + CNDTR3 + channel x number of data to transfer register + 0x34 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to transfer + 0 + 16 + + + + + CNDTR4 + CNDTR4 + channel x number of data to transfer register + 0x48 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to transfer + 0 + 16 + + + + + CNDTR5 + CNDTR5 + channel x number of data to transfer register + 0x5C + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to transfer + 0 + 16 + + + + + CNDTR6 + CNDTR6 + channel x number of data to transfer register + 0x70 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to transfer + 0 + 16 + + + + + CNDTR7 + CNDTR7 + channel x number of data to transfer register + 0x84 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to transfer + 0 + 16 + + + + + CNDTR8 + CNDTR8 + channel x number of data to transfer register + 0x98 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to transfer + 0 + 16 + + + + + CPAR1 + CPAR1 + DMA channel x peripheral address register + 0x10 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CPAR2 + CPAR2 + DMA channel x peripheral address register + 0x24 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CPAR3 + CPAR3 + DMA channel x peripheral address register + 0x38 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CPAR4 + CPAR4 + DMA channel x peripheral address register + 0x4C + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CPAR5 + CPAR5 + DMA channel x peripheral address register + 0x60 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CPAR6 + CPAR6 + DMA channel x peripheral address register + 0x74 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CPAR7 + CPAR7 + DMA channel x peripheral address register + 0x88 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CPAR8 + CPAR8 + DMA channel x peripheral address register + 0x9C + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR1 + CMAR1 + DMA channel x memory address register + 0x14 + 0x20 + read-write + 0x00000000 + + + MA + Memory 1 address (used in case of Double buffer mode) + 0 + 32 + + + + + CMAR2 + CMAR2 + DMA channel x memory address register + 0x28 + 0x20 + read-write + 0x00000000 + + + MA + Memory 1 address (used in case of Double buffer mode) + 0 + 32 + + + + + CMAR3 + CMAR3 + DMA channel x memory address register + 0x3C + 0x20 + read-write + 0x00000000 + + + MA + Memory 1 address (used in case of Double buffer mode) + 0 + 32 + + + + + CMAR4 + CMAR4 + DMA channel x memory address register + 0x50 + 0x20 + read-write + 0x00000000 + + + MA + Memory 1 address (used in case of Double buffer mode) + 0 + 32 + + + + + CMAR5 + CMAR5 + DMA channel x memory address register + 0x64 + 0x20 + read-write + 0x00000000 + + + MA + Memory 1 address (used in case of Double buffer mode) + 0 + 32 + + + + + CMAR6 + CMAR6 + DMA channel x memory address register + 0x78 + 0x20 + read-write + 0x00000000 + + + MA + Memory 1 address (used in case of Double buffer mode) + 0 + 32 + + + + + CMAR7 + CMAR7 + DMA channel x memory address register + 0x8C + 0x20 + read-write + 0x00000000 + + + MA + Memory 1 address (used in case of Double buffer mode) + 0 + 32 + + + + + CMAR8 + CMAR8 + DMA channel x memory address register + 0xA0 + 0x20 + read-write + 0x00000000 + + + MA + Memory 1 address (used in case of Double buffer mode) + 0 + 32 + + + + + + + DMA2 + 0x40020400 + + DMA1_CH7 + DMA1 channel 7 interrupt + 17 + + + DMA2_CH1 + DMA2_CH1 + 56 + + + DMA2_CH2 + DMA2_CH2 + 57 + + + DMA2_CH3 + DMA2_CH3 + 58 + + + DMA2_CH4 + DMA2_CH4 + 59 + + + DMA2_CH5 + DMA2_CH5 + 60 + + + DMA2_CH6 + DMA2_CH6 + 97 + + + DMA2_CH7 + DMA2_CH7 + 98 + + + DMA2_CH8 + DMA2_CH8 + 99 + + + + DMAMUX + DMAMUX + DMAMUX + 0x40020800 + + 0x0 + 0x400 + registers + + + DMAMUX_OVR + DMAMUX_OVR + 94 + + + + C0CR + C0CR + DMAMux - DMA request line multiplexer channel x control register + 0x0 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C1CR + C1CR + DMAMux - DMA request line multiplexer channel x control register + 0x4 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C2CR + C2CR + DMAMux - DMA request line multiplexer channel x control register + 0x8 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C3CR + C3CR + DMAMux - DMA request line multiplexer channel x control register + 0xC + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C4CR + C4CR + DMAMux - DMA request line multiplexer channel x control register + 0x10 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C5CR + C5CR + DMAMux - DMA request line multiplexer channel x control register + 0x14 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C6CR + C6CR + DMAMux - DMA request line multiplexer channel x control register + 0x18 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C7CR + C7CR + DMAMux - DMA request line multiplexer channel x control register + 0x1C + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C8CR + C8CR + DMAMux - DMA request line multiplexer channel x control register + 0x20 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C9CR + C9CR + DMAMux - DMA request line multiplexer channel x control register + 0x24 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C10CR + C10CR + DMAMux - DMA request line multiplexer channel x control register + 0x28 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C11CR + C11CR + DMAMux - DMA request line multiplexer channel x control register + 0x2C + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C12CR + C12CR + DMAMux - DMA request line multiplexer channel x control register + 0x30 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C13CR + C13CR + DMAMux - DMA request line multiplexer channel x control register + 0x34 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C14CR + C14CR + DMAMux - DMA request line multiplexer channel x control register + 0x38 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C15CR + C15CR + DMAMux - DMA request line multiplexer channel x control register + 0x3C + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + RG0CR + RG0CR + DMAMux - DMA request generator channel x control register + 0x100 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input selected + 0 + 5 + + + OIE + Interrupt enable at trigger event overrun + 8 + 1 + + + GE + DMA request generator channel enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset. + 19 + 5 + + + + + RG1CR + RG1CR + DMAMux - DMA request generator channel x control register + 0x104 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input selected + 0 + 5 + + + OIE + Interrupt enable at trigger event overrun + 8 + 1 + + + GE + DMA request generator channel enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset. + 19 + 5 + + + + + RG2CR + RG2CR + DMAMux - DMA request generator channel x control register + 0x108 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input selected + 0 + 5 + + + OIE + Interrupt enable at trigger event overrun + 8 + 1 + + + GE + DMA request generator channel enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset. + 19 + 5 + + + + + RG3CR + RG3CR + DMAMux - DMA request generator channel x control register + 0x10C + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input selected + 0 + 5 + + + OIE + Interrupt enable at trigger event overrun + 8 + 1 + + + GE + DMA request generator channel enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset. + 19 + 5 + + + + + RGSR + RGSR + DMAMux - DMA request generator status register + 0x140 + 0x20 + read-only + 0x00000000 + + + OF + Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register. + 0 + 4 + + + + + RGCFR + RGCFR + DMAMux - DMA request generator clear flag register + 0x144 + 0x20 + write-only + 0x00000000 + + + COF + Clear trigger event overrun flag Upon setting, this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register. + 0 + 4 + + + + + CSR + CSR + DMAMUX request line multiplexer interrupt channel status register + 0x80 + 0x20 + read-only + 0x00000000 + + + SOF + Synchronization overrun event flag + 0 + 16 + + + + + CFR + CFR + DMAMUX request line multiplexer interrupt clear flag register + 0x84 + 0x20 + write-only + 0x00000000 + + + CSOF + Clear synchronization overrun event flag + 0 + 16 + + + + + + + SYSCFG + System configuration controller + SYSCFG + 0x40010000 + + 0x0 + 0x2A + registers + + + + MEMRMP + MEMRMP + Remap Memory register + 0x0 + 0x20 + read-write + 0x00000000 + + + MEM_MODE + Memory mapping selection + 0 + 3 + + + FB_mode + User Flash Bank mode + 8 + 1 + + + + + CFGR1 + CFGR1 + peripheral mode configuration register + 0x4 + 0x20 + read-write + 0x7C000001 + + + BOOSTEN + BOOSTEN + 8 + 1 + + + ANASWVDD + GPIO analog switch control voltage selection + 9 + 1 + + + I2C_PB6_FMP + FM+ drive capability on PB6 + 16 + 1 + + + I2C_PB7_FMP + FM+ drive capability on PB6 + 17 + 1 + + + I2C_PB8_FMP + FM+ drive capability on PB6 + 18 + 1 + + + I2C_PB9_FMP + FM+ drive capability on PB6 + 19 + 1 + + + I2C1_FMP + I2C1 FM+ drive capability enable + 20 + 1 + + + I2C2_FMP + I2C1 FM+ drive capability enable + 21 + 1 + + + I2C3_FMP + I2C1 FM+ drive capability enable + 22 + 1 + + + I2C4_FMP + I2C1 FM+ drive capability enable + 23 + 1 + + + FPU_IE + FPU Interrupts Enable + 26 + 6 + + + + + EXTICR1 + EXTICR1 + external interrupt configuration register 1 + 0x8 + 0x20 + read-write + 0x0000 + + + EXTI3 + EXTI x configuration (x = 0 to 3) + 12 + 4 + + + EXTI2 + EXTI x configuration (x = 0 to 3) + 8 + 4 + + + EXTI1 + EXTI x configuration (x = 0 to 3) + 4 + 4 + + + EXTI0 + EXTI x configuration (x = 0 to 3) + 0 + 4 + + + + + EXTICR2 + EXTICR2 + external interrupt configuration register 2 + 0xC + 0x20 + read-write + 0x0000 + + + EXTI7 + EXTI x configuration (x = 4 to 7) + 12 + 4 + + + EXTI6 + EXTI x configuration (x = 4 to 7) + 8 + 4 + + + EXTI5 + EXTI x configuration (x = 4 to 7) + 4 + 4 + + + EXTI4 + EXTI x configuration (x = 4 to 7) + 0 + 4 + + + + + EXTICR3 + EXTICR3 + external interrupt configuration register 3 + 0x10 + 0x20 + read-write + 0x0000 + + + EXTI11 + EXTI x configuration (x = 8 to 11) + 12 + 4 + + + EXTI10 + EXTI10 + 8 + 4 + + + EXTI9 + EXTI x configuration (x = 8 to 11) + 4 + 4 + + + EXTI8 + EXTI x configuration (x = 8 to 11) + 0 + 4 + + + + + EXTICR4 + EXTICR4 + external interrupt configuration register 4 + 0x14 + 0x20 + read-write + 0x0000 + + + EXTI15 + EXTI x configuration (x = 12 to 15) + 12 + 4 + + + EXTI14 + EXTI x configuration (x = 12 to 15) + 8 + 4 + + + EXTI13 + EXTI x configuration (x = 12 to 15) + 4 + 4 + + + EXTI12 + EXTI x configuration (x = 12 to 15) + 0 + 4 + + + + + SCSR + SCSR + CCM SRAM control and status register + 0x18 + 0x20 + 0x00000000 + + + CCMER + CCM SRAM Erase + 0 + 1 + read-write + + + CCMBSY + CCM SRAM busy by erase operation + 1 + 1 + read-only + + + + + CFGR2 + CFGR2 + configuration register 2 + 0x1C + 0x20 + read-write + 0x00000000 + + + CLL + Core Lockup Lock + 0 + 1 + + + SPL + SRAM Parity Lock + 1 + 1 + + + PVDL + PVD Lock + 2 + 1 + + + ECCL + ECC Lock + 3 + 1 + + + SPF + SRAM Parity Flag + 8 + 1 + + + + + SWPR + SWPR + SRAM Write protection register 1 + 0x20 + 0x20 + read-write + 0x00000000 + + + Page0_WP + Write protection + 0 + 1 + + + Page1_WP + Write protection + 1 + 1 + + + Page2_WP + Write protection + 2 + 1 + + + Page3_WP + Write protection + 3 + 1 + + + Page4_WP + Write protection + 4 + 1 + + + Page5_WP + Write protection + 5 + 1 + + + Page6_WP + Write protection + 6 + 1 + + + Page7_WP + Write protection + 7 + 1 + + + Page8_WP + Write protection + 8 + 1 + + + Page9_WP + Write protection + 9 + 1 + + + Page10_WP + Write protection + 10 + 1 + + + Page11_WP + Write protection + 11 + 1 + + + Page12_WP + Write protection + 12 + 1 + + + Page13_WP + Write protection + 13 + 1 + + + Page14_WP + Write protection + 14 + 1 + + + Page15_WP + Write protection + 15 + 1 + + + Page16_WP + Write protection + 16 + 1 + + + Page17_WP + Write protection + 17 + 1 + + + Page18_WP + Write protection + 18 + 1 + + + Page19_WP + Write protection + 19 + 1 + + + Page20_WP + Write protection + 20 + 1 + + + Page21_WP + Write protection + 21 + 1 + + + Page22_WP + Write protection + 22 + 1 + + + Page23_WP + Write protection + 23 + 1 + + + Page24_WP + Write protection + 24 + 1 + + + Page25_WP + Write protection + 25 + 1 + + + Page26_WP + Write protection + 26 + 1 + + + Page27_WP + Write protection + 27 + 1 + + + Page28_WP + Write protection + 28 + 1 + + + Page29_WP + Write protection + 29 + 1 + + + Page30_WP + Write protection + 30 + 1 + + + Page31_WP + Write protection + 31 + 1 + + + + + SKR + SKR + SRAM2 Key Register + 0x24 + 0x20 + write-only + 0x00000000 + + + KEY + SRAM2 Key for software erase + 0 + 8 + + + + + + + VREFBUF + Voltage reference buffer + VREFBUF + 0x40010030 + + 0x0 + 0x1D0 + registers + + + + VREFBUF_CSR + VREFBUF_CSR + VREF_BUF Control and Status Register + 0x0 + 0x20 + 0x00000002 + + + ENVR + Enable Voltage Reference + 0 + 1 + read-write + + + HIZ + High impedence mode for the VREF_BUF + 1 + 1 + read-write + + + VRR + Voltage reference buffer ready + 3 + 1 + read-only + + + VRS + Voltage reference scale + 4 + 2 + read-write + + + + + VREFBUF_CCR + VREFBUF_CCR + VREF_BUF Calibration Control Register + 0x04 + 0x20 + read-write + 0x00000000 + + + TRIM + Trimming code + 0 + 6 + + + + + + + COMP + Comparator control and status register + COMP + 0x40010200 + + 0x0 + 0x100 + registers + + + COMP1_2_3 + COMP1_2_3 + 64 + + + COMP4_5_6 + COMP4_5_6 + 65 + + + COMP7 + COMP7 + 66 + + + + COMP_C1CSR + COMP_C1CSR + Comparator control/status register + 0x0 + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + INMSEL + INMSEL + 4 + 3 + read-write + + + INPSEL + INPSEL + 8 + 1 + read-write + + + POL + POL + 15 + 1 + read-write + + + HYST + HYST + 16 + 3 + read-write + + + BLANKSEL + BLANKSEL + 19 + 3 + read-write + + + BRGEN + BRGEN + 22 + 1 + read-write + + + SCALEN + SCALEN + 23 + 1 + read-write + + + VALUE + VALUE + 30 + 1 + read-only + + + LOCK + LOCK + 31 + 1 + read-write + + + + + COMP_C2CSR + COMP_C2CSR + Comparator control/status register + 0x4 + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + INMSEL + INMSEL + 4 + 3 + read-write + + + INPSEL + INPSEL + 8 + 1 + read-write + + + POL + POL + 15 + 1 + read-write + + + HYST + HYST + 16 + 3 + read-write + + + BLANKSEL + BLANKSEL + 19 + 3 + read-write + + + BRGEN + BRGEN + 22 + 1 + read-write + + + SCALEN + SCALEN + 23 + 1 + read-write + + + VALUE + VALUE + 30 + 1 + read-only + + + LOCK + LOCK + 31 + 1 + read-write + + + + + COMP_C3CSR + COMP_C3CSR + Comparator control/status register + 0x8 + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + INMSEL + INMSEL + 4 + 3 + read-write + + + INPSEL + INPSEL + 8 + 1 + read-write + + + POL + POL + 15 + 1 + read-write + + + HYST + HYST + 16 + 3 + read-write + + + BLANKSEL + BLANKSEL + 19 + 3 + read-write + + + BRGEN + BRGEN + 22 + 1 + read-write + + + SCALEN + SCALEN + 23 + 1 + read-write + + + VALUE + VALUE + 30 + 1 + read-only + + + LOCK + LOCK + 31 + 1 + read-write + + + + + COMP_C4CSR + COMP_C4CSR + Comparator control/status register + 0x0C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + INMSEL + INMSEL + 4 + 3 + read-write + + + INPSEL + INPSEL + 8 + 1 + read-write + + + POL + POL + 15 + 1 + read-write + + + HYST + HYST + 16 + 3 + read-write + + + BLANKSEL + BLANKSEL + 19 + 3 + read-write + + + BRGEN + BRGEN + 22 + 1 + read-write + + + SCALEN + SCALEN + 23 + 1 + read-write + + + VALUE + VALUE + 30 + 1 + read-only + + + LOCK + LOCK + 31 + 1 + read-write + + + + + COMP_C5CSR + COMP_C5CSR + Comparator control/status register + 0x10 + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + INMSEL + INMSEL + 4 + 3 + read-write + + + INPSEL + INPSEL + 8 + 1 + read-write + + + POL + POL + 15 + 1 + read-write + + + HYST + HYST + 16 + 3 + read-write + + + BLANKSEL + BLANKSEL + 19 + 3 + read-write + + + BRGEN + BRGEN + 22 + 1 + read-write + + + SCALEN + SCALEN + 23 + 1 + read-write + + + VALUE + VALUE + 30 + 1 + read-only + + + LOCK + LOCK + 31 + 1 + read-write + + + + + COMP_C6CSR + COMP_C6CSR + Comparator control/status register + 0x14 + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + INMSEL + INMSEL + 4 + 3 + read-write + + + INPSEL + INPSEL + 8 + 1 + read-write + + + POL + POL + 15 + 1 + read-write + + + HYST + HYST + 16 + 3 + read-write + + + BLANKSEL + BLANKSEL + 19 + 3 + read-write + + + BRGEN + BRGEN + 22 + 1 + read-write + + + SCALEN + SCALEN + 23 + 1 + read-write + + + VALUE + VALUE + 30 + 1 + read-only + + + LOCK + LOCK + 31 + 1 + read-write + + + + + COMP_C7CSR + COMP_C7CSR + Comparator control/status register + 0x18 + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + INMSEL + INMSEL + 4 + 3 + read-write + + + INPSEL + INPSEL + 8 + 1 + read-write + + + POL + POL + 15 + 1 + read-write + + + HYST + HYST + 16 + 3 + read-write + + + BLANKSEL + BLANKSEL + 19 + 3 + read-write + + + BRGEN + BRGEN + 22 + 1 + read-write + + + SCALEN + SCALEN + 23 + 1 + read-write + + + VALUE + VALUE + 30 + 1 + read-only + + + LOCK + LOCK + 31 + 1 + read-write + + + + + + + OPAMP + Operational amplifiers + OPAMP + 0x40010300 + + 0x0 + 0x100 + registers + + + + OPAMP1_CSR + OPAMP1_CSR + OPAMP1 control/status register + 0x0 + 0x20 + read-write + 0x00000000 + + + OPAEN + Operational amplifier Enable + 0 + 1 + + + FORCE_VP + FORCE_VP + 1 + 1 + + + VP_SEL + VP_SEL + 2 + 2 + + + USERTRIM + USERTRIM + 4 + 1 + + + VM_SEL + VM_SEL + 5 + 2 + + + OPAHSM + OPAHSM + 7 + 1 + + + OPAINTOEN + OPAINTOEN + 8 + 1 + + + CALON + CALON + 11 + 1 + + + CALSEL + CALSEL + 12 + 2 + + + PGA_GAIN + PGA_GAIN + 14 + 5 + + + TRIMOFFSETP + TRIMOFFSETP + 19 + 5 + + + TRIMOFFSETN + TRIMOFFSETN + 24 + 5 + + + CALOUT + CALOUT + 30 + 1 + + + LOCK + LOCK + 31 + 1 + + + + + + OPAMP2_CSR + OPAMP2_CSR + OPAMP2 control/status register + 0x4 + 0x20 + read-write + 0x00000000 + + + OPAEN + Operational amplifier Enable + 0 + 1 + + + FORCE_VP + FORCE_VP + 1 + 1 + + + VP_SEL + VP_SEL + 2 + 2 + + + USERTRIM + USERTRIM + 4 + 1 + + + VM_SEL + VM_SEL + 5 + 2 + + + OPAHSM + OPAHSM + 7 + 1 + + + OPAINTOEN + OPAINTOEN + 8 + 1 + + + CALON + CALON + 11 + 1 + + + CALSEL + CALSEL + 12 + 2 + + + PGA_GAIN + PGA_GAIN + 14 + 5 + + + TRIMOFFSETP + TRIMOFFSETP + 19 + 5 + + + TRIMOFFSETN + TRIMOFFSETN + 24 + 5 + + + CALOUT + CALOUT + 30 + 1 + + + LOCK + LOCK + 31 + 1 + + + + + + OPAMP3_CSR + OPAMP3_CSR + OPAMP3 control/status register + 0x8 + 0x20 + read-write + 0x00000000 + + + OPAEN + Operational amplifier Enable + 0 + 1 + + + FORCE_VP + FORCE_VP + 1 + 1 + + + VP_SEL + VP_SEL + 2 + 2 + + + USERTRIM + USERTRIM + 4 + 1 + + + VM_SEL + VM_SEL + 5 + 2 + + + OPAHSM + OPAHSM + 7 + 1 + + + OPAINTOEN + OPAINTOEN + 8 + 1 + + + CALON + CALON + 11 + 1 + + + CALSEL + CALSEL + 12 + 2 + + + PGA_GAIN + PGA_GAIN + 14 + 5 + + + TRIMOFFSETP + TRIMOFFSETP + 19 + 5 + + + TRIMOFFSETN + TRIMOFFSETN + 24 + 5 + + + CALOUT + CALOUT + 30 + 1 + + + LOCK + LOCK + 31 + 1 + + + + + + OPAMP4_CSR + OPAMP4_CSR + OPAMP4 control/status register + 0xC + 0x20 + read-write + 0x00000000 + + + OPAEN + Operational amplifier Enable + 0 + 1 + + + FORCE_VP + FORCE_VP + 1 + 1 + + + VP_SEL + VP_SEL + 2 + 2 + + + USERTRIM + USERTRIM + 4 + 1 + + + VM_SEL + VM_SEL + 5 + 2 + + + OPAHSM + OPAHSM + 7 + 1 + + + OPAINTOEN + OPAINTOEN + 8 + 1 + + + CALON + CALON + 11 + 1 + + + CALSEL + CALSEL + 12 + 2 + + + PGA_GAIN + PGA_GAIN + 14 + 5 + + + TRIMOFFSETP + TRIMOFFSETP + 19 + 5 + + + TRIMOFFSETN + TRIMOFFSETN + 24 + 5 + + + CALOUT + CALOUT + 30 + 1 + + + LOCK + LOCK + 31 + 1 + + + + + + OPAMP5_CSR + OPAMP5_CSR + OPAMP5 control/status register + 0x10 + 0x20 + read-write + 0x00000000 + + + OPAEN + Operational amplifier Enable + 0 + 1 + + + FORCE_VP + FORCE_VP + 1 + 1 + + + VP_SEL + VP_SEL + 2 + 2 + + + USERTRIM + USERTRIM + 4 + 1 + + + VM_SEL + VM_SEL + 5 + 2 + + + OPAHSM + OPAHSM + 7 + 1 + + + OPAINTOEN + OPAINTOEN + 8 + 1 + + + CALON + CALON + 11 + 1 + + + CALSEL + CALSEL + 12 + 2 + + + PGA_GAIN + PGA_GAIN + 14 + 5 + + + TRIMOFFSETP + TRIMOFFSETP + 19 + 5 + + + TRIMOFFSETN + TRIMOFFSETN + 24 + 5 + + + CALOUT + CALOUT + 30 + 1 + + + LOCK + LOCK + 31 + 1 + + + + + + OPAMP6_CSR + OPAMP6_CSR + OPAMP6 control/status register + 0x14 + 0x20 + read-write + 0x00000000 + + + OPAEN + Operational amplifier Enable + 0 + 1 + + + FORCE_VP + FORCE_VP + 1 + 1 + + + VP_SEL + VP_SEL + 2 + 2 + + + USERTRIM + USERTRIM + 4 + 1 + + + VM_SEL + VM_SEL + 5 + 2 + + + OPAHSM + OPAHSM + 7 + 1 + + + OPAINTOEN + OPAINTOEN + 8 + 1 + + + CALON + CALON + 11 + 1 + + + CALSEL + CALSEL + 12 + 2 + + + PGA_GAIN + PGA_GAIN + 14 + 5 + + + TRIMOFFSETP + TRIMOFFSETP + 19 + 5 + + + TRIMOFFSETN + TRIMOFFSETN + 24 + 5 + + + CALOUT + CALOUT + 30 + 1 + + + LOCK + LOCK + 31 + 1 + + + + + + OPAMP1_TCMR + OPAMP1_TCMR + OPAMP1 control/status register + 0x18 + 0x20 + read-write + 0x00000000 + + + VMS_SEL + VMS_SEL + 0 + 1 + + + VPS_SEL + VPS_SEL + 1 + 2 + + + T1CM_EN + T1CM_EN + 3 + 1 + + + T8CM_EN + T8CM_EN + 4 + 1 + + + T20CM_EN + T20CM_EN + 5 + 1 + + + LOCK + LOCK + 31 + 1 + + + + + + OPAMP2_TCMR + OPAMP2_TCMR + OPAMP2 control/status register + 0x1C + 0x20 + read-write + 0x00000000 + + + VMS_SEL + VMS_SEL + 0 + 1 + + + VPS_SEL + VPS_SEL + 1 + 2 + + + T1CM_EN + T1CM_EN + 3 + 1 + + + T8CM_EN + T8CM_EN + 4 + 1 + + + T20CM_EN + T20CM_EN + 5 + 1 + + + LOCK + LOCK + 31 + 1 + + + + + + OPAMP3_TCMR + OPAMP3_TCMR + OPAMP3 control/status register + 0x20 + 0x20 + read-write + 0x00000000 + + + VMS_SEL + VMS_SEL + 0 + 1 + + + VPS_SEL + VPS_SEL + 1 + 2 + + + T1CM_EN + T1CM_EN + 3 + 1 + + + T8CM_EN + T8CM_EN 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+ ADC Trigger 3 Register + 0x44 + 0x20 + read-write + 0x00000000 + + + AD1TEPER + AD1TEPER + 31 + 1 + + + AD1TEC4 + AD1TEC4 + 30 + 1 + + + AD1TEC3 + AD1TEC3 + 29 + 1 + + + AD1TEC2 + AD1TEC2 + 28 + 1 + + + AD1TDPER + AD1TDPER + 27 + 1 + + + AD1TDC4 + AD1TDC4 + 26 + 1 + + + AD1TDC3 + AD1TDC3 + 25 + 1 + + + AD1TDC2 + AD1TDC2 + 24 + 1 + + + AD1TCPER + AD1TCPER + 23 + 1 + + + AD1TCC4 + AD1TCC4 + 22 + 1 + + + AD1TCC3 + AD1TCC3 + 21 + 1 + + + AD1TCC2 + AD1TCC2 + 20 + 1 + + + AD1TBRST + AD1TBRST + 19 + 1 + + + AD1TBPER + AD1TBPER + 18 + 1 + + + AD1TBC4 + AD1TBC4 + 17 + 1 + + + AD1TBC3 + AD1TBC3 + 16 + 1 + + + AD1TBC2 + AD1TBC2 + 15 + 1 + + + AD1TARST + AD1TARST + 14 + 1 + + + AD1TAPER + AD1TAPER + 13 + 1 + + + AD1TAC4 + AD1TAC4 + 12 + 1 + + + AD1TAC3 + AD1TAC3 + 11 + 1 + + + AD1TAC2 + AD1TAC2 + 10 + 1 + + + AD1EEV5 + AD1EEV5 + 9 + 1 + + + AD1EEV4 + AD1EEV4 + 8 + 1 + + + AD1EEV3 + AD1EEV3 + 7 + 1 + + + AD1EEV2 + AD1EEV2 + 6 + 1 + + + AD1EEV1 + AD1EEV1 + 5 + 1 + + + AD1MPER + AD1MPER + 4 + 1 + + + AD1MC4 + AD1MC4 + 3 + 1 + + + AD1MC3 + AD1MC3 + 2 + 1 + + + AD1MC2 + AD1MC2 + 1 + 1 + + + AD1MC1 + AD1MC1 + 0 + 1 + + + + + ADC4R + ADC4R + ADC Trigger 4 Register + 0x48 + 0x20 + read-write + 0x00000000 + + + AD2TERST + AD2TERST + 31 + 1 + + + AD2TEC4 + AD2TEC4 + 30 + 1 + + + AD2TEC3 + AD2TEC3 + 29 + 1 + + + AD2TEC2 + AD2TEC2 + 28 + 1 + + + AD2TDRST + AD2TDRST + 27 + 1 + + + AD2TDPER + AD2TDPER + 26 + 1 + + + AD2TDC4 + AD2TDC4 + 25 + 1 + + + AD2TDC3 + AD2TDC3 + 24 + 1 + + + AD2TDC2 + AD2TDC2 + 23 + 1 + + + AD2TCRST + AD2TCRST + 22 + 1 + + + AD2TCPER + AD2TCPER + 21 + 1 + + + AD2TCC4 + AD2TCC4 + 20 + 1 + + + AD2TCC3 + AD2TCC3 + 19 + 1 + + + AD2TCC2 + AD2TCC2 + 18 + 1 + + + AD2TBPER + AD2TBPER + 17 + 1 + + + AD2TBC4 + AD2TBC4 + 16 + 1 + + + AD2TBC3 + AD2TBC3 + 15 + 1 + + + AD2TBC2 + AD2TBC2 + 14 + 1 + + + AD2TAPER + AD2TAPER + 13 + 1 + + + AD2TAC4 + AD2TAC4 + 12 + 1 + + + AD2TAC3 + AD2TAC3 + 11 + 1 + + + AD2TAC2 + AD2TAC2 + 10 + 1 + + + AD2EEV10 + AD2EEV10 + 9 + 1 + + + AD2EEV9 + AD2EEV9 + 8 + 1 + + + AD2EEV8 + AD2EEV8 + 7 + 1 + + + AD2EEV7 + AD2EEV7 + 6 + 1 + + + AD2EEV6 + AD2EEV6 + 5 + 1 + + + AD2MPER + AD2MPER + 4 + 1 + + + AD2MC4 + AD2MC4 + 3 + 1 + + + AD2MC3 + AD2MC3 + 2 + 1 + + + AD2MC2 + AD2MC2 + 1 + 1 + + + AD2MC1 + AD2MC1 + 0 + 1 + + + + + DLLCR + DLLCR + DLL Control Register + 0x4C + 0x20 + read-write + 0x00000000 + + + CALRTE + DLL Calibration rate + 2 + 2 + + + CALEN + DLL Calibration Enable + 1 + 1 + + + CAL + DLL Calibration Start + 0 + 1 + + + + + FLTINR1 + FLTINR1 + HRTIM Fault Input Register 1 + 0x50 + 0x20 + read-write + 0x00000000 + + + FLT4LCK + FLT4LCK + 31 + 1 + + + FLT4F + FLT4F + 27 + 4 + + + FLT4SRC + FLT4SRC + 26 + 1 + + + FLT4P + FLT4P + 25 + 1 + + + FLT4E + FLT4E + 24 + 1 + + + FLT3LCK + FLT3LCK + 23 + 1 + + + FLT3F + FLT3F + 19 + 4 + + + FLT3SRC + FLT3SRC + 18 + 1 + + + FLT3P + FLT3P + 17 + 1 + + + FLT3E + FLT3E + 16 + 1 + + + FLT2LCK + FLT2LCK + 15 + 1 + + + FLT2F + FLT2F + 11 + 4 + + + FLT2SRC + FLT2SRC + 10 + 1 + + + FLT2P + FLT2P + 9 + 1 + + + FLT2E + FLT2E + 8 + 1 + + + FLT1LCK + FLT1LCK + 7 + 1 + + + FLT1F + FLT1F + 3 + 4 + + + FLT1SRC + FLT1SRC + 2 + 1 + + + FLT1P + FLT1P + 1 + 1 + + + FLT1E + FLT1E + 0 + 1 + + + + + FLTINR2 + FLTINR2 + HRTIM Fault Input Register 2 + 0x54 + 0x20 + read-write + 0x00000000 + + + FLTSD + FLTSD + 24 + 2 + + + FLT6SRC_1 + FLT6SRC + 21 + 1 + + + FLT5SRC_1 + FLT5SRC_1 + 20 + 1 + + + FLT4SRC_1 + FLT4SRC_1 + 19 + 1 + + + FLT3SRC_1 + FLT3SRC_1 + 18 + 1 + + + FLT2SRC_1 + FLT2SRC_1 + 17 + 1 + + + FLT1SRC_1 + FLT1SRC_1 + 16 + 1 + + + FLT6LCK + FLT6LCK + 15 + 1 + + + FLT6F + FLT6F + 11 + 4 + + + FLT6SRC_0 + FLT6F + 10 + 1 + + + FLT6P + FLT6P + 9 + 1 + + + FLT6E + FLT6E + 8 + 1 + + + FLT5LCK + FLT5LCK + 7 + 1 + + + FLT5F + FLT5F + 3 + 4 + + + FLT5SRC + FLT5SRC + 2 + 1 + + + FLT5P + FLT5P + 1 + 1 + + + FLT5E + FLT5E + 0 + 1 + + + + + BDMUPDR + BDMUPDR + BDMUPDR + 0x58 + 0x20 + read-write + 0x00000000 + + + MCMP4 + MCMP4 + 9 + 1 + + + MCMP3 + MCMP3 + 8 + 1 + + + MCMP2 + MCMP2 + 7 + 1 + + + MCMP1 + MCMP1 + 6 + 1 + + + MREP + MREP + 5 + 1 + + + MPER + MPER + 4 + 1 + + + MCNT + MCNT + 3 + 1 + + + MDIER + MDIER + 2 + 1 + + + MICR + MICR + 1 + 1 + + + MCR + MCR + 0 + 1 + + + + + BDTAUPR + BDTAUPR + Burst DMA Timerx update Register + 0x5C + 0x20 + read-write + 0x00000000 + + + TIMxEEFR3 + TIMxEEFR3 + 22 + 1 + + + TIMxCR2 + TIMxCR2 + 21 + 1 + + + TIMxFLTR + HRTIM_FLTxR register update enable + 20 + 1 + + + TIMxOUTR + HRTIM_OUTxR register update enable + 19 + 1 + + + TIMxCHPR + HRTIM_CHPxR register update enable + 18 + 1 + + + TIMxRSTR + HRTIM_RSTxR register update enable + 17 + 1 + + + TIMxEEFR2 + HRTIM_EEFxR2 register update enable + 16 + 1 + + + TIMxEEFR1 + HRTIM_EEFxR1 register update enable + 15 + 1 + + + TIMxRST2R + HRTIM_RST2xR register update enable + 14 + 1 + + + TIMxSET2R + HRTIM_SET2xR register update enable + 13 + 1 + + + TIMxRST1R + HRTIM_RST1xR register update enable + 12 + 1 + + + TIMxSET1R + HRTIM_SET1xR register update enable + 11 + 1 + + + TIMx_DTxR + HRTIM_DTxR register update enable + 10 + 1 + + + TIMxCMP4 + HRTIM_CMP4xR register update enable + 9 + 1 + + + TIMxCMP3 + HRTIM_CMP3xR register update enable + 8 + 1 + + + TIMxCMP2 + HRTIM_CMP2xR register update enable + 7 + 1 + + + TIMxCMP1 + HRTIM_CMP1xR register update enable + 6 + 1 + + + TIMxREP + HRTIM_REPxR register update enable + 5 + 1 + + + TIMxPER + HRTIM_PERxR register update enable + 4 + 1 + + + TIMxCNT + HRTIM_CNTxR register update enable + 3 + 1 + + + TIMxDIER + HRTIM_TIMxDIER register update enable + 2 + 1 + + + TIMxICR + HRTIM_TIMxICR register update enable + 1 + 1 + + + TIMxCR + HRTIM_TIMxCR register update enable + 0 + 1 + + + + + BDTBUPR + BDTBUPR + Burst DMA Timerx update Register + 0x60 + 0x20 + read-write + 0x00000000 + + + TIMxEEFR3 + TIMxEEFR3 + 22 + 1 + + + TIMxCR2 + TIMxCR2 + 21 + 1 + + + TIMxFLTR + HRTIM_FLTxR register update enable + 20 + 1 + + + TIMxOUTR + HRTIM_OUTxR register update enable + 19 + 1 + + + TIMxCHPR + HRTIM_CHPxR register update enable + 18 + 1 + + + TIMxRSTR + HRTIM_RSTxR register update enable + 17 + 1 + + + TIMxEEFR2 + HRTIM_EEFxR2 register update enable + 16 + 1 + + + TIMxEEFR1 + HRTIM_EEFxR1 register update enable + 15 + 1 + + + TIMxRST2R + HRTIM_RST2xR register update enable + 14 + 1 + + + TIMxSET2R + HRTIM_SET2xR register update enable + 13 + 1 + + + TIMxRST1R + HRTIM_RST1xR register update enable + 12 + 1 + + + TIMxSET1R + HRTIM_SET1xR register update enable + 11 + 1 + + + TIMx_DTxR + HRTIM_DTxR register update enable + 10 + 1 + + + TIMxCMP4 + HRTIM_CMP4xR register update enable + 9 + 1 + + + TIMxCMP3 + HRTIM_CMP3xR register update enable + 8 + 1 + + + TIMxCMP2 + HRTIM_CMP2xR register update enable + 7 + 1 + + + TIMxCMP1 + HRTIM_CMP1xR register update enable + 6 + 1 + + + TIMxREP + HRTIM_REPxR register update enable + 5 + 1 + + + TIMxPER + HRTIM_PERxR register update enable + 4 + 1 + + + TIMxCNT + HRTIM_CNTxR register update enable + 3 + 1 + + + TIMxDIER + HRTIM_TIMxDIER register update enable + 2 + 1 + + + TIMxICR + HRTIM_TIMxICR register update enable + 1 + 1 + + + TIMxCR + HRTIM_TIMxCR register update enable + 0 + 1 + + + + + BDTCUPR + BDTCUPR + Burst DMA Timerx update Register + 0x64 + 0x20 + read-write + 0x00000000 + + + TIMxEEFR3 + TIMxEEFR3 + 22 + 1 + + + TIMxCR2 + TIMxCR2 + 21 + 1 + + + TIMxFLTR + HRTIM_FLTxR register update enable + 20 + 1 + + + TIMxOUTR + HRTIM_OUTxR register update enable + 19 + 1 + + + TIMxCHPR + HRTIM_CHPxR register update enable + 18 + 1 + + + TIMxRSTR + HRTIM_RSTxR register update enable + 17 + 1 + + + TIMxEEFR2 + HRTIM_EEFxR2 register update enable + 16 + 1 + + + TIMxEEFR1 + HRTIM_EEFxR1 register update enable + 15 + 1 + + + TIMxRST2R + HRTIM_RST2xR register update enable + 14 + 1 + + + TIMxSET2R + HRTIM_SET2xR register update enable + 13 + 1 + + + TIMxRST1R + HRTIM_RST1xR register update enable + 12 + 1 + + + TIMxSET1R + HRTIM_SET1xR register update enable + 11 + 1 + + + TIMx_DTxR + HRTIM_DTxR register update enable + 10 + 1 + + + TIMxCMP4 + HRTIM_CMP4xR register update enable + 9 + 1 + + + TIMxCMP3 + HRTIM_CMP3xR register update enable + 8 + 1 + + + TIMxCMP2 + HRTIM_CMP2xR register update enable + 7 + 1 + + + TIMxCMP1 + HRTIM_CMP1xR register update enable + 6 + 1 + + + TIMxREP + HRTIM_REPxR register update enable + 5 + 1 + + + TIMxPER + HRTIM_PERxR register update enable + 4 + 1 + + + TIMxCNT + HRTIM_CNTxR register update enable + 3 + 1 + + + TIMxDIER + HRTIM_TIMxDIER register update enable + 2 + 1 + + + TIMxICR + HRTIM_TIMxICR register update enable + 1 + 1 + + + TIMxCR + HRTIM_TIMxCR register update enable + 0 + 1 + + + + + BDTDUPR + BDTDUPR + Burst DMA Timerx update Register + 0x68 + 0x20 + read-write + 0x00000000 + + + TIMxEEFR3 + TIMxEEFR3 + 22 + 1 + + + TIMxCR2 + TIMxCR2 + 21 + 1 + + + TIMxFLTR + HRTIM_FLTxR register update enable + 20 + 1 + + + TIMxOUTR + HRTIM_OUTxR register update enable + 19 + 1 + + + TIMxCHPR + HRTIM_CHPxR register update enable + 18 + 1 + + + TIMxRSTR + HRTIM_RSTxR register update enable + 17 + 1 + + + TIMxEEFR2 + HRTIM_EEFxR2 register update enable + 16 + 1 + + + TIMxEEFR1 + HRTIM_EEFxR1 register update enable + 15 + 1 + + + TIMxRST2R + HRTIM_RST2xR register update enable + 14 + 1 + + + TIMxSET2R + HRTIM_SET2xR register update enable + 13 + 1 + + + TIMxRST1R + HRTIM_RST1xR register update enable + 12 + 1 + + + TIMxSET1R + HRTIM_SET1xR register update enable + 11 + 1 + + + TIMx_DTxR + HRTIM_DTxR register update enable + 10 + 1 + + + TIMxCMP4 + HRTIM_CMP4xR register update enable + 9 + 1 + + + TIMxCMP3 + HRTIM_CMP3xR register update enable + 8 + 1 + + + TIMxCMP2 + HRTIM_CMP2xR register update enable + 7 + 1 + + + TIMxCMP1 + HRTIM_CMP1xR register update enable + 6 + 1 + + + TIMxREP + HRTIM_REPxR register update enable + 5 + 1 + + + TIMxPER + HRTIM_PERxR register update enable + 4 + 1 + + + TIMxCNT + HRTIM_CNTxR register update enable + 3 + 1 + + + TIMxDIER + HRTIM_TIMxDIER register update enable + 2 + 1 + + + TIMxICR + HRTIM_TIMxICR register update enable + 1 + 1 + + + TIMxCR + HRTIM_TIMxCR register update enable + 0 + 1 + + + + + BDTEUPR + BDTEUPR + Burst DMA Timerx update Register + 0x6C + 0x20 + read-write + 0x00000000 + + + TIMxEEFR3 + TIMxEEFR3 + 22 + 1 + + + TIMxCR2 + TIMxCR2 + 21 + 1 + + + TIMxFLTR + HRTIM_FLTxR register update enable + 20 + 1 + + + TIMxOUTR + HRTIM_OUTxR register update enable + 19 + 1 + + + TIMxCHPR + HRTIM_CHPxR register update enable + 18 + 1 + + + TIMxRSTR + HRTIM_RSTxR register update enable + 17 + 1 + + + TIMxEEFR2 + HRTIM_EEFxR2 register update enable + 16 + 1 + + + TIMxEEFR1 + HRTIM_EEFxR1 register update enable + 15 + 1 + + + TIMxRST2R + HRTIM_RST2xR register update enable + 14 + 1 + + + TIMxSET2R + HRTIM_SET2xR register update enable + 13 + 1 + + + TIMxRST1R + HRTIM_RST1xR register update enable + 12 + 1 + + + TIMxSET1R + HRTIM_SET1xR register update enable + 11 + 1 + + + TIMx_DTxR + HRTIM_DTxR register update enable + 10 + 1 + + + TIMxCMP4 + HRTIM_CMP4xR register update enable + 9 + 1 + + + TIMxCMP3 + HRTIM_CMP3xR register update enable + 8 + 1 + + + TIMxCMP2 + HRTIM_CMP2xR register update enable + 7 + 1 + + + TIMxCMP1 + HRTIM_CMP1xR register update enable + 6 + 1 + + + TIMxREP + HRTIM_REPxR register update enable + 5 + 1 + + + TIMxPER + HRTIM_PERxR register update enable + 4 + 1 + + + TIMxCNT + HRTIM_CNTxR register update enable + 3 + 1 + + + TIMxDIER + HRTIM_TIMxDIER register update enable + 2 + 1 + + + TIMxICR + HRTIM_TIMxICR register update enable + 1 + 1 + + + TIMxCR + HRTIM_TIMxCR register update enable + 0 + 1 + + + + + BDTFUPR + BDTFUPR + Burst DMA Timerx update Register + 0x74 + 0x20 + read-write + 0x00000000 + + + TIMxEEFR3 + TIMxEEFR3 + 22 + 1 + + + TIMxCR2 + TIMxCR2 + 21 + 1 + + + TIMxFLTR + HRTIM_FLTxR register update enable + 20 + 1 + + + TIMxOUTR + HRTIM_OUTxR register update enable + 19 + 1 + + + TIMxCHPR + HRTIM_CHPxR register update enable + 18 + 1 + + + TIMxRSTR + HRTIM_RSTxR register update enable + 17 + 1 + + + TIMxEEFR2 + HRTIM_EEFxR2 register update enable + 16 + 1 + + + TIMxEEFR1 + HRTIM_EEFxR1 register update enable + 15 + 1 + + + TIMxRST2R + HRTIM_RST2xR register update enable + 14 + 1 + + + TIMxSET2R + HRTIM_SET2xR register update enable + 13 + 1 + + + TIMxRST1R + HRTIM_RST1xR register update enable + 12 + 1 + + + TIMxSET1R + HRTIM_SET1xR register update enable + 11 + 1 + + + TIMx_DTxR + HRTIM_DTxR register update enable + 10 + 1 + + + TIMxCMP4 + HRTIM_CMP4xR register update enable + 9 + 1 + + + TIMxCMP3 + HRTIM_CMP3xR register update enable + 8 + 1 + + + TIMxCMP2 + HRTIM_CMP2xR register update enable + 7 + 1 + + + TIMxCMP1 + HRTIM_CMP1xR register update enable + 6 + 1 + + + TIMxREP + HRTIM_REPxR register update enable + 5 + 1 + + + TIMxPER + HRTIM_PERxR register update enable + 4 + 1 + + + TIMxCNT + HRTIM_CNTxR register update enable + 3 + 1 + + + TIMxDIER + HRTIM_TIMxDIER register update enable + 2 + 1 + + + TIMxICR + HRTIM_TIMxICR register update enable + 1 + 1 + + + TIMxCR + HRTIM_TIMxCR register update enable + 0 + 1 + + + + + BDMADR + BDMADR + Burst DMA Data Register + 0x70 + 0x20 + write-only + 0x00000000 + + + BDMADR + Burst DMA Data register + 0 + 32 + + + + + ADCER + ADCER + HRTIM ADC Extended Trigger Register + 0x78 + 0x20 + read-write + 0x00000000 + + + ADC10TRG + ADC10TRG + 26 + 5 + + + ADC9TRG + ADC9TRG + 21 + 5 + + + ADC8TRG + ADC8TRG + 16 + 5 + + + ADC7TRG + ADC7TRG + 10 + 5 + + + ADC6TRG + ADC6TRG + 5 + 5 + + + ADC5TRG + ADC5TRG + 0 + 5 + + + + + ADCUR + ADCUR + HRTIM ADC Trigger Update Register + 0x7C + 0x20 + read-write + 0x00000000 + + + AD10USRC + AD10USRC + 20 + 3 + + + AD9USRC + AD9USRC + 16 + 3 + + + AD8USRC + AD8USRC + 12 + 3 + + + AD7USRC + AD7USRC + 8 + 3 + + + AD6USRC + AD6USRC + 4 + 3 + + + AD5USRC + AD5USRC + 0 + 3 + + + + + ADCPS1 + ADCPS1 + HRTIM ADC Post Scaler Register 1 + 0x80 + 0x20 + read-write + 0x00000000 + + + ADC5PSC + ADC5PSC + 24 + 5 + + + ADC4PSC + ADC4PSC + 18 + 5 + + + ADC3PSC + ADC3PSC + 12 + 5 + + + ADC2PSC + ADC2PSC + 6 + 5 + + + ADC1PSC + ADC1PSC + 0 + 5 + + + + + ADCPS2 + ADCPS2 + HRTIM ADC Post Scaler Register 2 + 0x84 + 0x20 + read-write + 0x00000000 + + + ADC10PSC + ADC10PSC + 24 + 5 + + + ADC9PSC + ADC9PSC + 18 + 5 + + + ADC8PSC + ADC8PSC + 12 + 5 + + + ADC7PSC + ADC7PSC + 6 + 5 + + + ADC6PSC + ADC6PSC + 0 + 5 + + + + + FLTINR3 + FLTINR3 + HRTIM Fault Input Register 3 + 0x88 + 0x20 + read-write + 0x00000000 + + + FLT4RSTM + FLT4RSTM + 31 + 1 + + + FLT4CRES + FLT4CRES + 30 + 1 + + + FLT4CNT + FLT4CNT + 26 + 4 + + + FLT4BLKS + FLT4BLKS + 25 + 1 + + + FLT4BLKE + FLT4BLKE + 24 + 1 + + + FLT3RSTM + FLT3RSTM + 23 + 1 + + + FLT3CRES + FLT3CRES + 22 + 1 + + + FLT3CNT + FLT3CNT + 18 + 4 + + + FLT3BLKS + FLT3BLKS + 17 + 1 + + + FLT3BLKE + FLT3BLKE + 16 + 1 + + + FLT2RSTM + FLT2RSTM + 15 + 1 + + + FLT2CRES + FLT2CRES + 14 + 1 + + + FLT2CNT + FLT2CNT + 10 + 4 + + + FLT2BLKS + FLT2BLKS + 9 + 1 + + + FLT2BLKE + FLT2BLKE + 8 + 1 + + + FLT1RSTM + FLT1RSTM + 7 + 1 + + + FLT1CRES + FLT1CRES + 6 + 1 + + + FLT1CNT + FLT1CNT + 2 + 4 + + + FLT1BLKS + FLT1BLKS + 1 + 1 + + + FLT1BLKE + FLT1BLKE + 0 + 1 + + + + + FLTINR4 + FLTINR4 + HRTIM Fault Input Register 4 + 0x8C + 0x20 + read-write + 0x00000000 + + + FLT6RSTM + FLT6RSTM + 15 + 1 + + + FLT6CRES + FLT6CRES + 14 + 1 + + + FLT6CNT + FLT6CNT + 10 + 4 + + + FLT6BLKS + FLT6BLKS + 9 + 1 + + + FLT6BLKE + FLT6BLKE + 8 + 1 + + + FLT5RSTM + FLT5RSTM + 7 + 1 + + + FLT5CRES + FLT5CRES + 6 + 1 + + + FLT5CNT + FLT5CNT + 2 + 4 + + + FLT5BLKS + FLT5BLKS + 1 + 1 + + + FLT5BLKE + FLT5BLKE + 0 + 1 + + + + + + + QUADSPI + QuadSPI interface + QUADSPI + 0xA0001000 + + 0x0 + 0x400 + registers + + + QUADSPI + QUADSPI + 95 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + PRESCALER + Clock prescaler + 24 + 8 + + + PMM + Polling match mode + 23 + 1 + + + APMS + Automatic poll mode stop + 22 + 1 + + + TOIE + TimeOut interrupt enable + 20 + 1 + + + SMIE + Status match interrupt enable + 19 + 1 + + + FTIE + FIFO threshold interrupt enable + 18 + 1 + + + TCIE + Transfer complete interrupt enable + 17 + 1 + + + TEIE + Transfer error interrupt enable + 16 + 1 + + + FTHRES + IFO threshold level + 8 + 5 + + + FSEL + FSEL + 7 + 1 + + + DFM + DFM + 6 + 1 + + + SSHIFT + Sample shift + 4 + 1 + + + TCEN + Timeout counter enable + 3 + 1 + + + DMAEN + DMA enable + 2 + 1 + + + ABORT + Abort request + 1 + 1 + + + EN + Enable + 0 + 1 + + + + + DCR + DCR + device configuration register + 0x4 + 0x20 + read-write + 0x00000000 + + + FSIZE + FLASH memory size + 16 + 5 + + + CSHT + Chip select high time + 8 + 3 + + + CKMODE + Mode 0 / mode 3 + 0 + 1 + + + + + SR + SR + status register + 0x8 + 0x20 + read-only + 0x00000000 + + + FLEVEL + FIFO level + 8 + 5 + + + BUSY + Busy + 5 + 1 + + + TOF + Timeout flag + 4 + 1 + + + SMF + Status match flag + 3 + 1 + + + FTF + FIFO threshold flag + 2 + 1 + + + TCF + Transfer complete flag + 1 + 1 + + + TEF + Transfer error flag + 0 + 1 + + + + + FCR + FCR + flag clear register + 0xC + 0x20 + read-write + 0x00000000 + + + CTOF + Clear timeout flag + 4 + 1 + + + CSMF + Clear status match flag + 3 + 1 + + + CTCF + Clear transfer complete flag + 1 + 1 + + + CTEF + Clear transfer error flag + 0 + 1 + + + + + DLR + DLR + data length register + 0x10 + 0x20 + read-write + 0x00000000 + + + DL + Data length + 0 + 32 + + + + + CCR + CCR + communication configuration register + 0x14 + 0x20 + read-write + 0x00000000 + + + DDRM + Double data rate mode + 31 + 1 + + + SIOO + Send instruction only once mode + 28 + 1 + + + FMODE + Functional mode + 26 + 2 + + + DMODE + Data mode + 24 + 2 + + + DCYC + Number of dummy cycles + 18 + 5 + + + ABSIZE + Alternate bytes size + 16 + 2 + + + ABMODE + Alternate bytes mode + 14 + 2 + + + ADSIZE + Address size + 12 + 2 + + + ADMODE + Address mode + 10 + 2 + + + IMODE + Instruction mode + 8 + 2 + + + INSTRUCTION + Instruction + 0 + 8 + + + + + AR + AR + address register + 0x18 + 0x20 + read-write + 0x00000000 + + + ADDRESS + Address + 0 + 32 + + + + + ABR + ABR + ABR + 0x1C + 0x20 + read-write + 0x00000000 + + + ALTERNATE + ALTERNATE + 0 + 32 + + + + + DR + DR + data register + 0x20 + 0x20 + read-write + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + PSMKR + PSMKR + polling status mask register + 0x24 + 0x20 + read-write + 0x00000000 + + + MASK + Status mask + 0 + 32 + + + + + PSMAR + PSMAR + polling status match register + 0x28 + 0x20 + read-write + 0x00000000 + + + MATCH + Status match + 0 + 32 + + + + + PIR + PIR + polling interval register + 0x2C + 0x20 + read-write + 0x00000000 + + + INTERVAL + Polling interval + 0 + 16 + + + + + LPTR + LPTR + low-power timeout register + 0x30 + 0x20 + read-write + 0x00000000 + + + TIMEOUT + Timeout period + 0 + 16 + + + + + + + DAC1 + Digital-to-analog converter + DAC + 0x50000800 + + 0x0 + 0x400 + registers + + + + DAC_CR + DAC_CR + DAC control register + 0x0 + 0x20 + read-write + 0x00000000 + + + EN1 + DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1. + 0 + 1 + + + TEN1 + DAC channel1 trigger enable + 1 + 1 + + + TSEL1 + DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled). + 2 + 4 + + + WAVE1 + DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled). + 6 + 2 + + + MAMP1 + DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 + 8 + 4 + + + DMAEN1 + DAC channel1 DMA enable This bit is set and cleared by software. + 12 + 1 + + + DMAUDRIE1 + DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software. + 13 + 1 + + + CEN1 + DAC Channel 1 calibration enable This bit is set and cleared by software to enable/disable DAC channel 1 calibration, it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored. + 14 + 1 + + + EN2 + DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2. + 16 + 1 + + + TEN2 + DAC channel2 trigger enable + 17 + 1 + + + TSEL2 + DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled). + 18 + 4 + + + WAVE2 + DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled) + 22 + 2 + + + MAMP2 + DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 + 24 + 4 + + + DMAEN2 + DAC channel2 DMA enable This bit is set and cleared by software. + 28 + 1 + + + DMAUDRIE2 + DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software. + 29 + 1 + + + CEN2 + DAC Channel 2 calibration enable This bit is set and cleared by software to enable/disable DAC channel 2 calibration, it can be written only if bit EN2=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored. + 30 + 1 + + + + + DAC_SWTRGR + DAC_SWTRGR + DAC software trigger register + 0x4 + 0x20 + write-only + 0x00000000 + + + SWTRIG1 + DAC channel1 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR1 register value has been loaded into the DAC_DOR1 register. + 0 + 1 + + + SWTRIG2 + DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2 register value has been loaded into the DAC_DOR2 register. + 1 + 1 + + + SWTRIGB1 + DAC channel1 software trigger B + 16 + 1 + + + SWTRIGB2 + DAC channel2 software trigger B + 17 + 1 + + + + + DAC_DHR12R1 + DAC_DHR12R1 + DAC channel1 12-bit right-aligned data holding register + 0x8 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. + 0 + 12 + + + DACC1DHRB + DAC channel1 12-bit right-aligned data B + 16 + 12 + + + + + DAC_DHR12L1 + DAC_DHR12L1 + DAC channel1 12-bit left aligned data holding register + 0xC + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. + 4 + 12 + + + DACC1DHRB + DAC channel1 12-bit left-aligned data B + 20 + 12 + + + + + DAC_DHR8R1 + DAC_DHR8R1 + DAC channel1 8-bit right aligned data holding register + 0x10 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1. + 0 + 8 + + + DACC1DHRB + DAC channel1 8-bit right-aligned data + 8 + 8 + + + + + DAC_DHR12R2 + DAC_DHR12R2 + DAC channel2 12-bit right aligned data holding register + 0x14 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. + 0 + 12 + + + DACC2DHRB + DAC channel2 12-bit right-aligned data + 16 + 12 + + + + + DAC_DHR12L2 + DAC_DHR12L2 + DAC channel2 12-bit left aligned data holding register + 0x18 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2. + 4 + 12 + + + DACC2DHRB + DAC channel2 12-bit left-aligned data B + 20 + 12 + + + + + DAC_DHR8R2 + DAC_DHR8R2 + DAC channel2 8-bit right-aligned data holding register + 0x1C + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2. + 0 + 8 + + + DACC2DHRB + DAC channel2 8-bit right-aligned data + 8 + 8 + + + + + DAC_DHR12RD + DAC_DHR12RD + Dual DAC 12-bit right-aligned data holding register + 0x20 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. + 0 + 12 + + + DACC2DHR + DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. + 16 + 12 + + + + + DAC_DHR12LD + DAC_DHR12LD + DUAL DAC 12-bit left aligned data holding register + 0x24 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. + 4 + 12 + + + DACC2DHR + DAC channel2 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. + 20 + 12 + + + + + DAC_DHR8RD + DAC_DHR8RD + DUAL DAC 8-bit right aligned data holding register + 0x28 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1. + 0 + 8 + + + DACC2DHR + DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2. + 8 + 8 + + + + + DAC_DOR1 + DAC_DOR1 + DAC channel1 data output register + 0x2C + 0x20 + read-only + 0x00000000 + + + DACC1DOR + DAC channel1 data output These bits are read-only, they contain data output for DAC channel1. + 0 + 12 + + + DACC1DORB + DAC channel1 data output + 16 + 12 + + + + + DAC_DOR2 + DAC_DOR2 + DAC channel2 data output register + 0x30 + 0x20 + read-only + 0x00000000 + + + DACC2DOR + DAC channel2 data output These bits are read-only, they contain data output for DAC channel2. + 0 + 12 + + + DACC2DORB + DAC channel2 data output + 16 + 12 + + + + + DAC_SR + DAC_SR + DAC status register + 0x34 + 0x20 + 0x00000000 + + + DAC1RDY + DAC channel1 ready status bit + 11 + 1 + read-write + + + DORSTAT1 + DAC channel1 output register status bit + 12 + 1 + read-write + + + DMAUDR1 + DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). + 13 + 1 + read-write + + + CAL_FLAG1 + DAC Channel 1 calibration offset status This bit is set and cleared by hardware + 14 + 1 + read-only + + + BWST1 + DAC Channel 1 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete. (It takes about 3LSI periods of synchronization). + 15 + 1 + read-only + + + DAC2RDY + DAC channel 2 ready status bit + 27 + 1 + read-write + + + DORSTAT2 + DAC channel 2 output register status bit + 28 + 1 + read-write + + + DMAUDR2 + DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). + 29 + 1 + read-write + + + CAL_FLAG2 + DAC Channel 2 calibration offset status This bit is set and cleared by hardware + 30 + 1 + read-only + + + BWST2 + DAC Channel 2 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR2, It is cleared by hardware when the write operation of DAC_SHSR2 is complete. (It takes about 3 LSI periods of synchronization). + 31 + 1 + read-only + + + + + DAC_CCR + DAC_CCR + DAC calibration control register + 0x38 + 0x20 + read-write + 0x00000000 + + + OTRIM1 + DAC Channel 1 offset trimming value + 0 + 5 + + + OTRIM2 + DAC Channel 2 offset trimming value + 16 + 5 + + + + + DAC_MCR + DAC_MCR + DAC mode control register + 0x3C + 0x20 + read-write + 0x00000000 + + + MODE1 + DAC Channel 1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1=0 and bit CEN1 =0 in the DAC_CR register). If EN1=1 or CEN1 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 1 mode: DAC Channel 1 in normal Mode DAC Channel 1 in sample &amp; hold mode + 0 + 3 + + + DMADOUBLE1 + DAC Channel1 DMA double data mode + 8 + 1 + + + SINFORMAT1 + Enable signed format for DAC channel1 + 9 + 1 + + + HFSEL + High frequency interface mode selection + 14 + 2 + + + MODE2 + DAC Channel 2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 2 mode: DAC Channel 2 in normal Mode DAC Channel 2 in sample &amp; hold mode + 16 + 3 + + + DMADOUBLE2 + DAC Channel2 DMA double data mode + 24 + 1 + + + SINFORMAT2 + Enable signed format for DAC channel2 + 25 + 1 + + + + + DAC_SHSR1 + DAC_SHSR1 + DAC Sample and Hold sample time register 1 + 0x40 + 0x20 + read-write + 0x00000000 + + + TSAMPLE1 + DAC Channel 1 sample Time (only valid in sample &amp; hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored. + 0 + 10 + + + + + DAC_SHSR2 + DAC_SHSR2 + DAC Sample and Hold sample time register 2 + 0x44 + 0x20 + read-write + 0x00000000 + + + TSAMPLE2 + DAC Channel 2 sample Time (only valid in sample &amp; hold mode) These bits can be written when the DAC channel2 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, if BWSTx=1, the write operation is ignored. + 0 + 10 + + + + + DAC_SHHR + DAC_SHHR + DAC Sample and Hold hold time register + 0x48 + 0x20 + read-write + 0x00010001 + + + THOLD1 + DAC Channel 1 hold Time (only valid in sample &amp; hold mode) Hold time= (THOLD[9:0]) x T LSI + 0 + 10 + + + THOLD2 + DAC Channel 2 hold time (only valid in sample &amp; hold mode). Hold time= (THOLD[9:0]) x T LSI + 16 + 10 + + + + + DAC_SHRR + DAC_SHRR + DAC Sample and Hold refresh time register + 0x4C + 0x20 + read-write + 0x00010001 + + + TREFRESH1 + DAC Channel 1 refresh Time (only valid in sample &amp; hold mode) Refresh time= (TREFRESH[7:0]) x T LSI + 0 + 8 + + + TREFRESH2 + DAC Channel 2 refresh Time (only valid in sample &amp; hold mode) Refresh time= (TREFRESH[7:0]) x T LSI + 16 + 8 + + + + + DAC_STR1 + DAC_STR1 + Sawtooth register + 0x58 + 0x20 + read-write + 0x00000000 + + + STRSTDATA1 + DAC Channel 1 Sawtooth reset value + 0 + 12 + + + STDIR1 + DAC Channel1 Sawtooth direction setting + 12 + 1 + + + STINCDATA1 + DAC CH1 Sawtooth increment value (12.4 bit format) + 16 + 16 + + + + + DAC_STR2 + DAC_STR2 + Sawtooth register + 0x5C + 0x20 + read-write + 0x00000000 + + + STRSTDATA2 + DAC Channel 2 Sawtooth reset value + 0 + 12 + + + STDIR2 + DAC Channel2 Sawtooth direction setting + 12 + 1 + + + STINCDATA2 + DAC CH2 Sawtooth increment value (12.4 bit format) + 16 + 16 + + + + + DAC_STMODR + DAC_STMODR + Sawtooth Mode register + 0x60 + 0x20 + read-write + 0x00000000 + + + STRSTTRIGSEL1 + DAC Channel 1 Sawtooth Reset trigger selection + 0 + 4 + + + STINCTRIGSEL1 + DAC Channel 1 Sawtooth Increment trigger selection + 8 + 4 + + + STRSTTRIGSEL2 + DAC Channel 1 Sawtooth Reset trigger selection + 16 + 4 + + + STINCTRIGSEL2 + DAC Channel 2 Sawtooth Increment trigger selection + 24 + 4 + + + + + + + DAC2 + 0x50000C00 + + + DAC3 + 0x50001000 + + + DAC4 + 0x50001400 + + + ADC1 + Analog-to-Digital Converter + ADC + 0x50000000 + + 0x0 + 0xD0 + registers + + + ADC1_2 + ADC1 and ADC2 global interrupt + 18 + + + + ISR + ISR + interrupt and status register + 0x0 + 0x20 + read-write + 0x00000000 + + + JQOVF + JQOVF + 10 + 1 + + + AWD3 + AWD3 + 9 + 1 + + + AWD2 + AWD2 + 8 + 1 + + + AWD1 + AWD1 + 7 + 1 + + + JEOS + JEOS + 6 + 1 + + + JEOC + JEOC + 5 + 1 + + + OVR + OVR + 4 + 1 + + + EOS + EOS + 3 + 1 + + + EOC + EOC + 2 + 1 + + + EOSMP + EOSMP + 1 + 1 + + + ADRDY + ADRDY + 0 + 1 + + + + + IER + IER + interrupt enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + JQOVFIE + JQOVFIE + 10 + 1 + + + AWD3IE + AWD3IE + 9 + 1 + + + AWD2IE + AWD2IE + 8 + 1 + + + AWD1IE + AWD1IE + 7 + 1 + + + JEOSIE + JEOSIE + 6 + 1 + + + JEOCIE + JEOCIE + 5 + 1 + + + OVRIE + OVRIE + 4 + 1 + + + EOSIE + EOSIE + 3 + 1 + + + EOCIE + EOCIE + 2 + 1 + + + EOSMPIE + EOSMPIE + 1 + 1 + + + ADRDYIE + ADRDYIE + 0 + 1 + + + + + CR + CR + control register + 0x8 + 0x20 + read-write + 0x20000000 + + + ADCAL + ADCAL + 31 + 1 + + + ADCALDIF + ADCALDIF + 30 + 1 + + + DEEPPWD + DEEPPWD + 29 + 1 + + + ADVREGEN + ADVREGEN + 28 + 1 + + + JADSTP + JADSTP + 5 + 1 + + + ADSTP + ADSTP + 4 + 1 + + + JADSTART + JADSTART + 3 + 1 + + + ADSTART + ADSTART + 2 + 1 + + + ADDIS + ADDIS + 1 + 1 + + + ADEN + ADEN + 0 + 1 + + + + + CFGR + CFGR + configuration register + 0xC + 0x20 + read-write + 0x80000000 + + + JQDIS + Injected Queue disable + 31 + 1 + + + AWD1CH + Analog watchdog 1 channel selection + 26 + 5 + + + JAUTO + JAUTO + 25 + 1 + + + JAWD1EN + JAWD1EN + 24 + 1 + + + AWD1EN + AWD1EN + 23 + 1 + + + AWD1SGL + AWD1SGL + 22 + 1 + + + JQM + JQM + 21 + 1 + + + JDISCEN + JDISCEN + 20 + 1 + + + DISCNUM + DISCNUM + 17 + 3 + + + DISCEN + DISCEN + 16 + 1 + + + ALIGN + ALIGN + 15 + 1 + + + AUTDLY + AUTDLY + 14 + 1 + + + CONT + CONT + 13 + 1 + + + OVRMOD + OVRMOD + 12 + 1 + + + EXTEN + EXTEN + 10 + 2 + + + EXTSEL + External trigger selection for regular group + 5 + 5 + + + RES + RES + 3 + 2 + + + DMACFG + DMACFG + 1 + 1 + + + DMAEN + DMAEN + 0 + 1 + + + + + CFGR2 + CFGR2 + configuration register + 0x10 + 0x20 + read-write + 0x00000000 + + + SMPTRIG + SMPTRIG + 27 + 1 + + + BULB + BULB + 26 + 1 + + + SWTRIG + SWTRIG + 25 + 1 + + + GCOMP + GCOMP + 16 + 1 + + + ROVSM + EXTEN + 10 + 1 + + + TROVS + Triggered Regular Oversampling + 9 + 1 + + + OVSS + ALIGN + 5 + 4 + + + OVSR + RES + 2 + 3 + + + JOVSE + DMACFG + 1 + 1 + + + ROVSE + DMAEN + 0 + 1 + + + + + SMPR1 + SMPR1 + sample time register 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + SMP9 + SMP9 + 27 + 3 + + + SMP8 + SMP8 + 24 + 3 + + + SMP7 + SMP7 + 21 + 3 + + + SMP6 + SMP6 + 18 + 3 + + + SMP5 + SMP5 + 15 + 3 + + + SMP4 + SMP4 + 12 + 3 + + + SMP3 + SMP3 + 9 + 3 + + + SMP2 + SMP2 + 6 + 3 + + + SMP1 + SMP1 + 3 + 3 + + + SMPPLUS + Addition of one clock cycle to the sampling time + 31 + 1 + + + SMP0 + SMP0 + 0 + 3 + + + + + SMPR2 + SMPR2 + sample time register 2 + 0x18 + 0x20 + read-write + 0x00000000 + + + SMP18 + SMP18 + 24 + 3 + + + SMP17 + SMP17 + 21 + 3 + + + SMP16 + SMP16 + 18 + 3 + + + SMP15 + SMP15 + 15 + 3 + + + SMP14 + SMP14 + 12 + 3 + + + SMP13 + SMP13 + 9 + 3 + + + SMP12 + SMP12 + 6 + 3 + + + SMP11 + SMP11 + 3 + 3 + + + SMP10 + SMP10 + 0 + 3 + + + + + TR1 + TR1 + watchdog threshold register 1 + 0x20 + 0x20 + read-write + 0x0FFF0000 + + + HT1 + HT1 + 16 + 12 + + + AWDFILT + AWDFILT + 12 + 3 + + + LT1 + LT1 + 0 + 12 + + + + + TR2 + TR2 + watchdog threshold register + 0x24 + 0x20 + read-write + 0x00FF0000 + + + HT2 + HT2 + 16 + 8 + + + LT2 + LT2 + 0 + 8 + + + + + TR3 + TR3 + watchdog threshold register 3 + 0x28 + 0x20 + read-write + 0x00FF0000 + + + HT3 + HT3 + 16 + 8 + + + LT3 + LT3 + 0 + 8 + + + + + SQR1 + SQR1 + regular sequence register 1 + 0x30 + 0x20 + read-write + 0x00000000 + + + SQ4 + SQ4 + 24 + 5 + + + SQ3 + SQ3 + 18 + 5 + + + SQ2 + SQ2 + 12 + 5 + + + SQ1 + SQ1 + 6 + 5 + + + L + Regular channel sequence length + 0 + 4 + + + + + SQR2 + SQR2 + regular sequence register 2 + 0x34 + 0x20 + read-write + 0x00000000 + + + SQ9 + SQ9 + 24 + 5 + + + SQ8 + SQ8 + 18 + 5 + + + SQ7 + SQ7 + 12 + 5 + + + SQ6 + SQ6 + 6 + 5 + + + SQ5 + SQ5 + 0 + 5 + + + + + SQR3 + SQR3 + regular sequence register 3 + 0x38 + 0x20 + read-write + 0x00000000 + + + SQ14 + SQ14 + 24 + 5 + + + SQ13 + SQ13 + 18 + 5 + + + SQ12 + SQ12 + 12 + 5 + + + SQ11 + SQ11 + 6 + 5 + + + SQ10 + SQ10 + 0 + 5 + + + + + SQR4 + SQR4 + regular sequence register 4 + 0x3C + 0x20 + read-write + 0x00000000 + + + SQ16 + SQ16 + 6 + 5 + + + SQ15 + SQ15 + 0 + 5 + + + + + DR + DR + regular Data Register + 0x40 + 0x20 + read-only + 0x00000000 + + + RDATA + Regular Data converted + 0 + 16 + + + + + JSQR + JSQR + injected sequence register + 0x4C + 0x20 + read-write + 0x00000000 + + + JSQ4 + JSQ4 + 27 + 5 + + + JSQ3 + JSQ3 + 21 + 5 + + + JSQ2 + JSQ2 + 15 + 5 + + + JSQ1 + JSQ1 + 9 + 5 + + + JEXTEN + JEXTEN + 7 + 2 + + + JEXTSEL + JEXTSEL + 2 + 5 + + + JL + JL + 0 + 2 + + + + + OFR1 + OFR1 + offset register 1 + 0x60 + 0x20 + read-write + 0x00000000 + + + OFFSET1_EN + OFFSET1_EN + 31 + 1 + + + OFFSET1_CH + OFFSET1_CH + 26 + 5 + + + SATEN + SATEN + 25 + 1 + + + OFFSETPOS + OFFSETPOS + 24 + 1 + + + OFFSET1 + OFFSET1 + 0 + 12 + + + + + OFR2 + OFR2 + offset register 2 + 0x64 + 0x20 + read-write + 0x00000000 + + + OFFSET1_EN + OFFSET1_EN + 31 + 1 + + + OFFSET1_CH + OFFSET1_CH + 26 + 5 + + + SATEN + SATEN + 25 + 1 + + + OFFSETPOS + OFFSETPOS + 24 + 1 + + + OFFSET1 + OFFSET1 + 0 + 12 + + + + + OFR3 + OFR3 + offset register 3 + 0x68 + 0x20 + read-write + 0x00000000 + + + OFFSET1_EN + OFFSET1_EN + 31 + 1 + + + OFFSET1_CH + OFFSET1_CH + 26 + 5 + + + SATEN + SATEN + 25 + 1 + + + OFFSETPOS + OFFSETPOS + 24 + 1 + + + OFFSET1 + OFFSET1 + 0 + 12 + + + + + OFR4 + OFR4 + offset register 4 + 0x6C + 0x20 + read-write + 0x00000000 + + + OFFSET1_EN + OFFSET1_EN + 31 + 1 + + + OFFSET1_CH + OFFSET1_CH + 26 + 5 + + + SATEN + SATEN + 25 + 1 + + + OFFSETPOS + OFFSETPOS + 24 + 1 + + + OFFSET1 + OFFSET1 + 0 + 12 + + + + + JDR1 + JDR1 + injected data register 1 + 0x80 + 0x20 + read-only + 0x00000000 + + + JDATA1 + JDATA1 + 0 + 16 + + + + + JDR2 + JDR2 + injected data register 2 + 0x84 + 0x20 + read-only + 0x00000000 + + + JDATA2 + JDATA2 + 0 + 16 + + + + + JDR3 + JDR3 + injected data register 3 + 0x88 + 0x20 + read-only + 0x00000000 + + + JDATA3 + JDATA3 + 0 + 16 + + + + + JDR4 + JDR4 + injected data register 4 + 0x8C + 0x20 + read-only + 0x00000000 + + + JDATA4 + JDATA4 + 0 + 16 + + + + + AWD2CR + AWD2CR + Analog Watchdog 2 Configuration Register + 0xA0 + 0x20 + read-write + 0x00000000 + + + AWD2CH + AWD2CH + 0 + 19 + + + + + AWD3CR + AWD3CR + Analog Watchdog 3 Configuration Register + 0xA4 + 0x20 + read-write + 0x00000000 + + + AWD3CH + AWD3CH + 0 + 19 + + + + + DIFSEL + DIFSEL + Differential Mode Selection Register 2 + 0xB0 + 0x20 + 0x00000000 + + + DIFSEL_0 + Differential mode for channels 0 + 0 + 1 + read-only + + + DIFSEL_1_18 + Differential mode for channels 15 to 1 + 1 + 18 + read-write + + + + + CALFACT + CALFACT + Calibration Factors + 0xB4 + 0x20 + read-write + 0x00000000 + + + CALFACT_D + CALFACT_D + 16 + 7 + + + CALFACT_S + CALFACT_S + 0 + 7 + + + + + GCOMP + GCOMP + Gain compensation Register + 0xC0 + 0x20 + read-write + 0x00000000 + + + GCOMPCOEFF + GCOMPCOEFF + 0 + 14 + + + + + + + ADC2 + 0x50000100 + + + ADC3 + Analog-to-Digital Converter + ADC + 0x50000400 + + 0x0 + 0xD0 + registers + + + ADC3 + ADC3 + 47 + + + + ISR + ISR + interrupt and status register + 0x0 + 0x20 + read-write + 0x00000000 + + + JQOVF + JQOVF + 10 + 1 + + + AWD3 + AWD3 + 9 + 1 + + + AWD2 + AWD2 + 8 + 1 + + + AWD1 + AWD1 + 7 + 1 + + + JEOS + JEOS + 6 + 1 + + + JEOC + JEOC + 5 + 1 + + + OVR + OVR + 4 + 1 + + + EOS + EOS + 3 + 1 + + + EOC + EOC + 2 + 1 + + + EOSMP + EOSMP + 1 + 1 + + + ADRDY + ADRDY + 0 + 1 + + + + + IER + IER + interrupt enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + JQOVFIE + JQOVFIE + 10 + 1 + + + AWD3IE + AWD3IE + 9 + 1 + + + AWD2IE + AWD2IE + 8 + 1 + + + AWD1IE + AWD1IE + 7 + 1 + + + JEOSIE + JEOSIE + 6 + 1 + + + JEOCIE + JEOCIE + 5 + 1 + + + OVRIE + OVRIE + 4 + 1 + + + EOSIE + EOSIE + 3 + 1 + + + EOCIE + EOCIE + 2 + 1 + + + EOSMPIE + EOSMPIE + 1 + 1 + + + ADRDYIE + ADRDYIE + 0 + 1 + + + + + CR + CR + control register + 0x8 + 0x20 + read-write + 0x20002000 + + + ADCAL + ADCAL + 31 + 1 + + + ADCALDIF + ADCALDIF + 30 + 1 + + + DEEPPWD + DEEPPWD + 29 + 1 + + + ADVREGEN + ADVREGEN + 28 + 1 + + + JADSTP + JADSTP + 5 + 1 + + + ADSTP + ADSTP + 4 + 1 + + + JADSTART + JADSTART + 3 + 1 + + + ADSTART + ADSTART + 2 + 1 + + + ADDIS + ADDIS + 1 + 1 + + + ADEN + ADEN + 0 + 1 + + + + + CFGR + CFGR + configuration register + 0xC + 0x20 + read-write + 0x80000000 + + + JQDIS + Injected Queue disable + 31 + 1 + + + AWDCH1CH + AWDCH1CH + 26 + 5 + + + JAUTO + JAUTO + 25 + 1 + + + JAWD1EN + JAWD1EN + 24 + 1 + + + AWD1EN + AWD1EN + 23 + 1 + + + AWD1SGL + AWD1SGL + 22 + 1 + + + JQM + JQM + 21 + 1 + + + JDISCEN + JDISCEN + 20 + 1 + + + DISCNUM + DISCNUM + 17 + 3 + + + DISCEN + DISCEN + 16 + 1 + + + ALIGN + ALIGN + 15 + 1 + + + AUTDLY + AUTDLY + 14 + 1 + + + CONT + CONT + 13 + 1 + + + OVRMOD + OVRMOD + 12 + 1 + + + EXTEN + EXTEN + 10 + 2 + + + EXTSEL + EXTSEL + 5 + 5 + + + RES + RES + 3 + 2 + + + DMACFG + DMACFG + 1 + 1 + + + DMAEN + DMAEN + 0 + 1 + + + + + CFGR2 + CFGR2 + configuration register + 0x10 + 0x20 + read-write + 0x00000000 + + + SMPTRIG + SMPTRIG + 27 + 1 + + + BULB + BULB + 26 + 1 + + + SWTRIG + SWTRIG + 25 + 1 + + + GCOMP + GCOMP + 16 + 1 + + + ROVSM + EXTEN + 10 + 1 + + + TROVS + Triggered Regular Oversampling + 9 + 1 + + + OVSS + ALIGN + 5 + 4 + + + OVSR + RES + 2 + 3 + + + JOVSE + DMACFG + 1 + 1 + + + ROVSE + DMAEN + 0 + 1 + + + + + SMPR1 + SMPR1 + sample time register 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + SMP9 + SMP9 + 27 + 3 + + + SMP8 + SMP8 + 24 + 3 + + + SMP7 + SMP7 + 21 + 3 + + + SMP6 + SMP6 + 18 + 3 + + + SMP5 + SMP5 + 15 + 3 + + + SMP4 + SMP4 + 12 + 3 + + + SMP3 + SMP3 + 9 + 3 + + + SMP2 + SMP2 + 6 + 3 + + + SMP1 + SMP1 + 3 + 3 + + + SMPPLUS + Addition of one clock cycle to the sampling time + 31 + 1 + + + SMP0 + SMP0 + 0 + 3 + + + + + SMPR2 + SMPR2 + sample time register 2 + 0x18 + 0x20 + read-write + 0x00000000 + + + SMP18 + SMP18 + 24 + 3 + + + SMP17 + SMP17 + 21 + 3 + + + SMP16 + SMP16 + 18 + 3 + + + SMP15 + SMP15 + 15 + 3 + + + SMP14 + SMP14 + 12 + 3 + + + SMP13 + SMP13 + 9 + 3 + + + SMP12 + SMP12 + 6 + 3 + + + SMP11 + SMP11 + 3 + 3 + + + SMP10 + SMP10 + 0 + 3 + + + + + TR1 + TR1 + watchdog threshold register 1 + 0x20 + 0x20 + read-write + 0x0FFF0000 + + + HT1 + HT1 + 16 + 12 + + + AWDFILT + AWDFILT + 12 + 3 + + + LT1 + LT1 + 0 + 12 + + + + + TR2 + TR2 + watchdog threshold register + 0x24 + 0x20 + read-write + 0x00FF0000 + + + HT2 + HT2 + 16 + 8 + + + LT2 + LT2 + 0 + 8 + + + + + TR3 + TR3 + watchdog threshold register 3 + 0x28 + 0x20 + read-write + 0x00FF0000 + + + HT3 + HT3 + 16 + 8 + + + LT3 + LT3 + 0 + 8 + + + + + SQR1 + SQR1 + regular sequence register 1 + 0x30 + 0x20 + read-write + 0x00000000 + + + SQ4 + SQ4 + 24 + 5 + + + SQ3 + SQ3 + 18 + 5 + + + SQ2 + SQ2 + 12 + 5 + + + SQ1 + SQ1 + 6 + 5 + + + L + Regular channel sequence length + 0 + 4 + + + + + SQR2 + SQR2 + regular sequence register 2 + 0x34 + 0x20 + read-write + 0x00000000 + + + SQ9 + SQ9 + 24 + 5 + + + SQ8 + SQ8 + 18 + 5 + + + SQ7 + SQ7 + 12 + 5 + + + SQ6 + SQ6 + 6 + 5 + + + SQ5 + SQ5 + 0 + 5 + + + + + SQR3 + SQR3 + regular sequence register 3 + 0x38 + 0x20 + read-write + 0x00000000 + + + SQ14 + SQ14 + 24 + 5 + + + SQ13 + SQ13 + 18 + 5 + + + SQ12 + SQ12 + 12 + 5 + + + SQ11 + SQ11 + 6 + 5 + + + SQ10 + SQ10 + 0 + 5 + + + + + SQR4 + SQR4 + regular sequence register 4 + 0x3C + 0x20 + read-write + 0x00000000 + + + SQ16 + SQ16 + 6 + 5 + + + SQ15 + SQ15 + 0 + 5 + + + + + DR + DR + regular Data Register + 0x40 + 0x20 + read-only + 0x00000000 + + + RDATA + Regular Data converted + 0 + 16 + + + + + JSQR + JSQR + injected sequence register + 0x4C + 0x20 + read-write + 0x00000000 + + + JSQ4 + JSQ4 + 27 + 5 + + + JSQ3 + JSQ3 + 21 + 5 + + + JSQ2 + JSQ2 + 15 + 5 + + + JSQ1 + JSQ1 + 9 + 5 + + + JEXTEN + JEXTEN + 7 + 2 + + + JEXTSEL + JEXTSEL + 2 + 5 + + + JL + JL + 0 + 2 + + + + + OFR1 + OFR1 + offset register 1 + 0x60 + 0x20 + read-write + 0x00000000 + + + OFFSET1_EN + OFFSET1_EN + 31 + 1 + + + OFFSET1_CH + OFFSET1_CH + 26 + 5 + + + SATEN + SATEN + 25 + 1 + + + OFFSETPOS + OFFSETPOS + 24 + 1 + + + OFFSET1 + OFFSET1 + 0 + 12 + + + + + OFR2 + OFR2 + offset register 2 + 0x64 + 0x20 + read-write + 0x00000000 + + + OFFSET1_EN + OFFSET1_EN + 31 + 1 + + + OFFSET1_CH + OFFSET1_CH + 26 + 5 + + + SATEN + SATEN + 25 + 1 + + + OFFSETPOS + OFFSETPOS + 24 + 1 + + + OFFSET1 + OFFSET1 + 0 + 12 + + + + + OFR3 + OFR3 + offset register 3 + 0x68 + 0x20 + read-write + 0x00000000 + + + OFFSET1_EN + OFFSET1_EN + 31 + 1 + + + OFFSET1_CH + OFFSET1_CH + 26 + 5 + + + SATEN + SATEN + 25 + 1 + + + OFFSETPOS + OFFSETPOS + 24 + 1 + + + OFFSET1 + OFFSET1 + 0 + 12 + + + + + OFR4 + OFR4 + offset register 4 + 0x6C + 0x20 + read-write + 0x00000000 + + + OFFSET1_EN + OFFSET1_EN + 31 + 1 + + + OFFSET1_CH + OFFSET1_CH + 26 + 5 + + + SATEN + SATEN + 25 + 1 + + + OFFSETPOS + OFFSETPOS + 24 + 1 + + + OFFSET1 + OFFSET1 + 0 + 12 + + + + + JDR1 + JDR1 + injected data register 1 + 0x80 + 0x20 + read-only + 0x00000000 + + + JDATA1 + JDATA1 + 0 + 16 + + + + + JDR2 + JDR2 + injected data register 2 + 0x84 + 0x20 + read-only + 0x00000000 + + + JDATA2 + JDATA2 + 0 + 16 + + + + + JDR3 + JDR3 + injected data register 3 + 0x88 + 0x20 + read-only + 0x00000000 + + + JDATA3 + JDATA3 + 0 + 16 + + + + + JDR4 + JDR4 + injected data register 4 + 0x8C + 0x20 + read-only + 0x00000000 + + + JDATA4 + JDATA4 + 0 + 16 + + + + + AWD2CR + AWD2CR + Analog Watchdog 2 Configuration Register + 0xA0 + 0x20 + read-write + 0x00000000 + + + AWD2CH + AWD2CH + 0 + 19 + + + + + AWD3CR + AWD3CR + Analog Watchdog 3 Configuration Register + 0xA4 + 0x20 + read-write + 0x00000000 + + + AWD3CH + AWD3CH + 0 + 19 + + + + + DIFSEL + DIFSEL + Differential Mode Selection Register 2 + 0xB0 + 0x20 + 0x00000000 + + + DIFSEL_0 + Differential mode for channels 0 + 0 + 1 + read-only + + + DIFSEL_1_18 + Differential mode for channels 15 to 1 + 1 + 18 + read-write + + + + + CALFACT + CALFACT + Calibration Factors + 0xB4 + 0x20 + read-write + 0x00000000 + + + CALFACT_D + CALFACT_D + 16 + 7 + + + CALFACT_S + CALFACT_S + 0 + 7 + + + + + GCOMP + GCOMP + Gain compensation Register + 0xC0 + 0x20 + read-write + 0x00000000 + + + GCOMPCOEFF + GCOMPCOEFF + 0 + 14 + + + + + + + ADC4 + 0x50000500 + + ADC4 + ADC4 + 61 + + + + ADC5 + 0x50000600 + + ADC5 + ADC5 + 62 + + + + ADC12_Common + Analog-to-Digital Converter + ADC + 0x50000300 + + 0x0 + 0x11 + registers + + + + CSR + CSR + ADC Common status register + 0x0 + 0x20 + read-only + 0x00000000 + + + ADDRDY_MST + ADDRDY_MST + 0 + 1 + + + EOSMP_MST + EOSMP_MST + 1 + 1 + + + EOC_MST + EOC_MST + 2 + 1 + + + EOS_MST + EOS_MST + 3 + 1 + + + OVR_MST + OVR_MST + 4 + 1 + + + JEOC_MST + JEOC_MST + 5 + 1 + + + JEOS_MST + JEOS_MST + 6 + 1 + + + AWD1_MST + AWD1_MST + 7 + 1 + + + AWD2_MST + AWD2_MST + 8 + 1 + + + AWD3_MST + AWD3_MST + 9 + 1 + + + JQOVF_MST + JQOVF_MST + 10 + 1 + + + ADRDY_SLV + ADRDY_SLV + 16 + 1 + + + EOSMP_SLV + EOSMP_SLV + 17 + 1 + + + EOC_SLV + End of regular conversion of the slave ADC + 18 + 1 + + + EOS_SLV + End of regular sequence flag of the slave ADC + 19 + 1 + + + OVR_SLV + Overrun flag of the slave ADC + 20 + 1 + + + JEOC_SLV + End of injected conversion flag of the slave ADC + 21 + 1 + + + JEOS_SLV + End of injected sequence flag of the slave ADC + 22 + 1 + + + AWD1_SLV + Analog watchdog 1 flag of the slave ADC + 23 + 1 + + + AWD2_SLV + Analog watchdog 2 flag of the slave ADC + 24 + 1 + + + AWD3_SLV + Analog watchdog 3 flag of the slave ADC + 25 + 1 + + + JQOVF_SLV + Injected Context Queue Overflow flag of the slave ADC + 26 + 1 + + + + + CCR + CCR + ADC common control register + 0x8 + 0x20 + read-write + 0x00000000 + + + DUAL + Dual ADC mode selection + 0 + 5 + + + DELAY + Delay between 2 sampling phases + 8 + 4 + + + DMACFG + DMA configuration (for multi-ADC mode) + 13 + 1 + + + MDMA + Direct memory access mode for multi ADC mode + 14 + 2 + + + CKMODE + ADC clock mode + 16 + 2 + + + VREFEN + VREFINT enable + 22 + 1 + + + VSENSESEL + VTS selection + 23 + 1 + + + VBATSEL + VBAT selection + 24 + 1 + + + PRESC + ADC prescaler + 18 + 4 + + + + + CDR + CDR + ADC common regular data register for dual and triple modes + 0xC + 0x20 + read-only + 0x00000000 + + + RDATA_SLV + Regular data of the slave ADC + 16 + 16 + + + RDATA_MST + Regular data of the master ADC + 0 + 16 + + + + + + + ADC345_Common + 0x50000700 + + + FMAC + Filter Math Accelerator + FMAC + 0x40021400 + + 0x0 + 0xC00 + registers + + + FMAC + FMAC + 101 + + + + X1BUFCFG + X1BUFCFG + FMAC X1 Buffer Configuration register + 0x0 + 0x20 + read-write + 0x00000000 + + + X1_BASE + X1_BASE + 0 + 8 + + + X1_BUF_SIZE + X1_BUF_SIZE + 8 + 8 + + + FULL_WM + FULL_WM + 24 + 2 + + + + + X2BUFCFG + X2BUFCFG + FMAC X2 Buffer Configuration register + 0x4 + 0x20 + read-write + 0x00000000 + + + X2_BASE + X1_BASE + 0 + 8 + + + X2_BUF_SIZE + X1_BUF_SIZE + 8 + 8 + + + + + YBUFCFG + YBUFCFG + FMAC Y Buffer Configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + Y_BASE + X1_BASE + 0 + 8 + + + Y_BUF_SIZE + X1_BUF_SIZE + 8 + 8 + + + EMPTY_WM + EMPTY_WM + 24 + 2 + + + + + PARAM + PARAM + FMAC Parameter register + 0xC + 0x20 + read-write + 0x00000000 + + + START + START + 31 + 1 + + + FUNC + FUNC + 24 + 7 + + + R + R + 16 + 8 + + + Q + Q + 8 + 8 + + + P + P + 0 + 8 + + + + + CR + CR + FMAC Control register + 0x10 + 0x20 + read-write + 0x00000000 + + + RESET + RESET + 16 + 1 + + + CLIPEN + CLIPEN + 15 + 1 + + + DMAWEN + DMAWEN + 9 + 1 + + + DMAREN + DMAREN + 8 + 1 + + + SATIEN + SATIEN + 4 + 1 + + + UNFLIEN + UNFLIEN + 3 + 1 + + + OVFLIEN + OVFLIEN + 2 + 1 + + + WIEN + WIEN + 1 + 1 + + + RIEN + RIEN + 0 + 1 + + + + + SR + SR + FMAC Status register + 0x14 + 0x20 + read-only + 0x00000000 + + + YEMPTY + YEMPTY + 0 + 1 + + + X1FULL + X1FULL + 1 + 1 + + + OVFL + OVFL + 8 + 1 + + + UNFL + UNFL + 9 + 1 + + + SAT + SAT + 10 + 1 + + + + + WDATA + WDATA + FMAC Write Data register + 0x18 + 0x20 + write-only + 0x00000000 + + + WDATA + WDATA + 0 + 16 + + + + + RDATA + RDATA + FMAC Read Data register + 0x1C + 0x20 + read-only + 0x00000000 + + + RDATA + RDATA + 0 + 16 + + + + + + + CORDIC + CORDIC Co-processor + CORDIC + 0x40020C00 + + 0x0 + 0x400 + registers + + + Cordic + Cordic + 100 + + + + CSR + CSR + CORDIC Control Status register + 0x0 + 0x20 + read-write + 0x00000000 + + + FUNC + FUNC + 0 + 4 + + + PRECISION + PRECISION + 4 + 4 + + + SCALE + SCALE + 8 + 3 + + + IEN + IEN + 16 + 1 + + + DMAREN + DMAREN + 17 + 1 + + + DMAWEN + DMAWEN + 18 + 1 + + + NRES + NRES + 19 + 1 + + + NARGS + NARGS + 20 + 1 + + + RESSIZE + RESSIZE + 21 + 1 + + + ARGSIZE + ARGSIZE + 22 + 1 + + + RRDY + RRDY + 31 + 1 + + + + + WDATA + WDATA + FMAC Write Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + ARG + ARG + 0 + 32 + + + + + RDATA + RDATA + FMAC Read Data register + 0x8 + 0x20 + read-only + 0x00000000 + + + RES + RES + 0 + 32 + + + + + + + SAI + Serial audio interface + SAI + 0x40015400 + + 0x0 + 0x400 + registers + + + SAI + SAI + 76 + + + + BCR1 + BCR1 + BConfiguration register 1 + 0x24 + 0x20 + read-write + 0x00000040 + + + MCKEN + MCKEN + 27 + 1 + + + OSR + OSR + 26 + 1 + + + MCJDIV + Master clock divider + 20 + 6 + + + NODIV + No divider + 19 + 1 + + + DMAEN + DMA enable + 17 + 1 + + + SAIBEN + Audio block B enable + 16 + 1 + + + OutDri + Output drive + 13 + 1 + + + MONO + Mono mode + 12 + 1 + + + SYNCEN + Synchronization enable + 10 + 2 + + + CKSTR + Clock strobing edge + 9 + 1 + + + LSBFIRST + Least significant bit first + 8 + 1 + + + DS + Data size + 5 + 3 + + + PRTCFG + Protocol configuration + 2 + 2 + + + MODE + Audio block mode + 0 + 2 + + + + + BCR2 + BCR2 + BConfiguration register 2 + 0x28 + 0x20 + read-write + 0x00000000 + + + COMP + Companding mode + 14 + 2 + + + CPL + Complement bit + 13 + 1 + + + MUTECN + Mute counter + 7 + 6 + + + MUTEVAL + Mute value + 6 + 1 + + + MUTE + Mute + 5 + 1 + + + TRIS + Tristate management on data line + 4 + 1 + + + FFLUS + FIFO flush + 3 + 1 + + + FTH + FIFO threshold + 0 + 3 + + + + + BFRCR + BFRCR + BFRCR + 0x2C + 0x20 + read-write + 0x00000007 + + + FSOFF + Frame synchronization offset + 18 + 1 + + + FSPOL + Frame synchronization polarity + 17 + 1 + + + FSDEF + Frame synchronization definition + 16 + 1 + + + FSALL + Frame synchronization active level length + 8 + 7 + + + FRL + Frame length + 0 + 8 + + + + + BSLOTR + BSLOTR + BSlot register + 0x30 + 0x20 + read-write + 0x00000000 + + + SLOTEN + Slot enable + 16 + 16 + + + NBSLOT + Number of slots in an audio frame + 8 + 4 + + + SLOTSZ + Slot size + 6 + 2 + + + FBOFF + First bit offset + 0 + 5 + + + + + BIM + BIM + BInterrupt mask register2 + 0x34 + 0x20 + read-write + 0x00000000 + + + LFSDETIE + Late frame synchronization detection interrupt enable + 6 + 1 + + + AFSDETIE + Anticipated frame synchronization detection interrupt enable + 5 + 1 + + + CNRDYIE + Codec not ready interrupt enable + 4 + 1 + + + FREQIE + FIFO request interrupt enable + 3 + 1 + + + WCKCFG + Wrong clock configuration interrupt enable + 2 + 1 + + + MUTEDET + Mute detection interrupt enable + 1 + 1 + + + OVRUDRIE + Overrun/underrun interrupt enable + 0 + 1 + + + + + BSR + BSR + BStatus register + 0x38 + 0x20 + read-only + 0x00000000 + + + FLVL + FIFO level threshold + 16 + 3 + + + LFSDET + Late frame synchronization detection + 6 + 1 + + + AFSDET + Anticipated frame synchronization detection + 5 + 1 + + + CNRDY + Codec not ready + 4 + 1 + + + FREQ + FIFO request + 3 + 1 + + + WCKCFG + Wrong clock configuration flag + 2 + 1 + + + MUTEDET + Mute detection + 1 + 1 + + + OVRUDR + Overrun / underrun + 0 + 1 + + + + + BCLRFR + BCLRFR + BClear flag register + 0x3C + 0x20 + write-only + 0x00000000 + + + LFSDET + Clear late frame synchronization detection flag + 6 + 1 + + + CAFSDET + Clear anticipated frame synchronization detection flag + 5 + 1 + + + CNRDY + Clear codec not ready flag + 4 + 1 + + + WCKCFG + Clear wrong clock configuration flag + 2 + 1 + + + MUTEDET + Mute detection flag + 1 + 1 + + + OVRUDR + Clear overrun / underrun + 0 + 1 + + + + + BDR + BDR + BData register + 0x40 + 0x20 + read-write + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + ACR1 + ACR1 + AConfiguration register 1 + 0x4 + 0x20 + read-write + 0x00000040 + + + MCKEN + MCKEN + 27 + 1 + + + OSR + OSR + 26 + 1 + + + MCJDIV + Master clock divider + 20 + 6 + + + NODIV + No divider + 19 + 1 + + + DMAEN + DMA enable + 17 + 1 + + + SAIAEN + Audio block A enable + 16 + 1 + + + OutDri + Output drive + 13 + 1 + + + MONO + Mono mode + 12 + 1 + + + SYNCEN + Synchronization enable + 10 + 2 + + + CKSTR + Clock strobing edge + 9 + 1 + + + LSBFIRST + Least significant bit first + 8 + 1 + + + DS + Data size + 5 + 3 + + + PRTCFG + Protocol configuration + 2 + 2 + + + MODE + Audio block mode + 0 + 2 + + + + + ACR2 + ACR2 + AConfiguration register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + COMP + Companding mode + 14 + 2 + + + CPL + Complement bit + 13 + 1 + + + MUTECN + Mute counter + 7 + 6 + + + MUTEVAL + Mute value + 6 + 1 + + + MUTE + Mute + 5 + 1 + + + TRIS + Tristate management on data line + 4 + 1 + + + FFLUS + FIFO flush + 3 + 1 + + + FTH + FIFO threshold + 0 + 3 + + + + + AFRCR + AFRCR + AFRCR + 0xC + 0x20 + read-write + 0x00000007 + + + FSOFF + Frame synchronization offset + 18 + 1 + + + FSPOL + Frame synchronization polarity + 17 + 1 + + + FSDEF + Frame synchronization definition + 16 + 1 + + + FSALL + Frame synchronization active level length + 8 + 7 + + + FRL + Frame length + 0 + 8 + + + + + ASLOTR + ASLOTR + ASlot register + 0x10 + 0x20 + read-write + 0x00000000 + + + SLOTEN + Slot enable + 16 + 16 + + + NBSLOT + Number of slots in an audio frame + 8 + 4 + + + SLOTSZ + Slot size + 6 + 2 + + + FBOFF + First bit offset + 0 + 5 + + + + + AIM + AIM + AInterrupt mask register2 + 0x14 + 0x20 + read-write + 0x00000000 + + + LFSDET + Late frame synchronization detection interrupt enable + 6 + 1 + + + AFSDETIE + Anticipated frame synchronization detection interrupt enable + 5 + 1 + + + CNRDYIE + Codec not ready interrupt enable + 4 + 1 + + + FREQIE + FIFO request interrupt enable + 3 + 1 + + + WCKCFG + Wrong clock configuration interrupt enable + 2 + 1 + + + MUTEDET + Mute detection interrupt enable + 1 + 1 + + + OVRUDRIE + Overrun/underrun interrupt enable + 0 + 1 + + + + + ASR + ASR + AStatus register + 0x18 + 0x20 + read-write + 0x00000000 + + + FLVL + FIFO level threshold + 16 + 3 + + + LFSDET + Late frame synchronization detection + 6 + 1 + + + AFSDET + Anticipated frame synchronization detection + 5 + 1 + + + CNRDY + Codec not ready + 4 + 1 + + + FREQ + FIFO request + 3 + 1 + + + WCKCFG + Wrong clock configuration flag. This bit is read only + 2 + 1 + + + MUTEDET + Mute detection + 1 + 1 + + + OVRUDR + Overrun / underrun + 0 + 1 + + + + + ACLRFR + ACLRFR + AClear flag register + 0x1C + 0x20 + read-write + 0x00000000 + + + LFSDET + Clear late frame synchronization detection flag + 6 + 1 + + + CAFSDET + Clear anticipated frame synchronization detection flag + 5 + 1 + + + CNRDY + Clear codec not ready flag + 4 + 1 + + + WCKCFG + Clear wrong clock configuration flag + 2 + 1 + + + MUTEDET + Mute detection flag + 1 + 1 + + + OVRUDR + Clear overrun / underrun + 0 + 1 + + + + + ADR + ADR + AData register + 0x20 + 0x20 + read-write + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + PDMCR + PDMCR + PDM control register + 0x44 + 0x20 + read-write + 0x00000000 + + + PDMEN + PDMEN + 0 + 1 + + + MICNBR + MICNBR + 4 + 2 + + + CKEN1 + CKEN1 + 8 + 1 + + + CKEN2 + CKEN2 + 9 + 1 + + + CKEN3 + CKEN3 + 10 + 1 + + + CKEN4 + CKEN4 + 11 + 1 + + + + + PDMDLY + PDMDLY + PDM delay register + 0x48 + 0x20 + read-write + 0x00000000 + + + DLYM1L + DLYM1L + 0 + 3 + + + DLYM1R + DLYM1R + 4 + 3 + + + DLYM2L + DLYM2L + 8 + 3 + + + DLYM2R + DLYM2R + 12 + 3 + + + DLYM3L + DLYM3L + 16 + 3 + + + DLYM3R + DLYM3R + 20 + 3 + + + DLYM4L + DLYM4L + 24 + 3 + + + DLYM4R + DLYM4R + 28 + 3 + + + + + + + TAMP + Tamper and backup registers + TAMP + 0x40002400 + + 0x0 + 0x400 + registers + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0xFFFF0000 + + + TAMP1E + TAMP1E + 0 + 1 + + + TAMP2E + TAMP2E + 1 + 1 + + + TAMP3E + TAMP2E + 2 + 1 + + + ITAMP3E + ITAMP3E + 18 + 1 + + + ITAMP4E + ITAMP4E + 19 + 1 + + + ITAMP5E + ITAMP5E + 20 + 1 + + + ITAMP6E + ITAMP6E + 21 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + TAMP1NOER + TAMP1NOER + 0 + 1 + + + TAMP2NOER + TAMP2NOER + 1 + 1 + + + TAMP3NOER + TAMP3NOER + 2 + 1 + + + TAMP1MSK + TAMP1MSK + 16 + 1 + + + TAMP2MSK + TAMP2MSK + 17 + 1 + + + TAMP3MSK + TAMP3MSK + 18 + 1 + + + TAMP1TRG + TAMP1TRG + 24 + 1 + + + TAMP2TRG + TAMP2TRG + 25 + 1 + + + TAMP3TRG + TAMP3TRG + 26 + 1 + + + + + FLTCR + FLTCR + TAMP filter control register + 0xC + 0x20 + read-write + 0x00000000 + + + TAMPFREQ + TAMPFREQ + 0 + 3 + + + TAMPFLT + TAMPFLT + 3 + 2 + + + TAMPPRCH + TAMPPRCH + 5 + 2 + + + TAMPPUDIS + TAMPPUDIS + 7 + 1 + + + + + IER + IER + TAMP interrupt enable register + 0x2C + 0x20 + read-write + 0x00000000 + + + TAMP1IE + TAMP1IE + 0 + 1 + + + TAMP2IE + TAMP2IE + 1 + 1 + + + TAMP3IE + TAMP3IE + 2 + 1 + + + ITAMP3IE + ITAMP3IE + 18 + 1 + + + ITAMP4IE + ITAMP4IE + 19 + 1 + + + ITAMP5IE + ITAMP5IE + 20 + 1 + + + ITAMP6IE + ITAMP6IE + 21 + 1 + + + + + SR + SR + TAMP status register + 0x30 + 0x20 + read-only + 0x00000000 + + + TAMP1F + TAMP1F + 0 + 1 + + + TAMP2F + TAMP2F + 1 + 1 + + + TAMP3F + TAMP3F + 2 + 1 + + + ITAMP3F + ITAMP3F + 18 + 1 + + + ITAMP4F + ITAMP4F + 19 + 1 + + + ITAMP5F + ITAMP5F + 20 + 1 + + + ITAMP6F + ITAMP6F + 21 + 1 + + + + + MISR + MISR + TAMP masked interrupt status register + 0x34 + 0x20 + read-only + 0x00000000 + + + TAMP1MF + TAMP1MF: + 0 + 1 + + + TAMP2MF + TAMP2MF + 1 + 1 + + + TAMP3MF + TAMP3MF + 2 + 1 + + + ITAMP3MF + ITAMP3MF + 18 + 1 + + + ITAMP4MF + ITAMP4MF + 19 + 1 + + + ITAMP5MF + ITAMP5MF + 20 + 1 + + + ITAMP6MF + ITAMP6MF + 21 + 1 + + + + + SCR + SCR + TAMP status clear register + 0x3C + 0x20 + read-write + 0x00000000 + + + CTAMP1F + CTAMP1F + 0 + 1 + + + CTAMP2F + CTAMP2F + 1 + 1 + + + CTAMP3F + CTAMP3F + 2 + 1 + + + CITAMP3F + CITAMP3F + 18 + 1 + + + CITAMP4F + CITAMP4F + 19 + 1 + + + CITAMP5F + CITAMP5F + 20 + 1 + + + CITAMP6F + CITAMP6F + 21 + 1 + + + + + BKP0R + BKP0R + TAMP backup register + 0x100 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP1R + BKP1R + TAMP backup register + 0x104 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP2R + BKP2R + TAMP backup register + 0x108 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP3R + BKP3R + TAMP backup register + 0x10C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP4R + BKP4R + TAMP backup register + 0x110 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP5R + BKP5R + TAMP backup register + 0x114 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP6R + BKP6R + TAMP backup register + 0x118 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP7R + BKP7R + TAMP backup register + 0x11C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP8R + BKP8R + TAMP backup register + 0x120 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP9R + BKP9R + TAMP backup register + 0x124 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP10R + BKP10R + TAMP backup register + 0x128 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP11R + BKP11R + TAMP backup register + 0x12C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP12R + BKP12R + TAMP backup register + 0x130 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP13R + BKP13R + TAMP backup register + 0x134 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP14R + BKP14R + TAMP backup register + 0x138 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP15R + BKP15R + TAMP backup register + 0x13C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP16R + BKP16R + TAMP backup register + 0x140 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP17R + BKP17R + TAMP backup register + 0x144 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP18R + BKP18R + TAMP backup register + 0x148 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP19R + BKP19R + TAMP backup register + 0x14C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP20R + BKP20R + TAMP backup register + 0x150 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP21R + BKP21R + TAMP backup register + 0x154 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP22R + BKP22R + TAMP backup register + 0x158 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP23R + BKP23R + TAMP backup register + 0x15C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP24R + BKP24R + TAMP backup register + 0x160 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP25R + BKP25R + TAMP backup register + 0x164 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP26R + BKP26R + TAMP backup register + 0x168 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP27R + BKP27R + TAMP backup register + 0x16C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP28R + BKP28R + TAMP backup register + 0x170 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP29R + BKP29R + TAMP backup register + 0x174 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP30R + BKP30R + TAMP backup register + 0x178 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP31R + BKP31R + TAMP backup register + 0x17C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + + + FDCAN + FDCAN + FDCAN + 0x4000A400 + + 0x0 + 0x400 + registers + + + + FDCAN_CREL + FDCAN_CREL + FDCAN core release register + 0x0000 + 0x20 + 0x32141218 + 0xFFFFFFFF + + + DAY + 18 + 0 + 8 + read-only + + + MON + 12 + 8 + 8 + read-only + + + YEAR + 4 + 16 + 4 + read-only + + + SUBSTEP + 1 + 20 + 4 + read-only + + + STEP + 2 + 24 + 4 + read-only + + + REL + 3 + 28 + 4 + read-only + + + + + FDCAN_ENDN + FDCAN_ENDN + FDCAN endian register + 0x0004 + 0x20 + 0x87654321 + 0xFFFFFFFF + + + ETV + Endianness test value +The endianness test value is 0x8765 4321. + 0 + 32 + read-only + + + + + FDCAN_DBTP + FDCAN_DBTP + FDCAN data bit timing and prescaler register + 0x000C + 0x20 + 0x00000A33 + 0xFFFFFFFF + + + DSJW + Synchronization jump width +Must always be smaller than DTSEG2, valid values are 0 to 15. The value used by the hardware is the one programmed, incremented by 1: t<sub>SJW</sub> = (DSJW + 1) x tq. + 0 + 4 + read-write + + + DTSEG2 + Data time segment after sample point +Valid values are 0 to 15. The value used by the hardware is the one programmed, incremented by 1, i.e. t<sub>BS2</sub> = (DTSEG2 + 1) x tq. + 4 + 4 + read-write + + + DTSEG1 + Data time segment before sample point +Valid values are 0 to 31. The value used by the hardware is the one programmed, incremented by 1, i.e. t<sub>BS1</sub> = (DTSEG1 + 1) x tq. + 8 + 5 + read-write + + + DBRP + Data bit rate prescaler +The value by which the oscillator frequency is divided to generate the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 31. The hardware interpreters this value as the value programmed plus 1. + 16 + 5 + read-write + + + TDC + Transceiver delay compensation + 23 + 1 + read-write + + + B_0x0 + Transceiver delay compensation disabled + 0x0 + + + B_0x1 + Transceiver delay compensation enabled + 0x1 + + + + + + + FDCAN_TEST + FDCAN_TEST + FDCAN test register + 0x0010 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LBCK + Loop back mode + 4 + 1 + read-write + + + B_0x0 + Reset value, Loop Back mode is disabled + 0x0 + + + B_0x1 + Loop Back mode is enabled (see Power down (Sleep mode)) + 0x1 + + + + + TX + Control of transmit pin + 5 + 2 + read-write + + + B_0x0 + Reset value, FDCANx_TX TX is controlled by the CAN core, updated at the end of the CAN bit time + 0x0 + + + B_0x1 + Sample point can be monitored at pin FDCANx_TX + 0x1 + + + B_0x2 + Dominant (0) level at pin FDCANx_TX + 0x2 + + + B_0x3 + Recessive (1) at pin FDCANx_TX + 0x3 + + + + + RX + Receive pin +Monitors the actual value of pin FDCANx_RX + 7 + 1 + read-only + + + B_0x0 + The CAN bus is dominant (FDCANx_RX = 0) + 0x0 + + + B_0x1 + The CAN bus is recessive (FDCANx_RX = 1) + 0x1 + + + + + + + FDCAN_RWD + FDCAN_RWD + FDCAN RAM watchdog register + 0x0014 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WDC + Watchdog configuration +Start value of the message RAM watchdog counter. With the reset value of 00, the counter is disabled. +These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of FDCAN_CCCR register are set to 1. + 0 + 8 + read-write + + + WDV + Watchdog value +Actual message RAM watchdog counter value. + 8 + 8 + read-only + + + + + FDCAN_CCCR + FDCAN_CCCR + FDCAN CC control register + 0x0018 + 0x20 + 0x00000001 + 0xFFFFFFFF + + + INIT + Initialization + 0 + 1 + read-write + + + B_0x0 + Normal operation + 0x0 + + + B_0x1 + Initialization started + 0x1 + + + + + CCE + Configuration change enable + 1 + 1 + read-write + + + B_0x0 + The CPU has no write access to the protected configuration registers. + 0x0 + + + B_0x1 + The CPU has write access to the protected configuration registers (while CCCR.INIT = 1). + 0x1 + + + + + ASM + ASM restricted operation mode +The restricted operation mode is intended for applications that adapt themselves to different CAN bit rates. The application tests different bit rates and leaves the Restricted operation Mode after it has received a valid frame. In the optional Restricted operation Mode the node is able to transmit and receive data and remote frames and it gives acknowledge to valid frames, but it does not send active error frames or overload frames. In case of an error condition or overload condition, it does not send dominant bits, instead it waits for the occurrence of bus idle condition to resynchronize itself to the CAN communication. The error counters are not incremented. Bit ASM can only be set by software when both CCE and INIT are set to 1. The bit can be reset by the software at any time. + 2 + 1 + read-write + + + B_0x0 + Normal CAN operation + 0x0 + + + B_0x1 + Restricted operation Mode active + 0x1 + + + + + CSA + Clock stop acknowledge + 3 + 1 + read-only + + + B_0x0 + No clock stop acknowledged + 0x0 + + + B_0x1 + FDCAN may be set in power down by stopping APB clock and kernel clock. + 0x1 + + + + + CSR + Clock stop request + 4 + 1 + read-write + + + B_0x0 + No clock stop requested + 0x0 + + + B_0x1 + Clock stop requested. When clock stop is requested, first INIT and then CSA is set after all pending transfer requests have been completed and the CAN bus reached idle. + 0x1 + + + + + MON + Bus monitoring mode +Bit MON can only be set by software when both CCE and INIT are set to 1. The bit can be reset by the Host at any time. + 5 + 1 + read-write + + + B_0x0 + Bus monitoring mode disabled + 0x0 + + + B_0x1 + Bus monitoring mode enabled + 0x1 + + + + + DAR + Disable automatic retransmission + 6 + 1 + read-write + + + B_0x0 + Automatic retransmission of messages not transmitted successfully enabled + 0x0 + + + B_0x1 + Automatic retransmission disabled + 0x1 + + + + + TEST + Test mode enable + 7 + 1 + read-write + + + B_0x0 + Normal operation, register TEST holds reset values + 0x0 + + + B_0x1 + Test Mode, write access to register TEST enabled + 0x1 + + + + + FDOE + FD operation enable + 8 + 1 + read-write + + + B_0x0 + FD operation disabled + 0x0 + + + B_0x1 + FD operation enabled + 0x1 + + + + + BRSE + FDCAN bit rate switching + 9 + 1 + read-write + + + B_0x0 + Bit rate switching for transmissions disabled + 0x0 + + + B_0x1 + Bit rate switching for transmissions enabled + 0x1 + + + + + PXHD + Protocol exception handling disable + 12 + 1 + read-write + + + B_0x0 + Protocol exception handling enabled + 0x0 + + + B_0x1 + Protocol exception handling disabled + 0x1 + + + + + EFBI + Edge filtering during bus integration + 13 + 1 + read-write + + + B_0x0 + Edge filtering disabled + 0x0 + + + B_0x1 + Two consecutive dominant tq required to detect an edge for hard synchronization + 0x1 + + + + + TXP + If this bit is set, the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame. + 14 + 1 + read-write + + + B_0x0 + disabled + 0x0 + + + B_0x1 + enabled + 0x1 + + + + + NISO + Non ISO operation +If this bit is set, the FDCAN uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0. + 15 + 1 + read-write + + + B_0x0 + CAN FD frame format according to ISO11898-1 + 0x0 + + + B_0x1 + CAN FD frame format according to Bosch CAN FD Specification V1.0 + 0x1 + + + + + + + FDCAN_NBTP + FDCAN_NBTP + FDCAN nominal bit timing and prescaler register + 0x001C + 0x20 + 0x06000A03 + 0xFFFFFFFF + + + NTSEG2 + Nominal time segment after sample point +Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. + 0 + 7 + read-write + + + NTSEG1 + Nominal time segment before sample point +Valid values are 0 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. +These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. + 8 + 8 + read-write + + + NBRP + Bit rate prescaler +Value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values are 0 to 511. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. +These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. + 16 + 9 + read-write + + + NSJW + Nominal (re)synchronization jump width +Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that the used value is the one programmed incremented by one. +These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. + 25 + 7 + read-write + + + + + FDCAN_TSCC + FDCAN_TSCC + FDCAN timestamp counter configuration register + 0x0020 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TSS + Timestamp select +These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. + 0 + 2 + read-write + + + B_0x0 + Timestamp counter value always 0x0000 + 0x0 + + + B_0x1 + Timestamp counter value incremented according to TCP + 0x1 + + + B_0x2 + External timestamp counter from TIM3 value (tim3_cnt[0:15]) + 0x2 + + + B_0x3 + Same as 00. + 0x3 + + + + + TCP + Timestamp counter prescaler + 16 + 4 + read-write + + + + + FDCAN_TSCV + FDCAN_TSCV + FDCAN timestamp counter value register + 0x0024 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TSC + Timestamp counter + 0 + 16 + read-write + + + + + FDCAN_TOCC + FDCAN_TOCC + FDCAN timeout counter configuration register + 0x0028 + 0x20 + 0xFFFF0000 + 0xFFFFFFFF + + + ETOC + Timeout counter enable +This is a protected write (P) bit, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. + 0 + 1 + read-write + + + B_0x0 + Timeout counter disabled + 0x0 + + + B_0x1 + Timeout counter enabled + 0x1 + + + + + TOS + Timeout select +When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC[TOP] and continues down-counting. When the timeout counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC[TOP]. Down-counting is started when the first FIFO element is stored. +These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. + 1 + 2 + read-write + + + B_0x0 + Continuous operation + 0x0 + + + B_0x1 + Timeout controlled by Tx event FIFO + 0x1 + + + B_0x2 + Timeout controlled by Rx FIFO 0 + 0x2 + + + B_0x3 + Timeout controlled by Rx FIFO 1 + 0x3 + + + + + TOP + Timeout period +Start value of the timeout counter (down-counter). Configures the timeout period. + 16 + 16 + read-write + + + + + FDCAN_TOCV + FDCAN_TOCV + FDCAN timeout counter value register + 0x002C + 0x20 + 0x0000FFFF + 0xFFFFFFFF + + + TOC + Timeout counter + 0 + 16 + read-write + + + + + FDCAN_ECR + FDCAN_ECR + FDCAN error counter register + 0x0040 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TEC + Transmit error counter +Actual state of the transmit error counter, values between 0 and 255. +When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented. + 0 + 8 + read-only + + + REC + Receive error counter +Actual state of the receive error counter, values between 0 and 127. + 8 + 7 + read-only + + + RP + Receive error passive + 15 + 1 + read-only + + + B_0x0 + The receive error counter is below the error passive level of 128. + 0x0 + + + B_0x1 + The receive error counter has reached the error passive level of 128. + 0x1 + + + + + CEL + CAN error logging +The counter is incremented each time when a CAN protocol error causes the transmit error counter or the receive error counter to be incremented. It is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR[ELO]. +Access type is RX: reset on read. + 16 + 8 + read-write + + + + + FDCAN_PSR + FDCAN_PSR + FDCAN protocol status register + 0x0044 + 0x20 + 0x00000707 + 0xFFFFFFFF + + + LEC + Last error code +The LEC indicates the type of the last error to occur on the CAN bus. This field is cleared to 0 when a message has been transferred (reception or transmission) without error. +Access type is RS: set on read. + 0 + 3 + read-write + + + B_0x0 + No Error: No error occurred since LEC has been reset by successful reception or transmission. + 0x0 + + + B_0x1 + Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. + 0x1 + + + B_0x2 + Form Error: A fixed format part of a received frame has the wrong format. + 0x2 + + + B_0x3 + AckError: The message transmitted by the FDCAN was not acknowledged by another node. + 0x3 + + + B_0x4 + Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value 1), but the monitored bus value was dominant. + 0x4 + + + B_0x5 + Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value 0), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). + 0x5 + + + B_0x6 + CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. + 0x6 + + + B_0x7 + NoChange: Any read access to the Protocol status register re-initializes the LEC to 7. When the LEC shows the value 7, no CAN bus event was detected since the last CPU read access to the Protocol status register. + 0x7 + + + + + ACT + Activity +Monitors the modules CAN communication state. + 3 + 2 + read-only + + + B_0x0 + Synchronizing: node is synchronizing on CAN communication. + 0x0 + + + B_0x1 + Idle: node is neither receiver nor transmitter. + 0x1 + + + B_0x2 + Receiver: node is operating as receiver. + 0x2 + + + B_0x3 + Transmitter: node is operating as transmitter. + 0x3 + + + + + EP + Error passive + 5 + 1 + read-only + + + B_0x0 + The FDCAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected. + 0x0 + + + B_0x1 + The FDCAN is in the Error_Passive state. + 0x1 + + + + + EW + Warning Sstatus + 6 + 1 + read-only + + + B_0x0 + Both error counters are below the Error_Warning limit of 96. + 0x0 + + + B_0x1 + At least one of error counter has reached the Error_Warning limit of 96. + 0x1 + + + + + BO + Bus_Off status + 7 + 1 + read-only + + + B_0x0 + The FDCAN is not Bus_Off. + 0x0 + + + B_0x1 + The FDCAN is in Bus_Off state. + 0x1 + + + + + DLEC + Data last error code +Type of last error that occurred in the data phase of a FDCAN format frame with its BRS flag set. Coding is the same as for LEC. This field is cleared to 0 when a FDCAN format frame with its BRS flag set has been transferred (reception or transmission) without error. +Access type is RS: set on read. + 8 + 3 + read-write + + + RESI + ESI flag of last received FDCAN message +This bit is set together with REDL, independent of acceptance filtering. +Access type is RX: reset on read. + 11 + 1 + read-write + + + B_0x0 + Last received FDCAN message did not have its ESI flag set. + 0x0 + + + B_0x1 + Last received FDCAN message had its ESI flag set. + 0x1 + + + + + RBRS + BRS flag of last received FDCAN message +This bit is set together with REDL, independent of acceptance filtering. +Access type is RX: reset on read. + 12 + 1 + read-write + + + B_0x0 + Last received FDCAN message did not have its BRS flag set. + 0x0 + + + B_0x1 + Last received FDCAN message had its BRS flag set. + 0x1 + + + + + REDL + Received FDCAN message +This bit is set independent of acceptance filtering. +Access type is RX: reset on read. + 13 + 1 + read-write + + + B_0x0 + Since this bit was reset by the CPU, no FDCAN message has been received. + 0x0 + + + B_0x1 + Message in FDCAN format with EDL flag set has been received. + 0x1 + + + + + PXE + Protocol exception event + 14 + 1 + read-write + + + B_0x0 + No protocol exception event occurred since last read access + 0x0 + + + B_0x1 + Protocol exception event occurred + 0x1 + + + + + TDCV + Transmitter delay compensation value +Position of the secondary sample point, defined by the sum of the measured delay from FDCAN_TX to FDCAN_RX and TDCR.TDCO. The SSP position is, in the data phase, the number of minimum time quanta (mtq) between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq. + 16 + 7 + read-only + + + + + FDCAN_TDCR + FDCAN_TDCR + FDCAN transmitter delay compensation register + 0x0048 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TDCF + Transmitter delay compensation filter window length +Defines the minimum value for the SSP position, dominant edges on FDCAN_RX that would result in an earlier SSP position are ignored for transmitter delay measurements. +These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. + 0 + 7 + read-write + + + TDCO + Transmitter delay compensation offset +Offset value defining the distance between the measured delay from FDCAN_TX to FDCAN_RX and the secondary sample point. Valid values are 0 to 127 mtq. +These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. + 8 + 7 + read-write + + + + + FDCAN_IR + FDCAN_IR + FDCAN interrupt register + 0x0050 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RF0N + Rx FIFO 0 new message + 0 + 1 + read-write + + + B_0x0 + No new message written to Rx FIFO 0 + 0x0 + + + B_0x1 + New message written to Rx FIFO 0 + 0x1 + + + + + RF0F + Rx FIFO 0 full + 1 + 1 + read-write + + + B_0x0 + Rx FIFO 0 not full + 0x0 + + + B_0x1 + Rx FIFO 0 full + 0x1 + + + + + RF0L + Rx FIFO 0 message lost + 2 + 1 + read-write + + + B_0x0 + No Rx FIFO 0 message lost + 0x0 + + + B_0x1 + Rx FIFO 0 message lost + 0x1 + + + + + RF1N + Rx FIFO 1 new message + 3 + 1 + read-write + + + B_0x0 + No new message written to Rx FIFO 1 + 0x0 + + + B_0x1 + New message written to Rx FIFO 1 + 0x1 + + + + + RF1F + Rx FIFO 1 full + 4 + 1 + read-write + + + B_0x0 + Rx FIFO 1 not full + 0x0 + + + B_0x1 + Rx FIFO 1 full + 0x1 + + + + + RF1L + Rx FIFO 1 message lost + 5 + 1 + read-write + + + B_0x0 + No Rx FIFO 1 message lost + 0x0 + + + B_0x1 + Rx FIFO 1 message lost + 0x1 + + + + + HPM + High-priority message + 6 + 1 + read-write + + + B_0x0 + No high-priority message received + 0x0 + + + B_0x1 + High-priority message received + 0x1 + + + + + TC + Transmission completed + 7 + 1 + read-write + + + B_0x0 + No transmission completed + 0x0 + + + B_0x1 + Transmission completed + 0x1 + + + + + TCF + Transmission cancellation finished + 8 + 1 + read-write + + + B_0x0 + No transmission cancellation finished + 0x0 + + + B_0x1 + Transmission cancellation finished + 0x1 + + + + + TFE + Tx FIFO empty + 9 + 1 + read-write + + + B_0x0 + Tx FIFO non-empty + 0x0 + + + B_0x1 + Tx FIFO empty + 0x1 + + + + + TEFN + Tx event FIFO New Entry + 10 + 1 + read-write + + + B_0x0 + Tx event FIFO unchanged + 0x0 + + + B_0x1 + Tx handler wrote Tx event FIFO element. + 0x1 + + + + + TEFF + Tx event FIFO full + 11 + 1 + read-write + + + B_0x0 + Tx event FIFO Not full + 0x0 + + + B_0x1 + Tx event FIFO full + 0x1 + + + + + TEFL + Tx event FIFO element lost + 12 + 1 + read-write + + + B_0x0 + No Tx event FIFO element lost + 0x0 + + + B_0x1 + Tx event FIFO element lost + 0x1 + + + + + TSW + Timestamp wraparound + 13 + 1 + read-write + + + B_0x0 + No timestamp counter wrap-around + 0x0 + + + B_0x1 + Timestamp counter wrapped around + 0x1 + + + + + MRAF + Message RAM access failure +The flag is set when the Rx handler: +has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx handler starts processing of the following message. +was unable to write a message to the message RAM. In this case message storage is aborted. +In both cases the FIFO put index is not updated. The partly stored message is overwritten when the next message is stored to this location. +The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the FDCAN is switched into Restricted operation Mode (see Restricted operation mode). To leave Restricted operation Mode, the Host CPU has to reset CCCR.ASM. + 14 + 1 + read-write + + + B_0x0 + No Message RAM access failure occurred + 0x0 + + + B_0x1 + Message RAM access failure occurred + 0x1 + + + + + TOO + Timeout occurred + 15 + 1 + read-write + + + B_0x0 + No timeout + 0x0 + + + B_0x1 + Timeout reached + 0x1 + + + + + ELO + Error logging overflow + 16 + 1 + read-write + + + B_0x0 + CAN error logging counter did not overflow. + 0x0 + + + B_0x1 + Overflow of CAN error logging counter occurred. + 0x1 + + + + + EP + Error passive + 17 + 1 + read-write + + + B_0x0 + Error_Passive status unchanged + 0x0 + + + B_0x1 + Error_Passive status changed + 0x1 + + + + + EW + Warning status + 18 + 1 + read-write + + + B_0x0 + Error_Warning status unchanged + 0x0 + + + B_0x1 + Error_Warning status changed + 0x1 + + + + + BO + Bus_Off status + 19 + 1 + read-write + + + B_0x0 + Bus_Off status unchanged + 0x0 + + + B_0x1 + Bus_Off status changed + 0x1 + + + + + WDI + Watchdog interrupt + 20 + 1 + read-write + + + B_0x0 + No message RAM watchdog event occurred + 0x0 + + + B_0x1 + Message RAM watchdog event due to missing READY + 0x1 + + + + + PEA + Protocol error in arbitration phase (nominal bit time is used) + 21 + 1 + read-write + + + B_0x0 + No protocol error in arbitration phase + 0x0 + + + B_0x1 + Protocol error in arbitration phase detected (PSR.LEC different from 0,7) + 0x1 + + + + + PED + Protocol error in data phase (data bit time is used) + 22 + 1 + read-write + + + B_0x0 + No protocol error in data phase + 0x0 + + + B_0x1 + Protocol error in data phase detected (PSR.DLEC different from 0,7) + 0x1 + + + + + ARA + Access to reserved address + 23 + 1 + read-write + + + B_0x0 + No access to reserved address occurred + 0x0 + + + B_0x1 + Access to reserved address occurred + 0x1 + + + + + + + FDCAN_IE + FDCAN_IE + FDCAN interrupt enable register + 0x0054 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RF0NE + Rx FIFO 0 new message interrupt enable + 0 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + RF0FE + Rx FIFO 0 full interrupt enable + 1 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + RF0LE + Rx FIFO 0 message lost interrupt enable + 2 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + RF1NE + Rx FIFO 1 new message interrupt enable + 3 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + RF1FE + Rx FIFO 1 full interrupt enable + 4 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + RF1LE + Rx FIFO 1 message lost interrupt enable + 5 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + HPME + High-priority message interrupt enable + 6 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + TCE + Transmission completed interrupt enable + 7 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + TCFE + Transmission cancellation finished interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + TFEE + Tx FIFO empty interrupt enable + 9 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + TEFNE + Tx event FIFO new entry interrupt enable + 10 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + TEFFE + Tx event FIFO full interrupt enable + 11 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + TEFLE + Tx event FIFO element lost interrupt enable + 12 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + TSWE + Timestamp wraparound interrupt enable + 13 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + MRAFE + Message RAM access failure interrupt enable + 14 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + TOOE + Timeout occurred interrupt enable + 15 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + ELOE + Error logging overflow interrupt enable + 16 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EPE + Error passive interrupt enable + 17 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EWE + Warning status interrupt enable + 18 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + BOE + Bus_Off status + 19 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + WDIE + Watchdog interrupt enable + 20 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + PEAE + Protocol error in arbitration phase enable + 21 + 1 + read-write + + + PEDE + Protocol error in data phase enable + 22 + 1 + read-write + + + ARAE + Access to reserved address enable + 23 + 1 + read-write + + + + + FDCAN_ILS + FDCAN_ILS + FDCAN interrupt line select register + 0x0058 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RXFIFO0 + RX FIFO bit grouping the following interruption +RF0LL: Rx FIFO 0 message lost interrupt line +RF0FL: Rx FIFO 0 full interrupt line +RF0NL: Rx FIFO 0 new message interrupt line + 0 + 1 + read-write + + + RXFIFO1 + RX FIFO bit grouping the following interruption +RF1LL: Rx FIFO 1 message lost interrupt line +RF1FL: Rx FIFO 1 full interrupt line +RF1NL: Rx FIFO 1 new message interrupt line + 1 + 1 + read-write + + + SMSG + Status message bit grouping the following interruption +TCFL: Transmission cancellation finished interrupt line +TCL: Transmission completed interrupt line +HPML: High-priority message interrupt line + 2 + 1 + read-write + + + TFERR + Tx FIFO ERROR grouping the following interruption +TEFLL: Tx event FIFO element lost interrupt line +TEFFL: Tx event FIFO full interrupt line +TEFNL: Tx event FIFO new entry interrupt line +TFEL: Tx FIFO empty interrupt line + 3 + 1 + read-write + + + MISC + Interrupt regrouping the following interruption +TOOL: Timeout occurred interrupt line +MRAFL: Message RAM access failure interrupt line +TSWL: Timestamp wraparound interrupt line + 4 + 1 + read-write + + + BERR + Bit and line error grouping the following interruption +EPL Error passive interrupt line +ELOL: Error logging overflow interrupt line + 5 + 1 + read-write + + + PERR + Protocol error grouping the following interruption +ARAL: Access to reserved address line +PEDL: Protocol error in data phase line +PEAL: Protocol error in arbitration phase line +WDIL: Watchdog interrupt line +BOL: Bus_Off status +EWL: Warning status interrupt line + 6 + 1 + read-write + + + + + FDCAN_ILE + FDCAN_ILE + FDCAN interrupt line enable register + 0x005C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EINT0 + Enable interrupt line 0 + 0 + 1 + read-write + + + B_0x0 + Interrupt line fdcan_intr1_it disabled + 0x0 + + + B_0x1 + Interrupt line fdcan_intr1_it enabled + 0x1 + + + + + EINT1 + Enable interrupt line 1 + 1 + 1 + read-write + + + B_0x0 + Interrupt line fdcan_intr0_it disabled + 0x0 + + + B_0x1 + Interrupt line fdcan_intr0_it enabled + 0x1 + + + + + + + FDCAN_RXGFC + FDCAN_RXGFC + FDCAN global filter configuration register + 0x0080 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RRFE + Reject remote frames extended +These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. + 0 + 1 + read-write + + + B_0x0 + Filter remote frames with 29-bit standard IDs + 0x0 + + + B_0x1 + Reject all remote frames with 29-bit standard IDs + 0x1 + + + + + RRFS + Reject remote frames standard +These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. + 1 + 1 + read-write + + + B_0x0 + Filter remote frames with 11-bit standard IDs + 0x0 + + + B_0x1 + Reject all remote frames with 11-bit standard IDs + 0x1 + + + + + ANFE + Accept non-matching frames extended +Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. +These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. + 2 + 2 + read-write + + + B_0x0 + Accept in Rx FIFO 0 + 0x0 + + + B_0x1 + Accept in Rx FIFO 1 + 0x1 + + + B_0x2 + Reject + 0x2 + + + B_0x3 + Reject + 0x3 + + + + + ANFS + Accept Non-matching frames standard +Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. +These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. + 4 + 2 + read-write + + + B_0x0 + Accept in Rx FIFO 0 + 0x0 + + + B_0x1 + Accept in Rx FIFO 1 + 0x1 + + + B_0x2 + Reject + 0x2 + + + B_0x3 + Reject + 0x3 + + + + + F1OM + FIFO 1 operation mode (overwrite or blocking) +This is a protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. + 8 + 1 + read-write + + + F0OM + FIFO 0 operation mode (overwrite or blocking) +This is protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. + 9 + 1 + read-write + + + LSS + List size standard +1 to 28: Number of standard message ID filter elements +>28: Values greater than 28 are interpreted as 28. +These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. + 16 + 5 + read-write + + + B_0x0 + No standard message ID filter + 0x0 + + + + + LSE + List size extended +1 to 8: Number of extended message ID filter elements +>8: Values greater than 8 are interpreted as 8. +These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. + 24 + 4 + read-write + + + B_0x0 + No extended message ID filter + 0x0 + + + + + + + FDCAN_XIDAM + FDCAN_XIDAM + FDCAN extended ID and mask register + 0x0084 + 0x20 + 0x1FFFFFFF + 0xFFFFFFFF + + + EIDM + Extended ID mask +For acceptance filtering of extended frames the Extended ID AND Mask is AND-ed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to 1 the mask is not active. +These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. + 0 + 29 + read-write + + + + + FDCAN_HPMS + FDCAN_HPMS + FDCAN high-priority message status register + 0x0088 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BIDX + Buffer index +Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] = 1. + 0 + 3 + read-only + + + MSI + Message storage indicator + 6 + 2 + read-only + + + B_0x0 + No FIFO selected + 0x0 + + + B_0x1 + FIFO overrun + 0x1 + + + B_0x2 + Message stored in FIFO 0 + 0x2 + + + B_0x3 + Message stored in FIFO 1 + 0x3 + + + + + FIDX + Filter index +Index of matching filter element. Range is 0 to RXGFC[LSS] - 1 or RXGFC[LSE] - 1. + 8 + 5 + read-only + + + FLST + Filter list +Indicates the filter list of the matching filter element. + 15 + 1 + read-only + + + B_0x0 + Standard filter list + 0x0 + + + B_0x1 + Extended filter list + 0x1 + + + + + + + FDCAN_RXF0S + FDCAN_RXF0S + FDCAN Rx FIFO 0 status register + 0x0090 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + F0FL + Rx FIFO 0 fill level +Number of elements stored in Rx FIFO 0, range 0 to 3. + 0 + 4 + read-only + + + F0GI + Rx FIFO 0 get index +Rx FIFO 0 read index pointer, range 0 to 2. + 8 + 2 + read-only + + + F0PI + Rx FIFO 0 put index +Rx FIFO 0 write index pointer, range 0 to 2. + 16 + 2 + read-only + + + F0F + Rx FIFO 0 full + 24 + 1 + read-only + + + B_0x0 + Rx FIFO 0 not full + 0x0 + + + B_0x1 + Rx FIFO 0 full + 0x1 + + + + + RF0L + Rx FIFO 0 message lost +This bit is a copy of interrupt flag IR[RF0L]. When IR[RF0L] is reset, this bit is also reset. + 25 + 1 + read-only + + + B_0x0 + No Rx FIFO 0 message lost + 0x0 + + + B_0x1 + Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size 0 + 0x1 + + + + + + + FDCAN_RXF0A + FDCAN_RXF0A + CAN Rx FIFO 0 acknowledge register + 0x0094 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + F0AI + Rx FIFO 0 acknowledge index +After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This sets the Rx FIFO 0 get index RXF0S[F0GI] to F0AI + 1 and update the FIFO 0 fill level RXF0S[F0FL]. + 0 + 3 + read-write + + + + + FDCAN_RXF1S + FDCAN_RXF1S + FDCAN Rx FIFO 1 status register + 0x0098 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + F1FL + Rx FIFO 1 fill level +Number of elements stored in Rx FIFO 1, range 0 to 3. + 0 + 4 + read-only + + + F1GI + Rx FIFO 1 get index +Rx FIFO 1 read index pointer, range 0 to 2. + 8 + 2 + read-only + + + F1PI + Rx FIFO 1 put index +Rx FIFO 1 write index pointer, range 0 to 2. + 16 + 2 + read-only + + + F1F + Rx FIFO 1 full + 24 + 1 + read-only + + + B_0x0 + Rx FIFO 1 not full + 0x0 + + + B_0x1 + Rx FIFO 1 full + 0x1 + + + + + RF1L + Rx FIFO 1 message lost +This bit is a copy of interrupt flag IR[RF1L]. When IR[RF1L] is reset, this bit is also reset. + 25 + 1 + read-only + + + B_0x0 + No Rx FIFO 1 message lost + 0x0 + + + B_0x1 + Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size 0 + 0x1 + + + + + + + FDCAN_RXF1A + FDCAN_RXF1A + FDCAN Rx FIFO 1 acknowledge register + 0x009C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + F1AI + Rx FIFO 1 acknowledge index +After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This sets the Rx FIFO 1 get index RXF1S[F1GI] to F1AI + 1 and update the FIFO 1 Fill Level RXF1S[F1FL]. + 0 + 3 + read-write + + + + + FDCAN_TXBC + FDCAN_TXBC + FDCAN Tx buffer configuration register + 0x00C0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TFQM + Tx FIFO/queue mode +This is a protected write (P) bit, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. + 24 + 1 + read-write + + + B_0x0 + Tx FIFO operation + 0x0 + + + B_0x1 + Tx queue operation. + 0x1 + + + + + + + FDCAN_TXFQS + FDCAN_TXFQS + FDCAN Tx FIFO/queue status register + 0x00C4 + 0x20 + 0x00000003 + 0xFFFFFFFF + + + TFFL + Tx FIFO free level +Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 3. Read as 0 when Tx queue operation is configured (TXBC[TFQM] = 1). + 0 + 3 + read-only + + + TFGI + Tx FIFO get index +Tx FIFO read index pointer, range 0 to 3. Read as 0 when Tx queue operation is configured (TXBC.TFQM = 1) + 8 + 2 + read-only + + + TFQPI + Tx FIFO/queue put index +Tx FIFO/queue write index pointer, range 0 to 3 + 16 + 2 + read-only + + + TFQF + Tx FIFO/queue full + 21 + 1 + read-only + + + B_0x0 + Tx FIFO/queue not full + 0x0 + + + B_0x1 + Tx FIFO/queue full + 0x1 + + + + + + + FDCAN_TXBRP + FDCAN_TXBRP + FDCAN Tx buffer request pending register + 0x00C8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TRP + Transmission request pending +Each Tx buffer has its own transmission request pending bit. The bits are set via register TXBAR. The bits are reset after a requested transmission has completed or has been canceled via register TXBCR. +After a TXBRP bit has been set, a Tx scan is started to check for the pending Tx request with the highest priority (Tx buffer with lowest Message ID). +A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. +After a cancellation has been requested, a finished cancellation is signaled via TXBCF +after successful transmission together with the corresponding TXBTO bit +when the transmission has not yet been started at the point of cancellation +when the transmission has been aborted due to lost arbitration +when an error occurred during frame transmission +In DAR mode all transmissions are automatically canceled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions. + 0 + 3 + read-only + + + B_0x0 + No transmission request pending + 0x0 + + + B_0x1 + Transmission request pending + 0x1 + + + + + + + FDCAN_TXBAR + FDCAN_TXBAR + FDCAN Tx buffer add request register + 0x00CC + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AR + Add request +Each Tx buffer has its own add request bit. Writing a 1 sets the corresponding add request bit; writing a 0 has no impact. This enables the Host to set transmission requests for multiple Tx buffers with one write to TXBAR. When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed. + 0 + 3 + read-write + + + B_0x0 + No transmission request added + 0x0 + + + B_0x1 + Transmission requested added. + 0x1 + + + + + + + FDCAN_TXBCR + FDCAN_TXBCR + FDCAN Tx buffer cancellation request register + 0x00D0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CR + Cancellation request +Each Tx buffer has its own cancellation request bit. Writing a 1 sets the corresponding CR bit; writing a 0 has no impact. +This enables the Host to set cancellation requests for multiple Tx buffers with one write to TXBCR. The bits remain set until the corresponding TXBRP bit is reset. + 0 + 3 + read-write + + + B_0x0 + No cancellation pending + 0x0 + + + B_0x1 + Cancellation pending + 0x1 + + + + + + + FDCAN_TXBTO + FDCAN_TXBTO + FDCAN Tx buffer transmission occurred register + 0x00D4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TO + Transmission occurred. +Each Tx buffer has its own TO bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register TXBAR. + 0 + 3 + read-only + + + B_0x0 + No transmission occurred + 0x0 + + + B_0x1 + Transmission occurred + 0x1 + + + + + + + FDCAN_TXBCF + FDCAN_TXBCF + FDCAN Tx buffer cancellation finished register + 0x00D8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CF + Cancellation finished +Each Tx buffer has its own CF bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register TXBAR. + 0 + 3 + read-only + + + B_0x0 + No transmit buffer cancellation + 0x0 + + + B_0x1 + Transmit buffer cancellation finished + 0x1 + + + + + + + FDCAN_TXBTIE + FDCAN_TXBTIE + FDCAN Tx buffer transmission interrupt enable register + 0x00DC + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIE + Transmission interrupt enable +Each Tx buffer has its own TIE bit. + 0 + 3 + read-write + + + B_0x0 + Transmission interrupt disabled + 0x0 + + + B_0x1 + Transmission interrupt enable + 0x1 + + + + + + + FDCAN_TXBCIE + FDCAN_TXBCIE + FDCAN Tx buffer cancellation finished interrupt enable register + 0x00E0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CFIE + Cancellation finished interrupt enable. +Each Tx buffer has its own CFIE bit. + 0 + 3 + read-write + + + B_0x0 + Cancellation finished interrupt disabled + 0x0 + + + B_0x1 + Cancellation finished interrupt enabled + 0x1 + + + + + + + FDCAN_TXEFS + FDCAN_TXEFS + FDCAN Tx event FIFO status register + 0x00E4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EFFL + Event FIFO fill level +Number of elements stored in Tx event FIFO, range 0 to 3. + 0 + 3 + read-only + + + EFGI + Event FIFO get index +Tx event FIFO read index pointer, range 0 to 3. + 8 + 2 + read-only + + + EFPI + Event FIFO put index +Tx event FIFO write index pointer, range 0 to 3. + 16 + 2 + read-only + + + EFF + Event FIFO full + 24 + 1 + read-only + + + B_0x0 + Tx event FIFO not full + 0x0 + + + B_0x1 + Tx event FIFO full + 0x1 + + + + + TEFL + Tx event FIFO element lost +This bit is a copy of interrupt flag IR[TEFL]. When IR[TEFL] is reset, this bit is also reset. +0 No Tx event FIFO element lost +1 Tx event FIFO element lost, also set after write attempt to Tx event FIFO of size 0. + 25 + 1 + read-only + + + + + FDCAN_TXEFA + FDCAN_TXEFA + FDCAN Tx event FIFO acknowledge register + 0x00E8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EFAI + Event FIFO acknowledge index +After the Host has read an element or a sequence of elements from the Tx event FIFO, it has to write the index of the last element read from Tx event FIFO to EFAI. This sets the Tx event FIFO get index TXEFS[EFGI] to EFAI + 1 and updates the FIFO 0 fill level TXEFS[EFFL]. + 0 + 2 + read-write + + + + + FDCAN_CKDIV + FDCAN_CKDIV + FDCAN CFG clock divider register + 0x0100 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PDIV + input clock divider +The APB clock could be divided prior to be used by the CAN sub system. The rate must be computed using the divider output clock. +These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. + 0 + 4 + read-write + + + B_0x0 + Divide by 1 + 0x0 + + + B_0x1 + Divide by 2 + 0x1 + + + B_0x2 + Divide by 4 + 0x2 + + + B_0x3 + Divide by 6 + 0x3 + + + B_0x4 + Divide by 8 + 0x4 + + + B_0x5 + Divide by 10 + 0x5 + + + B_0x6 + Divide by 12 + 0x6 + + + B_0x7 + Divide by 14 + 0x7 + + + B_0x8 + Divide by 16 + 0x8 + + + B_0x9 + Divide by 18 + 0x9 + + + B_0xA + Divide by 20 + 0xA + + + B_0xB + Divide by 22 + 0xB + + + B_0xC + Divide by 24 + 0xC + + + B_0xD + Divide by 26 + 0xD + + + B_0xE + Divide by 28 + 0xE + + + B_0xF + Divide by 30 + 0xF + + + + + + + + + FDCAN1 + 0x40006400 + + FDCAN1_IT0 + FDCAN1 interrupt 0 + 21 + + + FDCAN1_IT1 + FDCAN1 interrupt 1 + 22 + + + + FDCAN2 + 0x40006800 + + FDCAN2_IT0 + FDCAN2 interrupt 0 + 86 + + + FDCAN2_IT1 + FDCAN2 interrupt 1 + 87 + + + + FDCAN3 + 0x40006C00 + + FDCAN3_IT0 + FDCAN3 interrupt 0 + 88 + + + FDCAN3_IT1 + FDCAN3 interrupt 1 + 89 + + + + UCPD1 + UCPD1 + UCPD + 0x4000A000 + + 0x0 + 0x400 + registers + + + UCPD1 + UCPD1 + 63 + + + + CFG1 + CFG1 + UCPD configuration register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + HBITCLKDIV + HBITCLKDIV + 0 + 6 + + + IFRGAP + IFRGAP + 6 + 5 + + + TRANSWIN + TRANSWIN + 11 + 5 + + + PSC_USBPDCLK + PSC_USBPDCLK + 17 + 3 + + + RXORDSETEN + RXORDSETEN + 20 + 9 + + + TXDMAEN + TXDMAEN + 29 + 1 + + + RXDMAEN + RXDMAEN + 30 + 1 + + + UCPDEN + UCPDEN + 31 + 1 + + + + + CFG2 + CFG2 + UCPD configuration register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + RXFILTDIS + RXFILTDIS + 0 + 1 + + + RXFILT2N3 + RXFILT2N3 + 1 + 1 + + + FORCECLK + FORCECLK + 2 + 1 + + + WUPEN + WUPEN + 3 + 1 + + + + + CR + CR + UCPD configuration register 2 + 0xC + 0x20 + read-write + 0x00000000 + + + TXMODE + TXMODE + 0 + 2 + + + TXSEND + TXSEND + 2 + 1 + + + TXHRST + TXHRST + 3 + 1 + + + RXMODE + RXMODE + 4 + 1 + + + PHYRXEN + PHYRXEN + 5 + 1 + + + PHYCCSEL + PHYCCSEL + 6 + 1 + + + ANASUBMODE + ANASUBMODE + 7 + 2 + + + ANAMODE + ANAMODE + 9 + 1 + + + CCENABLE + CCENABLE + 10 + 2 + + + FRSRXEN + FRSRXEN + 16 + 1 + + + FRSTX + FRSTX + 17 + 1 + + + RDCH + RDCH + 18 + 1 + + + CC1TCDIS + CC1TCDIS + 20 + 1 + + + CC2TCDIS + CC2TCDIS + 21 + 1 + + + + + IMR + IMR + UCPD Interrupt Mask Register + 0x10 + 0x20 + read-write + 0x00000000 + + + TXISIE + TXISIE + 0 + 1 + + + TXMSGDISCIE + TXMSGDISCIE + 1 + 1 + + + TXMSGSENTIE + TXMSGSENTIE + 2 + 1 + + + TXMSGABTIE + TXMSGABTIE + 3 + 1 + + + HRSTDISCIE + HRSTDISCIE + 4 + 1 + + + HRSTSENTIE + HRSTSENTIE + 5 + 1 + + + TXUNDIE + TXUNDIE + 6 + 1 + + + RXNEIE + RXNEIE + 8 + 1 + + + RXORDDETIE + RXORDDETIE + 9 + 1 + + + RXHRSTDETIE + RXHRSTDETIE + 10 + 1 + + + RXOVRIE + RXOVRIE + 11 + 1 + + + RXMSGENDIE + RXMSGENDIE + 12 + 1 + + + TYPECEVT1IE + TYPECEVT1IE + 14 + 1 + + + TYPECEVT2IE + TYPECEVT2IE + 15 + 1 + + + FRSEVTIE + FRSEVTIE + 20 + 1 + + + + + SR + SR + UCPD Status Register + 0x14 + 0x20 + read-write + 0x00000000 + + + TXIS + TXIS + 0 + 1 + + + TXMSGDISC + TXMSGDISC + 1 + 1 + + + TXMSGSENT + TXMSGSENT + 2 + 1 + + + TXMSGABT + TXMSGABT + 3 + 1 + + + HRSTDISC + HRSTDISC + 4 + 1 + + + HRSTSENT + HRSTSENT + 5 + 1 + + + TXUND + TXUND + 6 + 1 + + + RXNE + RXNE + 8 + 1 + + + RXORDDET + RXORDDET + 9 + 1 + + + RXHRSTDET + RXHRSTDET + 10 + 1 + + + RXOVR + RXOVR + 11 + 1 + + + RXMSGEND + RXMSGEND + 12 + 1 + + + RXERR + RXERR + 13 + 1 + + + TYPECEVT1 + TYPECEVT1 + 14 + 1 + + + TYPECEVT2 + TYPECEVT2 + 15 + 1 + + + TYPEC_VSTATE_CC1 + TYPEC_VSTATE_CC1 + 16 + 2 + + + TYPEC_VSTATE_CC2 + TYPEC_VSTATE_CC2 + 18 + 2 + + + FRSEVT + FRSEVT + 20 + 1 + + + + + ICR + ICR + UCPD Interrupt Clear Register + 0x18 + 0x20 + read-write + 0x00000000 + + + TXMSGDISCCF + TXMSGDISCCF + 1 + 1 + + + TXMSGSENTCF + TXMSGSENTCF + 2 + 1 + + + TXMSGABTCF + TXMSGABTCF + 3 + 1 + + + HRSTDISCCF + HRSTDISCCF + 4 + 1 + + + HRSTSENTCF + HRSTSENTCF + 5 + 1 + + + TXUNDCF + TXUNDCF + 6 + 1 + + + RXORDDETCF + RXORDDETCF + 9 + 1 + + + RXHRSTDETCF + RXHRSTDETCF + 10 + 1 + + + RXOVRCF + RXOVRCF + 11 + 1 + + + RXMSGENDCF + RXMSGENDCF + 12 + 1 + + + TYPECEVT1CF + TYPECEVT1CF + 14 + 1 + + + TYPECEVT2CF + TYPECEVT2CF + 15 + 1 + + + FRSEVTCF + FRSEVTCF + 20 + 1 + + + + + TX_ORDSET + TX_ORDSET + UCPD Tx Ordered Set Type Register + 0x1C + 0x20 + read-write + 0x00000000 + + + TXORDSET + TXORDSET + 0 + 20 + + + + + TX_PAYSZ + TX_PAYSZ + UCPD Tx Paysize Register + 0x20 + 0x20 + read-write + 0x00000000 + + + TXPAYSZ + TXPAYSZ + 0 + 10 + + + + + TXDR + TXDR + UCPD Tx Data Register + 0x24 + 0x20 + read-write + 0x00000000 + + + TXDATA + TXDATA + 0 + 8 + + + + + RX_ORDSET + RX_ORDSET + UCPD Rx Ordered Set Register + 0x28 + 0x20 + read-only + 0x00000000 + + + RXORDSET + RXORDSET + 0 + 3 + + + RXSOP3OF4 + RXSOP3OF4 + 3 + 1 + + + RXSOPKINVALID + RXSOPKINVALID + 4 + 3 + + + + + RX_PAYSZ + RX_PAYSZ + UCPD Rx Paysize Register + 0x2C + 0x20 + read-only + 0x00000000 + + + RXPAYSZ + RXPAYSZ + 0 + 10 + + + + + RXDR + RXDR + UCPD Rx Data Register + 0x30 + 0x20 + read-only + 0x00000000 + + + RXDATA + RXDATA + 0 + 8 + + + + + RX_ORDEXT1 + RX_ORDEXT1 + UCPD Rx Ordered Set Extension Register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + RXSOPX1 + RXSOPX1 + 0 + 20 + + + + + RX_ORDEXT2 + RX_ORDEXT2 + UCPD Rx Ordered Set Extension Register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + RXSOPX2 + RXSOPX2 + 0 + 20 + + + + + + + USB_FS_device + USB_FS_device + USB + 0x40005C00 + + 0x0 + 0x400 + registers + + + + EP0R + EP0R + USB endpoint n register + 0x0 + 0x20 + read-write + 0x00000000 + + + EA + EA + 0 + 4 + + + STAT_TX + STAT_TX + 4 + 2 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + EP_KIND + EP_KIND + 8 + 1 + + + EP_TYPE + EP_TYPE + 9 + 2 + + + SETUP + SETUP + 11 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + CTR_RX + CTR_RX + 15 + 1 + + + + + EP1R + EP1R + USB endpoint n register + 0x4 + 0x20 + read-write + 0x00000000 + + + EA + EA + 0 + 4 + + + STAT_TX + STAT_TX + 4 + 2 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + EP_KIND + EP_KIND + 8 + 1 + + + EP_TYPE + EP_TYPE + 9 + 2 + + + SETUP + SETUP + 11 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + CTR_RX + CTR_RX + 15 + 1 + + + + + EP2R + EP2R + USB endpoint n register + 0x8 + 0x20 + read-write + 0x00000000 + + + EA + EA + 0 + 4 + + + STAT_TX + STAT_TX + 4 + 2 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + EP_KIND + EP_KIND + 8 + 1 + + + EP_TYPE + EP_TYPE + 9 + 2 + + + SETUP + SETUP + 11 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + CTR_RX + CTR_RX + 15 + 1 + + + + + EP3R + EP3R + USB endpoint n register + 0xC + 0x20 + read-write + 0x00000000 + + + EA + EA + 0 + 4 + + + STAT_TX + STAT_TX + 4 + 2 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + EP_KIND + EP_KIND + 8 + 1 + + + EP_TYPE + EP_TYPE + 9 + 2 + + + SETUP + SETUP + 11 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + CTR_RX + CTR_RX + 15 + 1 + + + + + EP4R + EP4R + USB endpoint n register + 0x10 + 0x20 + read-write + 0x00000000 + + + EA + EA + 0 + 4 + + + STAT_TX + STAT_TX + 4 + 2 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + EP_KIND + EP_KIND + 8 + 1 + + + EP_TYPE + EP_TYPE + 9 + 2 + + + SETUP + SETUP + 11 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + CTR_RX + CTR_RX + 15 + 1 + + + + + EP5R + EP5R + USB endpoint n register + 0x14 + 0x20 + read-write + 0x00000000 + + + EA + EA + 0 + 4 + + + STAT_TX + STAT_TX + 4 + 2 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + EP_KIND + EP_KIND + 8 + 1 + + + EP_TYPE + EP_TYPE + 9 + 2 + + + SETUP + SETUP + 11 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + CTR_RX + CTR_RX + 15 + 1 + + + + + EP6R + EP6R + USB endpoint n register + 0x18 + 0x20 + read-write + 0x00000000 + + + EA + EA + 0 + 4 + + + STAT_TX + STAT_TX + 4 + 2 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + EP_KIND + EP_KIND + 8 + 1 + + + EP_TYPE + EP_TYPE + 9 + 2 + + + SETUP + SETUP + 11 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + CTR_RX + CTR_RX + 15 + 1 + + + + + EP7R + EP7R + USB endpoint n register + 0x1C + 0x20 + read-write + 0x00000000 + + + EA + EA + 0 + 4 + + + STAT_TX + STAT_TX + 4 + 2 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + EP_KIND + EP_KIND + 8 + 1 + + + EP_TYPE + EP_TYPE + 9 + 2 + + + SETUP + SETUP + 11 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + CTR_RX + CTR_RX + 15 + 1 + + + + + CNTR + CNTR + USB control register + 0x40 + 0x20 + read-write + 0x00000000 + + + FRES + FRES + 0 + 1 + + + PDWN + PDWN + 1 + 1 + + + LP_MODE + LP_MODE + 2 + 1 + + + FSUSP + FSUSP + 3 + 1 + + + RESUME + RESUME + 4 + 1 + + + L1RESUME + L1RESUME + 5 + 1 + + + L1REQM + L1REQM + 7 + 1 + + + ESOFM + ESOFM + 8 + 1 + + + SOFM + SOFM + 9 + 1 + + + RESETM + RESETM + 10 + 1 + + + SUSPM + SUSPM + 11 + 1 + + + WKUPM + WKUPM + 12 + 1 + + + ERRM + ERRM + 13 + 1 + + + PMAOVRM + PMAOVRM + 14 + 1 + + + CTRM + CTRM + 15 + 1 + + + + + ISTR + ISTR + USB interrupt status register + 0x44 + 0x20 + read-write + 0x00000000 + + + EP_ID + EP_ID + 0 + 4 + + + DIR + DIR + 4 + 1 + + + L1REQ + L1REQ + 7 + 1 + + + ESOF + ESOF + 8 + 1 + + + SOF + SOF + 9 + 1 + + + RESET + RESET + 10 + 1 + + + SUSP + SUSP + 11 + 1 + + + WKUP + WKUP + 12 + 1 + + + ERR + ERR + 13 + 1 + + + PMAOVR + PMAOVR + 14 + 1 + + + CTR + CTR + 15 + 1 + + + + + FNR + FNR + USB frame number register + 0x48 + 0x20 + read-only + 0x00000000 + + + FN + FN + 0 + 11 + + + LSOF + LSOF + 11 + 2 + + + LCK + LCK + 13 + 1 + + + RXDM + RXDM + 14 + 1 + + + RXDP + RXDP + 15 + 1 + + + + + DADDR + DADDR + USB device address + 0x4C + 0x20 + read-write + 0x00000000 + + + ADD + ADD + 0 + 7 + + + EF + EF + 7 + 1 + + + + + BTABLE + BTABLE + Buffer table address + 0x50 + 0x20 + read-write + 0x00000000 + + + BTABLE + BTABLE + 3 + 13 + + + + + + + CRS + CRS + CRS + 0x40002000 + + 0x0 + 0x400 + registers + + + + CR + CR + CRS control register + 0x0 + 0x20 + 0x00004000 + + + SYNCOKIE + SYNC event OK interrupt enable + 0 + 1 + read-write + + + SYNCWARNIE + SYNC warning interrupt enable + 1 + 1 + read-write + + + ERRIE + Synchronization or trimming error interrupt enable + 2 + 1 + read-write + + + ESYNCIE + Expected SYNC interrupt enable + 3 + 1 + read-write + + + CEN + Frequency error counter enable This bit enables the oscillator clock for the frequency error counter. When this bit is set, the CRS_CFGR register is write-protected and cannot be modified. + 5 + 1 + read-write + + + AUTOTRIMEN + Automatic trimming enable This bit enables the automatic hardware adjustment of TRIM bits according to the measured frequency error between two SYNC events. If this bit is set, the TRIM bits are read-only. The TRIM value can be adjusted by hardware by one or two steps at a time, depending on the measured frequency error value. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details. + 6 + 1 + read-write + + + SWSYNC + Generate software SYNC event This bit is set by software in order to generate a software SYNC event. It is automatically cleared by hardware. + 7 + 1 + read-write + + + TRIM + HSI48 oscillator smooth trimming These bits provide a user-programmable trimming value to the HSI48 oscillator. They can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI48. The default value is 32, which corresponds to the middle of the trimming interval. The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value corresponds to a higher output frequency. When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only. + 8 + 7 + read-write + + + + + CFGR + CFGR + This register can be written only when the frequency error counter is disabled (CEN bit is cleared in CRS_CR). When the counter is enabled, this register is write-protected. + 0x4 + 0x20 + read-write + 0x2022BB7F + + + RELOAD + Counter reload value RELOAD is the value to be loaded in the frequency error counter with each SYNC event. Refer to Section7.3.3: Frequency error measurement for more details about counter behavior. + 0 + 16 + + + FELIM + Frequency error limit FELIM contains the value to be used to evaluate the captured frequency error value latched in the FECAP[15:0] bits of the CRS_ISR register. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details about FECAP evaluation. + 16 + 8 + + + SYNCDIV + SYNC divider These bits are set and cleared by software to control the division factor of the SYNC signal. + 24 + 3 + + + SYNCSRC + SYNC signal source selection These bits are set and cleared by software to select the SYNC signal source. Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the periodic USB SOF will not be generated by the host. No SYNC signal will therefore be provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs should be used as SYNC signal. + 28 + 2 + + + SYNCPOL + SYNC polarity selection This bit is set and cleared by software to select the input polarity for the SYNC signal source. + 31 + 1 + + + + + ISR + ISR + CRS interrupt and status register + 0x8 + 0x20 + read-only + 0x00000000 + + + SYNCOKF + SYNC event OK flag This flag is set by hardware when the measured frequency error is smaller than FELIM * 3. This means that either no adjustment of the TRIM value is needed or that an adjustment by one trimming step is enough to compensate the frequency error. An interrupt is generated if the SYNCOKIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCOKC bit in the CRS_ICR register. + 0 + 1 + + + SYNCWARNF + SYNC warning flag This flag is set by hardware when the measured frequency error is greater than or equal to FELIM * 3, but smaller than FELIM * 128. This means that to compensate the frequency error, the TRIM value must be adjusted by two steps or more. An interrupt is generated if the SYNCWARNIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCWARNC bit in the CRS_ICR register. + 1 + 1 + + + ERRF + Error flag This flag is set by hardware in case of any synchronization or trimming error. It is the logical OR of the TRIMOVF, SYNCMISS and SYNCERR bits. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software in reaction to setting the ERRC bit in the CRS_ICR register, which clears the TRIMOVF, SYNCMISS and SYNCERR bits. + 2 + 1 + + + ESYNCF + Expected SYNC flag This flag is set by hardware when the frequency error counter reached a zero value. An interrupt is generated if the ESYNCIE bit is set in the CRS_CR register. It is cleared by software by setting the ESYNCC bit in the CRS_ICR register. + 3 + 1 + + + SYNCERR + SYNC error This flag is set by hardware when the SYNC pulse arrives before the ESYNC event and the measured frequency error is greater than or equal to FELIM * 128. This means that the frequency error is too big (internal frequency too low) to be compensated by adjusting the TRIM value, and that some other action should be taken. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. + 8 + 1 + + + SYNCMISS + SYNC missed This flag is set by hardware when the frequency error counter reached value FELIM * 128 and no SYNC was detected, meaning either that a SYNC pulse was missed or that the frequency error is too big (internal frequency too high) to be compensated by adjusting the TRIM value, and that some other action should be taken. At this point, the frequency error counter is stopped (waiting for a next SYNC) and an interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. + 9 + 1 + + + TRIMOVF + Trimming overflow or underflow This flag is set by hardware when the automatic trimming tries to over- or under-flow the TRIM value. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. + 10 + 1 + + + FEDIR + Frequency error direction FEDIR is the counting direction of the frequency error counter latched in the time of the last SYNC event. It shows whether the actual frequency is below or above the target. + 15 + 1 + + + FECAP + Frequency error capture FECAP is the frequency error counter value latched in the time ofthe last SYNC event. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details about FECAP usage. + 16 + 16 + + + + + ICR + ICR + CRS interrupt flag clear register + 0xC + 0x20 + read-write + 0x00000000 + + + SYNCOKC + SYNC event OK clear flag Writing 1 to this bit clears the SYNCOKF flag in the CRS_ISR register. + 0 + 1 + + + SYNCWARNC + SYNC warning clear flag Writing 1 to this bit clears the SYNCWARNF flag in the CRS_ISR register. + 1 + 1 + + + ERRC + Error clear flag Writing 1 to this bit clears TRIMOVF, SYNCMISS and SYNCERR bits and consequently also the ERRF flag in the CRS_ISR register. + 2 + 1 + + + ESYNCC + Expected SYNC clear flag Writing 1 to this bit clears the ESYNCF flag in the CRS_ISR register. + 3 + 1 + + + + + + + diff --git a/Lib/Vendor/SVD/STM32H523.svd b/Lib/Vendor/SVD/STM32H523.svd new file mode 100644 index 000000000..169652ad4 --- /dev/null +++ b/Lib/Vendor/SVD/STM32H523.svd @@ -0,0 +1,175071 @@ + + + + STM32H523 + 1.3 + STM32H523 + + CM33 + r0p0 + little + true + true + 4 + false + + 8 + 32 + 0x0 + 0xFFFFFFFF + + + ADC + ADC register block + ADC + 0x42028000 + + 0x0 + 0xCC + registers + + + ADC1 + ADC1 global interrupt + 37 + + + + ADC_ISR + ADC_ISR + ADC interrupt and status register + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ADRDY + ADC ready + + 0 + 1 + read-write + + + B_0x0 + ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + ADC is ready to start conversion + 0x1 + + + + + EOSMP + End of sampling flag + + 1 + 1 + read-write + + + B_0x0 + not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + End of sampling phase reached + 0x1 + + + + + EOC + End of conversion flag + + 2 + 1 + read-write + + + B_0x0 + Regular channel conversion not complete (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Regular channel conversion complete + 0x1 + + + + + EOS + End of regular sequence flag + + 3 + 1 + read-write + + + B_0x0 + Regular Conversions sequence not complete (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Regular Conversions sequence complete + 0x1 + + + + + OVR + ADC overrun + + 4 + 1 + read-write + + + B_0x0 + No overrun occurred (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Overrun has occurred + 0x1 + + + + + JEOC + Injected channel end of conversion flag + + 5 + 1 + read-write + + + B_0x0 + Injected channel conversion not complete (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Injected channel conversion complete + 0x1 + + + + + JEOS + Injected channel end of sequence flag + + 6 + 1 + read-write + + + B_0x0 + Injected conversion sequence not complete (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Injected conversions complete + 0x1 + + + + + AWD1 + Analog watchdog 1 flag + + 7 + 1 + read-write + + + B_0x0 + No analog watchdog 1 event occurred (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Analog watchdog 1 event occurred + 0x1 + + + + + AWD2 + Analog watchdog 2 flag + + 8 + 1 + read-write + + + B_0x0 + No analog watchdog 2 event occurred (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Analog watchdog 2 event occurred + 0x1 + + + + + AWD3 + Analog watchdog 3 flag + + 9 + 1 + read-write + + + B_0x0 + No analog watchdog 3 event occurred (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Analog watchdog 3 event occurred + 0x1 + + + + + JQOVF + Injected context queue overflow + + 10 + 1 + read-write + + + B_0x0 + No injected context queue overflow occurred (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Injected context queue overflow has occurred + 0x1 + + + + + + + ADC_IER + ADC_IER + ADC interrupt enable register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ADRDYIE + ADC ready interrupt enable + + 0 + 1 + read-write + + + B_0x0 + ADRDY interrupt disabled + 0x0 + + + B_0x1 + ADRDY interrupt enabled. + 0x1 + + + + + EOSMPIE + End of sampling flag interrupt enable for regular conversions + + 1 + 1 + read-write + + + B_0x0 + EOSMP interrupt disabled. + 0x0 + + + B_0x1 + EOSMP interrupt enabled. + 0x1 + + + + + EOCIE + End of regular conversion interrupt enable + + 2 + 1 + read-write + + + B_0x0 + EOC interrupt disabled. + 0x0 + + + B_0x1 + EOC interrupt enabled. + 0x1 + + + + + EOSIE + End of regular sequence of conversions interrupt enable + + 3 + 1 + read-write + + + B_0x0 + EOS interrupt disabled + 0x0 + + + B_0x1 + EOS interrupt enabled. + 0x1 + + + + + OVRIE + Overrun interrupt enable + + 4 + 1 + read-write + + + B_0x0 + Overrun interrupt disabled + 0x0 + + + B_0x1 + Overrun interrupt enabled. + 0x1 + + + + + JEOCIE + End of injected conversion interrupt enable + + 5 + 1 + read-write + + + B_0x0 + JEOC interrupt disabled. + 0x0 + + + B_0x1 + JEOC interrupt enabled. + 0x1 + + + + + JEOSIE + End of injected sequence of conversions interrupt enable + + 6 + 1 + read-write + + + B_0x0 + JEOS interrupt disabled + 0x0 + + + B_0x1 + JEOS interrupt enabled. + 0x1 + + + + + AWD1IE + Analog watchdog 1 interrupt enable + + 7 + 1 + read-write + + + B_0x0 + Analog watchdog 1 interrupt disabled + 0x0 + + + B_0x1 + Analog watchdog 1 interrupt enabled + 0x1 + + + + + AWD2IE + Analog watchdog 2 interrupt enable + + 8 + 1 + read-write + + + B_0x0 + Analog watchdog 2 interrupt disabled + 0x0 + + + B_0x1 + Analog watchdog 2 interrupt enabled + 0x1 + + + + + AWD3IE + Analog watchdog 3 interrupt enable + + 9 + 1 + read-write + + + B_0x0 + Analog watchdog 3 interrupt disabled + 0x0 + + + B_0x1 + Analog watchdog 3 interrupt enabled + 0x1 + + + + + JQOVFIE + Injected context queue overflow interrupt enable + + 10 + 1 + read-write + + + B_0x0 + Injected Context Queue Overflow interrupt disabled + 0x0 + + + B_0x1 + Injected Context Queue Overflow interrupt enabled. + 0x1 + + + + + + + ADC_CR + ADC_CR + ADC control register + 0x08 + 0x20 + read-write + 0x20000000 + 0xFFFFFFFF + + + ADEN + ADC enable control + + 0 + 1 + read-write + + + B_0x0 + ADC is disabled (OFF state) + 0x0 + + + B_0x1 + Write 1 to enable the ADC. + 0x1 + + + + + ADDIS + ADC disable command + + 1 + 1 + read-write + + + B_0x0 + no ADDIS command ongoing + 0x0 + + + B_0x1 + Write 1 to disable the ADC. + 0x1 + + + + + ADSTART + ADC start of regular conversion + + 2 + 1 + read-write + + + B_0x0 + No ADC regular conversion is ongoing. + 0x0 + + + B_0x1 + Write 1 to start regular conversions. + 0x1 + + + + + JADSTART + ADC start of injected conversion + + 3 + 1 + read-write + + + B_0x0 + No ADC injected conversion is ongoing. + 0x0 + + + B_0x1 + Write 1 to start injected conversions. + 0x1 + + + + + ADSTP + ADC stop of regular conversion command + + 4 + 1 + read-write + + + B_0x0 + No ADC stop regular conversion command ongoing + 0x0 + + + B_0x1 + Write 1 to stop regular conversions ongoing. + 0x1 + + + + + JADSTP + ADC stop of injected conversion command + + 5 + 1 + read-write + + + B_0x0 + No ADC stop injected conversion command ongoing + 0x0 + + + B_0x1 + Write 1 to stop injected conversions ongoing. + 0x1 + + + + + ADVREGEN + ADC voltage regulator enable + + 28 + 1 + read-write + + + B_0x0 + ADC Voltage regulator disabled + 0x0 + + + B_0x1 + ADC Voltage regulator enabled. + 0x1 + + + + + DEEPPWD + Deep-power-down enable + + 29 + 1 + read-write + + + B_0x0 + ADC not in Deep-power down + 0x0 + + + B_0x1 + ADC in Deep-power-down (default reset state) + 0x1 + + + + + ADCALDIF + Differential mode for calibration + + 30 + 1 + read-write + + + B_0x0 + Writing ADCAL launches a calibration in single-ended inputs mode. + 0x0 + + + B_0x1 + Writing ADCAL launches a calibration in Differential inputs mode. + 0x1 + + + + + ADCAL + ADC calibration + + 31 + 1 + read-write + + + B_0x0 + Calibration complete + 0x0 + + + B_0x1 + Write 1 to calibrate the ADC. + 0x1 + + + + + + + ADC_CFGR + ADC_CFGR + ADC configuration register + 0x0C + 0x20 + read-write + 0x80000000 + 0xFFFFFFFF + + + DMAEN + Direct memory access enable + + 0 + 1 + read-write + + + B_0x0 + DMA disabled + 0x0 + + + B_0x1 + DMA enabled + 0x1 + + + + + DMACFG + Direct memory access configuration + + 1 + 1 + read-write + + + B_0x0 + DMA One Shot mode selected + 0x0 + + + B_0x1 + DMA Circular mode selected + 0x1 + + + + + RES + Data resolution + + 3 + 2 + read-write + + + B_0x0 + 12-bit + 0x0 + + + B_0x1 + 10-bit + 0x1 + + + B_0x2 + 8-bit + 0x2 + + + B_0x3 + 6-bit + 0x3 + + + + + EXTSEL + External trigger selection for regular group +These bits select the external event used to trigger the start of conversion of a regular group: +... +Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + 5 + 5 + read-write + + + B_0x0 + adc_ext_trg0 + 0x0 + + + B_0x1 + adc_ext_trg1 + 0x1 + + + B_0x2 + adc_ext_trg2 + 0x2 + + + B_0x3 + adc_ext_trg3 + 0x3 + + + B_0x4 + adc_ext_trg4 + 0x4 + + + B_0x5 + adc_ext_trg5 + 0x5 + + + B_0x6 + adc_ext_trg6 + 0x6 + + + B_0x7 + adc_ext_trg7 + 0x7 + + + B_0x8 + adc_ext_trg8 + 0x8 + + + B_0x9 + adc_ext_trg9 + 0x9 + + + B_0xA + adc_ext_trg10 + 0xA + + + B_0xB + adc_ext_trg11 + 0xB + + + B_0xC + adc_ext_trg12 + 0xC + + + B_0xD + adc_ext_trg13 + 0xD + + + B_0xE + adc_ext_trg14 + 0xE + + + B_0xF + adc_ext_trg15 + 0xF + + + B_0x10 + adc_ext_trg16 + 0x10 + + + B_0x11 + adc_ext_trg17 + 0x11 + + + B_0x12 + adc_ext_trg18 + 0x12 + + + B_0x13 + adc_ext_trg19 + 0x13 + + + B_0x14 + adc_ext_trg20 + 0x14 + + + B_0x15 + adc_ext_trg21 + 0x15 + + + B_0x16 + adc_ext_trg22 + 0x16 + + + B_0x17 + adc_ext_trg23 + 0x17 + + + B_0x18 + adc_ext_trg24 + 0x18 + + + B_0x19 + adc_ext_trg25 + 0x19 + + + B_0x1A + adc_ext_trg26 + 0x1A + + + B_0x1B + adc_ext_trg27 + 0x1B + + + B_0x1C + adc_ext_trg28 + 0x1C + + + B_0x1D + adc_ext_trg29 + 0x1D + + + B_0x1E + adc_ext_trg30 + 0x1E + + + B_0x1F + adc_ext_trg31 + 0x1F + + + + + EXTEN + External trigger enable and polarity selection for regular channels + + 10 + 2 + read-write + + + B_0x0 + Hardware trigger detection disabled (conversions can be launched by software) + 0x0 + + + B_0x1 + Hardware trigger detection on the rising edge + 0x1 + + + B_0x2 + Hardware trigger detection on the falling edge + 0x2 + + + B_0x3 + Hardware trigger detection on both the rising and falling edges + 0x3 + + + + + OVRMOD + Overrun mode + + 12 + 1 + read-write + + + B_0x0 + ADC_DR register is preserved with the old data when an overrun is detected. + 0x0 + + + B_0x1 + ADC_DR register is overwritten with the last conversion result when an overrun is detected. + 0x1 + + + + + CONT + Single / continuous conversion mode for regular conversions + + 13 + 1 + read-write + + + B_0x0 + Single conversion mode + 0x0 + + + B_0x1 + Continuous conversion mode + 0x1 + + + + + AUTDLY + Delayed conversion mode + + 14 + 1 + read-write + + + B_0x0 + Auto-delayed conversion mode off + 0x0 + + + B_0x1 + Auto-delayed conversion mode on + 0x1 + + + + + ALIGN + Data alignment + + 15 + 1 + read-write + + + B_0x0 + Right alignment + 0x0 + + + B_0x1 + Left alignment + 0x1 + + + + + DISCEN + Discontinuous mode for regular channels + + 16 + 1 + read-write + + + B_0x0 + Discontinuous mode for regular channels disabled + 0x0 + + + B_0x1 + Discontinuous mode for regular channels enabled + 0x1 + + + + + DISCNUM + Discontinuous mode channel count + + 17 + 3 + read-write + + + B_0x0 + 1 channel + 0x0 + + + B_0x1 + 2 channels + 0x1 + + + B_0x7 + 8 channels + 0x7 + + + + + JDISCEN + Discontinuous mode on injected channels + + 20 + 1 + read-write + + + B_0x0 + Discontinuous mode on injected channels disabled + 0x0 + + + B_0x1 + Discontinuous mode on injected channels enabled + 0x1 + + + + + JQM + JSQR queue mode + + 21 + 1 + read-write + + + B_0x0 + JSQR mode 0: The Queue is never empty and maintains the last written configuration into JSQR. + 0x0 + + + B_0x1 + JSQR mode 1: The Queue can be empty and when this occurs, the software and hardware triggers of the injected sequence are both internally disabled just after the completion of the last valid injected sequence. + 0x1 + + + + + AWD1SGL + Enable the watchdog 1 on a single channel or on all channels + + 22 + 1 + read-write + + + B_0x0 + Analog watchdog 1 enabled on all channels + 0x0 + + + B_0x1 + Analog watchdog 1 enabled on a single channel + 0x1 + + + + + AWD1EN + Analog watchdog 1 enable on regular channels + + 23 + 1 + read-write + + + B_0x0 + Analog watchdog 1 disabled on regular channels + 0x0 + + + B_0x1 + Analog watchdog 1 enabled on regular channels + 0x1 + + + + + JAWD1EN + Analog watchdog 1 enable on injected channels + + 24 + 1 + read-write + + + B_0x0 + Analog watchdog 1 disabled on injected channels + 0x0 + + + B_0x1 + Analog watchdog 1 enabled on injected channels + 0x1 + + + + + JAUTO + Automatic injected group conversion + + 25 + 1 + read-write + + + B_0x0 + Automatic injected group conversion disabled + 0x0 + + + B_0x1 + Automatic injected group conversion enabled + 0x1 + + + + + AWD1CH + Analog watchdog 1 channel selection + + 26 + 5 + read-write + + + B_0x0 + ADC analog input channel 0 monitored by AWD1 (available on ADC1 only) + 0x0 + + + B_0x1 + ADC analog input channel 1 monitored by AWD1 + 0x1 + + + B_0x13 + ADC analog input channel 19 monitored by AWD1 + 0x13 + + + + + JQDIS + Injected queue disable + + 31 + 1 + read-write + + + B_0x0 + Injected queue enabled + 0x0 + + + B_0x1 + Injected queue disabled + 0x1 + + + + + + + ADC_CFGR2 + ADC_CFGR2 + ADC configuration register 2 + 0x10 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ROVSE + Regular oversampling Enable + + 0 + 1 + read-write + + + B_0x0 + Regular oversampling disabled + 0x0 + + + B_0x1 + Regular oversampling enabled + 0x1 + + + + + JOVSE + Injected oversampling Enable + + 1 + 1 + read-write + + + B_0x0 + Injected oversampling disabled + 0x0 + + + B_0x1 + Injected oversampling enabled + 0x1 + + + + + OVSR + Oversampling ratio + + 2 + 3 + read-write + + + B_0x0 + 2x + 0x0 + + + B_0x1 + 4x + 0x1 + + + B_0x2 + 8x + 0x2 + + + B_0x3 + 16x + 0x3 + + + B_0x4 + 32x + 0x4 + + + B_0x5 + 64x + 0x5 + + + B_0x6 + 128x + 0x6 + + + B_0x7 + 256x + 0x7 + + + + + OVSS + Oversampling shift + + 5 + 4 + read-write + + + B_0x0 + No shift + 0x0 + + + B_0x1 + Shift 1-bit + 0x1 + + + B_0x2 + Shift 2-bits + 0x2 + + + B_0x3 + Shift 3-bits + 0x3 + + + B_0x4 + Shift 4-bits + 0x4 + + + B_0x5 + Shift 5-bits + 0x5 + + + B_0x6 + Shift 6-bits + 0x6 + + + B_0x7 + Shift 7-bits + 0x7 + + + B_0x8 + Shift 8-bits + 0x8 + + + + + TROVS + Triggered Regular oversampling + + 9 + 1 + read-write + + + B_0x0 + All oversampled conversions for a channel are done consecutively following a trigger + 0x0 + + + B_0x1 + Each oversampled conversion for a channel needs a new trigger + 0x1 + + + + + ROVSM + Regular oversampling mode + + 10 + 1 + read-write + + + B_0x0 + Continued mode: When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence) + 0x0 + + + B_0x1 + Resumed mode: When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start) + 0x1 + + + + + SWTRIG + Software trigger bit for sampling time control trigger mode + + 25 + 1 + read-write + + + B_0x0 + Software trigger starts the conversion for sampling time control trigger mode + 0x0 + + + B_0x1 + Software trigger starts the sampling for sampling time control trigger mode + 0x1 + + + + + BULB + Bulb sampling mode + + 26 + 1 + read-write + + + B_0x0 + Bulb sampling mode disabled + 0x0 + + + B_0x1 + Bulb sampling mode enabled. + 0x1 + + + + + SMPTRIG + Sampling time control trigger mode + + 27 + 1 + read-write + + + B_0x0 + Sampling time control trigger mode disabled + 0x0 + + + B_0x1 + Sampling time control trigger mode enabled + 0x1 + + + + + + + ADC_SMPR1 + ADC_SMPR1 + ADC sample time register 1 + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SMP0 + Channel x sampling time selection (x=9 to 0) + + 0 + 3 + read-write + + + B_0x0 + 2. + 0x0 + + + B_0x1 + 6. + 0x1 + + + B_0x2 + 12. + 0x2 + + + B_0x3 + 24. + 0x3 + + + B_0x4 + 47. + 0x4 + + + B_0x5 + 92. + 0x5 + + + B_0x6 + 247. + 0x6 + + + B_0x7 + 640. + 0x7 + + + + + SMP1 + Channel x sampling time selection (x=9 to 0) + + 3 + 3 + read-write + + + B_0x0 + 2. + 0x0 + + + B_0x1 + 6. + 0x1 + + + B_0x2 + 12. + 0x2 + + + B_0x3 + 24. + 0x3 + + + B_0x4 + 47. + 0x4 + + + B_0x5 + 92. + 0x5 + + + B_0x6 + 247. + 0x6 + + + B_0x7 + 640. + 0x7 + + + + + SMP2 + Channel x sampling time selection (x=9 to 0) + + 6 + 3 + read-write + + + B_0x0 + 2. + 0x0 + + + B_0x1 + 6. + 0x1 + + + B_0x2 + 12. + 0x2 + + + B_0x3 + 24. + 0x3 + + + B_0x4 + 47. + 0x4 + + + B_0x5 + 92. + 0x5 + + + B_0x6 + 247. + 0x6 + + + B_0x7 + 640. + 0x7 + + + + + SMP3 + Channel x sampling time selection (x=9 to 0) + + 9 + 3 + read-write + + + B_0x0 + 2. + 0x0 + + + B_0x1 + 6. + 0x1 + + + B_0x2 + 12. + 0x2 + + + B_0x3 + 24. + 0x3 + + + B_0x4 + 47. + 0x4 + + + B_0x5 + 92. + 0x5 + + + B_0x6 + 247. + 0x6 + + + B_0x7 + 640. + 0x7 + + + + + SMP4 + Channel x sampling time selection (x=9 to 0) + + 12 + 3 + read-write + + + B_0x0 + 2. + 0x0 + + + B_0x1 + 6. + 0x1 + + + B_0x2 + 12. + 0x2 + + + B_0x3 + 24. + 0x3 + + + B_0x4 + 47. + 0x4 + + + B_0x5 + 92. + 0x5 + + + B_0x6 + 247. + 0x6 + + + B_0x7 + 640. + 0x7 + + + + + SMP5 + Channel x sampling time selection (x=9 to 0) + + 15 + 3 + read-write + + + B_0x0 + 2. + 0x0 + + + B_0x1 + 6. + 0x1 + + + B_0x2 + 12. + 0x2 + + + B_0x3 + 24. + 0x3 + + + B_0x4 + 47. + 0x4 + + + B_0x5 + 92. + 0x5 + + + B_0x6 + 247. + 0x6 + + + B_0x7 + 640. + 0x7 + + + + + SMP6 + Channel x sampling time selection (x=9 to 0) + + 18 + 3 + read-write + + + B_0x0 + 2. + 0x0 + + + B_0x1 + 6. + 0x1 + + + B_0x2 + 12. + 0x2 + + + B_0x3 + 24. + 0x3 + + + B_0x4 + 47. + 0x4 + + + B_0x5 + 92. + 0x5 + + + B_0x6 + 247. + 0x6 + + + B_0x7 + 640. + 0x7 + + + + + SMP7 + Channel x sampling time selection (x=9 to 0) + + 21 + 3 + read-write + + + B_0x0 + 2. + 0x0 + + + B_0x1 + 6. + 0x1 + + + B_0x2 + 12. + 0x2 + + + B_0x3 + 24. + 0x3 + + + B_0x4 + 47. + 0x4 + + + B_0x5 + 92. + 0x5 + + + B_0x6 + 247. + 0x6 + + + B_0x7 + 640. + 0x7 + + + + + SMP8 + Channel x sampling time selection (x=9 to 0) + + 24 + 3 + read-write + + + B_0x0 + 2. + 0x0 + + + B_0x1 + 6. + 0x1 + + + B_0x2 + 12. + 0x2 + + + B_0x3 + 24. + 0x3 + + + B_0x4 + 47. + 0x4 + + + B_0x5 + 92. + 0x5 + + + B_0x6 + 247. + 0x6 + + + B_0x7 + 640. + 0x7 + + + + + SMP9 + Channel x sampling time selection (x=9 to 0) + + 27 + 3 + read-write + + + B_0x0 + 2. + 0x0 + + + B_0x1 + 6. + 0x1 + + + B_0x2 + 12. + 0x2 + + + B_0x3 + 24. + 0x3 + + + B_0x4 + 47. + 0x4 + + + B_0x5 + 92. + 0x5 + + + B_0x6 + 247. + 0x6 + + + B_0x7 + 640. + 0x7 + + + + + SMPPLUS + Addition of one clock cycle to the sampling time. + 31 + 1 + read-write + + + B_0x1 + 2. + 0x1 + + + B_0x0 + The sampling time remains set to 2. + 0x0 + + + + + + + ADC_SMPR2 + ADC_SMPR2 + ADC sample time register 2 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SMP10 + Channel x sampling time selection (x=19 to 10) + + 0 + 3 + read-write + + + B_0x0 + 2. + 0x0 + + + B_0x1 + 6. + 0x1 + + + B_0x2 + 12. + 0x2 + + + B_0x3 + 24. + 0x3 + + + B_0x4 + 47. + 0x4 + + + B_0x5 + 92. + 0x5 + + + B_0x6 + 247. + 0x6 + + + B_0x7 + 640. + 0x7 + + + + + SMP11 + Channel x sampling time selection (x=19 to 10) + + 3 + 3 + read-write + + + B_0x0 + 2. + 0x0 + + + B_0x1 + 6. + 0x1 + + + B_0x2 + 12. + 0x2 + + + B_0x3 + 24. + 0x3 + + + B_0x4 + 47. + 0x4 + + + B_0x5 + 92. + 0x5 + + + B_0x6 + 247. + 0x6 + + + B_0x7 + 640. + 0x7 + + + + + SMP12 + Channel x sampling time selection (x=19 to 10) + + 6 + 3 + read-write + + + B_0x0 + 2. + 0x0 + + + B_0x1 + 6. + 0x1 + + + B_0x2 + 12. + 0x2 + + + B_0x3 + 24. + 0x3 + + + B_0x4 + 47. + 0x4 + + + B_0x5 + 92. + 0x5 + + + B_0x6 + 247. + 0x6 + + + B_0x7 + 640. + 0x7 + + + + + SMP13 + Channel x sampling time selection (x=19 to 10) + + 9 + 3 + read-write + + + B_0x0 + 2. + 0x0 + + + B_0x1 + 6. + 0x1 + + + B_0x2 + 12. + 0x2 + + + B_0x3 + 24. + 0x3 + + + B_0x4 + 47. + 0x4 + + + B_0x5 + 92. + 0x5 + + + B_0x6 + 247. + 0x6 + + + B_0x7 + 640. + 0x7 + + + + + SMP14 + Channel x sampling time selection (x=19 to 10) + + 12 + 3 + read-write + + + B_0x0 + 2. + 0x0 + + + B_0x1 + 6. + 0x1 + + + B_0x2 + 12. + 0x2 + + + B_0x3 + 24. + 0x3 + + + B_0x4 + 47. + 0x4 + + + B_0x5 + 92. + 0x5 + + + B_0x6 + 247. + 0x6 + + + B_0x7 + 640. + 0x7 + + + + + SMP15 + Channel x sampling time selection (x=19 to 10) + + 15 + 3 + read-write + + + B_0x0 + 2. + 0x0 + + + B_0x1 + 6. + 0x1 + + + B_0x2 + 12. + 0x2 + + + B_0x3 + 24. + 0x3 + + + B_0x4 + 47. + 0x4 + + + B_0x5 + 92. + 0x5 + + + B_0x6 + 247. + 0x6 + + + B_0x7 + 640. + 0x7 + + + + + SMP16 + Channel x sampling time selection (x=19 to 10) + + 18 + 3 + read-write + + + B_0x0 + 2. + 0x0 + + + B_0x1 + 6. + 0x1 + + + B_0x2 + 12. + 0x2 + + + B_0x3 + 24. + 0x3 + + + B_0x4 + 47. + 0x4 + + + B_0x5 + 92. + 0x5 + + + B_0x6 + 247. + 0x6 + + + B_0x7 + 640. + 0x7 + + + + + SMP17 + Channel x sampling time selection (x=19 to 10) + + 21 + 3 + read-write + + + B_0x0 + 2. + 0x0 + + + B_0x1 + 6. + 0x1 + + + B_0x2 + 12. + 0x2 + + + B_0x3 + 24. + 0x3 + + + B_0x4 + 47. + 0x4 + + + B_0x5 + 92. + 0x5 + + + B_0x6 + 247. + 0x6 + + + B_0x7 + 640. + 0x7 + + + + + SMP18 + Channel x sampling time selection (x=19 to 10) + + 24 + 3 + read-write + + + B_0x0 + 2. + 0x0 + + + B_0x1 + 6. + 0x1 + + + B_0x2 + 12. + 0x2 + + + B_0x3 + 24. + 0x3 + + + B_0x4 + 47. + 0x4 + + + B_0x5 + 92. + 0x5 + + + B_0x6 + 247. + 0x6 + + + B_0x7 + 640. + 0x7 + + + + + SMP19 + Channel x sampling time selection (x=19 to 10) + + 27 + 3 + read-write + + + B_0x0 + 2. + 0x0 + + + B_0x1 + 6. + 0x1 + + + B_0x2 + 12. + 0x2 + + + B_0x3 + 24. + 0x3 + + + B_0x4 + 47. + 0x4 + + + B_0x5 + 92. + 0x5 + + + B_0x6 + 247. + 0x6 + + + B_0x7 + 640. + 0x7 + + + + + + + ADC_TR1 + ADC_TR1 + ADC watchdog threshold register 1 + 0x20 + 0x20 + read-write + 0x0FFF0000 + 0xFFFFFFFF + + + LT1 + Analog watchdog 1 lower threshold + + 0 + 12 + read-write + + + AWDFILT + Analog watchdog filtering parameter + + 12 + 3 + read-write + + + B_0x0 + No filtering + 0x0 + + + B_0x1 + two consecutive detection generates an AWDx flag or an interrupt + 0x1 + + + B_0x7 + Eight consecutive detection generates an AWDx flag or an interrupt + 0x7 + + + + + HT1 + Analog watchdog 1 higher threshold + + 16 + 12 + read-write + + + + + ADC_TR2 + ADC_TR2 + ADC watchdog threshold register 2 + 0x24 + 0x20 + read-write + 0x00FF0000 + 0xFFFFFFFF + + + LT2 + Analog watchdog 2 lower threshold + + 0 + 8 + read-write + + + HT2 + Analog watchdog 2 higher threshold + + 16 + 8 + read-write + + + + + ADC_TR3 + ADC_TR3 + ADC watchdog threshold register 3 + 0x28 + 0x20 + read-write + 0x00FF0000 + 0xFFFFFFFF + + + LT3 + Analog watchdog 3 lower threshold + + 0 + 8 + read-write + + + HT3 + Analog watchdog 3 higher threshold + + 16 + 8 + read-write + + + + + ADC_SQR1 + ADC_SQR1 + ADC regular sequence register 1 + 0x30 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + L + Regular channel sequence length + + 0 + 4 + read-write + + + B_0x0 + 1 conversion + 0x0 + + + B_0x1 + 2 conversions + 0x1 + + + B_0xF + 16 conversions + 0xF + + + + + SQ1 + 1st conversion in regular sequence + + 6 + 5 + read-write + + + SQ2 + 2nd conversion in regular sequence + + 12 + 5 + read-write + + + SQ3 + 3rd conversion in regular sequence + + 18 + 5 + read-write + + + SQ4 + 4th conversion in regular sequence + + 24 + 5 + read-write + + + + + ADC_SQR2 + ADC_SQR2 + ADC regular sequence register 2 + 0x34 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SQ5 + 5th conversion in regular sequence + + 0 + 5 + read-write + + + SQ6 + 6th conversion in regular sequence + + 6 + 5 + read-write + + + SQ7 + 7th conversion in regular sequence + + 12 + 5 + read-write + + + SQ8 + 8th conversion in regular sequence + + 18 + 5 + read-write + + + SQ9 + 9th conversion in regular sequence + + 24 + 5 + read-write + + + + + ADC_SQR3 + ADC_SQR3 + ADC regular sequence register 3 + 0x38 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SQ10 + 10th conversion in regular sequence + + 0 + 5 + read-write + + + SQ11 + 11th conversion in regular sequence + + 6 + 5 + read-write + + + SQ12 + 12th conversion in regular sequence + + 12 + 5 + read-write + + + SQ13 + 13th conversion in regular sequence + + 18 + 5 + read-write + + + SQ14 + 14th conversion in regular sequence + + 24 + 5 + read-write + + + + + ADC_SQR4 + ADC_SQR4 + ADC regular sequence register 4 + 0x3C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SQ15 + 15th conversion in regular sequence + + 0 + 5 + read-write + + + SQ16 + 16th conversion in regular sequence + + 6 + 5 + read-write + + + + + ADC_DR + ADC_DR + ADC regular data register + 0x40 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RDATA + Regular data converted + + 0 + 16 + read-only + + + + + ADC_JSQR + ADC_JSQR + ADC injected sequence register + 0x4C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + JL + Injected channel sequence length + + 0 + 2 + read-write + + + B_0x0 + 1 conversion + 0x0 + + + B_0x1 + 2 conversions + 0x1 + + + B_0x2 + 3 conversions + 0x2 + + + B_0x3 + 4 conversions + 0x3 + + + + + JEXTSEL + External Trigger Selection for injected group + + 2 + 5 + read-write + + + B_0x0 + adc_jext_trg0 + 0x0 + + + B_0x1 + adc_jext_trg1 + 0x1 + + + B_0x2 + adc_jext_trg2 + 0x2 + + + B_0x3 + adc_jext_trg3 + 0x3 + + + B_0x4 + adc_jext_trg4 + 0x4 + + + B_0x5 + adc_jext_trg5 + 0x5 + + + B_0x6 + adc_jext_trg6 + 0x6 + + + B_0x7 + adc_jext_trg7 + 0x7 + + + B_0x1F + adc_jext_trg31 + 0x1F + + + + + JEXTEN + External trigger enable and polarity selection for injected channels + + 7 + 2 + read-write + + + B_0x0 + If JQDIS=0 (queue enabled), hardware and software trigger detection disabled. + 0x0 + + + B_0x1 + Hardware trigger detection on the rising edge + 0x1 + + + B_0x2 + Hardware trigger detection on the falling edge + 0x2 + + + B_0x3 + Hardware trigger detection on both the rising and falling edges + 0x3 + + + + + JSQ1 + 1st conversion in the injected sequence + + 9 + 5 + read-write + + + JSQ2 + 2nd conversion in the injected sequence + + 15 + 5 + read-write + + + JSQ3 + 3rd conversion in the injected sequence + + 21 + 5 + read-write + + + JSQ4 + 4th conversion in the injected sequence + + 27 + 5 + read-write + + + + + ADC_OFR1 + ADC_OFR1 + ADC offset 1 register + 0x60 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OFFSET + Data offset y for the channel programmed into bits OFFSET_CH[4:0] + + 0 + 12 + read-write + + + OFFSETPOS + Positive offset + + 24 + 1 + read-write + + + B_0x0 + Negative offset + 0x0 + + + B_0x1 + Positive offset + 0x1 + + + + + SATEN + Saturation enable + + 25 + 1 + read-write + + + B_0x0 + No saturation control, offset result can be signed + 0x0 + + + B_0x1 + Saturation enabled, offset result unsigned and saturated at 0x000 and 0xFFF + 0x1 + + + + + OFFSET_CH + Channel selection for the data offset y + + 26 + 5 + read-write + + + OFFSET_EN + Offset y enable + + 31 + 1 + read-write + + + + + ADC_OFR2 + ADC_OFR2 + ADC offset 2 register + 0x64 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OFFSET + Data offset y for the channel programmed into bits OFFSET_CH[4:0] + + 0 + 12 + read-write + + + OFFSETPOS + Positive offset + + 24 + 1 + read-write + + + B_0x0 + Negative offset + 0x0 + + + B_0x1 + Positive offset + 0x1 + + + + + SATEN + Saturation enable + + 25 + 1 + read-write + + + B_0x0 + No saturation control, offset result can be signed + 0x0 + + + B_0x1 + Saturation enabled, offset result unsigned and saturated at 0x000 and 0xFFF + 0x1 + + + + + OFFSET_CH + Channel selection for the data offset y + + 26 + 5 + read-write + + + OFFSET_EN + Offset y enable + + 31 + 1 + read-write + + + + + ADC_OFR3 + ADC_OFR3 + ADC offset 3 register + 0x68 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OFFSET + Data offset y for the channel programmed into bits OFFSET_CH[4:0] + + 0 + 12 + read-write + + + OFFSETPOS + Positive offset + + 24 + 1 + read-write + + + B_0x0 + Negative offset + 0x0 + + + B_0x1 + Positive offset + 0x1 + + + + + SATEN + Saturation enable + + 25 + 1 + read-write + + + B_0x0 + No saturation control, offset result can be signed + 0x0 + + + B_0x1 + Saturation enabled, offset result unsigned and saturated at 0x000 and 0xFFF + 0x1 + + + + + OFFSET_CH + Channel selection for the data offset y + + 26 + 5 + read-write + + + OFFSET_EN + Offset y enable + + 31 + 1 + read-write + + + + + ADC_OFR4 + ADC_OFR4 + ADC offset 4 register + 0x6C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OFFSET + Data offset y for the channel programmed into bits OFFSET_CH[4:0] + + 0 + 12 + read-write + + + OFFSETPOS + Positive offset + + 24 + 1 + read-write + + + B_0x0 + Negative offset + 0x0 + + + B_0x1 + Positive offset + 0x1 + + + + + SATEN + Saturation enable + + 25 + 1 + read-write + + + B_0x0 + No saturation control, offset result can be signed + 0x0 + + + B_0x1 + Saturation enabled, offset result unsigned and saturated at 0x000 and 0xFFF + 0x1 + + + + + OFFSET_CH + Channel selection for the data offset y + + 26 + 5 + read-write + + + OFFSET_EN + Offset y enable + + 31 + 1 + read-write + + + + + ADC_JDR1 + ADC_JDR1 + ADC injected channel 1 data register + 0x80 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + JDATA + Injected data + + 0 + 16 + read-only + + + + + ADC_JDR2 + ADC_JDR2 + ADC injected channel 2 data register + 0x84 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + JDATA + Injected data + + 0 + 16 + read-only + + + + + ADC_JDR3 + ADC_JDR3 + ADC injected channel 3 data register + 0x88 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + JDATA + Injected data + + 0 + 16 + read-only + + + + + ADC_JDR4 + ADC_JDR4 + ADC injected channel 4 data register + 0x8C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + JDATA + Injected data + + 0 + 16 + read-only + + + + + ADC_AWD2CR + ADC_AWD2CR + ADC analog watchdog 2 configuration register + 0xA0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AWD2CH + Analog watchdog 2 channel selection + + 0 + 20 + read-write + + + + + ADC_AWD3CR + ADC_AWD3CR + ADC analog watchdog 3 configuration register + 0xA4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AWD3CH + Analog watchdog 3 channel selection + + 0 + 20 + read-write + + + + + ADC_DIFSEL + ADC_DIFSEL + ADC Differential mode selection register + 0xB0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DIFSEL + Differential mode for channels 19 to 0. + 0 + 20 + read-write + + + + + ADC_CALFACT + ADC_CALFACT + ADC calibration factors + 0xB4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CALFACT_S + Calibration Factors In single-ended mode + + 0 + 7 + read-write + + + CALFACT_D + Calibration Factors in differential mode + + 16 + 7 + read-write + + + + + ADC_OR + ADC_OR + ADC option register + 0xC8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OP0 + Option bit 0 + + 0 + 1 + read-write + + + B_0x0 + Vless thansub>DDCORE less than/sub>channel disabled + 0x0 + + + B_0x1 + Vless thansub>DDCORE less than/sub>channel enabled + 0x1 + + + + + + + + + ADC_S + 0X52028000 + + + ADC2 + 0x42028100 + + ADC2 + ADC2 global interrupt + 69 + + + + ADC2_S + 0x52028100 + + + ADCC + ADC common registers block + ADC + 0x42028300 + + 0x0 + 0x100 + registers + + + + ADC_CSR + ADC_CSR + ADC common status register + 0x000 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + ADRDY_MST + Master ADC ready + + 0 + 1 + read-only + + + EOSMP_MST + End of Sampling phase flag of the master ADC + + 1 + 1 + read-only + + + EOC_MST + End of regular conversion of the master ADC + + 2 + 1 + read-only + + + EOS_MST + End of regular sequence flag of the master ADC + + 3 + 1 + read-only + + + OVR_MST + Overrun flag of the master ADC + + 4 + 1 + read-only + + + JEOC_MST + End of injected conversion flag of the master ADC + + 5 + 1 + read-only + + + JEOS_MST + End of injected sequence flag of the master ADC + + 6 + 1 + read-only + + + AWD1_MST + Analog watchdog 1 flag of the master ADC + + 7 + 1 + read-only + + + AWD2_MST + Analog watchdog 2 flag of the master ADC + + 8 + 1 + read-only + + + AWD3_MST + Analog watchdog 3 flag of the master ADC + + 9 + 1 + read-only + + + JQOVF_MST + Injected Context Queue Overflow flag of the master ADC + + 10 + 1 + read-only + + + ADRDY_SLV + Slave ADC ready + + 16 + 1 + read-only + + + EOSMP_SLV + End of Sampling phase flag of the slave ADC + + 17 + 1 + read-only + + + EOC_SLV + End of regular conversion of the slave ADC + + 18 + 1 + read-only + + + EOS_SLV + End of regular sequence flag of the slave ADC. + 19 + 1 + read-only + + + OVR_SLV + Overrun flag of the slave ADC + + 20 + 1 + read-only + + + JEOC_SLV + End of injected conversion flag of the slave ADC + + 21 + 1 + read-only + + + JEOS_SLV + End of injected sequence flag of the slave ADC + + 22 + 1 + read-only + + + AWD1_SLV + Analog watchdog 1 flag of the slave ADC + + 23 + 1 + read-only + + + AWD2_SLV + Analog watchdog 2 flag of the slave ADC + + 24 + 1 + read-only + + + AWD3_SLV + Analog watchdog 3 flag of the slave ADC + + 25 + 1 + read-only + + + JQOVF_SLV + Injected Context Queue Overflow flag of the slave ADC + + 26 + 1 + read-only + + + + + ADC_CCR + ADC_CCR + ADC common control register + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DUAL + Dual ADC mode selection + + 0 + 5 + read-write + + + B_0x0 + Independent mode + 0x0 + + + B_0x1 + Combined regular simultaneous + injected simultaneous mode + 0x1 + + + B_0x2 + Combined regular simultaneous + alternate trigger mode + 0x2 + + + B_0x3 + Combined interleaved mode + injected simultaneous mode + 0x3 + + + B_0x5 + Injected simultaneous mode only + 0x5 + + + B_0x6 + Regular simultaneous mode only + 0x6 + + + B_0x7 + Interleaved mode only + 0x7 + + + B_0x9 + Alternate trigger mode only + 0x9 + + + + + DELAY + Delay between 2 sampling phases + + 8 + 4 + read-write + + + DMACFG + DMA configuration (for dual ADC mode) + + 13 + 1 + read-write + + + B_0x0 + DMA One Shot mode selected + 0x0 + + + B_0x1 + DMA Circular mode selected + 0x1 + + + + + MDMA + Direct memory access mode for dual ADC mode + + 14 + 2 + read-write + + + B_0x0 + MDMA mode disabled + 0x0 + + + B_0x2 + MDMA mode enabled for 12 and 10-bit resolution + 0x2 + + + B_0x3 + MDMA mode enabled for 8 and 6-bit resolution + 0x3 + + + + + CKMODE + ADC clock mode + + 16 + 2 + read-write + + + B_0x0 + adc_ker_ck (x = 1/2) (Asynchronous clock mode), generated at product level (refer to Section6: Reset and clock control (RCC)) + 0x0 + + + B_0x1 + adc_hclk/1 (Synchronous clock mode). + 0x1 + + + B_0x2 + adc_hclk/2 (Synchronous clock mode) + 0x2 + + + B_0x3 + adc_hclk/4 (Synchronous clock mode) + 0x3 + + + + + PRESC + ADC prescaler + + 18 + 4 + read-write + + + B_0x0 + input ADC clock not divided + 0x0 + + + B_0x1 + input ADC clock divided by 2 + 0x1 + + + B_0x2 + input ADC clock divided by 4 + 0x2 + + + B_0x3 + input ADC clock divided by 6 + 0x3 + + + B_0x4 + input ADC clock divided by 8 + 0x4 + + + B_0x5 + input ADC clock divided by 10 + 0x5 + + + B_0x6 + input ADC clock divided by 12 + 0x6 + + + B_0x7 + input ADC clock divided by 16 + 0x7 + + + B_0x8 + input ADC clock divided by 32 + 0x8 + + + B_0x9 + input ADC clock divided by 64 + 0x9 + + + B_0xA + input ADC clock divided by 128 + 0xA + + + B_0xB + input ADC clock divided by 256 + 0xB + + + + + VREFEN + Vless thansub>REFINTless than/sub> enable + + 22 + 1 + read-write + + + B_0x0 + Vless thansub>REFINTless than/sub> channel disabled + 0x0 + + + B_0x1 + Vless thansub>REFINTless than/sub> channel enabled + 0x1 + + + + + TSEN + Vless thansub>SENSEless than/sub> enable + + 23 + 1 + read-write + + + B_0x0 + Temperature sensor channel disabled + 0x0 + + + B_0x1 + Temperature sensor channel enabled + 0x1 + + + + + VBATEN + VBAT enable + + 24 + 1 + read-write + + + B_0x0 + Vless thansub>BATless than/sub> channel disabled + 0x0 + + + B_0x1 + Vless thansub>BATless than/sub> channel enabled + 0x1 + + + + + + + ADC_CDR + ADC_CDR + ADC common regular data register for dual mode + 0x00C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RDATA_MST + Regular data of the master ADC. + 0 + 16 + read-only + + + RDATA_SLV + Regular data of the slave ADC + + 16 + 16 + read-only + + + + + ADC_HWCFGR0 + ADC_HWCFGR0 + ADC hardware configuration register + 0x0F0 + 0x20 + read-only + 0x00001212 + 0xFFFFFFFF + + + ADCNUM + Number of ADCs implemented + 0 + 4 + read-only + + + B_0x1 + One ADC instance implemented + 0x1 + + + B_0x2 + Two ADC instances implemented + 0x2 + + + B_0x3 + Three ADCs instances implemented + 0x3 + + + + + MULPIPE + Number of pipeline stages + 4 + 4 + read-only + + + B_0x1 + One-stage pipeline + 0x1 + + + + + OPBITS + Number of option bits + 8 + 4 + read-only + + + B_0x0 + No option register implemented + 0x0 + + + B_0x1 + 1 option bit implemented in the ADC option register (ADC_OR) at address offset 0xC8 + 0x1 + + + + + IDLEVALUE + Idle value for non-selected channels + 12 + 4 + read-only + + + B_0x0 + Dummy channel selection is 0x13 + 0x0 + + + B_0x1 + Dummy channel selection is 0x1F + 0x1 + + + + + + + ADC_VERR + ADC_VERR + ADC version register + 0x0F4 + 0x20 + read-only + 0x00000012 + 0xFFFFFFFF + + + MINREV + Minor revision + + 0 + 4 + read-only + + + B_0x1 + Minor revision = X. + 0x1 + + + + + MAJREV + Major revision + + 4 + 4 + read-only + + + B_0x1 + Major revision = 1. + 0x1 + + + + + + + ADC_IPDR + ADC_IPDR + ADC identification register + 0x0F8 + 0x20 + read-only + 0x00110006 + 0xFFFFFFFF + + + ID + Peripheral identifier + + 0 + 32 + read-only + + + + + ADC_SIDR + ADC_SIDR + ADC size identification register + 0x0FC + 0x20 + read-only + 0xA3C5DD01 + 0xFFFFFFFF + + + SID + Size Identification + + 0 + 32 + read-only + + + B_0x01 + 1Kbytes address offset + 0x01 + + + B_0x02 + 2Kbytes address offset + 0x02 + + + B_0x04 + 4Kbytes address offset + 0x04 + + + B_0x08 + 8 Kbytes address offset + 0x08 + + + + + + + + + SEC_ADCC + 0x52028300 + + + CRC + CRC address block description + CRC + 0x40023000 + + 0x0 + 0x18 + registers + + + + CRC_DR + CRC_DR + CRC data register + 0x00 + 0x20 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + DR + Data register bits + + 0 + 32 + read-write + + + + + CRC_IDR + CRC_IDR + CRC independent data register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IDR + General-purpose 32-bit data register bits + + 0 + 32 + read-write + + + + + CRC_CR + CRC_CR + CRC control register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RESET + RESET bit + + 0 + 1 + read-write + + + POLYSIZE + Polynomial size + + 3 + 2 + read-write + + + B_0x0 + 32 bit polynomial + 0x0 + + + B_0x1 + 16 bit polynomial + 0x1 + + + B_0x2 + 8 bit polynomial + 0x2 + + + B_0x3 + 7 bit polynomial + 0x3 + + + + + REV_IN + Reverse input data + + 5 + 2 + read-write + + + B_0x0 + Bit order not affected + 0x0 + + + B_0x1 + Bit reversal done by byte + 0x1 + + + B_0x2 + Bit reversal done by half-word + 0x2 + + + B_0x3 + Bit reversal done by word + 0x3 + + + + + REV_OUT + Reverse output data + + 7 + 1 + read-write + + + B_0x0 + Bit order not affected + 0x0 + + + B_0x1 + Bit-reversed output format + 0x1 + + + + + + + CRC_INIT + CRC_INIT + CRC initial value + 0x10 + 0x20 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CRC_INIT + Programmable initial CRC value + + 0 + 32 + read-write + + + + + CRC_POL + CRC_POL + CRC polynomial + 0x14 + 0x20 + read-write + 0x04C11DB7 + 0xFFFFFFFF + + + POL + Programmable polynomial + + 0 + 32 + read-write + + + + + + + CRC_S + 0X50023000 + + + CRS + CRS address block description + CRS + 0x40006000 + + 0x0 + 0x10 + registers + + + CRS + Clock Recovery System global interrupt + 75 + + + + CRS_CR + CRS_CR + CRS control register + 0x00 + 0x20 + read-write + 0x00004000 + 0xFFFFFFFF + + + SYNCOKIE + SYNC event OK interrupt enable + 0 + 1 + read-write + + + B_0x0 + SYNC event OK (SYNCOKF) interrupt disabled + 0x0 + + + B_0x1 + SYNC event OK (SYNCOKF) interrupt enabled + 0x1 + + + + + SYNCWARNIE + SYNC warning interrupt enable + 1 + 1 + read-write + + + B_0x0 + SYNC warning (SYNCWARNF) interrupt disabled + 0x0 + + + B_0x1 + SYNC warning (SYNCWARNF) interrupt enabled + 0x1 + + + + + ERRIE + Synchronization or trimming error interrupt enable + 2 + 1 + read-write + + + B_0x0 + Synchronization or trimming error (ERRF) interrupt disabled + 0x0 + + + B_0x1 + Synchronization or trimming error (ERRF) interrupt enabled + 0x1 + + + + + ESYNCIE + Expected SYNC interrupt enable + 3 + 1 + read-write + + + B_0x0 + Expected SYNC (ESYNCF) interrupt disabled + 0x0 + + + B_0x1 + Expected SYNC (ESYNCF) interrupt enabled + 0x1 + + + + + CEN + Frequency error counter enable + + 5 + 1 + read-write + + + B_0x0 + Frequency error counter disabled + 0x0 + + + B_0x1 + Frequency error counter enabled + 0x1 + + + + + AUTOTRIMEN + Automatic trimming enable + + 6 + 1 + read-write + + + B_0x0 + Automatic trimming disabled, TRIM bits can be adjusted by the user. + 0x0 + + + B_0x1 + Automatic trimming enabled, TRIM bits are read-only and under hardware control. + 0x1 + + + + + SWSYNC + Generate software SYNC event + + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + A software SYNC event is generated. + 0x1 + + + + + TRIM + HSI48 oscillator smooth trimming + + 8 + 6 + read-write + + + + + CRS_CFGR + CRS_CFGR + CRS configuration register + 0x04 + 0x20 + read-write + 0x2022BB7F + 0xFFFFFFFF + + + RELOAD + Counter reload value + + 0 + 16 + read-write + + + FELIM + Frequency error limit + + 16 + 8 + read-write + + + SYNCDIV + SYNC divider + + 24 + 3 + read-write + + + B_0x0 + SYNC not divided (default) + 0x0 + + + B_0x1 + SYNC divided by 2 + 0x1 + + + B_0x2 + SYNC divided by 4 + 0x2 + + + B_0x3 + SYNC divided by 8 + 0x3 + + + B_0x4 + SYNC divided by 16 + 0x4 + + + B_0x5 + SYNC divided by 32 + 0x5 + + + B_0x6 + SYNC divided by 64 + 0x6 + + + B_0x7 + SYNC divided by 128 + 0x7 + + + + + SYNCSRC + SYNC signal source selection + + 28 + 2 + read-write + + + B_0x0 + crs_sync_in_1 selected as SYNC signal source + 0x0 + + + B_0x1 + crs_sync_in_2 selected as SYNC signal source + 0x1 + + + B_0x2 + crs_sync_in_3 selected as SYNC signal source + 0x2 + + + B_0x3 + crs_sync_in_4 selected as SYNC signal source + 0x3 + + + + + SYNCPOL + SYNC polarity selection + + 31 + 1 + read-write + + + B_0x0 + SYNC active on rising edge (default) + 0x0 + + + B_0x1 + SYNC active on falling edge + 0x1 + + + + + + + CRS_ISR + CRS_ISR + CRS interrupt and status register + 0x08 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + SYNCOKF + SYNC event OK flag + + 0 + 1 + read-only + + + B_0x0 + No SYNC event OK signaled + 0x0 + + + B_0x1 + SYNC event OK signaled + 0x1 + + + + + SYNCWARNF + SYNC warning flag + + 1 + 1 + read-only + + + B_0x0 + No SYNC warning signaled + 0x0 + + + B_0x1 + SYNC warning signaled + 0x1 + + + + + ERRF + Error flag + + 2 + 1 + read-only + + + B_0x0 + No synchronization or trimming error signaled + 0x0 + + + B_0x1 + Synchronization or trimming error signaled + 0x1 + + + + + ESYNCF + Expected SYNC flag + + 3 + 1 + read-only + + + B_0x0 + No expected SYNC signaled + 0x0 + + + B_0x1 + Expected SYNC signaled + 0x1 + + + + + SYNCERR + SYNC error + + 8 + 1 + read-only + + + B_0x0 + No SYNC error signaled + 0x0 + + + B_0x1 + SYNC error signaled + 0x1 + + + + + SYNCMISS + SYNC missed + + 9 + 1 + read-only + + + B_0x0 + No SYNC missed error signaled + 0x0 + + + B_0x1 + SYNC missed error signaled + 0x1 + + + + + TRIMOVF + Trimming overflow or underflow + + 10 + 1 + read-only + + + B_0x0 + No trimming error signaled + 0x0 + + + B_0x1 + Trimming error signaled + 0x1 + + + + + FEDIR + Frequency error direction + + 15 + 1 + read-only + + + B_0x0 + Up-counting direction, the actual frequency is above the target + 0x0 + + + B_0x1 + Down-counting direction, the actual frequency is below the target + 0x1 + + + + + FECAP + Frequency error capture + + 16 + 16 + read-only + + + + + CRS_ICR + CRS_ICR + CRS interrupt flag clear register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SYNCOKC + SYNC event OK clear flag + + 0 + 1 + read-write + + + SYNCWARNC + SYNC warning clear flag + + 1 + 1 + read-write + + + ERRC + Error clear flag + + 2 + 1 + read-write + + + ESYNCC + Expected SYNC clear flag + + 3 + 1 + read-write + + + + + + + CRS_S + 0X50006000 + + + DAC + DAC address block description + DAC + 0x42028400 + + 0x0 + 0x50 + registers + + + DAC1 + DAC1 global interrupt + 38 + + + + DAC_CR + DAC_CR + DAC control register + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EN1 + DAC channel1 enable + + 0 + 1 + read-write + + + B_0x0 + DAC channel1 disabled + 0x0 + + + B_0x1 + DAC channel1 enabled + 0x1 + + + + + TEN1 + DAC channel1 trigger enable + + 1 + 1 + read-write + + + B_0x0 + DAC channel1 trigger disabled and data written into the DAC_DHR1 register are transferred one dac_hclk clock cycle later to the DAC_DOR1 register + 0x0 + + + B_0x1 + DAC channel1 trigger enabled and data from the DAC_DHR1 register are transferred three dac_hclk clock cycles later to the DAC_DOR1 register + 0x1 + + + + + TSEL1 + DAC channel1 trigger selection + + 2 + 4 + read-write + + + B_0x0 + SWTRIG1 + 0x0 + + + B_0x1 + dac_ch1_trg1 + 0x1 + + + B_0x2 + dac_ch1_trg2 + 0x2 + + + B_0xF + dac_ch1_trg15 + 0xF + + + + + WAVE1 + DAC channel1 noise/triangle wave generation enable + + 6 + 2 + read-write + + + B_0x0 + wave generation disabled + 0x0 + + + B_0x1 + Noise wave generation enabled + 0x1 + + + + + MAMP1 + DAC channel1 mask/amplitude selector + + 8 + 4 + read-write + + + B_0x0 + Unmask bit0 of LFSR/ triangle amplitude equal to 1 + 0x0 + + + B_0x1 + Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3 + 0x1 + + + B_0x2 + Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7 + 0x2 + + + B_0x3 + Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15 + 0x3 + + + B_0x4 + Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31 + 0x4 + + + B_0x5 + Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63 + 0x5 + + + B_0x6 + Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127 + 0x6 + + + B_0x7 + Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255 + 0x7 + + + B_0x8 + Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511 + 0x8 + + + B_0x9 + Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023 + 0x9 + + + B_0xA + Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047 + 0xA + + + + + DMAEN1 + DAC channel1 DMA enable + + 12 + 1 + read-write + + + B_0x0 + DAC channel1 DMA mode disabled + 0x0 + + + B_0x1 + DAC channel1 DMA mode enabled + 0x1 + + + + + DMAUDRIE1 + DAC channel1 DMA Underrun Interrupt enable + + 13 + 1 + read-write + + + B_0x0 + DAC channel1 DMA Underrun Interrupt disabled + 0x0 + + + B_0x1 + DAC channel1 DMA Underrun Interrupt enabled + 0x1 + + + + + CEN1 + DAC channel1 calibration enable + + 14 + 1 + read-write + + + B_0x0 + DAC channel1 in Normal operating mode + 0x0 + + + B_0x1 + DAC channel1 in calibration mode + 0x1 + + + + + EN2 + DAC channel2 enable + + 16 + 1 + read-write + + + B_0x0 + DAC channel2 disabled + 0x0 + + + B_0x1 + DAC channel2 enabled + 0x1 + + + + + TEN2 + DAC channel2 trigger enable + + 17 + 1 + read-write + + + B_0x0 + DAC channel2 trigger disabled and data written into the DAC_DHR2 register are transferred one dac_hclk clock cycle later to the DAC_DOR2 register + 0x0 + + + B_0x1 + DAC channel2 trigger enabled and data from the DAC_DHR2 register are transferred three dac_hclk clock cycles later to the DAC_DOR2 register + 0x1 + + + + + TSEL2 + DAC channel2 trigger selection + + 18 + 4 + read-write + + + B_0x0 + SWTRIG2 + 0x0 + + + B_0x1 + dac_ch2_trg1 + 0x1 + + + B_0x2 + dac_ch2_trg2 + 0x2 + + + B_0xF + dac_ch2_trg15 + 0xF + + + + + WAVE2 + DAC channel2 noise/triangle wave generation enable + + 22 + 2 + read-write + + + B_0x0 + wave generation disabled + 0x0 + + + B_0x1 + Noise wave generation enabled + 0x1 + + + + + MAMP2 + DAC channel2 mask/amplitude selector + + 24 + 4 + read-write + + + B_0x0 + Unmask bit0 of LFSR/ triangle amplitude equal to 1 + 0x0 + + + B_0x1 + Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3 + 0x1 + + + B_0x2 + Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7 + 0x2 + + + B_0x3 + Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15 + 0x3 + + + B_0x4 + Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31 + 0x4 + + + B_0x5 + Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63 + 0x5 + + + B_0x6 + Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127 + 0x6 + + + B_0x7 + Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255 + 0x7 + + + B_0x8 + Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511 + 0x8 + + + B_0x9 + Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023 + 0x9 + + + B_0xA + Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047 + 0xA + + + + + DMAEN2 + DAC channel2 DMA enable + + 28 + 1 + read-write + + + B_0x0 + DAC channel2 DMA mode disabled + 0x0 + + + B_0x1 + DAC channel2 DMA mode enabled + 0x1 + + + + + DMAUDRIE2 + DAC channel2 DMA underrun interrupt enable + + 29 + 1 + read-write + + + B_0x0 + DAC channel2 DMA underrun interrupt disabled + 0x0 + + + B_0x1 + DAC channel2 DMA underrun interrupt enabled + 0x1 + + + + + CEN2 + DAC channel2 calibration enable + + 30 + 1 + read-write + + + B_0x0 + DAC channel2 in Normal operating mode + 0x0 + + + B_0x1 + DAC channel2 in calibration mode + 0x1 + + + + + + + DAC_SWTRGR + DAC_SWTRGR + DAC software trigger register + 0x04 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + SWTRIG1 + DAC channel1 software trigger + + 0 + 1 + write-only + + + B_0x0 + No trigger + 0x0 + + + B_0x1 + Trigger + 0x1 + + + + + SWTRIG2 + DAC channel2 software trigger + + 1 + 1 + write-only + + + B_0x0 + No trigger + 0x0 + + + B_0x1 + Trigger + 0x1 + + + + + + + DAC_DHR12R1 + DAC_DHR12R1 + DAC channel1 12-bit right-aligned data holding register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DACC1DHR + DAC channel1 12-bit right-aligned data + + 0 + 12 + read-write + + + DACC1DHRB + DAC channel1 12-bit right-aligned data B + + 16 + 12 + read-write + + + + + DAC_DHR12L1 + DAC_DHR12L1 + DAC channel1 12-bit left aligned data holding register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DACC1DHR + DAC channel1 12-bit left-aligned data + + 4 + 12 + read-write + + + DACC1DHRB + DAC channel1 12-bit left-aligned data B + + 20 + 12 + read-write + + + + + DAC_DHR8R1 + DAC_DHR8R1 + DAC channel1 8-bit right aligned data holding register + 0x10 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DACC1DHR + DAC channel1 8-bit right-aligned data + + 0 + 8 + read-write + + + DACC1DHRB + DAC channel1 8-bit right-aligned data + + 8 + 8 + read-write + + + + + DAC_DHR12R2 + DAC_DHR12R2 + DAC channel2 12-bit right aligned data holding register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DACC2DHR + DAC channel2 12-bit right-aligned data + + 0 + 12 + read-write + + + DACC2DHRB + DAC channel2 12-bit right-aligned data + + 16 + 12 + read-write + + + + + DAC_DHR12L2 + DAC_DHR12L2 + DAC channel2 12-bit left aligned data holding register + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DACC2DHR + DAC channel2 12-bit left-aligned data + + 4 + 12 + read-write + + + DACC2DHRB + DAC channel2 12-bit left-aligned data B + + 20 + 12 + read-write + + + + + DAC_DHR8R2 + DAC_DHR8R2 + DAC channel2 8-bit right-aligned data holding register + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DACC2DHR + DAC channel2 8-bit right-aligned data + + 0 + 8 + read-write + + + DACC2DHRB + DAC channel2 8-bit right-aligned data + + 8 + 8 + read-write + + + + + DAC_DHR12RD + DAC_DHR12RD + Dual DAC 12-bit right-aligned data holding register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DACC1DHR + DAC channel1 12-bit right-aligned data + + 0 + 12 + read-write + + + DACC2DHR + DAC channel2 12-bit right-aligned data + + 16 + 12 + read-write + + + + + DAC_DHR12LD + DAC_DHR12LD + Dual DAC 12-bit left aligned data holding register + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DACC1DHR + DAC channel1 12-bit left-aligned data + + 4 + 12 + read-write + + + DACC2DHR + DAC channel2 12-bit left-aligned data + + 20 + 12 + read-write + + + + + DAC_DHR8RD + DAC_DHR8RD + Dual DAC 8-bit right aligned data holding register + 0x28 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DACC1DHR + DAC channel1 8-bit right-aligned data + + 0 + 8 + read-write + + + DACC2DHR + DAC channel2 8-bit right-aligned data + + 8 + 8 + read-write + + + + + DAC_DOR1 + DAC_DOR1 + DAC channel1 data output register + 0x2C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + DACC1DOR + DAC channel1 data output + + 0 + 12 + read-only + + + DACC1DORB + DAC channel1 data output + + 16 + 12 + read-only + + + + + DAC_DOR2 + DAC_DOR2 + DAC channel2 data output register + 0x30 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + DACC2DOR + DAC channel2 data output + + 0 + 12 + read-only + + + DACC2DORB + DAC channel2 data output + + 16 + 12 + read-only + + + + + DAC_SR + DAC_SR + DAC status register + 0x34 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DAC1RDY + DAC channel1 ready status bit + + 11 + 1 + read-only + + + B_0x0 + DAC channel1 is not yet ready to accept the trigger nor output data + 0x0 + + + B_0x1 + DAC channel1 is ready to accept the trigger or output data + 0x1 + + + + + DORSTAT1 + DAC channel1 output register status bit + + 12 + 1 + read-only + + + B_0x0 + DOR[11:0] is used actual DAC output + 0x0 + + + B_0x1 + DORB[11:0] is used actual DAC output + 0x1 + + + + + DMAUDR1 + DAC channel1 DMA underrun flag + + 13 + 1 + read-write + + + B_0x0 + No DMA underrun error condition occurred for DAC channel1 + 0x0 + + + B_0x1 + DMA underrun error condition occurred for DAC channel1 (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate) + 0x1 + + + + + CAL_FLAG1 + DAC channel1 calibration offset status + + 14 + 1 + read-only + + + B_0x0 + calibration trimming value is lower than the offset correction value + 0x0 + + + B_0x1 + calibration trimming value is equal or greater than the offset correction value + 0x1 + + + + + BWST1 + DAC channel1 busy writing sample time flag + + 15 + 1 + read-only + + + B_0x0 + There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written + 0x0 + + + B_0x1 + There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written + 0x1 + + + + + DAC2RDY + DAC channel2 ready status bit + + 27 + 1 + read-only + + + B_0x0 + DAC channel2 is not yet ready to accept the trigger nor output data + 0x0 + + + B_0x1 + DAC channel2 is ready to accept the trigger or output data + 0x1 + + + + + DORSTAT2 + DAC channel2 output register status bit + + 28 + 1 + read-only + + + B_0x0 + DOR[11:0] is used actual DAC output + 0x0 + + + B_0x1 + DORB[11:0] is used actual DAC output + 0x1 + + + + + DMAUDR2 + DAC channel2 DMA underrun flag + + 29 + 1 + read-write + + + B_0x0 + No DMA underrun error condition occurred for DAC channel2 + 0x0 + + + B_0x1 + DMA underrun error condition occurred for DAC channel2 (the currently selected trigger is driving DAC channel2 conversion at a frequency higher than the DMA service capability rate). + 0x1 + + + + + CAL_FLAG2 + DAC channel2 calibration offset status + + 30 + 1 + read-only + + + B_0x0 + calibration trimming value is lower than the offset correction value + 0x0 + + + B_0x1 + calibration trimming value is equal or greater than the offset correction value + 0x1 + + + + + BWST2 + DAC channel2 busy writing sample time flag + + 31 + 1 + read-only + + + B_0x0 + There is no write operation of DAC_SHSR2 ongoing: DAC_SHSR2 can be written + 0x0 + + + B_0x1 + There is a write operation of DAC_SHSR2 ongoing: DAC_SHSR2 cannot be written + 0x1 + + + + + + + DAC_CCR + DAC_CCR + DAC calibration control register + 0x38 + 0x20 + read-write + 0x00000000 + 0xFF00FF00 + + + OTRIM1 + DAC channel1 offset trimming value + 0 + 5 + read-write + + + OTRIM2 + DAC channel2 offset trimming value + + 16 + 5 + read-write + + + + + DAC_MCR + DAC_MCR + DAC mode control register + 0x3C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + MODE1 + DAC channel1 mode + + 0 + 3 + read-write + + + B_0x0 + DAC channel1 is connected to external pin with Buffer enabled + 0x0 + + + B_0x2 + DAC channel1 is connected to external pin with Buffer disabled + 0x2 + + + B_0x4 + DAC channel1 is connected to external pin with Buffer enabled + 0x4 + + + B_0x6 + DAC channel1 is connected to external pin with Buffer disabled + 0x6 + + + + + DMADOUBLE1 + DAC channel1 DMA double data mode + + 8 + 1 + read-write + + + B_0x0 + DMA Normal mode selected + 0x0 + + + B_0x1 + DMA Double data mode selected + 0x1 + + + + + SINFORMAT1 + Enable signed format for DAC channel1 + + 9 + 1 + read-write + + + B_0x0 + Input data is in unsigned format + 0x0 + + + B_0x1 + Input data is in signed format (2's complement). + 0x1 + + + + + HFSEL + High frequency interface mode selection + 14 + 2 + read-write + + + B_0x0 + High frequency interface mode disabled + 0x0 + + + B_0x1 + High frequency interface mode enabled for AHB clock frequency > 80 MHz + 0x1 + + + B_0x2 + High frequency interface mode enabled for AHB clock frequency >160 MHz + 0x2 + + + + + MODE2 + DAC channel2 mode + + 16 + 3 + read-write + + + B_0x0 + DAC channel2 is connected to external pin with Buffer enabled + 0x0 + + + B_0x2 + DAC channel2 is connected to external pin with buffer disabled + 0x2 + + + B_0x4 + DAC channel2 is connected to external pin with Buffer enabled + 0x4 + + + B_0x6 + DAC channel2 is connected to external pin with Buffer disabled + 0x6 + + + + + DMADOUBLE2 + DAC channel2 DMA double data mode + + 24 + 1 + read-write + + + B_0x0 + DMA Normal mode selected + 0x0 + + + B_0x1 + DMA Double data mode selected + 0x1 + + + + + SINFORMAT2 + Enable signed format for DAC channel2 + + 25 + 1 + read-write + + + B_0x0 + Input data is in unsigned format + 0x0 + + + B_0x1 + Input data is in signed format (2's complement). + 0x1 + + + + + + + DAC_SHSR1 + DAC_SHSR1 + DAC channel1 sample and hold sample time register + 0x40 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TSAMPLE1 + DAC channel1 sample time (only valid in Sample and hold mode) + + 0 + 10 + read-write + + + + + DAC_SHSR2 + DAC_SHSR2 + DAC channel2 sample and hold sample time register + 0x44 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TSAMPLE2 + DAC channel2 sample time (only valid in Sample and hold mode) + + 0 + 10 + read-write + + + + + DAC_SHHR + DAC_SHHR + DAC sample and hold time register + 0x48 + 0x20 + read-write + 0x00010001 + 0xFFFFFFFF + + + THOLD1 + DAC channel1 hold time (only valid in Sample and hold mode) + + 0 + 10 + read-write + + + THOLD2 + DAC channel2 hold time (only valid in Sample and hold mode). + 16 + 10 + read-write + + + + + DAC_SHRR + DAC_SHRR + DAC sample and hold refresh time register + 0x4C + 0x20 + read-write + 0x00010001 + 0xFFFFFFFF + + + TREFRESH1 + DAC channel1 refresh time (only valid in Sample and hold mode) + + 0 + 8 + read-write + + + TREFRESH2 + DAC channel2 refresh time (only valid in Sample and hold mode) + + 16 + 8 + read-write + + + + + + + DAC_S + 0X52028400 + + + DBGMCU + DBGMCU register block + DBGMCU + 0x44024000 + + 0x0 + 0x1000 + registers + + + + DBGMCU_IDCODE + DBGMCU_IDCODE + DBGMCU identity code register + 0x00 + 0x20 + read-only + 0x00006000 + 0x0000F000 + + + DEV_ID + Device identification + 0 + 12 + read-only + + + B_0x484 + STM32H562/563/573 + 0x484 + + + B_0x478 + STM32H523/533 + 0x478 + + + + + REV_ID + Revision + + 16 + 16 + read-only + + + + + DBGMCU_CR + DBGMCU_CR + DBGMCU configuration register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DBG_STOP + Allows debug in Stop mode + + 1 + 1 + read-write + + + B_0x0 + normal operation + 0x0 + + + B_0x1 + automatic clock stop disabled + 0x1 + + + + + DBG_STANDBY + Allows debug in Standby mode + + 2 + 1 + read-write + + + B_0x0 + normal operation + 0x0 + + + B_0x1 + automatic clock stop/power down disabled + 0x1 + + + + + TRACE_IOEN + trace pin enable + 4 + 1 + read-write + + + B_0x0 + disabled - trace pins not assigned + 0x0 + + + B_0x1 + enabled - trace pins assigned according to the value of TRACE_MODE field + 0x1 + + + + + TRACE_EN + trace port and clock enable. + 5 + 1 + read-write + + + B_0x0 + disabled + 0x0 + + + B_0x1 + enabled + 0x1 + + + + + TRACE_MODE + trace pin assignment + 6 + 2 + read-write + + + B_0x0 + trace pins assigned for asynchronous mode (TRACESWO) + 0x0 + + + B_0x1 + trace pins assigned for synchronous mode with a port width of 1 (TRACECK, TRACED0) + 0x1 + + + B_0x2 + trace pins assigned for synchronous mode with a port width of 2 ((TRACECK, TRACED0-1) + 0x2 + + + B_0x3 + trace pins assigned for synchronous mode with a port width of 4 ((TRACECK, TRACED0-3) + 0x3 + + + + + DCRT + Debug credentials reset type + + 16 + 1 + read-write + + + B_0x0 + System reset + 0x0 + + + B_0x1 + Power reset + 0x1 + + + + + + + DBGMCU_APB1LFZR + DBGMCU_APB1LFZR + DBGMCU APB1L peripheral freeze register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DBG_TIM2_STOP + TIM2 stop in debug + 0 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_TIM3_STOP + TIM3 stop in debug + 1 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_TIM4_STOP + TIM4 stop in debug + 2 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_TIM5_STOP + TIM5 stop in debug + 3 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + Stop in debug. + 0x1 + + + + + DBG_TIM6_STOP + TIM6 stop in debug + 4 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_TIM7_STOP + TIM7 stop in debug + 5 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_TIM12_STOP + TIM12 stop in debug + 6 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_TIM13_STOP + TIM13 stop in debug + 7 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_TIM14_STOP + TIM14 stop in debug + 8 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_WWDG_STOP + WWDG stop in debug + 11 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_IWDG_STOP + IWDG stop in debug + 12 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_I2C1_STOP + I2C1 SMBUS timeout stop in debug + 21 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_I2C2_STOP + I2C2 SMBUS timeout stop in debug + 22 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_I3C1_STOP + I3C1 SCL stall counter stop in debug + 23 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + + + DBGMCU_APB1HFZR + DBGMCU_APB1HFZR + DBGMCU APB1H peripheral freeze register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DBG_LPTIM2_STOP + LPTIM2 stop in debug + 5 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + + + DBGMCU_APB2FZR + DBGMCU_APB2FZR + DBGMCU APB2 peripheral freeze register + 0x10 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DBG_TIM1_STOP + TIM1 stop in debug + 11 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_TIM8_STOP + TIM8 stop in debug + 13 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_TIM15_STOP + TIM15 stop in debug + 16 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_TIM16_STOP + TIM16 stop in debug + 17 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_TIM17_STOP + TIM17 stop in debug + 18 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + + + DBGMCU_APB3FZR + DBGMCU_APB3FZR + DBGMCU APB3 peripheral freeze register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DBG_I2C3_STOP + I2C3 SMBUS timeout stop in debug + 10 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_I2C4_STOP + I2C4 SMBUS timeout stop in debug + 11 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_LPTIM1_STOP + LPTIM1 stop in debug + 17 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_LPTIM3_STOP + LPTIM3 stop in debug + 18 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_LPTIM4_STOP + LPTIM4 stop in debug + 19 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_LPTIM5_STOP + LPTIM5 stop in debug + 20 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_LPTIM6_STOP + LPTIM6 stop in debug + 21 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_RTC_STOP + RTC stop in debug + 30 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + + + DBGMCU_AHB1FZR + DBGMCU_AHB1FZR + DBGMCU AHB1 peripheral freeze register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DBG_GPDMA1_0_STOP + GPDMA1 channel 0 stop in debug + 0 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_GPDMA1_1_STOP + GPDMA1 channel 1 stop in debug + 1 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_GPDMA1_2_STOP + GPDMA1 channel 2 stop in debug + 2 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_GPDMA1_3_STOP + GPDMA1 channel 3 stop in debug + 3 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_GPDMA1_4_STOP + GPDMA1 channel 4 stop in debug + 4 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_GPDMA1_5_STOP + GPDMA1 channel 5 stop in debug + 5 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_GPDMA1_6_STOP + GPDMA1 channel 6 stop in debug + 6 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_GPDMA1_7_STOP + GPDMA1 channel 7 stop in debug + 7 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_GPDMA2_0_STOP + GPDMA2 channel 0 stop in debug + 16 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_GPDMA2_1_STOP + GPDMA2 channel 1 stop in debug + 17 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_GPDMA2_2_STOP + GPDMA2 channel 2 stop in debug + 18 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_GPDMA2_3_STOP + GPDMA2 channel 3 stop in debug + 19 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_GPDMA2_4_STOP + GPDMA2 channel 4 stop in debug + 20 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_GPDMA2_5_STOP + GPDMA2 channel 5 stop in debug + 21 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_GPDMA2_6_STOP + GPDMA2 channel 6 stop in debug + 22 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_GPDMA2_7_STOP + GPDMA2 channel 7 stop in debug + 23 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + + + DBGMCU_SR + DBGMCU_SR + DBGMCU status register + 0xFC + 0x20 + read-only + 0x00010003 + 0xFFFF00FF + + + AP_PRESENT + Bit n identifies whether access port AP n is present in device + + 0 + 16 + read-only + + + AP_ENABLED + Bit n identifies whether access port AP n is open (can be accessed via the debug port) or locked (debug access to the AP is blocked) + + 16 + 16 + read-only + + + + + DBGMCU_DBG_AUTH_HOST + DBGMCU_DBG_AUTH_HOST + DBGMCU debug authentication mailbox host register + 0x100 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + MESSAGE + Debug host to device mailbox message. + 0 + 32 + read-write + + + + + DBGMCU_DBG_AUTH_DEVICE + DBGMCU_DBG_AUTH_DEVICE + DBGMCU debug authentication mailbox device register + 0x104 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + MESSAGE + Device to debug host mailbox message. + 0 + 32 + read-write + + + + + DBGMCU_DBG_AUTH_ACK + DBGMCU_DBG_AUTH_ACK + DBGMCU debug authentication mailbox acknowledge register + 0x108 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + HOST_ACK + Host to device acknowledge. + 0 + 1 + read-only + + + B_0x0 + DBGMCU_DBG_AUTH_HOST register is empty + 0x0 + + + + + DEV_ACK + Device to host acknowledge. + 1 + 1 + read-only + + + B_0x0 + DBGMCU_DBG_AUTH_DEVICE register is empty + 0x0 + + + + + + + DBGMCU_PIDR4 + DBGMCU_PIDR4 + DBGMCU CoreSight peripheral identity register 4 + 0xFD0 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + JEP106CON + JEP106 continuation code + 0 + 4 + read-only + + + B_0x0 + STMicroelectronics JEDEC code + 0x0 + + + + + SIZE + register file size + 4 + 4 + read-only + + + B_0x0 + The register file occupies a single 4-Kbyte region. + 0x0 + + + + + + + DBGMCU_PIDR0 + DBGMCU_PIDR0 + DBGMCU CoreSight peripheral identity register 0 + 0xFE0 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + PARTNUM + part number bits [7:0] + 0 + 8 + read-only + + + B_0x00 + DBGMCU part number + 0x00 + + + + + + + DBGMCU_PIDR1 + DBGMCU_PIDR1 + DBGMCU CoreSight peripheral identity register 1 + 0xFE4 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + PARTNUM + part number bits [11:8] + 0 + 4 + read-only + + + B_0x0 + DBGMCU part number + 0x0 + + + + + JEP106ID + JEP106 identity code bits [3:0] + 4 + 4 + read-only + + + B_0x0 + STMicroelectronics JEDEC code + 0x0 + + + + + + + DBGMCU_PIDR2 + DBGMCU_PIDR2 + DBGMCU CoreSight peripheral identity register 2 + 0xFE8 + 0x20 + read-only + 0x0000000A + 0xFFFFFFFF + + + JEP106ID + JEP106 identity code bits [6:4] + 0 + 3 + read-only + + + B_0x2 + STMicroelectronics JEDEC code + 0x2 + + + + + JEDEC + JEDEC assigned value + 3 + 1 + read-only + + + B_0x1 + designer identification specified by JEDEC + 0x1 + + + + + REVISION + component revision number + 4 + 4 + read-only + + + B_0x0 + r0p0 + 0x0 + + + + + + + DBGMCU_PIDR3 + DBGMCU_PIDR3 + DBGMCU CoreSight peripheral identity register 3 + 0xFEC + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + CMOD + customer modified + 0 + 4 + read-only + + + B_0x0 + no customer modifications + 0x0 + + + + + REVAND + metal fix version + 4 + 4 + read-only + + + B_0x0 + no metal fix + 0x0 + + + + + + + DBGMCU_CIDR0 + DBGMCU_CIDR0 + DBGMCU CoreSight component identity register 0 + 0xFF0 + 0x20 + read-only + 0x0000000D + 0xFFFFFFFF + + + PREAMBLE + component identification bits [7:0] + 0 + 8 + read-only + + + B_0x0D + common identification value + 0x0D + + + + + + + DBGMCU_CIDR1 + DBGMCU_CIDR1 + DBGMCU CoreSight component identity register 1 + 0xFF4 + 0x20 + read-only + 0x000000F0 + 0xFFFFFFFF + + + PREAMBLE + component identification bits [11:8] + 0 + 4 + read-only + + + B_0x0 + common identification value + 0x0 + + + + + CLASS + component identification bits [15:12] - component class + 4 + 4 + read-only + + + B_0xF + Non-CoreSight component + 0xF + + + + + + + DBGMCU_CIDR2 + DBGMCU_CIDR2 + DBGMCU CoreSight component identity register 2 + 0xFF8 + 0x20 + read-only + 0x00000005 + 0xFFFFFFFF + + + PREAMBLE + component identification bits [23:16] + 0 + 8 + read-only + + + B_0x05 + common identification value + 0x05 + + + + + + + DBGMCU_CIDR3 + DBGMCU_CIDR3 + DBGMCU CoreSight component identity register 3 + 0xFFC + 0x20 + read-only + 0x000000B1 + 0xFFFFFFFF + + + PREAMBLE + component identification bits [31:24] + 0 + 8 + read-only + + + B_0xB1 + common identification value + 0xB1 + + + + + + + + + DBGMCU_S + 0x54024000 + + + DCACHE + DCACHE register block + DCACHE + 0x40031400 + + 0x0 + 0x400 + registers + + + DCACHE + Data cache global interrupt + 105 + + + + DCACHE_CR + DCACHE_CR + DCACHE control register + 0x000 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EN + enable + 0 + 1 + read-write + + + B_0x0 + cache disabled + 0x0 + + + B_0x1 + cache enabled + 0x1 + + + + + CACHEINV + full cache invalidation + + 1 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + invalidate entire cache (all cache lines valid bit = 0) + 0x1 + + + + + CACHECMD + cache command maintenance operation (cleans and/or invalidates an address range) + + 8 + 3 + read-write + + + B_0x0 + no operation + 0x0 + + + B_0x1 + clean range + 0x1 + + + B_0x2 + invalidate range + 0x2 + + + B_0x3 + clean and invalidate range + 0x3 + + + + + STARTCMD + starts maintenance command (maintenance operation defined in CACHECMD). + 11 + 1 + write-only + + + B_0x0 + command operation (cache maintenance) finished + 0x0 + + + B_0x1 + start maintenance command (cache maintenance) + 0x1 + + + + + RHITMEN + read-hit monitor enable + 16 + 1 + read-write + + + B_0x0 + cache read-hit monitor switched off. + 0x0 + + + B_0x1 + cache read-hit monitor enabled + 0x1 + + + + + RMISSMEN + read-miss monitor enable + 17 + 1 + read-write + + + B_0x0 + cache read-miss monitor switched off. + 0x0 + + + B_0x1 + cache read-miss monitor enabled + 0x1 + + + + + RHITMRST + read-hit monitor reset + 18 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + reset cache read-hit monitor + 0x1 + + + + + RMISSMRST + read-miss monitor reset + 19 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + reset cache read-miss monitor + 0x1 + + + + + WHITMEN + write-hit monitor enable + 20 + 1 + read-write + + + B_0x0 + cache write-hit monitor switched off. + 0x0 + + + B_0x1 + cache write-hit monitor enabled + 0x1 + + + + + WMISSMEN + write-miss monitor enable + 21 + 1 + read-write + + + B_0x0 + cache write-miss monitor switched off. + 0x0 + + + B_0x1 + cache write-miss monitor enabled + 0x1 + + + + + WHITMRST + write-hit monitor reset + 22 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + reset cache write-hit monitor + 0x1 + + + + + WMISSMRST + write-miss monitor reset + 23 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + reset cache write-miss monitor + 0x1 + + + + + HBURST + output burst type for cache master port read accesses + + 31 + 1 + read-write + + + B_0x0 + WRAP + 0x0 + + + B_0x1 + INCR + 0x1 + + + + + + + DCACHE_SR + DCACHE_SR + DCACHE status register + 0x004 + 0x20 + read-only + 0x00000001 + 0xFFFFFFFF + + + BUSYF + full invalidate busy flag + 0 + 1 + read-only + + + B_0x0 + cache not busy on a CACHEINV operation + 0x0 + + + B_0x1 + cache executing a full invalidate CACHEINV operation + 0x1 + + + + + BSYENDF + full invalidate busy end flag + + 1 + 1 + read-only + + + B_0x0 + cache busy or in idle + 0x0 + + + B_0x1 + full invalidate CACHEINV operation finished + 0x1 + + + + + ERRF + cache error flag + + 2 + 1 + read-only + + + B_0x0 + no error + 0x0 + + + B_0x1 + an error occurred during the operation (eviction or clean operation write-back error). + 0x1 + + + + + BUSYCMDF + command busy flag + 3 + 1 + read-only + + + B_0x0 + cache not busy on a CACHECMD command + 0x0 + + + B_0x1 + cache busy on a CACHECMD command (clean and/or invalidate an address range) + 0x1 + + + + + CMDENDF + command end flag + + 4 + 1 + read-only + + + B_0x0 + cache busy or in idle + 0x0 + + + B_0x1 + CACHECMD command finished + 0x1 + + + + + + + DCACHE_IER + DCACHE_IER + DCACHE interrupt enable register + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BSYENDIE + interrupt enable on busy end + + 1 + 1 + read-write + + + B_0x0 + Interrupt disabled on busy end + 0x0 + + + B_0x1 + Interrupt enabled on busy end + 0x1 + + + + + ERRIE + interrupt enable on cache error + + 2 + 1 + read-write + + + B_0x0 + interrupt disabled on error + 0x0 + + + B_0x1 + interrupt enabled on error + 0x1 + + + + + CMDENDIE + interrupt enable on command end + + 4 + 1 + read-write + + + B_0x0 + interrupt disabled on command end + 0x0 + + + B_0x1 + interrupt enabled on command end + 0x1 + + + + + + + DCACHE_FCR + DCACHE_FCR + DCACHE flag clear register + 0x00C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + CBSYENDF + clear full invalidate busy end flag + + 1 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clears BSYENDF flag in DCACHE_SR + 0x1 + + + + + CERRF + clear cache error flag + + 2 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clears ERRF flag in DCACHE_SR + 0x1 + + + + + CCMDENDF + clear command end flag + + 4 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clears CMDENDF flag in DCACHE_SR + 0x1 + + + + + + + DCACHE_RHMONR + DCACHE_RHMONR + DCACHE read-hit monitor register + 0x010 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RHITMON + cache read-hit monitor counter + 0 + 32 + read-only + + + + + DCACHE_RMMONR + DCACHE_RMMONR + DCACHE read-miss monitor register + 0x014 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RMISSMON + cache read-miss monitor counter + 0 + 16 + read-only + + + + + DCACHE_WHMONR + DCACHE_WHMONR + DCACHE write-hit monitor register + 0x020 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + WHITMON + cache write-hit monitor counter + 0 + 32 + read-only + + + + + DCACHE_WMMONR + DCACHE_WMMONR + DCACHE write-miss monitor register + 0x024 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + WMISSMON + cache write-miss monitor counter + 0 + 16 + read-only + + + + + DCACHE_CMDRSADDRR + DCACHE_CMDRSADDRR + DCACHE command range start address register + 0x028 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CMDSTARTADDR + start address of range to which the cache maintenance command specified in DCACHE_CR. + 4 + 28 + read-write + + + + + DCACHE_CMDREADDRR + DCACHE_CMDREADDRR + DCACHE command range end address register + 0x02C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CMDENDADDR + end address of range to which the cache maintenance command specified in DCACHE_CR. + 4 + 28 + read-write + + + + + + + DCACHE_S + 0X50031400 + + + DCMI + DCMI address block description + DCMI + 0x4202c000 + + 0x0 + 0x2C + registers + + + DCMI_PSSI + DCMI/PSSI global interrupt + 108 + + + + DCMI_CR + DCMI_CR + DCMI control register + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CAPTURE + Capture enable + + 0 + 1 + read-write + + + B_0x0 + Capture disabled + 0x0 + + + B_0x1 + Capture enabled + 0x1 + + + + + CM + Capture mode + 1 + 1 + read-write + + + B_0x0 + Continuous grab mode - The received data are transferred into the destination memory through the DMA. + 0x0 + + + B_0x1 + Snapshot mode (single frame) - Once activated, the interface waits for the start of frame and then transfers a single frame through the DMA. + 0x1 + + + + + CROP + Crop feature + 2 + 1 + read-write + + + B_0x0 + The full image is captured. + 0x0 + + + B_0x1 + Only the data inside the window specified by the crop register is captured. + 0x1 + + + + + JPEG + JPEG format + 3 + 1 + read-write + + + B_0x0 + Uncompressed video format + 0x0 + + + B_0x1 + This bit is used for JPEG data transfers. + 0x1 + + + + + ESS + Embedded synchronization select + + 4 + 1 + read-write + + + B_0x0 + Hardware synchronization data capture (frame/line start/stop) is synchronized with the DCMI_HSYNC/DCMI_VSYNC signals. + 0x0 + + + B_0x1 + Embedded synchronization data capture is synchronized with synchronization codes embedded in the data flow. + 0x1 + + + + + PCKPOL + Pixel clock polarity + + 5 + 1 + read-write + + + B_0x0 + Falling edge active + 0x0 + + + B_0x1 + Rising edge active + 0x1 + + + + + HSPOL + Horizontal synchronization polarity + + 6 + 1 + read-write + + + B_0x0 + DCMI_HSYNC active low + 0x0 + + + B_0x1 + DCMI_HSYNC active high + 0x1 + + + + + VSPOL + Vertical synchronization polarity + + 7 + 1 + read-write + + + B_0x0 + DCMI_VSYNC active low + 0x0 + + + B_0x1 + DCMI_VSYNC active high + 0x1 + + + + + FCRC + Frame capture rate control + + 8 + 2 + read-write + + + B_0x0 + All frames are captured. + 0x0 + + + B_0x1 + Every alternate frame captured (50% bandwidth reduction) + 0x1 + + + B_0x2 + One frame out of four captured (75% bandwidth reduction) + 0x2 + + + + + EDM + Extended data mode + 10 + 2 + read-write + + + B_0x0 + Interface captures 8-bit data on every pixel clock. + 0x0 + + + B_0x1 + Interface captures 10-bit data on every pixel clock. + 0x1 + + + B_0x2 + Interface captures 12-bit data on every pixel clock. + 0x2 + + + B_0x3 + Interface captures 14-bit data on every pixel clock. + 0x3 + + + + + ENABLE + DCMI enable + + 14 + 1 + read-write + + + B_0x0 + DCMI disabled + 0x0 + + + B_0x1 + DCMI enabled + 0x1 + + + + + BSM + Byte Select mode + + 16 + 2 + read-write + + + B_0x0 + Interface captures all received data. + 0x0 + + + B_0x1 + Interface captures every other byte from the received data. + 0x1 + + + B_0x2 + Interface captures one byte out of four. + 0x2 + + + B_0x3 + Interface captures two bytes out of four. + 0x3 + + + + + OEBS + Odd/Even Byte Select (Byte Select Start) + + 18 + 1 + read-write + + + B_0x0 + Interface captures first data (byte or double byte) from the frame/line start, second one being dropped. + 0x0 + + + B_0x1 + Interface captures second data (byte or double byte) from the frame/line start, first one being dropped. + 0x1 + + + + + LSM + Line Select mode + 19 + 1 + read-write + + + B_0x0 + Interface captures all received lines. + 0x0 + + + B_0x1 + Interface captures one line out of two. + 0x1 + + + + + OELS + Odd/Even Line Select (Line Select Start) + + 20 + 1 + read-write + + + B_0x0 + Interface captures first line after the frame start, second one being dropped. + 0x0 + + + B_0x1 + Interface captures second line from the frame start, first one being dropped. + 0x1 + + + + + + + DCMI_SR + DCMI_SR + DCMI status register + 0x04 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + HSYNC + Horizontal synchronization + + 0 + 1 + read-only + + + B_0x0 + active line + 0x0 + + + B_0x1 + synchronization between lines + 0x1 + + + + + VSYNC + Vertical synchronization + + 1 + 1 + read-only + + + B_0x0 + active frame + 0x0 + + + B_0x1 + synchronization between frames + 0x1 + + + + + FNE + FIFO not empty + + 2 + 1 + read-only + + + B_0x1 + FIFO contains valid data. + 0x1 + + + B_0x0 + FIFO empty + 0x0 + + + + + + + DCMI_RIS + DCMI_RIS + DCMI raw interrupt status register + 0x08 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + FRAME_RIS + Capture complete raw interrupt status + + 0 + 1 + read-only + + + B_0x0 + No new capture + 0x0 + + + B_0x1 + A frame has been captured. + 0x1 + + + + + OVR_RIS + Overrun raw interrupt status + + 1 + 1 + read-only + + + B_0x0 + No data buffer overrun occurred + 0x0 + + + B_0x1 + A data buffer overrun occurred and the data FIFO is corrupted. + 0x1 + + + + + ERR_RIS + Synchronization error raw interrupt status + + 2 + 1 + read-only + + + B_0x0 + No synchronization error detected + 0x0 + + + B_0x1 + Embedded synchronization characters are not received in the correct order. + 0x1 + + + + + VSYNC_RIS + DCMI_VSYNC raw interrupt status + + 3 + 1 + read-only + + + LINE_RIS + Line raw interrupt status + + 4 + 1 + read-only + + + + + DCMI_IER + DCMI_IER + DCMI interrupt enable register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FRAME_IE + Capture complete interrupt enable + 0 + 1 + read-write + + + B_0x0 + No interrupt generation + 0x0 + + + B_0x1 + An interrupt is generated at the end of each received frame/crop window (in crop mode). + 0x1 + + + + + OVR_IE + Overrun interrupt enable + 1 + 1 + read-write + + + B_0x0 + No interrupt generation + 0x0 + + + B_0x1 + An interrupt is generated if the DMA was not able to transfer the last data before new data (32-bit) are received. + 0x1 + + + + + ERR_IE + Synchronization error interrupt enable + + 2 + 1 + read-write + + + B_0x0 + No interrupt generation + 0x0 + + + B_0x1 + An interrupt is generated if the embedded synchronization codes are not received in the correct order. + 0x1 + + + + + VSYNC_IE + DCMI_VSYNC interrupt enable + + 3 + 1 + read-write + + + B_0x0 + No interrupt generation + 0x0 + + + B_0x1 + An interrupt is generated on each DCMI_VSYNC transition from the inactive to the active state. + 0x1 + + + + + LINE_IE + Line interrupt enable + 4 + 1 + read-write + + + B_0x0 + No interrupt generation when the line is received + 0x0 + + + B_0x1 + An Interrupt is generated when a line has been completely received. + 0x1 + + + + + + + DCMI_MIS + DCMI_MIS + DCMI masked interrupt status register + 0x10 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + FRAME_MIS + Capture complete masked interrupt status + + 0 + 1 + read-only + + + B_0x0 + No interrupt is generated after a complete capture. + 0x0 + + + B_0x1 + An interrupt is generated at the end of each received frame/crop window (in crop mode) and the FRAME_IE bit is set in DCMI_IER. + 0x1 + + + + + OVR_MIS + Overrun masked interrupt status + + 1 + 1 + read-only + + + B_0x0 + No interrupt is generated on overrun. + 0x0 + + + B_0x1 + An interrupt is generated if the DMA was not able to transfer the last data before new data (32-bit) are received and the OVR_IE bit is set in DCMI_IER. + 0x1 + + + + + ERR_MIS + Synchronization error masked interrupt status + + 2 + 1 + read-only + + + B_0x0 + No interrupt is generated on a synchronization error. + 0x0 + + + B_0x1 + An interrupt is generated if the embedded synchronization codes are not received in the correct order and the ERR_IE bit in DCMI_IER is set. + 0x1 + + + + + VSYNC_MIS + VSYNC masked interrupt status + + 3 + 1 + read-only + + + B_0x0 + No interrupt is generated on DCMI_VSYNC transitions. + 0x0 + + + B_0x1 + An interrupt is generated on each DCMI_VSYNC transition from the inactive to the active state and the VSYNC_IE bit is set in DCMI_IER. + 0x1 + + + + + LINE_MIS + Line masked interrupt status + + 4 + 1 + read-only + + + B_0x0 + No interrupt generation when the line is received + 0x0 + + + B_0x1 + An Interrupt is generated when a line has been completely received and the LINE_IE bit is set in DCMI_IER. + 0x1 + + + + + + + DCMI_ICR + DCMI_ICR + DCMI interrupt clear register + 0x14 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + FRAME_ISC + Capture complete interrupt status clear + + 0 + 1 + write-only + + + OVR_ISC + Overrun interrupt status clear + + 1 + 1 + write-only + + + ERR_ISC + Synchronization error interrupt status clear + + 2 + 1 + write-only + + + VSYNC_ISC + Vertical Synchronization interrupt status clear + + 3 + 1 + write-only + + + LINE_ISC + line interrupt status clear + + 4 + 1 + write-only + + + + + DCMI_ESCR + DCMI_ESCR + DCMI embedded synchronization code register + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FSC + Frame start delimiter code + + 0 + 8 + read-write + + + LSC + Line start delimiter code + + 8 + 8 + read-write + + + LEC + Line end delimiter code + + 16 + 8 + read-write + + + FEC + Frame end delimiter code + + 24 + 8 + read-write + + + + + DCMI_ESUR + DCMI_ESUR + DCMI embedded synchronization unmask register + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FSU + Frame start delimiter unmask + + 0 + 8 + read-write + + + B_0x0 + The corresponding bit in the FSC byte in DCMI_ESCR is masked while comparing the frame start delimiter with the received data. + 0x0 + + + B_0x1 + The corresponding bit in the FSC byte in DCMI_ESCR is compared while comparing the frame start delimiter with the received data. + 0x1 + + + + + LSU + Line start delimiter unmask + + 8 + 8 + read-write + + + B_0x0 + The corresponding bit in the LSC byte in DCMI_ESCR is masked while comparing the line start delimiter with the received data. + 0x0 + + + B_0x1 + The corresponding bit in the LSC byte in DCMI_ESCR is compared while comparing the line start delimiter with the received data. + 0x1 + + + + + LEU + Line end delimiter unmask + + 16 + 8 + read-write + + + B_0x0 + The corresponding bit in the LEC byte in DCMI_ESCR is masked while comparing the line end delimiter with the received data. + 0x0 + + + B_0x1 + The corresponding bit in the LEC byte in DCMI_ESCR is compared while comparing the line end delimiter with the received data. + 0x1 + + + + + FEU + Frame end delimiter unmask + + 24 + 8 + read-write + + + B_0x0 + The corresponding bit in the FEC byte in DCMI_ESCR is masked while comparing the frame end delimiter with the received data. + 0x0 + + + B_0x1 + The corresponding bit in the FEC byte in DCMI_ESCR is compared while comparing the frame end delimiter with the received data. + 0x1 + + + + + + + DCMI_CWSTRT + DCMI_CWSTRT + DCMI crop window start + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + HOFFCNT + Horizontal offset count + + 0 + 14 + read-write + + + VST + Vertical start line count + + 16 + 13 + read-write + + + B_0x0000 + line 1 + 0x0000 + + + B_0x0001 + line 2 + 0x0001 + + + B_0x0002 + line 3 + 0x0002 + + + + + + + DCMI_CWSIZE + DCMI_CWSIZE + DCMI crop window size + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CAPCNT + Capture count + + 0 + 14 + read-write + + + B_0x0000 + 1 pixel + 0x0000 + + + B_0x0001 + 2 pixels + 0x0001 + + + B_0x0002 + 3 pixels + 0x0002 + + + + + VLINE + Vertical line count + + 16 + 14 + read-write + + + B_0x0000 + 1 line + 0x0000 + + + B_0x0001 + 2 lines + 0x0001 + + + B_0x0002 + 3 lines + 0x0002 + + + + + + + DCMI_DR + DCMI_DR + DCMI data register + 0x28 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + BYTE0 + Data byte 0 + 0 + 8 + read-only + + + BYTE1 + Data byte 1 + 8 + 8 + read-only + + + BYTE2 + Data byte 2 + 16 + 8 + read-only + + + BYTE3 + Data byte 3 + 24 + 8 + read-only + + + + + + + DCMI_S + 0X5202C000 + + + DLYBOS1 + DLYB address block description + DLYB + 0x4600F000 + + 0x0 + 0x8 + registers + + + + DLYB_CR + DLYB_CR + DLYB control register + 0x000 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DEN + Delay block enable bit + 0 + 1 + read-write + + + B_0x0 + DLYB disabled. + 0x0 + + + B_0x1 + DLYB enabled. + 0x1 + + + + + SEN + Sampler length enable bit + 1 + 1 + read-write + + + B_0x0 + Sampler length and register access to UNIT[6:0] and SEL[3:0] disabled, output clock enabled. + 0x0 + + + B_0x1 + Sampler length and register access to UNIT[6:0] and SEL[3:0] enabled, output clock disabled. + 0x1 + + + + + + + DLYB_CFGR + DLYB_CFGR + DLYB configuration register + 0x004 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SEL + Phase for the output clock. + 0 + 4 + read-write + + + UNIT + Delay of a unit delay cell. + 8 + 7 + read-write + + + LNG + Delay line length value + + 16 + 12 + read-only + + + LNGF + Length valid flag + + 31 + 1 + read-only + + + B_0x0 + Length value in LNG is not valid. + 0x0 + + + B_0x1 + Length value in LNG is valid. + 0x1 + + + + + + + + + DLYBOS1_S + 0x5600F000 + + + DLYBSD1 + 0x46008400 + + + DLYBSD1_S + 0x56008400 + + + DTS + DTS address block description + DTS + 0x40008c00 + + 0x0 + 0x30 + registers + + + DTS_OR_DTS_WKUP + DTS interrupt OR DTS AIT through EXTI line + 113 + + + + DTS_CFGR1 + DTS_CFGR1 + Temperature sensor configuration register 1 + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TS1_EN + Temperature sensor 1 enable bit + + 0 + 1 + read-write + + + B_0x0 + Temperature sensor 1 disabled + 0x0 + + + B_0x1 + Temperature sensor 1 enabled + 0x1 + + + + + TS1_START + Start frequency measurement on temperature sensor 1 + + 4 + 1 + read-write + + + B_0x0 + No software trigger. + 0x0 + + + B_0x1 + Software trigger for a frequency measurement. + 0x1 + + + + + TS1_INTRIG_SEL + Input trigger selection bit for temperature sensor 1 + + 8 + 4 + read-write + + + TS1_SMP_TIME + Sampling time for temperature sensor 1 + + 16 + 4 + read-write + + + REFCLK_SEL + Reference clock selection bit + + 20 + 1 + read-write + + + B_0x0 + High speed reference clock (PCLK) + 0x0 + + + B_0x1 + Low speed reference clock (LSE) + 0x1 + + + + + Q_MEAS_OPT + Quick measurement option bit + + 21 + 1 + read-write + + + B_0x0 + Measurement with calibration + 0x0 + + + B_0x1 + Measurement without calibration + 0x1 + + + + + HSREF_CLK_DIV + High speed clock division ratio + + 24 + 7 + read-write + + + B_0x0 + No divider + 0x0 + + + B_0x1 + No divider + 0x1 + + + B_0x2 + 1/2 division ratio + 0x2 + + + B_0x7F + 1/127 division ratio + 0x7F + + + + + + + DTS_T0VALR1 + DTS_T0VALR1 + Temperature sensor T0 value register 1 + 0x08 + 0x20 + read-only + 0x00000000 + 0xFFF00000 + + + TS1_FMT0 + Engineering value of the frequency measured at T0 for + + 0 + 16 + read-only + + + TS1_T0 + Engineering value of the T0 temperature for temperature sensor 1. + 16 + 2 + read-only + + + B_0x0 + 30 C + 0x0 + + + B_0x1 + 130 C + 0x1 + + + + + + + DTS_RAMPVALR + DTS_RAMPVALR + Temperature sensor ramp value register + 0x10 + 0x20 + read-only + 0x00000000 + 0x00000000 + + + TS1_RAMP_COEFF + Engineering value of the ramp coefficient for the temperature sensor 1. + 0 + 16 + read-only + + + + + DTS_ITR1 + DTS_ITR1 + Temperature sensor interrupt threshold register 1 + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TS1_LITTHD + Low interrupt threshold for temperature sensor 1 + + 0 + 16 + read-write + + + TS1_HITTHD + High interrupt threshold for temperature sensor 1 + + 16 + 16 + read-write + + + + + DTS_DR + DTS_DR + Temperature sensor data register + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TS1_MFREQ + Value of the counter output value for temperature sensor 1 + 0 + 16 + read-write + + + + + DTS_SR + DTS_SR + Temperature sensor status register + 0x20 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + TS1_ITEF + Interrupt flag for end of measurement on temperature sensor 1, synchronized on PCLK. + 0 + 1 + read-only + + + B_0x0 + No end of measurement detected on temperature sensor 1 + 0x0 + + + B_0x1 + End of measure detected on temperature sensor 1 + 0x1 + + + + + TS1_ITLF + Interrupt flag for low threshold on temperature sensor 1, synchronized on PCLK. + 1 + 1 + read-only + + + B_0x0 + Low threshold not reached on temperature sensor 1 + 0x0 + + + B_0x1 + Low threshold reached on temperature sensor 1 + 0x1 + + + + + TS1_ITHF + Interrupt flag for high threshold on temperature sensor 1, synchronized on PCLK + + 2 + 1 + read-only + + + B_0x0 + High threshold not reached on temperature sensor 1 + 0x0 + + + B_0x1 + High threshold reached on temperature sensor 1 + 0x1 + + + + + TS1_AITEF + Asynchronous interrupt flag for end of measure on temperature sensor 1 + + 4 + 1 + read-only + + + B_0x0 + End of measure not detected on temperature sensor 1 + 0x0 + + + B_0x1 + End of measure detected on temperature sensor 1 + 0x1 + + + + + TS1_AITLF + Asynchronous interrupt flag for low threshold on temperature sensor 1 + + 5 + 1 + read-only + + + B_0x0 + Low threshold not reached on temperature sensor 1 + 0x0 + + + B_0x1 + Low threshold reached on temperature sensor 1 + 0x1 + + + + + TS1_AITHF + Asynchronous interrupt flag for high threshold on temperature sensor 1 + + 6 + 1 + read-only + + + B_0x0 + High threshold not reached on temperature sensor 1 + 0x0 + + + B_0x1 + High threshold reached on temperature sensor 1 + 0x1 + + + + + TS1_RDY + Temperature sensor 1 ready flag + + 15 + 1 + read-only + + + B_0x0 + Temperature sensor 1 busy + 0x0 + + + B_0x1 + Temperature sensor 1 ready + 0x1 + + + + + + + DTS_ITENR + DTS_ITENR + Temperature sensor interrupt enable register + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TS1_ITEEN + Interrupt enable flag for end of measurement on temperature sensor 1, synchronized on PCLK. + 0 + 1 + read-write + + + B_0x0 + Synchronous interrupt for end of measurement disabled on temperature sensor 1 + 0x0 + + + B_0x1 + Synchronous interrupt for end of measurement enabled on temperature sensor 1 + 0x1 + + + + + TS1_ITLEN + Interrupt enable flag for low threshold on temperature sensor 1, synchronized on PCLK. + 1 + 1 + read-write + + + B_0x0 + Synchronous interrupt for low threshold disabled on temperature sensor 1 + 0x0 + + + B_0x1 + Synchronous interrupt for low threshold enabled on temperature sensor 1 + 0x1 + + + + + TS1_ITHEN + Interrupt enable flag for high threshold on temperature sensor 1, synchronized on PCLK. + 2 + 1 + read-write + + + B_0x0 + Synchronous interrupt for high threshold disabled on temperature sensor 1 + 0x0 + + + B_0x1 + Synchronous interrupt for high threshold enabled on temperature sensor 1 + 0x1 + + + + + TS1_AITEEN + Asynchronous interrupt enable flag for end of measurement on temperature sensor 1 + + 4 + 1 + read-write + + + B_0x0 + Asynchronous interrupt for end of measurement disabled on temperature sensor 1 + 0x0 + + + B_0x1 + Asynchronous interrupt for end of measurement enabled on temperature sensor 1 + 0x1 + + + + + TS1_AITLEN + Asynchronous interrupt enable flag for low threshold on temperature sensor 1. + 5 + 1 + read-write + + + B_0x0 + Asynchronous interrupt on low threshold disabled for temperature sensor 1 + 0x0 + + + B_0x1 + Asynchronous interrupt on low threshold enabled for temperature sensor 1 + 0x1 + + + + + TS1_AITHEN + Asynchronous interrupt enable flag on high threshold for temperature sensor 1. + 6 + 1 + read-write + + + B_0x0 + Asynchronous interrupt on high threshold disabled for temperature sensor 1 + 0x0 + + + B_0x1 + Asynchronous interrupt on high threshold enabled for temperature sensor 1 + 0x1 + + + + + + + DTS_ICIFR + DTS_ICIFR + Temperature sensor clear interrupt flag register + 0x28 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TS1_CITEF + Interrupt clear flag for end of measurement on temperature sensor 1 + + 0 + 1 + read-write + + + TS1_CITLF + Interrupt clear flag for low threshold on temperature sensor 1 + + 1 + 1 + read-write + + + TS1_CITHF + Interrupt clear flag for high threshold on temperature sensor 1 + + 2 + 1 + read-write + + + TS1_CAITEF + Write once bit. + 4 + 1 + read-write + + + TS1_CAITLF + Asynchronous interrupt clear flag for low threshold on temperature sensor 1 + + 5 + 1 + read-write + + + TS1_CAITHF + Asynchronous interrupt clear flag for high threshold on temperature sensor 1 + + 6 + 1 + read-write + + + + + DTS_OR + DTS_OR + Temperature sensor option register + 0x2C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TS_OP0 + general purpose option bits + 0 + 1 + read-write + + + TS_OP1 + general purpose option bits + 1 + 1 + read-write + + + TS_OP2 + general purpose option bits + 2 + 1 + read-write + + + TS_OP3 + general purpose option bits + 3 + 1 + read-write + + + TS_OP4 + general purpose option bits + 4 + 1 + read-write + + + TS_OP5 + general purpose option bits + 5 + 1 + read-write + + + TS_OP6 + general purpose option bits + 6 + 1 + read-write + + + TS_OP7 + general purpose option bits + 7 + 1 + read-write + + + TS_OP8 + general purpose option bits + 8 + 1 + read-write + + + TS_OP9 + general purpose option bits + 9 + 1 + read-write + + + TS_OP10 + general purpose option bits + 10 + 1 + read-write + + + TS_OP11 + general purpose option bits + 11 + 1 + read-write + + + TS_OP12 + general purpose option bits + 12 + 1 + read-write + + + TS_OP13 + general purpose option bits + 13 + 1 + read-write + + + TS_OP14 + general purpose option bits + 14 + 1 + read-write + + + TS_OP15 + general purpose option bits + 15 + 1 + read-write + + + TS_OP16 + general purpose option bits + 16 + 1 + read-write + + + TS_OP17 + general purpose option bits + 17 + 1 + read-write + + + TS_OP18 + general purpose option bits + 18 + 1 + read-write + + + TS_OP19 + general purpose option bits + 19 + 1 + read-write + + + TS_OP20 + general purpose option bits + 20 + 1 + read-write + + + TS_OP21 + general purpose option bits + 21 + 1 + read-write + + + TS_OP22 + general purpose option bits + 22 + 1 + read-write + + + TS_OP23 + general purpose option bits + 23 + 1 + read-write + + + TS_OP24 + general purpose option bits + 24 + 1 + read-write + + + TS_OP25 + general purpose option bits + 25 + 1 + read-write + + + TS_OP26 + general purpose option bits + 26 + 1 + read-write + + + TS_OP27 + general purpose option bits + 27 + 1 + read-write + + + TS_OP28 + general purpose option bits + 28 + 1 + read-write + + + TS_OP29 + general purpose option bits + 29 + 1 + read-write + + + TS_OP30 + general purpose option bits + 30 + 1 + read-write + + + TS_OP31 + general purpose option bits + 31 + 1 + read-write + + + + + + + DTS_S + 0X50008C00 + + + EXTI + EXTI address block description + EXTI + 0x44022000 + + 0x0 + 0x98 + registers + + + EXTI15 + EXTI Line15 interrupt + 26 + + + EXTI14 + EXTI Line14 interrupt + 25 + + + EXTI13 + EXTI Line13 interrupt + 24 + + + EXTI12 + EXTI Line12 interrupt + 23 + + + EXTI11 + EXTI Line11 interrupt + 22 + + + EXTI10 + EXTI Line10 interrupt + 21 + + + EXTI9 + EXTI Line9 interrupt + 20 + + + EXTI8 + EXTI Line8 interrupt + 19 + + + EXTI7 + EXTI Line7 interrupt + 18 + + + EXTI6 + EXTI Line6 interrupt + 17 + + + EXTI5 + EXTI Line5 interrupt + 16 + + + EXTI4 + EXTI Line4 interrupt + 15 + + + EXTI3 + EXTI Line3 interrupt + 14 + + + EXTI2 + EXTI Line2 interrupt + 13 + + + EXTI1 + EXTI Line1 interrupt + 12 + + + EXTI0 + EXTI Line0 interrupt + 11 + + + FPU + Floating point interrupt + 103 + + + CEC + HDMI-CEC global interrupt + 119 + + + + EXTI_RTSR1 + EXTI_RTSR1 + EXTI rising trigger selection register + 0x000 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RT0 + Rising trigger event configuration bit of configurable event input x + + 0 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT1 + Rising trigger event configuration bit of configurable event input x + + 1 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT2 + Rising trigger event configuration bit of configurable event input x + + 2 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT3 + Rising trigger event configuration bit of configurable event input x + + 3 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT4 + Rising trigger event configuration bit of configurable event input x + + 4 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT5 + Rising trigger event configuration bit of configurable event input x + + 5 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT6 + Rising trigger event configuration bit of configurable event input x + + 6 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT7 + Rising trigger event configuration bit of configurable event input x + + 7 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT8 + Rising trigger event configuration bit of configurable event input x + + 8 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT9 + Rising trigger event configuration bit of configurable event input x + + 9 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT10 + Rising trigger event configuration bit of configurable event input x + + 10 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT11 + Rising trigger event configuration bit of configurable event input x + + 11 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT12 + Rising trigger event configuration bit of configurable event input x + + 12 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT13 + Rising trigger event configuration bit of configurable event input x + + 13 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT14 + Rising trigger event configuration bit of configurable event input x + + 14 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT15 + Rising trigger event configuration bit of configurable event input x + + 15 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT16 + Rising trigger event configuration bit of configurable event input x + + 16 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + + + EXTI_FTSR1 + EXTI_FTSR1 + EXTI falling trigger selection register + 0x004 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FT0 + Falling trigger event configuration bit of configurable event input x + + 0 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and Interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and Interrupt) for input line. + 0x1 + + + + + FT1 + Falling trigger event configuration bit of configurable event input x + + 1 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and Interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and Interrupt) for input line. + 0x1 + + + + + FT2 + Falling trigger event configuration bit of configurable event input x + + 2 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and Interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and Interrupt) for input line. + 0x1 + + + + + FT3 + Falling trigger event configuration bit of configurable event input x + + 3 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and Interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and Interrupt) for input line. + 0x1 + + + + + FT4 + Falling trigger event configuration bit of configurable event input x + + 4 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and Interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and Interrupt) for input line. + 0x1 + + + + + FT5 + Falling trigger event configuration bit of configurable event input x + + 5 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and Interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and Interrupt) for input line. + 0x1 + + + + + FT6 + Falling trigger event configuration bit of configurable event input x + + 6 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and Interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and Interrupt) for input line. + 0x1 + + + + + FT7 + Falling trigger event configuration bit of configurable event input x + + 7 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and Interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and Interrupt) for input line. + 0x1 + + + + + FT8 + Falling trigger event configuration bit of configurable event input x + + 8 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and Interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and Interrupt) for input line. + 0x1 + + + + + FT9 + Falling trigger event configuration bit of configurable event input x + + 9 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and Interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and Interrupt) for input line. + 0x1 + + + + + FT10 + Falling trigger event configuration bit of configurable event input x + + 10 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and Interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and Interrupt) for input line. + 0x1 + + + + + FT11 + Falling trigger event configuration bit of configurable event input x + + 11 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and Interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and Interrupt) for input line. + 0x1 + + + + + FT12 + Falling trigger event configuration bit of configurable event input x + + 12 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and Interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and Interrupt) for input line. + 0x1 + + + + + FT13 + Falling trigger event configuration bit of configurable event input x + + 13 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and Interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and Interrupt) for input line. + 0x1 + + + + + FT14 + Falling trigger event configuration bit of configurable event input x + + 14 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and Interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and Interrupt) for input line. + 0x1 + + + + + FT15 + Falling trigger event configuration bit of configurable event input x + + 15 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and Interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and Interrupt) for input line. + 0x1 + + + + + FT16 + Falling trigger event configuration bit of configurable event input x + + 16 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and Interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and Interrupt) for input line. + 0x1 + + + + + + + EXTI_SWIER1 + EXTI_SWIER1 + EXTI software interrupt event register + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SWI0 + Software interrupt on event x + + 0 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. + 0x1 + + + + + SWI1 + Software interrupt on event x + + 1 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. + 0x1 + + + + + SWI2 + Software interrupt on event x + + 2 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. + 0x1 + + + + + SWI3 + Software interrupt on event x + + 3 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. + 0x1 + + + + + SWI4 + Software interrupt on event x + + 4 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. + 0x1 + + + + + SWI5 + Software interrupt on event x + + 5 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. + 0x1 + + + + + SWI6 + Software interrupt on event x + + 6 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. + 0x1 + + + + + SWI7 + Software interrupt on event x + + 7 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. + 0x1 + + + + + SWI8 + Software interrupt on event x + + 8 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. + 0x1 + + + + + SWI9 + Software interrupt on event x + + 9 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. + 0x1 + + + + + SWI10 + Software interrupt on event x + + 10 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. + 0x1 + + + + + SWI11 + Software interrupt on event x + + 11 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. + 0x1 + + + + + SWI12 + Software interrupt on event x + + 12 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. + 0x1 + + + + + SWI13 + Software interrupt on event x + + 13 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. + 0x1 + + + + + SWI14 + Software interrupt on event x + + 14 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. + 0x1 + + + + + SWI15 + Software interrupt on event x + + 15 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. + 0x1 + + + + + SWI16 + Software interrupt on event x + + 16 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. + 0x1 + + + + + + + EXTI_RPR1 + EXTI_RPR1 + EXTI rising edge pending register + 0x00C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RPIF0 + configurable event inputs x rising edge pending bit + + 0 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF1 + configurable event inputs x rising edge pending bit + + 1 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF2 + configurable event inputs x rising edge pending bit + + 2 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF3 + configurable event inputs x rising edge pending bit + + 3 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF4 + configurable event inputs x rising edge pending bit + + 4 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF5 + configurable event inputs x rising edge pending bit + + 5 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF6 + configurable event inputs x rising edge pending bit + + 6 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF7 + configurable event inputs x rising edge pending bit + + 7 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF8 + configurable event inputs x rising edge pending bit + + 8 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF9 + configurable event inputs x rising edge pending bit + + 9 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF10 + configurable event inputs x rising edge pending bit + + 10 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF11 + configurable event inputs x rising edge pending bit + + 11 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF12 + configurable event inputs x rising edge pending bit + + 12 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF13 + configurable event inputs x rising edge pending bit + + 13 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF14 + configurable event inputs x rising edge pending bit + + 14 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF15 + configurable event inputs x rising edge pending bit + + 15 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF16 + configurable event inputs x rising edge pending bit + + 16 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + + + EXTI_FPR1 + EXTI_FPR1 + EXTI falling edge pending register + 0x010 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FPIF0 + configurable event inputs x falling edge pending bit + + 0 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF1 + configurable event inputs x falling edge pending bit + + 1 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF2 + configurable event inputs x falling edge pending bit + + 2 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF3 + configurable event inputs x falling edge pending bit + + 3 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF4 + configurable event inputs x falling edge pending bit + + 4 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF5 + configurable event inputs x falling edge pending bit + + 5 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF6 + configurable event inputs x falling edge pending bit + + 6 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF7 + configurable event inputs x falling edge pending bit + + 7 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF8 + configurable event inputs x falling edge pending bit + + 8 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF9 + configurable event inputs x falling edge pending bit + + 9 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF10 + configurable event inputs x falling edge pending bit + + 10 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF11 + configurable event inputs x falling edge pending bit + + 11 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF12 + configurable event inputs x falling edge pending bit + + 12 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF13 + configurable event inputs x falling edge pending bit + + 13 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF14 + configurable event inputs x falling edge pending bit + + 14 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF15 + configurable event inputs x falling edge pending bit + + 15 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF16 + configurable event inputs x falling edge pending bit + + 16 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + + + EXTI_SECCFGR1 + EXTI_SECCFGR1 + EXTI security configuration register + 0x014 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SEC0 + Security enable on event input x + + 0 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC1 + Security enable on event input x + + 1 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC2 + Security enable on event input x + + 2 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC3 + Security enable on event input x + + 3 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC4 + Security enable on event input x + + 4 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC5 + Security enable on event input x + + 5 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC6 + Security enable on event input x + + 6 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC7 + Security enable on event input x + + 7 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC8 + Security enable on event input x + + 8 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC9 + Security enable on event input x + + 9 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC10 + Security enable on event input x + + 10 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC11 + Security enable on event input x + + 11 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC12 + Security enable on event input x + + 12 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC13 + Security enable on event input x + + 13 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC14 + Security enable on event input x + + 14 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC15 + Security enable on event input x + + 15 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC16 + Security enable on event input x + + 16 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC17 + Security enable on event input x + + 17 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC18 + Security enable on event input x + + 18 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC19 + Security enable on event input x + + 19 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC20 + Security enable on event input x + + 20 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC21 + Security enable on event input x + + 21 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC22 + Security enable on event input x + + 22 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC23 + Security enable on event input x + + 23 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC24 + Security enable on event input x + + 24 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC25 + Security enable on event input x + + 25 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC26 + Security enable on event input x + + 26 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC27 + Security enable on event input x + + 27 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC28 + Security enable on event input x + + 28 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC29 + Security enable on event input x + + 29 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC30 + Security enable on event input x + + 30 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC31 + Security enable on event input x + + 31 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + + + EXTI_PRIVCFGR1 + EXTI_PRIVCFGR1 + EXTI privilege configuration register + 0x018 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRIV0 + Security enable on event input x + + 0 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV1 + Security enable on event input x + + 1 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV2 + Security enable on event input x + + 2 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV3 + Security enable on event input x + + 3 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV4 + Security enable on event input x + + 4 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV5 + Security enable on event input x + + 5 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV6 + Security enable on event input x + + 6 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV7 + Security enable on event input x + + 7 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV8 + Security enable on event input x + + 8 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV9 + Security enable on event input x + + 9 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV10 + Security enable on event input x + + 10 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV11 + Security enable on event input x + + 11 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV12 + Security enable on event input x + + 12 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV13 + Security enable on event input x + + 13 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV14 + Security enable on event input x + + 14 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV15 + Security enable on event input x + + 15 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV16 + Security enable on event input x + + 16 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV17 + Security enable on event input x + + 17 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV18 + Security enable on event input x + + 18 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV19 + Security enable on event input x + + 19 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV20 + Security enable on event input x + + 20 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV21 + Security enable on event input x + + 21 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV22 + Security enable on event input x + + 22 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV23 + Security enable on event input x + + 23 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV24 + Security enable on event input x + + 24 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV25 + Security enable on event input x + + 25 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV26 + Security enable on event input x + + 26 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV27 + Security enable on event input x + + 27 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV28 + Security enable on event input x + + 28 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV29 + Security enable on event input x + + 29 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV30 + Security enable on event input x + + 30 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV31 + Security enable on event input x + + 31 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + + + EXTI_RTSR2 + EXTI_RTSR2 + EXTI rising trigger selection register 2 + 0x020 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RT46 + Rising trigger event configuration bit of configurable event input xless thansup>(1)less than/sup> + + 14 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT50 + Rising trigger event configuration bit of configurable event input xless thansup>(1)less than/sup> + + 18 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT53 + Rising trigger event configuration bit of configurable event input x + + 21 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + + + EXTI_FTSR2 + EXTI_FTSR2 + EXTI falling trigger selection register 2 + 0x024 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FT46 + Falling trigger event configuration bit of configurable event input x less thansup>(1)less than/sup> + + 14 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and Interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and Interrupt) for input line. + 0x1 + + + + + FT50 + Falling trigger event configuration bit of configurable event input x less thansup>(1)less than/sup> + + 18 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and Interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and Interrupt) for input line. + 0x1 + + + + + FT53 + Falling trigger event configuration bit of configurable event input x + + 21 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and Interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and Interrupt) for input line. + 0x1 + + + + + + + EXTI_SWIER2 + EXTI_SWIER2 + EXTI software interrupt event register 2 + 0x028 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SWI46 + Software interrupt on event x + + 14 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. + 0x1 + + + + + SWI50 + Software interrupt on event x + + 18 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. + 0x1 + + + + + SWI53 + Software interrupt on event x + + 21 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. + 0x1 + + + + + + + EXTI_RPR2 + EXTI_RPR2 + EXTI rising edge pending register 2 + 0x02C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RPIF46 + configurable event inputs x rising edge pending bit + + 14 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF50 + configurable event inputs x rising edge pending bit + + 18 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF53 + configurable event inputs x rising edge pending bit + + 21 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + + + EXTI_FPR2 + EXTI_FPR2 + EXTI falling edge pending register 2 + 0x030 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FPIF46 + configurable event inputs x falling edge pending bit + + 14 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF50 + configurable event inputs x falling edge pending bit + + 18 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF53 + configurable event inputs x falling edge pending bit + + 21 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + + + EXTI_SECCFGR2 + EXTI_SECCFGR2 + EXTI security configuration register 2 + 0x034 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SEC32 + Security enable on event input x + + 0 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC33 + Security enable on event input x + + 1 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC34 + Security enable on event input x + + 2 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC35 + Security enable on event input x + + 3 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC36 + Security enable on event input x + + 4 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC37 + Security enable on event input x + + 5 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC38 + Security enable on event input x + + 6 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC39 + Security enable on event input x + + 7 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC40 + Security enable on event input x + + 8 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC41 + Security enable on event input x + + 9 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC42 + Security enable on event input x + + 10 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC43 + Security enable on event input x + + 11 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC44 + Security enable on event input x + + 12 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC45 + Security enable on event input x + + 13 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC46 + Security enable on event input x + + 14 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC47 + Security enable on event input x + + 15 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC48 + Security enable on event input x + + 16 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC49 + Security enable on event input x + + 17 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC50 + Security enable on event input x + + 18 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC51 + Security enable on event input x + + 19 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC52 + Security enable on event input x + + 20 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC53 + Security enable on event input x + + 21 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC54 + Security enable on event input x + + 22 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC55 + Security enable on event input x + + 23 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC56 + Security enable on event input x + + 24 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC57 + Security enable on event input x + + 25 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + + + EXTI_PRIVCFGR2 + EXTI_PRIVCFGR2 + EXTI privilege configuration register 2 + 0x038 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRIV32 + Security enable on event input x + + 0 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV33 + Security enable on event input x + + 1 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV34 + Security enable on event input x + + 2 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV35 + Security enable on event input x + + 3 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV36 + Security enable on event input x + + 4 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV37 + Security enable on event input x + + 5 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV38 + Security enable on event input x + + 6 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV39 + Security enable on event input x + + 7 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV40 + Security enable on event input x + + 8 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV41 + Security enable on event input x + + 9 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV42 + Security enable on event input x + + 10 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV43 + Security enable on event input x + + 11 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV44 + Security enable on event input x + + 12 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV45 + Security enable on event input x + + 13 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV46 + Security enable on event input x + + 14 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV47 + Security enable on event input x + + 15 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV48 + Security enable on event input x + + 16 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV49 + Security enable on event input x + + 17 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV50 + Security enable on event input x + + 18 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV51 + Security enable on event input x + + 19 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV52 + Security enable on event input x + + 20 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV53 + Security enable on event input x + + 21 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV54 + Security enable on event input x + + 22 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV55 + Security enable on event input x + + 23 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV56 + Security enable on event input x + + 24 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV57 + Security enable on event input x + + 25 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + + + EXTI_EXTICR1 + EXTI_EXTICR1 + EXTI external interrupt selection register + 0x060 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EXTI0 + EXTI0 GPIO port selection + + 0 + 8 + read-write + + + B_0x00 + PA0 pin + 0x00 + + + B_0x01 + PB0 pin + 0x01 + + + B_0x02 + PC0 pin + 0x02 + + + B_0x03 + PD0 pin + 0x03 + + + B_0x04 + PE0 pin + 0x04 + + + B_0x05 + PF0 pin + 0x05 + + + B_0x06 + PG0 pin + 0x06 + + + B_0x07 + PH0 pin + 0x07 + + + B_0x08 + PI0 pin + 0x08 + + + + + EXTI1 + EXTI1 GPIO port selection + + 8 + 8 + read-write + + + B_0x00 + PA1 pin + 0x00 + + + B_0x01 + PB1 pin + 0x01 + + + B_0x02 + PC1 pin + 0x02 + + + B_0x03 + PD1 pin + 0x03 + + + B_0x04 + PE1 pin + 0x04 + + + B_0x05 + PF1 pin + 0x05 + + + B_0x06 + PG1 pin + 0x06 + + + B_0x07 + PH1 pin + 0x07 + + + B_0x08 + PI1 pin + 0x08 + + + + + EXTI2 + EXTI2 GPIO port selection + + 16 + 8 + read-write + + + B_0x00 + PA2 pin + 0x00 + + + B_0x01 + PB2 pin + 0x01 + + + B_0x02 + PC2 pin + 0x02 + + + B_0x03 + PD2 pin + 0x03 + + + B_0x04 + PE2 pin + 0x04 + + + B_0x05 + PF2 pin + 0x05 + + + B_0x06 + PG2 pin + 0x06 + + + B_0x07 + PH2 pin + 0x07 + + + B_0x08 + PI2 pin + 0x08 + + + + + EXTI3 + EXTI3 GPIO port selection + + 24 + 8 + read-write + + + B_0x00 + PA3 pin + 0x00 + + + B_0x01 + PB3 pin + 0x01 + + + B_0x02 + PC3 pin + 0x02 + + + B_0x03 + PD3 pin + 0x03 + + + B_0x04 + PE3 pin + 0x04 + + + B_0x05 + PF3 pin + 0x05 + + + B_0x06 + PG3 pin + 0x06 + + + B_0x07 + PH3 pin + 0x07 + + + B_0x08 + PI3 pin + 0x08 + + + + + + + EXTI_EXTICR4 + EXTI_EXTICR4 + EXTI external interrupt selection register + EXTI_EXTICR1 + 0x060 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EXTI12 + EXTI12 GPIO port selection + + 0 + 8 + read-write + + + B_0x00 + PA12 pin + 0x00 + + + B_0x01 + PB12 pin + 0x01 + + + B_0x02 + PC12 pin + 0x02 + + + B_0x03 + PD12 pin + 0x03 + + + B_0x04 + PE12 pin + 0x04 + + + B_0x05 + PF12 pin + 0x05 + + + B_0x06 + PG12 pin + 0x06 + + + B_0x07 + PH12 pin + 0x07 + + + + + EXTI13 + EXTI13 GPIO port selection + + 8 + 8 + read-write + + + B_0x00 + PA13 pin + 0x00 + + + B_0x01 + PB13 pin + 0x01 + + + B_0x02 + PC13 pin + 0x02 + + + B_0x03 + PD13 pin + 0x03 + + + B_0x04 + PE13 pin + 0x04 + + + B_0x05 + PF13 pin + 0x05 + + + B_0x06 + PG13 pin + 0x06 + + + B_0x07 + PH13 pin + 0x07 + + + + + EXTI14 + EXTI14 GPIO port selection + + 16 + 8 + read-write + + + B_0x00 + PA14 pin + 0x00 + + + B_0x01 + PB14 pin + 0x01 + + + B_0x02 + PC14 pin + 0x02 + + + B_0x03 + PD14 pin + 0x03 + + + B_0x04 + PE14 pin + 0x04 + + + B_0x05 + PF14 pin + 0x05 + + + B_0x06 + PG14 pin + 0x06 + + + B_0x07 + PH14 pin + 0x07 + + + + + EXTI15 + EXTI15 GPIO port selection + + 24 + 8 + read-write + + + B_0x00 + PA15 pin + 0x00 + + + B_0x01 + PB15 pin + 0x01 + + + B_0x02 + PC15 pin + 0x02 + + + B_0x03 + PD15 pin + 0x03 + + + B_0x04 + PE15 pin + 0x04 + + + B_0x05 + PF15 pin + 0x05 + + + B_0x06 + PG15 pin + 0x06 + + + B_0x07 + PH15 pin + 0x07 + + + + + + + EXTI_EXTICR2 + EXTI_EXTICR2 + EXTI external interrupt selection register + 0x064 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EXTI4 + EXTI4 GPIO port selection + + 0 + 8 + read-write + + + B_0x00 + PA4 pin + 0x00 + + + B_0x01 + PB4 pin + 0x01 + + + B_0x02 + PC4 pin + 0x02 + + + B_0x03 + PD4 pin + 0x03 + + + B_0x04 + PE4 pin + 0x04 + + + B_0x05 + PF4 pin + 0x05 + + + B_0x06 + PG4 pin + 0x06 + + + B_0x07 + PH4 pin + 0x07 + + + B_0x08 + PI4 pin + 0x08 + + + + + EXTI5 + EXTI5 GPIO port selection + + 8 + 8 + read-write + + + B_0x00 + PA5 pin + 0x00 + + + B_0x01 + PB5 pin + 0x01 + + + B_0x02 + PC5 pin + 0x02 + + + B_0x03 + PD5 pin + 0x03 + + + B_0x04 + PE5 pin + 0x04 + + + B_0x05 + PF5 pin + 0x05 + + + B_0x06 + PG5 pin + 0x06 + + + B_0x07 + PH5 pin + 0x07 + + + B_0x08 + PI5 pin + 0x08 + + + + + EXTI6 + EXTI6 GPIO port selection + + 16 + 8 + read-write + + + B_0x00 + PA6 pin + 0x00 + + + B_0x01 + PB6 pin + 0x01 + + + B_0x02 + PC6 pin + 0x02 + + + B_0x03 + PD6 pin + 0x03 + + + B_0x04 + PE6 pin + 0x04 + + + B_0x05 + PF6 pin + 0x05 + + + B_0x06 + PG6 pin + 0x06 + + + B_0x07 + PH6 pin + 0x07 + + + B_0x08 + PI6 pin + 0x08 + + + + + EXTI7 + EXTI7 GPIO port selection + + 24 + 8 + read-write + + + B_0x00 + PA7 pin + 0x00 + + + B_0x01 + PB7 pin + 0x01 + + + B_0x02 + PC7 pin + 0x02 + + + B_0x03 + PD7 pin + 0x03 + + + B_0x04 + PE7 pin + 0x04 + + + B_0x05 + PF7 pin + 0x05 + + + B_0x06 + PG7 pin + 0x06 + + + B_0x07 + PH7 pin + 0x07 + + + B_0x08 + PI7 pin + 0x08 + + + + + + + EXTI_EXTICR3 + EXTI_EXTICR3 + EXTI external interrupt selection register + 0x068 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EXTI8 + EXTI8 GPIO port selection + + 0 + 8 + read-write + + + B_0x00 + PA8 pin + 0x00 + + + B_0x01 + PB8 pin + 0x01 + + + B_0x02 + PC8 pin + 0x02 + + + B_0x03 + PD8 pin + 0x03 + + + B_0x04 + PE8 pin + 0x04 + + + B_0x05 + PF8 pin + 0x05 + + + B_0x06 + PG8 pin + 0x06 + + + B_0x07 + PH8 pin + 0x07 + + + B_0x08 + PI8 pin + 0x08 + + + + + EXTI9 + EXTI9 GPIO port selection + + 8 + 8 + read-write + + + B_0x00 + PA9 pin + 0x00 + + + B_0x01 + PB9 pin + 0x01 + + + B_0x02 + PC9 pin + 0x02 + + + B_0x03 + PD9 pin + 0x03 + + + B_0x04 + PE9 pin + 0x04 + + + B_0x05 + PF9 pin + 0x05 + + + B_0x06 + PG9 pin + 0x06 + + + B_0x07 + PH9 pin + 0x07 + + + B_0x08 + PI9 pin + 0x08 + + + + + EXTI10 + EXTI10 GPIO port selection + + 16 + 8 + read-write + + + B_0x00 + PA10 pin + 0x00 + + + B_0x01 + PB10 pin + 0x01 + + + B_0x02 + PC10 pin + 0x02 + + + B_0x03 + PD10 pin + 0x03 + + + B_0x04 + PE10 pin + 0x04 + + + B_0x05 + PF10 pin + 0x05 + + + B_0x06 + PG10 pin + 0x06 + + + B_0x07 + PH10 pin + 0x07 + + + B_0x08 + PI10 pin + 0x08 + + + + + EXTI11 + EXTI11 GPIO port selection + + 24 + 8 + read-write + + + B_0x00 + PA11 pin + 0x00 + + + B_0x01 + PB11 pin + 0x01 + + + B_0x02 + PC11 pin + 0x02 + + + B_0x03 + PD11 pin + 0x03 + + + B_0x04 + PE11 pin + 0x04 + + + B_0x05 + PF11 pin + 0x05 + + + B_0x06 + PG11 pin + 0x06 + + + B_0x07 + PH11 pin + 0x07 + + + B_0x08 + PI11 pin + 0x08 + + + + + + + EXTI_LOCKR + EXTI_LOCKR + EXTI lock register + 0x070 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LOCK + Global security and privilege configuration registers (EXTI_SECCFGR and EXTI_PRIVCFGR) lock + + 0 + 1 + read-write + + + B_0x0 + Security and privilege configuration open, can be modified. + 0x0 + + + B_0x1 + Security and privilege configuration locked, can no longer be modified. + 0x1 + + + + + + + EXTI_IMR1 + EXTI_IMR1 + EXTI CPU wake-up with interrupt mask register + 0x080 + 0x20 + read-write + 0xFFFE0000 + 0xFFFFFFFF + + + IM0 + CPU wake-up with interrupt mask on event input x + + 0 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM1 + CPU wake-up with interrupt mask on event input x + + 1 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM2 + CPU wake-up with interrupt mask on event input x + + 2 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM3 + CPU wake-up with interrupt mask on event input x + + 3 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM4 + CPU wake-up with interrupt mask on event input x + + 4 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM5 + CPU wake-up with interrupt mask on event input x + + 5 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM6 + CPU wake-up with interrupt mask on event input x + + 6 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM7 + CPU wake-up with interrupt mask on event input x + + 7 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM8 + CPU wake-up with interrupt mask on event input x + + 8 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM9 + CPU wake-up with interrupt mask on event input x + + 9 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM10 + CPU wake-up with interrupt mask on event input x + + 10 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM11 + CPU wake-up with interrupt mask on event input x + + 11 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM12 + CPU wake-up with interrupt mask on event input x + + 12 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM13 + CPU wake-up with interrupt mask on event input x + + 13 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM14 + CPU wake-up with interrupt mask on event input x + + 14 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM15 + CPU wake-up with interrupt mask on event input x + + 15 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM16 + CPU wake-up with interrupt mask on event input x + + 16 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM17 + CPU wake-up with interrupt mask on event input x + + 17 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM18 + CPU wake-up with interrupt mask on event input x + + 18 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM19 + CPU wake-up with interrupt mask on event input x + + 19 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM20 + CPU wake-up with interrupt mask on event input x + + 20 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM21 + CPU wake-up with interrupt mask on event input x + + 21 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM22 + CPU wake-up with interrupt mask on event input x + + 22 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM23 + CPU wake-up with interrupt mask on event input x + + 23 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM24 + CPU wake-up with interrupt mask on event input x + + 24 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM25 + CPU wake-up with interrupt mask on event input x + + 25 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM26 + CPU wake-up with interrupt mask on event input x + + 26 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM27 + CPU wake-up with interrupt mask on event input x + + 27 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM28 + CPU wake-up with interrupt mask on event input x + + 28 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM29 + CPU wake-up with interrupt mask on event input x + + 29 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM30 + CPU wake-up with interrupt mask on event input x + + 30 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM31 + CPU wake-up with interrupt mask on event input x + + 31 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + + + EXTI_EMR1 + EXTI_EMR1 + EXTI CPU wake-up with event mask register + 0x084 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EM0 + CPU wake-up with event generation mask on event input x + + 0 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM1 + CPU wake-up with event generation mask on event input x + + 1 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM2 + CPU wake-up with event generation mask on event input x + + 2 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM3 + CPU wake-up with event generation mask on event input x + + 3 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM4 + CPU wake-up with event generation mask on event input x + + 4 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM5 + CPU wake-up with event generation mask on event input x + + 5 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM6 + CPU wake-up with event generation mask on event input x + + 6 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM7 + CPU wake-up with event generation mask on event input x + + 7 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM8 + CPU wake-up with event generation mask on event input x + + 8 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM9 + CPU wake-up with event generation mask on event input x + + 9 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM10 + CPU wake-up with event generation mask on event input x + + 10 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM11 + CPU wake-up with event generation mask on event input x + + 11 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM12 + CPU wake-up with event generation mask on event input x + + 12 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM13 + CPU wake-up with event generation mask on event input x + + 13 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM14 + CPU wake-up with event generation mask on event input x + + 14 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM15 + CPU wake-up with event generation mask on event input x + + 15 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM16 + CPU wake-up with event generation mask on event input x + + 16 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM17 + CPU wake-up with event generation mask on event input x + + 17 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM18 + CPU wake-up with event generation mask on event input x + + 18 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM19 + CPU wake-up with event generation mask on event input x + + 19 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM20 + CPU wake-up with event generation mask on event input x + + 20 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM21 + CPU wake-up with event generation mask on event input x + + 21 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM22 + CPU wake-up with event generation mask on event input x + + 22 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM23 + CPU wake-up with event generation mask on event input x + + 23 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM24 + CPU wake-up with event generation mask on event input x + + 24 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM25 + CPU wake-up with event generation mask on event input x + + 25 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM26 + CPU wake-up with event generation mask on event input x + + 26 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM27 + CPU wake-up with event generation mask on event input x + + 27 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM28 + CPU wake-up with event generation mask on event input x + + 28 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM29 + CPU wake-up with event generation mask on event input x + + 29 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM30 + CPU wake-up with event generation mask on event input x + + 30 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM31 + CPU wake-up with event generation mask on event input x + + 31 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + + + EXTI_IMR2 + EXTI_IMR2 + EXTI CPU wake-up with interrupt mask register 2 + 0x090 + 0x20 + read-write + 0x07DBBFFF + 0xFFFFFFFF + + + IM32 + CPU wake-up with interrupt mask on event input x + + 0 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM33 + CPU wake-up with interrupt mask on event input x + + 1 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM34 + CPU wake-up with interrupt mask on event input x + + 2 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM35 + CPU wake-up with interrupt mask on event input x + + 3 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM36 + CPU wake-up with interrupt mask on event input x + + 4 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM37 + CPU wake-up with interrupt mask on event input x + + 5 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM38 + CPU wake-up with interrupt mask on event input x + + 6 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM39 + CPU wake-up with interrupt mask on event input x + + 7 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM40 + CPU wake-up with interrupt mask on event input x + + 8 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM41 + CPU wake-up with interrupt mask on event input x + + 9 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM42 + CPU wake-up with interrupt mask on event input x + + 10 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM43 + CPU wake-up with interrupt mask on event input x + + 11 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM44 + CPU wake-up with interrupt mask on event input x + + 12 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM45 + CPU wake-up with interrupt mask on event input x + + 13 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM46 + CPU wake-up with interrupt mask on event input x + + 14 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM47 + CPU wake-up with interrupt mask on event input x + + 15 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM48 + CPU wake-up with interrupt mask on event input x + + 16 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM49 + CPU wake-up with interrupt mask on event input x + + 17 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM50 + CPU wake-up with interrupt mask on event input x + + 18 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM51 + CPU wake-up with interrupt mask on event input x + + 19 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM52 + CPU wake-up with interrupt mask on event input x + + 20 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM53 + CPU wake-up with interrupt mask on event input x + + 21 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM54 + CPU wake-up with interrupt mask on event input x + + 22 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM55 + CPU wake-up with interrupt mask on event input x + + 23 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM56 + CPU wake-up with interrupt mask on event input x + + 24 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM57 + CPU wake-up with interrupt mask on event input x + + 25 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM58 + CPU wake-up with interrupt mask on event input x + + 26 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + + + EXTI_EMR2 + EXTI_EMR2 + EXTI CPU wake-up with event mask register 2 + 0x094 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EM32 + CPU wake-up with event generation mask on event input x + + 0 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM33 + CPU wake-up with event generation mask on event input x + + 1 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM34 + CPU wake-up with event generation mask on event input x + + 2 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM35 + CPU wake-up with event generation mask on event input x + + 3 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM36 + CPU wake-up with event generation mask on event input x + + 4 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM37 + CPU wake-up with event generation mask on event input x + + 5 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM38 + CPU wake-up with event generation mask on event input x + + 6 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM39 + CPU wake-up with event generation mask on event input x + + 7 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM40 + CPU wake-up with event generation mask on event input x + + 8 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM41 + CPU wake-up with event generation mask on event input x + + 9 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM42 + CPU wake-up with event generation mask on event input x + + 10 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM43 + CPU wake-up with event generation mask on event input x + + 11 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM44 + CPU wake-up with event generation mask on event input x + + 12 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM45 + CPU wake-up with event generation mask on event input x + + 13 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM46 + CPU wake-up with event generation mask on event input x + + 14 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM47 + CPU wake-up with event generation mask on event input x + + 15 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM48 + CPU wake-up with event generation mask on event input x + + 16 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM49 + CPU wake-up with event generation mask on event input x + + 17 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM50 + CPU wake-up with event generation mask on event input x + + 18 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM51 + CPU wake-up with event generation mask on event input x + + 19 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM52 + CPU wake-up with event generation mask on event input x + + 20 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM53 + CPU wake-up with event generation mask on event input x + + 21 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM54 + CPU wake-up with event generation mask on event input x + + 22 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM55 + CPU wake-up with event generation mask on event input x + + 23 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM56 + CPU wake-up with event generation mask on event input x + + 24 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM57 + CPU wake-up with event generation mask on event input x + + 25 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM58 + CPU wake-up with event generation mask on event input x + + 26 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + + + + + EXTI_S + 0X54022000 + + + FDCAN + FDCAN register blank and RAM + FDCAN + 0x4000a400 + + 0x0 + 0x400 + registers + + + FDCAN1_IT1 + FDCAN1 Interrupt 1 + 40 + + + FDCAN1_IT0 + FDCAN1 Interrupt 0 + 39 + + + + FDCAN_CREL + FDCAN_CREL + FDCAN core release register + 0x0000 + 0x20 + read-only + 0x32141218 + 0xFFFFFFFF + + + DAY + 18 + 0 + 8 + read-only + + + MON + 12 + 8 + 8 + read-only + + + YEAR + 4 + 16 + 4 + read-only + + + SUBSTEP + 1 + 20 + 4 + read-only + + + STEP + 2 + 24 + 4 + read-only + + + REL + 3 + 28 + 4 + read-only + + + + + FDCAN_ENDN + FDCAN_ENDN + FDCAN endian register + 0x0004 + 0x20 + read-only + 0x87654321 + 0xFFFFFFFF + + + ETV + Endianness test value + + 0 + 32 + read-only + + + + + FDCAN_DBTP + FDCAN_DBTP + FDCAN data bit timing and prescaler register + 0x000C + 0x20 + read-write + 0x00000A33 + 0xFFFFFFFF + + + DSJW + Synchronization jump width + + 0 + 4 + read-write + + + DTSEG2 + Data time segment after sample point + + 4 + 4 + read-write + + + DTSEG1 + Data time segment before sample point + + 8 + 5 + read-write + + + DBRP + Data bit rate prescaler + + 16 + 5 + read-write + + + TDC + Transceiver delay compensation + 23 + 1 + read-write + + + B_0x0 + Transceiver delay compensation disabled + 0x0 + + + B_0x1 + Transceiver delay compensation enabled + 0x1 + + + + + + + FDCAN_TEST + FDCAN_TEST + FDCAN test register + 0x0010 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LBCK + Loop back mode + 4 + 1 + read-write + + + B_0x0 + Reset value, Loop Back mode is disabled + 0x0 + + + B_0x1 + Loop Back mode is enabled (see Power down (Sleep mode)) + 0x1 + + + + + TX + Control of transmit pin + 5 + 2 + read-write + + + B_0x0 + Reset value, FDCANx_TX TX is controlled by the CAN core, updated at the end of the CAN bit time + 0x0 + + + B_0x1 + Sample point can be monitored at pin FDCANx_TX + 0x1 + + + B_0x2 + Dominant (0) level at pin FDCANx_TX + 0x2 + + + B_0x3 + Recessive (1) at pin FDCANx_TX + 0x3 + + + + + RX + Receive pin + + 7 + 1 + read-only + + + B_0x0 + The CAN bus is dominant (FDCANx_RX = 0) + 0x0 + + + B_0x1 + The CAN bus is recessive (FDCANx_RX = 1) + 0x1 + + + + + + + FDCAN_RWD + FDCAN_RWD + FDCAN RAM watchdog register + 0x0014 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + WDC + Watchdog configuration + + 0 + 8 + read-write + + + WDV + Watchdog value + + 8 + 8 + read-only + + + + + FDCAN_CCCR + FDCAN_CCCR + FDCAN CC control register + 0x0018 + 0x20 + read-write + 0x00000001 + 0xFFFFFFFF + + + INIT + Initialization + 0 + 1 + read-write + + + B_0x0 + Normal operation + 0x0 + + + B_0x1 + Initialization started + 0x1 + + + + + CCE + Configuration change enable + 1 + 1 + read-write + + + B_0x0 + The CPU has no write access to the protected configuration registers. + 0x0 + + + B_0x1 + The CPU has write access to the protected configuration registers (while CCCR. + 0x1 + + + + + ASM + ASM restricted operation mode + + 2 + 1 + read-write + + + B_0x0 + Normal CAN operation + 0x0 + + + B_0x1 + Restricted operation mode active + 0x1 + + + + + CSA + Clock stop acknowledge + 3 + 1 + read-only + + + B_0x0 + No clock stop acknowledged + 0x0 + + + B_0x1 + FDCAN can be set in power down by stopping APB clock and kernel clock. + 0x1 + + + + + CSR + Clock stop request + 4 + 1 + read-write + + + B_0x0 + No clock stop requested + 0x0 + + + B_0x1 + Clock stop requested. + 0x1 + + + + + MON + Bus monitoring mode + + 5 + 1 + read-write + + + B_0x0 + Bus monitoring mode disabled + 0x0 + + + B_0x1 + Bus monitoring mode enabled + 0x1 + + + + + DAR + Disable automatic retransmission + 6 + 1 + read-write + + + B_0x0 + Automatic retransmission of messages not transmitted successfully enabled + 0x0 + + + B_0x1 + Automatic retransmission disabled + 0x1 + + + + + TEST + Test mode enable + 7 + 1 + read-write + + + B_0x0 + Normal operation, register TEST holds reset values + 0x0 + + + B_0x1 + Test Mode, write access to register TEST enabled + 0x1 + + + + + FDOE + FD operation enable + 8 + 1 + read-write + + + B_0x0 + FD operation disabled + 0x0 + + + B_0x1 + FD operation enabled + 0x1 + + + + + BRSE + FDCAN bit rate switching + 9 + 1 + read-write + + + B_0x0 + Bit rate switching for transmissions disabled + 0x0 + + + B_0x1 + Bit rate switching for transmissions enabled + 0x1 + + + + + PXHD + Protocol exception handling disable + 12 + 1 + read-write + + + B_0x0 + Protocol exception handling enabled + 0x0 + + + B_0x1 + Protocol exception handling disabled + 0x1 + + + + + EFBI + Edge filtering during bus integration + 13 + 1 + read-write + + + B_0x0 + Edge filtering disabled + 0x0 + + + B_0x1 + Two consecutive dominant tq required to detect an edge for hard synchronization + 0x1 + + + + + TXP + If this bit is set, the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame. + 14 + 1 + read-write + + + B_0x0 + disabled + 0x0 + + + B_0x1 + enabled + 0x1 + + + + + NISO + Non ISO operation + + 15 + 1 + read-write + + + B_0x0 + CAN FD frame format according to ISO11898-1 + 0x0 + + + B_0x1 + CAN FD frame format according to Bosch CAN FD Specification V1. + 0x1 + + + + + + + FDCAN_NBTP + FDCAN_NBTP + FDCAN nominal bit timing and prescaler register + 0x001C + 0x20 + read-write + 0x06000A03 + 0xFFFFFFFF + + + NTSEG2 + Nominal time segment after sample point + + 0 + 7 + read-write + + + NTSEG1 + Nominal time segment before sample point + + 8 + 8 + read-write + + + NBRP + Bit rate prescaler + + 16 + 9 + read-write + + + NSJW + Nominal (re)synchronization jump width + + 25 + 7 + read-write + + + + + FDCAN_TSCC + FDCAN_TSCC + FDCAN timestamp counter configuration register + 0x0020 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TSS + Timestamp select + + 0 + 2 + read-write + + + B_0x0 + Timestamp counter value always 0x0000 + 0x0 + + + B_0x1 + Timestamp counter value incremented according to TCP + 0x1 + + + B_0x2 + External timestamp counter from TIM3 value (tim3_cnt[0:15]) + 0x2 + + + B_0x3 + Same as 00. + 0x3 + + + + + TCP + Timestamp counter prescaler + + 16 + 4 + read-write + + + + + FDCAN_TSCV + FDCAN_TSCV + FDCAN timestamp counter value register + 0x0024 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TSC + Timestamp counter + + 0 + 16 + read-write + + + + + FDCAN_TOCC + FDCAN_TOCC + FDCAN timeout counter configuration register + 0x0028 + 0x20 + read-write + 0xFFFF0000 + 0xFFFFFFFF + + + ETOC + Timeout counter enable + + 0 + 1 + read-write + + + B_0x0 + Timeout counter disabled + 0x0 + + + B_0x1 + Timeout counter enabled + 0x1 + + + + + TOS + Timeout select + + 1 + 2 + read-write + + + B_0x0 + Continuous operation + 0x0 + + + B_0x1 + Timeout controlled by Tx event FIFO + 0x1 + + + B_0x2 + Timeout controlled by Rx FIFO 0 + 0x2 + + + B_0x3 + Timeout controlled by Rx FIFO 1 + 0x3 + + + + + TOP + Timeout period + + 16 + 16 + read-write + + + + + FDCAN_TOCV + FDCAN_TOCV + FDCAN timeout counter value register + 0x002C + 0x20 + read-write + 0x0000FFFF + 0xFFFFFFFF + + + TOC + Timeout counter + + 0 + 16 + read-write + + + + + FDCAN_ECR + FDCAN_ECR + FDCAN error counter register + 0x0040 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TEC + Transmit error counter + + 0 + 8 + read-only + + + REC + Receive error counter + + 8 + 7 + read-only + + + RP + Receive error passive + 15 + 1 + read-only + + + B_0x0 + The receive error counter is below the error passive level of 128. + 0x0 + + + B_0x1 + The receive error counter has reached the error passive level of 128. + 0x1 + + + + + CEL + CAN error logging + + 16 + 8 + read-write + + + + + FDCAN_PSR + FDCAN_PSR + FDCAN protocol status register + 0x0044 + 0x20 + read-write + 0x00000707 + 0xFFFFFFFF + + + LEC + Last error code + + 0 + 3 + read-write + + + B_0x0 + No Error: No error occurred since LEC has been reset by successful reception or transmission. + 0x0 + + + B_0x1 + Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. + 0x1 + + + B_0x2 + Form Error: A fixed format part of a received frame has the wrong format. + 0x2 + + + B_0x3 + AckError: The message transmitted by the FDCAN was not acknowledged by another node. + 0x3 + + + B_0x4 + Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value 1), but the monitored bus value was dominant. + 0x4 + + + B_0x5 + Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value 0), but the monitored bus value was recessive. + 0x5 + + + B_0x6 + CRCError: The CRC check sum of a received message was incorrect. + 0x6 + + + B_0x7 + NoChange: Any read access to the Protocol status register re-initializes the LEC to 7'. + 0x7 + + + + + ACT + Activity + + 3 + 2 + read-only + + + B_0x0 + Synchronizing: node is synchronizing on CAN communication. + 0x0 + + + B_0x1 + Idle: node is neither receiver nor transmitter. + 0x1 + + + B_0x2 + Receiver: node is operating as receiver. + 0x2 + + + B_0x3 + Transmitter: node is operating as transmitter. + 0x3 + + + + + EP + Error passive + 5 + 1 + read-only + + + B_0x0 + The FDCAN is in the Error_Active state. + 0x0 + + + B_0x1 + The FDCAN is in the Error_Passive state. + 0x1 + + + + + EW + Warning Sstatus + 6 + 1 + read-only + + + B_0x0 + Both error counters are below the Error_Warning limit of 96. + 0x0 + + + B_0x1 + At least one of error counter has reached the Error_Warning limit of 96. + 0x1 + + + + + BO + Bus_Off status + 7 + 1 + read-only + + + B_0x0 + The FDCAN is not Bus_Off. + 0x0 + + + B_0x1 + The FDCAN is in Bus_Off state. + 0x1 + + + + + DLEC + Data last error code + + 8 + 3 + read-write + + + RESI + ESI flag of last received FDCAN message + + 11 + 1 + read-write + + + B_0x0 + Last received FDCAN message did not have its ESI flag set. + 0x0 + + + B_0x1 + Last received FDCAN message had its ESI flag set. + 0x1 + + + + + RBRS + BRS flag of last received FDCAN message + + 12 + 1 + read-write + + + B_0x0 + Last received FDCAN message did not have its BRS flag set. + 0x0 + + + B_0x1 + Last received FDCAN message had its BRS flag set. + 0x1 + + + + + REDL + Received FDCAN message + + 13 + 1 + read-write + + + B_0x0 + Since this bit was reset by the CPU, no FDCAN message has been received. + 0x0 + + + B_0x1 + Message in FDCAN format with EDL flag set has been received. + 0x1 + + + + + PXE + Protocol exception event + 14 + 1 + read-write + + + B_0x0 + No protocol exception event occurred since last read access + 0x0 + + + B_0x1 + Protocol exception event occurred + 0x1 + + + + + TDCV + Transmitter delay compensation value + + 16 + 7 + read-only + + + + + FDCAN_TDCR + FDCAN_TDCR + FDCAN transmitter delay compensation register + 0x0048 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TDCF + Transmitter delay compensation filter window length + + 0 + 7 + read-write + + + TDCO + Transmitter delay compensation offset + + 8 + 7 + read-write + + + + + FDCAN_IR + FDCAN_IR + FDCAN interrupt register + 0x0050 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RF0N + Rx FIFO 0 new message + 0 + 1 + read-write + + + B_0x0 + No new message written to Rx FIFO 0 + 0x0 + + + B_0x1 + New message written to Rx FIFO 0 + 0x1 + + + + + RF0F + Rx FIFO 0 full + 1 + 1 + read-write + + + B_0x0 + Rx FIFO 0 not full + 0x0 + + + B_0x1 + Rx FIFO 0 full + 0x1 + + + + + RF0L + Rx FIFO 0 message lost + 2 + 1 + read-write + + + B_0x0 + No Rx FIFO 0 message lost + 0x0 + + + B_0x1 + Rx FIFO 0 message lost + 0x1 + + + + + RF1N + Rx FIFO 1 new message + 3 + 1 + read-write + + + B_0x0 + No new message written to Rx FIFO 1 + 0x0 + + + B_0x1 + New message written to Rx FIFO 1 + 0x1 + + + + + RF1F + Rx FIFO 1 full + 4 + 1 + read-write + + + B_0x0 + Rx FIFO 1 not full + 0x0 + + + B_0x1 + Rx FIFO 1 full + 0x1 + + + + + RF1L + Rx FIFO 1 message lost + 5 + 1 + read-write + + + B_0x0 + No Rx FIFO 1 message lost + 0x0 + + + B_0x1 + Rx FIFO 1 message lost + 0x1 + + + + + HPM + High-priority message + 6 + 1 + read-write + + + B_0x0 + No high-priority message received + 0x0 + + + B_0x1 + High-priority message received + 0x1 + + + + + TC + Transmission completed + 7 + 1 + read-write + + + B_0x0 + No transmission completed + 0x0 + + + B_0x1 + Transmission completed + 0x1 + + + + + TCF + Transmission cancellation finished + 8 + 1 + read-write + + + B_0x0 + No transmission cancellation finished + 0x0 + + + B_0x1 + Transmission cancellation finished + 0x1 + + + + + TFE + Tx FIFO empty + 9 + 1 + read-write + + + B_0x0 + Tx FIFO non-empty + 0x0 + + + B_0x1 + Tx FIFO empty + 0x1 + + + + + TEFN + Tx event FIFO New Entry + 10 + 1 + read-write + + + B_0x0 + Tx event FIFO unchanged + 0x0 + + + B_0x1 + Tx handler wrote Tx event FIFO element. + 0x1 + + + + + TEFF + Tx event FIFO full + 11 + 1 + read-write + + + B_0x0 + Tx event FIFO Not full + 0x0 + + + B_0x1 + Tx event FIFO full + 0x1 + + + + + TEFL + Tx event FIFO element lost + 12 + 1 + read-write + + + B_0x0 + No Tx event FIFO element lost + 0x0 + + + B_0x1 + Tx event FIFO element lost + 0x1 + + + + + TSW + Timestamp wraparound + 13 + 1 + read-write + + + B_0x0 + No timestamp counter wrap-around + 0x0 + + + B_0x1 + Timestamp counter wrapped around + 0x1 + + + + + MRAF + Message RAM access failure + + 14 + 1 + read-write + + + B_0x0 + No Message RAM access failure occurred + 0x0 + + + B_0x1 + Message RAM access failure occurred + 0x1 + + + + + TOO + Timeout occurred + 15 + 1 + read-write + + + B_0x0 + No timeout + 0x0 + + + B_0x1 + Timeout reached + 0x1 + + + + + ELO + Error logging overflow + 16 + 1 + read-write + + + B_0x0 + CAN error logging counter did not overflow. + 0x0 + + + B_0x1 + Overflow of CAN error logging counter occurred. + 0x1 + + + + + EP + Error passive + 17 + 1 + read-write + + + B_0x0 + Error_Passive status unchanged + 0x0 + + + B_0x1 + Error_Passive status changed + 0x1 + + + + + EW + Warning status + 18 + 1 + read-write + + + B_0x0 + Error_Warning status unchanged + 0x0 + + + B_0x1 + Error_Warning status changed + 0x1 + + + + + BO + Bus_Off status + 19 + 1 + read-write + + + B_0x0 + Bus_Off status unchanged + 0x0 + + + B_0x1 + Bus_Off status changed + 0x1 + + + + + WDI + Watchdog interrupt + 20 + 1 + read-write + + + B_0x0 + No message RAM watchdog event occurred + 0x0 + + + B_0x1 + Message RAM watchdog event due to missing READY + 0x1 + + + + + PEA + Protocol error in arbitration phase (nominal bit time is used) + 21 + 1 + read-write + + + B_0x0 + No protocol error in arbitration phase + 0x0 + + + B_0x1 + Protocol error in arbitration phase detected (PSR. + 0x1 + + + + + PED + Protocol error in data phase (data bit time is used) + 22 + 1 + read-write + + + B_0x0 + No protocol error in data phase + 0x0 + + + B_0x1 + Protocol error in data phase detected (PSR. + 0x1 + + + + + ARA + Access to reserved address + 23 + 1 + read-write + + + B_0x0 + No access to reserved address occurred + 0x0 + + + B_0x1 + Access to reserved address occurred + 0x1 + + + + + + + FDCAN_IE + FDCAN_IE + FDCAN interrupt enable register + 0x0054 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RF0NE + Rx FIFO 0 new message interrupt enable + 0 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + RF0FE + Rx FIFO 0 full interrupt enable + 1 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + RF0LE + Rx FIFO 0 message lost interrupt enable + 2 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + RF1NE + Rx FIFO 1 new message interrupt enable + 3 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + RF1FE + Rx FIFO 1 full interrupt enable + 4 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + RF1LE + Rx FIFO 1 message lost interrupt enable + 5 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + HPME + High-priority message interrupt enable + 6 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + TCE + Transmission completed interrupt enable + 7 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + TCFE + Transmission cancellation finished interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + TFEE + Tx FIFO empty interrupt enable + 9 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + TEFNE + Tx event FIFO new entry interrupt enable + 10 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + TEFFE + Tx event FIFO full interrupt enable + 11 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + TEFLE + Tx event FIFO element lost interrupt enable + 12 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + TSWE + Timestamp wraparound interrupt enable + 13 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + MRAFE + Message RAM access failure interrupt enable + 14 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + TOOE + Timeout occurred interrupt enable + 15 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + ELOE + Error logging overflow interrupt enable + 16 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EPE + Error passive interrupt enable + 17 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EWE + Warning status interrupt enable + 18 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + BOE + Bus_Off status + 19 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + WDIE + Watchdog interrupt enable + 20 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + PEAE + Protocol error in arbitration phase enable + 21 + 1 + read-write + + + PEDE + Protocol error in data phase enable + 22 + 1 + read-write + + + ARAE + Access to reserved address enable + 23 + 1 + read-write + + + + + FDCAN_ILS + FDCAN_ILS + FDCAN interrupt line select register + 0x0058 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RXFIFO0 + RX FIFO bit grouping the following interruption + + 0 + 1 + read-write + + + RXFIFO1 + RX FIFO bit grouping the following interruption + + 1 + 1 + read-write + + + SMSG + Status message bit grouping the following interruption + + 2 + 1 + read-write + + + TFERR + Tx FIFO ERROR grouping the following interruption + + 3 + 1 + read-write + + + MISC + Interrupt regrouping the following interruption + + 4 + 1 + read-write + + + BERR + Bit and line error grouping the following interruption + + 5 + 1 + read-write + + + PERR + Protocol error grouping the following interruption + + 6 + 1 + read-write + + + + + FDCAN_ILE + FDCAN_ILE + FDCAN interrupt line enable register + 0x005C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EINT0 + Enable interrupt line 0 + 0 + 1 + read-write + + + B_0x0 + Interrupt line fdcan_intr1_it disabled + 0x0 + + + B_0x1 + Interrupt line fdcan_intr1_it enabled + 0x1 + + + + + EINT1 + Enable interrupt line 1 + 1 + 1 + read-write + + + B_0x0 + Interrupt line fdcan_intr0_it disabled + 0x0 + + + B_0x1 + Interrupt line fdcan_intr0_it enabled + 0x1 + + + + + + + FDCAN_RXGFC + FDCAN_RXGFC + FDCAN global filter configuration register + 0x0080 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RRFE + Reject remote frames extended + + 0 + 1 + read-write + + + B_0x0 + Filter remote frames with 29-bit standard IDs + 0x0 + + + B_0x1 + Reject all remote frames with 29-bit standard IDs + 0x1 + + + + + RRFS + Reject remote frames standard + + 1 + 1 + read-write + + + B_0x0 + Filter remote frames with 11-bit standard IDs + 0x0 + + + B_0x1 + Reject all remote frames with 11-bit standard IDs + 0x1 + + + + + ANFE + Accept non-matching frames extended + + 2 + 2 + read-write + + + B_0x0 + Accept in Rx FIFO 0 + 0x0 + + + B_0x1 + Accept in Rx FIFO 1 + 0x1 + + + B_0x2 + Reject + 0x2 + + + B_0x3 + Reject + 0x3 + + + + + ANFS + Accept Non-matching frames standard + + 4 + 2 + read-write + + + B_0x0 + Accept in Rx FIFO 0 + 0x0 + + + B_0x1 + Accept in Rx FIFO 1 + 0x1 + + + B_0x2 + Reject + 0x2 + + + B_0x3 + Reject + 0x3 + + + + + F1OM + FIFO 1 operation mode (overwrite or blocking) + + 8 + 1 + read-write + + + F0OM + FIFO 0 operation mode (overwrite or blocking) + + 9 + 1 + read-write + + + LSS + List size standard + + 16 + 5 + read-write + + + B_0x0 + No standard message ID filter + 0x0 + + + + + LSE + List size extended + + 24 + 4 + read-write + + + B_0x0 + No extended message ID filter + 0x0 + + + + + + + FDCAN_XIDAM + FDCAN_XIDAM + FDCAN extended ID and mask register + 0x0084 + 0x20 + read-write + 0x1FFFFFFF + 0xFFFFFFFF + + + EIDM + Extended ID mask + + 0 + 29 + read-write + + + + + FDCAN_HPMS + FDCAN_HPMS + FDCAN high-priority message status register + 0x0088 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + BIDX + Buffer index + + 0 + 3 + read-only + + + MSI + Message storage indicator + 6 + 2 + read-only + + + B_0x0 + No FIFO selected + 0x0 + + + B_0x1 + FIFO overrun + 0x1 + + + B_0x2 + Message stored in FIFO 0 + 0x2 + + + B_0x3 + Message stored in FIFO 1 + 0x3 + + + + + FIDX + Filter index + + 8 + 5 + read-only + + + FLST + Filter list + + 15 + 1 + read-only + + + B_0x0 + Standard filter list + 0x0 + + + B_0x1 + Extended filter list + 0x1 + + + + + + + FDCAN_RXF0S + FDCAN_RXF0S + FDCAN Rx FIFO 0 status register + 0x0090 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + F0FL + Rx FIFO 0 fill level + + 0 + 4 + read-only + + + F0GI + Rx FIFO 0 get index + + 8 + 2 + read-only + + + F0PI + Rx FIFO 0 put index + + 16 + 2 + read-only + + + F0F + Rx FIFO 0 full + 24 + 1 + read-only + + + B_0x0 + Rx FIFO 0 not full + 0x0 + + + B_0x1 + Rx FIFO 0 full + 0x1 + + + + + RF0L + Rx FIFO 0 message lost + + 25 + 1 + read-only + + + B_0x0 + No Rx FIFO 0 message lost + 0x0 + + + B_0x1 + Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size 0 + 0x1 + + + + + + + FDCAN_RXF0A + FDCAN_RXF0A + CAN Rx FIFO 0 acknowledge register + 0x0094 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + F0AI + Rx FIFO 0 acknowledge index + + 0 + 3 + read-write + + + + + FDCAN_RXF1S + FDCAN_RXF1S + FDCAN Rx FIFO 1 status register + 0x0098 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + F1FL + Rx FIFO 1 fill level + + 0 + 4 + read-only + + + F1GI + Rx FIFO 1 get index + + 8 + 2 + read-only + + + F1PI + Rx FIFO 1 put index + + 16 + 2 + read-only + + + F1F + Rx FIFO 1 full + 24 + 1 + read-only + + + B_0x0 + Rx FIFO 1 not full + 0x0 + + + B_0x1 + Rx FIFO 1 full + 0x1 + + + + + RF1L + Rx FIFO 1 message lost + + 25 + 1 + read-only + + + B_0x0 + No Rx FIFO 1 message lost + 0x0 + + + B_0x1 + Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size 0 + 0x1 + + + + + + + FDCAN_RXF1A + FDCAN_RXF1A + FDCAN Rx FIFO 1 acknowledge register + 0x009C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + F1AI + Rx FIFO 1 acknowledge index + + 0 + 3 + read-write + + + + + FDCAN_TXBC + FDCAN_TXBC + FDCAN Tx buffer configuration register + 0x00C0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TFQM + Tx FIFO/queue mode + + 24 + 1 + read-write + + + B_0x0 + Tx FIFO operation + 0x0 + + + B_0x1 + Tx queue operation. + 0x1 + + + + + + + FDCAN_TXFQS + FDCAN_TXFQS + FDCAN Tx FIFO/queue status register + 0x00C4 + 0x20 + read-only + 0x00000003 + 0xFFFFFFFF + + + TFFL + Tx FIFO free level + + 0 + 3 + read-only + + + TFGI + Tx FIFO get index + + 8 + 2 + read-only + + + TFQPI + Tx FIFO/queue put index + + 16 + 2 + read-only + + + TFQF + Tx FIFO/queue full + 21 + 1 + read-only + + + B_0x0 + Tx FIFO/queue not full + 0x0 + + + B_0x1 + Tx FIFO/queue full + 0x1 + + + + + + + FDCAN_TXBRP + FDCAN_TXBRP + FDCAN Tx buffer request pending register + 0x00C8 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + TRP + Transmission request pending + + 0 + 3 + read-only + + + B_0x0 + No transmission request pending + 0x0 + + + B_0x1 + Transmission request pending + 0x1 + + + + + + + FDCAN_TXBAR + FDCAN_TXBAR + FDCAN Tx buffer add request register + 0x00CC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AR + Add request + + 0 + 3 + read-write + + + B_0x0 + No transmission request added + 0x0 + + + B_0x1 + Transmission requested added. + 0x1 + + + + + + + FDCAN_TXBCR + FDCAN_TXBCR + FDCAN Tx buffer cancellation request register + 0x00D0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CR + Cancellation request + + 0 + 3 + read-write + + + B_0x0 + No cancellation pending + 0x0 + + + B_0x1 + Cancellation pending + 0x1 + + + + + + + FDCAN_TXBTO + FDCAN_TXBTO + FDCAN Tx buffer transmission occurred register + 0x00D4 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + TO + Transmission occurred. + 0 + 3 + read-only + + + B_0x0 + No transmission occurred + 0x0 + + + B_0x1 + Transmission occurred + 0x1 + + + + + + + FDCAN_TXBCF + FDCAN_TXBCF + FDCAN Tx buffer cancellation finished register + 0x00D8 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + CF + Cancellation finished + + 0 + 3 + read-only + + + B_0x0 + No transmit buffer cancellation + 0x0 + + + B_0x1 + Transmit buffer cancellation finished + 0x1 + + + + + + + FDCAN_TXBTIE + FDCAN_TXBTIE + FDCAN Tx buffer transmission interrupt enable register + 0x00DC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TIE + Transmission interrupt enable + + 0 + 3 + read-write + + + B_0x0 + Transmission interrupt disabled + 0x0 + + + B_0x1 + Transmission interrupt enable + 0x1 + + + + + + + FDCAN_TXBCIE + FDCAN_TXBCIE + FDCAN Tx buffer cancellation finished interrupt enable register + 0x00E0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CFIE + Cancellation finished interrupt enable. + 0 + 3 + read-write + + + B_0x0 + Cancellation finished interrupt disabled + 0x0 + + + B_0x1 + Cancellation finished interrupt enabled + 0x1 + + + + + + + FDCAN_TXEFS + FDCAN_TXEFS + FDCAN Tx event FIFO status register + 0x00E4 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + EFFL + Event FIFO fill level + + 0 + 3 + read-only + + + EFGI + Event FIFO get index + + 8 + 2 + read-only + + + EFPI + Event FIFO put index + + 16 + 2 + read-only + + + EFF + Event FIFO full + 24 + 1 + read-only + + + B_0x0 + Tx event FIFO not full + 0x0 + + + B_0x1 + Tx event FIFO full + 0x1 + + + + + TEFL + Tx event FIFO element lost + + 25 + 1 + read-only + + + + + FDCAN_TXEFA + FDCAN_TXEFA + FDCAN Tx event FIFO acknowledge register + 0x00E8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EFAI + Event FIFO acknowledge index + + 0 + 2 + read-write + + + + + FDCAN_CKDIV + FDCAN_CKDIV + FDCAN CFG clock divider register + 0x0100 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PDIV + input clock divider + + 0 + 4 + read-write + + + B_0x0 + Divide by 1 + 0x0 + + + B_0x1 + Divide by 2 + 0x1 + + + B_0x2 + Divide by 4 + 0x2 + + + B_0x3 + Divide by 6 + 0x3 + + + B_0x4 + Divide by 8 + 0x4 + + + B_0x5 + Divide by 10 + 0x5 + + + B_0x6 + Divide by 12 + 0x6 + + + B_0x7 + Divide by 14 + 0x7 + + + B_0x8 + Divide by 16 + 0x8 + + + B_0x9 + Divide by 18 + 0x9 + + + B_0xA + Divide by 20 + 0xA + + + B_0xB + Divide by 22 + 0xB + + + B_0xC + Divide by 24 + 0xC + + + B_0xD + Divide by 26 + 0xD + + + B_0xE + Divide by 28 + 0xE + + + B_0xF + Divide by 30 + 0xF + + + + + + + + + FDCAN_S + 0X5000A400 + + + FDCAN2 + 0x4000A800 + + FDCAN2_IT1 + FDCAN2 Interrupt 1 + 110 + + + FDCAN2_IT0 + FDCAN2 Interrupt 0 + 109 + + + + FDCAN2_S + 0x5000A800 + + + FLASH + Mustang_FLASH register block + FLASH + 0x40022000 + + 0x0 + 0x400 + registers + + + FLASH + Flash non-secure global interrupt + 6 + + + + FLASH_ACR + FLASH_ACR + FLASH access control register + 0x000 + 0x20 + read-write + 0x00000013 + 0xFFFFFFFF + + + LATENCY + Read latency + + 0 + 4 + read-write + + + B_0x0 + no wait states used to read a word from nonvolatile memory + 0x0 + + + B_0x1 + one wait state used to read a word from nonvolatile memory + 0x1 + + + B_0x2 + two wait states used to read a word from nonvolatile memory + 0x2 + + + B_0x7 + seven wait states used to read a word from nonvolatile memory + 0x7 + + + B_0xF + 15 wait states used to read a word from nonvolatile memory + 0xF + + + + + WRHIGHFREQ + Flash signal delay + + 4 + 2 + read-write + + + PRFTEN + Prefetch enable. + 8 + 1 + read-write + + + B_0x0 + prefetch disabled. + 0x0 + + + B_0x1 + prefetch enabled when latency is at least one wait state. + 0x1 + + + + + + + FLASH_NSKEYR + FLASH_NSKEYR + FLASH non-secure key register + 0x004 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + NSKEY + Non-volatile memory non-secure configuration access unlock key + 0 + 32 + write-only + + + + + FLASH_SECKEYR + FLASH_SECKEYR + FLASH secure key register + 0x008 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + SECKEY + Non-volatile memory secure configuration access unlock key + 0 + 32 + write-only + + + + + FLASH_OPTKEYR + FLASH_OPTKEYR + FLASH option key register + 0x00C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + OPTKEY + FLASH option bytes control access unlock key + 0 + 32 + write-only + + + + + FLASH_NSOBKKEYR + FLASH_NSOBKKEYR + FLASH non-secure OBK key register + 0x0010 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + NSOBKKEY + FLASH non-secure option bytes keys control access unlock key + 0 + 32 + write-only + + + + + FLASH_SECOBKKEYR + FLASH_SECOBKKEYR + FLASH secure OBK key register + 0x0014 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + SECOBKKEY + FLASH secure option bytes keys control access unlock key + 0 + 32 + write-only + + + + + FLASH_OPSR + FLASH_OPSR + FLASH operation status register + 0x0018 + 0x20 + read-only + 0x00000000 + 0x00000000 + + + ADDR_OP + Interrupted operation address + 0 + 20 + read-only + + + DATA_OP + Flash high-cycle data area operation interrupted + + 21 + 1 + read-only + + + BK_OP + Interrupted operation bank + + 22 + 1 + read-only + + + SYSF_OP + Operation in system flash memory interrupted + + 23 + 1 + read-only + + + OTP_OP + OTP operation interrupted + + 24 + 1 + read-only + + + CODE_OP + Flash memory operation code + 29 + 3 + read-only + + + B_0x0 + No flash operation on going during previous reset + 0x0 + + + B_0x1 + Single write operation interrupted + 0x1 + + + B_0x2 + OBK alternate sector erase + 0x2 + + + B_0x3 + Sector erase operation interrupted + 0x3 + + + B_0x4 + Bank erase operation interrupted + 0x4 + + + B_0x5 + Mass erase operation interrupted + 0x5 + + + B_0x6 + Option change operation interrupted + 0x6 + + + B_0x7 + OBK swap sector request + 0x7 + + + + + + + FLASH_OPTCR + FLASH_OPTCR + FLASH option control register + 0x01C + 0x20 + read-write + 0x00000001 + 0x0FFFFFFF + + + OPTLOCK + FLASH_OPTCR lock option configuration bit + + 0 + 1 + read-write + + + B_0x0 + FLASH_OPTCR register unlocked + 0x0 + + + B_0x1 + FLASH_OPTCR register locked. + 0x1 + + + + + OPTSTRT + Option byte start change option configuration bit + + 1 + 1 + read-write + + + SWAP_BANK + Bank swapping option configuration bit + + 31 + 1 + read-only + + + B_0x0 + Bank1 and Bank2 not swapped + 0x0 + + + B_0x1 + Bank1 and Bank2 swapped + 0x1 + + + + + + + FLASH_NSSR + FLASH_NSSR + FLASH non-secure status register + 0x020 + 0x20 + read-only + 0x00000000 + 0xFFFFFFF0 + + + BSY + busy flag + + 0 + 1 + read-only + + + B_0x0 + no programming, erase or option byte change operation being executed + 0x0 + + + B_0x1 + programming, erase or option byte change operation being executed + 0x1 + + + + + WBNE + write buffer not empty flag + + 1 + 1 + read-only + + + B_0x0 + write buffer empty or full + 0x0 + + + B_0x1 + write buffer waiting data to complete + 0x1 + + + + + DBNE + data buffer not empty flag + + 3 + 1 + read-only + + + B_0x0 + data buffer not used + 0x0 + + + B_0x1 + data buffer used, wait + 0x1 + + + + + EOP + end of operation flag + + 16 + 1 + read-only + + + B_0x0 + no operation completed + 0x0 + + + B_0x1 + a operation completed + 0x1 + + + + + WRPERR + write protection error flag + + 17 + 1 + read-only + + + B_0x0 + no write protection error occurred + 0x0 + + + B_0x1 + a write protection error occurred + 0x1 + + + + + PGSERR + programming sequence error flag + + 18 + 1 + read-only + + + B_0x0 + no sequence error occurred + 0x0 + + + B_0x1 + a sequence error occurred + 0x1 + + + + + STRBERR + strobe error flag + + 19 + 1 + read-only + + + B_0x0 + no strobe error occurred + 0x0 + + + B_0x1 + a strobe error occurred + 0x1 + + + + + INCERR + inconsistency error flag + + 20 + 1 + read-only + + + B_0x0 + no inconsistency error occurs + 0x0 + + + B_0x1 + a inconsistency error occurs + 0x1 + + + + + OBKERR + OBK general error flag + + 21 + 1 + read-only + + + B_0x0 + no OBK general error occurred + 0x0 + + + B_0x1 + an OBK general error occurred + 0x1 + + + + + OBKWERR + OBK write error flag + + 22 + 1 + read-only + + + B_0x0 + no OBK write error occurred + 0x0 + + + B_0x1 + an OBK write error occurred + 0x1 + + + + + OPTCHANGEERR + Option byte change error flag + + 23 + 1 + read-only + + + B_0x0 + no option byte change errors occurred + 0x0 + + + B_0x1 + one or more errors occurred during an option byte change operation. + 0x1 + + + + + + + FLASH_SECSR + FLASH_SECSR + FLASH secure status register + 0x024 + 0x20 + read-only + 0x00000000 + 0xFFFFFFF0 + + + BSY + busy flag + + 0 + 1 + read-only + + + B_0x0 + no programming, erase or option byte change operation being executed + 0x0 + + + B_0x1 + programming, erase or option byte change operation being executed + 0x1 + + + + + WBNE + write buffer not empty flag + + 1 + 1 + read-only + + + B_0x0 + write buffer empty or full + 0x0 + + + B_0x1 + write buffer waiting data to complete + 0x1 + + + + + DBNE + data buffer not empty flag + + 3 + 1 + read-only + + + B_0x0 + data buffer not used + 0x0 + + + B_0x1 + data buffer used, wait + 0x1 + + + + + EOP + end of operation flag + + 16 + 1 + read-only + + + B_0x0 + no operation completed + 0x0 + + + B_0x1 + a operation completed + 0x1 + + + + + WRPERR + write protection error flag + + 17 + 1 + read-only + + + B_0x0 + no write protection error occurred + 0x0 + + + B_0x1 + a write protection error occurred + 0x1 + + + + + PGSERR + programming sequence error flag + + 18 + 1 + read-only + + + B_0x0 + no sequence error occurred + 0x0 + + + B_0x1 + a sequence error occurred + 0x1 + + + + + STRBERR + strobe error flag + + 19 + 1 + read-only + + + B_0x0 + no strobe error occurred + 0x0 + + + B_0x1 + a strobe error occurred + 0x1 + + + + + INCERR + inconsistency error flag + + 20 + 1 + read-only + + + B_0x0 + no inconsistency error occurred + 0x0 + + + B_0x1 + a inconsistency error occurred + 0x1 + + + + + OBKERR + OBK general error flag + + 21 + 1 + read-only + + + B_0x0 + no OBK general error occurred + 0x0 + + + B_0x1 + an OBK general error occurred + 0x1 + + + + + OBKWERR + OBK write error flag + + 22 + 1 + read-only + + + B_0x0 + no OBK write error occurred + 0x0 + + + B_0x1 + an OBK write error occurred + 0x1 + + + + + + + FLASH_NSCR + FLASH_NSCR + FLASH non-secure control register + 0x028 + 0x20 + read-write + 0x00000001 + 0xFFFFFFFF + + + LOCK + configuration lock bit + + 0 + 1 + read-write + + + B_0x0 + FLASH_NSCR register unlocked + 0x0 + + + B_0x1 + FLASH_NSCR register locked + 0x1 + + + + + PG + programming control bit + + 1 + 1 + read-write + + + B_0x0 + programming disabled + 0x0 + + + B_0x1 + programming enabled + 0x1 + + + + + SER + sector erase request + + 2 + 1 + read-write + + + B_0x0 + sector erase not requested + 0x0 + + + B_0x1 + sector erase requested + 0x1 + + + + + BER + erase request + + 3 + 1 + read-write + + + B_0x0 + bank erase not requested + 0x0 + + + B_0x1 + bank erase requested + 0x1 + + + + + FW + write forcing control bit + + 4 + 1 + read-write + + + STRT + erase start control bit + + 5 + 1 + read-write + + + SNB + sector erase selection number + + 6 + 7 + read-write + + + B_0x00 + Sector 0 selected + 0x00 + + + B_0x01 + Sector 1 selected + 0x01 + + + B_0x7F + Sector 127 selected + 0x7F + + + + + MER + mass erase request + + 15 + 1 + read-write + + + B_0x0 + mass erase not requested + 0x0 + + + B_0x1 + mass erase requested + 0x1 + + + + + EOPIE + end of operation interrupt control bit + + 16 + 1 + read-write + + + B_0x0 + no interrupt generated at the end of operation. + 0x0 + + + B_0x1 + interrupt enabled when at the end of operation + 0x1 + + + + + WRPERRIE + write protection error interrupt enable bit + + 17 + 1 + read-write + + + B_0x0 + no interrupt generated when a protection error occurs + 0x0 + + + B_0x1 + interrupt generated when a protection error occurs + 0x1 + + + + + PGSERRIE + programming sequence error interrupt enable bit + + 18 + 1 + read-write + + + B_0x0 + no interrupt generated when a sequence error occurs + 0x0 + + + B_0x1 + interrupt generated when sequence error occurs + 0x1 + + + + + STRBERRIE + strobe error interrupt enable bit + + 19 + 1 + read-write + + + B_0x0 + no interrupt generated when a strobe error occurs + 0x0 + + + B_0x1 + interrupt generated when strobe error occurs. + 0x1 + + + + + INCERRIE + inconsistency error interrupt enable bit + + 20 + 1 + read-write + + + B_0x0 + no interrupt generated when a inconsistency error occurs + 0x0 + + + B_0x1 + interrupt generated when a inconsistency error occurs. + 0x1 + + + + + OBKERRIE + OBK general error interrupt enable bit + + 21 + 1 + read-write + + + B_0x0 + no interrupt is generated on OBK general access error + 0x0 + + + B_0x1 + an interrupt is generated on OBK general access error + 0x1 + + + + + OBKWERRIE + OBK write error interrupt enable bit + + 22 + 1 + read-write + + + B_0x0 + no interrupt is generated on OBK write error + 0x0 + + + B_0x1 + an interrupt is generated on OBK write error + 0x1 + + + + + OPTCHANGEERRIE + Option byte change error interrupt enable bit + + 23 + 1 + read-write + + + B_0x0 + no interrupt is generated when an error occurs during an option byte change + 0x0 + + + B_0x1 + an interrupt is generated when and error occurs during an option byte change. + 0x1 + + + + + BKSEL + Bank selector bit + + 31 + 1 + read-write + + + B_0x0 + Bank1 is selected for Bank erase / sector erase / interrupt enable + 0x0 + + + B_0x1 + Bank2 is selected for BER / SER + 0x1 + + + + + + + FLASH_SECCR + FLASH_SECCR + FLASH secure control register + 0x02C + 0x20 + read-write + 0x00000001 + 0xFFFFFFFF + + + LOCK + configuration lock bit + + 0 + 1 + read-write + + + B_0x0 + FLASH_SECCR register unlocked + 0x0 + + + B_0x1 + FLASH_SECCR register locked + 0x1 + + + + + PG + programming control bit + + 1 + 1 + read-write + + + B_0x0 + programming disabled + 0x0 + + + B_0x1 + programming enabled + 0x1 + + + + + SER + sector erase request + + 2 + 1 + read-write + + + B_0x0 + sector erase not requested + 0x0 + + + B_0x1 + sector erase requested + 0x1 + + + + + BER + erase request + + 3 + 1 + read-write + + + B_0x0 + bank erase not requested + 0x0 + + + B_0x1 + bank erase requested + 0x1 + + + + + FW + write forcing control bit + + 4 + 1 + read-write + + + STRT + erase start control bit + + 5 + 1 + read-write + + + SNB + sector erase selection number + + 6 + 7 + read-write + + + B_0x00 + Sector 0 selected + 0x00 + + + B_0x01 + Sector 1 selected + 0x01 + + + B_0x7F + Sector 127 selected + 0x7F + + + + + MER + mass erase request + + 15 + 1 + read-write + + + B_0x0 + mass erase not requested + 0x0 + + + B_0x1 + mass erase requested + 0x1 + + + + + EOPIE + end of operation interrupt control bit + + 16 + 1 + read-write + + + B_0x0 + no interrupt generated at the end of operation. + 0x0 + + + B_0x1 + interrupt enabled when at the end of operation + 0x1 + + + + + WRPERRIE + write protection error interrupt enable bit + + 17 + 1 + read-write + + + B_0x0 + no interrupt generated when a protection error occurs + 0x0 + + + B_0x1 + interrupt generated when a protection error occurs + 0x1 + + + + + PGSERRIE + programming sequence error interrupt enable bit + + 18 + 1 + read-write + + + B_0x0 + no interrupt generated when a sequence error occurs + 0x0 + + + B_0x1 + interrupt generated when sequence error occurs + 0x1 + + + + + STRBERRIE + strobe error interrupt enable bit + + 19 + 1 + read-write + + + B_0x0 + no interrupt generated when a strobe error occurs + 0x0 + + + B_0x1 + interrupt generated when strobe error occurs. + 0x1 + + + + + INCERRIE + inconsistency error interrupt enable bit + + 20 + 1 + read-write + + + B_0x0 + no interrupt generated when a inconsistency error occurs + 0x0 + + + B_0x1 + interrupt generated when a inconsistency error occurs. + 0x1 + + + + + OBKERRIE + OBK general error interrupt enable bit + + 21 + 1 + read-write + + + B_0x0 + no interrupt is generated on OBK general access error + 0x0 + + + B_0x1 + an interrupt is generated on OBK general access error + 0x1 + + + + + OBKWERRIE + OBK write error interrupt enable bit + + 22 + 1 + read-write + + + B_0x0 + no interrupt is generated on OBK write error + 0x0 + + + B_0x1 + an interrupt is generated on OBK write error + 0x1 + + + + + INV + Flash memory security state invert. + 29 + 1 + read-write + + + BKSEL + Bank selector bit + + 31 + 1 + read-write + + + B_0x0 + Bank1 is selected for Bank erase / sector erase / interrupt enable + 0x0 + + + B_0x1 + Bank2 is selected for BER / SER + 0x1 + + + + + + + FLASH_NSCCR + FLASH_NSCCR + FLASH non-secure clear control register + 0x030 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + CLR_EOP + EOP flag clear bit + + 16 + 1 + write-only + + + CLR_WRPERR + WRPERR flag clear bit + + 17 + 1 + write-only + + + CLR_PGSERR + PGSERR flag clear bit + + 18 + 1 + write-only + + + CLR_STRBERR + STRBERR flag clear bit + + 19 + 1 + write-only + + + CLR_INCERR + INCERR flag clear bit + + 20 + 1 + write-only + + + CLR_OBKERR + OBKERR flag clear bit. + 21 + 1 + write-only + + + CLR_OBKWERR + OBKWERR flag clear bit. + 22 + 1 + write-only + + + CLR_OPTCHANGEERR + Clear the flag corresponding flag in FLASH_NSSR by writing this bit. + 23 + 1 + write-only + + + + + FLASH_SECCCR + FLASH_SECCCR + FLASH secure clear control register + 0x034 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + CLR_EOP + EOP flag clear bit + + 16 + 1 + write-only + + + CLR_WRPERR + WRPERR flag clear bit + + 17 + 1 + write-only + + + CLR_PGSERR + PGSERR flag clear bit + + 18 + 1 + write-only + + + CLR_STRBERR + STRBERR flag clear bit + + 19 + 1 + write-only + + + CLR_INCERR + INCERR flag clear bit + + 20 + 1 + write-only + + + CLR_OBKERR + OBKWERR flag clear bit + + 21 + 1 + write-only + + + CLR_OBKWERR + OBKWERR flag clear bit + + 22 + 1 + write-only + + + + + FLASH_PRIVCFGR + FLASH_PRIVCFGR + FLASH privilege configuration register + 0x03C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SPRIV + privilege attribute for secure registers + 0 + 1 + read-write + + + B_0x0 + access to secure registers is always granted + 0x0 + + + B_0x1 + access to secure registers is denied in case of unprivileged access. + 0x1 + + + + + NSPRIV + privilege attribute for non secure registers + 1 + 1 + read-write + + + B_0x0 + access to non secure registers is always granted + 0x0 + + + B_0x1 + access to non secure registers is denied in case of unprivileged access. + 0x1 + + + + + + + FLASH_NSOBKCFGR + FLASH_NSOBKCFGR + FLASH non-secure OBK configuration register + 0x040 + 0x20 + read-write + 0x01FF0000 + 0xFFFFFFFF + + + LOCK + OBKCFGR lock option configuration bit + + 0 + 1 + read-write + + + B_0x0 + FLASH_NSOBKCFGR register unlocked + 0x0 + + + B_0x1 + FLASH_NSOBKCFGR register locked + 0x1 + + + + + SWAP_SECT_REQ + OBK swap sector request bit + + 1 + 1 + read-write + + + B_0x0 + no swap requested + 0x0 + + + B_0x1 + launch the sector swap + 0x1 + + + + + ALT_SECT + alternate sector bit + + 2 + 1 + read-write + + + B_0x0 + current OBK sector is mapped to OBK address range for access + 0x0 + + + B_0x1 + alternate OBK sector is mapped to OBK address range for access + 0x1 + + + + + ALT_SECT_ERASE + alternate sector erase bit + + 3 + 1 + read-write + + + B_0x0 + do not touch OBK sector + 0x0 + + + B_0x1 + erase the alternate OBK sector + 0x1 + + + + + SWAP_OFFSET + Key index (offset /16 bits) pointing for next swap. + 16 + 9 + read-write + + + B_0x00 + means that no OBK is copied from current to alternate OBK sector during SWAP operation. + 0x00 + + + B_0x1FF + means that all OBK data (511) are copied + 0x1FF + + + + + + + FLASH_SECOBKCFGR + FLASH_SECOBKCFGR + FLASH secure OBK configuration register + 0x044 + 0x20 + read-write + 0x01FF0000 + 0xFFFFFFFF + + + LOCK + OBKCFGR lock option configuration bit + + 0 + 1 + read-write + + + B_0x0 + FLASH_OBKCFGR register unlocked + 0x0 + + + B_0x1 + FLASH_OBKCFGR register locked + 0x1 + + + + + SWAP_SECT_REQ + OBK swap sector request bit + + 1 + 1 + read-write + + + B_0x0 + no swap requested + 0x0 + + + B_0x1 + launch the sector swap + 0x1 + + + + + ALT_SECT + alternate sector bit + + 2 + 1 + read-write + + + B_0x0 + current OBK sector is mapped to OBK address range for access + 0x0 + + + B_0x1 + alternate OBK sector is mapped to OBK address range for access + 0x1 + + + + + ALT_SECT_ERASE + alternate sector erase bit + + 3 + 1 + read-write + + + B_0x0 + do not touch OBK sector + 0x0 + + + B_0x1 + erase the alternate OBK sector + 0x1 + + + + + SWAP_OFFSET + key index (offset /16 bits) pointing for next swap. + 16 + 9 + read-write + + + B_0x0 + no OBK is copied from current to alternate OBK sector during SWAP operation. + 0x0 + + + B_0x1 + only the first OBK data (128 bits) are copied from current to alternate OBK sector + 0x1 + + + B_0x2 + the two first OBK data are copied + 0x2 + + + B_0x1FF + the 511 first OBK data are copied + 0x1FF + + + + + + + FLASH_HDPEXTR + FLASH_HDPEXTR + FLASH HDP extension register + 0x048 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + HDP1_EXT + HDP area extension in 8 Kbytes sectors in Bank1. + 0 + 7 + read-write + + + HDP2_EXT + HDP area extension in 8 Kbytes sectors in Bank2. + 16 + 7 + read-write + + + + + FLASH_OPTSR_CUR + FLASH_OPTSR_CUR + FLASH option status register + 0x050 + 0x20 + read-only + 0x00000000 + 0x00000000 + + + BOR_LEV + Brownout level option status bit + + 0 + 2 + read-only + + + B_0x1 + BOR Level 2, the threshold level is medium (around 2. + 0x1 + + + B_0x2 + BOR Level 3, the threshold level is high (around 2. + 0x2 + + + + + BORH_EN + Brownout high enable + 2 + 1 + read-only + + + B_0x0 + disable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + IWDG_SW + IWDG control mode option status bit + 3 + 1 + read-only + + + B_0x0 + IWDG watchdog is controlled by hardware + 0x0 + + + B_0x1 + IWDG watchdog is controlled by software + 0x1 + + + + + WWDG_SW + WWDG control mode option status bit + 4 + 1 + read-only + + + B_0x0 + WWDG watchdog is controlled by hardware + 0x0 + + + B_0x1 + WWDG watchdog is controlled by software + 0x1 + + + + + NRST_STOP + Core domain Stop entry reset option status bit + 6 + 1 + read-only + + + B_0x0 + a reset is generated when entering Stop mode on core domain + 0x0 + + + B_0x1 + no reset generated when entering Stop mode on core domain. + 0x1 + + + + + NRST_STDBY + Core domain Standby entry reset option status bit + 7 + 1 + read-only + + + B_0x0 + a reset is generated when entering Standby mode on core domain + 0x0 + + + B_0x1 + no reset generated when entering Standby mode on core domain. + 0x1 + + + + + PRODUCT_STATE + Life state code (based on Hamming 8,4). + 8 + 8 + read-only + + + IO_VDD_HSLV + High-speed IO at low Vless thansub>DDless than/sub> voltage configuration bit. + 16 + 1 + read-only + + + B_0x0 + High-speed IO at low Vless thansub>DDless than/sub> voltage feature disabled (Vless thansub>DDless than/sub> can exceed 2. + 0x0 + + + B_0x1 + High-speed IO at low Vless thansub>DDless than/sub> voltage feature enabled (Vless thansub>DDless than/sub> remains below 2. + 0x1 + + + + + IO_VDDIO2_HSLV + High-speed IO at low Vless thansub>DDIO2less than/sub> voltage configuration bit. + 17 + 1 + read-only + + + B_0x0 + High-speed IO at low Vless thansub>DDIO2less than/sub> voltage feature disabled (Vless thansub>DDIO2less than/sub> can exceed 2. + 0x0 + + + B_0x1 + High-speed IO at low Vless thansub>DDIO2less than/sub> voltage feature enabled (Vless thansub>DDIO2less than/sub> remains below 2. + 0x1 + + + + + IWDG_STOP + IWDG Stop mode freeze option status bit + + 20 + 1 + read-only + + + B_0x0 + Independent watchdog frozen in system Stop mode + 0x0 + + + B_0x1 + Independent watchdog keep running in system Stop mode. + 0x1 + + + + + IWDG_STDBY + IWDG Standby mode freeze option status bit + + 21 + 1 + read-only + + + B_0x0 + Independent watchdog frozen in Standby mode + 0x0 + + + B_0x1 + Independent watchdog keep running in Standby mode. + 0x1 + + + + + BOOT_UBE + Available only on cryptography enabled devices. + 22 + 8 + read-only + + + B_0xC3 + ST-iRoT (system flash) selected + 0xC3 + + + B_0xB4 + OEM-iRoT (user flash) selected. + 0xB4 + + + + + SWAP_BANK + Bank swapping option status bit + + 31 + 1 + read-only + + + B_0x0 + Bank1 and Bank2 not swapped + 0x0 + + + B_0x1 + Bank1 and Bank2 swapped + 0x1 + + + + + + + FLASH_OPTSR_PRG + FLASH_OPTSR_PRG + FLASH option status register + 0x054 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + BOR_LEV + Brownout level option configuration bit + + 0 + 2 + read-write + + + B_0x1 + BOR Level 2, the threshold level is medium (around 2. + 0x1 + + + B_0x2 + BOR Level 3, the threshold level is high (around 2. + 0x2 + + + + + BORH_EN + Brownout high enable configuration bit + 2 + 1 + read-write + + + B_0x0 + disabled + 0x0 + + + B_0x1 + enabled + 0x1 + + + + + IWDG_SW + IWDG control mode option configuration bit + 3 + 1 + read-write + + + B_0x0 + IWDG watchdog is controlled by hardware + 0x0 + + + B_0x1 + IWDG watchdog is controlled by software + 0x1 + + + + + WWDG_SW + WWDG control mode option configuration bit + 4 + 1 + read-write + + + B_0x0 + WWDG watchdog is controlled by hardware + 0x0 + + + B_0x1 + WWDG watchdog is controlled by software + 0x1 + + + + + NRST_STOP + Core domain Stop entry reset option configuration bit + 6 + 1 + read-write + + + B_0x0 + a reset is generated when entering Stop mode on core domain + 0x0 + + + B_0x1 + no reset generated when entering Stop mode on core domain. + 0x1 + + + + + NRST_STDBY + Core domain Standby entry reset option configuration bit + 7 + 1 + read-write + + + B_0x0 + a reset is generated when entering Standby mode on core domain + 0x0 + + + B_0x1 + no reset generated when entering Standby mode on core domain. + 0x1 + + + + + PRODUCT_STATE + Life state code (based on Hamming 8,4). + 8 + 8 + read-write + + + IO_VDD_HSLV + High-speed IO at low VDD voltage configuration bit. + 16 + 1 + read-write + + + B_0x0 + High-speed IO at low Vless thansub>DDless than/sub> voltage feature disabled (Vless thansub>DDless than/sub> can exceed 2. + 0x0 + + + B_0x1 + High-speed IO at low Vless thansub>DDless than/sub> voltage feature enabled (Vless thansub>DDless than/sub> remains below 2. + 0x1 + + + + + IO_VDDIO2_HSLV + High-speed IO at low Vless thansub>DDIO2less than/sub> voltage configuration bit. + 17 + 1 + read-write + + + B_0x0 + High-speed IO at low Vless thansub>DDIO2less than/sub> voltage feature disabled (Vless thansub>DDIO2less than/sub> can exceed 2. + 0x0 + + + B_0x1 + High-speed IO at low Vless thansub>DDIO2less than/sub> voltage feature enabled (Vless thansub>DDIO2less than/sub> remains below 2. + 0x1 + + + + + IWDG_STOP + IWDG Stop mode freeze option status bit + + 20 + 1 + read-write + + + B_0x0 + Independent watchdog frozen in system Stop mode + 0x0 + + + B_0x1 + Independent watchdog keep running in system Stop mode. + 0x1 + + + + + IWDG_STDBY + IWDG Standby mode freeze option status bit + + 21 + 1 + read-write + + + B_0x0 + Independent watchdog frozen in Standby mode + 0x0 + + + B_0x1 + Independent watchdog keep running in Standby mode. + 0x1 + + + + + BOOT_UBE + Available only on cryptography enabled devices. + 22 + 8 + read-write + + + B_0xC3 + ST-iRoT (system flash) selected + 0xC3 + + + B_0xB4 + OEM-iRoT (user flash) selected. + 0xB4 + + + + + SWAP_BANK + Bank swapping option configuration bit + + 31 + 1 + read-write + + + B_0x0 + Bank1 and Bank2 not swapped + 0x0 + + + B_0x1 + Bank1 and Bank2 swapped + 0x1 + + + + + + + FLASH_NSEPOCHR_CUR + FLASH_NSEPOCHR_CUR + FLASH non-secure EPOCH register + 0x060 + 0x20 + read-only + 0x00000000 + 0x00000000 + + + NS_EPOCH + Non-volatile non-secure EPOCH counter + 0 + 24 + read-only + + + + + FLASH_SECEPOCHR_CUR + FLASH_SECEPOCHR_CUR + FLASH secure EPOCH register + 0x068 + 0x20 + read-only + 0x00000000 + 0x00000000 + + + SEC_EPOCH + Non-volatile secure EPOCH counter + 0 + 24 + read-only + + + + + FLASH_OPTSR2_CUR + FLASH_OPTSR2_CUR + FLASH option status register 2 + 0x070 + 0x20 + read-only + 0x00000000 + 0x00000000 + + + SRAM13_RST + SRAM1 and SRAM3 erase upon system reset + 2 + 1 + read-only + + + B_0x0 + SRAM1 and SRAM3 erased when a system reset occurs + 0x0 + + + B_0x1 + SRAM1 and SRAM3 not erased when a system reset occurs + 0x1 + + + + + SRAM2_RST + SRAM2 erase when system reset + 3 + 1 + read-only + + + B_0x0 + SRAM2 erased when a system reset occurs + 0x0 + + + B_0x1 + SRAM2 not erased when a system reset occurs. + 0x1 + + + + + BKPRAM_ECC + Backup RAM ECC detection and correction disable + 4 + 1 + read-only + + + B_0x0 + BKPRAM ECC check enabled + 0x0 + + + B_0x1 + BKPRAM ECC check disabled + 0x1 + + + + + SRAM3_ECC + SRAM3 ECC detection and correction disable + 5 + 1 + read-only + + + B_0x0 + SRAM3 ECC check enabled + 0x0 + + + B_0x1 + SRAM3 ECC check disabled + 0x1 + + + + + SRAM2_ECC + SRAM2 ECC detection and correction disable + 6 + 1 + read-only + + + B_0x0 + SRAM2 ECC check enabled + 0x0 + + + B_0x1 + SRAM2 ECC check disabled + 0x1 + + + + + USBPD_DIS + USB power delivery configuration option bit + 8 + 1 + read-only + + + B_0x0 + Enabled + 0x0 + + + B_0x1 + Disabled + 0x1 + + + + + TZEN + TrustZone enable configuration bits + + 24 + 8 + read-only + + + B_0xC3 + TrustZone disabled + 0xC3 + + + B_0xB4 + TrustZone enabled. + 0xB4 + + + + + + + FLASH_OPTSR2_PRG + FLASH_OPTSR2_PRG + FLASH option status register 2 + 0x074 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + SRAM1_3_RST + SRAM1 and SRAM3 erase upon system reset + + 2 + 1 + read-write + + + B_0x0 + SRAM1 and SRAM3 erased when a system reset occurs + 0x0 + + + B_0x1 + SRAM1 and SRAM3 not erased when a system reset occurs + 0x1 + + + + + SRAM2_RST + SRAM2 erase when system reset + + 3 + 1 + read-write + + + B_0x0 + SRAM2 erased when a system reset occurs + 0x0 + + + B_0x1 + SRAM2 not erased when a system reset occurs. + 0x1 + + + + + BKPRAM_ECC + Backup RAM ECC detection and correction disable + 4 + 1 + read-write + + + B_0x0 + BKPRAM ECC check enabled + 0x0 + + + B_0x1 + BKPRAM ECC check disabled + 0x1 + + + + + SRAM3_ECC + SRAM3 ECC detection and correction disable + 5 + 1 + read-write + + + B_0x0 + SRAM3 ECC check enabled + 0x0 + + + B_0x1 + SRAM3 ECC check disabled + 0x1 + + + + + SRAM2_ECC + SRAM2 ECC detection and correction disable + 6 + 1 + read-write + + + B_0x0 + SRAM2 ECC check enabled + 0x0 + + + B_0x1 + SRAM2 ECC check disabled + 0x1 + + + + + USBPD_DIS + USB power delivery configuration option bit + 8 + 1 + read-write + + + B_0x0 + Enabled + 0x0 + + + B_0x1 + Disabled + 0x1 + + + + + TZEN + TrustZone enable configuration bits + + 24 + 8 + read-write + + + B_0xC3 + TrustZone disabled + 0xC3 + + + B_0xB4 + TrustZone enabled + 0xB4 + + + + + + + FLASH_NSBOOTR_CUR + FLASH_NSBOOTR_CUR + FLASH non-secure boot register + 0x080 + 0x20 + read-only + 0x00000000 + 0x00000000 + + + NSBOOT_LOCK + Field locking the values of SWAP_BANK, and NSBOOTADD settings. + 0 + 8 + read-only + + + B_0xC3 + SWAP_BANK and NSBOOTADD can still be modified following their individual rules. + 0xC3 + + + B_0xB4 + NSBOOTADD is frozen. + 0xB4 + + + + + NSBOOTADD + Non secure unique boot entry address + + 8 + 24 + read-only + + + + + FLASH_NSBOOTR_PRG + FLASH_NSBOOTR_PRG + FLASH non-secure boot register + 0x084 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + NSBOOT_LOCK + Field locking the values of SWAP_ BANK, and NSBOOTADD settings. + 0 + 8 + read-write + + + B_0xC3 + SWAP_ BANK and NSBOOTADD can still be modified following their individual rules. + 0xC3 + + + B_0xB4 + NSBOOTADD is frozen. + 0xB4 + + + + + NSBOOTADD + Non secure unique boot entry address + + 8 + 24 + read-write + + + + + FLASH_SECBOOTR_CUR + FLASH_SECBOOTR_CUR + FLASH secure boot register + 0x088 + 0x20 + read-only + 0x00000000 + 0x00000000 + + + SECBOOT_LOCK + Field locking the values of UBE, SWAP_BANK, and SECBOOTADD settings. + 0 + 8 + read-only + + + B_0xC3 + BOOT_UBE, SWAP_BANK and SECBOOTADD can still be modified following their individual rules. + 0xC3 + + + B_0xB4 + BOOT_UBE and SECBOOTADD are frozen. + 0xB4 + + + + + SECBOOTADD + Unique boot entry secure address + + 8 + 24 + read-only + + + + + FLASH_BOOTR_PRG + FLASH_BOOTR_PRG + FLASH secure boot register + 0x08C + 0x20 + read-write + 0x00000000 + 0x00000000 + + + SECBOOT_LOCK + Field locking the values of UBE, SWAP_ BANK, and SECBOOTADD setting. + 0 + 8 + read-write + + + B_0xC3 + BOOT_UBE, SWAP_ BANK and SECBOOTADD can still be modified following their individual rules. + 0xC3 + + + B_0xB4 + BOOT_UBE and SECBOOTADD are frozen. + 0xB4 + + + + + SECBOOTADD + Secure unique boot entry address. + 8 + 24 + read-write + + + + + FLASH_OTPBLR_CUR + FLASH_OTPBLR_CUR + FLASH non-secure OTP block lock + 0x090 + 0x20 + read-only + 0x00000000 + 0x00000000 + + + LOCKBL + OTP block lock + + 0 + 32 + read-only + + + + + FLASH_OTPBLR_PRG + FLASH_OTPBLR_PRG + FLASH non-secure OTP block lock + 0x094 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + LOCKBL + OTP block lock + + 0 + 32 + read-write + + + + + FLASH_SECBB1R1 + FLASH_SECBB1R1 + FLASH secure block based register for Bank1 + 0xA0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SECBB1 + Secure/non-secure 8 Kbytes flash Bank1 sector attributes + 0 + 32 + read-write + + + B_0x0 + sector (32 * (x-1) + y) in Bank1 is non secure. + 0x0 + + + B_0x1 + sector (32 * (x-1) + y) in Bank1 is secure. + 0x1 + + + + + + + FLASH_SECBB1R2 + FLASH_SECBB1R2 + FLASH secure block based register for Bank1 + 0xA4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SECBB1 + Secure/non-secure 8 Kbytes flash Bank1 sector attributes + 0 + 32 + read-write + + + B_0x0 + sector (32 * (x-1) + y) in Bank1 is non secure. + 0x0 + + + B_0x1 + sector (32 * (x-1) + y) in Bank1 is secure. + 0x1 + + + + + + + FLASH_SECBB1R3 + FLASH_SECBB1R3 + FLASH secure block based register for Bank1 + 0xA8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SECBB1 + Secure/non-secure 8 Kbytes flash Bank1 sector attributes + 0 + 32 + read-write + + + B_0x0 + sector (32 * (x-1) + y) in Bank1 is non secure. + 0x0 + + + B_0x1 + sector (32 * (x-1) + y) in Bank1 is secure. + 0x1 + + + + + + + FLASH_SECBB1R4 + FLASH_SECBB1R4 + FLASH secure block based register for Bank1 + 0xAC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SECBB1 + Secure/non-secure 8 Kbytes flash Bank1 sector attributes + 0 + 32 + read-write + + + B_0x0 + sector (32 * (x-1) + y) in Bank1 is non secure. + 0x0 + + + B_0x1 + sector (32 * (x-1) + y) in Bank1 is secure. + 0x1 + + + + + + + FLASH_PRIVBB1R1 + FLASH_PRIVBB1R1 + FLASH privilege block based register for Bank1 + 0xC0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRIVBB1 + Privileged/unprivileged 8-Kbyte flash Bank1 sector attribute + 0 + 32 + read-write + + + B_0x0 + sectors (32 * (x-1) + y) in Bank1 is unprivileged. + 0x0 + + + B_0x1 + sector (32 * (x-1) + y) in Bank1 is privileged. + 0x1 + + + + + + + FLASH_PRIVBB1R2 + FLASH_PRIVBB1R2 + FLASH privilege block based register for Bank1 + 0xC4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRIVBB1 + Privileged/unprivileged 8-Kbyte flash Bank1 sector attribute + 0 + 32 + read-write + + + B_0x0 + sectors (32 * (x-1) + y) in Bank1 is unprivileged. + 0x0 + + + B_0x1 + sector (32 * (x-1) + y) in Bank1 is privileged. + 0x1 + + + + + + + FLASH_PRIVBB1R3 + FLASH_PRIVBB1R3 + FLASH privilege block based register for Bank1 + 0xC8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRIVBB1 + Privileged/unprivileged 8-Kbyte flash Bank1 sector attribute + 0 + 32 + read-write + + + B_0x0 + sectors (32 * (x-1) + y) in Bank1 is unprivileged. + 0x0 + + + B_0x1 + sector (32 * (x-1) + y) in Bank1 is privileged. + 0x1 + + + + + + + FLASH_PRIVBB1R4 + FLASH_PRIVBB1R4 + FLASH privilege block based register for Bank1 + 0xCC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRIVBB1 + Privileged/unprivileged 8-Kbyte flash Bank1 sector attribute + 0 + 32 + read-write + + + B_0x0 + sectors (32 * (x-1) + y) in Bank1 is unprivileged. + 0x0 + + + B_0x1 + sector (32 * (x-1) + y) in Bank1 is privileged. + 0x1 + + + + + + + FLASH_SECWM1R_CUR + FLASH_SECWM1R_CUR + FLASH security watermark for Bank1 + 0x0E0 + 0x20 + read-only + 0x00000000 + 0xFF00FF00 + + + SECWM1_STRT + Bank1 security WM area 1 start sector + + 0 + 7 + read-only + + + SECWM1_END + Bank1 security WM area 1 end sector + + 16 + 7 + read-only + + + + + FLASH_SECWM1R_PRG + FLASH_SECWM1R_PRG + FLASH security watermark for Bank1 + 0x0E4 + 0x20 + read-write + 0x00000000 + 0xFF00FF00 + + + SECWM1_STRT + Bank1 security WM area 1 start sector + + 0 + 7 + read-write + + + SECWM1_END + Bank1 security WM area 1 end sector + + 16 + 7 + read-write + + + + + FLASH_WRP1R_CUR + FLASH_WRP1R_CUR + FLASH write sector group protection for Bank1 + 0x0E8 + 0x20 + read-only + 0x00000000 + 0x00000000 + + + WRPSG1 + Bank1 sector group protection option status byte + + 0 + 32 + read-only + + + + + FLASH_WRP1R_PRG + FLASH_WRP1R_PRG + FLASH write sector group protection for Bank1 + 0x0EC + 0x20 + read-write + 0x00000000 + 0x00000000 + + + WRPSG1 + Bank1 sector group protection option status byte + + 0 + 32 + read-write + + + + + FLASH_EDATA1R_CUR + FLASH_EDATA1R_CUR + FLASH data sector configuration Bank1 + 0x0F0 + 0x20 + read-only + 0x00000000 + 0x00000000 + + + EDATA1_STRT + EDATA1_STRT contains the start sectors of the flash high-cycle data area in Bank1 There is no hardware effect to those bits. + 0 + 3 + read-only + + + B_0x0 + The last sector of Bank1 is reserved for flash high-cycle data + 0x0 + + + B_0x1 + The two last sectors of Bank1 are reserved for flash high-cycle data + 0x1 + + + B_0x2 + The three last sectors of Bank1 are reserved for flash high-cycle data + 0x2 + + + B_0x7 + The eight last sectors of Bank1 are reserved for flash high-cycle data + 0x7 + + + + + EDATA1_EN + Bank1 flash high-cycle data enable + 15 + 1 + read-only + + + B_0x0 + No flash high-cycle data area + 0x0 + + + B_0x1 + Flash high-cycle data is used + 0x1 + + + + + + + FLASH_EDATA1R_PRG + FLASH_EDATA1R_PRG + FLASH data sector configuration Bank1 + 0xF4 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + EDATA1_STRT + EDATA1_STRT contains the start sectors of the flash high-cycle data area in Bank1 There is no hardware effect to those bits. + 0 + 3 + read-write + + + B_0x0 + The last sector of Bank1 is reserved for flash high-cycle data + 0x0 + + + B_0x1 + The two last sectors of Bank1 are reserved for flash high-cycle data + 0x1 + + + B_0x2 + The three last sectors of Bank1 are reserved for flash high-cycle data + 0x2 + + + + + EDATA1_EN + Bank1 flash high-cycle data enable + 15 + 1 + read-write + + + B_0x0 + No flash high-cycle data area + 0x0 + + + B_0x1 + Flash high-cycle data is used + 0x1 + + + + + + + FLASH_HDP1R_CUR + FLASH_HDP1R_CUR + FLASH HDP Bank1 configuration + 0x0F8 + 0x20 + read-only + 0x00000000 + 0x00000000 + + + HDP1_STRT + HDPL barrier start set in number of 8-Kbyte sectors + + 0 + 7 + read-only + + + HDP1_END + HDPL barrier end set in number of 8-Kbyte sectors + + 16 + 7 + read-only + + + + + FLASH_HDP1R_PRG + FLASH_HDP1R_PRG + FLASH HDP Bank1 configuration + 0x0FC + 0x20 + read-write + 0x00000000 + 0x00000000 + + + HDP1_STRT + HDPL barrier start set in number of 8-Kbyte sectors + + 0 + 7 + read-write + + + HDP1_END + HDPL barrier end set in number of 8-Kbyte sectors + + 16 + 7 + read-write + + + + + FLASH_ECCCORR + FLASH_ECCCORR + FLASH ECC correction register + 0x100 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ADDR_ECC + ECC error address + + 0 + 16 + read-only + + + OBK_ECC + Single ECC error corrected in flash OB Keys storage area. + 20 + 1 + read-only + + + EDATA_ECC + ECC fail for corrected ECC error in flash high-cycle data area + + 21 + 1 + read-only + + + BK_ECC + ECC fail bank for corrected ECC error + + 22 + 1 + read-only + + + SYSF_ECC + ECC fail for corrected ECC error in system flash memory + + 23 + 1 + read-only + + + OTP_ECC + OTP ECC error bit + + 24 + 1 + read-only + + + ECCCIE + ECC single correction error interrupt enable bit + + 25 + 1 + read-write + + + B_0x0 + no interrupt generated when an ECC single correction error occurs + 0x0 + + + B_0x1 + non-secure interrupt generated when an ECC single correction error occurs + 0x1 + + + + + ECCC + ECC correction set by hardware when single ECC error has been detected and corrected. + 30 + 1 + read-write + + + + + FLASH_ECCDETR + FLASH_ECCDETR + FLASH ECC detection register + 0x104 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ADDR_ECC + ECC error address + + 0 + 16 + read-only + + + OBK_ECC + ECC fail double ECC error in flash OB Keys storage area. + 20 + 1 + read-only + + + EDATA_ECC + ECC fail double ECC error in flash high-cycle data area + + 21 + 1 + read-only + + + BK_ECC + ECC fail bank for double ECC error + + 22 + 1 + read-only + + + SYSF_ECC + ECC fail for double ECC error in system flash memory + + 23 + 1 + read-only + + + OTP_ECC + OTP ECC error bit + + 24 + 1 + read-only + + + ECCD + ECC detection + + 31 + 1 + read-write + + + + + FLASH_ECCDR + FLASH_ECCDR + FLASH ECC data + 0x108 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + DATA_ECC + ECC error data + + 0 + 16 + read-only + + + + + FLASH_SECBB2R1 + FLASH_SECBB2R1 + FLASH secure block-based register for Bank2 + 0x1A0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SECBB2 + Secure/non-secure flash Bank2 sector attribute + 0 + 32 + read-write + + + B_0x0 + sectors (32 * (x-1) + y) in Bank2 is non secure + 0x0 + + + B_0x1 + sector (32 * (x-1) + y) in Bank2 is secure + 0x1 + + + + + + + FLASH_SECBB2R2 + FLASH_SECBB2R2 + FLASH secure block-based register for Bank2 + 0x1A4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SECBB2 + Secure/non-secure flash Bank2 sector attribute + 0 + 32 + read-write + + + B_0x0 + sectors (32 * (x-1) + y) in Bank2 is non secure + 0x0 + + + B_0x1 + sector (32 * (x-1) + y) in Bank2 is secure + 0x1 + + + + + + + FLASH_SECBB2R3 + FLASH_SECBB2R3 + FLASH secure block-based register for Bank2 + 0x1A8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SECBB2 + Secure/non-secure flash Bank2 sector attribute + 0 + 32 + read-write + + + B_0x0 + sectors (32 * (x-1) + y) in Bank2 is non secure + 0x0 + + + B_0x1 + sector (32 * (x-1) + y) in Bank2 is secure + 0x1 + + + + + + + FLASH_SECBB2R4 + FLASH_SECBB2R4 + FLASH secure block-based register for Bank2 + 0x1AC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SECBB2 + Secure/non-secure flash Bank2 sector attribute + 0 + 32 + read-write + + + B_0x0 + sectors (32 * (x-1) + y) in Bank2 is non secure + 0x0 + + + B_0x1 + sector (32 * (x-1) + y) in Bank2 is secure + 0x1 + + + + + + + FLASH_PRIVBB2R1 + FLASH_PRIVBB2R1 + FLASH privilege block-based register for Bank2 + 0x1C0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRIVBB2 + Privileged / non-privileged 8-Kbyte flash Bank2 sector attribute + 0 + 32 + read-write + + + B_0x0 + sectors (32 * (x-1) + y) in Bank2 is unprivileged + 0x0 + + + B_0x1 + sector (32 * (x-1) + y) in Bank2 is privileged + 0x1 + + + + + + + FLASH_PRIVBB2R2 + FLASH_PRIVBB2R2 + FLASH privilege block-based register for Bank2 + 0x1C4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRIVBB2 + Privileged / non-privileged 8-Kbyte flash Bank2 sector attribute + 0 + 32 + read-write + + + B_0x0 + sectors (32 * (x-1) + y) in Bank2 is unprivileged + 0x0 + + + B_0x1 + sector (32 * (x-1) + y) in Bank2 is privileged + 0x1 + + + + + + + FLASH_PRIVBB2R3 + FLASH_PRIVBB2R3 + FLASH privilege block-based register for Bank2 + 0x1C8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRIVBB2 + Privileged / non-privileged 8-Kbyte flash Bank2 sector attribute + 0 + 32 + read-write + + + B_0x0 + sectors (32 * (x-1) + y) in Bank2 is unprivileged + 0x0 + + + B_0x1 + sector (32 * (x-1) + y) in Bank2 is privileged + 0x1 + + + + + + + FLASH_PRIVBB2R4 + FLASH_PRIVBB2R4 + FLASH privilege block-based register for Bank2 + 0x1CC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRIVBB2 + Privileged / non-privileged 8-Kbyte flash Bank2 sector attribute + 0 + 32 + read-write + + + B_0x0 + sectors (32 * (x-1) + y) in Bank2 is unprivileged + 0x0 + + + B_0x1 + sector (32 * (x-1) + y) in Bank2 is privileged + 0x1 + + + + + + + FLASH_SECWM2R_CUR + FLASH_SECWM2R_CUR + FLASH security watermark for Bank2 + 0x1E0 + 0x20 + read-only + 0x00000000 + 0xFF00FF00 + + + SECWM2_STRT + Bank2 security WM area start sector + + 0 + 7 + read-only + + + SECWM2_END + Bank2 security WM end sector + + 16 + 7 + read-only + + + + + FLASH_SECWM2R_PRG + FLASH_SECWM2R_PRG + FLASH security watermark for Bank2 + 0x1E4 + 0x20 + read-write + 0x00000000 + 0xFF00FF00 + + + SECWM2_STRT + Bank2 security WM area start sector + + 0 + 7 + read-write + + + SECWM2_END + Bank2 security WM area end sector + + 16 + 7 + read-write + + + + + FLASH_WRP2R_CUR + FLASH_WRP2R_CUR + FLASH write sector group protection for Bank2 + 0x1E8 + 0x20 + read-only + 0x00000000 + 0x00000000 + + + WRPSG2 + Bank2 sector group protection option status byte + + 0 + 32 + read-only + + + + + FLASH_WRP2R_PRG + FLASH_WRP2R_PRG + FLASH write sector group protection for Bank2 + 0x1EC + 0x20 + read-write + 0x00000000 + 0x00000000 + + + WRPSG2 + Bank2 sector group protection option status byte + + 0 + 32 + read-write + + + + + FLASH_EDATA2R_CUR + FLASH_EDATA2R_CUR + FLASH data sectors configuration Bank2 + 0x1F0 + 0x20 + read-only + 0x00000000 + 0x00000000 + + + EDATA2_STRT + EDATA2_STRT contains the start sectors of the flash high-cycle data area in Bank2 There is no hardware effect to those bits. + 0 + 3 + read-only + + + B_0x0 + The last sector of Bank2 is reserved for flash high-cycle data + 0x0 + + + B_0x1 + The two last sectors of Bank2 are reserved for flash high-cycle data + 0x1 + + + B_0x2 + The three last sectors of Bank2 are reserved for flash high-cycle data + 0x2 + + + + + EDATA2_EN + Bank2 flash high-cycle data enable + 15 + 1 + read-only + + + B_0x0 + No flash high-cycle data area + 0x0 + + + B_0x1 + Flash high-cycle data is used + 0x1 + + + + + + + FLASH_EDATA2R_PRG + FLASH_EDATA2R_PRG + FLASH data sector configuration Bank2 + 0x1F4 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + EDATA2_STRT + EDATA2_STRT contains the start sectors of the flash high-cycle data area in Bank2 There is no hardware effect to those bits. + 0 + 3 + read-write + + + B_0x0 + The last sector of Bank2 is reserved for flash high-cycle data. + 0x0 + + + B_0x1 + The two last sectors of Bank2 are reserved for flash high-cycle data. + 0x1 + + + B_0x2 + The three last sectors of Bank2 are reserved for flash high-cycle data. + 0x2 + + + + + EDATA2_EN + Bank2 flash high-cycle data enable + 15 + 1 + read-write + + + B_0x0 + No flash high-cycle data area + 0x0 + + + B_0x1 + Flash high-cycle data is used + 0x1 + + + + + + + FLASH_HDP2R_CUR + FLASH_HDP2R_CUR + FLASH HDP Bank2 configuration + 0x1F8 + 0x20 + read-only + 0x00000000 + 0x00000000 + + + HDP2_STRT + HDPL barrier start set in number of 8-Kbyte sectors + + 0 + 7 + read-only + + + HDP2_END + HDPL barrier end set in number of 8-Kbyte sectors + + 16 + 7 + read-only + + + + + FLASH_HDP2R_PRG + FLASH_HDP2R_PRG + FLASH HDP Bank2 configuration + 0x1FC + 0x20 + read-write + 0x00000000 + 0x00000000 + + + HDP2_STRT + HDPL barrier start set in number of 8-Kbyte sectors + + 0 + 7 + read-write + + + HDP2_END + HDPL barrier end set in number of 8-Kbyte sectors + + 16 + 7 + read-write + + + + + + + FLASH_S + 0x50022000 + + FLASH_S + Flash secure global interrupt + 7 + + + + FMC + FMC address block description + FMC + 0x47000400 + + 0x0 + 0x15C + registers + + + FMC + FMC global interrupt + 77 + + + + FMC_BCR1 + FMC_BCR1 + SRAM/NOR-flash chip-select control register for bank 1 + 0x0 + 0x20 + read-write + 0x000030DB + 0xFFFFFFFF + + + MBKEN + Memory bank enable bit + + 0 + 1 + read-write + + + B_0x0 + Corresponding memory bank is disabled. + 0x0 + + + B_0x1 + Corresponding memory bank is enabled. + 0x1 + + + + + MUXEN + Address/data multiplexing enable bit + + 1 + 1 + read-write + + + B_0x0 + Address/data non multiplexed + 0x0 + + + B_0x1 + Address/data multiplexed on databus (default after reset) + 0x1 + + + + + MTYP + Memory type + + 2 + 2 + read-write + + + B_0x0 + SRAM/FRAM (default after reset for Bank 2. + 0x0 + + + B_0x1 + PSRAM (CRAM) / FRAM + 0x1 + + + B_0x2 + NOR flash/OneNAND flash (default after reset for Bank 1) + 0x2 + + + + + MWID + Memory data bus width + + 4 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits (default after reset) + 0x1 + + + + + FACCEN + Flash access enable + + 6 + 1 + read-write + + + B_0x0 + Corresponding NOR flash memory access is disabled. + 0x0 + + + B_0x1 + Corresponding NOR flash memory access is enabled (default after reset). + 0x1 + + + + + BURSTEN + Burst enable bit + + 8 + 1 + read-write + + + B_0x0 + Burst mode disabled (default after reset). + 0x0 + + + B_0x1 + Burst mode enable. + 0x1 + + + + + WAITPOL + Wait signal polarity bit + + 9 + 1 + read-write + + + B_0x0 + NWAIT active low (default after reset) + 0x0 + + + B_0x1 + NWAIT active high + 0x1 + + + + + WAITCFG + Wait timing configuration + + 11 + 1 + read-write + + + B_0x0 + NWAIT signal is active one data cycle before wait state (default after reset). + 0x0 + + + B_0x1 + NWAIT signal is active during wait state (not used for PSRAM). + 0x1 + + + + + WREN + Write enable bit + + 12 + 1 + read-write + + + B_0x0 + Write operations are disabled in the bank by the FMC, an AHB error is reported. + 0x0 + + + B_0x1 + Write operations are enabled for the bank by the FMC (default after reset). + 0x1 + + + + + WAITEN + Wait enable bit + + 13 + 1 + read-write + + + B_0x0 + NWAIT signal is disabled (its level not taken into account, no wait state inserted after the programmed flash latency period). + 0x0 + + + B_0x1 + NWAIT signal is enabled (its level is taken into account after the programmed latency period to insert wait states if asserted) (default after reset). + 0x1 + + + + + EXTMOD + Extended mode enable + + 14 + 1 + read-write + + + B_0x0 + values inside FMC_BWTR register are not taken into account (default after reset) + 0x0 + + + B_0x1 + values inside FMC_BWTR register are taken into account + 0x1 + + + + + ASYNCWAIT + Wait signal during asynchronous transfers + + 15 + 1 + read-write + + + B_0x0 + NWAIT signal is not taken in to account when running an asynchronous protocol (default after reset). + 0x0 + + + B_0x1 + NWAIT signal is taken in to account when running an asynchronous protocol. + 0x1 + + + + + CPSIZE + CRAM page size + + 16 + 3 + read-write + + + B_0x0 + No burst split when crossing page boundary (default after reset) + 0x0 + + + B_0x1 + 128 bytes + 0x1 + + + B_0x2 + 256 bytes + 0x2 + + + B_0x3 + 512 bytes + 0x3 + + + B_0x4 + 1024 bytes + 0x4 + + + + + CBURSTRW + Write burst enable + + 19 + 1 + read-write + + + B_0x0 + Write operations are always performed in Asynchronous mode. + 0x0 + + + B_0x1 + Write operations are performed in Synchronous mode. + 0x1 + + + + + CCLKEN + Continuous clock enable + + 20 + 1 + read-write + + + B_0x0 + The FMC_CLK is only generated during the synchronous memory access (read/write transaction). + 0x0 + + + B_0x1 + The FMC_CLK is generated continuously during asynchronous and synchronous access. + 0x1 + + + + + WFDIS + Write FIFO disable + + 21 + 1 + read-write + + + B_0x0 + Write FIFO enabled (Default after reset) + 0x0 + + + B_0x1 + Write FIFO disabled + 0x1 + + + + + NBLSET + Byte lane (NBL) setup + + 22 + 2 + read-write + + + B_0x0 + NBL setup time is 0 AHB clock cycle + 0x0 + + + B_0x1 + NBL setup time is 1 AHB clock cycle + 0x1 + + + B_0x2 + NBL setup time is 2 AHB clock cycles + 0x2 + + + B_0x3 + NBL setup time is 3 AHB clock cycles + 0x3 + + + + + FMCEN + FMC controller enable + + 31 + 1 + read-write + + + B_0x0 + Disable the FMC controller + 0x0 + + + B_0x1 + Enable the FMC controller + 0x1 + + + + + + + FMC_BTR1 + FMC_BTR1 + SRAM/NOR-flash chip-select timing register for bank 1 + 0x4 + 0x20 + read-write + 0x0FFFFFFF + 0xFFFFFFFF + + + ADDSET + Address setup phase duration + + 0 + 4 + read-write + + + B_0x0 + ADDSET phase duration = 0 HCLK clock cycle + 0x0 + + + B_0xF + ADDSET phase duration = 15 HCLK clock cycles (default value after reset) + 0xF + + + + + ADDHLD + Address-hold phase duration + + 4 + 4 + read-write + + + B_0x1 + ADDHLD phase duration =1 HCLK clock cycle + 0x1 + + + B_0x2 + ADDHLD phase duration = 2 HCLK clock cycle + 0x2 + + + B_0xF + ADDHLD phase duration = 15 HCLK clock cycles (default value after reset) + 0xF + + + + + DATAST + Data-phase duration + + 8 + 8 + read-write + + + B_0x1 + DATAST phase duration = 1 HCLK clock cycles + 0x1 + + + B_0x2 + DATAST phase duration = 2 HCLK clock cycles + 0x2 + + + B_0xFF + DATAST phase duration = 255 HCLK clock cycles (default value after reset) + 0xFF + + + + + BUSTURN + Bus turnaround phase duration + + 16 + 4 + read-write + + + B_0x0 + BUSTURN phase duration = 1 HCLK clock cycle added + 0x0 + + + B_0xF + BUSTURN phase duration = 16 x HCLK clock cycles added (default value after reset) + 0xF + + + + + CLKDIV + Clock divide ratio (for FMC_CLK signal) + + 20 + 4 + read-write + + + B_0x0 + FMC_CLK period= 1x HCLK period + 0x0 + + + B_0x1 + FMC_CLK period = 2 HCLK periods + 0x1 + + + B_0x2 + FMC_CLK period = 3 HCLK periods + 0x2 + + + B_0xF + FMC_CLK period = 16 HCLK periods (default value after reset) + 0xF + + + + + DATLAT + (see note below bit descriptions): Data latency for synchronous memory + + 24 + 4 + read-write + + + B_0x0 + Data latency of 2 CLK clock cycles for first burst access + 0x0 + + + B_0xF + Data latency of 17 CLK clock cycles for first burst access (default value after reset) + 0xF + + + + + ACCMOD + Access mode + + 28 + 2 + read-write + + + B_0x0 + Access mode A + 0x0 + + + B_0x1 + Access mode B + 0x1 + + + B_0x2 + Access mode C + 0x2 + + + B_0x3 + Access mode D + 0x3 + + + + + DATAHLD + Data hold phase duration + + 30 + 2 + read-write + + + B_0x0 + DATAHLD phase duration = 1 HCLK clock cycle (default) + 0x0 + + + B_0x1 + DATAHLD phase duration = 2 HCLK clock cycle + 0x1 + + + B_0x2 + DATAHLD phase duration = 3 HCLK clock cycle + 0x2 + + + B_0x3 + DATAHLD phase duration = 4 HCLK clock cycle + 0x3 + + + + + + + FMC_BCR2 + FMC_BCR2 + SRAM/NOR-flash chip-select control register for bank 2 + 0x8 + 0x20 + read-write + 0x000030D2 + 0xFFFFFFFF + + + MBKEN + Memory bank enable bit + + 0 + 1 + read-write + + + B_0x0 + Corresponding memory bank is disabled. + 0x0 + + + B_0x1 + Corresponding memory bank is enabled. + 0x1 + + + + + MUXEN + Address/data multiplexing enable bit + + 1 + 1 + read-write + + + B_0x0 + Address/data non multiplexed + 0x0 + + + B_0x1 + Address/data multiplexed on databus (default after reset) + 0x1 + + + + + MTYP + Memory type + + 2 + 2 + read-write + + + B_0x0 + SRAM/FRAM (default after reset for Bank 2. + 0x0 + + + B_0x1 + PSRAM (CRAM) / FRAM + 0x1 + + + B_0x2 + NOR flash/OneNAND flash (default after reset for Bank 1) + 0x2 + + + + + MWID + Memory data bus width + + 4 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits (default after reset) + 0x1 + + + + + FACCEN + Flash access enable + + 6 + 1 + read-write + + + B_0x0 + Corresponding NOR flash memory access is disabled. + 0x0 + + + B_0x1 + Corresponding NOR flash memory access is enabled (default after reset). + 0x1 + + + + + BURSTEN + Burst enable bit + + 8 + 1 + read-write + + + B_0x0 + Burst mode disabled (default after reset). + 0x0 + + + B_0x1 + Burst mode enable. + 0x1 + + + + + WAITPOL + Wait signal polarity bit + + 9 + 1 + read-write + + + B_0x0 + NWAIT active low (default after reset) + 0x0 + + + B_0x1 + NWAIT active high + 0x1 + + + + + WAITCFG + Wait timing configuration + + 11 + 1 + read-write + + + B_0x0 + NWAIT signal is active one data cycle before wait state (default after reset). + 0x0 + + + B_0x1 + NWAIT signal is active during wait state (not used for PSRAM). + 0x1 + + + + + WREN + Write enable bit + + 12 + 1 + read-write + + + B_0x0 + Write operations are disabled in the bank by the FMC, an AHB error is reported. + 0x0 + + + B_0x1 + Write operations are enabled for the bank by the FMC (default after reset). + 0x1 + + + + + WAITEN + Wait enable bit + + 13 + 1 + read-write + + + B_0x0 + NWAIT signal is disabled (its level not taken into account, no wait state inserted after the programmed flash latency period). + 0x0 + + + B_0x1 + NWAIT signal is enabled (its level is taken into account after the programmed latency period to insert wait states if asserted) (default after reset). + 0x1 + + + + + EXTMOD + Extended mode enable + + 14 + 1 + read-write + + + B_0x0 + values inside FMC_BWTR register are not taken into account (default after reset) + 0x0 + + + B_0x1 + values inside FMC_BWTR register are taken into account + 0x1 + + + + + ASYNCWAIT + Wait signal during asynchronous transfers + + 15 + 1 + read-write + + + B_0x0 + NWAIT signal is not taken in to account when running an asynchronous protocol (default after reset). + 0x0 + + + B_0x1 + NWAIT signal is taken in to account when running an asynchronous protocol. + 0x1 + + + + + CPSIZE + CRAM page size + + 16 + 3 + read-write + + + B_0x0 + No burst split when crossing page boundary (default after reset) + 0x0 + + + B_0x1 + 128 bytes + 0x1 + + + B_0x2 + 256 bytes + 0x2 + + + B_0x3 + 512 bytes + 0x3 + + + B_0x4 + 1024 bytes + 0x4 + + + + + CBURSTRW + Write burst enable + + 19 + 1 + read-write + + + B_0x0 + Write operations are always performed in Asynchronous mode. + 0x0 + + + B_0x1 + Write operations are performed in Synchronous mode. + 0x1 + + + + + CCLKEN + Continuous clock enable + + 20 + 1 + read-write + + + B_0x0 + The FMC_CLK is only generated during the synchronous memory access (read/write transaction). + 0x0 + + + B_0x1 + The FMC_CLK is generated continuously during asynchronous and synchronous access. + 0x1 + + + + + WFDIS + Write FIFO disable + + 21 + 1 + read-write + + + B_0x0 + Write FIFO enabled (Default after reset) + 0x0 + + + B_0x1 + Write FIFO disabled + 0x1 + + + + + NBLSET + Byte lane (NBL) setup + + 22 + 2 + read-write + + + B_0x0 + NBL setup time is 0 AHB clock cycle + 0x0 + + + B_0x1 + NBL setup time is 1 AHB clock cycle + 0x1 + + + B_0x2 + NBL setup time is 2 AHB clock cycles + 0x2 + + + B_0x3 + NBL setup time is 3 AHB clock cycles + 0x3 + + + + + FMCEN + FMC controller enable + + 31 + 1 + read-write + + + B_0x0 + Disable the FMC controller + 0x0 + + + B_0x1 + Enable the FMC controller + 0x1 + + + + + + + FMC_BTR2 + FMC_BTR2 + SRAM/NOR-flash chip-select timing register for bank 2 + 0xC + 0x20 + read-write + 0x0FFFFFFF + 0xFFFFFFFF + + + ADDSET + Address setup phase duration + + 0 + 4 + read-write + + + B_0x0 + ADDSET phase duration = 0 HCLK clock cycle + 0x0 + + + B_0xF + ADDSET phase duration = 15 HCLK clock cycles (default value after reset) + 0xF + + + + + ADDHLD + Address-hold phase duration + + 4 + 4 + read-write + + + B_0x1 + ADDHLD phase duration =1 HCLK clock cycle + 0x1 + + + B_0x2 + ADDHLD phase duration = 2 HCLK clock cycle + 0x2 + + + B_0xF + ADDHLD phase duration = 15 HCLK clock cycles (default value after reset) + 0xF + + + + + DATAST + Data-phase duration + + 8 + 8 + read-write + + + B_0x1 + DATAST phase duration = 1 HCLK clock cycles + 0x1 + + + B_0x2 + DATAST phase duration = 2 HCLK clock cycles + 0x2 + + + B_0xFF + DATAST phase duration = 255 HCLK clock cycles (default value after reset) + 0xFF + + + + + BUSTURN + Bus turnaround phase duration + + 16 + 4 + read-write + + + B_0x0 + BUSTURN phase duration = 1 HCLK clock cycle added + 0x0 + + + B_0xF + BUSTURN phase duration = 16 x HCLK clock cycles added (default value after reset) + 0xF + + + + + CLKDIV + Clock divide ratio (for FMC_CLK signal) + + 20 + 4 + read-write + + + B_0x0 + FMC_CLK period= 1x HCLK period + 0x0 + + + B_0x1 + FMC_CLK period = 2 HCLK periods + 0x1 + + + B_0x2 + FMC_CLK period = 3 HCLK periods + 0x2 + + + B_0xF + FMC_CLK period = 16 HCLK periods (default value after reset) + 0xF + + + + + DATLAT + (see note below bit descriptions): Data latency for synchronous memory + + 24 + 4 + read-write + + + B_0x0 + Data latency of 2 CLK clock cycles for first burst access + 0x0 + + + B_0xF + Data latency of 17 CLK clock cycles for first burst access (default value after reset) + 0xF + + + + + ACCMOD + Access mode + + 28 + 2 + read-write + + + B_0x0 + Access mode A + 0x0 + + + B_0x1 + Access mode B + 0x1 + + + B_0x2 + Access mode C + 0x2 + + + B_0x3 + Access mode D + 0x3 + + + + + DATAHLD + Data hold phase duration + + 30 + 2 + read-write + + + B_0x0 + DATAHLD phase duration = 1 HCLK clock cycle (default) + 0x0 + + + B_0x1 + DATAHLD phase duration = 2 HCLK clock cycle + 0x1 + + + B_0x2 + DATAHLD phase duration = 3 HCLK clock cycle + 0x2 + + + B_0x3 + DATAHLD phase duration = 4 HCLK clock cycle + 0x3 + + + + + + + FMC_BCR3 + FMC_BCR3 + SRAM/NOR-flash chip-select control register for bank 3 + 0x10 + 0x20 + read-write + 0x000030D2 + 0xFFFFFFFF + + + MBKEN + Memory bank enable bit + + 0 + 1 + read-write + + + B_0x0 + Corresponding memory bank is disabled. + 0x0 + + + B_0x1 + Corresponding memory bank is enabled. + 0x1 + + + + + MUXEN + Address/data multiplexing enable bit + + 1 + 1 + read-write + + + B_0x0 + Address/data non multiplexed + 0x0 + + + B_0x1 + Address/data multiplexed on databus (default after reset) + 0x1 + + + + + MTYP + Memory type + + 2 + 2 + read-write + + + B_0x0 + SRAM/FRAM (default after reset for Bank 2. + 0x0 + + + B_0x1 + PSRAM (CRAM) / FRAM + 0x1 + + + B_0x2 + NOR flash/OneNAND flash (default after reset for Bank 1) + 0x2 + + + + + MWID + Memory data bus width + + 4 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits (default after reset) + 0x1 + + + + + FACCEN + Flash access enable + + 6 + 1 + read-write + + + B_0x0 + Corresponding NOR flash memory access is disabled. + 0x0 + + + B_0x1 + Corresponding NOR flash memory access is enabled (default after reset). + 0x1 + + + + + BURSTEN + Burst enable bit + + 8 + 1 + read-write + + + B_0x0 + Burst mode disabled (default after reset). + 0x0 + + + B_0x1 + Burst mode enable. + 0x1 + + + + + WAITPOL + Wait signal polarity bit + + 9 + 1 + read-write + + + B_0x0 + NWAIT active low (default after reset) + 0x0 + + + B_0x1 + NWAIT active high + 0x1 + + + + + WAITCFG + Wait timing configuration + + 11 + 1 + read-write + + + B_0x0 + NWAIT signal is active one data cycle before wait state (default after reset). + 0x0 + + + B_0x1 + NWAIT signal is active during wait state (not used for PSRAM). + 0x1 + + + + + WREN + Write enable bit + + 12 + 1 + read-write + + + B_0x0 + Write operations are disabled in the bank by the FMC, an AHB error is reported. + 0x0 + + + B_0x1 + Write operations are enabled for the bank by the FMC (default after reset). + 0x1 + + + + + WAITEN + Wait enable bit + + 13 + 1 + read-write + + + B_0x0 + NWAIT signal is disabled (its level not taken into account, no wait state inserted after the programmed flash latency period). + 0x0 + + + B_0x1 + NWAIT signal is enabled (its level is taken into account after the programmed latency period to insert wait states if asserted) (default after reset). + 0x1 + + + + + EXTMOD + Extended mode enable + + 14 + 1 + read-write + + + B_0x0 + values inside FMC_BWTR register are not taken into account (default after reset) + 0x0 + + + B_0x1 + values inside FMC_BWTR register are taken into account + 0x1 + + + + + ASYNCWAIT + Wait signal during asynchronous transfers + + 15 + 1 + read-write + + + B_0x0 + NWAIT signal is not taken in to account when running an asynchronous protocol (default after reset). + 0x0 + + + B_0x1 + NWAIT signal is taken in to account when running an asynchronous protocol. + 0x1 + + + + + CPSIZE + CRAM page size + + 16 + 3 + read-write + + + B_0x0 + No burst split when crossing page boundary (default after reset) + 0x0 + + + B_0x1 + 128 bytes + 0x1 + + + B_0x2 + 256 bytes + 0x2 + + + B_0x3 + 512 bytes + 0x3 + + + B_0x4 + 1024 bytes + 0x4 + + + + + CBURSTRW + Write burst enable + + 19 + 1 + read-write + + + B_0x0 + Write operations are always performed in Asynchronous mode. + 0x0 + + + B_0x1 + Write operations are performed in Synchronous mode. + 0x1 + + + + + CCLKEN + Continuous clock enable + + 20 + 1 + read-write + + + B_0x0 + The FMC_CLK is only generated during the synchronous memory access (read/write transaction). + 0x0 + + + B_0x1 + The FMC_CLK is generated continuously during asynchronous and synchronous access. + 0x1 + + + + + WFDIS + Write FIFO disable + + 21 + 1 + read-write + + + B_0x0 + Write FIFO enabled (Default after reset) + 0x0 + + + B_0x1 + Write FIFO disabled + 0x1 + + + + + NBLSET + Byte lane (NBL) setup + + 22 + 2 + read-write + + + B_0x0 + NBL setup time is 0 AHB clock cycle + 0x0 + + + B_0x1 + NBL setup time is 1 AHB clock cycle + 0x1 + + + B_0x2 + NBL setup time is 2 AHB clock cycles + 0x2 + + + B_0x3 + NBL setup time is 3 AHB clock cycles + 0x3 + + + + + FMCEN + FMC controller enable + + 31 + 1 + read-write + + + B_0x0 + Disable the FMC controller + 0x0 + + + B_0x1 + Enable the FMC controller + 0x1 + + + + + + + FMC_BTR3 + FMC_BTR3 + SRAM/NOR-flash chip-select timing register for bank 3 + 0x14 + 0x20 + read-write + 0x0FFFFFFF + 0xFFFFFFFF + + + ADDSET + Address setup phase duration + + 0 + 4 + read-write + + + B_0x0 + ADDSET phase duration = 0 HCLK clock cycle + 0x0 + + + B_0xF + ADDSET phase duration = 15 HCLK clock cycles (default value after reset) + 0xF + + + + + ADDHLD + Address-hold phase duration + + 4 + 4 + read-write + + + B_0x1 + ADDHLD phase duration =1 HCLK clock cycle + 0x1 + + + B_0x2 + ADDHLD phase duration = 2 HCLK clock cycle + 0x2 + + + B_0xF + ADDHLD phase duration = 15 HCLK clock cycles (default value after reset) + 0xF + + + + + DATAST + Data-phase duration + + 8 + 8 + read-write + + + B_0x1 + DATAST phase duration = 1 HCLK clock cycles + 0x1 + + + B_0x2 + DATAST phase duration = 2 HCLK clock cycles + 0x2 + + + B_0xFF + DATAST phase duration = 255 HCLK clock cycles (default value after reset) + 0xFF + + + + + BUSTURN + Bus turnaround phase duration + + 16 + 4 + read-write + + + B_0x0 + BUSTURN phase duration = 1 HCLK clock cycle added + 0x0 + + + B_0xF + BUSTURN phase duration = 16 x HCLK clock cycles added (default value after reset) + 0xF + + + + + CLKDIV + Clock divide ratio (for FMC_CLK signal) + + 20 + 4 + read-write + + + B_0x0 + FMC_CLK period= 1x HCLK period + 0x0 + + + B_0x1 + FMC_CLK period = 2 HCLK periods + 0x1 + + + B_0x2 + FMC_CLK period = 3 HCLK periods + 0x2 + + + B_0xF + FMC_CLK period = 16 HCLK periods (default value after reset) + 0xF + + + + + DATLAT + (see note below bit descriptions): Data latency for synchronous memory + + 24 + 4 + read-write + + + B_0x0 + Data latency of 2 CLK clock cycles for first burst access + 0x0 + + + B_0xF + Data latency of 17 CLK clock cycles for first burst access (default value after reset) + 0xF + + + + + ACCMOD + Access mode + + 28 + 2 + read-write + + + B_0x0 + Access mode A + 0x0 + + + B_0x1 + Access mode B + 0x1 + + + B_0x2 + Access mode C + 0x2 + + + B_0x3 + Access mode D + 0x3 + + + + + DATAHLD + Data hold phase duration + + 30 + 2 + read-write + + + B_0x0 + DATAHLD phase duration = 1 HCLK clock cycle (default) + 0x0 + + + B_0x1 + DATAHLD phase duration = 2 HCLK clock cycle + 0x1 + + + B_0x2 + DATAHLD phase duration = 3 HCLK clock cycle + 0x2 + + + B_0x3 + DATAHLD phase duration = 4 HCLK clock cycle + 0x3 + + + + + + + FMC_BCR4 + FMC_BCR4 + SRAM/NOR-flash chip-select control register for bank 4 + 0x18 + 0x20 + read-write + 0x000030D2 + 0xFFFFFFFF + + + MBKEN + Memory bank enable bit + + 0 + 1 + read-write + + + B_0x0 + Corresponding memory bank is disabled. + 0x0 + + + B_0x1 + Corresponding memory bank is enabled. + 0x1 + + + + + MUXEN + Address/data multiplexing enable bit + + 1 + 1 + read-write + + + B_0x0 + Address/data non multiplexed + 0x0 + + + B_0x1 + Address/data multiplexed on databus (default after reset) + 0x1 + + + + + MTYP + Memory type + + 2 + 2 + read-write + + + B_0x0 + SRAM/FRAM (default after reset for Bank 2. + 0x0 + + + B_0x1 + PSRAM (CRAM) / FRAM + 0x1 + + + B_0x2 + NOR flash/OneNAND flash (default after reset for Bank 1) + 0x2 + + + + + MWID + Memory data bus width + + 4 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits (default after reset) + 0x1 + + + + + FACCEN + Flash access enable + + 6 + 1 + read-write + + + B_0x0 + Corresponding NOR flash memory access is disabled. + 0x0 + + + B_0x1 + Corresponding NOR flash memory access is enabled (default after reset). + 0x1 + + + + + BURSTEN + Burst enable bit + + 8 + 1 + read-write + + + B_0x0 + Burst mode disabled (default after reset). + 0x0 + + + B_0x1 + Burst mode enable. + 0x1 + + + + + WAITPOL + Wait signal polarity bit + + 9 + 1 + read-write + + + B_0x0 + NWAIT active low (default after reset) + 0x0 + + + B_0x1 + NWAIT active high + 0x1 + + + + + WAITCFG + Wait timing configuration + + 11 + 1 + read-write + + + B_0x0 + NWAIT signal is active one data cycle before wait state (default after reset). + 0x0 + + + B_0x1 + NWAIT signal is active during wait state (not used for PSRAM). + 0x1 + + + + + WREN + Write enable bit + + 12 + 1 + read-write + + + B_0x0 + Write operations are disabled in the bank by the FMC, an AHB error is reported. + 0x0 + + + B_0x1 + Write operations are enabled for the bank by the FMC (default after reset). + 0x1 + + + + + WAITEN + Wait enable bit + + 13 + 1 + read-write + + + B_0x0 + NWAIT signal is disabled (its level not taken into account, no wait state inserted after the programmed flash latency period). + 0x0 + + + B_0x1 + NWAIT signal is enabled (its level is taken into account after the programmed latency period to insert wait states if asserted) (default after reset). + 0x1 + + + + + EXTMOD + Extended mode enable + + 14 + 1 + read-write + + + B_0x0 + values inside FMC_BWTR register are not taken into account (default after reset) + 0x0 + + + B_0x1 + values inside FMC_BWTR register are taken into account + 0x1 + + + + + ASYNCWAIT + Wait signal during asynchronous transfers + + 15 + 1 + read-write + + + B_0x0 + NWAIT signal is not taken in to account when running an asynchronous protocol (default after reset). + 0x0 + + + B_0x1 + NWAIT signal is taken in to account when running an asynchronous protocol. + 0x1 + + + + + CPSIZE + CRAM page size + + 16 + 3 + read-write + + + B_0x0 + No burst split when crossing page boundary (default after reset) + 0x0 + + + B_0x1 + 128 bytes + 0x1 + + + B_0x2 + 256 bytes + 0x2 + + + B_0x3 + 512 bytes + 0x3 + + + B_0x4 + 1024 bytes + 0x4 + + + + + CBURSTRW + Write burst enable + + 19 + 1 + read-write + + + B_0x0 + Write operations are always performed in Asynchronous mode. + 0x0 + + + B_0x1 + Write operations are performed in Synchronous mode. + 0x1 + + + + + CCLKEN + Continuous clock enable + + 20 + 1 + read-write + + + B_0x0 + The FMC_CLK is only generated during the synchronous memory access (read/write transaction). + 0x0 + + + B_0x1 + The FMC_CLK is generated continuously during asynchronous and synchronous access. + 0x1 + + + + + WFDIS + Write FIFO disable + + 21 + 1 + read-write + + + B_0x0 + Write FIFO enabled (Default after reset) + 0x0 + + + B_0x1 + Write FIFO disabled + 0x1 + + + + + NBLSET + Byte lane (NBL) setup + + 22 + 2 + read-write + + + B_0x0 + NBL setup time is 0 AHB clock cycle + 0x0 + + + B_0x1 + NBL setup time is 1 AHB clock cycle + 0x1 + + + B_0x2 + NBL setup time is 2 AHB clock cycles + 0x2 + + + B_0x3 + NBL setup time is 3 AHB clock cycles + 0x3 + + + + + FMCEN + FMC controller enable + + 31 + 1 + read-write + + + B_0x0 + Disable the FMC controller + 0x0 + + + B_0x1 + Enable the FMC controller + 0x1 + + + + + + + FMC_BTR4 + FMC_BTR4 + SRAM/NOR-flash chip-select timing register for bank 4 + 0x1C + 0x20 + read-write + 0x0FFFFFFF + 0xFFFFFFFF + + + ADDSET + Address setup phase duration + + 0 + 4 + read-write + + + B_0x0 + ADDSET phase duration = 0 HCLK clock cycle + 0x0 + + + B_0xF + ADDSET phase duration = 15 HCLK clock cycles (default value after reset) + 0xF + + + + + ADDHLD + Address-hold phase duration + + 4 + 4 + read-write + + + B_0x1 + ADDHLD phase duration =1 HCLK clock cycle + 0x1 + + + B_0x2 + ADDHLD phase duration = 2 HCLK clock cycle + 0x2 + + + B_0xF + ADDHLD phase duration = 15 HCLK clock cycles (default value after reset) + 0xF + + + + + DATAST + Data-phase duration + + 8 + 8 + read-write + + + B_0x1 + DATAST phase duration = 1 HCLK clock cycles + 0x1 + + + B_0x2 + DATAST phase duration = 2 HCLK clock cycles + 0x2 + + + B_0xFF + DATAST phase duration = 255 HCLK clock cycles (default value after reset) + 0xFF + + + + + BUSTURN + Bus turnaround phase duration + + 16 + 4 + read-write + + + B_0x0 + BUSTURN phase duration = 1 HCLK clock cycle added + 0x0 + + + B_0xF + BUSTURN phase duration = 16 x HCLK clock cycles added (default value after reset) + 0xF + + + + + CLKDIV + Clock divide ratio (for FMC_CLK signal) + + 20 + 4 + read-write + + + B_0x0 + FMC_CLK period= 1x HCLK period + 0x0 + + + B_0x1 + FMC_CLK period = 2 HCLK periods + 0x1 + + + B_0x2 + FMC_CLK period = 3 HCLK periods + 0x2 + + + B_0xF + FMC_CLK period = 16 HCLK periods (default value after reset) + 0xF + + + + + DATLAT + (see note below bit descriptions): Data latency for synchronous memory + + 24 + 4 + read-write + + + B_0x0 + Data latency of 2 CLK clock cycles for first burst access + 0x0 + + + B_0xF + Data latency of 17 CLK clock cycles for first burst access (default value after reset) + 0xF + + + + + ACCMOD + Access mode + + 28 + 2 + read-write + + + B_0x0 + Access mode A + 0x0 + + + B_0x1 + Access mode B + 0x1 + + + B_0x2 + Access mode C + 0x2 + + + B_0x3 + Access mode D + 0x3 + + + + + DATAHLD + Data hold phase duration + + 30 + 2 + read-write + + + B_0x0 + DATAHLD phase duration = 1 HCLK clock cycle (default) + 0x0 + + + B_0x1 + DATAHLD phase duration = 2 HCLK clock cycle + 0x1 + + + B_0x2 + DATAHLD phase duration = 3 HCLK clock cycle + 0x2 + + + B_0x3 + DATAHLD phase duration = 4 HCLK clock cycle + 0x3 + + + + + + + FMC_PCSCNTR + FMC_PCSCNTR + PSRAM chip select counter register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CSCOUNT + Chip select counter. + 0 + 16 + read-write + + + CNTB1EN + Counter Bank 1 enable + + 16 + 1 + read-write + + + B_0x0 + Counter disabled for Bank 1 + 0x0 + + + B_0x1 + Counter enabled for Bank 1 + 0x1 + + + + + CNTB2EN + Counter Bank 2 enable + + 17 + 1 + read-write + + + B_0x0 + Counter disabled for Bank 2 + 0x0 + + + B_0x1 + Counter enabled for Bank 2 + 0x1 + + + + + CNTB3EN + Counter Bank 3 enable + + 18 + 1 + read-write + + + B_0x0 + Counter disabled for Bank 3. + 0x0 + + + B_0x1 + Counter enabled for Bank 3 + 0x1 + + + + + CNTB4EN + Counter Bank 4 enable + + 19 + 1 + read-write + + + B_0x0 + Counter disabled for Bank 4 + 0x0 + + + B_0x1 + Counter enabled for Bank 4 + 0x1 + + + + + + + FMC_PCR + FMC_PCR + NAND flash control registers + 0x80 + 0x20 + read-write + 0x00000018 + 0xFFFFFFFF + + + PWAITEN + Wait feature enable bit + + 1 + 1 + read-write + + + B_0x0 + disabled + 0x0 + + + B_0x1 + enabled + 0x1 + + + + + PBKEN + NAND flash memory bank enable bit + + 2 + 1 + read-write + + + B_0x0 + Corresponding memory bank is disabled (default after reset) + 0x0 + + + B_0x1 + Corresponding memory bank is enabled + 0x1 + + + + + PTYP + Memory type + + 3 + 1 + read-write + + + B_0x1 + NAND flash (default after reset) + 0x1 + + + + + PWID + Data bus width + + 4 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits (default after reset). + 0x1 + + + + + ECCEN + ECC computation logic enable bit + 6 + 1 + read-write + + + B_0x0 + ECC logic is disabled and reset (default after reset), + 0x0 + + + B_0x1 + ECC logic is enabled. + 0x1 + + + + + TCLR + CLE to RE delay + + 9 + 4 + read-write + + + B_0x0 + 1 HCLK cycle (default) + 0x0 + + + B_0xF + 16 HCLK cycles + 0xF + + + + + TAR + ALE to RE delay + + 13 + 3 + read-write + + + B_0x0 + 1 HCLK cycle (default) + 0x0 + + + + + TAR3 + ALE to RE delay + + 16 + 1 + read-write + + + B_0x0 + 1 HCLK cycle (default) + 0x0 + + + + + ECCPS + ECC page size + + 17 + 3 + read-write + + + B_0x0 + 256 bytes + 0x0 + + + B_0x1 + 512 bytes + 0x1 + + + B_0x2 + 1024 bytes + 0x2 + + + B_0x3 + 2048 bytes + 0x3 + + + B_0x4 + 4096 bytes + 0x4 + + + B_0x5 + 8192 bytes + 0x5 + + + + + + + FMC_SR + FMC_SR + FIFO status and interrupt register + 0x84 + 0x20 + read-write + 0x00000040 + 0xFFFFFFFF + + + IRS + Interrupt rising edge status + + 0 + 1 + read-write + + + B_0x0 + No interrupt rising edge occurred + 0x0 + + + B_0x1 + Interrupt rising edge occurred + 0x1 + + + + + ILS + Interrupt high-level status + + 1 + 1 + read-write + + + B_0x0 + No Interrupt high-level occurred + 0x0 + + + B_0x1 + Interrupt high-level occurred + 0x1 + + + + + IFS + Interrupt falling edge status + + 2 + 1 + read-write + + + B_0x0 + No interrupt falling edge occurred + 0x0 + + + B_0x1 + Interrupt falling edge occurred + 0x1 + + + + + IREN + Interrupt rising edge detection enable bit + 3 + 1 + read-write + + + B_0x0 + Interrupt rising edge detection request disabled + 0x0 + + + B_0x1 + Interrupt rising edge detection request enabled + 0x1 + + + + + ILEN + Interrupt high-level detection enable bit + 4 + 1 + read-write + + + B_0x0 + Interrupt high-level detection request disabled + 0x0 + + + B_0x1 + Interrupt high-level detection request enabled + 0x1 + + + + + IFEN + Interrupt falling edge detection enable bit + 5 + 1 + read-write + + + B_0x0 + Interrupt falling edge detection request disabled + 0x0 + + + B_0x1 + Interrupt falling edge detection request enabled + 0x1 + + + + + FEMPT + FIFO empty + + 6 + 1 + read-only + + + B_0x0 + FIFO not empty + 0x0 + + + B_0x1 + FIFO empty + 0x1 + + + + + + + FMC_PMEM + FMC_PMEM + Common memory space timing register + 0x88 + 0x20 + read-write + 0xFCFCFCFC + 0xFFFFFFFF + + + MEMSET + Common memory x setup time + + 0 + 8 + read-write + + + B_0x0 + 1 HCLK cycle + 0x0 + + + B_0xFE + 255 HCLK cycles + 0xFE + + + + + MEMWAIT + Common memory wait time + + 8 + 8 + read-write + + + B_0x1 + 2HCLK cycles (+ wait cycle introduced by deasserting NWAIT) + 0x1 + + + B_0xFE + 255 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) + 0xFE + + + + + MEMHOLD + Common memory hold time + + 16 + 8 + read-write + + + B_0x1 + 1 HCLK cycle for write access / 3 HCLK cycles for read access + 0x1 + + + B_0xFE + 254 HCLK cycles for write access / 256 HCLK cycles for read access + 0xFE + + + + + MEMHIZ + Common memory x data bus Hi-Z time + + 24 + 8 + read-write + + + B_0x0 + 1 HCLK cycle + 0x0 + + + B_0xFE + 255 HCLK cycles + 0xFE + + + + + + + FMC_PATT + FMC_PATT + Attribute memory space timing register + 0x8C + 0x20 + read-write + 0xFCFCFCFC + 0xFFFFFFFF + + + ATTSET + Attribute memory setup time + + 0 + 8 + read-write + + + B_0x0 + 1 HCLK cycle + 0x0 + + + B_0xFE + 255 HCLK cycles + 0xFE + + + + + ATTWAIT + Attribute memory wait time + + 8 + 8 + read-write + + + B_0x1 + 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) + 0x1 + + + B_0xFE + 255 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) + 0xFE + + + + + ATTHOLD + Attribute memory hold time + + 16 + 8 + read-write + + + B_0x1 + 1 HCLK cycle for write access / 3 HCLK cycles for read access + 0x1 + + + B_0xFE + 254 HCLK cycles for write access / 256 HCLK cycles for read access + 0xFE + + + + + ATTHIZ + Attribute memory data bus Hi-Z time + + 24 + 8 + read-write + + + B_0x0 + 0 HCLK cycle + 0x0 + + + B_0xFE + 255 HCLK cycles + 0xFE + + + + + + + FMC_ECCR + FMC_ECCR + ECC result registers + 0x94 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + ECC + ECC result + + 0 + 32 + read-only + + + + + FMC_BWTR1 + FMC_BWTR1 + SRAM/NOR-flash write timing registers 1 + 0x104 + 0x20 + read-write + 0x0FFFFFFF + 0xFFFFFFFF + + + ADDSET + Address setup phase duration. + 0 + 4 + read-write + + + B_0x0 + ADDSET phase duration = 0 HCLK clock cycle + 0x0 + + + B_0xF + ADDSET phase duration = 15 HCLK clock cycles (default value after reset) + 0xF + + + + + ADDHLD + Address-hold phase duration. + 4 + 4 + read-write + + + B_0x1 + ADDHLD phase duration = 1 HCLK clock cycle + 0x1 + + + B_0x2 + ADDHLD phase duration = 2 HCLK clock cycle + 0x2 + + + B_0xF + ADDHLD phase duration = 15 HCLK clock cycles (default value after reset) + 0xF + + + + + DATAST + Data-phase duration. + 8 + 8 + read-write + + + B_0x1 + DATAST phase duration = 1 HCLK clock cycles + 0x1 + + + B_0x2 + DATAST phase duration = 2 HCLK clock cycles + 0x2 + + + B_0xFF + DATAST phase duration = 255 HCLK clock cycles (default value after reset) + 0xFF + + + + + BUSTURN + Bus turnaround phase duration + + 16 + 4 + read-write + + + B_0x0 + BUSTURN phase duration = 1 HCLK clock cycle added + 0x0 + + + B_0xF + BUSTURN phase duration = 16 x HCLK clock cycles added (default value after reset) + 0xF + + + + + ACCMOD + Access mode. + 28 + 2 + read-write + + + B_0x0 + Access mode A + 0x0 + + + B_0x1 + Access mode B + 0x1 + + + B_0x2 + Access mode C + 0x2 + + + B_0x3 + Access mode D + 0x3 + + + + + DATAHLD + Data hold phase duration + + 30 + 2 + read-write + + + B_0x0 + DATAHLD phase duration = 1 HCLK clock cycle (default) + 0x0 + + + B_0x1 + DATAHLD phase duration = 2 HCLK clock cycle + 0x1 + + + B_0x2 + DATAHLD phase duration = 3 HCLK clock cycle + 0x2 + + + B_0x3 + DATAHLD phase duration = 4 HCLK clock cycle + 0x3 + + + + + + + FMC_BWTR2 + FMC_BWTR2 + SRAM/NOR-flash write timing registers 2 + 0x10C + 0x20 + read-write + 0x0FFFFFFF + 0xFFFFFFFF + + + ADDSET + Address setup phase duration. + 0 + 4 + read-write + + + B_0x0 + ADDSET phase duration = 0 HCLK clock cycle + 0x0 + + + B_0xF + ADDSET phase duration = 15 HCLK clock cycles (default value after reset) + 0xF + + + + + ADDHLD + Address-hold phase duration. + 4 + 4 + read-write + + + B_0x1 + ADDHLD phase duration = 1 HCLK clock cycle + 0x1 + + + B_0x2 + ADDHLD phase duration = 2 HCLK clock cycle + 0x2 + + + B_0xF + ADDHLD phase duration = 15 HCLK clock cycles (default value after reset) + 0xF + + + + + DATAST + Data-phase duration. + 8 + 8 + read-write + + + B_0x1 + DATAST phase duration = 1 HCLK clock cycles + 0x1 + + + B_0x2 + DATAST phase duration = 2 HCLK clock cycles + 0x2 + + + B_0xFF + DATAST phase duration = 255 HCLK clock cycles (default value after reset) + 0xFF + + + + + BUSTURN + Bus turnaround phase duration + + 16 + 4 + read-write + + + B_0x0 + BUSTURN phase duration = 1 HCLK clock cycle added + 0x0 + + + B_0xF + BUSTURN phase duration = 16 x HCLK clock cycles added (default value after reset) + 0xF + + + + + ACCMOD + Access mode. + 28 + 2 + read-write + + + B_0x0 + Access mode A + 0x0 + + + B_0x1 + Access mode B + 0x1 + + + B_0x2 + Access mode C + 0x2 + + + B_0x3 + Access mode D + 0x3 + + + + + DATAHLD + Data hold phase duration + + 30 + 2 + read-write + + + B_0x0 + DATAHLD phase duration = 1 HCLK clock cycle (default) + 0x0 + + + B_0x1 + DATAHLD phase duration = 2 HCLK clock cycle + 0x1 + + + B_0x2 + DATAHLD phase duration = 3 HCLK clock cycle + 0x2 + + + B_0x3 + DATAHLD phase duration = 4 HCLK clock cycle + 0x3 + + + + + + + FMC_BWTR3 + FMC_BWTR3 + SRAM/NOR-flash write timing registers 3 + 0x114 + 0x20 + read-write + 0x0FFFFFFF + 0xFFFFFFFF + + + ADDSET + Address setup phase duration. + 0 + 4 + read-write + + + B_0x0 + ADDSET phase duration = 0 HCLK clock cycle + 0x0 + + + B_0xF + ADDSET phase duration = 15 HCLK clock cycles (default value after reset) + 0xF + + + + + ADDHLD + Address-hold phase duration. + 4 + 4 + read-write + + + B_0x1 + ADDHLD phase duration = 1 HCLK clock cycle + 0x1 + + + B_0x2 + ADDHLD phase duration = 2 HCLK clock cycle + 0x2 + + + B_0xF + ADDHLD phase duration = 15 HCLK clock cycles (default value after reset) + 0xF + + + + + DATAST + Data-phase duration. + 8 + 8 + read-write + + + B_0x1 + DATAST phase duration = 1 HCLK clock cycles + 0x1 + + + B_0x2 + DATAST phase duration = 2 HCLK clock cycles + 0x2 + + + B_0xFF + DATAST phase duration = 255 HCLK clock cycles (default value after reset) + 0xFF + + + + + BUSTURN + Bus turnaround phase duration + + 16 + 4 + read-write + + + B_0x0 + BUSTURN phase duration = 1 HCLK clock cycle added + 0x0 + + + B_0xF + BUSTURN phase duration = 16 x HCLK clock cycles added (default value after reset) + 0xF + + + + + ACCMOD + Access mode. + 28 + 2 + read-write + + + B_0x0 + Access mode A + 0x0 + + + B_0x1 + Access mode B + 0x1 + + + B_0x2 + Access mode C + 0x2 + + + B_0x3 + Access mode D + 0x3 + + + + + DATAHLD + Data hold phase duration + + 30 + 2 + read-write + + + B_0x0 + DATAHLD phase duration = 1 HCLK clock cycle (default) + 0x0 + + + B_0x1 + DATAHLD phase duration = 2 HCLK clock cycle + 0x1 + + + B_0x2 + DATAHLD phase duration = 3 HCLK clock cycle + 0x2 + + + B_0x3 + DATAHLD phase duration = 4 HCLK clock cycle + 0x3 + + + + + + + FMC_BWTR4 + FMC_BWTR4 + SRAM/NOR-flash write timing registers 4 + 0x11C + 0x20 + read-write + 0x0FFFFFFF + 0xFFFFFFFF + + + ADDSET + Address setup phase duration. + 0 + 4 + read-write + + + B_0x0 + ADDSET phase duration = 0 HCLK clock cycle + 0x0 + + + B_0xF + ADDSET phase duration = 15 HCLK clock cycles (default value after reset) + 0xF + + + + + ADDHLD + Address-hold phase duration. + 4 + 4 + read-write + + + B_0x1 + ADDHLD phase duration = 1 HCLK clock cycle + 0x1 + + + B_0x2 + ADDHLD phase duration = 2 HCLK clock cycle + 0x2 + + + B_0xF + ADDHLD phase duration = 15 HCLK clock cycles (default value after reset) + 0xF + + + + + DATAST + Data-phase duration. + 8 + 8 + read-write + + + B_0x1 + DATAST phase duration = 1 HCLK clock cycles + 0x1 + + + B_0x2 + DATAST phase duration = 2 HCLK clock cycles + 0x2 + + + B_0xFF + DATAST phase duration = 255 HCLK clock cycles (default value after reset) + 0xFF + + + + + BUSTURN + Bus turnaround phase duration + + 16 + 4 + read-write + + + B_0x0 + BUSTURN phase duration = 1 HCLK clock cycle added + 0x0 + + + B_0xF + BUSTURN phase duration = 16 x HCLK clock cycles added (default value after reset) + 0xF + + + + + ACCMOD + Access mode. + 28 + 2 + read-write + + + B_0x0 + Access mode A + 0x0 + + + B_0x1 + Access mode B + 0x1 + + + B_0x2 + Access mode C + 0x2 + + + B_0x3 + Access mode D + 0x3 + + + + + DATAHLD + Data hold phase duration + + 30 + 2 + read-write + + + B_0x0 + DATAHLD phase duration = 1 HCLK clock cycle (default) + 0x0 + + + B_0x1 + DATAHLD phase duration = 2 HCLK clock cycle + 0x1 + + + B_0x2 + DATAHLD phase duration = 3 HCLK clock cycle + 0x2 + + + B_0x3 + DATAHLD phase duration = 4 HCLK clock cycle + 0x3 + + + + + + + FMC_SDCR1 + FMC_SDCR1 + SDRAM control registers 1,2 + 0x140 + 0x20 + read-write + 0x000002D0 + 0xFFFFFFFF + + + NC + Number of column address bits + + 0 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 9 bits + 0x1 + + + B_0x2 + 10 bits + 0x2 + + + B_0x3 + 11 bits. + 0x3 + + + + + NR + Number of row address bits + + 2 + 2 + read-write + + + B_0x0 + 11 bit + 0x0 + + + B_0x1 + 12 bits + 0x1 + + + B_0x2 + 13 bits + 0x2 + + + + + MWID + Memory data bus width. + 4 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + + + NB + Number of internal banks + + 6 + 1 + read-write + + + B_0x0 + Two internal Banks + 0x0 + + + B_0x1 + Four internal Banks + 0x1 + + + + + CAS + CAS Latency + + 7 + 2 + read-write + + + B_0x1 + 1 cycle + 0x1 + + + B_0x2 + 2 cycles + 0x2 + + + B_0x3 + 3 cycles + 0x3 + + + + + WP + Write protection + + 9 + 1 + read-write + + + B_0x0 + Write accesses allowed + 0x0 + + + B_0x1 + Write accesses ignored + 0x1 + + + + + SDCLK + SDRAM clock configuration + + 10 + 2 + read-write + + + B_0x0 + SDCLK clock disabled + 0x0 + + + B_0x1 + SDCLK period = 1x HCLK periods + 0x1 + + + B_0x2 + SDCLK period = 2 x HCLK periods + 0x2 + + + B_0x3 + SDCLK period = 3 x HCLK periods + 0x3 + + + + + RBURST + Burst read + + 12 + 1 + read-write + + + B_0x0 + single read requests are not managed as bursts + 0x0 + + + B_0x1 + single read requests are always managed as bursts + 0x1 + + + + + RPIPE + Read pipe + + 13 + 2 + read-write + + + B_0x0 + No clock cycle delay + 0x0 + + + B_0x1 + One clock cycle delay + 0x1 + + + B_0x2 + Two clock cycle delay + 0x2 + + + + + + + FMC_SDCR2 + FMC_SDCR2 + SDRAM control registers 1,2 + 0x144 + 0x20 + read-write + 0x000002D0 + 0xFFFFFFFF + + + NC + Number of column address bits + + 0 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 9 bits + 0x1 + + + B_0x2 + 10 bits + 0x2 + + + B_0x3 + 11 bits. + 0x3 + + + + + NR + Number of row address bits + + 2 + 2 + read-write + + + B_0x0 + 11 bit + 0x0 + + + B_0x1 + 12 bits + 0x1 + + + B_0x2 + 13 bits + 0x2 + + + + + MWID + Memory data bus width. + 4 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + + + NB + Number of internal banks + + 6 + 1 + read-write + + + B_0x0 + Two internal Banks + 0x0 + + + B_0x1 + Four internal Banks + 0x1 + + + + + CAS + CAS Latency + + 7 + 2 + read-write + + + B_0x1 + 1 cycle + 0x1 + + + B_0x2 + 2 cycles + 0x2 + + + B_0x3 + 3 cycles + 0x3 + + + + + WP + Write protection + + 9 + 1 + read-write + + + B_0x0 + Write accesses allowed + 0x0 + + + B_0x1 + Write accesses ignored + 0x1 + + + + + SDCLK + SDRAM clock configuration + + 10 + 2 + read-write + + + B_0x0 + SDCLK clock disabled + 0x0 + + + B_0x1 + SDCLK period = 1x HCLK periods + 0x1 + + + B_0x2 + SDCLK period = 2 x HCLK periods + 0x2 + + + B_0x3 + SDCLK period = 3 x HCLK periods + 0x3 + + + + + RBURST + Burst read + + 12 + 1 + read-write + + + B_0x0 + single read requests are not managed as bursts + 0x0 + + + B_0x1 + single read requests are always managed as bursts + 0x1 + + + + + RPIPE + Read pipe + + 13 + 2 + read-write + + + B_0x0 + No clock cycle delay + 0x0 + + + B_0x1 + One clock cycle delay + 0x1 + + + B_0x2 + Two clock cycle delay + 0x2 + + + + + + + FMC_SDTR1 + FMC_SDTR1 + SDRAM timing registers 1,2 + 0x148 + 0x20 + read-write + 0x0FFFFFFF + 0xFFFFFFFF + + + TMRD + Load Mode Register to Active + + 0 + 4 + read-write + + + B_0x0 + 1 cycle + 0x0 + + + B_0x1 + 2 cycles + 0x1 + + + B_0xF + 16 cycles + 0xF + + + + + TXSR + Exit Self-refresh delay + + 4 + 4 + read-write + + + B_0x0 + 1 cycle + 0x0 + + + B_0x1 + 2 cycles + 0x1 + + + B_0xF + 16 cycles + 0xF + + + + + TRAS + Self refresh time + + 8 + 4 + read-write + + + B_0x0 + 1 cycle + 0x0 + + + B_0x1 + 2 cycles + 0x1 + + + B_0xF + 16 cycles + 0xF + + + + + TRC + Row cycle delay + + 12 + 4 + read-write + + + B_0x0 + 1 cycle + 0x0 + + + B_0x1 + 2 cycles + 0x1 + + + B_0xF + 16 cycles + 0xF + + + + + TWR + Recovery delay + + 16 + 4 + read-write + + + B_0x0 + 1 cycle + 0x0 + + + B_0x1 + 2 cycles + 0x1 + + + B_0xF + 16 cycles + 0xF + + + + + TRP + Row precharge delay + + 20 + 4 + read-write + + + B_0x0 + 1 cycle + 0x0 + + + B_0x1 + 2 cycles + 0x1 + + + B_0xF + 16 cycles + 0xF + + + + + TRCD + Row to column delay + + 24 + 4 + read-write + + + B_0x0 + 1 cycle. + 0x0 + + + B_0x1 + 2 cycles + 0x1 + + + B_0xF + 16 cycles + 0xF + + + + + + + FMC_SDTR2 + FMC_SDTR2 + SDRAM timing registers 1,2 + 0x14C + 0x20 + read-write + 0x0FFFFFFF + 0xFFFFFFFF + + + TMRD + Load Mode Register to Active + + 0 + 4 + read-write + + + B_0x0 + 1 cycle + 0x0 + + + B_0x1 + 2 cycles + 0x1 + + + B_0xF + 16 cycles + 0xF + + + + + TXSR + Exit Self-refresh delay + + 4 + 4 + read-write + + + B_0x0 + 1 cycle + 0x0 + + + B_0x1 + 2 cycles + 0x1 + + + B_0xF + 16 cycles + 0xF + + + + + TRAS + Self refresh time + + 8 + 4 + read-write + + + B_0x0 + 1 cycle + 0x0 + + + B_0x1 + 2 cycles + 0x1 + + + B_0xF + 16 cycles + 0xF + + + + + TRC + Row cycle delay + + 12 + 4 + read-write + + + B_0x0 + 1 cycle + 0x0 + + + B_0x1 + 2 cycles + 0x1 + + + B_0xF + 16 cycles + 0xF + + + + + TWR + Recovery delay + + 16 + 4 + read-write + + + B_0x0 + 1 cycle + 0x0 + + + B_0x1 + 2 cycles + 0x1 + + + B_0xF + 16 cycles + 0xF + + + + + TRP + Row precharge delay + + 20 + 4 + read-write + + + B_0x0 + 1 cycle + 0x0 + + + B_0x1 + 2 cycles + 0x1 + + + B_0xF + 16 cycles + 0xF + + + + + TRCD + Row to column delay + + 24 + 4 + read-write + + + B_0x0 + 1 cycle. + 0x0 + + + B_0x1 + 2 cycles + 0x1 + + + B_0xF + 16 cycles + 0xF + + + + + + + FMC_SDCMR + FMC_SDCMR + SDRAM Command Mode register + 0x150 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + MODE + Command mode + + 0 + 3 + read-write + + + B_0x0 + Normal Mode + 0x0 + + + B_0x1 + Clock Configuration Enable + 0x1 + + + B_0x2 + PALL (All Bank Precharge) command + 0x2 + + + B_0x3 + Auto-refresh command + 0x3 + + + B_0x4 + Load Mode Register + 0x4 + + + B_0x5 + Self-refresh command + 0x5 + + + B_0x6 + Power-down command + 0x6 + + + + + CTB2 + Command Target Bank 2 + + 3 + 1 + read-write + + + B_0x0 + Command not issued to SDRAM Bank 2 + 0x0 + + + B_0x1 + Command issued to SDRAM Bank 2 + 0x1 + + + + + CTB1 + Command Target Bank 1 + + 4 + 1 + read-write + + + B_0x0 + Command not issued to SDRAM Bank 1 + 0x0 + + + B_0x1 + Command issued to SDRAM Bank 1 + 0x1 + + + + + NRFS + Number of Auto-refresh + + 5 + 4 + read-write + + + B_0x0 + 1 Auto-refresh cycle + 0x0 + + + B_0x1 + 2 Auto-refresh cycles + 0x1 + + + B_0xE + 15 Auto-refresh cycles + 0xE + + + B_0xF + 16 Auto-refresh cycles + 0xF + + + + + MRD + Mode Register definition + + 9 + 13 + read-write + + + + + FMC_SDRTR + FMC_SDRTR + SDRAM refresh timer register + 0x154 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CRE + Clear Refresh error flag + + 0 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + Refresh Error flag is cleared + 0x1 + + + + + COUNT + Refresh Timer Count + + 1 + 13 + read-write + + + REIE + RES Interrupt Enable + 14 + 1 + read-write + + + B_0x0 + Interrupt is disabled + 0x0 + + + B_0x1 + An Interrupt is generated if RE = 1 + 0x1 + + + + + + + FMC_SDSR + FMC_SDSR + SDRAM status register + 0x158 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RE + Refresh error flag + + 0 + 1 + read-only + + + B_0x0 + No refresh error has been detected + 0x0 + + + B_0x1 + A refresh error has been detected + 0x1 + + + + + MODES1 + Status Mode for Bank 1 + + 1 + 2 + read-only + + + B_0x0 + Normal Mode + 0x0 + + + B_0x1 + Self-refresh mode + 0x1 + + + B_0x2 + Power-down mode + 0x2 + + + + + MODES2 + Status Mode for Bank 2 + + 3 + 2 + read-only + + + B_0x0 + Normal Mode + 0x0 + + + B_0x1 + Self-refresh mode + 0x1 + + + B_0x2 + Power-down mode + 0x2 + + + + + BUSY + Busy status + + 5 + 1 + read-only + + + B_0x0 + SDRAM Controller is ready to accept a new request + 0x0 + + + + + + + + + FMC_S + 0X57000400 + + + GPDMA + GPDMA register block + GPDMA + 0x40020000 + + 0x0 + 0x1000 + registers + + + GPDMA1_CH7 + GPDMA1 channel7 global interrupt + 34 + + + GPDMA1_CH6 + GPDMA1 channel6 global interrupt + 33 + + + GPDMA1_CH5 + GPDMA1 channel5 global interrupt + 32 + + + GPDMA1_CH4 + GPDMA1 channel4 global interrupt + 31 + + + GPDMA1_CH3 + GPDMA1 channel3 global interrupt + 30 + + + GPDMA1_CH2 + GPDMA1 channel2 global interrupt + 29 + + + GPDMA1_CH1 + GPDMA1 channel1 global interrupt + 28 + + + GPDMA1_CH0 + GPDMA1 channel0 global interrupt + 27 + + + + GPDMA_SECCFGR + GPDMA_SECCFGR + GPDMA secure configuration register + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SEC0 + secure state of channel x + 0 + 1 + read-write + + + B_0x0 + nonsecure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + SEC1 + secure state of channel x + 1 + 1 + read-write + + + B_0x0 + nonsecure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + SEC2 + secure state of channel x + 2 + 1 + read-write + + + B_0x0 + nonsecure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + SEC3 + secure state of channel x + 3 + 1 + read-write + + + B_0x0 + nonsecure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + SEC4 + secure state of channel x + 4 + 1 + read-write + + + B_0x0 + nonsecure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + SEC5 + secure state of channel x + 5 + 1 + read-write + + + B_0x0 + nonsecure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + SEC6 + secure state of channel x + 6 + 1 + read-write + + + B_0x0 + nonsecure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + SEC7 + secure state of channel x + 7 + 1 + read-write + + + B_0x0 + nonsecure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + + + GPDMA_PRIVCFGR + GPDMA_PRIVCFGR + GPDMA privileged configuration register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRIV0 + privileged state of channel x + 0 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + PRIV1 + privileged state of channel x + 1 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + PRIV2 + privileged state of channel x + 2 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + PRIV3 + privileged state of channel x + 3 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + PRIV4 + privileged state of channel x + 4 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + PRIV5 + privileged state of channel x + 5 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + PRIV6 + privileged state of channel x + 6 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + PRIV7 + privileged state of channel x + 7 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + + + GPDMA_RCFGLOCKR + GPDMA_RCFGLOCKR + GPDMA configuration lock register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LOCK0 + lock the configuration of GPDMA_SECCFGR. + 0 + 1 + read-write + + + B_0x0 + secure privilege configuration of the channel x is writable. + 0x0 + + + B_0x1 + secure privilege configuration of the channel x is not writable. + 0x1 + + + + + LOCK1 + lock the configuration of GPDMA_SECCFGR. + 1 + 1 + read-write + + + B_0x0 + secure privilege configuration of the channel x is writable. + 0x0 + + + B_0x1 + secure privilege configuration of the channel x is not writable. + 0x1 + + + + + LOCK2 + lock the configuration of GPDMA_SECCFGR. + 2 + 1 + read-write + + + B_0x0 + secure privilege configuration of the channel x is writable. + 0x0 + + + B_0x1 + secure privilege configuration of the channel x is not writable. + 0x1 + + + + + LOCK3 + lock the configuration of GPDMA_SECCFGR. + 3 + 1 + read-write + + + B_0x0 + secure privilege configuration of the channel x is writable. + 0x0 + + + B_0x1 + secure privilege configuration of the channel x is not writable. + 0x1 + + + + + LOCK4 + lock the configuration of GPDMA_SECCFGR. + 4 + 1 + read-write + + + B_0x0 + secure privilege configuration of the channel x is writable. + 0x0 + + + B_0x1 + secure privilege configuration of the channel x is not writable. + 0x1 + + + + + LOCK5 + lock the configuration of GPDMA_SECCFGR. + 5 + 1 + read-write + + + B_0x0 + secure privilege configuration of the channel x is writable. + 0x0 + + + B_0x1 + secure privilege configuration of the channel x is not writable. + 0x1 + + + + + LOCK6 + lock the configuration of GPDMA_SECCFGR. + 6 + 1 + read-write + + + B_0x0 + secure privilege configuration of the channel x is writable. + 0x0 + + + B_0x1 + secure privilege configuration of the channel x is not writable. + 0x1 + + + + + LOCK7 + lock the configuration of GPDMA_SECCFGR. + 7 + 1 + read-write + + + B_0x0 + secure privilege configuration of the channel x is writable. + 0x0 + + + B_0x1 + secure privilege configuration of the channel x is not writable. + 0x1 + + + + + + + GPDMA_MISR + GPDMA_MISR + GPDMA nonsecure masked interrupt status register + 0x0C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + MIS0 + masked interrupt status of channel x + 0 + 1 + read-only + + + B_0x0 + no interrupt occurred on channel x + 0x0 + + + B_0x1 + an interrupt occurred on channel x + 0x1 + + + + + MIS1 + masked interrupt status of channel x + 1 + 1 + read-only + + + B_0x0 + no interrupt occurred on channel x + 0x0 + + + B_0x1 + an interrupt occurred on channel x + 0x1 + + + + + MIS2 + masked interrupt status of channel x + 2 + 1 + read-only + + + B_0x0 + no interrupt occurred on channel x + 0x0 + + + B_0x1 + an interrupt occurred on channel x + 0x1 + + + + + MIS3 + masked interrupt status of channel x + 3 + 1 + read-only + + + B_0x0 + no interrupt occurred on channel x + 0x0 + + + B_0x1 + an interrupt occurred on channel x + 0x1 + + + + + MIS4 + masked interrupt status of channel x + 4 + 1 + read-only + + + B_0x0 + no interrupt occurred on channel x + 0x0 + + + B_0x1 + an interrupt occurred on channel x + 0x1 + + + + + MIS5 + masked interrupt status of channel x + 5 + 1 + read-only + + + B_0x0 + no interrupt occurred on channel x + 0x0 + + + B_0x1 + an interrupt occurred on channel x + 0x1 + + + + + MIS6 + masked interrupt status of channel x + 6 + 1 + read-only + + + B_0x0 + no interrupt occurred on channel x + 0x0 + + + B_0x1 + an interrupt occurred on channel x + 0x1 + + + + + MIS7 + masked interrupt status of channel x + 7 + 1 + read-only + + + B_0x0 + no interrupt occurred on channel x + 0x0 + + + B_0x1 + an interrupt occurred on channel x + 0x1 + + + + + + + GPDMA_SMISR + GPDMA_SMISR + GPDMA secure masked interrupt status register + 0x10 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + MIS0 + masked interrupt status of the secure channel x + 0 + 1 + read-only + + + B_0x0 + no interrupt occurred on the secure channel x + 0x0 + + + B_0x1 + an interrupt occurred on the secure channel x + 0x1 + + + + + MIS1 + masked interrupt status of the secure channel x + 1 + 1 + read-only + + + B_0x0 + no interrupt occurred on the secure channel x + 0x0 + + + B_0x1 + an interrupt occurred on the secure channel x + 0x1 + + + + + MIS2 + masked interrupt status of the secure channel x + 2 + 1 + read-only + + + B_0x0 + no interrupt occurred on the secure channel x + 0x0 + + + B_0x1 + an interrupt occurred on the secure channel x + 0x1 + + + + + MIS3 + masked interrupt status of the secure channel x + 3 + 1 + read-only + + + B_0x0 + no interrupt occurred on the secure channel x + 0x0 + + + B_0x1 + an interrupt occurred on the secure channel x + 0x1 + + + + + MIS4 + masked interrupt status of the secure channel x + 4 + 1 + read-only + + + B_0x0 + no interrupt occurred on the secure channel x + 0x0 + + + B_0x1 + an interrupt occurred on the secure channel x + 0x1 + + + + + MIS5 + masked interrupt status of the secure channel x + 5 + 1 + read-only + + + B_0x0 + no interrupt occurred on the secure channel x + 0x0 + + + B_0x1 + an interrupt occurred on the secure channel x + 0x1 + + + + + MIS6 + masked interrupt status of the secure channel x + 6 + 1 + read-only + + + B_0x0 + no interrupt occurred on the secure channel x + 0x0 + + + B_0x1 + an interrupt occurred on the secure channel x + 0x1 + + + + + MIS7 + masked interrupt status of the secure channel x + 7 + 1 + read-only + + + B_0x0 + no interrupt occurred on the secure channel x + 0x0 + + + B_0x1 + an interrupt occurred on the secure channel x + 0x1 + + + + + + + GPDMA_C0LBAR + GPDMA_C0LBAR + GPDMA channel 0 linked-list base address register + 0x50 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LBA + linked-list base address of GPDMA channel x + 16 + 16 + read-write + + + + + GPDMA_C0FCR + GPDMA_C0FCR + GPDMA channel 0 flag clear register + 0x5C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + TCF + transfer complete flag clear + 8 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding TCF flag cleared + 0x1 + + + + + HTF + half transfer flag clear + 9 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding HTF flag cleared + 0x1 + + + + + DTEF + data transfer error flag clear + 10 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding DTEF flag cleared + 0x1 + + + + + ULEF + update link transfer error flag clear + 11 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding ULEF flag cleared + 0x1 + + + + + USEF + user setting error flag clear + 12 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding USEF flag cleared + 0x1 + + + + + SUSPF + completed suspension flag clear + 13 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding SUSPF flag cleared + 0x1 + + + + + TOF + trigger overrun flag clear + 14 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding TOF flag cleared + 0x1 + + + + + + + GPDMA_C0SR + GPDMA_C0SR + GPDMA channel 0 status register + 0x60 + 0x20 + read-only + 0x00000001 + 0xFFFFFFFF + + + IDLEF + idle flag + + 0 + 1 + read-only + + + B_0x0 + channel not in idle state + 0x0 + + + B_0x1 + channel in idle state + 0x1 + + + + + TCF + transfer complete flag + + 8 + 1 + read-only + + + B_0x0 + no transfer complete event + 0x0 + + + B_0x1 + a transfer complete event occurred + 0x1 + + + + + HTF + half transfer flag + + 9 + 1 + read-only + + + B_0x0 + no half transfer event + 0x0 + + + B_0x1 + a half transfer event occurred + 0x1 + + + + + DTEF + data transfer error flag + 10 + 1 + read-only + + + B_0x0 + no data transfer error event + 0x0 + + + B_0x1 + a master bus error event occurred on a data transfer + 0x1 + + + + + ULEF + update link transfer error flag + 11 + 1 + read-only + + + B_0x0 + no update link transfer error event + 0x0 + + + B_0x1 + a master bus error event occurred while updating a linked-list register from memory + 0x1 + + + + + USEF + user setting error flag + 12 + 1 + read-only + + + B_0x0 + no user setting error event + 0x0 + + + B_0x1 + a user setting error event occurred + 0x1 + + + + + SUSPF + completed suspension flag + 13 + 1 + read-only + + + B_0x0 + no completed suspension event + 0x0 + + + B_0x1 + a completed suspension event occurred + 0x1 + + + + + TOF + trigger overrun flag + 14 + 1 + read-only + + + B_0x0 + no trigger overrun event + 0x0 + + + B_0x1 + a trigger overrun event occurred + 0x1 + + + + + FIFOL + monitored FIFO level + + 16 + 8 + read-only + + + + + GPDMA_C0CR + GPDMA_C0CR + GPDMA channel 0 control register + 0x64 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EN + enable + + 0 + 1 + read-write + + + B_0x0 + write: ignored, read: channel disabled + 0x0 + + + B_0x1 + write: enable channel, read: channel enabled + 0x1 + + + + + RESET + reset + + 1 + 1 + write-only + + + B_0x0 + no channel reset + 0x0 + + + B_0x1 + channel reset + 0x1 + + + + + SUSP + suspend + + 2 + 1 + read-write + + + B_0x0 + write: resume channel, read: channel not suspended + 0x0 + + + B_0x1 + write: suspend channel, read: channel suspended. + 0x1 + + + + + TCIE + transfer complete interrupt enable + 8 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + HTIE + half transfer complete interrupt enable + 9 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + DTEIE + data transfer error interrupt enable + 10 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + ULEIE + update link transfer error interrupt enable + 11 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + USEIE + user setting error interrupt enable + 12 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SUSPIE + completed suspension interrupt enable + 13 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TOIE + trigger overrun interrupt enable + 14 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + LSM + Link step mode + + 16 + 1 + read-write + + + B_0x0 + channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). + 0x0 + + + B_0x1 + channel executed once for the current LLI + 0x1 + + + + + LAP + linked-list allocated port + + 17 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + PRIO + priority level of the channel x GPDMA transfer versus others + + 22 + 2 + read-write + + + B_0x0 + low priority, low weight + 0x0 + + + B_0x1 + low priority, mid weight + 0x1 + + + B_0x2 + low priority, high weight + 0x2 + + + B_0x3 + high priority + 0x3 + + + + + + + GPDMA_C0TR1 + GPDMA_C0TR1 + GPDMA channel 0 transfer register 1 + 0x90 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SDW_LOG2 + binary logarithm of the source data width of a burst in bytes + + 0 + 2 + read-write + + + B_0x0 + byte + 0x0 + + + B_0x1 + half-word (2 bytes) + 0x1 + + + B_0x2 + word (4 bytes) + 0x2 + + + B_0x3 + user setting error reported and no transfer issued + 0x3 + + + + + SINC + source incrementing burst + + 3 + 1 + read-write + + + B_0x0 + fixed burst + 0x0 + + + B_0x1 + contiguously incremented burst + 0x1 + + + + + SBL_1 + source burst length minus 1, between 0 and 63 + + 4 + 6 + read-write + + + PAM + padding/alignment mode + + 11 + 2 + read-write + + + B_0x0_PAM_1 + source data is transferred as right aligned, padded with 0s up to the destination data width + 0x0 + + + B_0x1_PAM_1 + source data is transferred as right aligned, sign extended up to the destination data width + 0x1 + + + B_0x2_PAM_1 + successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer + 0x2 + + + B_0x3_PAM_1 + successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer + 0x3 + + + + + SBX + source byte exchange within the unaligned half-word of each source word + + 13 + 1 + read-write + + + B_0x0 + no byte-based exchange within the unaligned half-word of each source word + 0x0 + + + B_0x1 + the two consecutive bytes within the unaligned half-word of each source word are exchanged. + 0x1 + + + + + SAP + source allocated port + + 14 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + SSEC + security attribute of the GPDMA transfer from the source + + 15 + 1 + read-write + + + B_0x0 + GPDMA transfer nonsecure + 0x0 + + + B_0x1 + GPDMA transfer secure + 0x1 + + + + + DDW_LOG2 + binary logarithm of the destination data width of a burst, in bytes + + 16 + 2 + read-write + + + B_0x0 + byte + 0x0 + + + B_0x1 + half-word (2 bytes) + 0x1 + + + B_0x2 + word (4 bytes) + 0x2 + + + B_0x3 + user setting error reported and no transfer issued + 0x3 + + + + + DINC + destination incrementing burst + + 19 + 1 + read-write + + + B_0x0 + fixed burst + 0x0 + + + B_0x1 + contiguously incremented burst + 0x1 + + + + + DBL_1 + destination burst length minus 1, between 0 and 63 + + 20 + 6 + read-write + + + DBX + destination byte exchange + + 26 + 1 + read-write + + + B_0x0 + no byte-based exchange within half-word + 0x0 + + + B_0x1 + the two consecutive (post PAM) bytes are exchanged in each destination half-word. + 0x1 + + + + + DHX + destination half-word exchange + + 27 + 1 + read-write + + + B_0x0 + no halfword-based exchanged within word + 0x0 + + + B_0x1 + the two consecutive (post PAM) half-words are exchanged in each destination word. + 0x1 + + + + + DAP + destination allocated port + + 30 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + DSEC + security attribute of the GPDMA transfer to the destination + + 31 + 1 + read-write + + + B_0x0 + GPDMA transfer nonsecure + 0x0 + + + B_0x1 + GPDMA transfer secure + 0x1 + + + + + + + GPDMA_C0TR2 + GPDMA_C0TR2 + GPDMA channel 0 transfer register 2 + 0x94 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + REQSEL + GPDMA hardware request selection + + 0 + 8 + read-write + + + SWREQ + software request + + 9 + 1 + read-write + + + B_0x0 + no software request. + 0x0 + + + B_0x1 + software request for a memory-to-memory transfer. + 0x1 + + + + + DREQ + destination hardware request + + 10 + 1 + read-write + + + B_0x0 + selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port) + 0x0 + + + B_0x1 + selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port) + 0x1 + + + + + BREQ + Block hardware request + + 11 + 1 + read-write + + + B_0x0 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level. + 0x0 + + + B_0x1 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 16. + 0x1 + + + + + PFREQ + Hardware request in peripheral flow control mode + + 12 + 1 + read-write + + + B_0x0 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. + 0x0 + + + B_0x1 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. + 0x1 + + + + + TRIGM + trigger mode + + 14 + 2 + read-write + + + B_0x0 + at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x (x = 6 to 7), for each block if a 2D/repeated block is configured with GPDMA_CxBR1. + 0x0 + + + B_0x1 + channel x (x = 0 to 5), same as 00; channel x (x = 6 to 7), at 2D/repeated block level. + 0x1 + + + B_0x2 + at link level: a LLI link transfer is conditioned by one hit trigger. + 0x2 + + + B_0x3 + at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. + 0x3 + + + + + TRIGSEL + trigger event input selection + + 16 + 6 + read-write + + + TRIGPOL + trigger event polarity + + 24 + 2 + read-write + + + B_0x0 + no trigger (masked trigger event) + 0x0 + + + B_0x1 + trigger on the rising edge + 0x1 + + + B_0x2 + trigger on the falling edge + 0x2 + + + B_0x3 + same as 00 + 0x3 + + + + + TCEM + transfer complete event mode + + 30 + 2 + read-write + + + B_0x0 + at block level (when GPDMA_CxBR1. + 0x0 + + + B_0x1 + channel x (x = 0 to 5), same as 00, channel x (x = 6 to 7), at 2D/repeated block level (when GPDMA_CxBR1. + 0x1 + + + B_0x2 + at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. + 0x2 + + + B_0x3 + at channel level: the complete transfer event is generated at the end of the last LLI transfer. + 0x3 + + + + + + + GPDMA_C0BR1 + GPDMA_C0BR1 + GPDMA channel 0 block register 1 + 0x98 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BNDT + block number of data bytes to transfer from the source + + 0 + 16 + read-write + + + + + GPDMA_C0SAR + GPDMA_C0SAR + GPDMA channel 0 source address register + 0x9C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SA + source address + + 0 + 32 + read-write + + + + + GPDMA_C0DAR + GPDMA_C0DAR + GPDMA channel 0 destination address register + 0xA0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DA + destination address + + 0 + 32 + read-write + + + + + GPDMA_C0LLR + GPDMA_C0LLR + GPDMA channel 0 linked-list address register + 0xCC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LA + pointer (16-bit low-significant address) to the next linked-list data structure + + 2 + 14 + read-write + + + ULL + Update GPDMA_CxLLR register from memory + + 16 + 1 + read-write + + + B_0x0 + no GPDMA_CxLLR update + 0x0 + + + B_0x1 + GPDMA_CxLLR update + 0x1 + + + + + UDA + Update GPDMA_CxDAR register from memory + + 27 + 1 + read-write + + + B_0x0 + no GPDMA_CxDAR update + 0x0 + + + B_0x1 + GPDMA_CxDAR update + 0x1 + + + + + USA + update GPDMA_CxSAR from memory + + 28 + 1 + read-write + + + B_0x0 + no GPDMA_CxSAR update + 0x0 + + + B_0x1 + GPDMA_CxSAR update + 0x1 + + + + + UB1 + Update GPDMA_CxBR1 from memory + + 29 + 1 + read-write + + + B_0x0 + no GPDMA_CxBR1 update from memory (GPDMA_CxBR1. + 0x0 + + + B_0x1 + GPDMA_CxBR1 update + 0x1 + + + + + UT2 + Update GPDMA_CxTR2 from memory + + 30 + 1 + read-write + + + B_0x0 + no GPDMA_CxTR2 update + 0x0 + + + B_0x1 + GPDMA_CxTR2 update + 0x1 + + + + + UT1 + Update GPDMA_CxTR1 from memory + + 31 + 1 + read-write + + + B_0x0 + no GPDMA_CxTR1 update + 0x0 + + + B_0x1 + GPDMA_CxTR1 update + 0x1 + + + + + + + GPDMA_C1LBAR + GPDMA_C1LBAR + GPDMA channel 1 linked-list base address register + 0xD0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LBA + linked-list base address of GPDMA channel x + 16 + 16 + read-write + + + + + GPDMA_C1FCR + GPDMA_C1FCR + GPDMA channel 1 flag clear register + 0xDC + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + TCF + transfer complete flag clear + 8 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding TCF flag cleared + 0x1 + + + + + HTF + half transfer flag clear + 9 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding HTF flag cleared + 0x1 + + + + + DTEF + data transfer error flag clear + 10 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding DTEF flag cleared + 0x1 + + + + + ULEF + update link transfer error flag clear + 11 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding ULEF flag cleared + 0x1 + + + + + USEF + user setting error flag clear + 12 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding USEF flag cleared + 0x1 + + + + + SUSPF + completed suspension flag clear + 13 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding SUSPF flag cleared + 0x1 + + + + + TOF + trigger overrun flag clear + 14 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding TOF flag cleared + 0x1 + + + + + + + GPDMA_C1SR + GPDMA_C1SR + GPDMA channel 1 status register + 0xE0 + 0x20 + read-only + 0x00000001 + 0xFFFFFFFF + + + IDLEF + idle flag + + 0 + 1 + read-only + + + B_0x0 + channel not in idle state + 0x0 + + + B_0x1 + channel in idle state + 0x1 + + + + + TCF + transfer complete flag + + 8 + 1 + read-only + + + B_0x0 + no transfer complete event + 0x0 + + + B_0x1 + a transfer complete event occurred + 0x1 + + + + + HTF + half transfer flag + + 9 + 1 + read-only + + + B_0x0 + no half transfer event + 0x0 + + + B_0x1 + a half transfer event occurred + 0x1 + + + + + DTEF + data transfer error flag + 10 + 1 + read-only + + + B_0x0 + no data transfer error event + 0x0 + + + B_0x1 + a master bus error event occurred on a data transfer + 0x1 + + + + + ULEF + update link transfer error flag + 11 + 1 + read-only + + + B_0x0 + no update link transfer error event + 0x0 + + + B_0x1 + a master bus error event occurred while updating a linked-list register from memory + 0x1 + + + + + USEF + user setting error flag + 12 + 1 + read-only + + + B_0x0 + no user setting error event + 0x0 + + + B_0x1 + a user setting error event occurred + 0x1 + + + + + SUSPF + completed suspension flag + 13 + 1 + read-only + + + B_0x0 + no completed suspension event + 0x0 + + + B_0x1 + a completed suspension event occurred + 0x1 + + + + + TOF + trigger overrun flag + 14 + 1 + read-only + + + B_0x0 + no trigger overrun event + 0x0 + + + B_0x1 + a trigger overrun event occurred + 0x1 + + + + + FIFOL + monitored FIFO level + + 16 + 8 + read-only + + + + + GPDMA_C1CR + GPDMA_C1CR + GPDMA channel 1 control register + 0xE4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EN + enable + + 0 + 1 + read-write + + + B_0x0 + write: ignored, read: channel disabled + 0x0 + + + B_0x1 + write: enable channel, read: channel enabled + 0x1 + + + + + RESET + reset + + 1 + 1 + write-only + + + B_0x0 + no channel reset + 0x0 + + + B_0x1 + channel reset + 0x1 + + + + + SUSP + suspend + + 2 + 1 + read-write + + + B_0x0 + write: resume channel, read: channel not suspended + 0x0 + + + B_0x1 + write: suspend channel, read: channel suspended. + 0x1 + + + + + TCIE + transfer complete interrupt enable + 8 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + HTIE + half transfer complete interrupt enable + 9 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + DTEIE + data transfer error interrupt enable + 10 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + ULEIE + update link transfer error interrupt enable + 11 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + USEIE + user setting error interrupt enable + 12 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SUSPIE + completed suspension interrupt enable + 13 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TOIE + trigger overrun interrupt enable + 14 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + LSM + Link step mode + + 16 + 1 + read-write + + + B_0x0 + channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). + 0x0 + + + B_0x1 + channel executed once for the current LLI + 0x1 + + + + + LAP + linked-list allocated port + + 17 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + PRIO + priority level of the channel x GPDMA transfer versus others + + 22 + 2 + read-write + + + B_0x0 + low priority, low weight + 0x0 + + + B_0x1 + low priority, mid weight + 0x1 + + + B_0x2 + low priority, high weight + 0x2 + + + B_0x3 + high priority + 0x3 + + + + + + + GPDMA_C1TR1 + GPDMA_C1TR1 + GPDMA channel 1 transfer register 1 + 0x110 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SDW_LOG2 + binary logarithm of the source data width of a burst in bytes + + 0 + 2 + read-write + + + B_0x0 + byte + 0x0 + + + B_0x1 + half-word (2 bytes) + 0x1 + + + B_0x2 + word (4 bytes) + 0x2 + + + B_0x3 + user setting error reported and no transfer issued + 0x3 + + + + + SINC + source incrementing burst + + 3 + 1 + read-write + + + B_0x0 + fixed burst + 0x0 + + + B_0x1 + contiguously incremented burst + 0x1 + + + + + SBL_1 + source burst length minus 1, between 0 and 63 + + 4 + 6 + read-write + + + PAM + padding/alignment mode + + 11 + 2 + read-write + + + B_0x0_PAM_1 + source data is transferred as right aligned, padded with 0s up to the destination data width + 0x0 + + + B_0x1_PAM_1 + source data is transferred as right aligned, sign extended up to the destination data width + 0x1 + + + B_0x2_PAM_1 + successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer + 0x2 + + + B_0x3_PAM_1 + successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer + 0x3 + + + + + SBX + source byte exchange within the unaligned half-word of each source word + + 13 + 1 + read-write + + + B_0x0 + no byte-based exchange within the unaligned half-word of each source word + 0x0 + + + B_0x1 + the two consecutive bytes within the unaligned half-word of each source word are exchanged. + 0x1 + + + + + SAP + source allocated port + + 14 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + SSEC + security attribute of the GPDMA transfer from the source + + 15 + 1 + read-write + + + B_0x0 + GPDMA transfer nonsecure + 0x0 + + + B_0x1 + GPDMA transfer secure + 0x1 + + + + + DDW_LOG2 + binary logarithm of the destination data width of a burst, in bytes + + 16 + 2 + read-write + + + B_0x0 + byte + 0x0 + + + B_0x1 + half-word (2 bytes) + 0x1 + + + B_0x2 + word (4 bytes) + 0x2 + + + B_0x3 + user setting error reported and no transfer issued + 0x3 + + + + + DINC + destination incrementing burst + + 19 + 1 + read-write + + + B_0x0 + fixed burst + 0x0 + + + B_0x1 + contiguously incremented burst + 0x1 + + + + + DBL_1 + destination burst length minus 1, between 0 and 63 + + 20 + 6 + read-write + + + DBX + destination byte exchange + + 26 + 1 + read-write + + + B_0x0 + no byte-based exchange within half-word + 0x0 + + + B_0x1 + the two consecutive (post PAM) bytes are exchanged in each destination half-word. + 0x1 + + + + + DHX + destination half-word exchange + + 27 + 1 + read-write + + + B_0x0 + no halfword-based exchanged within word + 0x0 + + + B_0x1 + the two consecutive (post PAM) half-words are exchanged in each destination word. + 0x1 + + + + + DAP + destination allocated port + + 30 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + DSEC + security attribute of the GPDMA transfer to the destination + + 31 + 1 + read-write + + + B_0x0 + GPDMA transfer nonsecure + 0x0 + + + B_0x1 + GPDMA transfer secure + 0x1 + + + + + + + GPDMA_C1TR2 + GPDMA_C1TR2 + GPDMA channel 1 transfer register 2 + 0x114 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + REQSEL + GPDMA hardware request selection + + 0 + 8 + read-write + + + SWREQ + software request + + 9 + 1 + read-write + + + B_0x0 + no software request. + 0x0 + + + B_0x1 + software request for a memory-to-memory transfer. + 0x1 + + + + + DREQ + destination hardware request + + 10 + 1 + read-write + + + B_0x0 + selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port) + 0x0 + + + B_0x1 + selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port) + 0x1 + + + + + BREQ + Block hardware request + + 11 + 1 + read-write + + + B_0x0 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level. + 0x0 + + + B_0x1 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 16. + 0x1 + + + + + PFREQ + Hardware request in peripheral flow control mode + + 12 + 1 + read-write + + + B_0x0 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. + 0x0 + + + B_0x1 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. + 0x1 + + + + + TRIGM + trigger mode + + 14 + 2 + read-write + + + B_0x0 + at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x (x = 6 to 7), for each block if a 2D/repeated block is configured with GPDMA_CxBR1. + 0x0 + + + B_0x1 + channel x (x = 0 to 5), same as 00; channel x (x = 6 to 7), at 2D/repeated block level. + 0x1 + + + B_0x2 + at link level: a LLI link transfer is conditioned by one hit trigger. + 0x2 + + + B_0x3 + at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. + 0x3 + + + + + TRIGSEL + trigger event input selection + + 16 + 6 + read-write + + + TRIGPOL + trigger event polarity + + 24 + 2 + read-write + + + B_0x0 + no trigger (masked trigger event) + 0x0 + + + B_0x1 + trigger on the rising edge + 0x1 + + + B_0x2 + trigger on the falling edge + 0x2 + + + B_0x3 + same as 00 + 0x3 + + + + + TCEM + transfer complete event mode + + 30 + 2 + read-write + + + B_0x0 + at block level (when GPDMA_CxBR1. + 0x0 + + + B_0x1 + channel x (x = 0 to 5), same as 00, channel x (x = 6 to 7), at 2D/repeated block level (when GPDMA_CxBR1. + 0x1 + + + B_0x2 + at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. + 0x2 + + + B_0x3 + at channel level: the complete transfer event is generated at the end of the last LLI transfer. + 0x3 + + + + + + + GPDMA_C1BR1 + GPDMA_C1BR1 + GPDMA channel 1 block register 1 + 0x118 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BNDT + block number of data bytes to transfer from the source + + 0 + 16 + read-write + + + + + GPDMA_C1SAR + GPDMA_C1SAR + GPDMA channel 1 source address register + 0x11C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SA + source address + + 0 + 32 + read-write + + + + + GPDMA_C1DAR + GPDMA_C1DAR + GPDMA channel 1 destination address register + 0x120 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DA + destination address + + 0 + 32 + read-write + + + + + GPDMA_C1LLR + GPDMA_C1LLR + GPDMA channel 1 linked-list address register + 0x14C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LA + pointer (16-bit low-significant address) to the next linked-list data structure + + 2 + 14 + read-write + + + ULL + Update GPDMA_CxLLR register from memory + + 16 + 1 + read-write + + + B_0x0 + no GPDMA_CxLLR update + 0x0 + + + B_0x1 + GPDMA_CxLLR update + 0x1 + + + + + UDA + Update GPDMA_CxDAR register from memory + + 27 + 1 + read-write + + + B_0x0 + no GPDMA_CxDAR update + 0x0 + + + B_0x1 + GPDMA_CxDAR update + 0x1 + + + + + USA + update GPDMA_CxSAR from memory + + 28 + 1 + read-write + + + B_0x0 + no GPDMA_CxSAR update + 0x0 + + + B_0x1 + GPDMA_CxSAR update + 0x1 + + + + + UB1 + Update GPDMA_CxBR1 from memory + + 29 + 1 + read-write + + + B_0x0 + no GPDMA_CxBR1 update from memory (GPDMA_CxBR1. + 0x0 + + + B_0x1 + GPDMA_CxBR1 update + 0x1 + + + + + UT2 + Update GPDMA_CxTR2 from memory + + 30 + 1 + read-write + + + B_0x0 + no GPDMA_CxTR2 update + 0x0 + + + B_0x1 + GPDMA_CxTR2 update + 0x1 + + + + + UT1 + Update GPDMA_CxTR1 from memory + + 31 + 1 + read-write + + + B_0x0 + no GPDMA_CxTR1 update + 0x0 + + + B_0x1 + GPDMA_CxTR1 update + 0x1 + + + + + + + GPDMA_C2LBAR + GPDMA_C2LBAR + GPDMA channel 2 linked-list base address register + 0x150 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LBA + linked-list base address of GPDMA channel x + 16 + 16 + read-write + + + + + GPDMA_C2FCR + GPDMA_C2FCR + GPDMA channel 2 flag clear register + 0x15C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + TCF + transfer complete flag clear + 8 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding TCF flag cleared + 0x1 + + + + + HTF + half transfer flag clear + 9 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding HTF flag cleared + 0x1 + + + + + DTEF + data transfer error flag clear + 10 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding DTEF flag cleared + 0x1 + + + + + ULEF + update link transfer error flag clear + 11 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding ULEF flag cleared + 0x1 + + + + + USEF + user setting error flag clear + 12 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding USEF flag cleared + 0x1 + + + + + SUSPF + completed suspension flag clear + 13 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding SUSPF flag cleared + 0x1 + + + + + TOF + trigger overrun flag clear + 14 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding TOF flag cleared + 0x1 + + + + + + + GPDMA_C2SR + GPDMA_C2SR + GPDMA channel 2 status register + 0x160 + 0x20 + read-only + 0x00000001 + 0xFFFFFFFF + + + IDLEF + idle flag + + 0 + 1 + read-only + + + B_0x0 + channel not in idle state + 0x0 + + + B_0x1 + channel in idle state + 0x1 + + + + + TCF + transfer complete flag + + 8 + 1 + read-only + + + B_0x0 + no transfer complete event + 0x0 + + + B_0x1 + a transfer complete event occurred + 0x1 + + + + + HTF + half transfer flag + + 9 + 1 + read-only + + + B_0x0 + no half transfer event + 0x0 + + + B_0x1 + a half transfer event occurred + 0x1 + + + + + DTEF + data transfer error flag + 10 + 1 + read-only + + + B_0x0 + no data transfer error event + 0x0 + + + B_0x1 + a master bus error event occurred on a data transfer + 0x1 + + + + + ULEF + update link transfer error flag + 11 + 1 + read-only + + + B_0x0 + no update link transfer error event + 0x0 + + + B_0x1 + a master bus error event occurred while updating a linked-list register from memory + 0x1 + + + + + USEF + user setting error flag + 12 + 1 + read-only + + + B_0x0 + no user setting error event + 0x0 + + + B_0x1 + a user setting error event occurred + 0x1 + + + + + SUSPF + completed suspension flag + 13 + 1 + read-only + + + B_0x0 + no completed suspension event + 0x0 + + + B_0x1 + a completed suspension event occurred + 0x1 + + + + + TOF + trigger overrun flag + 14 + 1 + read-only + + + B_0x0 + no trigger overrun event + 0x0 + + + B_0x1 + a trigger overrun event occurred + 0x1 + + + + + FIFOL + monitored FIFO level + + 16 + 8 + read-only + + + + + GPDMA_C2CR + GPDMA_C2CR + GPDMA channel 2 control register + 0x164 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EN + enable + + 0 + 1 + read-write + + + B_0x0 + write: ignored, read: channel disabled + 0x0 + + + B_0x1 + write: enable channel, read: channel enabled + 0x1 + + + + + RESET + reset + + 1 + 1 + write-only + + + B_0x0 + no channel reset + 0x0 + + + B_0x1 + channel reset + 0x1 + + + + + SUSP + suspend + + 2 + 1 + read-write + + + B_0x0 + write: resume channel, read: channel not suspended + 0x0 + + + B_0x1 + write: suspend channel, read: channel suspended. + 0x1 + + + + + TCIE + transfer complete interrupt enable + 8 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + HTIE + half transfer complete interrupt enable + 9 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + DTEIE + data transfer error interrupt enable + 10 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + ULEIE + update link transfer error interrupt enable + 11 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + USEIE + user setting error interrupt enable + 12 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SUSPIE + completed suspension interrupt enable + 13 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TOIE + trigger overrun interrupt enable + 14 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + LSM + Link step mode + + 16 + 1 + read-write + + + B_0x0 + channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). + 0x0 + + + B_0x1 + channel executed once for the current LLI + 0x1 + + + + + LAP + linked-list allocated port + + 17 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + PRIO + priority level of the channel x GPDMA transfer versus others + + 22 + 2 + read-write + + + B_0x0 + low priority, low weight + 0x0 + + + B_0x1 + low priority, mid weight + 0x1 + + + B_0x2 + low priority, high weight + 0x2 + + + B_0x3 + high priority + 0x3 + + + + + + + GPDMA_C2TR1 + GPDMA_C2TR1 + GPDMA channel 2 transfer register 1 + 0x190 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SDW_LOG2 + binary logarithm of the source data width of a burst in bytes + + 0 + 2 + read-write + + + B_0x0 + byte + 0x0 + + + B_0x1 + half-word (2 bytes) + 0x1 + + + B_0x2 + word (4 bytes) + 0x2 + + + B_0x3 + user setting error reported and no transfer issued + 0x3 + + + + + SINC + source incrementing burst + + 3 + 1 + read-write + + + B_0x0 + fixed burst + 0x0 + + + B_0x1 + contiguously incremented burst + 0x1 + + + + + SBL_1 + source burst length minus 1, between 0 and 63 + + 4 + 6 + read-write + + + PAM + padding/alignment mode + + 11 + 2 + read-write + + + B_0x0_PAM_1 + source data is transferred as right aligned, padded with 0s up to the destination data width + 0x0 + + + B_0x1_PAM_1 + source data is transferred as right aligned, sign extended up to the destination data width + 0x1 + + + B_0x2_PAM_1 + successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer + 0x2 + + + B_0x3_PAM_1 + successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer + 0x3 + + + + + SBX + source byte exchange within the unaligned half-word of each source word + + 13 + 1 + read-write + + + B_0x0 + no byte-based exchange within the unaligned half-word of each source word + 0x0 + + + B_0x1 + the two consecutive bytes within the unaligned half-word of each source word are exchanged. + 0x1 + + + + + SAP + source allocated port + + 14 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + SSEC + security attribute of the GPDMA transfer from the source + + 15 + 1 + read-write + + + B_0x0 + GPDMA transfer nonsecure + 0x0 + + + B_0x1 + GPDMA transfer secure + 0x1 + + + + + DDW_LOG2 + binary logarithm of the destination data width of a burst, in bytes + + 16 + 2 + read-write + + + B_0x0 + byte + 0x0 + + + B_0x1 + half-word (2 bytes) + 0x1 + + + B_0x2 + word (4 bytes) + 0x2 + + + B_0x3 + user setting error reported and no transfer issued + 0x3 + + + + + DINC + destination incrementing burst + + 19 + 1 + read-write + + + B_0x0 + fixed burst + 0x0 + + + B_0x1 + contiguously incremented burst + 0x1 + + + + + DBL_1 + destination burst length minus 1, between 0 and 63 + + 20 + 6 + read-write + + + DBX + destination byte exchange + + 26 + 1 + read-write + + + B_0x0 + no byte-based exchange within half-word + 0x0 + + + B_0x1 + the two consecutive (post PAM) bytes are exchanged in each destination half-word. + 0x1 + + + + + DHX + destination half-word exchange + + 27 + 1 + read-write + + + B_0x0 + no halfword-based exchanged within word + 0x0 + + + B_0x1 + the two consecutive (post PAM) half-words are exchanged in each destination word. + 0x1 + + + + + DAP + destination allocated port + + 30 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + DSEC + security attribute of the GPDMA transfer to the destination + + 31 + 1 + read-write + + + B_0x0 + GPDMA transfer nonsecure + 0x0 + + + B_0x1 + GPDMA transfer secure + 0x1 + + + + + + + GPDMA_C2TR2 + GPDMA_C2TR2 + GPDMA channel 2 transfer register 2 + 0x194 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + REQSEL + GPDMA hardware request selection + + 0 + 8 + read-write + + + SWREQ + software request + + 9 + 1 + read-write + + + B_0x0 + no software request. + 0x0 + + + B_0x1 + software request for a memory-to-memory transfer. + 0x1 + + + + + DREQ + destination hardware request + + 10 + 1 + read-write + + + B_0x0 + selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port) + 0x0 + + + B_0x1 + selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port) + 0x1 + + + + + BREQ + Block hardware request + + 11 + 1 + read-write + + + B_0x0 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level. + 0x0 + + + B_0x1 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 16. + 0x1 + + + + + PFREQ + Hardware request in peripheral flow control mode + + 12 + 1 + read-write + + + B_0x0 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. + 0x0 + + + B_0x1 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. + 0x1 + + + + + TRIGM + trigger mode + + 14 + 2 + read-write + + + B_0x0 + at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x (x = 6 to 7), for each block if a 2D/repeated block is configured with GPDMA_CxBR1. + 0x0 + + + B_0x1 + channel x (x = 0 to 5), same as 00; channel x (x = 6 to 7), at 2D/repeated block level. + 0x1 + + + B_0x2 + at link level: a LLI link transfer is conditioned by one hit trigger. + 0x2 + + + B_0x3 + at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. + 0x3 + + + + + TRIGSEL + trigger event input selection + + 16 + 6 + read-write + + + TRIGPOL + trigger event polarity + + 24 + 2 + read-write + + + B_0x0 + no trigger (masked trigger event) + 0x0 + + + B_0x1 + trigger on the rising edge + 0x1 + + + B_0x2 + trigger on the falling edge + 0x2 + + + B_0x3 + same as 00 + 0x3 + + + + + TCEM + transfer complete event mode + + 30 + 2 + read-write + + + B_0x0 + at block level (when GPDMA_CxBR1. + 0x0 + + + B_0x1 + channel x (x = 0 to 5), same as 00, channel x (x = 6 to 7), at 2D/repeated block level (when GPDMA_CxBR1. + 0x1 + + + B_0x2 + at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. + 0x2 + + + B_0x3 + at channel level: the complete transfer event is generated at the end of the last LLI transfer. + 0x3 + + + + + + + GPDMA_C2BR1 + GPDMA_C2BR1 + GPDMA channel 2 block register 1 + 0x198 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BNDT + block number of data bytes to transfer from the source + + 0 + 16 + read-write + + + + + GPDMA_C2SAR + GPDMA_C2SAR + GPDMA channel 2 source address register + 0x19C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SA + source address + + 0 + 32 + read-write + + + + + GPDMA_C2DAR + GPDMA_C2DAR + GPDMA channel 2 destination address register + 0x1A0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DA + destination address + + 0 + 32 + read-write + + + + + GPDMA_C2LLR + GPDMA_C2LLR + GPDMA channel 2 linked-list address register + 0x1CC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LA + pointer (16-bit low-significant address) to the next linked-list data structure + + 2 + 14 + read-write + + + ULL + Update GPDMA_CxLLR register from memory + + 16 + 1 + read-write + + + B_0x0 + no GPDMA_CxLLR update + 0x0 + + + B_0x1 + GPDMA_CxLLR update + 0x1 + + + + + UDA + Update GPDMA_CxDAR register from memory + + 27 + 1 + read-write + + + B_0x0 + no GPDMA_CxDAR update + 0x0 + + + B_0x1 + GPDMA_CxDAR update + 0x1 + + + + + USA + update GPDMA_CxSAR from memory + + 28 + 1 + read-write + + + B_0x0 + no GPDMA_CxSAR update + 0x0 + + + B_0x1 + GPDMA_CxSAR update + 0x1 + + + + + UB1 + Update GPDMA_CxBR1 from memory + + 29 + 1 + read-write + + + B_0x0 + no GPDMA_CxBR1 update from memory (GPDMA_CxBR1. + 0x0 + + + B_0x1 + GPDMA_CxBR1 update + 0x1 + + + + + UT2 + Update GPDMA_CxTR2 from memory + + 30 + 1 + read-write + + + B_0x0 + no GPDMA_CxTR2 update + 0x0 + + + B_0x1 + GPDMA_CxTR2 update + 0x1 + + + + + UT1 + Update GPDMA_CxTR1 from memory + + 31 + 1 + read-write + + + B_0x0 + no GPDMA_CxTR1 update + 0x0 + + + B_0x1 + GPDMA_CxTR1 update + 0x1 + + + + + + + GPDMA_C3LBAR + GPDMA_C3LBAR + GPDMA channel 3 linked-list base address register + 0x1D0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LBA + linked-list base address of GPDMA channel x + 16 + 16 + read-write + + + + + GPDMA_C3FCR + GPDMA_C3FCR + GPDMA channel 3 flag clear register + 0x1DC + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + TCF + transfer complete flag clear + 8 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding TCF flag cleared + 0x1 + + + + + HTF + half transfer flag clear + 9 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding HTF flag cleared + 0x1 + + + + + DTEF + data transfer error flag clear + 10 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding DTEF flag cleared + 0x1 + + + + + ULEF + update link transfer error flag clear + 11 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding ULEF flag cleared + 0x1 + + + + + USEF + user setting error flag clear + 12 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding USEF flag cleared + 0x1 + + + + + SUSPF + completed suspension flag clear + 13 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding SUSPF flag cleared + 0x1 + + + + + TOF + trigger overrun flag clear + 14 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding TOF flag cleared + 0x1 + + + + + + + GPDMA_C3SR + GPDMA_C3SR + GPDMA channel 3 status register + 0x1E0 + 0x20 + read-only + 0x00000001 + 0xFFFFFFFF + + + IDLEF + idle flag + + 0 + 1 + read-only + + + B_0x0 + channel not in idle state + 0x0 + + + B_0x1 + channel in idle state + 0x1 + + + + + TCF + transfer complete flag + + 8 + 1 + read-only + + + B_0x0 + no transfer complete event + 0x0 + + + B_0x1 + a transfer complete event occurred + 0x1 + + + + + HTF + half transfer flag + + 9 + 1 + read-only + + + B_0x0 + no half transfer event + 0x0 + + + B_0x1 + a half transfer event occurred + 0x1 + + + + + DTEF + data transfer error flag + 10 + 1 + read-only + + + B_0x0 + no data transfer error event + 0x0 + + + B_0x1 + a master bus error event occurred on a data transfer + 0x1 + + + + + ULEF + update link transfer error flag + 11 + 1 + read-only + + + B_0x0 + no update link transfer error event + 0x0 + + + B_0x1 + a master bus error event occurred while updating a linked-list register from memory + 0x1 + + + + + USEF + user setting error flag + 12 + 1 + read-only + + + B_0x0 + no user setting error event + 0x0 + + + B_0x1 + a user setting error event occurred + 0x1 + + + + + SUSPF + completed suspension flag + 13 + 1 + read-only + + + B_0x0 + no completed suspension event + 0x0 + + + B_0x1 + a completed suspension event occurred + 0x1 + + + + + TOF + trigger overrun flag + 14 + 1 + read-only + + + B_0x0 + no trigger overrun event + 0x0 + + + B_0x1 + a trigger overrun event occurred + 0x1 + + + + + FIFOL + monitored FIFO level + + 16 + 8 + read-only + + + + + GPDMA_C3CR + GPDMA_C3CR + GPDMA channel 3 control register + 0x1E4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EN + enable + + 0 + 1 + read-write + + + B_0x0 + write: ignored, read: channel disabled + 0x0 + + + B_0x1 + write: enable channel, read: channel enabled + 0x1 + + + + + RESET + reset + + 1 + 1 + write-only + + + B_0x0 + no channel reset + 0x0 + + + B_0x1 + channel reset + 0x1 + + + + + SUSP + suspend + + 2 + 1 + read-write + + + B_0x0 + write: resume channel, read: channel not suspended + 0x0 + + + B_0x1 + write: suspend channel, read: channel suspended. + 0x1 + + + + + TCIE + transfer complete interrupt enable + 8 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + HTIE + half transfer complete interrupt enable + 9 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + DTEIE + data transfer error interrupt enable + 10 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + ULEIE + update link transfer error interrupt enable + 11 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + USEIE + user setting error interrupt enable + 12 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SUSPIE + completed suspension interrupt enable + 13 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TOIE + trigger overrun interrupt enable + 14 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + LSM + Link step mode + + 16 + 1 + read-write + + + B_0x0 + channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). + 0x0 + + + B_0x1 + channel executed once for the current LLI + 0x1 + + + + + LAP + linked-list allocated port + + 17 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + PRIO + priority level of the channel x GPDMA transfer versus others + + 22 + 2 + read-write + + + B_0x0 + low priority, low weight + 0x0 + + + B_0x1 + low priority, mid weight + 0x1 + + + B_0x2 + low priority, high weight + 0x2 + + + B_0x3 + high priority + 0x3 + + + + + + + GPDMA_C3TR1 + GPDMA_C3TR1 + GPDMA channel 3 transfer register 1 + 0x210 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SDW_LOG2 + binary logarithm of the source data width of a burst in bytes + + 0 + 2 + read-write + + + B_0x0 + byte + 0x0 + + + B_0x1 + half-word (2 bytes) + 0x1 + + + B_0x2 + word (4 bytes) + 0x2 + + + B_0x3 + user setting error reported and no transfer issued + 0x3 + + + + + SINC + source incrementing burst + + 3 + 1 + read-write + + + B_0x0 + fixed burst + 0x0 + + + B_0x1 + contiguously incremented burst + 0x1 + + + + + SBL_1 + source burst length minus 1, between 0 and 63 + + 4 + 6 + read-write + + + PAM + padding/alignment mode + + 11 + 2 + read-write + + + B_0x0_PAM_1 + source data is transferred as right aligned, padded with 0s up to the destination data width + 0x0 + + + B_0x1_PAM_1 + source data is transferred as right aligned, sign extended up to the destination data width + 0x1 + + + B_0x2_PAM_1 + successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer + 0x2 + + + B_0x3_PAM_1 + successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer + 0x3 + + + + + SBX + source byte exchange within the unaligned half-word of each source word + + 13 + 1 + read-write + + + B_0x0 + no byte-based exchange within the unaligned half-word of each source word + 0x0 + + + B_0x1 + the two consecutive bytes within the unaligned half-word of each source word are exchanged. + 0x1 + + + + + SAP + source allocated port + + 14 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + SSEC + security attribute of the GPDMA transfer from the source + + 15 + 1 + read-write + + + B_0x0 + GPDMA transfer nonsecure + 0x0 + + + B_0x1 + GPDMA transfer secure + 0x1 + + + + + DDW_LOG2 + binary logarithm of the destination data width of a burst, in bytes + + 16 + 2 + read-write + + + B_0x0 + byte + 0x0 + + + B_0x1 + half-word (2 bytes) + 0x1 + + + B_0x2 + word (4 bytes) + 0x2 + + + B_0x3 + user setting error reported and no transfer issued + 0x3 + + + + + DINC + destination incrementing burst + + 19 + 1 + read-write + + + B_0x0 + fixed burst + 0x0 + + + B_0x1 + contiguously incremented burst + 0x1 + + + + + DBL_1 + destination burst length minus 1, between 0 and 63 + + 20 + 6 + read-write + + + DBX + destination byte exchange + + 26 + 1 + read-write + + + B_0x0 + no byte-based exchange within half-word + 0x0 + + + B_0x1 + the two consecutive (post PAM) bytes are exchanged in each destination half-word. + 0x1 + + + + + DHX + destination half-word exchange + + 27 + 1 + read-write + + + B_0x0 + no halfword-based exchanged within word + 0x0 + + + B_0x1 + the two consecutive (post PAM) half-words are exchanged in each destination word. + 0x1 + + + + + DAP + destination allocated port + + 30 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + DSEC + security attribute of the GPDMA transfer to the destination + + 31 + 1 + read-write + + + B_0x0 + GPDMA transfer nonsecure + 0x0 + + + B_0x1 + GPDMA transfer secure + 0x1 + + + + + + + GPDMA_C3TR2 + GPDMA_C3TR2 + GPDMA channel 3 transfer register 2 + 0x214 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + REQSEL + GPDMA hardware request selection + + 0 + 8 + read-write + + + SWREQ + software request + + 9 + 1 + read-write + + + B_0x0 + no software request. + 0x0 + + + B_0x1 + software request for a memory-to-memory transfer. + 0x1 + + + + + DREQ + destination hardware request + + 10 + 1 + read-write + + + B_0x0 + selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port) + 0x0 + + + B_0x1 + selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port) + 0x1 + + + + + BREQ + Block hardware request + + 11 + 1 + read-write + + + B_0x0 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level. + 0x0 + + + B_0x1 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 16. + 0x1 + + + + + PFREQ + Hardware request in peripheral flow control mode + + 12 + 1 + read-write + + + B_0x0 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. + 0x0 + + + B_0x1 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. + 0x1 + + + + + TRIGM + trigger mode + + 14 + 2 + read-write + + + B_0x0 + at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x (x = 6 to 7), for each block if a 2D/repeated block is configured with GPDMA_CxBR1. + 0x0 + + + B_0x1 + channel x (x = 0 to 5), same as 00; channel x (x = 6 to 7), at 2D/repeated block level. + 0x1 + + + B_0x2 + at link level: a LLI link transfer is conditioned by one hit trigger. + 0x2 + + + B_0x3 + at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. + 0x3 + + + + + TRIGSEL + trigger event input selection + + 16 + 6 + read-write + + + TRIGPOL + trigger event polarity + + 24 + 2 + read-write + + + B_0x0 + no trigger (masked trigger event) + 0x0 + + + B_0x1 + trigger on the rising edge + 0x1 + + + B_0x2 + trigger on the falling edge + 0x2 + + + B_0x3 + same as 00 + 0x3 + + + + + TCEM + transfer complete event mode + + 30 + 2 + read-write + + + B_0x0 + at block level (when GPDMA_CxBR1. + 0x0 + + + B_0x1 + channel x (x = 0 to 5), same as 00, channel x (x = 6 to 7), at 2D/repeated block level (when GPDMA_CxBR1. + 0x1 + + + B_0x2 + at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. + 0x2 + + + B_0x3 + at channel level: the complete transfer event is generated at the end of the last LLI transfer. + 0x3 + + + + + + + GPDMA_C3BR1 + GPDMA_C3BR1 + GPDMA channel 3 block register 1 + 0x218 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BNDT + block number of data bytes to transfer from the source + + 0 + 16 + read-write + + + + + GPDMA_C3SAR + GPDMA_C3SAR + GPDMA channel 3 source address register + 0x21C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SA + source address + + 0 + 32 + read-write + + + + + GPDMA_C3DAR + GPDMA_C3DAR + GPDMA channel 3 destination address register + 0x220 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DA + destination address + + 0 + 32 + read-write + + + + + GPDMA_C3LLR + GPDMA_C3LLR + GPDMA channel 3 linked-list address register + 0x24C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LA + pointer (16-bit low-significant address) to the next linked-list data structure + + 2 + 14 + read-write + + + ULL + Update GPDMA_CxLLR register from memory + + 16 + 1 + read-write + + + B_0x0 + no GPDMA_CxLLR update + 0x0 + + + B_0x1 + GPDMA_CxLLR update + 0x1 + + + + + UDA + Update GPDMA_CxDAR register from memory + + 27 + 1 + read-write + + + B_0x0 + no GPDMA_CxDAR update + 0x0 + + + B_0x1 + GPDMA_CxDAR update + 0x1 + + + + + USA + update GPDMA_CxSAR from memory + + 28 + 1 + read-write + + + B_0x0 + no GPDMA_CxSAR update + 0x0 + + + B_0x1 + GPDMA_CxSAR update + 0x1 + + + + + UB1 + Update GPDMA_CxBR1 from memory + + 29 + 1 + read-write + + + B_0x0 + no GPDMA_CxBR1 update from memory (GPDMA_CxBR1. + 0x0 + + + B_0x1 + GPDMA_CxBR1 update + 0x1 + + + + + UT2 + Update GPDMA_CxTR2 from memory + + 30 + 1 + read-write + + + B_0x0 + no GPDMA_CxTR2 update + 0x0 + + + B_0x1 + GPDMA_CxTR2 update + 0x1 + + + + + UT1 + Update GPDMA_CxTR1 from memory + + 31 + 1 + read-write + + + B_0x0 + no GPDMA_CxTR1 update + 0x0 + + + B_0x1 + GPDMA_CxTR1 update + 0x1 + + + + + + + GPDMA_C4LBAR + GPDMA_C4LBAR + GPDMA channel 4 linked-list base address register + 0x250 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LBA + linked-list base address of GPDMA channel x + 16 + 16 + read-write + + + + + GPDMA_C4FCR + GPDMA_C4FCR + GPDMA channel 4 flag clear register + 0x25C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + TCF + transfer complete flag clear + 8 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding TCF flag cleared + 0x1 + + + + + HTF + half transfer flag clear + 9 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding HTF flag cleared + 0x1 + + + + + DTEF + data transfer error flag clear + 10 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding DTEF flag cleared + 0x1 + + + + + ULEF + update link transfer error flag clear + 11 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding ULEF flag cleared + 0x1 + + + + + USEF + user setting error flag clear + 12 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding USEF flag cleared + 0x1 + + + + + SUSPF + completed suspension flag clear + 13 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding SUSPF flag cleared + 0x1 + + + + + TOF + trigger overrun flag clear + 14 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding TOF flag cleared + 0x1 + + + + + + + GPDMA_C4SR + GPDMA_C4SR + GPDMA channel 4 status register + 0x260 + 0x20 + read-only + 0x00000001 + 0xFFFFFFFF + + + IDLEF + idle flag + + 0 + 1 + read-only + + + B_0x0 + channel not in idle state + 0x0 + + + B_0x1 + channel in idle state + 0x1 + + + + + TCF + transfer complete flag + + 8 + 1 + read-only + + + B_0x0 + no transfer complete event + 0x0 + + + B_0x1 + a transfer complete event occurred + 0x1 + + + + + HTF + half transfer flag + + 9 + 1 + read-only + + + B_0x0 + no half transfer event + 0x0 + + + B_0x1 + a half transfer event occurred + 0x1 + + + + + DTEF + data transfer error flag + 10 + 1 + read-only + + + B_0x0 + no data transfer error event + 0x0 + + + B_0x1 + a master bus error event occurred on a data transfer + 0x1 + + + + + ULEF + update link transfer error flag + 11 + 1 + read-only + + + B_0x0 + no update link transfer error event + 0x0 + + + B_0x1 + a master bus error event occurred while updating a linked-list register from memory + 0x1 + + + + + USEF + user setting error flag + 12 + 1 + read-only + + + B_0x0 + no user setting error event + 0x0 + + + B_0x1 + a user setting error event occurred + 0x1 + + + + + SUSPF + completed suspension flag + 13 + 1 + read-only + + + B_0x0 + no completed suspension event + 0x0 + + + B_0x1 + a completed suspension event occurred + 0x1 + + + + + TOF + trigger overrun flag + 14 + 1 + read-only + + + B_0x0 + no trigger overrun event + 0x0 + + + B_0x1 + a trigger overrun event occurred + 0x1 + + + + + FIFOL + monitored FIFO level + + 16 + 8 + read-only + + + + + GPDMA_C4CR + GPDMA_C4CR + GPDMA channel 4 control register + 0x264 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EN + enable + + 0 + 1 + read-write + + + B_0x0 + write: ignored, read: channel disabled + 0x0 + + + B_0x1 + write: enable channel, read: channel enabled + 0x1 + + + + + RESET + reset + + 1 + 1 + write-only + + + B_0x0 + no channel reset + 0x0 + + + B_0x1 + channel reset + 0x1 + + + + + SUSP + suspend + + 2 + 1 + read-write + + + B_0x0 + write: resume channel, read: channel not suspended + 0x0 + + + B_0x1 + write: suspend channel, read: channel suspended. + 0x1 + + + + + TCIE + transfer complete interrupt enable + 8 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + HTIE + half transfer complete interrupt enable + 9 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + DTEIE + data transfer error interrupt enable + 10 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + ULEIE + update link transfer error interrupt enable + 11 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + USEIE + user setting error interrupt enable + 12 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SUSPIE + completed suspension interrupt enable + 13 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TOIE + trigger overrun interrupt enable + 14 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + LSM + Link step mode + + 16 + 1 + read-write + + + B_0x0 + channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). + 0x0 + + + B_0x1 + channel executed once for the current LLI + 0x1 + + + + + LAP + linked-list allocated port + + 17 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + PRIO + priority level of the channel x GPDMA transfer versus others + + 22 + 2 + read-write + + + B_0x0 + low priority, low weight + 0x0 + + + B_0x1 + low priority, mid weight + 0x1 + + + B_0x2 + low priority, high weight + 0x2 + + + B_0x3 + high priority + 0x3 + + + + + + + GPDMA_C4TR1 + GPDMA_C4TR1 + GPDMA channel 4 transfer register 1 + 0x290 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SDW_LOG2 + binary logarithm of the source data width of a burst in bytes + + 0 + 2 + read-write + + + B_0x0 + byte + 0x0 + + + B_0x1 + half-word (2 bytes) + 0x1 + + + B_0x2 + word (4 bytes) + 0x2 + + + B_0x3 + user setting error reported and no transfer issued + 0x3 + + + + + SINC + source incrementing burst + + 3 + 1 + read-write + + + B_0x0 + fixed burst + 0x0 + + + B_0x1 + contiguously incremented burst + 0x1 + + + + + SBL_1 + source burst length minus 1, between 0 and 63 + + 4 + 6 + read-write + + + PAM + padding/alignment mode + + 11 + 2 + read-write + + + B_0x0_PAM_1 + source data is transferred as right aligned, padded with 0s up to the destination data width + 0x0 + + + B_0x1_PAM_1 + source data is transferred as right aligned, sign extended up to the destination data width + 0x1 + + + B_0x2_PAM_1 + successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer + 0x2 + + + B_0x3_PAM_1 + successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer + 0x3 + + + + + SBX + source byte exchange within the unaligned half-word of each source word + + 13 + 1 + read-write + + + B_0x0 + no byte-based exchange within the unaligned half-word of each source word + 0x0 + + + B_0x1 + the two consecutive bytes within the unaligned half-word of each source word are exchanged. + 0x1 + + + + + SAP + source allocated port + + 14 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + SSEC + security attribute of the GPDMA transfer from the source + + 15 + 1 + read-write + + + B_0x0 + GPDMA transfer nonsecure + 0x0 + + + B_0x1 + GPDMA transfer secure + 0x1 + + + + + DDW_LOG2 + binary logarithm of the destination data width of a burst, in bytes + + 16 + 2 + read-write + + + B_0x0 + byte + 0x0 + + + B_0x1 + half-word (2 bytes) + 0x1 + + + B_0x2 + word (4 bytes) + 0x2 + + + B_0x3 + user setting error reported and no transfer issued + 0x3 + + + + + DINC + destination incrementing burst + + 19 + 1 + read-write + + + B_0x0 + fixed burst + 0x0 + + + B_0x1 + contiguously incremented burst + 0x1 + + + + + DBL_1 + destination burst length minus 1, between 0 and 63 + + 20 + 6 + read-write + + + DBX + destination byte exchange + + 26 + 1 + read-write + + + B_0x0 + no byte-based exchange within half-word + 0x0 + + + B_0x1 + the two consecutive (post PAM) bytes are exchanged in each destination half-word. + 0x1 + + + + + DHX + destination half-word exchange + + 27 + 1 + read-write + + + B_0x0 + no halfword-based exchanged within word + 0x0 + + + B_0x1 + the two consecutive (post PAM) half-words are exchanged in each destination word. + 0x1 + + + + + DAP + destination allocated port + + 30 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + DSEC + security attribute of the GPDMA transfer to the destination + + 31 + 1 + read-write + + + B_0x0 + GPDMA transfer nonsecure + 0x0 + + + B_0x1 + GPDMA transfer secure + 0x1 + + + + + + + GPDMA_C4TR2 + GPDMA_C4TR2 + GPDMA channel 4 transfer register 2 + 0x294 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + REQSEL + GPDMA hardware request selection + + 0 + 8 + read-write + + + SWREQ + software request + + 9 + 1 + read-write + + + B_0x0 + no software request. + 0x0 + + + B_0x1 + software request for a memory-to-memory transfer. + 0x1 + + + + + DREQ + destination hardware request + + 10 + 1 + read-write + + + B_0x0 + selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port) + 0x0 + + + B_0x1 + selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port) + 0x1 + + + + + BREQ + Block hardware request + + 11 + 1 + read-write + + + B_0x0 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level. + 0x0 + + + B_0x1 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 16. + 0x1 + + + + + PFREQ + Hardware request in peripheral flow control mode + + 12 + 1 + read-write + + + B_0x0 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. + 0x0 + + + B_0x1 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. + 0x1 + + + + + TRIGM + trigger mode + + 14 + 2 + read-write + + + B_0x0 + at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x (x = 6 to 7), for each block if a 2D/repeated block is configured with GPDMA_CxBR1. + 0x0 + + + B_0x1 + channel x (x = 0 to 5), same as 00; channel x (x = 6 to 7), at 2D/repeated block level. + 0x1 + + + B_0x2 + at link level: a LLI link transfer is conditioned by one hit trigger. + 0x2 + + + B_0x3 + at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. + 0x3 + + + + + TRIGSEL + trigger event input selection + + 16 + 6 + read-write + + + TRIGPOL + trigger event polarity + + 24 + 2 + read-write + + + B_0x0 + no trigger (masked trigger event) + 0x0 + + + B_0x1 + trigger on the rising edge + 0x1 + + + B_0x2 + trigger on the falling edge + 0x2 + + + B_0x3 + same as 00 + 0x3 + + + + + TCEM + transfer complete event mode + + 30 + 2 + read-write + + + B_0x0 + at block level (when GPDMA_CxBR1. + 0x0 + + + B_0x1 + channel x (x = 0 to 5), same as 00, channel x (x = 6 to 7), at 2D/repeated block level (when GPDMA_CxBR1. + 0x1 + + + B_0x2 + at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. + 0x2 + + + B_0x3 + at channel level: the complete transfer event is generated at the end of the last LLI transfer. + 0x3 + + + + + + + GPDMA_C4BR1 + GPDMA_C4BR1 + GPDMA channel 4 block register 1 + 0x298 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BNDT + block number of data bytes to transfer from the source + + 0 + 16 + read-write + + + + + GPDMA_C4SAR + GPDMA_C4SAR + GPDMA channel 4 source address register + 0x29C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SA + source address + + 0 + 32 + read-write + + + + + GPDMA_C4DAR + GPDMA_C4DAR + GPDMA channel 4 destination address register + 0x2A0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DA + destination address + + 0 + 32 + read-write + + + + + GPDMA_C4LLR + GPDMA_C4LLR + GPDMA channel 4 linked-list address register + 0x2CC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LA + pointer (16-bit low-significant address) to the next linked-list data structure + + 2 + 14 + read-write + + + ULL + Update GPDMA_CxLLR register from memory + + 16 + 1 + read-write + + + B_0x0 + no GPDMA_CxLLR update + 0x0 + + + B_0x1 + GPDMA_CxLLR update + 0x1 + + + + + UDA + Update GPDMA_CxDAR register from memory + + 27 + 1 + read-write + + + B_0x0 + no GPDMA_CxDAR update + 0x0 + + + B_0x1 + GPDMA_CxDAR update + 0x1 + + + + + USA + update GPDMA_CxSAR from memory + + 28 + 1 + read-write + + + B_0x0 + no GPDMA_CxSAR update + 0x0 + + + B_0x1 + GPDMA_CxSAR update + 0x1 + + + + + UB1 + Update GPDMA_CxBR1 from memory + + 29 + 1 + read-write + + + B_0x0 + no GPDMA_CxBR1 update from memory (GPDMA_CxBR1. + 0x0 + + + B_0x1 + GPDMA_CxBR1 update + 0x1 + + + + + UT2 + Update GPDMA_CxTR2 from memory + + 30 + 1 + read-write + + + B_0x0 + no GPDMA_CxTR2 update + 0x0 + + + B_0x1 + GPDMA_CxTR2 update + 0x1 + + + + + UT1 + Update GPDMA_CxTR1 from memory + + 31 + 1 + read-write + + + B_0x0 + no GPDMA_CxTR1 update + 0x0 + + + B_0x1 + GPDMA_CxTR1 update + 0x1 + + + + + + + GPDMA_C5LBAR + GPDMA_C5LBAR + GPDMA channel 5 linked-list base address register + 0x2D0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LBA + linked-list base address of GPDMA channel x + 16 + 16 + read-write + + + + + GPDMA_C5FCR + GPDMA_C5FCR + GPDMA channel 5 flag clear register + 0x2DC + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + TCF + transfer complete flag clear + 8 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding TCF flag cleared + 0x1 + + + + + HTF + half transfer flag clear + 9 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding HTF flag cleared + 0x1 + + + + + DTEF + data transfer error flag clear + 10 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding DTEF flag cleared + 0x1 + + + + + ULEF + update link transfer error flag clear + 11 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding ULEF flag cleared + 0x1 + + + + + USEF + user setting error flag clear + 12 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding USEF flag cleared + 0x1 + + + + + SUSPF + completed suspension flag clear + 13 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding SUSPF flag cleared + 0x1 + + + + + TOF + trigger overrun flag clear + 14 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding TOF flag cleared + 0x1 + + + + + + + GPDMA_C5SR + GPDMA_C5SR + GPDMA channel 5 status register + 0x2E0 + 0x20 + read-only + 0x00000001 + 0xFFFFFFFF + + + IDLEF + idle flag + + 0 + 1 + read-only + + + B_0x0 + channel not in idle state + 0x0 + + + B_0x1 + channel in idle state + 0x1 + + + + + TCF + transfer complete flag + + 8 + 1 + read-only + + + B_0x0 + no transfer complete event + 0x0 + + + B_0x1 + a transfer complete event occurred + 0x1 + + + + + HTF + half transfer flag + + 9 + 1 + read-only + + + B_0x0 + no half transfer event + 0x0 + + + B_0x1 + a half transfer event occurred + 0x1 + + + + + DTEF + data transfer error flag + 10 + 1 + read-only + + + B_0x0 + no data transfer error event + 0x0 + + + B_0x1 + a master bus error event occurred on a data transfer + 0x1 + + + + + ULEF + update link transfer error flag + 11 + 1 + read-only + + + B_0x0 + no update link transfer error event + 0x0 + + + B_0x1 + a master bus error event occurred while updating a linked-list register from memory + 0x1 + + + + + USEF + user setting error flag + 12 + 1 + read-only + + + B_0x0 + no user setting error event + 0x0 + + + B_0x1 + a user setting error event occurred + 0x1 + + + + + SUSPF + completed suspension flag + 13 + 1 + read-only + + + B_0x0 + no completed suspension event + 0x0 + + + B_0x1 + a completed suspension event occurred + 0x1 + + + + + TOF + trigger overrun flag + 14 + 1 + read-only + + + B_0x0 + no trigger overrun event + 0x0 + + + B_0x1 + a trigger overrun event occurred + 0x1 + + + + + FIFOL + monitored FIFO level + + 16 + 8 + read-only + + + + + GPDMA_C5CR + GPDMA_C5CR + GPDMA channel 5 control register + 0x2E4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EN + enable + + 0 + 1 + read-write + + + B_0x0 + write: ignored, read: channel disabled + 0x0 + + + B_0x1 + write: enable channel, read: channel enabled + 0x1 + + + + + RESET + reset + + 1 + 1 + write-only + + + B_0x0 + no channel reset + 0x0 + + + B_0x1 + channel reset + 0x1 + + + + + SUSP + suspend + + 2 + 1 + read-write + + + B_0x0 + write: resume channel, read: channel not suspended + 0x0 + + + B_0x1 + write: suspend channel, read: channel suspended. + 0x1 + + + + + TCIE + transfer complete interrupt enable + 8 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + HTIE + half transfer complete interrupt enable + 9 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + DTEIE + data transfer error interrupt enable + 10 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + ULEIE + update link transfer error interrupt enable + 11 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + USEIE + user setting error interrupt enable + 12 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SUSPIE + completed suspension interrupt enable + 13 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TOIE + trigger overrun interrupt enable + 14 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + LSM + Link step mode + + 16 + 1 + read-write + + + B_0x0 + channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). + 0x0 + + + B_0x1 + channel executed once for the current LLI + 0x1 + + + + + LAP + linked-list allocated port + + 17 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + PRIO + priority level of the channel x GPDMA transfer versus others + + 22 + 2 + read-write + + + B_0x0 + low priority, low weight + 0x0 + + + B_0x1 + low priority, mid weight + 0x1 + + + B_0x2 + low priority, high weight + 0x2 + + + B_0x3 + high priority + 0x3 + + + + + + + GPDMA_C5TR1 + GPDMA_C5TR1 + GPDMA channel 5 transfer register 1 + 0x310 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SDW_LOG2 + binary logarithm of the source data width of a burst in bytes + + 0 + 2 + read-write + + + B_0x0 + byte + 0x0 + + + B_0x1 + half-word (2 bytes) + 0x1 + + + B_0x2 + word (4 bytes) + 0x2 + + + B_0x3 + user setting error reported and no transfer issued + 0x3 + + + + + SINC + source incrementing burst + + 3 + 1 + read-write + + + B_0x0 + fixed burst + 0x0 + + + B_0x1 + contiguously incremented burst + 0x1 + + + + + SBL_1 + source burst length minus 1, between 0 and 63 + + 4 + 6 + read-write + + + PAM + padding/alignment mode + + 11 + 2 + read-write + + + B_0x0_PAM_1 + source data is transferred as right aligned, padded with 0s up to the destination data width + 0x0 + + + B_0x1_PAM_1 + source data is transferred as right aligned, sign extended up to the destination data width + 0x1 + + + B_0x2_PAM_1 + successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer + 0x2 + + + B_0x3_PAM_1 + successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer + 0x3 + + + + + SBX + source byte exchange within the unaligned half-word of each source word + + 13 + 1 + read-write + + + B_0x0 + no byte-based exchange within the unaligned half-word of each source word + 0x0 + + + B_0x1 + the two consecutive bytes within the unaligned half-word of each source word are exchanged. + 0x1 + + + + + SAP + source allocated port + + 14 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + SSEC + security attribute of the GPDMA transfer from the source + + 15 + 1 + read-write + + + B_0x0 + GPDMA transfer nonsecure + 0x0 + + + B_0x1 + GPDMA transfer secure + 0x1 + + + + + DDW_LOG2 + binary logarithm of the destination data width of a burst, in bytes + + 16 + 2 + read-write + + + B_0x0 + byte + 0x0 + + + B_0x1 + half-word (2 bytes) + 0x1 + + + B_0x2 + word (4 bytes) + 0x2 + + + B_0x3 + user setting error reported and no transfer issued + 0x3 + + + + + DINC + destination incrementing burst + + 19 + 1 + read-write + + + B_0x0 + fixed burst + 0x0 + + + B_0x1 + contiguously incremented burst + 0x1 + + + + + DBL_1 + destination burst length minus 1, between 0 and 63 + + 20 + 6 + read-write + + + DBX + destination byte exchange + + 26 + 1 + read-write + + + B_0x0 + no byte-based exchange within half-word + 0x0 + + + B_0x1 + the two consecutive (post PAM) bytes are exchanged in each destination half-word. + 0x1 + + + + + DHX + destination half-word exchange + + 27 + 1 + read-write + + + B_0x0 + no halfword-based exchanged within word + 0x0 + + + B_0x1 + the two consecutive (post PAM) half-words are exchanged in each destination word. + 0x1 + + + + + DAP + destination allocated port + + 30 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + DSEC + security attribute of the GPDMA transfer to the destination + + 31 + 1 + read-write + + + B_0x0 + GPDMA transfer nonsecure + 0x0 + + + B_0x1 + GPDMA transfer secure + 0x1 + + + + + + + GPDMA_C5TR2 + GPDMA_C5TR2 + GPDMA channel 5 transfer register 2 + 0x314 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + REQSEL + GPDMA hardware request selection + + 0 + 8 + read-write + + + SWREQ + software request + + 9 + 1 + read-write + + + B_0x0 + no software request. + 0x0 + + + B_0x1 + software request for a memory-to-memory transfer. + 0x1 + + + + + DREQ + destination hardware request + + 10 + 1 + read-write + + + B_0x0 + selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port) + 0x0 + + + B_0x1 + selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port) + 0x1 + + + + + BREQ + Block hardware request + + 11 + 1 + read-write + + + B_0x0 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level. + 0x0 + + + B_0x1 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 16. + 0x1 + + + + + PFREQ + Hardware request in peripheral flow control mode + + 12 + 1 + read-write + + + B_0x0 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. + 0x0 + + + B_0x1 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. + 0x1 + + + + + TRIGM + trigger mode + + 14 + 2 + read-write + + + B_0x0 + at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x (x = 6 to 7), for each block if a 2D/repeated block is configured with GPDMA_CxBR1. + 0x0 + + + B_0x1 + channel x (x = 0 to 5), same as 00; channel x (x = 6 to 7), at 2D/repeated block level. + 0x1 + + + B_0x2 + at link level: a LLI link transfer is conditioned by one hit trigger. + 0x2 + + + B_0x3 + at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. + 0x3 + + + + + TRIGSEL + trigger event input selection + + 16 + 6 + read-write + + + TRIGPOL + trigger event polarity + + 24 + 2 + read-write + + + B_0x0 + no trigger (masked trigger event) + 0x0 + + + B_0x1 + trigger on the rising edge + 0x1 + + + B_0x2 + trigger on the falling edge + 0x2 + + + B_0x3 + same as 00 + 0x3 + + + + + TCEM + transfer complete event mode + + 30 + 2 + read-write + + + B_0x0 + at block level (when GPDMA_CxBR1. + 0x0 + + + B_0x1 + channel x (x = 0 to 5), same as 00, channel x (x = 6 to 7), at 2D/repeated block level (when GPDMA_CxBR1. + 0x1 + + + B_0x2 + at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. + 0x2 + + + B_0x3 + at channel level: the complete transfer event is generated at the end of the last LLI transfer. + 0x3 + + + + + + + GPDMA_C5BR1 + GPDMA_C5BR1 + GPDMA channel 5 block register 1 + 0x318 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BNDT + block number of data bytes to transfer from the source + + 0 + 16 + read-write + + + + + GPDMA_C5SAR + GPDMA_C5SAR + GPDMA channel 5 source address register + 0x31C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SA + source address + + 0 + 32 + read-write + + + + + GPDMA_C5DAR + GPDMA_C5DAR + GPDMA channel 5 destination address register + 0x320 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DA + destination address + + 0 + 32 + read-write + + + + + GPDMA_C5LLR + GPDMA_C5LLR + GPDMA channel 5 linked-list address register + 0x34C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LA + pointer (16-bit low-significant address) to the next linked-list data structure + + 2 + 14 + read-write + + + ULL + Update GPDMA_CxLLR register from memory + + 16 + 1 + read-write + + + B_0x0 + no GPDMA_CxLLR update + 0x0 + + + B_0x1 + GPDMA_CxLLR update + 0x1 + + + + + UDA + Update GPDMA_CxDAR register from memory + + 27 + 1 + read-write + + + B_0x0 + no GPDMA_CxDAR update + 0x0 + + + B_0x1 + GPDMA_CxDAR update + 0x1 + + + + + USA + update GPDMA_CxSAR from memory + + 28 + 1 + read-write + + + B_0x0 + no GPDMA_CxSAR update + 0x0 + + + B_0x1 + GPDMA_CxSAR update + 0x1 + + + + + UB1 + Update GPDMA_CxBR1 from memory + + 29 + 1 + read-write + + + B_0x0 + no GPDMA_CxBR1 update from memory (GPDMA_CxBR1. + 0x0 + + + B_0x1 + GPDMA_CxBR1 update + 0x1 + + + + + UT2 + Update GPDMA_CxTR2 from memory + + 30 + 1 + read-write + + + B_0x0 + no GPDMA_CxTR2 update + 0x0 + + + B_0x1 + GPDMA_CxTR2 update + 0x1 + + + + + UT1 + Update GPDMA_CxTR1 from memory + + 31 + 1 + read-write + + + B_0x0 + no GPDMA_CxTR1 update + 0x0 + + + B_0x1 + GPDMA_CxTR1 update + 0x1 + + + + + + + GPDMA_C6LBAR + GPDMA_C6LBAR + GPDMA channel 6 linked-list base address register + 0x350 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LBA + linked-list base address of GPDMA channel x + 16 + 16 + read-write + + + + + GPDMA_C6FCR + GPDMA_C6FCR + GPDMA channel 6 flag clear register + 0x35C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + TCF + transfer complete flag clear + 8 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding TCF flag cleared + 0x1 + + + + + HTF + half transfer flag clear + 9 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding HTF flag cleared + 0x1 + + + + + DTEF + data transfer error flag clear + 10 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding DTEF flag cleared + 0x1 + + + + + ULEF + update link transfer error flag clear + 11 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding ULEF flag cleared + 0x1 + + + + + USEF + user setting error flag clear + 12 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding USEF flag cleared + 0x1 + + + + + SUSPF + completed suspension flag clear + 13 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding SUSPF flag cleared + 0x1 + + + + + TOF + trigger overrun flag clear + 14 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding TOF flag cleared + 0x1 + + + + + + + GPDMA_C6SR + GPDMA_C6SR + GPDMA channel 6 status register + 0x360 + 0x20 + read-only + 0x00000001 + 0xFFFFFFFF + + + IDLEF + idle flag + + 0 + 1 + read-only + + + B_0x0 + channel not in idle state + 0x0 + + + B_0x1 + channel in idle state + 0x1 + + + + + TCF + transfer complete flag + + 8 + 1 + read-only + + + B_0x0 + no transfer complete event + 0x0 + + + B_0x1 + a transfer complete event occurred + 0x1 + + + + + HTF + half transfer flag + + 9 + 1 + read-only + + + B_0x0 + no half transfer event + 0x0 + + + B_0x1 + a half transfer event occurred + 0x1 + + + + + DTEF + data transfer error flag + 10 + 1 + read-only + + + B_0x0 + no data transfer error event + 0x0 + + + B_0x1 + a master bus error event occurred on a data transfer + 0x1 + + + + + ULEF + update link transfer error flag + 11 + 1 + read-only + + + B_0x0 + no update link transfer error event + 0x0 + + + B_0x1 + a master bus error event occurred while updating a linked-list register from memory + 0x1 + + + + + USEF + user setting error flag + 12 + 1 + read-only + + + B_0x0 + no user setting error event + 0x0 + + + B_0x1 + a user setting error event occurred + 0x1 + + + + + SUSPF + completed suspension flag + 13 + 1 + read-only + + + B_0x0 + no completed suspension event + 0x0 + + + B_0x1 + a completed suspension event occurred + 0x1 + + + + + TOF + trigger overrun flag + 14 + 1 + read-only + + + B_0x0 + no trigger overrun event + 0x0 + + + B_0x1 + a trigger overrun event occurred + 0x1 + + + + + FIFOL + monitored FIFO level + + 16 + 8 + read-only + + + + + GPDMA_C6CR + GPDMA_C6CR + GPDMA channel 6 control register + 0x364 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EN + enable + + 0 + 1 + read-write + + + B_0x0 + write: ignored, read: channel disabled + 0x0 + + + B_0x1 + write: enable channel, read: channel enabled + 0x1 + + + + + RESET + reset + + 1 + 1 + write-only + + + B_0x0 + no channel reset + 0x0 + + + B_0x1 + channel reset + 0x1 + + + + + SUSP + suspend + + 2 + 1 + read-write + + + B_0x0 + write: resume channel, read: channel not suspended + 0x0 + + + B_0x1 + write: suspend channel, read: channel suspended. + 0x1 + + + + + TCIE + transfer complete interrupt enable + 8 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + HTIE + half transfer complete interrupt enable + 9 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + DTEIE + data transfer error interrupt enable + 10 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + ULEIE + update link transfer error interrupt enable + 11 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + USEIE + user setting error interrupt enable + 12 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SUSPIE + completed suspension interrupt enable + 13 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TOIE + trigger overrun interrupt enable + 14 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + LSM + Link step mode + + 16 + 1 + read-write + + + B_0x0 + channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). + 0x0 + + + B_0x1 + channel executed once for the current LLI + 0x1 + + + + + LAP + linked-list allocated port + + 17 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + PRIO + priority level of the channel x GPDMA transfer versus others + + 22 + 2 + read-write + + + B_0x0 + low priority, low weight + 0x0 + + + B_0x1 + low priority, mid weight + 0x1 + + + B_0x2 + low priority, high weight + 0x2 + + + B_0x3 + high priority + 0x3 + + + + + + + GPDMA_C6TR1 + GPDMA_C6TR1 + GPDMA channel 6 transfer register 1 + 0x390 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SDW_LOG2 + binary logarithm of the source data width of a burst in bytes + + 0 + 2 + read-write + + + B_0x0 + byte + 0x0 + + + B_0x1 + half-word (2 bytes) + 0x1 + + + B_0x2 + word (4 bytes) + 0x2 + + + B_0x3 + user setting error reported and no transfer issued + 0x3 + + + + + SINC + source incrementing burst + + 3 + 1 + read-write + + + B_0x0 + fixed burst + 0x0 + + + B_0x1 + contiguously incremented burst + 0x1 + + + + + SBL_1 + source burst length minus 1, between 0 and 63 + + 4 + 6 + read-write + + + PAM + padding/alignment mode + + 11 + 2 + read-write + + + B_0x0_PAM_1 + source data is transferred as right aligned, padded with 0s up to the destination data width + 0x0 + + + B_0x1_PAM_1 + source data is transferred as right aligned, sign extended up to the destination data width + 0x1 + + + B_0x2_PAM_1 + successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer + 0x2 + + + B_0x3_PAM_1 + successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer + 0x3 + + + + + SBX + source byte exchange within the unaligned half-word of each source word + + 13 + 1 + read-write + + + B_0x0 + no byte-based exchange within the unaligned half-word of each source word + 0x0 + + + B_0x1 + the two consecutive bytes within the unaligned half-word of each source word are exchanged. + 0x1 + + + + + SAP + source allocated port + + 14 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + SSEC + security attribute of the GPDMA transfer from the source + + 15 + 1 + read-write + + + B_0x0 + GPDMA transfer nonsecure + 0x0 + + + B_0x1 + GPDMA transfer secure + 0x1 + + + + + DDW_LOG2 + binary logarithm of the destination data width of a burst, in bytes + + 16 + 2 + read-write + + + B_0x0 + byte + 0x0 + + + B_0x1 + half-word (2 bytes) + 0x1 + + + B_0x2 + word (4 bytes) + 0x2 + + + B_0x3 + user setting error reported and no transfer issued + 0x3 + + + + + DINC + destination incrementing burst + + 19 + 1 + read-write + + + B_0x0 + fixed burst + 0x0 + + + B_0x1 + contiguously incremented burst + 0x1 + + + + + DBL_1 + destination burst length minus 1, between 0 and 63 + + 20 + 6 + read-write + + + DBX + destination byte exchange + + 26 + 1 + read-write + + + B_0x0 + no byte-based exchange within half-word + 0x0 + + + B_0x1 + the two consecutive (post PAM) bytes are exchanged in each destination half-word. + 0x1 + + + + + DHX + destination half-word exchange + + 27 + 1 + read-write + + + B_0x0 + no halfword-based exchanged within word + 0x0 + + + B_0x1 + the two consecutive (post PAM) half-words are exchanged in each destination word. + 0x1 + + + + + DAP + destination allocated port + + 30 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + DSEC + security attribute of the GPDMA transfer to the destination + + 31 + 1 + read-write + + + B_0x0 + GPDMA transfer nonsecure + 0x0 + + + B_0x1 + GPDMA transfer secure + 0x1 + + + + + + + GPDMA_C6TR2 + GPDMA_C6TR2 + GPDMA channel 6 transfer register 2 + 0x394 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + REQSEL + GPDMA hardware request selection + + 0 + 8 + read-write + + + SWREQ + software request + + 9 + 1 + read-write + + + B_0x0 + no software request. + 0x0 + + + B_0x1 + software request for a memory-to-memory transfer. + 0x1 + + + + + DREQ + destination hardware request + + 10 + 1 + read-write + + + B_0x0 + selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port) + 0x0 + + + B_0x1 + selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port) + 0x1 + + + + + BREQ + Block hardware request + + 11 + 1 + read-write + + + B_0x0 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level. + 0x0 + + + B_0x1 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 16. + 0x1 + + + + + PFREQ + Hardware request in peripheral flow control mode + + 12 + 1 + read-write + + + B_0x0 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. + 0x0 + + + B_0x1 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. + 0x1 + + + + + TRIGM + trigger mode + + 14 + 2 + read-write + + + B_0x0 + at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x (x = 6 to 7), for each block if a 2D/repeated block is configured with GPDMA_CxBR1. + 0x0 + + + B_0x1 + channel x (x = 0 to 5), same as 00; channel x (x = 6 to 7), at 2D/repeated block level. + 0x1 + + + B_0x2 + at link level: a LLI link transfer is conditioned by one hit trigger. + 0x2 + + + B_0x3 + at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. + 0x3 + + + + + TRIGSEL + trigger event input selection + + 16 + 6 + read-write + + + TRIGPOL + trigger event polarity + + 24 + 2 + read-write + + + B_0x0 + no trigger (masked trigger event) + 0x0 + + + B_0x1 + trigger on the rising edge + 0x1 + + + B_0x2 + trigger on the falling edge + 0x2 + + + B_0x3 + same as 00 + 0x3 + + + + + TCEM + transfer complete event mode + + 30 + 2 + read-write + + + B_0x0 + at block level (when GPDMA_CxBR1. + 0x0 + + + B_0x1 + channel x (x = 0 to 5), same as 00, channel x (x = 6 to 7), at 2D/repeated block level (when GPDMA_CxBR1. + 0x1 + + + B_0x2 + at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. + 0x2 + + + B_0x3 + at channel level: the complete transfer event is generated at the end of the last LLI transfer. + 0x3 + + + + + + + GPDMA_C6BR1 + GPDMA_C6BR1 + GPDMA channel 6 alternate block register 1 + 0x398 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BNDT + block number of data bytes to transfer from the source + + 0 + 16 + read-write + + + BRC + Block repeat counter + + 16 + 11 + read-write + + + SDEC + source address decrement + 28 + 1 + read-write + + + B_0x0 + At the end of a programmed burst transfer from the source, the GPDMA_CxSAR register is updated by adding the programmed offset GPDMA_CxTR3. + 0x0 + + + B_0x1 + At the end of a programmed burst transfer from the source, the GPDMA_CxSAR register is updated by subtracting the programmed offset GPDMA_CxTR3. + 0x1 + + + + + DDEC + destination address decrement + 29 + 1 + read-write + + + B_0x0 + At the end of a programmed burst transfer to the destination, the GPDMA_CxDAR register is updated by adding the programmed offset GPDMA_CxTR3. + 0x0 + + + B_0x1 + At the end of a programmed burst transfer to the destination, the GPDMA_CxDAR register is updated by subtracting the programmed offset GPDMA_CxTR3. + 0x1 + + + + + BRSDEC + Block repeat source address decrement + + 30 + 1 + read-write + + + B_0x0 + at the end of a block transfer, the GPDMA_CxSAR register is updated by adding the programmed offset GPDMA_CxBR2. + 0x0 + + + B_0x1 + at the end of a block transfer, the GPDMA_CxSAR register is updated by subtracting the programmed offset GPDMA_CxBR2. + 0x1 + + + + + BRDDEC + Block repeat destination address decrement + + 31 + 1 + read-write + + + B_0x0 + at the end of a block transfer, the GPDMA_CxDAR register is updated by adding the programmed offset GPDMA_CxBR2. + 0x0 + + + B_0x1 + at the end of a block transfer, the GPDMA_CxDAR register is updated by subtracting the programmed offset GPDMA_CxBR2. + 0x1 + + + + + + + GPDMA_C6SAR + GPDMA_C6SAR + GPDMA channel 6 source address register + 0x39C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SA + source address + + 0 + 32 + read-write + + + + + GPDMA_C6DAR + GPDMA_C6DAR + GPDMA channel 6 destination address register + 0x3A0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DA + destination address + + 0 + 32 + read-write + + + + + GPDMA_C6TR3 + GPDMA_C6TR3 + GPDMA channel 6 transfer register 3 + 0x3A4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SAO + source address offset increment + + 0 + 13 + read-write + + + DAO + destination address offset increment + + 16 + 13 + read-write + + + + + GPDMA_C6BR2 + GPDMA_C6BR2 + GPDMA channel 6 block register 2 + 0x3A8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BRSAO + Block repeated source address offset + + 0 + 16 + read-write + + + BRDAO + Block repeated destination address offset + + 16 + 16 + read-write + + + + + GPDMA_C6LLR + GPDMA_C6LLR + GPDMA channel 6 alternate linked-list address register + 0x3CC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LA + pointer (16-bit low-significant address) to the next linked-list data structure + + 2 + 14 + read-write + + + ULL + Update GPDMA_CxLLR register from memory + + 16 + 1 + read-write + + + B_0x0 + no GPDMA_CxLLR update + 0x0 + + + B_0x1 + GPDMA_CxLLR update + 0x1 + + + + + UB2 + Update GPDMA_CxBR2 from memory + + 25 + 1 + read-write + + + B_0x0 + no GPDMA_CxBR2 update + 0x0 + + + B_0x1 + GPDMA_CxBR2 update + 0x1 + + + + + UT3 + Update GPDMA_CxTR3 from memory + + 26 + 1 + read-write + + + B_0x0 + no GPDMA_CxTR3 update + 0x0 + + + B_0x1 + GPDMA_CxTR3 update + 0x1 + + + + + UDA + Update GPDMA_CxDAR register from memory + + 27 + 1 + read-write + + + B_0x0 + no GPDMA_CxDAR update + 0x0 + + + B_0x1 + GPDMA_CxDAR update + 0x1 + + + + + USA + update GPDMA_CxSAR from memory + + 28 + 1 + read-write + + + B_0x0 + no GPDMA_CxSAR update + 0x0 + + + B_0x1 + GPDMA_CxSAR update + 0x1 + + + + + UB1 + Update GPDMA_CxBR1 from memory + + 29 + 1 + read-write + + + B_0x0 + no GPDMA_CxBR1 update from memory (GPDMA_CxBR1. + 0x0 + + + B_0x1 + GPDMA_CxBR1 update + 0x1 + + + + + UT2 + Update GPDMA_CxTR2 from memory + + 30 + 1 + read-write + + + B_0x0 + no GPDMA_CxTR2 update + 0x0 + + + B_0x1 + GPDMA_CxTR2 update + 0x1 + + + + + UT1 + Update GPDMA_CxTR1 from memory + + 31 + 1 + read-write + + + B_0x0 + no GPDMA_CxTR1 update + 0x0 + + + B_0x1 + GPDMA_CxTR1 update + 0x1 + + + + + + + GPDMA_C7LBAR + GPDMA_C7LBAR + GPDMA channel 7 linked-list base address register + 0x3D0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LBA + linked-list base address of GPDMA channel x + 16 + 16 + read-write + + + + + GPDMA_C7FCR + GPDMA_C7FCR + GPDMA channel 7 flag clear register + 0x3DC + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + TCF + transfer complete flag clear + 8 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding TCF flag cleared + 0x1 + + + + + HTF + half transfer flag clear + 9 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding HTF flag cleared + 0x1 + + + + + DTEF + data transfer error flag clear + 10 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding DTEF flag cleared + 0x1 + + + + + ULEF + update link transfer error flag clear + 11 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding ULEF flag cleared + 0x1 + + + + + USEF + user setting error flag clear + 12 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding USEF flag cleared + 0x1 + + + + + SUSPF + completed suspension flag clear + 13 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding SUSPF flag cleared + 0x1 + + + + + TOF + trigger overrun flag clear + 14 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding TOF flag cleared + 0x1 + + + + + + + GPDMA_C7SR + GPDMA_C7SR + GPDMA channel 7 status register + 0x3E0 + 0x20 + read-only + 0x00000001 + 0xFFFFFFFF + + + IDLEF + idle flag + + 0 + 1 + read-only + + + B_0x0 + channel not in idle state + 0x0 + + + B_0x1 + channel in idle state + 0x1 + + + + + TCF + transfer complete flag + + 8 + 1 + read-only + + + B_0x0 + no transfer complete event + 0x0 + + + B_0x1 + a transfer complete event occurred + 0x1 + + + + + HTF + half transfer flag + + 9 + 1 + read-only + + + B_0x0 + no half transfer event + 0x0 + + + B_0x1 + a half transfer event occurred + 0x1 + + + + + DTEF + data transfer error flag + 10 + 1 + read-only + + + B_0x0 + no data transfer error event + 0x0 + + + B_0x1 + a master bus error event occurred on a data transfer + 0x1 + + + + + ULEF + update link transfer error flag + 11 + 1 + read-only + + + B_0x0 + no update link transfer error event + 0x0 + + + B_0x1 + a master bus error event occurred while updating a linked-list register from memory + 0x1 + + + + + USEF + user setting error flag + 12 + 1 + read-only + + + B_0x0 + no user setting error event + 0x0 + + + B_0x1 + a user setting error event occurred + 0x1 + + + + + SUSPF + completed suspension flag + 13 + 1 + read-only + + + B_0x0 + no completed suspension event + 0x0 + + + B_0x1 + a completed suspension event occurred + 0x1 + + + + + TOF + trigger overrun flag + 14 + 1 + read-only + + + B_0x0 + no trigger overrun event + 0x0 + + + B_0x1 + a trigger overrun event occurred + 0x1 + + + + + FIFOL + monitored FIFO level + + 16 + 8 + read-only + + + + + GPDMA_C7CR + GPDMA_C7CR + GPDMA channel 7 control register + 0x3E4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EN + enable + + 0 + 1 + read-write + + + B_0x0 + write: ignored, read: channel disabled + 0x0 + + + B_0x1 + write: enable channel, read: channel enabled + 0x1 + + + + + RESET + reset + + 1 + 1 + write-only + + + B_0x0 + no channel reset + 0x0 + + + B_0x1 + channel reset + 0x1 + + + + + SUSP + suspend + + 2 + 1 + read-write + + + B_0x0 + write: resume channel, read: channel not suspended + 0x0 + + + B_0x1 + write: suspend channel, read: channel suspended. + 0x1 + + + + + TCIE + transfer complete interrupt enable + 8 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + HTIE + half transfer complete interrupt enable + 9 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + DTEIE + data transfer error interrupt enable + 10 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + ULEIE + update link transfer error interrupt enable + 11 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + USEIE + user setting error interrupt enable + 12 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SUSPIE + completed suspension interrupt enable + 13 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TOIE + trigger overrun interrupt enable + 14 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + LSM + Link step mode + + 16 + 1 + read-write + + + B_0x0 + channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). + 0x0 + + + B_0x1 + channel executed once for the current LLI + 0x1 + + + + + LAP + linked-list allocated port + + 17 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + PRIO + priority level of the channel x GPDMA transfer versus others + + 22 + 2 + read-write + + + B_0x0 + low priority, low weight + 0x0 + + + B_0x1 + low priority, mid weight + 0x1 + + + B_0x2 + low priority, high weight + 0x2 + + + B_0x3 + high priority + 0x3 + + + + + + + GPDMA_C7TR1 + GPDMA_C7TR1 + GPDMA channel 7 transfer register 1 + 0x410 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SDW_LOG2 + binary logarithm of the source data width of a burst in bytes + + 0 + 2 + read-write + + + B_0x0 + byte + 0x0 + + + B_0x1 + half-word (2 bytes) + 0x1 + + + B_0x2 + word (4 bytes) + 0x2 + + + B_0x3 + user setting error reported and no transfer issued + 0x3 + + + + + SINC + source incrementing burst + + 3 + 1 + read-write + + + B_0x0 + fixed burst + 0x0 + + + B_0x1 + contiguously incremented burst + 0x1 + + + + + SBL_1 + source burst length minus 1, between 0 and 63 + + 4 + 6 + read-write + + + PAM + padding/alignment mode + + 11 + 2 + read-write + + + B_0x0_PAM_1 + source data is transferred as right aligned, padded with 0s up to the destination data width + 0x0 + + + B_0x1_PAM_1 + source data is transferred as right aligned, sign extended up to the destination data width + 0x1 + + + B_0x2_PAM_1 + successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer + 0x2 + + + B_0x3_PAM_1 + successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer + 0x3 + + + + + SBX + source byte exchange within the unaligned half-word of each source word + + 13 + 1 + read-write + + + B_0x0 + no byte-based exchange within the unaligned half-word of each source word + 0x0 + + + B_0x1 + the two consecutive bytes within the unaligned half-word of each source word are exchanged. + 0x1 + + + + + SAP + source allocated port + + 14 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + SSEC + security attribute of the GPDMA transfer from the source + + 15 + 1 + read-write + + + B_0x0 + GPDMA transfer nonsecure + 0x0 + + + B_0x1 + GPDMA transfer secure + 0x1 + + + + + DDW_LOG2 + binary logarithm of the destination data width of a burst, in bytes + + 16 + 2 + read-write + + + B_0x0 + byte + 0x0 + + + B_0x1 + half-word (2 bytes) + 0x1 + + + B_0x2 + word (4 bytes) + 0x2 + + + B_0x3 + user setting error reported and no transfer issued + 0x3 + + + + + DINC + destination incrementing burst + + 19 + 1 + read-write + + + B_0x0 + fixed burst + 0x0 + + + B_0x1 + contiguously incremented burst + 0x1 + + + + + DBL_1 + destination burst length minus 1, between 0 and 63 + + 20 + 6 + read-write + + + DBX + destination byte exchange + + 26 + 1 + read-write + + + B_0x0 + no byte-based exchange within half-word + 0x0 + + + B_0x1 + the two consecutive (post PAM) bytes are exchanged in each destination half-word. + 0x1 + + + + + DHX + destination half-word exchange + + 27 + 1 + read-write + + + B_0x0 + no halfword-based exchanged within word + 0x0 + + + B_0x1 + the two consecutive (post PAM) half-words are exchanged in each destination word. + 0x1 + + + + + DAP + destination allocated port + + 30 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + DSEC + security attribute of the GPDMA transfer to the destination + + 31 + 1 + read-write + + + B_0x0 + GPDMA transfer nonsecure + 0x0 + + + B_0x1 + GPDMA transfer secure + 0x1 + + + + + + + GPDMA_C7TR2 + GPDMA_C7TR2 + GPDMA channel 7 transfer register 2 + 0x414 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + REQSEL + GPDMA hardware request selection + + 0 + 8 + read-write + + + SWREQ + software request + + 9 + 1 + read-write + + + B_0x0 + no software request. + 0x0 + + + B_0x1 + software request for a memory-to-memory transfer. + 0x1 + + + + + DREQ + destination hardware request + + 10 + 1 + read-write + + + B_0x0 + selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port) + 0x0 + + + B_0x1 + selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port) + 0x1 + + + + + BREQ + Block hardware request + + 11 + 1 + read-write + + + B_0x0 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level. + 0x0 + + + B_0x1 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 16. + 0x1 + + + + + PFREQ + Hardware request in peripheral flow control mode + + 12 + 1 + read-write + + + B_0x0 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. + 0x0 + + + B_0x1 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. + 0x1 + + + + + TRIGM + trigger mode + + 14 + 2 + read-write + + + B_0x0 + at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x (x = 6 to 7), for each block if a 2D/repeated block is configured with GPDMA_CxBR1. + 0x0 + + + B_0x1 + channel x (x = 0 to 5), same as 00; channel x (x = 6 to 7), at 2D/repeated block level. + 0x1 + + + B_0x2 + at link level: a LLI link transfer is conditioned by one hit trigger. + 0x2 + + + B_0x3 + at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. + 0x3 + + + + + TRIGSEL + trigger event input selection + + 16 + 6 + read-write + + + TRIGPOL + trigger event polarity + + 24 + 2 + read-write + + + B_0x0 + no trigger (masked trigger event) + 0x0 + + + B_0x1 + trigger on the rising edge + 0x1 + + + B_0x2 + trigger on the falling edge + 0x2 + + + B_0x3 + same as 00 + 0x3 + + + + + TCEM + transfer complete event mode + + 30 + 2 + read-write + + + B_0x0 + at block level (when GPDMA_CxBR1. + 0x0 + + + B_0x1 + channel x (x = 0 to 5), same as 00, channel x (x = 6 to 7), at 2D/repeated block level (when GPDMA_CxBR1. + 0x1 + + + B_0x2 + at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. + 0x2 + + + B_0x3 + at channel level: the complete transfer event is generated at the end of the last LLI transfer. + 0x3 + + + + + + + GPDMA_C7BR1 + GPDMA_C7BR1 + GPDMA channel 7 alternate block register 1 + 0x418 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BNDT + block number of data bytes to transfer from the source + + 0 + 16 + read-write + + + BRC + Block repeat counter + + 16 + 11 + read-write + + + SDEC + source address decrement + 28 + 1 + read-write + + + B_0x0 + At the end of a programmed burst transfer from the source, the GPDMA_CxSAR register is updated by adding the programmed offset GPDMA_CxTR3. + 0x0 + + + B_0x1 + At the end of a programmed burst transfer from the source, the GPDMA_CxSAR register is updated by subtracting the programmed offset GPDMA_CxTR3. + 0x1 + + + + + DDEC + destination address decrement + 29 + 1 + read-write + + + B_0x0 + At the end of a programmed burst transfer to the destination, the GPDMA_CxDAR register is updated by adding the programmed offset GPDMA_CxTR3. + 0x0 + + + B_0x1 + At the end of a programmed burst transfer to the destination, the GPDMA_CxDAR register is updated by subtracting the programmed offset GPDMA_CxTR3. + 0x1 + + + + + BRSDEC + Block repeat source address decrement + + 30 + 1 + read-write + + + B_0x0 + at the end of a block transfer, the GPDMA_CxSAR register is updated by adding the programmed offset GPDMA_CxBR2. + 0x0 + + + B_0x1 + at the end of a block transfer, the GPDMA_CxSAR register is updated by subtracting the programmed offset GPDMA_CxBR2. + 0x1 + + + + + BRDDEC + Block repeat destination address decrement + + 31 + 1 + read-write + + + B_0x0 + at the end of a block transfer, the GPDMA_CxDAR register is updated by adding the programmed offset GPDMA_CxBR2. + 0x0 + + + B_0x1 + at the end of a block transfer, the GPDMA_CxDAR register is updated by subtracting the programmed offset GPDMA_CxBR2. + 0x1 + + + + + + + GPDMA_C7SAR + GPDMA_C7SAR + GPDMA channel 7 source address register + 0x41C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SA + source address + + 0 + 32 + read-write + + + + + GPDMA_C7DAR + GPDMA_C7DAR + GPDMA channel 7 destination address register + 0x420 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DA + destination address + + 0 + 32 + read-write + + + + + GPDMA_C7TR3 + GPDMA_C7TR3 + GPDMA channel 7 transfer register 3 + 0x424 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SAO + source address offset increment + + 0 + 13 + read-write + + + DAO + destination address offset increment + + 16 + 13 + read-write + + + + + GPDMA_C7BR2 + GPDMA_C7BR2 + GPDMA channel 7 block register 2 + 0x428 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BRSAO + Block repeated source address offset + + 0 + 16 + read-write + + + BRDAO + Block repeated destination address offset + + 16 + 16 + read-write + + + + + GPDMA_C7LLR + GPDMA_C7LLR + GPDMA channel 7 alternate linked-list address register + 0x44C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LA + pointer (16-bit low-significant address) to the next linked-list data structure + + 2 + 14 + read-write + + + ULL + Update GPDMA_CxLLR register from memory + + 16 + 1 + read-write + + + B_0x0 + no GPDMA_CxLLR update + 0x0 + + + B_0x1 + GPDMA_CxLLR update + 0x1 + + + + + UB2 + Update GPDMA_CxBR2 from memory + + 25 + 1 + read-write + + + B_0x0 + no GPDMA_CxBR2 update + 0x0 + + + B_0x1 + GPDMA_CxBR2 update + 0x1 + + + + + UT3 + Update GPDMA_CxTR3 from memory + + 26 + 1 + read-write + + + B_0x0 + no GPDMA_CxTR3 update + 0x0 + + + B_0x1 + GPDMA_CxTR3 update + 0x1 + + + + + UDA + Update GPDMA_CxDAR register from memory + + 27 + 1 + read-write + + + B_0x0 + no GPDMA_CxDAR update + 0x0 + + + B_0x1 + GPDMA_CxDAR update + 0x1 + + + + + USA + update GPDMA_CxSAR from memory + + 28 + 1 + read-write + + + B_0x0 + no GPDMA_CxSAR update + 0x0 + + + B_0x1 + GPDMA_CxSAR update + 0x1 + + + + + UB1 + Update GPDMA_CxBR1 from memory + + 29 + 1 + read-write + + + B_0x0 + no GPDMA_CxBR1 update from memory (GPDMA_CxBR1. + 0x0 + + + B_0x1 + GPDMA_CxBR1 update + 0x1 + + + + + UT2 + Update GPDMA_CxTR2 from memory + + 30 + 1 + read-write + + + B_0x0 + no GPDMA_CxTR2 update + 0x0 + + + B_0x1 + GPDMA_CxTR2 update + 0x1 + + + + + UT1 + Update GPDMA_CxTR1 from memory + + 31 + 1 + read-write + + + B_0x0 + no GPDMA_CxTR1 update + 0x0 + + + B_0x1 + GPDMA_CxTR1 update + 0x1 + + + + + + + + + GPDMA_S + 0x50020000 + + + GPDMA2 + 0X40021000 + + GPDMA2_CH7 + GPDMA2 channel7 global interrupt + 97 + + + GPDMA2_CH6 + GPDMA2 channel6 global interrupt + 96 + + + GPDMA2_CH5 + GPDMA2 channel5 global interrupt + 95 + + + GPDMA2_CH4 + GPDMA2 channel4 global interrupt + 94 + + + GPDMA2_CH3 + GPDMA2 channe3 global interrupt + 93 + + + GPDMA2_CH2 + GPDMA2 channel2 global interrupt + 92 + + + GPDMA2_CH1 + GPDMA2 channel1 global interrupt + 91 + + + GPDMA2_CH0 + GPDMA2 channel0 global interrupt + 90 + + + + GPDMA2_S + 0X50021000 + + + GPIOA + GPIOA address block description + GPIOA + 0x42020000 + + 0x0 + 0x34 + registers + + + + GPIOA_MODER + GPIOA_MODER + GPIO port mode register + 0x00 + 0x20 + read-write + 0x00FFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + + + GPIOA_OTYPER + GPIOA_OTYPER + GPIO port output type register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y + + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y + + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y + + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y + + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y + + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y + + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y + + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y + + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y + + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y + + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y + + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y + + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y + + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y + + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y + + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y + + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIOA_OSPEEDR + GPIOA_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + + + GPIOA_PUPDR + GPIOA_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + GPIOA_IDR + GPIOA_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O pin y + + 0 + 1 + read-only + + + ID1 + Port x input data I/O pin y + + 1 + 1 + read-only + + + ID2 + Port x input data I/O pin y + + 2 + 1 + read-only + + + ID3 + Port x input data I/O pin y + + 3 + 1 + read-only + + + ID4 + Port x input data I/O pin y + + 4 + 1 + read-only + + + ID5 + Port x input data I/O pin y + + 5 + 1 + read-only + + + ID6 + Port x input data I/O pin y + + 6 + 1 + read-only + + + ID7 + Port x input data I/O pin y + + 7 + 1 + read-only + + + ID8 + Port x input data I/O pin y + + 8 + 1 + read-only + + + ID9 + Port x input data I/O pin y + + 9 + 1 + read-only + + + ID10 + Port x input data I/O pin y + + 10 + 1 + read-only + + + ID11 + Port x input data I/O pin y + + 11 + 1 + read-only + + + ID12 + Port x input data I/O pin y + + 12 + 1 + read-only + + + ID13 + Port x input data I/O pin y + + 13 + 1 + read-only + + + ID14 + Port x input data I/O pin y + + 14 + 1 + read-only + + + ID15 + Port x input data I/O pin y + + 15 + 1 + read-only + + + + + GPIOA_ODR + GPIOA_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O pin y + + 0 + 1 + read-write + + + OD1 + Port output data I/O pin y + + 1 + 1 + read-write + + + OD2 + Port output data I/O pin y + + 2 + 1 + read-write + + + OD3 + Port output data I/O pin y + + 3 + 1 + read-write + + + OD4 + Port output data I/O pin y + + 4 + 1 + read-write + + + OD5 + Port output data I/O pin y + + 5 + 1 + read-write + + + OD6 + Port output data I/O pin y + + 6 + 1 + read-write + + + OD7 + Port output data I/O pin y + + 7 + 1 + read-write + + + OD8 + Port output data I/O pin y + + 8 + 1 + read-write + + + OD9 + Port output data I/O pin y + + 9 + 1 + read-write + + + OD10 + Port output data I/O pin y + + 10 + 1 + read-write + + + OD11 + Port output data I/O pin y + + 11 + 1 + read-write + + + OD12 + Port output data I/O pin y + + 12 + 1 + read-write + + + OD13 + Port output data I/O pin y + + 13 + 1 + read-write + + + OD14 + Port output data I/O pin y + + 14 + 1 + read-write + + + OD15 + Port output data I/O pin y + + 15 + 1 + read-write + + + + + GPIOA_BSRR + GPIOA_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y + + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS1 + Port x set I/O pin y + + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS2 + Port x set I/O pin y + + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS3 + Port x set I/O pin y + + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS4 + Port x set I/O pin y + + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS5 + Port x set I/O pin y + + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS6 + Port x set I/O pin y + + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS7 + Port x set I/O pin y + + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS8 + Port x set I/O pin y + + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS9 + Port x set I/O pin y + + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS10 + Port x set I/O pin y + + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS11 + Port x set I/O pin y + + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS12 + Port x set I/O pin y + + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS13 + Port x set I/O pin y + + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS14 + Port x set I/O pin y + + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS15 + Port x set I/O pin y + + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BR0 + Port x reset I/O pin y + + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset I/O pin y + + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset I/O pin y + + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset I/O pin y + + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset I/O pin y + + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset I/O pin y + + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset I/O pin y + + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset I/O pin y + + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset I/O pin y + + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset I/O pin y + + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset I/O pin y + + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset I/O pin y + + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset I/O pin y + + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset I/O pin y + + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset I/O pin y + + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset I/O pin y + + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + + + GPIOA_LCKR + GPIOA_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y + + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y + + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y + + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y + + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y + + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y + + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y + + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y + + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y + + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y + + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y + + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y + + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y + + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y + + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y + + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y + + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key + + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. + 0x1 + + + + + + + GPIOA_AFRL + GPIOA_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x I/O pin y + + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x I/O pin y + + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x I/O pin y + + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x I/O pin y + + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x I/O pin y + + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x I/O pin y + + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x I/O pin y + + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x I/O pin y + + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOA_AFRH + GPIOA_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x I/O pin y + + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x I/O pin y + + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x I/O pin y + + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x I/O pin y + + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x I/O pin y + + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x I/O pin y + + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x I/O pin y + + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x I/O pin y + + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOA_BRR + GPIOA_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y + + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset IO pin y + + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset IO pin y + + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset IO pin y + + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset IO pin y + + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset IO pin y + + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset IO pin y + + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset IO pin y + + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset IO pin y + + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset IO pin y + + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset IO pin y + + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset IO pin y + + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset IO pin y + + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset IO pin y + + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset IO pin y + + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset IO pin y + + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + + + GPIOA_HSLVR + GPIOA_HSLVR + GPIO high-speed low-voltage register + 0x2C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + HSLV0 + Port x high-speed low-voltage configuration + + 0 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV1 + Port x high-speed low-voltage configuration + + 1 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV2 + Port x high-speed low-voltage configuration + + 2 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV3 + Port x high-speed low-voltage configuration + + 3 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV4 + Port x high-speed low-voltage configuration + + 4 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV5 + Port x high-speed low-voltage configuration + + 5 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV6 + Port x high-speed low-voltage configuration + + 6 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV7 + Port x high-speed low-voltage configuration + + 7 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV8 + Port x high-speed low-voltage configuration + + 8 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV9 + Port x high-speed low-voltage configuration + + 9 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV10 + Port x high-speed low-voltage configuration + + 10 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV11 + Port x high-speed low-voltage configuration + + 11 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV12 + Port x high-speed low-voltage configuration + + 12 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV13 + Port x high-speed low-voltage configuration + + 13 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV14 + Port x high-speed low-voltage configuration + + 14 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV15 + Port x high-speed low-voltage configuration + + 15 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + + + GPIOA_SECCFGR + GPIOA_SECCFGR + GPIO secure configuration register + 0x30 + 0x20 + read-write + 0x00000FFF + 0xFFFFFFFF + + + SEC0 + I/O pin of Port x secure bit enable y + + 0 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC1 + I/O pin of Port x secure bit enable y + + 1 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC2 + I/O pin of Port x secure bit enable y + + 2 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC3 + I/O pin of Port x secure bit enable y + + 3 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC4 + I/O pin of Port x secure bit enable y + + 4 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC5 + I/O pin of Port x secure bit enable y + + 5 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC6 + I/O pin of Port x secure bit enable y + + 6 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC7 + I/O pin of Port x secure bit enable y + + 7 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC8 + I/O pin of Port x secure bit enable y + + 8 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC9 + I/O pin of Port x secure bit enable y + + 9 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC10 + I/O pin of Port x secure bit enable y + + 10 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC11 + I/O pin of Port x secure bit enable y + + 11 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC12 + I/O pin of Port x secure bit enable y + + 12 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC13 + I/O pin of Port x secure bit enable y + + 13 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC14 + I/O pin of Port x secure bit enable y + + 14 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC15 + I/O pin of Port x secure bit enable y + + 15 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + + + + + GPIOA_S + 0X52020000 + + + GPIOB + GPIOB address block description + GPIOB + 0x42020400 + + 0x0 + 0x34 + registers + + + + GPIOB_MODER + GPIOB_MODER + GPIO port mode register + 0x00 + 0x20 + read-write + 0x00FFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + + + GPIOB_OTYPER + GPIOB_OTYPER + GPIO port output type register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y + + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y + + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y + + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y + + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y + + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y + + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y + + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y + + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y + + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y + + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y + + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y + + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y + + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y + + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y + + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y + + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIOB_OSPEEDR + GPIOB_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + + + GPIOB_PUPDR + GPIOB_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + GPIOB_IDR + GPIOB_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O pin y + + 0 + 1 + read-only + + + ID1 + Port x input data I/O pin y + + 1 + 1 + read-only + + + ID2 + Port x input data I/O pin y + + 2 + 1 + read-only + + + ID3 + Port x input data I/O pin y + + 3 + 1 + read-only + + + ID4 + Port x input data I/O pin y + + 4 + 1 + read-only + + + ID5 + Port x input data I/O pin y + + 5 + 1 + read-only + + + ID6 + Port x input data I/O pin y + + 6 + 1 + read-only + + + ID7 + Port x input data I/O pin y + + 7 + 1 + read-only + + + ID8 + Port x input data I/O pin y + + 8 + 1 + read-only + + + ID9 + Port x input data I/O pin y + + 9 + 1 + read-only + + + ID10 + Port x input data I/O pin y + + 10 + 1 + read-only + + + ID11 + Port x input data I/O pin y + + 11 + 1 + read-only + + + ID12 + Port x input data I/O pin y + + 12 + 1 + read-only + + + ID13 + Port x input data I/O pin y + + 13 + 1 + read-only + + + ID14 + Port x input data I/O pin y + + 14 + 1 + read-only + + + ID15 + Port x input data I/O pin y + + 15 + 1 + read-only + + + + + GPIOB_ODR + GPIOB_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O pin y + + 0 + 1 + read-write + + + OD1 + Port output data I/O pin y + + 1 + 1 + read-write + + + OD2 + Port output data I/O pin y + + 2 + 1 + read-write + + + OD3 + Port output data I/O pin y + + 3 + 1 + read-write + + + OD4 + Port output data I/O pin y + + 4 + 1 + read-write + + + OD5 + Port output data I/O pin y + + 5 + 1 + read-write + + + OD6 + Port output data I/O pin y + + 6 + 1 + read-write + + + OD7 + Port output data I/O pin y + + 7 + 1 + read-write + + + OD8 + Port output data I/O pin y + + 8 + 1 + read-write + + + OD9 + Port output data I/O pin y + + 9 + 1 + read-write + + + OD10 + Port output data I/O pin y + + 10 + 1 + read-write + + + OD11 + Port output data I/O pin y + + 11 + 1 + read-write + + + OD12 + Port output data I/O pin y + + 12 + 1 + read-write + + + OD13 + Port output data I/O pin y + + 13 + 1 + read-write + + + OD14 + Port output data I/O pin y + + 14 + 1 + read-write + + + OD15 + Port output data I/O pin y + + 15 + 1 + read-write + + + + + GPIOB_BSRR + GPIOB_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y + + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS1 + Port x set I/O pin y + + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS2 + Port x set I/O pin y + + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS3 + Port x set I/O pin y + + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS4 + Port x set I/O pin y + + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS5 + Port x set I/O pin y + + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS6 + Port x set I/O pin y + + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS7 + Port x set I/O pin y + + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS8 + Port x set I/O pin y + + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS9 + Port x set I/O pin y + + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS10 + Port x set I/O pin y + + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS11 + Port x set I/O pin y + + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS12 + Port x set I/O pin y + + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS13 + Port x set I/O pin y + + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS14 + Port x set I/O pin y + + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS15 + Port x set I/O pin y + + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BR0 + Port x reset I/O pin y + + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset I/O pin y + + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset I/O pin y + + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset I/O pin y + + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset I/O pin y + + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset I/O pin y + + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset I/O pin y + + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset I/O pin y + + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset I/O pin y + + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset I/O pin y + + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset I/O pin y + + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset I/O pin y + + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset I/O pin y + + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset I/O pin y + + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset I/O pin y + + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset I/O pin y + + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + + + GPIOB_LCKR + GPIOB_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y + + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y + + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y + + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y + + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y + + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y + + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y + + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y + + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y + + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y + + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y + + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y + + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y + + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y + + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y + + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y + + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key + + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. + 0x1 + + + + + + + GPIOB_AFRL + GPIOB_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x I/O pin y + + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x I/O pin y + + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x I/O pin y + + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x I/O pin y + + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x I/O pin y + + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x I/O pin y + + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x I/O pin y + + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x I/O pin y + + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOB_AFRH + GPIOB_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x I/O pin y + + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x I/O pin y + + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x I/O pin y + + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x I/O pin y + + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x I/O pin y + + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x I/O pin y + + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x I/O pin y + + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x I/O pin y + + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOB_BRR + GPIOB_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y + + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset IO pin y + + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset IO pin y + + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset IO pin y + + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset IO pin y + + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset IO pin y + + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset IO pin y + + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset IO pin y + + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset IO pin y + + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset IO pin y + + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset IO pin y + + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset IO pin y + + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset IO pin y + + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset IO pin y + + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset IO pin y + + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset IO pin y + + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + + + GPIOB_HSLVR + GPIOB_HSLVR + GPIO high-speed low-voltage register + 0x2C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + HSLV0 + Port x high-speed low-voltage configuration + + 0 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV1 + Port x high-speed low-voltage configuration + + 1 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV2 + Port x high-speed low-voltage configuration + + 2 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV3 + Port x high-speed low-voltage configuration + + 3 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV4 + Port x high-speed low-voltage configuration + + 4 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV5 + Port x high-speed low-voltage configuration + + 5 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV6 + Port x high-speed low-voltage configuration + + 6 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV7 + Port x high-speed low-voltage configuration + + 7 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV8 + Port x high-speed low-voltage configuration + + 8 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV9 + Port x high-speed low-voltage configuration + + 9 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV10 + Port x high-speed low-voltage configuration + + 10 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV11 + Port x high-speed low-voltage configuration + + 11 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV12 + Port x high-speed low-voltage configuration + + 12 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV13 + Port x high-speed low-voltage configuration + + 13 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV14 + Port x high-speed low-voltage configuration + + 14 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV15 + Port x high-speed low-voltage configuration + + 15 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + + + GPIOB_SECCFGR + GPIOB_SECCFGR + GPIO secure configuration register + 0x30 + 0x20 + read-write + 0x00000FFF + 0xFFFFFFFF + + + SEC0 + I/O pin of Port x secure bit enable y + + 0 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC1 + I/O pin of Port x secure bit enable y + + 1 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC2 + I/O pin of Port x secure bit enable y + + 2 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC3 + I/O pin of Port x secure bit enable y + + 3 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC4 + I/O pin of Port x secure bit enable y + + 4 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC5 + I/O pin of Port x secure bit enable y + + 5 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC6 + I/O pin of Port x secure bit enable y + + 6 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC7 + I/O pin of Port x secure bit enable y + + 7 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC8 + I/O pin of Port x secure bit enable y + + 8 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC9 + I/O pin of Port x secure bit enable y + + 9 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC10 + I/O pin of Port x secure bit enable y + + 10 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC11 + I/O pin of Port x secure bit enable y + + 11 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC12 + I/O pin of Port x secure bit enable y + + 12 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC13 + I/O pin of Port x secure bit enable y + + 13 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC14 + I/O pin of Port x secure bit enable y + + 14 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC15 + I/O pin of Port x secure bit enable y + + 15 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + + + + + GPIOB_S + 0X52020400 + + + GPIOC + GPIOC address block description + GPIOC + 0x42020800 + + 0x0 + 0x34 + registers + + + + GPIOC_MODER + GPIOC_MODER + GPIO port mode register + 0x00 + 0x20 + read-write + 0x00FFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + + + GPIOC_OTYPER + GPIOC_OTYPER + GPIO port output type register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y + + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y + + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y + + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y + + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y + + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y + + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y + + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y + + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y + + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y + + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y + + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y + + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y + + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y + + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y + + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y + + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIOC_OSPEEDR + GPIOC_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + + + GPIOC_PUPDR + GPIOC_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + GPIOC_IDR + GPIOC_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O pin y + + 0 + 1 + read-only + + + ID1 + Port x input data I/O pin y + + 1 + 1 + read-only + + + ID2 + Port x input data I/O pin y + + 2 + 1 + read-only + + + ID3 + Port x input data I/O pin y + + 3 + 1 + read-only + + + ID4 + Port x input data I/O pin y + + 4 + 1 + read-only + + + ID5 + Port x input data I/O pin y + + 5 + 1 + read-only + + + ID6 + Port x input data I/O pin y + + 6 + 1 + read-only + + + ID7 + Port x input data I/O pin y + + 7 + 1 + read-only + + + ID8 + Port x input data I/O pin y + + 8 + 1 + read-only + + + ID9 + Port x input data I/O pin y + + 9 + 1 + read-only + + + ID10 + Port x input data I/O pin y + + 10 + 1 + read-only + + + ID11 + Port x input data I/O pin y + + 11 + 1 + read-only + + + ID12 + Port x input data I/O pin y + + 12 + 1 + read-only + + + ID13 + Port x input data I/O pin y + + 13 + 1 + read-only + + + ID14 + Port x input data I/O pin y + + 14 + 1 + read-only + + + ID15 + Port x input data I/O pin y + + 15 + 1 + read-only + + + + + GPIOC_ODR + GPIOC_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O pin y + + 0 + 1 + read-write + + + OD1 + Port output data I/O pin y + + 1 + 1 + read-write + + + OD2 + Port output data I/O pin y + + 2 + 1 + read-write + + + OD3 + Port output data I/O pin y + + 3 + 1 + read-write + + + OD4 + Port output data I/O pin y + + 4 + 1 + read-write + + + OD5 + Port output data I/O pin y + + 5 + 1 + read-write + + + OD6 + Port output data I/O pin y + + 6 + 1 + read-write + + + OD7 + Port output data I/O pin y + + 7 + 1 + read-write + + + OD8 + Port output data I/O pin y + + 8 + 1 + read-write + + + OD9 + Port output data I/O pin y + + 9 + 1 + read-write + + + OD10 + Port output data I/O pin y + + 10 + 1 + read-write + + + OD11 + Port output data I/O pin y + + 11 + 1 + read-write + + + OD12 + Port output data I/O pin y + + 12 + 1 + read-write + + + OD13 + Port output data I/O pin y + + 13 + 1 + read-write + + + OD14 + Port output data I/O pin y + + 14 + 1 + read-write + + + OD15 + Port output data I/O pin y + + 15 + 1 + read-write + + + + + GPIOC_BSRR + GPIOC_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y + + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS1 + Port x set I/O pin y + + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS2 + Port x set I/O pin y + + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS3 + Port x set I/O pin y + + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS4 + Port x set I/O pin y + + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS5 + Port x set I/O pin y + + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS6 + Port x set I/O pin y + + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS7 + Port x set I/O pin y + + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS8 + Port x set I/O pin y + + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS9 + Port x set I/O pin y + + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS10 + Port x set I/O pin y + + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS11 + Port x set I/O pin y + + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS12 + Port x set I/O pin y + + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS13 + Port x set I/O pin y + + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS14 + Port x set I/O pin y + + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS15 + Port x set I/O pin y + + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BR0 + Port x reset I/O pin y + + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset I/O pin y + + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset I/O pin y + + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset I/O pin y + + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset I/O pin y + + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset I/O pin y + + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset I/O pin y + + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset I/O pin y + + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset I/O pin y + + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset I/O pin y + + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset I/O pin y + + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset I/O pin y + + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset I/O pin y + + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset I/O pin y + + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset I/O pin y + + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset I/O pin y + + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + + + GPIOC_LCKR + GPIOC_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y + + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y + + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y + + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y + + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y + + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y + + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y + + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y + + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y + + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y + + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y + + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y + + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y + + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y + + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y + + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y + + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key + + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. + 0x1 + + + + + + + GPIOC_AFRL + GPIOC_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x I/O pin y + + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x I/O pin y + + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x I/O pin y + + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x I/O pin y + + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x I/O pin y + + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x I/O pin y + + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x I/O pin y + + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x I/O pin y + + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOC_AFRH + GPIOC_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x I/O pin y + + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x I/O pin y + + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x I/O pin y + + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x I/O pin y + + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x I/O pin y + + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x I/O pin y + + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x I/O pin y + + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x I/O pin y + + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOC_BRR + GPIOC_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y + + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset IO pin y + + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset IO pin y + + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset IO pin y + + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset IO pin y + + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset IO pin y + + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset IO pin y + + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset IO pin y + + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset IO pin y + + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset IO pin y + + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset IO pin y + + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset IO pin y + + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset IO pin y + + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset IO pin y + + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset IO pin y + + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset IO pin y + + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + + + GPIOC_HSLVR + GPIOC_HSLVR + GPIO high-speed low-voltage register + 0x2C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + HSLV0 + Port x high-speed low-voltage configuration + + 0 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV1 + Port x high-speed low-voltage configuration + + 1 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV2 + Port x high-speed low-voltage configuration + + 2 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV3 + Port x high-speed low-voltage configuration + + 3 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV4 + Port x high-speed low-voltage configuration + + 4 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV5 + Port x high-speed low-voltage configuration + + 5 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV6 + Port x high-speed low-voltage configuration + + 6 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV7 + Port x high-speed low-voltage configuration + + 7 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV8 + Port x high-speed low-voltage configuration + + 8 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV9 + Port x high-speed low-voltage configuration + + 9 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV10 + Port x high-speed low-voltage configuration + + 10 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV11 + Port x high-speed low-voltage configuration + + 11 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV12 + Port x high-speed low-voltage configuration + + 12 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV13 + Port x high-speed low-voltage configuration + + 13 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV14 + Port x high-speed low-voltage configuration + + 14 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV15 + Port x high-speed low-voltage configuration + + 15 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + + + GPIOC_SECCFGR + GPIOC_SECCFGR + GPIO secure configuration register + 0x30 + 0x20 + read-write + 0x00000FFF + 0xFFFFFFFF + + + SEC0 + I/O pin of Port x secure bit enable y + + 0 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC1 + I/O pin of Port x secure bit enable y + + 1 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC2 + I/O pin of Port x secure bit enable y + + 2 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC3 + I/O pin of Port x secure bit enable y + + 3 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC4 + I/O pin of Port x secure bit enable y + + 4 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC5 + I/O pin of Port x secure bit enable y + + 5 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC6 + I/O pin of Port x secure bit enable y + + 6 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC7 + I/O pin of Port x secure bit enable y + + 7 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC8 + I/O pin of Port x secure bit enable y + + 8 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC9 + I/O pin of Port x secure bit enable y + + 9 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC10 + I/O pin of Port x secure bit enable y + + 10 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC11 + I/O pin of Port x secure bit enable y + + 11 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC12 + I/O pin of Port x secure bit enable y + + 12 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC13 + I/O pin of Port x secure bit enable y + + 13 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC14 + I/O pin of Port x secure bit enable y + + 14 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC15 + I/O pin of Port x secure bit enable y + + 15 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + + + + + GPIOC_S + 0X52020800 + + + GPIOD + GPIOD address block description + GPIOD + 0x42020c00 + + 0x0 + 0x34 + registers + + + + GPIOD_MODER + GPIOD_MODER + GPIO port mode register + 0x00 + 0x20 + read-write + 0x00FFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + + + GPIOD_OTYPER + GPIOD_OTYPER + GPIO port output type register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y + + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y + + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y + + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y + + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y + + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y + + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y + + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y + + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y + + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y + + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y + + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y + + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y + + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y + + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y + + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y + + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIOD_OSPEEDR + GPIOD_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + + + GPIOD_PUPDR + GPIOD_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + GPIOD_IDR + GPIOD_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O pin y + + 0 + 1 + read-only + + + ID1 + Port x input data I/O pin y + + 1 + 1 + read-only + + + ID2 + Port x input data I/O pin y + + 2 + 1 + read-only + + + ID3 + Port x input data I/O pin y + + 3 + 1 + read-only + + + ID4 + Port x input data I/O pin y + + 4 + 1 + read-only + + + ID5 + Port x input data I/O pin y + + 5 + 1 + read-only + + + ID6 + Port x input data I/O pin y + + 6 + 1 + read-only + + + ID7 + Port x input data I/O pin y + + 7 + 1 + read-only + + + ID8 + Port x input data I/O pin y + + 8 + 1 + read-only + + + ID9 + Port x input data I/O pin y + + 9 + 1 + read-only + + + ID10 + Port x input data I/O pin y + + 10 + 1 + read-only + + + ID11 + Port x input data I/O pin y + + 11 + 1 + read-only + + + ID12 + Port x input data I/O pin y + + 12 + 1 + read-only + + + ID13 + Port x input data I/O pin y + + 13 + 1 + read-only + + + ID14 + Port x input data I/O pin y + + 14 + 1 + read-only + + + ID15 + Port x input data I/O pin y + + 15 + 1 + read-only + + + + + GPIOD_ODR + GPIOD_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O pin y + + 0 + 1 + read-write + + + OD1 + Port output data I/O pin y + + 1 + 1 + read-write + + + OD2 + Port output data I/O pin y + + 2 + 1 + read-write + + + OD3 + Port output data I/O pin y + + 3 + 1 + read-write + + + OD4 + Port output data I/O pin y + + 4 + 1 + read-write + + + OD5 + Port output data I/O pin y + + 5 + 1 + read-write + + + OD6 + Port output data I/O pin y + + 6 + 1 + read-write + + + OD7 + Port output data I/O pin y + + 7 + 1 + read-write + + + OD8 + Port output data I/O pin y + + 8 + 1 + read-write + + + OD9 + Port output data I/O pin y + + 9 + 1 + read-write + + + OD10 + Port output data I/O pin y + + 10 + 1 + read-write + + + OD11 + Port output data I/O pin y + + 11 + 1 + read-write + + + OD12 + Port output data I/O pin y + + 12 + 1 + read-write + + + OD13 + Port output data I/O pin y + + 13 + 1 + read-write + + + OD14 + Port output data I/O pin y + + 14 + 1 + read-write + + + OD15 + Port output data I/O pin y + + 15 + 1 + read-write + + + + + GPIOD_BSRR + GPIOD_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y + + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS1 + Port x set I/O pin y + + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS2 + Port x set I/O pin y + + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS3 + Port x set I/O pin y + + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS4 + Port x set I/O pin y + + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS5 + Port x set I/O pin y + + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS6 + Port x set I/O pin y + + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS7 + Port x set I/O pin y + + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS8 + Port x set I/O pin y + + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS9 + Port x set I/O pin y + + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS10 + Port x set I/O pin y + + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS11 + Port x set I/O pin y + + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS12 + Port x set I/O pin y + + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS13 + Port x set I/O pin y + + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS14 + Port x set I/O pin y + + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS15 + Port x set I/O pin y + + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BR0 + Port x reset I/O pin y + + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset I/O pin y + + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset I/O pin y + + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset I/O pin y + + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset I/O pin y + + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset I/O pin y + + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset I/O pin y + + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset I/O pin y + + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset I/O pin y + + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset I/O pin y + + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset I/O pin y + + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset I/O pin y + + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset I/O pin y + + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset I/O pin y + + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset I/O pin y + + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset I/O pin y + + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + + + GPIOD_LCKR + GPIOD_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y + + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y + + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y + + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y + + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y + + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y + + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y + + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y + + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y + + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y + + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y + + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y + + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y + + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y + + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y + + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y + + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key + + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. + 0x1 + + + + + + + GPIOD_AFRL + GPIOD_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x I/O pin y + + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x I/O pin y + + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x I/O pin y + + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x I/O pin y + + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x I/O pin y + + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x I/O pin y + + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x I/O pin y + + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x I/O pin y + + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOD_AFRH + GPIOD_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x I/O pin y + + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x I/O pin y + + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x I/O pin y + + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x I/O pin y + + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x I/O pin y + + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x I/O pin y + + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x I/O pin y + + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x I/O pin y + + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOD_BRR + GPIOD_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y + + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset IO pin y + + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset IO pin y + + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset IO pin y + + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset IO pin y + + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset IO pin y + + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset IO pin y + + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset IO pin y + + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset IO pin y + + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset IO pin y + + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset IO pin y + + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset IO pin y + + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset IO pin y + + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset IO pin y + + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset IO pin y + + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset IO pin y + + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + + + GPIOD_HSLVR + GPIOD_HSLVR + GPIO high-speed low-voltage register + 0x2C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + HSLV0 + Port x high-speed low-voltage configuration + + 0 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV1 + Port x high-speed low-voltage configuration + + 1 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV2 + Port x high-speed low-voltage configuration + + 2 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV3 + Port x high-speed low-voltage configuration + + 3 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV4 + Port x high-speed low-voltage configuration + + 4 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV5 + Port x high-speed low-voltage configuration + + 5 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV6 + Port x high-speed low-voltage configuration + + 6 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV7 + Port x high-speed low-voltage configuration + + 7 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV8 + Port x high-speed low-voltage configuration + + 8 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV9 + Port x high-speed low-voltage configuration + + 9 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV10 + Port x high-speed low-voltage configuration + + 10 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV11 + Port x high-speed low-voltage configuration + + 11 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV12 + Port x high-speed low-voltage configuration + + 12 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV13 + Port x high-speed low-voltage configuration + + 13 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV14 + Port x high-speed low-voltage configuration + + 14 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV15 + Port x high-speed low-voltage configuration + + 15 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + + + GPIOD_SECCFGR + GPIOD_SECCFGR + GPIO secure configuration register + 0x30 + 0x20 + read-write + 0x00000FFF + 0xFFFFFFFF + + + SEC0 + I/O pin of Port x secure bit enable y + + 0 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC1 + I/O pin of Port x secure bit enable y + + 1 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC2 + I/O pin of Port x secure bit enable y + + 2 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC3 + I/O pin of Port x secure bit enable y + + 3 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC4 + I/O pin of Port x secure bit enable y + + 4 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC5 + I/O pin of Port x secure bit enable y + + 5 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC6 + I/O pin of Port x secure bit enable y + + 6 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC7 + I/O pin of Port x secure bit enable y + + 7 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC8 + I/O pin of Port x secure bit enable y + + 8 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC9 + I/O pin of Port x secure bit enable y + + 9 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC10 + I/O pin of Port x secure bit enable y + + 10 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC11 + I/O pin of Port x secure bit enable y + + 11 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC12 + I/O pin of Port x secure bit enable y + + 12 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC13 + I/O pin of Port x secure bit enable y + + 13 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC14 + I/O pin of Port x secure bit enable y + + 14 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC15 + I/O pin of Port x secure bit enable y + + 15 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + + + + + GPIOD_S + 0X52020C00 + + + GPIOE + GPIOE address block description + GPIOE + 0x42021000 + + 0x0 + 0x34 + registers + + + + GPIOE_MODER + GPIOE_MODER + GPIO port mode register + 0x00 + 0x20 + read-write + 0x00FFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + + + GPIOE_OTYPER + GPIOE_OTYPER + GPIO port output type register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y + + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y + + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y + + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y + + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y + + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y + + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y + + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y + + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y + + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y + + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y + + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y + + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y + + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y + + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y + + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y + + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIOE_OSPEEDR + GPIOE_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + + + GPIOE_PUPDR + GPIOE_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + GPIOE_IDR + GPIOE_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O pin y + + 0 + 1 + read-only + + + ID1 + Port x input data I/O pin y + + 1 + 1 + read-only + + + ID2 + Port x input data I/O pin y + + 2 + 1 + read-only + + + ID3 + Port x input data I/O pin y + + 3 + 1 + read-only + + + ID4 + Port x input data I/O pin y + + 4 + 1 + read-only + + + ID5 + Port x input data I/O pin y + + 5 + 1 + read-only + + + ID6 + Port x input data I/O pin y + + 6 + 1 + read-only + + + ID7 + Port x input data I/O pin y + + 7 + 1 + read-only + + + ID8 + Port x input data I/O pin y + + 8 + 1 + read-only + + + ID9 + Port x input data I/O pin y + + 9 + 1 + read-only + + + ID10 + Port x input data I/O pin y + + 10 + 1 + read-only + + + ID11 + Port x input data I/O pin y + + 11 + 1 + read-only + + + ID12 + Port x input data I/O pin y + + 12 + 1 + read-only + + + ID13 + Port x input data I/O pin y + + 13 + 1 + read-only + + + ID14 + Port x input data I/O pin y + + 14 + 1 + read-only + + + ID15 + Port x input data I/O pin y + + 15 + 1 + read-only + + + + + GPIOE_ODR + GPIOE_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O pin y + + 0 + 1 + read-write + + + OD1 + Port output data I/O pin y + + 1 + 1 + read-write + + + OD2 + Port output data I/O pin y + + 2 + 1 + read-write + + + OD3 + Port output data I/O pin y + + 3 + 1 + read-write + + + OD4 + Port output data I/O pin y + + 4 + 1 + read-write + + + OD5 + Port output data I/O pin y + + 5 + 1 + read-write + + + OD6 + Port output data I/O pin y + + 6 + 1 + read-write + + + OD7 + Port output data I/O pin y + + 7 + 1 + read-write + + + OD8 + Port output data I/O pin y + + 8 + 1 + read-write + + + OD9 + Port output data I/O pin y + + 9 + 1 + read-write + + + OD10 + Port output data I/O pin y + + 10 + 1 + read-write + + + OD11 + Port output data I/O pin y + + 11 + 1 + read-write + + + OD12 + Port output data I/O pin y + + 12 + 1 + read-write + + + OD13 + Port output data I/O pin y + + 13 + 1 + read-write + + + OD14 + Port output data I/O pin y + + 14 + 1 + read-write + + + OD15 + Port output data I/O pin y + + 15 + 1 + read-write + + + + + GPIOE_BSRR + GPIOE_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y + + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS1 + Port x set I/O pin y + + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS2 + Port x set I/O pin y + + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS3 + Port x set I/O pin y + + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS4 + Port x set I/O pin y + + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS5 + Port x set I/O pin y + + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS6 + Port x set I/O pin y + + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS7 + Port x set I/O pin y + + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS8 + Port x set I/O pin y + + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS9 + Port x set I/O pin y + + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS10 + Port x set I/O pin y + + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS11 + Port x set I/O pin y + + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS12 + Port x set I/O pin y + + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS13 + Port x set I/O pin y + + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS14 + Port x set I/O pin y + + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS15 + Port x set I/O pin y + + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BR0 + Port x reset I/O pin y + + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset I/O pin y + + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset I/O pin y + + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset I/O pin y + + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset I/O pin y + + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset I/O pin y + + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset I/O pin y + + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset I/O pin y + + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset I/O pin y + + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset I/O pin y + + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset I/O pin y + + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset I/O pin y + + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset I/O pin y + + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset I/O pin y + + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset I/O pin y + + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset I/O pin y + + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + + + GPIOE_LCKR + GPIOE_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y + + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y + + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y + + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y + + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y + + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y + + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y + + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y + + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y + + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y + + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y + + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y + + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y + + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y + + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y + + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y + + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key + + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. + 0x1 + + + + + + + GPIOE_AFRL + GPIOE_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x I/O pin y + + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x I/O pin y + + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x I/O pin y + + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x I/O pin y + + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x I/O pin y + + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x I/O pin y + + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x I/O pin y + + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x I/O pin y + + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOE_AFRH + GPIOE_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x I/O pin y + + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x I/O pin y + + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x I/O pin y + + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x I/O pin y + + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x I/O pin y + + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x I/O pin y + + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x I/O pin y + + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x I/O pin y + + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOE_BRR + GPIOE_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y + + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset IO pin y + + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset IO pin y + + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset IO pin y + + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset IO pin y + + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset IO pin y + + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset IO pin y + + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset IO pin y + + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset IO pin y + + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset IO pin y + + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset IO pin y + + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset IO pin y + + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset IO pin y + + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset IO pin y + + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset IO pin y + + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset IO pin y + + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + + + GPIOE_HSLVR + GPIOE_HSLVR + GPIO high-speed low-voltage register + 0x2C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + HSLV0 + Port x high-speed low-voltage configuration + + 0 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV1 + Port x high-speed low-voltage configuration + + 1 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV2 + Port x high-speed low-voltage configuration + + 2 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV3 + Port x high-speed low-voltage configuration + + 3 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV4 + Port x high-speed low-voltage configuration + + 4 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV5 + Port x high-speed low-voltage configuration + + 5 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV6 + Port x high-speed low-voltage configuration + + 6 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV7 + Port x high-speed low-voltage configuration + + 7 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV8 + Port x high-speed low-voltage configuration + + 8 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV9 + Port x high-speed low-voltage configuration + + 9 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV10 + Port x high-speed low-voltage configuration + + 10 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV11 + Port x high-speed low-voltage configuration + + 11 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV12 + Port x high-speed low-voltage configuration + + 12 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV13 + Port x high-speed low-voltage configuration + + 13 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV14 + Port x high-speed low-voltage configuration + + 14 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV15 + Port x high-speed low-voltage configuration + + 15 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + + + GPIOE_SECCFGR + GPIOE_SECCFGR + GPIO secure configuration register + 0x30 + 0x20 + read-write + 0x00000FFF + 0xFFFFFFFF + + + SEC0 + I/O pin of Port x secure bit enable y + + 0 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC1 + I/O pin of Port x secure bit enable y + + 1 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC2 + I/O pin of Port x secure bit enable y + + 2 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC3 + I/O pin of Port x secure bit enable y + + 3 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC4 + I/O pin of Port x secure bit enable y + + 4 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC5 + I/O pin of Port x secure bit enable y + + 5 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC6 + I/O pin of Port x secure bit enable y + + 6 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC7 + I/O pin of Port x secure bit enable y + + 7 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC8 + I/O pin of Port x secure bit enable y + + 8 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC9 + I/O pin of Port x secure bit enable y + + 9 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC10 + I/O pin of Port x secure bit enable y + + 10 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC11 + I/O pin of Port x secure bit enable y + + 11 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC12 + I/O pin of Port x secure bit enable y + + 12 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC13 + I/O pin of Port x secure bit enable y + + 13 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC14 + I/O pin of Port x secure bit enable y + + 14 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC15 + I/O pin of Port x secure bit enable y + + 15 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + + + + + GPIOE_S + 0X52021000 + + + GPIOF + GPIOF address block description + GPIOF + 0x42021400 + + 0x0 + 0x34 + registers + + + + GPIOF_MODER + GPIOF_MODER + GPIO port mode register + 0x00 + 0x20 + read-write + 0x00FFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + + + GPIOF_OTYPER + GPIOF_OTYPER + GPIO port output type register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y + + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y + + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y + + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y + + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y + + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y + + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y + + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y + + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y + + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y + + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y + + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y + + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y + + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y + + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y + + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y + + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIOF_OSPEEDR + GPIOF_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + + + GPIOF_PUPDR + GPIOF_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + GPIOF_IDR + GPIOF_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O pin y + + 0 + 1 + read-only + + + ID1 + Port x input data I/O pin y + + 1 + 1 + read-only + + + ID2 + Port x input data I/O pin y + + 2 + 1 + read-only + + + ID3 + Port x input data I/O pin y + + 3 + 1 + read-only + + + ID4 + Port x input data I/O pin y + + 4 + 1 + read-only + + + ID5 + Port x input data I/O pin y + + 5 + 1 + read-only + + + ID6 + Port x input data I/O pin y + + 6 + 1 + read-only + + + ID7 + Port x input data I/O pin y + + 7 + 1 + read-only + + + ID8 + Port x input data I/O pin y + + 8 + 1 + read-only + + + ID9 + Port x input data I/O pin y + + 9 + 1 + read-only + + + ID10 + Port x input data I/O pin y + + 10 + 1 + read-only + + + ID11 + Port x input data I/O pin y + + 11 + 1 + read-only + + + ID12 + Port x input data I/O pin y + + 12 + 1 + read-only + + + ID13 + Port x input data I/O pin y + + 13 + 1 + read-only + + + ID14 + Port x input data I/O pin y + + 14 + 1 + read-only + + + ID15 + Port x input data I/O pin y + + 15 + 1 + read-only + + + + + GPIOF_ODR + GPIOF_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O pin y + + 0 + 1 + read-write + + + OD1 + Port output data I/O pin y + + 1 + 1 + read-write + + + OD2 + Port output data I/O pin y + + 2 + 1 + read-write + + + OD3 + Port output data I/O pin y + + 3 + 1 + read-write + + + OD4 + Port output data I/O pin y + + 4 + 1 + read-write + + + OD5 + Port output data I/O pin y + + 5 + 1 + read-write + + + OD6 + Port output data I/O pin y + + 6 + 1 + read-write + + + OD7 + Port output data I/O pin y + + 7 + 1 + read-write + + + OD8 + Port output data I/O pin y + + 8 + 1 + read-write + + + OD9 + Port output data I/O pin y + + 9 + 1 + read-write + + + OD10 + Port output data I/O pin y + + 10 + 1 + read-write + + + OD11 + Port output data I/O pin y + + 11 + 1 + read-write + + + OD12 + Port output data I/O pin y + + 12 + 1 + read-write + + + OD13 + Port output data I/O pin y + + 13 + 1 + read-write + + + OD14 + Port output data I/O pin y + + 14 + 1 + read-write + + + OD15 + Port output data I/O pin y + + 15 + 1 + read-write + + + + + GPIOF_BSRR + GPIOF_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y + + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS1 + Port x set I/O pin y + + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS2 + Port x set I/O pin y + + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS3 + Port x set I/O pin y + + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS4 + Port x set I/O pin y + + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS5 + Port x set I/O pin y + + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS6 + Port x set I/O pin y + + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS7 + Port x set I/O pin y + + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS8 + Port x set I/O pin y + + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS9 + Port x set I/O pin y + + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS10 + Port x set I/O pin y + + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS11 + Port x set I/O pin y + + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS12 + Port x set I/O pin y + + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS13 + Port x set I/O pin y + + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS14 + Port x set I/O pin y + + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS15 + Port x set I/O pin y + + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BR0 + Port x reset I/O pin y + + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset I/O pin y + + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset I/O pin y + + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset I/O pin y + + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset I/O pin y + + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset I/O pin y + + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset I/O pin y + + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset I/O pin y + + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset I/O pin y + + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset I/O pin y + + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset I/O pin y + + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset I/O pin y + + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset I/O pin y + + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset I/O pin y + + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset I/O pin y + + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset I/O pin y + + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + + + GPIOF_LCKR + GPIOF_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y + + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y + + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y + + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y + + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y + + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y + + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y + + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y + + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y + + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y + + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y + + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y + + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y + + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y + + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y + + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y + + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key + + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. + 0x1 + + + + + + + GPIOF_AFRL + GPIOF_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x I/O pin y + + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x I/O pin y + + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x I/O pin y + + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x I/O pin y + + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x I/O pin y + + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x I/O pin y + + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x I/O pin y + + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x I/O pin y + + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOF_AFRH + GPIOF_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x I/O pin y + + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x I/O pin y + + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x I/O pin y + + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x I/O pin y + + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x I/O pin y + + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x I/O pin y + + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x I/O pin y + + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x I/O pin y + + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOF_BRR + GPIOF_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y + + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset IO pin y + + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset IO pin y + + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset IO pin y + + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset IO pin y + + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset IO pin y + + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset IO pin y + + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset IO pin y + + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset IO pin y + + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset IO pin y + + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset IO pin y + + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset IO pin y + + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset IO pin y + + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset IO pin y + + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset IO pin y + + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset IO pin y + + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + + + GPIOF_HSLVR + GPIOF_HSLVR + GPIO high-speed low-voltage register + 0x2C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + HSLV0 + Port x high-speed low-voltage configuration + + 0 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV1 + Port x high-speed low-voltage configuration + + 1 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV2 + Port x high-speed low-voltage configuration + + 2 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV3 + Port x high-speed low-voltage configuration + + 3 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV4 + Port x high-speed low-voltage configuration + + 4 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV5 + Port x high-speed low-voltage configuration + + 5 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV6 + Port x high-speed low-voltage configuration + + 6 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV7 + Port x high-speed low-voltage configuration + + 7 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV8 + Port x high-speed low-voltage configuration + + 8 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV9 + Port x high-speed low-voltage configuration + + 9 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV10 + Port x high-speed low-voltage configuration + + 10 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV11 + Port x high-speed low-voltage configuration + + 11 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV12 + Port x high-speed low-voltage configuration + + 12 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV13 + Port x high-speed low-voltage configuration + + 13 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV14 + Port x high-speed low-voltage configuration + + 14 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV15 + Port x high-speed low-voltage configuration + + 15 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + + + GPIOF_SECCFGR + GPIOF_SECCFGR + GPIO secure configuration register + 0x30 + 0x20 + read-write + 0x00000FFF + 0xFFFFFFFF + + + SEC0 + I/O pin of Port x secure bit enable y + + 0 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC1 + I/O pin of Port x secure bit enable y + + 1 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC2 + I/O pin of Port x secure bit enable y + + 2 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC3 + I/O pin of Port x secure bit enable y + + 3 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC4 + I/O pin of Port x secure bit enable y + + 4 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC5 + I/O pin of Port x secure bit enable y + + 5 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC6 + I/O pin of Port x secure bit enable y + + 6 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC7 + I/O pin of Port x secure bit enable y + + 7 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC8 + I/O pin of Port x secure bit enable y + + 8 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC9 + I/O pin of Port x secure bit enable y + + 9 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC10 + I/O pin of Port x secure bit enable y + + 10 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC11 + I/O pin of Port x secure bit enable y + + 11 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC12 + I/O pin of Port x secure bit enable y + + 12 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC13 + I/O pin of Port x secure bit enable y + + 13 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC14 + I/O pin of Port x secure bit enable y + + 14 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC15 + I/O pin of Port x secure bit enable y + + 15 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + + + + + GPIOF_S + 0X52021400 + + + GPIOG + GPIOG address block description + GPIOG + 0x42021800 + + 0x0 + 0x34 + registers + + + + GPIOG_MODER + GPIOG_MODER + GPIO port mode register + 0x00 + 0x20 + read-write + 0x00FFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + + + GPIOG_OTYPER + GPIOG_OTYPER + GPIO port output type register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y + + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y + + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y + + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y + + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y + + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y + + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y + + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y + + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y + + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y + + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y + + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y + + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y + + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y + + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y + + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y + + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIOG_OSPEEDR + GPIOG_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + + + GPIOG_PUPDR + GPIOG_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + GPIOG_IDR + GPIOG_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O pin y + + 0 + 1 + read-only + + + ID1 + Port x input data I/O pin y + + 1 + 1 + read-only + + + ID2 + Port x input data I/O pin y + + 2 + 1 + read-only + + + ID3 + Port x input data I/O pin y + + 3 + 1 + read-only + + + ID4 + Port x input data I/O pin y + + 4 + 1 + read-only + + + ID5 + Port x input data I/O pin y + + 5 + 1 + read-only + + + ID6 + Port x input data I/O pin y + + 6 + 1 + read-only + + + ID7 + Port x input data I/O pin y + + 7 + 1 + read-only + + + ID8 + Port x input data I/O pin y + + 8 + 1 + read-only + + + ID9 + Port x input data I/O pin y + + 9 + 1 + read-only + + + ID10 + Port x input data I/O pin y + + 10 + 1 + read-only + + + ID11 + Port x input data I/O pin y + + 11 + 1 + read-only + + + ID12 + Port x input data I/O pin y + + 12 + 1 + read-only + + + ID13 + Port x input data I/O pin y + + 13 + 1 + read-only + + + ID14 + Port x input data I/O pin y + + 14 + 1 + read-only + + + ID15 + Port x input data I/O pin y + + 15 + 1 + read-only + + + + + GPIOG_ODR + GPIOG_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O pin y + + 0 + 1 + read-write + + + OD1 + Port output data I/O pin y + + 1 + 1 + read-write + + + OD2 + Port output data I/O pin y + + 2 + 1 + read-write + + + OD3 + Port output data I/O pin y + + 3 + 1 + read-write + + + OD4 + Port output data I/O pin y + + 4 + 1 + read-write + + + OD5 + Port output data I/O pin y + + 5 + 1 + read-write + + + OD6 + Port output data I/O pin y + + 6 + 1 + read-write + + + OD7 + Port output data I/O pin y + + 7 + 1 + read-write + + + OD8 + Port output data I/O pin y + + 8 + 1 + read-write + + + OD9 + Port output data I/O pin y + + 9 + 1 + read-write + + + OD10 + Port output data I/O pin y + + 10 + 1 + read-write + + + OD11 + Port output data I/O pin y + + 11 + 1 + read-write + + + OD12 + Port output data I/O pin y + + 12 + 1 + read-write + + + OD13 + Port output data I/O pin y + + 13 + 1 + read-write + + + OD14 + Port output data I/O pin y + + 14 + 1 + read-write + + + OD15 + Port output data I/O pin y + + 15 + 1 + read-write + + + + + GPIOG_BSRR + GPIOG_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y + + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS1 + Port x set I/O pin y + + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS2 + Port x set I/O pin y + + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS3 + Port x set I/O pin y + + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS4 + Port x set I/O pin y + + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS5 + Port x set I/O pin y + + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS6 + Port x set I/O pin y + + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS7 + Port x set I/O pin y + + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS8 + Port x set I/O pin y + + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS9 + Port x set I/O pin y + + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS10 + Port x set I/O pin y + + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS11 + Port x set I/O pin y + + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS12 + Port x set I/O pin y + + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS13 + Port x set I/O pin y + + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS14 + Port x set I/O pin y + + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS15 + Port x set I/O pin y + + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BR0 + Port x reset I/O pin y + + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset I/O pin y + + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset I/O pin y + + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset I/O pin y + + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset I/O pin y + + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset I/O pin y + + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset I/O pin y + + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset I/O pin y + + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset I/O pin y + + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset I/O pin y + + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset I/O pin y + + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset I/O pin y + + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset I/O pin y + + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset I/O pin y + + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset I/O pin y + + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset I/O pin y + + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + + + GPIOG_LCKR + GPIOG_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y + + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y + + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y + + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y + + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y + + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y + + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y + + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y + + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y + + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y + + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y + + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y + + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y + + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y + + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y + + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y + + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key + + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. + 0x1 + + + + + + + GPIOG_AFRL + GPIOG_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x I/O pin y + + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x I/O pin y + + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x I/O pin y + + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x I/O pin y + + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x I/O pin y + + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x I/O pin y + + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x I/O pin y + + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x I/O pin y + + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOG_AFRH + GPIOG_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x I/O pin y + + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x I/O pin y + + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x I/O pin y + + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x I/O pin y + + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x I/O pin y + + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x I/O pin y + + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x I/O pin y + + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x I/O pin y + + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOG_BRR + GPIOG_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y + + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset IO pin y + + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset IO pin y + + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset IO pin y + + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset IO pin y + + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset IO pin y + + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset IO pin y + + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset IO pin y + + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset IO pin y + + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset IO pin y + + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset IO pin y + + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset IO pin y + + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset IO pin y + + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset IO pin y + + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset IO pin y + + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset IO pin y + + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + + + GPIOG_HSLVR + GPIOG_HSLVR + GPIO high-speed low-voltage register + 0x2C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + HSLV0 + Port x high-speed low-voltage configuration + + 0 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV1 + Port x high-speed low-voltage configuration + + 1 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV2 + Port x high-speed low-voltage configuration + + 2 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV3 + Port x high-speed low-voltage configuration + + 3 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV4 + Port x high-speed low-voltage configuration + + 4 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV5 + Port x high-speed low-voltage configuration + + 5 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV6 + Port x high-speed low-voltage configuration + + 6 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV7 + Port x high-speed low-voltage configuration + + 7 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV8 + Port x high-speed low-voltage configuration + + 8 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV9 + Port x high-speed low-voltage configuration + + 9 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV10 + Port x high-speed low-voltage configuration + + 10 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV11 + Port x high-speed low-voltage configuration + + 11 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV12 + Port x high-speed low-voltage configuration + + 12 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV13 + Port x high-speed low-voltage configuration + + 13 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV14 + Port x high-speed low-voltage configuration + + 14 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV15 + Port x high-speed low-voltage configuration + + 15 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + + + GPIOG_SECCFGR + GPIOG_SECCFGR + GPIO secure configuration register + 0x30 + 0x20 + read-write + 0x00000FFF + 0xFFFFFFFF + + + SEC0 + I/O pin of Port x secure bit enable y + + 0 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC1 + I/O pin of Port x secure bit enable y + + 1 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC2 + I/O pin of Port x secure bit enable y + + 2 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC3 + I/O pin of Port x secure bit enable y + + 3 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC4 + I/O pin of Port x secure bit enable y + + 4 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC5 + I/O pin of Port x secure bit enable y + + 5 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC6 + I/O pin of Port x secure bit enable y + + 6 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC7 + I/O pin of Port x secure bit enable y + + 7 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC8 + I/O pin of Port x secure bit enable y + + 8 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC9 + I/O pin of Port x secure bit enable y + + 9 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC10 + I/O pin of Port x secure bit enable y + + 10 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC11 + I/O pin of Port x secure bit enable y + + 11 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC12 + I/O pin of Port x secure bit enable y + + 12 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC13 + I/O pin of Port x secure bit enable y + + 13 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC14 + I/O pin of Port x secure bit enable y + + 14 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC15 + I/O pin of Port x secure bit enable y + + 15 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + + + + + GPIOG_S + 0X52021800 + + + GPIOH + GPIOH address block description + GPIOH + 0x42021c00 + + 0x0 + 0x34 + registers + + + + GPIOH_MODER + GPIOH_MODER + GPIO port mode register + 0x00 + 0x20 + read-write + 0x00FFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + + + GPIOH_OTYPER + GPIOH_OTYPER + GPIO port output type register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y + + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y + + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y + + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y + + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y + + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y + + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y + + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y + + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y + + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y + + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y + + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y + + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y + + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y + + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y + + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y + + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIOH_OSPEEDR + GPIOH_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + + + GPIOH_PUPDR + GPIOH_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + GPIOH_IDR + GPIOH_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O pin y + + 0 + 1 + read-only + + + ID1 + Port x input data I/O pin y + + 1 + 1 + read-only + + + ID2 + Port x input data I/O pin y + + 2 + 1 + read-only + + + ID3 + Port x input data I/O pin y + + 3 + 1 + read-only + + + ID4 + Port x input data I/O pin y + + 4 + 1 + read-only + + + ID5 + Port x input data I/O pin y + + 5 + 1 + read-only + + + ID6 + Port x input data I/O pin y + + 6 + 1 + read-only + + + ID7 + Port x input data I/O pin y + + 7 + 1 + read-only + + + ID8 + Port x input data I/O pin y + + 8 + 1 + read-only + + + ID9 + Port x input data I/O pin y + + 9 + 1 + read-only + + + ID10 + Port x input data I/O pin y + + 10 + 1 + read-only + + + ID11 + Port x input data I/O pin y + + 11 + 1 + read-only + + + ID12 + Port x input data I/O pin y + + 12 + 1 + read-only + + + ID13 + Port x input data I/O pin y + + 13 + 1 + read-only + + + ID14 + Port x input data I/O pin y + + 14 + 1 + read-only + + + ID15 + Port x input data I/O pin y + + 15 + 1 + read-only + + + + + GPIOH_ODR + GPIOH_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O pin y + + 0 + 1 + read-write + + + OD1 + Port output data I/O pin y + + 1 + 1 + read-write + + + OD2 + Port output data I/O pin y + + 2 + 1 + read-write + + + OD3 + Port output data I/O pin y + + 3 + 1 + read-write + + + OD4 + Port output data I/O pin y + + 4 + 1 + read-write + + + OD5 + Port output data I/O pin y + + 5 + 1 + read-write + + + OD6 + Port output data I/O pin y + + 6 + 1 + read-write + + + OD7 + Port output data I/O pin y + + 7 + 1 + read-write + + + OD8 + Port output data I/O pin y + + 8 + 1 + read-write + + + OD9 + Port output data I/O pin y + + 9 + 1 + read-write + + + OD10 + Port output data I/O pin y + + 10 + 1 + read-write + + + OD11 + Port output data I/O pin y + + 11 + 1 + read-write + + + OD12 + Port output data I/O pin y + + 12 + 1 + read-write + + + OD13 + Port output data I/O pin y + + 13 + 1 + read-write + + + OD14 + Port output data I/O pin y + + 14 + 1 + read-write + + + OD15 + Port output data I/O pin y + + 15 + 1 + read-write + + + + + GPIOH_BSRR + GPIOH_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y + + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS1 + Port x set I/O pin y + + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS2 + Port x set I/O pin y + + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS3 + Port x set I/O pin y + + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS4 + Port x set I/O pin y + + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS5 + Port x set I/O pin y + + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS6 + Port x set I/O pin y + + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS7 + Port x set I/O pin y + + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS8 + Port x set I/O pin y + + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS9 + Port x set I/O pin y + + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS10 + Port x set I/O pin y + + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS11 + Port x set I/O pin y + + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS12 + Port x set I/O pin y + + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS13 + Port x set I/O pin y + + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS14 + Port x set I/O pin y + + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS15 + Port x set I/O pin y + + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BR0 + Port x reset I/O pin y + + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset I/O pin y + + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset I/O pin y + + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset I/O pin y + + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset I/O pin y + + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset I/O pin y + + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset I/O pin y + + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset I/O pin y + + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset I/O pin y + + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset I/O pin y + + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset I/O pin y + + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset I/O pin y + + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset I/O pin y + + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset I/O pin y + + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset I/O pin y + + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset I/O pin y + + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + + + GPIOH_LCKR + GPIOH_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y + + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y + + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y + + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y + + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y + + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y + + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y + + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y + + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y + + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y + + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y + + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y + + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y + + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y + + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y + + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y + + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key + + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. + 0x1 + + + + + + + GPIOH_AFRL + GPIOH_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x I/O pin y + + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x I/O pin y + + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x I/O pin y + + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x I/O pin y + + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x I/O pin y + + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x I/O pin y + + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x I/O pin y + + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x I/O pin y + + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOH_AFRH + GPIOH_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x I/O pin y + + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x I/O pin y + + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x I/O pin y + + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x I/O pin y + + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x I/O pin y + + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x I/O pin y + + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x I/O pin y + + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x I/O pin y + + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOH_BRR + GPIOH_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y + + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset IO pin y + + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset IO pin y + + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset IO pin y + + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset IO pin y + + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset IO pin y + + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset IO pin y + + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset IO pin y + + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset IO pin y + + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset IO pin y + + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset IO pin y + + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset IO pin y + + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset IO pin y + + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset IO pin y + + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset IO pin y + + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset IO pin y + + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + + + GPIOH_HSLVR + GPIOH_HSLVR + GPIO high-speed low-voltage register + 0x2C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + HSLV0 + Port x high-speed low-voltage configuration + + 0 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV1 + Port x high-speed low-voltage configuration + + 1 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV2 + Port x high-speed low-voltage configuration + + 2 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV3 + Port x high-speed low-voltage configuration + + 3 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV4 + Port x high-speed low-voltage configuration + + 4 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV5 + Port x high-speed low-voltage configuration + + 5 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV6 + Port x high-speed low-voltage configuration + + 6 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV7 + Port x high-speed low-voltage configuration + + 7 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV8 + Port x high-speed low-voltage configuration + + 8 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV9 + Port x high-speed low-voltage configuration + + 9 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV10 + Port x high-speed low-voltage configuration + + 10 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV11 + Port x high-speed low-voltage configuration + + 11 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV12 + Port x high-speed low-voltage configuration + + 12 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV13 + Port x high-speed low-voltage configuration + + 13 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV14 + Port x high-speed low-voltage configuration + + 14 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV15 + Port x high-speed low-voltage configuration + + 15 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + + + GPIOH_SECCFGR + GPIOH_SECCFGR + GPIO secure configuration register + 0x30 + 0x20 + read-write + 0x00000FFF + 0xFFFFFFFF + + + SEC0 + I/O pin of Port x secure bit enable y + + 0 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC1 + I/O pin of Port x secure bit enable y + + 1 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC2 + I/O pin of Port x secure bit enable y + + 2 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC3 + I/O pin of Port x secure bit enable y + + 3 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC4 + I/O pin of Port x secure bit enable y + + 4 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC5 + I/O pin of Port x secure bit enable y + + 5 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC6 + I/O pin of Port x secure bit enable y + + 6 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC7 + I/O pin of Port x secure bit enable y + + 7 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC8 + I/O pin of Port x secure bit enable y + + 8 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC9 + I/O pin of Port x secure bit enable y + + 9 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC10 + I/O pin of Port x secure bit enable y + + 10 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC11 + I/O pin of Port x secure bit enable y + + 11 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC12 + I/O pin of Port x secure bit enable y + + 12 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC13 + I/O pin of Port x secure bit enable y + + 13 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC14 + I/O pin of Port x secure bit enable y + + 14 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC15 + I/O pin of Port x secure bit enable y + + 15 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + + + + + GPIOH_S + 0X52021C00 + + + GTZC1_TZIC + GTZC1_MPCBBz register block + GTZC1 + 0x40032400 + + 0x0 + 0x30 + registers + + + GTZC + GTZC global interrupt + 8 + + + + GTZC1_TZIC_IER1 + GTZC1_TZIC_IER1 + GTZC1 TZIC interrupt enable register 1 + GTZC1_TZSC_CR + 0x000 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TIM2IE + illegal access interrupt enable for TIM2 + 0 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TIM3IE + illegal access interrupt enable for TIM3 + 1 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TIM4IE + illegal access interrupt enable for TIM4 + 2 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TIM5IE + illegal access interrupt enable for TIM5 + 3 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TIM6IE + illegal access interrupt enable for TIM6 + 4 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TIM7IE + illegal access interrupt enable for TIM7 + 5 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TIM12IE + illegal access interrupt enable for TIM12 + 6 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + WWDGIE + illegal access interrupt enable for WWDG + 9 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + IWDGIE + illegal access interrupt enable for IWDG + 10 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SPI2IE + illegal access interrupt enable for SPI2 + 11 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SPI3IE + illegal access interrupt enable for SPI3 + 12 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + USART2IE + illegal access interrupt enable for USART2 + 13 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + USART3IE + illegal access interrupt enable for USART3 + 14 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + UART4IE + illegal access interrupt enable for UART4 + 15 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + UART5IE + illegal access interrupt enable for UART5 + 16 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + I2C1IE + illegal access interrupt enable for I2C1 + 17 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + I2C2IE + illegal access interrupt enable for I2C2 + 18 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + I3C1IE + illegal access interrupt enable for I3C1 + 19 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + CRSIE + illegal access interrupt enable for CRS + 20 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + USART6IE + illegal access interrupt enable for USART6 + 21 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + USART10IE + illegal access interrupt enable for USART10 + 22 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + USART11IE + illegal access interrupt enable for USART11 + 23 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + HDMICECIE + illegal access interrupt enable for HDMICEC + 24 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + DAC1IE + illegal access interrupt enable for DAC1 + 25 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + UART7IE + illegal access interrupt enable for UART7 + 26 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + UART8IE + illegal access interrupt enable for UART8 + 27 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + UART9IE + illegal access interrupt enable for UART9 + 28 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + UART12IE + illegal access interrupt enable for UART12 + 29 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + DTSIE + illegal access interrupt enable for DTS + 30 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + LPTIM2IE + illegal access interrupt enable for LPTIM2 + 31 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + + + GTZC1_TZIC_IER2 + GTZC1_TZIC_IER2 + GTZC1 TZIC interrupt enable register 2 + 0x004 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FDCAN1IE + illegal access interrupt enable for FDCAN1 + 0 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + FDCAN2IE + illegal access interrupt enable for FDCAN2 + 1 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + UCPDIE + illegal access interrupt enable for UCPD + 2 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TIM1IE + illegal access interrupt enable for TIM1 + 8 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SPI1IE + illegal access interrupt enable for SPI1 + 9 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TIM8IE + illegal access interrupt enable for TIM8 + 10 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + USART1IE + illegal access interrupt enable for USART1 + 11 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TIM15IE + illegal access interrupt enable for TIM15 + 12 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SPI4IE + illegal access interrupt enable for SPI4 + 15 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SPI6IE + illegal access interrupt enable for SPI6 + 16 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SAI1IE + illegal access interrupt enable for SAI1 + 17 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SAI2IE + illegal access interrupt enable for SAI2 + 18 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + USBIE + illegal access interrupt enable for USB + 19 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + LPUART1IE + illegal access interrupt enable for LPUART + 25 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + I2C3IE + illegal access interrupt enable for I2C3 + 26 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + LPTIM1IE + illegal access interrupt enable for LPTIM1 + 28 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + LPTIM3IE + illegal access interrupt enable for LPTIM3 + 29 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + LPTIM4IE + illegal access interrupt enable for LPTIM4 + 30 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + LPTIM5IE + illegal access interrupt enable for LPTIM5 + 31 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + + + GTZC1_TZIC_IER3 + GTZC1_TZIC_IER3 + GTZC1 TZIC interrupt enable register 3 + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LPTIM6IE + illegal access interrupt enable for LPTIM6 + 0 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + VREFBUFIE + illegal access interrupt enable for VREFBUF + 1 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + I3C2IE + illegal access interrupt enable for I3C2 + 2 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + CRCIE + illegal access interrupt enable for CRC + 8 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + CORDICIE + illegal access interrupt enable for CORDIC + 9 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + FMACIE + illegal access interrupt enable for FMAC + 10 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + ETHIE + illegal access interrupt enable for register of ETH + 11 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + ICACHEIE + illegal access interrupt enable for ICACHE + 12 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + DCACHEIE + illegal access interrupt enable for DCACHE + 13 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + ADC12IE + illegal access interrupt enable for ADC1 and ADC2 + 14 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + DCMIIE + illegal access interrupt enable for DCMI + 15 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + AESIE + illegal access interrupt enable for AES + 16 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + HASHIE + illegal access interrupt enable for HASH + 17 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + RNGIE + illegal access interrupt enable for RNG + 18 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SAESIE + illegal access interrupt enable for SAES + 19 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + PKAIE + illegal access interrupt enable for PKA + 20 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SDMMC1IE + illegal access interrupt enable for SDMMC1 + 21 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + FMCIE + illegal access interrupt enable for FMC + 23 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + OCTOSPI1IE + illegal access interrupt enable for OCTOSPI1 + 24 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + RAMCFGIE + illegal access interrupt enable for RAMSCFG + 26 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + + + GTZC1_TZIC_IER4 + GTZC1_TZIC_IER4 + GTZC1 TZIC interrupt enable register 4 + 0x00C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + GPDMA1IE + illegal access interrupt enable for GPDMA1 + 0 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + GPDMA2IE + illegal access interrupt enable for GPDMA2 + 1 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + FLASH_REGIE + illegal access interrupt enable for FLASH registers + 2 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + FLASHIE + illegal access interrupt enable for FLASH memory + 3 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + OTFDEC1IE + illegal access interrupt enable for OTFDEC1 + 4 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SBSIE + illegal access interrupt enable for SBS + 6 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + RTCIE + illegal access interrupt enable for RTC + 7 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TAMPIE + illegal access interrupt enable for TAMP + 8 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + PWRIE + illegal access interrupt enable for PWR + 9 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + RCCIE + illegal access interrupt enable for RCC + 10 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + EXTIIE + illegal access interrupt enable for EXTI + 11 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TZSC1IE + illegal access interrupt enable for GTZC1 TZSC registers + 16 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TZIC1IE + illegal access interrupt enable for GTZC1 TZIC registers + 17 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + OCTOSPI1_MEMIE + illegal access interrupt enable for MPCWM1 (OCTOSPI1) memory bank + 18 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + FMC_MEMIE + illegal access interrupt enable for MPCWM2 (FMC_NOR bank), MPCWM3 (FMC_NAND bank and FMC_SDRAM bank 1), and MPCWM4 (FMC_SDRAM bank 2) + 19 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + BKPSRAMIE + illegal access interrupt enable for MPCWM4 (BKPSRAM) memory bank + 20 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SRAM1IE + illegal access interrupt enable for SRAM1 + 24 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + MPCBB1_REGIE + illegal access interrupt enable for MPCBB1 registers + 25 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SRAM2IE + illegal access interrupt enable for SRAM2 + 26 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + MPCBB2_REGIE + illegal access interrupt enable for MPCBB2 registers + 27 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SRAM3IE + illegal access interrupt enable for SRAM3 + 28 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + MPCBB3_REGIE + illegal access interrupt enable for MPCBB3 registers + 29 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + + + GTZC1_TZIC_SR1 + GTZC1_TZIC_SR1 + GTZC1 TZIC status register 1 + GTZC1_TZSC_SECCFGR1 + 0x010 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + TIM2F + illegal access flag for TIM2 + 0 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + TIM3F + illegal access flag for TIM3 + 1 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + TIM4F + illegal access flag for TIM4 + 2 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + TIM5F + illegal access flag for TIM5 + 3 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + TIM6F + illegal access flag for TIM6 + 4 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + TIM7F + illegal access flag for TIM7 + 5 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + TIM12F + illegal access flag for TIM12 + 6 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + WWDGF + illegal access flag for WWDG + 9 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + IWDGF + illegal access flag for IWDG + 10 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + SPI2F + illegal access flag for SPI2 + 11 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + SPI3F + illegal access flag for SPI3 + 12 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + USART2F + illegal access flag for USART2 + 13 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + USART3F + illegal access flag for USART3 + 14 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + UART4F + illegal access flag for UART4 + 15 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + UART5F + illegal access flag for UART5 + 16 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + I2C1F + illegal access flag for I2C1 + 17 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + I2C2F + illegal access flag for I2C2 + 18 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + I3C1F + illegal access flag for I3C1 + 19 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + CRSF + illegal access flag for CRS + 20 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + USART6F + illegal access flag for USART6 + 21 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + USART10F + illegal access flag for USART10 + 22 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + USART11F + illegal access flag for USART11 + 23 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + HDMICECF + illegal access flag for HDMICEC + 24 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + DAC1F + illegal access flag for DAC1 + 25 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + UART7F + illegal access flag for UART7 + 26 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + UART8F + illegal access flag for UART8 + 27 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + UART9F + illegal access flag for UART9 + 28 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + UART12F + illegal access flag for UART12 + 29 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + DTSF + illegal access flag for DTS + 30 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + LPTIM2F + illegal access flag for LPTIM2 + 31 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + + + GTZC1_TZIC_SR2 + GTZC1_TZIC_SR2 + GTZC1 TZIC status register 2 + GTZC1_TZSC_SECCFGR2 + 0x014 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + FDCAN1F + illegal access flag for FDCAN1 + 0 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + FDCAN2F + illegal access flag for FDCAN2 + 1 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + UCPDF + illegal access flag for UCPD + 2 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + TIM1F + illegal access flag for TIM1 + 8 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + SPI1F + illegal access flag for SPI1 + 9 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + TIM8F + illegal access flag for TIM8 + 10 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + USART1F + illegal access flag for USART1 + 11 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + TIM15F + illegal access flag for TIM15 + 12 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + SPI4F + illegal access flag for SPI4 + 15 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + SPI6F + illegal access flag for SPI6 + 16 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + SAI1F + illegal access flag for SAI1 + 17 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + SAI2F + illegal access flag for SAI2 + 18 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + USBF + illegal access flag for USB + 19 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + LPUART1F + illegal access flag for LPUART + 25 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + I2C3F + illegal access flag for I2C3 + 26 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + LPTIM1F + illegal access flag for LPTIM1 + 28 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + LPTIM3F + illegal access flag for LPTIM3 + 29 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + LPTIM4F + illegal access flag for LPTIM4 + 30 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + LPTIM5F + illegal access flag for LPTIM5 + 31 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + + + GTZC1_TZIC_SR3 + GTZC1_TZIC_SR3 + GTZC1 TZIC status register 3 + GTZC1_TZSC_SECCFGR3 + 0x018 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + LPTIM6F + illegal access flag for LPTIM6 + 0 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + VREFBUFF + illegal access flag for VREFBUF + 1 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + I3C2F + illegal access flag for I3C2 + 2 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + CRCF + illegal access flag for CRC + 8 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + CORDICF + illegal access flag for CORDIC + 9 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + FMACF + illegal access flag for FMAC + 10 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + ETHF + illegal access flag for register of ETH + 11 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + ICACHEF + illegal access flag for ICACHE + 12 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + DCACHEF + illegal access flag for DCACHE + 13 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + ADC12F + illegal access flag for ADC1 and ADC2 + 14 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + DCMIF + illegal access flag for DCMI + 15 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + AESF + illegal access flag for AES + 16 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + HASHF + illegal access flag for HASH + 17 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + RNGF + illegal access flag for RNG + 18 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + SAESF + illegal access flag for SAES + 19 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + PKAF + illegal access flag for PKA + 20 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + SDMMC1F + illegal access flag for SDMMC1 + 21 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + FMCF + illegal access flag for FMC + 23 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + OCTOSPI1F + illegal access flag for OCTOSPI1 + 24 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + RAMCFGF + illegal access flag for RAMSCFG + 26 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + + + GTZC1_TZIC_SR4 + GTZC1_TZIC_SR4 + GTZC1 TZIC status register 4 + 0x01C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + GPDMA1F + illegal access flag for GPDMA1 + 0 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + GPDMA2F + illegal access flag for GPDMA2 + 1 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + FLASH_REGF + illegal access flag for FLASH registers + 2 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + FLASHF + illegal access flag for FLASH memory + 3 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + OTFDEC1F + illegal access flag for OTFDEC1 + 4 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + SBSF + illegal access flag for SBS + 6 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + RTCF + illegal access flag for RTC + 7 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + TAMPF + illegal access flag for TAMP + 8 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + PWRF + illegal access flag for PWR + 9 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + RCCF + illegal access flag for RCC + 10 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + EXTIF + illegal access flag for EXTI + 11 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + TZSC1F + illegal access flag for GTZC1 TZSC registers + 16 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + TZIC1F + illegal access flag for GTZC1 TZIC registers + 17 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + OCTOSPI1_MEMF + illegal access flag for MPCWM1 (OCTOSPI1) memory bank + 18 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + FMC_MEMF + illegal access flag for MPCWM2 (FMC_NOR bank), MPCWM3 (FMC_NAND bank and FMC_SDRAM bank 1), and MPCWM4 (FMC_SDRAM bank 2) + 19 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + BKPSRAMF + illegal access flag for MPCWM4 (BKPSRAM) memory bank + 20 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + SRAM1F + illegal access flag for SRAM1 + 24 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + MPCBB1_REGF + illegal access flag for MPCBB1 registers + 25 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + SRAM2F + illegal access flag for SRAM2 + 26 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + MPCBB2_REGF + illegal access flag for MPCBB2 registers + 27 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + SRAM3F + illegal access flag for SRAM3 + 28 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + MPCBB3_REGF + illegal access flag for MPCBB3 registers + 29 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + + + GTZC1_TZIC_FCR1 + GTZC1_TZIC_FCR1 + GTZC1 TZIC flag clear register 1 + GTZC1_TZSC_PRIVCFGR1 + 0x020 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + CTIM2F + clear the illegal access flag for TIM2 + 0 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CTIM3F + clear the illegal access flag for TIM3 + 1 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CTIM4F + clear the illegal access flag for TIM4 + 2 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CTIM5F + clear the illegal access flag for TIM5 + 3 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CTIM6F + clear the illegal access flag for TIM6 + 4 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CTIM7F + clear the illegal access flag for TIM7 + 5 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CTIM12F + clear the illegal access flag for TIM12 + 6 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CTIM13F + clear the illegal access flag for TIM13 + 7 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CTIM14F + clear the illegal access flag for TIM14 + 8 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CWWDGF + clear the illegal access flag for WWDG + 9 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CIWDGF + clear the illegal access flag for IWDG + 10 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CSPI2F + clear the illegal access flag for SPI2 + 11 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CSPI3F + clear the illegal access flag for SPI3 + 12 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CUSART2F + clear the illegal access flag for USART2 + 13 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CUSART3F + clear the illegal access flag for USART3 + 14 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CUART4F + clear the illegal access flag for UART4 + 15 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CUART5F + clear the illegal access flag for UART5 + 16 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CI2C1F + clear the illegal access flag for I2C1 + 17 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CI2C2F + clear the illegal access flag for I2C2 + 18 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CI3C1F + clear the illegal access flag for I3C1 + 19 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CCRSF + clear the illegal access flag for CRS + 20 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CUSART6F + clear the illegal access flag for USART6 + 21 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CUSART10F + clear the illegal access flag for USART10 + 22 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CUSART11F + clear the illegal access flag for USART11 + 23 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CHDMICECF + clear the illegal access flag for HDMICEC + 24 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CDAC1F + clear the illegal access flag for DAC1 + 25 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CUART7F + clear the illegal access flag for UART7 + 26 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CUART8F + clear the illegal access flag for UART8 + 27 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CUART9F + clear the illegal access flag for UART9 + 28 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CUART12F + clear the illegal access flag for UART12 + 29 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CDTSF + clear the illegal access flag for DTS + 30 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CLPTIM2F + clear the illegal access flag for LPTIM2 + 31 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + + + GTZC1_TZIC_FCR2 + GTZC1_TZIC_FCR2 + GTZC1 TZIC flag clear register 2 + GTZC1_TZSC_PRIVCFGR2 + 0x024 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + CFDCAN1F + clear the illegal access flag for FDCAN1 + 0 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CFDCAN2F + clear the illegal access flag for FDCAN2 + 1 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CUCPDF + clear the illegal access flag for UCPD + 2 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CTIM1F + clear the illegal access flag for TIM1 + 8 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CSPI1F + clear the illegal access flag for SPI1 + 9 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CTIM8F + clear the illegal access flag for TIM8 + 10 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CUSART1F + clear the illegal access flag for USART1 + 11 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CTIM15F + clear the illegal access flag for TIM15 + 12 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CTIM16F + clear the illegal access flag for TIM16 + 13 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CTIM17F + clear the illegal access flag for TIM17 + 14 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CSPI4F + clear the illegal access flag for SPI4 + 15 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CSPI6F + clear the illegal access flag for SPI6 + 16 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CSAI1F + clear the illegal access flag for SAI1 + 17 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CSAI2F + clear the illegal access flag for SAI2 + 18 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CUSBF + clear the illegal access flag for USB + 19 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CSPI5F + clear the illegal access flag for SPI5 + 24 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CLPUART1F + clear the illegal access flag for LPUART + 25 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CI2C3F + clear the illegal access flag for I2C3 + 26 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CI2C4F + clear the illegal access flag for I2C4 + 27 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CLPTIM1F + clear the illegal access flag for LPTIM1 + 28 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CLPTIM3F + clear the illegal access flag for LPTIM3 + 29 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CLPTIM4F + clear the illegal access flag for LPTIM4 + 30 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CLPTIM5F + clear the illegal access flag for LPTIM5 + 31 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + + + GTZC1_TZIC_FCR3 + GTZC1_TZIC_FCR3 + GTZC1 TZIC flag clear register 3 + GTZC1_TZSC_PRIVCFGR3 + 0x028 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + CLPTIM6F + clear illegal access flag for LPTIM6 + 0 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CVREFBUFF + clear illegal access flag for VREFBUF + 1 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CI3C2F + clear illegal access flag for I3C2 + 2 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CCRCF + clear illegal access flag for CRC + 8 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CCORDICF + clear illegal access flag for CORDIC + 9 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CFMACF + clear illegal access flag for FMAC + 10 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CETHF + clear illegal access flag for register of ETH + 11 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CICACHEF + clear illegal access flag for ICACHE + 12 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CDCACHEF + clear illegal access flag for DCACHE + 13 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CADC12F + clear illegal access flag for ADC1 and ADC2 + 14 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CDCMIF + clear illegal access flag for DCMI + 15 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CAESF + clear illegal access flag for AES + 16 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CHASHF + clear illegal access flag for HASH + 17 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CRNGF + clear illegal access flag for RNG + 18 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CSAESF + clear illegal access flag for SAES + 19 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CPKAF + clear illegal access flag for PKA + 20 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CSDMMC1F + clear illegal access flag for SDMMC1 + 21 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CSDMMC2F + clear illegal access flag for SDMMC2 + 22 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CFMCF + clear illegal access flag for FMC + 23 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + COCTOSPI1F + clear illegal access flag for OCTOSPI1 + 24 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CRAMCFGF + clear illegal access flag for RAMSCFG + 26 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + + + GTZC1_TZIC_FCR4 + GTZC1_TZIC_FCR4 + GTZC1 TZIC flag clear register 4 + 0x02C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + CGPDMA1F + clear the illegal access flag for GPDMA1 + 0 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CGPDMA2F + clear the illegal access flag for GPDMA2 + 1 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CFLASH_REGF + clear the illegal access flag for FLASH registers + 2 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CFLASHF + clear the illegal access flag for FLASH memory + 3 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + COTFDEC1F + clear the illegal access flag for OTFDEC1 + 4 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CSBSF + clear the illegal access flag for SBS + 6 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CRTCF + clear the illegal access flag for RTC + 7 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CTAMPF + clear the illegal access flag for TAMP + 8 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CPWRF + clear the illegal access flag for PWR + 9 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CRCCF + clear the illegal access flag for RCC + 10 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CEXTIF + clear the illegal access flag for EXTI + 11 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CTZSC1F + clear the illegal access flag for GTZC1 TZSC registers + 16 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CTZIC1F + clear the illegal access flag for GTZC1 TZIC registers + 17 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + COCTOSPI1_MEMF + clear the illegal access flag for MPCWM1 (OCTOSPI1) memory bank + 18 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CFMC_MEMF + clear the illegal access flag for MPCWM2 (FMC_NOR bank), MPCWM3 (FMC_NAND bank and FMC_SDRAM bank 1), and MPCWM4 (FMC_SDRAM bank 2) + 19 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CBKPSRAMF + clear the illegal access flag for MPCWM4 (BKPSRAM) memory bank + 20 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CSRAM1F + clear the illegal access flag for SRAM1 + 24 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CMPCBB1_REGF + clear the illegal access flag for MPCBB1 registers + 25 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CSRAM2F + clear the illegal access flag for SRAM2 + 26 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CMPCBB2_REGF + clear the illegal access flag for MPCBB2 registers + 27 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CSRAM3F + clear the illegal access flag for SRAM3 + 28 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CMPCBB3_REGF + clear the illegal access flag for MPCBB3 registers + 29 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + + + + + GTZC1_TZIC_S + 0X50032400 + + + GTZC1_TZSC + GTZC1_MPCBBz register block + GTZC1 + 0x40036400 + + 0x0 + 0x80 + registers + + + + GTZC1_TZSC_CR + GTZC1_TZSC_CR + GTZC1 TZSC control register + 0x000 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LCK + lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx until next reset + + 0 + 1 + read-write + + + B_0x0 + configuration of all GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx not locked + 0x0 + + + B_0x1 + configuration of all GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx locked + 0x1 + + + + + + + GTZC1_TZSC_SECCFGR1 + GTZC1_TZSC_SECCFGR1 + GTZC1 TZSC secure configuration register 1 + 0x010 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TIM2SEC + secure access mode for TIM2 + 0 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + TIM3SEC + secure access mode for TIM3 + 1 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + TIM4SEC + secure access mode for TIM4 + 2 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + TIM5SEC + secure access mode for TIM5 + 3 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + TIM6SEC + secure access mode for TIM6 + 4 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + TIM7SEC + secure access mode for TIM7 + 5 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + TIM12SEC + secure access mode for TIM12 + 6 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + WWDGSEC + secure access mode for WWDG + 9 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + IWDGSEC + secure access mode for IWDG + 10 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + SPI2SEC + secure access mode for SPI2 + 11 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + SPI3SEC + secure access mode for SPI3 + 12 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + USART2SEC + secure access mode for USART2 + 13 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + USART3SEC + secure access mode for USART3 + 14 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + UART4SEC + secure access mode for UART4 + 15 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + UART5SEC + secure access mode for UART5 + 16 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + I2C1SEC + secure access mode for I2C1 + 17 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + I2C2SEC + secure access mode for I2C2 + 18 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + I3C1SEC + secure access mode for I3C1 + 19 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + CRSSEC + secure access mode for CRS + 20 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + USART6SEC + secure access mode for USART6 + 21 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + USART10SEC + secure access mode for USART10 + 22 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + USART11SEC + secure access mode for USART11 + 23 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + HDMICECSEC + secure access mode for HDMICEC + 24 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + DAC1SEC + secure access mode for DAC1 + 25 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + UART7SEC + secure access mode for UART7 + 26 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + UART8SEC + secure access mode for UART8 + 27 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + UART9SEC + secure access mode for UART9 + 28 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + UART12SEC + secure access mode for UART12 + 29 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + DTSSEC + secure access mode for DTS + 30 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + LPTIM2SEC + secure access mode for LPTIM2 + 31 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + + + GTZC1_TZSC_SECCFGR2 + GTZC1_TZSC_SECCFGR2 + GTZC1 TZSC secure configuration register 2 + 0x014 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FDCAN1SEC + secure access mode for FDCAN1 + 0 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + FDCAN2SEC + secure access mode for FDCAN2 + 1 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + UCPDSEC + secure access mode for UCPD + 2 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + TIM1SEC + secure access mode for TIM1 + 8 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + SPI1SEC + secure access mode for SPI1 + 9 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + TIM8SEC + secure access mode for TIM8 + 10 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + USART1SEC + secure access mode for USART1 + 11 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + TIM15SEC + secure access mode for TIM15 + 12 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + SPI4SEC + secure access mode for SPI4 + 15 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + SPI6SEC + secure access mode for SPI6 + 16 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + SAI1SEC + secure access mode for SAI1 + 17 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + SAI2SEC + secure access mode for SAI2 + 18 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + USBSEC + secure access mode for USB + 19 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + LPUART1SEC + secure access mode for LPUART + 25 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + I2C3SEC + secure access mode for I2C3 + 26 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + LPTIM1SEC + secure access mode for LPTIM1 + 28 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + LPTIM3SEC + secure access mode for LPTIM3 + 29 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + LPTIM4SEC + secure access mode for LPTIM4 + 30 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + LPTIM5SEC + secure access mode for LPTIM5 + 31 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + + + GTZC1_TZSC_SECCFGR3 + GTZC1_TZSC_SECCFGR3 + GTZC1 TZSC secure configuration register 3 + 0x018 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LPTIM6SEC + secure access mode for LPTIM6 + 0 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + VREFBUFSEC + secure access mode for VREFBUF + 1 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + I3C2SEC + secure access mode for I3C2 + 2 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + CRCSEC + secure access mode for CRC + 8 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + CORDICSEC + secure access mode for CORDIC + 9 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + FMACSEC + secure access mode for FMAC + 10 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + ETHSEC + secure access mode for register of ETH + 11 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + ICACHESEC + secure access mode for ICACHE + 12 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + DCACHESEC + secure access mode for DCACHE + 13 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + ADC12SEC + secure access mode for ADC1 and ADC2 + 14 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + DCMISEC + secure access mode for DCMI + 15 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + AESSEC + secure access mode for AES + 16 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + HASHSEC + secure access mode for HASH + 17 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + RNGSEC + secure access mode for RNG + 18 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + SAESSEC + secure access mode for SAES + 19 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + PKASEC + secure access mode for PKA + 20 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + SDMMC1SEC + secure access mode for SDMMC1 + 21 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + FMCSEC + secure access mode for FMC + 23 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + OCTOSPI1SEC + secure access mode for OCTOSPI1 + 24 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + RAMCFGSEC + secure access mode for RAMSCFG + 26 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + + + GTZC1_TZSC_PRIVCFGR1 + GTZC1_TZSC_PRIVCFGR1 + GTZC1 TZSC privilege configuration register 1 + 0x020 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TIM2PRIV + privileged access mode for TIM2 + 0 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + TIM3PRIV + privileged access mode for TIM3 + 1 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + TIM4PRIV + privileged access mode for TIM4 + 2 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + TIM5PRIV + privileged access mode for TIM5 + 3 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + TIM6PRIV + privileged access mode for TIM6 + 4 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + TIM7PRIV + privileged access mode for TIM7 + 5 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + TIM12PRIV + privileged access mode for TIM12 + 6 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + WWDGPRIV + privileged access mode for WWDG + 9 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + IWDGPRIV + privileged access mode for IWDG + 10 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + SPI2PRIV + privileged access mode for SPI2 + 11 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + SPI3PRIV + privileged access mode for SPI3 + 12 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + USART2PRIV + privileged access mode for USART2 + 13 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + USART3PRIV + privileged access mode for USART3 + 14 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + UART4PRIV + privileged access mode for UART4 + 15 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + UART5PRIV + privileged access mode for UART5 + 16 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + I2C1PRIV + privileged access mode for I2C1 + 17 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + I2C2PRIV + privileged access mode for I2C2 + 18 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + I3C1PRIV + privileged access mode for I3C1 + 19 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + CRSPRIV + privileged access mode for CRS + 20 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + USART6PRIV + privileged access mode for USART6 + 21 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + USART10PRIV + privileged access mode for USART10 + 22 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + USART11PRIV + privileged access mode for USART11 + 23 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + HDMICECPRIV + privileged access mode for HDMICEC + 24 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + DAC1PRIV + privileged access mode for DAC1 + 25 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + UART7PRIV + privileged access mode for UART7 + 26 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + UART8PRIV + privileged access mode for UART8 + 27 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + UART9PRIV + privileged access mode for UART9 + 28 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + UART12PRIV + privileged access mode for UART12 + 29 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + DTSPRIV + privileged access mode for DTS + 30 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + LPTIM2PRIV + privileged access mode for LPTIM2 + 31 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + + + GTZC1_TZSC_PRIVCFGR2 + GTZC1_TZSC_PRIVCFGR2 + GTZC1 TZSC privilege configuration register 2 + 0x024 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FDCAN1PRIV + privileged access mode for FDCAN1 + 0 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + FDCAN2PRIV + privileged access mode for FDCAN2 + 1 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + UCPDPRIV + privileged access mode for UCPD + 2 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + TIM1PRIV + privileged access mode for TIM1 + 8 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + SPI1PRIV + privileged access mode for SPI1 + 9 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + TIM8PRIV + privileged access mode for TIM8 + 10 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + USART1PRIV + privileged access mode for USART1 + 11 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + TIM15PRIV + privileged access mode for TIM15 + 12 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + SPI4PRIV + privileged access mode for SPI4 + 15 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + SPI6PRIV + privileged access mode for SPI6 + 16 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + SAI1PRIV + privileged access mode for SAI1 + 17 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + SAI2PRIV + privileged access mode for SAI2 + 18 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + USBPRIV + privileged access mode for USB + 19 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + LPUART1PRIV + privileged access mode for LPUART + 25 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + I2C3PRIV + privileged access mode for I2C3 + 26 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + LPTIM1PRIV + privileged access mode for LPTIM1 + 28 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + LPTIM3PRIV + privileged access mode for LPTIM3 + 29 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + LPTIM4PRIV + privileged access mode for LPTIM4 + 30 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + LPTIM5PRIV + privileged access mode for LPTIM5 + 31 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + + + GTZC1_TZSC_PRIVCFGR3 + GTZC1_TZSC_PRIVCFGR3 + GTZC1 TZSC privilege configuration register 3 + 0x028 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LPTIM6PRIV + privileged access mode for LPTIM6 + 0 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + VREFBUFPRIV + privileged access mode for VREFBUF + 1 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + I3C2PRIV + privileged access mode for I3C2 + 2 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + CRCPRIV + privileged access mode for CRC + 8 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + CORDICPRIV + privileged access mode for CORDIC + 9 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + FMACPRIV + privileged access mode for FMAC + 10 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + ETHPRIV + privileged access mode for register of ETH + 11 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + ICACHEPRIV + privileged access mode for ICACHE + 12 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + DCACHEPRIV + privileged access mode for DCACHE + 13 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + ADC12PRIV + privileged access mode for ADC1 and ADC2 + 14 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + DCMIPRIV + privileged access mode for DCMI + 15 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + AESPRIV + privileged access mode for AES + 16 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + HASHPRIV + privileged access mode for HASH + 17 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + RNGPRIV + privileged access mode for RNG + 18 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + SAESPRIV + privileged access mode for SAES + 19 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + PKAPRIV + privileged access mode for PKA + 20 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + SDMMC1PRIV + privileged access mode for SDMMC1 + 21 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + FMCPRIV + privileged access mode for FMC + 23 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + OCTOSPI1PRIV + privileged access mode for OCTOSPI1 + 24 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + RAMCFGPRIV + privileged access mode for RAMSCFG + 26 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + + + GTZC1_TZSC_MPCWM1ACFGR + GTZC1_TZSC_MPCWM1ACFGR + GTZC1 TZSC memory 1 subregion A watermark configuration register + 0x40 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SREN + subregion A enable + + 0 + 1 + read-write + + + B_0x0 + subregion A is disabled. + 0x0 + + + B_0x1 + subregion A of region x is enabled. + 0x1 + + + + + SRLOCK + subregion A lock + + 1 + 1 + read-write + + + B_0x0 + GTZC1_TZSC_MPCWMxCFGR, GTZC1_TZSC_MPCWMxAR and GTZC1_TZSC_MPCWMxBR can be written. + 0x0 + + + B_0x1 + Writes to GTZC1_TZSC_MPCWMxCFGR, GTZC1_TZSC_MPCWMxAR and GTZC1_TZSC_MPCWMxBR are ignored. + 0x1 + + + + + SEC + Secure subregion A of base region x + + 8 + 1 + read-write + + + B_0x0 + Only non-secure data accesses are granted to subregion A of region x. + 0x0 + + + B_0x1 + Only secure data accesses are granted to subregion A of region x. + 0x1 + + + + + PRIV + Privileged subregion A of base region x + + 9 + 1 + read-write + + + B_0x0 + Privileged and unprivileged accesses are granted in subregion A. + 0x0 + + + B_0x1 + Only privileged accesses are granted in subregion A of region x. + 0x1 + + + + + + + GTZC1_TZSC_MPCWM1AR + GTZC1_TZSC_MPCWM1AR + GTZC1 TZSC memory 1 subregion A watermark register + 0x44 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SUBA_START + Start of subregion A in region x + + 0 + 11 + read-write + + + SUBA_LENGTH + Length of subregion A in region x + + 16 + 12 + read-write + + + + + GTZC1_TZSC_MPCWM1BCFGR + GTZC1_TZSC_MPCWM1BCFGR + GTZC1 TZSC memory 1 subregion B watermark configuration register + 0x48 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SREN + subregion B enable + + 0 + 1 + read-write + + + B_0x0 + subregion B is disabled. + 0x0 + + + B_0x1 + subregion B of region B is enabled. + 0x1 + + + + + SRLOCK + subregion B lock + + 1 + 1 + read-write + + + B_0x0 + GTZC1_TZSC_MPCWMxCFGR, GTZC1_TZSC_MPCWMxAR and GTZC1_TZSC_MPCWMxBR can be written. + 0x0 + + + B_0x1 + Writes to GTZC1_TZSC_MPCWMxCFGR, GTZC1_TZSC_MPCWMxAR and GTZC1_TZSC_MPCWMxBR are ignored. + 0x1 + + + + + SEC + Secure subregion B of base region x + + 8 + 1 + read-write + + + B_0x0 + Only non-secure data accesses are granted to subregion B of region x. + 0x0 + + + B_0x1 + Only secure data accesses are granted to subregion B of region x. + 0x1 + + + + + PRIV + Privileged subregion B of base region x + + 9 + 1 + read-write + + + B_0x0 + Privileged and unprivileged accesses are granted in subregion B. + 0x0 + + + B_0x1 + Only privileged accesses are granted in subregion B of region x. + 0x1 + + + + + + + GTZC1_TZSC_MPCWM1BR + GTZC1_TZSC_MPCWM1BR + GTZC1 TZSC memory 1 subregion B watermark register + 0x4C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SUBB_START + Start of subregion B in region x + + 0 + 11 + read-write + + + SUBB_LENGTH + Length of subregion B in region x + + 16 + 12 + read-write + + + + + GTZC1_TZSC_MPCWM2ACFGR + GTZC1_TZSC_MPCWM2ACFGR + GTZC1 TZSC memory 2 subregion A watermark configuration register + 0x50 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SREN + subregion A enable + + 0 + 1 + read-write + + + B_0x0 + subregion A is disabled. + 0x0 + + + B_0x1 + subregion A of region x is enabled. + 0x1 + + + + + SRLOCK + subregion A lock + + 1 + 1 + read-write + + + B_0x0 + GTZC1_TZSC_MPCWMxCFGR, GTZC1_TZSC_MPCWMxAR and GTZC1_TZSC_MPCWMxBR can be written. + 0x0 + + + B_0x1 + Writes to GTZC1_TZSC_MPCWMxCFGR, GTZC1_TZSC_MPCWMxAR and GTZC1_TZSC_MPCWMxBR are ignored. + 0x1 + + + + + SEC + Secure subregion A of base region x + + 8 + 1 + read-write + + + B_0x0 + Only non-secure data accesses are granted to subregion A of region x. + 0x0 + + + B_0x1 + Only secure data accesses are granted to subregion A of region x. + 0x1 + + + + + PRIV + Privileged subregion A of base region x + + 9 + 1 + read-write + + + B_0x0 + Privileged and unprivileged accesses are granted in subregion A. + 0x0 + + + B_0x1 + Only privileged accesses are granted in subregion A of region x. + 0x1 + + + + + + + GTZC1_TZSC_MPCWM2AR + GTZC1_TZSC_MPCWM2AR + GTZC1 TZSC memory 2 subregion A watermark register + 0x54 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SUBA_START + Start of subregion A in region x + + 0 + 11 + read-write + + + SUBA_LENGTH + Length of subregion A in region x + + 16 + 12 + read-write + + + + + GTZC1_TZSC_MPCWM2BCFGR + GTZC1_TZSC_MPCWM2BCFGR + GTZC1 TZSC memory 2 subregion B watermark configuration register + 0x58 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SREN + subregion B enable + + 0 + 1 + read-write + + + B_0x0 + subregion B is disabled. + 0x0 + + + B_0x1 + subregion B of region B is enabled. + 0x1 + + + + + SRLOCK + subregion B lock + + 1 + 1 + read-write + + + B_0x0 + GTZC1_TZSC_MPCWMxCFGR, GTZC1_TZSC_MPCWMxAR and GTZC1_TZSC_MPCWMxBR can be written. + 0x0 + + + B_0x1 + Writes to GTZC1_TZSC_MPCWMxCFGR, GTZC1_TZSC_MPCWMxAR and GTZC1_TZSC_MPCWMxBR are ignored. + 0x1 + + + + + SEC + Secure subregion B of base region x + + 8 + 1 + read-write + + + B_0x0 + Only non-secure data accesses are granted to subregion B of region x. + 0x0 + + + B_0x1 + Only secure data accesses are granted to subregion B of region x. + 0x1 + + + + + PRIV + Privileged subregion B of base region x + + 9 + 1 + read-write + + + B_0x0 + Privileged and unprivileged accesses are granted in subregion B. + 0x0 + + + B_0x1 + Only privileged accesses are granted in subregion B of region x. + 0x1 + + + + + + + GTZC1_TZSC_MPCWM2BR + GTZC1_TZSC_MPCWM2BR + GTZC1 TZSC memory 2 subregion B watermark register + 0x5C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SUBB_START + Start of subregion B in region x + + 0 + 11 + read-write + + + SUBB_LENGTH + Length of subregion B in region x + + 16 + 12 + read-write + + + + + GTZC1_TZSC_MPCWM3ACFGR + GTZC1_TZSC_MPCWM3ACFGR + GTZC1 TZSC memory 3 subregion A watermark configuration register + 0x60 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SREN + subregion A enable + + 0 + 1 + read-write + + + B_0x0 + subregion A is disabled. + 0x0 + + + B_0x1 + subregion A of region x is enabled. + 0x1 + + + + + SRLOCK + subregion A lock + + 1 + 1 + read-write + + + B_0x0 + GTZC1_TZSC_MPCWMxCFGR, GTZC1_TZSC_MPCWMxAR and GTZC1_TZSC_MPCWMxBR can be written. + 0x0 + + + B_0x1 + Writes to GTZC1_TZSC_MPCWMxCFGR, GTZC1_TZSC_MPCWMxAR and GTZC1_TZSC_MPCWMxBR are ignored. + 0x1 + + + + + SEC + Secure subregion A of base region x + + 8 + 1 + read-write + + + B_0x0 + Only non-secure data accesses are granted to subregion A of region x. + 0x0 + + + B_0x1 + Only secure data accesses are granted to subregion A of region x. + 0x1 + + + + + PRIV + Privileged subregion A of base region x + + 9 + 1 + read-write + + + B_0x0 + Privileged and unprivileged accesses are granted in subregion A. + 0x0 + + + B_0x1 + Only privileged accesses are granted in subregion A of region x. + 0x1 + + + + + + + GTZC1_TZSC_MPCWM3AR + GTZC1_TZSC_MPCWM3AR + GTZC1 TZSC memory 3 subregion A watermark register + 0x64 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SUBA_START + Start of subregion A in region x + + 0 + 11 + read-write + + + SUBA_LENGTH + Length of subregion A in region x + + 16 + 12 + read-write + + + + + GTZC1_TZSC_MPCWM3BCFGR + GTZC1_TZSC_MPCWM3BCFGR + GTZC1 TZSC memory 3 subregion B watermark configuration register + 0x68 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SREN + subregion B enable + + 0 + 1 + read-write + + + B_0x0 + subregion B is disabled. + 0x0 + + + B_0x1 + subregion B of region B is enabled. + 0x1 + + + + + SRLOCK + subregion B lock + + 1 + 1 + read-write + + + B_0x0 + GTZC1_TZSC_MPCWMxCFGR, GTZC1_TZSC_MPCWMxAR and GTZC1_TZSC_MPCWMxBR can be written. + 0x0 + + + B_0x1 + Writes to GTZC1_TZSC_MPCWMxCFGR, GTZC1_TZSC_MPCWMxAR and GTZC1_TZSC_MPCWMxBR are ignored. + 0x1 + + + + + SEC + Secure subregion B of base region x + + 8 + 1 + read-write + + + B_0x0 + Only non-secure data accesses are granted to subregion B of region x. + 0x0 + + + B_0x1 + Only secure data accesses are granted to subregion B of region x. + 0x1 + + + + + PRIV + Privileged subregion B of base region x + + 9 + 1 + read-write + + + B_0x0 + Privileged and unprivileged accesses are granted in subregion B. + 0x0 + + + B_0x1 + Only privileged accesses are granted in subregion B of region x. + 0x1 + + + + + + + GTZC1_TZSC_MPCWM3BR + GTZC1_TZSC_MPCWM3BR + GTZC1 TZSC memory 3 subregion B watermark register + 0x6C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SUBB_START + Start of subregion B in region x + + 0 + 11 + read-write + + + SUBB_LENGTH + Length of subregion B in region x + + 16 + 12 + read-write + + + + + GTZC1_TZSC_MPCWM4ACFGR + GTZC1_TZSC_MPCWM4ACFGR + GTZC1 TZSC memory 4 subregion A watermark configuration register + 0x70 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SREN + subregion A enable + + 0 + 1 + read-write + + + B_0x0 + subregion A is disabled. + 0x0 + + + B_0x1 + subregion A of region x is enabled. + 0x1 + + + + + SRLOCK + subregion A lock + + 1 + 1 + read-write + + + B_0x0 + GTZC1_TZSC_MPCWMxCFGR, GTZC1_TZSC_MPCWMxAR and GTZC1_TZSC_MPCWMxBR can be written. + 0x0 + + + B_0x1 + Writes to GTZC1_TZSC_MPCWMxCFGR, GTZC1_TZSC_MPCWMxAR and GTZC1_TZSC_MPCWMxBR are ignored. + 0x1 + + + + + SEC + Secure subregion A of base region x + + 8 + 1 + read-write + + + B_0x0 + Only non-secure data accesses are granted to subregion A of region x. + 0x0 + + + B_0x1 + Only secure data accesses are granted to subregion A of region x. + 0x1 + + + + + PRIV + Privileged subregion A of base region x + + 9 + 1 + read-write + + + B_0x0 + Privileged and unprivileged accesses are granted in subregion A. + 0x0 + + + B_0x1 + Only privileged accesses are granted in subregion A of region x. + 0x1 + + + + + + + GTZC1_TZSC_MPCWM4AR + GTZC1_TZSC_MPCWM4AR + GTZC1 TZSC memory 4 subregion A watermark register + 0x74 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SUBA_START + Start of subregion A in region x + + 0 + 11 + read-write + + + SUBA_LENGTH + Length of subregion A in region x + + 16 + 12 + read-write + + + + + GTZC1_TZSC_MPCWM4BCFGR + GTZC1_TZSC_MPCWM4BCFGR + GTZC1 TZSC memory 4 subregion B watermark configuration register + 0x78 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SREN + subregion B enable + + 0 + 1 + read-write + + + B_0x0 + subregion B is disabled. + 0x0 + + + B_0x1 + subregion B of region B is enabled. + 0x1 + + + + + SRLOCK + subregion B lock + + 1 + 1 + read-write + + + B_0x0 + GTZC1_TZSC_MPCWMxCFGR, GTZC1_TZSC_MPCWMxAR and GTZC1_TZSC_MPCWMxBR can be written. + 0x0 + + + B_0x1 + Writes to GTZC1_TZSC_MPCWMxCFGR, GTZC1_TZSC_MPCWMxAR and GTZC1_TZSC_MPCWMxBR are ignored. + 0x1 + + + + + SEC + Secure subregion B of base region x + + 8 + 1 + read-write + + + B_0x0 + Only non-secure data accesses are granted to subregion B of region x. + 0x0 + + + B_0x1 + Only secure data accesses are granted to subregion B of region x. + 0x1 + + + + + PRIV + Privileged subregion B of base region x + + 9 + 1 + read-write + + + B_0x0 + Privileged and unprivileged accesses are granted in subregion B. + 0x0 + + + B_0x1 + Only privileged accesses are granted in subregion B of region x. + 0x1 + + + + + + + GTZC1_TZSC_MPCWM4BR + GTZC1_TZSC_MPCWM4BR + GTZC1 TZSC memory 4 subregion B watermark register + 0x7C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SUBB_START + Start of subregion B in region x + + 0 + 11 + read-write + + + SUBB_LENGTH + Length of subregion B in region x + + 16 + 12 + read-write + + + + + + + GTZC1_TZSC_S + 0x50036400 + + + HASH + HASH register bank + HASH + 0x420c0400 + + 0x0 + 0x400 + registers + + + HASH + HASH interrupt + 117 + + + + HASH_CR + HASH_CR + HASH control register + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + INIT + Initialize message digest calculation + + 2 + 1 + read-write + + + DMAE + DMA enable + + 3 + 1 + read-write + + + B_0x0 + DMA transfers disabled + 0x0 + + + B_0x1 + DMA transfers enabled. + 0x1 + + + + + DATATYPE + Data type selection + + 4 + 2 + read-write + + + B_0x0 + 32-bit data. + 0x0 + + + B_0x1 + 16-bit data or half-word. + 0x1 + + + B_0x2 + 8-bit data or bytes. + 0x2 + + + B_0x3 + bit data or bit string. + 0x3 + + + + + MODE + Mode selection + + 6 + 1 + read-write + + + B_0x0 + Hash mode selected + 0x0 + + + B_0x1 + HMAC mode selected. + 0x1 + + + + + NBW + Number of words already pushed + + 8 + 4 + read-only + + + DINNE + DIN not empty + + 12 + 1 + read-only + + + MDMAT + Multiple DMA transfers + + 13 + 1 + read-write + + + B_0x0 + DCAL is automatically set at the end of a DMA transfer. + 0x0 + + + B_0x1 + DCAL is not automatically set at the end of a DMA transfer. + 0x1 + + + + + LKEY + Long key selection + + 16 + 1 + read-write + + + B_0x0 + HMAC key is shorter or equal to the block size (short key). + 0x0 + + + B_0x1 + HMAC key is longer than the block size (long key). + 0x1 + + + + + ALGO + Algorithm selection + + 17 + 4 + read-write + + + B_0x0 + SHA-1 + 0x0 + + + B_0x2 + SHA2-224 + 0x2 + + + B_0x3 + SHA2-256 + 0x3 + + + B_0xC + SHA2-384 + 0xC + + + B_0xD + SHA2-512/224 + 0xD + + + B_0xE + SHA2-512/256 + 0xE + + + B_0xF + SHA2-512 + 0xF + + + + + + + HASH_DIN + HASH_DIN + HASH data input register + 0x04 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + DATAIN + Data input + + 0 + 32 + write-only + + + + + HASH_STR + HASH_STR + HASH start register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + NBLW + Number of valid bits in the last word + + 0 + 5 + read-write + + + B_0x00 + All the 32 bits of the last data written are valid message bits, that is M[31:0] + 0x00 + + + B_0x01 + Only one bit of the last data written (after swapping) is valid, that is M[0] + 0x01 + + + B_0x02 + Only two bits of the last data written (after swapping) are valid, that is M[1:0] + 0x02 + + + B_0x03 + Only three bits of the last data written (after swapping) are valid that is M[2:0] + 0x03 + + + B_0x1F + Only 31 bits of the last data written (after swapping) are valid that is M[30:0] + 0x1F + + + + + DCAL + Digest calculation + + 8 + 1 + read-write + + + + + HASH_HRA0 + HASH_HRA0 + HASH aliased digest register 0 + 0xC + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H0 + Hash data x + + 0 + 32 + read-only + + + + + HASH_HRA1 + HASH_HRA1 + HASH aliased digest register 1 + 0x10 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H1 + Hash data x + + 0 + 32 + read-only + + + + + HASH_HRA2 + HASH_HRA2 + HASH aliased digest register 2 + 0x14 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H2 + Hash data x + + 0 + 32 + read-only + + + + + HASH_HRA3 + HASH_HRA3 + HASH aliased digest register 3 + 0x18 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H3 + Hash data x + + 0 + 32 + read-only + + + + + HASH_HRA4 + HASH_HRA4 + HASH aliased digest register 4 + 0x1C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H4 + Hash data x + + 0 + 32 + read-only + + + + + HASH_IMR + HASH_IMR + HASH interrupt enable register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DINIE + Data input interrupt enable + 0 + 1 + read-write + + + B_0x0 + Data input interrupt disabled + 0x0 + + + B_0x1 + Data input interrupt enabled + 0x1 + + + + + DCIE + Digest calculation completion interrupt enable + 1 + 1 + read-write + + + B_0x0 + Digest calculation completion interrupt disabled + 0x0 + + + B_0x1 + Digest calculation completion interrupt enabled. + 0x1 + + + + + + + HASH_SR + HASH_SR + HASH status register + 0x24 + 0x20 + read-write + 0x00110001 + 0xFFFFFFFF + + + DINIS + Data input interrupt status + + 0 + 1 + read-write + + + B_0x0 + Less than 16 locations are free in the input buffer + 0x0 + + + B_0x1 + A new block can be entered into the input buffer. + 0x1 + + + + + DCIS + Digest calculation completion interrupt status + + 1 + 1 + read-write + + + B_0x0 + No digest available in the HASH_HRx registers (zeros are returned) + 0x0 + + + B_0x1 + Digest calculation complete, a digest is available in the HASH_HRx registers. + 0x1 + + + + + DMAS + DMA Status + + 2 + 1 + read-only + + + B_0x0 + DMA interface is disabled (DMAE = 0) and no transfer is ongoing + 0x0 + + + B_0x1 + DMA interface is enabled (DMAE = 1) or a transfer is ongoing + 0x1 + + + + + BUSY + Busy bit + 3 + 1 + read-only + + + B_0x0 + No block is currently being processed + 0x0 + + + B_0x1 + The hash core is processing a block of data + 0x1 + + + + + NBWP + Number of words already pushed + + 9 + 5 + read-only + + + DINNE + DIN not empty + + 15 + 1 + read-only + + + B_0x0 + No data are present in the data input buffer + 0x0 + + + B_0x1 + The input buffer contains at least one word of data + 0x1 + + + + + NBWE + Number of words expected + + 16 + 5 + read-only + + + + + HASH_CSR0 + HASH_CSR0 + HASH context swap register 0 + 0xF8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS0 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR1 + HASH_CSR1 + HASH context swap register 1 + 0xFC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS1 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR2 + HASH_CSR2 + HASH context swap register 2 + 0x100 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS2 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR3 + HASH_CSR3 + HASH context swap register 3 + 0x104 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS3 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR4 + HASH_CSR4 + HASH context swap register 4 + 0x108 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS4 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR5 + HASH_CSR5 + HASH context swap register 5 + 0x10C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS5 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR6 + HASH_CSR6 + HASH context swap register 6 + 0x110 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS6 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR7 + HASH_CSR7 + HASH context swap register 7 + 0x114 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS7 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR8 + HASH_CSR8 + HASH context swap register 8 + 0x118 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS8 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR9 + HASH_CSR9 + HASH context swap register 9 + 0x11C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS9 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR10 + HASH_CSR10 + HASH context swap register 10 + 0x120 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS10 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR11 + HASH_CSR11 + HASH context swap register 11 + 0x124 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS11 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR12 + HASH_CSR12 + HASH context swap register 12 + 0x128 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS12 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR13 + HASH_CSR13 + HASH context swap register 13 + 0x12C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS13 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR14 + HASH_CSR14 + HASH context swap register 14 + 0x130 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS14 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR15 + HASH_CSR15 + HASH context swap register 15 + 0x134 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS15 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR16 + HASH_CSR16 + HASH context swap register 16 + 0x138 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS16 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR17 + HASH_CSR17 + HASH context swap register 17 + 0x13C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS17 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR18 + HASH_CSR18 + HASH context swap register 18 + 0x140 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS18 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR19 + HASH_CSR19 + HASH context swap register 19 + 0x144 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS19 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR20 + HASH_CSR20 + HASH context swap register 20 + 0x148 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS20 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR21 + HASH_CSR21 + HASH context swap register 21 + 0x14C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS21 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR22 + HASH_CSR22 + HASH context swap register 22 + 0x150 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS22 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR23 + HASH_CSR23 + HASH context swap register 23 + 0x154 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS23 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR24 + HASH_CSR24 + HASH context swap register 24 + 0x158 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS24 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR25 + HASH_CSR25 + HASH context swap register 25 + 0x15C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS25 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR26 + HASH_CSR26 + HASH context swap register 26 + 0x160 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS26 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR27 + HASH_CSR27 + HASH context swap register 27 + 0x164 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS27 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR28 + HASH_CSR28 + HASH context swap register 28 + 0x168 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS28 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR29 + HASH_CSR29 + HASH context swap register 29 + 0x16C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS29 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR30 + HASH_CSR30 + HASH context swap register 30 + 0x170 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS30 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR31 + HASH_CSR31 + HASH context swap register 31 + 0x174 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS31 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR32 + HASH_CSR32 + HASH context swap register 32 + 0x178 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS32 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR33 + HASH_CSR33 + HASH context swap register 33 + 0x17C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS33 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR34 + HASH_CSR34 + HASH context swap register 34 + 0x180 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS34 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR35 + HASH_CSR35 + HASH context swap register 35 + 0x184 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS35 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR36 + HASH_CSR36 + HASH context swap register 36 + 0x188 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS36 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR37 + HASH_CSR37 + HASH context swap register 37 + 0x18C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS37 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR38 + HASH_CSR38 + HASH context swap register 38 + 0x190 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS38 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR39 + HASH_CSR39 + HASH context swap register 39 + 0x194 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS39 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR40 + HASH_CSR40 + HASH context swap register 40 + 0x198 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS40 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR41 + HASH_CSR41 + HASH context swap register 41 + 0x19C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS41 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR42 + HASH_CSR42 + HASH context swap register 42 + 0x1A0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS42 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR43 + HASH_CSR43 + HASH context swap register 43 + 0x1A4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS43 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR44 + HASH_CSR44 + HASH context swap register 44 + 0x1A8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS44 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR45 + HASH_CSR45 + HASH context swap register 45 + 0x1AC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS45 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR46 + HASH_CSR46 + HASH context swap register 46 + 0x1B0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS46 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR47 + HASH_CSR47 + HASH context swap register 47 + 0x1B4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS47 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR48 + HASH_CSR48 + HASH context swap register 48 + 0x1B8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS48 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR49 + HASH_CSR49 + HASH context swap register 49 + 0x1BC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS49 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR50 + HASH_CSR50 + HASH context swap register 50 + 0x1C0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS50 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR51 + HASH_CSR51 + HASH context swap register 51 + 0x1C4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS51 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR52 + HASH_CSR52 + HASH context swap register 52 + 0x1C8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS52 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR53 + HASH_CSR53 + HASH context swap register 53 + 0x1CC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS53 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR54 + HASH_CSR54 + HASH context swap register 54 + 0x1D0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS54 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR55 + HASH_CSR55 + HASH context swap register 55 + 0x1D4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS55 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR56 + HASH_CSR56 + HASH context swap register 56 + 0x1D8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS56 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR57 + HASH_CSR57 + HASH context swap register 57 + 0x1DC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS57 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR58 + HASH_CSR58 + HASH context swap register 58 + 0x1E0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS58 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR59 + HASH_CSR59 + HASH context swap register 59 + 0x1E4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS59 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR60 + HASH_CSR60 + HASH context swap register 60 + 0x1E8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS60 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR61 + HASH_CSR61 + HASH context swap register 61 + 0x1EC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS61 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR62 + HASH_CSR62 + HASH context swap register 62 + 0x1F0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS62 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR63 + HASH_CSR63 + HASH context swap register 63 + 0x1F4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS63 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR64 + HASH_CSR64 + HASH context swap register 64 + 0x1F8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS64 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR65 + HASH_CSR65 + HASH context swap register 65 + 0x1FC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS65 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR66 + HASH_CSR66 + HASH context swap register 66 + 0x200 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS66 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR67 + HASH_CSR67 + HASH context swap register 67 + 0x204 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS67 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR68 + HASH_CSR68 + HASH context swap register 68 + 0x208 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS68 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR69 + HASH_CSR69 + HASH context swap register 69 + 0x20C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS69 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR70 + HASH_CSR70 + HASH context swap register 70 + 0x210 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS70 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR71 + HASH_CSR71 + HASH context swap register 71 + 0x214 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS71 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR72 + HASH_CSR72 + HASH context swap register 72 + 0x218 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS72 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR73 + HASH_CSR73 + HASH context swap register 73 + 0x21C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS73 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR74 + HASH_CSR74 + HASH context swap register 74 + 0x220 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS74 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR75 + HASH_CSR75 + HASH context swap register 75 + 0x224 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS75 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR76 + HASH_CSR76 + HASH context swap register 76 + 0x228 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS76 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR77 + HASH_CSR77 + HASH context swap register 77 + 0x22C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS77 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR78 + HASH_CSR78 + HASH context swap register 78 + 0x230 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS78 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR79 + HASH_CSR79 + HASH context swap register 79 + 0x234 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS79 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR80 + HASH_CSR80 + HASH context swap register 80 + 0x238 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS80 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR81 + HASH_CSR81 + HASH context swap register 81 + 0x23C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS81 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR82 + HASH_CSR82 + HASH context swap register 82 + 0x240 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS82 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR83 + HASH_CSR83 + HASH context swap register 83 + 0x244 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS83 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR84 + HASH_CSR84 + HASH context swap register 84 + 0x248 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS84 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR85 + HASH_CSR85 + HASH context swap register 85 + 0x24C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS85 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR86 + HASH_CSR86 + HASH context swap register 86 + 0x250 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS86 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR87 + HASH_CSR87 + HASH context swap register 87 + 0x254 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS87 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR88 + HASH_CSR88 + HASH context swap register 88 + 0x258 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS88 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR89 + HASH_CSR89 + HASH context swap register 89 + 0x25C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS89 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR90 + HASH_CSR90 + HASH context swap register 90 + 0x260 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS90 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR91 + HASH_CSR91 + HASH context swap register 91 + 0x264 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS91 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR92 + HASH_CSR92 + HASH context swap register 92 + 0x268 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS92 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR93 + HASH_CSR93 + HASH context swap register 93 + 0x26C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS93 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR94 + HASH_CSR94 + HASH context swap register 94 + 0x270 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS94 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR95 + HASH_CSR95 + HASH context swap register 95 + 0x274 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS95 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR96 + HASH_CSR96 + HASH context swap register 96 + 0x278 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS96 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR97 + HASH_CSR97 + HASH context swap register 97 + 0x27C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS97 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR98 + HASH_CSR98 + HASH context swap register 98 + 0x280 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS98 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR99 + HASH_CSR99 + HASH context swap register 99 + 0x284 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS99 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR100 + HASH_CSR100 + HASH context swap register 100 + 0x288 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS100 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR101 + HASH_CSR101 + HASH context swap register 101 + 0x28C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS101 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR102 + HASH_CSR102 + HASH context swap register 102 + 0x290 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS102 + Context swap x + + 0 + 32 + read-write + + + + + HASH_HR0 + HASH_HR0 + HASH digest register 0 + 0x310 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H0 + Hash data x + + 0 + 32 + read-only + + + + + HASH_HR1 + HASH_HR1 + HASH digest register 1 + 0x314 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H1 + Hash data x + + 0 + 32 + read-only + + + + + HASH_HR2 + HASH_HR2 + HASH digest register 2 + 0x318 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H2 + Hash data x + + 0 + 32 + read-only + + + + + HASH_HR3 + HASH_HR3 + HASH digest register 3 + 0x31C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H3 + Hash data x + + 0 + 32 + read-only + + + + + HASH_HR4 + HASH_HR4 + HASH digest register 4 + 0x320 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H4 + Hash data x + + 0 + 32 + read-only + + + + + HASH_HR5 + HASH_HR5 + HASH supplementary digest register 5 + 0x324 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H5 + Hash data x + + 0 + 32 + read-only + + + + + HASH_HR6 + HASH_HR6 + HASH supplementary digest register 6 + 0x328 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H6 + Hash data x + + 0 + 32 + read-only + + + + + HASH_HR7 + HASH_HR7 + HASH supplementary digest register 7 + 0x32C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H7 + Hash data x + + 0 + 32 + read-only + + + + + HASH_HR8 + HASH_HR8 + HASH supplementary digest register 8 + 0x330 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H8 + Hash data x + + 0 + 32 + read-only + + + + + HASH_HR9 + HASH_HR9 + HASH supplementary digest register 9 + 0x334 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H9 + Hash data x + + 0 + 32 + read-only + + + + + HASH_HR10 + HASH_HR10 + HASH supplementary digest register 10 + 0x338 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H10 + Hash data x + + 0 + 32 + read-only + + + + + HASH_HR11 + HASH_HR11 + HASH supplementary digest register 11 + 0x33C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H11 + Hash data x + + 0 + 32 + read-only + + + + + HASH_HR12 + HASH_HR12 + HASH supplementary digest register 12 + 0x340 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H12 + Hash data x + + 0 + 32 + read-only + + + + + HASH_HR13 + HASH_HR13 + HASH supplementary digest register 13 + 0x344 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H13 + Hash data x + + 0 + 32 + read-only + + + + + HASH_HR14 + HASH_HR14 + HASH supplementary digest register 14 + 0x348 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H14 + Hash data x + + 0 + 32 + read-only + + + + + HASH_HR15 + HASH_HR15 + HASH supplementary digest register 15 + 0x34C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H15 + Hash data x + + 0 + 32 + read-only + + + + + + + HASH_S + 0X520C0400 + + + I2C + I2C address block description + I2C + 0x40005400 + + 0x0 + 0x2C + registers + + + I2C1_ERR + I2C1 error interrupt + 52 + + + I2C1_EV + I2C1 event interrupt + 51 + + + + I2C_CR1 + I2C_CR1 + I2C control register 1 + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PE + Peripheral enable + + 0 + 1 + read-write + + + B_0x0 + Peripheral disabled + 0x0 + + + B_0x1 + Peripheral enabled + 0x1 + + + + + TXIE + TX interrupt enable + 1 + 1 + read-write + + + B_0x0 + Transmit (TXIS) interrupt disabled + 0x0 + + + B_0x1 + Transmit (TXIS) interrupt enabled + 0x1 + + + + + RXIE + RX interrupt enable + 2 + 1 + read-write + + + B_0x0 + Receive (RXNE) interrupt disabled + 0x0 + + + B_0x1 + Receive (RXNE) interrupt enabled + 0x1 + + + + + ADDRIE + Address match interrupt enable (slave only) + 3 + 1 + read-write + + + B_0x0 + Address match (ADDR) interrupts disabled + 0x0 + + + B_0x1 + Address match (ADDR) interrupts enabled + 0x1 + + + + + NACKIE + Not acknowledge received interrupt enable + 4 + 1 + read-write + + + B_0x0 + Not acknowledge (NACKF) received interrupts disabled + 0x0 + + + B_0x1 + Not acknowledge (NACKF) received interrupts enabled + 0x1 + + + + + STOPIE + Stop detection interrupt enable + 5 + 1 + read-write + + + B_0x0 + Stop detection (STOPF) interrupt disabled + 0x0 + + + B_0x1 + Stop detection (STOPF) interrupt enabled + 0x1 + + + + + TCIE + Transfer complete interrupt enable + + 6 + 1 + read-write + + + B_0x0 + Transfer complete interrupt disabled + 0x0 + + + B_0x1 + Transfer complete interrupt enabled + 0x1 + + + + + ERRIE + Error interrupts enable + + 7 + 1 + read-write + + + B_0x0 + Error detection interrupts disabled + 0x0 + + + B_0x1 + Error detection interrupts enabled + 0x1 + + + + + DNF + Digital noise filter + + 8 + 4 + read-write + + + B_0x0 + Digital filter disabled + 0x0 + + + B_0x1 + Digital filter enabled and filtering capability up to one tless thansub>I2CCLKless than/sub> + 0x1 + + + B_0xF + digital filter enabled and filtering capability up to fifteen tless thansub>I2CCLKless than/sub> + 0xF + + + + + ANFOFF + Analog noise filter OFF + + 12 + 1 + read-write + + + B_0x0 + Analog noise filter enabled + 0x0 + + + B_0x1 + Analog noise filter disabled + 0x1 + + + + + TXDMAEN + DMA transmission requests enable + 14 + 1 + read-write + + + B_0x0 + DMA mode disabled for transmission + 0x0 + + + B_0x1 + DMA mode enabled for transmission + 0x1 + + + + + RXDMAEN + DMA reception requests enable + 15 + 1 + read-write + + + B_0x0 + DMA mode disabled for reception + 0x0 + + + B_0x1 + DMA mode enabled for reception + 0x1 + + + + + SBC + Slave byte control + + 16 + 1 + read-write + + + B_0x0 + Slave byte control disabled + 0x0 + + + B_0x1 + Slave byte control enabled + 0x1 + + + + + NOSTRETCH + Clock stretching disable + + 17 + 1 + read-write + + + B_0x0 + Clock stretching enabled + 0x0 + + + B_0x1 + Clock stretching disabled + 0x1 + + + + + WUPEN + Wake-up from Stop mode enable + + 18 + 1 + read-write + + + B_0x0 + Wake-up from Stop mode disabled. + 0x0 + + + B_0x1 + Wake-up from Stop mode enabled. + 0x1 + + + + + GCEN + General call enable + 19 + 1 + read-write + + + B_0x0 + General call disabled. + 0x0 + + + B_0x1 + General call enabled. + 0x1 + + + + + SMBHEN + SMBus host address enable + + 20 + 1 + read-write + + + B_0x0 + Host address disabled. + 0x0 + + + B_0x1 + Host address enabled. + 0x1 + + + + + SMBDEN + SMBus device default address enable + + 21 + 1 + read-write + + + B_0x0 + Device default address disabled. + 0x0 + + + B_0x1 + Device default address enabled. + 0x1 + + + + + ALERTEN + SMBus alert enable + + 22 + 1 + read-write + + + B_0x0 + The SMBus alert pin (SMBA) is not supported in host mode (SMBHEN = 1). + 0x0 + + + B_0x1 + The SMBus alert pin is supported in host mode (SMBHEN = 1). + 0x1 + + + + + PECEN + PEC enable + + 23 + 1 + read-write + + + B_0x0 + PEC calculation disabled + 0x0 + + + B_0x1 + PEC calculation enabled + 0x1 + + + + + FMP + Fast-mode Plus 20 mA drive enable + 24 + 1 + read-write + + + B_0x0 + 20 mA I/O drive disabled + 0x0 + + + B_0x1 + 20 mA I/O drive enabled + 0x1 + + + + + ADDRACLR + Address match flag (ADDR) automatic clear + 30 + 1 + read-write + + + B_0x0 + ADDR flag is set by hardware, cleared by software by setting ADDRCF bit. + 0x0 + + + B_0x1 + ADDR flag remains cleared by hardware. + 0x1 + + + + + STOPFACLR + STOP detection flag (STOPF) automatic clear + 31 + 1 + read-write + + + B_0x0 + STOPF flag is set by hardware, cleared by software by setting STOPCF bit. + 0x0 + + + B_0x1 + STOPF flag remains cleared by hardware. + 0x1 + + + + + + + I2C_CR2 + I2C_CR2 + I2C control register 2 + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SADD + Slave address (master mode) + + 0 + 10 + read-write + + + RD_WRN + Transfer direction (master mode) + + 10 + 1 + read-write + + + B_0x0 + Master requests a write transfer + 0x0 + + + B_0x1 + Master requests a read transfer + 0x1 + + + + + ADD10 + 10-bit addressing mode (master mode) + + 11 + 1 + read-write + + + B_0x0 + The master operates in 7-bit addressing mode + 0x0 + + + B_0x1 + The master operates in 10-bit addressing mode + 0x1 + + + + + HEAD10R + 10-bit address header only read direction (master receiver mode) + + 12 + 1 + read-write + + + B_0x0 + The master sends the complete 10-bit slave address read sequence: Start + 2 bytes 10-bit address in write direction + restart + first seven bits of the 10-bit address in read direction. + 0x0 + + + B_0x1 + The master sends only the first seven bits of the 10-bit address, followed by read direction. + 0x1 + + + + + START + Start generation + + 13 + 1 + read-write + + + B_0x0 + No Start generation + 0x0 + + + B_0x1 + Restart/Start generation: + 0x1 + + + + + STOP + Stop generation (master mode) + + 14 + 1 + read-write + + + B_0x0 + No Stop generation + 0x0 + + + B_0x1 + Stop generation after current byte transfer + 0x1 + + + + + NACK + NACK generation (slave mode) + + 15 + 1 + read-write + + + B_0x0 + an ACK is sent after current received byte. + 0x0 + + + B_0x1 + a NACK is sent after current received byte. + 0x1 + + + + + NBYTES + Number of bytes + + 16 + 8 + read-write + + + RELOAD + NBYTES reload mode + + 24 + 1 + read-write + + + B_0x0 + The transfer is completed after the NBYTES data transfer (STOP or RESTART follows). + 0x0 + + + B_0x1 + The transfer is not completed after the NBYTES data transfer (NBYTES is reloaded). + 0x1 + + + + + AUTOEND + Automatic end mode (master mode) + + 25 + 1 + read-write + + + B_0x0 + software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low. + 0x0 + + + B_0x1 + Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred. + 0x1 + + + + + PECBYTE + Packet error checking byte + + 26 + 1 + read-write + + + B_0x0 + No PEC transfer + 0x0 + + + B_0x1 + PEC transmission/reception is requested + 0x1 + + + + + + + I2C_OAR1 + I2C_OAR1 + I2C own address 1 register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OA1 + Interface own slave address + + 0 + 10 + read-write + + + OA1MODE + Own address 1 10-bit mode + + 10 + 1 + read-write + + + B_0x0 + Own address 1 is a 7-bit address. + 0x0 + + + B_0x1 + Own address 1 is a 10-bit address. + 0x1 + + + + + OA1EN + Own address 1 enable + 15 + 1 + read-write + + + B_0x0 + Own address 1 disabled. + 0x0 + + + B_0x1 + Own address 1 enabled. + 0x1 + + + + + + + I2C_OAR2 + I2C_OAR2 + I2C own address 2 register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OA2 + Interface address + + 1 + 7 + read-write + + + OA2MSK + Own address 2 masks + + 8 + 3 + read-write + + + B_0x0 + No mask + 0x0 + + + B_0x1 + OA2[1] is masked and don't care. + 0x1 + + + B_0x2 + OA2[2:1] are masked and don't care. + 0x2 + + + B_0x3 + OA2[3:1] are masked and don't care. + 0x3 + + + B_0x4 + OA2[4:1] are masked and don't care. + 0x4 + + + B_0x5 + OA2[5:1] are masked and don't care. + 0x5 + + + B_0x6 + OA2[6:1] are masked and don't care. + 0x6 + + + B_0x7 + OA2[7:1] are masked and don't care. + 0x7 + + + + + OA2EN + Own address 2 enable + 15 + 1 + read-write + + + B_0x0 + Own address 2 disabled. + 0x0 + + + B_0x1 + Own address 2 enabled. + 0x1 + + + + + + + I2C_TIMINGR + I2C_TIMINGR + I2C timing register + 0x10 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SCLL + SCL low period (master mode) + + 0 + 8 + read-write + + + SCLH + SCL high period (master mode) + + 8 + 8 + read-write + + + SDADEL + Data hold time + + 16 + 4 + read-write + + + SCLDEL + Data setup time + + 20 + 4 + read-write + + + PRESC + Timing prescaler + + 28 + 4 + read-write + + + + + I2C_TIMEOUTR + I2C_TIMEOUTR + I2C timeout register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TIMEOUTA + Bus timeout A + + 0 + 12 + read-write + + + TIDLE + Idle clock timeout detection + + 12 + 1 + read-write + + + B_0x0 + TIMEOUTA is used to detect SCL low timeout + 0x0 + + + B_0x1 + TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition) + 0x1 + + + + + TIMOUTEN + Clock timeout enable + 15 + 1 + read-write + + + B_0x0 + SCL timeout detection is disabled + 0x0 + + + B_0x1 + SCL timeout detection is enabled. + 0x1 + + + + + TIMEOUTB + Bus timeout B + + 16 + 12 + read-write + + + TEXTEN + Extended clock timeout enable + 31 + 1 + read-write + + + B_0x0 + Extended clock timeout detection is disabled + 0x0 + + + B_0x1 + Extended clock timeout detection is enabled. + 0x1 + + + + + + + I2C_ISR + I2C_ISR + I2C interrupt and status register + 0x18 + 0x20 + read-write + 0x00000001 + 0xFFFFFFFF + + + TXE + Transmit data register empty (transmitters) + + 0 + 1 + read-write + + + TXIS + Transmit interrupt status (transmitters) + + 1 + 1 + read-write + + + RXNE + Receive data register not empty (receivers) + + 2 + 1 + read-only + + + ADDR + Address matched (slave mode) + + 3 + 1 + read-only + + + NACKF + Not acknowledge received flag + + 4 + 1 + read-only + + + STOPF + Stop detection flag + + 5 + 1 + read-only + + + TC + Transfer complete (master mode) + + 6 + 1 + read-only + + + TCR + Transfer complete reload + + 7 + 1 + read-only + + + BERR + Bus error + + 8 + 1 + read-only + + + ARLO + Arbitration lost + + 9 + 1 + read-only + + + OVR + Overrun/underrun (slave mode) + + 10 + 1 + read-only + + + PECERR + PEC error in reception + + 11 + 1 + read-only + + + TIMEOUT + Timeout or tless thansub>LOWless than/sub> detection flag + + 12 + 1 + read-only + + + ALERT + SMBus alert + + 13 + 1 + read-only + + + BUSY + Bus busy + + 15 + 1 + read-only + + + DIR + Transfer direction (slave mode) + + 16 + 1 + read-only + + + B_0x0 + Write transfer, slave enters receiver mode. + 0x0 + + + B_0x1 + Read transfer, slave enters transmitter mode. + 0x1 + + + + + ADDCODE + Address match code (slave mode) + + 17 + 7 + read-only + + + + + I2C_ICR + I2C_ICR + I2C interrupt clear register + 0x1C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + ADDRCF + Address matched flag clear + + 3 + 1 + write-only + + + NACKCF + Not acknowledge flag clear + + 4 + 1 + write-only + + + STOPCF + STOP detection flag clear + + 5 + 1 + write-only + + + BERRCF + Bus error flag clear + + 8 + 1 + write-only + + + ARLOCF + Arbitration lost flag clear + + 9 + 1 + write-only + + + OVRCF + Overrun/underrun flag clear + + 10 + 1 + write-only + + + PECCF + PEC error flag clear + + 11 + 1 + write-only + + + TIMOUTCF + Timeout detection flag clear + + 12 + 1 + write-only + + + ALERTCF + Alert flag clear + + 13 + 1 + write-only + + + + + I2C_PECR + I2C_PECR + I2C PEC register + 0x20 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + PEC + Packet error checking register + + 0 + 8 + read-only + + + + + I2C_RXDR + I2C_RXDR + I2C receive data register + 0x24 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RXDATA + 8-bit receive data + + 0 + 8 + read-only + + + + + I2C_TXDR + I2C_TXDR + I2C transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TXDATA + 8-bit transmit data + + 0 + 8 + read-write + + + + + + + I2C_S + 0X50005400 + + + I2C2 + 0x40005800 + + I2C2_ERR + I2C2 error interrupt + 54 + + + I2C2_EV + I2C2 event interrupt + 53 + + + + I2C2_S + 0x50005800 + + + I2C3 + 0x44002800 + + I2C3_ERR + I2C3 error interrupt + 81 + + + I2C3_EV + I2C3 event interrupt + 80 + + + + I2C3_S + 0x54002800 + + + I3C + I3C register block + I3C + 0x40005c00 + + 0x0 + 0x400 + registers + + + I3C1_ERR + I3C1 error interrupt + 124 + + + I3C1_EV + I3C1 event interrupt + 123 + + + + I3C_CR + I3C_CR + I3C message control register + 0x000 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + DCNT + Count of data to transfer during a read or write message, in bytes (whatever I3C acts as controller/target) + + 0 + 16 + write-only + + + B_0x0000 + no data to transfer + 0x0000 + + + B_0x0001 + 1 byte + 0x0001 + + + B_0x0002 + 2 bytes + 0x0002 + + + B_0xFFFF + 64 Kbytes - 1 byte + 0xFFFF + + + + + RNW + Read / non-write message (when I3C acts as controller) + + 16 + 1 + write-only + + + B_0x0 + write message + 0x0 + + + B_0x1 + read message + 0x1 + + + + + ADD + 7-bit I3C dynamic / Iless thansup>2less than/sup>C static target address (when I3C acts as controller) + + 17 + 7 + write-only + + + MTYPE + Message type (whatever I3C acts as controller/target) + + 27 + 4 + write-only + + + B_0x0_WHEN_I3C_ACTS_AS_I3C_CONTROLLER + SCL clock is forced to stop until a next control word is executed + 0x0 + + + B_0x1_WHEN_I3C_ACTS_AS_I3C_CONTROLLER + header message + 0x1 + + + B_0x2_WHEN_I3C_ACTS_AS_I3C_CONTROLLER + private message (refer to Figure 665) + 0x2 + + + B_0x3_WHEN_I3C_ACTS_AS_I3C_CONTROLLER + direct message (second part of an I3C SDR direct CCC command) (refer to Figure 658) + 0x3 + + + B_0x4_WHEN_I3C_ACTS_AS_I3C_CONTROLLER + legacy Iless thansup>2less than/sup>C message (refer to Figure 667) + 0x4 + + + B_0x8_WHEN_I3C_ACTS_AS_I3C_TARGET + hot-join request (W) (refer to Figure 669) + 0x8 + + + B_0x9_WHEN_I3C_ACTS_AS_I3C_TARGET + controller-role request (W) (refer to Figure 670) + 0x9 + + + B_0xA_WHEN_I3C_ACTS_AS_I3C_TARGET + IBI (in-band interrupt) request (R) (refer to Figure 668) + 0xA + + + + + MEND + Message end type/last message of a frame (when the I3C acts as controller) + 31 + 1 + write-only + + + B_0x0 + this message from controller is followed by a repeated start (Sr), before another message must be emitted + 0x0 + + + B_0x1 + this message from controller ends with a stop (P), being the last message of a frame + 0x1 + + + + + + + I3C_CR_ALTERNATE1 + I3C_CR_ALTERNATE1 + I3C message control register + I3C_CR + 0x000 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + DCNT + Count of related data to the CCC command to transfer as CCC defining bytes, or CCC sub-command bytes, or CCC data bytes, in bytes + + 0 + 16 + write-only + + + B_0x0000 + no data to transfer. + 0x0000 + + + B_0x0001 + 1 byte + 0x0001 + + + B_0x0002 + 2 bytes + 0x0002 + + + B_0xFFFF + 64 Kbytes - 1 byte + 0xFFFF + + + + + CCC + 8-bit CCC code (when I3C acts as controller) + + 16 + 8 + write-only + + + MTYPE + Message type (when I3C acts as controller) + + 27 + 4 + write-only + + + B_0x6_WHEN_I3C_ACTS_AS_I3C_CONTROLLER + broadcast/direct CCC command (refer to Table 540, Figure 658, Figure 659, Figure 660) + 0x6 + + + + + MEND + Message end type/last message of a frame (when I3C acts as controller) + 31 + 1 + write-only + + + B_0x0 + this message from controller is followed by a repeated start (Sr), before another message must be emitted + 0x0 + + + B_0x1 + the message from the controller ends with a stop (P), being the last message of a frame + 0x1 + + + + + + + I3C_CFGR + I3C_CFGR + I3C configuration register + 0x004 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EN + I3C enable (whatever I3C acts as controller/target) + + 0 + 1 + read-write + + + B_0x0 + I3C is disabled + 0x0 + + + B_0x1 + I3C is enabled + 0x1 + + + + + CRINIT + Initial controller/target role + + 1 + 1 + read-write + + + B_0x0 + target role + 0x0 + + + B_0x1 + controller role + 0x1 + + + + + NOARBH + No arbitrable header after a start (when I3C acts as a controller) + + 2 + 1 + read-write + + + B_0x0 + An arbitrable header (0b111_1110 + RnW = 0) is emitted after a start and before a legacy Iless thansup>2less than/sup>C message or an I3C SDR private read/write message (default). + 0x0 + + + B_0x1 + No arbitrable header + 0x1 + + + + + RSTPTRN + HDR reset pattern enable (when I3C acts as a controller) + + 3 + 1 + read-write + + + B_0x0 + standard stop emitted at the end of a frame + 0x0 + + + B_0x1 + HDR reset pattern is inserted before the stop of any emitted frame that includes a RSTACT CCC command + 0x1 + + + + + EXITPTRN + HDR exit pattern enable (when I3C acts as a controller) + + 4 + 1 + read-write + + + B_0x0 + HDR exit pattern is not sent after the issued message header (MTYPE[3:0] = 0001 in the I3C_CR register). + 0x0 + + + B_0x1 + HDR exit pattern is sent after the issued message header (MTYPE[3:0] = 0001). + 0x1 + + + + + HKSDAEN + High-keeper enable on SDA line (when I3C acts as a controller) + + 5 + 1 + read-write + + + B_0x0 + High-keeper is disabled + 0x0 + + + B_0x1 + High-keeper is enabled, and the weak pull-up is effective on the T bit, instead of the open-drain class pull-up. + 0x1 + + + + + HJACK + Hot-join request acknowledge (when I3C acts as a controller) + + 7 + 1 + read-write + + + B_0x0 + hot-join request is not acknowledged + 0x0 + + + B_0x1 + hot-join request is acknowledged + 0x1 + + + + + RXDMAEN + RX-FIFO DMA request enable (whatever I3C acts as controller/target) + + 8 + 1 + read-write + + + B_0x0 + DMA mode is disabled for RX-FIFO + 0x0 + + + B_0x1 + DMA mode is enabled for RX-FIFO + 0x1 + + + + + RXFLUSH + RX-FIFO flush (whatever I3C acts as controller/target) + + 9 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + flush RX-FIFO + 0x1 + + + + + RXTHRES + RX-FIFO threshold (whatever I3C acts as controller/target) + + 10 + 1 + read-write + + + B_0x0 + 1-byte threshold + 0x0 + + + B_0x1 + 1-word/4-bytes threshold + 0x1 + + + + + TXDMAEN + TX-FIFO DMA request enable (whatever I3C acts as controller/target) + + 12 + 1 + read-write + + + B_0x0 + DMA mode is disabled for TX-FIFO + 0x0 + + + B_0x1 + DMA mode is enabled for TX-FIFO + 0x1 + + + + + TXFLUSH + TX-FIFO flush (whatever I3C acts as controller/target) + + 13 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + flush TX-FIFO + 0x1 + + + + + TXTHRES + TX-FIFO threshold (whatever I3C acts as controller/target) + + 14 + 1 + read-write + + + B_0x0 + 1-byte threshold + 0x0 + + + B_0x1 + 1-word / 4-byte threshold + 0x1 + + + + + SDMAEN + S-FIFO DMA request enable (when I3C acts as controller) + + 16 + 1 + read-write + + + B_0x0 + DMA mode is disabled for reading status register I3C_SR + 0x0 + + + B_0x1 + DMA mode is enabled for reading status register I3C_SR + 0x1 + + + + + SFLUSH + S-FIFO flush (when I3C acts as controller) + + 17 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + flush S-FIFO + 0x1 + + + + + SMODE + S-FIFO enable / status receive mode (when I3C acts as controller) + + 18 + 1 + read-write + + + B_0x0 + S-FIFO is disabled + 0x0 + + + B_0x1 + S-FIFO is enabled. + 0x1 + + + + + TMODE + Transmit mode (when I3C acts as controller) + + 19 + 1 + read-write + + + B_0x0 + C-FIFO and TX-FIFO are not preloaded before starting to emit a frame transfer. + 0x0 + + + B_0x1 + C-FIFO and TX-FIFO are first preloaded (also TX-FIFO if needed, depending on the frame format) before starting to emit a frame transfer. + 0x1 + + + + + CDMAEN + C-FIFO DMA request enable (when I3C acts as controller) + + 20 + 1 + read-write + + + B_0x0 + DMA mode is disabled for C-FIFO + 0x0 + + + B_0x1 + DMA mode is enabled for C-FIFO + 0x1 + + + + + CFLUSH + C-FIFO flush (when I3C acts as controller) + + 21 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + flush C-FIFO + 0x1 + + + + + TSFSET + Frame transfer set (software trigger) (when I3C acts as controller) + + 30 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + setting this bit initiates a frame transfer by causing the hardware to assert the flag CFNFF in the I3C_EVR register (C-FIFO not full and a control word is needed) + 0x1 + + + + + + + I3C_RDR + I3C_RDR + I3C receive data byte register + 0x010 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RDB0 + 8-bit received data on I3C bus. + 0 + 8 + read-only + + + + + I3C_RDWR + I3C_RDWR + I3C receive data word register + 0x014 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RDB0 + 8-bit received data (earliest byte on I3C bus). + 0 + 8 + read-only + + + RDB1 + 8-bit received data (next byte after RDB0 on I3C bus). + 8 + 8 + read-only + + + RDB2 + 8-bit received data (next byte after RDB1 on I3C bus). + 16 + 8 + read-only + + + RDB3 + 8-bit received data (latest byte on I3C bus). + 24 + 8 + read-only + + + + + I3C_TDR + I3C_TDR + I3C transmit data byte register + 0x018 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + TDB0 + 8-bit data to transmit on I3C bus. + 0 + 8 + write-only + + + + + I3C_TDWR + I3C_TDWR + I3C transmit data word register + 0x01C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + TDB0 + 8-bit transmit data (earliest byte on I3C bus) + 0 + 8 + write-only + + + TDB1 + 8-bit transmit data (next byte after TDB0[7:0] on I3C bus). + 8 + 8 + write-only + + + TDB2 + 8-bit transmit data (next byte after TDB1[7:0] on I3C bus). + 16 + 8 + write-only + + + TDB3 + 8-bit transmit data (latest byte on I3C bus). + 24 + 8 + write-only + + + + + I3C_IBIDR + I3C_IBIDR + I3C IBI payload data register + 0x020 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IBIDB0 + 8-bit IBI payload data (earliest byte on I3C bus, MDB[7:0] mandatory data byte). + 0 + 8 + read-write + + + IBIDB1 + 8-bit IBI payload data (next byte on I3C bus after IBIDB0[7:0]). + 8 + 8 + read-write + + + IBIDB2 + 8-bit IBI payload data (next byte on I3C bus after IBIDB1[7:0]). + 16 + 8 + read-write + + + IBIDB3 + 8-bit IBI payload data (latest byte on I3C bus). + 24 + 8 + read-write + + + + + I3C_TGTTDR + I3C_TGTTDR + I3C target transmit configuration register + 0x024 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TGTTDCNT + Transmit data counter, in bytes (when I3C is configured as target) + + 0 + 16 + read-write + + + PRELOAD + Preload of the TX-FIFO (when I3C is configured as target) + + 16 + 1 + read-write + + + B_0x0 + no TX-FIFO preload + 0x0 + + + B_0x1 + TX-FIFO preload + 0x1 + + + + + + + I3C_SR + I3C_SR + I3C status register + 0x030 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + XDCNT + Data counter + + 0 + 16 + read-only + + + ABT + A private read message is ended prematurely by the target (when the I3C acts as controller) + + 17 + 1 + read-only + + + B_0x0 + no early completion from the target + 0x0 + + + B_0x1 + early completion from the target + 0x1 + + + + + DIR + Message direction + + 18 + 1 + read-only + + + B_0x0 + write + 0x0 + + + B_0x1 + read + 0x1 + + + + + MID + Message identifier/counter of a given frame (when the I3C acts as controller) + + 24 + 8 + read-only + + + + + I3C_SER + I3C_SER + I3C status error register + 0x034 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + CODERR + Protocol error code/type + + 0 + 4 + read-only + + + B_0x0 + CE0 error (transaction after sending CCC): + 0x0 + + + B_0x1 + CE1 error (monitoring error): + 0x1 + + + B_0x2 + CE2 error (no response to broadcast address): + 0x2 + + + B_0x3 + CE3 error (failed controller-role hand-off): + 0x3 + + + B_0x8 + TE0 error (invalid broadcast address 0b111_1110 + W): + 0x8 + + + B_0x9 + TE1 error (CCC code): + 0x9 + + + B_0xA + TE2 error (write data): + 0xA + + + B_0xB + TE3 error (assigned address during dynamic address arbitration): + 0xB + + + B_0xC + TE4 error (0b111_1110 + R missing after Sr during dynamic address arbitration): + 0xC + + + B_0xD + TE5 error (transaction after detecting CCC): + 0xD + + + B_0xE + TE6 error (monitoring error): + 0xE + + + + + PERR + Protocol error + 4 + 1 + read-only + + + B_0x0 + no detected error + 0x0 + + + B_0x1 + whatever controller or target, hardware detected a protocol error, as detailed in CODERR[3:0] + 0x1 + + + + + STALL + SCL stall error (when the I3C acts as target) + 5 + 1 + read-only + + + B_0x0 + no detected error + 0x0 + + + B_0x1 + target detected that SCL was stable for more than 125 s during an I3C SDR data read (during a direct CCC read, a private read, or an IB) + 0x1 + + + + + DOVR + RX-FIFO overrun or TX-FIFO underrun + + 6 + 1 + read-only + + + B_0x0 + no detected error + 0x0 + + + B_0x1 + whatever controller or target, hardware detected either: + 0x1 + + + + + COVR + C-FIFO underrun or S-FIFO overrun (when the I3C acts as controller) + + 7 + 1 + read-only + + + B_0x0 + no detected error + 0x0 + + + B_0x1 + controller detected either: + 0x1 + + + + + ANACK + Address not acknowledged (when the I3C is configured as controller) + + 8 + 1 + read-only + + + B_0x0 + no detected error + 0x0 + + + B_0x1 + controller detected that the static/dynamic address was not acknowledged by a target, either during: + 0x1 + + + + + DNACK + Data not acknowledged (when the I3C acts as controller) + + 9 + 1 + read-only + + + B_0x0 + no detected error + 0x0 + + + B_0x1 + controller detected that a data byte is not acknowledged by a target, either during: + 0x1 + + + + + DERR + Data error (when the I3C acts as controller) + 10 + 1 + read-only + + + B_0x0 + no detected error + 0x0 + + + B_0x1 + controller detected a data error during the controller-role hand-off procedure (GETACCCR CCC, formerly known as GETACCMST) when the received target address or/and the parity bit do no match. + 0x1 + + + + + + + I3C_RMR + I3C_RMR + I3C received message register + 0x040 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + IBIRDCNT + IBI received payload data count (when the I3C is configured as controller) + + 0 + 3 + read-only + + + RCODE + Received CCC code (when the I3C is configured as target) + + 8 + 8 + read-only + + + RADD + Received target address (when the I3C is configured as controller) + + 17 + 7 + read-only + + + + + I3C_EVR + I3C_EVR + I3C event register + 0x050 + 0x20 + read-only + 0x00000003 + 0xFFFFFFFF + + + CFEF + C-FIFO empty flag (whatever the I3C acts as controller) + + 0 + 1 + read-only + + + TXFEF + TX-FIFO empty flag (whatever the I3C acts as controller/target) + + 1 + 1 + read-only + + + CFNFF + C-FIFO not full flag (when the I3C acts as controller) + + 2 + 1 + read-only + + + SFNEF + S-FIFO not empty flag (when the I3C acts as controller) + + 3 + 1 + read-only + + + TXFNFF + TX-FIFO not full flag (whatever the I3C acts as controller/target) + + 4 + 1 + read-only + + + RXFNEF + RX-FIFO not empty flag (whatever the I3C acts as controller/target) + + 5 + 1 + read-only + + + TXLASTF + Last written data byte/word flag (whatever the I3C acts as controller/target) + + 6 + 1 + read-only + + + RXLASTF + Last read data byte/word flag (when the I3C acts as controller) + + 7 + 1 + read-only + + + FCF + Frame complete flag (whatever the I3C acts as controller/target) + + 9 + 1 + read-only + + + RXTGTENDF + Target-initiated read end flag (when the I3C acts as controller) + + 10 + 1 + read-only + + + ERRF + Flag (whatever the I3C acts as controller/target) + + 11 + 1 + read-only + + + IBIF + IBI flag (when the I3C acts as controller) + + 15 + 1 + read-only + + + IBIENDF + IBI end flag (when the I3C acts as target) + + 16 + 1 + read-only + + + CRF + Controller-role request flag (when the I3C acts as controller) + + 17 + 1 + read-only + + + CRUPDF + Controller-role update flag (when the I3C acts as target) + + 18 + 1 + read-only + + + HJF + Hot-join flag (when the I3C acts as controller) + + 19 + 1 + read-only + + + WKPF + Wake-up/missed start flag (when the I3C acts as target) + + 21 + 1 + read-only + + + GETF + Get flag (when the I3C acts as target) + + 22 + 1 + read-only + + + STAF + Get status flag (when the I3C acts as target) + + 23 + 1 + read-only + + + DAUPDF + Dynamic address update flag (when the I3C acts as target) + + 24 + 1 + read-only + + + MWLUPDF + Maximum write length update flag (when the I3C acts as target) + + 25 + 1 + read-only + + + MRLUPDF + Maximum read length update flag (when the I3C acts as target) + + 26 + 1 + read-only + + + RSTF + Reset pattern flag (when the I3C acts as target) + + 27 + 1 + read-only + + + ASUPDF + Activity state update flag (when the I3C acts as target) + + 28 + 1 + read-only + + + INTUPDF + Interrupt/controller-role/hot-join update flag (when the I3C acts as target) + + 29 + 1 + read-only + + + DEFF + DEFTGTS flag (when the I3C acts as target) + + 30 + 1 + read-only + + + GRPF + Group addressing flag (when the I3C acts as target) + + 31 + 1 + read-only + + + + + I3C_IER + I3C_IER + I3C interrupt enable register + 0x054 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + CFNFIE + C-FIFO not full interrupt enable when the I3C acts as controller + 2 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SFNEIE + S-FIFO not empty interrupt enable when the I3C acts as controller + 3 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TXFNFIE + TX-FIFO not full interrupt enable (whatever the I3C acts as controller/target) + 4 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + RXFNEIE + RX-FIFO not empty interrupt enable (whatever the I3C acts as controller/target) + 5 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + FCIE + frame complete interrupt enable (whatever the I3C acts as controller/target) + 9 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + RXTGTENDIE + target-initiated read end interrupt enable (when the I3C acts as controller) + 10 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + ERRIE + error interrupt enable (whatever the I3C acts as controller/target) + 11 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + IBIIE + IBI request interrupt enable (when the I3C acts as controller) + 15 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + IBIENDIE + IBI end interrupt enable (when the I3C acts as target) + 16 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + CRIE + Controller-role request interrupt enable (when the I3C acts as controller) + 17 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + CRUPDIE + Controller-role update interrupt enable (when the I3C acts as target) + 18 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + HJIE + Hot-join interrupt enable (when the I3C acts as controller) + 19 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + WKPIE + Wake-up interrupt enable (when the I3C acts as target) + 21 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + GETIE + GETxxx CCC interrupt enable (except GETSTATUS of format 1) (when the I3C acts as target) + 22 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + STAIE + format 1 GETSTATUS CCC interrupt enable (when the I3C acts as target) + 23 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + DAUPDIE + ENTDAA/RSTDAA/SETNEWDA CCC interrupt enable (when the I3C acts as target) + 24 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + MWLUPDIE + SETMWL CCC interrupt enable (when the I3C acts as target) + 25 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + MRLUPDIE + SETMRL CCC interrupt enable (when the I3C acts as target) + 26 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + RSTIE + reset pattern interrupt enable (when the I3C acts as target) + 27 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + ASUPDIE + ENTASx CCC interrupt enable (when the I3C acts as target) + 28 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + INTUPDIE + ENEC/DISEC CCC interrupt enable (when the I3C acts as target) + 29 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + DEFIE + DEFTGTS CCC interrupt enable (when the I3C acts as target) + 30 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + GRPIE + DEFGRPA CCC interrupt enable (when the I3C acts as target) + 31 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + + + I3C_CEVR + I3C_CEVR + I3C clear event register + 0x058 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + CFCF + Clear frame complete flag (whatever the I3C acts as controller/target) + 9 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear FCF + 0x1 + + + + + CRXTGTENDF + Clear target-initiated read end flag (when the I3C acts as controller) + 10 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear RXTGTENDF + 0x1 + + + + + CERRF + Clear error flag (whatever the I3C acts as controller/target) + 11 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear ERRF + 0x1 + + + + + CIBIF + Clear IBI request flag (when the I3C acts as controller) + 15 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear IBIF + 0x1 + + + + + CIBIENDF + Clear IBI end flag (when the I3C acts as target) + 16 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear IBIENDF + 0x1 + + + + + CCRF + Clear controller-role request flag (when the I3C acts as controller) + 17 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear CRF + 0x1 + + + + + CCRUPDF + Clear controller-role update flag (when the I3C acts as target) + 18 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear CRUPDF + 0x1 + + + + + CHJF + Clear hot-join flag (when the I3C acts as controller) + 19 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear HJF + 0x1 + + + + + CWKPF + Clear wake-up flag (when the I3C acts as target) + 21 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear WKPF + 0x1 + + + + + CGETF + Clear GETxxx CCC flag (except GETSTATUS of format 1) (when the I3C acts as target) + 22 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear GETF + 0x1 + + + + + CSTAF + Clear format 1 GETSTATUS CCC flag (when the I3C acts as target) + 23 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear STAF + 0x1 + + + + + CDAUPDF + Clear ENTDAA/RSTDAA/SETNEWDA CCC flag (when the I3C acts as target) + 24 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear DAUPDF + 0x1 + + + + + CMWLUPDF + Clear SETMWL CCC flag (when the I3C acts as target) + 25 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear MWLUPDF + 0x1 + + + + + CMRLUPDF + Clear SETMRL CCC flag (when the I3C acts as target) + 26 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear MRLUPDF + 0x1 + + + + + CRSTF + Clear reset pattern flag (when the I3C acts as target) + 27 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear RSTF + 0x1 + + + + + CASUPDF + Clear ENTASx CCC flag (when the I3C acts as target) + 28 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear ASUPDF + 0x1 + + + + + CINTUPDF + Clear ENEC/DISEC CCC flag (when the I3C acts as target) + 29 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear CINTUPDF + 0x1 + + + + + CDEFF + Clear DEFTGTS CCC flag (when the I3C acts as target) + 30 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear DEFF + 0x1 + + + + + CGRPF + Clear DEFGRPA CCC flag (when the I3C acts as target) + 31 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear GRPF + 0x1 + + + + + + + I3C_DEVR0 + I3C_DEVR0 + I3C own device characteristics register + 0x060 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DAVAL + Dynamic address is valid (when the I3C acts as target) + + 0 + 1 + read-write + + + DA + 7-bit dynamic address + + 1 + 7 + read-write + + + IBIEN + IBI request enable (when the I3C acts as target) + + 16 + 1 + read-write + + + B_0x0 + IBI request disabled + 0x0 + + + B_0x1 + IBI request enabled + 0x1 + + + + + CREN + Controller-role request enable (when the I3C acts as target) + + 17 + 1 + read-write + + + B_0x0 + controller-role request disabled + 0x0 + + + B_0x1 + controller-role request enabled + 0x1 + + + + + HJEN + Hot-join request enable (when the I3C acts as target) + + 19 + 1 + read-write + + + B_0x0 + hot-join request disabled + 0x0 + + + B_0x1 + hot-join request enabled + 0x1 + + + + + AS + Activity state (when the I3C acts as target) + + 20 + 2 + read-only + + + B_0x0 + activity state 0 + 0x0 + + + B_0x1 + activity state 1 + 0x1 + + + B_0x2 + activity state 2 + 0x2 + + + B_0x3 + activity state 3 + 0x3 + + + + + RSTACT + Reset action/level on received reset pattern (when the I3C acts as target) + + 22 + 2 + read-only + + + B_0x0 + no reset action + 0x0 + + + B_0x1 + first level of reset: the application software must either: + 0x1 + + + B_0x2 + second level of reset: the application software must issue a warm reset, also known as a system reset. + 0x2 + + + B_0x3 + no reset action + 0x3 + + + + + RSTVAL + Reset action is valid (when the I3C acts as target) + + 24 + 1 + read-only + + + + + I3C_DEVR1 + I3C_DEVR1 + I3C device 1 characteristics register + 0x64 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DA + Assigned I3C dynamic address to target x (when the I3C acts as controller) + + 1 + 7 + read-write + + + IBIACK + IBI request acknowledge (when the I3C acts as controller) + + 16 + 1 + read-write + + + B_0x0 + an IBI request from target x must be NACK-ed + 0x0 + + + B_0x1 + an IBI request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed + 0x1 + + + + + CRACK + Controller-role request acknowledge (when the I3C acts as controller) + + 17 + 1 + read-write + + + B_0x0 + a controller-role request from target x must be NACK-ed + 0x0 + + + B_0x1 + a controller-role request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed + 0x1 + + + + + IBIDEN + IBI data enable (when the I3C acts as controller) + + 18 + 1 + read-write + + + B_0x0 + no data byte follows the acknowledged IBI from target x + 0x0 + + + B_0x1 + the mandatory data byte MDB[7:0] follows the acknowledged IBI from target x + 0x1 + + + + + SUSP + Suspend/stop I3C transfer on received IBI (when the I3C acts as controller) + + 19 + 1 + read-write + + + B_0x0 + C-FIFO and TX-FIFO are not flushed after an IBI request from target x is acknowledged and completed, and depending on the presence or absence of a next control word, a repeated start or a stop is emitted + 0x0 + + + B_0x1 + I3C transfer is stopped and both C-FIFO and TX-FIFO are flushed after receiving an IBI request from target x + 0x1 + + + + + DIS + DA[6:0] write disabled (when the I3C acts as controller) + + 31 + 1 + read-only + + + B_0x0 + write to DA[7:0] and to IBIDEN in the I3C_DEVRx register is allowed + 0x0 + + + B_0x1 + write to DA[7:0] and to IBIDEN is disabled/locked + 0x1 + + + + + + + I3C_DEVR2 + I3C_DEVR2 + I3C device 2 characteristics register + 0x68 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DA + Assigned I3C dynamic address to target x (when the I3C acts as controller) + + 1 + 7 + read-write + + + IBIACK + IBI request acknowledge (when the I3C acts as controller) + + 16 + 1 + read-write + + + B_0x0 + an IBI request from target x must be NACK-ed + 0x0 + + + B_0x1 + an IBI request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed + 0x1 + + + + + CRACK + Controller-role request acknowledge (when the I3C acts as controller) + + 17 + 1 + read-write + + + B_0x0 + a controller-role request from target x must be NACK-ed + 0x0 + + + B_0x1 + a controller-role request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed + 0x1 + + + + + IBIDEN + IBI data enable (when the I3C acts as controller) + + 18 + 1 + read-write + + + B_0x0 + no data byte follows the acknowledged IBI from target x + 0x0 + + + B_0x1 + the mandatory data byte MDB[7:0] follows the acknowledged IBI from target x + 0x1 + + + + + SUSP + Suspend/stop I3C transfer on received IBI (when the I3C acts as controller) + + 19 + 1 + read-write + + + B_0x0 + C-FIFO and TX-FIFO are not flushed after an IBI request from target x is acknowledged and completed, and depending on the presence or absence of a next control word, a repeated start or a stop is emitted + 0x0 + + + B_0x1 + I3C transfer is stopped and both C-FIFO and TX-FIFO are flushed after receiving an IBI request from target x + 0x1 + + + + + DIS + DA[6:0] write disabled (when the I3C acts as controller) + + 31 + 1 + read-only + + + B_0x0 + write to DA[7:0] and to IBIDEN in the I3C_DEVRx register is allowed + 0x0 + + + B_0x1 + write to DA[7:0] and to IBIDEN is disabled/locked + 0x1 + + + + + + + I3C_DEVR3 + I3C_DEVR3 + I3C device 3 characteristics register + 0x6C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DA + Assigned I3C dynamic address to target x (when the I3C acts as controller) + + 1 + 7 + read-write + + + IBIACK + IBI request acknowledge (when the I3C acts as controller) + + 16 + 1 + read-write + + + B_0x0 + an IBI request from target x must be NACK-ed + 0x0 + + + B_0x1 + an IBI request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed + 0x1 + + + + + CRACK + Controller-role request acknowledge (when the I3C acts as controller) + + 17 + 1 + read-write + + + B_0x0 + a controller-role request from target x must be NACK-ed + 0x0 + + + B_0x1 + a controller-role request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed + 0x1 + + + + + IBIDEN + IBI data enable (when the I3C acts as controller) + + 18 + 1 + read-write + + + B_0x0 + no data byte follows the acknowledged IBI from target x + 0x0 + + + B_0x1 + the mandatory data byte MDB[7:0] follows the acknowledged IBI from target x + 0x1 + + + + + SUSP + Suspend/stop I3C transfer on received IBI (when the I3C acts as controller) + + 19 + 1 + read-write + + + B_0x0 + C-FIFO and TX-FIFO are not flushed after an IBI request from target x is acknowledged and completed, and depending on the presence or absence of a next control word, a repeated start or a stop is emitted + 0x0 + + + B_0x1 + I3C transfer is stopped and both C-FIFO and TX-FIFO are flushed after receiving an IBI request from target x + 0x1 + + + + + DIS + DA[6:0] write disabled (when the I3C acts as controller) + + 31 + 1 + read-only + + + B_0x0 + write to DA[7:0] and to IBIDEN in the I3C_DEVRx register is allowed + 0x0 + + + B_0x1 + write to DA[7:0] and to IBIDEN is disabled/locked + 0x1 + + + + + + + I3C_DEVR4 + I3C_DEVR4 + I3C device 4 characteristics register + 0x70 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DA + Assigned I3C dynamic address to target x (when the I3C acts as controller) + + 1 + 7 + read-write + + + IBIACK + IBI request acknowledge (when the I3C acts as controller) + + 16 + 1 + read-write + + + B_0x0 + an IBI request from target x must be NACK-ed + 0x0 + + + B_0x1 + an IBI request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed + 0x1 + + + + + CRACK + Controller-role request acknowledge (when the I3C acts as controller) + + 17 + 1 + read-write + + + B_0x0 + a controller-role request from target x must be NACK-ed + 0x0 + + + B_0x1 + a controller-role request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed + 0x1 + + + + + IBIDEN + IBI data enable (when the I3C acts as controller) + + 18 + 1 + read-write + + + B_0x0 + no data byte follows the acknowledged IBI from target x + 0x0 + + + B_0x1 + the mandatory data byte MDB[7:0] follows the acknowledged IBI from target x + 0x1 + + + + + SUSP + Suspend/stop I3C transfer on received IBI (when the I3C acts as controller) + + 19 + 1 + read-write + + + B_0x0 + C-FIFO and TX-FIFO are not flushed after an IBI request from target x is acknowledged and completed, and depending on the presence or absence of a next control word, a repeated start or a stop is emitted + 0x0 + + + B_0x1 + I3C transfer is stopped and both C-FIFO and TX-FIFO are flushed after receiving an IBI request from target x + 0x1 + + + + + DIS + DA[6:0] write disabled (when the I3C acts as controller) + + 31 + 1 + read-only + + + B_0x0 + write to DA[7:0] and to IBIDEN in the I3C_DEVRx register is allowed + 0x0 + + + B_0x1 + write to DA[7:0] and to IBIDEN is disabled/locked + 0x1 + + + + + + + I3C_MAXRLR + I3C_MAXRLR + I3C maximum read length register + 0x090 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + MRL + Maximum data read length (when I3C acts as target) + + 0 + 16 + read-write + + + IBIP + IBI payload data maximum size, in bytes (when I3C acts as target) + + 16 + 3 + read-write + + + B_0x0 + null payload data size (only allowed when BCR2 = 0 in the I3C_BCR register) + 0x0 + + + B_0x1 + 1 byte (mandatory data byte MDB[7:0] + 0x1 + + + B_0x2 + 2 bytes (including first MDB[7:0]) + 0x2 + + + B_0x3 + 3 bytes (including first MDB[7:0]) + 0x3 + + + B_0x4 + 4 bytes (including first MDB[7:0]) + 0x4 + + + + + + + I3C_MAXWLR + I3C_MAXWLR + I3C maximum write length register + 0x094 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + MWL + Maximum data write length (when I3C acts as target) + + 0 + 16 + read-write + + + + + I3C_TIMINGR0 + I3C_TIMINGR0 + I3C timing register 0 + 0x0A0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SCLL_PP + SCL low duration in I3C push-pull phases, in number of kernel clocks cycles: + + 0 + 8 + read-write + + + SCLH_I3C + SCL high duration, used for I3C messages (both in push-pull and open-drain phases), in number of kernel clocks cycles: + + 8 + 8 + read-write + + + SCLL_OD + SCL low duration in open-drain phases, used for legacy Iless thansup>2less than/sup>C messages and for I3C open-drain phases (address phase following a start, ACK phase during controller-initiated messages, and T bit phase during direct/private/IBI payload), in number of kernel clocks cycles: + + 16 + 8 + read-write + + + SCLH_I2C + SCL high duration, used for legacy Iless thansup>2less than/sup>C messages, in number of kernel clocks cycles: + + 24 + 8 + read-write + + + + + I3C_TIMINGR1 + I3C_TIMINGR1 + I3C timing register 1 + 0x0A4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AVAL + Number of kernel clock cycles to set a time unit of 1 s, whatever I3C acts as controller or target. + 0 + 8 + read-write + + + ASNCR + Activity state of the new controller (when I3C acts as active controller) + + 8 + 2 + read-write + + + FREE + Number of kernel clocks cycles that is used to set some MIPI timings like bus free condition time (when the I3C acts as controller) + + 16 + 7 + read-write + + + SDA_HD + SDA hold time (when the I3C acts as controller), in number of kernel clocks cycles (refer to MIPI timing SDA hold time in push-pull tless thansub>HD_PPless than/sub>): + + 28 + 1 + read-write + + + + + I3C_TIMINGR2 + I3C_TIMINGR2 + I3C timing register 2 + 0x0A8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + STALLT + Controller clock stall enable on T-bit phase of data (and on the ACK/NACK phase of data byte of a legacy Iless thansup>2less than/sup>C read) + + 0 + 1 + read-write + + + B_0x0 + no stall + 0x0 + + + B_0x1 + stall enabled + 0x1 + + + + + STALLD + Controller clock stall enable on PAR phase of Data + + 1 + 1 + read-write + + + B_0x0 + no stall + 0x0 + + + B_0x1 + stall enabled + 0x1 + + + + + STALLC + Controller clock stall enable on PAR phase of CCC + + 2 + 1 + read-write + + + B_0x0 + no stall + 0x0 + + + B_0x1 + stall enabled + 0x1 + + + + + STALLA + Controller clock stall enable on ACK phase + + 3 + 1 + read-write + + + B_0x0 + no stall + 0x0 + + + B_0x1 + stall enabled + 0x1 + + + + + STALL + Controller clock stall time, in number of kernel clock cycles + + 8 + 8 + read-write + + + + + I3C_BCR + I3C_BCR + I3C bus characteristics register + 0x0C0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BCR0 + max data speed limitation + 0 + 1 + read-write + + + B_0x0 + no limitation + 0x0 + + + B_0x1 + limitation, as described by I3C_GETMXDSR. + 0x1 + + + + + BCR2 + in-band interrupt (IBI) payload + 2 + 1 + read-write + + + B_0x0 + no data byte follows the accepted IBI + 0x0 + + + B_0x1 + at least one mandatory data byte follows the accepted IBI (and at most 4 data bytes) + 0x1 + + + + + BCR6 + Controller capable + 6 + 1 + read-write + + + B_0x0 + I3C target (no controller capable) + 0x0 + + + B_0x1 + I3C controller capable + 0x1 + + + + + + + I3C_DCR + I3C_DCR + I3C device characteristics register + 0x0C4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DCR + device characteristics ID + + 0 + 8 + read-write + + + B_0x00 + generic device (for v1. + 0x00 + + + + + + + I3C_GETCAPR + I3C_GETCAPR + I3C get capability register + 0x0C8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CAPPEND + IBI MDB support for pending read notification + + 14 + 1 + read-write + + + B_0x0 + this I3C when acting as target sends an IBI request without a mandatory data byte value indicating a pending read notification + 0x0 + + + B_0x1 + this I3C when acting as target sends an IBI request with a mandatory data byte value (MDB[7:5] = 101), indicating a pending read notification + 0x1 + + + + + + + I3C_CRCAPR + I3C_CRCAPR + I3C controller-role capability register + 0x0CC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CAPDHOFF + delayed controller-role hand-off + + 3 + 1 + read-write + + + B_0x0 + this I3C does not needs additional time to process a controller-role hand-off + 0x0 + + + B_0x1 + this I3C needs additional time to process a controller-role hand-off + 0x1 + + + + + CAPGRP + group management support (when acting as controller) + + 9 + 1 + read-write + + + B_0x0 + this I3C does not support group address capabilities + 0x0 + + + B_0x1 + this I3C supports group address capabilities (when becoming controller) + 0x1 + + + + + + + I3C_GETMXDSR + I3C_GETMXDSR + I3C get max data speed register + 0x0D0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + HOFFAS + Controller hand-off activity state + + 0 + 2 + read-write + + + B_0x0 + activity state 0 is the initial activity state of this I3C before and when becoming controller + 0x0 + + + B_0x1 + activity state 1 is the initial activity state of this I3C when becoming controller + 0x1 + + + B_0x2 + activity state 2 is the initial activity state of this I3C when becoming controller + 0x2 + + + B_0x3 + activity state 3 is the initial activity state of this I3C when becoming controller + 0x3 + + + + + FMT + GETMXDS CCC format + + 8 + 2 + read-write + + + B_0x0 + format 1 (2 bytes with MaxWr with no defining byte, MaxRd) + 0x0 + + + B_0x1 + format 2: (5 bytes w. + 0x1 + + + B_0x2 + format 2 (5 bytes with MaxWr with no defining byte, MaxRd, and middle byte of MaxRdTurn) + 0x2 + + + B_0x3 + format 2 (5 bytes with MaxWr with no defining byte, MaxRd, MSB of MaxRdTurn) + 0x3 + + + + + RDTURN + programmed byte of the 3-byte MaxRdTurn (maximum read turnaround byte) + + 16 + 8 + read-write + + + TSCO + clock-to-data turnaround time (tless thansub>SCOless than/sub>) + + 24 + 1 + read-write + + + B_0x0 + tless thansub>SCOless than/sub> less than or equal to 12 ns + 0x0 + + + B_0x1 + tless thansub>SCOless than/sub> > 12 ns (refer to the datasheet for more details) + 0x1 + + + + + + + I3C_EPIDR + I3C_EPIDR + I3C extended provisioned ID register + 0xD4 + 0x20 + read-write + 0x02080000 + 0xFFFFFFFF + + + MIPIID + 4-bit MIPI Instance ID + + 12 + 4 + read-write + + + IDTSEL + provisioned ID type selector + + 16 + 1 + read-only + + + MIPIMID + 15-bit MIPI manufacturer ID + + 17 + 15 + read-only + + + + + + + I3C_S + 0X50005C00 + + + I3C2 + 0x44003000 + + I3C2_ERR + I3C2 error interrupt + 132 + + + I3C2_EV + I3C2 event interrupt + 131 + + + + I3C2_S + 0x54003000 + + + ICACHE + ICACHE register block + ICACHE + 0x40030400 + + 0x0 + 0x400 + registers + + + ICACHE + Instruction cache global interrupt + 104 + + + + ICACHE_CR + ICACHE_CR + ICACHE control register + 0x000 + 0x20 + read-write + 0x00000004 + 0xFFFFFFFF + + + EN + enable + 0 + 1 + read-write + + + B_0x0 + cache disabled + 0x0 + + + B_0x1 + cache enabled + 0x1 + + + + + CACHEINV + cache invalidation + + 1 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + invalidate entire cache (all cache lines valid bit = 0) + 0x1 + + + + + WAYSEL + cache associativity mode selection + + 2 + 1 + read-write + + + B_0x0 + direct mapped cache (1-way cache) + 0x0 + + + B_0x1 + n-way set associative cache (reset value) + 0x1 + + + + + HITMEN + hit monitor enable + 16 + 1 + read-write + + + B_0x0 + cache hit monitor switched off. + 0x0 + + + B_0x1 + cache hit monitor enabled + 0x1 + + + + + MISSMEN + miss monitor enable + 17 + 1 + read-write + + + B_0x0 + cache miss monitor switched off. + 0x0 + + + B_0x1 + cache miss monitor enabled + 0x1 + + + + + HITMRST + hit monitor reset + 18 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + reset cache hit monitor + 0x1 + + + + + MISSMRST + miss monitor reset + 19 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + reset cache miss monitor + 0x1 + + + + + + + ICACHE_SR + ICACHE_SR + ICACHE status register + 0x004 + 0x20 + read-only + 0x00000001 + 0xFFFFFFFF + + + BUSYF + busy flag + 0 + 1 + read-only + + + B_0x0 + cache not busy on a CACHEINV operation + 0x0 + + + B_0x1 + cache executing a full invalidate CACHEINV operation + 0x1 + + + + + BSYENDF + busy end flag + 1 + 1 + read-only + + + B_0x0 + cache busy + 0x0 + + + B_0x1 + full invalidate CACHEINV operation finished + 0x1 + + + + + ERRF + cache error flag + 2 + 1 + read-only + + + B_0x0 + no error + 0x0 + + + B_0x1 + an error occurred during the operation (cacheable write) + 0x1 + + + + + + + ICACHE_IER + ICACHE_IER + ICACHE interrupt enable register + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BSYENDIE + interrupt enable on busy end + + 1 + 1 + read-write + + + B_0x0 + interrupt disabled on busy end + 0x0 + + + B_0x1 + interrupt enabled on busy end + 0x1 + + + + + ERRIE + interrupt enable on cache error + + 2 + 1 + read-write + + + B_0x0 + interrupt disabled on error + 0x0 + + + B_0x1 + interrupt enabled on error + 0x1 + + + + + + + ICACHE_FCR + ICACHE_FCR + ICACHE flag clear register + 0x00C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + CBSYENDF + clear busy end flag + + 1 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clears BSYENDF flag in ICACHE_SR. + 0x1 + + + + + CERRF + clear cache error flag + + 2 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clears ERRF flag in ICACHE_SR + 0x1 + + + + + + + ICACHE_HMONR + ICACHE_HMONR + ICACHE hit monitor register + 0x010 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + HITMON + cache hit monitor counter + 0 + 32 + read-only + + + + + ICACHE_MMONR + ICACHE_MMONR + ICACHE miss monitor register + 0x014 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + MISSMON + cache miss monitor counter + 0 + 16 + read-only + + + + + ICACHE_CRR0 + ICACHE_CRR0 + ICACHE region 0 configuration register + 0x20 + 0x20 + read-write + 0x00000200 + 0xFFFFFFFF + + + BASEADDR + base address for region x + + 0 + 8 + read-write + + + RSIZE + size for region x + 9 + 3 + read-write + + + B_0x1 + 2 Mbytes + 0x1 + + + B_0x2 + 4 Mbytes + 0x2 + + + B_0x3 + 8 Mbytes + 0x3 + + + B_0x4 + 16 Mbytes + 0x4 + + + B_0x5 + 32 Mbytes + 0x5 + + + B_0x6 + 64 Mbytes + 0x6 + + + B_0x7 + 128 Mbytes + 0x7 + + + + + REN + enable for region x + 15 + 1 + read-write + + + B_0x0 + disabled + 0x0 + + + B_0x1 + enabled + 0x1 + + + + + REMAPADDR + remapped address for region x + + 16 + 11 + read-write + + + MSTSEL + AHB cache master selection for region x + 28 + 1 + read-write + + + B_0x0 + no action (master1 selected by default) + 0x0 + + + B_0x1 + master2 selected + 0x1 + + + + + HBURST + output burst type for region x + 31 + 1 + read-write + + + B_0x0 + WRAP + 0x0 + + + B_0x1 + INCR + 0x1 + + + + + + + ICACHE_CRR1 + ICACHE_CRR1 + ICACHE region 1 configuration register + 0x24 + 0x20 + read-write + 0x00000200 + 0xFFFFFFFF + + + BASEADDR + base address for region x + + 0 + 8 + read-write + + + RSIZE + size for region x + 9 + 3 + read-write + + + B_0x1 + 2 Mbytes + 0x1 + + + B_0x2 + 4 Mbytes + 0x2 + + + B_0x3 + 8 Mbytes + 0x3 + + + B_0x4 + 16 Mbytes + 0x4 + + + B_0x5 + 32 Mbytes + 0x5 + + + B_0x6 + 64 Mbytes + 0x6 + + + B_0x7 + 128 Mbytes + 0x7 + + + + + REN + enable for region x + 15 + 1 + read-write + + + B_0x0 + disabled + 0x0 + + + B_0x1 + enabled + 0x1 + + + + + REMAPADDR + remapped address for region x + + 16 + 11 + read-write + + + MSTSEL + AHB cache master selection for region x + 28 + 1 + read-write + + + B_0x0 + no action (master1 selected by default) + 0x0 + + + B_0x1 + master2 selected + 0x1 + + + + + HBURST + output burst type for region x + 31 + 1 + read-write + + + B_0x0 + WRAP + 0x0 + + + B_0x1 + INCR + 0x1 + + + + + + + ICACHE_CRR2 + ICACHE_CRR2 + ICACHE region 2 configuration register + 0x28 + 0x20 + read-write + 0x00000200 + 0xFFFFFFFF + + + BASEADDR + base address for region x + + 0 + 8 + read-write + + + RSIZE + size for region x + 9 + 3 + read-write + + + B_0x1 + 2 Mbytes + 0x1 + + + B_0x2 + 4 Mbytes + 0x2 + + + B_0x3 + 8 Mbytes + 0x3 + + + B_0x4 + 16 Mbytes + 0x4 + + + B_0x5 + 32 Mbytes + 0x5 + + + B_0x6 + 64 Mbytes + 0x6 + + + B_0x7 + 128 Mbytes + 0x7 + + + + + REN + enable for region x + 15 + 1 + read-write + + + B_0x0 + disabled + 0x0 + + + B_0x1 + enabled + 0x1 + + + + + REMAPADDR + remapped address for region x + + 16 + 11 + read-write + + + MSTSEL + AHB cache master selection for region x + 28 + 1 + read-write + + + B_0x0 + no action (master1 selected by default) + 0x0 + + + B_0x1 + master2 selected + 0x1 + + + + + HBURST + output burst type for region x + 31 + 1 + read-write + + + B_0x0 + WRAP + 0x0 + + + B_0x1 + INCR + 0x1 + + + + + + + ICACHE_CRR3 + ICACHE_CRR3 + ICACHE region 3 configuration register + 0x2C + 0x20 + read-write + 0x00000200 + 0xFFFFFFFF + + + BASEADDR + base address for region x + + 0 + 8 + read-write + + + RSIZE + size for region x + 9 + 3 + read-write + + + B_0x1 + 2 Mbytes + 0x1 + + + B_0x2 + 4 Mbytes + 0x2 + + + B_0x3 + 8 Mbytes + 0x3 + + + B_0x4 + 16 Mbytes + 0x4 + + + B_0x5 + 32 Mbytes + 0x5 + + + B_0x6 + 64 Mbytes + 0x6 + + + B_0x7 + 128 Mbytes + 0x7 + + + + + REN + enable for region x + 15 + 1 + read-write + + + B_0x0 + disabled + 0x0 + + + B_0x1 + enabled + 0x1 + + + + + REMAPADDR + remapped address for region x + + 16 + 11 + read-write + + + MSTSEL + AHB cache master selection for region x + 28 + 1 + read-write + + + B_0x0 + no action (master1 selected by default) + 0x0 + + + B_0x1 + master2 selected + 0x1 + + + + + HBURST + output burst type for region x + 31 + 1 + read-write + + + B_0x0 + WRAP + 0x0 + + + B_0x1 + INCR + 0x1 + + + + + + + + + ICACHE_S + 0X50030400 + + + IWDG + IWDG address block description + IWDG + 0x40003000 + + 0x0 + 0x18 + registers + + + IWDG + Independent watchdog interrupt + 35 + + + + IWDG_KR + IWDG_KR + IWDG key register + 0x00 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + KEY + Key value (write only, read 0x0000) + + 0 + 16 + write-only + + + + + IWDG_PR + IWDG_PR + IWDG prescaler register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PR + Prescaler divider + + 0 + 4 + read-write + + + B_0x0 + divider / 4 + 0x0 + + + B_0x1 + divider / 8 + 0x1 + + + B_0x2 + divider / 16 + 0x2 + + + B_0x3 + divider / 32 + 0x3 + + + B_0x4 + divider / 64 + 0x4 + + + B_0x5 + divider / 128 + 0x5 + + + B_0x6 + divider / 256 + 0x6 + + + B_0x7 + divider / 512 + 0x7 + + + + + + + IWDG_RLR + IWDG_RLR + IWDG reload register + 0x08 + 0x20 + read-write + 0x00000FFF + 0xFFFFFFFF + + + RL + Watchdog counter reload value + + 0 + 12 + read-write + + + + + IWDG_SR + IWDG_SR + IWDG status register + 0x0C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + PVU + Watchdog prescaler value update + + 0 + 1 + read-only + + + RVU + Watchdog counter reload value update + + 1 + 1 + read-only + + + WVU + Watchdog counter window value update + + 2 + 1 + read-only + + + EWU + Watchdog interrupt comparator value update + + 3 + 1 + read-only + + + ONF + Watchdog enable status bit + + 8 + 1 + read-only + + + B_0x0 + The IWDG is not activated + 0x0 + + + B_0x1 + The IWDG is activated and needs to be refreshed regularly by the application + 0x1 + + + + + EWIF + Watchdog early interrupt flag + + 14 + 1 + read-only + + + + + IWDG_WINR + IWDG_WINR + IWDG window register + 0x10 + 0x20 + read-write + 0x00000FFF + 0xFFFFFFFF + + + WIN + Watchdog counter window value + + 0 + 12 + read-write + + + + + IWDG_EWCR + IWDG_EWCR + IWDG early wake-up interrupt register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EWIT + Watchdog counter window value + + 0 + 12 + read-write + + + EWIC + Watchdog early interrupt acknowledge + + 14 + 1 + write-only + + + EWIE + Watchdog early interrupt enable + + 15 + 1 + read-write + + + B_0x0 + The early interrupt interface is disabled. + 0x0 + + + B_0x1 + The early interrupt interface is enabled. + 0x1 + + + + + + + + + IWDG_S + 0X50003000 + + + LPTIM1 + LPTIM1 address block description + LPTIM1 + 0x44004400 + + 0x0 + 0x38 + registers + + + LPTIM1 + LPTIM1 global interrupt OR LPTimer1 AIT through EXTI line + 64 + + + + LPTIM1_ISR + LPTIM1_ISR + LPTIM1 interrupt and status register [alternate] + 0x000 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + CC1IF + Compare 1 interrupt flag + + 0 + 1 + read-only + + + B_0x0 + No match + 0x0 + + + B_0x1 + The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR1 register's value + 0x1 + + + + + ARRM + Autoreload match + + 1 + 1 + read-only + + + EXTTRIG + External trigger edge event + + 2 + 1 + read-only + + + CMP1OK + Compare register 1 update OK + + 3 + 1 + read-only + + + ARROK + Autoreload register update OK + + 4 + 1 + read-only + + + UP + Counter direction change down to up + + 5 + 1 + read-only + + + DOWN + Counter direction change up to down + + 6 + 1 + read-only + + + UE + LPTIM update event occurred + + 7 + 1 + read-only + + + REPOK + Repetition register update OK + + 8 + 1 + read-only + + + CC2IF + Compare 2 interrupt flag + + 9 + 1 + read-only + + + B_0x0 + No match + 0x0 + + + B_0x1 + The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR2 register's value + 0x1 + + + + + CMP2OK + Compare register 2 update OK + + 19 + 1 + read-only + + + DIEROK + Interrupt enable register update OK + + 24 + 1 + read-only + + + + + LPTIM1_ISR_ALTERNATE1 + LPTIM1_ISR_ALTERNATE1 + LPTIM1 interrupt and status register + LPTIM1_ISR + 0x000 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + CC1IF + capture 1 interrupt flag + + 0 + 1 + read-only + + + B_0x0 + No input capture occurred + 0x0 + + + B_0x1 + The counter value has been captured in the LPTIM_CCR1 register. + 0x1 + + + + + ARRM + Autoreload match + + 1 + 1 + read-only + + + EXTTRIG + External trigger edge event + + 2 + 1 + read-only + + + ARROK + Autoreload register update OK + + 4 + 1 + read-only + + + UP + Counter direction change down to up + + 5 + 1 + read-only + + + DOWN + Counter direction change up to down + + 6 + 1 + read-only + + + UE + LPTIM update event occurred + + 7 + 1 + read-only + + + REPOK + Repetition register update OK + + 8 + 1 + read-only + + + CC2IF + Capture 2 interrupt flag + + 9 + 1 + read-only + + + B_0x0 + No input capture occurred + 0x0 + + + B_0x1 + The counter value has been captured in the LPTIM_CCR2 register. + 0x1 + + + + + CC1OF + Capture 1 over-capture flag + + 12 + 1 + read-only + + + B_0x0 + No over-capture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in LPTIM_CCR1 register while CC1IF flag was already set. + 0x1 + + + + + CC2OF + Capture 2 over-capture flag + + 13 + 1 + read-only + + + B_0x0 + No over-capture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in LPTIM_CCR2 register while CC2IF flag was already set. + 0x1 + + + + + DIEROK + Interrupt enable register update OK + + 24 + 1 + read-only + + + + + LPTIM1_ICR + LPTIM1_ICR + LPTIM1 interrupt clear register [alternate] + 0x004 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + CC1CF + Capture/compare 1 clear flag + + 0 + 1 + write-only + + + ARRMCF + Autoreload match clear flag + + 1 + 1 + write-only + + + EXTTRIGCF + External trigger valid edge clear flag + + 2 + 1 + write-only + + + CMP1OKCF + Compare register 1 update OK clear flag + + 3 + 1 + write-only + + + ARROKCF + Autoreload register update OK clear flag + + 4 + 1 + write-only + + + UPCF + Direction change to UP clear flag + + 5 + 1 + write-only + + + DOWNCF + Direction change to down clear flag + + 6 + 1 + write-only + + + UECF + Update event clear flag + + 7 + 1 + write-only + + + REPOKCF + Repetition register update OK clear flag + + 8 + 1 + write-only + + + CC2CF + Capture/compare 2 clear flag + + 9 + 1 + write-only + + + CMP2OKCF + Compare register 2 update OK clear flag + + 19 + 1 + write-only + + + DIEROKCF + Interrupt enable register update OK clear flag + + 24 + 1 + write-only + + + + + LPTIM1_ICR_ALTERNATE1 + LPTIM1_ICR_ALTERNATE1 + LPTIM1 interrupt clear register + LPTIM1_ICR + 0x004 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + CC1CF + Capture/compare 1 clear flag + + 0 + 1 + write-only + + + ARRMCF + Autoreload match clear flag + + 1 + 1 + write-only + + + EXTTRIGCF + External trigger valid edge clear flag + + 2 + 1 + write-only + + + ARROKCF + Autoreload register update OK clear flag + + 4 + 1 + write-only + + + UPCF + Direction change to UP clear flag + + 5 + 1 + write-only + + + DOWNCF + Direction change to down clear flag + + 6 + 1 + write-only + + + UECF + Update event clear flag + + 7 + 1 + write-only + + + REPOKCF + Repetition register update OK clear flag + + 8 + 1 + write-only + + + CC2CF + Capture/compare 2 clear flag + + 9 + 1 + write-only + + + CC1OCF + Capture/compare 1 over-capture clear flag + + 12 + 1 + write-only + + + CC2OCF + Capture/compare 2 over-capture clear flag + + 13 + 1 + write-only + + + DIEROKCF + Interrupt enable register update OK clear flag + + 24 + 1 + write-only + + + + + LPTIM1_DIER + LPTIM1_DIER + LPTIM1 interrupt enable register [alternate] + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1IE + Capture/compare 1 interrupt enable + 0 + 1 + read-write + + + B_0x0 + Capture/compare 1 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 1 interrupt enabled + 0x1 + + + + + ARRMIE + Autoreload match Interrupt Enable + 1 + 1 + read-write + + + B_0x0 + ARRM interrupt disabled + 0x0 + + + B_0x1 + ARRM interrupt enabled + 0x1 + + + + + EXTTRIGIE + External trigger valid edge Interrupt Enable + 2 + 1 + read-write + + + B_0x0 + EXTTRIG interrupt disabled + 0x0 + + + B_0x1 + EXTTRIG interrupt enabled + 0x1 + + + + + CMP1OKIE + Compare register 1 update OK interrupt enable + 3 + 1 + read-write + + + B_0x0 + CMPOK register 1 interrupt disabled + 0x0 + + + B_0x1 + CMPOK register 1 interrupt enabled + 0x1 + + + + + ARROKIE + Autoreload register update OK Interrupt Enable + 4 + 1 + read-write + + + B_0x0 + ARROK interrupt disabled + 0x0 + + + B_0x1 + ARROK interrupt enabled + 0x1 + + + + + UPIE + Direction change to UP Interrupt Enable + + 5 + 1 + read-write + + + B_0x0 + UP interrupt disabled + 0x0 + + + B_0x1 + UP interrupt enabled + 0x1 + + + + + DOWNIE + Direction change to down Interrupt Enable + + 6 + 1 + read-write + + + B_0x0 + DOWN interrupt disabled + 0x0 + + + B_0x1 + DOWN interrupt enabled + 0x1 + + + + + UEIE + Update event interrupt enable + 7 + 1 + read-write + + + B_0x0 + Update event interrupt disabled + 0x0 + + + B_0x1 + Update event interrupt enabled + 0x1 + + + + + REPOKIE + Repetition register update OK interrupt Enable + 8 + 1 + read-write + + + B_0x0 + Repetition register update OK interrupt disabled + 0x0 + + + B_0x1 + Repetition register update OK interrupt enabled + 0x1 + + + + + CC2IE + Capture/compare 2 interrupt enable + + 9 + 1 + read-write + + + B_0x0 + Capture/compare 2 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 2 interrupt enabled + 0x1 + + + + + CMP2OKIE + Compare register 2 update OK interrupt enable + + 19 + 1 + read-write + + + B_0x0 + CMPOK register 2 interrupt disabled + 0x0 + + + B_0x1 + CMPOK register 2 interrupt enabled + 0x1 + + + + + UEDE + Update event DMA request enable + + 23 + 1 + read-write + + + B_0x0 + UE DMA request disabled. + 0x0 + + + B_0x1 + UE DMA request enabled + 0x1 + + + + + + + LPTIM1_DIER_ALTERNATE1 + LPTIM1_DIER_ALTERNATE1 + LPTIM1 interrupt enable register + LPTIM1_DIER + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1IE + Capture/compare 1 interrupt enable + 0 + 1 + read-write + + + B_0x0 + Capture/compare 1 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 1 interrupt enabled + 0x1 + + + + + ARRMIE + Autoreload match Interrupt Enable + 1 + 1 + read-write + + + B_0x0 + ARRM interrupt disabled + 0x0 + + + B_0x1 + ARRM interrupt enabled + 0x1 + + + + + EXTTRIGIE + External trigger valid edge Interrupt Enable + 2 + 1 + read-write + + + B_0x0 + EXTTRIG interrupt disabled + 0x0 + + + B_0x1 + EXTTRIG interrupt enabled + 0x1 + + + + + ARROKIE + Autoreload register update OK Interrupt Enable + 4 + 1 + read-write + + + B_0x0 + ARROK interrupt disabled + 0x0 + + + B_0x1 + ARROK interrupt enabled + 0x1 + + + + + UPIE + Direction change to UP Interrupt Enable + + 5 + 1 + read-write + + + B_0x0 + UP interrupt disabled + 0x0 + + + B_0x1 + UP interrupt enabled + 0x1 + + + + + DOWNIE + Direction change to down Interrupt Enable + + 6 + 1 + read-write + + + B_0x0 + DOWN interrupt disabled + 0x0 + + + B_0x1 + DOWN interrupt enabled + 0x1 + + + + + UEIE + Update event interrupt enable + 7 + 1 + read-write + + + B_0x0 + Update event interrupt disabled + 0x0 + + + B_0x1 + Update event interrupt enabled + 0x1 + + + + + REPOKIE + Repetition register update OK interrupt Enable + 8 + 1 + read-write + + + B_0x0 + Repetition register update OK interrupt disabled + 0x0 + + + B_0x1 + Repetition register update OK interrupt enabled + 0x1 + + + + + CC2IE + Capture/compare 2 interrupt enable + + 9 + 1 + read-write + + + B_0x0 + Capture/compare 2 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 2 interrupt enabled + 0x1 + + + + + CC1OIE + Capture/compare 1 over-capture interrupt enable + + 12 + 1 + read-write + + + B_0x0 + CC1 over-capture interrupt disabled + 0x0 + + + B_0x1 + CC1 over-capture interrupt enabled + 0x1 + + + + + CC2OIE + Capture/compare 2 over-capture interrupt enable + + 13 + 1 + read-write + + + B_0x0 + CC2 over-capture interrupt disabled + 0x0 + + + B_0x1 + CC2 over-capture interrupt enabled + 0x1 + + + + + CC1DE + Capture/compare 1 DMA request enable + + 16 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled. + 0x0 + + + B_0x1 + CC1 DMA request enabled + 0x1 + + + + + UEDE + Update event DMA request enable + + 23 + 1 + read-write + + + B_0x0 + UE DMA request disabled. + 0x0 + + + B_0x1 + UE DMA request enabled + 0x1 + + + + + CC2DE + Capture/compare 2 DMA request enable + + 25 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled. + 0x0 + + + B_0x1 + CC2 DMA request enabled + 0x1 + + + + + + + LPTIM_CFGR + LPTIM_CFGR + LPTIM configuration register + 0x00C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CKSEL + Clock selector + + 0 + 1 + read-write + + + B_0x0 + LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators) + 0x0 + + + B_0x1 + LPTIM is clocked by an external clock source through the LPTIM external Input1 + 0x1 + + + + + CKPOL + Clock Polarity + + 1 + 2 + read-write + + + B_0x0 + the rising edge is the active edge used for counting. + 0x0 + + + B_0x1 + the falling edge is the active edge used for counting. + 0x1 + + + B_0x2 + both edges are active edges. + 0x2 + + + B_0x3 + not allowed + 0x3 + + + + + CKFLT + Configurable digital filter for external clock + + 3 + 2 + read-write + + + B_0x0 + any external clock signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + TRGFLT + Configurable digital filter for trigger + + 6 + 2 + read-write + + + B_0x0 + any trigger active level change is considered as a valid trigger + 0x0 + + + B_0x1 + trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger. + 0x1 + + + B_0x2 + trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger. + 0x2 + + + B_0x3 + trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger. + 0x3 + + + + + PRESC + Clock prescaler + + 9 + 3 + read-write + + + B_0x0 + /1 + 0x0 + + + B_0x1 + /2 + 0x1 + + + B_0x2 + /4 + 0x2 + + + B_0x3 + /8 + 0x3 + + + B_0x4 + /16 + 0x4 + + + B_0x5 + /32 + 0x5 + + + B_0x6 + /64 + 0x6 + + + B_0x7 + /128 + 0x7 + + + + + TRIGSEL + Trigger selector + + 13 + 3 + read-write + + + B_0x0 + lptim_ext_trig0 + 0x0 + + + B_0x1 + lptim_ext_trig1 + 0x1 + + + B_0x2 + lptim_ext_trig2 + 0x2 + + + B_0x3 + lptim_ext_trig3 + 0x3 + + + B_0x4 + lptim_ext_trig4 + 0x4 + + + B_0x5 + lptim_ext_trig5 + 0x5 + + + B_0x6 + lptim_ext_trig6 + 0x6 + + + B_0x7 + lptim_ext_trig7 + 0x7 + + + + + TRIGEN + Trigger enable and polarity + + 17 + 2 + read-write + + + B_0x0 + software trigger (counting start is initiated by software) + 0x0 + + + B_0x1 + rising edge is the active edge + 0x1 + + + B_0x2 + falling edge is the active edge + 0x2 + + + B_0x3 + both edges are active edges + 0x3 + + + + + TIMOUT + Timeout enable + + 19 + 1 + read-write + + + B_0x0 + A trigger event arriving when the timer is already started is ignored + 0x0 + + + B_0x1 + A trigger event arriving when the timer is already started resets and restarts the LPTIM counter and the repetition counter + 0x1 + + + + + WAVE + Waveform shape + + 20 + 1 + read-write + + + B_0x0 + Deactivate Set-once mode + 0x0 + + + B_0x1 + Activate the Set-once mode + 0x1 + + + + + WAVPOL + Waveform shape polarity + + 21 + 1 + read-write + + + B_0x0 + The LPTIM output reflects the compare results between LPTIM_CNT and LPTIM_CCRx registers + 0x0 + + + B_0x1 + The LPTIM output reflects the inverse of the compare results between LPTIM_CNT and LPTIM_CCRx registers + 0x1 + + + + + PRELOAD + Registers update mode + + 22 + 1 + read-write + + + B_0x0 + Registers are updated after each APB bus write access + 0x0 + + + B_0x1 + Registers are updated at the end of the current LPTIM period + 0x1 + + + + + COUNTMODE + counter mode enabled + + 23 + 1 + read-write + + + B_0x0 + the counter is incremented following each internal clock pulse + 0x0 + + + B_0x1 + the counter is incremented following each valid clock pulse on the LPTIM external Input1 + 0x1 + + + + + ENC + Encoder mode enable + + 24 + 1 + read-write + + + B_0x0 + Encoder mode disabled + 0x0 + + + B_0x1 + Encoder mode enabled + 0x1 + + + + + + + LPTIM_CR + LPTIM_CR + LPTIM control register + 0x010 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ENABLE + LPTIM enable + + 0 + 1 + read-write + + + B_0x0 + LPTIM is disabled. + 0x0 + + + B_0x1 + LPTIM is enabled + 0x1 + + + + + SNGSTRT + LPTIM start in Single mode + + 1 + 1 + read-write + + + CNTSTRT + Timer start in Continuous mode + + 2 + 1 + read-write + + + COUNTRST + Counter reset + + 3 + 1 + read-write + + + RSTARE + Reset after read enable + + 4 + 1 + read-write + + + + + LPTIM_CCR1 + LPTIM_CCR1 + LPTIM compare register 1 + 0x014 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR1 + Capture/compare 1 value + + 0 + 16 + read-write + + + + + LPTIM_ARR + LPTIM_ARR + LPTIM autoreload register + 0x018 + 0x20 + read-write + 0x00000001 + 0xFFFFFFFF + + + ARR + Auto reload value + + 0 + 16 + read-write + + + + + LPTIM_CNT + LPTIM_CNT + LPTIM counter register + 0x01C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + + 0 + 16 + read-only + + + + + LPTIM_CFGR2 + LPTIM_CFGR2 + LPTIM configuration register 2 + 0x024 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IN1SEL + LPTIM input 1 selection + + 0 + 2 + read-write + + + B_0x0 + lptim_in1_mux0 + 0x0 + + + B_0x1 + lptim_in1_mux1 + 0x1 + + + B_0x2 + lptim_in1_mux2 + 0x2 + + + B_0x3 + lptim_in1_mux3 + 0x3 + + + + + IN2SEL + LPTIM input 2 selection + + 4 + 2 + read-write + + + B_0x0 + lptim_in2_mux0 + 0x0 + + + B_0x1 + lptim_in2_mux1 + 0x1 + + + B_0x2 + lptim_in2_mux2 + 0x2 + + + B_0x3 + lptim_in2_mux3 + 0x3 + + + + + IC1SEL + LPTIM input capture 1 selection + + 16 + 2 + read-write + + + B_0x0 + lptim_ic1_mux0 + 0x0 + + + B_0x1 + lptim_ic1_mux1 + 0x1 + + + B_0x2 + lptim_ic1_mux2 + 0x2 + + + B_0x3 + lptim_ic1_mux3 + 0x3 + + + + + IC2SEL + LPTIM input capture 2 selection + + 20 + 2 + read-write + + + B_0x0 + lptim_ic2_mux0 + 0x0 + + + B_0x1 + lptim_ic2_mux1 + 0x1 + + + B_0x2 + lptim_ic2_mux2 + 0x2 + + + B_0x3 + lptim_ic2_mux3 + 0x3 + + + + + + + LPTIM_RCR + LPTIM_RCR + LPTIM repetition register + 0x028 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + REP + Repetition register value + + 0 + 8 + read-write + + + + + LPTIM_CCMR1 + LPTIM_CCMR1 + LPTIM capture/compare mode register 1 + 0x02C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1SEL + Capture/compare 1 selection + + 0 + 1 + read-write + + + B_0x0 + CC1 channel is configured in output PWM mode + 0x0 + + + B_0x1 + CC1 channel is configured in input capture mode + 0x1 + + + + + CC1E + Capture/compare 1 output enable. + 1 + 1 + read-write + + + B_0x0_CC1_AS_OUTPUT + Off - OC1 is not active. + 0x0 + + + B_0x1_CC1_AS_OUTPUT + On - OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/compare 1 output polarity. + 2 + 2 + read-write + + + B_0x0_CC1_AS_OUTPUT + OC1 active high, the LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CCRx registers + 0x0 + + + B_0x1_CC1_AS_OUTPUT + OC1 active low, the LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CCRx registers + 0x1 + + + B_0x3_CC1_AS_INPUT + both edges, circuit is sensitive to both IC1 rising and falling edges. + 0x3 + + + + + IC1PSC + Input capture 1 prescaler + + 8 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter + + 12 + 2 + read-write + + + B_0x0 + any external input capture signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + CC2SEL + Capture/compare 2 selection + + 16 + 1 + read-write + + + B_0x0 + CC2 channel is configured in output PWM mode + 0x0 + + + B_0x1 + CC2 channel is configured in input capture mode + 0x1 + + + + + CC2E + Capture/compare 2 output enable. + 17 + 1 + read-write + + + B_0x0_CC2_AS_OUTPUT + Off - OC2 is not active. + 0x0 + + + B_0x1_CC2_AS_OUTPUT + On - OC2 signal is output on the corresponding output pin + 0x1 + + + + + CC2P + Capture/compare 2 output polarity. + 18 + 2 + read-write + + + B_0x0_CC2_AS_OUTPUT + OC2 active high + 0x0 + + + B_0x1_CC2_AS_OUTPUT + OC2 active low + 0x1 + + + B_0x3_CC2_AS_INPUT + both edges, circuit is sensitive to both IC2 rising and falling edges. + 0x3 + + + + + IC2PSC + Input capture 2 prescaler + + 24 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC2F + Input capture 2 filter + + 28 + 2 + read-write + + + B_0x0 + any external input capture signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + + + LPTIM_CCR2 + LPTIM_CCR2 + LPTIM compare register 2 + 0x034 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR2 + Capture/compare 2 value + + 0 + 16 + read-write + + + + + + + LPTIM1_S + 0x54004400 + + + LPTIM2 + LPTIM2 address block description + LPTIM2 + 0x40009400 + + 0x0 + 0x38 + registers + + + LPTIM2 + LPTIM2 global interrupt OR LPTimer2 AIT through EXTI line + 70 + + + + LPTIM2_ISR + LPTIM2_ISR + LPTIM2 interrupt and status register [alternate] + 0x000 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + CC1IF + Compare 1 interrupt flag + + 0 + 1 + read-only + + + B_0x0 + No match + 0x0 + + + B_0x1 + The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR1 register's value + 0x1 + + + + + ARRM + Autoreload match + + 1 + 1 + read-only + + + EXTTRIG + External trigger edge event + + 2 + 1 + read-only + + + CMP1OK + Compare register 1 update OK + + 3 + 1 + read-only + + + ARROK + Autoreload register update OK + + 4 + 1 + read-only + + + UP + Counter direction change down to up + + 5 + 1 + read-only + + + DOWN + Counter direction change up to down + + 6 + 1 + read-only + + + UE + LPTIM update event occurred + + 7 + 1 + read-only + + + REPOK + Repetition register update OK + + 8 + 1 + read-only + + + CC2IF + Compare 2 interrupt flag + + 9 + 1 + read-only + + + B_0x0 + No match + 0x0 + + + B_0x1 + The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR2 register's value + 0x1 + + + + + CMP2OK + Compare register 2 update OK + + 19 + 1 + read-only + + + DIEROK + Interrupt enable register update OK + + 24 + 1 + read-only + + + + + LPTIM2_ISR_ALTERNATE1 + LPTIM2_ISR_ALTERNATE1 + LPTIM2 interrupt and status register + LPTIM2_ISR + 0x000 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + CC1IF + capture 1 interrupt flag + + 0 + 1 + read-only + + + B_0x0 + No input capture occurred + 0x0 + + + B_0x1 + The counter value has been captured in the LPTIM_CCR1 register. + 0x1 + + + + + ARRM + Autoreload match + + 1 + 1 + read-only + + + EXTTRIG + External trigger edge event + + 2 + 1 + read-only + + + ARROK + Autoreload register update OK + + 4 + 1 + read-only + + + UP + Counter direction change down to up + + 5 + 1 + read-only + + + DOWN + Counter direction change up to down + + 6 + 1 + read-only + + + UE + LPTIM update event occurred + + 7 + 1 + read-only + + + REPOK + Repetition register update OK + + 8 + 1 + read-only + + + CC2IF + Capture 2 interrupt flag + + 9 + 1 + read-only + + + B_0x0 + No input capture occurred + 0x0 + + + B_0x1 + The counter value has been captured in the LPTIM_CCR2 register. + 0x1 + + + + + CC1OF + Capture 1 over-capture flag + + 12 + 1 + read-only + + + B_0x0 + No over-capture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in LPTIM_CCR1 register while CC1IF flag was already set. + 0x1 + + + + + CC2OF + Capture 2 over-capture flag + + 13 + 1 + read-only + + + B_0x0 + No over-capture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in LPTIM_CCR2 register while CC2IF flag was already set. + 0x1 + + + + + DIEROK + Interrupt enable register update OK + + 24 + 1 + read-only + + + + + LPTIM2_ICR + LPTIM2_ICR + LPTIM2 interrupt clear register [alternate] + 0x004 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + CC1CF + Capture/compare 1 clear flag + + 0 + 1 + write-only + + + ARRMCF + Autoreload match clear flag + + 1 + 1 + write-only + + + EXTTRIGCF + External trigger valid edge clear flag + + 2 + 1 + write-only + + + CMP1OKCF + Compare register 1 update OK clear flag + + 3 + 1 + write-only + + + ARROKCF + Autoreload register update OK clear flag + + 4 + 1 + write-only + + + UPCF + Direction change to UP clear flag + + 5 + 1 + write-only + + + DOWNCF + Direction change to down clear flag + + 6 + 1 + write-only + + + UECF + Update event clear flag + + 7 + 1 + write-only + + + REPOKCF + Repetition register update OK clear flag + + 8 + 1 + write-only + + + CC2CF + Capture/compare 2 clear flag + + 9 + 1 + write-only + + + CMP2OKCF + Compare register 2 update OK clear flag + + 19 + 1 + write-only + + + DIEROKCF + Interrupt enable register update OK clear flag + + 24 + 1 + write-only + + + + + LPTIM2_ICR_ALTERNATE1 + LPTIM2_ICR_ALTERNATE1 + LPTIM2 interrupt clear register + LPTIM2_ICR + 0x004 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + CC1CF + Capture/compare 1 clear flag + + 0 + 1 + write-only + + + ARRMCF + Autoreload match clear flag + + 1 + 1 + write-only + + + EXTTRIGCF + External trigger valid edge clear flag + + 2 + 1 + write-only + + + ARROKCF + Autoreload register update OK clear flag + + 4 + 1 + write-only + + + UPCF + Direction change to UP clear flag + + 5 + 1 + write-only + + + DOWNCF + Direction change to down clear flag + + 6 + 1 + write-only + + + UECF + Update event clear flag + + 7 + 1 + write-only + + + REPOKCF + Repetition register update OK clear flag + + 8 + 1 + write-only + + + CC2CF + Capture/compare 2 clear flag + + 9 + 1 + write-only + + + CC1OCF + Capture/compare 1 over-capture clear flag + + 12 + 1 + write-only + + + CC2OCF + Capture/compare 2 over-capture clear flag + + 13 + 1 + write-only + + + DIEROKCF + Interrupt enable register update OK clear flag + + 24 + 1 + write-only + + + + + LPTIM2_DIER + LPTIM2_DIER + LPTIM2 interrupt enable register [alternate] + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1IE + Capture/compare 1 interrupt enable + 0 + 1 + read-write + + + B_0x0 + Capture/compare 1 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 1 interrupt enabled + 0x1 + + + + + ARRMIE + Autoreload match Interrupt Enable + 1 + 1 + read-write + + + B_0x0 + ARRM interrupt disabled + 0x0 + + + B_0x1 + ARRM interrupt enabled + 0x1 + + + + + EXTTRIGIE + External trigger valid edge Interrupt Enable + 2 + 1 + read-write + + + B_0x0 + EXTTRIG interrupt disabled + 0x0 + + + B_0x1 + EXTTRIG interrupt enabled + 0x1 + + + + + CMP1OKIE + Compare register 1 update OK interrupt enable + 3 + 1 + read-write + + + B_0x0 + CMPOK register 1 interrupt disabled + 0x0 + + + B_0x1 + CMPOK register 1 interrupt enabled + 0x1 + + + + + ARROKIE + Autoreload register update OK Interrupt Enable + 4 + 1 + read-write + + + B_0x0 + ARROK interrupt disabled + 0x0 + + + B_0x1 + ARROK interrupt enabled + 0x1 + + + + + UPIE + Direction change to UP Interrupt Enable + + 5 + 1 + read-write + + + B_0x0 + UP interrupt disabled + 0x0 + + + B_0x1 + UP interrupt enabled + 0x1 + + + + + DOWNIE + Direction change to down Interrupt Enable + + 6 + 1 + read-write + + + B_0x0 + DOWN interrupt disabled + 0x0 + + + B_0x1 + DOWN interrupt enabled + 0x1 + + + + + UEIE + Update event interrupt enable + 7 + 1 + read-write + + + B_0x0 + Update event interrupt disabled + 0x0 + + + B_0x1 + Update event interrupt enabled + 0x1 + + + + + REPOKIE + Repetition register update OK interrupt Enable + 8 + 1 + read-write + + + B_0x0 + Repetition register update OK interrupt disabled + 0x0 + + + B_0x1 + Repetition register update OK interrupt enabled + 0x1 + + + + + CC2IE + Capture/compare 2 interrupt enable + + 9 + 1 + read-write + + + B_0x0 + Capture/compare 2 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 2 interrupt enabled + 0x1 + + + + + CMP2OKIE + Compare register 2 update OK interrupt enable + + 19 + 1 + read-write + + + B_0x0 + CMPOK register 2 interrupt disabled + 0x0 + + + B_0x1 + CMPOK register 2 interrupt enabled + 0x1 + + + + + UEDE + Update event DMA request enable + + 23 + 1 + read-write + + + B_0x0 + UE DMA request disabled. + 0x0 + + + B_0x1 + UE DMA request enabled + 0x1 + + + + + + + LPTIM2_DIER_ALTERNATE1 + LPTIM2_DIER_ALTERNATE1 + LPTIM2 interrupt enable register + LPTIM2_DIER + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1IE + Capture/compare 1 interrupt enable + 0 + 1 + read-write + + + B_0x0 + Capture/compare 1 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 1 interrupt enabled + 0x1 + + + + + ARRMIE + Autoreload match Interrupt Enable + 1 + 1 + read-write + + + B_0x0 + ARRM interrupt disabled + 0x0 + + + B_0x1 + ARRM interrupt enabled + 0x1 + + + + + EXTTRIGIE + External trigger valid edge Interrupt Enable + 2 + 1 + read-write + + + B_0x0 + EXTTRIG interrupt disabled + 0x0 + + + B_0x1 + EXTTRIG interrupt enabled + 0x1 + + + + + ARROKIE + Autoreload register update OK Interrupt Enable + 4 + 1 + read-write + + + B_0x0 + ARROK interrupt disabled + 0x0 + + + B_0x1 + ARROK interrupt enabled + 0x1 + + + + + UPIE + Direction change to UP Interrupt Enable + + 5 + 1 + read-write + + + B_0x0 + UP interrupt disabled + 0x0 + + + B_0x1 + UP interrupt enabled + 0x1 + + + + + DOWNIE + Direction change to down Interrupt Enable + + 6 + 1 + read-write + + + B_0x0 + DOWN interrupt disabled + 0x0 + + + B_0x1 + DOWN interrupt enabled + 0x1 + + + + + UEIE + Update event interrupt enable + 7 + 1 + read-write + + + B_0x0 + Update event interrupt disabled + 0x0 + + + B_0x1 + Update event interrupt enabled + 0x1 + + + + + REPOKIE + Repetition register update OK interrupt Enable + 8 + 1 + read-write + + + B_0x0 + Repetition register update OK interrupt disabled + 0x0 + + + B_0x1 + Repetition register update OK interrupt enabled + 0x1 + + + + + CC2IE + Capture/compare 2 interrupt enable + + 9 + 1 + read-write + + + B_0x0 + Capture/compare 2 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 2 interrupt enabled + 0x1 + + + + + CC1OIE + Capture/compare 1 over-capture interrupt enable + + 12 + 1 + read-write + + + B_0x0 + CC1 over-capture interrupt disabled + 0x0 + + + B_0x1 + CC1 over-capture interrupt enabled + 0x1 + + + + + CC2OIE + Capture/compare 2 over-capture interrupt enable + + 13 + 1 + read-write + + + B_0x0 + CC2 over-capture interrupt disabled + 0x0 + + + B_0x1 + CC2 over-capture interrupt enabled + 0x1 + + + + + CC1DE + Capture/compare 1 DMA request enable + + 16 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled. + 0x0 + + + B_0x1 + CC1 DMA request enabled + 0x1 + + + + + UEDE + Update event DMA request enable + + 23 + 1 + read-write + + + B_0x0 + UE DMA request disabled. + 0x0 + + + B_0x1 + UE DMA request enabled + 0x1 + + + + + CC2DE + Capture/compare 2 DMA request enable + + 25 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled. + 0x0 + + + B_0x1 + CC2 DMA request enabled + 0x1 + + + + + + + LPTIM_CFGR + LPTIM_CFGR + LPTIM configuration register + 0x00C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CKSEL + Clock selector + + 0 + 1 + read-write + + + B_0x0 + LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators) + 0x0 + + + B_0x1 + LPTIM is clocked by an external clock source through the LPTIM external Input1 + 0x1 + + + + + CKPOL + Clock Polarity + + 1 + 2 + read-write + + + B_0x0 + the rising edge is the active edge used for counting. + 0x0 + + + B_0x1 + the falling edge is the active edge used for counting. + 0x1 + + + B_0x2 + both edges are active edges. + 0x2 + + + B_0x3 + not allowed + 0x3 + + + + + CKFLT + Configurable digital filter for external clock + + 3 + 2 + read-write + + + B_0x0 + any external clock signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + TRGFLT + Configurable digital filter for trigger + + 6 + 2 + read-write + + + B_0x0 + any trigger active level change is considered as a valid trigger + 0x0 + + + B_0x1 + trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger. + 0x1 + + + B_0x2 + trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger. + 0x2 + + + B_0x3 + trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger. + 0x3 + + + + + PRESC + Clock prescaler + + 9 + 3 + read-write + + + B_0x0 + /1 + 0x0 + + + B_0x1 + /2 + 0x1 + + + B_0x2 + /4 + 0x2 + + + B_0x3 + /8 + 0x3 + + + B_0x4 + /16 + 0x4 + + + B_0x5 + /32 + 0x5 + + + B_0x6 + /64 + 0x6 + + + B_0x7 + /128 + 0x7 + + + + + TRIGSEL + Trigger selector + + 13 + 3 + read-write + + + B_0x0 + lptim_ext_trig0 + 0x0 + + + B_0x1 + lptim_ext_trig1 + 0x1 + + + B_0x2 + lptim_ext_trig2 + 0x2 + + + B_0x3 + lptim_ext_trig3 + 0x3 + + + B_0x4 + lptim_ext_trig4 + 0x4 + + + B_0x5 + lptim_ext_trig5 + 0x5 + + + B_0x6 + lptim_ext_trig6 + 0x6 + + + B_0x7 + lptim_ext_trig7 + 0x7 + + + + + TRIGEN + Trigger enable and polarity + + 17 + 2 + read-write + + + B_0x0 + software trigger (counting start is initiated by software) + 0x0 + + + B_0x1 + rising edge is the active edge + 0x1 + + + B_0x2 + falling edge is the active edge + 0x2 + + + B_0x3 + both edges are active edges + 0x3 + + + + + TIMOUT + Timeout enable + + 19 + 1 + read-write + + + B_0x0 + A trigger event arriving when the timer is already started is ignored + 0x0 + + + B_0x1 + A trigger event arriving when the timer is already started resets and restarts the LPTIM counter and the repetition counter + 0x1 + + + + + WAVE + Waveform shape + + 20 + 1 + read-write + + + B_0x0 + Deactivate Set-once mode + 0x0 + + + B_0x1 + Activate the Set-once mode + 0x1 + + + + + WAVPOL + Waveform shape polarity + + 21 + 1 + read-write + + + B_0x0 + The LPTIM output reflects the compare results between LPTIM_CNT and LPTIM_CCRx registers + 0x0 + + + B_0x1 + The LPTIM output reflects the inverse of the compare results between LPTIM_CNT and LPTIM_CCRx registers + 0x1 + + + + + PRELOAD + Registers update mode + + 22 + 1 + read-write + + + B_0x0 + Registers are updated after each APB bus write access + 0x0 + + + B_0x1 + Registers are updated at the end of the current LPTIM period + 0x1 + + + + + COUNTMODE + counter mode enabled + + 23 + 1 + read-write + + + B_0x0 + the counter is incremented following each internal clock pulse + 0x0 + + + B_0x1 + the counter is incremented following each valid clock pulse on the LPTIM external Input1 + 0x1 + + + + + ENC + Encoder mode enable + + 24 + 1 + read-write + + + B_0x0 + Encoder mode disabled + 0x0 + + + B_0x1 + Encoder mode enabled + 0x1 + + + + + + + LPTIM_CR + LPTIM_CR + LPTIM control register + 0x010 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ENABLE + LPTIM enable + + 0 + 1 + read-write + + + B_0x0 + LPTIM is disabled. + 0x0 + + + B_0x1 + LPTIM is enabled + 0x1 + + + + + SNGSTRT + LPTIM start in Single mode + + 1 + 1 + read-write + + + CNTSTRT + Timer start in Continuous mode + + 2 + 1 + read-write + + + COUNTRST + Counter reset + + 3 + 1 + read-write + + + RSTARE + Reset after read enable + + 4 + 1 + read-write + + + + + LPTIM_CCR1 + LPTIM_CCR1 + LPTIM compare register 1 + 0x014 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR1 + Capture/compare 1 value + + 0 + 16 + read-write + + + + + LPTIM_ARR + LPTIM_ARR + LPTIM autoreload register + 0x018 + 0x20 + read-write + 0x00000001 + 0xFFFFFFFF + + + ARR + Auto reload value + + 0 + 16 + read-write + + + + + LPTIM_CNT + LPTIM_CNT + LPTIM counter register + 0x01C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + + 0 + 16 + read-only + + + + + LPTIM_CFGR2 + LPTIM_CFGR2 + LPTIM configuration register 2 + 0x024 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IN1SEL + LPTIM input 1 selection + + 0 + 2 + read-write + + + B_0x0 + lptim_in1_mux0 + 0x0 + + + B_0x1 + lptim_in1_mux1 + 0x1 + + + B_0x2 + lptim_in1_mux2 + 0x2 + + + B_0x3 + lptim_in1_mux3 + 0x3 + + + + + IN2SEL + LPTIM input 2 selection + + 4 + 2 + read-write + + + B_0x0 + lptim_in2_mux0 + 0x0 + + + B_0x1 + lptim_in2_mux1 + 0x1 + + + B_0x2 + lptim_in2_mux2 + 0x2 + + + B_0x3 + lptim_in2_mux3 + 0x3 + + + + + IC1SEL + LPTIM input capture 1 selection + + 16 + 2 + read-write + + + B_0x0 + lptim_ic1_mux0 + 0x0 + + + B_0x1 + lptim_ic1_mux1 + 0x1 + + + B_0x2 + lptim_ic1_mux2 + 0x2 + + + B_0x3 + lptim_ic1_mux3 + 0x3 + + + + + IC2SEL + LPTIM input capture 2 selection + + 20 + 2 + read-write + + + B_0x0 + lptim_ic2_mux0 + 0x0 + + + B_0x1 + lptim_ic2_mux1 + 0x1 + + + B_0x2 + lptim_ic2_mux2 + 0x2 + + + B_0x3 + lptim_ic2_mux3 + 0x3 + + + + + + + LPTIM_RCR + LPTIM_RCR + LPTIM repetition register + 0x028 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + REP + Repetition register value + + 0 + 8 + read-write + + + + + LPTIM_CCMR1 + LPTIM_CCMR1 + LPTIM capture/compare mode register 1 + 0x02C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1SEL + Capture/compare 1 selection + + 0 + 1 + read-write + + + B_0x0 + CC1 channel is configured in output PWM mode + 0x0 + + + B_0x1 + CC1 channel is configured in input capture mode + 0x1 + + + + + CC1E + Capture/compare 1 output enable. + 1 + 1 + read-write + + + B_0x0_CC1_AS_OUTPUT + Off - OC1 is not active. + 0x0 + + + B_0x1_CC1_AS_OUTPUT + On - OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/compare 1 output polarity. + 2 + 2 + read-write + + + B_0x0_CC1_AS_OUTPUT + OC1 active high, the LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CCRx registers + 0x0 + + + B_0x1_CC1_AS_OUTPUT + OC1 active low, the LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CCRx registers + 0x1 + + + B_0x3_CC1_AS_INPUT + both edges, circuit is sensitive to both IC1 rising and falling edges. + 0x3 + + + + + IC1PSC + Input capture 1 prescaler + + 8 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter + + 12 + 2 + read-write + + + B_0x0 + any external input capture signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + CC2SEL + Capture/compare 2 selection + + 16 + 1 + read-write + + + B_0x0 + CC2 channel is configured in output PWM mode + 0x0 + + + B_0x1 + CC2 channel is configured in input capture mode + 0x1 + + + + + CC2E + Capture/compare 2 output enable. + 17 + 1 + read-write + + + B_0x0_CC2_AS_OUTPUT + Off - OC2 is not active. + 0x0 + + + B_0x1_CC2_AS_OUTPUT + On - OC2 signal is output on the corresponding output pin + 0x1 + + + + + CC2P + Capture/compare 2 output polarity. + 18 + 2 + read-write + + + B_0x0_CC2_AS_OUTPUT + OC2 active high + 0x0 + + + B_0x1_CC2_AS_OUTPUT + OC2 active low + 0x1 + + + B_0x3_CC2_AS_INPUT + both edges, circuit is sensitive to both IC2 rising and falling edges. + 0x3 + + + + + IC2PSC + Input capture 2 prescaler + + 24 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC2F + Input capture 2 filter + + 28 + 2 + read-write + + + B_0x0 + any external input capture signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + + + LPTIM_CCR2 + LPTIM_CCR2 + LPTIM compare register 2 + 0x034 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR2 + Capture/compare 2 value + + 0 + 16 + read-write + + + + + + + LPTIM2_S + 0X50009400 + + + LPUART + LPUART address block description + LPUART + 0x44002400 + + 0x0 + 0x30 + registers + + + LPUART1 + LPUART1 global interrupt OR LPUART1 R Wakeup OR LPUART1 T Wakeup Char(10)through EXTI line + 63 + + + + LPUART_CR1 + LPUART_CR1 + LPUART control register 1 + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UE + LPUART enable + + 0 + 1 + read-write + + + B_0x0 + LPUART prescaler and outputs disabled, low-power mode + 0x0 + + + B_0x1 + LPUART enabled + 0x1 + + + + + UESM + LPUART enable in low-power mode + + 1 + 1 + read-write + + + B_0x0 + USART not able to wake up the MCU from low-power mode. + 0x0 + + + B_0x1 + USART able to wake up the MCU from low-power mode. + 0x1 + + + + + RE + Receiver enable + + 2 + 1 + read-write + + + B_0x0 + Receiver is disabled + 0x0 + + + B_0x1 + Receiver is enabled and begins searching for a start bit + 0x1 + + + + + TE + Transmitter enable + + 3 + 1 + read-write + + + B_0x0 + Transmitter is disabled + 0x0 + + + B_0x1 + Transmitter is enabled + 0x1 + + + + + IDLEIE + IDLE interrupt enable + + 4 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated whenever IDLE=1 in the LPUART_ISR register + 0x1 + + + + + RXFNEIE + RXFIFO not empty interrupt enable + + 5 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + A LPUART interrupt is generated whenever ORE=1 or RXFNE=1 in the LPUART_ISR register + 0x1 + + + + + TCIE + Transmission complete interrupt enable + + 6 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated whenever TC=1 in the LPUART_ISR register + 0x1 + + + + + TXFNFIE + TXFIFO not full interrupt enable + + 7 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + A LPUART interrupt is generated whenever TXFNF =1 in the LPUART_ISR register + 0x1 + + + + + PEIE + PE interrupt enable + + 8 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated whenever PE=1 in the LPUART_ISR register + 0x1 + + + + + PS + Parity selection + + 9 + 1 + read-write + + + B_0x0 + Even parity + 0x0 + + + B_0x1 + Odd parity + 0x1 + + + + + PCE + Parity control enable + + 10 + 1 + read-write + + + B_0x0 + Parity control disabled + 0x0 + + + B_0x1 + Parity control enabled + 0x1 + + + + + WAKE + Receiver wake-up method + + 11 + 1 + read-write + + + B_0x0 + Idle line + 0x0 + + + B_0x1 + Address mark + 0x1 + + + + + M0 + Word length + + 12 + 1 + read-write + + + MME + Mute mode enable + + 13 + 1 + read-write + + + B_0x0 + Receiver in active mode permanently + 0x0 + + + B_0x1 + Receiver can switch between mute mode and active mode. + 0x1 + + + + + CMIE + Character match interrupt enable + + 14 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + A LPUART interrupt is generated when the CMF bit is set in the LPUART_ISR register. + 0x1 + + + + + DEDT + Driver Enable deassertion time + + 16 + 5 + read-write + + + DEAT + Driver Enable assertion time + + 21 + 5 + read-write + + + M1 + Word length + + 28 + 1 + read-write + + + FIFOEN + FIFO mode enable + + 29 + 1 + read-write + + + B_0x0 + FIFO mode is disabled. + 0x0 + + + B_0x1 + FIFO mode is enabled. + 0x1 + + + + + TXFEIE + TXFIFO empty interrupt enable + + 30 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated when TXFE=1 in the LPUART_ISR register + 0x1 + + + + + RXFFIE + RXFIFO Full interrupt enable + + 31 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated when RXFF=1 in the LPUART_ISR register + 0x1 + + + + + + + LPUART_CR1_ALTERNATE1 + LPUART_CR1_ALTERNATE1 + LPUART control register 1 + LPUART_CR1 + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UE + LPUART enable + + 0 + 1 + read-write + + + B_0x0 + LPUART prescaler and outputs disabled, low-power mode + 0x0 + + + B_0x1 + LPUART enabled + 0x1 + + + + + UESM + LPUART enable in low-power mode + + 1 + 1 + read-write + + + B_0x0 + USART not able to wake up the MCU from low-power mode. + 0x0 + + + B_0x1 + USART able to wake up the MCU from low-power mode. + 0x1 + + + + + RE + Receiver enable + + 2 + 1 + read-write + + + B_0x0 + Receiver is disabled + 0x0 + + + B_0x1 + Receiver is enabled and begins searching for a start bit + 0x1 + + + + + TE + Transmitter enable + + 3 + 1 + read-write + + + B_0x0 + Transmitter is disabled + 0x0 + + + B_0x1 + Transmitter is enabled + 0x1 + + + + + IDLEIE + IDLE interrupt enable + + 4 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated whenever IDLE=1 in the LPUART_ISR register + 0x1 + + + + + RXNEIE + Receive data register not empty + + 5 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + A LPUART interrupt is generated whenever ORE=1 or RXNE=1 in the LPUART_ISR register + 0x1 + + + + + TCIE + Transmission complete interrupt enable + + 6 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated whenever TC=1 in the LPUART_ISR register + 0x1 + + + + + TXEIE + Transmit data register empty + + 7 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + A LPUART interrupt is generated whenever TXE =1 in the LPUART_ISR register + 0x1 + + + + + PEIE + PE interrupt enable + + 8 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated whenever PE=1 in the LPUART_ISR register + 0x1 + + + + + PS + Parity selection + + 9 + 1 + read-write + + + B_0x0 + Even parity + 0x0 + + + B_0x1 + Odd parity + 0x1 + + + + + PCE + Parity control enable + + 10 + 1 + read-write + + + B_0x0 + Parity control disabled + 0x0 + + + B_0x1 + Parity control enabled + 0x1 + + + + + WAKE + Receiver wake-up method + + 11 + 1 + read-write + + + B_0x0 + Idle line + 0x0 + + + B_0x1 + Address mark + 0x1 + + + + + M0 + Word length + + 12 + 1 + read-write + + + MME + Mute mode enable + + 13 + 1 + read-write + + + B_0x0 + Receiver in active mode permanently + 0x0 + + + B_0x1 + Receiver can switch between mute mode and active mode. + 0x1 + + + + + CMIE + Character match interrupt enable + + 14 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + A LPUART interrupt is generated when the CMF bit is set in the LPUART_ISR register. + 0x1 + + + + + DEDT + Driver Enable deassertion time + + 16 + 5 + read-write + + + DEAT + Driver Enable assertion time + + 21 + 5 + read-write + + + M1 + Word length + + 28 + 1 + read-write + + + FIFOEN + FIFO mode enable + + 29 + 1 + read-write + + + B_0x0 + FIFO mode is disabled. + 0x0 + + + B_0x1 + FIFO mode is enabled. + 0x1 + + + + + + + LPUART_CR2 + LPUART_CR2 + LPUART control register 2 + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ADDM7 + 7-bit Address Detection/4-bit Address Detection + + 4 + 1 + read-write + + + B_0x0 + 4-bit address detection + 0x0 + + + B_0x1 + 7-bit address detection (in 8-bit data mode) + 0x1 + + + + + STOP + STOP bits + + 12 + 2 + read-write + + + B_0x0 + 1 stop bit + 0x0 + + + B_0x2 + 2 stop bits + 0x2 + + + + + SWAP + Swap TX/RX pins + + 15 + 1 + read-write + + + B_0x0 + TX/RX pins are used as defined in standard pinout + 0x0 + + + B_0x1 + The TX and RX pins functions are swapped. + 0x1 + + + + + RXINV + RX pin active level inversion + + 16 + 1 + read-write + + + B_0x0 + RX pin signal works using the standard logic levels (Vless thansub>DDless than/sub> =1/idle, Gnd=0/mark) + 0x0 + + + B_0x1 + RX pin signal values are inverted. + 0x1 + + + + + TXINV + TX pin active level inversion + + 17 + 1 + read-write + + + B_0x0 + TX pin signal works using the standard logic levels (Vless thansub>DDless than/sub> =1/idle, Gnd=0/mark) + 0x0 + + + B_0x1 + TX pin signal values are inverted. + 0x1 + + + + + DATAINV + Binary data inversion + + 18 + 1 + read-write + + + B_0x0 + Logical data from the data register are send/received in positive/direct logic. + 0x0 + + + B_0x1 + Logical data from the data register are send/received in negative/inverse logic. + 0x1 + + + + + MSBFIRST + Most significant bit first + + 19 + 1 + read-write + + + B_0x0 + data is transmitted/received with data bit 0 first, following the start bit. + 0x0 + + + B_0x1 + data is transmitted/received with the MSB (bit 7/8) first, following the start bit. + 0x1 + + + + + ADD + Address of the LPUART node + + 24 + 8 + read-write + + + + + LPUART_CR3 + LPUART_CR3 + LPUART control register 3 + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EIE + Error interrupt enable + + 0 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An interrupt is generated when FE=1 or ORE=1 or NE=1 in the LPUART_ISR register. + 0x1 + + + + + HDSEL + Half-duplex selection + + 3 + 1 + read-write + + + B_0x0 + Half-duplex mode is not selected + 0x0 + + + B_0x1 + Half-duplex mode is selected + 0x1 + + + + + DMAR + DMA enable receiver + + 6 + 1 + read-write + + + B_0x1 + DMA mode is enabled for reception + 0x1 + + + B_0x0 + DMA mode is disabled for reception + 0x0 + + + + + DMAT + DMA enable transmitter + + 7 + 1 + read-write + + + B_0x1 + DMA mode is enabled for transmission + 0x1 + + + B_0x0 + DMA mode is disabled for transmission + 0x0 + + + + + RTSE + RTS enable + + 8 + 1 + read-write + + + B_0x0 + RTS hardware flow control disabled + 0x0 + + + B_0x1 + RTS output enabled, data is only requested when there is space in the receive buffer. + 0x1 + + + + + CTSE + CTS enable + + 9 + 1 + read-write + + + B_0x0 + CTS hardware flow control disabled + 0x0 + + + B_0x1 + CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). + 0x1 + + + + + CTSIE + CTS interrupt enable + 10 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An interrupt is generated whenever CTSIF=1 in the LPUART_ISR register + 0x1 + + + + + OVRDIS + Overrun Disable + + 12 + 1 + read-write + + + B_0x0 + Overrun Error Flag, ORE is set when received data is not read before receiving new data. + 0x0 + + + B_0x1 + Overrun functionality is disabled. + 0x1 + + + + + DDRE + DMA Disable on reception Error + + 13 + 1 + read-write + + + B_0x0 + DMA is not disabled in case of reception error. + 0x0 + + + B_0x1 + DMA is disabled following a reception error. + 0x1 + + + + + DEM + Driver enable mode + + 14 + 1 + read-write + + + B_0x0 + DE function is disabled. + 0x0 + + + B_0x1 + DE function is enabled. + 0x1 + + + + + DEP + Driver enable polarity selection + + 15 + 1 + read-write + + + B_0x0 + DE signal is active high. + 0x0 + + + B_0x1 + DE signal is active low. + 0x1 + + + + + WUS0 + Wake-up from low-power mode interrupt flag selection + + 20 + 1 + read-write + + + B_0x0 + WUF active on address match (as defined by ADD[7:0] and ADDM7) + 0x0 + + + + + WUS1 + Wake-up from low-power mode interrupt flag selection + + 21 + 1 + read-write + + + B_0x0 + WUF active on address match (as defined by ADD[7:0] and ADDM7) + 0x0 + + + + + WUFIE + Wake-up from low-power mode interrupt enable + + 22 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever WUF=1 in the LPUART_ISR register + 0x1 + + + + + TXFTIE + TXFIFO threshold interrupt enable + + 23 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + A LPUART interrupt is generated when TXFIFO reaches the threshold programmed in TXFTCFG. + 0x1 + + + + + RXFTCFG + Receive FIFO threshold configuration + + 25 + 3 + read-write + + + B_0x0 + Receive FIFO reaches 1/8 of its depth. + 0x0 + + + B_0x1 + Receive FIFO reaches 1/4 of its depth. + 0x1 + + + B_0x6 + Receive FIFO reaches 1/2 of its depth. + 0x6 + + + B_0x3 + Receive FIFO reaches 3/4 of its depth. + 0x3 + + + B_0x4 + Receive FIFO reaches 7/8 of its depth. + 0x4 + + + B_0x5 + Receive FIFO becomes full. + 0x5 + + + + + RXFTIE + RXFIFO threshold interrupt enable + + 28 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated when Receive FIFO reaches the threshold programmed in RXFTCFG. + 0x1 + + + + + TXFTCFG + TXFIFO threshold configuration + + 29 + 3 + read-write + + + B_0x0 + TXFIFO reaches 1/8 of its depth. + 0x0 + + + B_0x1 + TXFIFO reaches 1/4 of its depth. + 0x1 + + + B_0x6 + TXFIFO reaches 1/2 of its depth. + 0x6 + + + B_0x3 + TXFIFO reaches 3/4 of its depth. + 0x3 + + + B_0x4 + TXFIFO reaches 7/8 of its depth. + 0x4 + + + B_0x5 + TXFIFO becomes empty. + 0x5 + + + + + + + LPUART_CR3_ALTERNATE1 + LPUART_CR3_ALTERNATE1 + LPUART control register 3 + LPUART_CR3 + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EIE + Error interrupt enable + + 0 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An interrupt is generated when FE=1 or ORE=1 or NE=1 in the LPUART_ISR register. + 0x1 + + + + + HDSEL + Half-duplex selection + + 3 + 1 + read-write + + + B_0x0 + Half-duplex mode is not selected + 0x0 + + + B_0x1 + Half-duplex mode is selected + 0x1 + + + + + DMAR + DMA enable receiver + + 6 + 1 + read-write + + + B_0x1 + DMA mode is enabled for reception + 0x1 + + + B_0x0 + DMA mode is disabled for reception + 0x0 + + + + + DMAT + DMA enable transmitter + + 7 + 1 + read-write + + + B_0x1 + DMA mode is enabled for transmission + 0x1 + + + B_0x0 + DMA mode is disabled for transmission + 0x0 + + + + + RTSE + RTS enable + + 8 + 1 + read-write + + + B_0x0 + RTS hardware flow control disabled + 0x0 + + + B_0x1 + RTS output enabled, data is only requested when there is space in the receive buffer. + 0x1 + + + + + CTSE + CTS enable + + 9 + 1 + read-write + + + B_0x0 + CTS hardware flow control disabled + 0x0 + + + B_0x1 + CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). + 0x1 + + + + + CTSIE + CTS interrupt enable + 10 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An interrupt is generated whenever CTSIF=1 in the LPUART_ISR register + 0x1 + + + + + OVRDIS + Overrun Disable + + 12 + 1 + read-write + + + B_0x0 + Overrun Error Flag, ORE is set when received data is not read before receiving new data. + 0x0 + + + B_0x1 + Overrun functionality is disabled. + 0x1 + + + + + DDRE + DMA Disable on reception Error + + 13 + 1 + read-write + + + B_0x0 + DMA is not disabled in case of reception error. + 0x0 + + + B_0x1 + DMA is disabled following a reception error. + 0x1 + + + + + DEM + Driver enable mode + + 14 + 1 + read-write + + + B_0x0 + DE function is disabled. + 0x0 + + + B_0x1 + DE function is enabled. + 0x1 + + + + + DEP + Driver enable polarity selection + + 15 + 1 + read-write + + + B_0x0 + DE signal is active high. + 0x0 + + + B_0x1 + DE signal is active low. + 0x1 + + + + + WUS0 + Wake-up from low-power mode interrupt flag selection + + 20 + 1 + read-write + + + B_0x0 + WUF active on address match (as defined by ADD[7:0] and ADDM7) + 0x0 + + + + + WUS1 + Wake-up from low-power mode interrupt flag selection + + 21 + 1 + read-write + + + B_0x0 + WUF active on address match (as defined by ADD[7:0] and ADDM7) + 0x0 + + + + + WUFIE + Wake-up from low-power mode interrupt enable + + 22 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever WUF=1 in the LPUART_ISR register + 0x1 + + + + + + + LPUART_BRR + LPUART_BRR + LPUART baud rate register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BRR + LPUART baud rate division (LPUARTDIV) + 0 + 20 + read-write + + + + + LPUART_RQR + LPUART_RQR + LPUART request register + 0x18 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + SBKRQ + Send break request + + 1 + 1 + write-only + + + MMRQ + Mute mode request + + 2 + 1 + write-only + + + RXFRQ + Receive data flush request + + 3 + 1 + write-only + + + TXFRQ + Transmit data flush request + + 4 + 1 + write-only + + + + + LPUART_ISR + LPUART_ISR + LPUART interrupt and status register + 0x1C + 0x20 + read-only + 0x008000C0 + 0xFFFFFFFF + + + PE + Parity error + + 0 + 1 + read-only + + + B_0x0 + No parity error + 0x0 + + + B_0x1 + Parity error + 0x1 + + + + + FE + Framing error + + 1 + 1 + read-only + + + B_0x0 + No Framing error is detected + 0x0 + + + B_0x1 + Framing error or break character is detected + 0x1 + + + + + NE + Start bit noise detection flag + + 2 + 1 + read-only + + + B_0x0 + No noise is detected + 0x0 + + + B_0x1 + Noise is detected + 0x1 + + + + + ORE + Overrun error + + 3 + 1 + read-only + + + B_0x1 + Overrun error is detected + 0x1 + + + + + IDLE + Idle line detected + + 4 + 1 + read-only + + + B_0x0 + No Idle line is detected + 0x0 + + + B_0x1 + Idle line is detected + 0x1 + + + + + RXFNE + RXFIFO not empty + + 5 + 1 + read-only + + + B_0x0 + Data is not received + 0x0 + + + B_0x1 + Received data is ready to be read. + 0x1 + + + + + TC + Transmission complete + + 6 + 1 + read-only + + + TXFNF + TXFIFO not full + + 7 + 1 + read-only + + + B_0x0 + Data register is full/Transmit FIFO is full. + 0x0 + + + B_0x1 + Data register/Transmit FIFO is not full. + 0x1 + + + + + CTSIF + CTS interrupt flag + + 9 + 1 + read-only + + + B_0x0 + No change occurred on the CTS status line + 0x0 + + + B_0x1 + A change occurred on the CTS status line + 0x1 + + + + + CTS + CTS flag + + 10 + 1 + read-only + + + B_0x0 + CTS line set + 0x0 + + + B_0x1 + CTS line reset + 0x1 + + + + + BUSY + Busy flag + + 16 + 1 + read-only + + + B_0x0 + LPUART is idle (no reception) + 0x0 + + + B_0x1 + reception ongoing + 0x1 + + + + + CMF + Character match flag + + 17 + 1 + read-only + + + B_0x0 + No Character match detected + 0x0 + + + B_0x1 + Character match detected + 0x1 + + + + + SBKF + Send break flag + + 18 + 1 + read-only + + + B_0x0 + No break character transmitted + 0x0 + + + B_0x1 + Break character transmitted + 0x1 + + + + + RWU + Receiver wake-up from mute mode + + 19 + 1 + read-only + + + B_0x0 + Receiver in active mode + 0x0 + + + B_0x1 + Receiver in mute mode + 0x1 + + + + + WUF + Wake-up from low-power mode flag + + 20 + 1 + read-only + + + TEACK + Transmit enable acknowledge flag + + 21 + 1 + read-only + + + REACK + Receive enable acknowledge flag + + 22 + 1 + read-only + + + TXFE + TXFIFO Empty + + 23 + 1 + read-only + + + B_0x0 + TXFIFO is not empty. + 0x0 + + + B_0x1 + TXFIFO is empty. + 0x1 + + + + + RXFF + RXFIFO Full + + 24 + 1 + read-only + + + B_0x0 + RXFIFO is not Full. + 0x0 + + + B_0x1 + RXFIFO is Full. + 0x1 + + + + + RXFT + RXFIFO threshold flag + + 26 + 1 + read-only + + + B_0x0 + Receive FIFO does not reach the programmed threshold. + 0x0 + + + B_0x1 + Receive FIFO reached the programmed threshold. + 0x1 + + + + + TXFT + TXFIFO threshold flag + + 27 + 1 + read-only + + + B_0x0 + TXFIFO does not reach the programmed threshold. + 0x0 + + + B_0x1 + TXFIFO reached the programmed threshold. + 0x1 + + + + + + + LPUART_ISR_ALTERNATE1 + LPUART_ISR_ALTERNATE1 + LPUART interrupt and status register + LPUART_ISR + 0x1C + 0x20 + read-only + 0x000000C0 + 0xFFFFFFFF + + + PE + Parity error + + 0 + 1 + read-only + + + B_0x0 + No parity error + 0x0 + + + B_0x1 + Parity error + 0x1 + + + + + FE + Framing error + + 1 + 1 + read-only + + + B_0x0 + No Framing error is detected + 0x0 + + + B_0x1 + Framing error or break character is detected + 0x1 + + + + + NE + Start bit noise detection flag + + 2 + 1 + read-only + + + B_0x0 + No noise is detected + 0x0 + + + B_0x1 + Noise is detected + 0x1 + + + + + ORE + Overrun error + + 3 + 1 + read-only + + + B_0x1 + Overrun error is detected + 0x1 + + + + + IDLE + Idle line detected + + 4 + 1 + read-only + + + B_0x0 + No Idle line is detected + 0x0 + + + B_0x1 + Idle line is detected + 0x1 + + + + + RXNE + Read data register not empty + + 5 + 1 + read-only + + + B_0x0 + Data is not received + 0x0 + + + B_0x1 + Received data is ready to be read. + 0x1 + + + + + TC + Transmission complete + + 6 + 1 + read-only + + + TXE + Transmit data register empty + + 7 + 1 + read-only + + + B_0x0 + Data register full + 0x0 + + + B_0x1 + Data register empty + 0x1 + + + + + CTSIF + CTS interrupt flag + + 9 + 1 + read-only + + + B_0x0 + No change occurred on the CTS status line + 0x0 + + + B_0x1 + A change occurred on the CTS status line + 0x1 + + + + + CTS + CTS flag + + 10 + 1 + read-only + + + B_0x0 + CTS line set + 0x0 + + + B_0x1 + CTS line reset + 0x1 + + + + + BUSY + Busy flag + + 16 + 1 + read-only + + + B_0x0 + LPUART is idle (no reception) + 0x0 + + + B_0x1 + Reception ongoing + 0x1 + + + + + CMF + Character match flag + + 17 + 1 + read-only + + + B_0x0 + No Character match detected + 0x0 + + + B_0x1 + Character match detected + 0x1 + + + + + SBKF + Send break flag + + 18 + 1 + read-only + + + B_0x0 + No break character transmitted + 0x0 + + + B_0x1 + Break character transmitted + 0x1 + + + + + RWU + Receiver wake-up from mute mode + + 19 + 1 + read-only + + + B_0x0 + Receiver in active mode + 0x0 + + + B_0x1 + Receiver in mute mode + 0x1 + + + + + WUF + Wake-up from low-power mode flag + + 20 + 1 + read-only + + + TEACK + Transmit enable acknowledge flag + + 21 + 1 + read-only + + + REACK + Receive enable acknowledge flag + + 22 + 1 + read-only + + + + + LPUART_ICR + LPUART_ICR + LPUART interrupt flag clear register + 0x20 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + PECF + Parity error clear flag + + 0 + 1 + write-only + + + FECF + Framing error clear flag + + 1 + 1 + write-only + + + NECF + Noise detected clear flag + + 2 + 1 + write-only + + + ORECF + Overrun error clear flag + + 3 + 1 + write-only + + + IDLECF + Idle line detected clear flag + + 4 + 1 + write-only + + + TCCF + Transmission complete clear flag + + 6 + 1 + write-only + + + CTSCF + CTS clear flag + + 9 + 1 + write-only + + + CMCF + Character match clear flag + + 17 + 1 + write-only + + + WUCF + Wake-up from low-power mode clear flag + + 20 + 1 + write-only + + + + + LPUART_RDR + LPUART_RDR + LPUART receive data register + 0x24 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RDR + Receive data value + + 0 + 9 + read-only + + + + + LPUART_TDR + LPUART_TDR + LPUART transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TDR + Transmit data value + + 0 + 9 + read-write + + + + + LPUART_PRESC + LPUART_PRESC + LPUART prescaler register + 0x2C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRESCALER + Clock prescaler + + 0 + 4 + read-write + + + B_0x0 + input clock not divided + 0x0 + + + B_0x1 + input clock divided by 2 + 0x1 + + + B_0x2 + input clock divided by 4 + 0x2 + + + B_0x3 + input clock divided by 6 + 0x3 + + + B_0x4 + input clock divided by 8 + 0x4 + + + B_0x5 + input clock divided by 10 + 0x5 + + + B_0x6 + input clock divided by 12 + 0x6 + + + B_0x7 + input clock divided by 16 + 0x7 + + + B_0x8 + input clock divided by 32 + 0x8 + + + B_0x9 + input clock divided by 64 + 0x9 + + + B_0xA + input clock divided by 128 + 0xA + + + B_0xB + input clock divided by 256 + 0xB + + + + + + + + + LPUART_S + 0X54002400 + + + OCTOSPI + OCTOSPI register block + OCTOSPI + 0x47001400 + + 0x0 + 0x400 + registers + + + OCTOSPI1 + OCTOSPI1 global interrupt + 78 + + + + OCTOSPI_CR + OCTOSPI_CR + OCTOSPI control register + 0x0000 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EN + Enable + + 0 + 1 + read-write + + + B_0x0 + OCTOSPI disabled + 0x0 + + + B_0x1 + OCTOSPI enabled + 0x1 + + + + + ABORT + Abort request + + 1 + 1 + read-write + + + B_0x0 + No abort requested + 0x0 + + + B_0x1 + Abort requested + 0x1 + + + + + DMAEN + DMA enable + + 2 + 1 + read-write + + + B_0x0 + DMA disabled for indirect mode + 0x0 + + + B_0x1 + DMA enabled for indirect mode + 0x1 + + + + + TCEN + Timeout counter enable + + 3 + 1 + read-write + + + B_0x0 + The timeout counter is disabled, and thus the chip-select (NCS) remains active indefinitely after an access in memory-mapped mode. + 0x0 + + + B_0x1 + The timeout counter is enabled, and thus the chip-select is released in the memory-mapped mode after TIMEOUT[15:0] cycles of external device inactivity. + 0x1 + + + + + DMM + Dual-memory configuration + + 6 + 1 + read-write + + + B_0x0 + Dual-memory configuration disabled + 0x0 + + + B_0x1 + Dual-memory configuration enabled + 0x1 + + + + + MSEL + External memory select + + 7 + 1 + read-write + + + B_0x0 + External memory 1 selected (data exchanged over IO[3:0]) + 0x0 + + + B_0x1 + External memory 2 selected (data exchanged over IO[7:4]) + 0x1 + + + + + FTHRES + FIFO threshold level + + 8 + 5 + read-write + + + B_0x0 + FTF is set if there are one or more free bytes available to be written to in the FIFO in indirect-write mode, or if there are one or more valid bytes can be read from the FIFO in indirect-read mode. + 0x0 + + + B_0x1 + FTF is set if there are two or more free bytes available to be written to in the FIFO inindirect-write mode, or if there are two or more valid bytes can be read from the FIFO inindirect-read mode. + 0x1 + + + B_0x1F + FTF is set if there are 32 free bytes available to be written to in the FIFO in indirect-write mode, or if there are 32 valid bytes can be read from the FIFO in indirect-read mode. + 0x1F + + + + + TEIE + Transfer error interrupt enable + + 16 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + TCIE + Transfer complete interrupt enable + + 17 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + FTIE + FIFO threshold interrupt enable + + 18 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + SMIE + Status-match interrupt enable + + 19 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + TOIE + Timeout interrupt enable + + 20 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + APMS + Automatic status-polling mode stop + + 22 + 1 + read-write + + + B_0x0 + Automatic status-polling mode is stopped only by abort or by disabling the OCTOSPI. + 0x0 + + + B_0x1 + Automatic status-polling mode stops as soon as there is a match. + 0x1 + + + + + PMM + Polling match mode + + 23 + 1 + read-write + + + B_0x0 + AND-match mode, SMF is set if all the unmasked bits received from the device match the corresponding bits in the match register. + 0x0 + + + B_0x1 + OR-match mode, SMF is set if any of the unmasked bits received from the device matches its corresponding bit in the match register. + 0x1 + + + + + FMODE + Functional mode + + 28 + 2 + read-write + + + B_0x0 + Indirect-write mode + 0x0 + + + B_0x1 + Indirect-read mode + 0x1 + + + B_0x2 + Automatic status-polling mode (relevant in regular-command protocol only) + 0x2 + + + B_0x3 + Memory-mapped mode + 0x3 + + + + + + + OCTOSPI_DCR1 + OCTOSPI_DCR1 + OCTOSPI device configuration register 1 + 0x0008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CKMODE + Clock mode 0/mode 3 + + 0 + 1 + read-write + + + B_0x0 + CLK must stay low while NCS is high (chip-select released). + 0x0 + + + B_0x1 + CLK must stay high while NCS is high (chip-select released). + 0x1 + + + + + FRCK + Free running clock + + 1 + 1 + read-write + + + B_0x0 + CLK is not free running. + 0x0 + + + B_0x1 + CLK is free running (always provided). + 0x1 + + + + + DLYBYP + Delay block bypass + 3 + 1 + read-write + + + B_0x0 + The internal sampling clock (called feedback clock) or the DQS data strobe external signal is delayed by the delay block (for more details on this block, refer to the dedicated section of the reference manual as it is not part of the OCTOSPI peripheral). + 0x0 + + + B_0x1 + The delay block is bypassed, so the internal sampling clock or the DQS data strobe external signal is not affected by the delay block. + 0x1 + + + + + CSHT + Chip-select high time + + 8 + 6 + read-write + + + B_0x0 + NCS stays high for at least 1 cycle between external device commands. + 0x0 + + + B_0x1 + NCS stays high for at least 2 cycles between external device commands. + 0x1 + + + B_0x3F + NCS stays high for at least 64 cycles between external device commands. + 0x3F + + + + + DEVSIZE + Device size + + 16 + 5 + read-write + + + MTYP + Memory type + + 24 + 3 + read-write + + + B_0x0 + Micron mode, D0/D1 ordering in DTR 8-data-bit mode. + 0x0 + + + B_0x1 + Macronix mode, D1/D0 ordering in DTR 8-data-bit mode. + 0x1 + + + B_0x2 + Standard mode + 0x2 + + + B_0x3 + Macronix RAM mode, D1/D0 ordering in DTR 8-data-bit mode. + 0x3 + + + B_0x4 + HyperBus memory mode, the protocol follows the HyperBusless thansup> less than/sup>specification. + 0x4 + + + B_0x5 + HyperBus register mode, addressing register space. + 0x5 + + + + + + + OCTOSPI_DCR2 + OCTOSPI_DCR2 + OCTOSPI device configuration register 2 + 0x000C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRESCALER + Clock prescaler + + 0 + 8 + read-write + + + B_0x0 + Fless thansub>CLKless than/sub> = Fless thansub>KERNELless than/sub>, kernel clock used directly as OCTOSPI CLK (prescaler bypassed). + 0x0 + + + B_0x1 + Fless thansub>CLKless than/sub> = Fless thansub>KERNELless than/sub>/2 + 0x1 + + + + + WRAPSIZE + Wrap size + + 16 + 3 + read-write + + + B_0x0 + Wrapped reads are not supported by the memory. + 0x0 + + + B_0x2 + External memory supports wrap size of 16 bytes. + 0x2 + + + B_0x3 + External memory supports wrap size of 32 bytes. + 0x3 + + + B_0x4 + External memory supports wrap size of 64 bytes. + 0x4 + + + B_0x5 + External memory supports wrap size of 128 bytes. + 0x5 + + + + + + + OCTOSPI_DCR3 + OCTOSPI_DCR3 + OCTOSPI device configuration register 3 + 0x0010 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CSBOUND + NCS boundary + + 16 + 5 + read-write + + + B_0x0 + NCS boundary disabled + 0x0 + + + + + + + OCTOSPI_DCR4 + OCTOSPI_DCR4 + OCTOSPI device configuration register 4 + 0x0014 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + REFRESH + Refresh rate + + 0 + 32 + read-write + + + B_0x0 + Refresh disabled + 0x0 + + + + + + + OCTOSPI_SR + OCTOSPI_SR + OCTOSPI status register + 0x0020 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + TEF + Transfer error flag + + 0 + 1 + read-only + + + TCF + Transfer complete flag + + 1 + 1 + read-only + + + FTF + FIFO threshold flag + + 2 + 1 + read-only + + + SMF + Status match flag + + 3 + 1 + read-only + + + TOF + Timeout flag + + 4 + 1 + read-only + + + BUSY + Busy + + 5 + 1 + read-only + + + FLEVEL + FIFO level + + 8 + 6 + read-only + + + + + OCTOSPI_FCR + OCTOSPI_FCR + OCTOSPI flag clear register + 0x0024 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + CTEF + Clear transfer error flag + + 0 + 1 + write-only + + + CTCF + Clear transfer complete flag + + 1 + 1 + write-only + + + CSMF + Clear status match flag + + 3 + 1 + write-only + + + CTOF + Clear timeout flag + + 4 + 1 + write-only + + + + + OCTOSPI_DLR + OCTOSPI_DLR + OCTOSPI data length register + 0x0040 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DL + Data length + + 0 + 32 + read-write + + + + + OCTOSPI_AR + OCTOSPI_AR + OCTOSPI address register + 0x0048 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ADDRESS + Address + + 0 + 32 + read-write + + + + + OCTOSPI_DR + OCTOSPI_DR + OCTOSPI data register + 0x0050 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DATA + Data + + 0 + 32 + read-write + + + + + OCTOSPI_PSMKR + OCTOSPI_PSMKR + OCTOSPI polling status mask register + 0x0080 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + MASK + Status mask + + 0 + 32 + read-write + + + B_0x0 + Bit n of the data received in automatic status-polling mode is masked and its value is not considered in the matching logic. + 0x0 + + + B_0x1 + Bit n of the data received in automatic status-polling mode is unmasked and its value is considered in the matching logic. + 0x1 + + + + + + + OCTOSPI_PSMAR + OCTOSPI_PSMAR + OCTOSPI polling status match register + 0x0088 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + MATCH + Status match + + 0 + 32 + read-write + + + + + OCTOSPI_PIR + OCTOSPI_PIR + OCTOSPI polling interval register + 0x0090 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + INTERVAL + Polling interval + + 0 + 16 + read-write + + + + + OCTOSPI_CCR + OCTOSPI_CCR + OCTOSPI communication configuration register + 0x0100 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IMODE + Instruction mode + + 0 + 3 + read-write + + + B_0x0 + No instruction + 0x0 + + + B_0x1 + Instruction on a single line + 0x1 + + + B_0x2 + Instruction on two lines + 0x2 + + + B_0x3 + Instruction on four lines + 0x3 + + + B_0x4 + Instruction on eight lines + 0x4 + + + + + IDTR + Instruction double transfer rate + + 3 + 1 + read-write + + + B_0x0 + DTR mode disabled for the instruction phase + 0x0 + + + B_0x1 + DTR mode enabled for the instruction phase + 0x1 + + + + + ISIZE + Instruction size + + 4 + 2 + read-write + + + B_0x0 + 8-bit instruction + 0x0 + + + B_0x1 + 16-bit instruction + 0x1 + + + B_0x2 + 24-bit instruction + 0x2 + + + B_0x3 + 32-bit instruction + 0x3 + + + + + ADMODE + Address mode + + 8 + 3 + read-write + + + B_0x0 + No address + 0x0 + + + B_0x1 + Address on a single line + 0x1 + + + B_0x2 + Address on two lines + 0x2 + + + B_0x3 + Address on four lines + 0x3 + + + B_0x4 + Address on eight lines + 0x4 + + + + + ADDTR + Address double transfer rate + + 11 + 1 + read-write + + + B_0x0 + DTR mode disabled for the address phase + 0x0 + + + B_0x1 + DTR mode enabled for the address phase + 0x1 + + + + + ADSIZE + Address size + + 12 + 2 + read-write + + + B_0x0 + 8-bit address + 0x0 + + + B_0x1 + 16-bit address + 0x1 + + + B_0x2 + 24-bit address + 0x2 + + + B_0x3 + 32-bit address + 0x3 + + + + + ABMODE + Alternate-byte mode + + 16 + 3 + read-write + + + B_0x0 + No alternate bytes + 0x0 + + + B_0x1 + Alternate bytes on a single line + 0x1 + + + B_0x2 + Alternate bytes on two lines + 0x2 + + + B_0x3 + Alternate bytes on four lines + 0x3 + + + B_0x4 + Alternate bytes on eight lines + 0x4 + + + + + ABDTR + Alternate- byte double transfer rate + + 19 + 1 + read-write + + + B_0x0 + DTR mode disabled for the alternate-byte phase + 0x0 + + + B_0x1 + DTR mode enabled for the alternate-byte phase + 0x1 + + + + + ABSIZE + Alternate-byte size + + 20 + 2 + read-write + + + B_0x0 + 8-bit alternate bytes + 0x0 + + + B_0x1 + 16-bit alternate bytes + 0x1 + + + B_0x2 + 24-bit alternate bytes + 0x2 + + + B_0x3 + 32-bit alternate bytes + 0x3 + + + + + DMODE + Data mode + + 24 + 3 + read-write + + + B_0x0 + No data + 0x0 + + + B_0x1 + Data on a single line + 0x1 + + + B_0x2 + Data on two lines + 0x2 + + + B_0x3 + Data on four lines + 0x3 + + + B_0x4 + Data on eight lines + 0x4 + + + + + DDTR + Data double transfer rate + + 27 + 1 + read-write + + + B_0x0 + DTR mode disabled for data phase + 0x0 + + + B_0x1 + DTR mode enabled for data phase + 0x1 + + + + + DQSE + DQS enable + + 29 + 1 + read-write + + + B_0x0 + DQS disabled + 0x0 + + + B_0x1 + DQS enabled + 0x1 + + + + + + + OCTOSPI_TCR + OCTOSPI_TCR + OCTOSPI timing configuration register + 0x0108 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DCYC + Number of dummy cycles + + 0 + 5 + read-write + + + DHQC + Delay hold quarter cycle + 28 + 1 + read-write + + + B_0x0 + No delay hold + 0x0 + + + B_0x1 + 1/4 cycle hold + 0x1 + + + + + SSHIFT + Sample shift + + 30 + 1 + read-write + + + B_0x0 + No shift + 0x0 + + + B_0x1 + 1/2 cycle shift + 0x1 + + + + + + + OCTOSPI_IR + OCTOSPI_IR + OCTOSPI instruction register + 0x0110 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + INSTRUCTION + Instruction + + 0 + 32 + read-write + + + + + OCTOSPI_ABR + OCTOSPI_ABR + OCTOSPI alternate bytes register + 0x0120 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ALTERNATE + Alternate bytes + + 0 + 32 + read-write + + + + + OCTOSPI_LPTR + OCTOSPI_LPTR + OCTOSPI low-power timeout register + 0x00130 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TIMEOUT + Timeout period + + 0 + 16 + read-write + + + + + OCTOSPI_WPCCR + OCTOSPI_WPCCR + OCTOSPI wrap communication configuration register + 0x0140 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IMODE + Instruction mode + + 0 + 3 + read-write + + + B_0x0 + No instruction + 0x0 + + + B_0x1 + Instruction on a single line + 0x1 + + + B_0x2 + Instruction on two lines + 0x2 + + + B_0x3 + Instruction on four lines + 0x3 + + + B_0x4 + Instruction on eight lines + 0x4 + + + + + IDTR + Instruction double transfer rate + + 3 + 1 + read-write + + + B_0x0 + DTR mode disabled for the instruction phase + 0x0 + + + B_0x1 + DTR mode enabled for the instruction phase + 0x1 + + + + + ISIZE + Instruction size + + 4 + 2 + read-write + + + B_0x0 + 8-bit instruction + 0x0 + + + B_0x1 + 16-bit instruction + 0x1 + + + B_0x2 + 24-bit instruction + 0x2 + + + B_0x3 + 32-bit instruction + 0x3 + + + + + ADMODE + Address mode + + 8 + 3 + read-write + + + B_0x0 + No address + 0x0 + + + B_0x1 + Address on a single line + 0x1 + + + B_0x2 + Address on two lines + 0x2 + + + B_0x3 + Address on four lines + 0x3 + + + B_0x4 + Address on eight lines + 0x4 + + + + + ADDTR + Address double transfer rate + + 11 + 1 + read-write + + + B_0x0 + DTR mode disabled for address phase + 0x0 + + + B_0x1 + DTR mode enabled for address phase + 0x1 + + + + + ADSIZE + Address size + + 12 + 2 + read-write + + + B_0x0 + 8-bit address + 0x0 + + + B_0x1 + 16-bit address + 0x1 + + + B_0x2 + 24-bit address + 0x2 + + + B_0x3 + 32-bit address + 0x3 + + + + + ABMODE + Alternate-byte mode + + 16 + 3 + read-write + + + B_0x0 + no alternate bytes + 0x0 + + + B_0x1 + alternate bytes on a single line + 0x1 + + + B_0x2 + alternate bytes on two lines + 0x2 + + + B_0x3 + alternate bytes on four lines + 0x3 + + + B_0x4 + alternate bytes on eight lines + 0x4 + + + + + ABDTR + Alternate-byte double transfer rate + + 19 + 1 + read-write + + + B_0x0 + DTR mode disabled for the alternate-byte phase + 0x0 + + + B_0x1 + DTR mode enabled for the alternate-byte phase + 0x1 + + + + + ABSIZE + Alternate-byte size + + 20 + 2 + read-write + + + B_0x0 + 8-bit alternate bytes + 0x0 + + + B_0x1 + 16-bit alternate bytes + 0x1 + + + B_0x2 + 24-bit alternate bytes + 0x2 + + + B_0x3 + 32-bit alternate bytes + 0x3 + + + + + DMODE + Data mode + + 24 + 3 + read-write + + + B_0x0 + No data + 0x0 + + + B_0x1 + Data on a single line + 0x1 + + + B_0x2 + Data on two lines + 0x2 + + + B_0x3 + Data on four lines + 0x3 + + + B_0x4 + Data on eight lines + 0x4 + + + + + DDTR + Data double transfer rate + + 27 + 1 + read-write + + + B_0x0 + DTR mode disabled for the data phase + 0x0 + + + B_0x1 + DTR mode enabled for the data phase + 0x1 + + + + + DQSE + DQS enable + + 29 + 1 + read-write + + + B_0x0 + DQS disabled + 0x0 + + + B_0x1 + DQS enabled + 0x1 + + + + + + + OCTOSPI_WPTCR + OCTOSPI_WPTCR + OCTOSPI wrap timing configuration register + 0x0148 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DCYC + Number of dummy cycles + + 0 + 5 + read-write + + + DHQC + Delay hold quarter cycle + + 28 + 1 + read-write + + + B_0x0 + No quarter cycle delay + 0x0 + + + B_0x1 + 1/4 cycle delay inserted + 0x1 + + + + + SSHIFT + Sample shift + + 30 + 1 + read-write + + + B_0x0 + No shift + 0x0 + + + B_0x1 + 1/2 cycle shift + 0x1 + + + + + + + OCTOSPI_WPIR + OCTOSPI_WPIR + OCTOSPI wrap instruction register + 0x0150 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + INSTRUCTION + Instruction + + 0 + 32 + read-write + + + + + OCTOSPI_WPABR + OCTOSPI_WPABR + OCTOSPI wrap alternate bytes register + 0x0160 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ALTERNATE + Alternate bytes + + 0 + 32 + read-write + + + + + OCTOSPI_WCCR + OCTOSPI_WCCR + OCTOSPI write communication configuration register + 0x0180 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IMODE + Instruction mode + + 0 + 3 + read-write + + + B_0x0 + No instruction + 0x0 + + + B_0x1 + Instruction on a single line + 0x1 + + + B_0x2 + Instruction on two lines + 0x2 + + + B_0x3 + Instruction on four lines + 0x3 + + + B_0x4 + Instruction on eight lines + 0x4 + + + + + IDTR + Instruction double transfer rate + + 3 + 1 + read-write + + + B_0x0 + DTR mode disabled for instruction phase + 0x0 + + + B_0x1 + DTR mode enabled for instruction phase + 0x1 + + + + + ISIZE + Instruction size + + 4 + 2 + read-write + + + B_0x0 + 8-bit instruction + 0x0 + + + B_0x1 + 16-bit instruction + 0x1 + + + B_0x2 + 24-bit instruction + 0x2 + + + B_0x3 + 32-bit instruction + 0x3 + + + + + ADMODE + Address mode + + 8 + 3 + read-write + + + B_0x0 + No address + 0x0 + + + B_0x1 + Address on a single line + 0x1 + + + B_0x2 + Address on two lines + 0x2 + + + B_0x3 + Address on four lines + 0x3 + + + B_0x4 + Address on eight lines + 0x4 + + + + + ADDTR + Address double transfer rate + + 11 + 1 + read-write + + + B_0x0 + DTR mode disabled for the address phase + 0x0 + + + B_0x1 + DTR mode enabled for the address phase + 0x1 + + + + + ADSIZE + Address size + + 12 + 2 + read-write + + + B_0x0 + 8-bit address + 0x0 + + + B_0x1 + 16-bit address + 0x1 + + + B_0x2 + 24-bit address + 0x2 + + + B_0x3 + 32-bit address + 0x3 + + + + + ABMODE + Alternate-byte mode + + 16 + 3 + read-write + + + B_0x0 + No alternate bytes + 0x0 + + + B_0x1 + Alternate bytes on a single line + 0x1 + + + B_0x2 + Alternate bytes on two lines + 0x2 + + + B_0x3 + Alternate bytes on four lines + 0x3 + + + B_0x4 + Alternate bytes on eight lines + 0x4 + + + + + ABDTR + Alternate bytes double transfer rate + + 19 + 1 + read-write + + + B_0x0 + DTR mode disabled for alternate-bytes phase + 0x0 + + + B_0x1 + DTR mode enabled for alternate-bytes phase + 0x1 + + + + + ABSIZE + Alternate-byte size + + 20 + 2 + read-write + + + B_0x0 + 8-bit alternate bytes + 0x0 + + + B_0x1 + 16-bit alternate bytes + 0x1 + + + B_0x2 + 24-bit alternate bytes + 0x2 + + + B_0x3 + 32-bit alternate bytes + 0x3 + + + + + DMODE + Data mode + + 24 + 3 + read-write + + + B_0x0 + No data + 0x0 + + + B_0x1 + Data on a single line + 0x1 + + + B_0x2 + Data on two lines + 0x2 + + + B_0x3 + Data on four lines + 0x3 + + + B_0x4 + Data on eight lines + 0x4 + + + + + DDTR + data double transfer rate + + 27 + 1 + read-write + + + B_0x0 + DTR mode disabled for the data phase + 0x0 + + + B_0x1 + DTR mode enabled for the data phase + 0x1 + + + + + DQSE + DQS enable + + 29 + 1 + read-write + + + B_0x0 + DQS disabled + 0x0 + + + B_0x1 + DQS enabled + 0x1 + + + + + + + OCTOSPI_WTCR + OCTOSPI_WTCR + OCTOSPI write timing configuration register + 0x0188 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DCYC + Number of dummy cycles + + 0 + 5 + read-write + + + + + OCTOSPI_WIR + OCTOSPI_WIR + OCTOSPI write instruction register + 0x0190 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + INSTRUCTION + Instruction + + 0 + 32 + read-write + + + + + OCTOSPI_WABR + OCTOSPI_WABR + OCTOSPI write alternate bytes register + 0x01A0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ALTERNATE + Alternate bytes + + 0 + 32 + read-write + + + + + OCTOSPI_HLCR + OCTOSPI_HLCR + OCTOSPI HyperBus latency configuration register + 0x0200 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LM + Latency mode + + 0 + 1 + read-write + + + B_0x0 + Variable initial latency + 0x0 + + + B_0x1 + Fixed latency + 0x1 + + + + + WZL + Write zero latency + + 1 + 1 + read-write + + + B_0x0 + Latency on write accesses + 0x0 + + + B_0x1 + No latency on write accesses + 0x1 + + + + + TACC + Access time + + 8 + 8 + read-write + + + TRWR + Read-write minimum recovery time + + 16 + 8 + read-write + + + + + + + OCTOSPI_S + 0X57001400 + + + PSSI + PSSI register block + PSSI + 0x4202c400 + + 0x0 + 0x400 + registers + + + + PSSI_CR + PSSI_CR + PSSI control register + 0x00 + 0x20 + read-write + 0x40000000 + 0xFFFFFFFF + + + CKPOL + Parallel data clock polarity + + 5 + 1 + read-write + + + B_0x0 + Falling edge active for inputs or rising edge active for outputs + 0x0 + + + B_0x1 + Rising edge active for inputs or falling edge active for outputs. + 0x1 + + + + + DEPOL + Data enable (PSSI_DE) polarity + + 6 + 1 + read-write + + + B_0x0 + PSSI_DE active low (0 indicates that data is valid) + 0x0 + + + B_0x1 + PSSI_DE active high (1 indicates that data is valid) + 0x1 + + + + + RDYPOL + Ready (PSSI_RDY) polarity + + 8 + 1 + read-write + + + B_0x0 + PSSI_RDY active low (0 indicates that the receiver is ready to receive) + 0x0 + + + B_0x1 + PSSI_RDY active high (1 indicates that the receiver is ready to receive) + 0x1 + + + + + EDM + Extended data mode + 10 + 2 + read-write + + + B_0x0 + Interface captures 8-bit data on every parallel data clock + 0x0 + + + B_0x3 + The interface captures 16-bit data on every parallel data clock + 0x3 + + + + + ENABLE + PSSI enable + + 14 + 1 + read-write + + + B_0x0 + PSSI disabled + 0x0 + + + B_0x1 + PSSI enabled + 0x1 + + + + + DERDYCFG + Data enable and ready configuration + + 18 + 3 + read-write + + + B_0x0 + PSSI_DE and PSSI_RDY both disabled + 0x0 + + + B_0x1 + Only PSSI_RDY enabled + 0x1 + + + B_0x2 + Only PSSI_DE enabled + 0x2 + + + B_0x3 + Both PSSI_RDY and PSSI_DE alternate functions enabled + 0x3 + + + B_0x4 + Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_RDY pin (see Bidirectional PSSI_DE/PSSI_RDY signal on page 1245) + 0x4 + + + B_0x5 + Only PSSI_RDY function enabled, but mapped to PSSI_DE pin + 0x5 + + + B_0x6 + Only PSSI_DE function enabled, but mapped to PSSI_RDY pin + 0x6 + + + B_0x7 + Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_DE pin (see Bidirectional PSSI_DE/PSSI_RDY signal on page 1245) + 0x7 + + + + + DMAEN + DMA enable bit + 30 + 1 + read-write + + + B_0x0 + DMA transfers are disabled. + 0x0 + + + B_0x1 + DMA transfers are enabled (default configuration). + 0x1 + + + + + OUTEN + Data direction selection bit + 31 + 1 + read-write + + + B_0x0 + Receive mode: data is input synchronously with PSSI_PDCK + 0x0 + + + B_0x1 + Transmit mode: data is output synchronously with PSSI_PDCK + 0x1 + + + + + + + PSSI_SR + PSSI_SR + PSSI status register + 0x04 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RTT4B + FIFO is ready to transfer four bytes + 2 + 1 + read-only + + + B_0x1 + FIFO is ready for a four-byte (32-bit) transfer. + 0x1 + + + B_0x0 + FIFO is not ready for a four-byte transfer + 0x0 + + + + + RTT1B + FIFO is ready to transfer one byte + 3 + 1 + read-only + + + B_0x1 + FIFO is ready for a one byte (32-bit) transfer. + 0x1 + + + B_0x0 + FIFO is not ready for a 1-byte transfer + 0x0 + + + + + + + PSSI_RIS + PSSI_RIS + PSSI raw interrupt status register + 0x08 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + OVR_RIS + Data buffer overrun/underrun raw interrupt status + + 1 + 1 + read-only + + + B_0x0 + No overrun/underrun occurred + 0x0 + + + B_0x1 + An overrun/underrun occurred: overrun in receive mode, underrun in transmit mode. + 0x1 + + + + + + + PSSI_IER + PSSI_IER + PSSI interrupt enable register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OVR_IE + Data buffer overrun/underrun interrupt enable + 1 + 1 + read-write + + + B_0x0 + No interrupt generation + 0x0 + + + B_0x1 + An interrupt is generated if either an overrun or an underrun error occurred. + 0x1 + + + + + + + PSSI_MIS + PSSI_MIS + PSSI masked interrupt status register + 0x10 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + OVR_MIS + Data buffer overrun/underrun masked interrupt status + + 1 + 1 + read-only + + + B_0x0 + No interrupt is generated when an overrun/underrun error occurs + 0x0 + + + B_0x1 + An interrupt is generated if there is either an overrun or an underrun error and the OVR_IE bit is set in PSSI_IER. + 0x1 + + + + + + + PSSI_ICR + PSSI_ICR + PSSI interrupt clear register + 0x14 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + OVR_ISC + Data buffer overrun/underrun interrupt status clear + + 1 + 1 + write-only + + + + + PSSI_DR + PSSI_DR + PSSI data register + 0x28 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BYTE0 + Data byte 0 + 0 + 8 + read-write + + + BYTE1 + Data byte 1 + 8 + 8 + read-write + + + BYTE2 + Data byte 2 + 16 + 8 + read-write + + + BYTE3 + Data byte 3 + 24 + 8 + read-write + + + + + + + PSSI_S + 0X5202C400 + + + PWR + PWR address block description + PWR + 0x44020800 + + 0x0 + 0x108 + registers + + + + PWR_PMCR + PWR_PMCR + PWR power mode control register + 0x000 + 0x20 + read-write + 0x0000000C + 0xFFFFFFFF + + + LPMS + low-power mode selection + + 0 + 1 + read-write + + + B_0x0 + keeps Stop mode when entering DeepSleep. + 0x0 + + + B_0x1 + allows Standby mode when entering DeepSleep. + 0x1 + + + + + SVOS + system Stop mode voltage scaling selection + + 2 + 2 + read-write + + + B_0x1 + SVOS5 scale 5 + 0x1 + + + B_0x2 + SVOS4 scale 4 + 0x2 + + + B_0x3 + SVOS3 scale 3 (default) + 0x3 + + + + + CSSF + clear Standby and Stop flags (always read as 0) + + 7 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + STOPF and SBF flags cleared + 0x1 + + + + + FLPS + flash memory low-power mode in Stop mode + + 9 + 1 + read-write + + + B_0x0 + flash memory remains in normal mode when the system enters Stop mode (quick restart time). + 0x0 + + + B_0x1 + flash memory enters low-power mode when the system enters Stop mode(low-power consumption). + 0x1 + + + + + BOOSTE + analog switch Vless thansub>BOOSTless than/sub> control + + 12 + 1 + read-write + + + B_0x0 + booster disabled (default) + 0x0 + + + B_0x1 + booster enabled if analog voltage ready (AVD_READY = 1) + 0x1 + + + + + AVD_READY + analog voltage ready + + 13 + 1 + read-write + + + B_0x0 + peripheral analog voltage Vless thansub>DDAless than/sub> not ready (default) + 0x0 + + + B_0x1 + peripheral analog voltage Vless thansub>DDAless than/sub> ready. + 0x1 + + + + + ETHERNETSO + ETHERNET RAM shut-off in Stop mode. + 16 + 1 + read-write + + + B_0x0 + ETHERNET RAM content is kept in Stop mode. + 0x0 + + + B_0x1 + ETHERNET RAM content is lost in Stop mode. + 0x1 + + + + + SRAM3SO + AHB SRAM3 shut-off in Stop mode. + 23 + 1 + read-write + + + B_0x0 + AHB RAM3 content is kept in Stop mode. + 0x0 + + + B_0x1 + AHB RAM3 content is lost in Stop mode. + 0x1 + + + + + SRAM2_16SO + AHB SRAM2 16-Kbyte shut-off in Stop mode. + 24 + 1 + read-write + + + B_0x0 + AHB RAM2 16-Kbyte content is kept in Stop mode. + 0x0 + + + B_0x1 + AHB RAM2 16-Kbyte content is lost in Stop mode. + 0x1 + + + + + SRAM2_48SO + AHB SRAM2 48-Kbyte shut-off in Stop mode. + 25 + 1 + read-write + + + B_0x0 + AHB RAM2 48-Kbyte content is kept in Stop mode. + 0x0 + + + B_0x1 + AHB RAM2 48-Kbyte content is lost in Stop mode. + 0x1 + + + + + SRAM1SO + AHB SRAM1 shut-off in Stop mode + 26 + 1 + read-write + + + B_0x0 + AHB RA. + 0x0 + + + B_0x1 + AHB RAM1 content is lost in Stop mode. + 0x1 + + + + + + + PWR_PMCR_ALTERNATE1 + PWR_PMCR_ALTERNATE1 + PWR power mode control register + PWR_PMCR + 0x000 + 0x20 + read-write + 0x0000000C + 0xFFFFFFFF + + + LPMS + low-power mode selection + + 0 + 1 + read-write + + + B_0x0 + keeps Stop mode when entering DeepSleep. + 0x0 + + + B_0x1 + allows Standby mode when entering DeepSleep. + 0x1 + + + + + SVOS + system Stop mode voltage scaling selection + + 2 + 2 + read-write + + + B_0x1 + SVOS5 scale 5 + 0x1 + + + B_0x2 + SVOS4 scale 4 + 0x2 + + + B_0x3 + SVOS3 scale 3 (default) + 0x3 + + + + + CSSF + clear Standby and Stop flags (always read as 0) + + 7 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + STOPF and SBF flags cleared + 0x1 + + + + + FLPS + flash memory low-power mode in Stop mode + + 9 + 1 + read-write + + + B_0x0 + flash memory remains in normal mode when the system enters Stop mode (quick restart time). + 0x0 + + + B_0x1 + flash memory enters low-power mode when the system enters Stop mode(low-power consumption). + 0x1 + + + + + BOOSTE + analog switch Vless thansub>BOOSTless than/sub> control + + 12 + 1 + read-write + + + B_0x0 + booster disabled (default) + 0x0 + + + B_0x1 + booster enabled if analog voltage ready (AVD_READY = 1) + 0x1 + + + + + AVD_READY + analog voltage ready + + 13 + 1 + read-write + + + B_0x0 + peripheral analog voltage Vless thansub>DDAless than/sub> not ready (default) + 0x0 + + + B_0x1 + peripheral analog voltage Vless thansub>DDAless than/sub> ready. + 0x1 + + + + + SRAM3SO + AHB SRAM3 shut-off in Stop mode. + 23 + 1 + read-write + + + B_0x0 + AHB RAM3 content is kept in Stop mode. + 0x0 + + + B_0x1 + AHB RAM3 content is lost in Stop mode. + 0x1 + + + + + SRAM2_16LSO + AHB SRAM2 low 16-Kbyte shut-off in Stop mode. + 24 + 1 + read-write + + + B_0x0 + AHB RAM2 low 16-Kbyte content is kept in Stop mode. + 0x0 + + + B_0x1 + AHB RAM2 low 16-Kbyte content is lost in Stop mode. + 0x1 + + + + + SRAM2_16HSO + AHB SRAM2 high 16-Kbyte shut-off in Stop mode. + 25 + 1 + read-write + + + B_0x0 + AHB RAM2 high 16-Kbyte content is kept in Stop mode. + 0x0 + + + B_0x1 + AHB RAM2 ]high16-Kbyte content is lost in Stop mode. + 0x1 + + + + + SRAM2_48SO + AHB SRAM2 48-Kbyte shut-off in Stop mode. + 26 + 1 + read-write + + + B_0x0 + AHB RAM2 48-Kbyte content is kept in Stop mode. + 0x0 + + + B_0x1 + AHB RAM2 48-Kbyte content is lost in Stop mode. + 0x1 + + + + + SRAM1SO + AHB SRAM1 shut-off in Stop mode + 27 + 1 + read-write + + + B_0x0 + AHB RA. + 0x0 + + + B_0x1 + AHB RAM1 content is lost in Stop mode. + 0x1 + + + + + + + PWR_PMSR + PWR_PMSR + PWR status register + 0x004 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + STOPF + Stop flag + + 5 + 1 + read-only + + + B_0x0 + system has not been in Stop mode. + 0x0 + + + B_0x1 + system has been in Stop mode. + 0x1 + + + + + SBF + System standby flag + + 6 + 1 + read-only + + + B_0x0 + system has not been in Standby mode. + 0x0 + + + B_0x1 + system has been in Standby mode. + 0x1 + + + + + + + PWR_VOSCR + PWR_VOSCR + PWR voltage scaling control register + 0x0010 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + VOS + voltage scaling selection according to performance + + 4 + 2 + read-write + + + B_0x0 + scale 3 (default) + 0x0 + + + B_0x1 + scale 2 + 0x1 + + + B_0x2 + scale 1 + 0x2 + + + B_0x3 + scale 0 + 0x3 + + + + + + + PWR_VOSSR + PWR_VOSSR + PWR voltage scaling status register + 0x0014 + 0x20 + read-only + 0x00002008 + 0xFFFFFFFF + + + VOSRDY + Ready bit for Vless thansub>COREless than/sub> voltage scaling output selection. + 3 + 1 + read-only + + + B_0x0 + Not ready, voltage level below VOS selected level + 0x0 + + + B_0x1 + Ready, voltage level at or above VOS selected level + 0x1 + + + + + ACTVOSRDY + Voltage level ready for currently used VOS + 13 + 1 + read-only + + + B_0x0 + Vless thansub>COREless than/sub> is above or below the current voltage scaling provided by ACTVOS[1:0] + 0x0 + + + B_0x1 + Vless thansub>COREless than/sub> is equal to the current voltage scaling provided by ACTVOS[1:0] + 0x1 + + + + + ACTVOS + voltage output scaling currently applied to Vless thansub>COREless than/sub> + + 14 + 2 + read-only + + + B_0x0 + VOS3 (lowest power) + 0x0 + + + B_0x1 + VOS2 + 0x1 + + + B_0x2 + VOS1 + 0x2 + + + B_0x3 + VOS0 (highest frequency) + 0x3 + + + + + + + PWR_BDCR + PWR_BDCR + PWR Backup domain control register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BREN + Backup RAM retention in Standby and Vless thansub>BATless than/sub> modes + + 0 + 1 + read-write + + + B_0x0 + Backup RAM content lost in Standby and Vless thansub>BATless than/sub> modes. + 0x0 + + + B_0x1 + Backup RAM content preserved in Standby and Vless thansub>BATless than/sub> modes + 0x1 + + + + + MONEN + Backup domain voltage and temperature monitoring enable + 1 + 1 + read-write + + + B_0x0 + Backup domain voltage and temperature monitoring disabled + 0x0 + + + B_0x1 + Backup domain voltage and temperature monitoring enabled + 0x1 + + + + + VBE + Vless thansub>BATless than/sub> charging enable + + 8 + 1 + read-write + + + B_0x0 + Vless thansub>BATless than/sub> battery charging disabled. + 0x0 + + + B_0x1 + Vless thansub>BATless than/sub> battery charging enabled. + 0x1 + + + + + VBRS + Vless thansub>BATless than/sub> charging resistor selection + 9 + 1 + read-write + + + B_0x0 + Charge Vless thansub>BATless than/sub> through a 5 kohm resistor. + 0x0 + + + B_0x1 + Charge Vless thansub>BATless than/sub> through a 1. + 0x1 + + + + + + + PWR_DBPCR + PWR_DBPCR + PWR Backup domain control register + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DBP + Disable Backup domain write protection + + 0 + 1 + read-write + + + B_0x0 + Write access to Backup domain disabled + 0x0 + + + B_0x1 + Write access to Backup domain enabled + 0x1 + + + + + + + PWR_BDSR + PWR_BDSR + PWR Backup domain status register + 0x028 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + BRRDY + backup regulator ready + + 16 + 1 + read-only + + + B_0x0 + backup regulator not ready + 0x0 + + + B_0x1 + backup regulator ready + 0x1 + + + + + VBATL + Vless thansub>BATless than/sub> level monitoring versus low threshold + 20 + 1 + read-only + + + B_0x0 + Vless thansub>BATless than/sub> level above low threshold level + 0x0 + + + B_0x1 + Vless thansub>BATless than/sub> level equal or below low threshold level + 0x1 + + + + + VBATH + Vless thansub>BATless than/sub> level monitoring versus high threshold + 21 + 1 + read-only + + + B_0x0 + Vless thansub>BATless than/sub> level below high threshold level + 0x0 + + + B_0x1 + Vless thansub>BATless than/sub> level equal or above high threshold level + 0x1 + + + + + TEMPL + temperature level monitoring versus low threshold + 22 + 1 + read-only + + + B_0x0 + temperature above low threshold level + 0x0 + + + B_0x1 + temperature equal or below low threshold level + 0x1 + + + + + TEMPH + temperature level monitoring versus high threshold + 23 + 1 + read-only + + + B_0x0 + temperature below high threshold level + 0x0 + + + B_0x1 + temperature equal or above high threshold level + 0x1 + + + + + + + PWR_UCPDR + PWR_UCPDR + PWR USB Type-C power delivery register + 0x02C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UCPD_DBDIS + USB Type-C and power delivery dead battery disable + + 0 + 1 + read-write + + + B_0x0 + Enable USB Type-C dead battery pull-down behavior on UCPDx_CC1 and UCPDx_CC2 pins. + 0x0 + + + B_0x1 + Disable USB Type-C dead battery pull-down behavior on UCPDx_CC1 and UCPDx_CC2 pins. + 0x1 + + + + + UCPD_STBY + USB Type-c and Power delivery Standby mode + + 1 + 1 + read-write + + + + + PWR_SCCR + PWR_SCCR + PWR supply configuration control register + 0x030 + 0x20 + read-writeOnce + 0x00000100 + 0xFFFFFFFF + + + BYPASS + power management unit bypass + 0 + 1 + read-writeOnce + + + B_0x0 + Power management unit normal operation. + 0x0 + + + B_0x1 + Power management unit bypassed. + 0x1 + + + + + LDOEN + LDO enable + + 8 + 1 + read-only + + + SMPSEN + SMPS enable + + 9 + 1 + read-only + + + + + PWR_VMCR + PWR_VMCR + PWR voltage monitor control register + 0x034 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PVDE + PVD enable + 0 + 1 + read-write + + + B_0x0 + PVD disabled + 0x0 + + + B_0x1 + PVD enabled + 0x1 + + + + + PLS + programmable voltage detector (PVD) level selection + + 1 + 3 + read-write + + + B_0x0 + PVD level0 (VPVD0 ~ 1. + 0x0 + + + B_0x1 + PVD level1 (VPVD1 ~ 2. + 0x1 + + + B_0x2 + PVD level2 (VPVD2 ~ 2. + 0x2 + + + B_0x3 + PVD level3 (VPVD3 ~ 2. + 0x3 + + + B_0x4 + PVD level4 (VPVD4 ~ 2. + 0x4 + + + B_0x5 + PVD level5 (VPVD5 ~ 2. + 0x5 + + + B_0x6 + PVD level6 (VPVD6 ~ 2. + 0x6 + + + B_0x7 + PVD_IN pin + 0x7 + + + + + AVDEN + peripheral voltage monitor on Vless thansub>DDAless than/sub> enable + 8 + 1 + read-write + + + B_0x0 + peripheral voltage monitor on Vless thansub>DDAless than/sub> disabled + 0x0 + + + B_0x1 + peripheral voltage monitor on Vless thansub>DDAless than/sub> enabled + 0x1 + + + + + ALS + analog voltage detector (AVD) level selection + + 9 + 2 + read-write + + + B_0x0 + AVD level0 (Vless thansub>AVD0less than/sub> ~ 1. + 0x0 + + + B_0x1 + AVD level1 (Vless thansub>AVD1less than/sub> ~ 2. + 0x1 + + + B_0x2 + AVD level2 (Vless thansub>AVD2less than/sub> ~ 2. + 0x2 + + + B_0x3 + AVD level3 (Vless thansub>AVD3less than/sub> ~ 2. + 0x3 + + + + + + + PWR_USBSCR + PWR_USBSCR + PWR USB supply control register + 0x038 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + USB33DEN + Vless thansub>DDUSBless than/sub> voltage level detector enable + 24 + 1 + read-write + + + B_0x0 + Vless thansub>DDUSBless than/sub> voltage level detector disabled + 0x0 + + + B_0x1 + Vless thansub>DDUSBless than/sub> voltage level detector enabled + 0x1 + + + + + USB33SV + independent USB supply valid + + 25 + 1 + read-write + + + B_0x0 + Vless thansub>DDUSBless than/sub> is not present. + 0x0 + + + B_0x1 + Vless thansub>DDUSBless than/sub> is valid. + 0x1 + + + + + + + PWR_VMSR + PWR_VMSR + PWR voltage monitor status register + 0x03C + 0x20 + read-only + 0x00000000 + 0xFF0FFFFF + + + AVDO + analog voltage detector output on Vless thansub>DDAless than/sub> + + 19 + 1 + read-only + + + B_0x0 + Vless thansub>DDAless than/sub> is equal or higher than the AVD threshold selected with the ALS[2:0] bits. + 0x0 + + + B_0x1 + Vless thansub>DDAless than/sub> is lower than the AVD threshold selected with the ALS[2:0] bits. + 0x1 + + + + + VDDIO2RDY + voltage detector output on Vless thansub>DDIO2less than/sub> + + 20 + 1 + read-only + + + B_0x0 + Vless thansub>DDIO2less than/sub> is below 1. + 0x0 + + + B_0x1 + Vless thansub>DDIO2less than/sub> is above or equal to 1. + 0x1 + + + + + PVDO + programmable voltage detect output + + 22 + 1 + read-only + + + B_0x0 + Vless thansub>DDless than/sub> is equal or higher than the PVD threshold selected through the PLS[2:0] bits. + 0x0 + + + B_0x1 + Vless thansub>DDless than/sub> is lower than the PVD threshold selected through the PLS[2:0] bits. + 0x1 + + + + + USB33RDY + Vless thansub>DDUSBless than/sub> ready + 24 + 1 + read-only + + + B_0x0 + Vless thansub>DDUSBless than/sub> is below the threshold of the Vless thansub>DDUSBless than/sub> voltage monitor. + 0x0 + + + B_0x1 + Vless thansub>DDUSBless than/sub> is equal or above the threshold of the Vless thansub>DDUSBless than/sub> voltage monitor. + 0x1 + + + + + + + PWR_WUSCR + PWR_WUSCR + PWR wake-up status clear register + 0x040 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + CWUF1 + clear wake-up pin flag for WUFx (x = 8 to 1) + + 0 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + writing 1 clears the WUFx wake-up pin flag (bit is cleared to 0 by hardware). + 0x1 + + + + + CWUF2 + clear wake-up pin flag for WUFx (x = 8 to 1) + + 1 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + writing 1 clears the WUFx wake-up pin flag (bit is cleared to 0 by hardware). + 0x1 + + + + + CWUF3 + clear wake-up pin flag for WUFx (x = 8 to 1) + + 2 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + writing 1 clears the WUFx wake-up pin flag (bit is cleared to 0 by hardware). + 0x1 + + + + + CWUF4 + clear wake-up pin flag for WUFx (x = 8 to 1) + + 3 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + writing 1 clears the WUFx wake-up pin flag (bit is cleared to 0 by hardware). + 0x1 + + + + + CWUF5 + clear wake-up pin flag for WUFx (x = 8 to 1) + + 4 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + writing 1 clears the WUFx wake-up pin flag (bit is cleared to 0 by hardware). + 0x1 + + + + + CWUF6 + clear wake-up pin flag for WUFx (x = 8 to 1) + + 5 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + writing 1 clears the WUFx wake-up pin flag (bit is cleared to 0 by hardware). + 0x1 + + + + + CWUF7 + clear wake-up pin flag for WUFx (x = 8 to 1) + + 6 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + writing 1 clears the WUFx wake-up pin flag (bit is cleared to 0 by hardware). + 0x1 + + + + + CWUF8 + clear wake-up pin flag for WUFx (x = 8 to 1) + + 7 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + writing 1 clears the WUFx wake-up pin flag (bit is cleared to 0 by hardware). + 0x1 + + + + + + + PWR_WUSR + PWR_WUSR + PWR wake-up status register + 0x044 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + WUF1 + wake-up pin WUFx flag + + 0 + 1 + read-only + + + B_0x0 + no wake-up event occurred. + 0x0 + + + B_0x1 + wake-up event received from WUFx pin. + 0x1 + + + + + WUF2 + wake-up pin WUFx flag + + 1 + 1 + read-only + + + B_0x0 + no wake-up event occurred. + 0x0 + + + B_0x1 + wake-up event received from WUFx pin. + 0x1 + + + + + WUF3 + wake-up pin WUFx flag + + 2 + 1 + read-only + + + B_0x0 + no wake-up event occurred. + 0x0 + + + B_0x1 + wake-up event received from WUFx pin. + 0x1 + + + + + WUF4 + wake-up pin WUFx flag + + 3 + 1 + read-only + + + B_0x0 + no wake-up event occurred. + 0x0 + + + B_0x1 + wake-up event received from WUFx pin. + 0x1 + + + + + WUF5 + wake-up pin WUFx flag + + 4 + 1 + read-only + + + B_0x0 + no wake-up event occurred. + 0x0 + + + B_0x1 + wake-up event received from WUFx pin. + 0x1 + + + + + WUF6 + wake-up pin WUFx flag + + 5 + 1 + read-only + + + B_0x0 + no wake-up event occurred. + 0x0 + + + B_0x1 + wake-up event received from WUFx pin. + 0x1 + + + + + WUF7 + wake-up pin WUFx flag + + 6 + 1 + read-only + + + B_0x0 + no wake-up event occurred. + 0x0 + + + B_0x1 + wake-up event received from WUFx pin. + 0x1 + + + + + WUF8 + wake-up pin WUFx flag + + 7 + 1 + read-only + + + B_0x0 + no wake-up event occurred. + 0x0 + + + B_0x1 + wake-up event received from WUFx pin. + 0x1 + + + + + + + PWR_WUCR + PWR_WUCR + PWR wake-up configuration register + 0x048 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + WUPEN1 + enable wake-up pin WUPx (x = 8 to 1) + + 0 + 1 + read-write + + + B_0x0 + an event on WUPx pin does not wake-up the system from Standby mode. + 0x0 + + + B_0x1 + a rising or falling edge on WUPx pin wakes up the system from Standby mode. + 0x1 + + + + + WUPEN2 + enable wake-up pin WUPx (x = 8 to 1) + + 1 + 1 + read-write + + + B_0x0 + an event on WUPx pin does not wake-up the system from Standby mode. + 0x0 + + + B_0x1 + a rising or falling edge on WUPx pin wakes up the system from Standby mode. + 0x1 + + + + + WUPEN3 + enable wake-up pin WUPx (x = 8 to 1) + + 2 + 1 + read-write + + + B_0x0 + an event on WUPx pin does not wake-up the system from Standby mode. + 0x0 + + + B_0x1 + a rising or falling edge on WUPx pin wakes up the system from Standby mode. + 0x1 + + + + + WUPEN4 + enable wake-up pin WUPx (x = 8 to 1) + + 3 + 1 + read-write + + + B_0x0 + an event on WUPx pin does not wake-up the system from Standby mode. + 0x0 + + + B_0x1 + a rising or falling edge on WUPx pin wakes up the system from Standby mode. + 0x1 + + + + + WUPEN5 + enable wake-up pin WUPx (x = 8 to 1) + + 4 + 1 + read-write + + + B_0x0 + an event on WUPx pin does not wake-up the system from Standby mode. + 0x0 + + + B_0x1 + a rising or falling edge on WUPx pin wakes up the system from Standby mode. + 0x1 + + + + + WUPEN6 + enable wake-up pin WUPx (x = 8 to 1) + + 5 + 1 + read-write + + + B_0x0 + an event on WUPx pin does not wake-up the system from Standby mode. + 0x0 + + + B_0x1 + a rising or falling edge on WUPx pin wakes up the system from Standby mode. + 0x1 + + + + + WUPEN7 + enable wake-up pin WUPx (x = 8 to 1) + + 6 + 1 + read-write + + + B_0x0 + an event on WUPx pin does not wake-up the system from Standby mode. + 0x0 + + + B_0x1 + a rising or falling edge on WUPx pin wakes up the system from Standby mode. + 0x1 + + + + + WUPEN8 + enable wake-up pin WUPx (x = 8 to 1) + + 7 + 1 + read-write + + + B_0x0 + an event on WUPx pin does not wake-up the system from Standby mode. + 0x0 + + + B_0x1 + a rising or falling edge on WUPx pin wakes up the system from Standby mode. + 0x1 + + + + + WUPP1 + wake-up pin polarity bit for WUPx (x = 8 to 1) + + 8 + 1 + read-write + + + B_0x0 + detection on high level (rising edge) + 0x0 + + + B_0x1 + detection on low level (falling edge) + 0x1 + + + + + WUPP2 + wake-up pin polarity bit for WUPx (x = 8 to 1) + + 9 + 1 + read-write + + + B_0x0 + detection on high level (rising edge) + 0x0 + + + B_0x1 + detection on low level (falling edge) + 0x1 + + + + + WUPP3 + wake-up pin polarity bit for WUPx (x = 8 to 1) + + 10 + 1 + read-write + + + B_0x0 + detection on high level (rising edge) + 0x0 + + + B_0x1 + detection on low level (falling edge) + 0x1 + + + + + WUPP4 + wake-up pin polarity bit for WUPx (x = 8 to 1) + + 11 + 1 + read-write + + + B_0x0 + detection on high level (rising edge) + 0x0 + + + B_0x1 + detection on low level (falling edge) + 0x1 + + + + + WUPP5 + wake-up pin polarity bit for WUPx (x = 8 to 1) + + 12 + 1 + read-write + + + B_0x0 + detection on high level (rising edge) + 0x0 + + + B_0x1 + detection on low level (falling edge) + 0x1 + + + + + WUPP6 + wake-up pin polarity bit for WUPx (x = 8 to 1) + + 13 + 1 + read-write + + + B_0x0 + detection on high level (rising edge) + 0x0 + + + B_0x1 + detection on low level (falling edge) + 0x1 + + + + + WUPP7 + wake-up pin polarity bit for WUPx (x = 8 to 1) + + 14 + 1 + read-write + + + B_0x0 + detection on high level (rising edge) + 0x0 + + + B_0x1 + detection on low level (falling edge) + 0x1 + + + + + WUPP8 + wake-up pin polarity bit for WUPx (x = 8 to 1) + + 15 + 1 + read-write + + + B_0x0 + detection on high level (rising edge) + 0x0 + + + B_0x1 + detection on low level (falling edge) + 0x1 + + + + + WUPPUPD1 + wake-up pin pull configuration for WKUPx (x = 8 to 1) + + 16 + 2 + read-write + + + B_0x0 + no pull-up + 0x0 + + + B_0x1 + pull-up + 0x1 + + + B_0x2 + pull-down + 0x2 + + + + + WUPPUPD2 + wake-up pin pull configuration for WKUPx (x = 8 to 1) + + 18 + 2 + read-write + + + B_0x0 + no pull-up + 0x0 + + + B_0x1 + pull-up + 0x1 + + + B_0x2 + pull-down + 0x2 + + + + + WUPPUPD3 + wake-up pin pull configuration for WKUPx (x = 8 to 1) + + 20 + 2 + read-write + + + B_0x0 + no pull-up + 0x0 + + + B_0x1 + pull-up + 0x1 + + + B_0x2 + pull-down + 0x2 + + + + + WUPPUPD4 + wake-up pin pull configuration for WKUPx (x = 8 to 1) + + 22 + 2 + read-write + + + B_0x0 + no pull-up + 0x0 + + + B_0x1 + pull-up + 0x1 + + + B_0x2 + pull-down + 0x2 + + + + + WUPPUPD5 + wake-up pin pull configuration for WKUPx (x = 8 to 1) + + 24 + 2 + read-write + + + B_0x0 + no pull-up + 0x0 + + + B_0x1 + pull-up + 0x1 + + + B_0x2 + pull-down + 0x2 + + + + + WUPPUPD6 + wake-up pin pull configuration for WKUPx (x = 8 to 1) + + 26 + 2 + read-write + + + B_0x0 + no pull-up + 0x0 + + + B_0x1 + pull-up + 0x1 + + + B_0x2 + pull-down + 0x2 + + + + + WUPPUPD7 + wake-up pin pull configuration for WKUPx (x = 8 to 1) + + 28 + 2 + read-write + + + B_0x0 + no pull-up + 0x0 + + + B_0x1 + pull-up + 0x1 + + + B_0x2 + pull-down + 0x2 + + + + + WUPPUPD8 + wake-up pin pull configuration for WKUPx (x = 8 to 1) + + 30 + 2 + read-write + + + B_0x0 + no pull-up + 0x0 + + + B_0x1 + pull-up + 0x1 + + + B_0x2 + pull-down + 0x2 + + + + + + + PWR_IORETR + PWR_IORETR + PWR I/O retention register + 0x050 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IORETEN + IO retention enable + + 0 + 1 + read-write + + + B_0x0 + IO Retention mode is disabled. + 0x0 + + + B_0x1 + IO Retention mode is enabling for all IO except the IO support the standby functionality and PA13, PA14, PA15, and PB4. + 0x1 + + + + + JTAGIORETEN + IO retention enable for JTAG IOs + + 16 + 1 + read-write + + + B_0x0 + IO Retention mode is disabled. + 0x0 + + + B_0x1 + IO Retention mode is enabling for PA13, PA14, PA15, and PB4. + 0x1 + + + + + + + PWR_SECCFGR + PWR_SECCFGR + PWR security configuration register + 0x100 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + WUP1SEC + WUPx secure protection (x = 8 to 1) + 0 + 1 + read-write + + + B_0x0 + The bits related to the WKUPx wake-up pin in PWR_WUSCR and PWR_WUCR can be read and written with secure or non-secure access. + 0x0 + + + B_0x1 + The bits related to the WKUPx wake-up pin in PWR_WUSCR and PWR_WUCR can be read and written only with secure access. + 0x1 + + + + + WUP2SEC + WUPx secure protection (x = 8 to 1) + 1 + 1 + read-write + + + B_0x0 + The bits related to the WKUPx wake-up pin in PWR_WUSCR and PWR_WUCR can be read and written with secure or non-secure access. + 0x0 + + + B_0x1 + The bits related to the WKUPx wake-up pin in PWR_WUSCR and PWR_WUCR can be read and written only with secure access. + 0x1 + + + + + WUP3SEC + WUPx secure protection (x = 8 to 1) + 2 + 1 + read-write + + + B_0x0 + The bits related to the WKUPx wake-up pin in PWR_WUSCR and PWR_WUCR can be read and written with secure or non-secure access. + 0x0 + + + B_0x1 + The bits related to the WKUPx wake-up pin in PWR_WUSCR and PWR_WUCR can be read and written only with secure access. + 0x1 + + + + + WUP4SEC + WUPx secure protection (x = 8 to 1) + 3 + 1 + read-write + + + B_0x0 + The bits related to the WKUPx wake-up pin in PWR_WUSCR and PWR_WUCR can be read and written with secure or non-secure access. + 0x0 + + + B_0x1 + The bits related to the WKUPx wake-up pin in PWR_WUSCR and PWR_WUCR can be read and written only with secure access. + 0x1 + + + + + WUP5SEC + WUPx secure protection (x = 8 to 1) + 4 + 1 + read-write + + + B_0x0 + The bits related to the WKUPx wake-up pin in PWR_WUSCR and PWR_WUCR can be read and written with secure or non-secure access. + 0x0 + + + B_0x1 + The bits related to the WKUPx wake-up pin in PWR_WUSCR and PWR_WUCR can be read and written only with secure access. + 0x1 + + + + + WUP6SEC + WUPx secure protection (x = 8 to 1) + 5 + 1 + read-write + + + B_0x0 + The bits related to the WKUPx wake-up pin in PWR_WUSCR and PWR_WUCR can be read and written with secure or non-secure access. + 0x0 + + + B_0x1 + The bits related to the WKUPx wake-up pin in PWR_WUSCR and PWR_WUCR can be read and written only with secure access. + 0x1 + + + + + WUP7SEC + WUPx secure protection (x = 8 to 1) + 6 + 1 + read-write + + + B_0x0 + The bits related to the WKUPx wake-up pin in PWR_WUSCR and PWR_WUCR can be read and written with secure or non-secure access. + 0x0 + + + B_0x1 + The bits related to the WKUPx wake-up pin in PWR_WUSCR and PWR_WUCR can be read and written only with secure access. + 0x1 + + + + + WUP8SEC + WUPx secure protection (x = 8 to 1) + 7 + 1 + read-write + + + B_0x0 + The bits related to the WKUPx wake-up pin in PWR_WUSCR and PWR_WUCR can be read and written with secure or non-secure access. + 0x0 + + + B_0x1 + The bits related to the WKUPx wake-up pin in PWR_WUSCR and PWR_WUCR can be read and written only with secure access. + 0x1 + + + + + RETSEC + retention secure protection + 11 + 1 + read-write + + + B_0x0 + PWR_IORETR can be read and written with secure or non-secure access. + 0x0 + + + B_0x1 + PWR_IORETR can be read and written only with secure access. + 0x1 + + + + + LPMSEC + low-power modes secure protection + 12 + 1 + read-write + + + B_0x0 + PWR_PMCR can be read and written with secure or non-secure access. + 0x0 + + + B_0x1 + PWR_PMCR can be read and written only with secure access. + 0x1 + + + + + SCMSEC + supply configuration and monitoring secure protection. + 13 + 1 + read-write + + + B_0x0 + PWR_SCCR and PWR_VMCR can be read and written with secure or non-secure access. + 0x0 + + + B_0x1 + PWR_SCCR and PWR_VMCR can be read and written only with secure access. + 0x1 + + + + + VBSEC + Backup domain secure protection + 14 + 1 + read-write + + + B_0x0 + PWR_BDCR, PWR_DBPCR can be read and written with secure or non-secure access. + 0x0 + + + B_0x1 + PWR_BDCR, PWR_DBPCR can be read and written only with secure access. + 0x1 + + + + + VUSBSEC + voltage USB secure protection + 15 + 1 + read-write + + + B_0x0 + PWR_USBSCR can be read and written with secure or non-secure access. + 0x0 + + + B_0x1 + PWR_USBSCR can be read and written only with secure access. + 0x1 + + + + + + + PWR_PRIVCFGR + PWR_PRIVCFGR + PWR privilege configuration register + 0x104 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SPRIV + PWR secure functions privilege configuration + + 0 + 1 + read-write + + + B_0x0 + Read and write to PWR secure functions can be done by privileged or unprivileged access. + 0x0 + + + B_0x1 + Read and write to PWR secure functions can be done by privileged access only. + 0x1 + + + + + NSPRIV + PWR non-secure functions privilege configuration + + 1 + 1 + read-write + + + B_0x0 + Read and write to PWR non-secure functions can be done by privileged or unprivileged access. + 0x0 + + + B_0x1 + Read and write to PWR non-secure functions can be done by privileged access only. + 0x1 + + + + + + + + + PWR_S + 0X54020800 + + + RAMCFG + RAMCFG address block description + RAMCFG + 0x40026000 + + 0x0 + 0x12C + registers + + + RAMCFG + RAM configuration global interrupt + 5 + + + + RAMCFG_M1CR + RAMCFG_M1CR + RAMCFG memory 1 control register + 0x0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFF0 + + + ECCE + ECC enable. + 0 + 1 + read-write + + + B_0x0 + ECC disabled + 0x0 + + + B_0x1 + ECC enabled + 0x1 + + + + + ALE + Address latch enable + + 4 + 1 + read-write + + + B_0x0 + Failing address not stored in the SRAMx ECC single/double error address registers + 0x0 + + + B_0x1 + Failing address stored in the SRAMx ECC single/double error address registers + 0x1 + + + + + SRAMER + SRAM erase + + 8 + 1 + read-write + + + B_0x0 + No erase operation on going + 0x0 + + + B_0x1 + Erase operation on going + 0x1 + + + + + + + RAMCFG_M1ISR + RAMCFG_M1ISR + RAMCFG memory interrupt status register + 0x8 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + SEDC + ECC single error detected and corrected + + 0 + 1 + read-only + + + B_0x0 + No single error + 0x0 + + + B_0x1 + Single error detected and corrected + 0x1 + + + + + DED + ECC double error detected + + 1 + 1 + read-only + + + B_0x0 + No double error + 0x0 + + + B_0x1 + Double error detected + 0x1 + + + + + SRAMBUSY + SRAM busy with erase operation + + 8 + 1 + read-only + + + B_0x0 + No erase operation on going + 0x0 + + + B_0x1 + Erase operation on going + 0x1 + + + + + + + RAMCFG_M1ERKEYR + RAMCFG_M1ERKEYR + RAMCFG memory 1 erase key register + 0x28 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + ERASEKEY + Erase write protection key + + 0 + 8 + write-only + + + + + RAMCFG_M2CR + RAMCFG_M2CR + RAMCFG memory 2 control register + 0x40 + 0x20 + read-write + 0x00000000 + 0xFFFFFFF0 + + + ECCE + ECC enable. + 0 + 1 + read-write + + + B_0x0 + ECC disabled + 0x0 + + + B_0x1 + ECC enabled + 0x1 + + + + + ALE + Address latch enable + + 4 + 1 + read-write + + + B_0x0 + Failing address not stored in the SRAMx ECC single/double error address registers + 0x0 + + + B_0x1 + Failing address stored in the SRAMx ECC single/double error address registers + 0x1 + + + + + SRAMER + SRAM erase + + 8 + 1 + read-write + + + B_0x0 + No erase operation on going + 0x0 + + + B_0x1 + Erase operation on going + 0x1 + + + + + + + RAMCFG_M2IER + RAMCFG_M2IER + RAMCFG memory 2 interrupt enable register + 0x44 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SEIE + ECC single error interrupt enable + 0 + 1 + read-write + + + B_0x0 + Single error interrupt disabled + 0x0 + + + B_0x1 + Single error interrupt enabled + 0x1 + + + + + DEIE + ECC double error interrupt enable + 1 + 1 + read-write + + + B_0x0 + Double error interrupt disabled + 0x0 + + + B_0x1 + Double error interrupt enabled + 0x1 + + + + + ECCNMI + Double error NMI + + 3 + 1 + read-write + + + B_0x0 + NMI not generated in case of ECC double error + 0x0 + + + B_0x1 + NMI generated in case of ECC double error + 0x1 + + + + + + + RAMCFG_M2ISR + RAMCFG_M2ISR + RAMCFG memory interrupt status register + 0x48 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + SEDC + ECC single error detected and corrected + + 0 + 1 + read-only + + + B_0x0 + No single error + 0x0 + + + B_0x1 + Single error detected and corrected + 0x1 + + + + + DED + ECC double error detected + + 1 + 1 + read-only + + + B_0x0 + No double error + 0x0 + + + B_0x1 + Double error detected + 0x1 + + + + + SRAMBUSY + SRAM busy with erase operation + + 8 + 1 + read-only + + + B_0x0 + No erase operation on going + 0x0 + + + B_0x1 + Erase operation on going + 0x1 + + + + + + + RAMCFG_M2SEAR + RAMCFG_M2SEAR + RAMCFG memory 2 ECC single error address register + 0x4C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + ESEA + ECC single error address + + 0 + 32 + read-only + + + + + RAMCFG_M2DEAR + RAMCFG_M2DEAR + RAMCFG memory 2 ECC double error address register + 0x50 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + EDEA + ECC double error address + + 0 + 32 + read-only + + + + + RAMCFG_M2ICR + RAMCFG_M2ICR + RAMCFG memory 2 interrupt clear register 2 + 0x54 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CSEDC + Clear ECC single error detected and corrected + + 0 + 1 + read-write + + + CDED + Clear ECC double error detected + + 1 + 1 + read-write + + + + + RAMCFG_M2WPR1 + RAMCFG_M2WPR1 + RAMCFG memory 2 write protection register 1 + 0x058 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + P0WP + SRAM2 1-Kbyte page y write protection + + 0 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P1WP + SRAM2 1-Kbyte page y write protection + + 1 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P2WP + SRAM2 1-Kbyte page y write protection + + 2 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P3WP + SRAM2 1-Kbyte page y write protection + + 3 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P4WP + SRAM2 1-Kbyte page y write protection + + 4 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P5WP + SRAM2 1-Kbyte page y write protection + + 5 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P6WP + SRAM2 1-Kbyte page y write protection + + 6 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P7WP + SRAM2 1-Kbyte page y write protection + + 7 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P8WP + SRAM2 1-Kbyte page y write protection + + 8 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P9WP + SRAM2 1-Kbyte page y write protection + + 9 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P10WP + SRAM2 1-Kbyte page y write protection + + 10 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P11WP + SRAM2 1-Kbyte page y write protection + + 11 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P12WP + SRAM2 1-Kbyte page y write protection + + 12 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P13WP + SRAM2 1-Kbyte page y write protection + + 13 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P14WP + SRAM2 1-Kbyte page y write protection + + 14 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P15WP + SRAM2 1-Kbyte page y write protection + + 15 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P16WP + SRAM2 1-Kbyte page y write protection + + 16 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P17WP + SRAM2 1-Kbyte page y write protection + + 17 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P18WP + SRAM2 1-Kbyte page y write protection + + 18 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P19WP + SRAM2 1-Kbyte page y write protection + + 19 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P20WP + SRAM2 1-Kbyte page y write protection + + 20 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P21WP + SRAM2 1-Kbyte page y write protection + + 21 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P22WP + SRAM2 1-Kbyte page y write protection + + 22 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P23WP + SRAM2 1-Kbyte page y write protection + + 23 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P24WP + SRAM2 1-Kbyte page y write protection + + 24 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P25WP + SRAM2 1-Kbyte page y write protection + + 25 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P26WP + SRAM2 1-Kbyte page y write protection + + 26 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P27WP + SRAM2 1-Kbyte page y write protection + + 27 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P28WP + SRAM2 1-Kbyte page y write protection + + 28 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P29WP + SRAM2 1-Kbyte page y write protection + + 29 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P30WP + SRAM2 1-Kbyte page y write protection + + 30 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P31WP + SRAM2 1-Kbyte page y write protection + + 31 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + + + RAMCFG_M2WPR2 + RAMCFG_M2WPR2 + RAMCFG memory 2 write protection register 2 + 0x05C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + P32WP + SRAM2 1-Kbyte page y write protection + + 0 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P33WP + SRAM2 1-Kbyte page y write protection + + 1 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P34WP + SRAM2 1-Kbyte page y write protection + + 2 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P35WP + SRAM2 1-Kbyte page y write protection + + 3 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P36WP + SRAM2 1-Kbyte page y write protection + + 4 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P37WP + SRAM2 1-Kbyte page y write protection + + 5 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P38WP + SRAM2 1-Kbyte page y write protection + + 6 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P39WP + SRAM2 1-Kbyte page y write protection + + 7 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P40WP + SRAM2 1-Kbyte page y write protection + + 8 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P41WP + SRAM2 1-Kbyte page y write protection + + 9 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P42WP + SRAM2 1-Kbyte page y write protection + + 10 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P43WP + SRAM2 1-Kbyte page y write protection + + 11 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P44WP + SRAM2 1-Kbyte page y write protection + + 12 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P45WP + SRAM2 1-Kbyte page y write protection + + 13 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P46WP + SRAM2 1-Kbyte page y write protection + + 14 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P47WP + SRAM2 1-Kbyte page y write protection + + 15 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P48WP + SRAM2 1-Kbyte page y write protection + + 16 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P49WP + SRAM2 1-Kbyte page y write protection + + 17 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P50WP + SRAM2 1-Kbyte page y write protection + + 18 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P51WP + SRAM2 1-Kbyte page y write protection + + 19 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P52WP + SRAM2 1-Kbyte page y write protection + + 20 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P53WP + SRAM2 1-Kbyte page y write protection + + 21 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P54WP + SRAM2 1-Kbyte page y write protection + + 22 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P55WP + SRAM2 1-Kbyte page y write protection + + 23 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P56WP + SRAM2 1-Kbyte page y write protection + + 24 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P57WP + SRAM2 1-Kbyte page y write protection + + 25 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P58WP + SRAM2 1-Kbyte page y write protection + + 26 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P59WP + SRAM2 1-Kbyte page y write protection + + 27 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P60WP + SRAM2 1-Kbyte page y write protection + + 28 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P61WP + SRAM2 1-Kbyte page y write protection + + 29 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P62WP + SRAM2 1-Kbyte page y write protection + + 30 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P63WP + SRAM2 1-Kbyte page y write protection + + 31 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + + + RAMCFG_M2WPR3 + RAMCFG_M2WPR3 + RAMCFG memory 2 write protection register 3 + 0x060 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + P64WP + SRAM2 1-Kbyte page y write protection + + 0 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P65WP + SRAM2 1-Kbyte page y write protection + + 1 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P66WP + SRAM2 1-Kbyte page y write protection + + 2 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P67WP + SRAM2 1-Kbyte page y write protection + + 3 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P68WP + SRAM2 1-Kbyte page y write protection + + 4 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P69WP + SRAM2 1-Kbyte page y write protection + + 5 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P70WP + SRAM2 1-Kbyte page y write protection + + 6 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P71WP + SRAM2 1-Kbyte page y write protection + + 7 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P72WP + SRAM2 1-Kbyte page y write protection + + 8 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P73WP + SRAM2 1-Kbyte page y write protection + + 9 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P74WP + SRAM2 1-Kbyte page y write protection + + 10 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P75WP + SRAM2 1-Kbyte page y write protection + + 11 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P76WP + SRAM2 1-Kbyte page y write protection + + 12 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P77WP + SRAM2 1-Kbyte page y write protection + + 13 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P78WP + SRAM2 1-Kbyte page y write protection + + 14 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P79WP + SRAM2 1-Kbyte page y write protection + + 15 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + + + RAMCFG_M2ECCKEYR + RAMCFG_M2ECCKEYR + RAMCFG memory 2 ECC key register + 0x64 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + ECCKEY + ECC write protection key + + 0 + 8 + write-only + + + + + RAMCFG_M2ERKEYR + RAMCFG_M2ERKEYR + RAMCFG memory 2 erase key register + 0x68 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + ERASEKEY + Erase write protection key + + 0 + 8 + write-only + + + + + RAMCFG_M3CR + RAMCFG_M3CR + RAMCFG memory 3 control register + 0x80 + 0x20 + read-write + 0x00000000 + 0xFFFFFFF0 + + + ECCE + ECC enable. + 0 + 1 + read-write + + + B_0x0 + ECC disabled + 0x0 + + + B_0x1 + ECC enabled + 0x1 + + + + + ALE + Address latch enable + + 4 + 1 + read-write + + + B_0x0 + Failing address not stored in the SRAMx ECC single/double error address registers + 0x0 + + + B_0x1 + Failing address stored in the SRAMx ECC single/double error address registers + 0x1 + + + + + SRAMER + SRAM erase + + 8 + 1 + read-write + + + B_0x0 + No erase operation on going + 0x0 + + + B_0x1 + Erase operation on going + 0x1 + + + + + + + RAMCFG_M3IER + RAMCFG_M3IER + RAMCFG memory 3 interrupt enable register + 0x84 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SEIE + ECC single error interrupt enable + 0 + 1 + read-write + + + B_0x0 + Single error interrupt disabled + 0x0 + + + B_0x1 + Single error interrupt enabled + 0x1 + + + + + DEIE + ECC double error interrupt enable + 1 + 1 + read-write + + + B_0x0 + Double error interrupt disabled + 0x0 + + + B_0x1 + Double error interrupt enabled + 0x1 + + + + + ECCNMI + Double error NMI + + 3 + 1 + read-write + + + B_0x0 + NMI not generated in case of ECC double error + 0x0 + + + B_0x1 + NMI generated in case of ECC double error + 0x1 + + + + + + + RAMCFG_M3ISR + RAMCFG_M3ISR + RAMCFG memory interrupt status register + 0x88 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + SEDC + ECC single error detected and corrected + + 0 + 1 + read-only + + + B_0x0 + No single error + 0x0 + + + B_0x1 + Single error detected and corrected + 0x1 + + + + + DED + ECC double error detected + + 1 + 1 + read-only + + + B_0x0 + No double error + 0x0 + + + B_0x1 + Double error detected + 0x1 + + + + + SRAMBUSY + SRAM busy with erase operation + + 8 + 1 + read-only + + + B_0x0 + No erase operation on going + 0x0 + + + B_0x1 + Erase operation on going + 0x1 + + + + + + + RAMCFG_M3SEAR + RAMCFG_M3SEAR + RAMCFG memory 3 ECC single error address register + 0x8C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + ESEA + ECC single error address + + 0 + 32 + read-only + + + + + RAMCFG_M3DEAR + RAMCFG_M3DEAR + RAMCFG memory 3 ECC double error address register + 0x90 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + EDEA + ECC double error address + + 0 + 32 + read-only + + + + + RAMCFG_M3ICR + RAMCFG_M3ICR + RAMCFG memory 3 interrupt clear register 3 + 0x94 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CSEDC + Clear ECC single error detected and corrected + + 0 + 1 + read-write + + + CDED + Clear ECC double error detected + + 1 + 1 + read-write + + + + + RAMCFG_M3ECCKEYR + RAMCFG_M3ECCKEYR + RAMCFG memory 3 ECC key register + 0xA4 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + ECCKEY + ECC write protection key + + 0 + 8 + write-only + + + + + RAMCFG_M3ERKEYR + RAMCFG_M3ERKEYR + RAMCFG memory 3 erase key register + 0xA8 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + ERASEKEY + Erase write protection key + + 0 + 8 + write-only + + + + + RAMCFG_M4ERKEYR + RAMCFG_M4ERKEYR + RAMCFG memory 4 erase key register + 0xE8 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + ERASEKEY + Erase write protection key + + 0 + 8 + write-only + + + + + RAMCFG_M5CR + RAMCFG_M5CR + RAMCFG memory 5 control register + 0x100 + 0x20 + read-write + 0x00000000 + 0xFFFFFFF0 + + + ECCE + ECC enable. + 0 + 1 + read-write + + + B_0x0 + ECC disabled + 0x0 + + + B_0x1 + ECC enabled + 0x1 + + + + + ALE + Address latch enable + + 4 + 1 + read-write + + + B_0x0 + Failing address not stored in the SRAMx ECC single/double error address registers + 0x0 + + + B_0x1 + Failing address stored in the SRAMx ECC single/double error address registers + 0x1 + + + + + SRAMER + SRAM erase + + 8 + 1 + read-write + + + B_0x0 + No erase operation on going + 0x0 + + + B_0x1 + Erase operation on going + 0x1 + + + + + + + RAMCFG_M5IER + RAMCFG_M5IER + RAMCFG memory 5 interrupt enable register + 0x104 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SEIE + ECC single error interrupt enable + 0 + 1 + read-write + + + B_0x0 + Single error interrupt disabled + 0x0 + + + B_0x1 + Single error interrupt enabled + 0x1 + + + + + DEIE + ECC double error interrupt enable + 1 + 1 + read-write + + + B_0x0 + Double error interrupt disabled + 0x0 + + + B_0x1 + Double error interrupt enabled + 0x1 + + + + + ECCNMI + Double error NMI + + 3 + 1 + read-write + + + B_0x0 + NMI not generated in case of ECC double error + 0x0 + + + B_0x1 + NMI generated in case of ECC double error + 0x1 + + + + + + + RAMCFG_M5ISR + RAMCFG_M5ISR + RAMCFG memory interrupt status register + 0x108 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + SEDC + ECC single error detected and corrected + + 0 + 1 + read-only + + + B_0x0 + No single error + 0x0 + + + B_0x1 + Single error detected and corrected + 0x1 + + + + + DED + ECC double error detected + + 1 + 1 + read-only + + + B_0x0 + No double error + 0x0 + + + B_0x1 + Double error detected + 0x1 + + + + + SRAMBUSY + SRAM busy with erase operation + + 8 + 1 + read-only + + + B_0x0 + No erase operation on going + 0x0 + + + B_0x1 + Erase operation on going + 0x1 + + + + + + + RAMCFG_M5SEAR + RAMCFG_M5SEAR + RAMCFG memory 5 ECC single error address register + 0x10C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + ESEA + ECC single error address + + 0 + 32 + read-only + + + + + RAMCFG_M5DEAR + RAMCFG_M5DEAR + RAMCFG memory 5 ECC double error address register + 0x110 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + EDEA + ECC double error address + + 0 + 32 + read-only + + + + + RAMCFG_M5ICR + RAMCFG_M5ICR + RAMCFG memory 5 interrupt clear register 5 + 0x114 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CSEDC + Clear ECC single error detected and corrected + + 0 + 1 + read-write + + + CDED + Clear ECC double error detected + + 1 + 1 + read-write + + + + + RAMCFG_M5ECCKEYR + RAMCFG_M5ECCKEYR + RAMCFG memory 5 ECC key register + 0x124 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + ECCKEY + ECC write protection key + + 0 + 8 + write-only + + + + + RAMCFG_M5ERKEYR + RAMCFG_M5ERKEYR + RAMCFG memory 5 erase key register + 0x128 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + ERASEKEY + Erase write protection key + + 0 + 8 + write-only + + + + + + + RAMCFG_S + 0X50026000 + + + RCC + RCC address block description + RCC + 0x44020c00 + + 0x0 + 0x118 + registers + + + RCC_S + RCC secure global interrupt + 10 + + + RCC + RCC non-secure global interrupt + 9 + + + + RCC_CR + RCC_CR + RCC clock control register + 0x000 + 0x20 + read-write + 0x0000002B + 0xFFFFFFFF + + + HSION + HSI clock enable + + 0 + 1 + read-write + + + B_0x0 + HSI is OFF + 0x0 + + + B_0x1 + HSI is ON (default after reset) + 0x1 + + + + + HSIRDY + HSI clock ready flag + + 1 + 1 + read-only + + + B_0x0 + HSI clock is not ready (default after reset) + 0x0 + + + B_0x1 + HSI clock is ready + 0x1 + + + + + HSIKERON + HSI clock enable in Stop mode + + 2 + 1 + read-write + + + B_0x0 + no effect on HSI (default after reset) + 0x0 + + + B_0x1 + HSI is forced to ON even in Stop mode + 0x1 + + + + + HSIDIV + HSI clock divider + + 3 + 2 + read-write + + + B_0x0 + division by 1, hsi_ck, hsi_ker_ck = 64 MHz + 0x0 + + + B_0x1 + division by 2, hsi_ck, hsi_ker_ck = 32 MHz (default after reset) + 0x1 + + + B_0x2 + division by 4, hsi_ck, hsi_ker_ck = 16 MHz + 0x2 + + + B_0x3 + division by 8, hsi_ck, hsi_ker_ck = 8 MHz + 0x3 + + + + + HSIDIVF + HSI divider flag + + 5 + 1 + read-only + + + B_0x0 + new division ratio not yet propagated to hsi_ck , hsi_ker_ck (default after reset) + 0x0 + + + B_0x1 + hsi_ck , hsi_ker_ck clock frequency reflects the new HSIDIV value (default register value when the clock setting is completed). + 0x1 + + + + + CSION + CSI clock enable + + 8 + 1 + read-write + + + B_0x0 + CSI is OFF (default after reset) + 0x0 + + + B_0x1 + CSI is ON + 0x1 + + + + + CSIRDY + CSI clock ready flag + + 9 + 1 + read-only + + + B_0x0 + CSI clock is not ready (default after reset) + 0x0 + + + B_0x1 + CSI clock is ready + 0x1 + + + + + CSIKERON + CSI clock enable in Stop mode + + 10 + 1 + read-write + + + B_0x0 + no effect on CSI (default after reset) + 0x0 + + + B_0x1 + CSI is forced to ON even in Stop mode + 0x1 + + + + + HSI48ON + HSI48 clock enable + + 12 + 1 + read-write + + + B_0x0 + HSI48 is OFF (default after reset) + 0x0 + + + B_0x1 + HSI48 is ON + 0x1 + + + + + HSI48RDY + HSI48 clock ready flag + + 13 + 1 + read-only + + + B_0x0 + HSI48 clock is not ready (default after reset) + 0x0 + + + B_0x1 + HSI48 clock is ready + 0x1 + + + + + HSEON + HSE clock enable + + 16 + 1 + read-write + + + B_0x0 + HSE is OFF (default after reset) + 0x0 + + + B_0x1 + HSE is ON + 0x1 + + + + + HSERDY + HSE clock ready flag + + 17 + 1 + read-only + + + B_0x0 + HSE clock is not ready (default after reset) + 0x0 + + + B_0x1 + HSE clock is ready + 0x1 + + + + + HSEBYP + HSE clock bypass + + 18 + 1 + read-write + + + B_0x0 + HSE oscillator not bypassed (default after reset) + 0x0 + + + B_0x1 + HSE oscillator bypassed with an external clock + 0x1 + + + + + HSECSSON + HSE clock security system enable + + 19 + 1 + read-write + + + B_0x0 + CSS on HSE OFF (clock detector OFF) (default after reset) + 0x0 + + + B_0x1 + CSS on HSE ON (clock detector ON if the HSE oscillator is stable, OFF if not). + 0x1 + + + + + HSEEXT + external high speed clock type in Bypass mode + + 20 + 1 + read-write + + + B_0x0 + HSE in analog mode (default after reset) + 0x0 + + + B_0x1 + HSE in digital mode + 0x1 + + + + + PLL1ON + PLL1 enable + + 24 + 1 + read-write + + + B_0x0 + PLL1 OFF (default after reset) + 0x0 + + + B_0x1 + PLL1 ON + 0x1 + + + + + PLL1RDY + PLL1 clock ready flag + + 25 + 1 + read-only + + + B_0x0 + PLL1 unlocked (default after reset) + 0x0 + + + B_0x1 + PLL1 locked + 0x1 + + + + + PLL2ON + PLL2 enable + + 26 + 1 + read-write + + + B_0x0 + PLL2 OFF (default after reset) + 0x0 + + + B_0x1 + PLL2 ON + 0x1 + + + + + PLL2RDY + PLL2 clock ready flag + + 27 + 1 + read-only + + + B_0x0 + PLL2 unlocked + 0x0 + + + B_0x1 + PLL2 locked + 0x1 + + + + + PLL3ON + PLL3 enable + + 28 + 1 + read-write + + + B_0x0 + PLL3 OFF (default after reset) + 0x0 + + + B_0x1 + PLL3 ON + 0x1 + + + + + PLL3RDY + PLL3 clock ready flag + + 29 + 1 + read-only + + + B_0x0 + PLL3 unlocked (default after reset) + 0x0 + + + B_0x1 + PLL3 locked + 0x1 + + + + + + + RCC_HSICFGR + RCC_HSICFGR + RCC HSI calibration register + 0x010 + 0x20 + read-write + 0x00400000 + 0xFFFFF000 + + + HSICAL + HSI clock calibration + + 0 + 12 + read-only + + + HSITRIM + HSI clock trimming + + 16 + 7 + read-write + + + + + RCC_CRRCR + RCC_CRRCR + RCC clock recovery RC register + 0x014 + 0x20 + read-only + 0x00000000 + 0xFFFFF000 + + + HSI48CAL + Internal RC 48 MHz clock calibration + + 0 + 10 + read-only + + + + + RCC_CSICFGR + RCC_CSICFGR + RCC CSI calibration register + 0x018 + 0x20 + read-write + 0x00200000 + 0xFFFFF000 + + + CSICAL + CSI clock calibration + + 0 + 8 + read-write + + + CSITRIM + CSI clock trimming + + 16 + 6 + read-write + + + + + RCC_CFGR1 + RCC_CFGR1 + RCC clock configuration register1 + 0x01C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SW + system clock and trace clock switch + + 0 + 2 + read-write + + + B_0x0 + HSI selected as system clock (hsi_ck) (default after reset) + 0x0 + + + B_0x1 + CSI selected as system clock (csi_ck) + 0x1 + + + B_0x2 + HSE selected as system clock (hse_ck) + 0x2 + + + B_0x3 + PLL1 selected as system clock (pll1_p_ck for sys_ck) + 0x3 + + + + + SWS + system clock switch status + + 3 + 2 + read-only + + + B_0x1 + CSI used as system clock (csi_ck) + 0x1 + + + B_0x2 + HSE used as system clock (hse_ck) + 0x2 + + + B_0x3 + PLL1 used as system clock (pll1_p_ck) + 0x3 + + + + + STOPWUCK + system clock selection after a wakeup from system Stop + + 6 + 1 + read-write + + + B_0x1 + CSI selected as wakeup clock from system Stop + 0x1 + + + + + STOPKERWUCK + kernel clock selection after a wakeup from system Stop + + 7 + 1 + read-write + + + B_0x0 + HSI selected as wakeup clock from system Stop (default after reset) + 0x0 + + + B_0x1 + CSI selected as wakeup clock from system Stop + 0x1 + + + + + RTCPRE + HSE division factor for RTC clock + + 8 + 6 + read-write + + + B_0x0 + no clock (default after reset) + 0x0 + + + B_0x1 + no clock + 0x1 + + + B_0x2 + HSE/2 + 0x2 + + + B_0x3 + HSE/3 + 0x3 + + + B_0x4 + HSE/4 + 0x4 + + + B_0x3E + HSE/62 + 0x3E + + + B_0x3F + HSE/63 + 0x3F + + + + + TIMPRE + timers clocks prescaler selection + + 15 + 1 + read-write + + + B_0x0 + The timers kernel clock is equal to rcc_hclk1 if PPRE1 or PPRE2 corresponds to a division by 1 or 2, else it is equal to 2 x Fless thansub>rcc_pclk1less than/sub> or 2 x Fless thansub>rcc_pclk2less than/sub> (default after reset) + 0x0 + + + B_0x1 + The timers kernel clock is equal to 2 x Fless thansub>rcc_pclk1less than/sub> or 2 x Fless thansub>rcc_pclk2less than/sub> if PPRE1 or PPRE2 corresponds to a division by 1, 2 or 4, else it is equal to 4 x Fless thansub>rcc_pclk1less than/sub> or 4 x Fless thansub>rcc_pclk2less than/sub> + 0x1 + + + + + MCO1PRE + MCO1 prescaler + + 18 + 4 + read-write + + + B_0x0 + prescaler disabled (default after reset) + 0x0 + + + B_0x1 + division by 1 (bypass) + 0x1 + + + B_0x2 + division by 2 + 0x2 + + + B_0x3 + division by 3 + 0x3 + + + B_0x4 + division by 4 + 0x4 + + + B_0xF + division by 15 + 0xF + + + + + MCO1SEL + Microcontroller clock output 1 + + 22 + 3 + read-write + + + B_0x0 + HSI clock selected (hsi_ck) (default after reset) + 0x0 + + + B_0x1 + LSE oscillator clock selected (lse_ck) + 0x1 + + + B_0x2 + HSE clock selected (hse_ck) + 0x2 + + + B_0x3 + PLL1 clock selected (pll1_q_ck) + 0x3 + + + B_0x4 + HSI48 clock selected (hsi48_ck) + 0x4 + + + + + MCO2PRE + MCO2 prescaler + + 25 + 4 + read-write + + + B_0x0 + prescaler disabled (default after reset) + 0x0 + + + B_0x1 + division by 1 (bypass) + 0x1 + + + B_0x2 + division by 2 + 0x2 + + + B_0x3 + division by 3 + 0x3 + + + B_0x4 + division by 4 + 0x4 + + + B_0xF + division by 15 + 0xF + + + + + MCO2SEL + microcontroller clock output 2 + + 29 + 3 + read-write + + + B_0x0 + system clock selected (sys_ck) (default after reset) + 0x0 + + + B_0x1 + PLL2 oscillator clock selected (pll2_p_ck) + 0x1 + + + B_0x2 + HSE clock selected (hse_ck) + 0x2 + + + B_0x3 + PLL1 clock selected (pll1_p_ck) + 0x3 + + + B_0x4 + CSI clock selected (csi_ck) + 0x4 + + + B_0x5 + LSI clock selected (lsi_ck) + 0x5 + + + + + + + RCC_CFGR2 + RCC_CFGR2 + RCC CPU domain clock configuration register 2 + 0x020 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + HPRE + AHB prescaler + + 0 + 4 + read-write + + + B_0x8 + rcc_hclk = sys_ck / 2 + 0x8 + + + B_0x9 + rcc_hclk = sys_ck / 4 + 0x9 + + + B_0xA + rcc_hclk = sys_ck / 8 + 0xA + + + B_0xB + rcc_hclk = sys_ck / 16 + 0xB + + + B_0xC + rcc_hclk = sys_ck / 64 + 0xC + + + B_0xD + rcc_hclk = sys_ck / 128 + 0xD + + + B_0xE + rcc_hclk = sys_ck / 256 + 0xE + + + B_0xF + rcc_hclk = sys_ck / 512 + 0xF + + + + + PPRE1 + APB low-speed prescaler (APB1) + + 4 + 3 + read-write + + + B_0x4 + rcc_pclk1 = rcc_hclk1 / 2 + 0x4 + + + B_0x5 + rcc_pclk1 = rcc_hclk1 / 4 + 0x5 + + + B_0x6 + rcc_pclk1 = rcc_hclk1 / 8 + 0x6 + + + B_0x7 + rcc_pclk1 = rcc_hclk1 / 16 + 0x7 + + + + + PPRE2 + APB high-speed prescaler (APB2) + + 8 + 3 + read-write + + + B_0x4 + rcc_pclk2 = rcc_hclk1 / 2 + 0x4 + + + B_0x5 + rcc_pclk2 = rcc_hclk1 / 4 + 0x5 + + + B_0x6 + rcc_pclk2 = rcc_hclk1 / 8 + 0x6 + + + B_0x7 + rcc_pclk2 = rcc_hclk1 / 16 + 0x7 + + + + + PPRE3 + APB low-speed prescaler (APB3) + + 12 + 3 + read-write + + + B_0x4 + rcc_pclk3 = rcc_hclk1 / 2 + 0x4 + + + B_0x5 + rcc_pclk3 = rcc_hclk1 / 4 + 0x5 + + + B_0x6 + rcc_pclk3 = rcc_hclk1 / 8 + 0x6 + + + B_0x7 + rcc_pclk3 = rcc_hclk1 / 16 + 0x7 + + + + + AHB1DIS + AHB1 clock disable + + 16 + 1 + read-write + + + B_0x0 + AHB1 clock enabled, distributed to peripherals according to their dedicated clock enable control bits + 0x0 + + + B_0x1 + AHB1 clock disabled + 0x1 + + + + + AHB2DIS + AHB2 clock disable + + 17 + 1 + read-write + + + B_0x0 + AHB2 clock enabled, distributed to peripherals according to their dedicated clock enable control bits + 0x0 + + + B_0x1 + AHB2 clock disabled + 0x1 + + + + + AHB4DIS + AHB4 clock disable + + 19 + 1 + read-write + + + B_0x0 + AHB4 clock enabled, distributed to peripherals according to their dedicated clock enable control bits + 0x0 + + + B_0x1 + AHB4 clock disabled + 0x1 + + + + + APB1DIS + APB1 clock disable value + + 20 + 1 + read-write + + + B_0x0 + APB1 clock enabled, distributed to peripherals according to their dedicated clock enable control bits + 0x0 + + + B_0x1 + APB1 clock disabled + 0x1 + + + + + APB2DIS + APB2 clock disable value + + 21 + 1 + read-write + + + B_0x0 + APB2 clock enabled, distributed to peripherals according to their dedicated clock enable control bits + 0x0 + + + B_0x1 + APB2 clock disabled + 0x1 + + + + + APB3DIS + APB3 clock disable value. + 22 + 1 + read-write + + + B_0x0 + APB3 clock enabled, distributed to peripherals according to their dedicated clock enable control bits + 0x0 + + + B_0x1 + APB3 clock disabled + 0x1 + + + + + + + RCC_PLL1CFGR + RCC_PLL1CFGR + RCC PLL clock source selection register + 0x028 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PLL1SRC + PLL1M and PLLs clock source selection + + 0 + 2 + read-write + + + B_0x0 + no clock send to PLL1M divider and PLLs (default after reset). + 0x0 + + + B_0x1 + HSI selected as PLL clock (hsi_ck) + 0x1 + + + B_0x2 + CSI selected as PLL clock (csi_ck) + 0x2 + + + B_0x3 + HSE selected as PLL clock (hse_ck) + 0x3 + + + + + PLL1RGE + PLL1 input frequency range + + 2 + 2 + read-write + + + B_0x0 + PLL1 input (ref1_ck) clock range frequency between 1 and 2 MHz (default after reset) + 0x0 + + + B_0x1 + PLL1 input (ref1_ck) clock range frequency between 2 and 4 MHz + 0x1 + + + B_0x2 + PLL1 input (ref1_ck) clock range frequency between 4 and 8 MHz + 0x2 + + + B_0x3 + PLL1 input (ref1_ck) clock range frequency between 8 and 16 MHz + 0x3 + + + + + PLL1FRACEN + PLL1 fractional latch enable + + 4 + 1 + read-write + + + PLL1VCOSEL + PLL1 VCO selection + + 5 + 1 + read-write + + + B_0x0 + wide VCO range: 192 to 836 MHz (default after reset) + 0x0 + + + B_0x1 + medium VCO range: 150 to 420 MHz + 0x1 + + + + + PLL1M + prescaler for PLL1 + + 8 + 6 + read-write + + + B_0x0 + prescaler disabled (default after reset) + 0x0 + + + B_0x1 + division by 1 (bypass) + 0x1 + + + B_0x2 + division by 2 + 0x2 + + + B_0x3 + division by 3 + 0x3 + + + B_0x20 + division by 32 + 0x20 + + + B_0x3F + division by 63 + 0x3F + + + + + PLL1PEN + PLL1 DIVP divider output enable + + 16 + 1 + read-write + + + B_0x0 + pll1_p_ck output disabled (default after reset) + 0x0 + + + B_0x1 + pll1_p_ck output enabled + 0x1 + + + + + PLL1QEN + PLL1 DIVQ divider output enable + + 17 + 1 + read-write + + + B_0x0 + pll1_q_ck output disabled (default after reset) + 0x0 + + + B_0x1 + pll1_q_ck output enabled + 0x1 + + + + + PLL1REN + PLL1 DIVR divider output enable + + 18 + 1 + read-write + + + B_0x0 + pll1_r_ck output disabled (default after reset) + 0x0 + + + B_0x1 + pll1_r_ck output enabled + 0x1 + + + + + + + RCC_PLL2CFGR + RCC_PLL2CFGR + RCC PLL clock source selection register + 0x02C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PLL2SRC + PLL2M and PLLs clock source selection + + 0 + 2 + read-write + + + B_0x0 + no clock send to PLL2M divider and PLLs (default after reset) + 0x0 + + + B_0x1 + HSI selected as PLL clock (hsi_ck) + 0x1 + + + B_0x2 + CSI selected as PLL clock (csi_ck) + 0x2 + + + B_0x3 + HSE selected as PLL clock (hse_ck) + 0x3 + + + + + PLL2RGE + PLL2 input frequency range + + 2 + 2 + read-write + + + B_0x0 + PLL2 input (ref2_ck) clock range frequency between 1 and 2 MHz (default after reset) 01: PLL2 input (ref2_ck) clock range frequency between 2 and 4 MHz + 0x0 + + + B_0x2 + PLL2 input (ref2_ck) clock range frequency between 4 and 8 MHz + 0x2 + + + B_0x3 + PLL2 input (ref2_ck) clock range frequency between 8 and 16 MHz + 0x3 + + + + + PLL2FRACEN + PLL2 fractional latch enable + + 4 + 1 + read-write + + + B_0x0 + pll2_p_ck output disabled (default after reset) + 0x0 + + + B_0x1 + pll2_p_ck output enabled + 0x1 + + + + + PLL2VCOSEL + PLL2 VCO selection + + 5 + 1 + read-write + + + B_0x0 + wide VCO range 192 to 836 MHz (default after reset) + 0x0 + + + B_0x1 + medium VCO range 150 to 420 MHz + 0x1 + + + + + PLL2M + prescaler for PLL2 + + 8 + 6 + read-write + + + B_0x0 + prescaler disabled (default after reset) + 0x0 + + + B_0x1 + division by 1 (bypass) + 0x1 + + + B_0x2 + division by 2 + 0x2 + + + B_0x3 + division by 3 + 0x3 + + + B_0x20 + division by 32 + 0x20 + + + B_0x3F + division by 63 + 0x3F + + + + + PLL2PEN + PLL2 DIVP divider output enable + + 16 + 1 + read-write + + + B_0x0 + pll2_p_ck output disabled (default after reset) + 0x0 + + + B_0x1 + pll2_p_ck output enabled + 0x1 + + + + + PLL2QEN + PLL2 DIVQ divider output enable + + 17 + 1 + read-write + + + B_0x0 + pll2_q_ck output disabled (default after reset) + 0x0 + + + B_0x1 + pll2_q_ck output enabled + 0x1 + + + + + PLL2REN + PLL2 DIVR divider output enable + + 18 + 1 + read-write + + + B_0x0 + pll2_r_ck output disabled (default after reset) + 0x0 + + + B_0x1 + pll2_r_ck output enabled + 0x1 + + + + + + + RCC_PLL3CFGR + RCC_PLL3CFGR + RCC PLL clock source selection register + 0x030 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PLL3SRC + PLL3M and PLLs clock source selection + + 0 + 2 + read-write + + + B_0x0 + no clock send to PLL3M divider and PLLs (default after reset) + 0x0 + + + B_0x1 + HSI selected as PLL clock (hsi_ck) + 0x1 + + + B_0x2 + CSI selected as PLL clock (csi_ck) + 0x2 + + + B_0x3 + HSE selected as PLL clock (hse_ck) + 0x3 + + + + + PLL3RGE + PLL3 input frequency range + + 2 + 2 + read-write + + + B_0x0 + PLL3 input (ref3_ck) clock range frequency between 1 and 2 MHz (default after reset) + 0x0 + + + B_0x1 + PLL3 input (ref3_ck) clock range frequency between 2 and 4 MHz + 0x1 + + + B_0x2 + PLL3 input (ref3_ck) clock range frequency between 4 and 8 MHz + 0x2 + + + B_0x3 + PLL3 input (ref3_ck) clock range frequency between 8 and 16 MHz + 0x3 + + + + + PLL3FRACEN + PLL3 fractional latch enable + + 4 + 1 + read-write + + + PLL3VCOSEL + PLL3 VCO selection + + 5 + 1 + read-write + + + B_0x0 + wide VCO range 192 to 836 MHz (default after reset) + 0x0 + + + B_0x1 + medium VCO range 150 to 420 MHz + 0x1 + + + + + PLL3M + prescaler for PLL3 + + 8 + 6 + read-write + + + B_0x0 + prescaler disabled (default after reset) + 0x0 + + + B_0x1 + division by 1 (bypass) + 0x1 + + + B_0x2 + division by 2 + 0x2 + + + B_0x3 + division by 3 + 0x3 + + + B_0x20 + division by 32 + 0x20 + + + B_0x3F + division by 63 + 0x3F + + + + + PLL3PEN + PLL3 DIVP divider output enable + + 16 + 1 + read-write + + + B_0x0 + pll3_p_ck output disabled (default after reset) + 0x0 + + + B_0x1 + pll3_p_ck output enabled + 0x1 + + + + + PLL3QEN + PLL3 DIVQ divider output enable + + 17 + 1 + read-write + + + B_0x0 + pll3_q_ck output disabled (default after reset) + 0x0 + + + B_0x1 + pll3_q_ck output enabled + 0x1 + + + + + PLL3REN + PLL3 DIVR divider output enable + + 18 + 1 + read-write + + + B_0x0 + pll3_r_ck output disabled (default after reset) + 0x0 + + + B_0x1 + pll3_r_ck output enabled + 0x1 + + + + + + + RCC_PLL1DIVR + RCC_PLL1DIVR + RCC PLL1 dividers register + 0x034 + 0x20 + read-write + 0x01010280 + 0xFFFFFFFF + + + PLL1N + Multiplication factor for PLL1VCO + + 0 + 9 + read-write + + + B_0x003 + PLL1N = 4 + 0x003 + + + B_0x004 + PLL1N = 5 + 0x004 + + + B_0x005 + PLL1N = 6 + 0x005 + + + B_0x080 + PLL1N = 129 (default after reset) + 0x080 + + + B_0x1FF + PLL1N = 512 + 0x1FF + + + + + PLL1P + PLL1 DIVP division factor + + 9 + 7 + read-write + + + B_0x0 + Not allowed + 0x0 + + + B_0x1 + pll1_p_ck = vco1_ck / 2 (default after reset) + 0x1 + + + B_0x2 + Not allowed + 0x2 + + + B_0x3 + pll1_p_ck = vco1_ck / 4 + 0x3 + + + B_0x7F + pll1_p_ck = vco1_ck / 128 + 0x7F + + + + + PLL1Q + PLL1 DIVQ division factor + + 16 + 7 + read-write + + + B_0x0 + pll1_q_ck = vco1_ck + 0x0 + + + B_0x1 + pll1_q_ck = vco1_ck / 2 (default after reset) + 0x1 + + + B_0x2 + pll1_q_ck = vco1_ck / 3 + 0x2 + + + B_0x3 + pll1_q_ck = vco1_ck / 4 + 0x3 + + + B_0x7F + pll1_q_ck = vco1_ck / 128 + 0x7F + + + + + PLL1R + PLL1 DIVR division factor + + 24 + 7 + read-write + + + B_0x0 + pll1_r_ck = vco1_ck / 1 + 0x0 + + + B_0x1 + pll1_r_ck = vco1_ck / 2 (default after reset) + 0x1 + + + B_0x2 + pll1_r_ck = vco1_ck / 3 + 0x2 + + + B_0x3 + pll1_r_ck = vco1_ck / 4 + 0x3 + + + B_0x7F + pll1_r_ck = vco1_ck / 128 + 0x7F + + + + + + + RCC_PLL1FRACR + RCC_PLL1FRACR + RCC PLL1 fractional divider register + 0x038 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PLL1FRACN + fractional part of the multiplication factor for PLL1 VCO + + 3 + 13 + read-write + + + + + RCC_PLL2DIVR + RCC_PLL2DIVR + RCC PLL1 dividers register + 0x03C + 0x20 + read-write + 0x01010280 + 0xFFFFFFFF + + + PLL2N + Multiplication factor for PLL2VCO + + 0 + 9 + read-write + + + B_0x003 + PLL2N = 4 + 0x003 + + + B_0x004 + PLL2N = 5 + 0x004 + + + B_0x005 + PLL2N = 6 + 0x005 + + + B_0x080 + PLL2N = 129 (default after reset) + 0x080 + + + B_0x1FF + PLL2N = 512 + 0x1FF + + + + + PLL2P + PLL2 DIVP division factor + + 9 + 7 + read-write + + + B_0x0 + pll2_p_ck = vco2_ck + 0x0 + + + B_0x1 + pll2_p_ck = vco2_ck / 2 (default after reset) + 0x1 + + + B_0x2 + pll2_p_ck = vco2_ck / 3 + 0x2 + + + B_0x3 + pll2_p_ck = vco2_ck / 4 + 0x3 + + + B_0x7F + pll2_p_ck = vco2_ck / 128 + 0x7F + + + + + PLL2Q + PLL2 DIVQ division factor + + 16 + 7 + read-write + + + B_0x0 + pll2_q_ck = vco2_ck + 0x0 + + + B_0x1 + pll2_q_ck = vco2_ck / 2 (default after reset) + 0x1 + + + B_0x2 + pll2_q_ck = vco2_ck / 3 + 0x2 + + + B_0x3 + pll2_q_ck = vco2_ck / 4 + 0x3 + + + B_0x7F + pll2_q_ck = vco2_ck / 128 + 0x7F + + + + + PLL2R + PLL2 DIVR division factor + + 24 + 7 + read-write + + + B_0x0 + pll2_r_ck = vco2_ck + 0x0 + + + B_0x1 + pll2_r_ck = vco2_ck / 2 (default after reset) + 0x1 + + + B_0x2 + pll2_r_ck = vco2_ck / 3 + 0x2 + + + B_0x3 + pll2_r_ck = vco2_ck / 4 + 0x3 + + + B_0x7F + pll2_r_ck = vco2_ck / 128 + 0x7F + + + + + + + RCC_PLL2FRACR + RCC_PLL2FRACR + RCC PLL2 fractional divider register + 0x040 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PLL2FRACN + fractional part of the multiplication factor for PLL2 VCO + + 3 + 13 + read-write + + + + + RCC_PLL3DIVR + RCC_PLL3DIVR + RCC PLL3 dividers register + 0x044 + 0x20 + read-write + 0x01010280 + 0xFFFFFFFF + + + PLL3N + Multiplication factor for PLL3VCO + + 0 + 9 + read-write + + + B_0x003 + PLL3N = 4 + 0x003 + + + B_0x004 + PLL3N = 5 + 0x004 + + + B_0x005 + PLL3N = 6 + 0x005 + + + B_0x080 + PLL3N = 129 (default after reset) + 0x080 + + + B_0x1FF + PLL3N = 512 + 0x1FF + + + + + PLL3P + PLL3 DIVP division factor + + 9 + 7 + read-write + + + B_0x0 + pll3_p_ck = vco3_ck + 0x0 + + + B_0x1 + pll3_p_ck = vco3_ck / 2 (default after reset) + 0x1 + + + B_0x2 + pll3_p_ck = vco3_ck / 3 + 0x2 + + + B_0x3 + pll3_p_ck = vco3_ck / 4 + 0x3 + + + B_0x7F + pll3_p_ck = vco3_ck / 128 + 0x7F + + + + + PLL3Q + PLL3 DIVQ division factor + + 16 + 7 + read-write + + + B_0x0 + pll3_q_ck = vco3_ck + 0x0 + + + B_0x1 + pll3_q_ck = vco3_ck / 2 (default after reset) + 0x1 + + + B_0x2 + pll3_q_ck = vco3_ck / 3 + 0x2 + + + B_0x3 + pll3_q_ck = vco3_ck / 4 + 0x3 + + + B_0x7F + pll3_q_ck = vco3_ck / 128 + 0x7F + + + + + PLL3R + PLL3 DIVR division factor + + 24 + 7 + read-write + + + B_0x0 + pll3_r_ck = vco3_ck + 0x0 + + + B_0x1 + pll3_r_ck = vco3_ck / 2 (default after reset) + 0x1 + + + B_0x2 + pll3_r_ck = vco3_ck / 3 + 0x2 + + + B_0x3 + pll3_r_ck = vco3_ck / 4 + 0x3 + + + B_0x7F + pll3_r_ck = vco3_ck / 128 + 0x7F + + + + + + + RCC_PLL3FRACR + RCC_PLL3FRACR + RCC PLL3 fractional divider register + 0x048 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PLL3FRACN + fractional part of the multiplication factor for PLL3 VCO + + 3 + 13 + read-write + + + + + RCC_CIER + RCC_CIER + RCC clock source interrupt enable register + 0x050 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LSIRDYIE + LSI ready interrupt enable + + 0 + 1 + read-write + + + B_0x0 + LSI ready interrupt disabled (default after reset) + 0x0 + + + B_0x1 + LSI ready interrupt enabled + 0x1 + + + + + LSERDYIE + LSE ready interrupt enable + + 1 + 1 + read-write + + + B_0x0 + LSE ready interrupt disabled (default after reset) + 0x0 + + + B_0x1 + LSE ready interrupt enabled + 0x1 + + + + + CSIRDYIE + CSI ready interrupt enable + + 2 + 1 + read-write + + + B_0x0 + CSI ready interrupt disabled (default after reset) + 0x0 + + + B_0x1 + CSI ready interrupt enabled + 0x1 + + + + + HSIRDYIE + HSI ready interrupt enable + + 3 + 1 + read-write + + + B_0x0 + HSI ready interrupt disabled (default after reset) + 0x0 + + + B_0x1 + HSI ready interrupt enabled + 0x1 + + + + + HSERDYIE + HSE ready interrupt enable + + 4 + 1 + read-write + + + B_0x0 + HSE ready interrupt disabled (default after reset) + 0x0 + + + B_0x1 + HSE ready interrupt enabled + 0x1 + + + + + HSI48RDYIE + HSI48 ready interrupt enable + + 5 + 1 + read-write + + + B_0x0 + HSI48 ready interrupt disabled (default after reset) + 0x0 + + + B_0x1 + HSI48 ready interrupt enabled + 0x1 + + + + + PLL1RDYIE + PLL1 ready interrupt enable + + 6 + 1 + read-write + + + B_0x0 + PLL1 lock interrupt disabled (default after reset) + 0x0 + + + B_0x1 + PLL1 lock interrupt enabled + 0x1 + + + + + PLL2RDYIE + PLL2 ready interrupt enable + + 7 + 1 + read-write + + + B_0x0 + PLL2 lock interrupt disabled (default after reset) + 0x0 + + + B_0x1 + PLL2 lock interrupt enabled + 0x1 + + + + + PLL3RDYIE + PLL3 ready interrupt enable + + 8 + 1 + read-write + + + B_0x0 + PLL3 lock interrupt disabled (default after reset) + 0x0 + + + B_0x1 + PLL3 lock interrupt enabled + 0x1 + + + + + + + RCC_CIFR + RCC_CIFR + RCC clock source interrupt flag register + 0x054 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + LSIRDYF + LSI ready interrupt flag + + 0 + 1 + read-only + + + B_0x0 + no clock ready interrupt caused by the LSI (default after reset) + 0x0 + + + B_0x1 + clock ready interrupt caused by the LSI + 0x1 + + + + + LSERDYF + LSE ready interrupt flag + + 1 + 1 + read-only + + + B_0x0 + no clock ready interrupt caused by the LSE (default after reset) + 0x0 + + + B_0x1 + clock ready interrupt caused by the LSE + 0x1 + + + + + CSIRDYF + CSI ready interrupt flag + + 2 + 1 + read-only + + + B_0x0 + no clock ready interrupt caused by the CSI (default after reset) + 0x0 + + + B_0x1 + clock ready interrupt caused by the CSI + 0x1 + + + + + HSIRDYF + HSI ready interrupt flag + + 3 + 1 + read-only + + + B_0x0 + no clock ready interrupt caused by the HSI (default after reset) + 0x0 + + + B_0x1 + clock ready interrupt caused by the HSI + 0x1 + + + + + HSERDYF + HSE ready interrupt flag + + 4 + 1 + read-only + + + B_0x0 + no clock ready interrupt caused by the HSE (default after reset) + 0x0 + + + B_0x1 + clock ready interrupt caused by the HSE + 0x1 + + + + + HSI48RDYF + HSI48 ready interrupt flag + + 5 + 1 + read-only + + + B_0x0 + no clock ready interrupt caused by the HSI48 oscillator (default after reset) + 0x0 + + + B_0x1 + clock ready interrupt caused by the HSI48 oscillator + 0x1 + + + + + PLL1RDYF + PLL1 ready interrupt flag + + 6 + 1 + read-only + + + B_0x0 + no clock ready interrupt caused by PLL1 lock (default after reset) + 0x0 + + + B_0x1 + clock ready interrupt caused by PLL1 lock + 0x1 + + + + + PLL2RDYF + PLL2 ready interrupt flag + + 7 + 1 + read-only + + + B_0x0 + no clock ready interrupt caused by PLL2 lock (default after reset) + 0x0 + + + B_0x1 + clock ready interrupt caused by PLL2 lock + 0x1 + + + + + PLL3RDYF + PLL3 ready interrupt flag + + 8 + 1 + read-only + + + B_0x0 + no clock ready interrupt caused by PLL3 lock (default after reset) + 0x0 + + + B_0x1 + clock ready interrupt caused by PLL3 lock + 0x1 + + + + + HSECSSF + HSE clock security system interrupt flag + + 10 + 1 + read-only + + + B_0x0 + no clock security interrupt caused by HSE clock failure (default after reset) + 0x0 + + + B_0x1 + clock security interrupt caused by HSE clock failure + 0x1 + + + + + + + RCC_CICR + RCC_CICR + RCC clock source interrupt clear register + 0x058 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LSIRDYC + LSI ready interrupt clear + + 0 + 1 + read-write + + + B_0x0 + LSIRDYF no effect (default after reset) + 0x0 + + + B_0x1 + LSIRDYF cleared + 0x1 + + + + + LSERDYC + LSE ready interrupt clear + + 1 + 1 + read-write + + + B_0x0 + LSERDYF no effect (default after reset) + 0x0 + + + B_0x1 + LSERDYF cleared + 0x1 + + + + + CSIRDYC + HSI ready interrupt clear + + 2 + 1 + read-write + + + B_0x0 + CSIRDYF no effect (default after reset) + 0x0 + + + B_0x1 + CSIRDYF cleared + 0x1 + + + + + HSIRDYC + HSI ready interrupt clear + + 3 + 1 + read-write + + + B_0x0 + HSIRDYF no effect (default after reset) + 0x0 + + + B_0x1 + HSIRDYF cleared + 0x1 + + + + + HSERDYC + HSE ready interrupt clear + + 4 + 1 + read-write + + + B_0x0 + HSERDYF no effect (default after reset) + 0x0 + + + B_0x1 + HSERDYF cleared + 0x1 + + + + + HSI48RDYC + HSI48 ready interrupt clear + + 5 + 1 + read-write + + + B_0x0 + HSI48RDYF no effect (default after reset) + 0x0 + + + B_0x1 + HSI48RDYF cleared + 0x1 + + + + + PLL1RDYC + PLL1 ready interrupt clear + + 6 + 1 + read-write + + + B_0x0 + PLL1RDYF no effect (default after reset) + 0x0 + + + B_0x1 + PLL1RDYF cleared + 0x1 + + + + + PLL2RDYC + PLL2 ready interrupt clear + + 7 + 1 + read-write + + + B_0x0 + PLL2RDYF no effect (default after reset) + 0x0 + + + B_0x1 + PLL2RDYF cleared + 0x1 + + + + + PLL3RDYC + PLL3 ready interrupt clear + + 8 + 1 + read-write + + + B_0x0 + PLL3RDYF no effect (default after reset) + 0x0 + + + B_0x1 + PLL3RDYF cleared + 0x1 + + + + + HSECSSC + HSE clock security system interrupt clear + + 10 + 1 + read-write + + + B_0x0 + HSECSSF no effect (default after reset) + 0x0 + + + B_0x1 + HSECSSF cleared + 0x1 + + + + + + + RCC_AHB1RSTR + RCC_AHB1RSTR + RCC AHB1 reset register + 0x060 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + GPDMA1RST + GPDMA1 block reset + + 0 + 1 + read-write + + + B_0x0 + does not reset GPDMA1 block (default after reset) + 0x0 + + + B_0x1 + resets GPDMA1 block + 0x1 + + + + + GPDMA2RST + GPDMA2 block reset + + 1 + 1 + read-write + + + B_0x0 + does not reset GPDMA2 block (default after reset) + 0x0 + + + B_0x1 + resets GPDMA2 block + 0x1 + + + + + CRCRST + CRC block reset Set and reset by software. + 12 + 1 + read-write + + + B_0x0 + does not reset CRC block (default after reset) + 0x0 + + + B_0x1 + resets CRC block + 0x1 + + + + + CORDICRST + CORDIC block reset + + 14 + 1 + read-write + + + B_0x0 + does not reset CORDIC block (default after reset) + 0x0 + + + B_0x1 + resets CORDIC block + 0x1 + + + + + FMACRST + FMAC block reset + + 15 + 1 + read-write + + + B_0x0 + does not reset FMAC block (default after reset) + 0x0 + + + B_0x1 + resets FMAC block + 0x1 + + + + + RAMCFGRST + RAMCFG block reset + + 17 + 1 + read-write + + + B_0x0 + does not reset RAMCFG block (default after reset) + 0x0 + + + B_0x1 + resets RAMCFG block + 0x1 + + + + + ETHRST + ETHRST block reset + + 19 + 1 + read-write + + + B_0x0 + does not reset ETHRST block (default after reset) + 0x0 + + + B_0x1 + resets the ETHRST block + 0x1 + + + + + + + RCC_AHB2RSTR + RCC_AHB2RSTR + RCC AHB2 peripheral reset register + 0x064 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + GPIOARST + GPIOA block reset + + 0 + 1 + read-write + + + B_0x0 + does not reset the GPIOA block (default after reset) + 0x0 + + + B_0x1 + resets the GPIOA block + 0x1 + + + + + GPIOBRST + GPIOB block reset + + 1 + 1 + read-write + + + B_0x0 + does not reset the GPIOB block (default after reset) + 0x0 + + + B_0x1 + resets the GPIOB block + 0x1 + + + + + GPIOCRST + GPIOC block reset + + 2 + 1 + read-write + + + B_0x0 + does not reset the GPIOC block (default after reset) + 0x0 + + + B_0x1 + resets the GPIOC block + 0x1 + + + + + GPIODRST + GPIOD block reset + + 3 + 1 + read-write + + + B_0x0 + does not reset the GPIOD block (default after reset) + 0x0 + + + B_0x1 + resets the GPIOD block + 0x1 + + + + + GPIOERST + GPIOE block reset + + 4 + 1 + read-write + + + B_0x0 + does not reset the GPIOE block (default after reset) + 0x0 + + + B_0x1 + resets the GPIOE block + 0x1 + + + + + GPIOFRST + GPIOF block reset + + 5 + 1 + read-write + + + B_0x0 + does not reset the GPIOF block (default after reset) + 0x0 + + + B_0x1 + resets the GPIOF block + 0x1 + + + + + GPIOGRST + GPIOG block reset + + 6 + 1 + read-write + + + B_0x0 + does not reset the GPIOG block (default after reset) + 0x0 + + + B_0x1 + resets the GPIOG block + 0x1 + + + + + GPIOHRST + GPIOH block reset + + 7 + 1 + read-write + + + B_0x0 + does not reset the GPIOH block (default after reset) + 0x0 + + + B_0x1 + resets the GPIOH block + 0x1 + + + + + GPIOIRST + GPIOI block reset + + 8 + 1 + read-write + + + B_0x0 + does not reset the GPIOI block (default after reset) + 0x0 + + + B_0x1 + resets the GPIOI block + 0x1 + + + + + ADCRST + ADC1 and 2 blocks reset + + 10 + 1 + read-write + + + B_0x0 + does not reset ADC1 and 2 blocks (default after reset) + 0x0 + + + B_0x1 + resets ADC1 and 2 blocks + 0x1 + + + + + DAC1RST + DAC block reset + + 11 + 1 + read-write + + + B_0x0 + does not reset DAC block (default after reset) + 0x0 + + + B_0x1 + resets DAC block + 0x1 + + + + + DCMI_PSSIRST + digital camera interface block reset (DCMI or PSSI depending which interface is active) + + 12 + 1 + read-write + + + B_0x0 + does not reset the DCMI/PSSI block (default after reset) + 0x0 + + + B_0x1 + resets the DCMI/PSSI block + 0x1 + + + + + AESRST + AES block reset + + 16 + 1 + read-write + + + B_0x0 + does not reset AES block (default after reset) + 0x0 + + + B_0x1 + resets AES block + 0x1 + + + + + HASHRST + HASH block reset + + 17 + 1 + read-write + + + B_0x0 + does not reset HASH block (default after reset) + 0x0 + + + B_0x1 + resets HASH block + 0x1 + + + + + RNGRST + RNG block reset + + 18 + 1 + read-write + + + B_0x0 + does not reset RNG block (default after reset) + 0x0 + + + B_0x1 + resets RNG block + 0x1 + + + + + PKARST + PKA block reset + + 19 + 1 + read-write + + + B_0x0 + does not reset PKA block (default after reset) + 0x0 + + + B_0x1 + resets PKA block + 0x1 + + + + + SAESRST + SAES block reset + + 20 + 1 + read-write + + + B_0x0 + does not reset SAES block (default after reset) + 0x0 + + + B_0x1 + resets SAES block + 0x1 + + + + + + + RCC_AHB4RSTR + RCC_AHB4RSTR + RCC AHB4 peripheral reset register + 0x06C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OTFDEC1RST + OTFDEC1 block reset + + 7 + 1 + read-write + + + B_0x0 + does not reset OTFDEC1 block (default after reset) + 0x0 + + + B_0x1 + resets OTFDEC1 block + 0x1 + + + + + SDMMC1RST + SDMMC1 and SDMMC1 delay blocks reset + + 11 + 1 + read-write + + + B_0x0 + does not reset SDMMC1 and SDMMC1 delay blocks (default after reset) + 0x0 + + + B_0x1 + resets SDMMC1 and SDMMC1 delay blocks + 0x1 + + + + + FMCRST + FMC block reset + + 16 + 1 + read-write + + + B_0x0 + does not reset FMC block (default after reset) + 0x0 + + + B_0x1 + resets FMC block + 0x1 + + + + + OCTOSPI1RST + OCTOSPI1 block reset + + 20 + 1 + read-write + + + B_0x0 + does not reset OCTOSPI1 block (default after reset) + 0x0 + + + B_0x1 + resets OCTOSPI1 block + 0x1 + + + + + + + RCC_APB1LRSTR + RCC_APB1LRSTR + RCC APB1 peripheral low reset register + 0x074 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TIM2RST + TIM2 block reset + + 0 + 1 + read-write + + + B_0x0 + does not reset the TIM2 block (default after reset) + 0x0 + + + B_0x1 + resets the TIM2 block + 0x1 + + + + + TIM3RST + TIM3 block reset + + 1 + 1 + read-write + + + B_0x0 + does not reset the TIM3 block (default after reset) + 0x0 + + + B_0x1 + resets the TIM3 block + 0x1 + + + + + TIM4RST + TIM4 block reset + + 2 + 1 + read-write + + + B_0x0 + does not reset the TIM4 block (default after reset) + 0x0 + + + B_0x1 + resets the TIM4 block + 0x1 + + + + + TIM5RST + TIM5 block reset + + 3 + 1 + read-write + + + B_0x0 + does not reset the TIM5 block (default after reset) + 0x0 + + + B_0x1 + resets the TIM5 block + 0x1 + + + + + TIM6RST + TIM6 block reset + + 4 + 1 + read-write + + + B_0x0 + does not reset the TIM6 block (default after reset) + 0x0 + + + B_0x1 + resets the TIM6 block + 0x1 + + + + + TIM7RST + TIM7 block reset + + 5 + 1 + read-write + + + B_0x0 + does not reset the TIM7 block (default after reset) + 0x0 + + + B_0x1 + resets the TIM7 block + 0x1 + + + + + TIM12RST + TIM12 block reset + + 6 + 1 + read-write + + + B_0x0 + does not reset the TIM12 block (default after reset) + 0x0 + + + B_0x1 + resets the TIM12 block + 0x1 + + + + + SPI2RST + SPI2 block reset + + 14 + 1 + read-write + + + B_0x0 + does not reset the SPI2 block (default after reset) + 0x0 + + + B_0x1 + resets the SPI2 block + 0x1 + + + + + SPI3RST + SPI3 block reset + + 15 + 1 + read-write + + + B_0x0 + does not reset the SPI3 block (default after reset) + 0x0 + + + B_0x1 + resets the SPI3 block + 0x1 + + + + + USART2RST + USART2 block reset + + 17 + 1 + read-write + + + B_0x0 + does not reset the USART2 block (default after reset) + 0x0 + + + B_0x1 + resets the USART2 block + 0x1 + + + + + USART3RST + USART3 block reset + + 18 + 1 + read-write + + + B_0x0 + does not reset the USART3 block (default after reset) + 0x0 + + + B_0x1 + resets the USART3 block + 0x1 + + + + + UART4RST + UART4 block reset + + 19 + 1 + read-write + + + B_0x0 + does not reset the UART4 block (default after reset) + 0x0 + + + B_0x1 + resets the UART4 block + 0x1 + + + + + UART5RST + UART5 block reset + + 20 + 1 + read-write + + + B_0x0 + does not reset the UART5 block (default after reset) + 0x0 + + + B_0x1 + resets the UART5 block + 0x1 + + + + + I2C1RST + I2C1 block reset + + 21 + 1 + read-write + + + B_0x0 + does not reset the I2C1 block (default after reset) + 0x0 + + + B_0x1 + resets the I2C1 block + 0x1 + + + + + I2C2RST + I2C2 block reset + + 22 + 1 + read-write + + + B_0x0 + does not reset the I2C2 block (default after reset) + 0x0 + + + B_0x1 + resets the I2C2 block + 0x1 + + + + + I3C1RST + I3C1 block reset + + 23 + 1 + read-write + + + B_0x0 + does not reset the I3C1 block (default after reset) + 0x0 + + + B_0x1 + resets the I3C1 block + 0x1 + + + + + CRSRST + CRS block reset + + 24 + 1 + read-write + + + B_0x0 + does not reset the CRS block (default after reset) + 0x0 + + + B_0x1 + resets the CRS block + 0x1 + + + + + USART6RST + USART6 block reset + + 25 + 1 + read-write + + + B_0x0 + does not reset the USART6 block (default after reset) + 0x0 + + + B_0x1 + resets the USART6 block + 0x1 + + + + + USART10RST + USART10 block reset + + 26 + 1 + read-write + + + B_0x0 + does not reset the USART10 block (default after reset) + 0x0 + + + B_0x1 + resets the USART10 block + 0x1 + + + + + USART11RST + USART11 block reset + + 27 + 1 + read-write + + + B_0x0 + does not reset the USART11 block (default after reset) + 0x0 + + + B_0x1 + resets the USART11 block + 0x1 + + + + + CECRST + HDMI-CEC block reset + + 28 + 1 + read-write + + + B_0x0 + does not reset the HDMI-CEC block (default after reset) + 0x0 + + + B_0x1 + resets the HDMI-CEC block + 0x1 + + + + + UART7RST + UART7 block reset + + 30 + 1 + read-write + + + B_0x0 + does not reset the UART7 block (default after reset) + 0x0 + + + B_0x1 + resets the UART7 block + 0x1 + + + + + UART8RST + UART8 block reset + + 31 + 1 + read-write + + + B_0x0 + does not reset the UART8 block (default after reset) + 0x0 + + + B_0x1 + resets the UART8 block + 0x1 + + + + + + + RCC_APB1HRSTR + RCC_APB1HRSTR + RCC APB1 peripheral high reset register + 0x078 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UART9RST + UART9 block reset + + 0 + 1 + read-write + + + B_0x0 + does not reset UART9 block (default after reset) + 0x0 + + + B_0x1 + resets UART9 block + 0x1 + + + + + UART12RST + UART12 block reset + + 1 + 1 + read-write + + + B_0x0 + does not reset the UART12 block (default after reset) + 0x0 + + + B_0x1 + resets the UART12 block + 0x1 + + + + + DTSRST + DTS block reset + + 3 + 1 + read-write + + + B_0x0 + does not reset the DTS block (default after reset) + 0x0 + + + B_0x1 + resets the DTS block + 0x1 + + + + + LPTIM2RST + LPTIM2 block reset + + 5 + 1 + read-write + + + B_0x0 + does not reset the LPTIM2 block (default after reset) + 0x0 + + + B_0x1 + resets the LPTIM2 block + 0x1 + + + + + FDCANRST + FDCAN1 and FDCAN2 blocks reset + + 9 + 1 + read-write + + + B_0x0 + does not reset the FDCAN1 and FDCAN2 blocks (default after reset) + 0x0 + + + B_0x1 + resets the FDCAN1 and FDCAN2 blocks + 0x1 + + + + + UCPD1RST + UCPD1 block reset + + 23 + 1 + read-write + + + B_0x0 + does not reset the UCPD block (default after reset) + 0x0 + + + B_0x1 + resets the UCPD block + 0x1 + + + + + + + RCC_APB2RSTR + RCC_APB2RSTR + RCC APB2 peripheral reset register + 0x07C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TIM1RST + TIM1 block reset + + 11 + 1 + read-write + + + B_0x0 + does not reset the TIM1 block (default after reset) + 0x0 + + + B_0x1 + resets the TIM1 block + 0x1 + + + + + SPI1RST + SPI1 block reset + + 12 + 1 + read-write + + + B_0x0 + does not reset the SPI1 block (default after reset) + 0x0 + + + B_0x1 + resets the SPI1 block + 0x1 + + + + + TIM8RST + TIM8 block reset + + 13 + 1 + read-write + + + B_0x0 + does not reset the TIM8 block (default after reset) + 0x0 + + + B_0x1 + resets the TIM8 block + 0x1 + + + + + USART1RST + USART1 block reset + + 14 + 1 + read-write + + + B_0x0 + does not reset the USART1 block (default after reset) + 0x0 + + + B_0x1 + resets the USART1 block + 0x1 + + + + + TIM15RST + TIM15 block reset + + 16 + 1 + read-write + + + B_0x0 + does not reset the TIM15 block (default after reset) + 0x0 + + + B_0x1 + resets the TIM15 block + 0x1 + + + + + SPI4RST + SPI4 block reset + + 19 + 1 + read-write + + + B_0x0 + does not reset the SPI4 block (default after reset) + 0x0 + + + B_0x1 + resets the SPI4 block + 0x1 + + + + + SPI6RST + SPI6 block reset + + 20 + 1 + read-write + + + B_0x0 + does not reset the SPI6 block (default after reset) + 0x0 + + + B_0x1 + resets the SPI6 block + 0x1 + + + + + SAI1RST + SAI1 block reset + + 21 + 1 + read-write + + + B_0x0 + does not reset the SAI1 (default after reset) + 0x0 + + + B_0x1 + resets the SAI1 + 0x1 + + + + + SAI2RST + SAI2 block reset + + 22 + 1 + read-write + + + B_0x0 + does not reset the SAI2 block (default after reset) + 0x0 + + + B_0x1 + resets the SAI2 block + 0x1 + + + + + USBRST + USB block reset + + 24 + 1 + read-write + + + B_0x0 + does not reset the USB block (default after reset) + 0x0 + + + B_0x1 + resets the USB block + 0x1 + + + + + + + RCC_APB3RSTR + RCC_APB3RSTR + RCC APB3 peripheral reset register + 0x080 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LPUART1RST + LPUART1 block reset + + 6 + 1 + read-write + + + B_0x0 + does not reset the LPUART1 block (default after reset) + 0x0 + + + B_0x1 + resets the LPUART1 block + 0x1 + + + + + I2C3RST + I2C3 block reset + + 7 + 1 + read-write + + + B_0x0 + does not reset the I2C3 block (default after reset) + 0x0 + + + B_0x1 + resets the I2C3 block + 0x1 + + + + + I3C2RST + I3C2 block reset + + 9 + 1 + read-write + + + B_0x0 + does not reset the I3C2 block (default after reset) + 0x0 + + + B_0x1 + resets the I3C2 block + 0x1 + + + + + LPTIM1RST + LPTIM1 block reset + + 11 + 1 + read-write + + + B_0x0 + does not reset the LPTIM1 block (default after reset) + 0x0 + + + B_0x1 + resets the LPTIM1 block + 0x1 + + + + + LPTIM3RST + LPTIM3 block reset + + 12 + 1 + read-write + + + B_0x0 + does not reset the LPTIM3 block (default after reset) + 0x0 + + + B_0x1 + resets the LPTIM3 block + 0x1 + + + + + LPTIM4RST + LPTIM4 block reset + + 13 + 1 + read-write + + + B_0x0 + does not reset the LPTIM4 block (default after reset) + 0x0 + + + B_0x1 + resets the LPTIM4 block + 0x1 + + + + + LPTIM5RST + LPTIM5 block reset + + 14 + 1 + read-write + + + B_0x0 + does not reset the LPTIM5 block (default after reset) + 0x0 + + + B_0x1 + resets the LPTIM5 block + 0x1 + + + + + LPTIM6RST + LPTIM6 block reset + + 15 + 1 + read-write + + + B_0x0 + does not reset the LPTIM6 block (default after reset) + 0x0 + + + B_0x1 + resets the LPTIM6 block + 0x1 + + + + + VREFRST + VREFBUF block reset + + 20 + 1 + read-write + + + B_0x0 + does not reset the VREFBUF block (default after reset) + 0x0 + + + B_0x1 + resets the VREFBUF block + 0x1 + + + + + + + RCC_AHB1ENR + RCC_AHB1ENR + RCC AHB1 peripherals clock register + 0x088 + 0x20 + read-write + 0xD0000100 + 0xFFFFFFFF + + + GPDMA1EN + GPDMA1 clock enable + + 0 + 1 + read-write + + + B_0x0 + GPDMA1 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + GPDMA1 peripheral clock enabled + 0x1 + + + + + GPDMA2EN + GPDMA2 clock enable + + 1 + 1 + read-write + + + B_0x0 + GPDMA2 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + GPDMA2 peripheral clock enabled + 0x1 + + + + + FLITFEN + Flash interface clock enable + + 8 + 1 + read-write + + + B_0x0 + FLASH interface clock disabled + 0x0 + + + B_0x1 + FLASH interface clock enabled (default after reset) + 0x1 + + + + + CRCEN + CRC clock enable + + 12 + 1 + read-write + + + B_0x0 + CRC peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + CRC peripheral clock enabled + 0x1 + + + + + CORDICEN + CORDIC clock enable + + 14 + 1 + read-write + + + B_0x0 + CORDIC peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + CORDIC peripheral clock enabled + 0x1 + + + + + FMACEN + FMAC clock enable + + 15 + 1 + read-write + + + B_0x0 + FMAC peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + FMAC peripheral clock enabled + 0x1 + + + + + RAMCFGEN + RAMCFG clock enable + + 17 + 1 + read-write + + + B_0x0 + RAMCFG peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + RAMCFG peripheral clock enabled + 0x1 + + + + + ETHEN + ETH clock enable + + 19 + 1 + read-write + + + B_0x0 + ETH peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + ETH peripheral clock enabled + 0x1 + + + + + ETHTXEN + ETHTX clock enable + + 20 + 1 + read-write + + + B_0x0 + ETHTX clock disabled (default after reset) + 0x0 + + + B_0x1 + ETHTX clock enabled + 0x1 + + + + + ETHRXEN + ETHRX clock enable + + 21 + 1 + read-write + + + B_0x0 + ETHRX clock disabled (default after reset) + 0x0 + + + B_0x1 + ETHRX clock enabled + 0x1 + + + + + TZSC1EN + TZSC1 clock enable + + 24 + 1 + read-write + + + B_0x0 + TZSC1 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + TZSC1 peripheral clock enabled + 0x1 + + + + + BKPRAMEN + BKPRAM clock enable + + 28 + 1 + read-write + + + B_0x0 + BKPRAM peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + BKPRAM peripheral clock enabled + 0x1 + + + + + DCACHEEN + DCACHE clock enable + + 30 + 1 + read-write + + + B_0x0 + DCACHE peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + DCACHE peripheral clock enabled + 0x1 + + + + + SRAM1EN + SRAM1 clock enable + + 31 + 1 + read-write + + + B_0x0 + SRAM1 clock disabled + 0x0 + + + B_0x1 + SRAM1 clock enabled (default after reset) + 0x1 + + + + + + + RCC_AHB2ENR + RCC_AHB2ENR + RCC AHB2 peripheral clock register + 0x08C + 0x20 + read-write + 0xC0000000 + 0xFFFFFFFF + + + GPIOAEN + GPIOA clock enable + + 0 + 1 + read-write + + + B_0x0 + GPIOA peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + GPIOA peripheral clock enabled + 0x1 + + + + + GPIOBEN + GPIOB clock enable + + 1 + 1 + read-write + + + B_0x0 + GPIOB peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + GPIOB peripheral clock enabled + 0x1 + + + + + GPIOCEN + GPIOC clock enable + + 2 + 1 + read-write + + + B_0x0 + GPIOC peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + GPIOC peripheral clock enabled + 0x1 + + + + + GPIODEN + GPIOD clock enable + + 3 + 1 + read-write + + + B_0x0 + GPIOD peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + GPIOD peripheral clock enabled + 0x1 + + + + + GPIOEEN + GPIOE clock enable + + 4 + 1 + read-write + + + B_0x0 + GPIOE peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + GPIOE peripheral clock enabled + 0x1 + + + + + GPIOFEN + GPIOF clock enable + + 5 + 1 + read-write + + + B_0x0 + GPIOF peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + GPIOF peripheral clock enabled + 0x1 + + + + + GPIOGEN + GPIOG clock enable + + 6 + 1 + read-write + + + B_0x0 + GPIOG peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + GPIOG peripheral clock enabled + 0x1 + + + + + GPIOHEN + GPIOH clock enable + + 7 + 1 + read-write + + + B_0x0 + GPIOH peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + GPIOH peripheral clock enabled + 0x1 + + + + + GPIOIEN + GPIOI clock enable + + 8 + 1 + read-write + + + B_0x0 + GPIOI peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + GPIOI peripheral clock enabled + 0x1 + + + + + ADCEN + ADC1 and 2 peripherals clock enable + + 10 + 1 + read-write + + + B_0x0 + ADC1 and 2 peripherals clock disabled (default after reset) + 0x0 + + + B_0x1 + ADC1 and 2 peripherals clock enabled + 0x1 + + + + + DAC1EN + DAC clock enable + + 11 + 1 + read-write + + + B_0x0 + DAC peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + DAC peripheral clock enabled + 0x1 + + + + + DCMI_PSSIEN + digital camera interface clock enable (DCMI or PSSI depending which interface is active) + + 12 + 1 + read-write + + + B_0x0 + DCMI/PSSI peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + DCMI/PSSI peripheral clock enabled + 0x1 + + + + + AESEN + AES clock enable + + 16 + 1 + read-write + + + B_0x0 + AES peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + AES peripheral clock enabled + 0x1 + + + + + HASHEN + HASH clock enable + + 17 + 1 + read-write + + + B_0x0 + HASH peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + HASH peripheral clock enabled + 0x1 + + + + + RNGEN + RNG clock enable + + 18 + 1 + read-write + + + B_0x0 + RNG peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + RNG peripheral clock enabled + 0x1 + + + + + PKAEN + PKA clock enable + + 19 + 1 + read-write + + + B_0x0 + PKA peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + PKA peripheral clock enabled + 0x1 + + + + + SAESEN + SAES clock enable + + 20 + 1 + read-write + + + B_0x0 + SAES peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + SAES peripheral clock enabled + 0x1 + + + + + SRAM2EN + SRAM2 clock enable + + 30 + 1 + read-write + + + B_0x0 + SRAM2 clock disabled + 0x0 + + + B_0x1 + SRAM2 clock enabled (default after reset) + 0x1 + + + + + SRAM3EN + SRAM3 clock enable + + 31 + 1 + read-write + + + B_0x0 + SRAM3 clock disabled + 0x0 + + + B_0x1 + SRAM3 clock enabled (default after reset) + 0x1 + + + + + + + RCC_AHB4ENR + RCC_AHB4ENR + RCC AHB4 peripheral clock register + 0x094 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OTFDEC1EN + OTFDEC1 clock enable + + 7 + 1 + read-write + + + B_0x0 + OTFDEC1 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + OTFDEC1 peripheral clock enabled + 0x1 + + + + + SDMMC1EN + SDMMC1 and SDMMC1 delay peripheral clock enable reset + 11 + 1 + read-write + + + B_0x0 + SDMMC1 and SDMMC1 delay peripherals clock disabled (default after reset) + 0x0 + + + B_0x1 + SDMMC1 and SDMMC1 delay peripherals clock enabled + 0x1 + + + + + FMCEN + FMC clock enable + + 16 + 1 + read-write + + + B_0x0 + FMC peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + FMC peripheral clock enabled + 0x1 + + + + + OCTOSPI1EN + OCTOSPI1 clock enable + + 20 + 1 + read-write + + + B_0x0 + OCTOSPI1 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + OCTOSPI1 peripheral clock enabled + 0x1 + + + + + + + RCC_APB1LENR + RCC_APB1LENR + RCC APB1 peripheral clock register + 0x09C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TIM2EN + TIM2 clock enable + + 0 + 1 + read-write + + + B_0x0 + TIM2 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + TIM2 peripheral clock enabled + 0x1 + + + + + TIM3EN + TIM3 clock enable + + 1 + 1 + read-write + + + B_0x0 + TIM3 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + TIM3 peripheral clock enabled + 0x1 + + + + + TIM4EN + TIM4 clock enable + + 2 + 1 + read-write + + + B_0x0 + TIM4 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + TIM4 peripheral clock enabled + 0x1 + + + + + TIM5EN + TIM5 clock enable + + 3 + 1 + read-write + + + B_0x0 + TIM5 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + TIM5 peripheral clock enabled + 0x1 + + + + + TIM6EN + TIM6 clock enable + + 4 + 1 + read-write + + + B_0x0 + TIM6 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + TIM6 peripheral clock enabled + 0x1 + + + + + TIM7EN + TIM7 clock enable + + 5 + 1 + read-write + + + B_0x0 + TIM7 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + TIM7 peripheral clock enabled + 0x1 + + + + + TIM12EN + TIM12 clock enable + + 6 + 1 + read-write + + + B_0x0 + TIM12 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + TIM12 peripheral clock enabled + 0x1 + + + + + WWDGEN + WWDG clock enable + + 11 + 1 + read-write + + + B_0x0 + WWDG peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + WWDG peripheral clock enabled + 0x1 + + + + + SPI2EN + SPI2 clock enable + + 14 + 1 + read-write + + + B_0x0 + SPI2 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + SPI2 peripheral clock enabled + 0x1 + + + + + SPI3EN + SPI3 clock enable + + 15 + 1 + read-write + + + B_0x0 + SPI3 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + SPI3 peripheral clock enabled + 0x1 + + + + + USART2EN + USART2 clock enable + + 17 + 1 + read-write + + + B_0x0 + USART2 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + USART2 peripheral clock enabled + 0x1 + + + + + USART3EN + USART3 clock enable + + 18 + 1 + read-write + + + B_0x0 + USART3 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + USART3 peripheral clock enabled + 0x1 + + + + + UART4EN + UART4 clock enable + + 19 + 1 + read-write + + + B_0x0 + UART4 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + UART4 peripheral clock enabled + 0x1 + + + + + UART5EN + UART5 clock enable + + 20 + 1 + read-write + + + B_0x0 + UART5 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + UART5 peripheral clock enabled + 0x1 + + + + + I2C1EN + I2C1 clock enable + + 21 + 1 + read-write + + + B_0x0 + I2C1 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + I2C1 peripheral clock enabled + 0x1 + + + + + I2C2EN + I2C2 clock enable + + 22 + 1 + read-write + + + B_0x0 + I2C2 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + I2C2 peripheral clock enabled + 0x1 + + + + + I3C1EN + I3C1 clock enable + + 23 + 1 + read-write + + + B_0x0 + I3C1 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + I3C1 peripheral clock enabled + 0x1 + + + + + CRSEN + CRS clock enable + + 24 + 1 + read-write + + + B_0x0 + CRS peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + CRS peripheral clock enabled + 0x1 + + + + + USART6EN + USART6 clock enable + + 25 + 1 + read-write + + + B_0x0 + USART6 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + USART6 peripheral clock enabled + 0x1 + + + + + USART10EN + USART10 clock enable + + 26 + 1 + read-write + + + B_0x0 + USART10 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + USART10 peripheral clock enabled + 0x1 + + + + + USART11EN + USART11 clock enable + + 27 + 1 + read-write + + + B_0x0 + USART11 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + USART11 peripheral clock enabled + 0x1 + + + + + CECEN + HDMI-CEC clock enable + + 28 + 1 + read-write + + + B_0x0 + HDMI-CEC peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + HDMI-CEC peripheral clock enabled + 0x1 + + + + + UART7EN + UART7 clock enable + + 30 + 1 + read-write + + + B_0x0 + UART7 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + UART7 peripheral clock enabled + 0x1 + + + + + UART8EN + UART8 clock enable + + 31 + 1 + read-write + + + B_0x0 + UART8 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + UART8 peripheral clock enabled + 0x1 + + + + + + + RCC_APB1HENR + RCC_APB1HENR + RCC APB1 peripheral clock register + 0x0A0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UART9EN + UART9 clock enable + + 0 + 1 + read-write + + + B_0x0 + UART9 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + resets UART9 peripheral clock enabled + 0x1 + + + + + UART12EN + UART12 clock enable + + 1 + 1 + read-write + + + B_0x0 + UART12 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + UART12 peripheral clock enabled + 0x1 + + + + + DTSEN + DTS clock enable + + 3 + 1 + read-write + + + B_0x0 + DTS peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + DTS peripheral clock enabled + 0x1 + + + + + LPTIM2EN + LPTIM2 clock enable + + 5 + 1 + read-write + + + B_0x0 + LPTIM2 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + LPTIM2 peripheral clock enabled + 0x1 + + + + + FDCANEN + FDCAN1 and FDCAN2 peripheral clock enable + + 9 + 1 + read-write + + + B_0x0 + FDCAN1 and FDCAN2 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + FDCAN1 and FDCAN2 peripheral clock enabled + 0x1 + + + + + UCPD1EN + UCPD1 clock enable + + 23 + 1 + read-write + + + B_0x0 + UCPD peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + UCPD peripheral clock enabled + 0x1 + + + + + + + RCC_APB2ENR + RCC_APB2ENR + RCC APB2 peripheral clock register + 0x0A4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TIM1EN + TIM1 clock enable + + 11 + 1 + read-write + + + B_0x0 + TIM1 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + TIM1 peripheral clock enabled + 0x1 + + + + + SPI1EN + SPI1 clock enable + + 12 + 1 + read-write + + + B_0x0 + SPI1 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + SPI1 peripheral clock enabled + 0x1 + + + + + TIM8EN + TIM8 clock enable + + 13 + 1 + read-write + + + B_0x0 + TIM8 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + TIM8 peripheral clock enabled + 0x1 + + + + + USART1EN + USART1 clock enable + + 14 + 1 + read-write + + + B_0x0 + USART1 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + USART1 peripheral clock enabled + 0x1 + + + + + TIM15EN + TIM15 clock enable + + 16 + 1 + read-write + + + B_0x0 + TIM15 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + TIM15 peripheral clock enabled + 0x1 + + + + + SPI4EN + SPI4 clock enable + + 19 + 1 + read-write + + + B_0x0 + SPI4 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + SPI4 peripheral clock enabled + 0x1 + + + + + SPI6EN + SPI6 clock enable + + 20 + 1 + read-write + + + B_0x0 + SPI6 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + SPI6 peripheral clock enabled + 0x1 + + + + + SAI1EN + SAI1 clock enable + + 21 + 1 + read-write + + + B_0x0 + SAI1 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + SAI1 peripheral clock enabled + 0x1 + + + + + SAI2EN + SAI2 clock enable + + 22 + 1 + read-write + + + B_0x0 + SAI2 clock disabled + 0x0 + + + B_0x1 + SAI2 clock enabled + 0x1 + + + + + USBEN + USB clock enable + + 24 + 1 + read-write + + + B_0x0 + USB peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + USB peripheral clock enabled + 0x1 + + + + + + + RCC_APB3ENR + RCC_APB3ENR + RCC APB3 peripheral clock register + 0x0A8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SBSEN + SBS clock enable + + 1 + 1 + read-write + + + B_0x0 + SBS peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + SBS peripheral clock enabled + 0x1 + + + + + LPUART1EN + LPUART1 clock enable + + 6 + 1 + read-write + + + B_0x0 + LPUART1 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + LPUART1 peripheral clock enabled + 0x1 + + + + + I2C3EN + I2C3 clock enable + + 7 + 1 + read-write + + + B_0x0 + I2C3 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + I2C3 peripheral clock enabled + 0x1 + + + + + I3C2EN + I3C2 clock enable + + 9 + 1 + read-write + + + B_0x0 + I3C2 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + I3C2 peripheral clock enabled + 0x1 + + + + + LPTIM1EN + LPTIM1 clock enable + + 11 + 1 + read-write + + + B_0x0 + LPTIM1 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + LPTIM1 peripheral clock enabled + 0x1 + + + + + LPTIM3EN + LPTIM3 clock enable + + 12 + 1 + read-write + + + B_0x0 + LPTIM3 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + LPTIM3 peripheral clock enabled + 0x1 + + + + + LPTIM4EN + LPTIM4 clock enable + + 13 + 1 + read-write + + + B_0x0 + LPTIM4 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + LPTIM4 peripheral clock enabled + 0x1 + + + + + LPTIM5EN + LPTIM5 clock enable + + 14 + 1 + read-write + + + B_0x0 + LPTIM5 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + LPTIM5 peripheral clock enabled + 0x1 + + + + + LPTIM6EN + LPTIM6 clock enable + + 15 + 1 + read-write + + + B_0x0 + LPTIM6 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + LPTIM6 peripheral clock enabled + 0x1 + + + + + VREFBUFEN + VREFBUF clock enable + + 20 + 1 + read-write + + + B_0x0 + VREFBUF peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + VREFBUF peripheral clock enabled + 0x1 + + + + + RTCAPBEN + RTC APB interface clock enable + + 21 + 1 + read-write + + + B_0x0 + RTC APB interface clock disabled (default after reset) + 0x0 + + + B_0x1 + RTC APB interface clock enabled + 0x1 + + + + + + + RCC_AHB1LPENR + RCC_AHB1LPENR + RCC AHB1 sleep clock register + 0x0B0 + 0x20 + read-write + 0xF1021103 + 0xFFFFFFFF + + + GPDMA1LPEN + GPDMA1 clock enable during Sleep mode + + 0 + 1 + read-write + + + B_0x0 + GPDMA1 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + GPDMA1 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + GPDMA2LPEN + GPDMA2 clock enable during Sleep mode + + 1 + 1 + read-write + + + B_0x0 + GPDMA2 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + GPDMA2 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + FLITFLPEN + Flash interface (FLITF) clock enable during Sleep mode + + 8 + 1 + read-write + + + B_0x0 + FLITF peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + FLITF peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + CRCLPEN + CRC clock enable during Sleep mode + + 12 + 1 + read-write + + + B_0x0 + CRC peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + CRC peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + CORDICLPEN + CORDIC clock enable during Sleep mode + + 14 + 1 + read-write + + + B_0x0 + CORDIC peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + CORDIC peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + FMACLPEN + FMAC clock enable during Sleep mode + + 15 + 1 + read-write + + + B_0x0 + FMAC peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + FMAC peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + RAMCFGLPEN + RAMCFG clock enable during Sleep mode + + 17 + 1 + read-write + + + B_0x0 + RAMCFG peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + RAMCFG peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + ETHLPEN + ETH clock enable during Sleep mode + + 19 + 1 + read-write + + + B_0x0 + ETH peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + ETH peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + ETHTXLPEN + ETHTX clock enable during Sleep mode + + 20 + 1 + read-write + + + B_0x0 + ETHTX clock disabled during Sleep mode + 0x0 + + + B_0x1 + ETHTX clock enabled during Sleep mode (default after reset) + 0x1 + + + + + ETHRXLPEN + ETHRX clock enable during Sleep mode + + 21 + 1 + read-write + + + B_0x0 + ETHRX clock disabled during Sleep mode + 0x0 + + + B_0x1 + ETHRX clock enabled during Sleep mode (default after reset) + 0x1 + + + + + TZSC1LPEN + TZSC1 clock enable during Sleep mode + + 24 + 1 + read-write + + + B_0x0 + TZSC1 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + TZSC1 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + BKPRAMLPEN + BKPRAM clock enable during Sleep mode + + 28 + 1 + read-write + + + B_0x0 + BKPRAM peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + BKPRAM peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + ICACHELPEN + ICACHE clock enable during Sleep mode + + 29 + 1 + read-write + + + B_0x0 + ICACHE peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + ICACHE peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + DCACHELPEN + DCACHE clock enable during Sleep mode + + 30 + 1 + read-write + + + B_0x0 + DCACHE peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + DCACHE peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + SRAM1LPEN + SRAM1 clock enable during Sleep mode + + 31 + 1 + read-write + + + B_0x0 + SRAM1 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + SRAM1 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + + + RCC_AHB2LPENR + RCC_AHB2LPENR + RCC AHB2 sleep clock register + 0x0B4 + 0x20 + read-write + 0xC01F1CFF + 0xFFFFFFFF + + + GPIOALPEN + GPIOA clock enable during Sleep mode + + 0 + 1 + read-write + + + B_0x0 + GPIOA peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + GPIOA peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + GPIOBLPEN + GPIOB clock enable during Sleep mode + + 1 + 1 + read-write + + + B_0x0 + GPIOB peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + GPIOB peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + GPIOCLPEN + GPIOC clock enable during Sleep mode + + 2 + 1 + read-write + + + B_0x0 + GPIOC peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + GPIOC peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + GPIODLPEN + GPIOD clock enable during Sleep mode + + 3 + 1 + read-write + + + B_0x0 + GPIOD peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + GPIOD peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + GPIOELPEN + GPIOE clock enable during Sleep mode + + 4 + 1 + read-write + + + B_0x0 + GPIOE peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + GPIOE peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + GPIOFLPEN + GPIOF clock enable during Sleep mode + + 5 + 1 + read-write + + + B_0x0 + GPIOF peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + GPIOF peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + GPIOGLPEN + GPIOG clock enable during Sleep mode + + 6 + 1 + read-write + + + B_0x0 + GPIOG peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + GPIOG peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + GPIOHLPEN + GPIOH clock enable during Sleep mode + + 7 + 1 + read-write + + + B_0x0 + GPIOH peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + GPIOH peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + GPIOILPEN + GPIOI clock enable during Sleep mode + + 8 + 1 + read-write + + + B_0x0 + GPIOI peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + GPIOI peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + ADCLPEN + ADC1 and 2 peripherals clock enable during Sleep mode + + 10 + 1 + read-write + + + B_0x0 + ADC1 and 2 peripherals clock disabled during Sleep mode + 0x0 + + + B_0x1 + ADC1 and 2 peripherals clock enabled during Sleep mode (default after reset) + 0x1 + + + + + DAC1LPEN + DAC clock enable during Sleep mode + + 11 + 1 + read-write + + + B_0x0 + DAC peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + DAC peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + DCMI_PSSILPEN + digital camera interface clock enable during Sleep mode (DCMI or PSSI depending which interface is active) + + 12 + 1 + read-write + + + B_0x0 + DCMI/PSSI peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + DCMI/PSSI peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + AESLPEN + AES clock enable during Sleep mode + + 16 + 1 + read-write + + + B_0x0 + AES peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + AES peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + HASHLPEN + HASH clock enable during Sleep mode + + 17 + 1 + read-write + + + B_0x0 + HASH peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + HASH peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + RNGLPEN + RNG clock enable during Sleep mode + + 18 + 1 + read-write + + + B_0x0 + RNG peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + RNG peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + PKALPEN + PKA clock enable during Sleep mode + + 19 + 1 + read-write + + + B_0x0 + PKA peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + PKA peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + SAESLPEN + SAES clock enable during Sleep mode + + 20 + 1 + read-write + + + B_0x0 + SAES peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + SAES peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + SRAM2LPEN + SRAM2 clock enable during Sleep mode + + 30 + 1 + read-write + + + B_0x0 + SRAM2 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + SRAM2 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + SRAM3LPEN + SRAM3 clock enable during Sleep mode + + 31 + 1 + read-write + + + B_0x0 + SRAM3 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + SRAM3 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + + + RCC_AHB4LPENR + RCC_AHB4LPENR + RCC AHB4 sleep clock register + 0x0BC + 0x20 + read-write + 0x00110880 + 0xFFFFFFFF + + + OTFDEC1LPEN + OTFDEC1 clock enable during Sleep mode + + 7 + 1 + read-write + + + B_0x0 + OTFDEC1 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + OTFDEC1 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + SDMMC1LPEN + SDMMC1 and SDMMC1 delay peripheral clock enable during Sleep mode + + 11 + 1 + read-write + + + B_0x0 + SDMMC1 and SDMMC1 delay peripherals clock disabled during Sleep mode + 0x0 + + + B_0x1 + SDMMC1 and SDMMC1 delay peripherals clock enabled during Sleep mode (default after reset) + 0x1 + + + + + FMCLPEN + FMC clock enable during Sleep mode + + 16 + 1 + read-write + + + B_0x0 + FMC peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + FMC peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + OCTOSPI1LPEN + OCTOSPI1 clock enable during Sleep mode + + 20 + 1 + read-write + + + B_0x0 + OCTOSPI1 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + OCTOSPI1 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + + + RCC_APB1LLPENR + RCC_APB1LLPENR + RCC APB1 sleep clock register + 0x0C4 + 0x20 + read-write + 0x13FEC87F + 0xFFFFFFFF + + + TIM2LPEN + TIM2 clock enable during Sleep mode + + 0 + 1 + read-write + + + B_0x0 + TIM2 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + TIM2 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + TIM3LPEN + TIM3 clock enable during Sleep mode + + 1 + 1 + read-write + + + B_0x0 + TIM3 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + TIM3 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + TIM4LPEN + TIM4 clock enable during Sleep mode + + 2 + 1 + read-write + + + B_0x0 + TIM4 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + TIM4 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + TIM5LPEN + TIM5 clock enable during Sleep mode + + 3 + 1 + read-write + + + B_0x0 + TIM5 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + TIM5 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + TIM6LPEN + TIM6 clock enable during Sleep mode + + 4 + 1 + read-write + + + B_0x0 + TIM6 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + TIM6 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + TIM7LPEN + TIM7 clock enable during Sleep mode + + 5 + 1 + read-write + + + B_0x0 + TIM7 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + TIM7 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + TIM12LPEN + TIM12 clock enable during Sleep mode + + 6 + 1 + read-write + + + B_0x0 + TIM12 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + TIM12 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + WWDGLPEN + WWDG clock enable during Sleep mode + + 11 + 1 + read-write + + + B_0x0 + WWDG peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + WWDG peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + SPI2LPEN + SPI2 clock enable during Sleep mode + + 14 + 1 + read-write + + + B_0x0 + SPI2 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + SPI2 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + SPI3LPEN + SPI3 clock enable during Sleep mode + + 15 + 1 + read-write + + + B_0x0 + SPI3 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + SPI3 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + USART2LPEN + USART2 clock enable during Sleep mode + + 17 + 1 + read-write + + + B_0x0 + USART2 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + USART2 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + USART3LPEN + USART3 clock enable during Sleep mode + + 18 + 1 + read-write + + + B_0x0 + USART3 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + USART3 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + UART4LPEN + UART4 clock enable during Sleep mode + + 19 + 1 + read-write + + + B_0x0 + UART4 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + UART4 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + UART5LPEN + UART5 clock enable during Sleep mode + + 20 + 1 + read-write + + + B_0x0 + UART5 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + UART5 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + I2C1LPEN + I2C1 clock enable during Sleep mode + + 21 + 1 + read-write + + + B_0x0 + I2C1 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + I2C1 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + I2C2LPEN + I2C2 clock enable during Sleep mode + + 22 + 1 + read-write + + + B_0x0 + I2C2 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + I2C2 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + I3C1LPEN + I3C1 clock enable during Sleep mode + + 23 + 1 + read-write + + + B_0x0 + I3C1 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + I3C1 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + CRSLPEN + CRS clock enable during Sleep mode + + 24 + 1 + read-write + + + B_0x0 + CRS peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + CRS peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + USART6LPEN + USART6 clock enable during Sleep mode + + 25 + 1 + read-write + + + B_0x0 + USART6 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + USART6 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + USART10LPEN + USART10 clock enable during Sleep mode + + 26 + 1 + read-write + + + B_0x0 + USART10 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + USART10 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + USART11LPEN + USART11 clock enable during Sleep mode + + 27 + 1 + read-write + + + B_0x0 + USART11 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + USART11 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + CECLPEN + HDMI-CEC clock enable during Sleep mode + + 28 + 1 + read-write + + + B_0x0 + HDMI-CEC peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + HDMI-CEC peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + UART7LPEN + UART7 clock enable during Sleep mode + + 30 + 1 + read-write + + + B_0x0 + UART7 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + UART7 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + UART8LPEN + UART8 clock enable during Sleep mode + + 31 + 1 + read-write + + + B_0x0 + UART8 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + UART8 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + + + RCC_APB1HLPENR + RCC_APB1HLPENR + RCC APB1 sleep clock register + 0x0C8 + 0x20 + read-write + 0x40800228 + 0xFFFFFFFF + + + UART9LPEN + UART9 clock enable during Sleep mode + + 0 + 1 + read-write + + + B_0x0 + UART9 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + resets UART9 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + UART12LPEN + UART12 clock enable during Sleep mode + + 1 + 1 + read-write + + + B_0x0 + UART12 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + UART12 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + DTSLPEN + DTS clock enable during Sleep mode + + 3 + 1 + read-write + + + B_0x0 + DTS peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + DTS peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + LPTIM2LPEN + LPTIM2 clock enable during Sleep mode + + 5 + 1 + read-write + + + B_0x0 + LPTIM2 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + LPTIM2 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + FDCANLPEN + FDCAN1 and FDCAN2 peripheral clock enable during Sleep mode + + 9 + 1 + read-write + + + B_0x0 + FDCAN1 and FDCAN2 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + FDCAN1 and FDCAN2 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + UCPD1LPEN + UCPD1 clock enable during Sleep mode + + 23 + 1 + read-write + + + B_0x0 + UCPD peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + UCPD peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + + + RCC_APB2LPENR + RCC_APB2LPENR + RCC APB2 sleep clock register + 0x0CC + 0x20 + read-write + 0x01097800 + 0xFFFFFFFF + + + TIM1LPEN + TIM1 clock enable during Sleep mode + + 11 + 1 + read-write + + + B_0x0 + TIM1 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + TIM1 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + SPI1LPEN + SPI1 clock enable during Sleep mode + + 12 + 1 + read-write + + + B_0x0 + SPI1 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + SPI1 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + TIM8LPEN + TIM8 clock enable during Sleep mode + + 13 + 1 + read-write + + + B_0x0 + TIM8 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + TIM8 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + USART1LPEN + USART1 clock enable during Sleep mode + + 14 + 1 + read-write + + + B_0x0 + USART1 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + USART1 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + TIM15LPEN + TIM15 clock enable during Sleep mode + + 16 + 1 + read-write + + + B_0x0 + TIM15 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + TIM15 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + SPI4LPEN + SPI4 clock enable during Sleep mode + + 19 + 1 + read-write + + + B_0x0 + SPI4 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + SPI4 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + SPI6LPEN + SPI6 clock enable during Sleep mode + + 20 + 1 + read-write + + + B_0x0 + SPI6 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + SPI6 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + SAI1LPEN + SAI1 clock enable during Sleep mode + + 21 + 1 + read-write + + + B_0x0 + SAI1 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + SAI1 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + SAI2LPEN + SAI2 clock enable during Sleep mode + + 22 + 1 + read-write + + + B_0x0 + SAI2 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + SAI2 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + USBLPEN + USB clock enable during Sleep mode + + 24 + 1 + read-write + + + B_0x0 + USB peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + USB peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + + + RCC_APB3LPENR + RCC_APB3LPENR + RCC APB3 sleep clock register + 0x0D0 + 0x20 + read-write + 0x0030FAE2 + 0xFFFFFFFF + + + SBSLPEN + SBS clock enable during Sleep mode + + 1 + 1 + read-write + + + B_0x0 + SBS peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + SBS peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + LPUART1LPEN + LPUART1 clock enable during Sleep mode + + 6 + 1 + read-write + + + B_0x0 + LPUART1 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + LPUART1 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + I2C3LPEN + I2C3 clock enable during Sleep mode + + 7 + 1 + read-write + + + B_0x0 + I2C3 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + I2C3 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + I3C2LPEN + I3C2 clock enable during Sleep mode + + 9 + 1 + read-write + + + B_0x0 + I3C2 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + I3C2 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + LPTIM1LPEN + LPTIM1 clock enable during Sleep mode + + 11 + 1 + read-write + + + B_0x0 + LPTIM1 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + LPTIM1 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + LPTIM3LPEN + LPTIM3 clock enable during Sleep mode + + 12 + 1 + read-write + + + B_0x0 + LPTIM3 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + LPTIM3 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + LPTIM4LPEN + LPTIM4 clock enable during Sleep mode + + 13 + 1 + read-write + + + B_0x0 + LPTIM4 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + LPTIM4 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + LPTIM5LPEN + LPTIM5 clock enable during Sleep mode + + 14 + 1 + read-write + + + B_0x0 + LPTIM5 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + LPTIM5 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + LPTIM6LPEN + LPTIM6 clock enable during Sleep mode + + 15 + 1 + read-write + + + B_0x0 + LPTIM6 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + LPTIM6 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + VREFLPEN + VREFBUF clock enable during Sleep mode + + 20 + 1 + read-write + + + B_0x0 + VREFBUF peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + VREFBUF peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + RTCAPBLPEN + RTC APB interface clock enable during Sleep mode + + 21 + 1 + read-write + + + B_0x0 + RTC APB interface clock disabled during Sleep mode + 0x0 + + + B_0x1 + RTC APB interface clock enabled during Sleep mode (default after reset) + 0x1 + + + + + + + RCC_CCIPR1 + RCC_CCIPR1 + RCC kernel clock configuration register + 0x0D8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + USART1SEL + USART1 kernel clock source selection + + 0 + 3 + read-write + + + B_0x0 + rcc_pclk2 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_q_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_q_ck selected as kernel clock + 0x2 + + + B_0x3 + hsi_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + csi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + lse_ck selected as kernel clock + 0x5 + + + + + USART2SEL + USART2 kernel clock source selection + + 3 + 3 + read-write + + + B_0x0 + rcc_pclk1 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_q_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_q_ck selected as kernel clock + 0x2 + + + B_0x3 + hsi_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + csi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + lse_ck selected as kernel clock + 0x5 + + + + + USART3SEL + USART3 kernel clock source selection + + 6 + 3 + read-write + + + B_0x0 + rcc_pclk1 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_q_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_q_ck selected as kernel clock + 0x2 + + + B_0x3 + hsi_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + csi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + lse_ck selected as kernel clock + 0x5 + + + + + UART4SEL + UART4 kernel clock source selection + + 9 + 3 + read-write + + + B_0x0 + rcc_pclk1 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_q_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_q_ck selected as kernel clock + 0x2 + + + B_0x3 + hsi_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + csi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + lse_ck selected as kernel clock + 0x5 + + + + + UART5SEL + UART5 kernel clock source selection + + 12 + 3 + read-write + + + B_0x0 + rcc_pclk1 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_q_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_q_ck selected as kernel clock + 0x2 + + + B_0x3 + hsi_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + csi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + lse_ck selected as kernel clock + 0x5 + + + + + USART6SEL + USART6 kernel clock source selection + + 15 + 3 + read-write + + + B_0x0 + rcc_pclk1 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_q_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_q_ck selected as kernel clock + 0x2 + + + B_0x3 + hsi_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + csi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + lse_ck selected as kernel clock + 0x5 + + + + + UART7SEL + UART7 kernel clock source selection + + 18 + 3 + read-write + + + B_0x0 + rcc_pclk1 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_q_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_q_ck selected as kernel clock + 0x2 + + + B_0x3 + hsi_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + csi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + lse_ck selected as kernel clock + 0x5 + + + + + UART8SEL + UART8 kernel clock source selection + + 21 + 3 + read-write + + + B_0x0 + rcc_pclk1 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_q_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_q_ck selected as kernel clock + 0x2 + + + B_0x3 + hsi_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + csi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + lse_ck selected as kernel clock + 0x5 + + + + + UART9SEL + UART9 kernel clock source selection + + 24 + 3 + read-write + + + B_0x0 + rcc_pclk1 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_q_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_q_ck selected as kernel clock + 0x2 + + + B_0x3 + hsi_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + csi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + lse_ck selected as kernel clock + 0x5 + + + + + USART10SEL + USART10 kernel clock source selection + + 27 + 3 + read-write + + + B_0x0 + rcc_pclk1 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_q_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_q_ck selected as kernel clock + 0x2 + + + B_0x3 + hsi_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + csi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + lse_ck selected as kernel clock + 0x5 + + + + + TIMICSEL + TIM12, TIM15 and LPTIM2 input capture source selection + + 31 + 1 + read-write + + + B_0x0 + No internal clock available for timers input capture (default after reset) + 0x0 + + + B_0x1 + hsi_ker_ck/1024, hsi_ker_ck/8 and csi_ker_ck/128 selected for timers input capture + 0x1 + + + + + + + RCC_CCIPR2 + RCC_CCIPR2 + RCC kernel clock configuration register + 0x0DC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + USART11SEL + USART11 kernel clock source selection + + 0 + 3 + read-write + + + B_0x0 + rcc_pclk1 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_q_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_q_ck selected as kernel clock + 0x2 + + + B_0x3 + hsi_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + csi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + lse_ck selected as kernel clock + 0x5 + + + + + UART12SEL + UART12 kernel clock source selection + + 4 + 3 + read-write + + + B_0x0 + rcc_pclk1 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_q_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_q_ck selected as kernel clock + 0x2 + + + B_0x3 + hsi_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + csi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + lse_ck selected as kernel clock + 0x5 + + + + + LPTIM1SEL + LPTIM1 kernel clock source selection + + 8 + 3 + read-write + + + B_0x0 + rcc_pclk3 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_p_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_r_ck selected as kernel clock + 0x2 + + + B_0x3 + lse_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + lsi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + per_ck selected as kernel clock + 0x5 + + + + + LPTIM2SEL + LPTIM2 kernel clock source selection + + 12 + 3 + read-write + + + B_0x0 + rcc_pclk1 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_p_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_r_ck selected as kernel clock + 0x2 + + + B_0x3 + lse_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + lsi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + per_ck selected as kernel clock + 0x5 + + + + + LPTIM3SEL + LPTIM3 kernel clock source selection + + 16 + 3 + read-write + + + B_0x0 + rcc_pclk3 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_p_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_r_ck selected as kernel clock + 0x2 + + + B_0x3 + lse_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + lsi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + per_ck selected as kernel clock + 0x5 + + + + + LPTIM4SEL + LPTIM4 kernel clock source selection + + 20 + 3 + read-write + + + B_0x0 + rcc_pclk3 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_p_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_r_ck selected as kernel clock + 0x2 + + + B_0x3 + lse_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + lsi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + per_ck selected as kernel clock + 0x5 + + + + + LPTIM5SEL + LPTIM5 kernel clock source selection + + 24 + 3 + read-write + + + B_0x0 + rcc_pclk3 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_p_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_r_ck selected as kernel clock + 0x2 + + + B_0x3 + lse_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + lsi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + per_ck selected as kernel clock + 0x5 + + + + + LPTIM6SEL + LPTIM6 kernel clock source selection + + 28 + 3 + read-write + + + B_0x0 + rcc_pclk3 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_p_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_r_ck selected as kernel clock + 0x2 + + + B_0x3 + lse_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + lsi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + per_ck selected as kernel clock + 0x5 + + + + + + + RCC_CCIPR3 + RCC_CCIPR3 + RCC kernel clock configuration register + 0x0E0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SPI1SEL + SPI1 kernel clock source selection + + 0 + 3 + read-write + + + B_0x0 + pll1_q_ck selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_p_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_p_ck selected as kernel clock + 0x2 + + + B_0x3 + AUDIOCLK selected as kernel clock + 0x3 + + + B_0x4 + per_ck selected as kernel clock + 0x4 + + + + + SPI2SEL + SPI2 kernel clock source selection + + 3 + 3 + read-write + + + B_0x0 + pll1_q_ck selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_p_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_p_ck selected as kernel clock + 0x2 + + + B_0x3 + AUDIOCLK selected as kernel clock + 0x3 + + + B_0x4 + per_ck selected as kernel clock + 0x4 + + + + + SPI3SEL + SPI3 kernel clock source selection + + 6 + 3 + read-write + + + B_0x0 + pll1_q_ck selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_p_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_p_ck selected as kernel clock + 0x2 + + + B_0x3 + AUDIOCLK selected as kernel clock + 0x3 + + + B_0x4 + per_ck selected as kernel clock + 0x4 + + + + + SPI4SEL + SPI4 kernel clock source selection + + 9 + 3 + read-write + + + B_0x0 + rcc_pclk2 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_q_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_q_ck selected as kernel clock + 0x2 + + + B_0x3 + hsi_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + csi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + hse_ck selected as kernel clock + 0x5 + + + + + SPI6SEL + SPI6 kernel clock source selection + + 15 + 3 + read-write + + + B_0x0 + rcc_pclk2 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_q_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_q_ck selected as kernel clock + 0x2 + + + B_0x3 + hsi_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + csi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + hse_ck selected as kernel clock + 0x5 + + + + + LPUART1SEL + LPUART1 kernel clock source selection + + 24 + 3 + read-write + + + B_0x0 + rcc_pclk3 s elected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_q_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_q_ck selected as kernel clock + 0x2 + + + B_0x3 + hsi_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + csi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + lse_ck selected as kernel clock + 0x5 + + + + + + + RCC_CCIPR4 + RCC_CCIPR4 + RCC kernel clock configuration register + 0x0E4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OCTOSPI1SEL + OCTOSPI1 kernel clock source selection + + 0 + 2 + read-write + + + B_0x0 + rcc_hclk4 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll1_q_ck selected as kernel clock + 0x1 + + + B_0x2 + pll2_r_ck selected as kernel clock + 0x2 + + + B_0x3 + per_ck selected as kernel clock + 0x3 + + + + + SYSTICKSEL + SYSTICK clock source selection + + 2 + 2 + read-write + + + B_0x0 + rcc_hclk/8 selected as clock source (default after reset) + 0x0 + + + B_0x1 + lsi_ker_ck[1] selected as clock source + 0x1 + + + B_0x2 + lse_ck[1] selected as clock source + 0x2 + + + + + USBSEL + USB kernel clock source selection + 4 + 2 + read-write + + + B_0x0 + no clock is selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll1_q_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_q_ck selected as kernel clock + 0x2 + + + B_0x3 + hsi48_ker_ck selected as kernel clock + 0x3 + + + + + SDMMC1SEL + SDMMC1 kernel clock source selection + 6 + 1 + read-write + + + B_0x0 + pll1_q_ck selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_r_ck selected as kernel clock + 0x1 + + + + + I2C1SEL + I2C1 kernel clock source selection + 16 + 2 + read-write + + + B_0x0 + rcc_pclk1 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll3_r_ck selected as kernel clock + 0x1 + + + B_0x2 + hsi_ker_ck selected as kernel clock + 0x2 + + + B_0x3 + csi_ker_ck selected as kernel clock + 0x3 + + + + + I2C2SEL + I2C2 kernel clock source selection + 18 + 2 + read-write + + + B_0x0 + rcc_pclk1 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll3_r_ck selected as kernel clock + 0x1 + + + B_0x2 + hsi_ker_ck selected as kernel clock + 0x2 + + + B_0x3 + csi_ker_ck selected as kernel clock + 0x3 + + + + + I2C3SEL + I2C3 kernel clock source selection + 20 + 2 + read-write + + + B_0x0 + rcc_pclk3 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll3_r_ck selected as kernel clock + 0x1 + + + B_0x2 + hsi_ker_ck selected as kernel clock + 0x2 + + + B_0x3 + csi_ker_ck selected as kernel clock + 0x3 + + + + + I3C1SEL + I3C1 kernel clock source selection + 24 + 2 + read-write + + + B_0x0 + rcc_pclk1 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll3_r_ck selected as kernel clock + 0x1 + + + B_0x2 + hsi_ker_ck selected as kernel clock + 0x2 + + + B_0x3 + no clock selected + 0x3 + + + + + I3C2SEL + I3C2 kernel clock source selection + 26 + 2 + read-write + + + B_0x0 + rcc_pclk1 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll3_r_ck selected as kernel clock + 0x1 + + + B_0x2 + hsi_ker_ck selected as kernel clock + 0x2 + + + B_0x3 + no clock selected + 0x3 + + + + + + + RCC_CCIPR5 + RCC_CCIPR5 + RCC kernel clock configuration register + 0x0E8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ADCDACSEL + ADC and DAC kernel clock source selection + + 0 + 3 + read-write + + + B_0x0 + rcc_hclk selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + sys_ck selected as kernel clock + 0x1 + + + B_0x2 + pll2_r_ck selected as kernel clock + 0x2 + + + B_0x3 + hse_ck selected as kernel clock + 0x3 + + + B_0x4 + hsi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + csi_ker_ck selected as kernel clock + 0x5 + + + + + DACSEL + DAC sample and hold clock + 3 + 1 + read-write + + + B_0x0 + dac_hold_ck selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + dac_hold_ck selected as kernel clock + 0x1 + + + + + RNGSEL + RNG kernel clock source selection + 4 + 2 + read-write + + + B_0x0 + hsi48_ker_ck selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll1_q_ck selected as kernel clock + 0x1 + + + B_0x2 + lse_ck selected as kernel clock + 0x2 + + + B_0x3 + lsi_ker_ck selected as kernel clock + 0x3 + + + + + CECSEL + HSMI-CEC kernel clock source selection + 6 + 2 + read-write + + + B_0x0 + lse_ck selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + lsi_ker_ck selected as kernel clock + 0x1 + + + B_0x2 + csi_ker_ck/122 selected as kernel clock + 0x2 + + + + + FDCANSEL + FDCAN1 and FDCAN2 kernel clock source selection + 8 + 2 + read-write + + + B_0x0 + hse_ck selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll1_q_ck selected as kernel clock + 0x1 + + + B_0x2 + pll2_q_ck selected as kernel clock + 0x2 + + + + + SAI1SEL + SAI1 kernel clock source selection + + 16 + 3 + read-write + + + B_0x0 + pll1_q_ck selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_p_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_p_ck selected as kernel clock + 0x2 + + + B_0x3 + AUDIOCLK selected as kernel clock + 0x3 + + + B_0x4 + per_ck selected as kernel clock + 0x4 + + + + + SAI2SEL + SAI2 kernel clock source selection + + 19 + 3 + read-write + + + B_0x0 + pll1_q_ck selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_p_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_p_ck selected as kernel clock + 0x2 + + + B_0x3 + AUDIOCLK selected as kernel clock + 0x3 + + + B_0x4 + per_ck selected as kernel clock + 0x4 + + + + + CKPERSEL + per_ck clock source selection + 30 + 2 + read-write + + + B_0x0 + hsi_ker_ck selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + csi_ker_ck selected as kernel clock + 0x1 + + + B_0x2 + hse_ck selected as kernel clock + 0x2 + + + + + + + RCC_BDCR + RCC_BDCR + RCC Backup domain control register + 0x0F0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LSEON + LSE oscillator enabled + + 0 + 1 + read-write + + + B_0x0 + LSE oscillator OFF (default after Backup domain reset) + 0x0 + + + B_0x1 + LSE oscillator ON + 0x1 + + + + + LSERDY + LSE oscillator ready + + 1 + 1 + read-write + + + B_0x0 + LSE oscillator not ready (default after Backup domain reset) + 0x0 + + + B_0x1 + LSE oscillator ready + 0x1 + + + + + LSEBYP + LSE oscillator bypass + + 2 + 1 + read-write + + + B_0x0 + LSE oscillator not bypassed (default after Backup domain reset) + 0x0 + + + B_0x1 + LSE oscillator bypassed + 0x1 + + + + + LSEDRV + LSE oscillator driving capability + + 3 + 2 + read-write + + + B_0x0 + lowest drive (default after Backup domain reset) + 0x0 + + + B_0x1 + medium-low drive + 0x1 + + + B_0x2 + medium-high drive + 0x2 + + + B_0x3 + highest drive + 0x3 + + + + + LSECSSON + LSE clock security system enable + + 5 + 1 + read-write + + + B_0x0 + CSS on 32 kHz oscillator OFF (default after Backup domain reset) + 0x0 + + + B_0x1 + CSS on 32 kHz oscillator ON + 0x1 + + + + + LSECSSD + LSE clock security system failure detection + + 6 + 1 + read-write + + + B_0x0 + no failure detected on 32 kHz oscillator (default after Backup domain reset) + 0x0 + + + B_0x1 + failure detected on 32 kHz oscillator + 0x1 + + + + + LSEEXT + low-speed external clock type in bypass mode + + 7 + 1 + read-write + + + B_0x0 + LSE in analog mode (default after Backup domain reset) + 0x0 + + + B_0x1 + LSE in digital mode (do not use if RTC is active). + 0x1 + + + + + RTCSEL + RTC clock source selection + + 8 + 2 + read-write + + + B_0x0 + no clock (default after Backup domain reset) + 0x0 + + + B_0x1 + LSE selected as RTC clock + 0x1 + + + B_0x2 + LSI selected as RTC clock + 0x2 + + + B_0x3 + HSE divided by RTCPRE value selected as RTC clock + 0x3 + + + + + RTCEN + RTC clock enable + + 15 + 1 + read-write + + + B_0x0 + rtc_ck disabled (default after Backup domain reset) + 0x0 + + + B_0x1 + rtc_ck enabled + 0x1 + + + + + VSWRST + VSwitch domain software reset + + 16 + 1 + read-write + + + B_0x0 + reset not activated (default after Backup domain reset) + 0x0 + + + B_0x1 + resets the entire VSW domain + 0x1 + + + + + LSCOEN + Low-speed clock output (LSCO) enable + + 24 + 1 + read-write + + + B_0x0 + LSCO output disabled + 0x0 + + + B_0x1 + LSCO output enabled + 0x1 + + + + + LSCOSEL + Low-speed clock output selection + + 25 + 1 + read-write + + + B_0x0 + LSI clock selected + 0x0 + + + B_0x1 + LSE clock selected + 0x1 + + + + + LSION + LSI oscillator enable + + 26 + 1 + read-write + + + B_0x0 + LSI oscillator off + 0x0 + + + B_0x1 + LSI oscillator on + 0x1 + + + + + LSIRDY + LSI oscillator ready + + 27 + 1 + read-write + + + B_0x0 + LSI oscillator not ready + 0x0 + + + B_0x1 + LSI oscillator ready + 0x1 + + + + + + + RCC_RSR + RCC_RSR + RCC reset status register + 0x0F4 + 0x20 + read-write + 0x0C000000 + 0xFFFFFFFF + + + RMVF + remove reset flag + + 23 + 1 + read-write + + + B_0x0 + reset of the reset flags not activated (default after power-on reset) + 0x0 + + + B_0x1 + resets the value of the reset flags + 0x1 + + + + + PINRSTF + pin reset flag (NRST) + + 26 + 1 + read-write + + + B_0x0 + no reset from pin occurred + 0x0 + + + B_0x1 + reset from pin occurred (default after power-on reset) + 0x1 + + + + + BORRSTF + BOR reset flag + + 27 + 1 + read-write + + + B_0x0 + no BOR reset occurred + 0x0 + + + B_0x1 + BOR reset occurred (default after power-on reset) + 0x1 + + + + + SFTRSTF + system reset from CPU reset flag + + 28 + 1 + read-write + + + B_0x0 + no CPU software reset occurred (default after power-on reset) + 0x0 + + + B_0x1 + a system reset has been generated by the CPU + 0x1 + + + + + IWDGRSTF + independent watchdog reset flag + + 29 + 1 + read-write + + + B_0x0 + no independent watchdog reset occurred (default after power-on reset) + 0x0 + + + B_0x1 + independent watchdog reset occurred + 0x1 + + + + + WWDGRSTF + window watchdog reset flag + + 30 + 1 + read-write + + + B_0x0 + no window watchdog reset occurred from WWDG (default after power-on reset) + 0x0 + + + B_0x1 + window watchdog reset occurred from WWDG + 0x1 + + + + + LPWRRSTF + Low-power reset flag + + 31 + 1 + read-write + + + B_0x0 + No illegal low-power mode reset occurred + 0x0 + + + B_0x1 + Illegal low-power mode reset occurred + 0x1 + + + + + + + RCC_SECCFGR + RCC_SECCFGR + RCC secure configuration register + 0x110 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + HSISEC + HSI clock configuration and status bits security + + 0 + 1 + read-write + + + B_0x0 + non secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + HSESEC + HSE clock configuration bits, status bits and HSE_CSS security + + 1 + 1 + read-write + + + B_0x0 + non secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + CSISEC + CSI clock configuration and status bits security + + 2 + 1 + read-write + + + B_0x0 + non secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + LSISEC + LSI clock configuration and status bits security + + 3 + 1 + read-write + + + B_0x0 + non secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + LSESEC + LSE clock configuration and status bits security + + 4 + 1 + read-write + + + B_0x0 + non secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + SYSCLKSEC + SYSCLK clock selection, STOPWUCK bit, clock output on MCO configuration security + + 5 + 1 + read-write + + + B_0x0 + non secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + PRESCSEC + AHBx/APBx prescaler configuration bits security + + 6 + 1 + read-write + + + B_0x0 + non secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + PLL1SEC + PLL1 clock configuration and status bits security + + 7 + 1 + read-write + + + B_0x0 + non secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + PLL2SEC + PLL2 clock configuration and status bits security + + 8 + 1 + read-write + + + B_0x0 + non secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + PLL3SEC + PLL3 clock configuration and status bits security + + 9 + 1 + read-write + + + B_0x0 + non secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + HSI48SEC + HSI48 clock configuration and status bits security + + 11 + 1 + read-write + + + B_0x0 + non secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + RMVFSEC + Remove reset flag security + + 12 + 1 + read-write + + + B_0x0 + non secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + CKPERSELSEC + per_ck selection security + + 13 + 1 + read-write + + + B_0x0 + non secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + + + RCC_PRIVCFGR + RCC_PRIVCFGR + RCC privilege configuration register + 0x114 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SPRIV + RCC secure functions privilege configuration + + 0 + 1 + read-write + + + B_0x0 + Read and write to RCC secure functions can be done by privileged or unprivileged access. + 0x0 + + + B_0x1 + Read and write to RCC secure functions can be done by privileged access only + 0x1 + + + + + NSPRIV + RCC non-secure functions privilege configuration + + 1 + 1 + read-write + + + B_0x0 + Read and write to RCC non-secure functions can be done by privileged or unprivileged access. + 0x0 + + + B_0x1 + Read and write to RCC non-secure functions can be done by privileged access only + 0x1 + + + + + + + + + RCC_S + 0X54020C00 + + + RNG + RNG address block description + RNG + 0x420c0800 + + 0x0 + 0x14 + registers + + + RNG + RNG global interrupt + 114 + + + + RNG_CR + RNG_CR + RNG control register + 0x000 + 0x20 + read-write + 0x00800D00 + 0xFFFFFFFF + + + RNGEN + True random number generator enable + 2 + 1 + read-write + + + B_0x0 + True random number generator is disabled. + 0x0 + + + B_0x1 + True random number generator is enabled. + 0x1 + + + + + IE + Interrupt enable + 3 + 1 + read-write + + + B_0x0 + RNG interrupt is disabled + 0x0 + + + B_0x1 + RNG interrupt is enabled. + 0x1 + + + + + CED + Clock error detection + + 5 + 1 + read-write + + + B_0x0 + Clock error detection enabled + 0x0 + + + B_0x1 + Clock error detection is disabled + 0x1 + + + + + ARDIS + Auto reset disable + + 7 + 1 + read-write + + + B_0x0 + Auto-reset enabled + 0x0 + + + B_0x1 + Auto-reset disabled + 0x1 + + + + + RNG_CONFIG3 + RNG configuration 3 + + 8 + 4 + read-write + + + NISTC + NIST custom + + 12 + 1 + read-write + + + B_0x0 + Hardware default values for NIST compliant RNG. + 0x0 + + + B_0x1 + Custom values for NIST compliant RNG. + 0x1 + + + + + RNG_CONFIG2 + RNG configuration 2 + + 13 + 3 + read-write + + + CLKDIV + Clock divider factor + + 16 + 4 + read-write + + + B_0x0 + internal RNG clock after divider is similar to incoming RNG clock. + 0x0 + + + B_0x1 + two RNG clock cycles per internal RNG clock. + 0x1 + + + B_0x2 + 2less thansup>2less than/sup> (= 4) RNG clock cycles per internal RNG clock. + 0x2 + + + B_0xF + 2less thansup>15less than/sup> RNG clock cycles per internal clock (for example. + 0xF + + + + + RNG_CONFIG1 + RNG configuration 1 + + 20 + 6 + read-write + + + CONDRST + Conditioning soft reset + + 30 + 1 + read-write + + + CONFIGLOCK + RNG Config lock + + 31 + 1 + read-write + + + B_0x0 + Writes to the RNG_NSCR, RNG_HTCR and RNG_CR configuration bits [29:4] are allowed. + 0x0 + + + B_0x1 + Writes to the RNG_NSCR, RNG_HTCR and RNG_CR configuration bits [29:4] are ignored until the next RNG reset. + 0x1 + + + + + + + RNG_SR + RNG_SR + RNG status register + 0x004 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DRDY + Data ready + + 0 + 1 + read-only + + + B_0x0 + The RNG_DR register is not yet valid, no random data is available. + 0x0 + + + B_0x1 + The RNG_DR register contains valid random data. + 0x1 + + + + + CECS + Clock error current status + + 1 + 1 + read-only + + + B_0x0 + The RNG clock is correct (fless thansub>RNGCLKless than/sub>> fless thansub>HCLKless than/sub>/32). + 0x0 + + + B_0x1 + The RNG clock is too slow (fless thansub>RNGCLKless than/sub>less than fless thansub>HCLKless than/sub>/32). + 0x1 + + + + + SECS + Seed error current status + + 2 + 1 + read-only + + + B_0x0 + No faulty sequence has currently been detected. + 0x0 + + + B_0x1 + At least one of the following faulty sequences has been detected: + 0x1 + + + + + CEIS + Clock error interrupt status + + 5 + 1 + read-write + + + B_0x0 + The RNG clock is correct (fless thansub>RNGCLKless than/sub>> fless thansub>HCLKless than/sub>/32) + 0x0 + + + B_0x1 + The RNG clock before the internal divider is detected too slow (fless thansub>RNGCLKless than/sub>less than fless thansub>HCLKless than/sub>/32) + 0x1 + + + + + SEIS + Seed error interrupt status + + 6 + 1 + read-write + + + B_0x0 + No faulty sequence detected + 0x0 + + + B_0x1 + At least one faulty sequence is detected. + 0x1 + + + + + + + RNG_DR + RNG_DR + RNG data register + 0x008 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RNDATA + Random data + + 0 + 32 + read-only + + + + + RNG_NSCR + RNG_NSCR + RNG noise source control register + 0x00C + 0x20 + read-write + 0x0003FFFF + 0xFFFFFFFF + + + EN_OSC1 + Each bit drives one oscillator enable signal input of instance number 1, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). + 0 + 3 + read-write + + + EN_OSC2 + Each bit drives one oscillator enable signal input of instance number 2, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). + 3 + 3 + read-write + + + EN_OSC3 + Each bit drives one oscillator enable signal input of instance number 3, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). + 6 + 3 + read-write + + + EN_OSC4 + Each bit drives one oscillator enable signal input of instance number 4, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). + 9 + 3 + read-write + + + EN_OSC5 + Each bit drives one oscillator enable signal input of instance number 5, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). + 12 + 3 + read-write + + + EN_OSC6 + Each bit drives one oscillator enable signal input of instance number 6, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). + 15 + 3 + read-write + + + + + RNG_HTCR + RNG_HTCR + RNG health test control register + 0x010 + 0x20 + read-write + 0x000072AC + 0xFFFFFFFF + + + HTCFG + health test configuration + + 0 + 32 + read-write + + + + + + + RNG_S + 0X520C0800 + + + RTC + RTC register block + RTC + 0x44007800 + + 0x0 + 0x400 + registers + + + RTC_S + RTC global secure interrupts + 3 + + + RTC + RTC global non-secure interrupts + 2 + + + + RTC_TR + RTC_TR + RTC time register + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SU + Second units in BCD format + 0 + 4 + read-write + + + ST + Second tens in BCD format + 4 + 3 + read-write + + + MNU + Minute units in BCD format + 8 + 4 + read-write + + + MNT + Minute tens in BCD format + 12 + 3 + read-write + + + HU + Hour units in BCD format + 16 + 4 + read-write + + + HT + Hour tens in BCD format + 20 + 2 + read-write + + + PM + AM/PM notation + 22 + 1 + read-write + + + B_0x0 + AM or 24-hour format + 0x0 + + + B_0x1 + PM + 0x1 + + + + + + + RTC_DR + RTC_DR + RTC date register + 0x04 + 0x20 + read-write + 0x00002101 + 0xFFFFFFFF + + + DU + Date units in BCD format + 0 + 4 + read-write + + + DT + Date tens in BCD format + 4 + 2 + read-write + + + MU + Month units in BCD format + 8 + 4 + read-write + + + MT + Month tens in BCD format + 12 + 1 + read-write + + + WDU + Week day units + + 13 + 3 + read-write + + + B_0x0 + forbidden + 0x0 + + + B_0x1 + Monday + 0x1 + + + B_0x7 + Sunday + 0x7 + + + + + YU + Year units in BCD format + 16 + 4 + read-write + + + YT + Year tens in BCD format + 20 + 4 + read-write + + + + + RTC_SSR + RTC_SSR + RTC subsecond register + 0x08 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + SS + Synchronous binary counter + + 0 + 32 + read-only + + + + + RTC_ICSR + RTC_ICSR + RTC initialization control and status register + 0x0C + 0x20 + read-write + 0x00000007 + 0xFFFFFFFF + + + WUTWF + Wake-up timer write flag + + 2 + 1 + read-only + + + B_0x0 + Wake-up timer configuration update not allowed except in initialization mode + 0x0 + + + B_0x1 + Wake-up timer configuration update allowed + 0x1 + + + + + SHPF + Shift operation pending + + 3 + 1 + read-only + + + B_0x0 + No shift operation is pending + 0x0 + + + B_0x1 + A shift operation is pending + 0x1 + + + + + INITS + Initialization status flag + + 4 + 1 + read-only + + + B_0x0 + Calendar has not been initialized + 0x0 + + + B_0x1 + Calendar has been initialized + 0x1 + + + + + RSF + Registers synchronization flag + + 5 + 1 + read-write + + + B_0x0 + Calendar shadow registers not yet synchronized + 0x0 + + + B_0x1 + Calendar shadow registers synchronized + 0x1 + + + + + INITF + Initialization flag + + 6 + 1 + read-only + + + B_0x0 + Calendar registers update is not allowed + 0x0 + + + B_0x1 + Calendar registers update is allowed + 0x1 + + + + + INIT + Initialization mode + 7 + 1 + read-write + + + B_0x0 + Free running mode + 0x0 + + + B_0x1 + Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER), plus BIN and BCDU fields. + 0x1 + + + + + BIN + Binary mode + 8 + 2 + read-write + + + B_0x0 + Free running BCD calendar mode (Binary mode disabled). + 0x0 + + + B_0x1 + Free running Binary mode (BCD mode disabled) + 0x1 + + + B_0x2 + Free running BCD calendar and Binary modes + 0x2 + + + B_0x3 + Free running BCD calendar and Binary modes + 0x3 + + + + + BCDU + BCD update (BIN = 10 or 11) + + 10 + 3 + read-write + + + B_0x0 + 1s calendar increment is generated each time SS[7:0] = 0 + 0x0 + + + B_0x1 + 1s calendar increment is generated each time SS[8:0] = 0 + 0x1 + + + B_0x2 + 1s calendar increment is generated each time SS[9:0] = 0 + 0x2 + + + B_0x3 + 1s calendar increment is generated each time SS[10:0] = 0 + 0x3 + + + B_0x4 + 1s calendar increment is generated each time SS[11:0] = 0 + 0x4 + + + B_0x5 + 1s calendar increment is generated each time SS[12:0] = 0 + 0x5 + + + B_0x6 + 1s calendar increment is generated each time SS[13:0] = 0 + 0x6 + + + B_0x7 + 1s calendar increment is generated each time SS[14:0] = 0 + 0x7 + + + + + RECALPF + Recalibration pending Flag + + 16 + 1 + read-only + + + + + RTC_PRER + RTC_PRER + RTC prescaler register + 0x10 + 0x20 + read-write + 0x007F00FF + 0xFFFFFFFF + + + PREDIV_S + Synchronous prescaler factor + + 0 + 15 + read-write + + + PREDIV_A + Asynchronous prescaler factor + + 16 + 7 + read-write + + + + + RTC_WUTR + RTC_WUTR + RTC wake-up timer register + 0x14 + 0x20 + read-write + 0x0000FFFF + 0xFFFFFFFF + + + WUT + Wake-up auto-reload value bits + + 0 + 16 + read-write + + + WUTOCLR + Wake-up auto-reload output clear value + + 16 + 16 + read-write + + + + + RTC_CR + RTC_CR + RTC control register + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + WUCKSEL + ck_wut wake-up clock selection + + 0 + 3 + read-write + + + B_0x0 + RTC/16 clock is selected + 0x0 + + + B_0x1 + RTC/8 clock is selected + 0x1 + + + B_0x2 + RTC/4 clock is selected + 0x2 + + + B_0x3 + RTC/2 clock is selected + 0x3 + + + + + TSEDGE + Timestamp event active edge + + 3 + 1 + read-write + + + B_0x0 + RTC_TS input rising edge generates a timestamp event + 0x0 + + + B_0x1 + RTC_TS input falling edge generates a timestamp event + 0x1 + + + + + REFCKON + RTC_REFIN reference clock detection enable (50 or 60 Hz) + + 4 + 1 + read-write + + + B_0x0 + RTC_REFIN detection disabled + 0x0 + + + B_0x1 + RTC_REFIN detection enabled + 0x1 + + + + + BYPSHAD + Bypass the shadow registers + + 5 + 1 + read-write + + + B_0x0 + Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles. + 0x0 + + + B_0x1 + Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters. + 0x1 + + + + + FMT + Hour format + 6 + 1 + read-write + + + B_0x0 + 24 hour/day format + 0x0 + + + B_0x1 + AM/PM hour format + 0x1 + + + + + SSRUIE + SSR underflow interrupt enable + 7 + 1 + read-write + + + B_0x0 + SSR underflow interrupt disabled + 0x0 + + + B_0x1 + SSR underflow interrupt enabled + 0x1 + + + + + ALRAE + Alarm A enable + 8 + 1 + read-write + + + B_0x0 + Alarm A disabled + 0x0 + + + B_0x1 + Alarm A enabled + 0x1 + + + + + ALRBE + Alarm B enable + 9 + 1 + read-write + + + B_0x0 + Alarm B disabled + 0x0 + + + B_0x1 + Alarm B enabled + 0x1 + + + + + WUTE + Wake-up timer enable + + 10 + 1 + read-write + + + B_0x0 + Wake-up timer disabled + 0x0 + + + B_0x1 + Wake-up timer enabled + 0x1 + + + + + TSE + timestamp enable + 11 + 1 + read-write + + + B_0x0 + timestamp disable + 0x0 + + + B_0x1 + timestamp enable + 0x1 + + + + + ALRAIE + Alarm A interrupt enable + 12 + 1 + read-write + + + B_0x0 + Alarm A interrupt disabled + 0x0 + + + B_0x1 + Alarm A interrupt enabled + 0x1 + + + + + ALRBIE + Alarm B interrupt enable + 13 + 1 + read-write + + + B_0x0 + Alarm B interrupt disable + 0x0 + + + B_0x1 + Alarm B interrupt enable + 0x1 + + + + + WUTIE + Wake-up timer interrupt enable + 14 + 1 + read-write + + + B_0x0 + Wake-up timer interrupt disabled + 0x0 + + + B_0x1 + Wake-up timer interrupt enabled + 0x1 + + + + + TSIE + Timestamp interrupt enable + 15 + 1 + read-write + + + B_0x0 + Timestamp interrupt disable + 0x0 + + + B_0x1 + Timestamp interrupt enable + 0x1 + + + + + ADD1H + Add 1 hour (summer time change) + + 16 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Adds 1 hour to the current time. + 0x1 + + + + + SUB1H + Subtract 1 hour (winter time change) + + 17 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Subtracts 1 hour to the current time. + 0x1 + + + + + BKP + Backup + + 18 + 1 + read-write + + + COSEL + Calibration output selection + + 19 + 1 + read-write + + + B_0x0 + Calibration output is 512 Hz + 0x0 + + + B_0x1 + Calibration output is 1 Hz + 0x1 + + + + + POL + Output polarity + + 20 + 1 + read-write + + + B_0x0 + The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]), or when a TAMPxF/ITAMPxF is asserted (if TAMPOE = 1). + 0x0 + + + B_0x1 + The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]), or when a TAMPxF/ITAMPxF is asserted (if TAMPOE = 1). + 0x1 + + + + + OSEL + Output selection + + 21 + 2 + read-write + + + B_0x0 + Output disabled + 0x0 + + + B_0x1 + Alarm A output enabled + 0x1 + + + B_0x2 + Alarm B output enabled + 0x2 + + + B_0x3 + Wake-up output enabled + 0x3 + + + + + COE + Calibration output enable + + 23 + 1 + read-write + + + B_0x0 + Calibration output disabled + 0x0 + + + B_0x1 + Calibration output enabled + 0x1 + + + + + ITSE + timestamp on internal event enable + 24 + 1 + read-write + + + B_0x0 + internal event timestamp disabled + 0x0 + + + B_0x1 + internal event timestamp enabled + 0x1 + + + + + TAMPTS + Activate timestamp on tamper detection event + + 25 + 1 + read-write + + + B_0x0 + Tamper detection event does not cause a RTC timestamp to be saved + 0x0 + + + B_0x1 + Save RTC timestamp on tamper detection event + 0x1 + + + + + TAMPOE + Tamper detection output enable on TAMPALRM + 26 + 1 + read-write + + + B_0x0 + The tamper flag is not routed on TAMPALRM + 0x0 + + + B_0x1 + The tamper flag is routed on TAMPALRM, combined with the signal provided by OSEL and with the polarity provided by POL. + 0x1 + + + + + ALRAFCLR + Alarm A flag automatic clear + 27 + 1 + read-write + + + B_0x0 + Alarm A event generates a trigger event and ALRAF must be cleared by software to allow next alarm event. + 0x0 + + + B_0x1 + Alarm A event generates a trigger event. + 0x1 + + + + + ALRBFCLR + Alarm B flag automatic clear + 28 + 1 + read-write + + + B_0x0 + Alarm B event generates a trigger event and ALRBF must be cleared by software to allow next alarm event. + 0x0 + + + B_0x1 + Alarm B event generates a trigger event. + 0x1 + + + + + TAMPALRM_PU + TAMPALRM pull-up enable + 29 + 1 + read-write + + + B_0x0 + No pull-up is applied on TAMPALRM output + 0x0 + + + B_0x1 + A pull-up is applied on TAMPALRM output + 0x1 + + + + + TAMPALRM_TYPE + TAMPALRM output type + 30 + 1 + read-write + + + B_0x0 + TAMPALRM is push-pull output + 0x0 + + + B_0x1 + TAMPALRM is open-drain output + 0x1 + + + + + OUT2EN + RTC_OUT2 output enable + + 31 + 1 + read-write + + + + + RTC_PRIVCFGR + RTC_PRIVCFGR + RTC privilege mode control register + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ALRAPRIV + Alarm A and SSR underflow privilege protection + 0 + 1 + read-write + + + B_0x0 + RTC Alarm A and SSR underflow configuration and interrupt clear can be written when the APB access is privileged or non-privileged. + 0x0 + + + B_0x1 + RTC Alarm A and SSR underflow configuration and interrupt clear can be written only when the APB access is privileged. + 0x1 + + + + + ALRBPRIV + Alarm B privilege protection + 1 + 1 + read-write + + + B_0x0 + RTC Alarm B configuration and interrupt clear can be written when the APB access is privileged or non-privileged. + 0x0 + + + B_0x1 + RTC Alarm B configuration and interrupt clear can be written only when the APB access is privileged. + 0x1 + + + + + WUTPRIV + Wake-up timer privilege protection + 2 + 1 + read-write + + + B_0x0 + RTC wake-up timer configuration and interrupt clear can be written when the APB access is privileged or non-privileged. + 0x0 + + + B_0x1 + RTC wake-up timer configuration and interrupt clear can be written only when the APB access is privileged. + 0x1 + + + + + TSPRIV + Timestamp privilege protection + 3 + 1 + read-write + + + B_0x0 + RTC Timestamp configuration and interrupt clear can be written when the APB access is privileged or non-privileged. + 0x0 + + + B_0x1 + RTC Timestamp configuration and interrupt clear can be written only when the APB access is privileged. + 0x1 + + + + + CALPRIV + Shift register, Delight saving, calibration and reference clock privilege protection + 13 + 1 + read-write + + + B_0x0 + Shift register, Delight saving, calibration and reference clock can be written when the APB access is privileged or non-privileged. + 0x0 + + + B_0x1 + Shift register, Delight saving, calibration and reference clock can be written only when the APB access is privileged. + 0x1 + + + + + INITPRIV + Initialization privilege protection + 14 + 1 + read-write + + + B_0x0 + RTC Initialization mode, calendar and prescalers registers can be written when the APB access is privileged or non-privileged. + 0x0 + + + B_0x1 + RTC Initialization mode, calendar and prescalers registers can be written only when the APB access is privileged. + 0x1 + + + + + PRIV + RTC privilege protection + 15 + 1 + read-write + + + B_0x0 + All RTC registers can be written when the APB access is privileged or non-privileged, except the registers protected by other privilege protection bits. + 0x0 + + + B_0x1 + All RTC registers can be written only when the APB access is privileged. + 0x1 + + + + + + + RTC_SECCFGR + RTC_SECCFGR + RTC secure configuration register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ALRASEC + Alarm A and SSR underflow protection + 0 + 1 + read-write + + + B_0x0 + RTC alarm A and SSR underflow configuration and interrupt clear can be written when the APB access is secure or nonsecure. + 0x0 + + + B_0x1 + RTC alarm A and SSR underflow configuration and interrupt clear can be written only when the APB access is secure. + 0x1 + + + + + ALRBSEC + Alarm B protection + 1 + 1 + read-write + + + B_0x0 + RTC alarm B configuration and interrupt clear can be written when the APB access is secure or nonsecure. + 0x0 + + + B_0x1 + RTC alarm B configuration and interrupt clear can be written only when the APB access is secure. + 0x1 + + + + + WUTSEC + Wake-up timer protection + 2 + 1 + read-write + + + B_0x0 + RTC wake-up timer configuration and interrupt clear can be written when the APB access is secure or nonsecure. + 0x0 + + + B_0x1 + RTC wake-up timer configuration and interrupt clear can be written only when the APB access is secure. + 0x1 + + + + + TSSEC + Timestamp protection + 3 + 1 + read-write + + + B_0x0 + RTC timestamp configuration and interrupt clear can be written when the APB access is secure or nonsecure. + 0x0 + + + B_0x1 + RTC timestamp configuration and interrupt clear can be written only when the APB access is secure. + 0x1 + + + + + CALSEC + Shift register, daylight saving, calibration and reference clock protection + 13 + 1 + read-write + + + B_0x0 + Shift register, daylight saving, calibration and reference clock can be written when the APB access is secure or nonsecure. + 0x0 + + + B_0x1 + Shift register, daylight saving, calibration and reference clock can be written only when the APB access is secure. + 0x1 + + + + + INITSEC + Initialization protection + 14 + 1 + read-write + + + B_0x0 + RTC Initialization mode, calendar and prescalers registers can be written when the APB access is secure or nonsecure. + 0x0 + + + B_0x1 + RTC Initialization mode, calendar and prescalers registers can be written only when the APB access is secure. + 0x1 + + + + + SEC + RTC global protection + 15 + 1 + read-write + + + B_0x0 + All RTC registers can be written when the APB access is secure or non-secure, except the registers protected by other secure protection bits. + 0x0 + + + B_0x1 + All RTC registers can be written only when the APB access is secure. + 0x1 + + + + + + + RTC_WPR + RTC_WPR + RTC write protection register + 0x24 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + KEY + Write protection key + + 0 + 8 + write-only + + + + + RTC_CALR + RTC_CALR + RTC calibration register + 0x28 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CALM + Calibration minus + + 0 + 9 + read-write + + + LPCAL + RTC low-power mode + 12 + 1 + read-write + + + B_0x0 + Calibration window is 2less thansup>20less than/sup> RTCCLK, which is a high-consumption mode. + 0x0 + + + B_0x1 + Calibration window is 2less thansup>20less than/sup> ck_apre, which is the required configuration for ultra-low consumption mode. + 0x1 + + + + + CALW16 + Use a 16-second calibration cycle period + + 13 + 1 + read-write + + + CALW8 + Use an 8-second calibration cycle period + + 14 + 1 + read-write + + + CALP + Increase frequency of RTC by 488. + 15 + 1 + read-write + + + B_0x0 + No RTCCLK pulses are added. + 0x0 + + + B_0x1 + One RTCCLK pulse is effectively inserted every 2less thansup>11less than/sup> pulses (frequency increased by 488. + 0x1 + + + + + + + RTC_SHIFTR + RTC_SHIFTR + RTC shift control register + 0x2C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + SUBFS + Subtract a fraction of a second + + 0 + 15 + write-only + + + ADD1S + Add one second + + 31 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Add one second to the clock/calendar + 0x1 + + + + + + + RTC_TSTR + RTC_TSTR + RTC timestamp time register + 0x30 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + SU + Second units in BCD format. + 0 + 4 + read-only + + + ST + Second tens in BCD format. + 4 + 3 + read-only + + + MNU + Minute units in BCD format. + 8 + 4 + read-only + + + MNT + Minute tens in BCD format. + 12 + 3 + read-only + + + HU + Hour units in BCD format. + 16 + 4 + read-only + + + HT + Hour tens in BCD format. + 20 + 2 + read-only + + + PM + AM/PM notation + 22 + 1 + read-only + + + B_0x0 + AM or 24-hour format + 0x0 + + + B_0x1 + PM + 0x1 + + + + + + + RTC_TSDR + RTC_TSDR + RTC timestamp date register + 0x34 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + DU + Date units in BCD format + 0 + 4 + read-only + + + DT + Date tens in BCD format + 4 + 2 + read-only + + + MU + Month units in BCD format + 8 + 4 + read-only + + + MT + Month tens in BCD format + 12 + 1 + read-only + + + WDU + Week day units + 13 + 3 + read-only + + + + + RTC_TSSSR + RTC_TSSSR + RTC timestamp subsecond register + 0x38 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + SS + Subsecond value/synchronous binary counter values + + 0 + 32 + read-only + + + + + RTC_ALRMAR + RTC_ALRMAR + RTC alarm A register + 0x40 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SU + Second units in BCD format. + 0 + 4 + read-write + + + ST + Second tens in BCD format. + 4 + 3 + read-write + + + MSK1 + Alarm A seconds mask + 7 + 1 + read-write + + + B_0x0 + Alarm A set if the seconds match + 0x0 + + + B_0x1 + Seconds don't care in alarm A comparison + 0x1 + + + + + MNU + Minute units in BCD format + 8 + 4 + read-write + + + MNT + Minute tens in BCD format + 12 + 3 + read-write + + + MSK2 + Alarm A minutes mask + 15 + 1 + read-write + + + B_0x0 + Alarm A set if the minutes match + 0x0 + + + B_0x1 + Minutes don't care in alarm A comparison + 0x1 + + + + + HU + Hour units in BCD format + 16 + 4 + read-write + + + HT + Hour tens in BCD format + 20 + 2 + read-write + + + PM + AM/PM notation + 22 + 1 + read-write + + + B_0x0 + AM or 24-hour format + 0x0 + + + B_0x1 + PM + 0x1 + + + + + MSK3 + Alarm A hours mask + 23 + 1 + read-write + + + B_0x0 + Alarm A set if the hours match + 0x0 + + + B_0x1 + Hours don't care in alarm A comparison + 0x1 + + + + + DU + Date units or day in BCD format + 24 + 4 + read-write + + + DT + Date tens in BCD format + 28 + 2 + read-write + + + WDSEL + Week day selection + 30 + 1 + read-write + + + B_0x0 + DU[3:0] represents the date units + 0x0 + + + B_0x1 + DU[3:0] represents the week day. + 0x1 + + + + + MSK4 + Alarm A date mask + 31 + 1 + read-write + + + B_0x0 + Alarm A set if the date/day match + 0x0 + + + B_0x1 + Date/day don't care in alarm A comparison + 0x1 + + + + + + + RTC_ALRMASSR + RTC_ALRMASSR + RTC alarm A subsecond register + 0x44 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SS + Subseconds value + + 0 + 15 + read-write + + + MASKSS + Mask the most-significant bits starting at this bit + + 24 + 6 + read-write + + + B_0x0 + No comparison on subseconds for Alarm A. + 0x0 + + + B_0x1 + SS[31:1] are don't care in Alarm A comparison. + 0x1 + + + + + SSCLR + Clear synchronous counter on alarm (Binary mode only) + + 31 + 1 + read-write + + + B_0x0 + The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running. + 0x0 + + + B_0x1 + The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRABINR. + 0x1 + + + + + + + RTC_ALRMBR + RTC_ALRMBR + RTC alarm B register + 0x48 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SU + Second units in BCD format + 0 + 4 + read-write + + + ST + Second tens in BCD format + 4 + 3 + read-write + + + MSK1 + Alarm B seconds mask + 7 + 1 + read-write + + + B_0x0 + Alarm B set if the seconds match + 0x0 + + + B_0x1 + Seconds don't care in alarm B comparison + 0x1 + + + + + MNU + Minute units in BCD format + 8 + 4 + read-write + + + MNT + Minute tens in BCD format + 12 + 3 + read-write + + + MSK2 + Alarm B minutes mask + 15 + 1 + read-write + + + B_0x0 + Alarm B set if the minutes match + 0x0 + + + B_0x1 + Minutes don't care in alarm B comparison + 0x1 + + + + + HU + Hour units in BCD format + 16 + 4 + read-write + + + HT + Hour tens in BCD format + 20 + 2 + read-write + + + PM + AM/PM notation + 22 + 1 + read-write + + + B_0x0 + AM or 24-hour format + 0x0 + + + B_0x1 + PM + 0x1 + + + + + MSK3 + Alarm B hours mask + 23 + 1 + read-write + + + B_0x0 + Alarm B set if the hours match + 0x0 + + + B_0x1 + Hours don't care in alarm B comparison + 0x1 + + + + + DU + Date units or day in BCD format + 24 + 4 + read-write + + + DT + Date tens in BCD format + 28 + 2 + read-write + + + WDSEL + Week day selection + 30 + 1 + read-write + + + B_0x0 + DU[3:0] represents the date units + 0x0 + + + B_0x1 + DU[3:0] represents the week day. + 0x1 + + + + + MSK4 + Alarm B date mask + 31 + 1 + read-write + + + B_0x0 + Alarm B set if the date and day match + 0x0 + + + B_0x1 + Date and day don't care in alarm B comparison + 0x1 + + + + + + + RTC_ALRMBSSR + RTC_ALRMBSSR + RTC alarm B subsecond register + 0x4C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SS + Subseconds value + + 0 + 15 + read-write + + + MASKSS + Mask the most-significant bits starting at this bit + + 24 + 6 + read-write + + + B_0x0 + No comparison on subseconds for Alarm B. + 0x0 + + + B_0x1 + SS[31:1] are don't care in Alarm B comparison. + 0x1 + + + + + SSCLR + Clear synchronous counter on alarm (Binary mode only) + + 31 + 1 + read-write + + + B_0x0 + The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running. + 0x0 + + + B_0x1 + The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRBBINR. + 0x1 + + + + + + + RTC_SR + RTC_SR + RTC status register + 0x50 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + ALRAF + Alarm A flag + + 0 + 1 + read-only + + + ALRBF + Alarm B flag + + 1 + 1 + read-only + + + WUTF + Wake-up timer flag + + 2 + 1 + read-only + + + TSF + Timestamp flag + + 3 + 1 + read-only + + + TSOVF + Timestamp overflow flag + + 4 + 1 + read-only + + + ITSF + Internal timestamp flag + + 5 + 1 + read-only + + + SSRUF + SSR underflow flag + + 6 + 1 + read-only + + + + + RTC_MISR + RTC_MISR + RTC nonsecure masked interrupt status register + 0x54 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + ALRAMF + Alarm A masked flag + + 0 + 1 + read-only + + + ALRBMF + Alarm B nonsecure masked flag + + 1 + 1 + read-only + + + WUTMF + Wake-up timer nonsecure masked flag + + 2 + 1 + read-only + + + TSMF + Timestamp nonsecure masked flag + + 3 + 1 + read-only + + + TSOVMF + Timestamp overflow nonsecure masked flag + + 4 + 1 + read-only + + + ITSMF + Internal timestamp nonsecure masked flag + + 5 + 1 + read-only + + + SSRUMF + SSR underflow nonsecure masked flag + + 6 + 1 + read-only + + + + + RTC_SMISR + RTC_SMISR + RTC secure masked interrupt status register + 0x58 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + ALRAMF + Alarm A interrupt secure masked flag + + 0 + 1 + read-only + + + ALRBMF + Alarm B interrupt secure masked flag + + 1 + 1 + read-only + + + WUTMF + Wake-up timer interrupt secure masked flag + + 2 + 1 + read-only + + + TSMF + Timestamp interrupt secure masked flag + + 3 + 1 + read-only + + + TSOVMF + Timestamp overflow interrupt secure masked flag + + 4 + 1 + read-only + + + ITSMF + Internal timestamp interrupt secure masked flag + + 5 + 1 + read-only + + + SSRUMF + SSR underflow secure masked flag + + 6 + 1 + read-only + + + + + RTC_SCR + RTC_SCR + RTC status clear register + 0x5C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + CALRAF + Clear alarm A flag + + 0 + 1 + write-only + + + CALRBF + Clear alarm B flag + + 1 + 1 + write-only + + + CWUTF + Clear wake-up timer flag + + 2 + 1 + write-only + + + CTSF + Clear timestamp flag + + 3 + 1 + write-only + + + CTSOVF + Clear timestamp overflow flag + + 4 + 1 + write-only + + + CITSF + Clear internal timestamp flag + + 5 + 1 + write-only + + + CSSRUF + Clear SSR underflow flag + + 6 + 1 + write-only + + + + + RTC_OR + RTC_OR + RTC option register + 0x60 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OUT2_RMP + RTC_OUT2 mapping + 0 + 1 + read-write + + + B_0x0 + RTC_OUT2 is mapped on PI8 + 0x0 + + + B_0x1 + RTC_OUT2 is mapped on PB2 + 0x1 + + + + + + + RTC_ALRABINR + RTC_ALRABINR + RTC alarm A binary mode register + 0x70 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SS + Synchronous counter alarm value in Binary mode + + 0 + 32 + read-write + + + + + RTC_ALRBBINR + RTC_ALRBBINR + RTC alarm B binary mode register + 0x74 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SS + Synchronous counter alarm value in Binary mode + + 0 + 32 + read-write + + + + + + + RTC_S + 0X54007800 + + + SBS + SBS address block description + SBS + 0x44000400 + + 0x0 + 0x150 + registers + + + + SBS_HDPLCR + SBS_HDPLCR + SBS temporal isolation control register + 0x010 + 0x20 + read-write + 0x000000B4 + 0xFFFFFFFF + + + INCR_HDPL + increment HDPL value + + 0 + 8 + read-write + + + B_0xB4 + no increment + 0xB4 + + + B_0x6A + recommended value to increment HDPL level by one + 0x6A + + + + + + + SBS_HDPLSR + SBS_HDPLSR + SBS temporal isolation status register + 0x014 + 0x20 + read-only + 0x00000000 + 0x00000000 + + + HDPL + temporal isolation level + + 0 + 8 + read-only + + + B_0xB4 + HDPL0, RSS + 0xB4 + + + B_0x51 + HDPL1, iRoT + 0x51 + + + B_0x8A + HDPL2, uRoT + 0x8A + + + B_0x6F + HDPL3, application (secure/non-secure) + 0x6F + + + + + + + SBS_NEXTHDPLCR + SBS_NEXTHDPLCR + SBS next HDPL control register + 0x018 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + NEXTHDPL + index to point to a higher HDPL than the current one + + 0 + 2 + read-write + + + + + SBS_DBGCR + SBS_DBGCR + SBS debug control register + 0x020 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AP_UNLOCK + access port unlock + + 0 + 8 + read-write + + + DBG_UNLOCK + debug unlock when DBG_AUTH_HDPL is reached + + 8 + 8 + read-write + + + DBG_AUTH_HDPL + authenticated debug temporal isolation level + + 16 + 8 + read-write + + + B_0x51 + HDPL1 + 0x51 + + + B_0x8A + HDPL2 + 0x8A + + + B_0x6F + HDPL3 + 0x6F + + + + + DBG_AUTH_SEC + control debug opening secure/non-secure + + 24 + 8 + read-write + + + + + SBS_DBGLOCKR + SBS_DBGLOCKR + SBS debug lock register + 0x024 + 0x20 + read-write + 0x000000B4 + 0xFFFFFFFF + + + DBGCFG_LOCK + debug configuration lock + + 0 + 8 + read-write + + + B_0xB4 + Writes to SBS_DBGCR allowed (default) + 0xB4 + + + + + + + SBS_RSSCMDR + SBS_RSSCMDR + SBS RSS command register + 0x034 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RSSCMD + RSS command + + 0 + 16 + read-write + + + + + SBS_EPOCHSELCR + SBS_EPOCHSELCR + SBS EPOCH selection control register + 0x0A0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EPOCH_SEL + select EPOCH value to be sent to the SAES + + 0 + 2 + read-write + + + B_0x0 + NS_EPOCH (non-secure) counter input selected + 0x0 + + + B_0x1 + SEC_EPOCH counter input selected + 0x1 + + + + + + + SBS_SECCFGR + SBS_SECCFGR + SBS security mode configuration control register + 0x0C0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SBSSEC + SBS clock control, memory-erase status register and compensation cell register security enable + 0 + 1 + read-write + + + B_0x0 + SBS_MESR, SBS_CCCSR, SBS_CCVALR, SBS_CCSWCR registers accessible through secure or non-secure transaction + 0x0 + + + B_0x1 + SBS_MESR, SBS_CCCSR, SBS_CCVALR, SBS_CCSWCR registers accessible only through secure transaction + 0x1 + + + + + CLASSBSEC + ClassB security enable + 1 + 1 + read-write + + + B_0x0 + SBS_CFGR2 register accessible through secure or non-secure transaction + 0x0 + + + B_0x1 + SBS_CFGR2 register accessible only through secure transaction + 0x1 + + + + + FPUSEC + FPU security enable + + 3 + 1 + read-write + + + B_0x0 + SBS_FPUIMP register accessible through secure or non-secure transaction + 0x0 + + + B_0x1 + SBS_FPUIMP register accessible only through secure transaction + 0x1 + + + + + + + SBS_PMCR + SBS_PMCR + SBS product mode and configuration register + 0x100 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PB6_FMP + Fast-mode Plus driving capability activation on PB6 + + 16 + 1 + read-write + + + B_0x0 + PB6 pin operates in standard mode. + 0x0 + + + B_0x1 + Fm+ mode is enabled on PB6 pin and the speed control is bypassed. + 0x1 + + + + + PB7_FMP + Fast-mode Plus driving capability activation on PB7 + + 17 + 1 + read-write + + + B_0x0 + PB7 pin operates in standard mode. + 0x0 + + + B_0x1 + Fm+ mode is enabled on PB7 pin and the speed control is bypassed. + 0x1 + + + + + PB8_FMP + Fast-mode Plus driving capability activation on PB8 + + 18 + 1 + read-write + + + B_0x0 + PB8 pin operates in standard mode. + 0x0 + + + B_0x1 + Fm+ mode is enabled on PB8 pin and the speed control is bypassed. + 0x1 + + + + + PB9_FMP + Fast-mode Plus driving capability activation on PB9 + + 19 + 1 + read-write + + + B_0x0 + PB9 pin operates in standard mode. + 0x0 + + + B_0x1 + Fm+ mode is enabled on PB9 pin and the speed control is bypassed. + 0x1 + + + + + ETH_SEL_PHY + Ethernet PHY interface selection + + 21 + 3 + read-write + + + B_0x0 + GMII or MII + 0x0 + + + B_0x4 + RMII + 0x4 + + + + + + + SBS_FPUIMR + SBS_FPUIMR + SBS FPU interrupt mask register + 0x104 + 0x20 + read-write + 0x0000001F + 0xFFFFFFFF + + + FPU_IE + FPU interrupt enable + + 0 + 6 + read-write + + + + + SBS_MESR + SBS_MESR + SBS memory erase status register + 0x108 + 0x20 + read-write + 0x00000000 + 0xFFFFFFF0 + + + MCLR + device memories erase status + + 0 + 1 + read-write + + + B_0x0 + memory erase on going if not yet cleared by software + 0x0 + + + B_0x1 + Memory erase done + 0x1 + + + + + IPMEE + ICACHE erase status + + 16 + 1 + read-write + + + B_0x0 + ICACHE and PKA RAM erase on going + 0x0 + + + B_0x1 + ICACHE and PKA SRAM erase done + 0x1 + + + + + + + SBS_CCCSR + SBS_CCCSR + SBS compensation cell for I/Os control and status register + 0x110 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EN1 + enable compensation cell for VDDIO power rail + + 0 + 1 + read-write + + + B_0x0 + I/O compensation cell disabled + 0x0 + + + B_0x1 + I/O compensation cell enabled + 0x1 + + + + + CS1 + code selection for VDDIO power rail (reset value set to 1) + + 1 + 1 + read-write + + + B_0x0 + Code from the cell (available in the SBS_CCVR) + 0x0 + + + B_0x1 + Code from SBS_CCCR + 0x1 + + + + + EN2 + enable compensation cell for VDDIO2 power rail + + 2 + 1 + read-write + + + B_0x0 + I/O compensation cell disabled + 0x0 + + + B_0x1 + I/O compensation cell enabled + 0x1 + + + + + CS2 + code selection for VDDIO2 power rail (reset value set to 1) + + 3 + 1 + read-write + + + B_0x0 + Code from the cell (available in SBS_CCVR) + 0x0 + + + B_0x1 + Code from SBS_CCCR + 0x1 + + + + + RDY1 + VDDIO compensation cell ready flag + + 8 + 1 + read-only + + + B_0x0 + VDDIO compensation cell not ready + 0x0 + + + B_0x1 + VDDIO compensation cell ready (code value provided by the cell can be used) + 0x1 + + + + + RDY2 + VDDIO2 compensation cell ready flag + + 9 + 1 + read-only + + + B_0x0 + VDDIO2 compensation cell not ready + 0x0 + + + B_0x1 + VDDIO2 compensation cell ready (code value provided by the cell can be used) + 0x1 + + + + + + + SBS_CCVALR + SBS_CCVALR + SBS compensation cell for I/Os value register + 0x114 + 0x20 + read-only + 0x00000088 + 0xFFFFFFFF + + + ANSRC1 + compensation value for the NMOS transistor + + 0 + 4 + read-only + + + APSRC1 + compensation value for the PMOS transistor + + 4 + 4 + read-only + + + ANSRC2 + Compensation value for the NMOS transistor + + 8 + 4 + read-only + + + APSRC2 + compensation value for the PMOS transistor + + 12 + 4 + read-only + + + + + SBS_CCSWCR + SBS_CCSWCR + SBS compensation cell for I/Os software code register + 0x118 + 0x20 + read-write + 0x00007878 + 0xFFFFFFFF + + + SW_ANSRC1 + NMOS compensation code for VDD power rails + + 0 + 4 + read-write + + + SW_APSRC1 + PMOS compensation code for the VDD power rails + + 4 + 4 + read-write + + + SW_ANSRC2 + NMOS compensation code for VDDIO power rails + + 8 + 4 + read-write + + + SW_APSRC2 + PMOS compensation code for the Vless thansub>DDIOless than/sub> power rails + + 12 + 4 + read-write + + + + + SBS_CFGR2 + SBS_CFGR2 + SBS Class B register + 0x120 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CLL + core lockup lock + + 0 + 1 + read-write + + + B_0x0 + lockup output disconnected from timer break inputs + 0x0 + + + B_0x1 + lockup output connected to timer break inputs + 0x1 + + + + + SEL + SRAM ECC error lock + + 1 + 1 + read-write + + + B_0x0 + SRAM double ECC error flag disconnected from timer break inputs + 0x0 + + + B_0x1 + SRAM double ECC error flag connected to timer break inputs + 0x1 + + + + + PVDL + PVD lock + + 2 + 1 + read-write + + + B_0x0 + PVD interrupt disconnected from timer break inputs. + 0x0 + + + B_0x1 + PVD interrupt is connected to timer break inputs. + 0x1 + + + + + ECCL + ECC lock + + 3 + 1 + read-write + + + B_0x0 + double ECC error flag disconnected to timer break inputs + 0x0 + + + B_0x1 + double ECC error flag connected to timer break inputs + 0x1 + + + + + + + SBS_CNSLCKR + SBS_CNSLCKR + SBS CPU non-secure lock register + 0x144 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LOCKNSVTOR + VTOR_NS register lock + + 0 + 1 + read-write + + + B_0x0 + VTOR_NS register write enabled + 0x0 + + + B_0x1 + VTOR_NS register write disabled + 0x1 + + + + + LOCKNSMPU + non-secure MPU register lock + + 1 + 1 + read-write + + + B_0x0 + non-secure MPU registers write enabled + 0x0 + + + B_0x1 + non-secure MPU registers write disabled + 0x1 + + + + + + + SBS_CSLCKR + SBS_CSLCKR + SBS CPU secure lock register + 0x148 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LOCKSVTAIRCR + VTOR_S and AIRCR register lock + + 0 + 1 + read-write + + + B_0x0 + VTOR_S register PRIS and BFHFNMINS bits in the AIRCR register write enabled + 0x0 + + + B_0x1 + VTOR_S register PRIS and BFHFNMINS bits in the AIRCR register write disabled + 0x1 + + + + + LOCKSMPU + secure MPU registers lock + + 1 + 1 + read-write + + + B_0x0 + Secure MPU registers writes enabled + 0x0 + + + B_0x1 + Secure MPU registers writes disabled + 0x1 + + + + + LOCKSAU + SAU registers lock + + 2 + 1 + read-write + + + B_0x0 + SAU registers write enabled + 0x0 + + + B_0x1 + SAU registers write disabled + 0x1 + + + + + + + SBS_ECCNMIR + SBS_ECCNMIR + SBS flift ECC NMI mask register + 0x14C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ECCNMI_MASK_EN + NMI behavior setup when a double ECC error occurs on flitf data part + 0 + 1 + read-write + + + B_0x0 + NMI generated if a double ECC error in the flitf data part + 0x0 + + + B_0x1 + NMI not generated if a double ECC error in the flitf data part + 0x1 + + + + + + + + + SBS_S + 0X54000400 + + + SDMMC + SDMMC address block description + SDMMC + 0x46008000 + + 0x0 + 0xC0 + registers + + + SDMMC1 + SDMMC1 global interrupt + 79 + + + + SDMMC_POWER + SDMMC_POWER + SDMMC power control register + 0x000 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PWRCTRL + SDMMC state control bits + + 0 + 2 + read-write + + + B_0x0 + After reset, Reset: the SDMMC is disabled and the clock to the Card is stopped, SDMMC_D[7:0], and SDMMC_CMD are HiZ and SDMMC_CK is driven low. + 0x0 + + + B_0x2 + Power-cycle, the SDMMC is disabled and the clock to the card is stopped, SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK are driven low. + 0x2 + + + B_0x3 + Power-on: the card is clocked, The first 74 SDMMC_CK cycles the SDMMC is still disabled. + 0x3 + + + + + VSWITCH + Voltage switch sequence start + + 2 + 1 + read-write + + + B_0x0 + Voltage switch sequence not started and not active. + 0x0 + + + B_0x1 + Voltage switch sequence started or active. + 0x1 + + + + + VSWITCHEN + Voltage switch procedure enable + + 3 + 1 + read-write + + + B_0x0 + SDMMC_CK clock kept unchanged after successfully received command response. + 0x0 + + + B_0x1 + SDMMC_CK clock stopped after successfully received command response. + 0x1 + + + + + DIRPOL + Data and command direction signals polarity selection + + 4 + 1 + read-write + + + B_0x0 + Voltage transceiver IOs driven as output when direction signal is low. + 0x0 + + + B_0x1 + Voltage transceiver IOs driven as output when direction signal is high. + 0x1 + + + + + + + SDMMC_CLKCR + SDMMC_CLKCR + SDMMC clock control register + 0x004 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CLKDIV + Clock divide factor + + 0 + 10 + read-write + + + B_0x000 + SDMMC_CK frequency = sdmmc_ker_ck / 1 (Does not support DDR) + 0x000 + + + B_0x001 + SDMMC_CK frequency = sdmmc_ker_ck / 2 + 0x001 + + + B_0x002 + SDMMC_CK frequency = sdmmc_ker_ck / 4 + 0x002 + + + B_0x080 + SDMMC_CK frequency = sdmmc_ker_ck / 256 + 0x080 + + + B_0x3FF + SDMMC_CK frequency = sdmmc_ker_ck / 2046 + 0x3FF + + + + + PWRSAV + Power saving configuration bit + + 12 + 1 + read-write + + + B_0x0 + SDMMC_CK clock is always enabled + 0x0 + + + B_0x1 + SDMMC_CK is only enabled when the bus is active + 0x1 + + + + + WIDBUS + Wide bus mode enable bit + + 14 + 2 + read-write + + + B_0x0 + Default 1-bit wide bus mode: SDMMC_D0 used (Does not support DDR) + 0x0 + + + B_0x1 + 4-bit wide bus mode: SDMMC_D[3:0] used + 0x1 + + + B_0x2 + 8-bit wide bus mode: SDMMC_D[7:0] used + 0x2 + + + + + NEGEDGE + SDMMC_CK dephasing selection bit for data and command + + 16 + 1 + read-write + + + B_0x0 + When clock division >1 (CLKDIV > 0) and DDR = 0: + 0x0 + + + B_0x1 + When clock division >1 (CLKDIV > 0) and DDR = 0: + 0x1 + + + + + HWFC_EN + Hardware flow control enable + + 17 + 1 + read-write + + + B_0x0 + Hardware flow control is disabled + 0x0 + + + B_0x1 + Hardware flow control is enabled + 0x1 + + + + + DDR + Data rate signaling selection + + 18 + 1 + read-write + + + B_0x0 + SDR Single data rate signaling + 0x0 + + + B_0x1 + DDR double data rate signaling + 0x1 + + + + + BUSSPEED + Bus speed for selection of SDMMC operating modes + + 19 + 1 + read-write + + + B_0x0 + DS, HS, SDR12, SDR25, Legacy compatible, High speed SDR, High speed DDR bus speed mode selected + 0x0 + + + B_0x1 + SDR50, DDR50, SDR104, HS200 bus speed mode selected. + 0x1 + + + + + SELCLKRX + Receive clock selection + + 20 + 2 + read-write + + + B_0x0 + sdmmc_io_in_ck selected as receive clock + 0x0 + + + B_0x1 + SDMMC_CKIN feedback clock selected as receive clock + 0x1 + + + B_0x2 + sdmmc_fb_ck tuned feedback clock selected as receive clock. + 0x2 + + + + + + + SDMMC_ARGR + SDMMC_ARGR + SDMMC argument register + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CMDARG + Command argument + + 0 + 32 + read-write + + + + + SDMMC_CMDR + SDMMC_CMDR + SDMMC command register + 0x00C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CMDINDEX + Command index + + 0 + 6 + read-write + + + CMDTRANS + The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM + + 6 + 1 + read-write + + + CMDSTOP + The CPSM treats the command as a Stop Transmission command and signals abort to the DPSM + + 7 + 1 + read-write + + + WAITRESP + Wait for response bits + + 8 + 2 + read-write + + + B_0x0 + No response, expect CMDSENT flag + 0x0 + + + B_0x1 + Short response, expect CMDREND or CCRCFAIL flag + 0x1 + + + B_0x2 + Short response, expect CMDREND flag (No CRC) + 0x2 + + + B_0x3 + Long response, expect CMDREND or CCRCFAIL flag + 0x3 + + + + + WAITINT + CPSM waits for interrupt request + + 10 + 1 + read-write + + + WAITPEND + CPSM waits for end of data transfer (CmdPend internal signal) from DPSM + + 11 + 1 + read-write + + + CPSMEN + Command path state machine (CPSM) enable bit + + 12 + 1 + read-write + + + DTHOLD + Hold new data block transmission and reception in the DPSM + + 13 + 1 + read-write + + + BOOTMODE + Select the boot mode procedure to be used + + 14 + 1 + read-write + + + B_0x0 + Normal boot mode procedure selected + 0x0 + + + B_0x1 + Alternative boot mode procedure selected. + 0x1 + + + + + BOOTEN + Enable boot mode procedure + 15 + 1 + read-write + + + B_0x0 + Boot mode procedure disabled + 0x0 + + + B_0x1 + Boot mode procedure enabled + 0x1 + + + + + CMDSUSPEND + The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end + + 16 + 1 + read-write + + + + + SDMMC_RESPCMDR + SDMMC_RESPCMDR + SDMMC command response register + 0x010 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RESPCMD + Response command index + + 0 + 6 + read-only + + + + + SDMMC_RESP1R + SDMMC_RESP1R + SDMMC response 1 register + 0x14 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + CARDSTATUS + Card status according table below + + 0 + 32 + read-only + + + + + SDMMC_RESP2R + SDMMC_RESP2R + SDMMC response 2 register + 0x18 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + CARDSTATUS + Card status according table below + + 0 + 32 + read-only + + + + + SDMMC_RESP3R + SDMMC_RESP3R + SDMMC response 3 register + 0x1C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + CARDSTATUS + Card status according table below + + 0 + 32 + read-only + + + + + SDMMC_RESP4R + SDMMC_RESP4R + SDMMC response 4 register + 0x20 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + CARDSTATUS + Card status according table below + + 0 + 32 + read-only + + + + + SDMMC_DTIMER + SDMMC_DTIMER + SDMMC data timer register + 0x024 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DATATIME + Data and R1b busy timeout period + + 0 + 32 + read-write + + + + + SDMMC_DLENR + SDMMC_DLENR + SDMMC data length register + 0x028 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DATALENGTH + Data length value + + 0 + 25 + read-write + + + + + SDMMC_DCTRL + SDMMC_DCTRL + SDMMC data control register + 0x02C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DTEN + Data transfer enable bit + + 0 + 1 + read-write + + + B_0x0 + Do not start data transfer without CPSM data transfer command. + 0x0 + + + B_0x1 + Start data transfer without CPSM data transfer command. + 0x1 + + + + + DTDIR + Data transfer direction selection + + 1 + 1 + read-write + + + B_0x0 + From host to card. + 0x0 + + + B_0x1 + From card to host. + 0x1 + + + + + DTMODE + Data transfer mode selection + + 2 + 2 + read-write + + + B_0x0 + Block data transfer ending on block count. + 0x0 + + + B_0x1 + SDIO multibyte data transfer. + 0x1 + + + B_0x2 + e MMC Stream data transfer. + 0x2 + + + B_0x3 + Block data transfer ending with STOP_TRANSMISSION command (not to be used with DTEN initiated data transfers). + 0x3 + + + + + DBLOCKSIZE + Data block size + + 4 + 4 + read-write + + + B_0x0 + Block length = 2less thansup>0less than/sup> = 1 byte + 0x0 + + + B_0x1 + Block length = 2less thansup>1less than/sup> = 2 bytes + 0x1 + + + B_0x2 + Block length = 2less thansup>2 less than/sup>= 4 bytes + 0x2 + + + B_0x3 + Block length = 2less thansup>3less than/sup> = 8 bytes + 0x3 + + + B_0x4 + Block length = 2less thansup>4less than/sup> = 16 bytes + 0x4 + + + B_0x5 + Block length = 2less thansup>5less than/sup> = 32 bytes + 0x5 + + + B_0x6 + Block length = 2less thansup>6less than/sup> = 64 bytes + 0x6 + + + B_0x7 + Block length = 2less thansup>7less than/sup> = 128 bytes + 0x7 + + + B_0x8 + Block length = 2less thansup>8less than/sup> = 256 bytes + 0x8 + + + B_0x9 + Block length = 2less thansup>9less than/sup> = 512 bytes + 0x9 + + + B_0xA + Block length = 2less thansup>10less than/sup> = 1024 bytes + 0xA + + + B_0xB + Block length = 2less thansup>11less than/sup> = 2048 bytes + 0xB + + + B_0xC + Block length = 2less thansup>12less than/sup> = 4096 bytes + 0xC + + + B_0xD + Block length = 2less thansup>13less than/sup> = 8192 bytes + 0xD + + + B_0xE + Block length = 2less thansup>14less than/sup> = 16384 bytes + 0xE + + + + + RWSTART + Read Wait start + + 8 + 1 + read-write + + + RWSTOP + Read Wait stop + + 9 + 1 + read-write + + + B_0x0 + No Read Wait stop. + 0x0 + + + B_0x1 + Enable for Read Wait stop when DPSM is in the R_W state. + 0x1 + + + + + RWMOD + Read Wait mode + + 10 + 1 + read-write + + + B_0x0 + Read Wait control using SDMMC_D2 + 0x0 + + + B_0x1 + Read Wait control stopping SDMMC_CK + 0x1 + + + + + SDIOEN + SD I/O interrupt enable functions + + 11 + 1 + read-write + + + BOOTACKEN + Enable the reception of the boot acknowledgment + + 12 + 1 + read-write + + + B_0x0 + Boot acknowledgment disabled, not expected to be received + 0x0 + + + B_0x1 + Boot acknowledgment enabled, expected to be received + 0x1 + + + + + FIFORST + FIFO reset, flushes any remaining data + + 13 + 1 + read-write + + + B_0x0 + FIFO not affected. + 0x0 + + + B_0x1 + Flush any remaining data and reset the FIFO pointers. + 0x1 + + + + + + + SDMMC_DCNTR + SDMMC_DCNTR + SDMMC data counter register + 0x030 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + DATACOUNT + Data count value + + 0 + 25 + read-only + + + + + SDMMC_STAR + SDMMC_STAR + SDMMC status register + 0x034 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + CCRCFAIL + Command response received (CRC check failed) + + 0 + 1 + read-only + + + DCRCFAIL + Data block sent/received (CRC check failed) + + 1 + 1 + read-only + + + CTIMEOUT + Command response timeout + + 2 + 1 + read-only + + + DTIMEOUT + Data timeout + + 3 + 1 + read-only + + + TXUNDERR + Transmit FIFO underrun error (masked by hardware when IDMA is enabled) + + 4 + 1 + read-only + + + RXOVERR + Received FIFO overrun error (masked by hardware when IDMA is enabled) + + 5 + 1 + read-only + + + CMDREND + Command response received (CRC check passed, or no CRC) + + 6 + 1 + read-only + + + CMDSENT + Command sent (no response required) + + 7 + 1 + read-only + + + DATAEND + Data transfer ended correctly + + 8 + 1 + read-only + + + DHOLD + Data transfer Hold + + 9 + 1 + read-only + + + DBCKEND + Data block sent/received + + 10 + 1 + read-only + + + DABORT + Data transfer aborted by CMD12 + + 11 + 1 + read-only + + + DPSMACT + Data path state machine active, i. + 12 + 1 + read-only + + + CPSMACT + Command path state machine active, i. + 13 + 1 + read-only + + + TXFIFOHE + Transmit FIFO half empty + + 14 + 1 + read-only + + + RXFIFOHF + Receive FIFO half full + + 15 + 1 + read-only + + + TXFIFOF + Transmit FIFO full + + 16 + 1 + read-only + + + RXFIFOF + Receive FIFO full + + 17 + 1 + read-only + + + TXFIFOE + Transmit FIFO empty + + 18 + 1 + read-only + + + RXFIFOE + Receive FIFO empty + + 19 + 1 + read-only + + + BUSYD0 + Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response + + 20 + 1 + read-only + + + B_0x0 + card signals not busy on SDMMC_D0. + 0x0 + + + B_0x1 + card signals busy on SDMMC_D0. + 0x1 + + + + + BUSYD0END + end of SDMMC_D0 Busy following a CMD response detected + + 21 + 1 + read-only + + + B_0x0 + card SDMMC_D0 signal does NOT signal change from busy to not busy. + 0x0 + + + B_0x1 + card SDMMC_D0 signal changed from busy to NOT busy. + 0x1 + + + + + SDIOIT + SDIO interrupt received + + 22 + 1 + read-only + + + ACKFAIL + Boot acknowledgment received (boot acknowledgment check fail) + + 23 + 1 + read-only + + + ACKTIMEOUT + Boot acknowledgment timeout + + 24 + 1 + read-only + + + VSWEND + Voltage switch critical timing section completion + + 25 + 1 + read-only + + + CKSTOP + SDMMC_CK stopped in Voltage switch procedure + + 26 + 1 + read-only + + + IDMATE + IDMA transfer error + + 27 + 1 + read-only + + + IDMABTC + IDMA buffer transfer complete + + 28 + 1 + read-only + + + + + SDMMC_ICR + SDMMC_ICR + SDMMC interrupt clear register + 0x038 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCRCFAILC + CCRCFAIL flag clear bit + + 0 + 1 + read-write + + + B_0x0 + CCRCFAIL not cleared + 0x0 + + + B_0x1 + CCRCFAIL cleared + 0x1 + + + + + DCRCFAILC + DCRCFAIL flag clear bit + + 1 + 1 + read-write + + + B_0x0 + DCRCFAIL not cleared + 0x0 + + + B_0x1 + DCRCFAIL cleared + 0x1 + + + + + CTIMEOUTC + CTIMEOUT flag clear bit + + 2 + 1 + read-write + + + B_0x0 + CTIMEOUT not cleared + 0x0 + + + B_0x1 + CTIMEOUT cleared + 0x1 + + + + + DTIMEOUTC + DTIMEOUT flag clear bit + + 3 + 1 + read-write + + + B_0x0 + DTIMEOUT not cleared + 0x0 + + + B_0x1 + DTIMEOUT cleared + 0x1 + + + + + TXUNDERRC + TXUNDERR flag clear bit + + 4 + 1 + read-write + + + B_0x0 + TXUNDERR not cleared + 0x0 + + + B_0x1 + TXUNDERR cleared + 0x1 + + + + + RXOVERRC + RXOVERR flag clear bit + + 5 + 1 + read-write + + + B_0x0 + RXOVERR not cleared + 0x0 + + + B_0x1 + RXOVERR cleared + 0x1 + + + + + CMDRENDC + CMDREND flag clear bit + + 6 + 1 + read-write + + + B_0x0 + CMDREND not cleared + 0x0 + + + B_0x1 + CMDREND cleared + 0x1 + + + + + CMDSENTC + CMDSENT flag clear bit + + 7 + 1 + read-write + + + B_0x0 + CMDSENT not cleared + 0x0 + + + B_0x1 + CMDSENT cleared + 0x1 + + + + + DATAENDC + DATAEND flag clear bit + + 8 + 1 + read-write + + + B_0x0 + DATAEND not cleared + 0x0 + + + B_0x1 + DATAEND cleared + 0x1 + + + + + DHOLDC + DHOLD flag clear bit + + 9 + 1 + read-write + + + B_0x0 + DHOLD not cleared + 0x0 + + + B_0x1 + DHOLD cleared + 0x1 + + + + + DBCKENDC + DBCKEND flag clear bit + + 10 + 1 + read-write + + + B_0x0 + DBCKEND not cleared + 0x0 + + + B_0x1 + DBCKEND cleared + 0x1 + + + + + DABORTC + DABORT flag clear bit + + 11 + 1 + read-write + + + B_0x0 + DABORT not cleared + 0x0 + + + B_0x1 + DABORT cleared + 0x1 + + + + + BUSYD0ENDC + BUSYD0END flag clear bit + + 21 + 1 + read-write + + + B_0x0 + BUSYD0END not cleared + 0x0 + + + B_0x1 + BUSYD0END cleared + 0x1 + + + + + SDIOITC + SDIOIT flag clear bit + + 22 + 1 + read-write + + + B_0x0 + SDIOIT not cleared + 0x0 + + + B_0x1 + SDIOIT cleared + 0x1 + + + + + ACKFAILC + ACKFAIL flag clear bit + + 23 + 1 + read-write + + + B_0x0 + ACKFAIL not cleared + 0x0 + + + B_0x1 + ACKFAIL cleared + 0x1 + + + + + ACKTIMEOUTC + ACKTIMEOUT flag clear bit + + 24 + 1 + read-write + + + B_0x0 + ACKTIMEOUT not cleared + 0x0 + + + B_0x1 + ACKTIMEOUT cleared + 0x1 + + + + + VSWENDC + VSWEND flag clear bit + + 25 + 1 + read-write + + + B_0x0 + VSWEND not cleared + 0x0 + + + B_0x1 + VSWEND cleared + 0x1 + + + + + CKSTOPC + CKSTOP flag clear bit + + 26 + 1 + read-write + + + B_0x0 + CKSTOP not cleared + 0x0 + + + B_0x1 + CKSTOP cleared + 0x1 + + + + + IDMATEC + IDMA transfer error clear bit + + 27 + 1 + read-write + + + B_0x0 + IDMATE not cleared + 0x0 + + + B_0x1 + IDMATE cleared + 0x1 + + + + + IDMABTCC + IDMA buffer transfer complete clear bit + + 28 + 1 + read-write + + + B_0x0 + IDMABTC not cleared + 0x0 + + + B_0x1 + IDMABTC cleared + 0x1 + + + + + + + SDMMC_MASKR + SDMMC_MASKR + SDMMC mask register + 0x03C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCRCFAILIE + Command CRC fail interrupt enable + + 0 + 1 + read-write + + + B_0x0 + Command CRC fail interrupt disabled + 0x0 + + + B_0x1 + Command CRC fail interrupt enabled + 0x1 + + + + + DCRCFAILIE + Data CRC fail interrupt enable + + 1 + 1 + read-write + + + B_0x0 + Data CRC fail interrupt disabled + 0x0 + + + B_0x1 + Data CRC fail interrupt enabled + 0x1 + + + + + CTIMEOUTIE + Command timeout interrupt enable + + 2 + 1 + read-write + + + B_0x0 + Command timeout interrupt disabled + 0x0 + + + B_0x1 + Command timeout interrupt enabled + 0x1 + + + + + DTIMEOUTIE + Data timeout interrupt enable + + 3 + 1 + read-write + + + B_0x0 + Data timeout interrupt disabled + 0x0 + + + B_0x1 + Data timeout interrupt enabled + 0x1 + + + + + TXUNDERRIE + Tx FIFO underrun error interrupt enable + + 4 + 1 + read-write + + + B_0x0 + Tx FIFO underrun error interrupt disabled + 0x0 + + + B_0x1 + Tx FIFO underrun error interrupt enabled + 0x1 + + + + + RXOVERRIE + Rx FIFO overrun error interrupt enable + + 5 + 1 + read-write + + + B_0x0 + Rx FIFO overrun error interrupt disabled + 0x0 + + + B_0x1 + Rx FIFO overrun error interrupt enabled + 0x1 + + + + + CMDRENDIE + Command response received interrupt enable + + 6 + 1 + read-write + + + B_0x0 + Command response received interrupt disabled + 0x0 + + + B_0x1 + command Response received interrupt enabled + 0x1 + + + + + CMDSENTIE + Command sent interrupt enable + + 7 + 1 + read-write + + + B_0x0 + Command sent interrupt disabled + 0x0 + + + B_0x1 + Command sent interrupt enabled + 0x1 + + + + + DATAENDIE + Data end interrupt enable + + 8 + 1 + read-write + + + B_0x0 + Data end interrupt disabled + 0x0 + + + B_0x1 + Data end interrupt enabled + 0x1 + + + + + DHOLDIE + Data hold interrupt enable + + 9 + 1 + read-write + + + B_0x0 + Data hold interrupt disabled + 0x0 + + + B_0x1 + Data hold interrupt enabled + 0x1 + + + + + DBCKENDIE + Data block end interrupt enable + + 10 + 1 + read-write + + + B_0x0 + Data block end interrupt disabled + 0x0 + + + B_0x1 + Data block end interrupt enabled + 0x1 + + + + + DABORTIE + Data transfer aborted interrupt enable + + 11 + 1 + read-write + + + B_0x0 + Data transfer abort interrupt disabled + 0x0 + + + B_0x1 + Data transfer abort interrupt enabled + 0x1 + + + + + TXFIFOHEIE + Tx FIFO half empty interrupt enable + + 14 + 1 + read-write + + + B_0x0 + Tx FIFO half empty interrupt disabled + 0x0 + + + B_0x1 + Tx FIFO half empty interrupt enabled + 0x1 + + + + + RXFIFOHFIE + Rx FIFO half full interrupt enable + + 15 + 1 + read-write + + + B_0x0 + Rx FIFO half full interrupt disabled + 0x0 + + + B_0x1 + Rx FIFO half full interrupt enabled + 0x1 + + + + + RXFIFOFIE + Rx FIFO full interrupt enable + + 17 + 1 + read-write + + + B_0x0 + Rx FIFO full interrupt disabled + 0x0 + + + B_0x1 + Rx FIFO full interrupt enabled + 0x1 + + + + + TXFIFOEIE + Tx FIFO empty interrupt enable + + 18 + 1 + read-write + + + B_0x0 + Tx FIFO empty interrupt disabled + 0x0 + + + B_0x1 + Tx FIFO empty interrupt enabled + 0x1 + + + + + BUSYD0ENDIE + BUSYD0END interrupt enable + + 21 + 1 + read-write + + + B_0x0 + BUSYD0END interrupt disabled + 0x0 + + + B_0x1 + BUSYD0END interrupt enabled + 0x1 + + + + + SDIOITIE + SDIO mode interrupt received interrupt enable + + 22 + 1 + read-write + + + B_0x0 + SDIO Mode interrupt received interrupt disabled + 0x0 + + + B_0x1 + SDIO Mode interrupt received interrupt enabled + 0x1 + + + + + ACKFAILIE + Acknowledgment Fail interrupt enable + + 23 + 1 + read-write + + + B_0x0 + Acknowledgment Fail interrupt disabled + 0x0 + + + B_0x1 + Acknowledgment Fail interrupt enabled + 0x1 + + + + + ACKTIMEOUTIE + Acknowledgment timeout interrupt enable + + 24 + 1 + read-write + + + B_0x0 + Acknowledgment timeout interrupt disabled + 0x0 + + + B_0x1 + Acknowledgment timeout interrupt enabled + 0x1 + + + + + VSWENDIE + Voltage switch critical timing section completion interrupt enable + + 25 + 1 + read-write + + + B_0x0 + Voltage switch critical timing section completion interrupt disabled + 0x0 + + + B_0x1 + Voltage switch critical timing section completion interrupt enabled + 0x1 + + + + + CKSTOPIE + Voltage Switch clock stopped interrupt enable + + 26 + 1 + read-write + + + B_0x0 + Voltage Switch clock stopped interrupt disabled + 0x0 + + + B_0x1 + Voltage Switch clock stopped interrupt enabled + 0x1 + + + + + IDMABTCIE + IDMA buffer transfer complete interrupt enable + + 28 + 1 + read-write + + + B_0x0 + IDMA buffer transfer complete interrupt disabled + 0x0 + + + B_0x1 + IDMA buffer transfer complete interrupt enabled + 0x1 + + + + + + + SDMMC_ACKTIMER + SDMMC_ACKTIMER + SDMMC acknowledgment timer register + 0x040 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ACKTIME + Boot acknowledgment timeout period + + 0 + 25 + read-write + + + + + SDMMC_IDMACTRLR + SDMMC_IDMACTRLR + SDMMC DMA control register + 0x050 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IDMAEN + IDMA enable + + 0 + 1 + read-write + + + B_0x0 + IDMA disabled + 0x0 + + + B_0x1 + IDMA enabled + 0x1 + + + + + IDMABMODE + Buffer mode selection + + 1 + 1 + read-write + + + B_0x0 + Single buffer mode. + 0x0 + + + B_0x1 + Linked list mode. + 0x1 + + + + + + + SDMMC_IDMABSIZER + SDMMC_IDMABSIZER + SDMMC IDMA buffer size register + 0x054 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IDMABNDT + Number of bytes per buffer + + 5 + 12 + read-write + + + + + SDMMC_IDMABASER + SDMMC_IDMABASER + SDMMC IDMA buffer base address register + 0x058 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IDMABASE + Buffer memory base address bits [31:2], must be word aligned (bit [1:0] are always 0 and read only) + + 0 + 32 + read-write + + + + + SDMMC_IDMALAR + SDMMC_IDMALAR + SDMMC IDMA linked list address register + 0x064 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IDMALA + Word aligned linked list item address offset + + 2 + 14 + read-write + + + ABR + Acknowledge linked list buffer ready + + 29 + 1 + read-write + + + B_0x0 + Loaded linked list buffer is not ready (this causes a linked list IDMA transfer error to be generated). + 0x0 + + + B_0x1 + Loaded linked list buffer ready acknowledge. + 0x1 + + + + + ULS + Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR. + 30 + 1 + read-write + + + B_0x0 + SDMMC_IDMABSIZER is not to be updated from next linked list table. + 0x0 + + + B_0x1 + SDMMC_IDMABSIZER is to be updated from next linked list table. + 0x1 + + + + + ULA + Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR. + 31 + 1 + read-write + + + B_0x0 + SDMMC_IDMALAR is not to be updated, last linked list item. + 0x0 + + + B_0x1 + SDMMC_IDMALAR is to be updated from linked list table. + 0x1 + + + + + + + SDMMC_IDMABAR + SDMMC_IDMABAR + SDMMC IDMA linked list memory base register + 0x068 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IDMABA + Word aligned Linked list memory base address + + 2 + 30 + read-write + + + + + SDMMC_FIFOR0 + SDMMC_FIFOR0 + SDMMC data FIFO registers 0 + 0x80 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FIFODATA + Receive and transmit FIFO data + + 0 + 32 + read-write + + + + + SDMMC_FIFOR1 + SDMMC_FIFOR1 + SDMMC data FIFO registers 1 + 0x84 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FIFODATA + Receive and transmit FIFO data + + 0 + 32 + read-write + + + + + SDMMC_FIFOR2 + SDMMC_FIFOR2 + SDMMC data FIFO registers 2 + 0x88 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FIFODATA + Receive and transmit FIFO data + + 0 + 32 + read-write + + + + + SDMMC_FIFOR3 + SDMMC_FIFOR3 + SDMMC data FIFO registers 3 + 0x8C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FIFODATA + Receive and transmit FIFO data + + 0 + 32 + read-write + + + + + SDMMC_FIFOR4 + SDMMC_FIFOR4 + SDMMC data FIFO registers 4 + 0x90 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FIFODATA + Receive and transmit FIFO data + + 0 + 32 + read-write + + + + + SDMMC_FIFOR5 + SDMMC_FIFOR5 + SDMMC data FIFO registers 5 + 0x94 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FIFODATA + Receive and transmit FIFO data + + 0 + 32 + read-write + + + + + SDMMC_FIFOR6 + SDMMC_FIFOR6 + SDMMC data FIFO registers 6 + 0x98 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FIFODATA + Receive and transmit FIFO data + + 0 + 32 + read-write + + + + + SDMMC_FIFOR7 + SDMMC_FIFOR7 + SDMMC data FIFO registers 7 + 0x9C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FIFODATA + Receive and transmit FIFO data + + 0 + 32 + read-write + + + + + SDMMC_FIFOR8 + SDMMC_FIFOR8 + SDMMC data FIFO registers 8 + 0xA0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FIFODATA + Receive and transmit FIFO data + + 0 + 32 + read-write + + + + + SDMMC_FIFOR9 + SDMMC_FIFOR9 + SDMMC data FIFO registers 9 + 0xA4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FIFODATA + Receive and transmit FIFO data + + 0 + 32 + read-write + + + + + SDMMC_FIFOR10 + SDMMC_FIFOR10 + SDMMC data FIFO registers 10 + 0xA8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FIFODATA + Receive and transmit FIFO data + + 0 + 32 + read-write + + + + + SDMMC_FIFOR11 + SDMMC_FIFOR11 + SDMMC data FIFO registers 11 + 0xAC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FIFODATA + Receive and transmit FIFO data + + 0 + 32 + read-write + + + + + SDMMC_FIFOR12 + SDMMC_FIFOR12 + SDMMC data FIFO registers 12 + 0xB0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FIFODATA + Receive and transmit FIFO data + + 0 + 32 + read-write + + + + + SDMMC_FIFOR13 + SDMMC_FIFOR13 + SDMMC data FIFO registers 13 + 0xB4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FIFODATA + Receive and transmit FIFO data + + 0 + 32 + read-write + + + + + SDMMC_FIFOR14 + SDMMC_FIFOR14 + SDMMC data FIFO registers 14 + 0xB8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FIFODATA + Receive and transmit FIFO data + + 0 + 32 + read-write + + + + + SDMMC_FIFOR15 + SDMMC_FIFOR15 + SDMMC data FIFO registers 15 + 0xBC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FIFODATA + Receive and transmit FIFO data + + 0 + 32 + read-write + + + + + + + SDMMC_S + 0X56008000 + + + SPI + SPI address block description + SPI + 0x40013000 + + 0x0 + 0x54 + registers + + + SPI1 + SPI1 global interrupt + 55 + + + + SPI_CR1 + SPI_CR1 + SPI/I2S control register 1 + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SPE + serial peripheral enable + + 0 + 1 + read-write + + + B_0x0 + Serial peripheral disabled. + 0x0 + + + B_0x1 + Serial peripheral enabled + 0x1 + + + + + MASRX + master automatic suspension in Receive mode + + 8 + 1 + read-write + + + B_0x0 + SPI flow/clock generation is continuous, regardless of overrun condition. + 0x0 + + + B_0x1 + SPI flow is suspended temporary on RxFIFO full condition, before reaching overrun condition. + 0x1 + + + + + CSTART + master transfer start + + 9 + 1 + read-write + + + B_0x0 + master transfer is at idle + 0x0 + + + B_0x1 + master transfer is ongoing or temporary suspended by automatic suspend + 0x1 + + + + + CSUSP + master suspend request + + 10 + 1 + write-only + + + HDDIR + Rx/Tx direction at half-duplex mode + + 11 + 1 + read-write + + + B_0x0 + SPI is receiver + 0x0 + + + B_0x1 + SPI is transmitter + 0x1 + + + + + SSI + internal SS signal input level + + 12 + 1 + read-write + + + CRC33_17 + 32-bit CRC polynomial configuration + 13 + 1 + read-write + + + B_0x0 + Full size (33-bit or 17-bit) CRC polynomial is not used + 0x0 + + + B_0x1 + Full size (33-bit or 17-bit) CRC polynomial is used + 0x1 + + + + + RCRCINI + CRC calculation initialization pattern control for receiver + 14 + 1 + read-write + + + B_0x0 + All zero pattern is applied + 0x0 + + + B_0x1 + All ones pattern is applied + 0x1 + + + + + TCRCINI + CRC calculation initialization pattern control for transmitter + 15 + 1 + read-write + + + B_0x0 + all zero pattern is applied + 0x0 + + + B_0x1 + all ones pattern is applied + 0x1 + + + + + IOLOCK + locking the AF configuration of associated I/Os + + 16 + 1 + read-write + + + B_0x0 + AF configuration is not locked + 0x0 + + + B_0x1 + AF configuration is locked + 0x1 + + + + + + + SPI_CR2 + SPI_CR2 + SPI/I2S control register 2 + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TSIZE + number of data at current transfer + + 0 + 16 + read-write + + + + + SPI_CFG1 + SPI_CFG1 + SPI/I2S configuration register 1 + 0x08 + 0x20 + read-write + 0x00070007 + 0xFFFFFFFF + + + DSIZE + number of bits in a single SPI data frame + + 0 + 5 + read-write + + + B_0x0 + not used + 0x0 + + + B_0x1 + not used + 0x1 + + + B_0x2 + not used + 0x2 + + + B_0x3 + 4 bits + 0x3 + + + B_0x4 + 5 bits + 0x4 + + + B_0x5 + 6 bits + 0x5 + + + B_0x6 + 7 bits + 0x6 + + + B_0x7 + 8 bits + 0x7 + + + B_0x1D + 30 bits + 0x1D + + + B_0x1E + 31 bits + 0x1E + + + B_0x1F + 32 bits + 0x1F + + + + + FTHLV + FIFO threshold level + + 5 + 4 + read-write + + + B_0x0 + 1-data + 0x0 + + + B_0x1 + 2-data + 0x1 + + + B_0x2 + 3-data + 0x2 + + + B_0x3 + 4-data + 0x3 + + + B_0x4 + 5-data + 0x4 + + + B_0x5 + 6-data + 0x5 + + + B_0x6 + 7-data + 0x6 + + + B_0x7 + 8-data + 0x7 + + + B_0x8 + 9-data + 0x8 + + + B_0x9 + 10-data + 0x9 + + + B_0xA + 11-data + 0xA + + + B_0xB + 12-data + 0xB + + + B_0xC + 13-data + 0xC + + + B_0xD + 14-data + 0xD + + + B_0xE + 15-data + 0xE + + + B_0xF + 16-data + 0xF + + + + + UDRCFG + behavior of slave transmitter at underrun condition + + 9 + 1 + read-write + + + B_0x0 + slave sends a constant pattern defined by the user at the SPI_UDRDR register + 0x0 + + + B_0x1 + Slave repeats lastly received data from master. + 0x1 + + + + + RXDMAEN + Rx DMA stream enable + 14 + 1 + read-write + + + B_0x0 + Rx-DMA disabled + 0x0 + + + B_0x1 + Rx-DMA enabled + 0x1 + + + + + TXDMAEN + Tx DMA stream enable + 15 + 1 + read-write + + + B_0x0 + Tx DMA disabled + 0x0 + + + B_0x1 + Tx DMA enabled + 0x1 + + + + + CRCSIZE + length of CRC frame to be transacted and compared + + 16 + 5 + read-write + + + B_0x3 + 4-bits + 0x3 + + + B_0x4 + 5-bits + 0x4 + + + B_0x5 + 6-bits + 0x5 + + + B_0x6 + 7-bits + 0x6 + + + B_0x7 + 8-bits + 0x7 + + + B_0x1D + 30-bits + 0x1D + + + B_0x1E + 31-bits + 0x1E + + + B_0x1F + 32-bits + 0x1F + + + + + CRCEN + hardware CRC computation enable + 22 + 1 + read-write + + + B_0x0 + CRC calculation disabled + 0x0 + + + B_0x1 + CRC calculation enabled + 0x1 + + + + + MBR + master baud rate prescaler setting + + 28 + 3 + read-write + + + B_0x0 + SPI master clock/2 + 0x0 + + + B_0x1 + SPI master clock/4 + 0x1 + + + B_0x2 + SPI master clock/8 + 0x2 + + + B_0x3 + SPI master clock/16 + 0x3 + + + B_0x4 + SPI master clock/32 + 0x4 + + + B_0x5 + SPI master clock/64 + 0x5 + + + B_0x6 + SPI master clock/128 + 0x6 + + + B_0x7 + SPI master clock/256 + 0x7 + + + + + BPASS + bypass of the prescaler at master baud rate clock generator + 31 + 1 + read-write + + + B_0x0 + bypass is disabled + 0x0 + + + B_0x1 + bypass is enabled + 0x1 + + + + + + + SPI_CFG2 + SPI_CFG2 + SPI/I2S configuration register 2 + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + MSSI + Master SS Idleness + + 0 + 4 + read-write + + + B_0x0 + no extra delay + 0x0 + + + B_0x1 + 1 clock cycle period delay added + 0x1 + + + B_0xF + 15 clock cycle periods delay added + 0xF + + + + + MIDI + master Inter-Data Idleness + + 4 + 4 + read-write + + + B_0x0 + no delay + 0x0 + + + B_0x1 + 1 clock cycle period delay + 0x1 + + + B_0xF + 15 clock cycle periods delay + 0xF + + + + + RDIOM + RDY signal input/output management + + 13 + 1 + read-write + + + B_0x0 + RDY signal is defined internally fixed as permanently active (RDIOP setting has no effect) + 0x0 + + + B_0x1 + RDY signal is overtaken from alternate function input (at master case) or output (at slave case) of the dedicated pin (RDIOP setting takes effect) + 0x1 + + + + + RDIOP + RDY signal input/output polarity + 14 + 1 + read-write + + + B_0x0 + high level of the signal means the slave is ready for communication + 0x0 + + + B_0x1 + low level of the signal means the slave is ready for communication + 0x1 + + + + + IOSWP + swap functionality of MISO and MOSI pins + + 15 + 1 + read-write + + + B_0x0 + no swap + 0x0 + + + B_0x1 + MOSI and MISO are swapped + 0x1 + + + + + COMM + SPI Communication Mode + 17 + 2 + read-write + + + B_0x0 + full-duplex + 0x0 + + + B_0x1 + simplex transmitter + 0x1 + + + B_0x2 + simplex receiver + 0x2 + + + B_0x3 + half-duplex + 0x3 + + + + + SP + serial protocol + + 19 + 3 + read-write + + + B_0x0 + SPI Motorola + 0x0 + + + B_0x1 + SPI TI + 0x1 + + + + + MASTER + SPI master + 22 + 1 + read-write + + + B_0x0 + SPI slave + 0x0 + + + B_0x1 + SPI master + 0x1 + + + + + LSBFRST + data frame format + + 23 + 1 + read-write + + + B_0x0 + MSB transmitted first + 0x0 + + + B_0x1 + LSB transmitted first + 0x1 + + + + + CPHA + clock phase + 24 + 1 + read-write + + + B_0x0 + the first clock transition is the first data capture edge + 0x0 + + + B_0x1 + the second clock transition is the first data capture edge + 0x1 + + + + + CPOL + clock polarity + 25 + 1 + read-write + + + B_0x0 + SCK signal is at 0 when idle + 0x0 + + + B_0x1 + SCK signal is at 1 when idle + 0x1 + + + + + SSM + software management of SS signal input + + 26 + 1 + read-write + + + B_0x0 + SS input value is determined by the SS PAD + 0x0 + + + B_0x1 + SS input value is determined by the SSI bit + 0x1 + + + + + SSIOP + SS input/output polarity + 28 + 1 + read-write + + + B_0x0 + low level is active for SS signal + 0x0 + + + B_0x1 + high level is active for SS signal + 0x1 + + + + + SSOE + SS output enable + + 29 + 1 + read-write + + + B_0x0 + SS output is disabled and the SPI can work in multimaster configuration + 0x0 + + + B_0x1 + SS output is enabled. + 0x1 + + + + + SSOM + SS output management in master mode + + 30 + 1 + read-write + + + B_0x0 + SS is kept at active level till data transfer is completed, it becomes inactive with EOT flag + 0x0 + + + B_0x1 + SPI data frames are interleaved with SS non active pulses when MIDI[3:0]>1 + 0x1 + + + + + AFCNTR + alternate function GPIOs control + + 31 + 1 + read-write + + + B_0x0 + The peripheral takes no control of GPIOs while it is disabled + 0x0 + + + B_0x1 + The peripheral keeps always control of all associated GPIOs + 0x1 + + + + + + + SPI_IER + SPI_IER + SPI/I2S interrupt enable register + 0x10 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RXPIE + RXP interrupt enable + 0 + 1 + read-write + + + B_0x0 + RXP interrupt disabled + 0x0 + + + B_0x1 + RXP interrupt enabled + 0x1 + + + + + TXPIE + TXP interrupt enable + + 1 + 1 + read-write + + + B_0x0 + TXP interrupt disabled + 0x0 + + + B_0x1 + TXP interrupt enabled + 0x1 + + + + + DXPIE + DXP interrupt enabled + + 2 + 1 + read-write + + + B_0x0 + DXP interrupt disabled + 0x0 + + + B_0x1 + DXP interrupt enabled + 0x1 + + + + + EOTIE + EOT, SUSP and TXC interrupt enable + 3 + 1 + read-write + + + B_0x0 + EOT/SUSP/TXC interrupt disabled + 0x0 + + + B_0x1 + EOT/SUSP/TXC interrupt enabled + 0x1 + + + + + TXTFIE + TXTFIE interrupt enable + 4 + 1 + read-write + + + B_0x0 + TXTF interrupt disabled + 0x0 + + + B_0x1 + TXTF interrupt enabled + 0x1 + + + + + UDRIE + UDR interrupt enable + 5 + 1 + read-write + + + B_0x0 + UDR interrupt disabled + 0x0 + + + B_0x1 + UDR interrupt enabled + 0x1 + + + + + OVRIE + OVR interrupt enable + 6 + 1 + read-write + + + B_0x0 + OVR interrupt disabled + 0x0 + + + B_0x1 + OVR interrupt enabled + 0x1 + + + + + CRCEIE + CRC error interrupt enable + 7 + 1 + read-write + + + B_0x0 + CRC interrupt disabled + 0x0 + + + B_0x1 + CRC interrupt enabled + 0x1 + + + + + TIFREIE + TIFRE interrupt enable + 8 + 1 + read-write + + + B_0x0 + TIFRE interrupt disabled + 0x0 + + + B_0x1 + TIFRE interrupt enabled + 0x1 + + + + + MODFIE + mode Fault interrupt enable + 9 + 1 + read-write + + + B_0x0 + MODF interrupt disabled + 0x0 + + + B_0x1 + MODF interrupt enabled + 0x1 + + + + + + + SPI_SR + SPI_SR + SPI/I2S status register + 0x14 + 0x20 + read-only + 0x00001002 + 0xFFFFFFFF + + + RXP + Rx-packet available + + 0 + 1 + read-only + + + B_0x0 + RxFIFO is empty or an incomplete data packet is received + 0x0 + + + B_0x1 + RxFIFO contains at least one data packet + 0x1 + + + + + TXP + Tx-packet space available + + 1 + 1 + read-only + + + B_0x0 + not enough free space at TxFIFO to host next data packet + 0x0 + + + B_0x1 + enough free space at TxFIFO to host at least one data packet + 0x1 + + + + + DXP + duplex packet + + 2 + 1 + read-only + + + B_0x0 + TxFIFO is Full and/or RxFIFO is Empty + 0x0 + + + B_0x1 + both TxFIFO has space for write and RxFIFO contains for read a single packet at least + 0x1 + + + + + EOT + end of transfer + + 3 + 1 + read-only + + + B_0x0 + transfer is ongoing or not started + 0x0 + + + B_0x1 + transfer complete + 0x1 + + + + + TXTF + transmission transfer filled + + 4 + 1 + read-only + + + B_0x0 + upload of TxFIFO is ongoing or not started + 0x0 + + + B_0x1 + TxFIFO upload is finished + 0x1 + + + + + UDR + underrun + + 5 + 1 + read-only + + + B_0x0 + no underrun + 0x0 + + + B_0x1 + underrun detected + 0x1 + + + + + OVR + overrun + + 6 + 1 + read-only + + + B_0x0 + no overrun + 0x0 + + + B_0x1 + overrun detected + 0x1 + + + + + CRCE + CRC error + + 7 + 1 + read-only + + + B_0x0 + no CRC error + 0x0 + + + B_0x1 + CRC error detected + 0x1 + + + + + TIFRE + TI frame format error + + 8 + 1 + read-only + + + B_0x0 + no TI Frame Error + 0x0 + + + B_0x1 + TI frame error detected + 0x1 + + + + + MODF + mode fault + + 9 + 1 + read-only + + + B_0x0 + no mode fault + 0x0 + + + B_0x1 + mode fault detected. + 0x1 + + + + + SUSP + suspension status + + 11 + 1 + read-only + + + B_0x0 + SPI not suspended (master mode active or other mode). + 0x0 + + + B_0x1 + Master mode is suspended (current frame completed). + 0x1 + + + + + TXC + TxFIFO transmission complete + + 12 + 1 + read-only + + + B_0x0 + current data transaction is still ongoing, data is available in TxFIFO or last frame transmission is on going. + 0x0 + + + B_0x1 + last TxFIFO frame transmission complete + 0x1 + + + + + RXPLVL + RxFIFO packing level + + 13 + 2 + read-only + + + B_0x0 + no next frame is available at RxFIFO + 0x0 + + + B_0x1 + 1 frame is available + 0x1 + + + B_0x2 + 2 frames are available* + 0x2 + + + B_0x3 + 3 frames are available* + 0x3 + + + + + RXWNE + RxFIFO word not empty + + 15 + 1 + read-only + + + B_0x0 + less than four bytes of RxFIFO space is occupied by data + 0x0 + + + B_0x1 + at least four bytes of RxFIFO space is occupied by data + 0x1 + + + + + CTSIZE + number of data frames remaining in current TSIZE session + + 16 + 16 + read-only + + + + + SPI_IFCR + SPI_IFCR + SPI/I2S interrupt/status flags clear register + 0x18 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + EOTC + end of transfer flag clear + + 3 + 1 + write-only + + + TXTFC + transmission transfer filled flag clear + + 4 + 1 + write-only + + + UDRC + underrun flag clear + + 5 + 1 + write-only + + + OVRC + overrun flag clear + + 6 + 1 + write-only + + + CRCEC + CRC error flag clear + + 7 + 1 + write-only + + + TIFREC + TI frame format error flag clear + + 8 + 1 + write-only + + + MODFC + mode fault flag clear + + 9 + 1 + write-only + + + SUSPC + Suspend flag clear + + 11 + 1 + write-only + + + + + SPI_TXDR + SPI_TXDR + /I2SSPI/I2S transmit data register + 0x20 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + TXDR + transmit data register + + 0 + 32 + write-only + + + + + SPI_RXDR + SPI_RXDR + SPI/I2S receive data register + 0x30 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RXDR + receive data register + + 0 + 32 + read-only + + + + + SPI_CRCPOLY + SPI_CRCPOLY + SPI/I2S polynomial register + 0x40 + 0x20 + read-write + 0x00000107 + 0xFFFFFFFF + + + CRCPOLY + CRC polynomial register + + 0 + 32 + read-write + + + + + SPI_TXCRC + SPI_TXCRC + SPI/I2S transmitter CRC register + 0x44 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + TXCRC + CRC register for transmitter + + 0 + 32 + read-only + + + + + SPI_RXCRC + SPI_RXCRC + SPI/I2S receiver CRC register + 0x48 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RXCRC + CRC register for receiver + + 0 + 32 + read-only + + + + + SPI_UDRDR + SPI_UDRDR + SPI underrun data register + 0x4C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UDRDR + data at slave underrun condition + + 0 + 32 + read-write + + + + + SPI_I2SCFGR + SPI_I2SCFGR + SPI/I2S configuration register + 0x50 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + I2SMOD + I2S mode selection + 0 + 1 + read-write + + + B_0x0 + SPI mode is selected + 0x0 + + + B_0x1 + I2S/PCM mode is selected + 0x1 + + + + + I2SCFG + I2S configuration mode + + 1 + 3 + read-write + + + B_0x0 + slave - transmit + 0x0 + + + B_0x1 + slave - receive + 0x1 + + + B_0x2 + master - transmit + 0x2 + + + B_0x3 + master - receive + 0x3 + + + B_0x4 + slave - Full Duplex + 0x4 + + + B_0x5 + master - Full Duplex + 0x5 + + + + + I2SSTD + Iless thansup>2less than/sup>S standard selection + + 4 + 2 + read-write + + + B_0x0 + Iless thansup>2less than/sup>S Philips standard. + 0x0 + + + B_0x1 + MSB justified standard (left justified) + 0x1 + + + B_0x2 + LSB justified standard (right justified) + 0x2 + + + B_0x3 + PCM standard + 0x3 + + + + + PCMSYNC + PCM frame synchronization + 7 + 1 + read-write + + + B_0x0 + short frame synchronization + 0x0 + + + B_0x1 + long frame synchronization + 0x1 + + + + + DATLEN + data length to be transferred. + 8 + 2 + read-write + + + B_0x0 + 16-bit data length + 0x0 + + + B_0x1 + 24-bit data length + 0x1 + + + B_0x2 + 32-bit data length + 0x2 + + + B_0x3 + Not allowed + 0x3 + + + + + CHLEN + channel length (number of bits per audio channel) + 10 + 1 + read-write + + + B_0x0 + 16-bit wide + 0x0 + + + B_0x1 + 32-bit wide + 0x1 + + + + + CKPOL + serial audio clock polarity + 11 + 1 + read-write + + + B_0x0 + the signals generated by the SPI/I2S (i. + 0x0 + + + B_0x1 + the signals generated by the SPI/I2S (i. + 0x1 + + + + + FIXCH + fixed channel length in slave + 12 + 1 + read-write + + + B_0x0 + the channel length in slave mode is different from 16 or 32 bits (CHLEN must be set) + 0x0 + + + B_0x1 + the channel length in slave mode is supposed to be 16 or 32 bits (according to CHLEN) + 0x1 + + + + + WSINV + word select inversion + + 13 + 1 + read-write + + + B_0x0 + In I2S Philips standard, the left channel transfer starts one CK cycle after the WS falling edge, and the right channel one CK cycle after the WS rising edge. + 0x0 + + + B_0x1 + In I2S Philips standard, the left channel transfer starts one CK cycle after the WS rising edge, and the right channel one CK cycle after the WS falling edge. + 0x1 + + + + + DATFMT + data format + 14 + 1 + read-write + + + B_0x0 + The data inside the SPI_RXDR or SPI_TXDR are right aligned + 0x0 + + + B_0x1 + The data inside the SPI_RXDR or SPI_TXDR are left aligned. + 0x1 + + + + + I2SDIV + Iless thansup>2less than/sup>S linear prescaler + + 16 + 8 + read-write + + + ODD + odd factor for the prescaler + + 24 + 1 + read-write + + + B_0x0 + Real divider value is = I2SDIV *2 + 0x0 + + + B_0x1 + Real divider value is = (I2SDIV * 2) + 1 + 0x1 + + + + + MCKOE + master clock output enable + 25 + 1 + read-write + + + B_0x0 + Master clock output is disabled + 0x0 + + + B_0x1 + Master clock output is enabled + 0x1 + + + + + + + + + SPI_S + 0X50013000 + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global interrupt + 56 + + + + SPI2_S + 0x50003800 + + + SPI3 + 0x40003C00 + + SPI3 + SPI3 global interrupt + 57 + + + + SPI3_S + 0x50003C00 + + + SPI4 + 0x40014C00 + + SPI4 + SPI4 global interrupt + 82 + + + + SPI4_S + 0x50014C00 + + + TAMP + TAMP register block + TAMP + 0x44007c00 + + 0x0 + 0x400 + registers + + + TAMP + Tamper global interrupts + 4 + + + + TAMP_CR1 + TAMP_CR1 + TAMP control register 1 + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TAMP1E + Tamper detection on TAMP_IN1 enable + 0 + 1 + read-write + + + B_0x0 + Tamper detection on TAMP_IN1 is disabled. + 0x0 + + + B_0x1 + Tamper detection on TAMP_IN1 is enabled. + 0x1 + + + + + TAMP2E + Tamper detection on TAMP_IN2 enableless thansup>(1)less than/sup> + 1 + 1 + read-write + + + B_0x0 + Tamper detection on TAMP_IN2 is disabled. + 0x0 + + + B_0x1 + Tamper detection on TAMP_IN2 is enabled. + 0x1 + + + + + TAMP3E + Tamper detection on TAMP_IN3 enableless thansup>(1)less than/sup> + 2 + 1 + read-write + + + B_0x0 + Tamper detection on TAMP_IN3 is disabled. + 0x0 + + + B_0x1 + Tamper detection on TAMP_IN3 is enabled. + 0x1 + + + + + TAMP4E + Tamper detection on TAMP_IN4 enableless thansup>(1)less than/sup> + 3 + 1 + read-write + + + B_0x0 + Tamper detection on TAMP_IN4 is disabled. + 0x0 + + + B_0x1 + Tamper detection on TAMP_IN4 is enabled. + 0x1 + + + + + TAMP5E + Tamper detection on TAMP_IN5 enableless thansup>(1)less than/sup> + 4 + 1 + read-write + + + B_0x0 + Tamper detection on TAMP_IN5 is disabled. + 0x0 + + + B_0x1 + Tamper detection on TAMP_IN5 is enabled. + 0x1 + + + + + TAMP6E + Tamper detection on TAMP_IN6 enableless thansup>(1)less than/sup> + 5 + 1 + read-write + + + B_0x0 + Tamper detection on TAMP_IN6 is disabled. + 0x0 + + + B_0x1 + Tamper detection on TAMP_IN6 is enabled. + 0x1 + + + + + TAMP7E + Tamper detection on TAMP_IN7 enableless thansup>(1)less than/sup> + 6 + 1 + read-write + + + B_0x0 + Tamper detection on TAMP_IN7 is disabled. + 0x0 + + + B_0x1 + Tamper detection on TAMP_IN7 is enabled. + 0x1 + + + + + TAMP8E + Tamper detection on TAMP_IN8 enableless thansup>(1)less than/sup> + 7 + 1 + read-write + + + B_0x0 + Tamper detection on TAMP_IN8 is disabled. + 0x0 + + + B_0x1 + Tamper detection on TAMP_IN8 is enabled. + 0x1 + + + + + ITAMP1E + Internal tamper 1 enable + 16 + 1 + read-write + + + B_0x0 + Internal tamper 1 disabled. + 0x0 + + + B_0x1 + Internal tamper 1 enabled. + 0x1 + + + + + ITAMP2E + Internal tamper 2 enable + 17 + 1 + read-write + + + B_0x0 + Internal tamper 2 disabled. + 0x0 + + + B_0x1 + Internal tamper 2 enabled. + 0x1 + + + + + ITAMP3E + Internal tamper 3 enable + 18 + 1 + read-write + + + B_0x0 + Internal tamper 3 disabled. + 0x0 + + + B_0x1 + Internal tamper 3 enabled. + 0x1 + + + + + ITAMP4E + Internal tamper 4 enable + 19 + 1 + read-write + + + B_0x0 + Internal tamper 4 disabled. + 0x0 + + + B_0x1 + Internal tamper 4 enabled. + 0x1 + + + + + ITAMP5E + Internal tamper 5 enable + 20 + 1 + read-write + + + B_0x0 + Internal tamper 5 disabled. + 0x0 + + + B_0x1 + Internal tamper 5 enabled. + 0x1 + + + + + ITAMP6E + Internal tamper 6 enable + 21 + 1 + read-write + + + B_0x0 + Internal tamper 6 disabled. + 0x0 + + + B_0x1 + Internal tamper 6 enabled. + 0x1 + + + + + ITAMP7E + Internal tamper 7 enable + 22 + 1 + read-write + + + B_0x0 + Internal tamper 7 disabled. + 0x0 + + + B_0x1 + Internal tamper 7 enabled + 0x1 + + + + + ITAMP8E + Internal tamper 8 enable + 23 + 1 + read-write + + + B_0x0 + Internal tamper 8 disabled. + 0x0 + + + B_0x1 + Internal tamper 8 enabled. + 0x1 + + + + + ITAMP9E + Internal tamper 9 enable + 24 + 1 + read-write + + + B_0x0 + Internal tamper 9 disabled. + 0x0 + + + B_0x1 + Internal tamper 9 enabled. + 0x1 + + + + + ITAMP11E + Internal tamper 11 enable + 26 + 1 + read-write + + + B_0x0 + Internal tamper 11 disabled. + 0x0 + + + B_0x1 + Internal tamper 11 enabled. + 0x1 + + + + + ITAMP12E + Internal tamper 12 enable + 27 + 1 + read-write + + + B_0x0 + Internal tamper 12 disabled. + 0x0 + + + B_0x1 + Internal tamper 12 enabled. + 0x1 + + + + + ITAMP13E + Internal tamper 13 enable + 28 + 1 + read-write + + + B_0x0 + Internal tamper 13 disabled. + 0x0 + + + B_0x1 + Internal tamper 13 enabled. + 0x1 + + + + + ITAMP15E + Internal tamper 15 enable + 30 + 1 + read-write + + + B_0x0 + Internal tamper 15 disabled. + 0x0 + + + B_0x1 + Internal tamper 15 enabled. + 0x1 + + + + + + + TAMP_CR2 + TAMP_CR2 + TAMP control register 2 + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TAMP1POM + Tamper 1 potential mode + 0 + 1 + read-write + + + B_0x0 + Tamper 1 event detection is in confirmed mode. + 0x0 + + + B_0x1 + Tamper 1 event detection is in potential mode. + 0x1 + + + + + TAMP2POM + Tamper 2 potential mode + 1 + 1 + read-write + + + B_0x0 + Tamper 2 event detection is in confirmed modeless thansup>(1)less than/sup>. + 0x0 + + + B_0x1 + Tamper 2 event detection is in potential modeless thansup>(2)less than/sup>. + 0x1 + + + + + TAMP3POM + Tamper 3 potential mode + 2 + 1 + read-write + + + B_0x0 + Tamper 3 event detection is in confirmed modeless thansup>(1)less than/sup>. + 0x0 + + + B_0x1 + Tamper 3 event detection is in potential modeless thansup>(2)less than/sup>. + 0x1 + + + + + TAMP4POM + Tamper 4 potential mode + 3 + 1 + read-write + + + B_0x0 + Tamper 4 event detection is in confirmed modeless thansup>(1)less than/sup>. + 0x0 + + + B_0x1 + Tamper 4 event detection is in potential modeless thansup>(2)less than/sup>. + 0x1 + + + + + TAMP5POM + Tamper 5 potential mode + 4 + 1 + read-write + + + B_0x0 + Tamper 5 event detection is in confirmed modeless thansup>(1)less than/sup>. + 0x0 + + + B_0x1 + Tamper 5 event detection is in potential modeless thansup>(2)less than/sup>. + 0x1 + + + + + TAMP6POM + Tamper 6 potential mode + 5 + 1 + read-write + + + B_0x0 + Tamper 6 event detection is in confirmed modeless thansup>(1)less than/sup>. + 0x0 + + + B_0x1 + Tamper 6 event detection is in potential modeless thansup>(2)less than/sup>. + 0x1 + + + + + TAMP7POM + Tamper 7 potential mode + 6 + 1 + read-write + + + B_0x0 + Tamper 7 event detection is in confirmed modeless thansup>(1)less than/sup>. + 0x0 + + + B_0x1 + Tamper 7 event detection is in potential modeless thansup>(2)less than/sup>. + 0x1 + + + + + TAMP8POM + Tamper 8 potential mode + 7 + 1 + read-write + + + B_0x0 + Tamper 8 event detection is in confirmed modeless thansup>(1)less than/sup>. + 0x0 + + + B_0x1 + Tamper 8 event detection is in potential modeless thansup>(2)less than/sup>. + 0x1 + + + + + TAMP1MSK + Tamper 1 mask + + 16 + 1 + read-write + + + B_0x0 + Tamper 1 event generates a trigger event and TAMP1F must be cleared by software to allow next tamper event detection. + 0x0 + + + B_0x1 + Tamper 1 event generates a trigger event. + 0x1 + + + + + TAMP2MSK + Tamper 2 mask + + 17 + 1 + read-write + + + B_0x0 + Tamper 2 event generates a trigger event and TAMP2F must be cleared by software to allow next tamper event detection. + 0x0 + + + B_0x1 + Tamper 2 event generates a trigger event. + 0x1 + + + + + TAMP3MSK + Tamper 3 mask + + 18 + 1 + read-write + + + B_0x0 + Tamper 3 event generates a trigger event and TAMP3F must be cleared by software to allow next tamper event detection. + 0x0 + + + B_0x1 + Tamper 3 event generates a trigger event. + 0x1 + + + + + BKBLOCK + Backup registers and device secretsless thansup>(1)less than/sup> access blocked + 22 + 1 + read-write + + + B_0x0 + backup registers and device secretsless thansup>(1)less than/sup> can be accessed if no tamper flag is set + 0x0 + + + B_0x1 + backup registers and device secretsless thansup>(1)less than/sup> cannot be accessed + 0x1 + + + + + BKERASE + Backup registers and device secretsless thansup>(1)less than/sup> erase + + 23 + 1 + write-only + + + TAMP1TRG + Active level for tamper 1 input + + 24 + 1 + read-write + + + B_0x0 + If TAMPFLT different to 00 tamper 1 input staying low triggers a tamper detection event. + 0x0 + + + B_0x1 + If TAMPFLT different to 00 tamper 1 input staying high triggers a tamper detection event. + 0x1 + + + + + TAMP2TRG + Active level for tamper 2 input + + 25 + 1 + read-write + + + B_0x0 + If TAMPFLT different to 00 tamper 2 input staying low triggers a tamper detection event. + 0x0 + + + B_0x1 + If TAMPFLT different to 00 tamper 2 input staying high triggers a tamper detection event. + 0x1 + + + + + TAMP3TRG + Active level for tamper 3 input + + 26 + 1 + read-write + + + B_0x0 + If TAMPFLT different to 00 tamper 3 input staying low triggers a tamper detection event. + 0x0 + + + B_0x1 + If TAMPFLT different to 00 tamper 3 input staying high triggers a tamper detection event. + 0x1 + + + + + TAMP4TRG + Active level for tamper 4 input (active mode disabled) + + 27 + 1 + read-write + + + B_0x0 + If TAMPFLT different to 00 tamper 4 input staying low triggers a tamper detection event. + 0x0 + + + B_0x1 + If TAMPFLT different to 00 tamper 4 input staying high triggers a tamper detection event. + 0x1 + + + + + TAMP5TRG + Active level for tamper 5 input (active mode disabled) + + 28 + 1 + read-write + + + B_0x0 + If TAMPFLT different to 00 tamper 5 input staying low triggers a tamper detection event. + 0x0 + + + B_0x1 + If TAMPFLT different to 00 tamper 5 input staying high triggers a tamper detection event. + 0x1 + + + + + TAMP6TRG + Active level for tamper 6 input (active mode disabled) + + 29 + 1 + read-write + + + B_0x0 + If TAMPFLT different to 00 tamper 6 input staying low triggers a tamper detection event. + 0x0 + + + B_0x1 + If TAMPFLT different to 00 tamper 6 input staying high triggers a tamper detection event. + 0x1 + + + + + TAMP7TRG + Active level for tamper 7 input (active mode disabled) + + 30 + 1 + read-write + + + B_0x0 + If TAMPFLT different to 00 tamper 7 input staying low triggers a tamper detection event. + 0x0 + + + B_0x1 + If TAMPFLT different to 00 tamper 7 input staying high triggers a tamper detection event. + 0x1 + + + + + TAMP8TRG + Active level for tamper 8 input (active mode disabled) + + 31 + 1 + read-write + + + B_0x0 + If TAMPFLT different to 00 tamper 8 input staying low triggers a tamper detection event. + 0x0 + + + B_0x1 + If TAMPFLT different to 00 tamper 8 input staying high triggers a tamper detection event. + 0x1 + + + + + + + TAMP_CR3 + TAMP_CR3 + TAMP control register 3 + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ITAMP1POM + Internal tamper 1 potential mode + 0 + 1 + read-write + + + B_0x0 + Internal tamper 1 event detection is in confirmed modeless thansup>(1)less than/sup>. + 0x0 + + + B_0x1 + Internal tamper 1 event detection is in potential modeless thansup>(2)less than/sup>. + 0x1 + + + + + ITAMP2POM + Internal tamper 2 potential mode + 1 + 1 + read-write + + + B_0x0 + Internal tamper 2 event detection is in confirmed modeless thansup>(1)less than/sup>. + 0x0 + + + B_0x1 + Internal tamper 2 event detection is in potential modeless thansup>(2)less than/sup>. + 0x1 + + + + + ITAMP3POM + Internal tamper 3 potential mode + 2 + 1 + read-write + + + B_0x0 + Internal tamper 3 event detection is in confirmed modeless thansup>(1)less than/sup>. + 0x0 + + + B_0x1 + Internal tamper 3 event detection is in potential modeless thansup>(2)less than/sup>. + 0x1 + + + + + ITAMP4POM + Internal tamper 4 potential mode + 3 + 1 + read-write + + + B_0x0 + Internal tamper 4 event detection is in confirmed modeless thansup>(1)less than/sup>. + 0x0 + + + B_0x1 + Internal tamper 4 event detection is in potential modeless thansup>(2)less than/sup>. + 0x1 + + + + + ITAMP5POM + Internal tamper 5 potential mode + 4 + 1 + read-write + + + B_0x0 + Internal tamper 5 event detection is in confirmed modeless thansup>(1)less than/sup>. + 0x0 + + + B_0x1 + Internal tamper 5 event detection is in potential modeless thansup>(2)less than/sup>. + 0x1 + + + + + ITAMP6POM + Internal tamper 6 potential mode + 5 + 1 + read-write + + + B_0x0 + Internal tamper 6 event detection is in confirmed mode. + 0x0 + + + B_0x1 + Internal tamper 6 event detection is in potential mode. + 0x1 + + + + + ITAMP7POM + Internal tamper 7 potential mode + 6 + 1 + read-write + + + B_0x0 + Internal tamper 7 event detection is in confirmed modeless thansup>(1)less than/sup>. + 0x0 + + + B_0x1 + Internal tamper 7 event detection is in potential modeless thansup>(2)less than/sup>. + 0x1 + + + + + ITAMP8POM + Internal tamper 8 potential mode + 7 + 1 + read-write + + + B_0x0 + Internal tamper 8 event detection is in confirmed modeless thansup>(1)less than/sup>. + 0x0 + + + B_0x1 + Internal tamper 8 event detection is in potential modeless thansup>(2)less than/sup>. + 0x1 + + + + + ITAMP9POM + Internal tamper 9 potential mode + 8 + 1 + read-write + + + B_0x0 + Internal tamper 9 event detection is in confirmed modeless thansup>(1)less than/sup>. + 0x0 + + + B_0x1 + Internal tamper 9 event detection is in potential modeless thansup>(2)less than/sup>. + 0x1 + + + + + ITAMP11POM + Internal tamper 11 potential mode + 10 + 1 + read-write + + + B_0x0 + Internal tamper 11 event detection is in confirmed modeless thansup>(1)less than/sup>. + 0x0 + + + B_0x1 + Internal tamper 11 event detection is in potential modeless thansup>(2)less than/sup>. + 0x1 + + + + + ITAMP12POM + Internal tamper 12 potential mode + 11 + 1 + read-write + + + B_0x0 + Internal tamper 12 event detection is in confirmed modeless thansup>(1)less than/sup>. + 0x0 + + + B_0x1 + Internal tamper 12 event detection is in potential modeless thansup>(2)less than/sup>. + 0x1 + + + + + ITAMP13POM + Internal tamper 13 potential mode + 12 + 1 + read-write + + + B_0x0 + Internal tamper 13 event detection is in confirmed modeless thansup>(1)less than/sup>. + 0x0 + + + B_0x1 + Internal tamper 13 event detection is in potential modeless thansup>(2)less than/sup>. + 0x1 + + + + + ITAMP15POM + Internal tamper 15 potential mode + 14 + 1 + read-write + + + B_0x0 + Internal tamper 15 event detection is in confirmed modeless thansup>(1)less than/sup>. + 0x0 + + + B_0x1 + Internal tamper 15 event detection is in potential modeless thansup>(2)less than/sup>. + 0x1 + + + + + + + TAMP_FLTCR + TAMP_FLTCR + TAMP filter control register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TAMPFREQ + Tamper sampling frequency + + 0 + 3 + read-write + + + B_0x0 + RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) + 0x0 + + + B_0x1 + RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) + 0x1 + + + B_0x2 + RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) + 0x2 + + + B_0x3 + RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) + 0x3 + + + B_0x4 + RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) + 0x4 + + + B_0x5 + RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) + 0x5 + + + B_0x6 + RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) + 0x6 + + + B_0x7 + RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + 0x7 + + + + + TAMPFLT + TAMP_INx filter count + + 3 + 2 + read-write + + + B_0x0 + Tamper event is activated on edge of TAMP_INx input transitions to the active level (no internal pull-up on TAMP_INx input). + 0x0 + + + B_0x1 + Tamper event is activated after 2 consecutive samples at the active level. + 0x1 + + + B_0x2 + Tamper event is activated after 4 consecutive samples at the active level. + 0x2 + + + B_0x3 + Tamper event is activated after 8 consecutive samples at the active level. + 0x3 + + + + + TAMPPRCH + TAMP_INx precharge duration + + 5 + 2 + read-write + + + B_0x0 + 1 RTCCLK cycle + 0x0 + + + B_0x1 + 2 RTCCLK cycles + 0x1 + + + B_0x2 + 4 RTCCLK cycles + 0x2 + + + B_0x3 + 8 RTCCLK cycles + 0x3 + + + + + TAMPPUDIS + TAMP_INx pull-up disable + + 7 + 1 + read-write + + + B_0x0 + Precharge TAMP_INx pins before sampling (enable internal pull-up) + 0x0 + + + B_0x1 + Disable precharge of TAMP_INx pins. + 0x1 + + + + + + + TAMP_ATCR1 + TAMP_ATCR1 + TAMP active tamper control register 1 + 0x10 + 0x20 + read-write + 0x00070000 + 0xFFFFFFFF + + + TAMP1AM + Tamper 1 active mode + 0 + 1 + read-write + + + B_0x0 + Tamper 1 detection mode is passive. + 0x0 + + + B_0x1 + Tamper 1 detection mode is active. + 0x1 + + + + + TAMP2AM + Tamper 2 active mode + 1 + 1 + read-write + + + B_0x0 + Tamper 2 detection mode is passive. + 0x0 + + + B_0x1 + Tamper 2 detection mode is active. + 0x1 + + + + + TAMP3AM + Tamper 3 active mode + 2 + 1 + read-write + + + B_0x0 + Tamper 3 detection mode is passive. + 0x0 + + + B_0x1 + Tamper 3 detection mode is active. + 0x1 + + + + + TAMP4AM + Tamper 4 active mode + 3 + 1 + read-write + + + B_0x0 + Tamper 4 detection mode is passive. + 0x0 + + + B_0x1 + Tamper 4 detection mode is active. + 0x1 + + + + + TAMP5AM + Tamper 5 active mode + 4 + 1 + read-write + + + B_0x0 + Tamper 5 detection mode is passive. + 0x0 + + + B_0x1 + Tamper 5 detection mode is active. + 0x1 + + + + + TAMP6AM + Tamper 6 active mode + 5 + 1 + read-write + + + B_0x0 + Tamper 6 detection mode is passive. + 0x0 + + + B_0x1 + Tamper 6 detection mode is active. + 0x1 + + + + + TAMP7AM + Tamper 7 active mode + 6 + 1 + read-write + + + B_0x0 + Tamper 7 detection mode is passive. + 0x0 + + + B_0x1 + Tamper 7 detection mode is active. + 0x1 + + + + + TAMP8AM + Tamper 8 active mode + 7 + 1 + read-write + + + B_0x0 + Tamper 8 detection mode is passive. + 0x0 + + + B_0x1 + Tamper 8 detection mode is active. + 0x1 + + + + + ATOSEL1 + Active tamper shared output 1 selection + + 8 + 2 + read-write + + + B_0x0 + TAMPOUTSEL1 = TAMP_OUT1 + 0x0 + + + B_0x1 + TAMPOUTSEL1 = TAMP_OUT2 + 0x1 + + + B_0x2 + TAMPOUTSEL1 = TAMP_OUT3 + 0x2 + + + B_0x3 + TAMPOUTSEL1 = TAMP_OUT4 + 0x3 + + + + + ATOSEL2 + Active tamper shared output 2 selection + + 10 + 2 + read-write + + + B_0x0 + TAMPOUTSEL2 = TAMP_OUT1 + 0x0 + + + B_0x1 + TAMPOUTSEL2 = TAMP_OUT2 + 0x1 + + + B_0x2 + TAMPOUTSEL2 = TAMP_OUT3 + 0x2 + + + B_0x3 + TAMPOUTSEL2 = TAMP_OUT4 + 0x3 + + + + + ATOSEL3 + Active tamper shared output 3 selection + + 12 + 2 + read-write + + + B_0x0 + TAMPOUTSEL3 = TAMP_OUT1 + 0x0 + + + B_0x1 + TAMPOUTSEL3 = TAMP_OUT2 + 0x1 + + + B_0x2 + TAMPOUTSEL3 = TAMP_OUT3 + 0x2 + + + B_0x3 + TAMPOUTSEL3 = TAMP_OUT4 + 0x3 + + + + + ATOSEL4 + Active tamper shared output 4 selection + + 14 + 2 + read-write + + + B_0x0 + TAMPOUTSEL4 = TAMP_OUT1 + 0x0 + + + B_0x1 + TAMPOUTSEL4 = TAMP_OUT2 + 0x1 + + + B_0x2 + TAMPOUTSEL4 = TAMP_OUT3 + 0x2 + + + B_0x3 + TAMPOUTSEL4 = TAMP_OUT4 + 0x3 + + + + + ATCKSEL + Active tamper RTC asynchronous prescaler clock selection + + 16 + 4 + read-write + + + B_0x0 + RTCCLK is selected + 0x0 + + + B_0x1 + RTCCLK/2 is selected + 0x1 + + + B_0x2 + RTCCLK/4 is selected + 0x2 + + + B_0x3 + RTCCLK/8 is selected + 0x3 + + + B_0x4 + RTCCLK/16 is selected + 0x4 + + + B_0x5 + RTCCLK/32 is selected + 0x5 + + + B_0x6 + RTCCLK/64 is selected + 0x6 + + + B_0x7 + RTCCLK/128 is selected + 0x7 + + + B_0xB + RTCCLK/2048 is selected when (PREDIV_A+1) = 128 and (PREDIV_S+1) is a multiple of 16. + 0xB + + + + + ATPER + Active tamper output change period + + 24 + 3 + read-write + + + ATOSHARE + Active tamper output sharing + 30 + 1 + read-write + + + B_0x0 + Each active tamper input TAMP_INi is compared with its dedicated output TAMP_OUTi + 0x0 + + + B_0x1 + Each active tamper input TAMP_INi is compared with TAMPOUTSELi defined by ATOSELi bits. + 0x1 + + + + + FLTEN + Active tamper filter enable + 31 + 1 + read-write + + + B_0x0 + Active tamper filtering disable + 0x0 + + + B_0x1 + Active tamper filtering enable: a tamper event is detected when 2 comparison mismatches occur out of 4 consecutive samples. + 0x1 + + + + + + + TAMP_ATSEEDR + TAMP_ATSEEDR + TAMP active tamper seed register + 0x14 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + SEED + Pseudo-random generator seed value + + 0 + 32 + write-only + + + + + TAMP_ATOR + TAMP_ATOR + TAMP active tamper output register + 0x18 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + PRNG + Pseudo-random generator value + + 0 + 8 + read-only + + + SEEDF + Seed running flag + + 14 + 1 + read-only + + + INITS + Active tamper initialization status + + 15 + 1 + read-only + + + + + TAMP_ATCR2 + TAMP_ATCR2 + TAMP active tamper control register 2 + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ATOSEL1 + Active tamper shared output 1 selection + + 8 + 3 + read-write + + + B_0x0 + TAMPOUTSEL1 = TAMP_OUT1 + 0x0 + + + B_0x1 + TAMPOUTSEL1 = TAMP_OUT2 + 0x1 + + + B_0x2 + TAMPOUTSEL1 = TAMP_OUT3 + 0x2 + + + B_0x3 + TAMPOUTSEL1 = TAMP_OUT4 + 0x3 + + + B_0x4 + TAMPOUTSEL1 = TAMP_OUT5 + 0x4 + + + B_0x5 + TAMPOUTSEL1 = TAMP_OUT6 + 0x5 + + + B_0x6 + TAMPOUTSEL1 = TAMP_OUT7 + 0x6 + + + B_0x7 + TAMPOUTSEL1 = TAMP_OUT8 + 0x7 + + + + + ATOSEL2 + Active tamper shared output 2 selection + + 11 + 3 + read-write + + + B_0x0 + TAMPOUTSEL2 = TAMP_OUT1 + 0x0 + + + B_0x1 + TAMPOUTSEL2 = TAMP_OUT2 + 0x1 + + + B_0x2 + TAMPOUTSEL2 = TAMP_OUT3 + 0x2 + + + B_0x3 + TAMPOUTSEL2 = TAMP_OUT4 + 0x3 + + + B_0x4 + TAMPOUTSEL2 = TAMP_OUT5 + 0x4 + + + B_0x5 + TAMPOUTSEL2 = TAMP_OUT6 + 0x5 + + + B_0x6 + TAMPOUTSEL2 = TAMP_OUT7 + 0x6 + + + B_0x7 + TAMPOUTSEL2 = TAMP_OUT8 + 0x7 + + + + + ATOSEL3 + Active tamper shared output 3 selection + + 14 + 3 + read-write + + + B_0x0 + TAMPOUTSEL3 = TAMP_OUT1 + 0x0 + + + B_0x1 + TAMPOUTSEL3 = TAMP_OUT2 + 0x1 + + + B_0x2 + TAMPOUTSEL3 = TAMP_OUT3 + 0x2 + + + B_0x3 + TAMPOUTSEL3 = TAMP_OUT4 + 0x3 + + + B_0x4 + TAMPOUTSEL3 = TAMP_OUT5 + 0x4 + + + B_0x5 + TAMPOUTSEL3 = TAMP_OUT6 + 0x5 + + + B_0x6 + TAMPOUTSEL3 = TAMP_OUT7 + 0x6 + + + B_0x7 + TAMPOUTSEL3 = TAMP_OUT8 + 0x7 + + + + + ATOSEL4 + Active tamper shared output 4 selection + + 17 + 3 + read-write + + + B_0x0 + TAMPOUTSEL4 = TAMP_OUT1 + 0x0 + + + B_0x1 + TAMPOUTSEL4 = TAMP_OUT2 + 0x1 + + + B_0x2 + TAMPOUTSEL4 = TAMP_OUT3 + 0x2 + + + B_0x3 + TAMPOUTSEL4 = TAMP_OUT4 + 0x3 + + + B_0x4 + TAMPOUTSEL4 = TAMP_OUT5 + 0x4 + + + B_0x5 + TAMPOUTSEL4 = TAMP_OUT6 + 0x5 + + + B_0x6 + TAMPOUTSEL4 = TAMP_OUT7 + 0x6 + + + B_0x7 + TAMPOUTSEL4 = TAMP_OUT8 + 0x7 + + + + + ATOSEL5 + Active tamper shared output 5 selection + + 20 + 3 + read-write + + + B_0x0 + TAMPOUTSEL5 = TAMP_OUT1 + 0x0 + + + B_0x1 + TAMPOUTSEL5 = TAMP_OUT2 + 0x1 + + + B_0x2 + TAMPOUTSEL5 = TAMP_OUT3 + 0x2 + + + B_0x3 + TAMPOUTSEL5 = TAMP_OUT4 + 0x3 + + + B_0x4 + TAMPOUTSEL5 = TAMP_OUT5 + 0x4 + + + B_0x5 + TAMPOUTSEL5 = TAMP_OUT6 + 0x5 + + + B_0x6 + TAMPOUTSEL5 = TAMP_OUT7 + 0x6 + + + B_0x7 + TAMPOUTSEL5 = TAMP_OUT8 + 0x7 + + + + + ATOSEL6 + Active tamper shared output 6 selection + + 23 + 3 + read-write + + + B_0x0 + TAMPOUTSEL6 = TAMP_OUT1 + 0x0 + + + B_0x1 + TAMPOUTSEL6 = TAMP_OUT2 + 0x1 + + + B_0x2 + TAMPOUTSEL6 = TAMP_OUT3 + 0x2 + + + B_0x3 + TAMPOUTSEL6 = TAMP_OUT4 + 0x3 + + + B_0x4 + TAMPOUTSEL6 = TAMP_OUT5 + 0x4 + + + B_0x5 + TAMPOUTSEL6 = TAMP_OUT6 + 0x5 + + + B_0x6 + TAMPOUTSEL6 = TAMP_OUT7 + 0x6 + + + B_0x7 + TAMPOUTSEL6 = TAMP_OUT8 + 0x7 + + + + + ATOSEL7 + Active tamper shared output 7 selection + + 26 + 3 + read-write + + + B_0x0 + TAMPOUTSEL7 = TAMP_OUT1 + 0x0 + + + B_0x1 + TAMPOUTSEL7 = TAMP_OUT2 + 0x1 + + + B_0x2 + TAMPOUTSEL7 = TAMP_OUT3 + 0x2 + + + B_0x3 + TAMPOUTSEL7 = TAMP_OUT4 + 0x3 + + + B_0x4 + TAMPOUTSEL7 = TAMP_OUT5 + 0x4 + + + B_0x5 + TAMPOUTSEL7 = TAMP_OUT6 + 0x5 + + + B_0x6 + TAMPOUTSEL7 = TAMP_OUT7 + 0x6 + + + B_0x7 + TAMPOUTSEL7 = TAMP_OUT8 + 0x7 + + + + + ATOSEL8 + Active tamper shared output 8 selection + + 29 + 3 + read-write + + + B_0x0 + TAMPOUTSEL8 = TAMP_OUT1 + 0x0 + + + B_0x1 + TAMPOUTSEL8 = TAMP_OUT2 + 0x1 + + + B_0x2 + TAMPOUTSEL8 = TAMP_OUT3 + 0x2 + + + B_0x3 + TAMPOUTSEL8 = TAMP_OUT4 + 0x3 + + + B_0x4 + TAMPOUTSEL8 = TAMP_OUT5 + 0x4 + + + B_0x5 + TAMPOUTSEL8 = TAMP_OUT6 + 0x5 + + + B_0x6 + TAMPOUTSEL8 = TAMP_OUT7 + 0x6 + + + B_0x7 + TAMPOUTSEL8 = TAMP_OUT8 + 0x7 + + + + + + + TAMP_SECCFGR + TAMP_SECCFGR + TAMP secure configuration register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKPRWSEC + Backup registers read/write protection offset + + 0 + 8 + read-write + + + CNT1SEC + Monotonic counter 1 secure protection + 15 + 1 + read-write + + + B_0x0 + Monotonic counter 1 (TAMP_COUNT1R) can be read and written when the APB access is secure or nonsecure. + 0x0 + + + B_0x1 + Monotonic counter 1 (TAMP_COUNT1R) can be read and written only when the APB access is secure. + 0x1 + + + + + BKPWSEC + Backup registers write protection offset + + 16 + 8 + read-write + + + BHKLOCK + Boot hardware key lock + + 30 + 1 + read-write + + + B_0x0 + The Backup registers from TAMP_BKP0R to TAMP_BKP7R can be accessed according to the Protection zone they belong to. + 0x0 + + + B_0x1 + The backup registers from TAMP_BKP0R to TAMP_BKP7R cannot be accessed neither in read nor in write (they are read as 0 and write ignore). + 0x1 + + + + + TAMPSEC + Tamper protection (excluding monotonic counters and backup registers) + + 31 + 1 + read-write + + + B_0x0 + Tamper configuration and interrupt can be written when the APB access is secure or nonsecure. + 0x0 + + + B_0x1 + Tamper configuration and interrupt can be written only when the APB access is secure. + 0x1 + + + + + + + TAMP_PRIVCFGR + TAMP_PRIVCFGR + TAMP privilege configuration register + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT1PRIV + Monotonic counter 1 privilege protection + 15 + 1 + read-write + + + B_0x0 + Monotonic counter 1 (TAMP_COUNT1R) can be read and written when the APB access is privileged or non-privileged. + 0x0 + + + B_0x1 + Monotonic counter 1 (TAMP_COUNT1R) can be read and written only when the APB access is privileged. + 0x1 + + + + + BKPRWPRIV + Backup registers zone 1 privilege protection + 29 + 1 + read-write + + + B_0x0 + Backup registers zone 1 can be read and written with privileged or unprivileged access. + 0x0 + + + B_0x1 + Backup registers zone 1 can be read and written only with privileged access + 0x1 + + + + + BKPWPRIV + Backup registers zone 2 privilege protection + 30 + 1 + read-write + + + B_0x0 + Backup registers zone 2 can be written with privileged or unprivileged access. + 0x0 + + + B_0x1 + Backup registers zone 2 can be written only with privileged access. + 0x1 + + + + + TAMPPRIV + Tamper privilege protection (excluding backup registers) + + 31 + 1 + read-write + + + B_0x0 + Tamper configuration and interrupt can be written with privileged or unprivileged access. + 0x0 + + + B_0x1 + Tamper configuration and interrupt can be written only with privileged access. + 0x1 + + + + + + + TAMP_IER + TAMP_IER + TAMP interrupt enable register + 0x2C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TAMP1IE + Tamper 1 interrupt enable + 0 + 1 + read-write + + + B_0x0 + Tamper 1 interrupt disabled. + 0x0 + + + B_0x1 + Tamper 1 interrupt enabled. + 0x1 + + + + + TAMP2IE + Tamper 2 interrupt enable + 1 + 1 + read-write + + + B_0x0 + Tamper 2 interrupt disabled. + 0x0 + + + B_0x1 + Tamper 2 interrupt enabled. + 0x1 + + + + + TAMP3IE + Tamper 3 interrupt enable + 2 + 1 + read-write + + + B_0x0 + Tamper 3 interrupt disabled. + 0x0 + + + B_0x1 + Tamper 3 interrupt enabled. + 0x1 + + + + + TAMP4IE + Tamper 4 interrupt enable + 3 + 1 + read-write + + + B_0x0 + Tamper 4 interrupt disabled. + 0x0 + + + B_0x1 + Tamper 4 interrupt enabled. + 0x1 + + + + + TAMP5IE + Tamper 5 interrupt enable + 4 + 1 + read-write + + + B_0x0 + Tamper 5 interrupt disabled. + 0x0 + + + B_0x1 + Tamper 5 interrupt enabled. + 0x1 + + + + + TAMP6IE + Tamper 6 interrupt enable + 5 + 1 + read-write + + + B_0x0 + Tamper 6 interrupt disabled. + 0x0 + + + B_0x1 + Tamper 6 interrupt enabled. + 0x1 + + + + + TAMP7IE + Tamper 7interrupt enable + 6 + 1 + read-write + + + B_0x0 + Tamper 7 interrupt disabled. + 0x0 + + + B_0x1 + Tamper 7interrupt enabled. + 0x1 + + + + + TAMP8IE + Tamper 8 interrupt enable + 7 + 1 + read-write + + + B_0x0 + Tamper 8 interrupt disabled. + 0x0 + + + B_0x1 + Tamper 8 interrupt enabled. + 0x1 + + + + + ITAMP1IE + Internal tamper 1 interrupt enable + 16 + 1 + read-write + + + B_0x0 + Internal tamper 1 interrupt disabled. + 0x0 + + + B_0x1 + Internal tamper 1 interrupt enabled + 0x1 + + + + + ITAMP2IE + Internal tamper 2 interrupt enable + 17 + 1 + read-write + + + B_0x0 + Internal tamper 2 interrupt disabled. + 0x0 + + + B_0x1 + Internal tamper 2 interrupt enabled. + 0x1 + + + + + ITAMP3IE + Internal tamper 3 interrupt enable + 18 + 1 + read-write + + + B_0x0 + Internal tamper 3 interrupt disabled. + 0x0 + + + B_0x1 + Internal tamper 3 interrupt enabled. + 0x1 + + + + + ITAMP4IE + Internal tamper 4 interrupt enable + 19 + 1 + read-write + + + B_0x0 + Internal tamper 4 interrupt disabled. + 0x0 + + + B_0x1 + Internal tamper 4 interrupt enabled. + 0x1 + + + + + ITAMP5IE + Internal tamper 5 interrupt enable + 20 + 1 + read-write + + + B_0x0 + Internal tamper 5 interrupt disabled. + 0x0 + + + B_0x1 + Internal tamper 5 interrupt enabled. + 0x1 + + + + + ITAMP6IE + Internal tamper 6 interrupt enable + 21 + 1 + read-write + + + B_0x0 + Internal tamper 6 interrupt disabled. + 0x0 + + + B_0x1 + Internal tamper 6 interrupt enabled. + 0x1 + + + + + ITAMP7IE + Internal tamper 7 interrupt enable + 22 + 1 + read-write + + + B_0x0 + Internal tamper 7 interrupt disabled. + 0x0 + + + B_0x1 + Internal tamper 7 interrupt enabled. + 0x1 + + + + + ITAMP8IE + Internal tamper 8 interrupt enable + 23 + 1 + read-write + + + B_0x0 + Internal tamper 8 interrupt disabled. + 0x0 + + + B_0x1 + Internal tamper 8 interrupt enabled. + 0x1 + + + + + ITAMP9IE + Internal tamper 9 interrupt enable + 24 + 1 + read-write + + + B_0x0 + Internal tamper 9 interrupt disabled. + 0x0 + + + B_0x1 + Internal tamper 9 interrupt enabled. + 0x1 + + + + + ITAMP11IE + Internal tamper 11 interrupt enable + 26 + 1 + read-write + + + B_0x0 + Internal tamper 11 interrupt disabled. + 0x0 + + + B_0x1 + Internal tamper 11 interrupt enabled. + 0x1 + + + + + ITAMP12IE + Internal tamper 12 interrupt enable + 27 + 1 + read-write + + + B_0x0 + Internal tamper 12 interrupt disabled. + 0x0 + + + B_0x1 + Internal tamper 12 interrupt enabled. + 0x1 + + + + + ITAMP13IE + Internal tamper 13 interrupt enable + 28 + 1 + read-write + + + B_0x0 + Internal tamper 13 interrupt disabled. + 0x0 + + + B_0x1 + Internal tamper 13 interrupt enabled. + 0x1 + + + + + ITAMP15IE + Internal tamper 15 interrupt enable + 30 + 1 + read-write + + + B_0x0 + Internal tamper 15 interrupt disabled. + 0x0 + + + B_0x1 + Internal tamper 15 interrupt enabled. + 0x1 + + + + + + + TAMP_SR + TAMP_SR + TAMP status register + 0x30 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TAMP1F + TAMP1 detection flag + + 0 + 1 + read-only + + + TAMP2F + TAMP2 detection flag + + 1 + 1 + read-only + + + TAMP3F + TAMP3 detection flag + + 2 + 1 + read-only + + + TAMP4F + TAMP4 detection flag + + 3 + 1 + read-only + + + TAMP5F + TAMP5 detection flag + + 4 + 1 + read-only + + + TAMP6F + TAMP6 detection flag + + 5 + 1 + read-only + + + TAMP7F + TAMP7 detection flag + + 6 + 1 + read-only + + + TAMP8F + TAMP8 detection flag + + 7 + 1 + read-only + + + ITAMP1F + Internal tamper 1 flag + + 16 + 1 + read-only + + + ITAMP2F + Internal tamper 2 flag + + 17 + 1 + read-only + + + ITAMP3F + Internal tamper 3 flag + + 18 + 1 + read-only + + + ITAMP4F + Internal tamper 4 flag + + 19 + 1 + read-only + + + ITAMP5F + Internal tamper 5 flag + + 20 + 1 + read-only + + + ITAMP6F + Internal tamper 6 flag + + 21 + 1 + read-only + + + ITAMP7F + Internal tamper 7 flag + + 22 + 1 + read-only + + + ITAMP8F + Internal tamper 8 flag + + 23 + 1 + read-only + + + ITAMP9F + Internal tamper 9 flag + + 24 + 1 + read-only + + + ITAMP11F + Internal tamper 11 flag + + 26 + 1 + read-only + + + ITAMP12F + Internal tamper 12 flag + + 27 + 1 + read-only + + + ITAMP13F + Internal tamper 13 flag + + 28 + 1 + read-only + + + ITAMP15F + Internal tamper 15 flag + + 30 + 1 + read-write + + + + + TAMP_MISR + TAMP_MISR + TAMP nonsecure masked interrupt status register + 0x34 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + TAMP1MF + TAMP1 nonsecure interrupt masked flag + + 0 + 1 + read-only + + + TAMP2MF + TAMP2 nonsecure interrupt masked flag + + 1 + 1 + read-only + + + TAMP3MF + TAMP3 nonsecure interrupt masked flag + + 2 + 1 + read-only + + + TAMP4MF + TAMP4 nonsecure interrupt masked flag + + 3 + 1 + read-only + + + TAMP5MF + TAMP5 nonsecure interrupt masked flag + + 4 + 1 + read-only + + + TAMP6MF + TAMP6 nonsecure interrupt masked flag + + 5 + 1 + read-only + + + TAMP7MF + TAMP7 nonsecure interrupt masked flag + + 6 + 1 + read-only + + + TAMP8MF + TAMP8 nonsecure interrupt masked flag + + 7 + 1 + read-only + + + ITAMP1MF + Internal tamper 1 nonsecure interrupt masked flag + + 16 + 1 + read-only + + + ITAMP2MF + Internal tamper 2 nonsecure interrupt masked flag + + 17 + 1 + read-only + + + ITAMP3MF + Internal tamper 3 nonsecure interrupt masked flag + + 18 + 1 + read-only + + + ITAMP4MF + Internal tamper 4 nonsecure interrupt masked flag + + 19 + 1 + read-only + + + ITAMP5MF + Internal tamper 5 nonsecure interrupt masked flag + + 20 + 1 + read-only + + + ITAMP6MF + Internal tamper 6 nonsecure interrupt masked flag + + 21 + 1 + read-only + + + ITAMP7MF + Internal tamper 7 tamper nonsecure interrupt masked flag + + 22 + 1 + read-only + + + ITAMP8MF + Internal tamper 8 nonsecure interrupt masked flag + + 23 + 1 + read-only + + + ITAMP9MF + internal tamper 9 nonsecure interrupt masked flag + + 24 + 1 + read-only + + + ITAMP11MF + internal tamper 11 nonsecure interrupt masked flag + + 26 + 1 + read-only + + + ITAMP12MF + internal tamper 12 nonsecure interrupt masked flag + + 27 + 1 + read-only + + + ITAMP13MF + internal tamper 13 nonsecure interrupt masked flag + + 28 + 1 + read-only + + + ITAMP15MF + internal tamper 15 nonsecure interrupt masked flag + + 30 + 1 + read-only + + + + + TAMP_SMISR + TAMP_SMISR + TAMP secure masked interrupt status register + 0x38 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + TAMP1MF + TAMP1 secure interrupt masked flag + + 0 + 1 + read-only + + + TAMP2MF + TAMP2 secure interrupt masked flag + + 1 + 1 + read-only + + + TAMP3MF + TAMP3 secure interrupt masked flag + + 2 + 1 + read-only + + + TAMP4MF + TAMP4 secure interrupt masked flag + + 3 + 1 + read-only + + + TAMP5MF + TAMP5 secure interrupt masked flag + + 4 + 1 + read-only + + + TAMP6MF + TAMP6 secure interrupt masked flag + + 5 + 1 + read-only + + + TAMP7MF + TAMP7 secure interrupt masked flag + + 6 + 1 + read-only + + + TAMP8MF + TAMP8 secure interrupt masked flag + + 7 + 1 + read-only + + + ITAMP1MF + Internal tamper 1 secure interrupt masked flag + + 16 + 1 + read-only + + + ITAMP2MF + Internal tamper 2 secure interrupt masked flag + + 17 + 1 + read-only + + + ITAMP3MF + Internal tamper 3 secure interrupt masked flag + + 18 + 1 + read-only + + + ITAMP4MF + Internal tamper 4 secure interrupt masked flag + + 19 + 1 + read-only + + + ITAMP5MF + Internal tamper 5 secure interrupt masked flag + + 20 + 1 + read-only + + + ITAMP6MF + Internal tamper 6 secure interrupt masked flag + + 21 + 1 + read-only + + + ITAMP7MF + Internal tamper 7 secure interrupt masked flag + + 22 + 1 + read-only + + + ITAMP8MF + Internal tamper 8 secure interrupt masked flag + + 23 + 1 + read-only + + + ITAMP9MF + internal tamper 9 secure interrupt masked flag + + 24 + 1 + read-only + + + ITAMP11MF + internal tamper 11 secure interrupt masked flag + + 26 + 1 + read-only + + + ITAMP12MF + internal tamper 12 secure interrupt masked flag + + 27 + 1 + read-only + + + ITAMP13MF + internal tamper 13 secure interrupt masked flag + + 28 + 1 + read-only + + + ITAMP15MF + internal tamper 15 secure interrupt masked flag + + 30 + 1 + read-only + + + + + TAMP_SCR + TAMP_SCR + TAMP status clear register + 0x3C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + CTAMP1F + Clear TAMP1 detection flag + + 0 + 1 + write-only + + + CTAMP2F + Clear TAMP2 detection flag + + 1 + 1 + write-only + + + CTAMP3F + Clear TAMP3 detection flag + + 2 + 1 + write-only + + + CTAMP4F + Clear TAMP4 detection flag + + 3 + 1 + write-only + + + CTAMP5F + Clear TAMP5 detection flag + + 4 + 1 + write-only + + + CTAMP6F + Clear TAMP6 detection flag + + 5 + 1 + write-only + + + CTAMP7F + Clear TAMP7 detection flag + + 6 + 1 + write-only + + + CTAMP8F + Clear TAMP8 detection flag + + 7 + 1 + write-only + + + CITAMP1F + Clear ITAMP1 detection flag + + 16 + 1 + write-only + + + CITAMP2F + Clear ITAMP2 detection flag + + 17 + 1 + write-only + + + CITAMP3F + Clear ITAMP3 detection flag + + 18 + 1 + write-only + + + CITAMP4F + Clear ITAMP4 detection flag + + 19 + 1 + write-only + + + CITAMP5F + Clear ITAMP5 detection flag + + 20 + 1 + write-only + + + CITAMP6F + Clear ITAMP6 detection flag + + 21 + 1 + write-only + + + CITAMP7F + Clear ITAMP7 detection flag + + 22 + 1 + write-only + + + CITAMP8F + Clear ITAMP8 detection flag + + 23 + 1 + write-only + + + CITAMP9F + Clear ITAMP9 detection flag + + 24 + 1 + write-only + + + CITAMP11F + Clear ITAMP11 detection flag + + 26 + 1 + write-only + + + CITAMP12F + Clear ITAMP12 detection flag + + 27 + 1 + write-only + + + CITAMP13F + Clear ITAMP13 detection flag + + 28 + 1 + write-only + + + CITAMP15F + Clear ITAMP15 detection flag + + 30 + 1 + write-only + + + + + TAMP_COUNT1R + TAMP_COUNT1R + TAMP monotonic counter 1 register + 0x040 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + COUNT + This register is read-only only and is incremented by one when a write access is done to this register. + 0 + 32 + read-only + + + + + TAMP_OR + TAMP_OR + TAMP option register + 0x50 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OUT3_RMP + TAMP_OUT3 mapping + 1 + 2 + read-write + + + B_0x0 + TAMP_OUT3 is on PC13 + 0x0 + + + B_0x1 + TAMP_OUT3 is on PI8 + 0x1 + + + B_0x2 + TAMP_OUT3 is on PE3 + 0x2 + + + B_0x3 + TAMP_OUT3 is on PA2 + 0x3 + + + + + OUT5_RMP + TAMP_OUT5 mapping + 3 + 1 + read-write + + + B_0x0 + TAMP_OUT5 is on PI11 + 0x0 + + + B_0x1 + TAMP_OUT5 is on PC1 + 0x1 + + + + + IN2_RMP + TAMP_IN2 mapping + 8 + 1 + read-write + + + B_0x0 + TAMP_IN2 is on PA0 + 0x0 + + + B_0x1 + TAMP_IN2 is on PI8 + 0x1 + + + + + IN3_RMP + TAMP_IN3 mapping + 9 + 1 + read-write + + + B_0x0 + TAMP_IN3 is on PC1 + 0x0 + + + B_0x1 + TAMP_IN3 is on PE6 + 0x1 + + + + + IN4_RMP + TAMP_IN4 mapping + 10 + 1 + read-write + + + B_0x0 + TAMP_IN4 is on PA2 + 0x0 + + + B_0x1 + TAMP_IN4 is on PI11 + 0x1 + + + + + + + TAMP_RPCFGR + TAMP_RPCFGR + TAMP resources protection configuration register + 0x54 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RPCFG0 + Configurable resource 0 protection + 0 + 1 + read-write + + + B_0x0 + Resource 0 is not included in the device secrets protected by TAMP peripheral + 0x0 + + + B_0x1 + Resource 0 is included in the device secrets protected by TAMP peripheral + 0x1 + + + + + + + TAMP_BKP0R + TAMP_BKP0R + TAMP backup 0 register + 0x100 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP1R + TAMP_BKP1R + TAMP backup 1 register + 0x104 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP2R + TAMP_BKP2R + TAMP backup 2 register + 0x108 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP3R + TAMP_BKP3R + TAMP backup 3 register + 0x10C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP4R + TAMP_BKP4R + TAMP backup 4 register + 0x110 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP5R + TAMP_BKP5R + TAMP backup 5 register + 0x114 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP6R + TAMP_BKP6R + TAMP backup 6 register + 0x118 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP7R + TAMP_BKP7R + TAMP backup 7 register + 0x11C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP8R + TAMP_BKP8R + TAMP backup 8 register + 0x120 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP9R + TAMP_BKP9R + TAMP backup 9 register + 0x124 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP10R + TAMP_BKP10R + TAMP backup 10 register + 0x128 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP11R + TAMP_BKP11R + TAMP backup 11 register + 0x12C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP12R + TAMP_BKP12R + TAMP backup 12 register + 0x130 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP13R + TAMP_BKP13R + TAMP backup 13 register + 0x134 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP14R + TAMP_BKP14R + TAMP backup 14 register + 0x138 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP15R + TAMP_BKP15R + TAMP backup 15 register + 0x13C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP16R + TAMP_BKP16R + TAMP backup 16 register + 0x140 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP17R + TAMP_BKP17R + TAMP backup 17 register + 0x144 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP18R + TAMP_BKP18R + TAMP backup 18 register + 0x148 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP19R + TAMP_BKP19R + TAMP backup 19 register + 0x14C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP20R + TAMP_BKP20R + TAMP backup 20 register + 0x150 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP21R + TAMP_BKP21R + TAMP backup 21 register + 0x154 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP22R + TAMP_BKP22R + TAMP backup 22 register + 0x158 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP23R + TAMP_BKP23R + TAMP backup 23 register + 0x15C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP24R + TAMP_BKP24R + TAMP backup 24 register + 0x160 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP25R + TAMP_BKP25R + TAMP backup 25 register + 0x164 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP26R + TAMP_BKP26R + TAMP backup 26 register + 0x168 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP27R + TAMP_BKP27R + TAMP backup 27 register + 0x16C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP28R + TAMP_BKP28R + TAMP backup 28 register + 0x170 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP29R + TAMP_BKP29R + TAMP backup 29 register + 0x174 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP30R + TAMP_BKP30R + TAMP backup 30 register + 0x178 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP31R + TAMP_BKP31R + TAMP backup 31 register + 0x17C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + + + TAMP_S + 0X54007C00 + + + TIM1 + TIM1 address block description + TIM1 + 0x40012c00 + + 0x0 + 0x3E4 + registers + + + TIM1_CC + TIM1 capture compare interrupt + 44 + + + TIM1_TRGI_COM_DIR_IDX + TIM1 trigger and commutation/TIM1 Direction Change interrupt/TIM1 Index + 43 + + + TIM1_UPD + TIM1 Update + 42 + + + TIM1_BRK_TERR_IERR + TIM1 Break/TIM1 Transition error/TIM1 Index error + 41 + + + + TIM1_CR1 + TIM1_CR1 + TIM1 control register 1 + 0x000 + 16 + read-write + 0x0000 + 0xFFFF + + + CEN + Counter enable + + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable + + 1 + 1 + read-write + + + B_0x0 + UEV enabled. + 0x0 + + + B_0x1 + UEV disabled. + 0x1 + + + + + URS + Update request source + + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt or DMA request if enabled. + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + DIR + Direction + + 4 + 1 + read-write + + + B_0x0 + Counter used as upcounter + 0x0 + + + B_0x1 + Counter used as downcounter + 0x1 + + + + + CMS + Center-aligned mode selection + + 5 + 2 + read-write + + + B_0x0 + Edge-aligned mode. + 0x0 + + + B_0x1 + Center-aligned mode 1. + 0x1 + + + B_0x2 + Center-aligned mode 2. + 0x2 + + + B_0x3 + Center-aligned mode 3. + 0x3 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division + + 8 + 2 + read-write + + + B_0x0 + tless thansub>DTSless than/sub>=tless thansub>tim_ker_ckless than/sub> + 0x0 + + + B_0x1 + tless thansub>DTSless than/sub>=2*tless thansub>tim_ker_ckless than/sub> + 0x1 + + + B_0x2 + tless thansub>DTSless than/sub>=4*tless thansub>tim_ker_ckless than/sub> + 0x2 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. + 0x0 + + + B_0x1 + Remapping enabled. + 0x1 + + + + + DITHEN + Dithering enable + + 12 + 1 + read-write + + + B_0x0 + Dithering disabled + 0x0 + + + B_0x1 + Dithering enabled + 0x1 + + + + + + + TIM1_CR2 + TIM1_CR2 + TIM1 control register 2 + 0x004 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCPC + Capture/compare preloaded control + + 0 + 1 + read-write + + + B_0x0 + CCxE, CCxNE and OCxM bits are not preloaded + 0x0 + + + B_0x1 + CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on tim_trgi, depending on the CCUS bit). + 0x1 + + + + + CCUS + Capture/compare control update selection + + 2 + 1 + read-write + + + B_0x0 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only + 0x0 + + + B_0x1 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on tim_trgi + 0x1 + + + + + CCDS + Capture/compare DMA selection + 3 + 1 + read-write + + + B_0x0 + CCx DMA request sent when CCx event occurs + 0x0 + + + B_0x1 + CCx DMA requests sent when update event occurs + 0x1 + + + + + MMS + MMS[2:0]: Master mode selection + + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo). + 0x0 + + + B_0x1 + Enable - the Counter Enable signal CNT_EN is used as trigger output (tim_trgo). + 0x1 + + + B_0x2 + Update - The update event is selected as trigger output (tim_trgo). + 0x2 + + + B_0x3 + Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. + 0x3 + + + B_0x4 + Compare - tim_oc1refc signal is used as trigger output (tim_trgo) + 0x4 + + + B_0x5 + Compare - tim_oc2refc signal is used as trigger output (tim_trgo) + 0x5 + + + B_0x6 + Compare - tim_oc3refc signal is used as trigger output (tim_trgo) + 0x6 + + + B_0x7 + Compare - tim_oc4refc signal is used as trigger output (tim_trgo) + 0x7 + + + + + TI1S + tim_ti1 selection + 7 + 1 + read-write + + + B_0x0 + The tim_ti1_in[15:0] multiplexer output is connected to tim_ti1 input + 0x0 + + + B_0x1 + tim_ti1_in[15:0], tim_ti2_in[15:0] and tim_ti3_in[15:0] multiplexers outputs are XORed and connected to the tim_ti1 input + 0x1 + + + + + OIS1 + Output idle state 1 (tim_oc1 output) + + 8 + 1 + read-write + + + B_0x0 + tim_oc1=0 (after a dead-time) when MOE=0 + 0x0 + + + B_0x1 + tim_oc1=1 (after a dead-time) when MOE=0 + 0x1 + + + + + OIS1N + Output idle state 1 (tim_oc1n output) + + 9 + 1 + read-write + + + B_0x0 + tim_oc1n=0 after a dead-time when MOE=0 + 0x0 + + + B_0x1 + tim_oc1n=1 after a dead-time when MOE=0 + 0x1 + + + + + OIS2 + Output idle state 2 (tim_oc2 output) + + 10 + 1 + read-write + + + OIS2N + Output idle state 2 (tim_oc2n output) + + 11 + 1 + read-write + + + OIS3 + Output idle state 3 (tim_oc3n output) + + 12 + 1 + read-write + + + OIS3N + Output idle state 3 (tim_oc3n output) + + 13 + 1 + read-write + + + OIS4 + Output idle state 4 (tim_oc4 output) + + 14 + 1 + read-write + + + OIS4N + Output idle state 4 (tim_oc4n output) + + 15 + 1 + read-write + + + OIS5 + Output idle state 5 (tim_oc5 output) + + 16 + 1 + read-write + + + OIS6 + Output idle state 6 (tim_oc6 output) + + 18 + 1 + read-write + + + MMS2 + Master mode selection 2 + + 20 + 4 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo2). + 0x0 + + + B_0x1 + Enable - the Counter Enable signal CNT_EN is used as trigger output (tim_trgo2). + 0x1 + + + B_0x2 + Update - the update event is selected as trigger output (tim_trgo2). + 0x2 + + + B_0x3 + Compare pulse - the trigger output sends a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or compare match occurs (tim_trgo2). + 0x3 + + + B_0x4 + Compare - tim_oc1refc signal is used as trigger output (tim_trgo2) + 0x4 + + + B_0x5 + Compare - tim_oc2refc signal is used as trigger output (tim_trgo2) + 0x5 + + + B_0x6 + Compare - tim_oc3refc signal is used as trigger output (tim_trgo2) + 0x6 + + + B_0x7 + Compare - tim_oc4refc signal is used as trigger output (tim_trgo2) + 0x7 + + + B_0x8 + Compare - tim_oc5refc signal is used as trigger output (tim_trgo2) + 0x8 + + + B_0x9 + Compare - tim_oc6refc signal is used as trigger output (tim_trgo2) + 0x9 + + + B_0xA + Compare Pulse - tim_oc4refc rising or falling edges generate pulses on tim_trgo2 + 0xA + + + B_0xB + Compare pulse - tim_oc6refc rising or falling edges generate pulses on tim_trgo2 + 0xB + + + B_0xC + Compare pulse - tim_oc4refc or tim_oc6refc rising edges generate pulses on tim_trgo2 + 0xC + + + B_0xD + Compare pulse - tim_oc4refc rising or tim_oc6refc falling edges generate pulses on tim_trgo2 + 0xD + + + B_0xE + Compare pulse - tim_oc5refc or tim_oc6refc rising edges generate pulses on tim_trgo2 + 0xE + + + B_0xF + Compare pulse - tim_oc5refc rising or tim_oc6refc falling edges generate pulses on tim_trgo2 + 0xF + + + + + MMS_1 + MMS[3] + 25 + 1 + read-write + + + + + TIM1_SMCR + TIM1_SMCR + TIM1 slave mode control register + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SMS + SMS[2:0]: Slave mode selection + + 0 + 3 + read-write + + + B_0x0 + Slave mode disabled - if CEN = 1' then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Quadrature encoder mode 1, x2 mode- Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level. + 0x1 + + + B_0x2 + Quadrature encoder mode 2, x2 mode - Counter counts up/down on tim_ti2fp2 edge depending on tim_ti1fp1 level. + 0x2 + + + B_0x3 + Quadrature encoder mode 3, x4 mode - Counter counts up/down on both tim_ti1fp1 and tim_ti2fp2 edges depending on the level of the other input. + 0x3 + + + B_0x4 + Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers. + 0x4 + + + B_0x5 + Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high. + 0x5 + + + B_0x6 + Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). + 0x6 + + + B_0x7 + External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter. + 0x7 + + + + + OCCS + OCREF clear selection + + 3 + 1 + read-write + + + B_0x0 + tim_ocref_clr_int is connected to the tim_ocref_clr input + 0x0 + + + B_0x1 + tim_ocref_clr_int is connected to tim_etrf + 0x1 + + + + + TS + TS[2:0]: Trigger selection + + 4 + 3 + read-write + + + B_0x0 + Internal Trigger 0 (tim_itr0) + 0x0 + + + B_0x1 + Internal Trigger 1 (tim_itr1) + 0x1 + + + B_0x2 + Internal Trigger 2 (tim_itr2) + 0x2 + + + B_0x3 + Internal Trigger 3 (tim_itr3) + 0x3 + + + B_0x4 + tim_ti1 Edge Detector (tim_ti1f_ed) + 0x4 + + + B_0x5 + Filtered Timer Input 1 (tim_ti1fp1) + 0x5 + + + B_0x6 + Filtered Timer Input 2 (tim_ti2fp2) + 0x6 + + + B_0x7 + External Trigger input (tim_etrf) + 0x7 + + + + + MSM + Master/slave mode + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). + 0x1 + + + + + ETF + External trigger filter + + 8 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + ETPS + External trigger prescaler + + 12 + 2 + read-write + + + B_0x0 + Prescaler OFF + 0x0 + + + B_0x1 + tim_etr_in frequency divided by 2 + 0x1 + + + B_0x2 + tim_etr_in frequency divided by 4 + 0x2 + + + B_0x3 + tim_etr_in frequency divided by 8 + 0x3 + + + + + ECE + External clock enable + + 14 + 1 + read-write + + + B_0x0 + External clock mode 2 disabled + 0x0 + + + B_0x1 + External clock mode 2 enabled. + 0x1 + + + + + ETP + External trigger polarity + + 15 + 1 + read-write + + + B_0x0 + tim_etr_in is non-inverted, active at high level or rising edge. + 0x0 + + + B_0x1 + tim_etr_in is inverted, active at low level or falling edge. + 0x1 + + + + + SMS_1 + Slave mode selection +When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (see Input Control register and Control Register description. +Note: The gated mode must not be used if tim_ti1f_ed is selected as the trigger input (TS=00100). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on tim_ti1f, whereas the gated mode checks the level of the trigger signal. +Note: The clock of the slave peripherals (timer, ADC, ...) receiving the tim_trgo signal must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. + 16 + 1 + read-write + + + B_0x0 + Slave mode disabled - if CEN = '1 then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level. + 0x1 + + + + + TS_1 + Trigger selection +This bit-field selects the trigger input to be used to synchronize the counter. +Others: Reserved +See for product specific implementation details. +Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. + 20 + 2 + read-write + + + B_0x0 + Internal trigger 0 (tim_itr0) + 0x0 + + + B_0x1 + Internal trigger 1 (tim_itr1) + 0x1 + + + B_0x2 + Internal trigger 2 (tim_itr2) + 0x2 + + + B_0x3 + Internal trigger 3 (tim_itr3) + 0x3 + + + + + SMSPE + SMS preload enable + + 24 + 1 + read-write + + + B_0x0 + SMS[3:0] bitfield is not preloaded + 0x0 + + + B_0x1 + SMS[3:0] preload is enabled + 0x1 + + + + + SMSPS + SMS preload source + + 25 + 1 + read-write + + + B_0x0 + The transfer is triggered by the Timer's Update event + 0x0 + + + B_0x1 + The transfer is triggered by the Index event + 0x1 + + + + + + + TIM1_DIER + TIM1_DIER + TIM1 DMA/interrupt enable register + 0x00C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled + 0x0 + + + B_0x1 + Update interrupt enabled + 0x1 + + + + + CC1IE + Capture/compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled + 0x0 + + + B_0x1 + CC1 interrupt enabled + 0x1 + + + + + CC2IE + Capture/compare 2 interrupt enable + 2 + 1 + read-write + + + B_0x0 + CC2 interrupt disabled + 0x0 + + + B_0x1 + CC2 interrupt enabled + 0x1 + + + + + CC3IE + Capture/compare 3 interrupt enable + 3 + 1 + read-write + + + B_0x0 + CC3 interrupt disabled + 0x0 + + + B_0x1 + CC3 interrupt enabled + 0x1 + + + + + CC4IE + Capture/compare 4 interrupt enable + 4 + 1 + read-write + + + B_0x0 + CC4 interrupt disabled + 0x0 + + + B_0x1 + CC4 interrupt enabled + 0x1 + + + + + COMIE + COM interrupt enable + 5 + 1 + read-write + + + B_0x0 + COM interrupt disabled + 0x0 + + + B_0x1 + COM interrupt enabled + 0x1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + read-write + + + B_0x0 + Trigger interrupt disabled + 0x0 + + + B_0x1 + Trigger interrupt enabled + 0x1 + + + + + BIE + Break interrupt enable + 7 + 1 + read-write + + + B_0x0 + Break interrupt disabled + 0x0 + + + B_0x1 + Break interrupt enabled + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled + 0x0 + + + B_0x1 + Update DMA request enabled + 0x1 + + + + + CC1DE + Capture/compare 1 DMA request enable + 9 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled + 0x0 + + + B_0x1 + CC1 DMA request enabled + 0x1 + + + + + CC2DE + Capture/compare 2 DMA request enable + 10 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled + 0x0 + + + B_0x1 + CC2 DMA request enabled + 0x1 + + + + + CC3DE + Capture/compare 3 DMA request enable + 11 + 1 + read-write + + + B_0x0 + CC3 DMA request disabled + 0x0 + + + B_0x1 + CC3 DMA request enabled + 0x1 + + + + + CC4DE + Capture/compare 4 DMA request enable + 12 + 1 + read-write + + + B_0x0 + CC4 DMA request disabled + 0x0 + + + B_0x1 + CC4 DMA request enabled + 0x1 + + + + + COMDE + COM DMA request enable + 13 + 1 + read-write + + + B_0x0 + COM DMA request disabled + 0x0 + + + B_0x1 + COM DMA request enabled + 0x1 + + + + + TDE + Trigger DMA request enable + 14 + 1 + read-write + + + B_0x0 + Trigger DMA request disabled + 0x0 + + + B_0x1 + Trigger DMA request enabled + 0x1 + + + + + IDXIE + Index interrupt enable + 20 + 1 + read-write + + + B_0x0 + Index interrupt disabled + 0x0 + + + B_0x1 + Index Change interrupt enabled + 0x1 + + + + + DIRIE + Direction change interrupt enable + 21 + 1 + read-write + + + B_0x0 + Direction Change interrupt disabled + 0x0 + + + B_0x1 + Direction Change interrupt enabled + 0x1 + + + + + IERRIE + Index error interrupt enable + 22 + 1 + read-write + + + B_0x0 + Index error interrupt disabled + 0x0 + + + B_0x1 + Index error interrupt enabled + 0x1 + + + + + TERRIE + Transition error interrupt enable + 23 + 1 + read-write + + + B_0x0 + Transition error interrupt disabled + 0x0 + + + B_0x1 + Transition error interrupt enabled + 0x1 + + + + + + + TIM1_SR + TIM1_SR + TIM1 status register + 0x010 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UIF + Update interrupt flag + + 0 + 1 + read-write + + + B_0x0 + No update occurred. + 0x0 + + + B_0x1 + Update interrupt pending. + 0x1 + + + + + CC1IF + Capture/compare 1 interrupt flag + + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred + 0x1 + + + + + CC2IF + Capture/compare 2 interrupt flag + + 2 + 1 + read-write + + + CC3IF + Capture/compare 3 interrupt flag + + 3 + 1 + read-write + + + CC4IF + Capture/compare 4 interrupt flag + + 4 + 1 + read-write + + + COMIF + COM interrupt flag + + 5 + 1 + read-write + + + B_0x0 + No COM event occurred. + 0x0 + + + B_0x1 + COM interrupt pending. + 0x1 + + + + + TIF + Trigger interrupt flag + + 6 + 1 + read-write + + + B_0x0 + No trigger event occurred. + 0x0 + + + B_0x1 + Trigger interrupt pending. + 0x1 + + + + + BIF + Break interrupt flag + + 7 + 1 + read-write + + + B_0x0 + No break event occurred. + 0x0 + + + B_0x1 + An active level has been detected on the break input. + 0x1 + + + + + B2IF + Break 2 interrupt flag + + 8 + 1 + read-write + + + B_0x0 + No break event occurred. + 0x0 + + + B_0x1 + An active level has been detected on the break 2 input. + 0x1 + + + + + CC1OF + Capture/compare 1 overcapture flag + + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + CC2OF + Capture/compare 2 overcapture flag + + 10 + 1 + read-write + + + CC3OF + Capture/compare 3 overcapture flag + + 11 + 1 + read-write + + + CC4OF + Capture/compare 4 overcapture flag + + 12 + 1 + read-write + + + SBIF + System break interrupt flag + + 13 + 1 + read-write + + + B_0x0 + No break event occurred. + 0x0 + + + B_0x1 + An active level has been detected on the system break input. + 0x1 + + + + + CC5IF + Compare 5 interrupt flag + + 16 + 1 + read-write + + + CC6IF + Compare 6 interrupt flag + + 17 + 1 + read-write + + + IDXF + Index interrupt flag + + 20 + 1 + read-write + + + B_0x0 + No index event occurred. + 0x0 + + + B_0x1 + An index event has occurred + 0x1 + + + + + DIRF + Direction change interrupt flag + + 21 + 1 + read-write + + + B_0x0 + No direction change + 0x0 + + + B_0x1 + Direction change + 0x1 + + + + + IERRF + Index error interrupt flag + + 22 + 1 + read-write + + + B_0x0 + No index error has been detected. + 0x0 + + + B_0x1 + An index error has been detected + 0x1 + + + + + TERRF + Transition error interrupt flag + + 23 + 1 + read-write + + + B_0x0 + No encoder transition error has been detected. + 0x0 + + + B_0x1 + An encoder transition error has been detected + 0x1 + + + + + + + TIM1_EGR + TIM1_EGR + TIM1 event generation register + 0x014 + 16 + write-only + 0x0000 + 0xFFFF + + + UG + Update generation + + 0 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Reinitialize the counter and generates an update of the registers. + 0x1 + + + + + CC1G + Capture/compare 1 generation + + 1 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + CC2G + Capture/compare 2 generation + + 2 + 1 + write-only + + + CC3G + Capture/compare 3 generation + + 3 + 1 + write-only + + + CC4G + Capture/compare 4 generation + + 4 + 1 + write-only + + + COMG + Capture/compare control update generation + + 5 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + CCxE, CCxNE and OCxM bits update (providing CCPC bit is set) + 0x1 + + + + + TG + Trigger generation + + 6 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + The TIF flag is set in TIMx_SR register. + 0x1 + + + + + BG + Break generation + + 7 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A break event is generated. + 0x1 + + + + + B2G + Break 2 generation + + 8 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A break 2 event is generated. + 0x1 + + + + + + + TIM1_CCMR1 + TIM1_CCMR1 + TIM1 capture/compare mode register 1 + 0x018 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/compare 1 Selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. + 0x3 + + + + + IC1PSC + Input capture 1 prescaler + + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter + + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + CC2S + Capture/compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. + 0x3 + + + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + read-write + + + IC2F + Input capture 2 filter + 12 + 4 + read-write + + + + + TIM1_CCMR1_ALTERNATE1 + TIM1_CCMR1_ALTERNATE1 + TIM1 capture/compare mode register 1 + TIM1_CCMR1 + 0x018 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. + 0x3 + + + + + OC1FE + Output compare 1 fast enable + + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. + 0x1 + + + + + OC1PE + Output compare 1 preload enable + + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. + 0x1 + + + + + OC1M + OC1M[2:0]: Output compare 1 mode + + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. + 0x2 + + + B_0x3 + Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - tim_oc1ref is forced low. + 0x4 + + + B_0x5 + Force active level - tim_oc1ref is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. + 0x6 + + + B_0x7 + PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. + 0x7 + + + + + OC1CE + Output compare 1 clear enable + 7 + 1 + read-write + + + B_0x0 + tim_oc1ref is not affected by the tim_ocref_clr_int signal + 0x0 + + + B_0x1 + tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr_int signal (tim_ocref_clr input or tim_etrf input) + 0x1 + + + + + CC2S + Capture/compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. + 0x3 + + + + + OC2FE + Output compare 2 fast enable + 10 + 1 + read-write + + + OC2PE + Output compare 2 preload enable + 11 + 1 + read-write + + + OC2M + OC2M[2:0]: Output compare 2 mode + 12 + 3 + read-write + + + OC2CE + Output compare 2 clear enable + 15 + 1 + read-write + + + OC1M_1 + OC1M[3] + 16 + 1 + read-write + + + OC2M_1 + OC2M[3] + 24 + 1 + read-write + + + + + TIM1_CCMR2 + TIM1_CCMR2 + TIM1 capture/compare mode register 2 + 0x01C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/compare 3 selection + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. + 0x3 + + + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + read-write + + + IC3F + Input capture 3 filter + 4 + 4 + read-write + + + CC4S + Capture/compare 4 selection + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. + 0x3 + + + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + read-write + + + IC4F + Input capture 4 filter + 12 + 4 + read-write + + + + + TIM1_CCMR2_ALTERNATE1 + TIM1_CCMR2_ALTERNATE1 + TIM1 capture/compare mode register 2 + TIM1_CCMR2 + 0x01C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/compare 3 selection + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. + 0x3 + + + + + OC3FE + Output compare 3 fast enable + 2 + 1 + read-write + + + OC3PE + Output compare 3 preload enable + 3 + 1 + read-write + + + OC3M + OC3M[2:0]: Output compare 3 mode + + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR3 and the counter TIMx_CNT has no effect on the outputs. + 0x0 + + + B_0x1 + Set channel 3 to active level on match. + 0x1 + + + B_0x2 + Set channel 3 to inactive level on match. + 0x2 + + + B_0x3 + Toggle - tim_oc3ref toggles when TIMx_CNT=TIMx_CCR3. + 0x3 + + + B_0x4 + Force inactive level - tim_oc3ref is forced low. + 0x4 + + + B_0x5 + Force active level - tim_oc3ref is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - In upcounting, channel 3 is active as long as TIMx_CNTless thanTIMx_CCR3 else inactive. + 0x6 + + + B_0x7 + PWM mode 2 - In upcounting, channel 3 is inactive as long as TIMx_CNTless thanTIMx_CCR3 else active. + 0x7 + + + + + OC3CE + Output compare 3 clear enable + 7 + 1 + read-write + + + CC4S + Capture/compare 4 selection + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. + 0x3 + + + + + OC4FE + Output compare 4 fast enable + 10 + 1 + read-write + + + OC4PE + Output compare 4 preload enable + 11 + 1 + read-write + + + OC4M + OC4M[2:0]: Output compare 4 mode + + 12 + 3 + read-write + + + OC4CE + Output compare 4 clear enable + 15 + 1 + read-write + + + OC3M_1 + OC3M[3] + 16 + 1 + read-write + + + OC4M_1 + OC4M[3] + 24 + 1 + read-write + + + + + TIM1_CCER + TIM1_CCER + TIM1 capture/compare enable register + 0x020 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1E + Capture/compare 1 output enable + + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active (see below) + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/compare 1 output polarity + + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NE + Capture/compare 1 complementary output enable + + 2 + 1 + read-write + + + B_0x0 + Off - tim_oc1n is not active. + 0x0 + + + B_0x1 + On - tim_oc1n signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. + 0x1 + + + + + CC1NP + Capture/compare 1 complementary output polarity + + 3 + 1 + read-write + + + B_0x0 + tim_oc1n active high. + 0x0 + + + B_0x1 + tim_oc1n active low. + 0x1 + + + + + CC2E + Capture/compare 2 output enable + + 4 + 1 + read-write + + + CC2P + Capture/compare 2 output polarity + + 5 + 1 + read-write + + + CC2NE + Capture/compare 2 complementary output enable + + 6 + 1 + read-write + + + CC2NP + Capture/compare 2 complementary output polarity + + 7 + 1 + read-write + + + CC3E + Capture/compare 3 output enable + + 8 + 1 + read-write + + + CC3P + Capture/compare 3 output polarity + + 9 + 1 + read-write + + + CC3NE + Capture/compare 3 complementary output enable + + 10 + 1 + read-write + + + CC3NP + Capture/compare 3 complementary output polarity + + 11 + 1 + read-write + + + CC4E + Capture/compare 4 output enable + + 12 + 1 + read-write + + + CC4P + Capture/compare 4 output polarity + + 13 + 1 + read-write + + + CC4NE + Capture/compare 4 complementary output enable + + 14 + 1 + read-write + + + CC4NP + Capture/compare 4 complementary output polarity + + 15 + 1 + read-write + + + CC5E + Capture/compare 5 output enable + + 16 + 1 + read-write + + + CC5P + Capture/compare 5 output polarity + + 17 + 1 + read-write + + + CC6E + Capture/compare 6 output enable + + 20 + 1 + read-write + + + CC6P + Capture/compare 6 output polarity + + 21 + 1 + read-write + + + + + TIM1_CNT + TIM1_CNT + TIM1 counter + 0x024 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + + 0 + 16 + read-write + + + UIFCPY + UIF copy + + 31 + 1 + read-only + + + + + TIM1_PSC + TIM1_PSC + TIM1 prescaler + 0x028 + 16 + read-write + 0x0000 + 0xFFFF + + + PSC + Prescaler value + + 0 + 16 + read-write + + + + + TIM1_ARR + TIM1_ARR + TIM1 auto-reload register + 0x02C + 0x20 + read-write + 0x0000FFFF + 0xFFFFFFFF + + + ARR + Auto-reload value + + 0 + 20 + read-write + + + + + TIM1_RCR + TIM1_RCR + TIM1 repetition counter register + 0x030 + 16 + read-write + 0x0000 + 0xFFFF + + + REP + Repetition counter reload value + + 0 + 16 + read-write + + + + + TIM1_CCR1 + TIM1_CCR1 + TIM1 capture/compare register 1 + 0x034 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR1 + Capture/compare 1 value + + 0 + 20 + read-write + + + + + TIM1_CCR2 + TIM1_CCR2 + TIM1 capture/compare register 2 + 0x038 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR2 + Capture/compare 2 value + + 0 + 20 + read-write + + + + + TIM1_CCR3 + TIM1_CCR3 + TIM1 capture/compare register 3 + 0x03C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR3 + Capture/compare value + + 0 + 20 + read-write + + + + + TIM1_CCR4 + TIM1_CCR4 + TIM1 capture/compare register 4 + 0x040 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR4 + Capture/compare value + + 0 + 20 + read-write + + + + + TIM1_BDTR + TIM1_BDTR + TIM1 break and dead-time register + 0x044 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DTG + Dead-time generator setup + + 0 + 8 + read-write + + + LOCK + Lock configuration + + 8 + 2 + read-write + + + B_0x0 + LOCK OFF - No bit is write protected. + 0x0 + + + B_0x1 + LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BK2BID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written. + 0x1 + + + B_0x2 + LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. + 0x2 + + + B_0x3 + LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. + 0x3 + + + + + OSSI + Off-state selection for idle mode + + 10 + 1 + read-write + + + B_0x0 + When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic and which imposes a Hi-Z state). + 0x0 + + + B_0x1 + When inactive, OC/OCN outputs are first forced with their inactive level then forced to their idle level after the deadtime. + 0x1 + + + + + OSSR + Off-state selection for Run mode + + 11 + 1 + read-write + + + B_0x0 + When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic, which forces a Hi-Z state). + 0x0 + + + B_0x1 + When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer). + 0x1 + + + + + BKE + Break enable + + 12 + 1 + read-write + + + B_0x0 + Break function disabled + 0x0 + + + B_0x1 + Break function enabled + 0x1 + + + + + BKP + Break polarity + + 13 + 1 + read-write + + + B_0x0 + Break input tim_brk is active low + 0x0 + + + B_0x1 + Break input tim_brk is active high + 0x1 + + + + + AOE + Automatic output enable + + 14 + 1 + read-write + + + B_0x0 + MOE can be set only by software + 0x0 + + + B_0x1 + MOE can be set by software or automatically at the next update event (if none of the break inputs tim_brk and tim_brk2 is active) + 0x1 + + + + + MOE + Main output enable + + 15 + 1 + read-write + + + B_0x0 + In response to a break 2 event. + 0x0 + + + B_0x1 + OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register). + 0x1 + + + + + BKF + Break filter + + 16 + 4 + read-write + + + B_0x0 + No filter, tim_brk acts asynchronously + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + BK2F + Break 2 filter + + 20 + 4 + read-write + + + B_0x0 + No filter, tim_brk2 acts asynchronously + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + BK2E + Break 2 enable + + 24 + 1 + read-write + + + B_0x0 + Break2 function disabled + 0x0 + + + B_0x1 + Break2 function enabled + 0x1 + + + + + BK2P + Break 2 polarity + + 25 + 1 + read-write + + + B_0x0 + Break input tim_brk2 is active low + 0x0 + + + B_0x1 + Break input tim_brk2 is active high + 0x1 + + + + + BKDSRM + Break disarm + + 26 + 1 + read-write + + + B_0x0 + Break input tim_brk is armed + 0x0 + + + B_0x1 + Break input tim_brk is disarmed + 0x1 + + + + + BK2DSRM + Break2 disarm + + 27 + 1 + read-write + + + BKBID + Break bidirectional + + 28 + 1 + read-write + + + B_0x0 + Break input tim_brk in input mode + 0x0 + + + B_0x1 + Break input tim_brk in bidirectional mode + 0x1 + + + + + BK2BID + Break2 bidirectional + + 29 + 1 + read-write + + + + + TIM1_CCR5 + TIM1_CCR5 + TIM1 capture/compare register 5 + 0x048 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR5 + Capture/compare 5 value + + 0 + 20 + read-write + + + GC5C1 + Group channel 5 and channel 1 + + 29 + 1 + read-write + + + B_0x0 + No effect of oc5ref on oc1refc + 0x0 + + + B_0x1 + oc1refc is the logical AND of oc1ref and oc5ref + 0x1 + + + + + GC5C2 + Group channel 5 and channel 2 + + 30 + 1 + read-write + + + B_0x0 + No effect of tim_oc5ref on tim_oc2refc + 0x0 + + + B_0x1 + tim_oc2refc is the logical AND of tim_oc2ref and tim_oc5ref + 0x1 + + + + + GC5C3 + Group channel 5 and channel 3 + + 31 + 1 + read-write + + + B_0x0 + No effect of tim_oc5ref on tim_oc3refc + 0x0 + + + B_0x1 + tim_oc3refc is the logical AND of tim_oc3ref and tim_oc5ref + 0x1 + + + + + + + TIM1_CCR6 + TIM1_CCR6 + TIM1 capture/compare register 6 + 0x04C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR6 + Capture/compare 6 value + + 0 + 20 + read-write + + + + + TIM1_CCMR3 + TIM1_CCMR3 + TIM1 capture/compare mode register 3 + 0x050 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OC5FE + Output compare 5 fast enable + 2 + 1 + read-write + + + OC5PE + Output compare 5 preload enable + 3 + 1 + read-write + + + OC5M + OC5M[2:0]: Output compare 5 mode + 4 + 3 + read-write + + + OC5CE + Output compare 5 clear enable + 7 + 1 + read-write + + + OC6FE + Output compare 6 fast enable + 10 + 1 + read-write + + + OC6PE + Output compare 6 preload enable + 11 + 1 + read-write + + + OC6M + OC6M[2:0]: Output compare 6 mode + 12 + 3 + read-write + + + OC6CE + Output compare 6 clear enable + 15 + 1 + read-write + + + OC5M_1 + OC5M[3] + 16 + 1 + read-write + + + OC6M_1 + OC6M[3] + 24 + 1 + read-write + + + + + TIM1_DTR2 + TIM1_DTR2 + TIM1 timer deadtime register 2 + 0x054 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DTGF + Dead-time falling edge generator setup + + 0 + 8 + read-write + + + DTAE + Deadtime asymmetric enable + + 16 + 1 + read-write + + + B_0x0 + Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register + 0x0 + + + B_0x1 + Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits. + 0x1 + + + + + DTPE + Deadtime preload enable + + 17 + 1 + read-write + + + B_0x0 + Deadtime value is not preloaded + 0x0 + + + B_0x1 + Deadtime value preload is enabled + 0x1 + + + + + + + TIM1_ECR + TIM1_ECR + TIM1 timer encoder control register + 0x058 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IE + Index enable + + 0 + 1 + read-write + + + B_0x0 + Index disabled + 0x0 + + + B_0x1 + Index enabled + 0x1 + + + + + IDIR + Index direction + + 1 + 2 + read-write + + + B_0x0 + Index resets the counter whatever the direction + 0x0 + + + B_0x1 + Index resets the counter when up-counting only + 0x1 + + + B_0x2 + Index resets the counter when down-counting only + 0x2 + + + + + IBLK + Index blanking + + 3 + 2 + read-write + + + B_0x0 + Index always active + 0x0 + + + B_0x1 + Index disabled when tim_ti3 input is active, as per CC3P bitfield + 0x1 + + + B_0x2 + Index disabled when tim_ti4 input is active, as per CC4P bitfield + 0x2 + + + + + FIDX + First index + + 5 + 1 + read-write + + + B_0x0 + Index is always active + 0x0 + + + B_0x1 + the first Index only resets the counter + 0x1 + + + + + IPOS + Index positioning + + 6 + 2 + read-write + + + B_0x0 + Index resets the counter when AB = 00 + 0x0 + + + B_0x1 + Index resets the counter when AB = 01 + 0x1 + + + B_0x2 + Index resets the counter when AB = 10 + 0x2 + + + B_0x3 + Index resets the counter when AB = 11 + 0x3 + + + + + PW + Pulse width + + 16 + 8 + read-write + + + PWPRSC + Pulse width prescaler + + 24 + 3 + read-write + + + + + TIM1_TISEL + TIM1_TISEL + TIM1 timer input selection register + 0x05C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + Selects tim_ti1[15:0] input + + 0 + 4 + read-write + + + B_0x0 + tim_ti1_in0: TIMx_CH1 + 0x0 + + + B_0x1 + tim_ti1_in1 + 0x1 + + + B_0xF + tim_ti1_in15 + 0xF + + + + + TI2SEL + Selects tim_ti2[15:0] input + + 8 + 4 + read-write + + + B_0x0 + tim_ti2_in0: TIMx_CH2 + 0x0 + + + B_0x1 + tim_ti2_in1 + 0x1 + + + B_0xF + tim_ti2_in15 + 0xF + + + + + TI3SEL + Selects tim_ti3[15:0] input + + 16 + 4 + read-write + + + B_0x0 + tim_ti3_in0: TIMx_CH2 + 0x0 + + + B_0x1 + tim_ti3_in1 + 0x1 + + + B_0xF + tim_ti3_in15 + 0xF + + + + + TI4SEL + Selects tim_ti4[15:0] input + + 24 + 4 + read-write + + + B_0x0 + tim_ti4_in0: TIMx_CH4 + 0x0 + + + B_0x1 + tim_ti4_in1 + 0x1 + + + B_0xF + tim_ti4_in15 + 0xF + + + + + + + TIM1_AF1 + TIM1_AF1 + TIM1 alternate function option register 1 + 0x060 + 0x20 + read-write + 0x00000001 + 0xFFFFFFFF + + + BKINE + TIMx_BKIN input enable + + 0 + 1 + read-write + + + B_0x0 + TIMx_BKIN input disabled + 0x0 + + + B_0x1 + TIMx_BKIN input enabled + 0x1 + + + + + BKCMP1E + tim_brk_cmp1 enable + + 1 + 1 + read-write + + + B_0x0 + tim_brk_cmp1 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp1 input enabled + 0x1 + + + + + BKCMP2E + tim_brk_cmp2 enable + + 2 + 1 + read-write + + + B_0x0 + tim_brk_cmp2 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp2 input enabled + 0x1 + + + + + BKCMP3E + tim_brk_cmp3 enable + + 3 + 1 + read-write + + + B_0x0 + tim_brk_cmp3 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp3 input enabled + 0x1 + + + + + BKCMP4E + tim_brk_cmp4 enable + + 4 + 1 + read-write + + + B_0x0 + tim_brk_cmp4 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp4 input enabled + 0x1 + + + + + BKCMP5E + tim_brk_cmp5 enable + + 5 + 1 + read-write + + + B_0x0 + tim_brk_cmp5 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp5 input enabled + 0x1 + + + + + BKCMP6E + tim_brk_cmp6 enable + + 6 + 1 + read-write + + + B_0x0 + tim_brk_cmp6 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp6 input enabled + 0x1 + + + + + BKCMP7E + tim_brk_cmp7 enable + + 7 + 1 + read-write + + + B_0x0 + tim_brk_cmp7 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp7 input enabled + 0x1 + + + + + BKCMP8E + tim_brk_cmp8 enable + + 8 + 1 + read-write + + + B_0x0 + tim_brk_cmp8 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp8 input enabled + 0x1 + + + + + BKINP + TIMx_BKIN input polarity + + 9 + 1 + read-write + + + B_0x0 + TIMx_BKIN input polarity is not inverted (active low if BKP = 0, active high if BKP = 1) + 0x0 + + + B_0x1 + TIMx_BKIN input polarity is inverted (active high if BKP = 0, active low if BKP = 1) + 0x1 + + + + + BKCMP1P + tim_brk_cmp1 input polarity + + 10 + 1 + read-write + + + B_0x0 + tim_brk_cmp1 input polarity is not inverted (active low if BKP = 0, active high if BKP = 1) + 0x0 + + + B_0x1 + tim_brk_cmp1 input polarity is inverted (active high if BKP = 0, active low if BKP = 1) + 0x1 + + + + + BKCMP2P + tim_brk_cmp2 input polarity + + 11 + 1 + read-write + + + B_0x0 + tim_brk_cmp2 input polarity is not inverted (active low if BKP = 0, active high if BKP = 1) + 0x0 + + + B_0x1 + tim_brk_cmp2 input polarity is inverted (active high if BKP = 0, active low if BKP = 1) + 0x1 + + + + + BKCMP3P + tim_brk_cmp3 input polarity + + 12 + 1 + read-write + + + B_0x0 + tim_brk_cmp3 input polarity is not inverted (active low if BKP = 0, active high if BKP = 1) + 0x0 + + + B_0x1 + tim_brk_cmp3 input polarity is inverted (active high if BKP = 0, active low if BKP = 1) + 0x1 + + + + + BKCMP4P + tim_brk_cmp4 input polarity + + 13 + 1 + read-write + + + B_0x0 + tim_brk_cmp4 input polarity is not inverted (active low if BKP = 0, active high if BKP = 1) + 0x0 + + + B_0x1 + tim_brk_cmp4 input polarity is inverted (active high if BKP = 0, active low if BKP = 1) + 0x1 + + + + + ETRSEL + etr_in source selection + + 14 + 4 + read-write + + + B_0x0 + tim_etr0: TIMx_ETR input + 0x0 + + + B_0x1 + tim_etr1 + 0x1 + + + B_0xF + tim_etr15 + 0xF + + + + + + + TIM1_AF2 + TIM1_AF2 + TIM1 alternate function register 2 + 0x064 + 0x20 + read-write + 0x00000001 + 0xFFFFFFFF + + + BK2INE + TIMx_BKIN2 input enable + + 0 + 1 + read-write + + + B_0x0 + TIMx_BKIN2 input disabled + 0x0 + + + B_0x1 + TIMx_BKIN2 input enabled + 0x1 + + + + + BK2CMP1E + tim_brk2_cmp1 enable + + 1 + 1 + read-write + + + B_0x0 + tim_brk2_cmp1 input disabled + 0x0 + + + B_0x1 + tim_brk2_cmp1 input enabled + 0x1 + + + + + BK2CMP2E + tim_brk2_cmp2 enable + + 2 + 1 + read-write + + + B_0x0 + tim_brk2_cmp2 input disabled + 0x0 + + + B_0x1 + tim_brk2_cmp2 input enabled + 0x1 + + + + + BK2CMP3E + tim_brk2_cmp3 enable + + 3 + 1 + read-write + + + B_0x0 + tim_brk2_cmp3 input disabled + 0x0 + + + B_0x1 + tim_brk2_cmp3 input enabled + 0x1 + + + + + BK2CMP4E + tim_brk2_cmp4 enable + + 4 + 1 + read-write + + + B_0x0 + tim_brk2_cmp4 input disabled + 0x0 + + + B_0x1 + tim_brk2_cmp4 input enabled + 0x1 + + + + + BK2CMP5E + tim_brk2_cmp5 enable + + 5 + 1 + read-write + + + B_0x0 + tim_brk2_cmp5 input disabled + 0x0 + + + B_0x1 + tim_brk2_cmp5 input enabled + 0x1 + + + + + BK2CMP6E + tim_brk2_cmp6 enable + + 6 + 1 + read-write + + + B_0x0 + tim_brk2_cmp6 input disabled + 0x0 + + + B_0x1 + tim_brk2_cmp6 input enabled + 0x1 + + + + + BK2CMP7E + tim_brk2_cmp7 enable + + 7 + 1 + read-write + + + B_0x0 + tim_brk2_cmp7 input disabled + 0x0 + + + B_0x1 + tim_brk2_cmp7 input enabled + 0x1 + + + + + BK2CMP8E + tim_brk2_cmp8 enable + + 8 + 1 + read-write + + + B_0x0 + tim_brk2_cmp8 input disabled + 0x0 + + + B_0x1 + tim_brk2_cmp8 input enabled + 0x1 + + + + + BK2INP + TIMx_BKIN2 input polarity + + 9 + 1 + read-write + + + B_0x0 + TIMx_BKIN2 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1) + 0x0 + + + B_0x1 + TIMx_BKIN2 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1) + 0x1 + + + + + BK2CMP1P + tim_brk2_cmp1 input polarity + + 10 + 1 + read-write + + + B_0x0 + tim_brk2_cmp1 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1) + 0x0 + + + B_0x1 + tim_brk2_cmp1 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1) + 0x1 + + + + + BK2CMP2P + tim_brk2_cmp2 input polarity + + 11 + 1 + read-write + + + B_0x0 + tim_brk2_cmp2 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1) + 0x0 + + + B_0x1 + tim_brk2_cmp2 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1) + 0x1 + + + + + BK2CMP3P + tim_brk2_cmp3 input polarity + + 12 + 1 + read-write + + + B_0x0 + tim_brk2_cmp3 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1) + 0x0 + + + B_0x1 + tim_brk2_cmp3 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1) + 0x1 + + + + + BK2CMP4P + tim_brk2_cmp4 input polarity + + 13 + 1 + read-write + + + B_0x0 + tim_brk2_cmp4 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1) + 0x0 + + + B_0x1 + tim_brk2_cmp4 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1) + 0x1 + + + + + OCRSEL + ocref_clr source selection + + 16 + 3 + read-write + + + B_0x0 + tim_ocref_clr0 + 0x0 + + + B_0x1 + tim_ocref_clr1 + 0x1 + + + B_0x7 + tim_ocref_clr7 + 0x7 + + + + + + + TIM1_DCR + TIM1_DCR + TIM1 DMA control register + 0x3DC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DBA + DMA base address + + 0 + 5 + read-write + + + B_0x0 + TIMx_CR1 + 0x0 + + + B_0x1 + TIMx_CR2 + 0x1 + + + B_0x2 + TIMx_SMCR + 0x2 + + + + + DBL + DMA burst length + + 8 + 5 + read-write + + + B_0x0 + 1 transfer + 0x0 + + + B_0x1 + 2 transfers + 0x1 + + + B_0x2 + 3 transfers + 0x2 + + + B_0x1A + 26 transfers + 0x1A + + + + + DBSS + DMA burst source selection + + 16 + 4 + read-write + + + B_0x1 + Update + 0x1 + + + B_0x2 + CC1 + 0x2 + + + B_0x3 + CC2 + 0x3 + + + B_0x4 + CC3 + 0x4 + + + B_0x5 + CC4 + 0x5 + + + B_0x6 + COM + 0x6 + + + B_0x7 + Trigger + 0x7 + + + + + + + TIM1_DMAR + TIM1_DMAR + TIM1 DMA address for full transfer + 0x3E0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DMAB + DMA register for burst accesses + + 0 + 32 + read-write + + + + + + + TIM1_S + 0X50012C00 + + + TIM2 + TIM2 address block description + TIM2 + 0x40000000 + + 0x0 + 0x3E4 + registers + + + TIM2 + TIM2 global interrupt + 45 + + + + TIM2_CR1 + TIM2_CR1 + TIM2 control register 1 + 0x000 + 16 + read-write + 0x0000 + 0xFFFF + + + CEN + Counter enable + + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable + + 1 + 1 + read-write + + + B_0x0 + UEV enabled. + 0x0 + + + B_0x1 + UEV disabled. + 0x1 + + + + + URS + Update request source + + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt or DMA request if enabled. + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + DIR + Direction + + 4 + 1 + read-write + + + B_0x0 + Counter used as upcounter + 0x0 + + + B_0x1 + Counter used as downcounter + 0x1 + + + + + CMS + Center-aligned mode selection + + 5 + 2 + read-write + + + B_0x0 + Edge-aligned mode. + 0x0 + + + B_0x1 + Center-aligned mode 1. + 0x1 + + + B_0x2 + Center-aligned mode 2. + 0x2 + + + B_0x3 + Center-aligned mode 3. + 0x3 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division + + 8 + 2 + read-write + + + B_0x0 + tless thansub>DTSless than/sub> = tless thansub>tim_ker_ckless than/sub> + 0x0 + + + B_0x1 + tless thansub>DTSless than/sub> = 2 tless thansub>tim_ker_ckless than/sub> + 0x1 + + + B_0x2 + tless thansub>DTSless than/sub> = 4 tless thansub>tim_ker_ckless than/sub> + 0x2 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. + 0x0 + + + B_0x1 + Remapping enabled. + 0x1 + + + + + DITHEN + Dithering Enable + + 12 + 1 + read-write + + + B_0x0 + Dithering disabled + 0x0 + + + B_0x1 + Dithering enabled + 0x1 + + + + + + + TIM2_CR2 + TIM2_CR2 + TIM2 control register 2 + 0x004 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCDS + Capture/compare DMA selection + 3 + 1 + read-write + + + B_0x0 + CCx DMA request sent when CCx event occurs + 0x0 + + + B_0x1 + CCx DMA requests sent when update event occurs + 0x1 + + + + + MMS + MMS[2:0]: Master mode selection + + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo). + 0x0 + + + B_0x1 + Enable - the Counter enable signal, CNT_EN, is used as trigger output (tim_trgo). + 0x1 + + + B_0x2 + Update - The update event is selected as trigger output (tim_trgo). + 0x2 + + + B_0x3 + Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred (tim_trgo). + 0x3 + + + B_0x4 + Compare - tim_oc1refc signal is used as trigger output (tim_trgo) + 0x4 + + + B_0x5 + Compare - tim_oc2refc signal is used as trigger output (tim_trgo) + 0x5 + + + B_0x6 + Compare - tim_oc3refc signal is used as trigger output (tim_trgo) + 0x6 + + + B_0x7 + Compare - tim_oc4refc signal is used as trigger output (tim_trgo) + 0x7 + + + + + TI1S + tim_ti1 selection + 7 + 1 + read-write + + + B_0x0 + The tim_ti1_in[15:0] multiplexer output is to tim_ti1 input + 0x0 + + + B_0x1 + The tim_ti1_in[15:0], tim_ti2_in[15:0] and tim_ti3_in[15:0] multiplexers outputs are XORed and connected to the tim_ti1 input. + 0x1 + + + + + MMS_1 + MMS[3] + 25 + 1 + read-write + + + + + TIM2_SMCR + TIM2_SMCR + TIM2 slave mode control register + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SMS + SMS[2:0]: Slave mode selection + + 0 + 3 + read-write + + + B_0x0 + Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level. + 0x1 + + + B_0x2 + Encoder mode 2 - Counter counts up/down on tim_ti2fp2 edge depending on tim_ti1fp1 level. + 0x2 + + + B_0x3 + Encoder mode 3 - Counter counts up/down on both tim_ti1fp1 and tim_ti2fp2 edges depending on the level of the other input. + 0x3 + + + B_0x4 + Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers. + 0x4 + + + B_0x5 + Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high. + 0x5 + + + B_0x6 + Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). + 0x6 + + + B_0x7 + External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter. + 0x7 + + + + + OCCS + OCREF clear selection + + 3 + 1 + read-write + + + B_0x0 + tim_ocref_clr_int is connected to the tim_ocref_clr input + 0x0 + + + B_0x1 + tim_ocref_clr_int is connected to tim_etrf + 0x1 + + + + + TS + TS[2:0]: Trigger selection + + 4 + 3 + read-write + + + B_0x0 + Internal trigger 0 (tim_itr0) + 0x0 + + + B_0x1 + Internal trigger 1 (tim_itr1) + 0x1 + + + B_0x2 + Internal trigger 2 (tim_itr2) + 0x2 + + + B_0x3 + Internal trigger 3 (tim_itr3) + 0x3 + + + B_0x4 + tim_ti1 edge detector (tim_ti1f_ed) + 0x4 + + + B_0x5 + Filtered timer input 1 (tim_ti1fp1) + 0x5 + + + B_0x6 + Filtered timer input 2 (tim_ti2fp2) + 0x6 + + + B_0x7 + External trigger input (tim_etrf) + 0x7 + + + + + MSM + Master/Slave mode + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). + 0x1 + + + + + ETF + External trigger filter + + 8 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + ETPS + External trigger prescaler + + 12 + 2 + read-write + + + B_0x0 + Prescaler OFF + 0x0 + + + B_0x1 + tim_etrp frequency divided by 2 + 0x1 + + + B_0x2 + tim_etrp frequency divided by 4 + 0x2 + + + B_0x3 + tim_etrp frequency divided by 8 + 0x3 + + + + + ECE + External clock enable + + 14 + 1 + read-write + + + B_0x0 + External clock mode 2 disabled + 0x0 + + + B_0x1 + External clock mode 2 enabled. + 0x1 + + + + + ETP + External trigger polarity + + 15 + 1 + read-write + + + B_0x0 + tim_etr_in is non-inverted, active at high level or rising edge + 0x0 + + + B_0x1 + tim_etr_in is inverted, active at low level or falling edge + 0x1 + + + + + SMS_1 + Slave mode selection +When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (see Input Control register and Control Register description. +Note: The gated mode must not be used if tim_ti1f_ed is selected as the trigger input (TS=00100). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on tim_ti1f, whereas the gated mode checks the level of the trigger signal. +Note: The clock of the slave peripherals (timer, ADC, ...) receiving the tim_trgo signal must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. + 16 + 1 + read-write + + + B_0x0 + Slave mode disabled - if CEN = '1 then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level. + 0x1 + + + + + TS_1 + Trigger selection +This bit-field selects the trigger input to be used to synchronize the counter. +Others: Reserved +See for product specific implementation details. +Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. + 20 + 2 + read-write + + + B_0x0 + Internal trigger 0 (tim_itr0) + 0x0 + + + B_0x1 + Internal trigger 1 (tim_itr1) + 0x1 + + + B_0x2 + Internal trigger 2 (tim_itr2) + 0x2 + + + B_0x3 + Internal trigger 3 (tim_itr3) + 0x3 + + + + + SMSPE + SMS preload enable + + 24 + 1 + read-write + + + B_0x0 + SMS[3:0] bitfield is not preloaded + 0x0 + + + B_0x1 + SMS[3:0] preload is enabled + 0x1 + + + + + SMSPS + SMS preload source + + 25 + 1 + read-write + + + B_0x0 + The transfer is triggered by the Timer's Update event + 0x0 + + + B_0x1 + The transfer is triggered by the Index event + 0x1 + + + + + + + TIM2_DIER + TIM2_DIER + TIM2 DMA/Interrupt enable register + 0x00C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled. + 0x0 + + + B_0x1 + Update interrupt enabled. + 0x1 + + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled. + 0x0 + + + B_0x1 + CC1 interrupt enabled. + 0x1 + + + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + read-write + + + B_0x0 + CC2 interrupt disabled. + 0x0 + + + B_0x1 + CC2 interrupt enabled. + 0x1 + + + + + CC3IE + Capture/Compare 3 interrupt enable + 3 + 1 + read-write + + + B_0x0 + CC3 interrupt disabled. + 0x0 + + + B_0x1 + CC3 interrupt enabled. + 0x1 + + + + + CC4IE + Capture/Compare 4 interrupt enable + 4 + 1 + read-write + + + B_0x0 + CC4 interrupt disabled. + 0x0 + + + B_0x1 + CC4 interrupt enabled. + 0x1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + read-write + + + B_0x0 + Trigger interrupt disabled. + 0x0 + + + B_0x1 + Trigger interrupt enabled. + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled. + 0x0 + + + B_0x1 + Update DMA request enabled. + 0x1 + + + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled. + 0x0 + + + B_0x1 + CC1 DMA request enabled. + 0x1 + + + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled. + 0x0 + + + B_0x1 + CC2 DMA request enabled. + 0x1 + + + + + CC3DE + Capture/Compare 3 DMA request enable + 11 + 1 + read-write + + + B_0x0 + CC3 DMA request disabled. + 0x0 + + + B_0x1 + CC3 DMA request enabled. + 0x1 + + + + + CC4DE + Capture/Compare 4 DMA request enable + 12 + 1 + read-write + + + B_0x0 + CC4 DMA request disabled. + 0x0 + + + B_0x1 + CC4 DMA request enabled. + 0x1 + + + + + TDE + Trigger DMA request enable + 14 + 1 + read-write + + + B_0x0 + Trigger DMA request disabled. + 0x0 + + + B_0x1 + Trigger DMA request enabled. + 0x1 + + + + + IDXIE + Index interrupt enable + 20 + 1 + read-write + + + B_0x0 + Index interrupt disabled + 0x0 + + + B_0x1 + Index interrupt enabled + 0x1 + + + + + DIRIE + Direction change interrupt enable + 21 + 1 + read-write + + + B_0x0 + Direction change interrupt disabled + 0x0 + + + B_0x1 + Direction change interrupt enabled + 0x1 + + + + + IERRIE + Index error interrupt enable + 22 + 1 + read-write + + + B_0x0 + Index error interrupt disabled + 0x0 + + + B_0x1 + Index error interrupt enabled + 0x1 + + + + + TERRIE + Transition error interrupt enable + 23 + 1 + read-write + + + B_0x0 + Transition error interrupt disabled + 0x0 + + + B_0x1 + Transition error interrupt enabled + 0x1 + + + + + + + TIM2_SR + TIM2_SR + TIM2 status register + 0x010 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UIF + Update interrupt flag + + 0 + 1 + read-write + + + B_0x0 + No update occurred + 0x0 + + + B_0x1 + Update interrupt pending. + 0x1 + + + + + CC1IF + Capture/compare 1 interrupt flag + + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred + 0x1 + + + + + CC2IF + Capture/Compare 2 interrupt flag + + 2 + 1 + read-write + + + CC3IF + Capture/Compare 3 interrupt flag + + 3 + 1 + read-write + + + CC4IF + Capture/Compare 4 interrupt flag + + 4 + 1 + read-write + + + TIF + Trigger interrupt flag + + 6 + 1 + read-write + + + B_0x0 + No trigger event occurred. + 0x0 + + + B_0x1 + Trigger interrupt pending. + 0x1 + + + + + CC1OF + Capture/Compare 1 overcapture flag + + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + CC2OF + Capture/compare 2 overcapture flag + + 10 + 1 + read-write + + + CC3OF + Capture/Compare 3 overcapture flag + + 11 + 1 + read-write + + + CC4OF + Capture/Compare 4 overcapture flag + + 12 + 1 + read-write + + + IDXF + Index interrupt flag + + 20 + 1 + read-write + + + B_0x0 + No index event occurred. + 0x0 + + + B_0x1 + An index event has occurred + 0x1 + + + + + DIRF + Direction change interrupt flag + + 21 + 1 + read-write + + + B_0x0 + No direction change + 0x0 + + + B_0x1 + Direction change + 0x1 + + + + + IERRF + Index error interrupt flag + + 22 + 1 + read-write + + + B_0x0 + No index error has been detected. + 0x0 + + + B_0x1 + An index error has been detected + 0x1 + + + + + TERRF + Transition error interrupt flag + + 23 + 1 + read-write + + + B_0x0 + No encoder transition error has been detected. + 0x0 + + + B_0x1 + An encoder transition error has been detected + 0x1 + + + + + + + TIM2_EGR + TIM2_EGR + TIM2 event generation register + 0x014 + 16 + write-only + 0x0000 + 0xFFFF + + + UG + Update generation + + 0 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Re-initialize the counter and generates an update of the registers. + 0x1 + + + + + CC1G + Capture/compare 1 generation + + 1 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + CC2G + Capture/compare 2 generation + + 2 + 1 + write-only + + + CC3G + Capture/compare 3 generation + + 3 + 1 + write-only + + + CC4G + Capture/compare 4 generation + + 4 + 1 + write-only + + + TG + Trigger generation + + 6 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + The TIF flag is set in TIMx_SR register. + 0x1 + + + + + + + TIM2_CCMR1 + TIM2_CCMR1 + TIM2 capture/compare mode register 1 + 0x018 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. + 0x3 + + + + + IC1PSC + Input capture 1 prescaler + + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter + + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + CC2S + Capture/compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output. + 0x0 + + + B_0x1 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2. + 0x1 + + + B_0x2 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1. + 0x2 + + + B_0x3 + CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. + 0x3 + + + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + read-write + + + IC2F + Input capture 2 filter + 12 + 4 + read-write + + + + + TIM2_CCMR1_ALTERNATE1 + TIM2_CCMR1_ALTERNATE1 + TIM2 capture/compare mode register 1 + TIM2_CCMR1 + 0x018 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output. + 0x0 + + + B_0x1 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1. + 0x1 + + + B_0x2 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2. + 0x2 + + + B_0x3 + CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. + 0x3 + + + + + OC1FE + Output compare 1 fast enable + + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. + 0x1 + + + + + OC1PE + Output compare 1 preload enable + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. + 0x1 + + + + + OC1M + OC1M[2:0]: Output compare 1 mode + + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. + 0x2 + + + B_0x3 + Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - tim_oc1ref is forced low. + 0x4 + + + B_0x5 + Force active level - tim_oc1ref is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. + 0x6 + + + B_0x7 + PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. + 0x7 + + + + + OC1CE + Output compare 1 clear enable + 7 + 1 + read-write + + + B_0x0 + tim_oc1ref is not affected by the tim_ocref_clr_int input + 0x0 + + + B_0x1 + tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr_int input + 0x1 + + + + + CC2S + Capture/Compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. + 0x3 + + + + + OC2FE + Output compare 2 fast enable + 10 + 1 + read-write + + + OC2PE + Output compare 2 preload enable + 11 + 1 + read-write + + + OC2M + OC2M[2:0]: Output compare 2 mode + + 12 + 3 + read-write + + + OC2CE + Output compare 2 clear enable + 15 + 1 + read-write + + + OC1M_1 + OC1M[3] + 16 + 1 + read-write + + + OC2M_1 + OC2M[3] + 24 + 1 + read-write + + + + + TIM2_CCMR2 + TIM2_CCMR2 + TIM2 capture/compare mode register 2 + 0x01C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. + 0x3 + + + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + read-write + + + IC3F + Input capture 3 filter + 4 + 4 + read-write + + + CC4S + Capture/Compare 4 selection + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. + 0x3 + + + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + read-write + + + IC4F + Input capture 4 filter + 12 + 4 + read-write + + + + + TIM2_CCMR2_ALTERNATE1 + TIM2_CCMR2_ALTERNATE1 + TIM2 capture/compare mode register 2 + TIM2_CCMR2 + 0x01C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. + 0x3 + + + + + OC3FE + Output compare 3 fast enable + 2 + 1 + read-write + + + OC3PE + Output compare 3 preload enable + 3 + 1 + read-write + + + OC3M + OC3M[2:0]: Output compare 3 mode + + 4 + 3 + read-write + + + OC3CE + Output compare 3 clear enable + 7 + 1 + read-write + + + CC4S + Capture/Compare 4 selection + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. + 0x3 + + + + + OC4FE + Output compare 4 fast enable + 10 + 1 + read-write + + + OC4PE + Output compare 4 preload enable + 11 + 1 + read-write + + + OC4M + OC4M[2:0]: Output compare 4 mode + + 12 + 3 + read-write + + + OC4CE + Output compare 4 clear enable + 15 + 1 + read-write + + + OC3M_1 + OC3M[3] + 16 + 1 + read-write + + + OC4M_1 + OC4M[3] + 24 + 1 + read-write + + + + + TIM2_CCER + TIM2_CCER + TIM2 capture/compare enable register + 0x020 + 16 + read-write + 0x0000 + 0xFFFF + + + CC1E + Capture/Compare 1 output enable. + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/Compare 1 output Polarity. + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NP + Capture/Compare 1 output Polarity. + 3 + 1 + read-write + + + CC2E + Capture/Compare 2 output enable. + 4 + 1 + read-write + + + CC2P + Capture/Compare 2 output Polarity. + 5 + 1 + read-write + + + CC2NP + Capture/Compare 2 output Polarity. + 7 + 1 + read-write + + + CC3E + Capture/Compare 3 output enable. + 8 + 1 + read-write + + + CC3P + Capture/Compare 3 output Polarity. + 9 + 1 + read-write + + + CC3NP + Capture/Compare 3 output Polarity. + 11 + 1 + read-write + + + CC4E + Capture/Compare 4 output enable. + 12 + 1 + read-write + + + CC4P + Capture/Compare 4 output Polarity. + 13 + 1 + read-write + + + CC4NP + Capture/Compare 4 output Polarity. + 15 + 1 + read-write + + + + + TIM2_CNT + TIM2_CNT + TIM2 counter + 0x024 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Least significant part of counter value + + 0 + 31 + read-write + + + UIFCPY_CNT + Value depends on IUFREMAP in TIMx_CR1. + 31 + 1 + read-write + + + + + TIM2_PSC + TIM2_PSC + TIM2 prescaler + 0x028 + 16 + read-write + 0x0000 + 0xFFFF + + + PSC + Prescaler value + + 0 + 16 + read-write + + + + + TIM2_ARR + TIM2_ARR + TIM2 auto-reload register + 0x02C + 0x20 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + ARR + Auto-reload value + + 0 + 32 + read-write + + + + + TIM2_CCR1 + TIM2_CCR1 + TIM2 capture/compare register 1 + 0x034 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR1 + Capture/compare 1 value + + 0 + 32 + read-write + + + + + TIM2_CCR2 + TIM2_CCR2 + TIM2 capture/compare register 2 + 0x038 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR2 + Capture/compare 2 value + + 0 + 32 + read-write + + + + + TIM2_CCR3 + TIM2_CCR3 + TIM2 capture/compare register 3 + 0x03C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR3 + Capture/compare 3 value + + 0 + 32 + read-write + + + + + TIM2_CCR4 + TIM2_CCR4 + TIM2 capture/compare register 4 + 0x040 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR4 + Capture/compare 4 value + + 0 + 32 + read-write + + + + + TIM2_ECR + TIM2_ECR + TIM2 timer encoder control register + 0x058 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IE + Index enable + + 0 + 1 + read-write + + + B_0x0 + Index disabled + 0x0 + + + B_0x1 + Index enabled + 0x1 + + + + + IDIR + Index direction + + 1 + 2 + read-write + + + B_0x0 + Index resets the counter whatever the direction + 0x0 + + + B_0x1 + Index resets the counter when up-counting only + 0x1 + + + B_0x2 + Index resets the counter when down-counting only + 0x2 + + + + + IBLK + Index blanking + + 3 + 2 + read-write + + + B_0x0 + Index always active + 0x0 + + + B_0x1 + Index disabled hen tim_ti3 input is active, as per CC3P bitfield + 0x1 + + + B_0x2 + Index disabled when tim_ti4 input is active, as per CC4P bitfield + 0x2 + + + + + FIDX + First index + + 5 + 1 + read-write + + + B_0x0 + Index is always active + 0x0 + + + B_0x1 + the first Index only resets the counter + 0x1 + + + + + IPOS + Index positioning + + 6 + 2 + read-write + + + B_0x0 + Index resets the counter when AB = 00 + 0x0 + + + B_0x1 + Index resets the counter when AB = 01 + 0x1 + + + B_0x2 + Index resets the counter when AB = 10 + 0x2 + + + B_0x3 + Index resets the counter when AB = 11 + 0x3 + + + + + PW + Pulse width + + 16 + 8 + read-write + + + PWPRSC + Pulse width prescaler + + 24 + 3 + read-write + + + + + TIM2_TISEL + TIM2_TISEL + TIM2 timer input selection register + 0x05C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + Selects tim_ti1[15:0] input + + 0 + 4 + read-write + + + B_0x0 + tim_ti1_in0: TIMx_CH1 + 0x0 + + + B_0x1 + tim_ti1_in1 + 0x1 + + + B_0xF + tim_ti1_in15 + 0xF + + + + + TI2SEL + Selects tim_ti2[15:0] input + + 8 + 4 + read-write + + + B_0x0 + tim_ti2_in0: TIMx_CH2 + 0x0 + + + B_0x1 + tim_ti2_in1 + 0x1 + + + B_0xF + tim_ti2_in15 + 0xF + + + + + TI3SEL + Selects tim_ti3[15:0] input + + 16 + 4 + read-write + + + B_0x0 + tim_ti3_in0: TIMx_CH3 + 0x0 + + + B_0x1 + tim_ti3_in1 + 0x1 + + + B_0xF + tim_ti3_in15 + 0xF + + + + + TI4SEL + Selects tim_ti4[15:0] input + + 24 + 4 + read-write + + + B_0x0 + tim_ti4_in0: TIMx_CH4 + 0x0 + + + B_0x1 + tim_ti4_in1 + 0x1 + + + B_0xF + tim_ti4_in15 + 0xF + + + + + + + TIM2_AF1 + TIM2_AF1 + TIM2 alternate function register 1 + 0x060 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ETRSEL + etr_in source selection + + 14 + 4 + read-write + + + B_0x0 + tim_etr0: TIMx_ETR input + 0x0 + + + B_0x1 + tim_etr1 + 0x1 + + + B_0xF + tim_etr15 + 0xF + + + + + + + TIM2_AF2 + TIM2_AF2 + TIM2 alternate function register 2 + 0x064 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OCRSEL + ocref_clr source selection + + 16 + 3 + read-write + + + B_0x0 + tim_ocref_clr0 + 0x0 + + + B_0x1 + tim_ocref_clr1 + 0x1 + + + B_0x7 + tim_ocref_clr7 + 0x7 + + + + + + + TIM2_DCR + TIM2_DCR + TIM2 DMA control register + 0x3DC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DBA + DMA base address + + 0 + 5 + read-write + + + B_0x0 + TIMx_CR1, + 0x0 + + + B_0x1 + TIMx_CR2, + 0x1 + + + B_0x2 + TIMx_SMCR, + 0x2 + + + + + DBL + DMA burst length + + 8 + 5 + read-write + + + B_0x0 + 1 transfer + 0x0 + + + B_0x1 + 2 transfers + 0x1 + + + B_0x2 + 3 transfers + 0x2 + + + B_0x1A + 26 transfers + 0x1A + + + + + DBSS + DMA burst source selection + + 16 + 4 + read-write + + + B_0x1 + Update + 0x1 + + + B_0x2 + CC1 + 0x2 + + + B_0x3 + CC2 + 0x3 + + + B_0x4 + CC3 + 0x4 + + + B_0x5 + CC4 + 0x5 + + + B_0x6 + COM + 0x6 + + + B_0x7 + Trigger + 0x7 + + + + + + + TIM2_DMAR + TIM2_DMAR + TIM2 DMA address for full transfer + 0x3E0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DMAB + DMA register for burst accesses + + 0 + 32 + read-write + + + + + + + TIM2_S + 0X50000000 + + + TIM3 + TIM3 address block description + TIM3 + 0x40000400 + + 0x0 + 0x3E4 + registers + + + TIM3 + TIM3 global interrupt + 46 + + + + TIM3_CR1 + TIM3_CR1 + TIM3 control register 1 + 0x000 + 16 + read-write + 0x0000 + 0xFFFF + + + CEN + Counter enable + + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable + + 1 + 1 + read-write + + + B_0x0 + UEV enabled. + 0x0 + + + B_0x1 + UEV disabled. + 0x1 + + + + + URS + Update request source + + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt or DMA request if enabled. + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + DIR + Direction + + 4 + 1 + read-write + + + B_0x0 + Counter used as upcounter + 0x0 + + + B_0x1 + Counter used as downcounter + 0x1 + + + + + CMS + Center-aligned mode selection + + 5 + 2 + read-write + + + B_0x0 + Edge-aligned mode. + 0x0 + + + B_0x1 + Center-aligned mode 1. + 0x1 + + + B_0x2 + Center-aligned mode 2. + 0x2 + + + B_0x3 + Center-aligned mode 3. + 0x3 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division + + 8 + 2 + read-write + + + B_0x0 + tless thansub>DTSless than/sub> = tless thansub>tim_ker_ckless than/sub> + 0x0 + + + B_0x1 + tless thansub>DTSless than/sub> = 2 tless thansub>tim_ker_ckless than/sub> + 0x1 + + + B_0x2 + tless thansub>DTSless than/sub> = 4 tless thansub>tim_ker_ckless than/sub> + 0x2 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. + 0x0 + + + B_0x1 + Remapping enabled. + 0x1 + + + + + DITHEN + Dithering Enable + + 12 + 1 + read-write + + + B_0x0 + Dithering disabled + 0x0 + + + B_0x1 + Dithering enabled + 0x1 + + + + + + + TIM3_CR2 + TIM3_CR2 + TIM3 control register 2 + 0x004 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCDS + Capture/compare DMA selection + 3 + 1 + read-write + + + B_0x0 + CCx DMA request sent when CCx event occurs + 0x0 + + + B_0x1 + CCx DMA requests sent when update event occurs + 0x1 + + + + + MMS + MMS[2:0]: Master mode selection + + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo). + 0x0 + + + B_0x1 + Enable - the Counter enable signal, CNT_EN, is used as trigger output (tim_trgo). + 0x1 + + + B_0x2 + Update - The update event is selected as trigger output (tim_trgo). + 0x2 + + + B_0x3 + Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred (tim_trgo). + 0x3 + + + B_0x4 + Compare - tim_oc1refc signal is used as trigger output (tim_trgo) + 0x4 + + + B_0x5 + Compare - tim_oc2refc signal is used as trigger output (tim_trgo) + 0x5 + + + B_0x6 + Compare - tim_oc3refc signal is used as trigger output (tim_trgo) + 0x6 + + + B_0x7 + Compare - tim_oc4refc signal is used as trigger output (tim_trgo) + 0x7 + + + + + TI1S + tim_ti1 selection + 7 + 1 + read-write + + + B_0x0 + The tim_ti1_in[15:0] multiplexer output is to tim_ti1 input + 0x0 + + + B_0x1 + The tim_ti1_in[15:0], tim_ti2_in[15:0] and tim_ti3_in[15:0] multiplexers outputs are XORed and connected to the tim_ti1 input. + 0x1 + + + + + MMS_1 + MMS[3] + 25 + 1 + read-write + + + + + TIM3_SMCR + TIM3_SMCR + TIM3 slave mode control register + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SMS + SMS[2:0]: Slave mode selection + + 0 + 3 + read-write + + + B_0x0 + Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level. + 0x1 + + + B_0x2 + Encoder mode 2 - Counter counts up/down on tim_ti2fp2 edge depending on tim_ti1fp1 level. + 0x2 + + + B_0x3 + Encoder mode 3 - Counter counts up/down on both tim_ti1fp1 and tim_ti2fp2 edges depending on the level of the other input. + 0x3 + + + B_0x4 + Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers. + 0x4 + + + B_0x5 + Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high. + 0x5 + + + B_0x6 + Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). + 0x6 + + + B_0x7 + External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter. + 0x7 + + + + + OCCS + OCREF clear selection + + 3 + 1 + read-write + + + B_0x0 + tim_ocref_clr_int is connected to the tim_ocref_clr input + 0x0 + + + B_0x1 + tim_ocref_clr_int is connected to tim_etrf + 0x1 + + + + + TS + TS[2:0]: Trigger selection + + 4 + 3 + read-write + + + B_0x0 + Internal trigger 0 (tim_itr0) + 0x0 + + + B_0x1 + Internal trigger 1 (tim_itr1) + 0x1 + + + B_0x2 + Internal trigger 2 (tim_itr2) + 0x2 + + + B_0x3 + Internal trigger 3 (tim_itr3) + 0x3 + + + B_0x4 + tim_ti1 edge detector (tim_ti1f_ed) + 0x4 + + + B_0x5 + Filtered timer input 1 (tim_ti1fp1) + 0x5 + + + B_0x6 + Filtered timer input 2 (tim_ti2fp2) + 0x6 + + + B_0x7 + External trigger input (tim_etrf) + 0x7 + + + + + MSM + Master/Slave mode + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). + 0x1 + + + + + ETF + External trigger filter + + 8 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + ETPS + External trigger prescaler + + 12 + 2 + read-write + + + B_0x0 + Prescaler OFF + 0x0 + + + B_0x1 + tim_etrp frequency divided by 2 + 0x1 + + + B_0x2 + tim_etrp frequency divided by 4 + 0x2 + + + B_0x3 + tim_etrp frequency divided by 8 + 0x3 + + + + + ECE + External clock enable + + 14 + 1 + read-write + + + B_0x0 + External clock mode 2 disabled + 0x0 + + + B_0x1 + External clock mode 2 enabled. + 0x1 + + + + + ETP + External trigger polarity + + 15 + 1 + read-write + + + B_0x0 + tim_etr_in is non-inverted, active at high level or rising edge + 0x0 + + + B_0x1 + tim_etr_in is inverted, active at low level or falling edge + 0x1 + + + + + SMS_1 + Slave mode selection +When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (see Input Control register and Control Register description. +Note: The gated mode must not be used if tim_ti1f_ed is selected as the trigger input (TS=00100). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on tim_ti1f, whereas the gated mode checks the level of the trigger signal. +Note: The clock of the slave peripherals (timer, ADC, ...) receiving the tim_trgo signal must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. + 16 + 1 + read-write + + + B_0x0 + Slave mode disabled - if CEN = '1 then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level. + 0x1 + + + + + TS_1 + Trigger selection +This bit-field selects the trigger input to be used to synchronize the counter. +Others: Reserved +See for product specific implementation details. +Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. + 20 + 2 + read-write + + + B_0x0 + Internal trigger 0 (tim_itr0) + 0x0 + + + B_0x1 + Internal trigger 1 (tim_itr1) + 0x1 + + + B_0x2 + Internal trigger 2 (tim_itr2) + 0x2 + + + B_0x3 + Internal trigger 3 (tim_itr3) + 0x3 + + + + + SMSPE + SMS preload enable + + 24 + 1 + read-write + + + B_0x0 + SMS[3:0] bitfield is not preloaded + 0x0 + + + B_0x1 + SMS[3:0] preload is enabled + 0x1 + + + + + SMSPS + SMS preload source + + 25 + 1 + read-write + + + B_0x0 + The transfer is triggered by the Timer's Update event + 0x0 + + + B_0x1 + The transfer is triggered by the Index event + 0x1 + + + + + + + TIM3_DIER + TIM3_DIER + TIM3 DMA/Interrupt enable register + 0x00C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled. + 0x0 + + + B_0x1 + Update interrupt enabled. + 0x1 + + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled. + 0x0 + + + B_0x1 + CC1 interrupt enabled. + 0x1 + + + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + read-write + + + B_0x0 + CC2 interrupt disabled. + 0x0 + + + B_0x1 + CC2 interrupt enabled. + 0x1 + + + + + CC3IE + Capture/Compare 3 interrupt enable + 3 + 1 + read-write + + + B_0x0 + CC3 interrupt disabled. + 0x0 + + + B_0x1 + CC3 interrupt enabled. + 0x1 + + + + + CC4IE + Capture/Compare 4 interrupt enable + 4 + 1 + read-write + + + B_0x0 + CC4 interrupt disabled. + 0x0 + + + B_0x1 + CC4 interrupt enabled. + 0x1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + read-write + + + B_0x0 + Trigger interrupt disabled. + 0x0 + + + B_0x1 + Trigger interrupt enabled. + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled. + 0x0 + + + B_0x1 + Update DMA request enabled. + 0x1 + + + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled. + 0x0 + + + B_0x1 + CC1 DMA request enabled. + 0x1 + + + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled. + 0x0 + + + B_0x1 + CC2 DMA request enabled. + 0x1 + + + + + CC3DE + Capture/Compare 3 DMA request enable + 11 + 1 + read-write + + + B_0x0 + CC3 DMA request disabled. + 0x0 + + + B_0x1 + CC3 DMA request enabled. + 0x1 + + + + + CC4DE + Capture/Compare 4 DMA request enable + 12 + 1 + read-write + + + B_0x0 + CC4 DMA request disabled. + 0x0 + + + B_0x1 + CC4 DMA request enabled. + 0x1 + + + + + TDE + Trigger DMA request enable + 14 + 1 + read-write + + + B_0x0 + Trigger DMA request disabled. + 0x0 + + + B_0x1 + Trigger DMA request enabled. + 0x1 + + + + + IDXIE + Index interrupt enable + 20 + 1 + read-write + + + B_0x0 + Index interrupt disabled + 0x0 + + + B_0x1 + Index interrupt enabled + 0x1 + + + + + DIRIE + Direction change interrupt enable + 21 + 1 + read-write + + + B_0x0 + Direction change interrupt disabled + 0x0 + + + B_0x1 + Direction change interrupt enabled + 0x1 + + + + + IERRIE + Index error interrupt enable + 22 + 1 + read-write + + + B_0x0 + Index error interrupt disabled + 0x0 + + + B_0x1 + Index error interrupt enabled + 0x1 + + + + + TERRIE + Transition error interrupt enable + 23 + 1 + read-write + + + B_0x0 + Transition error interrupt disabled + 0x0 + + + B_0x1 + Transition error interrupt enabled + 0x1 + + + + + + + TIM3_SR + TIM3_SR + TIM3 status register + 0x010 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UIF + Update interrupt flag + + 0 + 1 + read-write + + + B_0x0 + No update occurred + 0x0 + + + B_0x1 + Update interrupt pending. + 0x1 + + + + + CC1IF + Capture/compare 1 interrupt flag + + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred + 0x1 + + + + + CC2IF + Capture/Compare 2 interrupt flag + + 2 + 1 + read-write + + + CC3IF + Capture/Compare 3 interrupt flag + + 3 + 1 + read-write + + + CC4IF + Capture/Compare 4 interrupt flag + + 4 + 1 + read-write + + + TIF + Trigger interrupt flag + + 6 + 1 + read-write + + + B_0x0 + No trigger event occurred. + 0x0 + + + B_0x1 + Trigger interrupt pending. + 0x1 + + + + + CC1OF + Capture/Compare 1 overcapture flag + + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + CC2OF + Capture/compare 2 overcapture flag + + 10 + 1 + read-write + + + CC3OF + Capture/Compare 3 overcapture flag + + 11 + 1 + read-write + + + CC4OF + Capture/Compare 4 overcapture flag + + 12 + 1 + read-write + + + IDXF + Index interrupt flag + + 20 + 1 + read-write + + + B_0x0 + No index event occurred. + 0x0 + + + B_0x1 + An index event has occurred + 0x1 + + + + + DIRF + Direction change interrupt flag + + 21 + 1 + read-write + + + B_0x0 + No direction change + 0x0 + + + B_0x1 + Direction change + 0x1 + + + + + IERRF + Index error interrupt flag + + 22 + 1 + read-write + + + B_0x0 + No index error has been detected. + 0x0 + + + B_0x1 + An index error has been detected + 0x1 + + + + + TERRF + Transition error interrupt flag + + 23 + 1 + read-write + + + B_0x0 + No encoder transition error has been detected. + 0x0 + + + B_0x1 + An encoder transition error has been detected + 0x1 + + + + + + + TIM3_EGR + TIM3_EGR + TIM3 event generation register + 0x014 + 16 + write-only + 0x0000 + 0xFFFF + + + UG + Update generation + + 0 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Re-initialize the counter and generates an update of the registers. + 0x1 + + + + + CC1G + Capture/compare 1 generation + + 1 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + CC2G + Capture/compare 2 generation + + 2 + 1 + write-only + + + CC3G + Capture/compare 3 generation + + 3 + 1 + write-only + + + CC4G + Capture/compare 4 generation + + 4 + 1 + write-only + + + TG + Trigger generation + + 6 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + The TIF flag is set in TIMx_SR register. + 0x1 + + + + + + + TIM3_CCMR1 + TIM3_CCMR1 + TIM3 capture/compare mode register 1 + 0x018 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. + 0x3 + + + + + IC1PSC + Input capture 1 prescaler + + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter + + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + CC2S + Capture/compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output. + 0x0 + + + B_0x1 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2. + 0x1 + + + B_0x2 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1. + 0x2 + + + B_0x3 + CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. + 0x3 + + + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + read-write + + + IC2F + Input capture 2 filter + 12 + 4 + read-write + + + + + TIM3_CCMR1_ALTERNATE1 + TIM3_CCMR1_ALTERNATE1 + TIM3 capture/compare mode register 1 + TIM3_CCMR1 + 0x018 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output. + 0x0 + + + B_0x1 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1. + 0x1 + + + B_0x2 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2. + 0x2 + + + B_0x3 + CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. + 0x3 + + + + + OC1FE + Output compare 1 fast enable + + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. + 0x1 + + + + + OC1PE + Output compare 1 preload enable + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. + 0x1 + + + + + OC1M + OC1M[2:0]: Output compare 1 mode + + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. + 0x2 + + + B_0x3 + Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - tim_oc1ref is forced low. + 0x4 + + + B_0x5 + Force active level - tim_oc1ref is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. + 0x6 + + + B_0x7 + PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. + 0x7 + + + + + OC1CE + Output compare 1 clear enable + 7 + 1 + read-write + + + B_0x0 + tim_oc1ref is not affected by the tim_ocref_clr_int input + 0x0 + + + B_0x1 + tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr_int input + 0x1 + + + + + CC2S + Capture/Compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. + 0x3 + + + + + OC2FE + Output compare 2 fast enable + 10 + 1 + read-write + + + OC2PE + Output compare 2 preload enable + 11 + 1 + read-write + + + OC2M + OC2M[2:0]: Output compare 2 mode + + 12 + 3 + read-write + + + OC2CE + Output compare 2 clear enable + 15 + 1 + read-write + + + OC1M_1 + OC1M[3] + 16 + 1 + read-write + + + OC2M_1 + OC2M[3] + 24 + 1 + read-write + + + + + TIM3_CCMR2 + TIM3_CCMR2 + TIM3 capture/compare mode register 2 + 0x01C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. + 0x3 + + + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + read-write + + + IC3F + Input capture 3 filter + 4 + 4 + read-write + + + CC4S + Capture/Compare 4 selection + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. + 0x3 + + + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + read-write + + + IC4F + Input capture 4 filter + 12 + 4 + read-write + + + + + TIM3_CCMR2_ALTERNATE1 + TIM3_CCMR2_ALTERNATE1 + TIM3 capture/compare mode register 2 + TIM3_CCMR2 + 0x01C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. + 0x3 + + + + + OC3FE + Output compare 3 fast enable + 2 + 1 + read-write + + + OC3PE + Output compare 3 preload enable + 3 + 1 + read-write + + + OC3M + OC3M[2:0]: Output compare 3 mode + + 4 + 3 + read-write + + + OC3CE + Output compare 3 clear enable + 7 + 1 + read-write + + + CC4S + Capture/Compare 4 selection + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. + 0x3 + + + + + OC4FE + Output compare 4 fast enable + 10 + 1 + read-write + + + OC4PE + Output compare 4 preload enable + 11 + 1 + read-write + + + OC4M + OC4M[2:0]: Output compare 4 mode + + 12 + 3 + read-write + + + OC4CE + Output compare 4 clear enable + 15 + 1 + read-write + + + OC3M_1 + OC3M[3] + 16 + 1 + read-write + + + OC4M_1 + OC4M[3] + 24 + 1 + read-write + + + + + TIM3_CCER + TIM3_CCER + TIM3 capture/compare enable register + 0x020 + 16 + read-write + 0x0000 + 0xFFFF + + + CC1E + Capture/Compare 1 output enable. + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/Compare 1 output Polarity. + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NP + Capture/Compare 1 output Polarity. + 3 + 1 + read-write + + + CC2E + Capture/Compare 2 output enable. + 4 + 1 + read-write + + + CC2P + Capture/Compare 2 output Polarity. + 5 + 1 + read-write + + + CC2NP + Capture/Compare 2 output Polarity. + 7 + 1 + read-write + + + CC3E + Capture/Compare 3 output enable. + 8 + 1 + read-write + + + CC3P + Capture/Compare 3 output Polarity. + 9 + 1 + read-write + + + CC3NP + Capture/Compare 3 output Polarity. + 11 + 1 + read-write + + + CC4E + Capture/Compare 4 output enable. + 12 + 1 + read-write + + + CC4P + Capture/Compare 4 output Polarity. + 13 + 1 + read-write + + + CC4NP + Capture/Compare 4 output Polarity. + 15 + 1 + read-write + + + + + TIM3_CNT + TIM3_CNT + TIM3 counter + 0x024 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + + 0 + 16 + read-write + + + UIFCPY + Value depends on IUFREMAP in TIMx_CR1. + 31 + 1 + read-write + + + + + TIM3_PSC + TIM3_PSC + TIM3 prescaler + 0x028 + 16 + read-write + 0x0000 + 0xFFFF + + + PSC + Prescaler value + + 0 + 16 + read-write + + + + + TIM3_ARR + TIM3_ARR + TIM3 auto-reload register + 0x02C + 0x20 + read-write + 0x0000FFFF + 0xFFFFFFFF + + + ARR + Low Auto-reload value + + 0 + 20 + read-write + + + + + TIM3_CCR1 + TIM3_CCR1 + TIM3 capture/compare register 1 + 0x034 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR1 + Capture/compare 1 value + + 0 + 20 + read-write + + + + + TIM3_CCR2 + TIM3_CCR2 + TIM3 capture/compare register 2 + 0x038 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR2 + Capture/compare 1 value + + 0 + 20 + read-write + + + + + TIM3_CCR3 + TIM3_CCR3 + TIM3 capture/compare register 3 + 0x03C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR3 + Capture/compare 3 value + + 0 + 20 + read-write + + + + + TIM3_CCR4 + TIM3_CCR4 + TIM3 capture/compare register 4 + 0x040 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR4 + Capture/compare 4 value + + 0 + 20 + read-write + + + + + TIM3_ECR + TIM3_ECR + TIM3 timer encoder control register + 0x058 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IE + Index enable + + 0 + 1 + read-write + + + B_0x0 + Index disabled + 0x0 + + + B_0x1 + Index enabled + 0x1 + + + + + IDIR + Index direction + + 1 + 2 + read-write + + + B_0x0 + Index resets the counter whatever the direction + 0x0 + + + B_0x1 + Index resets the counter when up-counting only + 0x1 + + + B_0x2 + Index resets the counter when down-counting only + 0x2 + + + + + IBLK + Index blanking + + 3 + 2 + read-write + + + B_0x0 + Index always active + 0x0 + + + B_0x1 + Index disabled hen tim_ti3 input is active, as per CC3P bitfield + 0x1 + + + B_0x2 + Index disabled when tim_ti4 input is active, as per CC4P bitfield + 0x2 + + + + + FIDX + First index + + 5 + 1 + read-write + + + B_0x0 + Index is always active + 0x0 + + + B_0x1 + the first Index only resets the counter + 0x1 + + + + + IPOS + Index positioning + + 6 + 2 + read-write + + + B_0x0 + Index resets the counter when AB = 00 + 0x0 + + + B_0x1 + Index resets the counter when AB = 01 + 0x1 + + + B_0x2 + Index resets the counter when AB = 10 + 0x2 + + + B_0x3 + Index resets the counter when AB = 11 + 0x3 + + + + + PW + Pulse width + + 16 + 8 + read-write + + + PWPRSC + Pulse width prescaler + + 24 + 3 + read-write + + + + + TIM3_TISEL + TIM3_TISEL + TIM3 timer input selection register + 0x05C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + Selects tim_ti1[15:0] input + + 0 + 4 + read-write + + + B_0x0 + tim_ti1_in0: TIMx_CH1 + 0x0 + + + B_0x1 + tim_ti1_in1 + 0x1 + + + B_0xF + tim_ti1_in15 + 0xF + + + + + TI2SEL + Selects tim_ti2[15:0] input + + 8 + 4 + read-write + + + B_0x0 + tim_ti2_in0: TIMx_CH2 + 0x0 + + + B_0x1 + tim_ti2_in1 + 0x1 + + + B_0xF + tim_ti2_in15 + 0xF + + + + + TI3SEL + Selects tim_ti3[15:0] input + + 16 + 4 + read-write + + + B_0x0 + tim_ti3_in0: TIMx_CH3 + 0x0 + + + B_0x1 + tim_ti3_in1 + 0x1 + + + B_0xF + tim_ti3_in15 + 0xF + + + + + TI4SEL + Selects tim_ti4[15:0] input + + 24 + 4 + read-write + + + B_0x0 + tim_ti4_in0: TIMx_CH4 + 0x0 + + + B_0x1 + tim_ti4_in1 + 0x1 + + + B_0xF + tim_ti4_in15 + 0xF + + + + + + + TIM3_AF1 + TIM3_AF1 + TIM3 alternate function register 1 + 0x060 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ETRSEL + etr_in source selection + + 14 + 4 + read-write + + + B_0x0 + tim_etr0: TIMx_ETR input + 0x0 + + + B_0x1 + tim_etr1 + 0x1 + + + B_0xF + tim_etr15 + 0xF + + + + + + + TIM3_AF2 + TIM3_AF2 + TIM3 alternate function register 2 + 0x064 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OCRSEL + ocref_clr source selection + + 16 + 3 + read-write + + + B_0x0 + tim_ocref_clr0 + 0x0 + + + B_0x1 + tim_ocref_clr1 + 0x1 + + + B_0x7 + tim_ocref_clr7 + 0x7 + + + + + + + TIM3_DCR + TIM3_DCR + TIM3 DMA control register + 0x3DC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DBA + DMA base address + + 0 + 5 + read-write + + + B_0x0 + TIMx_CR1, + 0x0 + + + B_0x1 + TIMx_CR2, + 0x1 + + + B_0x2 + TIMx_SMCR, + 0x2 + + + + + DBL + DMA burst length + + 8 + 5 + read-write + + + B_0x0 + 1 transfer + 0x0 + + + B_0x1 + 2 transfers + 0x1 + + + B_0x2 + 3 transfers + 0x2 + + + B_0x1A + 26 transfers + 0x1A + + + + + DBSS + DMA burst source selection + + 16 + 4 + read-write + + + B_0x1 + Update + 0x1 + + + B_0x2 + CC1 + 0x2 + + + B_0x3 + CC2 + 0x3 + + + B_0x4 + CC3 + 0x4 + + + B_0x5 + CC4 + 0x5 + + + B_0x6 + COM + 0x6 + + + B_0x7 + Trigger + 0x7 + + + + + + + TIM3_DMAR + TIM3_DMAR + TIM3 DMA address for full transfer + 0x3E0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DMAB + DMA register for burst accesses + + 0 + 32 + read-write + + + + + + + TIM3_S + 0X50000400 + + + TIM4 + TIM4 address block description + TIM4 + 0x40000800 + + 0x0 + 0x3E4 + registers + + + TIM4 + TIM4 global interrupt + 47 + + + + TIM4_CR1 + TIM4_CR1 + TIM4 control register 1 + 0x000 + 16 + read-write + 0x0000 + 0xFFFF + + + CEN + Counter enable + + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable + + 1 + 1 + read-write + + + B_0x0 + UEV enabled. + 0x0 + + + B_0x1 + UEV disabled. + 0x1 + + + + + URS + Update request source + + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt or DMA request if enabled. + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + DIR + Direction + + 4 + 1 + read-write + + + B_0x0 + Counter used as upcounter + 0x0 + + + B_0x1 + Counter used as downcounter + 0x1 + + + + + CMS + Center-aligned mode selection + + 5 + 2 + read-write + + + B_0x0 + Edge-aligned mode. + 0x0 + + + B_0x1 + Center-aligned mode 1. + 0x1 + + + B_0x2 + Center-aligned mode 2. + 0x2 + + + B_0x3 + Center-aligned mode 3. + 0x3 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division + + 8 + 2 + read-write + + + B_0x0 + tless thansub>DTSless than/sub> = tless thansub>tim_ker_ckless than/sub> + 0x0 + + + B_0x1 + tless thansub>DTSless than/sub> = 2 tless thansub>tim_ker_ckless than/sub> + 0x1 + + + B_0x2 + tless thansub>DTSless than/sub> = 4 tless thansub>tim_ker_ckless than/sub> + 0x2 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. + 0x0 + + + B_0x1 + Remapping enabled. + 0x1 + + + + + DITHEN + Dithering Enable + + 12 + 1 + read-write + + + B_0x0 + Dithering disabled + 0x0 + + + B_0x1 + Dithering enabled + 0x1 + + + + + + + TIM4_CR2 + TIM4_CR2 + TIM4 control register 2 + 0x004 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCDS + Capture/compare DMA selection + 3 + 1 + read-write + + + B_0x0 + CCx DMA request sent when CCx event occurs + 0x0 + + + B_0x1 + CCx DMA requests sent when update event occurs + 0x1 + + + + + MMS + MMS[2:0]: Master mode selection + + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo). + 0x0 + + + B_0x1 + Enable - the Counter enable signal, CNT_EN, is used as trigger output (tim_trgo). + 0x1 + + + B_0x2 + Update - The update event is selected as trigger output (tim_trgo). + 0x2 + + + B_0x3 + Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred (tim_trgo). + 0x3 + + + B_0x4 + Compare - tim_oc1refc signal is used as trigger output (tim_trgo) + 0x4 + + + B_0x5 + Compare - tim_oc2refc signal is used as trigger output (tim_trgo) + 0x5 + + + B_0x6 + Compare - tim_oc3refc signal is used as trigger output (tim_trgo) + 0x6 + + + B_0x7 + Compare - tim_oc4refc signal is used as trigger output (tim_trgo) + 0x7 + + + + + TI1S + tim_ti1 selection + 7 + 1 + read-write + + + B_0x0 + The tim_ti1_in[15:0] multiplexer output is to tim_ti1 input + 0x0 + + + B_0x1 + The tim_ti1_in[15:0], tim_ti2_in[15:0] and tim_ti3_in[15:0] multiplexers outputs are XORed and connected to the tim_ti1 input. + 0x1 + + + + + MMS_1 + MMS[3] + 25 + 1 + read-write + + + + + TIM4_SMCR + TIM4_SMCR + TIM4 slave mode control register + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SMS + SMS[2:0]: Slave mode selection + + 0 + 3 + read-write + + + B_0x0 + Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level. + 0x1 + + + B_0x2 + Encoder mode 2 - Counter counts up/down on tim_ti2fp2 edge depending on tim_ti1fp1 level. + 0x2 + + + B_0x3 + Encoder mode 3 - Counter counts up/down on both tim_ti1fp1 and tim_ti2fp2 edges depending on the level of the other input. + 0x3 + + + B_0x4 + Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers. + 0x4 + + + B_0x5 + Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high. + 0x5 + + + B_0x6 + Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). + 0x6 + + + B_0x7 + External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter. + 0x7 + + + + + OCCS + OCREF clear selection + + 3 + 1 + read-write + + + B_0x0 + tim_ocref_clr_int is connected to the tim_ocref_clr input + 0x0 + + + B_0x1 + tim_ocref_clr_int is connected to tim_etrf + 0x1 + + + + + TS + TS[2:0]: Trigger selection + + 4 + 3 + read-write + + + B_0x0 + Internal trigger 0 (tim_itr0) + 0x0 + + + B_0x1 + Internal trigger 1 (tim_itr1) + 0x1 + + + B_0x2 + Internal trigger 2 (tim_itr2) + 0x2 + + + B_0x3 + Internal trigger 3 (tim_itr3) + 0x3 + + + B_0x4 + tim_ti1 edge detector (tim_ti1f_ed) + 0x4 + + + B_0x5 + Filtered timer input 1 (tim_ti1fp1) + 0x5 + + + B_0x6 + Filtered timer input 2 (tim_ti2fp2) + 0x6 + + + B_0x7 + External trigger input (tim_etrf) + 0x7 + + + + + MSM + Master/Slave mode + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). + 0x1 + + + + + ETF + External trigger filter + + 8 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + ETPS + External trigger prescaler + + 12 + 2 + read-write + + + B_0x0 + Prescaler OFF + 0x0 + + + B_0x1 + tim_etrp frequency divided by 2 + 0x1 + + + B_0x2 + tim_etrp frequency divided by 4 + 0x2 + + + B_0x3 + tim_etrp frequency divided by 8 + 0x3 + + + + + ECE + External clock enable + + 14 + 1 + read-write + + + B_0x0 + External clock mode 2 disabled + 0x0 + + + B_0x1 + External clock mode 2 enabled. + 0x1 + + + + + ETP + External trigger polarity + + 15 + 1 + read-write + + + B_0x0 + tim_etr_in is non-inverted, active at high level or rising edge + 0x0 + + + B_0x1 + tim_etr_in is inverted, active at low level or falling edge + 0x1 + + + + + SMS_1 + Slave mode selection +When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (see Input Control register and Control Register description. +Note: The gated mode must not be used if tim_ti1f_ed is selected as the trigger input (TS=00100). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on tim_ti1f, whereas the gated mode checks the level of the trigger signal. +Note: The clock of the slave peripherals (timer, ADC, ...) receiving the tim_trgo signal must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. + 16 + 1 + read-write + + + B_0x0 + Slave mode disabled - if CEN = '1 then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level. + 0x1 + + + + + TS_1 + Trigger selection +This bit-field selects the trigger input to be used to synchronize the counter. +Others: Reserved +See for product specific implementation details. +Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. + 20 + 2 + read-write + + + B_0x0 + Internal trigger 0 (tim_itr0) + 0x0 + + + B_0x1 + Internal trigger 1 (tim_itr1) + 0x1 + + + B_0x2 + Internal trigger 2 (tim_itr2) + 0x2 + + + B_0x3 + Internal trigger 3 (tim_itr3) + 0x3 + + + + + SMSPE + SMS preload enable + + 24 + 1 + read-write + + + B_0x0 + SMS[3:0] bitfield is not preloaded + 0x0 + + + B_0x1 + SMS[3:0] preload is enabled + 0x1 + + + + + SMSPS + SMS preload source + + 25 + 1 + read-write + + + B_0x0 + The transfer is triggered by the Timer's Update event + 0x0 + + + B_0x1 + The transfer is triggered by the Index event + 0x1 + + + + + + + TIM4_DIER + TIM4_DIER + TIM4 DMA/Interrupt enable register + 0x00C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled. + 0x0 + + + B_0x1 + Update interrupt enabled. + 0x1 + + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled. + 0x0 + + + B_0x1 + CC1 interrupt enabled. + 0x1 + + + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + read-write + + + B_0x0 + CC2 interrupt disabled. + 0x0 + + + B_0x1 + CC2 interrupt enabled. + 0x1 + + + + + CC3IE + Capture/Compare 3 interrupt enable + 3 + 1 + read-write + + + B_0x0 + CC3 interrupt disabled. + 0x0 + + + B_0x1 + CC3 interrupt enabled. + 0x1 + + + + + CC4IE + Capture/Compare 4 interrupt enable + 4 + 1 + read-write + + + B_0x0 + CC4 interrupt disabled. + 0x0 + + + B_0x1 + CC4 interrupt enabled. + 0x1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + read-write + + + B_0x0 + Trigger interrupt disabled. + 0x0 + + + B_0x1 + Trigger interrupt enabled. + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled. + 0x0 + + + B_0x1 + Update DMA request enabled. + 0x1 + + + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled. + 0x0 + + + B_0x1 + CC1 DMA request enabled. + 0x1 + + + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled. + 0x0 + + + B_0x1 + CC2 DMA request enabled. + 0x1 + + + + + CC3DE + Capture/Compare 3 DMA request enable + 11 + 1 + read-write + + + B_0x0 + CC3 DMA request disabled. + 0x0 + + + B_0x1 + CC3 DMA request enabled. + 0x1 + + + + + CC4DE + Capture/Compare 4 DMA request enable + 12 + 1 + read-write + + + B_0x0 + CC4 DMA request disabled. + 0x0 + + + B_0x1 + CC4 DMA request enabled. + 0x1 + + + + + TDE + Trigger DMA request enable + 14 + 1 + read-write + + + B_0x0 + Trigger DMA request disabled. + 0x0 + + + B_0x1 + Trigger DMA request enabled. + 0x1 + + + + + IDXIE + Index interrupt enable + 20 + 1 + read-write + + + B_0x0 + Index interrupt disabled + 0x0 + + + B_0x1 + Index interrupt enabled + 0x1 + + + + + DIRIE + Direction change interrupt enable + 21 + 1 + read-write + + + B_0x0 + Direction change interrupt disabled + 0x0 + + + B_0x1 + Direction change interrupt enabled + 0x1 + + + + + IERRIE + Index error interrupt enable + 22 + 1 + read-write + + + B_0x0 + Index error interrupt disabled + 0x0 + + + B_0x1 + Index error interrupt enabled + 0x1 + + + + + TERRIE + Transition error interrupt enable + 23 + 1 + read-write + + + B_0x0 + Transition error interrupt disabled + 0x0 + + + B_0x1 + Transition error interrupt enabled + 0x1 + + + + + + + TIM4_SR + TIM4_SR + TIM4 status register + 0x010 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UIF + Update interrupt flag + + 0 + 1 + read-write + + + B_0x0 + No update occurred + 0x0 + + + B_0x1 + Update interrupt pending. + 0x1 + + + + + CC1IF + Capture/compare 1 interrupt flag + + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred + 0x1 + + + + + CC2IF + Capture/Compare 2 interrupt flag + + 2 + 1 + read-write + + + CC3IF + Capture/Compare 3 interrupt flag + + 3 + 1 + read-write + + + CC4IF + Capture/Compare 4 interrupt flag + + 4 + 1 + read-write + + + TIF + Trigger interrupt flag + + 6 + 1 + read-write + + + B_0x0 + No trigger event occurred. + 0x0 + + + B_0x1 + Trigger interrupt pending. + 0x1 + + + + + CC1OF + Capture/Compare 1 overcapture flag + + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + CC2OF + Capture/compare 2 overcapture flag + + 10 + 1 + read-write + + + CC3OF + Capture/Compare 3 overcapture flag + + 11 + 1 + read-write + + + CC4OF + Capture/Compare 4 overcapture flag + + 12 + 1 + read-write + + + IDXF + Index interrupt flag + + 20 + 1 + read-write + + + B_0x0 + No index event occurred. + 0x0 + + + B_0x1 + An index event has occurred + 0x1 + + + + + DIRF + Direction change interrupt flag + + 21 + 1 + read-write + + + B_0x0 + No direction change + 0x0 + + + B_0x1 + Direction change + 0x1 + + + + + IERRF + Index error interrupt flag + + 22 + 1 + read-write + + + B_0x0 + No index error has been detected. + 0x0 + + + B_0x1 + An index error has been detected + 0x1 + + + + + TERRF + Transition error interrupt flag + + 23 + 1 + read-write + + + B_0x0 + No encoder transition error has been detected. + 0x0 + + + B_0x1 + An encoder transition error has been detected + 0x1 + + + + + + + TIM4_EGR + TIM4_EGR + TIM4 event generation register + 0x014 + 16 + write-only + 0x0000 + 0xFFFF + + + UG + Update generation + + 0 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Re-initialize the counter and generates an update of the registers. + 0x1 + + + + + CC1G + Capture/compare 1 generation + + 1 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + CC2G + Capture/compare 2 generation + + 2 + 1 + write-only + + + CC3G + Capture/compare 3 generation + + 3 + 1 + write-only + + + CC4G + Capture/compare 4 generation + + 4 + 1 + write-only + + + TG + Trigger generation + + 6 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + The TIF flag is set in TIMx_SR register. + 0x1 + + + + + + + TIM4_CCMR1 + TIM4_CCMR1 + TIM4 capture/compare mode register 1 + 0x018 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. + 0x3 + + + + + IC1PSC + Input capture 1 prescaler + + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter + + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + CC2S + Capture/compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output. + 0x0 + + + B_0x1 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2. + 0x1 + + + B_0x2 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1. + 0x2 + + + B_0x3 + CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. + 0x3 + + + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + read-write + + + IC2F + Input capture 2 filter + 12 + 4 + read-write + + + + + TIM4_CCMR1_ALTERNATE1 + TIM4_CCMR1_ALTERNATE1 + TIM4 capture/compare mode register 1 + TIM4_CCMR1 + 0x018 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output. + 0x0 + + + B_0x1 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1. + 0x1 + + + B_0x2 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2. + 0x2 + + + B_0x3 + CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. + 0x3 + + + + + OC1FE + Output compare 1 fast enable + + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. + 0x1 + + + + + OC1PE + Output compare 1 preload enable + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. + 0x1 + + + + + OC1M + OC1M[2:0]: Output compare 1 mode + + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. + 0x2 + + + B_0x3 + Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - tim_oc1ref is forced low. + 0x4 + + + B_0x5 + Force active level - tim_oc1ref is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. + 0x6 + + + B_0x7 + PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. + 0x7 + + + + + OC1CE + Output compare 1 clear enable + 7 + 1 + read-write + + + B_0x0 + tim_oc1ref is not affected by the tim_ocref_clr_int input + 0x0 + + + B_0x1 + tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr_int input + 0x1 + + + + + CC2S + Capture/Compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. + 0x3 + + + + + OC2FE + Output compare 2 fast enable + 10 + 1 + read-write + + + OC2PE + Output compare 2 preload enable + 11 + 1 + read-write + + + OC2M + OC2M[2:0]: Output compare 2 mode + + 12 + 3 + read-write + + + OC2CE + Output compare 2 clear enable + 15 + 1 + read-write + + + OC1M_1 + OC1M[3] + 16 + 1 + read-write + + + OC2M_1 + OC2M[3] + 24 + 1 + read-write + + + + + TIM4_CCMR2 + TIM4_CCMR2 + TIM4 capture/compare mode register 2 + 0x01C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. + 0x3 + + + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + read-write + + + IC3F + Input capture 3 filter + 4 + 4 + read-write + + + CC4S + Capture/Compare 4 selection + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. + 0x3 + + + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + read-write + + + IC4F + Input capture 4 filter + 12 + 4 + read-write + + + + + TIM4_CCMR2_ALTERNATE1 + TIM4_CCMR2_ALTERNATE1 + TIM4 capture/compare mode register 2 + TIM4_CCMR2 + 0x01C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. + 0x3 + + + + + OC3FE + Output compare 3 fast enable + 2 + 1 + read-write + + + OC3PE + Output compare 3 preload enable + 3 + 1 + read-write + + + OC3M + OC3M[2:0]: Output compare 3 mode + + 4 + 3 + read-write + + + OC3CE + Output compare 3 clear enable + 7 + 1 + read-write + + + CC4S + Capture/Compare 4 selection + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. + 0x3 + + + + + OC4FE + Output compare 4 fast enable + 10 + 1 + read-write + + + OC4PE + Output compare 4 preload enable + 11 + 1 + read-write + + + OC4M + OC4M[2:0]: Output compare 4 mode + + 12 + 3 + read-write + + + OC4CE + Output compare 4 clear enable + 15 + 1 + read-write + + + OC3M_1 + OC3M[3] + 16 + 1 + read-write + + + OC4M_1 + OC4M[3] + 24 + 1 + read-write + + + + + TIM4_CCER + TIM4_CCER + TIM4 capture/compare enable register + 0x020 + 16 + read-write + 0x0000 + 0xFFFF + + + CC1E + Capture/Compare 1 output enable. + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/Compare 1 output Polarity. + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NP + Capture/Compare 1 output Polarity. + 3 + 1 + read-write + + + CC2E + Capture/Compare 2 output enable. + 4 + 1 + read-write + + + CC2P + Capture/Compare 2 output Polarity. + 5 + 1 + read-write + + + CC2NP + Capture/Compare 2 output Polarity. + 7 + 1 + read-write + + + CC3E + Capture/Compare 3 output enable. + 8 + 1 + read-write + + + CC3P + Capture/Compare 3 output Polarity. + 9 + 1 + read-write + + + CC3NP + Capture/Compare 3 output Polarity. + 11 + 1 + read-write + + + CC4E + Capture/Compare 4 output enable. + 12 + 1 + read-write + + + CC4P + Capture/Compare 4 output Polarity. + 13 + 1 + read-write + + + CC4NP + Capture/Compare 4 output Polarity. + 15 + 1 + read-write + + + + + TIM4_CNT + TIM4_CNT + TIM4 counter + 0x024 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + + 0 + 16 + read-write + + + UIFCPY + Value depends on IUFREMAP in TIMx_CR1. + 31 + 1 + read-write + + + + + TIM4_PSC + TIM4_PSC + TIM4 prescaler + 0x028 + 16 + read-write + 0x0000 + 0xFFFF + + + PSC + Prescaler value + + 0 + 16 + read-write + + + + + TIM4_ARR + TIM4_ARR + TIM4 auto-reload register + 0x02C + 0x20 + read-write + 0x0000FFFF + 0xFFFFFFFF + + + ARR + Low Auto-reload value + + 0 + 20 + read-write + + + + + TIM4_CCR1 + TIM4_CCR1 + TIM4 capture/compare register 1 + 0x034 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR1 + Capture/compare 1 value + + 0 + 20 + read-write + + + + + TIM4_CCR2 + TIM4_CCR2 + TIM4 capture/compare register 2 + 0x038 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR2 + Capture/compare 1 value + + 0 + 20 + read-write + + + + + TIM4_CCR3 + TIM4_CCR3 + TIM4 capture/compare register 3 + 0x03C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR3 + Capture/compare 3 value + + 0 + 20 + read-write + + + + + TIM4_CCR4 + TIM4_CCR4 + TIM4 capture/compare register 4 + 0x040 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR4 + Capture/compare 4 value + + 0 + 20 + read-write + + + + + TIM4_ECR + TIM4_ECR + TIM4 timer encoder control register + 0x058 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IE + Index enable + + 0 + 1 + read-write + + + B_0x0 + Index disabled + 0x0 + + + B_0x1 + Index enabled + 0x1 + + + + + IDIR + Index direction + + 1 + 2 + read-write + + + B_0x0 + Index resets the counter whatever the direction + 0x0 + + + B_0x1 + Index resets the counter when up-counting only + 0x1 + + + B_0x2 + Index resets the counter when down-counting only + 0x2 + + + + + IBLK + Index blanking + + 3 + 2 + read-write + + + B_0x0 + Index always active + 0x0 + + + B_0x1 + Index disabled hen tim_ti3 input is active, as per CC3P bitfield + 0x1 + + + B_0x2 + Index disabled when tim_ti4 input is active, as per CC4P bitfield + 0x2 + + + + + FIDX + First index + + 5 + 1 + read-write + + + B_0x0 + Index is always active + 0x0 + + + B_0x1 + the first Index only resets the counter + 0x1 + + + + + IPOS + Index positioning + + 6 + 2 + read-write + + + B_0x0 + Index resets the counter when AB = 00 + 0x0 + + + B_0x1 + Index resets the counter when AB = 01 + 0x1 + + + B_0x2 + Index resets the counter when AB = 10 + 0x2 + + + B_0x3 + Index resets the counter when AB = 11 + 0x3 + + + + + PW + Pulse width + + 16 + 8 + read-write + + + PWPRSC + Pulse width prescaler + + 24 + 3 + read-write + + + + + TIM4_TISEL + TIM4_TISEL + TIM4 timer input selection register + 0x05C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + Selects tim_ti1[15:0] input + + 0 + 4 + read-write + + + B_0x0 + tim_ti1_in0: TIMx_CH1 + 0x0 + + + B_0x1 + tim_ti1_in1 + 0x1 + + + B_0xF + tim_ti1_in15 + 0xF + + + + + TI2SEL + Selects tim_ti2[15:0] input + + 8 + 4 + read-write + + + B_0x0 + tim_ti2_in0: TIMx_CH2 + 0x0 + + + B_0x1 + tim_ti2_in1 + 0x1 + + + B_0xF + tim_ti2_in15 + 0xF + + + + + TI3SEL + Selects tim_ti3[15:0] input + + 16 + 4 + read-write + + + B_0x0 + tim_ti3_in0: TIMx_CH3 + 0x0 + + + B_0x1 + tim_ti3_in1 + 0x1 + + + B_0xF + tim_ti3_in15 + 0xF + + + + + TI4SEL + Selects tim_ti4[15:0] input + + 24 + 4 + read-write + + + B_0x0 + tim_ti4_in0: TIMx_CH4 + 0x0 + + + B_0x1 + tim_ti4_in1 + 0x1 + + + B_0xF + tim_ti4_in15 + 0xF + + + + + + + TIM4_AF1 + TIM4_AF1 + TIM4 alternate function register 1 + 0x060 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ETRSEL + etr_in source selection + + 14 + 4 + read-write + + + B_0x0 + tim_etr0: TIMx_ETR input + 0x0 + + + B_0x1 + tim_etr1 + 0x1 + + + B_0xF + tim_etr15 + 0xF + + + + + + + TIM4_AF2 + TIM4_AF2 + TIM4 alternate function register 2 + 0x064 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OCRSEL + ocref_clr source selection + + 16 + 3 + read-write + + + B_0x0 + tim_ocref_clr0 + 0x0 + + + B_0x1 + tim_ocref_clr1 + 0x1 + + + B_0x7 + tim_ocref_clr7 + 0x7 + + + + + + + TIM4_DCR + TIM4_DCR + TIM4 DMA control register + 0x3DC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DBA + DMA base address + + 0 + 5 + read-write + + + B_0x0 + TIMx_CR1, + 0x0 + + + B_0x1 + TIMx_CR2, + 0x1 + + + B_0x2 + TIMx_SMCR, + 0x2 + + + + + DBL + DMA burst length + + 8 + 5 + read-write + + + B_0x0 + 1 transfer + 0x0 + + + B_0x1 + 2 transfers + 0x1 + + + B_0x2 + 3 transfers + 0x2 + + + B_0x1A + 26 transfers + 0x1A + + + + + DBSS + DMA burst source selection + + 16 + 4 + read-write + + + B_0x1 + Update + 0x1 + + + B_0x2 + CC1 + 0x2 + + + B_0x3 + CC2 + 0x3 + + + B_0x4 + CC3 + 0x4 + + + B_0x5 + CC4 + 0x5 + + + B_0x6 + COM + 0x6 + + + B_0x7 + Trigger + 0x7 + + + + + + + TIM4_DMAR + TIM4_DMAR + TIM4 DMA address for full transfer + 0x3E0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DMAB + DMA register for burst accesses + + 0 + 32 + read-write + + + + + + + TIM4_S + 0X50000800 + + + TIM5 + TIM5 address block description + TIM5 + 0x40000c00 + + 0x0 + 0x3E4 + registers + + + TIM5 + TIM5 global interrupt + 48 + + + + TIM5_CR1 + TIM5_CR1 + TIM5 control register 1 + 0x000 + 16 + read-write + 0x0000 + 0xFFFF + + + CEN + Counter enable + + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable + + 1 + 1 + read-write + + + B_0x0 + UEV enabled. + 0x0 + + + B_0x1 + UEV disabled. + 0x1 + + + + + URS + Update request source + + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt or DMA request if enabled. + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + DIR + Direction + + 4 + 1 + read-write + + + B_0x0 + Counter used as upcounter + 0x0 + + + B_0x1 + Counter used as downcounter + 0x1 + + + + + CMS + Center-aligned mode selection + + 5 + 2 + read-write + + + B_0x0 + Edge-aligned mode. + 0x0 + + + B_0x1 + Center-aligned mode 1. + 0x1 + + + B_0x2 + Center-aligned mode 2. + 0x2 + + + B_0x3 + Center-aligned mode 3. + 0x3 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division + + 8 + 2 + read-write + + + B_0x0 + tless thansub>DTSless than/sub> = tless thansub>tim_ker_ckless than/sub> + 0x0 + + + B_0x1 + tless thansub>DTSless than/sub> = 2 tless thansub>tim_ker_ckless than/sub> + 0x1 + + + B_0x2 + tless thansub>DTSless than/sub> = 4 tless thansub>tim_ker_ckless than/sub> + 0x2 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. + 0x0 + + + B_0x1 + Remapping enabled. + 0x1 + + + + + DITHEN + Dithering Enable + + 12 + 1 + read-write + + + B_0x0 + Dithering disabled + 0x0 + + + B_0x1 + Dithering enabled + 0x1 + + + + + + + TIM5_CR2 + TIM5_CR2 + TIM5 control register 2 + 0x004 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCDS + Capture/compare DMA selection + 3 + 1 + read-write + + + B_0x0 + CCx DMA request sent when CCx event occurs + 0x0 + + + B_0x1 + CCx DMA requests sent when update event occurs + 0x1 + + + + + MMS + MMS[2:0]: Master mode selection + + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo). + 0x0 + + + B_0x1 + Enable - the Counter enable signal, CNT_EN, is used as trigger output (tim_trgo). + 0x1 + + + B_0x2 + Update - The update event is selected as trigger output (tim_trgo). + 0x2 + + + B_0x3 + Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred (tim_trgo). + 0x3 + + + B_0x4 + Compare - tim_oc1refc signal is used as trigger output (tim_trgo) + 0x4 + + + B_0x5 + Compare - tim_oc2refc signal is used as trigger output (tim_trgo) + 0x5 + + + B_0x6 + Compare - tim_oc3refc signal is used as trigger output (tim_trgo) + 0x6 + + + B_0x7 + Compare - tim_oc4refc signal is used as trigger output (tim_trgo) + 0x7 + + + + + TI1S + tim_ti1 selection + 7 + 1 + read-write + + + B_0x0 + The tim_ti1_in[15:0] multiplexer output is to tim_ti1 input + 0x0 + + + B_0x1 + The tim_ti1_in[15:0], tim_ti2_in[15:0] and tim_ti3_in[15:0] multiplexers outputs are XORed and connected to the tim_ti1 input. + 0x1 + + + + + MMS_1 + MMS[3] + 25 + 1 + read-write + + + + + TIM5_SMCR + TIM5_SMCR + TIM5 slave mode control register + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SMS + SMS[2:0]: Slave mode selection + + 0 + 3 + read-write + + + B_0x0 + Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level. + 0x1 + + + B_0x2 + Encoder mode 2 - Counter counts up/down on tim_ti2fp2 edge depending on tim_ti1fp1 level. + 0x2 + + + B_0x3 + Encoder mode 3 - Counter counts up/down on both tim_ti1fp1 and tim_ti2fp2 edges depending on the level of the other input. + 0x3 + + + B_0x4 + Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers. + 0x4 + + + B_0x5 + Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high. + 0x5 + + + B_0x6 + Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). + 0x6 + + + B_0x7 + External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter. + 0x7 + + + + + OCCS + OCREF clear selection + + 3 + 1 + read-write + + + B_0x0 + tim_ocref_clr_int is connected to the tim_ocref_clr input + 0x0 + + + B_0x1 + tim_ocref_clr_int is connected to tim_etrf + 0x1 + + + + + TS + TS[2:0]: Trigger selection + + 4 + 3 + read-write + + + B_0x0 + Internal trigger 0 (tim_itr0) + 0x0 + + + B_0x1 + Internal trigger 1 (tim_itr1) + 0x1 + + + B_0x2 + Internal trigger 2 (tim_itr2) + 0x2 + + + B_0x3 + Internal trigger 3 (tim_itr3) + 0x3 + + + B_0x4 + tim_ti1 edge detector (tim_ti1f_ed) + 0x4 + + + B_0x5 + Filtered timer input 1 (tim_ti1fp1) + 0x5 + + + B_0x6 + Filtered timer input 2 (tim_ti2fp2) + 0x6 + + + B_0x7 + External trigger input (tim_etrf) + 0x7 + + + + + MSM + Master/Slave mode + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). + 0x1 + + + + + ETF + External trigger filter + + 8 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + ETPS + External trigger prescaler + + 12 + 2 + read-write + + + B_0x0 + Prescaler OFF + 0x0 + + + B_0x1 + tim_etrp frequency divided by 2 + 0x1 + + + B_0x2 + tim_etrp frequency divided by 4 + 0x2 + + + B_0x3 + tim_etrp frequency divided by 8 + 0x3 + + + + + ECE + External clock enable + + 14 + 1 + read-write + + + B_0x0 + External clock mode 2 disabled + 0x0 + + + B_0x1 + External clock mode 2 enabled. + 0x1 + + + + + ETP + External trigger polarity + + 15 + 1 + read-write + + + B_0x0 + tim_etr_in is non-inverted, active at high level or rising edge + 0x0 + + + B_0x1 + tim_etr_in is inverted, active at low level or falling edge + 0x1 + + + + + SMS_1 + Slave mode selection +When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (see Input Control register and Control Register description. +Note: The gated mode must not be used if tim_ti1f_ed is selected as the trigger input (TS=00100). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on tim_ti1f, whereas the gated mode checks the level of the trigger signal. +Note: The clock of the slave peripherals (timer, ADC, ...) receiving the tim_trgo signal must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. + 16 + 1 + read-write + + + B_0x0 + Slave mode disabled - if CEN = '1 then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level. + 0x1 + + + + + TS_1 + Trigger selection +This bit-field selects the trigger input to be used to synchronize the counter. +Others: Reserved +See for product specific implementation details. +Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. + 20 + 2 + read-write + + + B_0x0 + Internal trigger 0 (tim_itr0) + 0x0 + + + B_0x1 + Internal trigger 1 (tim_itr1) + 0x1 + + + B_0x2 + Internal trigger 2 (tim_itr2) + 0x2 + + + B_0x3 + Internal trigger 3 (tim_itr3) + 0x3 + + + + + SMSPE + SMS preload enable + + 24 + 1 + read-write + + + B_0x0 + SMS[3:0] bitfield is not preloaded + 0x0 + + + B_0x1 + SMS[3:0] preload is enabled + 0x1 + + + + + SMSPS + SMS preload source + + 25 + 1 + read-write + + + B_0x0 + The transfer is triggered by the Timer's Update event + 0x0 + + + B_0x1 + The transfer is triggered by the Index event + 0x1 + + + + + + + TIM5_DIER + TIM5_DIER + TIM5 DMA/Interrupt enable register + 0x00C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled. + 0x0 + + + B_0x1 + Update interrupt enabled. + 0x1 + + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled. + 0x0 + + + B_0x1 + CC1 interrupt enabled. + 0x1 + + + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + read-write + + + B_0x0 + CC2 interrupt disabled. + 0x0 + + + B_0x1 + CC2 interrupt enabled. + 0x1 + + + + + CC3IE + Capture/Compare 3 interrupt enable + 3 + 1 + read-write + + + B_0x0 + CC3 interrupt disabled. + 0x0 + + + B_0x1 + CC3 interrupt enabled. + 0x1 + + + + + CC4IE + Capture/Compare 4 interrupt enable + 4 + 1 + read-write + + + B_0x0 + CC4 interrupt disabled. + 0x0 + + + B_0x1 + CC4 interrupt enabled. + 0x1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + read-write + + + B_0x0 + Trigger interrupt disabled. + 0x0 + + + B_0x1 + Trigger interrupt enabled. + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled. + 0x0 + + + B_0x1 + Update DMA request enabled. + 0x1 + + + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled. + 0x0 + + + B_0x1 + CC1 DMA request enabled. + 0x1 + + + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled. + 0x0 + + + B_0x1 + CC2 DMA request enabled. + 0x1 + + + + + CC3DE + Capture/Compare 3 DMA request enable + 11 + 1 + read-write + + + B_0x0 + CC3 DMA request disabled. + 0x0 + + + B_0x1 + CC3 DMA request enabled. + 0x1 + + + + + CC4DE + Capture/Compare 4 DMA request enable + 12 + 1 + read-write + + + B_0x0 + CC4 DMA request disabled. + 0x0 + + + B_0x1 + CC4 DMA request enabled. + 0x1 + + + + + TDE + Trigger DMA request enable + 14 + 1 + read-write + + + B_0x0 + Trigger DMA request disabled. + 0x0 + + + B_0x1 + Trigger DMA request enabled. + 0x1 + + + + + IDXIE + Index interrupt enable + 20 + 1 + read-write + + + B_0x0 + Index interrupt disabled + 0x0 + + + B_0x1 + Index interrupt enabled + 0x1 + + + + + DIRIE + Direction change interrupt enable + 21 + 1 + read-write + + + B_0x0 + Direction change interrupt disabled + 0x0 + + + B_0x1 + Direction change interrupt enabled + 0x1 + + + + + IERRIE + Index error interrupt enable + 22 + 1 + read-write + + + B_0x0 + Index error interrupt disabled + 0x0 + + + B_0x1 + Index error interrupt enabled + 0x1 + + + + + TERRIE + Transition error interrupt enable + 23 + 1 + read-write + + + B_0x0 + Transition error interrupt disabled + 0x0 + + + B_0x1 + Transition error interrupt enabled + 0x1 + + + + + + + TIM5_SR + TIM5_SR + TIM5 status register + 0x010 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UIF + Update interrupt flag + + 0 + 1 + read-write + + + B_0x0 + No update occurred + 0x0 + + + B_0x1 + Update interrupt pending. + 0x1 + + + + + CC1IF + Capture/compare 1 interrupt flag + + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred + 0x1 + + + + + CC2IF + Capture/Compare 2 interrupt flag + + 2 + 1 + read-write + + + CC3IF + Capture/Compare 3 interrupt flag + + 3 + 1 + read-write + + + CC4IF + Capture/Compare 4 interrupt flag + + 4 + 1 + read-write + + + TIF + Trigger interrupt flag + + 6 + 1 + read-write + + + B_0x0 + No trigger event occurred. + 0x0 + + + B_0x1 + Trigger interrupt pending. + 0x1 + + + + + CC1OF + Capture/Compare 1 overcapture flag + + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + CC2OF + Capture/compare 2 overcapture flag + + 10 + 1 + read-write + + + CC3OF + Capture/Compare 3 overcapture flag + + 11 + 1 + read-write + + + CC4OF + Capture/Compare 4 overcapture flag + + 12 + 1 + read-write + + + IDXF + Index interrupt flag + + 20 + 1 + read-write + + + B_0x0 + No index event occurred. + 0x0 + + + B_0x1 + An index event has occurred + 0x1 + + + + + DIRF + Direction change interrupt flag + + 21 + 1 + read-write + + + B_0x0 + No direction change + 0x0 + + + B_0x1 + Direction change + 0x1 + + + + + IERRF + Index error interrupt flag + + 22 + 1 + read-write + + + B_0x0 + No index error has been detected. + 0x0 + + + B_0x1 + An index error has been detected + 0x1 + + + + + TERRF + Transition error interrupt flag + + 23 + 1 + read-write + + + B_0x0 + No encoder transition error has been detected. + 0x0 + + + B_0x1 + An encoder transition error has been detected + 0x1 + + + + + + + TIM5_EGR + TIM5_EGR + TIM5 event generation register + 0x014 + 16 + write-only + 0x0000 + 0xFFFF + + + UG + Update generation + + 0 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Re-initialize the counter and generates an update of the registers. + 0x1 + + + + + CC1G + Capture/compare 1 generation + + 1 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + CC2G + Capture/compare 2 generation + + 2 + 1 + write-only + + + CC3G + Capture/compare 3 generation + + 3 + 1 + write-only + + + CC4G + Capture/compare 4 generation + + 4 + 1 + write-only + + + TG + Trigger generation + + 6 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + The TIF flag is set in TIMx_SR register. + 0x1 + + + + + + + TIM5_CCMR1 + TIM5_CCMR1 + TIM5 capture/compare mode register 1 + 0x018 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. + 0x3 + + + + + IC1PSC + Input capture 1 prescaler + + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter + + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + CC2S + Capture/compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output. + 0x0 + + + B_0x1 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2. + 0x1 + + + B_0x2 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1. + 0x2 + + + B_0x3 + CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. + 0x3 + + + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + read-write + + + IC2F + Input capture 2 filter + 12 + 4 + read-write + + + + + TIM5_CCMR1_ALTERNATE1 + TIM5_CCMR1_ALTERNATE1 + TIM5 capture/compare mode register 1 + TIM5_CCMR1 + 0x018 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output. + 0x0 + + + B_0x1 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1. + 0x1 + + + B_0x2 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2. + 0x2 + + + B_0x3 + CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. + 0x3 + + + + + OC1FE + Output compare 1 fast enable + + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. + 0x1 + + + + + OC1PE + Output compare 1 preload enable + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. + 0x1 + + + + + OC1M + OC1M[2:0]: Output compare 1 mode + + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. + 0x2 + + + B_0x3 + Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - tim_oc1ref is forced low. + 0x4 + + + B_0x5 + Force active level - tim_oc1ref is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. + 0x6 + + + B_0x7 + PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. + 0x7 + + + + + OC1CE + Output compare 1 clear enable + 7 + 1 + read-write + + + B_0x0 + tim_oc1ref is not affected by the tim_ocref_clr_int input + 0x0 + + + B_0x1 + tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr_int input + 0x1 + + + + + CC2S + Capture/Compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. + 0x3 + + + + + OC2FE + Output compare 2 fast enable + 10 + 1 + read-write + + + OC2PE + Output compare 2 preload enable + 11 + 1 + read-write + + + OC2M + OC2M[2:0]: Output compare 2 mode + + 12 + 3 + read-write + + + OC2CE + Output compare 2 clear enable + 15 + 1 + read-write + + + OC1M_1 + OC1M[3] + 16 + 1 + read-write + + + OC2M_1 + OC2M[3] + 24 + 1 + read-write + + + + + TIM5_CCMR2 + TIM5_CCMR2 + TIM5 capture/compare mode register 2 + 0x01C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. + 0x3 + + + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + read-write + + + IC3F + Input capture 3 filter + 4 + 4 + read-write + + + CC4S + Capture/Compare 4 selection + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. + 0x3 + + + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + read-write + + + IC4F + Input capture 4 filter + 12 + 4 + read-write + + + + + TIM5_CCMR2_ALTERNATE1 + TIM5_CCMR2_ALTERNATE1 + TIM5 capture/compare mode register 2 + TIM5_CCMR2 + 0x01C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. + 0x3 + + + + + OC3FE + Output compare 3 fast enable + 2 + 1 + read-write + + + OC3PE + Output compare 3 preload enable + 3 + 1 + read-write + + + OC3M + OC3M[2:0]: Output compare 3 mode + + 4 + 3 + read-write + + + OC3CE + Output compare 3 clear enable + 7 + 1 + read-write + + + CC4S + Capture/Compare 4 selection + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. + 0x3 + + + + + OC4FE + Output compare 4 fast enable + 10 + 1 + read-write + + + OC4PE + Output compare 4 preload enable + 11 + 1 + read-write + + + OC4M + OC4M[2:0]: Output compare 4 mode + + 12 + 3 + read-write + + + OC4CE + Output compare 4 clear enable + 15 + 1 + read-write + + + OC3M_1 + OC3M[3] + 16 + 1 + read-write + + + OC4M_1 + OC4M[3] + 24 + 1 + read-write + + + + + TIM5_CCER + TIM5_CCER + TIM5 capture/compare enable register + 0x020 + 16 + read-write + 0x0000 + 0xFFFF + + + CC1E + Capture/Compare 1 output enable. + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/Compare 1 output Polarity. + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NP + Capture/Compare 1 output Polarity. + 3 + 1 + read-write + + + CC2E + Capture/Compare 2 output enable. + 4 + 1 + read-write + + + CC2P + Capture/Compare 2 output Polarity. + 5 + 1 + read-write + + + CC2NP + Capture/Compare 2 output Polarity. + 7 + 1 + read-write + + + CC3E + Capture/Compare 3 output enable. + 8 + 1 + read-write + + + CC3P + Capture/Compare 3 output Polarity. + 9 + 1 + read-write + + + CC3NP + Capture/Compare 3 output Polarity. + 11 + 1 + read-write + + + CC4E + Capture/Compare 4 output enable. + 12 + 1 + read-write + + + CC4P + Capture/Compare 4 output Polarity. + 13 + 1 + read-write + + + CC4NP + Capture/Compare 4 output Polarity. + 15 + 1 + read-write + + + + + TIM5_CNT + TIM5_CNT + TIM5 counter + 0x024 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Least significant part of counter value + + 0 + 31 + read-write + + + UIFCPY_CNT + Value depends on IUFREMAP in TIMx_CR1. + 31 + 1 + read-write + + + + + TIM5_PSC + TIM5_PSC + TIM5 prescaler + 0x028 + 16 + read-write + 0x0000 + 0xFFFF + + + PSC + Prescaler value + + 0 + 16 + read-write + + + + + TIM5_ARR + TIM5_ARR + TIM5 auto-reload register + 0x02C + 0x20 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + ARR + Auto-reload value + + 0 + 32 + read-write + + + + + TIM5_CCR1 + TIM5_CCR1 + TIM5 capture/compare register 1 + 0x034 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR1 + Capture/compare 1 value + + 0 + 32 + read-write + + + + + TIM5_CCR2 + TIM5_CCR2 + TIM5 capture/compare register 2 + 0x038 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR2 + Capture/compare 2 value + + 0 + 32 + read-write + + + + + TIM5_CCR3 + TIM5_CCR3 + TIM5 capture/compare register 3 + 0x03C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR3 + Capture/compare 3 value + + 0 + 32 + read-write + + + + + TIM5_CCR4 + TIM5_CCR4 + TIM5 capture/compare register 4 + 0x040 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR4 + Capture/compare 4 value + + 0 + 32 + read-write + + + + + TIM5_ECR + TIM5_ECR + TIM5 timer encoder control register + 0x058 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IE + Index enable + + 0 + 1 + read-write + + + B_0x0 + Index disabled + 0x0 + + + B_0x1 + Index enabled + 0x1 + + + + + IDIR + Index direction + + 1 + 2 + read-write + + + B_0x0 + Index resets the counter whatever the direction + 0x0 + + + B_0x1 + Index resets the counter when up-counting only + 0x1 + + + B_0x2 + Index resets the counter when down-counting only + 0x2 + + + + + IBLK + Index blanking + + 3 + 2 + read-write + + + B_0x0 + Index always active + 0x0 + + + B_0x1 + Index disabled hen tim_ti3 input is active, as per CC3P bitfield + 0x1 + + + B_0x2 + Index disabled when tim_ti4 input is active, as per CC4P bitfield + 0x2 + + + + + FIDX + First index + + 5 + 1 + read-write + + + B_0x0 + Index is always active + 0x0 + + + B_0x1 + the first Index only resets the counter + 0x1 + + + + + IPOS + Index positioning + + 6 + 2 + read-write + + + B_0x0 + Index resets the counter when AB = 00 + 0x0 + + + B_0x1 + Index resets the counter when AB = 01 + 0x1 + + + B_0x2 + Index resets the counter when AB = 10 + 0x2 + + + B_0x3 + Index resets the counter when AB = 11 + 0x3 + + + + + PW + Pulse width + + 16 + 8 + read-write + + + PWPRSC + Pulse width prescaler + + 24 + 3 + read-write + + + + + TIM5_TISEL + TIM5_TISEL + TIM5 timer input selection register + 0x05C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + Selects tim_ti1[15:0] input + + 0 + 4 + read-write + + + B_0x0 + tim_ti1_in0: TIMx_CH1 + 0x0 + + + B_0x1 + tim_ti1_in1 + 0x1 + + + B_0xF + tim_ti1_in15 + 0xF + + + + + TI2SEL + Selects tim_ti2[15:0] input + + 8 + 4 + read-write + + + B_0x0 + tim_ti2_in0: TIMx_CH2 + 0x0 + + + B_0x1 + tim_ti2_in1 + 0x1 + + + B_0xF + tim_ti2_in15 + 0xF + + + + + TI3SEL + Selects tim_ti3[15:0] input + + 16 + 4 + read-write + + + B_0x0 + tim_ti3_in0: TIMx_CH3 + 0x0 + + + B_0x1 + tim_ti3_in1 + 0x1 + + + B_0xF + tim_ti3_in15 + 0xF + + + + + TI4SEL + Selects tim_ti4[15:0] input + + 24 + 4 + read-write + + + B_0x0 + tim_ti4_in0: TIMx_CH4 + 0x0 + + + B_0x1 + tim_ti4_in1 + 0x1 + + + B_0xF + tim_ti4_in15 + 0xF + + + + + + + TIM5_AF1 + TIM5_AF1 + TIM5 alternate function register 1 + 0x060 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ETRSEL + etr_in source selection + + 14 + 4 + read-write + + + B_0x0 + tim_etr0: TIMx_ETR input + 0x0 + + + B_0x1 + tim_etr1 + 0x1 + + + B_0xF + tim_etr15 + 0xF + + + + + + + TIM5_AF2 + TIM5_AF2 + TIM5 alternate function register 2 + 0x064 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OCRSEL + ocref_clr source selection + + 16 + 3 + read-write + + + B_0x0 + tim_ocref_clr0 + 0x0 + + + B_0x1 + tim_ocref_clr1 + 0x1 + + + B_0x7 + tim_ocref_clr7 + 0x7 + + + + + + + TIM5_DCR + TIM5_DCR + TIM5 DMA control register + 0x3DC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DBA + DMA base address + + 0 + 5 + read-write + + + B_0x0 + TIMx_CR1, + 0x0 + + + B_0x1 + TIMx_CR2, + 0x1 + + + B_0x2 + TIMx_SMCR, + 0x2 + + + + + DBL + DMA burst length + + 8 + 5 + read-write + + + B_0x0 + 1 transfer + 0x0 + + + B_0x1 + 2 transfers + 0x1 + + + B_0x2 + 3 transfers + 0x2 + + + B_0x1A + 26 transfers + 0x1A + + + + + DBSS + DMA burst source selection + + 16 + 4 + read-write + + + B_0x1 + Update + 0x1 + + + B_0x2 + CC1 + 0x2 + + + B_0x3 + CC2 + 0x3 + + + B_0x4 + CC3 + 0x4 + + + B_0x5 + CC4 + 0x5 + + + B_0x6 + COM + 0x6 + + + B_0x7 + Trigger + 0x7 + + + + + + + TIM5_DMAR + TIM5_DMAR + TIM5 DMA address for full transfer + 0x3E0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DMAB + DMA register for burst accesses + + 0 + 32 + read-write + + + + + + + TIM5_S + 0X50000C00 + + + TIM6 + TIM6 address block description + TIM6 + 0x40001000 + + 0x0 + 0x30 + registers + + + TIM6 + TIM6 global interrupt + 49 + + + + TIM6_CR1 + TIM6_CR1 + TIM6 control register 1 + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + CEN + Counter enable + + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable + + 1 + 1 + read-write + + + B_0x0 + UEV enabled. + 0x0 + + + B_0x1 + UEV disabled. + 0x1 + + + + + URS + Update request source + + 2 + 1 + read-write + + + B_0x0 + Any of the following events generates an update interrupt or DMA request if enabled. + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the CEN bit). + 0x1 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered. + 0x0 + + + B_0x1 + TIMx_ARR register is buffered. + 0x1 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. + 0x0 + + + B_0x1 + Remapping enabled. + 0x1 + + + + + DITHEN + Dithering enable + + 12 + 1 + read-write + + + B_0x0 + Dithering disabled + 0x0 + + + B_0x1 + Dithering enabled + 0x1 + + + + + + + TIM6_CR2 + TIM6_CR2 + TIM6 control register 2 + 0x04 + 16 + read-write + 0x0000 + 0xFFFF + + + MMS + Master mode selection + + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as a trigger output (tim_trgo). + 0x0 + + + B_0x1 + Enable - the Counter enable signal, tim_cnt_en, is used as a trigger output (tim_trgo). + 0x1 + + + B_0x2 + Update - The update event is selected as a trigger output (tim_trgo). + 0x2 + + + + + + + TIM6_DIER + TIM6_DIER + TIM6 DMA/Interrupt enable register + 0x0C + 16 + read-write + 0x0000 + 0xFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled. + 0x0 + + + B_0x1 + Update interrupt enabled. + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled. + 0x0 + + + B_0x1 + Update DMA request enabled. + 0x1 + + + + + + + TIM6_SR + TIM6_SR + TIM6 status register + 0x10 + 16 + read-write + 0x0000 + 0xFFFF + + + UIF + Update interrupt flag + + 0 + 1 + read-write + + + B_0x0 + No update occurred. + 0x0 + + + B_0x1 + Update interrupt pending. + 0x1 + + + + + + + TIM6_EGR + TIM6_EGR + TIM6 event generation register + 0x14 + 16 + write-only + 0x0000 + 0xFFFF + + + UG + Update generation + + 0 + 1 + write-only + + + B_0x0 + No action. + 0x0 + + + B_0x1 + Re-initializes the timer counter and generates an update of the registers. + 0x1 + + + + + + + TIM6_CNT + TIM6_CNT + TIM6 counter + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + + 0 + 16 + read-write + + + UIFCPY + UIF copy + + 31 + 1 + read-only + + + + + TIM6_PSC + TIM6_PSC + TIM6 prescaler + 0x28 + 16 + read-write + 0x0000 + 0xFFFF + + + PSC + Prescaler value + + 0 + 16 + read-write + + + + + TIM6_ARR + TIM6_ARR + TIM6 auto-reload register + 0x2C + 0x20 + read-write + 0x0000FFFF + 0xFFFFFFFF + + + ARR + Auto-reload value + + 0 + 20 + read-write + + + + + + + TIM6_S + 0X50001000 + + + TIM7 + TIM7 address block description + TIM7 + 0x40001400 + + 0x0 + 0x30 + registers + + + TIM7 + TIM7 global interrupt + 50 + + + + TIM7_CR1 + TIM7_CR1 + TIM7 control register 1 + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + CEN + Counter enable + + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable + + 1 + 1 + read-write + + + B_0x0 + UEV enabled. + 0x0 + + + B_0x1 + UEV disabled. + 0x1 + + + + + URS + Update request source + + 2 + 1 + read-write + + + B_0x0 + Any of the following events generates an update interrupt or DMA request if enabled. + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the CEN bit). + 0x1 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered. + 0x0 + + + B_0x1 + TIMx_ARR register is buffered. + 0x1 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. + 0x0 + + + B_0x1 + Remapping enabled. + 0x1 + + + + + DITHEN + Dithering enable + + 12 + 1 + read-write + + + B_0x0 + Dithering disabled + 0x0 + + + B_0x1 + Dithering enabled + 0x1 + + + + + + + TIM7_CR2 + TIM7_CR2 + TIM7 control register 2 + 0x04 + 16 + read-write + 0x0000 + 0xFFFF + + + MMS + Master mode selection + + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as a trigger output (tim_trgo). + 0x0 + + + B_0x1 + Enable - the Counter enable signal, tim_cnt_en, is used as a trigger output (tim_trgo). + 0x1 + + + B_0x2 + Update - The update event is selected as a trigger output (tim_trgo). + 0x2 + + + + + + + TIM7_DIER + TIM7_DIER + TIM7 DMA/Interrupt enable register + 0x0C + 16 + read-write + 0x0000 + 0xFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled. + 0x0 + + + B_0x1 + Update interrupt enabled. + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled. + 0x0 + + + B_0x1 + Update DMA request enabled. + 0x1 + + + + + + + TIM7_SR + TIM7_SR + TIM7 status register + 0x10 + 16 + read-write + 0x0000 + 0xFFFF + + + UIF + Update interrupt flag + + 0 + 1 + read-write + + + B_0x0 + No update occurred. + 0x0 + + + B_0x1 + Update interrupt pending. + 0x1 + + + + + + + TIM7_EGR + TIM7_EGR + TIM7 event generation register + 0x14 + 16 + write-only + 0x0000 + 0xFFFF + + + UG + Update generation + + 0 + 1 + write-only + + + B_0x0 + No action. + 0x0 + + + B_0x1 + Re-initializes the timer counter and generates an update of the registers. + 0x1 + + + + + + + TIM7_CNT + TIM7_CNT + TIM7 counter + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + + 0 + 16 + read-write + + + UIFCPY + UIF copy + + 31 + 1 + read-only + + + + + TIM7_PSC + TIM7_PSC + TIM7 prescaler + 0x28 + 16 + read-write + 0x0000 + 0xFFFF + + + PSC + Prescaler value + + 0 + 16 + read-write + + + + + TIM7_ARR + TIM7_ARR + TIM7 auto-reload register + 0x2C + 0x20 + read-write + 0x0000FFFF + 0xFFFFFFFF + + + ARR + Auto-reload value + + 0 + 20 + read-write + + + + + + + TIM7_S + 0X50001400 + + + TIM8 + TIM8 address block description + TIM8 + 0x40013400 + + 0x0 + 0x3E4 + registers + + + TIM8_CC + TIM8 capture compare interrupt + 68 + + + TIM8_TRGI_DIR_IDX + TIM8 trigger and commutation interrupt/TIM8 Direction Change interrupt/TIM8 Index + 67 + + + TIM8_UPD + TIM8 Update interrupt + 66 + + + TIM8_BRK_TERR_IERR + TIM8 Break interrupt/TIM8 Transition error/TIM8 Index error + 65 + + + + TIM8_CR1 + TIM8_CR1 + TIM8 control register 1 + 0x000 + 16 + read-write + 0x0000 + 0xFFFF + + + CEN + Counter enable + + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable + + 1 + 1 + read-write + + + B_0x0 + UEV enabled. + 0x0 + + + B_0x1 + UEV disabled. + 0x1 + + + + + URS + Update request source + + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt or DMA request if enabled. + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + DIR + Direction + + 4 + 1 + read-write + + + B_0x0 + Counter used as upcounter + 0x0 + + + B_0x1 + Counter used as downcounter + 0x1 + + + + + CMS + Center-aligned mode selection + + 5 + 2 + read-write + + + B_0x0 + Edge-aligned mode. + 0x0 + + + B_0x1 + Center-aligned mode 1. + 0x1 + + + B_0x2 + Center-aligned mode 2. + 0x2 + + + B_0x3 + Center-aligned mode 3. + 0x3 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division + + 8 + 2 + read-write + + + B_0x0 + tless thansub>DTSless than/sub>=tless thansub>tim_ker_ckless than/sub> + 0x0 + + + B_0x1 + tless thansub>DTSless than/sub>=2*tless thansub>tim_ker_ckless than/sub> + 0x1 + + + B_0x2 + tless thansub>DTSless than/sub>=4*tless thansub>tim_ker_ckless than/sub> + 0x2 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. + 0x0 + + + B_0x1 + Remapping enabled. + 0x1 + + + + + DITHEN + Dithering enable + + 12 + 1 + read-write + + + B_0x0 + Dithering disabled + 0x0 + + + B_0x1 + Dithering enabled + 0x1 + + + + + + + TIM8_CR2 + TIM8_CR2 + TIM8 control register 2 + 0x004 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCPC + Capture/compare preloaded control + + 0 + 1 + read-write + + + B_0x0 + CCxE, CCxNE and OCxM bits are not preloaded + 0x0 + + + B_0x1 + CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on tim_trgi, depending on the CCUS bit). + 0x1 + + + + + CCUS + Capture/compare control update selection + + 2 + 1 + read-write + + + B_0x0 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only + 0x0 + + + B_0x1 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on tim_trgi + 0x1 + + + + + CCDS + Capture/compare DMA selection + 3 + 1 + read-write + + + B_0x0 + CCx DMA request sent when CCx event occurs + 0x0 + + + B_0x1 + CCx DMA requests sent when update event occurs + 0x1 + + + + + MMS + MMS[2:0]: Master mode selection + + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo). + 0x0 + + + B_0x1 + Enable - the Counter Enable signal CNT_EN is used as trigger output (tim_trgo). + 0x1 + + + B_0x2 + Update - The update event is selected as trigger output (tim_trgo). + 0x2 + + + B_0x3 + Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. + 0x3 + + + B_0x4 + Compare - tim_oc1refc signal is used as trigger output (tim_trgo) + 0x4 + + + B_0x5 + Compare - tim_oc2refc signal is used as trigger output (tim_trgo) + 0x5 + + + B_0x6 + Compare - tim_oc3refc signal is used as trigger output (tim_trgo) + 0x6 + + + B_0x7 + Compare - tim_oc4refc signal is used as trigger output (tim_trgo) + 0x7 + + + + + TI1S + tim_ti1 selection + 7 + 1 + read-write + + + B_0x0 + The tim_ti1_in[15:0] multiplexer output is connected to tim_ti1 input + 0x0 + + + B_0x1 + tim_ti1_in[15:0], tim_ti2_in[15:0] and tim_ti3_in[15:0] multiplexers outputs are XORed and connected to the tim_ti1 input + 0x1 + + + + + OIS1 + Output idle state 1 (tim_oc1 output) + + 8 + 1 + read-write + + + B_0x0 + tim_oc1=0 (after a dead-time) when MOE=0 + 0x0 + + + B_0x1 + tim_oc1=1 (after a dead-time) when MOE=0 + 0x1 + + + + + OIS1N + Output idle state 1 (tim_oc1n output) + + 9 + 1 + read-write + + + B_0x0 + tim_oc1n=0 after a dead-time when MOE=0 + 0x0 + + + B_0x1 + tim_oc1n=1 after a dead-time when MOE=0 + 0x1 + + + + + OIS2 + Output idle state 2 (tim_oc2 output) + + 10 + 1 + read-write + + + OIS2N + Output idle state 2 (tim_oc2n output) + + 11 + 1 + read-write + + + OIS3 + Output idle state 3 (tim_oc3n output) + + 12 + 1 + read-write + + + OIS3N + Output idle state 3 (tim_oc3n output) + + 13 + 1 + read-write + + + OIS4 + Output idle state 4 (tim_oc4 output) + + 14 + 1 + read-write + + + OIS4N + Output idle state 4 (tim_oc4n output) + + 15 + 1 + read-write + + + OIS5 + Output idle state 5 (tim_oc5 output) + + 16 + 1 + read-write + + + OIS6 + Output idle state 6 (tim_oc6 output) + + 18 + 1 + read-write + + + MMS2 + Master mode selection 2 + + 20 + 4 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo2). + 0x0 + + + B_0x1 + Enable - the Counter Enable signal CNT_EN is used as trigger output (tim_trgo2). + 0x1 + + + B_0x2 + Update - the update event is selected as trigger output (tim_trgo2). + 0x2 + + + B_0x3 + Compare pulse - the trigger output sends a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or compare match occurs (tim_trgo2). + 0x3 + + + B_0x4 + Compare - tim_oc1refc signal is used as trigger output (tim_trgo2) + 0x4 + + + B_0x5 + Compare - tim_oc2refc signal is used as trigger output (tim_trgo2) + 0x5 + + + B_0x6 + Compare - tim_oc3refc signal is used as trigger output (tim_trgo2) + 0x6 + + + B_0x7 + Compare - tim_oc4refc signal is used as trigger output (tim_trgo2) + 0x7 + + + B_0x8 + Compare - tim_oc5refc signal is used as trigger output (tim_trgo2) + 0x8 + + + B_0x9 + Compare - tim_oc6refc signal is used as trigger output (tim_trgo2) + 0x9 + + + B_0xA + Compare Pulse - tim_oc4refc rising or falling edges generate pulses on tim_trgo2 + 0xA + + + B_0xB + Compare pulse - tim_oc6refc rising or falling edges generate pulses on tim_trgo2 + 0xB + + + B_0xC + Compare pulse - tim_oc4refc or tim_oc6refc rising edges generate pulses on tim_trgo2 + 0xC + + + B_0xD + Compare pulse - tim_oc4refc rising or tim_oc6refc falling edges generate pulses on tim_trgo2 + 0xD + + + B_0xE + Compare pulse - tim_oc5refc or tim_oc6refc rising edges generate pulses on tim_trgo2 + 0xE + + + B_0xF + Compare pulse - tim_oc5refc rising or tim_oc6refc falling edges generate pulses on tim_trgo2 + 0xF + + + + + MMS_1 + MMS[3] + 25 + 1 + read-write + + + + + TIM8_SMCR + TIM8_SMCR + TIM8 slave mode control register + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SMS + SMS[2:0]: Slave mode selection + + 0 + 3 + read-write + + + B_0x0 + Slave mode disabled - if CEN = 1' then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Quadrature encoder mode 1, x2 mode- Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level. + 0x1 + + + B_0x2 + Quadrature encoder mode 2, x2 mode - Counter counts up/down on tim_ti2fp2 edge depending on tim_ti1fp1 level. + 0x2 + + + B_0x3 + Quadrature encoder mode 3, x4 mode - Counter counts up/down on both tim_ti1fp1 and tim_ti2fp2 edges depending on the level of the other input. + 0x3 + + + B_0x4 + Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers. + 0x4 + + + B_0x5 + Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high. + 0x5 + + + B_0x6 + Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). + 0x6 + + + B_0x7 + External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter. + 0x7 + + + + + OCCS + OCREF clear selection + + 3 + 1 + read-write + + + B_0x0 + tim_ocref_clr_int is connected to the tim_ocref_clr input + 0x0 + + + B_0x1 + tim_ocref_clr_int is connected to tim_etrf + 0x1 + + + + + TS + TS[2:0]: Trigger selection + + 4 + 3 + read-write + + + B_0x0 + Internal Trigger 0 (tim_itr0) + 0x0 + + + B_0x1 + Internal Trigger 1 (tim_itr1) + 0x1 + + + B_0x2 + Internal Trigger 2 (tim_itr2) + 0x2 + + + B_0x3 + Internal Trigger 3 (tim_itr3) + 0x3 + + + B_0x4 + tim_ti1 Edge Detector (tim_ti1f_ed) + 0x4 + + + B_0x5 + Filtered Timer Input 1 (tim_ti1fp1) + 0x5 + + + B_0x6 + Filtered Timer Input 2 (tim_ti2fp2) + 0x6 + + + B_0x7 + External Trigger input (tim_etrf) + 0x7 + + + + + MSM + Master/slave mode + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). + 0x1 + + + + + ETF + External trigger filter + + 8 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + ETPS + External trigger prescaler + + 12 + 2 + read-write + + + B_0x0 + Prescaler OFF + 0x0 + + + B_0x1 + tim_etr_in frequency divided by 2 + 0x1 + + + B_0x2 + tim_etr_in frequency divided by 4 + 0x2 + + + B_0x3 + tim_etr_in frequency divided by 8 + 0x3 + + + + + ECE + External clock enable + + 14 + 1 + read-write + + + B_0x0 + External clock mode 2 disabled + 0x0 + + + B_0x1 + External clock mode 2 enabled. + 0x1 + + + + + ETP + External trigger polarity + + 15 + 1 + read-write + + + B_0x0 + tim_etr_in is non-inverted, active at high level or rising edge. + 0x0 + + + B_0x1 + tim_etr_in is inverted, active at low level or falling edge. + 0x1 + + + + + SMS_1 + Slave mode selection +When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (see Input Control register and Control Register description. +Note: The gated mode must not be used if tim_ti1f_ed is selected as the trigger input (TS=00100). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on tim_ti1f, whereas the gated mode checks the level of the trigger signal. +Note: The clock of the slave peripherals (timer, ADC, ...) receiving the tim_trgo signal must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. + 16 + 1 + read-write + + + B_0x0 + Slave mode disabled - if CEN = '1 then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level. + 0x1 + + + + + TS_1 + Trigger selection +This bit-field selects the trigger input to be used to synchronize the counter. +Others: Reserved +See for product specific implementation details. +Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. + 20 + 2 + read-write + + + B_0x0 + Internal trigger 0 (tim_itr0) + 0x0 + + + B_0x1 + Internal trigger 1 (tim_itr1) + 0x1 + + + B_0x2 + Internal trigger 2 (tim_itr2) + 0x2 + + + B_0x3 + Internal trigger 3 (tim_itr3) + 0x3 + + + + + SMSPE + SMS preload enable + + 24 + 1 + read-write + + + B_0x0 + SMS[3:0] bitfield is not preloaded + 0x0 + + + B_0x1 + SMS[3:0] preload is enabled + 0x1 + + + + + SMSPS + SMS preload source + + 25 + 1 + read-write + + + B_0x0 + The transfer is triggered by the Timer's Update event + 0x0 + + + B_0x1 + The transfer is triggered by the Index event + 0x1 + + + + + + + TIM8_DIER + TIM8_DIER + TIM8 DMA/interrupt enable register + 0x00C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled + 0x0 + + + B_0x1 + Update interrupt enabled + 0x1 + + + + + CC1IE + Capture/compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled + 0x0 + + + B_0x1 + CC1 interrupt enabled + 0x1 + + + + + CC2IE + Capture/compare 2 interrupt enable + 2 + 1 + read-write + + + B_0x0 + CC2 interrupt disabled + 0x0 + + + B_0x1 + CC2 interrupt enabled + 0x1 + + + + + CC3IE + Capture/compare 3 interrupt enable + 3 + 1 + read-write + + + B_0x0 + CC3 interrupt disabled + 0x0 + + + B_0x1 + CC3 interrupt enabled + 0x1 + + + + + CC4IE + Capture/compare 4 interrupt enable + 4 + 1 + read-write + + + B_0x0 + CC4 interrupt disabled + 0x0 + + + B_0x1 + CC4 interrupt enabled + 0x1 + + + + + COMIE + COM interrupt enable + 5 + 1 + read-write + + + B_0x0 + COM interrupt disabled + 0x0 + + + B_0x1 + COM interrupt enabled + 0x1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + read-write + + + B_0x0 + Trigger interrupt disabled + 0x0 + + + B_0x1 + Trigger interrupt enabled + 0x1 + + + + + BIE + Break interrupt enable + 7 + 1 + read-write + + + B_0x0 + Break interrupt disabled + 0x0 + + + B_0x1 + Break interrupt enabled + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled + 0x0 + + + B_0x1 + Update DMA request enabled + 0x1 + + + + + CC1DE + Capture/compare 1 DMA request enable + 9 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled + 0x0 + + + B_0x1 + CC1 DMA request enabled + 0x1 + + + + + CC2DE + Capture/compare 2 DMA request enable + 10 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled + 0x0 + + + B_0x1 + CC2 DMA request enabled + 0x1 + + + + + CC3DE + Capture/compare 3 DMA request enable + 11 + 1 + read-write + + + B_0x0 + CC3 DMA request disabled + 0x0 + + + B_0x1 + CC3 DMA request enabled + 0x1 + + + + + CC4DE + Capture/compare 4 DMA request enable + 12 + 1 + read-write + + + B_0x0 + CC4 DMA request disabled + 0x0 + + + B_0x1 + CC4 DMA request enabled + 0x1 + + + + + COMDE + COM DMA request enable + 13 + 1 + read-write + + + B_0x0 + COM DMA request disabled + 0x0 + + + B_0x1 + COM DMA request enabled + 0x1 + + + + + TDE + Trigger DMA request enable + 14 + 1 + read-write + + + B_0x0 + Trigger DMA request disabled + 0x0 + + + B_0x1 + Trigger DMA request enabled + 0x1 + + + + + IDXIE + Index interrupt enable + 20 + 1 + read-write + + + B_0x0 + Index interrupt disabled + 0x0 + + + B_0x1 + Index Change interrupt enabled + 0x1 + + + + + DIRIE + Direction change interrupt enable + 21 + 1 + read-write + + + B_0x0 + Direction Change interrupt disabled + 0x0 + + + B_0x1 + Direction Change interrupt enabled + 0x1 + + + + + IERRIE + Index error interrupt enable + 22 + 1 + read-write + + + B_0x0 + Index error interrupt disabled + 0x0 + + + B_0x1 + Index error interrupt enabled + 0x1 + + + + + TERRIE + Transition error interrupt enable + 23 + 1 + read-write + + + B_0x0 + Transition error interrupt disabled + 0x0 + + + B_0x1 + Transition error interrupt enabled + 0x1 + + + + + + + TIM8_SR + TIM8_SR + TIM8 status register + 0x010 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UIF + Update interrupt flag + + 0 + 1 + read-write + + + B_0x0 + No update occurred. + 0x0 + + + B_0x1 + Update interrupt pending. + 0x1 + + + + + CC1IF + Capture/compare 1 interrupt flag + + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred + 0x1 + + + + + CC2IF + Capture/compare 2 interrupt flag + + 2 + 1 + read-write + + + CC3IF + Capture/compare 3 interrupt flag + + 3 + 1 + read-write + + + CC4IF + Capture/compare 4 interrupt flag + + 4 + 1 + read-write + + + COMIF + COM interrupt flag + + 5 + 1 + read-write + + + B_0x0 + No COM event occurred. + 0x0 + + + B_0x1 + COM interrupt pending. + 0x1 + + + + + TIF + Trigger interrupt flag + + 6 + 1 + read-write + + + B_0x0 + No trigger event occurred. + 0x0 + + + B_0x1 + Trigger interrupt pending. + 0x1 + + + + + BIF + Break interrupt flag + + 7 + 1 + read-write + + + B_0x0 + No break event occurred. + 0x0 + + + B_0x1 + An active level has been detected on the break input. + 0x1 + + + + + B2IF + Break 2 interrupt flag + + 8 + 1 + read-write + + + B_0x0 + No break event occurred. + 0x0 + + + B_0x1 + An active level has been detected on the break 2 input. + 0x1 + + + + + CC1OF + Capture/compare 1 overcapture flag + + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + CC2OF + Capture/compare 2 overcapture flag + + 10 + 1 + read-write + + + CC3OF + Capture/compare 3 overcapture flag + + 11 + 1 + read-write + + + CC4OF + Capture/compare 4 overcapture flag + + 12 + 1 + read-write + + + SBIF + System break interrupt flag + + 13 + 1 + read-write + + + B_0x0 + No break event occurred. + 0x0 + + + B_0x1 + An active level has been detected on the system break input. + 0x1 + + + + + CC5IF + Compare 5 interrupt flag + + 16 + 1 + read-write + + + CC6IF + Compare 6 interrupt flag + + 17 + 1 + read-write + + + IDXF + Index interrupt flag + + 20 + 1 + read-write + + + B_0x0 + No index event occurred. + 0x0 + + + B_0x1 + An index event has occurred + 0x1 + + + + + DIRF + Direction change interrupt flag + + 21 + 1 + read-write + + + B_0x0 + No direction change + 0x0 + + + B_0x1 + Direction change + 0x1 + + + + + IERRF + Index error interrupt flag + + 22 + 1 + read-write + + + B_0x0 + No index error has been detected. + 0x0 + + + B_0x1 + An index error has been detected + 0x1 + + + + + TERRF + Transition error interrupt flag + + 23 + 1 + read-write + + + B_0x0 + No encoder transition error has been detected. + 0x0 + + + B_0x1 + An encoder transition error has been detected + 0x1 + + + + + + + TIM8_EGR + TIM8_EGR + TIM8 event generation register + 0x014 + 16 + write-only + 0x0000 + 0xFFFF + + + UG + Update generation + + 0 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Reinitialize the counter and generates an update of the registers. + 0x1 + + + + + CC1G + Capture/compare 1 generation + + 1 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + CC2G + Capture/compare 2 generation + + 2 + 1 + write-only + + + CC3G + Capture/compare 3 generation + + 3 + 1 + write-only + + + CC4G + Capture/compare 4 generation + + 4 + 1 + write-only + + + COMG + Capture/compare control update generation + + 5 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + CCxE, CCxNE and OCxM bits update (providing CCPC bit is set) + 0x1 + + + + + TG + Trigger generation + + 6 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + The TIF flag is set in TIMx_SR register. + 0x1 + + + + + BG + Break generation + + 7 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A break event is generated. + 0x1 + + + + + B2G + Break 2 generation + + 8 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A break 2 event is generated. + 0x1 + + + + + + + TIM8_CCMR1 + TIM8_CCMR1 + TIM8 capture/compare mode register 1 + 0x018 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/compare 1 Selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. + 0x3 + + + + + IC1PSC + Input capture 1 prescaler + + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter + + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + CC2S + Capture/compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. + 0x3 + + + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + read-write + + + IC2F + Input capture 2 filter + 12 + 4 + read-write + + + + + TIM8_CCMR1_ALTERNATE1 + TIM8_CCMR1_ALTERNATE1 + TIM8 capture/compare mode register 1 + TIM8_CCMR1 + 0x018 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. + 0x3 + + + + + OC1FE + Output compare 1 fast enable + + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. + 0x1 + + + + + OC1PE + Output compare 1 preload enable + + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. + 0x1 + + + + + OC1M + OC1M[2:0]: Output compare 1 mode + + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. + 0x2 + + + B_0x3 + Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - tim_oc1ref is forced low. + 0x4 + + + B_0x5 + Force active level - tim_oc1ref is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. + 0x6 + + + B_0x7 + PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. + 0x7 + + + + + OC1CE + Output compare 1 clear enable + 7 + 1 + read-write + + + B_0x0 + tim_oc1ref is not affected by the tim_ocref_clr_int signal + 0x0 + + + B_0x1 + tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr_int signal (tim_ocref_clr input or tim_etrf input) + 0x1 + + + + + CC2S + Capture/compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. + 0x3 + + + + + OC2FE + Output compare 2 fast enable + 10 + 1 + read-write + + + OC2PE + Output compare 2 preload enable + 11 + 1 + read-write + + + OC2M + OC2M[2:0]: Output compare 2 mode + 12 + 3 + read-write + + + OC2CE + Output compare 2 clear enable + 15 + 1 + read-write + + + OC1M_1 + OC1M[3] + 16 + 1 + read-write + + + OC2M_1 + OC2M[3] + 24 + 1 + read-write + + + + + TIM8_CCMR2 + TIM8_CCMR2 + TIM8 capture/compare mode register 2 + 0x01C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/compare 3 selection + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. + 0x3 + + + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + read-write + + + IC3F + Input capture 3 filter + 4 + 4 + read-write + + + CC4S + Capture/compare 4 selection + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. + 0x3 + + + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + read-write + + + IC4F + Input capture 4 filter + 12 + 4 + read-write + + + + + TIM8_CCMR2_ALTERNATE1 + TIM8_CCMR2_ALTERNATE1 + TIM8 capture/compare mode register 2 + TIM8_CCMR2 + 0x01C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/compare 3 selection + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. + 0x3 + + + + + OC3FE + Output compare 3 fast enable + 2 + 1 + read-write + + + OC3PE + Output compare 3 preload enable + 3 + 1 + read-write + + + OC3M + OC3M[2:0]: Output compare 3 mode + + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR3 and the counter TIMx_CNT has no effect on the outputs. + 0x0 + + + B_0x1 + Set channel 3 to active level on match. + 0x1 + + + B_0x2 + Set channel 3 to inactive level on match. + 0x2 + + + B_0x3 + Toggle - tim_oc3ref toggles when TIMx_CNT=TIMx_CCR3. + 0x3 + + + B_0x4 + Force inactive level - tim_oc3ref is forced low. + 0x4 + + + B_0x5 + Force active level - tim_oc3ref is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - In upcounting, channel 3 is active as long as TIMx_CNTless thanTIMx_CCR3 else inactive. + 0x6 + + + B_0x7 + PWM mode 2 - In upcounting, channel 3 is inactive as long as TIMx_CNTless thanTIMx_CCR3 else active. + 0x7 + + + + + OC3CE + Output compare 3 clear enable + 7 + 1 + read-write + + + CC4S + Capture/compare 4 selection + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. + 0x3 + + + + + OC4FE + Output compare 4 fast enable + 10 + 1 + read-write + + + OC4PE + Output compare 4 preload enable + 11 + 1 + read-write + + + OC4M + OC4M[2:0]: Output compare 4 mode + + 12 + 3 + read-write + + + OC4CE + Output compare 4 clear enable + 15 + 1 + read-write + + + OC3M_1 + OC3M[3] + 16 + 1 + read-write + + + OC4M_1 + OC4M[3] + 24 + 1 + read-write + + + + + TIM8_CCER + TIM8_CCER + TIM8 capture/compare enable register + 0x020 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1E + Capture/compare 1 output enable + + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active (see below) + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/compare 1 output polarity + + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NE + Capture/compare 1 complementary output enable + + 2 + 1 + read-write + + + B_0x0 + Off - tim_oc1n is not active. + 0x0 + + + B_0x1 + On - tim_oc1n signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. + 0x1 + + + + + CC1NP + Capture/compare 1 complementary output polarity + + 3 + 1 + read-write + + + B_0x0 + tim_oc1n active high. + 0x0 + + + B_0x1 + tim_oc1n active low. + 0x1 + + + + + CC2E + Capture/compare 2 output enable + + 4 + 1 + read-write + + + CC2P + Capture/compare 2 output polarity + + 5 + 1 + read-write + + + CC2NE + Capture/compare 2 complementary output enable + + 6 + 1 + read-write + + + CC2NP + Capture/compare 2 complementary output polarity + + 7 + 1 + read-write + + + CC3E + Capture/compare 3 output enable + + 8 + 1 + read-write + + + CC3P + Capture/compare 3 output polarity + + 9 + 1 + read-write + + + CC3NE + Capture/compare 3 complementary output enable + + 10 + 1 + read-write + + + CC3NP + Capture/compare 3 complementary output polarity + + 11 + 1 + read-write + + + CC4E + Capture/compare 4 output enable + + 12 + 1 + read-write + + + CC4P + Capture/compare 4 output polarity + + 13 + 1 + read-write + + + CC4NE + Capture/compare 4 complementary output enable + + 14 + 1 + read-write + + + CC4NP + Capture/compare 4 complementary output polarity + + 15 + 1 + read-write + + + CC5E + Capture/compare 5 output enable + + 16 + 1 + read-write + + + CC5P + Capture/compare 5 output polarity + + 17 + 1 + read-write + + + CC6E + Capture/compare 6 output enable + + 20 + 1 + read-write + + + CC6P + Capture/compare 6 output polarity + + 21 + 1 + read-write + + + + + TIM8_CNT + TIM8_CNT + TIM8 counter + 0x024 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + + 0 + 16 + read-write + + + UIFCPY + UIF copy + + 31 + 1 + read-only + + + + + TIM8_PSC + TIM8_PSC + TIM8 prescaler + 0x028 + 16 + read-write + 0x0000 + 0xFFFF + + + PSC + Prescaler value + + 0 + 16 + read-write + + + + + TIM8_ARR + TIM8_ARR + TIM8 auto-reload register + 0x02C + 0x20 + read-write + 0x0000FFFF + 0xFFFFFFFF + + + ARR + Auto-reload value + + 0 + 20 + read-write + + + + + TIM8_RCR + TIM8_RCR + TIM8 repetition counter register + 0x030 + 16 + read-write + 0x0000 + 0xFFFF + + + REP + Repetition counter reload value + + 0 + 16 + read-write + + + + + TIM8_CCR1 + TIM8_CCR1 + TIM8 capture/compare register 1 + 0x034 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR1 + Capture/compare 1 value + + 0 + 20 + read-write + + + + + TIM8_CCR2 + TIM8_CCR2 + TIM8 capture/compare register 2 + 0x038 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR2 + Capture/compare 2 value + + 0 + 20 + read-write + + + + + TIM8_CCR3 + TIM8_CCR3 + TIM8 capture/compare register 3 + 0x03C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR3 + Capture/compare value + + 0 + 20 + read-write + + + + + TIM8_CCR4 + TIM8_CCR4 + TIM8 capture/compare register 4 + 0x040 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR4 + Capture/compare value + + 0 + 20 + read-write + + + + + TIM8_BDTR + TIM8_BDTR + TIM8 break and dead-time register + 0x044 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DTG + Dead-time generator setup + + 0 + 8 + read-write + + + LOCK + Lock configuration + + 8 + 2 + read-write + + + B_0x0 + LOCK OFF - No bit is write protected. + 0x0 + + + B_0x1 + LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BK2BID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written. + 0x1 + + + B_0x2 + LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. + 0x2 + + + B_0x3 + LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. + 0x3 + + + + + OSSI + Off-state selection for idle mode + + 10 + 1 + read-write + + + B_0x0 + When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic and which imposes a Hi-Z state). + 0x0 + + + B_0x1 + When inactive, OC/OCN outputs are first forced with their inactive level then forced to their idle level after the deadtime. + 0x1 + + + + + OSSR + Off-state selection for Run mode + + 11 + 1 + read-write + + + B_0x0 + When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic, which forces a Hi-Z state). + 0x0 + + + B_0x1 + When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer). + 0x1 + + + + + BKE + Break enable + + 12 + 1 + read-write + + + B_0x0 + Break function disabled + 0x0 + + + B_0x1 + Break function enabled + 0x1 + + + + + BKP + Break polarity + + 13 + 1 + read-write + + + B_0x0 + Break input tim_brk is active low + 0x0 + + + B_0x1 + Break input tim_brk is active high + 0x1 + + + + + AOE + Automatic output enable + + 14 + 1 + read-write + + + B_0x0 + MOE can be set only by software + 0x0 + + + B_0x1 + MOE can be set by software or automatically at the next update event (if none of the break inputs tim_brk and tim_brk2 is active) + 0x1 + + + + + MOE + Main output enable + + 15 + 1 + read-write + + + B_0x0 + In response to a break 2 event. + 0x0 + + + B_0x1 + OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register). + 0x1 + + + + + BKF + Break filter + + 16 + 4 + read-write + + + B_0x0 + No filter, tim_brk acts asynchronously + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + BK2F + Break 2 filter + + 20 + 4 + read-write + + + B_0x0 + No filter, tim_brk2 acts asynchronously + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + BK2E + Break 2 enable + + 24 + 1 + read-write + + + B_0x0 + Break2 function disabled + 0x0 + + + B_0x1 + Break2 function enabled + 0x1 + + + + + BK2P + Break 2 polarity + + 25 + 1 + read-write + + + B_0x0 + Break input tim_brk2 is active low + 0x0 + + + B_0x1 + Break input tim_brk2 is active high + 0x1 + + + + + BKDSRM + Break disarm + + 26 + 1 + read-write + + + B_0x0 + Break input tim_brk is armed + 0x0 + + + B_0x1 + Break input tim_brk is disarmed + 0x1 + + + + + BK2DSRM + Break2 disarm + + 27 + 1 + read-write + + + BKBID + Break bidirectional + + 28 + 1 + read-write + + + B_0x0 + Break input tim_brk in input mode + 0x0 + + + B_0x1 + Break input tim_brk in bidirectional mode + 0x1 + + + + + BK2BID + Break2 bidirectional + + 29 + 1 + read-write + + + + + TIM8_CCR5 + TIM8_CCR5 + TIM8 capture/compare register 5 + 0x048 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR5 + Capture/compare 5 value + + 0 + 20 + read-write + + + GC5C1 + Group channel 5 and channel 1 + + 29 + 1 + read-write + + + B_0x0 + No effect of oc5ref on oc1refc + 0x0 + + + B_0x1 + oc1refc is the logical AND of oc1ref and oc5ref + 0x1 + + + + + GC5C2 + Group channel 5 and channel 2 + + 30 + 1 + read-write + + + B_0x0 + No effect of tim_oc5ref on tim_oc2refc + 0x0 + + + B_0x1 + tim_oc2refc is the logical AND of tim_oc2ref and tim_oc5ref + 0x1 + + + + + GC5C3 + Group channel 5 and channel 3 + + 31 + 1 + read-write + + + B_0x0 + No effect of tim_oc5ref on tim_oc3refc + 0x0 + + + B_0x1 + tim_oc3refc is the logical AND of tim_oc3ref and tim_oc5ref + 0x1 + + + + + + + TIM8_CCR6 + TIM8_CCR6 + TIM8 capture/compare register 6 + 0x04C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR6 + Capture/compare 6 value + + 0 + 20 + read-write + + + + + TIM8_CCMR3 + TIM8_CCMR3 + TIM8 capture/compare mode register 3 + 0x050 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OC5FE + Output compare 5 fast enable + 2 + 1 + read-write + + + OC5PE + Output compare 5 preload enable + 3 + 1 + read-write + + + OC5M + OC5M[2:0]: Output compare 5 mode + 4 + 3 + read-write + + + OC5CE + Output compare 5 clear enable + 7 + 1 + read-write + + + OC6FE + Output compare 6 fast enable + 10 + 1 + read-write + + + OC6PE + Output compare 6 preload enable + 11 + 1 + read-write + + + OC6M + OC6M[2:0]: Output compare 6 mode + 12 + 3 + read-write + + + OC6CE + Output compare 6 clear enable + 15 + 1 + read-write + + + OC5M_1 + OC5M[3] + 16 + 1 + read-write + + + OC6M_1 + OC6M[3] + 24 + 1 + read-write + + + + + TIM8_DTR2 + TIM8_DTR2 + TIM8 timer deadtime register 2 + 0x054 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DTGF + Dead-time falling edge generator setup + + 0 + 8 + read-write + + + DTAE + Deadtime asymmetric enable + + 16 + 1 + read-write + + + B_0x0 + Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register + 0x0 + + + B_0x1 + Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits. + 0x1 + + + + + DTPE + Deadtime preload enable + + 17 + 1 + read-write + + + B_0x0 + Deadtime value is not preloaded + 0x0 + + + B_0x1 + Deadtime value preload is enabled + 0x1 + + + + + + + TIM8_ECR + TIM8_ECR + TIM8 timer encoder control register + 0x058 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IE + Index enable + + 0 + 1 + read-write + + + B_0x0 + Index disabled + 0x0 + + + B_0x1 + Index enabled + 0x1 + + + + + IDIR + Index direction + + 1 + 2 + read-write + + + B_0x0 + Index resets the counter whatever the direction + 0x0 + + + B_0x1 + Index resets the counter when up-counting only + 0x1 + + + B_0x2 + Index resets the counter when down-counting only + 0x2 + + + + + IBLK + Index blanking + + 3 + 2 + read-write + + + B_0x0 + Index always active + 0x0 + + + B_0x1 + Index disabled when tim_ti3 input is active, as per CC3P bitfield + 0x1 + + + B_0x2 + Index disabled when tim_ti4 input is active, as per CC4P bitfield + 0x2 + + + + + FIDX + First index + + 5 + 1 + read-write + + + B_0x0 + Index is always active + 0x0 + + + B_0x1 + the first Index only resets the counter + 0x1 + + + + + IPOS + Index positioning + + 6 + 2 + read-write + + + B_0x0 + Index resets the counter when AB = 00 + 0x0 + + + B_0x1 + Index resets the counter when AB = 01 + 0x1 + + + B_0x2 + Index resets the counter when AB = 10 + 0x2 + + + B_0x3 + Index resets the counter when AB = 11 + 0x3 + + + + + PW + Pulse width + + 16 + 8 + read-write + + + PWPRSC + Pulse width prescaler + + 24 + 3 + read-write + + + + + TIM8_TISEL + TIM8_TISEL + TIM8 timer input selection register + 0x05C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + Selects tim_ti1[15:0] input + + 0 + 4 + read-write + + + B_0x0 + tim_ti1_in0: TIMx_CH1 + 0x0 + + + B_0x1 + tim_ti1_in1 + 0x1 + + + B_0xF + tim_ti1_in15 + 0xF + + + + + TI2SEL + Selects tim_ti2[15:0] input + + 8 + 4 + read-write + + + B_0x0 + tim_ti2_in0: TIMx_CH2 + 0x0 + + + B_0x1 + tim_ti2_in1 + 0x1 + + + B_0xF + tim_ti2_in15 + 0xF + + + + + TI3SEL + Selects tim_ti3[15:0] input + + 16 + 4 + read-write + + + B_0x0 + tim_ti3_in0: TIMx_CH2 + 0x0 + + + B_0x1 + tim_ti3_in1 + 0x1 + + + B_0xF + tim_ti3_in15 + 0xF + + + + + TI4SEL + Selects tim_ti4[15:0] input + + 24 + 4 + read-write + + + B_0x0 + tim_ti4_in0: TIMx_CH4 + 0x0 + + + B_0x1 + tim_ti4_in1 + 0x1 + + + B_0xF + tim_ti4_in15 + 0xF + + + + + + + TIM8_AF1 + TIM8_AF1 + TIM8 alternate function option register 1 + 0x060 + 0x20 + read-write + 0x00000001 + 0xFFFFFFFF + + + BKINE + TIMx_BKIN input enable + + 0 + 1 + read-write + + + B_0x0 + TIMx_BKIN input disabled + 0x0 + + + B_0x1 + TIMx_BKIN input enabled + 0x1 + + + + + BKCMP1E + tim_brk_cmp1 enable + + 1 + 1 + read-write + + + B_0x0 + tim_brk_cmp1 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp1 input enabled + 0x1 + + + + + BKCMP2E + tim_brk_cmp2 enable + + 2 + 1 + read-write + + + B_0x0 + tim_brk_cmp2 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp2 input enabled + 0x1 + + + + + BKCMP3E + tim_brk_cmp3 enable + + 3 + 1 + read-write + + + B_0x0 + tim_brk_cmp3 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp3 input enabled + 0x1 + + + + + BKCMP4E + tim_brk_cmp4 enable + + 4 + 1 + read-write + + + B_0x0 + tim_brk_cmp4 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp4 input enabled + 0x1 + + + + + BKCMP5E + tim_brk_cmp5 enable + + 5 + 1 + read-write + + + B_0x0 + tim_brk_cmp5 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp5 input enabled + 0x1 + + + + + BKCMP6E + tim_brk_cmp6 enable + + 6 + 1 + read-write + + + B_0x0 + tim_brk_cmp6 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp6 input enabled + 0x1 + + + + + BKCMP7E + tim_brk_cmp7 enable + + 7 + 1 + read-write + + + B_0x0 + tim_brk_cmp7 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp7 input enabled + 0x1 + + + + + BKCMP8E + tim_brk_cmp8 enable + + 8 + 1 + read-write + + + B_0x0 + tim_brk_cmp8 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp8 input enabled + 0x1 + + + + + BKINP + TIMx_BKIN input polarity + + 9 + 1 + read-write + + + B_0x0 + TIMx_BKIN input polarity is not inverted (active low if BKP = 0, active high if BKP = 1) + 0x0 + + + B_0x1 + TIMx_BKIN input polarity is inverted (active high if BKP = 0, active low if BKP = 1) + 0x1 + + + + + BKCMP1P + tim_brk_cmp1 input polarity + + 10 + 1 + read-write + + + B_0x0 + tim_brk_cmp1 input polarity is not inverted (active low if BKP = 0, active high if BKP = 1) + 0x0 + + + B_0x1 + tim_brk_cmp1 input polarity is inverted (active high if BKP = 0, active low if BKP = 1) + 0x1 + + + + + BKCMP2P + tim_brk_cmp2 input polarity + + 11 + 1 + read-write + + + B_0x0 + tim_brk_cmp2 input polarity is not inverted (active low if BKP = 0, active high if BKP = 1) + 0x0 + + + B_0x1 + tim_brk_cmp2 input polarity is inverted (active high if BKP = 0, active low if BKP = 1) + 0x1 + + + + + BKCMP3P + tim_brk_cmp3 input polarity + + 12 + 1 + read-write + + + B_0x0 + tim_brk_cmp3 input polarity is not inverted (active low if BKP = 0, active high if BKP = 1) + 0x0 + + + B_0x1 + tim_brk_cmp3 input polarity is inverted (active high if BKP = 0, active low if BKP = 1) + 0x1 + + + + + BKCMP4P + tim_brk_cmp4 input polarity + + 13 + 1 + read-write + + + B_0x0 + tim_brk_cmp4 input polarity is not inverted (active low if BKP = 0, active high if BKP = 1) + 0x0 + + + B_0x1 + tim_brk_cmp4 input polarity is inverted (active high if BKP = 0, active low if BKP = 1) + 0x1 + + + + + ETRSEL + etr_in source selection + + 14 + 4 + read-write + + + B_0x0 + tim_etr0: TIMx_ETR input + 0x0 + + + B_0x1 + tim_etr1 + 0x1 + + + B_0xF + tim_etr15 + 0xF + + + + + + + TIM8_AF2 + TIM8_AF2 + TIM8 alternate function register 2 + 0x064 + 0x20 + read-write + 0x00000001 + 0xFFFFFFFF + + + BK2INE + TIMx_BKIN2 input enable + + 0 + 1 + read-write + + + B_0x0 + TIMx_BKIN2 input disabled + 0x0 + + + B_0x1 + TIMx_BKIN2 input enabled + 0x1 + + + + + BK2CMP1E + tim_brk2_cmp1 enable + + 1 + 1 + read-write + + + B_0x0 + tim_brk2_cmp1 input disabled + 0x0 + + + B_0x1 + tim_brk2_cmp1 input enabled + 0x1 + + + + + BK2CMP2E + tim_brk2_cmp2 enable + + 2 + 1 + read-write + + + B_0x0 + tim_brk2_cmp2 input disabled + 0x0 + + + B_0x1 + tim_brk2_cmp2 input enabled + 0x1 + + + + + BK2CMP3E + tim_brk2_cmp3 enable + + 3 + 1 + read-write + + + B_0x0 + tim_brk2_cmp3 input disabled + 0x0 + + + B_0x1 + tim_brk2_cmp3 input enabled + 0x1 + + + + + BK2CMP4E + tim_brk2_cmp4 enable + + 4 + 1 + read-write + + + B_0x0 + tim_brk2_cmp4 input disabled + 0x0 + + + B_0x1 + tim_brk2_cmp4 input enabled + 0x1 + + + + + BK2CMP5E + tim_brk2_cmp5 enable + + 5 + 1 + read-write + + + B_0x0 + tim_brk2_cmp5 input disabled + 0x0 + + + B_0x1 + tim_brk2_cmp5 input enabled + 0x1 + + + + + BK2CMP6E + tim_brk2_cmp6 enable + + 6 + 1 + read-write + + + B_0x0 + tim_brk2_cmp6 input disabled + 0x0 + + + B_0x1 + tim_brk2_cmp6 input enabled + 0x1 + + + + + BK2CMP7E + tim_brk2_cmp7 enable + + 7 + 1 + read-write + + + B_0x0 + tim_brk2_cmp7 input disabled + 0x0 + + + B_0x1 + tim_brk2_cmp7 input enabled + 0x1 + + + + + BK2CMP8E + tim_brk2_cmp8 enable + + 8 + 1 + read-write + + + B_0x0 + tim_brk2_cmp8 input disabled + 0x0 + + + B_0x1 + tim_brk2_cmp8 input enabled + 0x1 + + + + + BK2INP + TIMx_BKIN2 input polarity + + 9 + 1 + read-write + + + B_0x0 + TIMx_BKIN2 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1) + 0x0 + + + B_0x1 + TIMx_BKIN2 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1) + 0x1 + + + + + BK2CMP1P + tim_brk2_cmp1 input polarity + + 10 + 1 + read-write + + + B_0x0 + tim_brk2_cmp1 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1) + 0x0 + + + B_0x1 + tim_brk2_cmp1 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1) + 0x1 + + + + + BK2CMP2P + tim_brk2_cmp2 input polarity + + 11 + 1 + read-write + + + B_0x0 + tim_brk2_cmp2 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1) + 0x0 + + + B_0x1 + tim_brk2_cmp2 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1) + 0x1 + + + + + BK2CMP3P + tim_brk2_cmp3 input polarity + + 12 + 1 + read-write + + + B_0x0 + tim_brk2_cmp3 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1) + 0x0 + + + B_0x1 + tim_brk2_cmp3 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1) + 0x1 + + + + + BK2CMP4P + tim_brk2_cmp4 input polarity + + 13 + 1 + read-write + + + B_0x0 + tim_brk2_cmp4 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1) + 0x0 + + + B_0x1 + tim_brk2_cmp4 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1) + 0x1 + + + + + OCRSEL + ocref_clr source selection + + 16 + 3 + read-write + + + B_0x0 + tim_ocref_clr0 + 0x0 + + + B_0x1 + tim_ocref_clr1 + 0x1 + + + B_0x7 + tim_ocref_clr7 + 0x7 + + + + + + + TIM8_DCR + TIM8_DCR + TIM8 DMA control register + 0x3DC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DBA + DMA base address + + 0 + 5 + read-write + + + B_0x0 + TIMx_CR1 + 0x0 + + + B_0x1 + TIMx_CR2 + 0x1 + + + B_0x2 + TIMx_SMCR + 0x2 + + + + + DBL + DMA burst length + + 8 + 5 + read-write + + + B_0x0 + 1 transfer + 0x0 + + + B_0x1 + 2 transfers + 0x1 + + + B_0x2 + 3 transfers + 0x2 + + + B_0x1A + 26 transfers + 0x1A + + + + + DBSS + DMA burst source selection + + 16 + 4 + read-write + + + B_0x1 + Update + 0x1 + + + B_0x2 + CC1 + 0x2 + + + B_0x3 + CC2 + 0x3 + + + B_0x4 + CC3 + 0x4 + + + B_0x5 + CC4 + 0x5 + + + B_0x6 + COM + 0x6 + + + B_0x7 + Trigger + 0x7 + + + + + + + TIM8_DMAR + TIM8_DMAR + TIM8 DMA address for full transfer + 0x3E0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DMAB + DMA register for burst accesses + + 0 + 32 + read-write + + + + + + + TIM8_S + 0X50013400 + + + TIM15 + TIM15 address block description + TIM15 + 0x40014000 + + 0x0 + 0x3E4 + registers + + + TIM15 + TIM15 global interrupt + 71 + + + + TIM15_CR1 + TIM15_CR1 + TIM15 control register 1 + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + CEN + Counter enable + + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable + + 1 + 1 + read-write + + + B_0x0 + UEV enabled. + 0x0 + + + B_0x1 + UEV disabled. + 0x1 + + + + + URS + Update request source + + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt if enabled. + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt if enabled + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIM15_ARR register is not buffered + 0x0 + + + B_0x1 + TIM15_ARR register is buffered + 0x1 + + + + + CKD + Clock division + + 8 + 2 + read-write + + + B_0x0 + tless thansub>DTS less than/sub>= tless thansub>tim_ker_ckless than/sub> + 0x0 + + + B_0x1 + tless thansub>DTSless than/sub> = 2*tless thansub>tim_ker_ckless than/sub> + 0x1 + + + B_0x2 + tless thansub>DTSless than/sub> = 4*tless thansub>tim_ker_ckless than/sub> + 0x2 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. + 0x0 + + + B_0x1 + Remapping enabled. + 0x1 + + + + + DITHEN + Dithering enable + + 12 + 1 + read-write + + + B_0x0 + Dithering disabled + 0x0 + + + B_0x1 + Dithering enabled + 0x1 + + + + + + + TIM15_CR2 + TIM15_CR2 + TIM15 control register 2 + 0x04 + 16 + read-write + 0x0000 + 0xFFFF + + + CCPC + Capture/compare preloaded control + + 0 + 1 + read-write + + + B_0x0 + CCxE, CCxNE and OCxM bits are not preloaded + 0x0 + + + B_0x1 + CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on tim_trgi, depending on the CCUS bit). + 0x1 + + + + + CCUS + Capture/compare control update selection + + 2 + 1 + read-write + + + B_0x0 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only. + 0x0 + + + B_0x1 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on tim_trgi. + 0x1 + + + + + CCDS + Capture/compare DMA selection + 3 + 1 + read-write + + + B_0x0 + CCx DMA request sent when CCx event occurs + 0x0 + + + B_0x1 + CCx DMA requests sent when update event occurs + 0x1 + + + + + MMS + Master mode selection + + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIM15_EGR register is used as trigger output (tim_trgo). + 0x0 + + + B_0x1 + Enable - the Counter Enable signal CNT_EN is used as trigger output (tim_trgo). + 0x1 + + + B_0x2 + Update - The update event is selected as trigger output (tim_trgo). + 0x2 + + + B_0x3 + Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred (tim_trgo). + 0x3 + + + B_0x4 + Compare - tim_oc1refc signal is used as trigger output (tim_trgo). + 0x4 + + + B_0x5 + Compare - tim_oc2refc signal is used as trigger output (tim_trgo). + 0x5 + + + + + TI1S + tim_ti1 selection + 7 + 1 + read-write + + + B_0x0 + The tim_ti1_in[15:0] multiplexer output is connected to tim_ti1 input + 0x0 + + + B_0x1 + The tim_ti1_in[15:0] and tim_ti2_in[15:0] multiplexers output are connected to the tim_ti1 input (XOR combination) + 0x1 + + + + + OIS1 + Output Idle state 1 (tim_oc1 output) + + 8 + 1 + read-write + + + B_0x0 + tim_oc1=0 after a dead-time when MOE=0 + 0x0 + + + B_0x1 + tim_oc1=1 after a dead-time when MOE=0 + 0x1 + + + + + OIS1N + Output Idle state 1 (tim_oc1n output) + + 9 + 1 + read-write + + + B_0x0 + tim_oc1n=0 after a dead-time when MOE=0 + 0x0 + + + B_0x1 + tim_oc1n=1 after a dead-time when MOE=0 + 0x1 + + + + + OIS2 + Output idle state 2 (tim_oc2 output) + + 10 + 1 + read-write + + + B_0x0 + tim_oc2=0 when MOE=0 + 0x0 + + + B_0x1 + tim_oc2=1 when MOE=0 + 0x1 + + + + + + + TIM15_SMCR + TIM15_SMCR + TIM15 slave mode control register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SMS + SMS[2:0]: Slave mode selection + + 0 + 3 + read-write + + + B_0x0 + Slave mode disabled - if CEN = 1' then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x4 + Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers. + 0x4 + + + B_0x5 + Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high. + 0x5 + + + B_0x6 + Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). + 0x6 + + + B_0x7 + External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter. + 0x7 + + + + + TS + TS[2:0]: Trigger selection + + 4 + 3 + read-write + + + B_0x0 + Internal Trigger 0 (tim_itr0) + 0x0 + + + B_0x1 + Internal Trigger 1 (tim_itr1) + 0x1 + + + B_0x2 + Internal Trigger 2 (tim_itr2) + 0x2 + + + B_0x3 + Internal Trigger 3 (tim_itr3) + 0x3 + + + B_0x4 + tim_ti1 Edge Detector (tim_ti1f_ed) + 0x4 + + + B_0x5 + Filtered Timer Input 1 (tim_ti1fp1) + 0x5 + + + B_0x6 + Filtered Timer Input 2 (tim_ti2fp2) + 0x6 + + + + + MSM + Master/slave mode + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). + 0x1 + + + + + SMS_1 + Slave mode selection +When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (see Input Control register and Control Register description. +Note: The gated mode must not be used if tim_ti1f_ed is selected as the trigger input (TS=00100). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on tim_ti1f, whereas the gated mode checks the level of the trigger signal. +Note: The clock of the slave peripherals (timer, ADC, ...) receiving the tim_trgo signal must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. + 16 + 1 + read-write + + + B_0x0 + Slave mode disabled - if CEN = '1 then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level. + 0x1 + + + + + TS_1 + Trigger selection +This bit-field selects the trigger input to be used to synchronize the counter. +Others: Reserved +See for product specific implementation details. +Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. + 20 + 2 + read-write + + + B_0x0 + Internal trigger 0 (tim_itr0) + 0x0 + + + B_0x1 + Internal trigger 1 (tim_itr1) + 0x1 + + + B_0x2 + Internal trigger 2 (tim_itr2) + 0x2 + + + B_0x3 + Internal trigger 3 (tim_itr3) + 0x3 + + + + + SMSPE + SMS preload enable + + 24 + 1 + read-write + + + B_0x0 + SMS[3:0] bitfield is not preloaded + 0x0 + + + B_0x1 + SMS[3:0] preload is enabled + 0x1 + + + + + + + TIM15_DIER + TIM15_DIER + TIM15 DMA/interrupt enable register + 0x0C + 16 + read-write + 0x0000 + 0xFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled + 0x0 + + + B_0x1 + Update interrupt enabled + 0x1 + + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled + 0x0 + + + B_0x1 + CC1 interrupt enabled + 0x1 + + + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + read-write + + + B_0x0 + CC2 interrupt disabled + 0x0 + + + B_0x1 + CC2 interrupt enabled + 0x1 + + + + + COMIE + COM interrupt enable + 5 + 1 + read-write + + + B_0x0 + COM interrupt disabled + 0x0 + + + B_0x1 + COM interrupt enabled + 0x1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + read-write + + + B_0x0 + Trigger interrupt disabled + 0x0 + + + B_0x1 + Trigger interrupt enabled + 0x1 + + + + + BIE + Break interrupt enable + 7 + 1 + read-write + + + B_0x0 + Break interrupt disabled + 0x0 + + + B_0x1 + Break interrupt enabled + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled + 0x0 + + + B_0x1 + Update DMA request enabled + 0x1 + + + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled + 0x0 + + + B_0x1 + CC1 DMA request enabled + 0x1 + + + + + COMDE + COM DMA request enable + 13 + 1 + read-write + + + B_0x0 + COM DMA request disabled + 0x0 + + + B_0x1 + COM DMA request enabled + 0x1 + + + + + TDE + Trigger DMA request enable + 14 + 1 + read-write + + + B_0x0 + Trigger DMA request disabled + 0x0 + + + B_0x1 + Trigger DMA request enabled + 0x1 + + + + + + + TIM15_SR + TIM15_SR + TIM15 status register + 0x10 + 16 + read-write + 0x0000 + 0xFFFF + + + UIF + Update interrupt flag + + 0 + 1 + read-write + + + B_0x0 + No update occurred. + 0x0 + + + B_0x1 + Update interrupt pending. + 0x1 + + + + + CC1IF + Capture/Compare 1 interrupt flag + + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred + 0x1 + + + + + CC2IF + Capture/Compare 2 interrupt flag + + 2 + 1 + read-write + + + COMIF + COM interrupt flag + + 5 + 1 + read-write + + + B_0x0 + No COM event occurred + 0x0 + + + B_0x1 + COM interrupt pending + 0x1 + + + + + TIF + Trigger interrupt flag + + 6 + 1 + read-write + + + B_0x0 + No trigger event occurred + 0x0 + + + B_0x1 + Trigger interrupt pending + 0x1 + + + + + BIF + Break interrupt flag + + 7 + 1 + read-write + + + B_0x0 + No break event occurred + 0x0 + + + B_0x1 + An active level has been detected on the break input + 0x1 + + + + + CC1OF + Capture/Compare 1 overcapture flag + + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected + 0x0 + + + B_0x1 + The counter value has been captured in TIM15_CCR1 register while CC1IF flag was already set + 0x1 + + + + + CC2OF + Capture/Compare 2 overcapture flag + + 10 + 1 + read-write + + + + + TIM15_EGR + TIM15_EGR + TIM15 event generation register + 0x14 + 16 + read-write + 0x0000 + 0xFFFF + + + UG + Update generation + + 0 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Reinitialize the counter and generates an update of the registers. + 0x1 + + + + + CC1G + Capture/Compare 1 generation + + 1 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + + + CC2G + Capture/Compare 2 generation + + 2 + 1 + write-only + + + COMG + Capture/Compare control update generation + + 5 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits + 0x1 + + + + + TG + Trigger generation + + 6 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + The TIF flag is set in TIM15_SR register. + 0x1 + + + + + BG + Break generation + + 7 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A break event is generated. + 0x1 + + + + + + + TIM15_CCMR1 + TIM15_CCMR1 + TIM15 capture/compare mode register 1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. + 0x3 + + + + + IC1PSC + Input capture 1 prescaler + + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter + + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + CC2S + Capture/Compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. + 0x3 + + + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + read-write + + + IC2F + Input capture 2 filter + 12 + 4 + read-write + + + + + TIM15_CCMR1_ALTERNATE1 + TIM15_CCMR1_ALTERNATE1 + TIM15 capture/compare mode register 1 + TIM15_CCMR1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output. + 0x0 + + + B_0x1 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1. + 0x1 + + + B_0x2 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2. + 0x2 + + + B_0x3 + CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. + 0x3 + + + + + OC1FE + Output Compare 1 fast enable + + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. + 0x1 + + + + + OC1PE + Output Compare 1 preload enable + + 3 + 1 + read-write + + + B_0x0 + Preload register on TIM15_CCR1 disabled. + 0x0 + + + B_0x1 + Preload register on TIM15_CCR1 enabled. + 0x1 + + + + + OC1M + OC1M[2:0]: Output compare 1 mode + + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIM15_CCR1 and the counter TIM15_CNT has no effect on the outputs. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. + 0x2 + + + B_0x3 + Toggle - tim_oc1ref toggles when TIM15_CNT=TIM15_CCR1. + 0x3 + + + B_0x4 + Force inactive level - tim_oc1ref is forced low. + 0x4 + + + B_0x5 + Force active level - tim_oc1ref is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - Channel 1 is active as long as TIM15_CNTless thanTIM15_CCR1 else inactive. + 0x6 + + + B_0x7 + PWM mode 2 - Channel 1 is inactive as long as TIM15_CNTless thanTIM15_CCR1 else active. + 0x7 + + + + + OC1CE + Output compare 1 clear enable + 7 + 1 + read-write + + + B_0x0 + tim_oc1ref is not affected by the tim_ocref_clr_int input. + 0x0 + + + B_0x1 + tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr_int input. + 0x1 + + + + + CC2S + Capture/Compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output. + 0x0 + + + B_0x1 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2. + 0x1 + + + B_0x2 + C2 channel is configured as input, tim_ic2 is mapped on tim_ti1. + 0x2 + + + B_0x3 + CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. + 0x3 + + + + + OC2FE + Output compare 2 fast enable + 10 + 1 + read-write + + + OC2PE + Output compare 2 preload enable + 11 + 1 + read-write + + + OC2M + OC2M[2:0]: Output compare 2 mode + 12 + 3 + read-write + + + OC2CE + Output compare 2 clear enable + 15 + 1 + read-write + + + OC1M_1 + OC1M[3] + 16 + 1 + read-write + + + OC2M_1 + OC2M[3] + 24 + 1 + read-write + + + + + TIM15_CCER + TIM15_CCER + TIM15 capture/compare enable register + 0x20 + 16 + read-write + 0x0000 + 0xFFFF + + + CC1E + Capture/Compare 1 output enable + + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active (see below) + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/Compare 1 output polarity + + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NE + Capture/Compare 1 complementary output enable + 2 + 1 + read-write + + + B_0x0 + Off - tim_oc1n is not active. + 0x0 + + + B_0x1 + On - tim_oc1n signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. + 0x1 + + + + + CC1NP + Capture/Compare 1 complementary output polarity + + 3 + 1 + read-write + + + B_0x0 + tim_oc1n active high + 0x0 + + + B_0x1 + tim_oc1n active low + 0x1 + + + + + CC2E + Capture/Compare 2 output enable + + 4 + 1 + read-write + + + CC2P + Capture/Compare 2 output polarity + + 5 + 1 + read-write + + + CC2NP + Capture/Compare 2 complementary output polarity + + 7 + 1 + read-write + + + + + TIM15_CNT + TIM15_CNT + TIM15 counter + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + + 0 + 16 + read-write + + + UIFCPY + UIF Copy + + 31 + 1 + read-only + + + + + TIM15_PSC + TIM15_PSC + TIM15 prescaler + 0x28 + 16 + read-write + 0x0000 + 0xFFFF + + + PSC + Prescaler value + + 0 + 16 + read-write + + + + + TIM15_ARR + TIM15_ARR + TIM15 auto-reload register + 0x2C + 0x20 + read-write + 0x0000FFFF + 0xFFFFFFFF + + + ARR + Auto-reload value + + 0 + 20 + read-write + + + + + TIM15_RCR + TIM15_RCR + TIM15 repetition counter register + 0x30 + 16 + read-write + 0x0000 + 0xFFFF + + + REP + Repetition counter reload value + + 0 + 8 + read-write + + + + + TIM15_CCR1 + TIM15_CCR1 + TIM15 capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR1 + Capture/compare 1 value + + 0 + 20 + read-write + + + + + TIM15_CCR2 + TIM15_CCR2 + TIM15 capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR2 + Capture/compare 2 value + + 0 + 20 + read-write + + + + + TIM15_BDTR + TIM15_BDTR + TIM15 break and dead-time register + 0x44 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DTG + Dead-time generator setup + + 0 + 8 + read-write + + + LOCK + Lock configuration + + 8 + 2 + read-write + + + B_0x0 + LOCK OFF - No bit is write protected + 0x0 + + + B_0x1 + LOCK Level 1 = DTG bits in TIM15_BDTR register, OISx and OISxN bits in TIM15_CR2 register and BKBID/BKE/BKP/AOE bits in TIM15_BDTR register can no longer be written + 0x1 + + + B_0x2 + LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIM15_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. + 0x2 + + + B_0x3 + OCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIM15_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. + 0x3 + + + + + OSSI + Off-state selection for Idle mode + + 10 + 1 + read-write + + + B_0x0 + When inactive, tim_ocx/tim_ocxn outputs are disabled (tim_ocx/tim_ocxn enable output signal=0) + 0x0 + + + B_0x1 + When inactive, tim_ocx/tim_ocxn outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. + 0x1 + + + + + OSSR + Off-state selection for Run mode + + 11 + 1 + read-write + + + B_0x0 + When inactive, tim_ocx/tim_ocxn outputs are disabled (the timer releases the output control which is taken over by the GPIO, which forces a Hi-Z state) + 0x0 + + + B_0x1 + When inactive, tim_ocx/tim_ocxn outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer). + 0x1 + + + + + BKE + Break enable + + 12 + 1 + read-write + + + B_0x0 + Break inputs (tim_brk and tim_sys_brk clock failure event) disabled + 0x0 + + + + + BKP + Break polarity + + 13 + 1 + read-write + + + B_0x0 + Break input tim_brk is active low + 0x0 + + + B_0x1 + Break input tim_brk is active high + 0x1 + + + + + AOE + Automatic output enable + + 14 + 1 + read-write + + + B_0x0 + MOE can be set only by software + 0x0 + + + B_0x1 + MOE can be set by software or automatically at the next update event (if the break input is not be active) + 0x1 + + + + + MOE + Main output enable + + 15 + 1 + read-write + + + B_0x0 + tim_ocx and tim_ocxn outputs are disabled or forced to idle state depending on the OSSI bit. + 0x0 + + + B_0x1 + tim_ocx and tim_ocxn outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIM15_CCER register) + 0x1 + + + + + BKF + Break filter + + 16 + 4 + read-write + + + B_0x0 + No filter, tim_brk acts asynchronously + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + BKDSRM + Break disarm + + 26 + 1 + read-write + + + B_0x0 + Break input tim_brk is armed + 0x0 + + + B_0x1 + Break input tim_brk is disarmed + 0x1 + + + + + BKBID + Break bidirectional + + 28 + 1 + read-write + + + B_0x0 + Break input tim_brk in input mode + 0x0 + + + B_0x1 + Break input tim_brk in bidirectional mode + 0x1 + + + + + + + TIM15_DTR2 + TIM15_DTR2 + TIM15 timer deadtime register 2 + 0x054 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DTGF + Dead-time falling edge generator setup + + 0 + 8 + read-write + + + DTAE + Deadtime asymmetric enable + + 16 + 1 + read-write + + + B_0x0 + Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register + 0x0 + + + B_0x1 + Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits. + 0x1 + + + + + DTPE + Deadtime preload enable + + 17 + 1 + read-write + + + B_0x0 + Deadtime value is not preloaded + 0x0 + + + B_0x1 + Deadtime value preload is enabled + 0x1 + + + + + + + TIM15_TISEL + TIM15_TISEL + TIM15 input selection register + 0x5C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + selects tim_ti1_in[15:0] input + + 0 + 4 + read-write + + + B_0x0 + TIM15_CH1 input (tim_ti1_in0) + 0x0 + + + B_0x1 + tim_ti1_in1 + 0x1 + + + B_0xF + tim_ti1_in15 + 0xF + + + + + TI2SEL + selects tim_ti2_in[15:0] input + + 8 + 4 + read-write + + + B_0x0 + TIM15_CH2 input (tim_ti2_in0) + 0x0 + + + B_0x1 + tim_ti2_in1 + 0x1 + + + B_0xF + tim_ti2_in15 + 0xF + + + + + + + TIM15_AF1 + TIM15_AF1 + TIM15 alternate function register 1 + 0x060 + 0x20 + read-write + 0x00000001 + 0xFFFFFFFF + + + BKINE + TIMx_BKIN input enable + + 0 + 1 + read-write + + + B_0x0 + TIMx_BKIN input disabled + 0x0 + + + B_0x1 + TIMx_BKIN input enabled + 0x1 + + + + + BKCMP1E + tim_brk_cmp1 enable + + 1 + 1 + read-write + + + B_0x0 + tim_brk_cmp1 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp1 input enabled + 0x1 + + + + + BKCMP2E + tim_brk_cmp2 enable + + 2 + 1 + read-write + + + B_0x0 + tim_brk_cmp2 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp2 input enabled + 0x1 + + + + + BKCMP3E + tim_brk_cmp3 enable + + 3 + 1 + read-write + + + B_0x0 + tim_brk_cmp3 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp3 input enabled + 0x1 + + + + + BKCMP4E + tim_brk_cmp4 enable + + 4 + 1 + read-write + + + B_0x0 + tim_brk_cmp4 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp4 input enabled + 0x1 + + + + + BKCMP5E + tim_brk_cmp5 enable + + 5 + 1 + read-write + + + B_0x0 + tim_brk_cmp5 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp5 input enabled + 0x1 + + + + + BKCMP6E + tim_brk_cmp6 enable + + 6 + 1 + read-write + + + B_0x0 + tim_brk_cmp6 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp6 input enabled + 0x1 + + + + + BKCMP7E + tim_brk_cmp7 enable + + 7 + 1 + read-write + + + B_0x0 + tim_brk_cmp7 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp7 input enabled + 0x1 + + + + + BKCMP8E + tim_brk_cmp8 enable + + 8 + 1 + read-write + + + B_0x0 + tim_brk_cmp8 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp8 input enabled + 0x1 + + + + + BKINP + TIMx_BKIN input polarity + + 9 + 1 + read-write + + + B_0x0 + TIMx_BKIN input is active high + 0x0 + + + B_0x1 + TIMx_BKIN input is active low + 0x1 + + + + + BKCMP1P + tim_brk_cmp1 input polarity + + 10 + 1 + read-write + + + B_0x0 + tim_brk_cmp1 input is active high + 0x0 + + + B_0x1 + tim_brk_cmp1 input is active low + 0x1 + + + + + BKCMP2P + tim_brk_cmp2 input polarity + + 11 + 1 + read-write + + + B_0x0 + tim_brk_cmp2 input is active high + 0x0 + + + B_0x1 + tim_brk_cmp2 input is active low + 0x1 + + + + + BKCMP3P + tim_brk_cmp3 input polarity + + 12 + 1 + read-write + + + B_0x0 + tim_brk_cmp3 input is active high + 0x0 + + + B_0x1 + tim_brk_cmp3 input is active low + 0x1 + + + + + BKCMP4P + tim_brk_cmp4 input polarity + + 13 + 1 + read-write + + + B_0x0 + tim_brk_cmp4 input is active high + 0x0 + + + B_0x1 + tim_brk_cmp4 input is active low + 0x1 + + + + + + + TIM15_AF2 + TIM15_AF2 + TIM15 alternate function register 2 + 0x064 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OCRSEL + ocref_clr source selection + + 16 + 3 + read-write + + + B_0x0 + tim_ocref_clr0 + 0x0 + + + B_0x1 + tim_ocref_clr1 + 0x1 + + + B_0x2 + tim_ocref_clr2 + 0x2 + + + B_0x3 + tim_ocref_clr3 + 0x3 + + + B_0x4 + tim_ocref_clr4 + 0x4 + + + B_0x5 + tim_ocref_clr5 + 0x5 + + + B_0x6 + tim_ocref_clr6 + 0x6 + + + B_0x7 + tim_ocref_clr7 + 0x7 + + + + + + + TIM15_DCR + TIM15_DCR + TIM15 DMA control register + 0x3DC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DBA + DMA base address + + 0 + 5 + read-write + + + B_0x0 + TIM15_CR1, + 0x0 + + + B_0x1 + TIM15_CR2, + 0x1 + + + B_0x2 + TIM15_SMCR, + 0x2 + + + + + DBL + DMA burst length + + 8 + 5 + read-write + + + B_0x0 + 1 transfer, + 0x0 + + + B_0x1 + 2 transfers, + 0x1 + + + B_0x2 + 3 transfers, + 0x2 + + + B_0x11 + 18 transfers. + 0x11 + + + + + DBSS + DMA burst source selection + + 16 + 4 + read-write + + + B_0x1 + Update + 0x1 + + + B_0x2 + CC1 + 0x2 + + + B_0x6 + COM + 0x6 + + + B_0x7 + Trigger + 0x7 + + + + + + + TIM15_DMAR + TIM15_DMAR + TIM15 DMA address for full transfer + 0x3E0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DMAB + DMA register for burst accesses + + 0 + 32 + read-write + + + + + + + TIM15_S + 0X50014000 + + + UCPD + UCPD register block + UCPD + 0x4000dc00 + + 0x0 + 0x400 + registers + + + UCPD1 + UCPD1 global interrupt + 76 + + + + UCPD_CFGR1 + UCPD_CFGR1 + UCPD configuration register 1 + 0x000 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + HBITCLKDIV + Division ratio for producing half-bit clock + + 0 + 6 + read-write + + + B_0x00 + 1 (bypass) + 0x00 + + + B_0x1A + 27 + 0x1A + + + B_0x3F + 64 + 0x3F + + + + + IFRGAP + Division ratio for producing inter-frame gap timer clock + + 6 + 5 + read-write + + + B_0x00 + Not supported + 0x00 + + + B_0x01 + 2 + 0x01 + + + B_0x0D + 14 + 0x0D + + + B_0x0E + 15 + 0x0E + + + B_0x0F + 16 + 0x0F + + + B_0x1F + 32 + 0x1F + + + + + TRANSWIN + Transition window duration + + 11 + 5 + read-write + + + B_0x00 + Not supported + 0x00 + + + B_0x01 + 2 + 0x01 + + + B_0x09 + 10 (recommended) + 0x09 + + + B_0x1F + 32 + 0x1F + + + + + PSC_USBPDCLK + Pre-scaler division ratio for generating ucpd_clk + + 17 + 3 + read-write + + + B_0x0 + 1 (bypass) + 0x0 + + + B_0x1 + 2 + 0x1 + + + B_0x2 + 4 + 0x2 + + + B_0x3 + 8 + 0x3 + + + B_0x4 + 16 + 0x4 + + + + + RXORDSETEN + Receiver ordered set enable + + 20 + 9 + read-write + + + TXDMAEN + Transmission DMA mode enable + + 29 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RXDMAEN + Reception DMA mode enable + + 30 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + UCPDEN + UCPD peripheral enable + + 31 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + UCPD_CFGR2 + UCPD_CFGR2 + UCPD configuration register 2 + 0x004 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RXFILTDIS + BMC decoder Rx pre-filter enable + + 0 + 1 + read-write + + + B_0x0 + Enable + 0x0 + + + B_0x1 + Disable + 0x1 + + + + + RXFILT2N3 + BMC decoder Rx pre-filter sampling method + + 1 + 1 + read-write + + + B_0x0 + 3 samples + 0x0 + + + B_0x1 + 2 samples + 0x1 + + + + + FORCECLK + Force ClkReq clock request + 2 + 1 + read-write + + + B_0x0 + Do not force clock request + 0x0 + + + B_0x1 + Force clock request + 0x1 + + + + + WUPEN + Wake-up from Stop mode enable + + 3 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RXAFILTEN + Rx analog filter enable + + 8 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + UCPD_CFGR3 + UCPD_CFGR3 + UCPD configuration register 3 + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TRIM_CC1_RD + SW trim value for Rd resistor on the CC1 line + 0 + 4 + read-write + + + TRIM_CC1_RP + SW trim value for Rp current sources on the CC1 line + 9 + 4 + read-write + + + TRIM_CC2_RD + SW trim value for Rd resistor on the CC2 line + 16 + 4 + read-write + + + TRIM_CC2_RP + SW trim value for Rp current sources on the CC2 line + 25 + 4 + read-write + + + + + UCPD_CR + UCPD_CR + UCPD control register + 0x00C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TXMODE + Type of Tx packet + + 0 + 2 + read-write + + + B_0x0 + Transmission of Tx packet previously defined in other registers + 0x0 + + + B_0x1 + Cable Reset sequence + 0x1 + + + B_0x2 + BIST test sequence (BIST Carrier Mode 2) + 0x2 + + + + + TXSEND + Command to send a Tx packet + + 2 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Start Tx packet transmission + 0x1 + + + + + TXHRST + Command to send a Tx Hard Reset + + 3 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Start Tx Hard Reset message + 0x1 + + + + + RXMODE + Receiver mode + + 4 + 1 + read-write + + + B_0x0 + Normal receive mode + 0x0 + + + B_0x1 + BIST receive mode (BIST test data mode) + 0x1 + + + + + PHYRXEN + USB Power Delivery receiver enable + + 5 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + PHYCCSEL + CC1/CC2 line selector for USB Power Delivery signaling + + 6 + 1 + read-write + + + B_0x0 + Use CC1 IO for Power Delivery communication + 0x0 + + + B_0x1 + Use CC2 IO for Power Delivery communication + 0x1 + + + + + ANASUBMODE + Analog PHY sub-mode + + 7 + 2 + read-write + + + ANAMODE + Analog PHY operating mode + + 9 + 1 + read-write + + + B_0x0 + Source + 0x0 + + + B_0x1 + Sink + 0x1 + + + + + CCENABLE + CC line enable + + 10 + 2 + read-write + + + B_0x0 + Disable both PHYs + 0x0 + + + B_0x1 + Enable CC1 PHY + 0x1 + + + B_0x2 + Enable CC2 PHY + 0x2 + + + B_0x3 + Enable CC1 and CC2 PHY + 0x3 + + + + + FRSRXEN + FRS event detection enable + + 16 + 1 + read-write + + + B_0x1 + Enable + 0x1 + + + + + FRSTX + FRS Tx signaling enable. + 17 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RDCH + Rdch condition drive + + 18 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rdch condition drive + 0x1 + + + + + CC1TCDIS + CC1 Type-C detector disable + + 20 + 1 + read-write + + + B_0x0 + Enable + 0x0 + + + B_0x1 + Disable + 0x1 + + + + + CC2TCDIS + CC2 Type-C detector disable + + 21 + 1 + read-write + + + B_0x0 + Enable + 0x0 + + + B_0x1 + Disable + 0x1 + + + + + + + UCPD_IMR + UCPD_IMR + UCPD interrupt mask register + 0x010 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TXISIE + TXIS interrupt enable + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TXMSGDISCIE + TXMSGDISC interrupt enable + 1 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TXMSGSENTIE + TXMSGSENT interrupt enable + 2 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TXMSGABTIE + TXMSGABT interrupt enable + 3 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + HRSTDISCIE + HRSTDISC interrupt enable + 4 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + HRSTSENTIE + HRSTSENT interrupt enable + 5 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TXUNDIE + TXUND interrupt enable + 6 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RXNEIE + RXNE interrupt enable + 8 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RXORDDETIE + RXORDDET interrupt enable + 9 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RXHRSTDETIE + RXHRSTDET interrupt enable + 10 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RXOVRIE + RXOVR interrupt enable + 11 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RXMSGENDIE + RXMSGEND interrupt enable + 12 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TYPECEVT1IE + TYPECEVT1 interrupt enable + 14 + 1 + read-write + + + TYPECEVT2IE + TYPECEVT2 interrupt enable + 15 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FRSEVTIE + FRSEVT interrupt enable + 20 + 1 + read-only + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + UCPD_SR + UCPD_SR + UCPD status register + 0x014 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + TXIS + Transmit interrupt status + + 0 + 1 + read-only + + + B_0x0 + New Tx data write not required + 0x0 + + + B_0x1 + New Tx data write required + 0x1 + + + + + TXMSGDISC + Message transmission discarded + + 1 + 1 + read-only + + + B_0x0 + No Tx message discarded + 0x0 + + + B_0x1 + Tx message discarded + 0x1 + + + + + TXMSGSENT + Message transmission completed + + 2 + 1 + read-only + + + B_0x0 + No Tx message completed + 0x0 + + + B_0x1 + Tx message completed + 0x1 + + + + + TXMSGABT + Transmit message abort + + 3 + 1 + read-only + + + B_0x0 + No transmit message abort + 0x0 + + + B_0x1 + Transmit message abort + 0x1 + + + + + HRSTDISC + Hard Reset discarded + + 4 + 1 + read-only + + + B_0x0 + No Hard Reset discarded + 0x0 + + + B_0x1 + Hard Reset discarded + 0x1 + + + + + HRSTSENT + Hard Reset message sent + + 5 + 1 + read-only + + + B_0x0 + No Hard Reset message sent + 0x0 + + + B_0x1 + Hard Reset message sent + 0x1 + + + + + TXUND + Tx data underrun detection + + 6 + 1 + read-only + + + B_0x0 + No Tx data underrun detected + 0x0 + + + B_0x1 + Tx data underrun detected + 0x1 + + + + + RXNE + Receive data register not empty detection + + 8 + 1 + read-only + + + B_0x0 + Rx data register empty + 0x0 + + + B_0x1 + Rx data register not empty + 0x1 + + + + + RXORDDET + Rx ordered set (4 K-codes) detection + + 9 + 1 + read-only + + + B_0x0 + No ordered set detected + 0x0 + + + B_0x1 + A new ordered set detected + 0x1 + + + + + RXHRSTDET + Rx Hard Reset receipt detection + + 10 + 1 + read-only + + + B_0x0 + Hard Reset not received + 0x0 + + + B_0x1 + Hard Reset received + 0x1 + + + + + RXOVR + Rx data overflow detection + + 11 + 1 + read-only + + + B_0x0 + No overflow + 0x0 + + + B_0x1 + Overflow + 0x1 + + + + + RXMSGEND + Rx message received + + 12 + 1 + read-only + + + B_0x0 + No new Rx message received + 0x0 + + + B_0x1 + A new Rx message received + 0x1 + + + + + RXERR + Receive message error + + 13 + 1 + read-only + + + B_0x0 + No error detected + 0x0 + + + B_0x1 + Error(s) detected + 0x1 + + + + + TYPECEVT1 + Type-C voltage level event on CC1 line + + 14 + 1 + read-only + + + B_0x0 + No new event + 0x0 + + + B_0x1 + A new Type-C event + 0x1 + + + + + TYPECEVT2 + Type-C voltage level event on CC2 line + + 15 + 1 + read-only + + + B_0x0 + No new event + 0x0 + + + B_0x1 + A new Type-C event + 0x1 + + + + + TYPEC_VSTATE_CC1 + The status bitfield indicates the voltage level on the CC1 line in its steady state. + 16 + 2 + read-only + + + B_0x0 + Lowest + 0x0 + + + B_0x1 + Low + 0x1 + + + B_0x2 + High + 0x2 + + + B_0x3 + Highest + 0x3 + + + + + TYPEC_VSTATE_CC2 + CC2 line voltage level + + 18 + 2 + read-only + + + B_0x0 + Lowest + 0x0 + + + B_0x1 + Low + 0x1 + + + B_0x2 + High + 0x2 + + + B_0x3 + Highest + 0x3 + + + + + FRSEVT + FRS detection event + + 20 + 1 + read-only + + + B_0x0 + No new event + 0x0 + + + B_0x1 + New FRS receive event occurred + 0x1 + + + + + + + UCPD_ICR + UCPD_ICR + UCPD interrupt clear register + 0x018 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + TXMSGDISCCF + Tx message discard flag (TXMSGDISC) clear + + 1 + 1 + write-only + + + TXMSGSENTCF + Tx message send flag (TXMSGSENT) clear + + 2 + 1 + write-only + + + TXMSGABTCF + Tx message abort flag (TXMSGABT) clear + + 3 + 1 + write-only + + + HRSTDISCCF + Hard reset discard flag (HRSTDISC) clear + + 4 + 1 + write-only + + + HRSTSENTCF + Hard reset send flag (HRSTSENT) clear + + 5 + 1 + write-only + + + TXUNDCF + Tx underflow flag (TXUND) clear + + 6 + 1 + write-only + + + RXORDDETCF + Rx ordered set detect flag (RXORDDET) clear + + 9 + 1 + write-only + + + RXHRSTDETCF + Rx Hard Reset detect flag (RXHRSTDET) clear + + 10 + 1 + write-only + + + RXOVRCF + Rx overflow flag (RXOVR) clear + + 11 + 1 + write-only + + + RXMSGENDCF + Rx message received flag (RXMSGEND) clear + + 12 + 1 + write-only + + + TYPECEVT1CF + Type-C CC1 event flag (TYPECEVT1) clear + + 14 + 1 + write-only + + + TYPECEVT2CF + Type-C CC2 line event flag (TYPECEVT2) clear + + 15 + 1 + write-only + + + FRSEVTCF + FRS event flag (FRSEVT) clear + + 20 + 1 + write-only + + + + + UCPD_TX_ORDSETR + UCPD_TX_ORDSETR + UCPD Tx ordered set type register + 0x01C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TXORDSET + Ordered set to transmit + + 0 + 20 + read-write + + + + + UCPD_TX_PAYSZR + UCPD_TX_PAYSZR + UCPD Tx payload size register + 0x020 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TXPAYSZ + Payload size yet to transmit + + 0 + 10 + read-write + + + B_0x2 + 2 bytes - the size of Control message from the protocol layer + 0x2 + + + B_0x6 + 6 bytes - the shortest Data message allowed from the protocol layer) + 0x6 + + + B_0x1E + 30 bytes - the longest non-extended Data message allowed from the protocol layer + 0x1E + + + B_0x106 + 262 bytes - the longest possible extended message + 0x106 + + + B_0x3FF + 1024 bytes - the longest possible payload (for future expansion) + 0x3FF + + + + + + + UCPD_TXDR + UCPD_TXDR + UCPD Tx data register + 0x024 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TXDATA + Data byte to transmit + 0 + 8 + read-write + + + + + UCPD_RX_ORDSETR + UCPD_RX_ORDSETR + UCPD Rx ordered set register + 0x028 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RXORDSET + Rx ordered set code detected + 0 + 3 + read-only + + + B_0x0 + SOP code detected in receiver + 0x0 + + + B_0x1 + SOP' code detected in receiver + 0x1 + + + B_0x2 + SOP'' code detected in receiver + 0x2 + + + B_0x3 + SOP'_Debug detected in receiver + 0x3 + + + B_0x4 + SOP''_Debug detected in receiver + 0x4 + + + B_0x5 + Cable Reset detected in receiver + 0x5 + + + B_0x6 + SOP extension#1 detected in receiver + 0x6 + + + B_0x7 + SOP extension#2 detected in receiver + 0x7 + + + + + RXSOP3OF4 + The bit indicates the number of correct K-codes. + 3 + 1 + read-only + + + B_0x0 + 4 correct K-codes out of 4 + 0x0 + + + B_0x1 + 3 correct K-codes out of 4 + 0x1 + + + + + RXSOPKINVALID + The bitfield is for debug purposes only. + 4 + 3 + read-only + + + B_0x0 + No K-code corrupted + 0x0 + + + B_0x1 + First K-code corrupted + 0x1 + + + B_0x2 + Second K-code corrupted + 0x2 + + + B_0x3 + Third K-code corrupted + 0x3 + + + B_0x4 + Fourth K-code corrupted + 0x4 + + + + + + + UCPD_RX_PAYSZR + UCPD_RX_PAYSZR + UCPD Rx payload size register + 0x02C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RXPAYSZ + Rx payload size received + + 0 + 10 + read-only + + + B_0x2 + 2 bytes - the size of Control message from the protocol layer + 0x2 + + + B_0x6 + 6 bytes - the shortest Data message allowed from the protocol layer) + 0x6 + + + B_0x1E + 30 bytes - the longest non-extended Data message allowed from the protocol layer + 0x1E + + + B_0x106 + 262 bytes - the longest possible extended message + 0x106 + + + B_0x3FF + 1024 bytes - the longest possible payload (for future expansion) + 0x3FF + + + + + + + UCPD_RXDR + UCPD_RXDR + UCPD receive data register + 0x030 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RXDATA + Data byte received + 0 + 8 + read-only + + + + + UCPD_RX_ORDEXTR1 + UCPD_RX_ORDEXTR1 + UCPD Rx ordered set extension register 1 + 0x034 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RXSOPX1 + Ordered set 1 received + + 0 + 20 + read-write + + + + + UCPD_RX_ORDEXTR2 + UCPD_RX_ORDEXTR2 + UCPD Rx ordered set extension register 2 + 0x038 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RXSOPX2 + Ordered set 2 received + + 0 + 20 + read-write + + + + + + + UCPD_S + 0X5000DC00 + + + USART + USART address block description + USART + 0x40013800 + + 0x0 + 0x30 + registers + + + USART1 + USART1 global interrupt + 58 + + + + USART_CR1 + USART_CR1 + USART control register 1 + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UE + USART enable + + 0 + 1 + read-write + + + B_0x0 + USART prescaler and outputs disabled, low-power mode + 0x0 + + + B_0x1 + USART enabled + 0x1 + + + + + UESM + USART enable in low-power mode + + 1 + 1 + read-write + + + B_0x0 + USART not able to wake up the MCU from low-power mode. + 0x0 + + + B_0x1 + USART able to wake up the MCU from low-power mode. + 0x1 + + + + + RE + Receiver enable + + 2 + 1 + read-write + + + B_0x0 + Receiver is disabled + 0x0 + + + B_0x1 + Receiver is enabled and begins searching for a start bit + 0x1 + + + + + TE + Transmitter enable + + 3 + 1 + read-write + + + B_0x0 + Transmitter is disabled + 0x0 + + + B_0x1 + Transmitter is enabled + 0x1 + + + + + IDLEIE + IDLE interrupt enable + + 4 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever IDLE = 1 in the USART_ISR register + 0x1 + + + + + RXFNEIE + RXFIFO not empty interrupt enable + + 5 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever ORE=1 or RXFNE=1 in the USART_ISR register + 0x1 + + + + + TCIE + Transmission complete interrupt enable + + 6 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TC=1 in the USART_ISR register + 0x1 + + + + + TXFNFIE + TXFIFO not full interrupt enable + + 7 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TXFNF =1 in the USART_ISR register + 0x1 + + + + + PEIE + PE interrupt enable + + 8 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever PE=1 in the USART_ISR register + 0x1 + + + + + PS + Parity selection + + 9 + 1 + read-write + + + B_0x0 + Even parity + 0x0 + + + B_0x1 + Odd parity + 0x1 + + + + + PCE + Parity control enable + + 10 + 1 + read-write + + + B_0x0 + Parity control disabled + 0x0 + + + B_0x1 + Parity control enabled + 0x1 + + + + + WAKE + Receiver wake-up method + + 11 + 1 + read-write + + + B_0x0 + Idle line + 0x0 + + + B_0x1 + Address mark + 0x1 + + + + + M0 + Word length + + 12 + 1 + read-write + + + MME + Mute mode enable + + 13 + 1 + read-write + + + B_0x0 + Receiver in active mode permanently + 0x0 + + + B_0x1 + Receiver can switch between mute mode and active mode. + 0x1 + + + + + CMIE + Character match interrupt enable + + 14 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the CMF bit is set in the USART_ISR register. + 0x1 + + + + + OVER8 + Oversampling mode + + 15 + 1 + read-write + + + B_0x0 + Oversampling by 16 + 0x0 + + + B_0x1 + Oversampling by 8 + 0x1 + + + + + DEDT + Driver Enable deassertion time + + 16 + 5 + read-write + + + DEAT + Driver Enable assertion time + + 21 + 5 + read-write + + + RTOIE + Receiver timeout interrupt enable + + 26 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the RTOF bit is set in the USART_ISR register. + 0x1 + + + + + EOBIE + End of block interrupt enable + + 27 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the EOBF flag is set in the USART_ISR register + 0x1 + + + + + M1 + Word length + + 28 + 1 + read-write + + + FIFOEN + FIFO mode enable + + 29 + 1 + read-write + + + B_0x0 + FIFO mode is disabled. + 0x0 + + + B_0x1 + FIFO mode is enabled. + 0x1 + + + + + TXFEIE + TXFIFO empty interrupt enable + + 30 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when TXFE=1 in the USART_ISR register + 0x1 + + + + + RXFFIE + RXFIFO Full interrupt enable + + 31 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when RXFF=1 in the USART_ISR register + 0x1 + + + + + + + USART_CR1_ALTERNATE1 + USART_CR1_ALTERNATE1 + USART control register 1 + USART_CR1 + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UE + USART enable + + 0 + 1 + read-write + + + B_0x0 + USART prescaler and outputs disabled, low-power mode + 0x0 + + + B_0x1 + USART enabled + 0x1 + + + + + UESM + USART enable in low-power mode + + 1 + 1 + read-write + + + B_0x0 + USART not able to wake up the MCU from low-power mode. + 0x0 + + + B_0x1 + USART able to wake up the MCU from low-power mode. + 0x1 + + + + + RE + Receiver enable + + 2 + 1 + read-write + + + B_0x0 + Receiver is disabled + 0x0 + + + B_0x1 + Receiver is enabled and begins searching for a start bit + 0x1 + + + + + TE + Transmitter enable + + 3 + 1 + read-write + + + B_0x0 + Transmitter is disabled + 0x0 + + + B_0x1 + Transmitter is enabled + 0x1 + + + + + IDLEIE + IDLE interrupt enable + + 4 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever IDLE = 1 in the USART_ISR register + 0x1 + + + + + RXNEIE + Receive data register not empty + + 5 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever ORE=1 or RXNE=1 in the USART_ISR register + 0x1 + + + + + TCIE + Transmission complete interrupt enable + + 6 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TC=1 in the USART_ISR register + 0x1 + + + + + TXEIE + Transmit data register empty + + 7 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TXE =1 in the USART_ISR register + 0x1 + + + + + PEIE + PE interrupt enable + + 8 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever PE=1 in the USART_ISR register + 0x1 + + + + + PS + Parity selection + + 9 + 1 + read-write + + + B_0x0 + Even parity + 0x0 + + + B_0x1 + Odd parity + 0x1 + + + + + PCE + Parity control enable + + 10 + 1 + read-write + + + B_0x0 + Parity control disabled + 0x0 + + + B_0x1 + Parity control enabled + 0x1 + + + + + WAKE + Receiver wake-up method + + 11 + 1 + read-write + + + B_0x0 + Idle line + 0x0 + + + B_0x1 + Address mark + 0x1 + + + + + M0 + Word length + + 12 + 1 + read-write + + + MME + Mute mode enable + + 13 + 1 + read-write + + + B_0x0 + Receiver in active mode permanently + 0x0 + + + B_0x1 + Receiver can switch between mute mode and active mode. + 0x1 + + + + + CMIE + Character match interrupt enable + + 14 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the CMF bit is set in the USART_ISR register. + 0x1 + + + + + OVER8 + Oversampling mode + + 15 + 1 + read-write + + + B_0x0 + Oversampling by 16 + 0x0 + + + B_0x1 + Oversampling by 8 + 0x1 + + + + + DEDT + Driver Enable deassertion time + + 16 + 5 + read-write + + + DEAT + Driver Enable assertion time + + 21 + 5 + read-write + + + RTOIE + Receiver timeout interrupt enable + + 26 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the RTOF bit is set in the USART_ISR register. + 0x1 + + + + + EOBIE + End of block interrupt enable + + 27 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the EOBF flag is set in the USART_ISR register + 0x1 + + + + + M1 + Word length + + 28 + 1 + read-write + + + FIFOEN + FIFO mode enable + + 29 + 1 + read-write + + + B_0x0 + FIFO mode is disabled. + 0x0 + + + B_0x1 + FIFO mode is enabled. + 0x1 + + + + + + + USART_CR2 + USART_CR2 + USART control register 2 + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SLVEN + Synchronous slave mode enable + + 0 + 1 + read-write + + + B_0x0 + Slave mode disabled. + 0x0 + + + B_0x1 + Slave mode enabled. + 0x1 + + + + + DIS_NSS + When the DIS_NSS bit is set, the NSS pin input is ignored. + 3 + 1 + read-write + + + B_0x0 + SPI slave selection depends on NSS input pin. + 0x0 + + + B_0x1 + SPI slave is always selected and NSS input pin is ignored. + 0x1 + + + + + ADDM7 + 7-bit Address Detection/4-bit Address Detection + + 4 + 1 + read-write + + + B_0x0 + 4-bit address detection + 0x0 + + + B_0x1 + 7-bit address detection (in 8-bit data mode) + 0x1 + + + + + LBDL + LIN break detection length + + 5 + 1 + read-write + + + B_0x0 + 10-bit break detection + 0x0 + + + B_0x1 + 11-bit break detection + 0x1 + + + + + LBDIE + LIN break detection interrupt enable + + 6 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An interrupt is generated whenever LBDF=1 in the USART_ISR register + 0x1 + + + + + LBCL + Last bit clock pulse + + 8 + 1 + read-write + + + B_0x0 + The clock pulse of the last data bit is not output to the CK pin + 0x0 + + + B_0x1 + The clock pulse of the last data bit is output to the CK pin + 0x1 + + + + + CPHA + Clock phase + + 9 + 1 + read-write + + + B_0x0 + The first clock transition is the first data capture edge + 0x0 + + + B_0x1 + The second clock transition is the first data capture edge + 0x1 + + + + + CPOL + Clock polarity + + 10 + 1 + read-write + + + B_0x0 + Steady low value on CK pin outside transmission window + 0x0 + + + B_0x1 + Steady high value on CK pin outside transmission window + 0x1 + + + + + CLKEN + Clock enable + + 11 + 1 + read-write + + + B_0x0 + CK pin disabled + 0x0 + + + B_0x1 + CK pin enabled + 0x1 + + + + + STOP + stop bits + + 12 + 2 + read-write + + + B_0x0 + 1 stop bit + 0x0 + + + B_0x1 + 0. + 0x1 + + + B_0x2 + 2 stop bits + 0x2 + + + B_0x3 + 1. + 0x3 + + + + + LINEN + LIN mode enable + + 14 + 1 + read-write + + + B_0x0 + LIN mode disabled + 0x0 + + + B_0x1 + LIN mode enabled + 0x1 + + + + + SWAP + Swap TX/RX pins + + 15 + 1 + read-write + + + B_0x0 + TX/RX pins are used as defined in standard pinout + 0x0 + + + B_0x1 + The TX and RX pins functions are swapped. + 0x1 + + + + + RXINV + RX pin active level inversion + + 16 + 1 + read-write + + + B_0x0 + RX pin signal works using the standard logic levels (Vless thansub>DDless than/sub> =1/idle, Gnd=0/mark) + 0x0 + + + B_0x1 + RX pin signal values are inverted. + 0x1 + + + + + TXINV + TX pin active level inversion + + 17 + 1 + read-write + + + B_0x0 + TX pin signal works using the standard logic levels (Vless thansub>DDless than/sub> =1/idle, Gnd=0/mark) + 0x0 + + + B_0x1 + TX pin signal values are inverted. + 0x1 + + + + + DATAINV + Binary data inversion + + 18 + 1 + read-write + + + B_0x0 + Logical data from the data register are send/received in positive/direct logic. + 0x0 + + + B_0x1 + Logical data from the data register are send/received in negative/inverse logic. + 0x1 + + + + + MSBFIRST + Most significant bit first + + 19 + 1 + read-write + + + B_0x0 + data is transmitted/received with data bit 0 first, following the start bit. + 0x0 + + + B_0x1 + data is transmitted/received with the MSB (bit 7/8) first, following the start bit. + 0x1 + + + + + ABREN + Auto baud rate enable + + 20 + 1 + read-write + + + B_0x0 + Auto baud rate detection is disabled. + 0x0 + + + B_0x1 + Auto baud rate detection is enabled. + 0x1 + + + + + ABRMOD + Auto baud rate mode + + 21 + 2 + read-write + + + B_0x0 + Measurement of the start bit is used to detect the baud rate. + 0x0 + + + B_0x1 + Falling edge to falling edge measurement (the received frame must start with a single bit = 1 -> Frame = Start10xxxxxx) + 0x1 + + + B_0x2 + 0x7F frame detection. + 0x2 + + + B_0x3 + 0x55 frame detection + 0x3 + + + + + RTOEN + Receiver timeout enable + + 23 + 1 + read-write + + + B_0x0 + Receiver timeout feature disabled. + 0x0 + + + B_0x1 + Receiver timeout feature enabled. + 0x1 + + + + + ADD + Address of the USART node + + 24 + 8 + read-write + + + + + USART_CR3 + USART_CR3 + USART control register 3 + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EIE + Error interrupt enable + + 0 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + interrupt generated when FE=1 or ORE=1 or NE=1 or UDR = 1 (in SPI slave mode) in the USART_ISR register. + 0x1 + + + + + IREN + IrDA mode enable + + 1 + 1 + read-write + + + B_0x0 + IrDA disabled + 0x0 + + + B_0x1 + IrDA enabled + 0x1 + + + + + IRLP + IrDA low-power + + 2 + 1 + read-write + + + B_0x0 + Normal mode + 0x0 + + + B_0x1 + Low-power mode + 0x1 + + + + + HDSEL + Half-duplex selection + + 3 + 1 + read-write + + + B_0x0 + Half-duplex mode is not selected + 0x0 + + + B_0x1 + Half-duplex mode is selected + 0x1 + + + + + NACK + Smartcard NACK enable + + 4 + 1 + read-write + + + B_0x0 + NACK transmission in case of parity error is disabled + 0x0 + + + B_0x1 + NACK transmission during parity error is enabled + 0x1 + + + + + SCEN + Smartcard mode enable + + 5 + 1 + read-write + + + B_0x0 + Smartcard mode disabled + 0x0 + + + B_0x1 + Smartcard mode enabled + 0x1 + + + + + DMAR + DMA enable receiver + + 6 + 1 + read-write + + + B_0x1 + DMA mode is enabled for reception + 0x1 + + + B_0x0 + DMA mode is disabled for reception + 0x0 + + + + + DMAT + DMA enable transmitter + + 7 + 1 + read-write + + + B_0x1 + DMA mode is enabled for transmission + 0x1 + + + B_0x0 + DMA mode is disabled for transmission + 0x0 + + + + + RTSE + RTS enable + + 8 + 1 + read-write + + + B_0x0 + RTS hardware flow control disabled + 0x0 + + + B_0x1 + RTS output enabled, data is only requested when there is space in the receive buffer. + 0x1 + + + + + CTSE + CTS enable + + 9 + 1 + read-write + + + B_0x0 + CTS hardware flow control disabled + 0x0 + + + B_0x1 + CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). + 0x1 + + + + + CTSIE + CTS interrupt enable + + 10 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An interrupt is generated whenever CTSIF=1 in the USART_ISR register + 0x1 + + + + + ONEBIT + One sample bit method enable + + 11 + 1 + read-write + + + B_0x0 + Three sample bit method + 0x0 + + + B_0x1 + One sample bit method + 0x1 + + + + + OVRDIS + Overrun Disable + + 12 + 1 + read-write + + + B_0x0 + Overrun Error Flag, ORE, is set when received data is not read before receiving new data. + 0x0 + + + B_0x1 + Overrun functionality is disabled. + 0x1 + + + + + DDRE + DMA Disable on reception Error + + 13 + 1 + read-write + + + B_0x0 + DMA is not disabled in case of reception error. + 0x0 + + + B_0x1 + DMA is disabled following a reception error. + 0x1 + + + + + DEM + Driver enable mode + + 14 + 1 + read-write + + + B_0x0 + DE function is disabled. + 0x0 + + + B_0x1 + DE function is enabled. + 0x1 + + + + + DEP + Driver enable polarity selection + + 15 + 1 + read-write + + + B_0x0 + DE signal is active high. + 0x0 + + + B_0x1 + DE signal is active low. + 0x1 + + + + + SCARCNT + Smartcard auto-retry count + + 17 + 3 + read-write + + + B_0x0 + retransmission disabled - No automatic retransmission in transmission mode. + 0x0 + + + + + WUS0 + Wake-up from low-power mode interrupt flag selection + + 20 + 1 + read-write + + + B_0x0 + WUF active on address match (as defined by ADD[7:0] and ADDM7) + 0x0 + + + + + WUS1 + Wake-up from low-power mode interrupt flag selection + + 21 + 1 + read-write + + + B_0x0 + WUF active on address match (as defined by ADD[7:0] and ADDM7) + 0x0 + + + + + WUFIE + Wake-up from low-power mode interrupt enable + + 22 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever WUF=1 in the USART_ISR register + 0x1 + + + + + TXFTIE + TXFIFO threshold interrupt enable + + 23 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG. + 0x1 + + + + + TCBGTIE + Transmission Complete before guard time, interrupt enable + + 24 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TCBGT=1 in the USART_ISR register + 0x1 + + + + + RXFTCFG + Receive FIFO threshold configuration + + 25 + 3 + read-write + + + B_0x0 + Receive FIFO reaches 1/8 of its depth + 0x0 + + + B_0x1 + Receive FIFO reaches 1/4 of its depth + 0x1 + + + B_0x2 + Receive FIFO reaches 1/2 of its depth + 0x2 + + + B_0x3 + Receive FIFO reaches 3/4 of its depth + 0x3 + + + B_0x4 + Receive FIFO reaches 7/8 of its depth + 0x4 + + + B_0x5 + Receive FIFO becomes full + 0x5 + + + + + RXFTIE + RXFIFO threshold interrupt enable + + 28 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG. + 0x1 + + + + + TXFTCFG + TXFIFO threshold configuration + + 29 + 3 + read-write + + + B_0x0 + TXFIFO reaches 1/8 of its depth + 0x0 + + + B_0x1 + TXFIFO reaches 1/4 of its depth + 0x1 + + + B_0x2 + TXFIFO reaches 1/2 of its depth + 0x2 + + + B_0x3 + TXFIFO reaches 3/4 of its depth + 0x3 + + + B_0x4 + TXFIFO reaches 7/8 of its depth + 0x4 + + + B_0x5 + TXFIFO becomes empty + 0x5 + + + + + + + USART_CR3_ALTERNATE1 + USART_CR3_ALTERNATE1 + USART control register 3 + USART_CR3 + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EIE + Error interrupt enable + + 0 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + interrupt generated when FE=1 or ORE=1 or NE=1 or UDR = 1 (in SPI slave mode) in the USART_ISR register. + 0x1 + + + + + IREN + IrDA mode enable + + 1 + 1 + read-write + + + B_0x0 + IrDA disabled + 0x0 + + + B_0x1 + IrDA enabled + 0x1 + + + + + IRLP + IrDA low-power + + 2 + 1 + read-write + + + B_0x0 + Normal mode + 0x0 + + + B_0x1 + Low-power mode + 0x1 + + + + + HDSEL + Half-duplex selection + + 3 + 1 + read-write + + + B_0x0 + Half-duplex mode is not selected + 0x0 + + + B_0x1 + Half-duplex mode is selected + 0x1 + + + + + NACK + Smartcard NACK enable + + 4 + 1 + read-write + + + B_0x0 + NACK transmission in case of parity error is disabled + 0x0 + + + B_0x1 + NACK transmission during parity error is enabled + 0x1 + + + + + SCEN + Smartcard mode enable + + 5 + 1 + read-write + + + B_0x0 + Smartcard mode disabled + 0x0 + + + B_0x1 + Smartcard mode enabled + 0x1 + + + + + DMAR + DMA enable receiver + + 6 + 1 + read-write + + + B_0x1 + DMA mode is enabled for reception + 0x1 + + + B_0x0 + DMA mode is disabled for reception + 0x0 + + + + + DMAT + DMA enable transmitter + + 7 + 1 + read-write + + + B_0x1 + DMA mode is enabled for transmission + 0x1 + + + B_0x0 + DMA mode is disabled for transmission + 0x0 + + + + + RTSE + RTS enable + + 8 + 1 + read-write + + + B_0x0 + RTS hardware flow control disabled + 0x0 + + + B_0x1 + RTS output enabled, data is only requested when there is space in the receive buffer. + 0x1 + + + + + CTSE + CTS enable + + 9 + 1 + read-write + + + B_0x0 + CTS hardware flow control disabled + 0x0 + + + B_0x1 + CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). + 0x1 + + + + + CTSIE + CTS interrupt enable + + 10 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An interrupt is generated whenever CTSIF=1 in the USART_ISR register + 0x1 + + + + + ONEBIT + One sample bit method enable + + 11 + 1 + read-write + + + B_0x0 + Three sample bit method + 0x0 + + + B_0x1 + One sample bit method + 0x1 + + + + + OVRDIS + Overrun Disable + + 12 + 1 + read-write + + + B_0x0 + Overrun Error Flag, ORE, is set when received data is not read before receiving new data. + 0x0 + + + B_0x1 + Overrun functionality is disabled. + 0x1 + + + + + DDRE + DMA Disable on reception Error + + 13 + 1 + read-write + + + B_0x0 + DMA is not disabled in case of reception error. + 0x0 + + + B_0x1 + DMA is disabled following a reception error. + 0x1 + + + + + DEM + Driver enable mode + + 14 + 1 + read-write + + + B_0x0 + DE function is disabled. + 0x0 + + + B_0x1 + DE function is enabled. + 0x1 + + + + + DEP + Driver enable polarity selection + + 15 + 1 + read-write + + + B_0x0 + DE signal is active high. + 0x0 + + + B_0x1 + DE signal is active low. + 0x1 + + + + + SCARCNT + Smartcard auto-retry count + + 17 + 3 + read-write + + + B_0x0 + retransmission disabled - No automatic retransmission in transmission mode. + 0x0 + + + + + WUS0 + Wake-up from low-power mode interrupt flag selection + + 20 + 1 + read-write + + + B_0x0 + WUF active on address match (as defined by ADD[7:0] and ADDM7) + 0x0 + + + + + WUS1 + Wake-up from low-power mode interrupt flag selection + + 21 + 1 + read-write + + + B_0x0 + WUF active on address match (as defined by ADD[7:0] and ADDM7) + 0x0 + + + + + WUFIE + Wake-up from low-power mode interrupt enable + + 22 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever WUF=1 in the USART_ISR register + 0x1 + + + + + TCBGTIE + Transmission Complete before guard time, interrupt enable + + 24 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TCBGT=1 in the USART_ISR register + 0x1 + + + + + + + USART_BRR + USART_BRR + USART baud rate register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BRR + USART baud rate + + 0 + 16 + read-write + + + + + USART_GTPR + USART_GTPR + USART guard time and prescaler register + 0x10 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PSC + Prescaler value + + 0 + 8 + read-write + + + B_0x1_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE + divides the source clock by 1 + 0x1 + + + B_0x2_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE + divides the source clock by 2 + 0x2 + + + B_0x3_SMARTCARD_MODE + divides the source clock by 6 + 0x3 + + + + + GT + Guard time value + + 8 + 8 + read-write + + + + + USART_RTOR + USART_RTOR + USART receiver timeout register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RTO + Receiver timeout value + + 0 + 24 + read-write + + + BLEN + Block Length + + 24 + 8 + read-write + + + + + USART_RQR + USART_RQR + USART request register + 0x18 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + ABRRQ + Auto baud rate request + + 0 + 1 + write-only + + + SBKRQ + Send break request + + 1 + 1 + write-only + + + MMRQ + Mute mode request + + 2 + 1 + write-only + + + RXFRQ + Receive data flush request + + 3 + 1 + write-only + + + TXFRQ + Transmit data flush request + + 4 + 1 + write-only + + + + + USART_ISR + USART_ISR + USART interrupt and status register + 0x1C + 0x20 + read-only + 0x000000C0 + 0xF00FFFFF + + + PE + Parity error + + 0 + 1 + read-only + + + B_0x0 + No parity error + 0x0 + + + B_0x1 + Parity error + 0x1 + + + + + FE + Framing error + + 1 + 1 + read-only + + + B_0x0 + No Framing error is detected + 0x0 + + + B_0x1 + Framing error or break character is detected + 0x1 + + + + + NE + Noise detection flag + + 2 + 1 + read-only + + + B_0x0 + No noise is detected + 0x0 + + + B_0x1 + Noise is detected + 0x1 + + + + + ORE + Overrun error + + 3 + 1 + read-only + + + B_0x0 + No overrun error + 0x0 + + + B_0x1 + Overrun error is detected + 0x1 + + + + + IDLE + Idle line detected + + 4 + 1 + read-only + + + B_0x0 + No Idle line is detected + 0x0 + + + B_0x1 + Idle line is detected + 0x1 + + + + + RXFNE + RXFIFO not empty + + 5 + 1 + read-only + + + B_0x0 + Data is not received + 0x0 + + + B_0x1 + Received data is ready to be read. + 0x1 + + + + + TC + Transmission complete + + 6 + 1 + read-only + + + TXFNF + TXFIFO not full + + 7 + 1 + read-only + + + B_0x0 + Transmit FIFO is full + 0x0 + + + B_0x1 + Transmit FIFO is not full + 0x1 + + + + + LBDF + LIN break detection flag + + 8 + 1 + read-only + + + B_0x0 + LIN Break not detected + 0x0 + + + B_0x1 + LIN break detected + 0x1 + + + + + CTSIF + CTS interrupt flag + + 9 + 1 + read-only + + + B_0x0 + No change occurred on the CTS status line + 0x0 + + + B_0x1 + A change occurred on the CTS status line + 0x1 + + + + + CTS + CTS flag + + 10 + 1 + read-only + + + B_0x0 + CTS line set + 0x0 + + + B_0x1 + CTS line reset + 0x1 + + + + + RTOF + Receiver timeout + + 11 + 1 + read-only + + + B_0x0 + Timeout value not reached + 0x0 + + + B_0x1 + Timeout value reached without any data reception + 0x1 + + + + + EOBF + End of block flag + + 12 + 1 + read-only + + + B_0x0 + End of block not reached + 0x0 + + + B_0x1 + End of block (number of characters) reached + 0x1 + + + + + UDR + SPI slave underrun error flag + + 13 + 1 + read-only + + + B_0x0 + No underrun error + 0x0 + + + B_0x1 + underrun error + 0x1 + + + + + ABRE + Auto baud rate error + + 14 + 1 + read-only + + + ABRF + Auto baud rate flag + + 15 + 1 + read-only + + + BUSY + Busy flag + + 16 + 1 + read-only + + + B_0x0 + USART is idle (no reception) + 0x0 + + + B_0x1 + Reception ongoing + 0x1 + + + + + CMF + Character match flag + + 17 + 1 + read-only + + + B_0x0 + No Character match detected + 0x0 + + + B_0x1 + Character match detected + 0x1 + + + + + SBKF + Send break flag + + 18 + 1 + read-only + + + B_0x0 + No break character transmitted + 0x0 + + + B_0x1 + Break character transmitted + 0x1 + + + + + RWU + Receiver wake-up from mute mode + + 19 + 1 + read-only + + + B_0x0 + Receiver in active mode + 0x0 + + + B_0x1 + Receiver in mute mode + 0x1 + + + + + WUF + Wake-up from low-power mode flag + + 20 + 1 + read-only + + + TEACK + Transmit enable acknowledge flag + + 21 + 1 + read-only + + + REACK + Receive enable acknowledge flag + + 22 + 1 + read-only + + + TXFE + TXFIFO Empty + + 23 + 1 + read-only + + + B_0x0 + TXFIFO not empty. + 0x0 + + + B_0x1 + TXFIFO empty. + 0x1 + + + + + RXFF + RXFIFO Full + + 24 + 1 + read-only + + + B_0x0 + RXFIFO not full. + 0x0 + + + B_0x1 + RXFIFO Full. + 0x1 + + + + + TCBGT + Transmission complete before guard time flag + + 25 + 1 + read-only + + + B_0x0 + Transmission is not complete or transmission is complete unsuccessfully (i. + 0x0 + + + B_0x1 + Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card). + 0x1 + + + + + RXFT + RXFIFO threshold flag + + 26 + 1 + read-only + + + B_0x0 + Receive FIFO does not reach the programmed threshold. + 0x0 + + + B_0x1 + Receive FIFO reached the programmed threshold. + 0x1 + + + + + TXFT + TXFIFO threshold flag + + 27 + 1 + read-only + + + B_0x0 + TXFIFO does not reach the programmed threshold. + 0x0 + + + B_0x1 + TXFIFO reached the programmed threshold. + 0x1 + + + + + + + USART_ISR_ALTERNATE1 + USART_ISR_ALTERNATE1 + USART interrupt and status register + USART_ISR + 0x1C + 0x20 + read-only + 0x000000C0 + 0xF00FFFFF + + + PE + Parity error + + 0 + 1 + read-only + + + B_0x0 + No parity error + 0x0 + + + B_0x1 + Parity error + 0x1 + + + + + FE + Framing error + + 1 + 1 + read-only + + + B_0x0 + No Framing error is detected + 0x0 + + + B_0x1 + Framing error or break character is detected + 0x1 + + + + + NE + Noise detection flag + + 2 + 1 + read-only + + + B_0x0 + No noise is detected + 0x0 + + + B_0x1 + Noise is detected + 0x1 + + + + + ORE + Overrun error + + 3 + 1 + read-only + + + B_0x1 + Overrun error is detected + 0x1 + + + + + IDLE + Idle line detected + + 4 + 1 + read-only + + + B_0x0 + No Idle line is detected + 0x0 + + + B_0x1 + Idle line is detected + 0x1 + + + + + RXNE + Read data register not empty + + 5 + 1 + read-only + + + B_0x0 + Data is not received + 0x0 + + + B_0x1 + Received data is ready to be read. + 0x1 + + + + + TC + Transmission complete + + 6 + 1 + read-only + + + TXE + Transmit data register empty + + 7 + 1 + read-only + + + B_0x0 + Data register full + 0x0 + + + B_0x1 + Data register empty + 0x1 + + + + + LBDF + LIN break detection flag + + 8 + 1 + read-only + + + B_0x0 + LIN Break not detected + 0x0 + + + B_0x1 + LIN break detected + 0x1 + + + + + CTSIF + CTS interrupt flag + + 9 + 1 + read-only + + + B_0x0 + No change occurred on the CTS status line + 0x0 + + + B_0x1 + A change occurred on the CTS status line + 0x1 + + + + + CTS + CTS flag + + 10 + 1 + read-only + + + B_0x0 + CTS line set + 0x0 + + + B_0x1 + CTS line reset + 0x1 + + + + + RTOF + Receiver timeout + + 11 + 1 + read-only + + + B_0x0 + Timeout value not reached + 0x0 + + + B_0x1 + Timeout value reached without any data reception + 0x1 + + + + + EOBF + End of block flag + + 12 + 1 + read-only + + + B_0x0 + End of block not reached + 0x0 + + + B_0x1 + End of block (number of characters) reached + 0x1 + + + + + UDR + SPI slave underrun error flag + + 13 + 1 + read-only + + + B_0x0 + No underrun error + 0x0 + + + B_0x1 + underrun error + 0x1 + + + + + ABRE + Auto baud rate error + + 14 + 1 + read-only + + + ABRF + Auto baud rate flag + + 15 + 1 + read-only + + + BUSY + Busy flag + + 16 + 1 + read-only + + + B_0x0 + USART is idle (no reception) + 0x0 + + + B_0x1 + Reception ongoing + 0x1 + + + + + CMF + Character match flag + + 17 + 1 + read-only + + + B_0x0 + No Character match detected + 0x0 + + + B_0x1 + Character match detected + 0x1 + + + + + SBKF + Send break flag + + 18 + 1 + read-only + + + B_0x0 + No break character transmitted + 0x0 + + + B_0x1 + Break character transmitted + 0x1 + + + + + RWU + Receiver wake-up from mute mode + + 19 + 1 + read-only + + + B_0x0 + Receiver in active mode + 0x0 + + + B_0x1 + Receiver in mute mode + 0x1 + + + + + WUF + Wake-up from low-power mode flag + + 20 + 1 + read-only + + + TEACK + Transmit enable acknowledge flag + + 21 + 1 + read-only + + + REACK + Receive enable acknowledge flag + + 22 + 1 + read-only + + + TCBGT + Transmission complete before guard time flag + + 25 + 1 + read-only + + + B_0x0 + Transmission is not complete or transmission is complete unsuccessfully (i. + 0x0 + + + B_0x1 + Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card). + 0x1 + + + + + + + USART_ICR + USART_ICR + USART interrupt flag clear register + 0x20 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + PECF + Parity error clear flag + + 0 + 1 + write-only + + + FECF + Framing error clear flag + + 1 + 1 + write-only + + + NECF + Noise detected clear flag + + 2 + 1 + write-only + + + ORECF + Overrun error clear flag + + 3 + 1 + write-only + + + IDLECF + Idle line detected clear flag + + 4 + 1 + write-only + + + TXFECF + TXFIFO empty clear flag + + 5 + 1 + write-only + + + TCCF + Transmission complete clear flag + + 6 + 1 + write-only + + + TCBGTCF + Transmission complete before Guard time clear flag + + 7 + 1 + write-only + + + LBDCF + LIN break detection clear flag + + 8 + 1 + write-only + + + CTSCF + CTS clear flag + + 9 + 1 + write-only + + + RTOCF + Receiver timeout clear flag + + 11 + 1 + write-only + + + EOBCF + End of block clear flag + + 12 + 1 + write-only + + + UDRCF + SPI slave underrun clear flag + + 13 + 1 + write-only + + + CMCF + Character match clear flag + + 17 + 1 + write-only + + + WUCF + Wake-up from low-power mode clear flag + + 20 + 1 + write-only + + + + + USART_RDR + USART_RDR + USART receive data register + 0x24 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RDR + Receive data value + + 0 + 9 + read-only + + + + + USART_TDR + USART_TDR + USART transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TDR + Transmit data value + + 0 + 9 + read-write + + + + + USART_PRESC + USART_PRESC + USART prescaler register + 0x2C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRESCALER + Clock prescaler + + 0 + 4 + read-write + + + B_0x0 + input clock not divided + 0x0 + + + B_0x1 + input clock divided by 2 + 0x1 + + + B_0x2 + input clock divided by 4 + 0x2 + + + B_0x3 + input clock divided by 6 + 0x3 + + + B_0x4 + input clock divided by 8 + 0x4 + + + B_0x5 + input clock divided by 10 + 0x5 + + + B_0x6 + input clock divided by 12 + 0x6 + + + B_0x7 + input clock divided by 16 + 0x7 + + + B_0x8 + input clock divided by 32 + 0x8 + + + B_0x9 + input clock divided by 64 + 0x9 + + + B_0xA + input clock divided by 128 + 0xA + + + B_0xB + input clock divided by 256 + 0xB + + + + + + + + + USART_S + 0X50013800 + + + USART2 + 0X40004400 + + USART2 + USART2 global interrupt + 59 + + + + USART2_S + 0X50004400 + + + USART3 + 0X40004800 + + USART3 + USART3 global interrupt + 60 + + + + USART3_S + 0X50004800 + + + UART4 + 0X40004c00 + + UART4 + UART4 global interrupt + 61 + + + + UART4_S + 0X50004c00 + + + UART5 + 0X40005000 + + UART5 + UART5 global interrupt + 62 + + + + UART5_S + 0X50005000 + + + USART6 + 0X40006400 + + USART6 + USART6 global interrupt + 85 + + + + USART6_S + 0X50006400 + + + USB + USB address block description + USB + 0x40016000 + + 0x0 + 0x5C + registers + + + USB_FS + USB OTG FS global interrupt + 74 + + + + USB_CHEP0R + USB_CHEP0R + USB endpoint/channel 0 register + 0x0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EA + endpoint/channel address + + 0 + 4 + read-write + + + STATTX + Status bits, for transmission transfers + + 4 + 2 + write-only + + + DTOGTX + Data toggle, for transmission transfers + + 6 + 1 + write-only + + + VTTX + Valid USB transaction transmitted + + 7 + 1 + read-write + + + EPKIND + endpoint/channel kind + + 8 + 1 + read-write + + + UTYPE + USB type of transaction + + 9 + 2 + read-write + + + SETUP + Setup transaction completed + + 11 + 1 + read-only + + + STATRX + Status bits, for reception transfers + + 12 + 2 + write-only + + + DTOGRX + Data Toggle, for reception transfers + + 14 + 1 + write-only + + + VTRX + USB valid transaction received + + 15 + 1 + read-write + + + DEVADDR + Host mode + + 16 + 7 + read-write + + + NAK + Host mode + + 23 + 1 + read-write + + + LS_EP + Low speed endpoint host with HUB only + + 24 + 1 + read-write + + + B_0x0 + Full speed endpoint + 0x0 + + + B_0x1 + Low speed endpoint + 0x1 + + + + + ERR_TX + Received error for an OUT/SETUP transaction + + 25 + 1 + read-write + + + ERR_RX + Received error for an IN transaction + + 26 + 1 + read-write + + + THREE_ERR_TX + Three errors for an OUT or SETUP transaction + + 27 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + THREE_ERR_RX + Three errors for an IN transaction + + 29 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + + + USB_CHEP1R + USB_CHEP1R + USB endpoint/channel 1 register + 0x4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EA + endpoint/channel address + + 0 + 4 + read-write + + + STATTX + Status bits, for transmission transfers + + 4 + 2 + write-only + + + DTOGTX + Data toggle, for transmission transfers + + 6 + 1 + write-only + + + VTTX + Valid USB transaction transmitted + + 7 + 1 + read-write + + + EPKIND + endpoint/channel kind + + 8 + 1 + read-write + + + UTYPE + USB type of transaction + + 9 + 2 + read-write + + + SETUP + Setup transaction completed + + 11 + 1 + read-only + + + STATRX + Status bits, for reception transfers + + 12 + 2 + write-only + + + DTOGRX + Data Toggle, for reception transfers + + 14 + 1 + write-only + + + VTRX + USB valid transaction received + + 15 + 1 + read-write + + + DEVADDR + Host mode + + 16 + 7 + read-write + + + NAK + Host mode + + 23 + 1 + read-write + + + LS_EP + Low speed endpoint host with HUB only + + 24 + 1 + read-write + + + B_0x0 + Full speed endpoint + 0x0 + + + B_0x1 + Low speed endpoint + 0x1 + + + + + ERR_TX + Received error for an OUT/SETUP transaction + + 25 + 1 + read-write + + + ERR_RX + Received error for an IN transaction + + 26 + 1 + read-write + + + THREE_ERR_TX + Three errors for an OUT or SETUP transaction + + 27 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + THREE_ERR_RX + Three errors for an IN transaction + + 29 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + + + USB_CHEP2R + USB_CHEP2R + USB endpoint/channel 2 register + 0x8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EA + endpoint/channel address + + 0 + 4 + read-write + + + STATTX + Status bits, for transmission transfers + + 4 + 2 + write-only + + + DTOGTX + Data toggle, for transmission transfers + + 6 + 1 + write-only + + + VTTX + Valid USB transaction transmitted + + 7 + 1 + read-write + + + EPKIND + endpoint/channel kind + + 8 + 1 + read-write + + + UTYPE + USB type of transaction + + 9 + 2 + read-write + + + SETUP + Setup transaction completed + + 11 + 1 + read-only + + + STATRX + Status bits, for reception transfers + + 12 + 2 + write-only + + + DTOGRX + Data Toggle, for reception transfers + + 14 + 1 + write-only + + + VTRX + USB valid transaction received + + 15 + 1 + read-write + + + DEVADDR + Host mode + + 16 + 7 + read-write + + + NAK + Host mode + + 23 + 1 + read-write + + + LS_EP + Low speed endpoint host with HUB only + + 24 + 1 + read-write + + + B_0x0 + Full speed endpoint + 0x0 + + + B_0x1 + Low speed endpoint + 0x1 + + + + + ERR_TX + Received error for an OUT/SETUP transaction + + 25 + 1 + read-write + + + ERR_RX + Received error for an IN transaction + + 26 + 1 + read-write + + + THREE_ERR_TX + Three errors for an OUT or SETUP transaction + + 27 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + THREE_ERR_RX + Three errors for an IN transaction + + 29 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + + + USB_CHEP3R + USB_CHEP3R + USB endpoint/channel 3 register + 0xC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EA + endpoint/channel address + + 0 + 4 + read-write + + + STATTX + Status bits, for transmission transfers + + 4 + 2 + write-only + + + DTOGTX + Data toggle, for transmission transfers + + 6 + 1 + write-only + + + VTTX + Valid USB transaction transmitted + + 7 + 1 + read-write + + + EPKIND + endpoint/channel kind + + 8 + 1 + read-write + + + UTYPE + USB type of transaction + + 9 + 2 + read-write + + + SETUP + Setup transaction completed + + 11 + 1 + read-only + + + STATRX + Status bits, for reception transfers + + 12 + 2 + write-only + + + DTOGRX + Data Toggle, for reception transfers + + 14 + 1 + write-only + + + VTRX + USB valid transaction received + + 15 + 1 + read-write + + + DEVADDR + Host mode + + 16 + 7 + read-write + + + NAK + Host mode + + 23 + 1 + read-write + + + LS_EP + Low speed endpoint host with HUB only + + 24 + 1 + read-write + + + B_0x0 + Full speed endpoint + 0x0 + + + B_0x1 + Low speed endpoint + 0x1 + + + + + ERR_TX + Received error for an OUT/SETUP transaction + + 25 + 1 + read-write + + + ERR_RX + Received error for an IN transaction + + 26 + 1 + read-write + + + THREE_ERR_TX + Three errors for an OUT or SETUP transaction + + 27 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + THREE_ERR_RX + Three errors for an IN transaction + + 29 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + + + USB_CHEP4R + USB_CHEP4R + USB endpoint/channel 4 register + 0x10 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EA + endpoint/channel address + + 0 + 4 + read-write + + + STATTX + Status bits, for transmission transfers + + 4 + 2 + write-only + + + DTOGTX + Data toggle, for transmission transfers + + 6 + 1 + write-only + + + VTTX + Valid USB transaction transmitted + + 7 + 1 + read-write + + + EPKIND + endpoint/channel kind + + 8 + 1 + read-write + + + UTYPE + USB type of transaction + + 9 + 2 + read-write + + + SETUP + Setup transaction completed + + 11 + 1 + read-only + + + STATRX + Status bits, for reception transfers + + 12 + 2 + write-only + + + DTOGRX + Data Toggle, for reception transfers + + 14 + 1 + write-only + + + VTRX + USB valid transaction received + + 15 + 1 + read-write + + + DEVADDR + Host mode + + 16 + 7 + read-write + + + NAK + Host mode + + 23 + 1 + read-write + + + LS_EP + Low speed endpoint host with HUB only + + 24 + 1 + read-write + + + B_0x0 + Full speed endpoint + 0x0 + + + B_0x1 + Low speed endpoint + 0x1 + + + + + ERR_TX + Received error for an OUT/SETUP transaction + + 25 + 1 + read-write + + + ERR_RX + Received error for an IN transaction + + 26 + 1 + read-write + + + THREE_ERR_TX + Three errors for an OUT or SETUP transaction + + 27 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + THREE_ERR_RX + Three errors for an IN transaction + + 29 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + + + USB_CHEP5R + USB_CHEP5R + USB endpoint/channel 5 register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EA + endpoint/channel address + + 0 + 4 + read-write + + + STATTX + Status bits, for transmission transfers + + 4 + 2 + write-only + + + DTOGTX + Data toggle, for transmission transfers + + 6 + 1 + write-only + + + VTTX + Valid USB transaction transmitted + + 7 + 1 + read-write + + + EPKIND + endpoint/channel kind + + 8 + 1 + read-write + + + UTYPE + USB type of transaction + + 9 + 2 + read-write + + + SETUP + Setup transaction completed + + 11 + 1 + read-only + + + STATRX + Status bits, for reception transfers + + 12 + 2 + write-only + + + DTOGRX + Data Toggle, for reception transfers + + 14 + 1 + write-only + + + VTRX + USB valid transaction received + + 15 + 1 + read-write + + + DEVADDR + Host mode + + 16 + 7 + read-write + + + NAK + Host mode + + 23 + 1 + read-write + + + LS_EP + Low speed endpoint host with HUB only + + 24 + 1 + read-write + + + B_0x0 + Full speed endpoint + 0x0 + + + B_0x1 + Low speed endpoint + 0x1 + + + + + ERR_TX + Received error for an OUT/SETUP transaction + + 25 + 1 + read-write + + + ERR_RX + Received error for an IN transaction + + 26 + 1 + read-write + + + THREE_ERR_TX + Three errors for an OUT or SETUP transaction + + 27 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + THREE_ERR_RX + Three errors for an IN transaction + + 29 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + + + USB_CHEP6R + USB_CHEP6R + USB endpoint/channel 6 register + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EA + endpoint/channel address + + 0 + 4 + read-write + + + STATTX + Status bits, for transmission transfers + + 4 + 2 + write-only + + + DTOGTX + Data toggle, for transmission transfers + + 6 + 1 + write-only + + + VTTX + Valid USB transaction transmitted + + 7 + 1 + read-write + + + EPKIND + endpoint/channel kind + + 8 + 1 + read-write + + + UTYPE + USB type of transaction + + 9 + 2 + read-write + + + SETUP + Setup transaction completed + + 11 + 1 + read-only + + + STATRX + Status bits, for reception transfers + + 12 + 2 + write-only + + + DTOGRX + Data Toggle, for reception transfers + + 14 + 1 + write-only + + + VTRX + USB valid transaction received + + 15 + 1 + read-write + + + DEVADDR + Host mode + + 16 + 7 + read-write + + + NAK + Host mode + + 23 + 1 + read-write + + + LS_EP + Low speed endpoint host with HUB only + + 24 + 1 + read-write + + + B_0x0 + Full speed endpoint + 0x0 + + + B_0x1 + Low speed endpoint + 0x1 + + + + + ERR_TX + Received error for an OUT/SETUP transaction + + 25 + 1 + read-write + + + ERR_RX + Received error for an IN transaction + + 26 + 1 + read-write + + + THREE_ERR_TX + Three errors for an OUT or SETUP transaction + + 27 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + THREE_ERR_RX + Three errors for an IN transaction + + 29 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + + + USB_CHEP7R + USB_CHEP7R + USB endpoint/channel 7 register + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EA + endpoint/channel address + + 0 + 4 + read-write + + + STATTX + Status bits, for transmission transfers + + 4 + 2 + write-only + + + DTOGTX + Data toggle, for transmission transfers + + 6 + 1 + write-only + + + VTTX + Valid USB transaction transmitted + + 7 + 1 + read-write + + + EPKIND + endpoint/channel kind + + 8 + 1 + read-write + + + UTYPE + USB type of transaction + + 9 + 2 + read-write + + + SETUP + Setup transaction completed + + 11 + 1 + read-only + + + STATRX + Status bits, for reception transfers + + 12 + 2 + write-only + + + DTOGRX + Data Toggle, for reception transfers + + 14 + 1 + write-only + + + VTRX + USB valid transaction received + + 15 + 1 + read-write + + + DEVADDR + Host mode + + 16 + 7 + read-write + + + NAK + Host mode + + 23 + 1 + read-write + + + LS_EP + Low speed endpoint host with HUB only + + 24 + 1 + read-write + + + B_0x0 + Full speed endpoint + 0x0 + + + B_0x1 + Low speed endpoint + 0x1 + + + + + ERR_TX + Received error for an OUT/SETUP transaction + + 25 + 1 + read-write + + + ERR_RX + Received error for an IN transaction + + 26 + 1 + read-write + + + THREE_ERR_TX + Three errors for an OUT or SETUP transaction + + 27 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + THREE_ERR_RX + Three errors for an IN transaction + + 29 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + + + USB_CNTR + USB_CNTR + USB control register + 0x40 + 0x20 + read-write + 0x00000003 + 0xFFFFFFFF + + + USBRST + USB Reset + + 0 + 1 + read-write + + + B_0x0_DEVICE_MODE + No effect + 0x0 + + + B_0x1_DEVICE_MODE + USB core is under reset + 0x1 + + + + + PDWN + Power down + + 1 + 1 + read-write + + + B_0x0 + Exit power down + 0x0 + + + B_0x1 + Enter power down mode + 0x1 + + + + + SUSPRDY + Suspend state effective + + 2 + 1 + read-only + + + B_0x0 + Normal operation + 0x0 + + + B_0x1 + Suspend state + 0x1 + + + + + SUSPEN + Suspend state enable + + 3 + 1 + read-write + + + B_0x0_DEVICE_MODE + No effect + 0x0 + + + B_0x1_DEVICE_MODE + Enter L1/L2 suspend + 0x1 + + + + + L2RES + L2 remote wake-up / resume driver + + 4 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Send L2 resume signaling to device + 0x1 + + + + + L1RES + L1 remote wake-up / resume driver + + 5 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Send 50us remote-wake-up signaling to host + 0x1 + + + + + L1REQM + LPM L1 state request interrupt mask + 7 + 1 + read-write + + + B_0x0 + LPM L1 state request (L1REQ) interrupt disabled. + 0x0 + + + B_0x1 + L1REQ interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + ESOFM + Expected start of frame interrupt mask + 8 + 1 + read-write + + + B_0x0 + Expected start of frame (ESOF) interrupt disabled. + 0x0 + + + B_0x1 + ESOF interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + SOFM + Start of frame interrupt mask + 9 + 1 + read-write + + + B_0x0 + SOF interrupt disabled. + 0x0 + + + B_0x1 + SOF interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + RST_DCONM + USB reset request (Device mode) or device connect/disconnect (Host mode) interrupt mask + 10 + 1 + read-write + + + B_0x0 + RESET interrupt disabled. + 0x0 + + + B_0x1 + RESET interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + SUSPM + Suspend mode interrupt mask + 11 + 1 + read-write + + + B_0x0 + Suspend mode request (SUSP) interrupt disabled. + 0x0 + + + B_0x1 + SUSP interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + WKUPM + Wake-up interrupt mask + 12 + 1 + read-write + + + B_0x0 + WKUP interrupt disabled. + 0x0 + + + B_0x1 + WKUP interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + ERRM + Error interrupt mask + 13 + 1 + read-write + + + B_0x0 + ERR interrupt disabled. + 0x0 + + + B_0x1 + ERR interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + PMAOVRM + Packet memory area over / underrun interrupt mask + 14 + 1 + read-write + + + B_0x0 + PMAOVR interrupt disabled. + 0x0 + + + B_0x1 + PMAOVR interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + CTRM + Correct transfer interrupt mask + 15 + 1 + read-write + + + B_0x0 + Correct transfer (CTR) interrupt disabled. + 0x0 + + + B_0x1 + CTR interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + THR512M + 512 byte threshold interrupt mask + 16 + 1 + read-write + + + B_0x0 + 512 byte threshold interrupt disabled + 0x0 + + + B_0x1 + 512 byte threshold interrupt enabled + 0x1 + + + + + DDISCM + Device disconnection mask + + 17 + 1 + read-write + + + B_0x0 + Device disconnection interrupt disabled + 0x0 + + + B_0x1 + Device disconnection interrupt enabled + 0x1 + + + + + HOST + HOST mode + + 31 + 1 + read-write + + + B_0x0 + USB Device function + 0x0 + + + B_0x1 + USB host function + 0x1 + + + + + + + USB_ISTR + USB_ISTR + USB interrupt status register + 0x44 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IDN + Device Endpoint / host channel identification number + + 0 + 4 + read-only + + + DIR + Direction of transaction + + 4 + 1 + read-only + + + L1REQ + LPM L1 state request + + 7 + 1 + read-write + + + ESOF + Expected start of frame + + 8 + 1 + read-write + + + SOF + Start of frame + + 9 + 1 + read-write + + + RST_DCON + USB reset request (Device mode) or device connect/disconnect (Host mode) + + 10 + 1 + read-write + + + SUSP + Suspend mode request + + 11 + 1 + read-write + + + WKUP + Wake-up + + 12 + 1 + read-write + + + ERR + Error + + 13 + 1 + read-write + + + PMAOVR + Packet memory area over / underrun + + 14 + 1 + read-write + + + CTR + Completed transfer in host mode + + 15 + 1 + read-only + + + THR512 + 512 byte threshold interrupt + + 16 + 1 + read-write + + + DDISC + Device connection + + 17 + 1 + read-write + + + DCON_STAT + Device connection status + + 29 + 1 + read-only + + + B_0x0 + No device connected + 0x0 + + + B_0x1 + FS or LS device connected to the host + 0x1 + + + + + LS_DCON + Low speed device connected + + 30 + 1 + read-only + + + + + USB_FNR + USB_FNR + USB frame number register + 0x48 + 0x20 + read-only + 0x00000000 + 0xFFFFF000 + + + FN + Frame number + + 0 + 11 + read-only + + + LSOF + Lost SOF + + 11 + 2 + read-only + + + LCK + Locked + + 13 + 1 + read-only + + + RXDM + Receive data - line status + + 14 + 1 + read-only + + + RXDP + Receive data + line status + + 15 + 1 + read-only + + + + + USB_DADDR + USB_DADDR + USB Device address + 0x4C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ADD + Device address + + 0 + 7 + read-write + + + EF + Enable function + + 7 + 1 + read-write + + + + + USB_LPMCSR + USB_LPMCSR + LPM control and status register + 0x54 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LPMEN + LPM support enable + + 0 + 1 + read-write + + + LPMACK + LPM token acknowledge enable + + 1 + 1 + read-write + + + B_0x0 + the valid LPM token is NYET. + 0x0 + + + B_0x1 + the valid LPM token is ACK. + 0x1 + + + + + REMWAKE + bRemoteWake value + + 3 + 1 + read-only + + + BESL + BESL value + + 4 + 4 + read-only + + + + + USB_BCDR + USB_BCDR + Battery charging detector + 0x58 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BCDEN + Battery charging detector (BCD) enable + + 0 + 1 + read-write + + + DCDEN + Data contact detection (DCD) mode enable + + 1 + 1 + read-write + + + PDEN + Primary detection (PD) mode enable + + 2 + 1 + read-write + + + SDEN + Secondary detection (SD) mode enable + + 3 + 1 + read-write + + + DCDET + Data contact detection (DCD) status + + 4 + 1 + read-only + + + B_0x0 + data lines contact not detected. + 0x0 + + + B_0x1 + data lines contact detected. + 0x1 + + + + + PDET + Primary detection (PD) status + + 5 + 1 + read-only + + + B_0x0 + no BCD support detected (connected to SDP or proprietary device). + 0x0 + + + B_0x1 + BCD support detected (connected to ACA, CDP or DCP). + 0x1 + + + + + SDET + Secondary detection (SD) status + + 6 + 1 + read-only + + + B_0x0 + CDP detected. + 0x0 + + + B_0x1 + DCP detected. + 0x1 + + + + + PS2DET + DM pull-up detection status + + 7 + 1 + read-only + + + B_0x0 + Normal port detected (connected to SDP, ACA, CDP or DCP). + 0x0 + + + B_0x1 + PS2 port or proprietary charger detected. + 0x1 + + + + + DPPU_DPD + DP pull-up / DPDM pull-down + + 15 + 1 + read-write + + + + + + + USB_S + 0X50016000 + + + USBSRAM + USBSRAM address block description + USBSRAM + 0x40016400 + + 0x0 + 0x40 + registers + + + + USBSRAM_CHEP_TXRXBD_0 + USBSRAM_CHEP_TXRXBD_0 + Channel/endpoint transmit buffer descriptor 0 + 0x0 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_TX + Transmission buffer address + + 0 + 16 + read-write + + + COUNT_TX + Transmission byte count + + 16 + 10 + read-write + + + + + USBSRAM_CHEP_TXRXBD_0_ALTERNATE1 + USBSRAM_CHEP_TXRXBD_0_ALTERNATE1 + Channel/endpoint receive buffer descriptor 0 + USBSRAM_CHEP_TXRXBD_0 + 0x0 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_RX + Reception buffer address + + 0 + 16 + read-write + + + COUNT_RX + Reception byte count + + 16 + 10 + read-only + + + NUM_BLOCK + Number of blocks + + 26 + 5 + read-write + + + BLSIZE + Block size + + 31 + 1 + read-write + + + + + USBSRAM_CHEP_RXTXBD_0 + USBSRAM_CHEP_RXTXBD_0 + Channel/endpoint receive buffer descriptor 0 + 0x4 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_RX + Reception buffer address + + 0 + 16 + read-write + + + COUNT_RX + Reception byte count + + 16 + 10 + read-only + + + NUM_BLOCK + Number of blocks + + 26 + 5 + read-write + + + BLSIZE + Block size + + 31 + 1 + read-write + + + + + USBSRAM_CHEP_RXTXBD_0_ALTERNATE1 + USBSRAM_CHEP_RXTXBD_0_ALTERNATE1 + Channel/endpoint transmit buffer descriptor 0 + USBSRAM_CHEP_RXTXBD_0 + 0x4 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_TX + Transmission buffer address + + 0 + 16 + read-write + + + COUNT_TX + Transmission byte count + + 16 + 10 + read-write + + + + + USBSRAM_CHEP_TXRXBD_1 + USBSRAM_CHEP_TXRXBD_1 + Channel/endpoint transmit buffer descriptor 1 + 0x8 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_TX + Transmission buffer address + + 0 + 16 + read-write + + + COUNT_TX + Transmission byte count + + 16 + 10 + read-write + + + + + USBSRAM_CHEP_TXRXBD_1_ALTERNATE1 + USBSRAM_CHEP_TXRXBD_1_ALTERNATE1 + Channel/endpoint receive buffer descriptor 1 + USBSRAM_CHEP_TXRXBD_1 + 0x8 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_RX + Reception buffer address + + 0 + 16 + read-write + + + COUNT_RX + Reception byte count + + 16 + 10 + read-only + + + NUM_BLOCK + Number of blocks + + 26 + 5 + read-write + + + BLSIZE + Block size + + 31 + 1 + read-write + + + + + USBSRAM_CHEP_RXTXBD_1 + USBSRAM_CHEP_RXTXBD_1 + Channel/endpoint receive buffer descriptor 1 + 0xC + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_RX + Reception buffer address + + 0 + 16 + read-write + + + COUNT_RX + Reception byte count + + 16 + 10 + read-only + + + NUM_BLOCK + Number of blocks + + 26 + 5 + read-write + + + BLSIZE + Block size + + 31 + 1 + read-write + + + + + USBSRAM_CHEP_RXTXBD_1_ALTERNATE1 + USBSRAM_CHEP_RXTXBD_1_ALTERNATE1 + Channel/endpoint transmit buffer descriptor 1 + USBSRAM_CHEP_RXTXBD_1 + 0xC + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_TX + Transmission buffer address + + 0 + 16 + read-write + + + COUNT_TX + Transmission byte count + + 16 + 10 + read-write + + + + + USBSRAM_CHEP_TXRXBD_2 + USBSRAM_CHEP_TXRXBD_2 + Channel/endpoint transmit buffer descriptor 2 + 0x10 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_TX + Transmission buffer address + + 0 + 16 + read-write + + + COUNT_TX + Transmission byte count + + 16 + 10 + read-write + + + + + USBSRAM_CHEP_TXRXBD_2_ALTERNATE1 + USBSRAM_CHEP_TXRXBD_2_ALTERNATE1 + Channel/endpoint receive buffer descriptor 2 + USBSRAM_CHEP_TXRXBD_2 + 0x10 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_RX + Reception buffer address + + 0 + 16 + read-write + + + COUNT_RX + Reception byte count + + 16 + 10 + read-only + + + NUM_BLOCK + Number of blocks + + 26 + 5 + read-write + + + BLSIZE + Block size + + 31 + 1 + read-write + + + + + USBSRAM_CHEP_RXTXBD_2 + USBSRAM_CHEP_RXTXBD_2 + Channel/endpoint receive buffer descriptor 2 + 0x14 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_RX + Reception buffer address + + 0 + 16 + read-write + + + COUNT_RX + Reception byte count + + 16 + 10 + read-only + + + NUM_BLOCK + Number of blocks + + 26 + 5 + read-write + + + BLSIZE + Block size + + 31 + 1 + read-write + + + + + USBSRAM_CHEP_RXTXBD_2_ALTERNATE1 + USBSRAM_CHEP_RXTXBD_2_ALTERNATE1 + Channel/endpoint transmit buffer descriptor 2 + USBSRAM_CHEP_RXTXBD_2 + 0x14 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_TX + Transmission buffer address + + 0 + 16 + read-write + + + COUNT_TX + Transmission byte count + + 16 + 10 + read-write + + + + + USBSRAM_CHEP_TXRXBD_3 + USBSRAM_CHEP_TXRXBD_3 + Channel/endpoint transmit buffer descriptor 3 + 0x18 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_TX + Transmission buffer address + + 0 + 16 + read-write + + + COUNT_TX + Transmission byte count + + 16 + 10 + read-write + + + + + USBSRAM_CHEP_TXRXBD_3_ALTERNATE1 + USBSRAM_CHEP_TXRXBD_3_ALTERNATE1 + Channel/endpoint receive buffer descriptor 3 + USBSRAM_CHEP_TXRXBD_3 + 0x18 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_RX + Reception buffer address + + 0 + 16 + read-write + + + COUNT_RX + Reception byte count + + 16 + 10 + read-only + + + NUM_BLOCK + Number of blocks + + 26 + 5 + read-write + + + BLSIZE + Block size + + 31 + 1 + read-write + + + + + USBSRAM_CHEP_RXTXBD_3 + USBSRAM_CHEP_RXTXBD_3 + Channel/endpoint receive buffer descriptor 3 + 0x1C + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_RX + Reception buffer address + + 0 + 16 + read-write + + + COUNT_RX + Reception byte count + + 16 + 10 + read-only + + + NUM_BLOCK + Number of blocks + + 26 + 5 + read-write + + + BLSIZE + Block size + + 31 + 1 + read-write + + + + + USBSRAM_CHEP_RXTXBD_3_ALTERNATE1 + USBSRAM_CHEP_RXTXBD_3_ALTERNATE1 + Channel/endpoint transmit buffer descriptor 3 + USBSRAM_CHEP_RXTXBD_3 + 0x1C + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_TX + Transmission buffer address + + 0 + 16 + read-write + + + COUNT_TX + Transmission byte count + + 16 + 10 + read-write + + + + + USBSRAM_CHEP_TXRXBD_4 + USBSRAM_CHEP_TXRXBD_4 + Channel/endpoint transmit buffer descriptor 4 + 0x20 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_TX + Transmission buffer address + + 0 + 16 + read-write + + + COUNT_TX + Transmission byte count + + 16 + 10 + read-write + + + + + USBSRAM_CHEP_TXRXBD_4_ALTERNATE1 + USBSRAM_CHEP_TXRXBD_4_ALTERNATE1 + Channel/endpoint receive buffer descriptor 4 + USBSRAM_CHEP_TXRXBD_4 + 0x20 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_RX + Reception buffer address + + 0 + 16 + read-write + + + COUNT_RX + Reception byte count + + 16 + 10 + read-only + + + NUM_BLOCK + Number of blocks + + 26 + 5 + read-write + + + BLSIZE + Block size + + 31 + 1 + read-write + + + + + USBSRAM_CHEP_RXTXBD_4 + USBSRAM_CHEP_RXTXBD_4 + Channel/endpoint receive buffer descriptor 4 + 0x24 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_RX + Reception buffer address + + 0 + 16 + read-write + + + COUNT_RX + Reception byte count + + 16 + 10 + read-only + + + NUM_BLOCK + Number of blocks + + 26 + 5 + read-write + + + BLSIZE + Block size + + 31 + 1 + read-write + + + + + USBSRAM_CHEP_RXTXBD_4_ALTERNATE1 + USBSRAM_CHEP_RXTXBD_4_ALTERNATE1 + Channel/endpoint transmit buffer descriptor 4 + USBSRAM_CHEP_RXTXBD_4 + 0x24 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_TX + Transmission buffer address + + 0 + 16 + read-write + + + COUNT_TX + Transmission byte count + + 16 + 10 + read-write + + + + + USBSRAM_CHEP_TXRXBD_5 + USBSRAM_CHEP_TXRXBD_5 + Channel/endpoint transmit buffer descriptor 5 + 0x28 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_TX + Transmission buffer address + + 0 + 16 + read-write + + + COUNT_TX + Transmission byte count + + 16 + 10 + read-write + + + + + USBSRAM_CHEP_TXRXBD_5_ALTERNATE1 + USBSRAM_CHEP_TXRXBD_5_ALTERNATE1 + Channel/endpoint receive buffer descriptor 5 + USBSRAM_CHEP_TXRXBD_5 + 0x28 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_RX + Reception buffer address + + 0 + 16 + read-write + + + COUNT_RX + Reception byte count + + 16 + 10 + read-only + + + NUM_BLOCK + Number of blocks + + 26 + 5 + read-write + + + BLSIZE + Block size + + 31 + 1 + read-write + + + + + USBSRAM_CHEP_RXTXBD_5 + USBSRAM_CHEP_RXTXBD_5 + Channel/endpoint receive buffer descriptor 5 + 0x2C + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_RX + Reception buffer address + + 0 + 16 + read-write + + + COUNT_RX + Reception byte count + + 16 + 10 + read-only + + + NUM_BLOCK + Number of blocks + + 26 + 5 + read-write + + + BLSIZE + Block size + + 31 + 1 + read-write + + + + + USBSRAM_CHEP_RXTXBD_5_ALTERNATE1 + USBSRAM_CHEP_RXTXBD_5_ALTERNATE1 + Channel/endpoint transmit buffer descriptor 5 + USBSRAM_CHEP_RXTXBD_5 + 0x2C + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_TX + Transmission buffer address + + 0 + 16 + read-write + + + COUNT_TX + Transmission byte count + + 16 + 10 + read-write + + + + + USBSRAM_CHEP_TXRXBD_6 + USBSRAM_CHEP_TXRXBD_6 + Channel/endpoint transmit buffer descriptor 6 + 0x30 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_TX + Transmission buffer address + + 0 + 16 + read-write + + + COUNT_TX + Transmission byte count + + 16 + 10 + read-write + + + + + USBSRAM_CHEP_TXRXBD_6_ALTERNATE1 + USBSRAM_CHEP_TXRXBD_6_ALTERNATE1 + Channel/endpoint receive buffer descriptor 6 + USBSRAM_CHEP_TXRXBD_6 + 0x30 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_RX + Reception buffer address + + 0 + 16 + read-write + + + COUNT_RX + Reception byte count + + 16 + 10 + read-only + + + NUM_BLOCK + Number of blocks + + 26 + 5 + read-write + + + BLSIZE + Block size + + 31 + 1 + read-write + + + + + USBSRAM_CHEP_RXTXBD_6 + USBSRAM_CHEP_RXTXBD_6 + Channel/endpoint receive buffer descriptor 6 + 0x34 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_RX + Reception buffer address + + 0 + 16 + read-write + + + COUNT_RX + Reception byte count + + 16 + 10 + read-only + + + NUM_BLOCK + Number of blocks + + 26 + 5 + read-write + + + BLSIZE + Block size + + 31 + 1 + read-write + + + + + USBSRAM_CHEP_RXTXBD_6_ALTERNATE1 + USBSRAM_CHEP_RXTXBD_6_ALTERNATE1 + Channel/endpoint transmit buffer descriptor 6 + USBSRAM_CHEP_RXTXBD_6 + 0x34 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_TX + Transmission buffer address + + 0 + 16 + read-write + + + COUNT_TX + Transmission byte count + + 16 + 10 + read-write + + + + + USBSRAM_CHEP_TXRXBD_7 + USBSRAM_CHEP_TXRXBD_7 + Channel/endpoint transmit buffer descriptor 7 + 0x38 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_TX + Transmission buffer address + + 0 + 16 + read-write + + + COUNT_TX + Transmission byte count + + 16 + 10 + read-write + + + + + USBSRAM_CHEP_TXRXBD_7_ALTERNATE1 + USBSRAM_CHEP_TXRXBD_7_ALTERNATE1 + Channel/endpoint receive buffer descriptor 7 + USBSRAM_CHEP_TXRXBD_7 + 0x38 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_RX + Reception buffer address + + 0 + 16 + read-write + + + COUNT_RX + Reception byte count + + 16 + 10 + read-only + + + NUM_BLOCK + Number of blocks + + 26 + 5 + read-write + + + BLSIZE + Block size + + 31 + 1 + read-write + + + + + USBSRAM_CHEP_RXTXBD_7 + USBSRAM_CHEP_RXTXBD_7 + Channel/endpoint receive buffer descriptor 7 + 0x3C + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_RX + Reception buffer address + + 0 + 16 + read-write + + + COUNT_RX + Reception byte count + + 16 + 10 + read-only + + + NUM_BLOCK + Number of blocks + + 26 + 5 + read-write + + + BLSIZE + Block size + + 31 + 1 + read-write + + + + + USBSRAM_CHEP_RXTXBD_7_ALTERNATE1 + USBSRAM_CHEP_RXTXBD_7_ALTERNATE1 + Channel/endpoint transmit buffer descriptor 7 + USBSRAM_CHEP_RXTXBD_7 + 0x3C + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_TX + Transmission buffer address + + 0 + 16 + read-write + + + COUNT_TX + Transmission byte count + + 16 + 10 + read-write + + + + + + + USBSRAM_S + 0x50016400 + + + VREFBUF + VREFBUF address block description + VREFBUF + 0x44007400 + + 0x0 + 0x8 + registers + + + + VREFBUF_CSR + VREFBUF_CSR + VREFBUF control and status register + 0x00 + 0x20 + read-write + 0x00000002 + 0xFFFFFFFF + + + ENVR + Voltage reference buffer mode enable + + 0 + 1 + read-write + + + B_0x0 + Internal voltage reference mode disable (external voltage reference mode). + 0x0 + + + B_0x1 + Internal voltage reference mode (reference buffer enable or hold mode) enable. + 0x1 + + + + + HIZ + High impedance mode + + 1 + 1 + read-write + + + B_0x0 + Vless thansub>REF+less than/sub> pin is internally connected to the voltage reference buffer output. + 0x0 + + + B_0x1 + Vless thansub>REF+less than/sub> pin is high impedance. + 0x1 + + + + + VRR + Voltage reference buffer ready + 3 + 1 + read-only + + + B_0x0 + the voltage reference buffer output is not ready. + 0x0 + + + B_0x1 + the voltage reference buffer output reached the requested level. + 0x1 + + + + + VRS + Voltage reference scale + + 4 + 3 + read-write + + + + + VREFBUF_CCR + VREFBUF_CCR + VREFBUF calibration control register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFF00 + + + TRIM + Trimming code + + 0 + 6 + read-write + + + + + + + VREFBUF_S + 0X54007400 + + + WWDG + WWDG address block description + WWDG + 0x40002c00 + + 0x0 + 0xC + registers + + + WWDG + Window Watchdog interrupt + 0 + + + + WWDG_CR + WWDG_CR + WWDG control register + 0x000 + 0x20 + read-write + 0x0000007F + 0xFFFFFFFF + + + T + 7-bit counter (MSB to LSB) + + 0 + 7 + read-write + + + WDGA + Activation bit + + 7 + 1 + read-write + + + B_0x0 + Watchdog disabled + 0x0 + + + B_0x1 + Watchdog enabled + 0x1 + + + + + + + WWDG_CFR + WWDG_CFR + WWDG configuration register + 0x004 + 0x20 + read-write + 0x0000007F + 0xFFFFFFFF + + + W + 7-bit window value + + 0 + 7 + read-write + + + EWI + Early wake-up interrupt enable + + 9 + 1 + read-write + + + WDGTB + Timer base + + 11 + 3 + read-write + + + B_0x0 + CK counter clock (PCLK div 4096) div 1 + 0x0 + + + B_0x1 + CK counter clock (PCLK div 4096) div 2 + 0x1 + + + B_0x2 + CK counter clock (PCLK div 4096) div 4 + 0x2 + + + B_0x3 + CK counter clock (PCLK div 4096) div 8 + 0x3 + + + B_0x4 + CK counter clock (PCLK div 4096) div 16 + 0x4 + + + B_0x5 + CK counter clock (PCLK div 4096) div 32 + 0x5 + + + B_0x6 + CK counter clock (PCLK div 4096) div 64 + 0x6 + + + B_0x7 + CK counter clock (PCLK div 4096) div 128 + 0x7 + + + + + + + WWDG_SR + WWDG_SR + WWDG status register + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EWIF + Early wake-up interrupt flag + + 0 + 1 + read-write + + + + + + + WWDG_S + 0X50002C00 + + + diff --git a/Lib/Vendor/SVD/STM32L476.svd b/Lib/Vendor/SVD/STM32L476.svd new file mode 100644 index 000000000..94740dbed --- /dev/null +++ b/Lib/Vendor/SVD/STM32L476.svd @@ -0,0 +1,56176 @@ + + + + STM32L476 + 1.8 + STM32L476 + + CM4 + r0p1 + little + true + true + 4 + false + + 8 + 32 + 0x20 + 0x0 + 0xFFFFFFFF + + + DAC + Digital-to-analog converter + DAC + 0x40007400 + + 0x0 + 0x400 + registers + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + EN1 + DAC channel1 enable + 0 + 1 + + + TEN1 + DAC channel1 trigger enable + 2 + 1 + + + TSEL1 + DAC channel1 trigger selection + 3 + 3 + + + WAVE1 + DAC channel1 noise/triangle wave generation enable + 6 + 2 + + + MAMP1 + DAC channel1 mask/amplitude selector + 8 + 4 + + + DMAEN1 + DAC channel1 DMA enable + 12 + 1 + + + DMAUDRIE1 + DAC channel1 DMA Underrun Interrupt enable + 13 + 1 + + + CEN1 + DAC Channel 1 calibration enable + 14 + 1 + + + EN2 + DAC channel2 enable + 16 + 1 + + + TEN2 + DAC channel2 trigger enable + 18 + 1 + + + TSEL2 + DAC channel2 trigger selection + 19 + 3 + + + WAVE2 + DAC channel2 noise/triangle wave generation enable + 22 + 2 + + + MAMP2 + DAC channel2 mask/amplitude selector + 24 + 4 + + + DMAEN2 + DAC channel2 DMA enable + 28 + 1 + + + DMAUDRIE2 + DAC channel2 DMA underrun interrupt enable + 29 + 1 + + + CEN2 + DAC Channel 2 calibration enable + 30 + 1 + + + + + SWTRIGR + SWTRIGR + software trigger register + 0x4 + 0x20 + write-only + 0x00000000 + + + SWTRIG1 + DAC channel1 software trigger + 0 + 1 + + + SWTRIG2 + DAC channel2 software trigger + 1 + 1 + + + + + DHR12R1 + DHR12R1 + channel1 12-bit right-aligned data holding register + 0x8 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit right-aligned data + 0 + 12 + + + + + DHR12L1 + DHR12L1 + channel1 12-bit left-aligned data holding register + 0xC + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit left-aligned data + 4 + 12 + + + + + DHR8R1 + DHR8R1 + channel1 8-bit right-aligned data holding register + 0x10 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 8-bit right-aligned data + 0 + 8 + + + + + DHR12R2 + DHR12R2 + channel2 12-bit right aligned data holding register + 0x14 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit right-aligned data + 0 + 12 + + + + + DHR12L2 + DHR12L2 + channel2 12-bit left aligned data holding register + 0x18 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit left-aligned data + 4 + 12 + + + + + DHR8R2 + DHR8R2 + channel2 8-bit right-aligned data holding register + 0x1C + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 8-bit right-aligned data + 0 + 8 + + + + + DHR12RD + DHR12RD + Dual DAC 12-bit right-aligned data holding register + 0x20 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit right-aligned data + 0 + 12 + + + DACC2DHR + DAC channel2 12-bit right-aligned data + 16 + 12 + + + + + DHR12LD + DHR12LD + DUAL DAC 12-bit left aligned data holding register + 0x24 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit left-aligned data + 4 + 12 + + + DACC2DHR + DAC channel2 12-bit left-aligned data + 20 + 12 + + + + + DHR8RD + DHR8RD + DUAL DAC 8-bit right aligned data holding register + 0x28 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 8-bit right-aligned data + 0 + 8 + + + DACC2DHR + DAC channel2 8-bit right-aligned data + 8 + 8 + + + + + DOR1 + DOR1 + channel1 data output register + 0x2C + 0x20 + read-only + 0x00000000 + + + DACC1DOR + DAC channel1 data output + 0 + 12 + + + + + DOR2 + DOR2 + channel2 data output register + 0x30 + 0x20 + read-only + 0x00000000 + + + DACC2DOR + DAC channel2 data output + 0 + 12 + + + + + SR + SR + status register + 0x34 + 0x20 + 0x00000000 + + + DMAUDR1 + DAC channel1 DMA underrun flag + 13 + 1 + read-write + + + CAL_FLAG1 + DAC Channel 1 calibration offset status + 14 + 1 + read-only + + + BWST1 + DAC Channel 1 busy writing sample time flag + 15 + 1 + read-only + + + DMAUDR2 + DAC channel2 DMA underrun flag + 29 + 1 + read-write + + + CAL_FLAG2 + DAC Channel 2 calibration offset status + 30 + 1 + read-only + + + BWST2 + DAC Channel 2 busy writing sample time flag + 31 + 1 + read-only + + + + + CCR + CCR + calibration control register + 0x38 + 0x20 + read-write + 0x00000000 + + + OTRIM1 + DAC Channel 1 offset trimming value + 0 + 5 + + + OTRIM2 + DAC Channel 2 offset trimming value + 16 + 5 + + + + + MCR + MCR + mode control register + 0x3C + 0x20 + read-write + 0x00000000 + + + MODE1 + DAC Channel 1 mode + 0 + 3 + + + MODE2 + DAC Channel 2 mode + 16 + 3 + + + + + SHSR1 + SHSR1 + Sample and Hold sample time register 1 + 0x40 + 0x20 + read-write + 0x00000000 + + + TSAMPLE1 + DAC Channel 1 sample Time + 0 + 10 + + + + + SHSR2 + SHSR2 + Sample and Hold sample time register 2 + 0x44 + 0x20 + read-write + 0x00000000 + + + TSAMPLE2 + DAC Channel 2 sample Time + 0 + 10 + + + + + SHHR + SHHR + Sample and Hold hold time register + 0x48 + 0x20 + read-write + 0x00010001 + + + THOLD1 + DAC Channel 1 hold Time + 0 + 10 + + + THOLD2 + DAC Channel 2 hold time + 16 + 10 + + + + + SHRR + SHRR + Sample and Hold refresh time register + 0x4C + 0x20 + read-write + 0x00000001 + + + TREFRESH1 + DAC Channel 1 refresh Time + 0 + 8 + + + TREFRESH2 + DAC Channel 2 refresh Time + 16 + 8 + + + + + + + DMA1 + Direct memory access controller + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA1_CH1 + DMA1 Channel1 global interrupt + 11 + + + DMA1_CH2 + DMA1 Channel2 global interrupt + 12 + + + DMA1_CH3 + DMA1 Channel3 interrupt + 13 + + + DMA1_CH4 + DMA1 Channel4 interrupt + 14 + + + DMA1_CH5 + DMA1 Channel5 interrupt + 15 + + + DMA1_CH6 + DMA1 Channel6 interrupt + 16 + + + DMA1_CH7 + DMA1 Channel 7 interrupt + 17 + + + + ISR + ISR + interrupt status register + 0x0 + 0x20 + read-only + 0x00000000 + + + TEIF7 + Channel x transfer error flag (x = 1 ..7) + 27 + 1 + + + HTIF7 + Channel x half transfer flag (x = 1 ..7) + 26 + 1 + + + TCIF7 + Channel x transfer complete flag (x = 1 ..7) + 25 + 1 + + + GIF7 + Channel x global interrupt flag (x = 1 ..7) + 24 + 1 + + + TEIF6 + Channel x transfer error flag (x = 1 ..7) + 23 + 1 + + + HTIF6 + Channel x half transfer flag (x = 1 ..7) + 22 + 1 + + + TCIF6 + Channel x transfer complete flag (x = 1 ..7) + 21 + 1 + + + GIF6 + Channel x global interrupt flag (x = 1 ..7) + 20 + 1 + + + TEIF5 + Channel x transfer error flag (x = 1 ..7) + 19 + 1 + + + HTIF5 + Channel x half transfer flag (x = 1 ..7) + 18 + 1 + + + TCIF5 + Channel x transfer complete flag (x = 1 ..7) + 17 + 1 + + + GIF5 + Channel x global interrupt flag (x = 1 ..7) + 16 + 1 + + + TEIF4 + Channel x transfer error flag (x = 1 ..7) + 15 + 1 + + + HTIF4 + Channel x half transfer flag (x = 1 ..7) + 14 + 1 + + + TCIF4 + Channel x transfer complete flag (x = 1 ..7) + 13 + 1 + + + GIF4 + Channel x global interrupt flag (x = 1 ..7) + 12 + 1 + + + TEIF3 + Channel x transfer error flag (x = 1 ..7) + 11 + 1 + + + HTIF3 + Channel x half transfer flag (x = 1 ..7) + 10 + 1 + + + TCIF3 + Channel x transfer complete flag (x = 1 ..7) + 9 + 1 + + + GIF3 + Channel x global interrupt flag (x = 1 ..7) + 8 + 1 + + + TEIF2 + Channel x transfer error flag (x = 1 ..7) + 7 + 1 + + + HTIF2 + Channel x half transfer flag (x = 1 ..7) + 6 + 1 + + + TCIF2 + Channel x transfer complete flag (x = 1 ..7) + 5 + 1 + + + GIF2 + Channel x global interrupt flag (x = 1 ..7) + 4 + 1 + + + TEIF1 + Channel x transfer error flag (x = 1 ..7) + 3 + 1 + + + HTIF1 + Channel x half transfer flag (x = 1 ..7) + 2 + 1 + + + TCIF1 + Channel x transfer complete flag (x = 1 ..7) + 1 + 1 + + + GIF1 + Channel x global interrupt flag (x = 1 ..7) + 0 + 1 + + + + + IFCR + IFCR + interrupt flag clear register + 0x4 + 0x20 + write-only + 0x00000000 + + + CTEIF7 + Channel x transfer error clear (x = 1 ..7) + 27 + 1 + + + CHTIF7 + Channel x half transfer clear (x = 1 ..7) + 26 + 1 + + + CTCIF7 + Channel x transfer complete clear (x = 1 ..7) + 25 + 1 + + + CGIF7 + Channel x global interrupt clear (x = 1 ..7) + 24 + 1 + + + CTEIF6 + Channel x transfer error clear (x = 1 ..7) + 23 + 1 + + + CHTIF6 + Channel x half transfer clear (x = 1 ..7) + 22 + 1 + + + CTCIF6 + Channel x transfer complete clear (x = 1 ..7) + 21 + 1 + + + CGIF6 + Channel x global interrupt clear (x = 1 ..7) + 20 + 1 + + + CTEIF5 + Channel x transfer error clear (x = 1 ..7) + 19 + 1 + + + CHTIF5 + Channel x half transfer clear (x = 1 ..7) + 18 + 1 + + + CTCIF5 + Channel x transfer complete clear (x = 1 ..7) + 17 + 1 + + + CGIF5 + Channel x global interrupt clear (x = 1 ..7) + 16 + 1 + + + CTEIF4 + Channel x transfer error clear (x = 1 ..7) + 15 + 1 + + + CHTIF4 + Channel x half transfer clear (x = 1 ..7) + 14 + 1 + + + CTCIF4 + Channel x transfer complete clear (x = 1 ..7) + 13 + 1 + + + CGIF4 + Channel x global interrupt clear (x = 1 ..7) + 12 + 1 + + + CTEIF3 + Channel x transfer error clear (x = 1 ..7) + 11 + 1 + + + CHTIF3 + Channel x half transfer clear (x = 1 ..7) + 10 + 1 + + + CTCIF3 + Channel x transfer complete clear (x = 1 ..7) + 9 + 1 + + + CGIF3 + Channel x global interrupt clear (x = 1 ..7) + 8 + 1 + + + CTEIF2 + Channel x transfer error clear (x = 1 ..7) + 7 + 1 + + + CHTIF2 + Channel x half transfer clear (x = 1 ..7) + 6 + 1 + + + CTCIF2 + Channel x transfer complete clear (x = 1 ..7) + 5 + 1 + + + CGIF2 + Channel x global interrupt clear (x = 1 ..7) + 4 + 1 + + + CTEIF1 + Channel x transfer error clear (x = 1 ..7) + 3 + 1 + + + CHTIF1 + Channel x half transfer clear (x = 1 ..7) + 2 + 1 + + + CTCIF1 + Channel x transfer complete clear (x = 1 ..7) + 1 + 1 + + + CGIF1 + Channel x global interrupt clear (x = 1 ..7) + 0 + 1 + + + + + CCR1 + CCR1 + channel x configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt enable + 3 + 1 + + + HTIE + Half transfer interrupt enable + 2 + 1 + + + TCIE + Transfer complete interrupt enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR1 + CNDTR1 + channel x number of data register + 0xC + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR1 + CPAR1 + channel x peripheral address register + 0x10 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR1 + CMAR1 + channel x memory address register + 0x14 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR2 + CCR2 + channel x configuration register + 0x1C + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt enable + 3 + 1 + + + HTIE + Half transfer interrupt enable + 2 + 1 + + + TCIE + Transfer complete interrupt enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR2 + CNDTR2 + channel x number of data register + 0x20 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR2 + CPAR2 + channel x peripheral address register + 0x24 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR2 + CMAR2 + channel x memory address register + 0x28 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR3 + CCR3 + channel x configuration register + 0x30 + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt enable + 3 + 1 + + + HTIE + Half transfer interrupt enable + 2 + 1 + + + TCIE + Transfer complete interrupt enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR3 + CNDTR3 + channel x number of data register + 0x34 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR3 + CPAR3 + channel x peripheral address register + 0x38 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR3 + CMAR3 + channel x memory address register + 0x3C + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR4 + CCR4 + channel x configuration register + 0x44 + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt enable + 3 + 1 + + + HTIE + Half transfer interrupt enable + 2 + 1 + + + TCIE + Transfer complete interrupt enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR4 + CNDTR4 + channel x number of data register + 0x48 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR4 + CPAR4 + channel x peripheral address register + 0x4C + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR4 + CMAR4 + channel x memory address register + 0x50 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR5 + CCR5 + channel x configuration register + 0x58 + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt enable + 3 + 1 + + + HTIE + Half transfer interrupt enable + 2 + 1 + + + TCIE + Transfer complete interrupt enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR5 + CNDTR5 + channel x number of data register + 0x5C + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR5 + CPAR5 + channel x peripheral address register + 0x60 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR5 + CMAR5 + channel x memory address register + 0x64 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR6 + CCR6 + channel x configuration register + 0x6C + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt enable + 3 + 1 + + + HTIE + Half transfer interrupt enable + 2 + 1 + + + TCIE + Transfer complete interrupt enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR6 + CNDTR6 + channel x number of data register + 0x70 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR6 + CPAR6 + channel x peripheral address register + 0x74 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR6 + CMAR6 + channel x memory address register + 0x78 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR7 + CCR7 + channel x configuration register + 0x80 + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt enable + 3 + 1 + + + HTIE + Half transfer interrupt enable + 2 + 1 + + + TCIE + Transfer complete interrupt enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR7 + CNDTR7 + channel x number of data register + 0x84 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR7 + CPAR7 + channel x peripheral address register + 0x88 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR7 + CMAR7 + channel x memory address register + 0x8C + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CSELR + CSELR + channel selection register + 0xA8 + 0x20 + read-write + 0x00000000 + + + C7S + DMA channel 7 selection + 24 + 4 + + + C6S + DMA channel 6 selection + 20 + 4 + + + C5S + DMA channel 5 selection + 16 + 4 + + + C4S + DMA channel 4 selection + 12 + 4 + + + C3S + DMA channel 3 selection + 8 + 4 + + + C2S + DMA channel 2 selection + 4 + 4 + + + C1S + DMA channel 1 selection + 0 + 4 + + + + + + + DMA2 + 0x40020400 + + DMA2_CH1 + DMA2 Channel 1 global Interrupt + 56 + + + DMA2_CH2 + DMA2 Channel 2 global Interrupt + 57 + + + DMA2_CH3 + DMA2 Channel 3 global Interrupt + 58 + + + DMA2_CH4 + DMA2 Channel 4 global Interrupt + 59 + + + DMA2_CH5 + DMA2 Channel 5 global Interrupt + 60 + + + DMA2_CH6 + DMA2 Channel 6 global Interrupt + 68 + + + DMA2_CH7 + DMA2 Channel 7 global Interrupt + 69 + + + + CRC + Cyclic redundancy check calculation unit + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DR + DR + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DR + Data register bits + 0 + 32 + + + + + IDR + IDR + Independent data register + 0x4 + 0x20 + read-write + 0x00000000 + + + IDR + General-purpose 8-bit data register bits + 0 + 8 + + + + + CR + CR + Control register + 0x8 + 0x20 + 0x00000000 + + + REV_OUT + Reverse output data + 7 + 1 + read-write + + + REV_IN + Reverse input data + 5 + 2 + read-write + + + POLYSIZE + Polynomial size + 3 + 2 + read-write + + + RESET + RESET bit + 0 + 1 + write-only + + + + + INIT + INIT + Initial CRC value + 0x10 + 0x20 + read-write + 0xFFFFFFFF + + + CRC_INIT + Programmable initial CRC value + 0 + 32 + + + + + POL + POL + polynomial + 0x14 + 0x20 + read-write + 0x04C11DB7 + + + Polynomialcoefficients + Programmable polynomial + 0 + 32 + + + + + + + LCD + Liquid crystal display controller + LCD + 0x40002400 + + 0x0 + 0x400 + registers + + + LCD + LCD global interrupt + 78 + + + + LCD_CR + LCD_CR + LCD control register + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LCDEN + LCD controller enable +This bit is set by software to enable the LCD Controller/Driver. It is cleared by software to turn off the LCD at the beginning of the next frame. When the LCD is disabled all COM and SEG pins are driven to V<sub>SS</sub>. + 0 + 1 + read-write + + + B_0x0 + LCD controller disabled + 0x0 + + + B_0x1 + LCD controller enabled + 0x1 + + + + + VSEL + Voltage source selection +The VSEL bit determines the voltage source for the LCD. + 1 + 1 + read-write + + + B_0x0 + Internal source (voltage step-up converter) + 0x0 + + + B_0x1 + External source (VLCD pin) + 0x1 + + + + + DUTY + Duty selection +These bits determine the duty cycle.Unused COM pins can serve as general purpose input pins if COMIN is set. Values 101, 110 and 111 are forbidden. +Others: Reserved + 2 + 3 + read-write + + + B_0x0 + Static duty + 0x0 + + + B_0x1 + 1/2 duty + 0x1 + + + B_0x2 + 1/3 duty + 0x2 + + + B_0x3 + 1/4 duty + 0x3 + + + B_0x4 + 1/8 duty + 0x4 + + + + + BIAS + Bias selector +These bits determine the bias used. Value 11 is forbidden. + 5 + 2 + read-write + + + B_0x0 + Bias 1/4 + 0x0 + + + B_0x1 + Bias 1/2 + 0x1 + + + B_0x2 + Bias 1/3 + 0x2 + + + + + MUX_SEG + Mux segment enable +This bit is used to enable SEG pin remapping. Four SEG pins can be multiplexed with SEG[31:28] or SEG[15:12]. See Sectionm19.3.7. + 7 + 1 + read-write + + + B_0x0 + SEG pin multiplexing disabled + 0x0 + + + B_0x1 + SEG[31:28] are multiplexed with SEG[43:40] + 0x1 + + + + + BUFEN + Voltage output buffer enable +This bit is used to enable/disable the voltage output buffer for higher driving capability. + 8 + 1 + read-write + + + B_0x0 + Output buffer disabled + 0x0 + + + B_0x1 + Output buffer enabled + 0x1 + + + + + + + LCD_FCR + LCD_FCR + LCD frame control register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + HD + High drive enable +This bit is written by software to enable a low resistance divider. Displays with high internal resistance may need a longer drive time to achieve satisfactory contrast. This bit is useful in this case if some additional power consumption can be tolerated. + 0 + 1 + read-write + + + B_0x0 + Permanent high drive disabled + 0x0 + + + B_0x1 + Permanent high drive enabled. When HD=1, then the PON bits have to be programmed tom001. + 0x1 + + + + + SOFIE + Start of frame interrupt enable +This bit is set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + LCD start-of-frame interrupt disabled + 0x0 + + + B_0x1 + LCD start-of-frame interrupt enabled + 0x1 + + + + + UDDIE + Update display done interrupt enable +This bit is set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + LCD Update display done interrupt disabled + 0x0 + + + B_0x1 + LCD Update display done interrupt enabled + 0x1 + + + + + PON + Pulse ON duration +These bits are written by software to define the pulse duration in terms of ck_ps pulses. Amshort pulse leads to lower power consumption, but displays with high internal resistance may need a longer pulse to achieve satisfactory contrast. +Note that the pulse is never longer than one half prescaled LCD clock period. +PON duration example with LCDCLK = 32.768mkHz and PS=0x03: + 4 + 3 + read-write + + + B_0x0 + 0 ms + 0x0 + + + B_0x1 + 244 ms + 0x1 + + + B_0x2 + 488 ms + 0x2 + + + B_0x3 + 782 ms + 0x3 + + + B_0x4 + 976 ms + 0x4 + + + B_0x5 + 1.22 ms + 0x5 + + + B_0x6 + 1.46 ms + 0x6 + + + B_0x7 + 1.71 ms + 0x7 + + + + + DEAD + Dead time duration +These bits are written by software to configure the length of the dead time between frames. During the dead time the COM and SEG voltage levels are held at 0 V to reduce the contrast without modifying the frame rate. +...... + 7 + 3 + read-write + + + B_0x0 + No dead time + 0x0 + + + B_0x1 + 1 phase period dead time + 0x1 + + + B_0x2 + 2 phase period dead time + 0x2 + + + B_0x7 + 7 phase period dead time + 0x7 + + + + + CC + Contrast control + 10 + 3 + read-write + + + B_0x0 + V<sub>LCD0</sub> + 0x0 + + + B_0x1 + V<sub>LCD1</sub> + 0x1 + + + B_0x2 + V<sub>LCD2</sub> + 0x2 + + + B_0x3 + V<sub>LCD3</sub> + 0x3 + + + B_0x4 + V<sub>LCD4</sub> + 0x4 + + + B_0x5 + V<sub>LCD5</sub> + 0x5 + + + B_0x6 + V<sub>LCD6</sub> + 0x6 + + + B_0x7 + V<sub>LCD7</sub> + 0x7 + + + + + BLINKF + Blink frequency selection + 13 + 3 + read-write + + + B_0x0 + f<sub>LCD</sub>/8 + 0x0 + + + B_0x1 + f<sub>LCD</sub>/16 + 0x1 + + + B_0x2 + f<sub>LCD</sub>/32 + 0x2 + + + B_0x3 + f<sub>LCD</sub>/64 + 0x3 + + + B_0x4 + f<sub>LCD</sub>/128 + 0x4 + + + B_0x5 + f<sub>LCD</sub>/256 + 0x5 + + + B_0x6 + f<sub>LCD</sub>/512 + 0x6 + + + B_0x7 + f<sub>LCD</sub>/1024 + 0x7 + + + + + BLINK + Blink mode selection + 16 + 2 + read-write + + + B_0x0 + Blink disabled + 0x0 + + + B_0x1 + Blink enabled on SEG[0], COM[0] (1 pixel) + 0x1 + + + B_0x2 + Blink enabled on SEG[0], all COMs (up to 8 pixels depending on the programmed duty) + 0x2 + + + B_0x3 + Blink enabled on all SEGs and all COMs (all pixels) + 0x3 + + + + + DIV + DIV clock divider + 18 + 4 + read-write + + + B_0x0 + ck_div = ck_ps/16 + 0x0 + + + B_0x1 + ck_div = ck_ps/17 + 0x1 + + + B_0xF + ck_div = ck_ps/31 + 0xF + + + + + PS + PS 16-bit prescaler + 22 + 4 + read-write + + + B_0x0 + ck_ps = LCDCLK + 0x0 + + + B_0x1 + ck_ps = LCDCLK/2 + 0x1 + + + B_0xF + ck_ps = LCDCLK/32768 + 0xF + + + + + + + LCD_SR + LCD_SR + LCD status register + 0x08 + 0x20 + 0x00000020 + 0xFFFFFFFF + + + ENS + LCD enabled status +This bit is set and cleared by hardware. It indicates the LCD controller status. +The ENS bit is set immediately when the LCDEN bit in the LCD_CR goes from 0 to 1. On deactivation it reflects the real status of LCD so it becomes 0 at the end of the last displayed frame. + 0 + 1 + read-only + + + B_0x0 + LCD controller disabled + 0x0 + + + B_0x1 + LCD controller enabled + 0x1 + + + + + SOF + Start-of-frame flag +This bit is set by hardware at the beginning of a new frame, at the same time as the display data is updated. It is cleared by writing a 1 to the SOFC bit in the LCD_CLR register. The bit clear has priority over the set. + 1 + 1 + read-only + + + B_0x0 + No event + 0x0 + + + B_0x1 + Start-of-frame event occurred. + 0x1 + + + + + UDR + Update display request + 2 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Update display request + 0x1 + + + + + UDD + Update display done +This bit is set by hardware. It is cleared by writing 1 to the UDDC bit in the LCD_CLR register. The bit set has priority over the clear. +If the device is in Stop mode (PCLK not provided), UDD does not generate an interrupt even if UDDIE = 1. If the display is not enabled the UDD interrupt never occurs. + 3 + 1 + read-only + + + B_0x0 + No event + 0x0 + + + B_0x1 + Update Display Request done. + 0x1 + + + + + RDY + Ready flag +This bit is set and cleared by hardware. It indicates the status of the step-up converter. + 4 + 1 + read-only + + + B_0x0 + Not ready + 0x0 + + + B_0x1 + Step-up converter is enabled and ready to provide the correct voltage. + 0x1 + + + + + FCRSF + LCD frame control register synchronization flag +This bit is set by hardware each time the LCD_FCR register is updated in the LCDCLK domain. It is cleared by hardware when writing to the LCD_FCR register. + 5 + 1 + read-only + + + B_0x0 + LCD frame control register not yet synchronized + 0x0 + + + B_0x1 + LCD frame control register synchronized + 0x1 + + + + + + + LCD_CLR + LCD_CLR + LCD clear register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SOFC + Start of frame flag clear +This bit is written by software to clear the SOF flag in the LCD_SR register. + 1 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear SOF flag. + 0x1 + + + + + UDDC + Update display done clear +This bit is written by software to clear the UDD flag in the LCD_SR register. + 3 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear UDD flag. + 0x1 + + + + + + + LCD_RAM0 + LCD_RAM0 + LCD display memory + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 32 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM1 + LCD_RAM1 + LCD display memory + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 12 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM2 + LCD_RAM2 + LCD display memory + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 32 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM3 + LCD_RAM3 + LCD display memory + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 12 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM4 + LCD_RAM4 + LCD display memory + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 32 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM5 + LCD_RAM5 + LCD display memory + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 12 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM6 + LCD_RAM6 + LCD display memory + 0x2C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 32 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM7 + LCD_RAM7 + LCD display memory + 0x30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 12 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM8 + LCD_RAM8 + LCD display memory + 0x34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 32 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM9 + LCD_RAM9 + LCD display memory + 0x38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 8 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM10 + LCD_RAM10 + LCD display memory + 0x3C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 32 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM11 + LCD_RAM11 + LCD display memory + 0x40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 8 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM12 + LCD_RAM12 + LCD display memory + 0x44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 32 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM13 + LCD_RAM13 + LCD display memory + 0x48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 8 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM14 + LCD_RAM14 + LCD display memory + 0x4C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 32 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM15 + LCD_RAM15 + LCD display memory + 0x50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 8 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + + + TSC + Touch sensing controller + TSC + 0x40024000 + + 0x0 + 0x400 + registers + + + TSC + TSC global interrupt + 77 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + CTPH + Charge transfer pulse high + 28 + 4 + + + CTPL + Charge transfer pulse low + 24 + 4 + + + SSD + Spread spectrum deviation + 17 + 7 + + + SSE + Spread spectrum enable + 16 + 1 + + + SSPSC + Spread spectrum prescaler + 15 + 1 + + + PGPSC + pulse generator prescaler + 12 + 3 + + + MCV + Max count value + 5 + 3 + + + IODEF + I/O Default mode + 4 + 1 + + + SYNCPOL + Synchronization pin polarity + 3 + 1 + + + AM + Acquisition mode + 2 + 1 + + + START + Start a new acquisition + 1 + 1 + + + TSCE + Touch sensing controller enable + 0 + 1 + + + + + IER + IER + interrupt enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + MCEIE + Max count error interrupt enable + 1 + 1 + + + EOAIE + End of acquisition interrupt enable + 0 + 1 + + + + + ICR + ICR + interrupt clear register + 0x8 + 0x20 + read-write + 0x00000000 + + + MCEIC + Max count error interrupt clear + 1 + 1 + + + EOAIC + End of acquisition interrupt clear + 0 + 1 + + + + + ISR + ISR + interrupt status register + 0xC + 0x20 + read-write + 0x00000000 + + + MCEF + Max count error flag + 1 + 1 + + + EOAF + End of acquisition flag + 0 + 1 + + + + + IOHCR + IOHCR + I/O hysteresis control register + 0x10 + 0x20 + read-write + 0xFFFFFFFF + + + G8_IO4 + G8_IO4 + 31 + 1 + + + G8_IO3 + G8_IO3 + 30 + 1 + + + G8_IO2 + G8_IO2 + 29 + 1 + + + G8_IO1 + G8_IO1 + 28 + 1 + + + G7_IO4 + G7_IO4 + 27 + 1 + + + G7_IO3 + G7_IO3 + 26 + 1 + + + G7_IO2 + G7_IO2 + 25 + 1 + + + G7_IO1 + G7_IO1 + 24 + 1 + + + G6_IO4 + G6_IO4 + 23 + 1 + + + G6_IO3 + G6_IO3 + 22 + 1 + + + G6_IO2 + G6_IO2 + 21 + 1 + + + G6_IO1 + G6_IO1 + 20 + 1 + + + G5_IO4 + G5_IO4 + 19 + 1 + + + G5_IO3 + G5_IO3 + 18 + 1 + + + G5_IO2 + G5_IO2 + 17 + 1 + + + G5_IO1 + G5_IO1 + 16 + 1 + + + G4_IO4 + G4_IO4 + 15 + 1 + + + G4_IO3 + G4_IO3 + 14 + 1 + + + G4_IO2 + G4_IO2 + 13 + 1 + + + G4_IO1 + G4_IO1 + 12 + 1 + + + G3_IO4 + G3_IO4 + 11 + 1 + + + G3_IO3 + G3_IO3 + 10 + 1 + + + G3_IO2 + G3_IO2 + 9 + 1 + + + G3_IO1 + G3_IO1 + 8 + 1 + + + G2_IO4 + G2_IO4 + 7 + 1 + + + G2_IO3 + G2_IO3 + 6 + 1 + + + G2_IO2 + G2_IO2 + 5 + 1 + + + G2_IO1 + G2_IO1 + 4 + 1 + + + G1_IO4 + G1_IO4 + 3 + 1 + + + G1_IO3 + G1_IO3 + 2 + 1 + + + G1_IO2 + G1_IO2 + 1 + 1 + + + G1_IO1 + G1_IO1 + 0 + 1 + + + + + IOASCR + IOASCR + I/O analog switch control register + 0x18 + 0x20 + read-write + 0x00000000 + + + G8_IO4 + G8_IO4 + 31 + 1 + + + G8_IO3 + G8_IO3 + 30 + 1 + + + G8_IO2 + G8_IO2 + 29 + 1 + + + G8_IO1 + G8_IO1 + 28 + 1 + + + G7_IO4 + G7_IO4 + 27 + 1 + + + G7_IO3 + G7_IO3 + 26 + 1 + + + G7_IO2 + G7_IO2 + 25 + 1 + + + G7_IO1 + G7_IO1 + 24 + 1 + + + G6_IO4 + G6_IO4 + 23 + 1 + + + G6_IO3 + G6_IO3 + 22 + 1 + + + G6_IO2 + G6_IO2 + 21 + 1 + + + G6_IO1 + G6_IO1 + 20 + 1 + + + G5_IO4 + G5_IO4 + 19 + 1 + + + G5_IO3 + G5_IO3 + 18 + 1 + + + G5_IO2 + G5_IO2 + 17 + 1 + + + G5_IO1 + G5_IO1 + 16 + 1 + + + G4_IO4 + G4_IO4 + 15 + 1 + + + G4_IO3 + G4_IO3 + 14 + 1 + + + G4_IO2 + G4_IO2 + 13 + 1 + + + G4_IO1 + G4_IO1 + 12 + 1 + + + G3_IO4 + G3_IO4 + 11 + 1 + + + G3_IO3 + G3_IO3 + 10 + 1 + + + G3_IO2 + G3_IO2 + 9 + 1 + + + G3_IO1 + G3_IO1 + 8 + 1 + + + G2_IO4 + G2_IO4 + 7 + 1 + + + G2_IO3 + G2_IO3 + 6 + 1 + + + G2_IO2 + G2_IO2 + 5 + 1 + + + G2_IO1 + G2_IO1 + 4 + 1 + + + G1_IO4 + G1_IO4 + 3 + 1 + + + G1_IO3 + G1_IO3 + 2 + 1 + + + G1_IO2 + G1_IO2 + 1 + 1 + + + G1_IO1 + G1_IO1 + 0 + 1 + + + + + IOSCR + IOSCR + I/O sampling control register + 0x20 + 0x20 + read-write + 0x00000000 + + + G8_IO4 + G8_IO4 + 31 + 1 + + + G8_IO3 + G8_IO3 + 30 + 1 + + + G8_IO2 + G8_IO2 + 29 + 1 + + + G8_IO1 + G8_IO1 + 28 + 1 + + + G7_IO4 + G7_IO4 + 27 + 1 + + + G7_IO3 + G7_IO3 + 26 + 1 + + + G7_IO2 + G7_IO2 + 25 + 1 + + + G7_IO1 + G7_IO1 + 24 + 1 + + + G6_IO4 + G6_IO4 + 23 + 1 + + + G6_IO3 + G6_IO3 + 22 + 1 + + + G6_IO2 + G6_IO2 + 21 + 1 + + + G6_IO1 + G6_IO1 + 20 + 1 + + + G5_IO4 + G5_IO4 + 19 + 1 + + + G5_IO3 + G5_IO3 + 18 + 1 + + + G5_IO2 + G5_IO2 + 17 + 1 + + + G5_IO1 + G5_IO1 + 16 + 1 + + + G4_IO4 + G4_IO4 + 15 + 1 + + + G4_IO3 + G4_IO3 + 14 + 1 + + + G4_IO2 + G4_IO2 + 13 + 1 + + + G4_IO1 + G4_IO1 + 12 + 1 + + + G3_IO4 + G3_IO4 + 11 + 1 + + + G3_IO3 + G3_IO3 + 10 + 1 + + + G3_IO2 + G3_IO2 + 9 + 1 + + + G3_IO1 + G3_IO1 + 8 + 1 + + + G2_IO4 + G2_IO4 + 7 + 1 + + + G2_IO3 + G2_IO3 + 6 + 1 + + + G2_IO2 + G2_IO2 + 5 + 1 + + + G2_IO1 + G2_IO1 + 4 + 1 + + + G1_IO4 + G1_IO4 + 3 + 1 + + + G1_IO3 + G1_IO3 + 2 + 1 + + + G1_IO2 + G1_IO2 + 1 + 1 + + + G1_IO1 + G1_IO1 + 0 + 1 + + + + + IOCCR + IOCCR + I/O channel control register + 0x28 + 0x20 + read-write + 0x00000000 + + + G8_IO4 + G8_IO4 + 31 + 1 + + + G8_IO3 + G8_IO3 + 30 + 1 + + + G8_IO2 + G8_IO2 + 29 + 1 + + + G8_IO1 + G8_IO1 + 28 + 1 + + + G7_IO4 + G7_IO4 + 27 + 1 + + + G7_IO3 + G7_IO3 + 26 + 1 + + + G7_IO2 + G7_IO2 + 25 + 1 + + + G7_IO1 + G7_IO1 + 24 + 1 + + + G6_IO4 + G6_IO4 + 23 + 1 + + + G6_IO3 + G6_IO3 + 22 + 1 + + + G6_IO2 + G6_IO2 + 21 + 1 + + + G6_IO1 + G6_IO1 + 20 + 1 + + + G5_IO4 + G5_IO4 + 19 + 1 + + + G5_IO3 + G5_IO3 + 18 + 1 + + + G5_IO2 + G5_IO2 + 17 + 1 + + + G5_IO1 + G5_IO1 + 16 + 1 + + + G4_IO4 + G4_IO4 + 15 + 1 + + + G4_IO3 + G4_IO3 + 14 + 1 + + + G4_IO2 + G4_IO2 + 13 + 1 + + + G4_IO1 + G4_IO1 + 12 + 1 + + + G3_IO4 + G3_IO4 + 11 + 1 + + + G3_IO3 + G3_IO3 + 10 + 1 + + + G3_IO2 + G3_IO2 + 9 + 1 + + + G3_IO1 + G3_IO1 + 8 + 1 + + + G2_IO4 + G2_IO4 + 7 + 1 + + + G2_IO3 + G2_IO3 + 6 + 1 + + + G2_IO2 + G2_IO2 + 5 + 1 + + + G2_IO1 + G2_IO1 + 4 + 1 + + + G1_IO4 + G1_IO4 + 3 + 1 + + + G1_IO3 + G1_IO3 + 2 + 1 + + + G1_IO2 + G1_IO2 + 1 + 1 + + + G1_IO1 + G1_IO1 + 0 + 1 + + + + + IOGCSR + IOGCSR + I/O group control status register + 0x30 + 0x20 + 0x00000000 + + + G8S + Analog I/O group x status + 23 + 1 + read-only + + + G7S + Analog I/O group x status + 22 + 1 + read-only + + + G6S + Analog I/O group x status + 21 + 1 + read-only + + + G5S + Analog I/O group x status + 20 + 1 + read-only + + + G4S + Analog I/O group x status + 19 + 1 + read-only + + + G3S + Analog I/O group x status + 18 + 1 + read-only + + + G2S + Analog I/O group x status + 17 + 1 + read-only + + + G1S + Analog I/O group x status + 16 + 1 + read-only + + + G8E + Analog I/O group x enable + 7 + 1 + read-write + + + G7E + Analog I/O group x enable + 6 + 1 + read-write + + + G6E + Analog I/O group x enable + 5 + 1 + read-write + + + G5E + Analog I/O group x enable + 4 + 1 + read-write + + + G4E + Analog I/O group x enable + 3 + 1 + read-write + + + G3E + Analog I/O group x enable + 2 + 1 + read-write + + + G2E + Analog I/O group x enable + 1 + 1 + read-write + + + G1E + Analog I/O group x enable + 0 + 1 + read-write + + + + + IOG1CR + IOG1CR + I/O group x counter register + 0x34 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG2CR + IOG2CR + I/O group x counter register + 0x38 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG3CR + IOG3CR + I/O group x counter register + 0x3C + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG4CR + IOG4CR + I/O group x counter register + 0x40 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG5CR + IOG5CR + I/O group x counter register + 0x44 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG6CR + IOG6CR + I/O group x counter register + 0x48 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG7CR + IOG7CR + I/O group x counter register + 0x4C + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG8CR + IOG8CR + I/O group x counter register + 0x50 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + + + IWDG + Independent watchdog + IWDG + 0x40003000 + + 0x0 + 0x400 + registers + + + + KR + KR + Key register + 0x0 + 0x20 + write-only + 0x00000000 + + + KEY + Key value (write only, read 0x0000) + 0 + 16 + + + + + PR + PR + Prescaler register + 0x4 + 0x20 + read-write + 0x00000000 + + + PR + Prescaler divider + 0 + 3 + + + + + RLR + RLR + Reload register + 0x8 + 0x20 + read-write + 0x00000FFF + + + RL + Watchdog counter reload value + 0 + 12 + + + + + SR + SR + Status register + 0xC + 0x20 + read-only + 0x00000000 + + + WVU + Watchdog counter window value update + 2 + 1 + + + RVU + Watchdog counter reload value update + 1 + 1 + + + PVU + Watchdog prescaler value update + 0 + 1 + + + + + WINR + WINR + Window register + 0x10 + 0x20 + read-write + 0x00000FFF + + + WIN + Watchdog counter window value + 0 + 12 + + + + + + + WWDG + System window watchdog + WWDG + 0x40002C00 + + 0x0 + 0x400 + registers + + + WWDG + Window Watchdog interrupt + 0 + + + + CR + CR + Control register + 0x0 + 0x20 + read-write + 0x0000007F + + + WDGA + Activation bit + 7 + 1 + + + T + 7-bit counter (MSB to LSB) + 0 + 7 + + + + + CFR + CFR + Configuration register + 0x4 + 0x20 + read-write + 0x0000007F + + + EWI + Early wakeup interrupt + 9 + 1 + + + WDGTB + Timer base + 7 + 2 + + + W + 7-bit window value + 0 + 7 + + + + + SR + SR + Status register + 0x8 + 0x20 + read-write + 0x00000000 + + + EWIF + Early wakeup interrupt flag + 0 + 1 + + + + + + + COMP + Comparator + COMP + 0x40010200 + + 0x0 + 0x200 + registers + + + COMP + COMP1 and COMP2 interrupts + 64 + + + + COMP1_CSR + COMP1_CSR + Comparator 1 control and status register + 0x0 + 0x20 + 0x0 + + + COMP1_EN + Comparator 1 enable bit + 0 + 1 + read-write + + + COMP1_PWRMODE + Power Mode of the comparator 1 + 2 + 2 + read-write + + + COMP1_INMSEL + Comparator 1 Input Minus connection configuration bit + 4 + 3 + read-write + + + COMP1_INPSEL + Comparator1 input plus selection bit + 7 + 1 + read-write + + + COMP1_POLARITY + Comparator 1 polarity selection bit + 15 + 1 + read-write + + + COMP1_HYST + Comparator 1 hysteresis selection bits + 16 + 2 + read-write + + + COMP1_BLANKING + Comparator 1 blanking source selection bits + 18 + 3 + read-write + + + COMP1_BRGEN + Scaler bridge enable + 22 + 1 + read-write + + + COMP1_SCALEN + Voltage scaler enable bit + 23 + 1 + read-write + + + COMP1_VALUE + Comparator 1 output status bit + 30 + 1 + read-only + + + COMP1_LOCK + COMP1_CSR register lock bit + 31 + 1 + write-only + + + + + COMP2_CSR + COMP2_CSR + Comparator 2 control and status register + 0x4 + 0x20 + 0x0 + + + COMP2_EN + Comparator 2 enable bit + 0 + 1 + read-write + + + COMP2_PWRMODE + Power Mode of the comparator 2 + 2 + 2 + read-write + + + COMP2_INMSEL + Comparator 2 Input Minus connection configuration bit + 4 + 3 + read-write + + + COMP2_INPSEL + Comparator 2 Input Plus connection configuration bit + 7 + 1 + read-write + + + COMP2_WINMODE + Windows mode selection bit + 9 + 1 + read-write + + + COMP2_POLARITY + Comparator 2 polarity selection bit + 15 + 1 + read-write + + + COMP2_HYST + Comparator 2 hysteresis selection bits + 16 + 2 + read-write + + + COMP2_BLANKING + Comparator 2 blanking source selection bits + 18 + 3 + read-write + + + COMP2_BRGEN + Scaler bridge enable + 22 + 1 + read-write + + + COMP2_SCALEN + Voltage scaler enable bit + 23 + 1 + read-write + + + COMP2_VALUE + Comparator 2 output status bit + 30 + 1 + read-only + + + COMP2_LOCK + COMP2_CSR register lock bit + 31 + 1 + write-only + + + + + + + FIREWALL + Firewall + Firewall + 0x40011C00 + + 0x0 + 0x400 + registers + + + + CSSA + CSSA + Code segment start address + 0x0 + 0x20 + read-write + 0x00000000 + + + ADD + code segment start address + 8 + 16 + + + + + CSL + CSL + Code segment length + 0x4 + 0x20 + read-write + 0x00000000 + + + LENG + code segment length + 8 + 14 + + + + + NVDSSA + NVDSSA + Non-volatile data segment start address + 0x8 + 0x20 + read-write + 0x00000000 + + + ADD + Non-volatile data segment start address + 8 + 16 + + + + + NVDSL + NVDSL + Non-volatile data segment length + 0xC + 0x20 + read-write + 0x00000000 + + + LENG + Non-volatile data segment length + 8 + 14 + + + + + VDSSA + VDSSA + Volatile data segment start address + 0x10 + 0x20 + read-write + 0x00000000 + + + ADD + Volatile data segment start address + 6 + 10 + + + + + VDSL + VDSL + Volatile data segment length + 0x14 + 0x20 + read-write + 0x00000000 + + + LENG + Non-volatile data segment length + 6 + 10 + + + + + CR + CR + Configuration register + 0x20 + 0x20 + read-write + 0x00000000 + + + VDE + Volatile data execution + 2 + 1 + + + VDS + Volatile data shared + 1 + 1 + + + FPA + Firewall pre alarm + 0 + 1 + + + + + + + I2C1 + Inter-integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1_EV + I2C1 event interrupt + 31 + + + I2C1_ER + I2C1 error interrupt + 32 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + PE + Peripheral enable + 0 + 1 + + + TXIE + TX Interrupt enable + 1 + 1 + + + RXIE + RX Interrupt enable + 2 + 1 + + + ADDRIE + Address match interrupt enable (slave only) + 3 + 1 + + + NACKIE + Not acknowledge received interrupt enable + 4 + 1 + + + STOPIE + STOP detection Interrupt enable + 5 + 1 + + + TCIE + Transfer Complete interrupt enable + 6 + 1 + + + ERRIE + Error interrupts enable + 7 + 1 + + + DNF + Digital noise filter + 8 + 4 + + + ANFOFF + Analog noise filter OFF + 12 + 1 + + + TXDMAEN + DMA transmission requests enable + 14 + 1 + + + RXDMAEN + DMA reception requests enable + 15 + 1 + + + SBC + Slave byte control + 16 + 1 + + + NOSTRETCH + Clock stretching disable + 17 + 1 + + + WUPEN + Wakeup from STOP enable + 18 + 1 + + + GCEN + General call enable + 19 + 1 + + + SMBHEN + SMBus Host address enable + 20 + 1 + + + SMBDEN + SMBus Device Default address enable + 21 + 1 + + + ALERTEN + SMBUS alert enable + 22 + 1 + + + PECEN + PEC enable + 23 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + PECBYTE + Packet error checking byte + 26 + 1 + + + AUTOEND + Automatic end mode (master mode) + 25 + 1 + + + RELOAD + NBYTES reload mode + 24 + 1 + + + NBYTES + Number of bytes + 16 + 8 + + + NACK + NACK generation (slave mode) + 15 + 1 + + + STOP + Stop generation (master mode) + 14 + 1 + + + START + Start generation + 13 + 1 + + + HEAD10R + 10-bit address header only read direction (master receiver mode) + 12 + 1 + + + ADD10 + 10-bit addressing mode (master mode) + 11 + 1 + + + RD_WRN + Transfer direction (master mode) + 10 + 1 + + + SADD + Slave address bit (master mode) + 0 + 10 + + + + + OAR1 + OAR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x00000000 + + + OA1 + Interface address + 0 + 10 + + + OA1MODE + Own Address 1 10-bit mode + 10 + 1 + + + OA1EN + Own Address 1 enable + 15 + 1 + + + + + OAR2 + OAR2 + Own address register 2 + 0xC + 0x20 + read-write + 0x00000000 + + + OA2 + Interface address + 1 + 7 + + + OA2MSK + Own Address 2 masks + 8 + 3 + + + OA2EN + Own Address 2 enable + 15 + 1 + + + + + TIMINGR + TIMINGR + Timing register + 0x10 + 0x20 + read-write + 0x00000000 + + + SCLL + SCL low period (master mode) + 0 + 8 + + + SCLH + SCL high period (master mode) + 8 + 8 + + + SDADEL + Data hold time + 16 + 4 + + + SCLDEL + Data setup time + 20 + 4 + + + PRESC + Timing prescaler + 28 + 4 + + + + + TIMEOUTR + TIMEOUTR + Status register 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + TIMEOUTA + Bus timeout A + 0 + 12 + + + TIDLE + Idle clock timeout detection + 12 + 1 + + + TIMOUTEN + Clock timeout enable + 15 + 1 + + + TIMEOUTB + Bus timeout B + 16 + 12 + + + TEXTEN + Extended clock timeout enable + 31 + 1 + + + + + ISR + ISR + Interrupt and Status register + 0x18 + 0x20 + 0x00000001 + + + ADDCODE + Address match code (Slave mode) + 17 + 7 + read-only + + + DIR + Transfer direction (Slave mode) + 16 + 1 + read-only + + + BUSY + Bus busy + 15 + 1 + read-only + + + ALERT + SMBus alert + 13 + 1 + read-only + + + TIMEOUT + Timeout or t_low detection flag + 12 + 1 + read-only + + + PECERR + PEC Error in reception + 11 + 1 + read-only + + + OVR + Overrun/Underrun (slave mode) + 10 + 1 + read-only + + + ARLO + Arbitration lost + 9 + 1 + read-only + + + BERR + Bus error + 8 + 1 + read-only + + + TCR + Transfer Complete Reload + 7 + 1 + read-only + + + TC + Transfer Complete (master mode) + 6 + 1 + read-only + + + STOPF + Stop detection flag + 5 + 1 + read-only + + + NACKF + Not acknowledge received flag + 4 + 1 + read-only + + + ADDR + Address matched (slave mode) + 3 + 1 + read-only + + + RXNE + Receive data register not empty (receivers) + 2 + 1 + read-only + + + TXIS + Transmit interrupt status (transmitters) + 1 + 1 + read-write + + + TXE + Transmit data register empty (transmitters) + 0 + 1 + read-write + + + + + ICR + ICR + Interrupt clear register + 0x1C + 0x20 + write-only + 0x00000000 + + + ALERTCF + Alert flag clear + 13 + 1 + + + TIMOUTCF + Timeout detection flag clear + 12 + 1 + + + PECCF + PEC Error flag clear + 11 + 1 + + + OVRCF + Overrun/Underrun flag clear + 10 + 1 + + + ARLOCF + Arbitration lost flag clear + 9 + 1 + + + BERRCF + Bus error flag clear + 8 + 1 + + + STOPCF + Stop detection flag clear + 5 + 1 + + + NACKCF + Not Acknowledge flag clear + 4 + 1 + + + ADDRCF + Address Matched flag clear + 3 + 1 + + + + + PECR + PECR + PEC register + 0x20 + 0x20 + read-only + 0x00000000 + + + PEC + Packet error checking register + 0 + 8 + + + + + RXDR + RXDR + Receive data register + 0x24 + 0x20 + read-only + 0x00000000 + + + RXDATA + 8-bit receive data + 0 + 8 + + + + + TXDR + TXDR + Transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + + + TXDATA + 8-bit transmit data + 0 + 8 + + + + + + + I2C2 + 0x40005800 + + I2C2_EV + I2C2 event interrupt + 33 + + + I2C2_ER + I2C2 error interrupt + 34 + + + + I2C3 + 0x40005C00 + + I2C3_EV + I2C3 event interrupt + 72 + + + I2C3_ER + I2C3 error interrupt + 73 + + + + FLASH + Flash + Flash + 0x40022000 + + 0x0 + 0x400 + registers + + + FLASH + Flash global interrupt + 4 + + + + ACR + ACR + Access control register + 0x0 + 0x20 + read-write + 0x00000600 + + + LATENCY + Latency + 0 + 3 + + + PRFTEN + Prefetch enable + 8 + 1 + + + ICEN + Instruction cache enable + 9 + 1 + + + DCEN + Data cache enable + 10 + 1 + + + ICRST + Instruction cache reset + 11 + 1 + + + DCRST + Data cache reset + 12 + 1 + + + RUN_PD + Flash Power-down mode during Low-power run mode + 13 + 1 + + + SLEEP_PD + Flash Power-down mode during Low-power sleep mode + 14 + 1 + + + + + PDKEYR + PDKEYR + Power down key register + 0x4 + 0x20 + write-only + 0x00000000 + + + PDKEYR + RUN_PD in FLASH_ACR key + 0 + 32 + + + + + KEYR + KEYR + Flash key register + 0x8 + 0x20 + write-only + 0x00000000 + + + KEYR + KEYR + 0 + 32 + + + + + OPTKEYR + OPTKEYR + Option byte key register + 0xC + 0x20 + write-only + 0x00000000 + + + OPTKEYR + Option byte key + 0 + 32 + + + + + SR + SR + Status register + 0x10 + 0x20 + 0x00000000 + + + EOP + End of operation + 0 + 1 + read-write + + + OPERR + Operation error + 1 + 1 + read-write + + + PROGERR + Programming error + 3 + 1 + read-write + + + WRPERR + Write protected error + 4 + 1 + read-write + + + PGAERR + Programming alignment error + 5 + 1 + read-write + + + SIZERR + Size error + 6 + 1 + read-write + + + PGSERR + Programming sequence error + 7 + 1 + read-write + + + MISERR + Fast programming data miss error + 8 + 1 + read-write + + + FASTERR + Fast programming error + 9 + 1 + read-write + + + RDERR + PCROP read error + 14 + 1 + read-write + + + OPTVERR + Option validity error + 15 + 1 + read-write + + + BSY + Busy + 16 + 1 + read-only + + + + + CR + CR + Flash control register + 0x14 + 0x20 + read-write + 0xC0000000 + + + PG + Programming + 0 + 1 + + + PER + Page erase + 1 + 1 + + + MER1 + Bank 1 Mass erase + 2 + 1 + + + PNB + Page number + 3 + 8 + + + BKER + Bank erase + 11 + 1 + + + MER2 + Bank 2 Mass erase + 15 + 1 + + + START + Start + 16 + 1 + + + OPTSTRT + Options modification start + 17 + 1 + + + FSTPG + Fast programming + 18 + 1 + + + EOPIE + End of operation interrupt enable + 24 + 1 + + + ERRIE + Error interrupt enable + 25 + 1 + + + RDERRIE + PCROP read error interrupt enable + 26 + 1 + + + OBL_LAUNCH + Force the option byte loading + 27 + 1 + + + OPTLOCK + Options Lock + 30 + 1 + + + LOCK + FLASH_CR Lock + 31 + 1 + + + + + ECCR + ECCR + Flash ECC register + 0x18 + 0x20 + 0x00000000 + + + ADDR_ECC + ECC fail address + 0 + 19 + read-only + + + BK_ECC + ECC fail bank + 19 + 1 + read-only + + + SYSF_ECC + System Flash ECC fail + 20 + 1 + read-only + + + ECCIE + ECC correction interrupt enable + 24 + 1 + read-write + + + ECCC + ECC correction + 30 + 1 + read-write + + + ECCD + ECC detection + 31 + 1 + read-write + + + + + OPTR + OPTR + Flash option register + 0x20 + 0x20 + read-write + 0xF0000000 + + + RDP + Read protection level + 0 + 8 + + + BOR_LEV + BOR reset Level + 8 + 3 + + + nRST_STOP + nRST_STOP + 12 + 1 + + + nRST_STDBY + nRST_STDBY + 13 + 1 + + + nRST_SHDW + nRST_SHDW + 14 + 1 + + + IDWG_SW + Independent watchdog selection + 16 + 1 + + + IWDG_STOP + Independent watchdog counter freeze in Stop mode + 17 + 1 + + + IWDG_STDBY + Independent watchdog counter freeze in Standby mode + 18 + 1 + + + WWDG_SW + Window watchdog selection + 19 + 1 + + + BFB2 + Dual-bank boot + 20 + 1 + + + DUALBANK + Dual-Bank on 512 KB or 256 KB Flash memory devices + 21 + 1 + + + nBOOT1 + Boot configuration + 23 + 1 + + + SRAM2_PE + SRAM2 parity check enable + 24 + 1 + + + SRAM2_RST + SRAM2 Erase when system reset + 25 + 1 + + + nSWBOOT0 + Software BOOT0 + 26 + 1 + + + nBOOT0 + nBOOT0 option bit + 27 + 1 + + + + + PCROP1SR + PCROP1SR + Flash Bank 1 PCROP Start address register + 0x24 + 0x20 + read-write + 0xFFFF0000 + + + PCROP1_STRT + Bank 1 PCROP area start offset + 0 + 16 + + + + + PCROP1ER + PCROP1ER + Flash Bank 1 PCROP End address register + 0x28 + 0x20 + read-write + 0x0FFF0000 + + + PCROP1_END + Bank 1 PCROP area end offset + 0 + 16 + + + PCROP_RDP + PCROP area preserved when RDP level decreased + 31 + 1 + + + + + WRP1AR + WRP1AR + Flash Bank 1 WRP area A address register + 0x2C + 0x20 + read-write + 0xFF00FF00 + + + WRP1A_STRT + Bank 1 WRP first area start offset + 0 + 8 + + + WRP1A_END + Bank 1 WRP first area A end offset + 16 + 8 + + + + + WRP1BR + WRP1BR + Flash Bank 1 WRP area B address register + 0x30 + 0x20 + read-write + 0xFF00FF00 + + + WRP1B_END + Bank 1 WRP second area B end offset + 16 + 8 + + + WRP1B_STRT + Bank 1 WRP second area B start offset + 0 + 8 + + + + + PCROP2SR + PCROP2SR + Flash Bank 2 PCROP Start address register + 0x44 + 0x20 + read-write + 0xFFFF0000 + + + PCROP2_STRT + Bank 2 PCROP area start offset + 0 + 16 + + + + + PCROP2ER + PCROP2ER + Flash Bank 2 PCROP End address register + 0x48 + 0x20 + read-write + 0xFFFF0000 + + + PCROP2_END + Bank 2 PCROP area end offset + 0 + 16 + + + + + WRP2AR + WRP2AR + Flash Bank 2 WRP area A address register + 0x4C + 0x20 + read-write + 0xFF00FF00 + + + WRP2A_STRT + Bank 2 WRP first area A start offset + 0 + 8 + + + WRP2A_END + Bank 2 WRP first area A end offset + 16 + 8 + + + + + WRP2BR + WRP2BR + Flash Bank 2 WRP area B address register + 0x50 + 0x20 + read-write + 0xFF00FF00 + + + WRP2B_STRT + Bank 2 WRP second area B start offset + 0 + 8 + + + WRP2B_END + Bank 2 WRP second area B end offset + 16 + 8 + + + + + + + DBGMCU + Debug support + DBGMCU + 0xE0042000 + + 0x0 + 0x400 + registers + + + + IDCODE + IDCODE + MCU Device ID Code Register + 0x0 + 0x20 + read-only + 0x0 + + + DEV_ID + Device Identifier + 0 + 16 + + + REV_ID + Revision Identifier + 16 + 16 + + + + + CR + CR + Debug MCU Configuration Register + 0x4 + 0x20 + read-write + 0x0 + + + DBG_SLEEP + Debug Sleep Mode + 0 + 1 + + + DBG_STOP + Debug Stop Mode + 1 + 1 + + + DBG_STANDBY + Debug Standby Mode + 2 + 1 + + + TRACE_IOEN + Trace pin assignment control + 5 + 1 + + + TRACE_MODE + Trace pin assignment control + 6 + 2 + + + + + APB1_FZR1 + APB1_FZR1 + APB Low Freeze Register 1 + 0x8 + 0x20 + read-write + 0x0 + + + DBG_TIMER2_STOP + Debug Timer 2 stopped when Core is halted + 0 + 1 + + + DBG_TIM3_STOP + TIM3 counter stopped when core is halted + 1 + 1 + + + DBG_TIM4_STOP + TIM4 counter stopped when core is halted + 2 + 1 + + + DBG_TIM5_STOP + TIM5 counter stopped when core is halted + 3 + 1 + + + DBG_TIMER6_STOP + Debug Timer 6 stopped when Core is halted + 4 + 1 + + + DBG_TIM7_STOP + TIM7 counter stopped when core is halted + 5 + 1 + + + DBG_RTC_STOP + Debug RTC stopped when Core is halted + 10 + 1 + + + DBG_WWDG_STOP + Debug Window Wachdog stopped when Core is halted + 11 + 1 + + + DBG_IWDG_STOP + Debug Independent Wachdog stopped when Core is halted + 12 + 1 + + + DBG_I2C1_STOP + I2C1 SMBUS timeout mode stopped when core is halted + 21 + 1 + + + DBG_I2C2_STOP + I2C2 SMBUS timeout mode stopped when core is halted + 22 + 1 + + + DBG_I2C3_STOP + I2C3 SMBUS timeout counter stopped when core is halted + 23 + 1 + + + DBG_CAN_STOP + bxCAN stopped when core is halted + 25 + 1 + + + DBG_LPTIMER_STOP + LPTIM1 counter stopped when core is halted + 31 + 1 + + + + + APB1_FZR2 + APB1_FZR2 + APB Low Freeze Register 2 + 0xC + 0x20 + read-write + 0x0 + + + DBG_LPTIM2_STOP + LPTIM2 counter stopped when core is halted + 5 + 1 + + + + + APB2_FZR + APB2_FZR + APB High Freeze Register + 0x10 + 0x20 + read-write + 0x0 + + + DBG_TIM1_STOP + TIM1 counter stopped when core is halted + 11 + 1 + + + DBG_TIM8_STOP + TIM8 counter stopped when core is halted + 13 + 1 + + + DBG_TIM15_STOP + TIM15 counter stopped when core is halted + 16 + 1 + + + DBG_TIM16_STOP + TIM16 counter stopped when core is halted + 17 + 1 + + + DBG_TIM17_STOP + TIM17 counter stopped when core is halted + 18 + 1 + + + + + + + QUADSPI + QuadSPI interface + QUADSPI + 0xA0001000 + + 0x0 + 0x400 + registers + + + QUADSPI + Quad SPI global interrupt + 71 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + PRESCALER + Clock prescaler + 24 + 8 + + + PMM + Polling match mode + 23 + 1 + + + APMS + Automatic poll mode stop + 22 + 1 + + + TOIE + TimeOut interrupt enable + 20 + 1 + + + SMIE + Status match interrupt enable + 19 + 1 + + + FTIE + FIFO threshold interrupt enable + 18 + 1 + + + TCIE + Transfer complete interrupt enable + 17 + 1 + + + TEIE + Transfer error interrupt enable + 16 + 1 + + + FTHRES + IFO threshold level + 8 + 5 + + + FSEL + FLASH memory selection + 7 + 1 + + + DFM + Dual-flash mode + 6 + 1 + + + SSHIFT + Sample shift + 4 + 1 + + + TCEN + Timeout counter enable + 3 + 1 + + + DMAEN + DMA enable + 2 + 1 + + + ABORT + Abort request + 1 + 1 + + + EN + Enable + 0 + 1 + + + + + DCR + DCR + device configuration register + 0x4 + 0x20 + read-write + 0x00000000 + + + FSIZE + FLASH memory size + 16 + 5 + + + CSHT + Chip select high time + 8 + 3 + + + CKMODE + Mode 0 / mode 3 + 0 + 1 + + + + + SR + SR + status register + 0x8 + 0x20 + read-only + 0x00000000 + + + FLEVEL + FIFO level + 8 + 7 + + + BUSY + Busy + 5 + 1 + + + TOF + Timeout flag + 4 + 1 + + + SMF + Status match flag + 3 + 1 + + + FTF + FIFO threshold flag + 2 + 1 + + + TCF + Transfer complete flag + 1 + 1 + + + TEF + Transfer error flag + 0 + 1 + + + + + FCR + FCR + flag clear register + 0xC + 0x20 + read-write + 0x00000000 + + + CTOF + Clear timeout flag + 4 + 1 + + + CSMF + Clear status match flag + 3 + 1 + + + CTCF + Clear transfer complete flag + 1 + 1 + + + CTEF + Clear transfer error flag + 0 + 1 + + + + + DLR + DLR + data length register + 0x10 + 0x20 + read-write + 0x00000000 + + + DL + Data length + 0 + 32 + + + + + CCR + CCR + communication configuration register + 0x14 + 0x20 + read-write + 0x00000000 + + + DDRM + Double data rate mode + 31 + 1 + + + DHHC + DDR hold half cycle + 30 + 1 + + + SIOO + Send instruction only once mode + 28 + 1 + + + FMODE + Functional mode + 26 + 2 + + + DMODE + Data mode + 24 + 2 + + + DCYC + Number of dummy cycles + 18 + 5 + + + ABSIZE + Alternate bytes size + 16 + 2 + + + ABMODE + Alternate bytes mode + 14 + 2 + + + ADSIZE + Address size + 12 + 2 + + + ADMODE + Address mode + 10 + 2 + + + IMODE + Instruction mode + 8 + 2 + + + INSTRUCTION + Instruction + 0 + 8 + + + + + AR + AR + address register + 0x18 + 0x20 + read-write + 0x00000000 + + + ADDRESS + Address + 0 + 32 + + + + + ABR + ABR + ABR + 0x1C + 0x20 + read-write + 0x00000000 + + + ALTERNATE + ALTERNATE + 0 + 32 + + + + + DR + DR + data register + 0x20 + 0x20 + read-write + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + PSMKR + PSMKR + polling status mask register + 0x24 + 0x20 + read-write + 0x00000000 + + + MASK + Status mask + 0 + 32 + + + + + PSMAR + PSMAR + polling status match register + 0x28 + 0x20 + read-write + 0x00000000 + + + MATCH + Status match + 0 + 32 + + + + + PIR + PIR + polling interval register + 0x2C + 0x20 + read-write + 0x00000000 + + + INTERVAL + Polling interval + 0 + 16 + + + + + LPTR + LPTR + low-power timeout register + 0x30 + 0x20 + read-write + 0x00000000 + + + TIMEOUT + Timeout period + 0 + 16 + + + + + + + RCC + Reset and clock control + RCC + 0x40021000 + + 0x0 + 0x400 + registers + + + RCC + RCC global interrupt + 5 + + + + CR + CR + Clock control register + 0x0 + 0x20 + 0x00000063 + + + PLLSAI2RDY + SAI2 PLL clock ready flag + 29 + 1 + read-only + + + PLLSAI2ON + SAI2 PLL enable + 28 + 1 + read-write + + + PLLSAI1RDY + SAI1 PLL clock ready flag + 27 + 1 + read-only + + + PLLSAI1ON + SAI1 PLL enable + 26 + 1 + read-write + + + PLLRDY + Main PLL clock ready flag + 25 + 1 + read-only + + + PLLON + Main PLL enable + 24 + 1 + read-write + + + CSSON + Clock security system enable + 19 + 1 + write-only + + + HSEBYP + HSE crystal oscillator bypass + 18 + 1 + read-write + + + HSERDY + HSE clock ready flag + 17 + 1 + read-only + + + HSEON + HSE clock enable + 16 + 1 + read-write + + + HSIASFS + HSI automatic start from Stop + 11 + 1 + read-write + + + HSIRDY + HSI clock ready flag + 10 + 1 + read-only + + + HSIKERON + HSI always enable for peripheral kernels + 9 + 1 + read-write + + + HSION + HSI clock enable + 8 + 1 + read-write + + + MSIRANGE + MSI clock ranges + 4 + 4 + read-write + + + MSIRGSEL + MSI clock range selection + 3 + 1 + write-only + + + MSIPLLEN + MSI clock PLL enable + 2 + 1 + read-write + + + MSIRDY + MSI clock ready flag + 1 + 1 + read-only + + + MSION + MSI clock enable + 0 + 1 + read-write + + + + + ICSCR + ICSCR + Internal clock sources calibration register + 0x4 + 0x20 + 0x10000000 + + + HSITRIM + HSI clock trimming + 24 + 7 + read-write + + + HSICAL + HSI clock calibration + 16 + 8 + read-only + + + MSITRIM + MSI clock trimming + 8 + 8 + read-write + + + MSICAL + MSI clock calibration + 0 + 8 + read-only + + + + + CFGR + CFGR + Clock configuration register + 0x8 + 0x20 + 0x00000000 + + + MCOPRE + Microcontroller clock output prescaler + 28 + 3 + read-only + + + MCOSEL + Microcontroller clock output + 24 + 3 + read-write + + + STOPWUCK + Wakeup from Stop and CSS backup clock selection + 15 + 1 + read-write + + + PPRE2 + APB high-speed prescaler (APB2) + 11 + 3 + read-write + + + PPRE1 + PB low-speed prescaler (APB1) + 8 + 3 + read-write + + + HPRE + AHB prescaler + 4 + 4 + read-write + + + SWS + System clock switch status + 2 + 2 + read-only + + + SW + System clock switch + 0 + 2 + read-write + + + + + PLLCFGR + PLLCFGR + PLL configuration register + 0xC + 0x20 + read-write + 0x00001000 + + + PLLR + Main PLL division factor for PLLCLK (system clock) + 25 + 2 + + + PLLREN + Main PLL PLLCLK output enable + 24 + 1 + + + PLLQ + Main PLL division factor for PLLUSB1CLK(48 MHz clock) + 21 + 2 + + + PLLQEN + Main PLL PLLUSB1CLK output enable + 20 + 1 + + + PLLP + Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock) + 17 + 1 + + + PLLPEN + Main PLL PLLSAI3CLK output enable + 16 + 1 + + + PLLN + Main PLL multiplication factor for VCO + 8 + 7 + + + PLLM + Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock + 4 + 3 + + + PLLSRC + Main PLL, PLLSAI1 and PLLSAI2 entry clock source + 0 + 2 + + + PLLPDIV + Main PLL division factor for PLLSAI2CLK + 27 + 5 + + + + + PLLSAI1CFGR + PLLSAI1CFGR + PLLSAI1 configuration register + 0x10 + 0x20 + read-write + 0x00001000 + + + PLLSAI1R + PLLSAI1 division factor for PLLADC1CLK (ADC clock) + 25 + 2 + + + PLLSAI1REN + PLLSAI1 PLLADC1CLK output enable + 24 + 1 + + + PLLSAI1Q + SAI1PLL division factor for PLLUSB2CLK (48 MHz clock) + 21 + 2 + + + PLLSAI1QEN + SAI1PLL PLLUSB2CLK output enable + 20 + 1 + + + PLLSAI1P + SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock) + 17 + 1 + + + PLLSAI1PEN + SAI1PLL PLLSAI1CLK output enable + 16 + 1 + + + PLLSAI1N + SAI1PLL multiplication factor for VCO + 8 + 7 + + + PLLSAI1PDIV + PLLSAI1 division factor for PLLSAI1CLK + 27 + 5 + + + + + PLLSAI2CFGR + PLLSAI2CFGR + PLLSAI2 configuration register + 0x14 + 0x20 + read-write + 0x00001000 + + + PLLSAI2R + PLLSAI2 division factor for PLLADC2CLK (ADC clock) + 25 + 2 + + + PLLSAI2REN + PLLSAI2 PLLADC2CLK output enable + 24 + 1 + + + PLLSAI2P + SAI1PLL division factor for PLLSAI2CLK (SAI1 or SAI2 clock) + 17 + 1 + + + PLLSAI2PEN + SAI2PLL PLLSAI2CLK output enable + 16 + 1 + + + PLLSAI2N + SAI2PLL multiplication factor for VCO + 8 + 7 + + + PLLSAI2PDIV + PLLSAI2 division factor for PLLSAI2CLK + 27 + 5 + + + + + CIER + CIER + Clock interrupt enable register + 0x18 + 0x20 + read-write + 0x00000000 + + + LSECSSIE + LSE clock security system interrupt enable + 9 + 1 + + + PLLSAI2RDYIE + PLLSAI2 ready interrupt enable + 7 + 1 + + + PLLSAI1RDYIE + PLLSAI1 ready interrupt enable + 6 + 1 + + + PLLRDYIE + PLL ready interrupt enable + 5 + 1 + + + HSERDYIE + HSE ready interrupt enable + 4 + 1 + + + HSIRDYIE + HSI ready interrupt enable + 3 + 1 + + + MSIRDYIE + MSI ready interrupt enable + 2 + 1 + + + LSERDYIE + LSE ready interrupt enable + 1 + 1 + + + LSIRDYIE + LSI ready interrupt enable + 0 + 1 + + + HSI48RDYIE + HSI48 ready interrupt enable + 10 + 1 + + + + + CIFR + CIFR + Clock interrupt flag register + 0x1C + 0x20 + read-only + 0x00000000 + + + LSECSSF + LSE Clock security system interrupt flag + 9 + 1 + + + CSSF + Clock security system interrupt flag + 8 + 1 + + + PLLSAI2RDYF + PLLSAI2 ready interrupt flag + 7 + 1 + + + PLLSAI1RDYF + PLLSAI1 ready interrupt flag + 6 + 1 + + + PLLRDYF + PLL ready interrupt flag + 5 + 1 + + + HSERDYF + HSE ready interrupt flag + 4 + 1 + + + HSIRDYF + HSI ready interrupt flag + 3 + 1 + + + MSIRDYF + MSI ready interrupt flag + 2 + 1 + + + LSERDYF + LSE ready interrupt flag + 1 + 1 + + + LSIRDYF + LSI ready interrupt flag + 0 + 1 + + + HSI48RDYF + HSI48 ready interrupt flag + 10 + 1 + + + + + CICR + CICR + Clock interrupt clear register + 0x20 + 0x20 + write-only + 0x00000000 + + + LSECSSC + LSE Clock security system interrupt clear + 9 + 1 + + + CSSC + Clock security system interrupt clear + 8 + 1 + + + PLLSAI2RDYC + PLLSAI2 ready interrupt clear + 7 + 1 + + + PLLSAI1RDYC + PLLSAI1 ready interrupt clear + 6 + 1 + + + PLLRDYC + PLL ready interrupt clear + 5 + 1 + + + HSERDYC + HSE ready interrupt clear + 4 + 1 + + + HSIRDYC + HSI ready interrupt clear + 3 + 1 + + + MSIRDYC + MSI ready interrupt clear + 2 + 1 + + + LSERDYC + LSE ready interrupt clear + 1 + 1 + + + LSIRDYC + LSI ready interrupt clear + 0 + 1 + + + HSI48RDYC + HSI48 oscillator ready interrupt clear + 10 + 1 + + + + + AHB1RSTR + AHB1RSTR + AHB1 peripheral reset register + 0x28 + 0x20 + read-write + 0x00000000 + + + TSCRST + Touch Sensing Controller reset + 16 + 1 + + + CRCRST + CRC reset + 12 + 1 + + + FLASHRST + Flash memory interface reset + 8 + 1 + + + DMA2RST + DMA2 reset + 1 + 1 + + + DMA1RST + DMA1 reset + 0 + 1 + + + DMA2DRST + DMA2D reset + 17 + 1 + + + + + AHB2RSTR + AHB2RSTR + AHB2 peripheral reset register + 0x2C + 0x20 + read-write + 0x00000000 + + + RNGRST + Random number generator reset + 18 + 1 + + + AESRST + AES hardware accelerator reset + 16 + 1 + + + ADCRST + ADC reset + 13 + 1 + + + OTGFSRST + USB OTG FS reset + 12 + 1 + + + GPIOHRST + IO port H reset + 7 + 1 + + + GPIOGRST + IO port G reset + 6 + 1 + + + GPIOFRST + IO port F reset + 5 + 1 + + + GPIOERST + IO port E reset + 4 + 1 + + + GPIODRST + IO port D reset + 3 + 1 + + + GPIOCRST + IO port C reset + 2 + 1 + + + GPIOBRST + IO port B reset + 1 + 1 + + + GPIOARST + IO port A reset + 0 + 1 + + + GPIOIRST + IO port I reset + 8 + 1 + + + DCMIRST + Digital Camera Interface reset + 14 + 1 + + + HASH1RST + Hash reset + 17 + 1 + + + + + AHB3RSTR + AHB3RSTR + AHB3 peripheral reset register + 0x30 + 0x20 + read-write + 0x00000000 + + + QSPIRST + Quad SPI memory interface reset + 8 + 1 + + + FMCRST + Flexible memory controller reset + 0 + 1 + + + + + APB1RSTR1 + APB1RSTR1 + APB1 peripheral reset register 1 + 0x38 + 0x20 + read-write + 0x00000000 + + + LPTIM1RST + Low Power Timer 1 reset + 31 + 1 + + + OPAMPRST + OPAMP interface reset + 30 + 1 + + + DAC1RST + DAC1 interface reset + 29 + 1 + + + PWRRST + Power interface reset + 28 + 1 + + + CAN1RST + CAN1 reset + 25 + 1 + + + I2C3RST + I2C3 reset + 23 + 1 + + + I2C2RST + I2C2 reset + 22 + 1 + + + I2C1RST + I2C1 reset + 21 + 1 + + + UART5RST + UART5 reset + 20 + 1 + + + UART4RST + UART4 reset + 19 + 1 + + + USART3RST + USART3 reset + 18 + 1 + + + USART2RST + USART2 reset + 17 + 1 + + + SPI3RST + SPI3 reset + 15 + 1 + + + SPI2RST + SPI2 reset + 14 + 1 + + + LCDRST + LCD interface reset + 9 + 1 + + + TIM7RST + TIM7 timer reset + 5 + 1 + + + TIM6RST + TIM6 timer reset + 4 + 1 + + + TIM5RST + TIM5 timer reset + 3 + 1 + + + TIM4RST + TIM3 timer reset + 2 + 1 + + + TIM3RST + TIM3 timer reset + 1 + 1 + + + TIM2RST + TIM2 timer reset + 0 + 1 + + + CRSRST + CRS reset + 24 + 1 + + + CAN2RST + CAN2 reset + 26 + 1 + + + + + APB1RSTR2 + APB1RSTR2 + APB1 peripheral reset register 2 + 0x3C + 0x20 + read-write + 0x00000000 + + + LPTIM2RST + Low-power timer 2 reset + 5 + 1 + + + SWPMI1RST + Single wire protocol reset + 2 + 1 + + + LPUART1RST + Low-power UART 1 reset + 0 + 1 + + + I2C4RST + I2C4 reset + 1 + 1 + + + + + APB2RSTR + APB2RSTR + APB2 peripheral reset register + 0x40 + 0x20 + read-write + 0x00000000 + + + DFSDMRST + Digital filters for sigma-delata modulators (DFSDM) reset + 24 + 1 + + + SAI2RST + Serial audio interface 2 (SAI2) reset + 22 + 1 + + + SAI1RST + Serial audio interface 1 (SAI1) reset + 21 + 1 + + + TIM17RST + TIM17 timer reset + 18 + 1 + + + TIM16RST + TIM16 timer reset + 17 + 1 + + + TIM15RST + TIM15 timer reset + 16 + 1 + + + USART1RST + USART1 reset + 14 + 1 + + + TIM8RST + TIM8 timer reset + 13 + 1 + + + SPI1RST + SPI1 reset + 12 + 1 + + + TIM1RST + TIM1 timer reset + 11 + 1 + + + SDMMCRST + SDMMC reset + 10 + 1 + + + SYSCFGRST + System configuration (SYSCFG) reset + 0 + 1 + + + + + AHB1ENR + AHB1ENR + AHB1 peripheral clock enable register + 0x48 + 0x20 + read-write + 0x00000100 + + + TSCEN + Touch Sensing Controller clock enable + 16 + 1 + + + CRCEN + CRC clock enable + 12 + 1 + + + FLASHEN + Flash memory interface clock enable + 8 + 1 + + + DMA2EN + DMA2 clock enable + 1 + 1 + + + DMA1EN + DMA1 clock enable + 0 + 1 + + + DMA2DEN + DMA2D clock enable + 17 + 1 + + + + + AHB2ENR + AHB2ENR + AHB2 peripheral clock enable register + 0x4C + 0x20 + read-write + 0x00000000 + + + RNGEN + Random Number Generator clock enable + 18 + 1 + + + AESEN + AES accelerator clock enable + 16 + 1 + + + ADCEN + ADC clock enable + 13 + 1 + + + OTGFSEN + OTG full speed clock enable + 12 + 1 + + + GPIOHEN + IO port H clock enable + 7 + 1 + + + GPIOGEN + IO port G clock enable + 6 + 1 + + + GPIOFEN + IO port F clock enable + 5 + 1 + + + GPIOEEN + IO port E clock enable + 4 + 1 + + + GPIODEN + IO port D clock enable + 3 + 1 + + + GPIOCEN + IO port C clock enable + 2 + 1 + + + GPIOBEN + IO port B clock enable + 1 + 1 + + + GPIOAEN + IO port A clock enable + 0 + 1 + + + GPIOIEN + IO port I clock enable + 8 + 1 + + + DCMIEN + DCMI clock enable + 14 + 1 + + + HASH1EN + HASH clock enable + 17 + 1 + + + + + AHB3ENR + AHB3ENR + AHB3 peripheral clock enable register + 0x50 + 0x20 + read-write + 0x00000000 + + + QSPIEN + QSPIEN + 8 + 1 + + + FMCEN + Flexible memory controller clock enable + 0 + 1 + + + + + APB1ENR1 + APB1ENR1 + APB1ENR1 + 0x58 + 0x20 + read-write + 0x00000000 + + + LPTIM1EN + Low power timer 1 clock enable + 31 + 1 + + + OPAMPEN + OPAMP interface clock enable + 30 + 1 + + + DAC1EN + DAC1 interface clock enable + 29 + 1 + + + PWREN + Power interface clock enable + 28 + 1 + + + CAN1EN + CAN1 clock enable + 25 + 1 + + + I2C3EN + I2C3 clock enable + 23 + 1 + + + I2C2EN + I2C2 clock enable + 22 + 1 + + + I2C1EN + I2C1 clock enable + 21 + 1 + + + UART5EN + UART5 clock enable + 20 + 1 + + + UART4EN + UART4 clock enable + 19 + 1 + + + USART3EN + USART3 clock enable + 18 + 1 + + + USART2EN + USART2 clock enable + 17 + 1 + + + SP3EN + SPI3 clock enable + 15 + 1 + + + SPI2EN + SPI2 clock enable + 14 + 1 + + + WWDGEN + Window watchdog clock enable + 11 + 1 + + + LCDEN + LCD clock enable + 9 + 1 + + + TIM7EN + TIM7 timer clock enable + 5 + 1 + + + TIM6EN + TIM6 timer clock enable + 4 + 1 + + + TIM5EN + TIM5 timer clock enable + 3 + 1 + + + TIM4EN + TIM4 timer clock enable + 2 + 1 + + + TIM3EN + TIM3 timer clock enable + 1 + 1 + + + TIM2EN + TIM2 timer clock enable + 0 + 1 + + + RTCAPBEN + RTC APB clock enable + 10 + 1 + + + CRSEN + Clock Recovery System clock enable + 24 + 1 + + + CAN2EN + CAN2 clock enable + 26 + 1 + + + + + APB1ENR2 + APB1ENR2 + APB1 peripheral clock enable register 2 + 0x5C + 0x20 + read-write + 0x00000000 + + + LPTIM2EN + LPTIM2EN + 5 + 1 + + + SWPMI1EN + Single wire protocol clock enable + 2 + 1 + + + LPUART1EN + Low power UART 1 clock enable + 0 + 1 + + + I2C4EN + I2C4 clock enable + 1 + 1 + + + + + APB2ENR + APB2ENR + APB2ENR + 0x60 + 0x20 + read-write + 0x00000000 + + + DFSDMEN + DFSDM timer clock enable + 24 + 1 + + + SAI2EN + SAI2 clock enable + 22 + 1 + + + SAI1EN + SAI1 clock enable + 21 + 1 + + + + + TIM17EN + TIM17 timer clock enable + 18 + 1 + + + TIM16EN + TIM16 timer clock enable + 17 + 1 + + + TIM15EN + TIM15 timer clock enable + 16 + 1 + + + USART1EN + USART1clock enable + 14 + 1 + + + TIM8EN + TIM8 timer clock enable + 13 + 1 + + + SPI1EN + SPI1 clock enable + 12 + 1 + + + TIM1EN + TIM1 timer clock enable + 11 + 1 + + + SDMMCEN + SDMMC clock enable + 10 + 1 + + + FIREWALLEN + Firewall clock enable + 7 + 1 + + + SYSCFGEN + SYSCFG clock enable + 0 + 1 + + + + + AHB1SMENR + AHB1SMENR + AHB1 peripheral clocks enable in Sleep and Stop modes register + 0x68 + 0x20 + read-write + 0x00011303 + + + TSCSMEN + Touch Sensing Controller clocks enable during Sleep and Stop modes + 16 + 1 + + + CRCSMEN + CRCSMEN + 12 + 1 + + + SRAM1SMEN + SRAM1 interface clocks enable during Sleep and Stop modes + 9 + 1 + + + FLASHSMEN + Flash memory interface clocks enable during Sleep and Stop modes + 8 + 1 + + + DMA2SMEN + DMA2 clocks enable during Sleep and Stop modes + 1 + 1 + + + DMA1SMEN + DMA1 clocks enable during Sleep and Stop modes + 0 + 1 + + + DMA2DSMEN + DMA2D clock enable during Sleep and Stop modes + 17 + 1 + + + + + AHB2SMENR + AHB2SMENR + AHB2 peripheral clocks enable in Sleep and Stop modes register + 0x6C + 0x20 + read-write + 0x000532FF + + + RNGSMEN + Random Number Generator clocks enable during Sleep and Stop modes + 18 + 1 + + + AESSMEN + AES accelerator clocks enable during Sleep and Stop modes + 16 + 1 + + + ADCFSSMEN + ADC clocks enable during Sleep and Stop modes + 13 + 1 + + + OTGFSSMEN + OTG full speed clocks enable during Sleep and Stop modes + 12 + 1 + + + SRAM2SMEN + SRAM2 interface clocks enable during Sleep and Stop modes + 9 + 1 + + + GPIOHSMEN + IO port H clocks enable during Sleep and Stop modes + 7 + 1 + + + GPIOGSMEN + IO port G clocks enable during Sleep and Stop modes + 6 + 1 + + + GPIOFSMEN + IO port F clocks enable during Sleep and Stop modes + 5 + 1 + + + GPIOESMEN + IO port E clocks enable during Sleep and Stop modes + 4 + 1 + + + GPIODSMEN + IO port D clocks enable during Sleep and Stop modes + 3 + 1 + + + GPIOCSMEN + IO port C clocks enable during Sleep and Stop modes + 2 + 1 + + + GPIOBSMEN + IO port B clocks enable during Sleep and Stop modes + 1 + 1 + + + GPIOASMEN + IO port A clocks enable during Sleep and Stop modes + 0 + 1 + + + GPIOISMEN + IO port I clocks enable during Sleep and Stop modes + 8 + 1 + + + DCMISMEN + DCMI clock enable during Sleep and Stop modes + 14 + 1 + + + HASH1SMEN + HASH clock enable during Sleep and Stop modes + 17 + 1 + + + + + AHB3SMENR + AHB3SMENR + AHB3 peripheral clocks enable in Sleep and Stop modes register + 0x70 + 0x20 + read-write + 0x000000101 + + + QSPISMEN + QSPISMEN + 8 + 1 + + + FMCSMEN + Flexible memory controller clocks enable during Sleep and Stop modes + 0 + 1 + + + + + APB1SMENR1 + APB1SMENR1 + APB1SMENR1 + 0x78 + 0x20 + read-write + 0xF2FECA3F + + + LPTIM1SMEN + Low power timer 1 clocks enable during Sleep and Stop modes + 31 + 1 + + + OPAMPSMEN + OPAMP interface clocks enable during Sleep and Stop modes + 30 + 1 + + + DAC1SMEN + DAC1 interface clocks enable during Sleep and Stop modes + 29 + 1 + + + PWRSMEN + Power interface clocks enable during Sleep and Stop modes + 28 + 1 + + + CAN1SMEN + CAN1 clocks enable during Sleep and Stop modes + 25 + 1 + + + I2C3SMEN + I2C3 clocks enable during Sleep and Stop modes + 23 + 1 + + + I2C2SMEN + I2C2 clocks enable during Sleep and Stop modes + 22 + 1 + + + I2C1SMEN + I2C1 clocks enable during Sleep and Stop modes + 21 + 1 + + + UART5SMEN + UART5 clocks enable during Sleep and Stop modes + 20 + 1 + + + UART4SMEN + UART4 clocks enable during Sleep and Stop modes + 19 + 1 + + + USART3SMEN + USART3 clocks enable during Sleep and Stop modes + 18 + 1 + + + USART2SMEN + USART2 clocks enable during Sleep and Stop modes + 17 + 1 + + + SP3SMEN + SPI3 clocks enable during Sleep and Stop modes + 15 + 1 + + + SPI2SMEN + SPI2 clocks enable during Sleep and Stop modes + 14 + 1 + + + WWDGSMEN + Window watchdog clocks enable during Sleep and Stop modes + 11 + 1 + + + LCDSMEN + LCD clocks enable during Sleep and Stop modes + 9 + 1 + + + TIM7SMEN + TIM7 timer clocks enable during Sleep and Stop modes + 5 + 1 + + + TIM6SMEN + TIM6 timer clocks enable during Sleep and Stop modes + 4 + 1 + + + TIM5SMEN + TIM5 timer clocks enable during Sleep and Stop modes + 3 + 1 + + + TIM4SMEN + TIM4 timer clocks enable during Sleep and Stop modes + 2 + 1 + + + TIM3SMEN + TIM3 timer clocks enable during Sleep and Stop modes + 1 + 1 + + + TIM2SMEN + TIM2 timer clocks enable during Sleep and Stop modes + 0 + 1 + + + RTCAPBSMEN + RTC APB clock enable during Sleep and Stop modes + 10 + 1 + + + CAN2SMEN + CAN2 clocks enable during Sleep and Stop modes + 26 + 1 + + + + + APB1SMENR2 + APB1SMENR2 + APB1 peripheral clocks enable in Sleep and Stop modes register 2 + 0x7C + 0x20 + read-write + 0x000000025 + + + LPTIM2SMEN + LPTIM2SMEN + 5 + 1 + + + SWPMI1SMEN + Single wire protocol clocks enable during Sleep and Stop modes + 2 + 1 + + + LPUART1SMEN + Low power UART 1 clocks enable during Sleep and Stop modes + 0 + 1 + + + I2C4SMEN + I2C4 clocks enable during Sleep and Stop modes + 1 + 1 + + + + + APB2SMENR + APB2SMENR + APB2SMENR + 0x80 + 0x20 + read-write + 0x01677C01 + + + DFSDMSMEN + DFSDM timer clocks enable during Sleep and Stop modes + 24 + 1 + + + SAI2SMEN + SAI2 clocks enable during Sleep and Stop modes + 22 + 1 + + + SAI1SMEN + SAI1 clocks enable during Sleep and Stop modes + 21 + 1 + + + TIM17SMEN + TIM17 timer clocks enable during Sleep and Stop modes + 18 + 1 + + + TIM16SMEN + TIM16 timer clocks enable during Sleep and Stop modes + 17 + 1 + + + TIM15SMEN + TIM15 timer clocks enable during Sleep and Stop modes + 16 + 1 + + + USART1SMEN + USART1clocks enable during Sleep and Stop modes + 14 + 1 + + + TIM8SMEN + TIM8 timer clocks enable during Sleep and Stop modes + 13 + 1 + + + SPI1SMEN + SPI1 clocks enable during Sleep and Stop modes + 12 + 1 + + + TIM1SMEN + TIM1 timer clocks enable during Sleep and Stop modes + 11 + 1 + + + SDMMCSMEN + SDMMC clocks enable during Sleep and Stop modes + 10 + 1 + + + SYSCFGSMEN + SYSCFG clocks enable during Sleep and Stop modes + 0 + 1 + + + + + CCIPR + CCIPR + CCIPR + 0x88 + 0x20 + read-write + 0x00000000 + + + DFSDMSEL + DFSDM clock source selection + 31 + 1 + + + SWPMI1SEL + SWPMI1 clock source selection + 30 + 1 + + + ADCSEL + ADCs clock source selection + 28 + 2 + + + CLK48SEL + 48 MHz clock source selection + 26 + 2 + + + SAI2SEL + SAI2 clock source selection + 24 + 2 + + + SAI1SEL + SAI1 clock source selection + 22 + 2 + + + LPTIM2SEL + Low power timer 2 clock source selection + 20 + 2 + + + LPTIM1SEL + Low power timer 1 clock source selection + 18 + 2 + + + I2C3SEL + I2C3 clock source selection + 16 + 2 + + + I2C2SEL + I2C2 clock source selection + 14 + 2 + + + I2C1SEL + I2C1 clock source selection + 12 + 2 + + + LPUART1SEL + LPUART1 clock source selection + 10 + 2 + + + UART5SEL + UART5 clock source selection + 8 + 2 + + + UART4SEL + UART4 clock source selection + 6 + 2 + + + USART3SEL + USART3 clock source selection + 4 + 2 + + + USART2SEL + USART2 clock source selection + 2 + 2 + + + USART1SEL + USART1 clock source selection + 0 + 2 + + + + + BDCR + BDCR + BDCR + 0x90 + 0x20 + 0x00000000 + + + LSCOSEL + Low speed clock output selection + 25 + 1 + read-write + + + LSCOEN + Low speed clock output enable + 24 + 1 + read-write + + + BDRST + Backup domain software reset + 16 + 1 + read-write + + + RTCEN + RTC clock enable + 15 + 1 + read-write + + + RTCSEL + RTC clock source selection + 8 + 2 + read-write + + + LSECSSD + LSECSSD + 6 + 1 + read-only + + + LSECSSON + LSECSSON + 5 + 1 + read-write + + + LSEDRV + SE oscillator drive capability + 3 + 2 + read-write + + + LSEBYP + LSE oscillator bypass + 2 + 1 + read-write + + + LSERDY + LSE oscillator ready + 1 + 1 + read-only + + + LSEON + LSE oscillator enable + 0 + 1 + read-write + + + + + CSR + CSR + CSR + 0x94 + 0x20 + 0x0C000600 + + + LPWRSTF + Low-power reset flag + 31 + 1 + read-only + + + WWDGRSTF + Window watchdog reset flag + 30 + 1 + read-only + + + IWDGRSTF + Independent window watchdog reset flag + 29 + 1 + read-only + + + SFTRSTF + Software reset flag + 28 + 1 + read-only + + + BORRSTF + BOR flag + 27 + 1 + read-only + + + PINRSTF + Pin reset flag + 26 + 1 + read-only + + + OBLRSTF + Option byte loader reset flag + 25 + 1 + read-only + + + FIREWALLRSTF + Firewall reset flag + 24 + 1 + read-only + + + RMVF + Remove reset flag + 23 + 1 + read-write + + + MSISRANGE + SI range after Standby mode + 8 + 4 + read-write + + + LSIRDY + LSI oscillator ready + 1 + 1 + read-only + + + LSION + LSI oscillator enable + 0 + 1 + read-write + + + + + + + PWR + Power control + PWR + 0x40007000 + + 0x0 + 0x400 + registers + + + + CR1 + CR1 + Power control register 1 + 0x0 + 0x20 + read-write + 0x00000200 + + + LPR + Low-power run + 14 + 1 + + + VOS + Voltage scaling range selection + 9 + 2 + + + DBP + Disable backup domain write protection + 8 + 1 + + + LPMS + Low-power mode selection + 0 + 3 + + + + + CR2 + CR2 + Power control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + USV + VDDUSB USB supply valid + 10 + 1 + + + IOSV + VDDIO2 Independent I/Os supply valid + 9 + 1 + + + PVME4 + Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V + 7 + 1 + + + PVME3 + Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V + 6 + 1 + + + PVME2 + Peripheral voltage monitoring 2 enable: VDDIO2 vs. 0.9V + 5 + 1 + + + PVME1 + Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V + 4 + 1 + + + PLS + Power voltage detector level selection + 1 + 3 + + + PVDE + Power voltage detector enable + 0 + 1 + + + + + CR3 + CR3 + Power control register 3 + 0x8 + 0x20 + read-write + 0X00008000 + + + EWF + Enable internal wakeup line + 15 + 1 + + + APC + Apply pull-up and pull-down configuration + 10 + 1 + + + RRS + SRAM2 retention in Standby mode + 8 + 1 + + + EWUP5 + Enable Wakeup pin WKUP5 + 4 + 1 + + + EWUP4 + Enable Wakeup pin WKUP4 + 3 + 1 + + + EWUP3 + Enable Wakeup pin WKUP3 + 2 + 1 + + + EWUP2 + Enable Wakeup pin WKUP2 + 1 + 1 + + + EWUP1 + Enable Wakeup pin WKUP1 + 0 + 1 + + + + + CR4 + CR4 + Power control register 4 + 0xC + 0x20 + read-write + 0x00000000 + + + VBRS + VBAT battery charging resistor selection + 9 + 1 + + + VBE + VBAT battery charging enable + 8 + 1 + + + WP5 + Wakeup pin WKUP5 polarity + 4 + 1 + + + WP4 + Wakeup pin WKUP4 polarity + 3 + 1 + + + WP3 + Wakeup pin WKUP3 polarity + 2 + 1 + + + WP2 + Wakeup pin WKUP2 polarity + 1 + 1 + + + WP1 + Wakeup pin WKUP1 polarity + 0 + 1 + + + + + SR1 + SR1 + Power status register 1 + 0x10 + 0x20 + read-only + 0x00000000 + + + WUFI + Wakeup flag internal + 15 + 1 + + + SBF + Standby flag + 8 + 1 + + + WUF5 + Wakeup flag 5 + 4 + 1 + + + WUF4 + Wakeup flag 4 + 3 + 1 + + + WUF3 + Wakeup flag 3 + 2 + 1 + + + WUF2 + Wakeup flag 2 + 1 + 1 + + + WUF1 + Wakeup flag 1 + 0 + 1 + + + + + SR2 + SR2 + Power status register 2 + 0x14 + 0x20 + read-only + 0x00000000 + + + PVMO4 + Peripheral voltage monitoring output: VDDA vs. 2.2 V + 15 + 1 + + + PVMO3 + Peripheral voltage monitoring output: VDDA vs. 1.62 V + 14 + 1 + + + PVMO2 + Peripheral voltage monitoring output: VDDIO2 vs. 0.9 V + 13 + 1 + + + PVMO1 + Peripheral voltage monitoring output: VDDUSB vs. 1.2 V + 12 + 1 + + + PVDO + Power voltage detector output + 11 + 1 + + + VOSF + Voltage scaling flag + 10 + 1 + + + REGLPF + Low-power regulator flag + 9 + 1 + + + REGLPS + Low-power regulator started + 8 + 1 + + + + + SCR + SCR + Power status clear register + 0x18 + 0x20 + write-only + 0x00000000 + + + CSBF + Clear standby flag + 8 + 1 + + + CWUF5 + Clear wakeup flag 5 + 4 + 1 + + + CWUF4 + Clear wakeup flag 4 + 3 + 1 + + + CWUF3 + Clear wakeup flag 3 + 2 + 1 + + + CWUF2 + Clear wakeup flag 2 + 1 + 1 + + + CWUF1 + Clear wakeup flag 1 + 0 + 1 + + + + + PUCRA + PUCRA + Power Port A pull-up control register + 0x20 + 0x20 + read-write + 0x00000000 + + + PU15 + Port A pull-up bit y (y=0..15) + 15 + 1 + + + PU14 + Port A pull-up bit y (y=0..15) + 14 + 1 + + + PU13 + Port A pull-up bit y (y=0..15) + 13 + 1 + + + PU12 + Port A pull-up bit y (y=0..15) + 12 + 1 + + + PU11 + Port A pull-up bit y (y=0..15) + 11 + 1 + + + PU10 + Port A pull-up bit y (y=0..15) + 10 + 1 + + + PU9 + Port A pull-up bit y (y=0..15) + 9 + 1 + + + PU8 + Port A pull-up bit y (y=0..15) + 8 + 1 + + + PU7 + Port A pull-up bit y (y=0..15) + 7 + 1 + + + PU6 + Port A pull-up bit y (y=0..15) + 6 + 1 + + + PU5 + Port A pull-up bit y (y=0..15) + 5 + 1 + + + PU4 + Port A pull-up bit y (y=0..15) + 4 + 1 + + + PU3 + Port A pull-up bit y (y=0..15) + 3 + 1 + + + PU2 + Port A pull-up bit y (y=0..15) + 2 + 1 + + + PU1 + Port A pull-up bit y (y=0..15) + 1 + 1 + + + PU0 + Port A pull-up bit y (y=0..15) + 0 + 1 + + + + + PDCRA + PDCRA + Power Port A pull-down control register + 0x24 + 0x20 + read-write + 0x00000000 + + + PD15 + Port A pull-down bit y (y=0..15) + 15 + 1 + + + PD14 + Port A pull-down bit y (y=0..15) + 14 + 1 + + + PD13 + Port A pull-down bit y (y=0..15) + 13 + 1 + + + PD12 + Port A pull-down bit y (y=0..15) + 12 + 1 + + + PD11 + Port A pull-down bit y (y=0..15) + 11 + 1 + + + PD10 + Port A pull-down bit y (y=0..15) + 10 + 1 + + + PD9 + Port A pull-down bit y (y=0..15) + 9 + 1 + + + PD8 + Port A pull-down bit y (y=0..15) + 8 + 1 + + + PD7 + Port A pull-down bit y (y=0..15) + 7 + 1 + + + PD6 + Port A pull-down bit y (y=0..15) + 6 + 1 + + + PD5 + Port A pull-down bit y (y=0..15) + 5 + 1 + + + PD4 + Port A pull-down bit y (y=0..15) + 4 + 1 + + + PD3 + Port A pull-down bit y (y=0..15) + 3 + 1 + + + PD2 + Port A pull-down bit y (y=0..15) + 2 + 1 + + + PD1 + Port A pull-down bit y (y=0..15) + 1 + 1 + + + PD0 + Port A pull-down bit y (y=0..15) + 0 + 1 + + + + + PUCRB + PUCRB + Power Port B pull-up control register + 0x28 + 0x20 + read-write + 0x00000000 + + + PU15 + Port B pull-up bit y (y=0..15) + 15 + 1 + + + PU14 + Port B pull-up bit y (y=0..15) + 14 + 1 + + + PU13 + Port B pull-up bit y (y=0..15) + 13 + 1 + + + PU12 + Port B pull-up bit y (y=0..15) + 12 + 1 + + + PU11 + Port B pull-up bit y (y=0..15) + 11 + 1 + + + PU10 + Port B pull-up bit y (y=0..15) + 10 + 1 + + + PU9 + Port B pull-up bit y (y=0..15) + 9 + 1 + + + PU8 + Port B pull-up bit y (y=0..15) + 8 + 1 + + + PU7 + Port B pull-up bit y (y=0..15) + 7 + 1 + + + PU6 + Port B pull-up bit y (y=0..15) + 6 + 1 + + + PU5 + Port B pull-up bit y (y=0..15) + 5 + 1 + + + PU4 + Port B pull-up bit y (y=0..15) + 4 + 1 + + + PU3 + Port B pull-up bit y (y=0..15) + 3 + 1 + + + PU2 + Port B pull-up bit y (y=0..15) + 2 + 1 + + + PU1 + Port B pull-up bit y (y=0..15) + 1 + 1 + + + PU0 + Port B pull-up bit y (y=0..15) + 0 + 1 + + + + + PDCRB + PDCRB + Power Port B pull-down control register + 0x2C + 0x20 + read-write + 0x00000000 + + + PD15 + Port B pull-down bit y (y=0..15) + 15 + 1 + + + PD14 + Port B pull-down bit y (y=0..15) + 14 + 1 + + + PD13 + Port B pull-down bit y (y=0..15) + 13 + 1 + + + PD12 + Port B pull-down bit y (y=0..15) + 12 + 1 + + + PD11 + Port B pull-down bit y (y=0..15) + 11 + 1 + + + PD10 + Port B pull-down bit y (y=0..15) + 10 + 1 + + + PD9 + Port B pull-down bit y (y=0..15) + 9 + 1 + + + PD8 + Port B pull-down bit y (y=0..15) + 8 + 1 + + + PD7 + Port B pull-down bit y (y=0..15) + 7 + 1 + + + PD6 + Port B pull-down bit y (y=0..15) + 6 + 1 + + + PD5 + Port B pull-down bit y (y=0..15) + 5 + 1 + + + PD4 + Port B pull-down bit y (y=0..15) + 4 + 1 + + + PD3 + Port B pull-down bit y (y=0..15) + 3 + 1 + + + PD2 + Port B pull-down bit y (y=0..15) + 2 + 1 + + + PD1 + Port B pull-down bit y (y=0..15) + 1 + 1 + + + PD0 + Port B pull-down bit y (y=0..15) + 0 + 1 + + + + + PUCRC + PUCRC + Power Port C pull-up control register + 0x30 + 0x20 + read-write + 0x00000000 + + + PU15 + Port C pull-up bit y (y=0..15) + 15 + 1 + + + PU14 + Port C pull-up bit y (y=0..15) + 14 + 1 + + + PU13 + Port C pull-up bit y (y=0..15) + 13 + 1 + + + PU12 + Port C pull-up bit y (y=0..15) + 12 + 1 + + + PU11 + Port C pull-up bit y (y=0..15) + 11 + 1 + + + PU10 + Port C pull-up bit y (y=0..15) + 10 + 1 + + + PU9 + Port C pull-up bit y (y=0..15) + 9 + 1 + + + PU8 + Port C pull-up bit y (y=0..15) + 8 + 1 + + + PU7 + Port C pull-up bit y (y=0..15) + 7 + 1 + + + PU6 + Port C pull-up bit y (y=0..15) + 6 + 1 + + + PU5 + Port C pull-up bit y (y=0..15) + 5 + 1 + + + PU4 + Port C pull-up bit y (y=0..15) + 4 + 1 + + + PU3 + Port C pull-up bit y (y=0..15) + 3 + 1 + + + PU2 + Port C pull-up bit y (y=0..15) + 2 + 1 + + + PU1 + Port C pull-up bit y (y=0..15) + 1 + 1 + + + PU0 + Port C pull-up bit y (y=0..15) + 0 + 1 + + + + + PDCRC + PDCRC + Power Port C pull-down control register + 0x34 + 0x20 + read-write + 0x00000000 + + + PD15 + Port C pull-down bit y (y=0..15) + 15 + 1 + + + PD14 + Port C pull-down bit y (y=0..15) + 14 + 1 + + + PD13 + Port C pull-down bit y (y=0..15) + 13 + 1 + + + PD12 + Port C pull-down bit y (y=0..15) + 12 + 1 + + + PD11 + Port C pull-down bit y (y=0..15) + 11 + 1 + + + PD10 + Port C pull-down bit y (y=0..15) + 10 + 1 + + + PD9 + Port C pull-down bit y (y=0..15) + 9 + 1 + + + PD8 + Port C pull-down bit y (y=0..15) + 8 + 1 + + + PD7 + Port C pull-down bit y (y=0..15) + 7 + 1 + + + PD6 + Port C pull-down bit y (y=0..15) + 6 + 1 + + + PD5 + Port C pull-down bit y (y=0..15) + 5 + 1 + + + PD4 + Port C pull-down bit y (y=0..15) + 4 + 1 + + + PD3 + Port C pull-down bit y (y=0..15) + 3 + 1 + + + PD2 + Port C pull-down bit y (y=0..15) + 2 + 1 + + + PD1 + Port C pull-down bit y (y=0..15) + 1 + 1 + + + PD0 + Port C pull-down bit y (y=0..15) + 0 + 1 + + + + + PUCRD + PUCRD + Power Port D pull-up control register + 0x38 + 0x20 + read-write + 0x00000000 + + + PU15 + Port D pull-up bit y (y=0..15) + 15 + 1 + + + PU14 + Port D pull-up bit y (y=0..15) + 14 + 1 + + + PU13 + Port D pull-up bit y (y=0..15) + 13 + 1 + + + PU12 + Port D pull-up bit y (y=0..15) + 12 + 1 + + + PU11 + Port D pull-up bit y (y=0..15) + 11 + 1 + + + PU10 + Port D pull-up bit y (y=0..15) + 10 + 1 + + + PU9 + Port D pull-up bit y (y=0..15) + 9 + 1 + + + PU8 + Port D pull-up bit y (y=0..15) + 8 + 1 + + + PU7 + Port D pull-up bit y (y=0..15) + 7 + 1 + + + PU6 + Port D pull-up bit y (y=0..15) + 6 + 1 + + + PU5 + Port D pull-up bit y (y=0..15) + 5 + 1 + + + PU4 + Port D pull-up bit y (y=0..15) + 4 + 1 + + + PU3 + Port D pull-up bit y (y=0..15) + 3 + 1 + + + PU2 + Port D pull-up bit y (y=0..15) + 2 + 1 + + + PU1 + Port D pull-up bit y (y=0..15) + 1 + 1 + + + PU0 + Port D pull-up bit y (y=0..15) + 0 + 1 + + + + + PDCRD + PDCRD + Power Port D pull-down control register + 0x3C + 0x20 + read-write + 0x00000000 + + + PD15 + Port D pull-down bit y (y=0..15) + 15 + 1 + + + PD14 + Port D pull-down bit y (y=0..15) + 14 + 1 + + + PD13 + Port D pull-down bit y (y=0..15) + 13 + 1 + + + PD12 + Port D pull-down bit y (y=0..15) + 12 + 1 + + + PD11 + Port D pull-down bit y (y=0..15) + 11 + 1 + + + PD10 + Port D pull-down bit y (y=0..15) + 10 + 1 + + + PD9 + Port D pull-down bit y (y=0..15) + 9 + 1 + + + PD8 + Port D pull-down bit y (y=0..15) + 8 + 1 + + + PD7 + Port D pull-down bit y (y=0..15) + 7 + 1 + + + PD6 + Port D pull-down bit y (y=0..15) + 6 + 1 + + + PD5 + Port D pull-down bit y (y=0..15) + 5 + 1 + + + PD4 + Port D pull-down bit y (y=0..15) + 4 + 1 + + + PD3 + Port D pull-down bit y (y=0..15) + 3 + 1 + + + PD2 + Port D pull-down bit y (y=0..15) + 2 + 1 + + + PD1 + Port D pull-down bit y (y=0..15) + 1 + 1 + + + PD0 + Port D pull-down bit y (y=0..15) + 0 + 1 + + + + + PUCRE + PUCRE + Power Port E pull-up control register + 0x40 + 0x20 + read-write + 0x00000000 + + + PU15 + Port E pull-up bit y (y=0..15) + 15 + 1 + + + PU14 + Port E pull-up bit y (y=0..15) + 14 + 1 + + + PU13 + Port E pull-up bit y (y=0..15) + 13 + 1 + + + PU12 + Port E pull-up bit y (y=0..15) + 12 + 1 + + + PU11 + Port E pull-up bit y (y=0..15) + 11 + 1 + + + PU10 + Port E pull-up bit y (y=0..15) + 10 + 1 + + + PU9 + Port E pull-up bit y (y=0..15) + 9 + 1 + + + PU8 + Port E pull-up bit y (y=0..15) + 8 + 1 + + + PU7 + Port E pull-up bit y (y=0..15) + 7 + 1 + + + PU6 + Port E pull-up bit y (y=0..15) + 6 + 1 + + + PU5 + Port E pull-up bit y (y=0..15) + 5 + 1 + + + PU4 + Port E pull-up bit y (y=0..15) + 4 + 1 + + + PU3 + Port E pull-up bit y (y=0..15) + 3 + 1 + + + PU2 + Port E pull-up bit y (y=0..15) + 2 + 1 + + + PU1 + Port E pull-up bit y (y=0..15) + 1 + 1 + + + PU0 + Port E pull-up bit y (y=0..15) + 0 + 1 + + + + + PDCRE + PDCRE + Power Port E pull-down control register + 0x44 + 0x20 + read-write + 0x00000000 + + + PD15 + Port E pull-down bit y (y=0..15) + 15 + 1 + + + PD14 + Port E pull-down bit y (y=0..15) + 14 + 1 + + + PD13 + Port E pull-down bit y (y=0..15) + 13 + 1 + + + PD12 + Port E pull-down bit y (y=0..15) + 12 + 1 + + + PD11 + Port E pull-down bit y (y=0..15) + 11 + 1 + + + PD10 + Port E pull-down bit y (y=0..15) + 10 + 1 + + + PD9 + Port E pull-down bit y (y=0..15) + 9 + 1 + + + PD8 + Port E pull-down bit y (y=0..15) + 8 + 1 + + + PD7 + Port E pull-down bit y (y=0..15) + 7 + 1 + + + PD6 + Port E pull-down bit y (y=0..15) + 6 + 1 + + + PD5 + Port E pull-down bit y (y=0..15) + 5 + 1 + + + PD4 + Port E pull-down bit y (y=0..15) + 4 + 1 + + + PD3 + Port E pull-down bit y (y=0..15) + 3 + 1 + + + PD2 + Port E pull-down bit y (y=0..15) + 2 + 1 + + + PD1 + Port E pull-down bit y (y=0..15) + 1 + 1 + + + PD0 + Port E pull-down bit y (y=0..15) + 0 + 1 + + + + + PUCRF + PUCRF + Power Port F pull-up control register + 0x48 + 0x20 + read-write + 0x00000000 + + + PU15 + Port F pull-up bit y (y=0..15) + 15 + 1 + + + PU14 + Port F pull-up bit y (y=0..15) + 14 + 1 + + + PU13 + Port F pull-up bit y (y=0..15) + 13 + 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+ 24 + + + DTRBS + DTRBS + 3 + 5 + + + + + CH5AWSCDR + CH5AWSCDR + CH5AWSCDR + 0xA8 + 0x20 + read-write + 0x0 + + + AWFORD + AWFORD + 22 + 2 + + + AWFOSR + AWFOSR + 16 + 5 + + + BKSCD + BKSCD + 12 + 4 + + + SCDT + SCDT + 0 + 8 + + + + + CH5WDATR + CH5WDATR + CH5WDATR + 0xAC + 0x20 + read-write + 0x0 + + + WDATA + WDATA + 0 + 16 + + + + + CH5DATINR + CH5DATINR + CH5DATINR + 0xB0 + 0x20 + read-write + 0x0 + + + INDAT1 + INDAT1 + 16 + 16 + + + INDAT0 + INDAT0 + 0 + 16 + + + + + CH5DLYR + CH5DLYR + channel y delay register + 0xB4 + 0x20 + read-write + 0x0 + + + PLSSKP + PLSSKP + 0 + 6 + + + + + CH6CFGR1 + CH6CFGR1 + CH6CFGR1 + 0xC0 + 0x20 + read-write + 0x0 + + + DATPACK + DATPACK + 14 + 2 + + + DATMPX + DATMPX + 12 + 2 + + + CHINSEL + CHINSEL + 8 + 1 + + + CHEN + CHEN + 7 + 1 + + + CKABEN + CKABEN + 6 + 1 + + + SCDEN + SCDEN + 5 + 1 + + + SPICKSEL + SPICKSEL + 2 + 2 + + + SITP + SITP + 0 + 2 + + + + + CH6CFGR2 + CH6CFGR2 + CH6CFGR2 + 0xC4 + 0x20 + read-write + 0x0 + + + OFFSET + OFFSET + 8 + 24 + + + DTRBS + DTRBS + 3 + 5 + + + + + CH6AWSCDR + CH6AWSCDR + CH6AWSCDR + 0xC8 + 0x20 + read-write + 0x0 + + + AWFORD + AWFORD + 22 + 2 + + + AWFOSR + AWFOSR + 16 + 5 + + + BKSCD + BKSCD + 12 + 4 + + + SCDT + SCDT + 0 + 8 + + + + + CH6WDATR + CH6WDATR + CH6WDATR + 0xCC + 0x20 + read-write + 0x0 + + + WDATA + WDATA + 0 + 16 + + + + + CH6DATINR + CH6DATINR + CH6DATINR + 0xD0 + 0x20 + read-write + 0x0 + + + INDAT1 + INDAT1 + 16 + 16 + + + INDAT0 + INDAT0 + 0 + 16 + + + + + CH6DLYR + CH6DLYR + channel y delay register + 0xD4 + 0x20 + read-write + 0x0 + + + PLSSKP + PLSSKP + 0 + 6 + + + + + CH7CFGR1 + CH7CFGR1 + CH7CFGR1 + 0xE0 + 0x20 + read-write + 0x0 + + + DATPACK + DATPACK + 14 + 2 + + + DATMPX + DATMPX + 12 + 2 + + + CHINSEL + CHINSEL + 8 + 1 + + + CHEN + CHEN + 7 + 1 + + + CKABEN + CKABEN + 6 + 1 + + + SCDEN + SCDEN + 5 + 1 + + + SPICKSEL + SPICKSEL + 2 + 2 + + + SITP + SITP + 0 + 2 + + + + + CH7CFGR2 + CH7CFGR2 + CH7CFGR2 + 0xE4 + 0x20 + read-write + 0x0 + + + OFFSET + OFFSET + 8 + 24 + + + DTRBS + DTRBS + 3 + 5 + + + + + CH7AWSCDR + CH7AWSCDR + CH7AWSCDR + 0xE8 + 0x20 + read-write + 0x0 + + + AWFORD + AWFORD + 22 + 2 + + + AWFOSR + AWFOSR + 16 + 5 + + + BKSCD + BKSCD + 12 + 4 + + + SCDT + SCDT + 0 + 8 + + + + + CH7WDATR + CH7WDATR + CH7WDATR + 0xEC + 0x20 + read-write + 0x0 + + + WDATA + WDATA + 0 + 16 + + + + + CH7DATINR + CH7DATINR + CH7DATINR + 0xF0 + 0x20 + read-write + 0x0 + + + INDAT1 + INDAT1 + 16 + 16 + + + INDAT0 + INDAT0 + 0 + 16 + + + + + CH7DLYR + CH7DLYR + channel y delay register + 0xF4 + 0x20 + read-write + 0x0 + + + PLSSKP + PLSSKP + 0 + 6 + + + + + DFSDM_FLT0CR1 + DFSDM_FLT0CR1 + control register 1 + 0x100 + 0x20 + read-write + 0x00000000 + + + AWFSEL + Analog watchdog fast mode + select + 30 + 1 + + + FAST + Fast conversion mode selection for + regular conversions + 29 + 1 + + + RCH + Regular channel selection + 24 + 3 + + + RDMAEN + DMA channel enabled to read data for the + regular conversion + 21 + 1 + + + RSYNC + Launch regular conversion synchronously + with DFSDM0 + 19 + 1 + + + RCONT + Continuous mode selection for regular + conversions + 18 + 1 + + + RSWSTART + Software start of a conversion on the + regular channel + 17 + 1 + + + JEXTEN + Trigger enable and trigger edge + selection for injected conversions + 13 + 2 + + + JEXTSEL + Trigger signal selection for launching + injected conversions + 8 + 3 + + + JDMAEN + DMA channel enabled to read data for the + injected channel group + 5 + 1 + + + JSCAN + Scanning conversion mode for injected + conversions + 4 + 1 + + + JSYNC + Launch an injected conversion + synchronously with the DFSDM0 JSWSTART + trigger + 3 + 1 + + + JSWSTART + Start a conversion of the injected group + of channels + 1 + 1 + + + DFEN + DFSDM enable + 0 + 1 + + + + + DFSDM_FLT0CR2 + DFSDM_FLT0CR2 + control register 2 + 0x104 + 0x20 + read-write + 0x00000000 + + + AWDCH + Analog watchdog channel + selection + 16 + 8 + + + EXCH + Extremes detector channel + selection + 8 + 8 + + + CKABIE + Clock absence interrupt + enable + 6 + 1 + + + SCDIE + Short-circuit detector interrupt + enable + 5 + 1 + + + AWDIE + Analog watchdog interrupt + enable + 4 + 1 + + + ROVRIE + Regular data overrun interrupt + enable + 3 + 1 + + + JOVRIE + Injected data overrun interrupt + enable + 2 + 1 + + + REOCIE + Regular end of conversion interrupt + enable + 1 + 1 + + + JEOCIE + Injected end of conversion interrupt + enable + 0 + 1 + + + + + DFSDM_FLT0ISR + DFSDM_FLT0ISR + interrupt and status register + 0x108 + 0x20 + read-only + 0x00FF0000 + + + SCDF + short-circuit detector + flag + 24 + 8 + + + CKABF + Clock absence flag + 16 + 8 + + + RCIP + Regular conversion in progress + status + 14 + 1 + + + JCIP + Injected conversion in progress + status + 13 + 1 + + + AWDF + Analog watchdog + 4 + 1 + + + ROVRF + Regular conversion overrun + flag + 3 + 1 + + + JOVRF + Injected conversion overrun + flag + 2 + 1 + + + REOCF + End of regular conversion + flag + 1 + 1 + + + JEOCF + End of injected conversion + flag + 0 + 1 + + + + + DFSDM_FLT0ICR + DFSDM_FLT0ICR + interrupt flag clear register + 0x10C + 0x20 + read-write + 0x00000000 + + + CLRSCDF + Clear the short-circuit detector + flag + 24 + 8 + + + CLRCKABF + Clear the clock absence + flag + 16 + 8 + + + CLRROVRF + Clear the regular conversion overrun + flag + 3 + 1 + + + CLRJOVRF + Clear the injected conversion overrun + flag + 2 + 1 + + + + + DFSDM_FLT0JCHGR + DFSDM_FLT0JCHGR + injected channel group selection + register + 0x110 + 0x20 + read-write + 0x00000001 + + + JCHG + Injected channel group + selection + 0 + 8 + + + + + DFSDM_FLT0FCR + DFSDM_FLT0FCR + filter control register + 0x114 + 0x20 + read-write + 0x00000000 + + + FORD + Sinc filter order + 29 + 3 + + + FOSR + Sinc filter oversampling ratio + (decimation rate) + 16 + 10 + + + IOSR + Integrator oversampling ratio (averaging + length) + 0 + 8 + + + + + DFSDM_FLT0JDATAR + DFSDM_FLT0JDATAR + data register for injected + group + 0x118 + 0x20 + read-only + 0x00000000 + + + JDATA + Injected group conversion + data + 8 + 24 + + + JDATACH + Injected channel most recently + converted + 0 + 3 + + + + + DFSDM_FLT0RDATAR + DFSDM_FLT0RDATAR + data register for the regular + channel + 0x11C + 0x20 + read-only + 0x00000000 + + + RDATA + Regular channel conversion + data + 8 + 24 + + + RPEND + Regular channel pending + data + 4 + 1 + + + RDATACH + Regular channel most recently + converted + 0 + 3 + + + + + DFSDM_FLT0AWHTR + DFSDM_FLT0AWHTR + analog watchdog high threshold + register + 0x120 + 0x20 + read-write + 0x00000000 + + + AWHT + Analog watchdog high + threshold + 8 + 24 + + + BKAWH + Break signal assignment to analog + watchdog high threshold event + 0 + 4 + + + + + DFSDM_FLT0AWLTR + DFSDM_FLT0AWLTR + analog watchdog low threshold + register + 0x124 + 0x20 + read-write + 0x00000000 + + + AWLT + Analog watchdog low + threshold + 8 + 24 + + + BKAWL + Break signal assignment to analog + watchdog low threshold event + 0 + 4 + + + + + DFSDM_FLT0AWSR + DFSDM_FLT0AWSR + analog watchdog status + register + 0x128 + 0x20 + read-only + 0x00000000 + + + AWHTF + Analog watchdog high threshold + flag + 8 + 8 + + + AWLTF + Analog watchdog low threshold + flag + 0 + 8 + + + + + DFSDM_FLT0AWCFR + DFSDM_FLT0AWCFR + analog watchdog clear flag + register + 0x12C + 0x20 + read-write + 0x00000000 + + + CLRAWHTF + Clear the analog watchdog high threshold + flag + 8 + 8 + + + CLRAWLTF + Clear the analog watchdog low threshold + flag + 0 + 8 + + + + + DFSDM_FLT0EXMAX + DFSDM_FLT0EXMAX + Extremes detector maximum + register + 0x130 + 0x20 + read-only + 0x80000000 + + + EXMAX + Extremes detector maximum + value + 8 + 24 + + + EXMAXCH + Extremes detector maximum data + channel + 0 + 3 + + + + + DFSDM_FLT0EXMIN + DFSDM_FLT0EXMIN + Extremes detector minimum + register + 0x134 + 0x20 + read-only + 0x7FFFFF00 + + + EXMIN + EXMIN + 8 + 24 + + + EXMINCH + Extremes detector minimum data + channel + 0 + 3 + + + + + DFSDM_FLT0CNVTIMR + DFSDM_FLT0CNVTIMR + conversion timer register + 0x138 + 0x20 + read-only + 0x00000000 + + + CNVCNT + 28-bit timer counting conversion time t + = CNVCNT[27:0] / fDFSDM_CKIN + 4 + 28 + + + + + DFSDM_FLT1CR1 + DFSDM_FLT1CR1 + control register 1 + 0x180 + 0x20 + read-write + 0x00000000 + + + AWFSEL + Analog watchdog fast mode + select + 30 + 1 + + + FAST + Fast conversion mode selection for + regular conversions + 29 + 1 + + + RCH + Regular channel selection + 24 + 3 + + + RDMAEN + DMA channel enabled to read data for the + regular conversion + 21 + 1 + + + RSYNC + Launch regular conversion synchronously + with DFSDM0 + 19 + 1 + + + RCONT + Continuous mode selection for regular + conversions + 18 + 1 + + + RSWSTART + Software start of a conversion on the + regular channel + 17 + 1 + + + JEXTEN + Trigger enable and trigger edge + selection for injected conversions + 13 + 2 + + + JEXTSEL + Trigger signal selection for launching + injected conversions + 8 + 3 + + + JDMAEN + DMA channel enabled to read data for the + injected channel group + 5 + 1 + + + JSCAN + Scanning conversion mode for injected + conversions + 4 + 1 + + + JSYNC + Launch an injected conversion + synchronously with the DFSDM0 JSWSTART + trigger + 3 + 1 + + + JSWSTART + Start a conversion of the injected group + of channels + 1 + 1 + + + DFEN + DFSDM enable + 0 + 1 + + + + + DFSDM_FLT1CR2 + DFSDM_FLT1CR2 + control register 2 + 0x184 + 0x20 + read-write + 0x00000000 + + + AWDCH + Analog watchdog channel + selection + 16 + 8 + + + EXCH + Extremes detector channel + selection + 8 + 8 + + + CKABIE + Clock absence interrupt + enable + 6 + 1 + + + SCDIE + Short-circuit detector interrupt + enable + 5 + 1 + + + AWDIE + Analog watchdog interrupt + enable + 4 + 1 + + + ROVRIE + Regular data overrun interrupt + enable + 3 + 1 + + + JOVRIE + Injected data overrun interrupt + enable + 2 + 1 + + + REOCIE + Regular end of conversion interrupt + enable + 1 + 1 + + + JEOCIE + Injected end of conversion interrupt + enable + 0 + 1 + + + + + DFSDM_FLT1ISR + DFSDM_FLT1ISR + interrupt and status register + 0x188 + 0x20 + read-only + 0x00FF0000 + + + SCDF + short-circuit detector + flag + 24 + 8 + + + CKABF + Clock absence flag + 16 + 8 + + + RCIP + Regular conversion in progress + status + 14 + 1 + + + JCIP + Injected conversion in progress + status + 13 + 1 + + + AWDF + Analog watchdog + 4 + 1 + + + ROVRF + Regular conversion overrun + flag + 3 + 1 + + + JOVRF + Injected conversion overrun + flag + 2 + 1 + + + REOCF + End of regular conversion + flag + 1 + 1 + + + JEOCF + End of injected conversion + flag + 0 + 1 + + + + + DFSDM_FLT1ICR + DFSDM1_ICR + interrupt flag clear register + 0x18C + 0x20 + read-write + 0x00000000 + + + CLRSCDF + Clear the short-circuit detector + flag + 24 + 8 + + + CLRCKABF + Clear the clock absence + flag + 16 + 8 + + + CLRROVRF + Clear the regular conversion overrun + flag + 3 + 1 + + + CLRJOVRF + Clear the injected conversion overrun + flag + 2 + 1 + + + + + DFSDM_FLT1CHGR + DFSDM_FLT1JCHGR + injected channel group selection + register + 0x190 + 0x20 + read-write + 0x00000001 + + + JCHG + Injected channel group + selection + 0 + 8 + + + + + DFSDM_FLT1FCR + DFSDM1_FCR + filter control register + 0x194 + 0x20 + read-write + 0x00000000 + + + FORD + Sinc filter order + 29 + 3 + + + FOSR + Sinc filter oversampling ratio + (decimation rate) + 16 + 10 + + + IOSR + Integrator oversampling ratio (averaging + length) + 0 + 8 + + + + + DFSDM_FLT1JDATAR + DFSDM_FLT1JDATAR + data register for injected + group + 0x198 + 0x20 + read-only + 0x00000000 + + + JDATA + Injected group conversion + data + 8 + 24 + + + JDATACH + Injected channel most recently + converted + 0 + 3 + + + + + DFSDM_FLT1RDATAR + DFSDM_FLT1RDATAR + data register for the regular + channel + 0x19C + 0x20 + read-only + 0x00000000 + + + RDATA + Regular channel conversion + data + 8 + 24 + + + RPEND + Regular channel pending + data + 4 + 1 + + + RDATACH + Regular channel most recently + converted + 0 + 3 + + + + + DFSDM_FLT1AWHTR + DFSDM_FLT1AWHTR + analog watchdog high threshold + register + 0x1A0 + 0x20 + read-write + 0x00000000 + + + AWHT + Analog watchdog high + threshold + 8 + 24 + + + BKAWH + Break signal assignment to analog + watchdog high threshold event + 0 + 4 + + + + + DFSDM_FLT1AWLTR + DFSDM_FLT1AWLTR + analog watchdog low threshold + register + 0x1A4 + 0x20 + read-write + 0x00000000 + + + AWLT + Analog watchdog low + threshold + 8 + 24 + + + BKAWL + Break signal assignment to analog + watchdog low threshold event + 0 + 4 + + + + + DFSDM_FLT1AWSR + DFSDM_FLT1AWSR + analog watchdog status + register + 0x1A8 + 0x20 + read-only + 0x00000000 + + + AWHTF + Analog watchdog high threshold + flag + 8 + 8 + + + AWLTF + Analog watchdog low threshold + flag + 0 + 8 + + + + + DFSDM_FLT1AWCFR + DFSDM_FLT1AWCFR + analog watchdog clear flag + register + 0x1AC + 0x20 + read-write + 0x00000000 + + + CLRAWHTF + Clear the analog watchdog high threshold + flag + 8 + 8 + + + CLRAWLTF + Clear the analog watchdog low threshold + flag + 0 + 8 + + + + + DFSDM_FLT1EXMAX + DFSDM_FLT1EXMAX + Extremes detector maximum + register + 0x1B0 + 0x20 + read-only + 0x80000000 + + + EXMAX + Extremes detector maximum + value + 8 + 24 + + + EXMAXCH + Extremes detector maximum data + channel + 0 + 3 + + + + + DFSDM_FLT1EXMIN + DFSDM_FLT1EXMIN + Extremes detector minimum + register + 0x1B4 + 0x20 + read-only + 0x7FFFFF00 + + + EXMIN + EXMIN + 8 + 24 + + + EXMINCH + Extremes detector minimum data + channel + 0 + 3 + + + + + DFSDM_FLT1CNVTIMR + DFSDM_FLT1CNVTIMR + conversion timer register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + CNVCNT + 28-bit timer counting conversion time t + = CNVCNT[27:0] / fDFSDM_CKIN + 4 + 28 + + + + + DFSDM_FLT2CR1 + DFSDM_FLT2CR1 + control register 1 + 0x200 + 0x20 + read-write + 0x00000000 + + + AWFSEL + Analog watchdog fast mode + select + 30 + 1 + + + FAST + Fast conversion mode selection for + regular conversions + 29 + 1 + + + RCH + Regular channel selection + 24 + 3 + + + RDMAEN + DMA channel enabled to read data for the + regular conversion + 21 + 1 + + + RSYNC + Launch regular conversion synchronously + with DFSDM0 + 19 + 1 + + + RCONT + Continuous mode selection for regular + conversions + 18 + 1 + + + RSWSTART + Software start of a conversion on the + regular channel + 17 + 1 + + + JEXTEN + Trigger enable and trigger edge + selection for injected conversions + 13 + 2 + + + JEXTSEL + Trigger signal selection for launching + injected conversions + 8 + 3 + + + JDMAEN + DMA channel enabled to read data for the + injected channel group + 5 + 1 + + + JSCAN + Scanning conversion mode for injected + conversions + 4 + 1 + + + JSYNC + Launch an injected conversion + synchronously with the DFSDM0 JSWSTART + trigger + 3 + 1 + + + JSWSTART + Start a conversion of the injected group + of channels + 1 + 1 + + + DFEN + DFSDM enable + 0 + 1 + + + + + DFSDM_FLT2CR2 + DFSDM_FLT2CR2 + control register 2 + 0x204 + 0x20 + read-write + 0x00000000 + + + AWDCH + Analog watchdog channel + selection + 16 + 8 + + + EXCH + Extremes detector channel + selection + 8 + 8 + + + CKABIE + Clock absence interrupt + enable + 6 + 1 + + + SCDIE + Short-circuit detector interrupt + enable + 5 + 1 + + + AWDIE + Analog watchdog interrupt + enable + 4 + 1 + + + ROVRIE + Regular data overrun interrupt + enable + 3 + 1 + + + JOVRIE + Injected data overrun interrupt + enable + 2 + 1 + + + REOCIE + Regular end of conversion interrupt + enable + 1 + 1 + + + JEOCIE + Injected end of conversion interrupt + enable + 0 + 1 + + + + + DFSDM_FLT2ISR + DFSDM_FLT2ISR + interrupt and status register + 0x208 + 0x20 + read-only + 0x00FF0000 + + + SCDF + short-circuit detector + flag + 24 + 8 + + + CKABF + Clock absence flag + 16 + 8 + + + RCIP + Regular conversion in progress + status + 14 + 1 + + + JCIP + Injected conversion in progress + status + 13 + 1 + + + AWDF + Analog watchdog + 4 + 1 + + + ROVRF + Regular conversion overrun + flag + 3 + 1 + + + JOVRF + Injected conversion overrun + flag + 2 + 1 + + + REOCF + End of regular conversion + flag + 1 + 1 + + + JEOCF + End of injected conversion + flag + 0 + 1 + + + + + DFSDM_FLT2ICR + DFSDM_FLT2ICR + interrupt flag clear register + 0x20C + 0x20 + read-write + 0x00000000 + + + CLRSCDF + Clear the short-circuit detector + flag + 24 + 8 + + + CLRCKABF + Clear the clock absence + flag + 16 + 8 + + + CLRROVRF + Clear the regular conversion overrun + flag + 3 + 1 + + + CLRJOVRF + Clear the injected conversion overrun + flag + 2 + 1 + + + + + DFSDM_FLT2JCHGR + DFSDM_FLT2JCHGR + injected channel group selection + register + 0x210 + 0x20 + read-write + 0x00000001 + + + JCHG + Injected channel group + selection + 0 + 8 + + + + + DFSDM_FLT2FCR + DFSDM_FLT2FCR + filter control register + 0x214 + 0x20 + read-write + 0x00000000 + + + FORD + Sinc filter order + 29 + 3 + + + FOSR + Sinc filter oversampling ratio + (decimation rate) + 16 + 10 + + + IOSR + Integrator oversampling ratio (averaging + length) + 0 + 8 + + + + + DFSDM_FLT2JDATAR + DFSDM_FLT2JDATAR + data register for injected + group + 0x218 + 0x20 + read-only + 0x00000000 + + + JDATA + Injected group conversion + data + 8 + 24 + + + JDATACH + Injected channel most recently + converted + 0 + 3 + + + + + DFSDM_FLT2RDATAR + DFSDM_FLT2RDATAR + data register for the regular + channel + 0x21C + 0x20 + read-only + 0x00000000 + + + RDATA + Regular channel conversion + data + 8 + 24 + + + RPEND + Regular channel pending + data + 4 + 1 + + + RDATACH + Regular channel most recently + converted + 0 + 3 + + + + + DFSDM_FLT2AWHTR + DFSDM_FLT2AWHTR + analog watchdog high threshold + register + 0x220 + 0x20 + read-write + 0x00000000 + + + AWHT + Analog watchdog high + threshold + 8 + 24 + + + BKAWH + Break signal assignment to analog + watchdog high threshold event + 0 + 4 + + + + + DFSDM_FLT2AWLTR + DFSDM_FLT2AWLTR + analog watchdog low threshold + register + 0x224 + 0x20 + read-write + 0x00000000 + + + AWLT + Analog watchdog low + threshold + 8 + 24 + + + BKAWL + Break signal assignment to analog + watchdog low threshold event + 0 + 4 + + + + + DFSDM_FLT2AWSR + DFSDM_FLT2AWSR + analog watchdog status + register + 0x228 + 0x20 + read-only + 0x00000000 + + + AWHTF + Analog watchdog high threshold + flag + 8 + 8 + + + AWLTF + Analog watchdog low threshold + flag + 0 + 8 + + + + + DFSDM_FLT2AWCFR + DFSDM_FLT2AWCFR + analog watchdog clear flag + register + 0x22C + 0x20 + read-write + 0x00000000 + + + CLRAWHTF + Clear the analog watchdog high threshold + flag + 8 + 8 + + + CLRAWLTF + Clear the analog watchdog low threshold + flag + 0 + 8 + + + + + DFSDM_FLT2EXMAX + DFSDM_FLT2EXMAX + Extremes detector maximum + register + 0x230 + 0x20 + read-only + 0x80000000 + + + EXMAX + Extremes detector maximum + value + 8 + 24 + + + EXMAXCH + Extremes detector maximum data + channel + 0 + 3 + + + + + DFSDM_FLT2EXMIN + DFSDM_FLT2EXMIN + Extremes detector minimum + register + 0x234 + 0x20 + read-only + 0x7FFFFF00 + + + EXMIN + EXMIN + 8 + 24 + + + EXMINCH + Extremes detector minimum data + channel + 0 + 3 + + + + + DFSDM_FLT2CNVTIMR + DFSDM_FLT2CNVTIMR + conversion timer register + 0x238 + 0x20 + read-only + 0x00000000 + + + CNVCNT + 28-bit timer counting conversion time t + = CNVCNT[27:0] / fDFSDM_CKIN + 4 + 28 + + + + + DFSDM_FLT3CR1 + DFSDM_FLT3CR1 + control register 1 + 0x280 + 0x20 + read-write + 0x00000000 + + + AWFSEL + Analog watchdog fast mode + select + 30 + 1 + + + FAST + Fast conversion mode selection for + regular conversions + 29 + 1 + + + RCH + Regular channel selection + 24 + 3 + + + RDMAEN + DMA channel enabled to read data for the + regular conversion + 21 + 1 + + + RSYNC + Launch regular conversion synchronously + with DFSDM0 + 19 + 1 + + + RCONT + Continuous mode selection for regular + conversions + 18 + 1 + + + RSWSTART + Software start of a conversion on the + regular channel + 17 + 1 + + + JEXTEN + Trigger enable and trigger edge + selection for injected conversions + 13 + 2 + + + JEXTSEL + Trigger signal selection for launching + injected conversions + 8 + 3 + + + JDMAEN + DMA channel enabled to read data for the + injected channel group + 5 + 1 + + + JSCAN + Scanning conversion mode for injected + conversions + 4 + 1 + + + JSYNC + Launch an injected conversion + synchronously with the DFSDM0 JSWSTART + trigger + 3 + 1 + + + JSWSTART + Start a conversion of the injected group + of channels + 1 + 1 + + + DFEN + DFSDM enable + 0 + 1 + + + + + DFSDM_FLT3CR2 + DFSDM_FLT3CR2 + control register 2 + 0x284 + 0x20 + read-write + 0x00000000 + + + AWDCH + Analog watchdog channel + selection + 16 + 8 + + + EXCH + Extremes detector channel + selection + 8 + 8 + + + CKABIE + Clock absence interrupt + enable + 6 + 1 + + + SCDIE + Short-circuit detector interrupt + enable + 5 + 1 + + + AWDIE + Analog watchdog interrupt + enable + 4 + 1 + + + ROVRIE + Regular data overrun interrupt + enable + 3 + 1 + + + JOVRIE + Injected data overrun interrupt + enable + 2 + 1 + + + REOCIE + Regular end of conversion interrupt + enable + 1 + 1 + + + JEOCIE + Injected end of conversion interrupt + enable + 0 + 1 + + + + + DFSDM_FLT3ISR + DFSDM_FLT3ISR + interrupt and status register + 0x288 + 0x20 + read-only + 0x00FF0000 + + + SCDF + short-circuit detector + flag + 24 + 8 + + + CKABF + Clock absence flag + 16 + 8 + + + RCIP + Regular conversion in progress + status + 14 + 1 + + + JCIP + Injected conversion in progress + status + 13 + 1 + + + AWDF + Analog watchdog + 4 + 1 + + + ROVRF + Regular conversion overrun + flag + 3 + 1 + + + JOVRF + Injected conversion overrun + flag + 2 + 1 + + + REOCF + End of regular conversion + flag + 1 + 1 + + + JEOCF + End of injected conversion + flag + 0 + 1 + + + + + DFSDM_FLT3ICR + DFSDM_FLT3ICR + interrupt flag clear register + 0x28C + 0x20 + read-write + 0x00000000 + + + CLRSCDF + Clear the short-circuit detector + flag + 24 + 8 + + + CLRCKABF + Clear the clock absence + flag + 16 + 8 + + + CLRROVRF + Clear the regular conversion overrun + flag + 3 + 1 + + + CLRJOVRF + Clear the injected conversion overrun + flag + 2 + 1 + + + + + DFSDM_FLT3JCHGR + DFSDM_FLT3JCHGR + injected channel group selection + register + 0x290 + 0x20 + read-write + 0x00000001 + + + JCHG + Injected channel group + selection + 0 + 8 + + + + + DFSDM_FLT3FCR + DFSDM_FLT3FCR + filter control register + 0x294 + 0x20 + read-write + 0x00000000 + + + FORD + Sinc filter order + 29 + 3 + + + FOSR + Sinc filter oversampling ratio + (decimation rate) + 16 + 10 + + + IOSR + Integrator oversampling ratio (averaging + length) + 0 + 8 + + + + + DFSDM_FLT3JDATAR + DFSDM_FLT3JDATAR + data register for injected + group + 0x298 + 0x20 + read-only + 0x00000000 + + + JDATA + Injected group conversion + data + 8 + 24 + + + JDATACH + Injected channel most recently + converted + 0 + 3 + + + + + DFSDM_FLT3RDATAR + DFSDM_FLT3RDATAR + data register for the regular + channel + 0x29C + 0x20 + read-only + 0x00000000 + + + RDATA + Regular channel conversion + data + 8 + 24 + + + RPEND + Regular channel pending + data + 4 + 1 + + + RDATACH + Regular channel most recently + converted + 0 + 3 + + + + + DFSDM_FLT3AWHTR + DFSDM_FLT3AWHTR + analog watchdog high threshold + register + 0x2A0 + 0x20 + read-write + 0x00000000 + + + AWHT + Analog watchdog high + threshold + 8 + 24 + + + BKAWH + Break signal assignment to analog + watchdog high threshold event + 0 + 4 + + + + + DFSDM_FLT3AWLTR + DFSDM_FLT3AWLTR + analog watchdog low threshold + register + 0x2A4 + 0x20 + read-write + 0x00000000 + + + AWLT + Analog watchdog low + threshold + 8 + 24 + + + BKAWL + Break signal assignment to analog + watchdog low threshold event + 0 + 4 + + + + + DFSDM_FLT3AWSR + DFSDM_FLT3AWSR + analog watchdog status + register + 0x2A8 + 0x20 + read-only + 0x00000000 + + + AWHTF + Analog watchdog high threshold + flag + 8 + 8 + + + AWLTF + Analog watchdog low threshold + flag + 0 + 8 + + + + + DFSDM_FLT3AWCFR + DFSDM_FLT3AWCFR + analog watchdog clear flag + register + 0x2AC + 0x20 + read-write + 0x00000000 + + + CLRAWHTF + Clear the analog watchdog high threshold + flag + 8 + 8 + + + CLRAWLTF + Clear the analog watchdog low threshold + flag + 0 + 8 + + + + + DFSDM_FLT3EXMAX + DFSDM_FLT3EXMAX + Extremes detector maximum + register + 0x2B0 + 0x20 + read-only + 0x80000000 + + + EXMAX + Extremes detector maximum + value + 8 + 24 + + + EXMAXCH + Extremes detector maximum data + channel + 0 + 3 + + + + + DFSDM_FLT3EXMIN + DFSDM_FLT3EXMIN + Extremes detector minimum + register + 0x2B4 + 0x20 + read-only + 0x7FFFFF00 + + + EXMIN + EXMIN + 8 + 24 + + + EXMINCH + Extremes detector minimum data + channel + 0 + 3 + + + + + DFSDM_FLT3CNVTIMR + DFSDM_FLT3CNVTIMR + conversion timer register + 0x2B8 + 0x20 + read-only + 0x00000000 + + + CNVCNT + 28-bit timer counting conversion time t + = CNVCNT[27:0] / fDFSDM_CKIN + 4 + 28 + + + + + + + RNG + Random number generator + RNG + 0x50060800 + + 0x0 + 0x400 + registers + + + RNG + RNG and HASH global interrupt + 80 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + IE + Interrupt enable + 3 + 1 + + + RNGEN + Random number generator enable + 2 + 1 + + + + + SR + SR + status register + 0x4 + 0x20 + 0x00000000 + + + SEIS + Seed error interrupt status + 6 + 1 + read-write + + + CEIS + Clock error interrupt status + 5 + 1 + read-write + + + SECS + Seed error current status + 2 + 1 + read-only + + + CECS + Clock error current status + 1 + 1 + read-only + + + DRDY + Data ready + 0 + 1 + read-only + + + + + DR + DR + data register + 0x8 + 0x20 + read-only + 0x00000000 + + + RNDATA + Random data + 0 + 32 + + + + + + + AES + Advanced encryption standard hardware accelerator + AES + 0x50060000 + + 0x0 + 0x400 + registers + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + DMAOUTEN + Enable DMA management of data output phase + 12 + 1 + + + DMAINEN + Enable DMA management of data input phase + 11 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + CCFIE + CCF flag interrupt enable + 9 + 1 + + + ERRC + Error clear + 8 + 1 + + + CCFC + Computation Complete Flag Clear + 7 + 1 + + + CHMOD + AES chaining mode + 5 + 2 + + + MODE + AES operating mode + 3 + 2 + + + DATATYPE + Data type selection (for data in and data out to/from the cryptographic block) + 1 + 2 + + + EN + AES enable + 0 + 1 + + + + + SR + SR + status register + 0x4 + 0x20 + read-only + 0x00000000 + + + WRERR + Write error flag + 2 + 1 + + + RDERR + Read error flag + 1 + 1 + + + CCF + Computation complete flag + 0 + 1 + + + + + DINR + DINR + data input register + 0x8 + 0x20 + read-write + 0x00000000 + + + AES_DINR + Data Input Register + 0 + 32 + + + + + DOUTR + DOUTR + data output register + 0xC + 0x20 + read-only + 0x00000000 + + + AES_DOUTR + Data output register + 0 + 32 + + + + + KEYR0 + KEYR0 + key register 0 + 0x10 + 0x20 + read-write + 0x00000000 + + + AES_KEYR0 + Data Output Register (LSB key [31:0]) + 0 + 32 + + + + + KEYR1 + KEYR1 + key register 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + AES_KEYR1 + AES key register (key [63:32]) + 0 + 32 + + + + + KEYR2 + KEYR2 + key register 2 + 0x18 + 0x20 + read-write + 0x00000000 + + + AES_KEYR2 + AES key register (key [95:64]) + 0 + 32 + + + + + KEYR3 + KEYR3 + key register 3 + 0x1C + 0x20 + read-write + 0x00000000 + + + AES_KEYR3 + AES key register (MSB key [127:96]) + 0 + 32 + + + + + IVR0 + IVR0 + initialization vector register 0 + 0x20 + 0x20 + read-write + 0x00000000 + + + AES_IVR0 + initialization vector register (LSB IVR [31:0]) + 0 + 32 + + + + + IVR1 + IVR1 + initialization vector register 1 + 0x24 + 0x20 + read-write + 0x00000000 + + + AES_IVR1 + Initialization Vector Register (IVR [63:32]) + 0 + 32 + + + + + IVR2 + IVR2 + initialization vector register 2 + 0x28 + 0x20 + read-write + 0x00000000 + + + AES_IVR2 + Initialization Vector Register (IVR [95:64]) + 0 + 32 + + + + + IVR3 + IVR3 + initialization vector register 3 + 0x2C + 0x20 + read-write + 0x00000000 + + + AES_IVR3 + Initialization Vector Register (MSB IVR [127:96]) + 0 + 32 + + + + + + + ADC1 + Analog-to-Digital Converter + ADC + 0x50040000 + + 0x0 + 0xB9 + registers + + + + ISR + ISR + interrupt and status register + 0x0 + 0x20 + read-write + 0x00000000 + + + JQOVF + JQOVF + 10 + 1 + + + AWD3 + AWD3 + 9 + 1 + + + AWD2 + AWD2 + 8 + 1 + + + AWD1 + AWD1 + 7 + 1 + + + JEOS + JEOS + 6 + 1 + + + JEOC + JEOC + 5 + 1 + + + OVR + OVR + 4 + 1 + + + EOS + EOS + 3 + 1 + + + EOC + EOC + 2 + 1 + + + EOSMP + EOSMP + 1 + 1 + + + ADRDY + ADRDY + 0 + 1 + + + + + IER + IER + interrupt enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + JQOVFIE + JQOVFIE + 10 + 1 + + + AWD3IE + AWD3IE + 9 + 1 + + + AWD2IE + AWD2IE + 8 + 1 + + + AWD1IE + AWD1IE + 7 + 1 + + + JEOSIE + JEOSIE + 6 + 1 + + + JEOCIE + JEOCIE + 5 + 1 + + + OVRIE + OVRIE + 4 + 1 + + + EOSIE + EOSIE + 3 + 1 + + + EOCIE + EOCIE + 2 + 1 + + + EOSMPIE + EOSMPIE + 1 + 1 + + + ADRDYIE + ADRDYIE + 0 + 1 + + + + + CR + CR + control register + 0x8 + 0x20 + read-write + 0x00000000 + + + ADCAL + ADCAL + 31 + 1 + + + ADCALDIF + ADCALDIF + 30 + 1 + + + DEEPPWD + DEEPPWD + 29 + 1 + + + ADVREGEN + ADVREGEN + 28 + 1 + + + JADSTP + JADSTP + 5 + 1 + + + ADSTP + ADSTP + 4 + 1 + + + JADSTART + JADSTART + 3 + 1 + + + ADSTART + ADSTART + 2 + 1 + + + ADDIS + ADDIS + 1 + 1 + + + ADEN + ADEN + 0 + 1 + + + + + CFGR + CFGR + configuration register + 0xC + 0x20 + read-write + 0x00000000 + + + JQDIS + Injected Queue disable + 31 + 1 + + + AWDCH1CH + AWDCH1CH + 26 + 5 + + + JAUTO + JAUTO + 25 + 1 + + + JAWD1EN + JAWD1EN + 24 + 1 + + + AWD1EN + AWD1EN + 23 + 1 + + + AWD1SGL + AWD1SGL + 22 + 1 + + + JQM + JQM + 21 + 1 + + + JDISCEN + JDISCEN + 20 + 1 + + + DISCNUM + DISCNUM + 17 + 3 + + + DISCEN + DISCEN + 16 + 1 + + + AUTDLY + AUTDLY + 14 + 1 + + + CONT + CONT + 13 + 1 + + + OVRMOD + OVRMOD + 12 + 1 + + + EXTEN + EXTEN + 10 + 2 + + + EXTSEL + EXTSEL + 6 + 4 + + + ALIGN + ALIGN + 5 + 1 + + + RES + RES + 3 + 2 + + + DFSDMCFG + DFSDMCFG + 2 + 1 + + + DMACFG + DMACFG + 1 + 1 + + + DMAEN + DMAEN + 0 + 1 + + + + + CFGR2 + CFGR2 + configuration register + 0x10 + 0x20 + read-write + 0x00000000 + + + ROVSM + EXTEN + 10 + 1 + + + TROVS + Triggered Regular Oversampling + 9 + 1 + + + OVSS + ALIGN + 5 + 4 + + + OVSR + RES + 2 + 3 + + + JOVSE + DMACFG + 1 + 1 + + + ROVSE + DMAEN + 0 + 1 + + + + + SMPR1 + SMPR1 + sample time register 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + SMP9 + SMP9 + 27 + 3 + + + SMP8 + SMP8 + 24 + 3 + + + SMP7 + SMP7 + 21 + 3 + + + SMP6 + SMP6 + 18 + 3 + + + SMP5 + SMP5 + 15 + 3 + + + SMP4 + SMP4 + 12 + 3 + + + SMP3 + SMP3 + 9 + 3 + + + SMP2 + SMP2 + 6 + 3 + + + SMP1 + SMP1 + 3 + 3 + + + SMPPLUS + Addition of one clock cycle to the sampling time + 31 + 1 + + + SMP0 + SMP0 + 0 + 3 + + + + + SMPR2 + SMPR2 + sample time register 2 + 0x18 + 0x20 + read-write + 0x00000000 + + + SMP18 + SMP18 + 24 + 3 + + + SMP17 + SMP17 + 21 + 3 + + + SMP16 + SMP16 + 18 + 3 + + + SMP15 + SMP15 + 15 + 3 + + + SMP14 + SMP14 + 12 + 3 + + + SMP13 + SMP13 + 9 + 3 + + + SMP12 + SMP12 + 6 + 3 + + + SMP11 + SMP11 + 3 + 3 + + + SMP10 + SMP10 + 0 + 3 + + + + + TR1 + TR1 + watchdog threshold register 1 + 0x20 + 0x20 + read-write + 0x0FFF0000 + + + HT1 + HT1 + 16 + 12 + + + LT1 + LT1 + 0 + 12 + + + + + TR2 + TR2 + watchdog threshold register + 0x24 + 0x20 + read-write + 0x0FFF0000 + + + HT2 + HT2 + 16 + 8 + + + LT2 + LT2 + 0 + 8 + + + + + TR3 + TR3 + watchdog threshold register 3 + 0x28 + 0x20 + read-write + 0x0FFF0000 + + + HT3 + HT3 + 16 + 8 + + + LT3 + LT3 + 0 + 8 + + + + + SQR1 + SQR1 + regular sequence register 1 + 0x30 + 0x20 + read-write + 0x00000000 + + + SQ4 + SQ4 + 24 + 5 + + + SQ3 + SQ3 + 18 + 5 + + + SQ2 + SQ2 + 12 + 5 + + + SQ1 + SQ1 + 6 + 5 + + + L + Regular channel sequence length + 0 + 4 + + + + + SQR2 + SQR2 + regular sequence register 2 + 0x34 + 0x20 + read-write + 0x00000000 + + + SQ9 + SQ9 + 24 + 5 + + + SQ8 + SQ8 + 18 + 5 + + + SQ7 + SQ7 + 12 + 5 + + + SQ6 + SQ6 + 6 + 5 + + + SQ5 + SQ5 + 0 + 5 + + + + + SQR3 + SQR3 + regular sequence register 3 + 0x38 + 0x20 + read-write + 0x00000000 + + + SQ14 + SQ14 + 24 + 5 + + + SQ13 + SQ13 + 18 + 5 + + + SQ12 + SQ12 + 12 + 5 + + + SQ11 + SQ11 + 6 + 5 + + + SQ10 + SQ10 + 0 + 5 + + + + + SQR4 + SQR4 + regular sequence register 4 + 0x3C + 0x20 + read-write + 0x00000000 + + + SQ16 + SQ16 + 6 + 5 + + + SQ15 + SQ15 + 0 + 5 + + + + + DR + DR + regular Data Register + 0x40 + 0x20 + read-only + 0x00000000 + + + RDATA + Regular Data converted + 0 + 16 + + + + + JSQR + JSQR + injected sequence register + 0x4C + 0x20 + read-write + 0x00000000 + + + JSQ4 + JSQ4 + 26 + 5 + + + JSQ3 + JSQ3 + 20 + 5 + + + JSQ2 + JSQ2 + 14 + 5 + + + JSQ1 + JSQ1 + 8 + 5 + + + JEXTEN + JEXTEN + 6 + 2 + + + JEXTSEL + JEXTSEL + 2 + 4 + + + JL + JL + 0 + 2 + + + + + OFR1 + OFR1 + offset register 1 + 0x60 + 0x20 + read-write + 0x00000000 + + + OFFSET1_EN + OFFSET1_EN + 31 + 1 + + + OFFSET1_CH + OFFSET1_CH + 26 + 5 + + + OFFSET1 + OFFSET1 + 0 + 12 + + + + + OFR2 + OFR2 + offset register 2 + 0x64 + 0x20 + read-write + 0x00000000 + + + OFFSET2_EN + OFFSET2_EN + 31 + 1 + + + OFFSET2_CH + OFFSET2_CH + 26 + 5 + + + OFFSET2 + OFFSET2 + 0 + 12 + + + + + OFR3 + OFR3 + offset register 3 + 0x68 + 0x20 + read-write + 0x00000000 + + + OFFSET3_EN + OFFSET3_EN + 31 + 1 + + + OFFSET3_CH + OFFSET3_CH + 26 + 5 + + + OFFSET3 + OFFSET3 + 0 + 12 + + + + + OFR4 + OFR4 + offset register 4 + 0x6C + 0x20 + read-write + 0x00000000 + + + OFFSET4_EN + OFFSET4_EN + 31 + 1 + + + OFFSET4_CH + OFFSET4_CH + 26 + 5 + + + OFFSET4 + OFFSET4 + 0 + 12 + + + + + JDR1 + JDR1 + injected data register 1 + 0x80 + 0x20 + read-only + 0x00000000 + + + JDATA1 + JDATA1 + 0 + 16 + + + + + JDR2 + JDR2 + injected data register 2 + 0x84 + 0x20 + read-only + 0x00000000 + + + JDATA2 + JDATA2 + 0 + 16 + + + + + JDR3 + JDR3 + injected data register 3 + 0x88 + 0x20 + read-only + 0x00000000 + + + JDATA3 + JDATA3 + 0 + 16 + + + + + JDR4 + JDR4 + injected data register 4 + 0x8C + 0x20 + read-only + 0x00000000 + + + JDATA4 + JDATA4 + 0 + 16 + + + + + AWD2CR + AWD2CR + Analog Watchdog 2 Configuration Register + 0xA0 + 0x20 + read-write + 0x00000000 + + + AWD2CH + AWD2CH + 0 + 19 + + + + + AWD3CR + AWD3CR + Analog Watchdog 3 Configuration Register + 0xA4 + 0x20 + read-write + 0x00000000 + + + AWD3CH + AWD3CH + 0 + 19 + + + + + DIFSEL + DIFSEL + Differential Mode Selection Register 2 + 0xB0 + 0x20 + 0x00000000 + + + DIFSEL_0 + Differential mode for channels 0 + 0 + 1 + read-only + + + DIFSEL_1_15 + Differential mode for channels 15 to 1 + 1 + 15 + read-write + + + DIFSEL_16_18 + Differential mode for channels 18 to 16 + 16 + 3 + read-only + + + + + CALFACT + CALFACT + Calibration Factors + 0xB4 + 0x20 + read-write + 0x00000000 + + + CALFACT_D + CALFACT_D + 16 + 7 + + + CALFACT_S + CALFACT_S + 0 + 7 + + + + + + + ADC2 + 0x50040100 + + + ADC3 + 0x50040200 + + ADC3 + ADC3 global interrupt + 47 + + + + ADC_Common + Analog-to-Digital Converter + ADC + 0x50040300 + + 0x0 + 0x11 + registers + + + ADC1_2 + ADC1 and ADC2 global interrupt + 18 + + + + CSR + CSR + ADC Common status register + 0x0 + 0x20 + read-only + 0x00000000 + + + ADDRDY_MST + ADDRDY_MST + 0 + 1 + + + EOSMP_MST + EOSMP_MST + 1 + 1 + + + EOC_MST + EOC_MST + 2 + 1 + + + EOS_MST + EOS_MST + 3 + 1 + + + OVR_MST + OVR_MST + 4 + 1 + + + JEOC_MST + JEOC_MST + 5 + 1 + + + JEOS_MST + JEOS_MST + 6 + 1 + + + AWD1_MST + AWD1_MST + 7 + 1 + + + AWD2_MST + AWD2_MST + 8 + 1 + + + AWD3_MST + AWD3_MST + 9 + 1 + + + JQOVF_MST + JQOVF_MST + 10 + 1 + + + ADRDY_SLV + ADRDY_SLV + 16 + 1 + + + EOSMP_SLV + EOSMP_SLV + 17 + 1 + + + EOC_SLV + End of regular conversion of the slave ADC + 18 + 1 + + + EOS_SLV + End of regular sequence flag of the slave ADC + 19 + 1 + + + OVR_SLV + Overrun flag of the slave ADC + 20 + 1 + + + JEOC_SLV + End of injected conversion flag of the slave ADC + 21 + 1 + + + JEOS_SLV + End of injected sequence flag of the slave ADC + 22 + 1 + + + AWD1_SLV + Analog watchdog 1 flag of the slave ADC + 23 + 1 + + + AWD2_SLV + Analog watchdog 2 flag of the slave ADC + 24 + 1 + + + AWD3_SLV + Analog watchdog 3 flag of the slave ADC + 25 + 1 + + + JQOVF_SLV + Injected Context Queue Overflow flag of the slave ADC + 26 + 1 + + + + + CCR + CCR + ADC common control register + 0x8 + 0x20 + read-write + 0x00000000 + + + DUAL + Dual ADC mode selection + 0 + 5 + + + DELAY + Delay between 2 sampling phases + 8 + 4 + + + DMACFG + DMA configuration (for multi-ADC mode) + 13 + 1 + + + MDMA + Direct memory access mode for multi ADC mode + 14 + 2 + + + CKMODE + ADC clock mode + 16 + 2 + + + VREFEN + VREFINT enable + 22 + 1 + + + CH17SEL + CH17 selection + 23 + 1 + + + CH18SEL + CH18 selection + 24 + 1 + + + PRESC + ADC prescaler + 18 + 4 + + + + + CDR + CDR + ADC common regular data register for dual and triple modes + 0xC + 0x20 + read-only + 0x00000000 + + + RDATA_SLV + Regular data of the slave ADC + 16 + 16 + + + RDATA_MST + Regular data of the master ADC + 0 + 16 + + + + + + + GPIOA + General-purpose I/Os + GPIO + 0x48000000 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xA8000000 + + + MODER15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + MODER14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + MODER13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + MODER12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + MODER11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + MODER10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + MODER9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + MODER8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + MODER7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + MODER6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + MODER5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + MODER4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + MODER3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + MODER2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + MODER1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + MODER0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT15 + Port x configuration bits (y = 0..15) + 15 + 1 + + + OT14 + Port x configuration bits (y = 0..15) + 14 + 1 + + + OT13 + Port x configuration bits (y = 0..15) + 13 + 1 + + + OT12 + Port x configuration bits (y = 0..15) + 12 + 1 + + + OT11 + Port x configuration bits (y = 0..15) + 11 + 1 + + + OT10 + Port x configuration bits (y = 0..15) + 10 + 1 + + + OT9 + Port x configuration bits (y = 0..15) + 9 + 1 + + + OT8 + Port x configuration bits (y = 0..15) + 8 + 1 + + + OT7 + Port x configuration bits (y = 0..15) + 7 + 1 + + + OT6 + Port x configuration bits (y = 0..15) + 6 + 1 + + + OT5 + Port x configuration bits (y = 0..15) + 5 + 1 + + + OT4 + Port x configuration bits (y = 0..15) + 4 + 1 + + + OT3 + Port x configuration bits (y = 0..15) + 3 + 1 + + + OT2 + Port x configuration bits (y = 0..15) + 2 + 1 + + + OT1 + Port x configuration bits (y = 0..15) + 1 + 1 + + + OT0 + Port x configuration bits (y = 0..15) + 0 + 1 + + + + + OSPEEDR + OSPEEDR + GPIO port output speed register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEEDR15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + OSPEEDR14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + OSPEEDR13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + OSPEEDR12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + OSPEEDR11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + OSPEEDR10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + OSPEEDR9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + OSPEEDR8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + OSPEEDR7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + OSPEEDR6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + OSPEEDR5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + OSPEEDR4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + OSPEEDR3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + OSPEEDR2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + OSPEEDR1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + OSPEEDR0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down register + 0xC + 0x20 + read-write + 0x64000000 + + + PUPDR15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + PUPDR14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + PUPDR13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + PUPDR12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + PUPDR11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + PUPDR10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + PUPDR9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + PUPDR8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + PUPDR7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + PUPDR6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + PUPDR5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + PUPDR4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + PUPDR3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + PUPDR2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + PUPDR1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + PUPDR0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR15 + Port input data (y = 0..15) + 15 + 1 + + + IDR14 + Port input data (y = 0..15) + 14 + 1 + + + IDR13 + Port input data (y = 0..15) + 13 + 1 + + + IDR12 + Port input data (y = 0..15) + 12 + 1 + + + IDR11 + Port input data (y = 0..15) + 11 + 1 + + + IDR10 + Port input data (y = 0..15) + 10 + 1 + + + IDR9 + Port input data (y = 0..15) + 9 + 1 + + + IDR8 + Port input data (y = 0..15) + 8 + 1 + + + IDR7 + Port input data (y = 0..15) + 7 + 1 + + + IDR6 + Port input data (y = 0..15) + 6 + 1 + + + IDR5 + Port input data (y = 0..15) + 5 + 1 + + + IDR4 + Port input data (y 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x lock bit y (y= 0..15) + 15 + 1 + + + LCK14 + Port x lock bit y (y= 0..15) + 14 + 1 + + + LCK13 + Port x lock bit y (y= 0..15) + 13 + 1 + + + LCK12 + Port x lock bit y (y= 0..15) + 12 + 1 + + + LCK11 + Port x lock bit y (y= 0..15) + 11 + 1 + + + LCK10 + Port x lock bit y (y= 0..15) + 10 + 1 + + + LCK9 + Port x lock bit y (y= 0..15) + 9 + 1 + + + LCK8 + Port x lock bit y (y= 0..15) + 8 + 1 + + + LCK7 + Port x lock bit y (y= 0..15) + 7 + 1 + + + LCK6 + Port x lock bit y (y= 0..15) + 6 + 1 + + + LCK5 + Port x lock bit y (y= 0..15) + 5 + 1 + + + LCK4 + Port x lock bit y (y= 0..15) + 4 + 1 + + + LCK3 + Port x lock bit y (y= 0..15) + 3 + 1 + + + LCK2 + Port x lock bit y (y= 0..15) + 2 + 1 + + + LCK1 + Port x lock bit y (y= 0..15) + 1 + 1 + + + LCK0 + Port x lock bit y (y= 0..15) + 0 + 1 + + + + + AFRL + AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFRL7 + Alternate function selection for port x bit y (y = 0..7) + 28 + 4 + + + AFRL6 + Alternate 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selection for port x bit y (y = 8..15) + 12 + 4 + + + AFRH10 + Alternate function selection for port x bit y (y = 8..15) + 8 + 4 + + + AFRH9 + Alternate function selection for port x bit y (y = 8..15) + 4 + 4 + + + AFRH8 + Alternate function selection for port x bit y (y = 8..15) + 0 + 4 + + + + + BRR + BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + Port Reset bit + 0 + 1 + + + BR1 + Port Reset bit + 1 + 1 + + + BR2 + Port Reset bit + 2 + 1 + + + BR3 + Port Reset bit + 3 + 1 + + + BR4 + Port Reset bit + 4 + 1 + + + BR5 + Port Reset bit + 5 + 1 + + + BR6 + Port Reset bit + 6 + 1 + + + BR7 + Port Reset bit + 7 + 1 + + + BR8 + Port Reset bit + 8 + 1 + + + BR9 + Port Reset bit + 9 + 1 + + + BR10 + Port Reset bit + 10 + 1 + + + BR11 + Port Reset bit + 11 + 1 + + + BR12 + Port Reset bit + 12 + 1 + + + BR13 + Port Reset bit + 13 + 1 + + + BR14 + Port Reset bit + 14 + 1 + + + BR15 + Port Reset bit + 15 + 1 + + + + + ASCR + ASCR + GPIO port analog switch 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configuration bits (y = 0..15) + 8 + 2 + + + PUPDR3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + PUPDR2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + PUPDR1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + PUPDR0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR15 + Port input data (y = 0..15) + 15 + 1 + + + IDR14 + Port input data (y = 0..15) + 14 + 1 + + + IDR13 + Port input data (y = 0..15) + 13 + 1 + + + IDR12 + Port input data (y = 0..15) + 12 + 1 + + + IDR11 + Port input data (y = 0..15) + 11 + 1 + + + IDR10 + Port input data (y = 0..15) + 10 + 1 + + + IDR9 + Port input data (y = 0..15) + 9 + 1 + + + IDR8 + Port input data (y = 0..15) + 8 + 1 + + + IDR7 + Port input data (y = 0..15) + 7 + 1 + + + IDR6 + Port input data (y = 0..15) + 6 + 1 + + + IDR5 + Port input data (y = 0..15) + 5 + 1 + + + IDR4 + Port input data (y = 0..15) + 4 + 1 + + + IDR3 + Port input data (y = 0..15) + 3 + 1 + + + IDR2 + Port input data (y = 0..15) + 2 + 1 + + + IDR1 + Port input data (y = 0..15) + 1 + 1 + + + IDR0 + Port input data (y = 0..15) + 0 + 1 + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR15 + Port output data (y = 0..15) + 15 + 1 + + + ODR14 + Port output data (y = 0..15) + 14 + 1 + + + ODR13 + Port output data (y = 0..15) + 13 + 1 + + + ODR12 + Port output data (y = 0..15) + 12 + 1 + + + ODR11 + Port output data (y = 0..15) + 11 + 1 + + + ODR10 + Port output data (y = 0..15) + 10 + 1 + + + ODR9 + Port output data (y = 0..15) + 9 + 1 + + + ODR8 + Port output data (y = 0..15) + 8 + 1 + + + ODR7 + Port output data (y = 0..15) + 7 + 1 + + + ODR6 + Port output data (y = 0..15) + 6 + 1 + + + ODR5 + Port output data (y = 0..15) + 5 + 1 + + + ODR4 + Port output data (y = 0..15) + 4 + 1 + + + ODR3 + Port output data (y = 0..15) + 3 + 1 + + + ODR2 + Port output data (y = 0..15) + 2 + 1 + + + ODR1 + Port output data (y = 0..15) + 1 + 1 + + + ODR0 + Port output data (y = 0..15) + 0 + 1 + + + + + BSRR + BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + + + BR15 + Port x reset bit y (y = 0..15) + 31 + 1 + + + BR14 + Port x reset bit y (y = 0..15) + 30 + 1 + + + BR13 + Port x reset bit y (y = 0..15) + 29 + 1 + + + BR12 + Port x reset bit y (y = 0..15) + 28 + 1 + + + BR11 + Port x reset bit y (y = 0..15) + 27 + 1 + + + BR10 + Port x reset bit y (y = 0..15) + 26 + 1 + + + BR9 + Port x reset bit y (y = 0..15) + 25 + 1 + + + BR8 + Port x reset bit y (y = 0..15) + 24 + 1 + + + BR7 + Port x reset bit y (y = 0..15) + 23 + 1 + + + BR6 + Port x reset bit y (y = 0..15) + 22 + 1 + + + BR5 + Port x reset bit y (y = 0..15) + 21 + 1 + + + BR4 + Port x reset bit y (y = 0..15) + 20 + 1 + + + BR3 + Port x reset bit y (y = 0..15) + 19 + 1 + + + BR2 + Port x reset bit y (y = 0..15) + 18 + 1 + + + BR1 + Port x reset bit y (y = 0..15) + 17 + 1 + + + BR0 + Port x set bit y (y= 0..15) + 16 + 1 + + + BS15 + Port x set bit y (y= 0..15) + 15 + 1 + + + BS14 + Port x set bit y (y= 0..15) + 14 + 1 + + + BS13 + Port x set bit y (y= 0..15) + 13 + 1 + + + BS12 + Port x set bit y (y= 0..15) + 12 + 1 + + + BS11 + Port x set bit y (y= 0..15) + 11 + 1 + + + BS10 + Port x set bit y (y= 0..15) + 10 + 1 + + + BS9 + Port x set bit y (y= 0..15) + 9 + 1 + + + BS8 + Port x set bit y (y= 0..15) + 8 + 1 + + + BS7 + Port x set bit y (y= 0..15) + 7 + 1 + + + BS6 + Port x set bit y (y= 0..15) + 6 + 1 + + + BS5 + Port x set bit y (y= 0..15) + 5 + 1 + + + BS4 + Port x set bit y (y= 0..15) + 4 + 1 + + + BS3 + Port x set bit y (y= 0..15) + 3 + 1 + + + BS2 + Port x set bit y (y= 0..15) + 2 + 1 + + + BS1 + Port x set bit y (y= 0..15) + 1 + 1 + + + BS0 + Port x set bit y (y= 0..15) + 0 + 1 + + + + + LCKR + LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y (y= 0..15) + 16 + 1 + + + LCK15 + Port x lock bit y (y= 0..15) + 15 + 1 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(y = 0..7) + 24 + 4 + + + AFRL5 + Alternate function selection for port x bit y (y = 0..7) + 20 + 4 + + + AFRL4 + Alternate function selection for port x bit y (y = 0..7) + 16 + 4 + + + AFRL3 + Alternate function selection for port x bit y (y = 0..7) + 12 + 4 + + + AFRL2 + Alternate function selection for port x bit y (y = 0..7) + 8 + 4 + + + AFRL1 + Alternate function selection for port x bit y (y = 0..7) + 4 + 4 + + + AFRL0 + Alternate function selection for port x bit y (y = 0..7) + 0 + 4 + + + + + AFRH + AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFRH15 + Alternate function selection for port x bit y (y = 8..15) + 28 + 4 + + + AFRH14 + Alternate function selection for port x bit y (y = 8..15) + 24 + 4 + + + AFRH13 + Alternate function selection for port x bit y (y = 8..15) + 20 + 4 + + + AFRH12 + Alternate function selection for port x bit y (y = 8..15) + 16 + 4 + + + AFRH11 + Alternate function selection for port x bit y (y = 8..15) + 12 + 4 + + + AFRH10 + Alternate function selection for port x bit y (y = 8..15) + 8 + 4 + + + AFRH9 + Alternate function selection for port x bit y (y = 8..15) + 4 + 4 + + + AFRH8 + Alternate function selection for port x bit y (y = 8..15) + 0 + 4 + + + + + BRR + BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + Port Reset bit + 0 + 1 + + + BR1 + Port Reset bit + 1 + 1 + + + BR2 + Port Reset bit + 2 + 1 + + + BR3 + Port Reset bit + 3 + 1 + + + BR4 + Port Reset bit + 4 + 1 + + + BR5 + Port Reset bit + 5 + 1 + + + BR6 + Port Reset bit + 6 + 1 + + + BR7 + Port Reset bit + 7 + 1 + + + BR8 + Port Reset bit + 8 + 1 + + + BR9 + Port Reset bit + 9 + 1 + + + BR10 + Port Reset bit + 10 + 1 + + + BR11 + Port Reset bit + 11 + 1 + + + BR12 + Port Reset bit + 12 + 1 + + + BR13 + Port Reset bit + 13 + 1 + + + BR14 + Port Reset bit + 14 + 1 + + + BR15 + Port Reset bit + 15 + 1 + + + + + ASCR + ASCR + GPIO port analog switch control register + 0x2C + 0x20 + read-write + 0x00000000 + + + ASC0 + Port analog switch control + 0 + 1 + + + ASC1 + Port analog switch control + 1 + 1 + + + ASC2 + Port analog switch control + 2 + 1 + + + ASC3 + Port analog switch control + 3 + 1 + + + ASC4 + Port analog switch control + 4 + 1 + + + ASC5 + Port analog switch control + 5 + 1 + + + ASC6 + Port analog switch control + 6 + 1 + + + ASC7 + Port analog switch control + 7 + 1 + + + ASC8 + Port analog switch control + 8 + 1 + + + ASC9 + Port analog switch control + 9 + 1 + + + ASC10 + Port analog switch control + 10 + 1 + + + ASC11 + Port analog switch control + 11 + 1 + + + ASC12 + Port analog switch control + 12 + 1 + + + ASC13 + Port analog switch control + 13 + 1 + + + ASC14 + Port analog switch control + 14 + 1 + + + ASC15 + Port analog switch control + 15 + 1 + + + + + + + GPIOC + General-purpose I/Os + GPIO + 0x48000800 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0x00000000 + + + MODER15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + MODER14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + MODER13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + MODER12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + MODER11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + MODER10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + MODER9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + MODER8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + MODER7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + MODER6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + MODER5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + MODER4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + MODER3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + MODER2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + MODER1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + MODER0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT15 + Port x configuration bits (y = 0..15) + 15 + 1 + + + OT14 + Port x configuration bits (y = 0..15) + 14 + 1 + + + OT13 + Port x configuration bits (y = 0..15) + 13 + 1 + + + OT12 + Port x configuration bits (y = 0..15) + 12 + 1 + + + OT11 + Port x configuration bits (y = 0..15) + 11 + 1 + + + OT10 + Port x configuration bits (y = 0..15) + 10 + 1 + + + OT9 + Port x configuration bits (y = 0..15) + 9 + 1 + + + OT8 + Port x configuration bits (y = 0..15) + 8 + 1 + + + OT7 + Port x configuration bits (y = 0..15) + 7 + 1 + + + OT6 + Port x configuration bits (y = 0..15) + 6 + 1 + + + OT5 + Port x configuration bits (y = 0..15) + 5 + 1 + + + OT4 + Port x configuration bits (y = 0..15) + 4 + 1 + + + OT3 + Port x configuration bits (y = 0..15) + 3 + 1 + + + OT2 + Port x configuration bits (y = 0..15) + 2 + 1 + + + OT1 + Port x configuration bits (y = 0..15) + 1 + 1 + + + OT0 + Port x configuration bits (y = 0..15) + 0 + 1 + + + + + OSPEEDR + OSPEEDR + GPIO port output speed register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEEDR15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + OSPEEDR14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + OSPEEDR13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + OSPEEDR12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + OSPEEDR11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + OSPEEDR10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + OSPEEDR9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + OSPEEDR8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + OSPEEDR7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + OSPEEDR6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + OSPEEDR5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + OSPEEDR4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + OSPEEDR3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + OSPEEDR2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + OSPEEDR1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + OSPEEDR0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000000 + + + PUPDR15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + PUPDR14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + PUPDR13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + PUPDR12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + PUPDR11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + PUPDR10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + PUPDR9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + PUPDR8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + PUPDR7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + PUPDR6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + PUPDR5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + PUPDR4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + PUPDR3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + PUPDR2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + PUPDR1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + PUPDR0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR15 + Port input data (y = 0..15) + 15 + 1 + + + IDR14 + Port input data (y = 0..15) + 14 + 1 + + + IDR13 + Port input data (y = 0..15) + 13 + 1 + + + IDR12 + Port input data (y = 0..15) + 12 + 1 + + + IDR11 + Port input data (y = 0..15) + 11 + 1 + + + IDR10 + Port input data (y = 0..15) + 10 + 1 + + + IDR9 + Port input data (y = 0..15) + 9 + 1 + + + IDR8 + Port input data (y = 0..15) + 8 + 1 + + + IDR7 + Port input data (y = 0..15) + 7 + 1 + + + IDR6 + Port input data (y = 0..15) + 6 + 1 + + + IDR5 + Port input data (y = 0..15) + 5 + 1 + + + IDR4 + Port input data (y = 0..15) + 4 + 1 + + + IDR3 + Port input data (y = 0..15) + 3 + 1 + + + IDR2 + Port input data (y = 0..15) + 2 + 1 + + + IDR1 + Port input data (y = 0..15) + 1 + 1 + + + IDR0 + Port input data (y = 0..15) + 0 + 1 + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR15 + Port output data (y = 0..15) + 15 + 1 + + + ODR14 + Port output data (y = 0..15) + 14 + 1 + + + ODR13 + Port output data (y = 0..15) + 13 + 1 + + + ODR12 + Port output data (y = 0..15) + 12 + 1 + + + ODR11 + Port output data (y = 0..15) + 11 + 1 + + + ODR10 + Port output data (y = 0..15) + 10 + 1 + + + ODR9 + Port output data (y = 0..15) + 9 + 1 + + + ODR8 + Port output data (y = 0..15) + 8 + 1 + + + ODR7 + Port output data (y = 0..15) + 7 + 1 + + + ODR6 + Port output data (y = 0..15) + 6 + 1 + + + ODR5 + Port output data (y = 0..15) + 5 + 1 + + + ODR4 + Port output data (y = 0..15) + 4 + 1 + + + ODR3 + Port output data (y = 0..15) + 3 + 1 + + + ODR2 + Port output data (y = 0..15) + 2 + 1 + + + ODR1 + Port output data (y = 0..15) + 1 + 1 + + + ODR0 + Port output data (y = 0..15) + 0 + 1 + + + + + BSRR + BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + + + BR15 + Port x reset bit y (y = 0..15) + 31 + 1 + + + BR14 + Port x reset bit y (y = 0..15) + 30 + 1 + + + BR13 + Port x reset bit y (y = 0..15) + 29 + 1 + + + BR12 + Port x reset bit y (y = 0..15) + 28 + 1 + + + BR11 + Port x reset bit y (y = 0..15) + 27 + 1 + + + BR10 + Port x reset bit y (y = 0..15) + 26 + 1 + + + BR9 + Port x reset bit y (y = 0..15) + 25 + 1 + + + BR8 + Port x reset bit y (y = 0..15) + 24 + 1 + + + BR7 + Port x reset bit y (y = 0..15) + 23 + 1 + + + BR6 + Port x reset bit y (y = 0..15) + 22 + 1 + + + BR5 + Port x reset bit y (y = 0..15) + 21 + 1 + + + BR4 + Port x reset bit y (y = 0..15) + 20 + 1 + + + BR3 + Port x reset bit y (y = 0..15) + 19 + 1 + + + BR2 + Port x reset bit y (y = 0..15) + 18 + 1 + + + BR1 + Port x reset bit y (y = 0..15) + 17 + 1 + + + BR0 + Port x set bit y (y= 0..15) + 16 + 1 + + + BS15 + Port x set bit y (y= 0..15) + 15 + 1 + + + BS14 + Port x set bit y (y= 0..15) + 14 + 1 + + + BS13 + Port x set bit y (y= 0..15) + 13 + 1 + + + BS12 + Port x set bit y (y= 0..15) + 12 + 1 + + + BS11 + Port x set bit y (y= 0..15) + 11 + 1 + + + BS10 + Port x set bit y (y= 0..15) + 10 + 1 + + + BS9 + Port x set bit y (y= 0..15) + 9 + 1 + + + BS8 + Port x set bit y (y= 0..15) + 8 + 1 + + + BS7 + Port x set bit y (y= 0..15) + 7 + 1 + + + BS6 + Port x set bit y (y= 0..15) + 6 + 1 + + + BS5 + Port x set bit y (y= 0..15) + 5 + 1 + + + BS4 + Port x set bit y (y= 0..15) + 4 + 1 + + + BS3 + Port x set bit y (y= 0..15) + 3 + 1 + + + BS2 + Port x set bit y (y= 0..15) + 2 + 1 + + + BS1 + Port x set bit y (y= 0..15) + 1 + 1 + + + BS0 + Port x set bit y (y= 0..15) + 0 + 1 + + + + + LCKR + LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y (y= 0..15) + 16 + 1 + + + LCK15 + Port x lock bit y (y= 0..15) + 15 + 1 + + + LCK14 + Port x lock bit y (y= 0..15) + 14 + 1 + + + LCK13 + Port x lock bit y (y= 0..15) + 13 + 1 + + + LCK12 + Port x lock bit y (y= 0..15) + 12 + 1 + + + LCK11 + Port x lock bit y (y= 0..15) + 11 + 1 + + + LCK10 + Port x lock bit y (y= 0..15) + 10 + 1 + + + LCK9 + Port x lock bit y (y= 0..15) + 9 + 1 + + + LCK8 + Port x lock bit y (y= 0..15) + 8 + 1 + + + LCK7 + Port x lock bit y (y= 0..15) + 7 + 1 + + + LCK6 + Port x lock bit y (y= 0..15) + 6 + 1 + + + LCK5 + Port x lock bit y (y= 0..15) + 5 + 1 + + + LCK4 + Port x lock bit y (y= 0..15) + 4 + 1 + + + LCK3 + Port x lock bit y (y= 0..15) + 3 + 1 + + + LCK2 + Port x lock bit y (y= 0..15) + 2 + 1 + + + LCK1 + Port x lock bit y (y= 0..15) + 1 + 1 + + + LCK0 + Port x lock bit y (y= 0..15) + 0 + 1 + + + + + AFRL + AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFRL7 + Alternate function selection for port x bit y (y = 0..7) + 28 + 4 + + + AFRL6 + Alternate function selection for port x bit y (y = 0..7) + 24 + 4 + + + AFRL5 + Alternate function selection for port x bit y (y = 0..7) + 20 + 4 + + + AFRL4 + Alternate function selection for port x bit y (y = 0..7) + 16 + 4 + + + AFRL3 + Alternate function selection for port x bit y (y = 0..7) + 12 + 4 + + + AFRL2 + Alternate function selection for port x bit y (y = 0..7) + 8 + 4 + + + AFRL1 + Alternate function selection for port x bit y (y = 0..7) + 4 + 4 + + + AFRL0 + Alternate function selection for port x bit y (y = 0..7) + 0 + 4 + + + + + AFRH + AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFRH15 + Alternate function selection for port x bit y (y = 8..15) + 28 + 4 + + + AFRH14 + Alternate function selection for port x bit y (y = 8..15) + 24 + 4 + + + AFRH13 + Alternate function selection for port x bit y (y = 8..15) + 20 + 4 + + + AFRH12 + Alternate function selection for port x bit y (y = 8..15) + 16 + 4 + + + AFRH11 + Alternate function selection for port x bit y (y = 8..15) + 12 + 4 + + + AFRH10 + Alternate function selection for port x bit y (y = 8..15) + 8 + 4 + + + AFRH9 + Alternate function selection for port x bit y (y = 8..15) + 4 + 4 + + + AFRH8 + Alternate function selection for port x bit y (y = 8..15) + 0 + 4 + + + + + BRR + BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + Port Reset bit + 0 + 1 + + + BR1 + Port Reset bit + 1 + 1 + + + BR2 + Port Reset bit + 2 + 1 + + + BR3 + Port Reset bit + 3 + 1 + + + BR4 + Port Reset bit + 4 + 1 + + + BR5 + Port Reset bit + 5 + 1 + + + BR6 + Port Reset bit + 6 + 1 + + + BR7 + Port Reset bit + 7 + 1 + + + BR8 + Port Reset bit + 8 + 1 + + + BR9 + Port Reset bit + 9 + 1 + + + BR10 + Port Reset bit + 10 + 1 + + + BR11 + Port Reset bit + 11 + 1 + + + BR12 + Port Reset bit + 12 + 1 + + + BR13 + Port Reset bit + 13 + 1 + + + BR14 + Port Reset bit + 14 + 1 + + + BR15 + Port Reset bit + 15 + 1 + + + + + ASCR + ASCR + GPIO port analog switch control register + 0x2C + 0x20 + read-write + 0x00000000 + + + ASC0 + Port analog switch control + 0 + 1 + + + ASC1 + Port analog switch control + 1 + 1 + + + ASC2 + Port analog switch control + 2 + 1 + + + ASC3 + Port analog switch control + 3 + 1 + + + ASC4 + Port analog switch control + 4 + 1 + + + ASC5 + Port analog switch control + 5 + 1 + + + ASC6 + Port analog switch control + 6 + 1 + + + ASC7 + Port analog switch control + 7 + 1 + + + ASC8 + Port analog switch control + 8 + 1 + + + ASC9 + Port analog switch control + 9 + 1 + + + ASC10 + Port analog switch control + 10 + 1 + + + ASC11 + Port analog switch control + 11 + 1 + + + ASC12 + Port analog switch control + 12 + 1 + + + ASC13 + Port analog switch control + 13 + 1 + + + ASC14 + Port analog switch control + 14 + 1 + + + ASC15 + Port analog switch control + 15 + 1 + + + + + + + GPIOD + 0x48000C00 + + + GPIOE + 0x48001000 + + + GPIOF + 0x48001400 + + + GPIOG + 0x48001800 + + + GPIOH + 0x48001C00 + + + SAI1 + Serial audio interface + SAI + 0x40015400 + + 0x0 + 0x400 + registers + + + SAI1 + SAI1 global interrupt + 74 + + + + BCR1 + BCR1 + BConfiguration register 1 + 0x24 + 0x20 + read-write + 0x00000040 + + + MCKDIV + Master clock divider + 20 + 4 + + + NODIV + No divider + 19 + 1 + + + DMAEN + DMA enable + 17 + 1 + + + SAIBEN + Audio block B enable + 16 + 1 + + + OutDri + Output drive + 13 + 1 + + + MONO + Mono mode + 12 + 1 + + + SYNCEN + Synchronization enable + 10 + 2 + + + CKSTR + Clock strobing edge + 9 + 1 + + + LSBFIRST + Least significant bit first + 8 + 1 + + + DS + Data size + 5 + 3 + + + PRTCFG + Protocol configuration + 2 + 2 + + + MODE + Audio block mode + 0 + 2 + + + + + BCR2 + BCR2 + BConfiguration register 2 + 0x28 + 0x20 + read-write + 0x00000000 + + + COMP + Companding mode + 14 + 2 + + + CPL + Complement bit + 13 + 1 + + + MUTECN + Mute counter + 7 + 6 + + + MUTEVAL + Mute value + 6 + 1 + + + MUTE + Mute + 5 + 1 + + + TRIS + Tristate management on data line + 4 + 1 + + + FFLUS + FIFO flush + 3 + 1 + + + FTH + FIFO threshold + 0 + 3 + + + + + BFRCR + BFRCR + BFRCR + 0x2C + 0x20 + read-write + 0x00000007 + + + FSOFF + Frame synchronization offset + 18 + 1 + + + FSPOL + Frame synchronization polarity + 17 + 1 + + + FSDEF + Frame synchronization definition + 16 + 1 + + + FSALL + Frame synchronization active level length + 8 + 7 + + + FRL + Frame length + 0 + 8 + + + + + BSLOTR + BSLOTR + BSlot register + 0x30 + 0x20 + read-write + 0x00000000 + + + SLOTEN + Slot enable + 16 + 16 + + + NBSLOT + Number of slots in an audio frame + 8 + 4 + + + SLOTSZ + Slot size + 6 + 2 + + + FBOFF + First bit offset + 0 + 5 + + + + + BIM + BIM + BInterrupt mask register2 + 0x34 + 0x20 + read-write + 0x00000000 + + + LFSDETIE + Late frame synchronization detection interrupt enable + 6 + 1 + + + AFSDETIE + Anticipated frame synchronization detection interrupt enable + 5 + 1 + + + CNRDYIE + Codec not ready interrupt enable + 4 + 1 + + + FREQIE + FIFO request interrupt enable + 3 + 1 + + + WCKCFG + Wrong clock configuration interrupt enable + 2 + 1 + + + MUTEDET + Mute detection interrupt enable + 1 + 1 + + + OVRUDRIE + Overrun/underrun interrupt enable + 0 + 1 + + + + + BSR + BSR + BStatus register + 0x38 + 0x20 + read-only + 0x00000000 + + + FLVL + FIFO level threshold + 16 + 3 + + + LFSDET + Late frame synchronization detection + 6 + 1 + + + AFSDET + Anticipated frame synchronization detection + 5 + 1 + + + CNRDY + Codec not ready + 4 + 1 + + + FREQ + FIFO request + 3 + 1 + + + WCKCFG + Wrong clock configuration flag + 2 + 1 + + + MUTEDET + Mute detection + 1 + 1 + + + OVRUDR + Overrun / underrun + 0 + 1 + + + + + BCLRFR + BCLRFR + BClear flag register + 0x3C + 0x20 + write-only + 0x00000000 + + + LFSDET + Clear late frame synchronization detection flag + 6 + 1 + + + CAFSDET + Clear anticipated frame synchronization detection flag + 5 + 1 + + + CNRDY + Clear codec not ready flag + 4 + 1 + + + WCKCFG + Clear wrong clock configuration flag + 2 + 1 + + + MUTEDET + Mute detection flag + 1 + 1 + + + OVRUDR + Clear overrun / underrun + 0 + 1 + + + + + BDR + BDR + BData register + 0x40 + 0x20 + read-write + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + ACR1 + ACR1 + AConfiguration register 1 + 0x4 + 0x20 + read-write + 0x00000040 + + + MCKDIV + Master clock divider + 20 + 4 + + + NODIV + No divider + 19 + 1 + + + DMAEN + DMA enable + 17 + 1 + + + SAIAEN + Audio block A enable + 16 + 1 + + + OutDri + Output drive + 13 + 1 + + + MONO + Mono mode + 12 + 1 + + + SYNCEN + Synchronization enable + 10 + 2 + + + CKSTR + Clock strobing edge + 9 + 1 + + + LSBFIRST + Least significant bit first + 8 + 1 + + + DS + Data size + 5 + 3 + + + PRTCFG + Protocol configuration + 2 + 2 + + + MODE + Audio block mode + 0 + 2 + + + + + ACR2 + ACR2 + AConfiguration register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + COMP + Companding mode + 14 + 2 + + + CPL + Complement bit + 13 + 1 + + + MUTECN + Mute counter + 7 + 6 + + + MUTEVAL + Mute value + 6 + 1 + + + MUTE + Mute + 5 + 1 + + + TRIS + Tristate management on data line + 4 + 1 + + + FFLUS + FIFO flush + 3 + 1 + + + FTH + FIFO threshold + 0 + 3 + + + + + AFRCR + AFRCR + AFRCR + 0xC + 0x20 + read-write + 0x00000007 + + + FSOFF + Frame synchronization offset + 18 + 1 + + + FSPOL + Frame synchronization polarity + 17 + 1 + + + FSDEF + Frame synchronization definition + 16 + 1 + + + FSALL + Frame synchronization active level length + 8 + 7 + + + FRL + Frame length + 0 + 8 + + + + + ASLOTR + ASLOTR + ASlot register + 0x10 + 0x20 + read-write + 0x00000000 + + + SLOTEN + Slot enable + 16 + 16 + + + NBSLOT + Number of slots in an audio frame + 8 + 4 + + + SLOTSZ + Slot size + 6 + 2 + + + FBOFF + First bit offset + 0 + 5 + + + + + AIM + AIM + AInterrupt mask register2 + 0x14 + 0x20 + read-write + 0x00000000 + + + LFSDET + Late frame synchronization detection interrupt enable + 6 + 1 + + + AFSDETIE + Anticipated frame synchronization detection interrupt enable + 5 + 1 + + + CNRDYIE + Codec not ready interrupt enable + 4 + 1 + + + FREQIE + FIFO request interrupt enable + 3 + 1 + + + WCKCFG + Wrong clock configuration interrupt enable + 2 + 1 + + + MUTEDET + Mute detection interrupt enable + 1 + 1 + + + OVRUDRIE + Overrun/underrun interrupt enable + 0 + 1 + + + + + ASR + ASR + AStatus register + 0x18 + 0x20 + read-write + 0x00000000 + + + FLVL + FIFO level threshold + 16 + 3 + + + LFSDET + Late frame synchronization detection + 6 + 1 + + + AFSDET + Anticipated frame synchronization detection + 5 + 1 + + + CNRDY + Codec not ready + 4 + 1 + + + FREQ + FIFO request + 3 + 1 + + + WCKCFG + Wrong clock configuration flag. This bit is read only + 2 + 1 + + + MUTEDET + Mute detection + 1 + 1 + + + OVRUDR + Overrun / underrun + 0 + 1 + + + + + ACLRFR + ACLRFR + AClear flag register + 0x1C + 0x20 + read-write + 0x00000000 + + + LFSDET + Clear late frame synchronization detection flag + 6 + 1 + + + CAFSDET + Clear anticipated frame synchronization detection flag + 5 + 1 + + + CNRDY + Clear codec not ready flag + 4 + 1 + + + WCKCFG + Clear wrong clock configuration flag + 2 + 1 + + + MUTEDET + Mute detection flag + 1 + 1 + + + OVRUDR + Clear overrun / underrun + 0 + 1 + + + + + ADR + ADR + AData register + 0x20 + 0x20 + read-write + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + GCR + GCR + Global configuration register + 0x0 + 0x20 + read-write + 0x00000000 + + + SYNCIN + Synchronization inputs + 0 + 2 + + + SYNCOUT + Synchronization outputs + 4 + 2 + + + + + + + SAI2 + 0x40015800 + + SAI2 + SAI2 global interrupt + 75 + + + + TIM2 + General-purpose-timers + TIM + 0x40000000 + + 0x0 + 0x400 + registers + + + TIM2 + TIM2 global interrupt + 28 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CMS + Center-aligned mode selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + TI1S + TI1 selection + 7 + 1 + + + MMS + Master mode selection + 4 + 3 + + + CCDS + Capture/compare DMA selection + 3 + 1 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + ETP + External trigger polarity + 15 + 1 + + + ECE + External clock enable + 14 + 1 + + + ETPS + External trigger prescaler + 12 + 2 + + + ETF + External trigger filter + 8 + 4 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + SMS + Slave mode selection + 0 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + COMDE + COM DMA request enable + 13 + 1 + + + CC4DE + Capture/Compare 4 DMA request enable + 12 + 1 + + + CC3DE + Capture/Compare 3 DMA request enable + 11 + 1 + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + CC4IE + Capture/Compare 4 interrupt enable + 4 + 1 + + + CC3IE + Capture/Compare 3 interrupt enable + 3 + 1 + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC4OF + Capture/Compare 4 overcapture flag + 12 + 1 + + + CC3OF + Capture/Compare 3 overcapture flag + 11 + 1 + + + CC2OF + Capture/compare 2 overcapture flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture flag + 9 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + CC4IF + Capture/Compare 4 interrupt flag + 4 + 1 + + + CC3IF + Capture/Compare 3 interrupt flag + 3 + 1 + + + CC2IF + Capture/Compare 2 interrupt flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + TG + Trigger generation + 6 + 1 + + + CC4G + Capture/compare 4 generation + 4 + 1 + + + CC3G + Capture/compare 3 generation + 3 + 1 + + + CC2G + Capture/compare 2 generation + 2 + 1 + + + CC1G + Capture/compare 1 generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2M_bit3 + Output Compare 2 mode + 24 + 1 + + + OC1M_bit3 + Output Compare 1 mode + 16 + 1 + + + OC2CE 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prescaler + 2 + 2 + + + CC3S + Capture/Compare 3 selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable register + 0x20 + 0x20 + read-write + 0x0000 + + + CC4NP + Capture/Compare 4 output Polarity + 15 + 1 + + + CC4P + Capture/Compare 3 output Polarity + 13 + 1 + + + CC4E + Capture/Compare 4 output enable + 12 + 1 + + + CC3NP + Capture/Compare 3 output Polarity + 11 + 1 + + + CC3P + Capture/Compare 3 output Polarity + 9 + 1 + + + CC3E + Capture/Compare 3 output enable + 8 + 1 + + + CC2NP + Capture/Compare 2 output Polarity + 7 + 1 + + + CC2P + Capture/Compare 2 output Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output Polarity + 3 + 1 + + + CC1P + Capture/Compare 1 output Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT_H + High counter value (TIM2 only) + 16 + 16 + + + CNT_L + Low counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR_H + High Auto-reload value (TIM2 only) + 16 + 16 + + + ARR_L + Low Auto-reload value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1_H + High Capture/Compare 1 value (TIM2 only) + 16 + 16 + + + CCR1_L + Low Capture/Compare 1 value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2_H + High Capture/Compare 2 value (TIM2 only) + 16 + 16 + + + CCR2_L + Low Capture/Compare 2 value + 0 + 16 + + + + + CCR3 + CCR3 + capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + CCR3_H + High Capture/Compare value (TIM2 only) + 16 + 16 + + + CCR3_L + Low Capture/Compare value + 0 + 16 + + + + + CCR4 + CCR4 + capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + + + CCR4_H + High Capture/Compare value (TIM2 only) + 16 + 16 + + + CCR4_L + Low Capture/Compare value + 0 + 16 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst accesses + 0 + 16 + + + + + OR + OR + TIM2 option register + 0x50 + 0x20 + read-write + 0x0000 + + + ETR_RMP + Timer2 ETR remap + 0 + 3 + + + TI4_RMP + Internal trigger + 3 + 2 + + + + + + + TIM3 + 0x40000400 + + TIM3 + TIM3 global interrupt + 29 + + + + TIM4 + 0x40000800 + + TIM4 + TIM4 global interrupt + 30 + + + + TIM5 + 0x40000C00 + + TIM5 + TIM5 global Interrupt + 50 + + + + TIM15 + General purpose timers + TIM + 0x40014000 + + 0x0 + 0x400 + registers + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CEN + Counter enable + 0 + 1 + + + UDIS + Update disable + 1 + 1 + + + URS + Update request source + 2 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CKD + Clock division + 8 + 2 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + CCDS + Capture/compare DMA selection + 3 + 1 + + + CCUS + Capture/compare control update selection + 2 + 1 + + + CCPC + Capture/compare preloaded control + 0 + 1 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + COMDE + COM DMA request enable + 13 + 1 + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + CC1IE + Capture/Compare 1 interrupt enable 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Compare 1 fast enable + 2 + 1 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable register + 0x20 + 0x20 + read-write + 0x0000 + + + CC1NP + Capture/Compare 1 output Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output enable + 2 + 1 + + + CC1P + Capture/Compare 1 output Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + 0x00000000 + + + CNT + counter value + 0 + 16 + read-write + + + UIFCPY + UIF Copy + 31 + 1 + read-only + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + REP + Repetition counter value + 0 + 8 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x0000 + + + DTG + Dead-time generator setup + 0 + 8 + + + LOCK + Lock configuration + 8 + 2 + + + OSSI + Off-state selection for Idle mode + 10 + 1 + + + OSSR + Off-state selection for Run mode + 11 + 1 + + + BKE + Break enable + 12 + 1 + + + BKP + Break polarity + 13 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + MOE + Main output enable + 15 + 1 + + + BKF + Break filter + 16 + 4 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst accesses + 0 + 16 + + + + + + + TIM16 + General purpose timers + TIM + 0x40014400 + + 0x0 + 0x400 + registers + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CEN + Counter enable + 0 + 1 + + + UDIS + Update disable + 1 + 1 + + + URS + Update request source + 2 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CKD + Clock division + 8 + 2 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + CCDS + Capture/compare DMA selection + 3 + 1 + + + CCUS + Capture/compare control update selection + 2 + 1 + + + CCPC + Capture/compare preloaded control + 0 + 1 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + COMDE + COM DMA request enable + 13 + 1 + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC1OF + Capture/Compare 1 overcapture flag + 9 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + CC1IF + Capture/compare 1 interrupt flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + BG + Break generation + 7 + 1 + + + TG + Trigger generation + 6 + 1 + + + COMG + Capture/Compare control update generation + 5 + 1 + + + CC1G + Capture/compare 1 generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register (output mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC1M_2 + Output Compare 1 mode + 16 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload enable + 3 + 1 + + + OC1FE + Output Compare 1 fast enable + 2 + 1 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable register + 0x20 + 0x20 + read-write + 0x0000 + + + CC1NP + Capture/Compare 1 output Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output enable + 2 + 1 + + + CC1P + Capture/Compare 1 output Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + 0x00000000 + + + CNT + counter value + 0 + 16 + read-write + + + UIFCPY + UIF Copy + 31 + 1 + read-only + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + REP + Repetition counter value + 0 + 8 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x0000 + + + DTG + Dead-time generator setup + 0 + 8 + + + LOCK + Lock configuration + 8 + 2 + + + OSSI + Off-state selection for Idle mode + 10 + 1 + + + OSSR + Off-state selection for Run mode + 11 + 1 + + + BKE + Break enable + 12 + 1 + + + BKP + Break polarity + 13 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + MOE + Main output enable + 15 + 1 + + + BKF + Break filter + 16 + 4 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst accesses + 0 + 16 + + + + + OR1 + OR1 + TIM16 option register 1 + 0x50 + 0x20 + read-write + 0x0000 + + + TI1_RMP + Input capture 1 remap + 0 + 2 + + + + + OR2 + OR2 + TIM17 option register 1 + 0x60 + 0x20 + read-write + 0x0000 + + + BKINE + BRK BKIN input enable + 0 + 1 + + + BKCMP1E + BRK COMP1 enable + 1 + 1 + + + BKCMP2E + BRK COMP2 enable + 2 + 1 + + + BKDFBK1E + BRK DFSDM_BREAK1 enable + 8 + 1 + + + BKINP + BRK BKIN input polarity + 9 + 1 + + + BKCMP1P + BRK COMP1 input polarity + 10 + 1 + + + BKCMP2P + BRK COMP2 input polarit + 11 + 1 + + + + + + + TIM17 + 0x40014800 + + + TIM1 + Advanced-timers + TIM + 0x40012C00 + + 0x0 + 0x400 + registers + + + TIM1_BRK_TIM15 + TIM1 Break/TIM15 global + interrupts + 24 + + + TIM1_UP_TIM16 + TIM1 Update/TIM16 global + interrupts + 25 + + + TIM1_TRG_COM_TIM17 + TIM1 Trigger and Commutation interrupts and + TIM17 global interrupt + 26 + + + TIM1_CC + TIM1 Capture Compare interrupt + 27 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CMS + Center-aligned mode selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + OIS4 + Output Idle state 4 + 14 + 1 + + + OIS3N + Output Idle state 3 + 13 + 1 + + + OIS3 + Output Idle state 3 + 12 + 1 + + + OIS2N + Output Idle state 2 + 11 + 1 + + + OIS2 + Output Idle state 2 + 10 + 1 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + TI1S + TI1 selection + 7 + 1 + + + MMS + Master mode selection + 4 + 3 + + + CCDS + Capture/compare DMA selection + 3 + 1 + + + CCUS + Capture/compare control update selection + 2 + 1 + + + CCPC + Capture/compare preloaded control + 0 + 1 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + ETP + External trigger polarity + 15 + 1 + + + ECE + External clock enable + 14 + 1 + + + ETPS + External trigger prescaler + 12 + 2 + + + ETF + External trigger filter + 8 + 4 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + SMS + Slave mode selection + 0 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + COMDE + COM DMA request enable + 13 + 1 + + + CC4DE + Capture/Compare 4 DMA request enable + 12 + 1 + + + CC3DE + Capture/Compare 3 DMA request enable + 11 + 1 + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + CC4IE + Capture/Compare 4 interrupt enable + 4 + 1 + + + CC3IE + Capture/Compare 3 interrupt enable + 3 + 1 + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC4OF + Capture/Compare 4 overcapture flag + 12 + 1 + + + CC3OF + Capture/Compare 3 overcapture flag + 11 + 1 + + + CC2OF + Capture/compare 2 overcapture flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture flag + 9 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + CC4IF + Capture/Compare 4 interrupt flag + 4 + 1 + + + CC3IF + Capture/Compare 3 interrupt flag + 3 + 1 + + + CC2IF + Capture/Compare 2 interrupt flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + BG + Break generation + 7 + 1 + + + TG + Trigger generation + 6 + 1 + + + COMG + Capture/Compare control update generation + 5 + 1 + + + CC4G + Capture/compare 4 generation + 4 + 1 + + + CC3G + Capture/compare 3 generation + 3 + 1 + + + CC2G + Capture/compare 2 generation + 2 + 1 + + + CC1G + Capture/compare 1 generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2M_bit3 + Output Compare 2 mode + 24 + 1 + + + OC1M_bit3 + Output Compare 1 mode + 16 + 1 + + + OC2CE + Output Compare 2 clear enable + 15 + 1 + + + OC2M + Output Compare 2 mode + 12 + 3 + + + OC2PE + Output Compare 2 preload enable + 11 + 1 + + + OC2FE + Output Compare 2 fast enable + 10 + 1 + + + CC2S + Capture/Compare 2 selection + 8 + 2 + + + OC1CE + Output Compare 1 clear enable + 7 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload enable + 3 + 1 + + + OC1FE + Output Compare 1 fast enable + 2 + 1 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCMR2_Output + CCMR2_Output + capture/compare mode register 2 (output mode) + 0x1C + 0x20 + read-write + 0x00000000 + + + OC4M_bit3 + Output Compare 4 mode + 24 + 1 + + + OC3M_bit3 + Output Compare 3 mode + 16 + 1 + + + OC4CE + Output compare 4 clear enable + 15 + 1 + + + OC4M + Output compare 4 mode + 12 + 3 + + + OC4PE + Output compare 4 preload enable + 11 + 1 + + + OC4FE + Output compare 4 fast enable + 10 + 1 + + + CC4S + Capture/Compare 4 selection + 8 + 2 + + + OC3CE + Output compare 3 clear enable + 7 + 1 + + + OC3M + Output compare 3 mode + 4 + 3 + + + OC3PE + Output compare 3 preload enable + 3 + 1 + + + OC3FE + Output compare 3 fast enable + 2 + 1 + + + CC3S + Capture/Compare 3 selection + 0 + 2 + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (input mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + CC4S + Capture/Compare 4 selection + 8 + 2 + + + IC3F + Input capture 3 filter + 4 + 4 + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + CC3S + Capture/compare 3 selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable register + 0x20 + 0x20 + read-write + 0x0000 + + + CC4P + Capture/Compare 3 output Polarity + 13 + 1 + + + CC4E + Capture/Compare 4 output enable + 12 + 1 + + + CC3NP + Capture/Compare 3 output Polarity + 11 + 1 + + + CC3NE + Capture/Compare 3 complementary output enable + 10 + 1 + + + CC3P + Capture/Compare 3 output Polarity + 9 + 1 + + + CC3E + Capture/Compare 3 output enable + 8 + 1 + + + CC2NP + Capture/Compare 2 output Polarity + 7 + 1 + + + CC2NE + Capture/Compare 2 complementary output enable + 6 + 1 + + + CC2P + Capture/Compare 2 output Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output enable + 2 + 1 + + + CC1P + Capture/Compare 1 output Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + REP + Repetition counter value + 0 + 8 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/Compare 2 value + 0 + 16 + + + + + CCR3 + CCR3 + capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + CCR3 + Capture/Compare value + 0 + 16 + + + + + CCR4 + CCR4 + capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + + + CCR4 + Capture/Compare value + 0 + 16 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x0000 + + + MOE + Main output enable + 15 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + BKP + Break polarity + 13 + 1 + + + BKE + Break enable + 12 + 1 + + + OSSR + Off-state selection for Run mode + 11 + 1 + + + OSSI + Off-state selection for Idle mode + 10 + 1 + + + LOCK + Lock configuration + 8 + 2 + + + DTG + Dead-time generator setup + 0 + 8 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst accesses + 0 + 16 + + + + + OR1 + OR1 + DMA address for full transfer + 0x50 + 0x20 + read-write + 0x0000 + + + ETR_ADC1_RMP + External trigger remap on ADC1 analog watchdog + 0 + 2 + + + ETR_ADC3_RMP + External trigger remap on ADC3 analog watchdog + 2 + 2 + + + TI1_RMP + Input Capture 1 remap + 4 + 1 + + + + + CCMR3_Output + CCMR3_Output + capture/compare mode register 2 (output mode) + 0x54 + 0x20 + read-write + 0x00000000 + + + OC6M_bit3 + Output Compare 6 mode bit 3 + 24 + 1 + + + OC5M_bit3 + Output Compare 5 mode bit 3 + 16 + 3 + + + OC6CE + Output compare 6 clear enable + 15 + 1 + + + OC6M + Output compare 6 mode + 12 + 3 + + + OC6PE + Output compare 6 preload enable + 11 + 1 + + + OC6FE + Output compare 6 fast enable + 10 + 1 + + + OC5CE + Output compare 5 clear enable + 7 + 1 + + + OC5M + Output compare 5 mode + 4 + 3 + + + OC5PE + Output compare 5 preload enable + 3 + 1 + + + OC5FE + Output compare 5 fast enable + 2 + 1 + + + + + CCR5 + CCR5 + capture/compare register 4 + 0x58 + 0x20 + read-write + 0x00000000 + + + CCR5 + Capture/Compare value + 0 + 16 + + + GC5C1 + Group Channel 5 and Channel 1 + 29 + 1 + + + GC5C2 + Group Channel 5 and Channel 2 + 30 + 1 + + + GC5C3 + Group Channel 5 and Channel 3 + 31 + 1 + + + + + CCR6 + CCR6 + capture/compare register 4 + 0x5C + 0x20 + read-write + 0x00000000 + + + CCR6 + Capture/Compare value + 0 + 16 + + + + + OR2 + OR2 + DMA address for full transfer + 0x60 + 0x20 + read-write + 0x00000001 + + + BKINE + BRK BKIN input enable + 0 + 1 + + + BKCMP1E + BRK COMP1 enable + 1 + 1 + + + BKCMP2E + BRK COMP2 enable + 2 + 1 + + + BKDFBK0E + BRK DFSDM_BREAK0 enable + 8 + 1 + + + BKINP + BRK BKIN input polarity + 9 + 1 + + + BKCMP1P + BRK COMP1 input polarity + 10 + 1 + + + BKCMP2P + BRK COMP2 input polarity + 11 + 1 + + + ETRSEL + ETR source selection + 14 + 3 + + + + + OR3 + OR3 + DMA address for full transfer + 0x64 + 0x20 + read-write + 0x00000001 + + + BK2INE + BRK2 BKIN input enable + 0 + 1 + + + BK2CMP1E + BRK2 COMP1 enable + 1 + 1 + + + BK2CMP2E + BRK2 COMP2 enable + 2 + 1 + + + BK2DFBK0E + BRK2 DFSDM_BREAK0 enable + 8 + 1 + + + BK2INP + BRK2 BKIN input polarity + 9 + 1 + + + BK2CMP1P + BRK2 COMP1 input polarity + 10 + 1 + + + BK2CMP2P + BRK2 COMP2 input polarity + 11 + 1 + + + + + + + TIM8 + Advanced-timers + TIM + 0x40013400 + + 0x0 + 0x400 + registers + + + TIM8_BRK + TIM8 Break Interrupt + 43 + + + TIM8_UP + TIM8 Update Interrupt + 44 + + + TIM8_TRG_COM + TIM8 Trigger and Commutation + Interrupt + 45 + + + TIM8_CC + TIM8 Capture Compare Interrupt + 46 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CMS + Center-aligned mode selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + OIS4 + Output Idle state 4 + 14 + 1 + + + OIS3N + Output Idle state 3 + 13 + 1 + + + OIS3 + Output Idle state 3 + 12 + 1 + + + OIS2N + Output Idle state 2 + 11 + 1 + + + OIS2 + Output Idle state 2 + 10 + 1 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + TI1S + TI1 selection + 7 + 1 + + + MMS + Master mode selection + 4 + 3 + + + CCDS + Capture/compare DMA selection + 3 + 1 + + + CCUS + Capture/compare control update selection + 2 + 1 + + + CCPC + Capture/compare preloaded control + 0 + 1 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + ETP + External trigger polarity + 15 + 1 + + + ECE + External clock enable + 14 + 1 + + + ETPS + External trigger prescaler + 12 + 2 + + + ETF + External trigger filter + 8 + 4 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + SMS + Slave mode selection + 0 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + COMDE + COM DMA request enable + 13 + 1 + + + CC4DE + Capture/Compare 4 DMA request enable + 12 + 1 + + + CC3DE + Capture/Compare 3 DMA request enable + 11 + 1 + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + CC4IE + Capture/Compare 4 interrupt enable + 4 + 1 + + + CC3IE + Capture/Compare 3 interrupt enable + 3 + 1 + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC4OF + Capture/Compare 4 overcapture flag + 12 + 1 + + + CC3OF + Capture/Compare 3 overcapture flag + 11 + 1 + + + CC2OF + Capture/compare 2 overcapture flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture flag + 9 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + CC4IF + Capture/Compare 4 interrupt flag + 4 + 1 + + + CC3IF + Capture/Compare 3 interrupt flag + 3 + 1 + + + CC2IF + Capture/Compare 2 interrupt flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + BG + Break generation + 7 + 1 + + + TG + Trigger generation + 6 + 1 + + + COMG + Capture/Compare control update generation + 5 + 1 + + + CC4G + Capture/compare 4 generation + 4 + 1 + + + CC3G + Capture/compare 3 generation + 3 + 1 + + + CC2G + Capture/compare 2 generation + 2 + 1 + + + CC1G + Capture/compare 1 generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2M_bit3 + Output Compare 2 mode + 24 + 1 + + + OC1M_bit3 + Output Compare 1 mode + 16 + 1 + + + OC2CE + Output Compare 2 clear enable + 15 + 1 + + + OC2M + Output Compare 2 mode + 12 + 3 + + + OC2PE + Output Compare 2 preload enable + 11 + 1 + + + OC2FE + Output Compare 2 fast enable + 10 + 1 + + + CC2S + Capture/Compare 2 selection + 8 + 2 + + + OC1CE + Output Compare 1 clear enable + 7 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload enable + 3 + 1 + + + OC1FE + Output Compare 1 fast enable + 2 + 1 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCMR2_Output + CCMR2_Output + capture/compare mode register 2 (output mode) + 0x1C + 0x20 + read-write + 0x00000000 + + + OC4M_bit3 + Output Compare 4 mode + 24 + 1 + + + OC3M_bit3 + Output Compare 3 mode + 16 + 1 + + + OC4CE + Output compare 4 clear enable + 15 + 1 + + + OC4M + Output compare 4 mode + 12 + 3 + + + OC4PE + Output compare 4 preload enable + 11 + 1 + + + OC4FE + Output compare 4 fast enable + 10 + 1 + + + CC4S + Capture/Compare 4 selection + 8 + 2 + + + OC3CE + Output compare 3 clear enable + 7 + 1 + + + OC3M + Output compare 3 mode + 4 + 3 + + + OC3PE + Output compare 3 preload enable + 3 + 1 + + + OC3FE + Output compare 3 fast enable + 2 + 1 + + + CC3S + Capture/Compare 3 selection + 0 + 2 + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (input mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + CC4S + Capture/Compare 4 selection + 8 + 2 + + + IC3F + Input capture 3 filter + 4 + 4 + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + CC3S + Capture/compare 3 selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable register + 0x20 + 0x20 + read-write + 0x0000 + + + CC4P + Capture/Compare 3 output Polarity + 13 + 1 + + + CC4E + Capture/Compare 4 output enable + 12 + 1 + + + CC3NP + Capture/Compare 3 output Polarity + 11 + 1 + + + CC3NE + Capture/Compare 3 complementary output enable + 10 + 1 + + + CC3P + Capture/Compare 3 output Polarity + 9 + 1 + + + CC3E + Capture/Compare 3 output enable + 8 + 1 + + + CC2NP + Capture/Compare 2 output Polarity + 7 + 1 + + + CC2NE + Capture/Compare 2 complementary output enable + 6 + 1 + + + CC2P + Capture/Compare 2 output Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output enable + 2 + 1 + + + CC1P + Capture/Compare 1 output Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + REP + Repetition counter value + 0 + 8 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/Compare 2 value + 0 + 16 + + + + + CCR3 + CCR3 + capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + CCR3 + Capture/Compare value + 0 + 16 + + + + + CCR4 + CCR4 + capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + + + CCR4 + Capture/Compare value + 0 + 16 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x0000 + + + MOE + Main output enable + 15 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + BKP + Break polarity + 13 + 1 + + + BKE + Break enable + 12 + 1 + + + OSSR + Off-state selection for Run mode + 11 + 1 + + + OSSI + Off-state selection for Idle mode + 10 + 1 + + + LOCK + Lock configuration + 8 + 2 + + + DTG + Dead-time generator setup + 0 + 8 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst accesses + 0 + 16 + + + + + OR1 + OR1 + DMA address for full transfer + 0x50 + 0x20 + read-write + 0x0000 + + + ETR_ADC2_RMP + External trigger remap on ADC2 analog watchdog + 0 + 2 + + + ETR_ADC3_RMP + External trigger remap on ADC3 analog watchdog + 2 + 2 + + + TI1_RMP + Input Capture 1 remap + 4 + 1 + + + + + CCMR3_Output + CCMR3_Output + capture/compare mode register 2 (output mode) + 0x54 + 0x20 + read-write + 0x00000000 + + + OC6M_bit3 + Output Compare 6 mode bit 3 + 24 + 1 + + + OC5M_bit3 + Output Compare 5 mode bit 3 + 16 + 3 + + + OC6CE + Output compare 6 clear enable + 15 + 1 + + + OC6M + Output compare 6 mode + 12 + 3 + + + OC6PE + Output compare 6 preload enable + 11 + 1 + + + OC6FE + Output compare 6 fast enable + 10 + 1 + + + OC5CE + Output compare 5 clear enable + 7 + 1 + + + OC5M + Output compare 5 mode + 4 + 3 + + + OC5PE + Output compare 5 preload enable + 3 + 1 + + + OC5FE + Output compare 5 fast enable + 2 + 1 + + + + + CCR5 + CCR5 + capture/compare register 4 + 0x58 + 0x20 + read-write + 0x00000000 + + + CCR5 + Capture/Compare value + 0 + 16 + + + GC5C1 + Group Channel 5 and Channel 1 + 29 + 1 + + + GC5C2 + Group Channel 5 and Channel 2 + 30 + 1 + + + GC5C3 + Group Channel 5 and Channel 3 + 31 + 1 + + + + + CCR6 + CCR6 + capture/compare register 4 + 0x5C + 0x20 + read-write + 0x00000000 + + + CCR6 + Capture/Compare value + 0 + 16 + + + + + OR2 + OR2 + DMA address for full transfer + 0x60 + 0x20 + read-write + 0x00000001 + + + BKINE + BRK BKIN input enable + 0 + 1 + + + BKCMP1E + BRK COMP1 enable + 1 + 1 + + + BKCMP2E + BRK COMP2 enable + 2 + 1 + + + BKDFBK2E + BRK DFSDM_BREAK2 enable + 8 + 1 + + + BKINP + BRK BKIN input polarity + 9 + 1 + + + BKCMP1P + BRK COMP1 input polarity + 10 + 1 + + + BKCMP2P + BRK COMP2 input polarity + 11 + 1 + + + ETRSEL + ETR source selection + 14 + 3 + + + + + OR3 + OR3 + DMA address for full transfer + 0x64 + 0x20 + read-write + 0x00000001 + + + BK2INE + BRK2 BKIN input enable + 0 + 1 + + + BK2CMP1E + BRK2 COMP1 enable + 1 + 1 + + + BK2CMP2E + BRK2 COMP2 enable + 2 + 1 + + + BK2DFBK3E + BRK2 DFSDM_BREAK3 enable + 8 + 1 + + + BK2INP + BRK2 BKIN input polarity + 9 + 1 + + + BK2CMP1P + BRK2 COMP1 input polarity + 10 + 1 + + + BK2CMP2P + BRK2 COMP2 input polarity + 11 + 1 + + + + + + + TIM6 + Basic-timers + TIM + 0x40001000 + + 0x0 + 0x400 + registers + + + TIM6_DACUNDER + TIM6 global and DAC1 and 2 underrun error + interrupts + 54 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + MMS + Master mode selection + 4 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + UDE + Update DMA request enable + 8 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + UG + Update generation + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + Low counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Low Auto-reload value + 0 + 16 + + + + + + + TIM7 + 0x40001400 + + TIM7 + TIM7 global interrupt + 55 + + + + LPTIM1 + Low power timer + LPTIM + 0x40007C00 + + 0x0 + 0x400 + registers + + + LPTIM1 + LP TIM1 interrupt + 65 + + + + ISR + ISR + Interrupt and Status Register + 0x0 + 0x20 + read-only + 0x00000000 + + + DOWN + Counter direction change up to down + 6 + 1 + + + UP + Counter direction change down to up + 5 + 1 + + + ARROK + Autoreload register update OK + 4 + 1 + + + CMPOK + Compare register update OK + 3 + 1 + + + EXTTRIG + External trigger edge event + 2 + 1 + + + ARRM + Autoreload match + 1 + 1 + + + CMPM + Compare match + 0 + 1 + + + + + ICR + ICR + Interrupt Clear Register + 0x4 + 0x20 + write-only + 0x00000000 + + + DOWNCF + Direction change to down Clear Flag + 6 + 1 + + + UPCF + Direction change to UP Clear Flag + 5 + 1 + + + ARROKCF + Autoreload register update OK Clear Flag + 4 + 1 + + + CMPOKCF + Compare register update OK Clear Flag + 3 + 1 + + + EXTTRIGCF + External trigger valid edge Clear Flag + 2 + 1 + + + ARRMCF + Autoreload match Clear Flag + 1 + 1 + + + CMPMCF + compare match Clear Flag + 0 + 1 + + + + + IER + IER + Interrupt Enable Register + 0x8 + 0x20 + read-write + 0x00000000 + + + DOWNIE + Direction change to down Interrupt Enable + 6 + 1 + + + UPIE + Direction change to UP Interrupt Enable + 5 + 1 + + + ARROKIE + Autoreload register update OK Interrupt Enable + 4 + 1 + + + CMPOKIE + Compare register update OK Interrupt Enable + 3 + 1 + + + EXTTRIGIE + External trigger valid edge Interrupt Enable + 2 + 1 + + + ARRMIE + Autoreload match Interrupt Enable + 1 + 1 + + + CMPMIE + Compare match Interrupt Enable + 0 + 1 + + + + + CFGR + CFGR + Configuration Register + 0xC + 0x20 + read-write + 0x00000000 + + + ENC + Encoder mode enable + 24 + 1 + + + COUNTMODE + counter mode enabled + 23 + 1 + + + PRELOAD + Registers update mode + 22 + 1 + + + WAVPOL + Waveform shape polarity + 21 + 1 + + + WAVE + Waveform shape + 20 + 1 + + + TIMOUT + Timeout enable + 19 + 1 + + + TRIGEN + Trigger enable and polarity + 17 + 2 + + + TRIGSEL + Trigger selector + 13 + 3 + + + PRESC + Clock prescaler + 9 + 3 + + + TRGFLT + Configurable digital filter for trigger + 6 + 2 + + + CKFLT + Configurable digital filter for external clock + 3 + 2 + + + CKPOL + Clock Polarity + 1 + 2 + + + CKSEL + Clock selector + 0 + 1 + + + + + CR + CR + Control Register + 0x10 + 0x20 + read-write + 0x00000000 + + + CNTSTRT + Timer start in continuous mode + 2 + 1 + + + SNGSTRT + LPTIM start in single mode + 1 + 1 + + + ENABLE + LPTIM Enable + 0 + 1 + + + + + CMP + CMP + Compare Register + 0x14 + 0x20 + read-write + 0x00000000 + + + CMP + Compare value + 0 + 16 + + + + + ARR + ARR + Autoreload Register + 0x18 + 0x20 + read-write + 0x00000001 + + + ARR + Auto reload value + 0 + 16 + + + + + CNT + CNT + Counter Register + 0x1C + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 16 + + + + + + + LPTIM2 + 0x40009400 + + LPTIM2 + LP TIM2 interrupt + 66 + + + + USART1 + Universal synchronous asynchronous receiver transmitter + USART + 0x40013800 + + 0x0 + 0x400 + registers + + + USART1 + USART1 global interrupt + 37 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + M1 + Word length + 28 + 1 + + + EOBIE + End of Block interrupt enable + 27 + 1 + + + RTOIE + Receiver timeout interrupt enable + 26 + 1 + + + DEAT4 + Driver Enable assertion time + 25 + 1 + + + DEAT3 + DEAT3 + 24 + 1 + + + DEAT2 + DEAT2 + 23 + 1 + + + DEAT1 + DEAT1 + 22 + 1 + + + DEAT0 + DEAT0 + 21 + 1 + + + DEDT4 + Driver Enable de-assertion time + 20 + 1 + + + DEDT3 + DEDT3 + 19 + 1 + + + DEDT2 + DEDT2 + 18 + 1 + + + DEDT1 + DEDT1 + 17 + 1 + + + DEDT0 + DEDT0 + 16 + 1 + + + OVER8 + Oversampling mode + 15 + 1 + + + CMIE + Character match interrupt enable + 14 + 1 + + + MME + Mute mode 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break detection length + 5 + 1 + + + ADDM7 + 7-bit Address Detection/4-bit Address Detection + 4 + 1 + + + + + CR3 + CR3 + Control register 3 + 0x8 + 0x20 + read-write + 0x00000000 + + + WUFIE + Wakeup from Stop mode interrupt enable + 22 + 1 + + + WUS + Wakeup from Stop mode interrupt flag selection + 20 + 2 + + + SCARCNT + Smartcard auto-retry count + 17 + 3 + + + DEP + Driver enable polarity selection + 15 + 1 + + + DEM + Driver enable mode + 14 + 1 + + + DDRE + DMA Disable on Reception Error + 13 + 1 + + + OVRDIS + Overrun Disable + 12 + 1 + + + ONEBIT + One sample bit method enable + 11 + 1 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSE + CTS enable + 9 + 1 + + + RTSE + RTS enable + 8 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + DMAR + DMA enable receiver + 6 + 1 + + + SCEN + Smartcard mode enable + 5 + 1 + + + NACK + Smartcard NACK enable + 4 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + IRLP + Ir low-power + 2 + 1 + + + IREN + Ir mode enable + 1 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + + + BRR + BRR + Baud rate register + 0xC + 0x20 + read-write + 0x00000000 + + + DIV_Mantissa + DIV_Mantissa + 4 + 12 + + + DIV_Fraction + DIV_Fraction + 0 + 4 + + + + + GTPR + GTPR + Guard time and prescaler register + 0x10 + 0x20 + read-write + 0x00000000 + + + GT + Guard time value + 8 + 8 + + + PSC + Prescaler value + 0 + 8 + + + + + RTOR + RTOR + Receiver timeout register + 0x14 + 0x20 + read-write + 0x00000000 + + + BLEN + Block Length + 24 + 8 + + + RTO + Receiver timeout value + 0 + 24 + + + + + RQR + RQR + Request register + 0x18 + 0x20 + write-only + 0x00000000 + + + TXFRQ + Transmit data flush request + 4 + 1 + + + RXFRQ + Receive data flush request + 3 + 1 + + + MMRQ + Mute mode request + 2 + 1 + + + SBKRQ + Send break request + 1 + 1 + + + ABRRQ + Auto baud rate request + 0 + 1 + + + + + ISR + ISR + Interrupt & status register + 0x1C + 0x20 + read-only + 0x020000C0 + + + REACK + REACK + 22 + 1 + + + TEACK + TEACK + 21 + 1 + + + WUF + WUF + 20 + 1 + + + RWU + RWU + 19 + 1 + + + SBKF + SBKF + 18 + 1 + + + CMF + CMF + 17 + 1 + + + BUSY + BUSY + 16 + 1 + + + ABRF + ABRF + 15 + 1 + + + ABRE + ABRE + 14 + 1 + + + EOBF + EOBF + 12 + 1 + + + RTOF + RTOF + 11 + 1 + + + CTS + CTS + 10 + 1 + + + CTSIF + CTSIF + 9 + 1 + + + LBDF + LBDF + 8 + 1 + + + TXE + TXE + 7 + 1 + + + TC + TC + 6 + 1 + + + RXNE + RXNE + 5 + 1 + + + IDLE + IDLE + 4 + 1 + + + ORE + ORE + 3 + 1 + + + NF + NF + 2 + 1 + + + FE + FE + 1 + 1 + + + PE + PE + 0 + 1 + + + + + ICR + ICR + Interrupt flag clear register + 0x20 + 0x20 + write-only + 0x00000000 + + + WUCF + Wakeup from Stop mode clear flag + 20 + 1 + + + CMCF + Character match clear flag + 17 + 1 + + + EOBCF + End of block clear flag + 12 + 1 + + + RTOCF + Receiver timeout clear flag + 11 + 1 + + + CTSCF + CTS clear flag + 9 + 1 + + + LBDCF + LIN break detection clear flag + 8 + 1 + + + TCCF + Transmission complete clear flag + 6 + 1 + + + IDLECF + Idle line detected clear flag + 4 + 1 + + + ORECF + Overrun error clear flag + 3 + 1 + + + NCF + Noise detected clear flag + 2 + 1 + + + FECF + Framing error clear flag + 1 + 1 + + + PECF + Parity error clear flag + 0 + 1 + + + + + RDR + RDR + Receive data register + 0x24 + 0x20 + read-only + 0x00000000 + + + RDR + Receive data value + 0 + 9 + + + + + TDR + TDR + Transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + + + TDR + Transmit data value + 0 + 9 + + + + + + + UART5 + 0x40005000 + + UART5 + UART5 global Interrupt + 53 + + + + LPUART1 + Universal synchronous asynchronous receiver transmitter + USART + 0x40008000 + + 0x0 + 0x400 + registers + + + LPUART1 + LPUART1 global interrupt + 70 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + M1 + Word length + 28 + 1 + + + DEAT4 + Driver Enable assertion time + 25 + 1 + + + DEAT3 + DEAT3 + 24 + 1 + + + DEAT2 + DEAT2 + 23 + 1 + + + DEAT1 + DEAT1 + 22 + 1 + + + DEAT0 + DEAT0 + 21 + 1 + + + DEDT4 + Driver Enable de-assertion time + 20 + 1 + + + DEDT3 + DEDT3 + 19 + 1 + + + DEDT2 + DEDT2 + 18 + 1 + + + DEDT1 + DEDT1 + 17 + 1 + + + DEDT0 + DEDT0 + 16 + 1 + + + CMIE + Character match interrupt enable + 14 + 1 + + + MME + Mute mode enable + 13 + 1 + + + M0 + Word length + 12 + 1 + + + WAKE + Receiver wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXEIE + interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt enable + 6 + 1 + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + UESM + USART enable in Stop mode + 1 + 1 + + + UE + USART enable + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + ADD4_7 + Address of the USART node + 28 + 4 + + + ADD0_3 + Address of the USART node + 24 + 4 + + + MSBFIRST + Most significant bit first + 19 + 1 + + + TAINV + Binary data inversion + 18 + 1 + + + TXINV + TX pin active level inversion + 17 + 1 + + + RXINV + RX pin active level inversion + 16 + 1 + + + SWAP + Swap TX/RX pins + 15 + 1 + + + STOP + STOP bits + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + ADDM7 + 7-bit Address Detection/4-bit Address Detection + 4 + 1 + + + + + CR3 + CR3 + Control register 3 + 0x8 + 0x20 + read-write + 0x00000000 + + + WUFIE + Wakeup from Stop mode interrupt enable + 22 + 1 + + + WUS + Wakeup from Stop mode interrupt flag selection + 20 + 2 + + + DEP + Driver enable polarity selection + 15 + 1 + + + DEM + Driver enable mode + 14 + 1 + + + DDRE + DMA Disable on Reception Error + 13 + 1 + + + OVRDIS + Overrun Disable + 12 + 1 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSE + CTS enable + 9 + 1 + + + RTSE + RTS enable + 8 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + DMAR + DMA enable receiver + 6 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + UCESM_ + LPUART Clock Enable in Stop mode + 23 + 1 + + + + + BRR + BRR + Baud rate register + 0xC + 0x20 + read-write + 0x00000000 + + + BRR + BRR + 0 + 20 + + + + + RQR + RQR + Request register + 0x18 + 0x20 + write-only + 0x00000000 + + + RXFRQ + Receive data flush request + 3 + 1 + + + MMRQ + Mute mode request + 2 + 1 + + + SBKRQ + Send break request + 1 + 1 + + + + + ISR + ISR + Interrupt & status register + 0x1C + 0x20 + read-only + 0x020000C0 + + + REACK + REACK + 22 + 1 + + + TEACK + TEACK + 21 + 1 + + + WUF + WUF + 20 + 1 + + + RWU + RWU + 19 + 1 + + + SBKF + SBKF + 18 + 1 + + + CMF + CMF + 17 + 1 + + + BUSY + BUSY + 16 + 1 + + + CTS + CTS + 10 + 1 + + + CTSIF + CTSIF + 9 + 1 + + + TXE + TXE + 7 + 1 + + + TC + TC + 6 + 1 + + + RXNE + RXNE + 5 + 1 + + + IDLE + IDLE + 4 + 1 + + + ORE + ORE + 3 + 1 + + + NF + NF + 2 + 1 + + + FE + FE + 1 + 1 + + + PE + PE + 0 + 1 + + + + + ICR + ICR + Interrupt flag clear register + 0x20 + 0x20 + write-only + 0x00000000 + + + WUCF + Wakeup from Stop mode clear flag + 20 + 1 + + + CMCF + Character match clear flag + 17 + 1 + + + CTSCF + CTS clear flag + 9 + 1 + + + TCCF + Transmission complete clear flag + 6 + 1 + + + IDLECF + Idle line detected clear flag + 4 + 1 + + + ORECF + Overrun error clear flag + 3 + 1 + + + NCF + Noise detected clear flag + 2 + 1 + + + FECF + Framing error clear flag + 1 + 1 + + + PECF + Parity error clear flag + 0 + 1 + + + + + RDR + RDR + Receive data register + 0x24 + 0x20 + read-only + 0x00000000 + + + RDR + Receive data value + 0 + 9 + + + + + TDR + TDR + Transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + + + TDR + Transmit data value + 0 + 9 + + + + + + + SPI1 + Serial peripheral interface/Inter-IC sound + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global interrupt + 35 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + BIDIMODE + Bidirectional data mode enable + 15 + 1 + + + BIDIOE + Output enable in bidirectional mode + 14 + 1 + + + CRCEN + Hardware CRC calculation enable + 13 + 1 + + + CRCNEXT + CRC transfer next + 12 + 1 + + + DFF + Data frame format + 11 + 1 + + + RXONLY + Receive only + 10 + 1 + + + SSM + Software slave management + 9 + 1 + + + SSI + Internal slave select + 8 + 1 + + + LSBFIRST + Frame format + 7 + 1 + + + SPE + SPI enable + 6 + 1 + + + BR + Baud rate control + 3 + 3 + + + MSTR + Master selection + 2 + 1 + + + CPOL + Clock polarity + 1 + 1 + + + CPHA + Clock phase + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + RXDMAEN + Rx buffer DMA enable + 0 + 1 + + + TXDMAEN + Tx buffer DMA enable + 1 + 1 + + + SSOE + SS output enable + 2 + 1 + + + NSSP + NSS pulse management + 3 + 1 + + + FRF + Frame format + 4 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + RXNEIE + RX buffer not empty interrupt enable + 6 + 1 + + + TXEIE + Tx buffer empty interrupt enable + 7 + 1 + + + DS + Data size + 8 + 4 + + + FRXTH + FIFO reception threshold + 12 + 1 + + + LDMA_RX + Last DMA transfer for reception + 13 + 1 + + + LDMA_TX + Last DMA transfer for transmission + 14 + 1 + + + + + SR + SR + status register + 0x8 + 0x20 + 0x0002 + + + RXNE + Receive buffer not empty + 0 + 1 + read-only + + + TXE + Transmit buffer empty + 1 + 1 + read-only + + + CRCERR + CRC error flag + 4 + 1 + read-write + + + MODF + Mode fault + 5 + 1 + read-only + + + OVR + Overrun flag + 6 + 1 + read-only + + + BSY + Busy flag + 7 + 1 + read-only + + + TIFRFE + TI frame format error + 8 + 1 + read-only + + + FRLVL + FIFO reception level + 9 + 2 + read-only + + + FTLVL + FIFO transmission level + 11 + 2 + read-only + + + + + DR + DR + data register + 0xC + 0x20 + read-write + 0x0000 + + + DR + Data register + 0 + 16 + + + + + CRCPR + CRCPR + CRC polynomial register + 0x10 + 0x20 + read-write + 0x0007 + + + CRCPOLY + CRC polynomial register + 0 + 16 + + + + + RXCRCR + RXCRCR + RX CRC register + 0x14 + 0x20 + read-only + 0x0000 + + + RxCRC + Rx CRC register + 0 + 16 + + + + + TXCRCR + TXCRCR + TX CRC register + 0x18 + 0x20 + read-only + 0x0000 + + + TxCRC + Tx CRC register + 0 + 16 + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global interrupt + 36 + + + + SPI3 + 0x40003C00 + + SPI3 + SPI3 global Interrupt + 51 + + + + SDMMC1 + Secure digital input/output interface + SDIO + 0x40012800 + + 0x0 + 0x400 + registers + + + SDMMC1 + SDMMC global Interrupt + 49 + + + + POWER + POWER + power control register + 0x0 + 0x20 + read-write + 0x00000000 + + + PWRCTRL + PWRCTRL + 0 + 2 + + + + + CLKCR + CLKCR + SDI clock control register + 0x4 + 0x20 + read-write + 0x00000000 + + + HWFC_EN + HW Flow Control enable + 14 + 1 + + + NEGEDGE + SDIO_CK dephasing selection bit + 13 + 1 + + + WIDBUS + Wide bus mode enable bit + 11 + 2 + + + BYPASS + Clock divider bypass enable bit + 10 + 1 + + + PWRSAV + Power saving configuration bit + 9 + 1 + + + CLKEN + Clock enable bit + 8 + 1 + + + CLKDIV + Clock divide factor + 0 + 8 + + + + + ARG + ARG + argument register + 0x8 + 0x20 + read-write + 0x00000000 + + + CMDARG + Command argument + 0 + 32 + + + + + CMD + CMD + command register + 0xC + 0x20 + read-write + 0x00000000 + + + CE_ATACMD + CE-ATA command + 14 + 1 + + + nIEN + not Interrupt Enable + 13 + 1 + + + ENCMDcompl + Enable CMD completion + 12 + 1 + + + SDIOSuspend + SD I/O suspend command + 11 + 1 + + + CPSMEN + Command path state machine (CPSM) Enable bit + 10 + 1 + + + WAITPEND + CPSM Waits for ends of data transfer (CmdPend internal signal) + 9 + 1 + + + WAITINT + CPSM waits for interrupt request + 8 + 1 + + + WAITRESP + Wait for response bits + 6 + 2 + + + CMDINDEX + Command index + 0 + 6 + + + + + RESPCMD + RESPCMD + command response register + 0x10 + 0x20 + read-only + 0x00000000 + + + RESPCMD + Response command index + 0 + 6 + + + + + RESP1 + RESP1 + response 1..4 register + 0x14 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS1 + see Table 132 + 0 + 32 + + + + + RESP2 + RESP2 + response 1..4 register + 0x18 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS2 + see Table 132 + 0 + 32 + + + + + RESP3 + RESP3 + response 1..4 register + 0x1C + 0x20 + read-only + 0x00000000 + + + CARDSTATUS3 + see Table 132 + 0 + 32 + + + + + RESP4 + RESP4 + response 1..4 register + 0x20 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS4 + see Table 132 + 0 + 32 + + + + + DTIMER + DTIMER + data timer register + 0x24 + 0x20 + read-write + 0x00000000 + + + DATATIME + Data timeout period + 0 + 32 + + + + + DLEN + DLEN + data length register + 0x28 + 0x20 + read-write + 0x00000000 + + + DATALENGTH + Data length value + 0 + 25 + + + + + DCTRL + DCTRL + data control register + 0x2C + 0x20 + read-write + 0x00000000 + + + SDIOEN + SD I/O enable functions + 11 + 1 + + + RWMOD + Read wait mode + 10 + 1 + + + RWSTOP + Read wait stop + 9 + 1 + + + RWSTART + Read wait start + 8 + 1 + + + DBLOCKSIZE + Data block size + 4 + 4 + + + DMAEN + DMA enable bit + 3 + 1 + + + DTMODE + Data transfer mode selection 1: Stream or SDIO multibyte data transfer + 2 + 1 + + + DTDIR + Data transfer direction selection + 1 + 1 + + + DTEN + DTEN + 0 + 1 + + + + + DCOUNT + DCOUNT + data counter register + 0x30 + 0x20 + read-only + 0x00000000 + + + DATACOUNT + Data count value + 0 + 25 + + + + + STA + STA + status register + 0x34 + 0x20 + read-only + 0x00000000 + + + CEATAEND + CE-ATA command completion signal received for CMD61 + 23 + 1 + + + SDIOIT + SDIO interrupt received + 22 + 1 + + + RXDAVL + Data available in receive FIFO + 21 + 1 + + + TXDAVL + Data available in transmit FIFO + 20 + 1 + + + RXFIFOE + Receive FIFO empty + 19 + 1 + + + TXFIFOE + Transmit FIFO empty + 18 + 1 + + + RXFIFOF + Receive FIFO full + 17 + 1 + + + TXFIFOF + Transmit FIFO full + 16 + 1 + + + RXFIFOHF + Receive FIFO half full: there are at least 8 words in the FIFO + 15 + 1 + + + TXFIFOHE + Transmit FIFO half empty: at least 8 words can be written into the FIFO + 14 + 1 + + + RXACT + Data receive in progress + 13 + 1 + + + TXACT + Data transmit in progress + 12 + 1 + + + CMDACT + Command transfer in progress + 11 + 1 + + + DBCKEND + Data block sent/received (CRC check passed) + 10 + 1 + + + STBITERR + Start bit not detected on all data signals in wide bus mode + 9 + 1 + + + DATAEND + Data end (data counter, SDIDCOUNT, is zero) + 8 + 1 + + + CMDSENT + Command sent (no response required) + 7 + 1 + + + CMDREND + Command response received (CRC check passed) + 6 + 1 + + + RXOVERR + Received FIFO overrun error + 5 + 1 + + + TXUNDERR + Transmit FIFO underrun error + 4 + 1 + + + DTIMEOUT + Data timeout + 3 + 1 + + + CTIMEOUT + Command response timeout + 2 + 1 + + + DCRCFAIL + Data block sent/received (CRC check failed) + 1 + 1 + + + CCRCFAIL + Command response received (CRC check failed) + 0 + 1 + + + + + ICR + ICR + interrupt clear register + 0x38 + 0x20 + read-write + 0x00000000 + + + CEATAENDC + CEATAEND flag clear bit + 23 + 1 + + + SDIOITC + SDIOIT flag clear bit + 22 + 1 + + + DBCKENDC + DBCKEND flag clear bit + 10 + 1 + + + STBITERRC + STBITERR flag clear bit + 9 + 1 + + + DATAENDC + DATAEND flag clear bit + 8 + 1 + + + CMDSENTC + CMDSENT flag clear bit + 7 + 1 + + + CMDRENDC + CMDREND flag clear bit + 6 + 1 + + + RXOVERRC + RXOVERR flag clear bit + 5 + 1 + + + TXUNDERRC + TXUNDERR flag clear bit + 4 + 1 + + + DTIMEOUTC + DTIMEOUT flag clear bit + 3 + 1 + + + CTIMEOUTC + CTIMEOUT flag clear bit + 2 + 1 + + + DCRCFAILC + DCRCFAIL flag clear bit + 1 + 1 + + + CCRCFAILC + CCRCFAIL flag clear bit + 0 + 1 + + + + + MASK + MASK + mask register + 0x3C + 0x20 + read-write + 0x00000000 + + + CEATAENDIE + CE-ATA command completion signal received interrupt enable + 23 + 1 + + + SDIOITIE + SDIO mode interrupt received interrupt enable + 22 + 1 + + + RXDAVLIE + Data available in Rx FIFO interrupt enable + 21 + 1 + + + TXDAVLIE + Data available in Tx FIFO interrupt enable + 20 + 1 + + + RXFIFOEIE + Rx FIFO empty interrupt enable + 19 + 1 + + + TXFIFOEIE + Tx FIFO empty interrupt enable + 18 + 1 + + + RXFIFOFIE + Rx FIFO full interrupt enable + 17 + 1 + + + TXFIFOFIE + Tx FIFO full interrupt enable + 16 + 1 + + + RXFIFOHFIE + Rx FIFO half full interrupt enable + 15 + 1 + + + TXFIFOHEIE + Tx FIFO half empty interrupt enable + 14 + 1 + + + RXACTIE + Data receive acting interrupt enable + 13 + 1 + + + TXACTIE + Data transmit acting interrupt enable + 12 + 1 + + + CMDACTIE + Command acting interrupt enable + 11 + 1 + + + DBCKENDIE + Data block end interrupt enable + 10 + 1 + + + STBITERRIE + Start bit error interrupt enable + 9 + 1 + + + DATAENDIE + Data end interrupt enable + 8 + 1 + + + CMDSENTIE + Command sent interrupt enable + 7 + 1 + + + CMDRENDIE + Command response received interrupt enable + 6 + 1 + + + RXOVERRIE + Rx FIFO overrun error interrupt enable + 5 + 1 + + + TXUNDERRIE + Tx FIFO underrun error interrupt enable + 4 + 1 + + + DTIMEOUTIE + Data timeout interrupt enable + 3 + 1 + + + CTIMEOUTIE + Command timeout interrupt enable + 2 + 1 + + + DCRCFAILIE + Data CRC fail interrupt enable + 1 + 1 + + + CCRCFAILIE + Command CRC fail interrupt enable + 0 + 1 + + + + + FIFOCNT + FIFOCNT + FIFO counter register + 0x48 + 0x20 + read-only + 0x00000000 + + + FIFOCOUNT + Remaining number of words to be written to or read from the FIFO + 0 + 24 + + + + + FIFO + FIFO + data FIFO register + 0x80 + 0x20 + read-write + 0x00000000 + + + FIFOData + Receive and transmit FIFO data + 0 + 32 + + + + + + + EXTI + External interrupt/event controller + EXTI + 0x40010400 + + 0x0 + 0x400 + registers + + + PVD_PVM + PVD through EXTI line detection + 1 + + + EXTI0 + EXTI Line 0 interrupt + 6 + + + EXTI1 + EXTI Line 1 interrupt + 7 + + + EXTI2 + EXTI Line 2 interrupt + 8 + + + EXTI3 + EXTI Line 3 interrupt + 9 + + + EXTI4 + EXTI Line 4 interrupt + 10 + + + EXTI9_5 + EXTI Line5 to Line9 interrupts + 23 + + + EXTI15_10 + EXTI Lines 10 to 15 interrupts + 40 + + + FPU + Floating point interrupt + 81 + + + + IMR1 + IMR1 + Interrupt mask register + 0x0 + 0x20 + read-write + 0xFF820000 + + + MR0 + Interrupt Mask on line 0 + 0 + 1 + + + MR1 + Interrupt Mask on line 1 + 1 + 1 + + + MR2 + Interrupt Mask on line 2 + 2 + 1 + + + MR3 + Interrupt Mask on line 3 + 3 + 1 + + + MR4 + Interrupt Mask on line 4 + 4 + 1 + + + MR5 + Interrupt Mask on line 5 + 5 + 1 + + + MR6 + Interrupt Mask on line 6 + 6 + 1 + + + MR7 + Interrupt Mask on line 7 + 7 + 1 + + + MR8 + Interrupt Mask on line 8 + 8 + 1 + + + MR9 + Interrupt Mask on line 9 + 9 + 1 + + + MR10 + Interrupt Mask on line 10 + 10 + 1 + + + MR11 + Interrupt Mask on line 11 + 11 + 1 + + + MR12 + Interrupt Mask on line 12 + 12 + 1 + + + MR13 + Interrupt Mask on line 13 + 13 + 1 + + + MR14 + Interrupt Mask on line 14 + 14 + 1 + + + MR15 + Interrupt Mask on line 15 + 15 + 1 + + + MR16 + Interrupt Mask on line 16 + 16 + 1 + + + MR17 + Interrupt Mask on line 17 + 17 + 1 + + + MR18 + Interrupt Mask on line 18 + 18 + 1 + + + MR19 + Interrupt Mask on line 19 + 19 + 1 + + + MR20 + Interrupt Mask on line 20 + 20 + 1 + + + MR21 + Interrupt Mask on line 21 + 21 + 1 + + + MR22 + Interrupt Mask on line 22 + 22 + 1 + + + MR23 + Interrupt Mask on line 23 + 23 + 1 + + + MR24 + Interrupt Mask on line 24 + 24 + 1 + + + MR25 + Interrupt Mask on line 25 + 25 + 1 + + + MR26 + Interrupt Mask on line 26 + 26 + 1 + + + MR27 + Interrupt Mask on line 27 + 27 + 1 + + + MR28 + Interrupt Mask on line 28 + 28 + 1 + + + MR29 + Interrupt Mask on line 29 + 29 + 1 + + + MR30 + Interrupt Mask on line 30 + 30 + 1 + + + MR31 + Interrupt Mask on line 31 + 31 + 1 + + + + + EMR1 + EMR1 + Event mask register + 0x4 + 0x20 + read-write + 0x00000000 + + + MR0 + Event Mask on line 0 + 0 + 1 + + + MR1 + Event Mask on line 1 + 1 + 1 + + + MR2 + Event Mask on line 2 + 2 + 1 + + + MR3 + Event Mask on line 3 + 3 + 1 + + + MR4 + Event Mask on line 4 + 4 + 1 + + + MR5 + Event Mask on line 5 + 5 + 1 + + + MR6 + Event Mask on line 6 + 6 + 1 + + + MR7 + Event Mask on line 7 + 7 + 1 + + + MR8 + Event Mask on line 8 + 8 + 1 + + + MR9 + Event Mask on line 9 + 9 + 1 + + + MR10 + Event Mask on line 10 + 10 + 1 + + + MR11 + Event Mask on line 11 + 11 + 1 + + + MR12 + Event Mask on line 12 + 12 + 1 + + + MR13 + Event Mask on line 13 + 13 + 1 + + + MR14 + Event Mask on line 14 + 14 + 1 + + + MR15 + Event Mask on line 15 + 15 + 1 + + + MR16 + Event Mask on line 16 + 16 + 1 + + + MR17 + Event Mask on line 17 + 17 + 1 + + + MR18 + Event Mask on line 18 + 18 + 1 + + + MR19 + Event Mask on line 19 + 19 + 1 + + + MR20 + Event Mask on line 20 + 20 + 1 + + + MR21 + Event Mask on line 21 + 21 + 1 + + + MR22 + Event Mask on line 22 + 22 + 1 + + + MR23 + Event Mask on line 23 + 23 + 1 + + + MR24 + Event Mask on line 24 + 24 + 1 + + + MR25 + Event Mask on line 25 + 25 + 1 + + + MR26 + Event Mask on line 26 + 26 + 1 + + + MR27 + Event Mask on line 27 + 27 + 1 + + + MR28 + Event Mask on line 28 + 28 + 1 + + + MR29 + Event Mask on line 29 + 29 + 1 + + + MR30 + Event Mask on line 30 + 30 + 1 + + + MR31 + Event Mask on line 31 + 31 + 1 + + + + + RTSR1 + RTSR1 + Rising Trigger selection register + 0x8 + 0x20 + read-write + 0x00000000 + + + TR0 + Rising trigger event configuration of line 0 + 0 + 1 + + + TR1 + Rising trigger event configuration of line 1 + 1 + 1 + + + TR2 + Rising trigger event configuration of line 2 + 2 + 1 + + + TR3 + Rising trigger event configuration of line 3 + 3 + 1 + + + TR4 + Rising trigger event configuration of line 4 + 4 + 1 + + + TR5 + Rising trigger event configuration of line 5 + 5 + 1 + + + TR6 + Rising trigger event configuration of line 6 + 6 + 1 + + + TR7 + Rising trigger event configuration of line 7 + 7 + 1 + + + TR8 + Rising trigger event configuration of line 8 + 8 + 1 + + + TR9 + Rising trigger event configuration of line 9 + 9 + 1 + + + TR10 + Rising trigger event configuration of line 10 + 10 + 1 + + + TR11 + Rising trigger event configuration of line 11 + 11 + 1 + + + TR12 + Rising trigger event configuration of line 12 + 12 + 1 + + + TR13 + Rising trigger event configuration of line 13 + 13 + 1 + + + TR14 + Rising trigger event configuration of line 14 + 14 + 1 + + + TR15 + Rising trigger event configuration of line 15 + 15 + 1 + + + TR16 + Rising trigger event configuration of line 16 + 16 + 1 + + + TR18 + Rising trigger event configuration of line 18 + 18 + 1 + + + TR19 + Rising trigger event configuration of line 19 + 19 + 1 + + + TR20 + Rising trigger event configuration of line 20 + 20 + 1 + + + TR21 + Rising trigger event configuration of line 21 + 21 + 1 + + + TR22 + Rising trigger event configuration of line 22 + 22 + 1 + + + + + FTSR1 + FTSR1 + Falling Trigger selection register + 0xC + 0x20 + read-write + 0x00000000 + + + TR0 + Falling trigger event configuration of line 0 + 0 + 1 + + + TR1 + Falling trigger event configuration of line 1 + 1 + 1 + + + TR2 + Falling trigger event configuration of line 2 + 2 + 1 + + + TR3 + Falling trigger event configuration of line 3 + 3 + 1 + + + TR4 + Falling trigger event configuration of line 4 + 4 + 1 + + + TR5 + Falling trigger event configuration of line 5 + 5 + 1 + + + TR6 + Falling trigger event configuration of line 6 + 6 + 1 + + + TR7 + Falling trigger event configuration of line 7 + 7 + 1 + + + TR8 + Falling trigger event configuration of line 8 + 8 + 1 + + + TR9 + Falling trigger event configuration of line 9 + 9 + 1 + + + TR10 + Falling trigger event configuration of line 10 + 10 + 1 + + + TR11 + Falling trigger event configuration of line 11 + 11 + 1 + + + TR12 + Falling trigger event configuration of line 12 + 12 + 1 + + + TR13 + Falling trigger event configuration of line 13 + 13 + 1 + + + TR14 + Falling trigger event configuration of line 14 + 14 + 1 + + + TR15 + Falling trigger event configuration of line 15 + 15 + 1 + + + TR16 + Falling trigger event configuration of line 16 + 16 + 1 + + + TR18 + Falling trigger event configuration of line 18 + 18 + 1 + + + TR19 + Falling trigger event configuration of line 19 + 19 + 1 + + + TR20 + Falling trigger event configuration of line 20 + 20 + 1 + + + TR21 + Falling trigger event configuration of line 21 + 21 + 1 + + + TR22 + Falling trigger event configuration of line 22 + 22 + 1 + + + + + SWIER1 + SWIER1 + Software interrupt event register + 0x10 + 0x20 + read-write + 0x00000000 + + + SWIER0 + Software Interrupt on line 0 + 0 + 1 + + + SWIER1 + Software Interrupt on line 1 + 1 + 1 + + + SWIER2 + Software Interrupt on line 2 + 2 + 1 + + + SWIER3 + Software Interrupt on line 3 + 3 + 1 + + + SWIER4 + Software Interrupt on line 4 + 4 + 1 + + + SWIER5 + Software Interrupt on line 5 + 5 + 1 + + + SWIER6 + Software Interrupt on line 6 + 6 + 1 + + + SWIER7 + Software Interrupt on line 7 + 7 + 1 + + + SWIER8 + Software Interrupt on line 8 + 8 + 1 + + + SWIER9 + Software Interrupt on line 9 + 9 + 1 + + + SWIER10 + Software Interrupt on line 10 + 10 + 1 + + + SWIER11 + Software Interrupt on line 11 + 11 + 1 + + + SWIER12 + Software Interrupt on line 12 + 12 + 1 + + + SWIER13 + Software Interrupt on line 13 + 13 + 1 + + + SWIER14 + Software Interrupt on line 14 + 14 + 1 + + + SWIER15 + Software Interrupt on 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bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F27R1 + F27R1 + Filter bank 27 register 1 + 0x318 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F27R2 + F27R2 + Filter bank 27 register 2 + 0x31C + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + + + RTC + Real-time clock + RTC + 0x40002800 + + 0x0 + 0x400 + registers + + + TAMP_STAMP + Tamper and TimeStamp interrupts + 2 + + + RTC_WKUP + RTC Tamper or TimeStamp /CSS on LSE through + EXTI line 19 interrupts + 3 + + + RTC_ALARM + RTC alarms through EXTI line 18 + interrupts + 41 + + + + TR + TR + time register + 0x0 + 0x20 + read-write + 0x00000000 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + DR + DR + date register + 0x4 + 0x20 + read-write + 0x00002101 + + + YT + Year tens in BCD format + 20 + 4 + + + YU + Year units in BCD format + 16 + 4 + + + WDU + Week day units + 13 + 3 + + + MT + Month tens in BCD format + 12 + 1 + + + MU + Month units in BCD format + 8 + 4 + + + DT + Date tens in BCD format + 4 + 2 + + + DU + Date units in BCD format + 0 + 4 + + + + + CR + CR + control register + 0x8 + 0x20 + read-write + 0x00000000 + + + WCKSEL + Wakeup clock selection + 0 + 3 + + + TSEDGE + Time-stamp event active edge + 3 + 1 + + + REFCKON + Reference clock detection enable (50 or 60 Hz) + 4 + 1 + + + BYPSHAD + Bypass the shadow registers + 5 + 1 + + + FMT + Hour format + 6 + 1 + + + ALRAE + Alarm A enable + 8 + 1 + + + ALRBE + Alarm B enable + 9 + 1 + + + WUTE + Wakeup timer enable + 10 + 1 + + + TSE + Time stamp enable + 11 + 1 + + + ALRAIE + Alarm A interrupt enable + 12 + 1 + + + ALRBIE + Alarm B interrupt enable + 13 + 1 + + + WUTIE + Wakeup timer interrupt enable + 14 + 1 + + + TSIE + Time-stamp interrupt enable + 15 + 1 + + + ADD1H + Add 1 hour (summer time change) + 16 + 1 + + + SUB1H + Subtract 1 hour (winter time change) + 17 + 1 + + + BKP + Backup + 18 + 1 + + + COSEL + Calibration output selection + 19 + 1 + + + POL + Output polarity + 20 + 1 + + + OSEL + Output selection + 21 + 2 + + + COE + Calibration output enable + 23 + 1 + + + ITSE + timestamp on internal event enable + 24 + 1 + + + + + ISR + ISR + initialization and status register + 0xC + 0x20 + 0x00000007 + + + ALRAWF + Alarm A write flag + 0 + 1 + read-only + + + ALRBWF + Alarm B write flag + 1 + 1 + read-only + + + WUTWF + Wakeup timer write flag + 2 + 1 + read-only + + + SHPF + Shift operation pending + 3 + 1 + read-write + + + INITS + Initialization status flag + 4 + 1 + read-only + + + RSF + Registers synchronization flag + 5 + 1 + read-write + + + INITF + Initialization flag + 6 + 1 + read-only + + + INIT + Initialization mode + 7 + 1 + read-write + + + ALRAF + Alarm A flag + 8 + 1 + read-write + + + ALRBF + Alarm B flag + 9 + 1 + read-write + + + WUTF + Wakeup timer flag + 10 + 1 + read-write + + + TSF + Time-stamp flag + 11 + 1 + read-write + + + TSOVF + Time-stamp overflow flag + 12 + 1 + read-write + + + TAMP1F + Tamper detection flag + 13 + 1 + read-write + + + TAMP2F + RTC_TAMP2 detection flag + 14 + 1 + read-write + + + TAMP3F + RTC_TAMP3 detection flag + 15 + 1 + read-write + + + RECALPF + Recalibration pending Flag + 16 + 1 + read-only + + + + + PRER + PRER + prescaler register + 0x10 + 0x20 + read-write + 0x007F00FF + + + PREDIV_A + Asynchronous prescaler factor + 16 + 7 + + + PREDIV_S + Synchronous prescaler factor + 0 + 15 + + + + + WUTR + WUTR + wakeup timer register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + WUT + Wakeup auto-reload value bits + 0 + 16 + + + + + ALRMAR + ALRMAR + alarm A register + 0x1C + 0x20 + read-write + 0x00000000 + + + MSK4 + Alarm A date mask + 31 + 1 + + + WDSEL + Week day selection + 30 + 1 + + + DT + Date tens in BCD format + 28 + 2 + + + DU + Date units or day in BCD format + 24 + 4 + + + MSK3 + Alarm A hours mask + 23 + 1 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MSK2 + Alarm A minutes mask + 15 + 1 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + MSK1 + Alarm A seconds mask + 7 + 1 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + ALRMBR + ALRMBR + alarm B register + 0x20 + 0x20 + read-write + 0x00000000 + + + MSK4 + Alarm B date mask + 31 + 1 + + + WDSEL + Week day selection + 30 + 1 + + + DT + Date tens in BCD format + 28 + 2 + + + DU + Date units or day in BCD format + 24 + 4 + + + MSK3 + Alarm B hours mask + 23 + 1 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MSK2 + Alarm B minutes mask + 15 + 1 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + MSK1 + Alarm B seconds mask + 7 + 1 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + WPR + WPR + write protection register + 0x24 + 0x20 + write-only + 0x00000000 + + + KEY + Write protection key + 0 + 8 + + + + + SSR + SSR + sub second register + 0x28 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value + 0 + 16 + + + + + SHIFTR + SHIFTR + shift control register + 0x2C + 0x20 + write-only + 0x00000000 + + + ADD1S + Add one second + 31 + 1 + + + SUBFS + Subtract a fraction of a second + 0 + 15 + + + + + TSTR + TSTR + time stamp time register + 0x30 + 0x20 + read-only + 0x00000000 + + + SU + Second units in BCD format + 0 + 4 + + + ST + Second tens in BCD format + 4 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + MNT + Minute tens in BCD format + 12 + 3 + + + HU + Hour units in BCD format + 16 + 4 + + + HT + Hour tens in BCD format + 20 + 2 + + + PM + AM/PM notation + 22 + 1 + + + + + TSDR + TSDR + time stamp date register + 0x34 + 0x20 + read-only + 0x00000000 + + + WDU + Week day units + 13 + 3 + + + MT + Month tens in BCD format + 12 + 1 + + + MU + Month units in BCD format + 8 + 4 + + + DT + Date tens in BCD format + 4 + 2 + + + DU + Date units in BCD format + 0 + 4 + + + + + TSSSR + TSSSR + timestamp sub second register + 0x38 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value + 0 + 16 + + + + + CALR + CALR + calibration register + 0x3C + 0x20 + read-write + 0x00000000 + + + CALP + Increase frequency of RTC by 488.5 ppm + 15 + 1 + + + CALW8 + Use an 8-second calibration cycle period + 14 + 1 + + + CALW16 + Use a 16-second calibration cycle period + 13 + 1 + + + CALM + Calibration minus + 0 + 9 + + + + + TAMPCR + TAMPCR + tamper configuration register + 0x40 + 0x20 + read-write + 0x00000000 + + + TAMP1E + Tamper 1 detection enable + 0 + 1 + + + TAMP1TRG + Active level for tamper 1 + 1 + 1 + + + TAMPIE + Tamper interrupt enable + 2 + 1 + + + TAMP2E + Tamper 2 detection enable + 3 + 1 + + + TAMP2TRG + Active level for tamper 2 + 4 + 1 + + + TAMP3E + Tamper 3 detection enable + 5 + 1 + + + TAMP3TRG + Active level for tamper 3 + 6 + 1 + + + TAMPTS + Activate timestamp on tamper detection event + 7 + 1 + + + TAMPFREQ + Tamper sampling frequency + 8 + 3 + + + TAMPFLT + Tamper filter count + 11 + 2 + + + TAMPPRCH + Tamper precharge duration + 13 + 2 + + + TAMPPUDIS + TAMPER pull-up disable + 15 + 1 + + + TAMP1IE + Tamper 1 interrupt enable + 16 + 1 + + + TAMP1NOERASE + Tamper 1 no erase + 17 + 1 + + + TAMP1MF + Tamper 1 mask flag + 18 + 1 + + + TAMP2IE + Tamper 2 interrupt enable + 19 + 1 + + + TAMP2NOERASE + Tamper 2 no erase + 20 + 1 + + + TAMP2MF + Tamper 2 mask flag + 21 + 1 + + + TAMP3IE + Tamper 3 interrupt enable + 22 + 1 + + + TAMP3NOERASE + Tamper 3 no erase + 23 + 1 + + + TAMP3MF + Tamper 3 mask flag + 24 + 1 + + + + + ALRMASSR + ALRMASSR + alarm A sub second register + 0x44 + 0x20 + read-write + 0x00000000 + + + MASKSS + Mask the most-significant bits starting at this bit + 24 + 4 + + + SS + Sub seconds value + 0 + 15 + + + + + ALRMBSSR + ALRMBSSR + alarm B sub second register + 0x48 + 0x20 + read-write + 0x00000000 + + + MASKSS + Mask the most-significant bits starting at this bit + 24 + 4 + + + SS + Sub seconds value + 0 + 15 + + + + + OR + OR + option register + 0x4C + 0x20 + read-write + 0x00000000 + + + RTC_ALARM_TYPE + RTC_ALARM on PC13 output type + 0 + 1 + + + RTC_OUT_RMP + RTC_OUT remap + 1 + 1 + + + + + BKP0R + BKP0R + backup register + 0x50 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP1R + BKP1R + backup register + 0x54 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP2R + BKP2R + backup register + 0x58 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP3R + BKP3R + backup register + 0x5C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP4R + BKP4R + backup register + 0x60 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP5R + BKP5R + backup register + 0x64 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP6R + BKP6R + backup register + 0x68 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP7R + BKP7R + backup register + 0x6C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP8R + BKP8R + backup register + 0x70 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP9R + BKP9R + backup register + 0x74 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP10R + BKP10R + backup register + 0x78 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP11R + BKP11R + backup register + 0x7C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP12R + BKP12R + backup register + 0x80 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP13R + BKP13R + backup register + 0x84 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP14R + BKP14R + backup register + 0x88 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP15R + BKP15R + backup register + 0x8C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP16R + BKP16R + backup register + 0x90 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP17R + BKP17R + backup register + 0x94 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP18R + BKP18R + backup register + 0x98 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP19R + BKP19R + backup register + 0x9C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP20R + BKP20R + backup register + 0xA0 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP21R + BKP21R + backup register + 0xA4 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP22R + BKP22R + backup register + 0xA8 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP23R + BKP23R + backup register + 0xAC + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP24R + BKP24R + backup register + 0xB0 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP25R + BKP25R + backup register + 0xB4 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP26R + BKP26R + backup register + 0xB8 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP27R + BKP27R + backup register + 0xBC + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP28R + BKP28R + backup register + 0xC0 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP29R + BKP29R + backup register + 0xC4 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP30R + BKP30R + backup register + 0xC8 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP31R + BKP31R + backup register + 0xCC + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + + + OTG_FS_GLOBAL + USB on the go full speed + USB_OTG_FS + 0x50000000 + + 0x0 + 0x400 + registers + + + OTG_FS + USB OTG FS global Interrupt + 67 + + + + FS_GOTGCTL + FS_GOTGCTL + OTG_FS control and status register (OTG_FS_GOTGCTL) + 0x0 + 0x20 + 0x00000800 + + + SRQSCS + Session request success + 0 + 1 + read-only + + + SRQ + Session request + 1 + 1 + read-write + + + HNGSCS + Host negotiation success + 8 + 1 + read-only + + + HNPRQ + HNP request + 9 + 1 + read-write + + + HSHNPEN + Host set HNP enable + 10 + 1 + read-write + + + DHNPEN + Device HNP enabled + 11 + 1 + read-write + + + CIDSTS + Connector ID status + 16 + 1 + read-only + + + DBCT + Long/short debounce time + 17 + 1 + read-only + + + ASVLD + A-session valid + 18 + 1 + read-only + + + BSVLD + B-session valid + 19 + 1 + read-only + + + + + FS_GOTGINT + FS_GOTGINT + OTG_FS interrupt register (OTG_FS_GOTGINT) + 0x4 + 0x20 + read-write + 0x00000000 + + + SEDET + Session end detected + 2 + 1 + + + SRSSCHG + Session request success status change + 8 + 1 + + + HNSSCHG + Host negotiation success status change + 9 + 1 + + + HNGDET + Host negotiation detected + 17 + 1 + + + ADTOCHG + A-device timeout change + 18 + 1 + + + DBCDNE + Debounce done + 19 + 1 + + + + + FS_GAHBCFG + FS_GAHBCFG + OTG_FS AHB configuration register (OTG_FS_GAHBCFG) + 0x8 + 0x20 + read-write + 0x00000000 + + + GINT + Global interrupt mask + 0 + 1 + + + TXFELVL + TxFIFO empty level + 7 + 1 + + + PTXFELVL + Periodic TxFIFO empty level + 8 + 1 + + + + + FS_GUSBCFG + FS_GUSBCFG + OTG_FS USB configuration register (OTG_FS_GUSBCFG) + 0xC + 0x20 + 0x00000A00 + + + TOCAL + FS timeout calibration + 0 + 3 + read-write + + + PHYSEL + Full Speed serial transceiver select + 6 + 1 + write-only + + + SRPCAP + SRP-capable + 8 + 1 + read-write + + + HNPCAP + HNP-capable + 9 + 1 + read-write + + + TRDT + USB turnaround time + 10 + 4 + read-write + + + FHMOD + Force host mode + 29 + 1 + read-write + + + FDMOD + Force device mode + 30 + 1 + read-write + + + CTXPKT + Corrupt Tx packet + 31 + 1 + read-write + + + + + FS_GRSTCTL + FS_GRSTCTL + OTG_FS reset register (OTG_FS_GRSTCTL) + 0x10 + 0x20 + 0x20000000 + + + CSRST + Core soft reset + 0 + 1 + read-write + + + HSRST + HCLK soft reset + 1 + 1 + read-write + + + FCRST + Host frame counter reset + 2 + 1 + read-write + + + RXFFLSH + RxFIFO flush + 4 + 1 + read-write + + + TXFFLSH + TxFIFO flush + 5 + 1 + read-write + + + TXFNUM + TxFIFO number + 6 + 5 + read-write + + + AHBIDL + AHB master idle + 31 + 1 + read-only + + + + + FS_GINTSTS + FS_GINTSTS + OTG_FS core interrupt register (OTG_FS_GINTSTS) + 0x14 + 0x20 + 0x04000020 + + + CMOD + Current mode of operation + 0 + 1 + read-only + + + MMIS + Mode mismatch interrupt + 1 + 1 + read-write + + + OTGINT + OTG interrupt + 2 + 1 + read-only + + + SOF + Start of frame + 3 + 1 + read-write + + + RXFLVL + RxFIFO non-empty + 4 + 1 + read-only + + + NPTXFE + Non-periodic TxFIFO empty + 5 + 1 + read-only + + + GINAKEFF + Global IN non-periodic NAK effective + 6 + 1 + read-only + + + GOUTNAKEFF + Global OUT NAK effective + 7 + 1 + read-only + + + ESUSP + Early suspend + 10 + 1 + read-write + + + USBSUSP + USB suspend + 11 + 1 + read-write + + + USBRST + USB reset + 12 + 1 + read-write + + + ENUMDNE + Enumeration done + 13 + 1 + read-write + + + ISOODRP + Isochronous OUT packet dropped interrupt + 14 + 1 + read-write + + + EOPF + End of periodic frame interrupt + 15 + 1 + read-write + + + IEPINT + IN endpoint interrupt + 18 + 1 + read-only + + + OEPINT + OUT endpoint interrupt + 19 + 1 + read-only + + + IISOIXFR + Incomplete isochronous IN transfer + 20 + 1 + read-write + + + IPXFR_INCOMPISOOUT + Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode) + 21 + 1 + read-write + + + HPRTINT + Host port interrupt + 24 + 1 + read-only + + + HCINT + Host channels interrupt + 25 + 1 + read-only + + + PTXFE + Periodic TxFIFO empty + 26 + 1 + read-only + + + CIDSCHG + Connector ID status change + 28 + 1 + read-write + + + DISCINT + Disconnect detected interrupt + 29 + 1 + read-write + + + SRQINT + Session request/new session detected interrupt + 30 + 1 + read-write + + + WKUPINT + Resume/remote wakeup detected interrupt + 31 + 1 + read-write + + + + + FS_GINTMSK + FS_GINTMSK + OTG_FS interrupt mask register (OTG_FS_GINTMSK) + 0x18 + 0x20 + 0x00000000 + + + MMISM + Mode mismatch interrupt mask + 1 + 1 + read-write + + + OTGINT + OTG interrupt mask + 2 + 1 + read-write + + + SOFM + Start of frame mask + 3 + 1 + read-write + + + RXFLVLM + Receive FIFO non-empty mask + 4 + 1 + read-write + + + NPTXFEM + Non-periodic TxFIFO empty mask + 5 + 1 + read-write + + + GINAKEFFM + Global non-periodic IN NAK effective mask + 6 + 1 + read-write + + + GONAKEFFM + Global OUT NAK effective mask + 7 + 1 + read-write + + + ESUSPM + Early suspend mask + 10 + 1 + read-write + + + USBSUSPM + USB suspend mask + 11 + 1 + read-write + + + USBRST + USB reset mask + 12 + 1 + read-write + + + ENUMDNEM + Enumeration done mask + 13 + 1 + read-write + + + ISOODRPM + Isochronous OUT packet dropped interrupt mask + 14 + 1 + read-write + + + EOPFM + End of periodic frame interrupt mask + 15 + 1 + read-write + + + EPMISM + Endpoint mismatch interrupt mask + 17 + 1 + read-write + + + IEPINT + IN endpoints interrupt mask + 18 + 1 + read-write + + + OEPINT + OUT endpoints interrupt mask + 19 + 1 + read-write + + + IISOIXFRM + Incomplete isochronous IN transfer mask + 20 + 1 + read-write + + + IPXFRM_IISOOXFRM + Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode) + 21 + 1 + read-write + + + PRTIM + Host port interrupt mask + 24 + 1 + read-only + + + HCIM + Host channels interrupt mask + 25 + 1 + read-write + + + PTXFEM + Periodic TxFIFO empty mask + 26 + 1 + read-write + + + CIDSCHGM + Connector ID status change mask + 28 + 1 + read-write + + + DISCINT + Disconnect detected interrupt mask + 29 + 1 + read-write + + + SRQIM + Session request/new session detected interrupt mask + 30 + 1 + read-write + + + WUIM + Resume/remote wakeup detected interrupt mask + 31 + 1 + read-write + + + + + FS_GRXSTSR_Device + FS_GRXSTSR_Device + OTG_FS Receive status debug read(Device mode) + 0x1C + 0x20 + read-only + 0x00000000 + + + EPNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FRMNUM + Frame number + 21 + 4 + + + + + FS_GRXSTSR_Host + FS_GRXSTSR_Host + OTG_FS Receive status debug read(Host mode) + FS_GRXSTSR_Device + 0x1C + 0x20 + read-only + 0x00000000 + + + EPNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FRMNUM + Frame number + 21 + 4 + + + + + FS_GRXFSIZ + FS_GRXFSIZ + OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ) + 0x24 + 0x20 + read-write + 0x00000200 + + + RXFD + RxFIFO depth + 0 + 16 + + + + + FS_GNPTXFSIZ_Device + FS_GNPTXFSIZ_Device + OTG_FS non-periodic transmit FIFO size register (Device mode) + 0x28 + 0x20 + read-write + 0x00000200 + + + TX0FSA + Endpoint 0 transmit RAM start address + 0 + 16 + + + TX0FD + Endpoint 0 TxFIFO depth + 16 + 16 + + + + + FS_GNPTXFSIZ_Host + FS_GNPTXFSIZ_Host + OTG_FS non-periodic transmit FIFO size register (Host mode) + FS_GNPTXFSIZ_Device + 0x28 + 0x20 + read-write + 0x00000200 + + + NPTXFSA + Non-periodic transmit RAM start address + 0 + 16 + + + NPTXFD + Non-periodic TxFIFO depth + 16 + 16 + + + + + FS_GNPTXSTS + FS_GNPTXSTS + OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS) + 0x2C + 0x20 + read-only + 0x00080200 + + + NPTXFSAV + Non-periodic TxFIFO space available + 0 + 16 + + + NPTQXSAV + Non-periodic transmit request queue space available + 16 + 8 + + + NPTXQTOP + Top of the non-periodic transmit request queue + 24 + 7 + + + + + FS_GCCFG + FS_GCCFG + OTG_FS general core configuration register (OTG_FS_GCCFG) + 0x38 + 0x20 + read-write + 0x00000000 + + + PWRDWN + Power down + 16 + 1 + + + VBUSASEN + Enable the VBUS sensing device + 18 + 1 + + + VBUSBSEN + Enable the VBUS sensing device + 19 + 1 + + + SOFOUTEN + SOF output enable + 20 + 1 + + + + + FS_CID + FS_CID + core ID register + 0x3C + 0x20 + read-write + 0x00001000 + + + PRODUCT_ID + Product ID field + 0 + 32 + + + + + FS_HPTXFSIZ + FS_HPTXFSIZ + OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ) + 0x100 + 0x20 + read-write + 0x02000600 + + + PTXSA + Host periodic TxFIFO start address + 0 + 16 + + + PTXFSIZ + Host periodic TxFIFO depth + 16 + 16 + + + + + FS_DIEPTXF1 + FS_DIEPTXF1 + OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2) + 0x104 + 0x20 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFO2 transmit RAM start address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + FS_DIEPTXF2 + FS_DIEPTXF2 + OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3) + 0x108 + 0x20 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFO3 transmit RAM start address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + FS_DIEPTXF3 + FS_DIEPTXF3 + OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4) + 0x10C + 0x20 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFO4 transmit RAM start address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + + + OTG_FS_HOST + USB on the go full speed + USB_OTG_FS + 0x50000400 + + 0x0 + 0x400 + registers + + + + FS_HCFG + FS_HCFG + OTG_FS host configuration register (OTG_FS_HCFG) + 0x0 + 0x20 + 0x00000000 + + + FSLSPCS + FS/LS PHY clock select + 0 + 2 + read-write + + + FSLSS + FS- and LS-only support + 2 + 1 + read-only + + + + + HFIR + HFIR + OTG_FS Host frame interval register + 0x4 + 0x20 + read-write + 0x0000EA60 + + + FRIVL + Frame interval + 0 + 16 + + + + + FS_HFNUM + FS_HFNUM + OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM) + 0x8 + 0x20 + read-only + 0x00003FFF + + + FRNUM + Frame number + 0 + 16 + + + FTREM + Frame time remaining + 16 + 16 + + + + + FS_HPTXSTS + FS_HPTXSTS + OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS) + 0x10 + 0x20 + 0x00080100 + + + PTXFSAVL + Periodic transmit data FIFO space available + 0 + 16 + read-write + + + PTXQSAV + Periodic transmit request queue space available + 16 + 8 + read-only + + + PTXQTOP + Top of the periodic transmit request queue + 24 + 8 + read-only + + + + + HAINT + HAINT + OTG_FS Host all channels interrupt register + 0x14 + 0x20 + read-only + 0x00000000 + + + HAINT + Channel interrupts + 0 + 16 + + + + + HAINTMSK + HAINTMSK + OTG_FS host all channels interrupt mask register + 0x18 + 0x20 + read-write + 0x00000000 + + + HAINTM + Channel interrupt mask + 0 + 16 + + + + + FS_HPRT + FS_HPRT + OTG_FS host port control and status register (OTG_FS_HPRT) + 0x40 + 0x20 + 0x00000000 + + + PCSTS + Port connect status + 0 + 1 + read-only + + + PCDET + Port connect detected + 1 + 1 + read-write + + + PENA + Port enable + 2 + 1 + read-write + + + PENCHNG + Port enable/disable change + 3 + 1 + read-write + + + POCA + Port overcurrent active + 4 + 1 + read-only + + + POCCHNG + Port overcurrent change + 5 + 1 + read-write + + + PRES + Port resume + 6 + 1 + read-write + + + PSUSP + Port suspend + 7 + 1 + read-write + + + PRST + Port reset + 8 + 1 + read-write + + + PLSTS + Port line status + 10 + 2 + read-only + + + PPWR + Port power + 12 + 1 + read-write + + + PTCTL + Port test control + 13 + 4 + read-write + + + PSPD + Port speed + 17 + 2 + read-only + + + + + FS_HCCHAR0 + FS_HCCHAR0 + OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0) + 0x100 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR1 + FS_HCCHAR1 + OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1) + 0x120 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR2 + FS_HCCHAR2 + OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2) + 0x140 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR3 + FS_HCCHAR3 + OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3) + 0x160 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR4 + FS_HCCHAR4 + OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4) + 0x180 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR5 + FS_HCCHAR5 + OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5) + 0x1A0 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR6 + FS_HCCHAR6 + OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6) + 0x1C0 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR7 + FS_HCCHAR7 + OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7) + 0x1E0 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCINT0 + FS_HCINT0 + OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0) + 0x108 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received interrupt + 3 + 1 + + + NAK + NAK response received interrupt + 4 + 1 + + + ACK + ACK response received/transmitted interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT1 + FS_HCINT1 + OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1) + 0x128 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received interrupt + 3 + 1 + + + NAK + NAK response received interrupt + 4 + 1 + + + ACK + ACK response received/transmitted interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT2 + FS_HCINT2 + OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2) + 0x148 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received interrupt + 3 + 1 + + + NAK + NAK response received interrupt + 4 + 1 + + + ACK + ACK response received/transmitted interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT3 + FS_HCINT3 + OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3) + 0x168 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received interrupt + 3 + 1 + + + NAK + NAK response received interrupt + 4 + 1 + + + ACK + ACK response received/transmitted interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT4 + FS_HCINT4 + OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4) + 0x188 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received interrupt + 3 + 1 + + + NAK + NAK response received interrupt + 4 + 1 + + + ACK + ACK response received/transmitted interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT5 + FS_HCINT5 + OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5) + 0x1A8 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received interrupt + 3 + 1 + + + NAK + NAK response received interrupt + 4 + 1 + + + ACK + ACK response received/transmitted interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT6 + FS_HCINT6 + OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6) + 0x1C8 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received interrupt + 3 + 1 + + + NAK + NAK response received interrupt + 4 + 1 + + + ACK + ACK response received/transmitted interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT7 + FS_HCINT7 + OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7) + 0x1E8 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received interrupt + 3 + 1 + + + NAK + NAK response received interrupt + 4 + 1 + + + ACK + ACK response received/transmitted interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINTMSK0 + FS_HCINTMSK0 + OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0) + 0x10C + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt mask + 3 + 1 + + + NAKM + NAK response received interrupt mask + 4 + 1 + + + ACKM + ACK response received/transmitted interrupt mask + 5 + 1 + + + NYET + response received interrupt mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK1 + FS_HCINTMSK1 + OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1) + 0x12C + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt mask + 3 + 1 + + + NAKM + NAK response received interrupt mask + 4 + 1 + + + ACKM + ACK response received/transmitted interrupt mask + 5 + 1 + + + NYET + response received interrupt mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK2 + FS_HCINTMSK2 + OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2) + 0x14C + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt mask + 3 + 1 + + + NAKM + NAK response received interrupt mask + 4 + 1 + + + ACKM + ACK response received/transmitted interrupt mask + 5 + 1 + + + NYET + response received interrupt mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK3 + FS_HCINTMSK3 + OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3) + 0x16C + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt mask + 3 + 1 + + + NAKM + NAK response received interrupt mask + 4 + 1 + + + ACKM + ACK response received/transmitted interrupt mask + 5 + 1 + + + NYET + response received interrupt mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK4 + FS_HCINTMSK4 + OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4) + 0x18C + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt mask + 3 + 1 + + + NAKM + NAK response received interrupt mask + 4 + 1 + + + ACKM + ACK response received/transmitted interrupt mask + 5 + 1 + + + NYET + response received interrupt mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK5 + FS_HCINTMSK5 + OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5) + 0x1AC + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt mask + 3 + 1 + + + NAKM + NAK response received interrupt mask + 4 + 1 + + + ACKM + ACK response received/transmitted interrupt mask + 5 + 1 + + + NYET + response received interrupt mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK6 + FS_HCINTMSK6 + OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6) + 0x1CC + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt mask + 3 + 1 + + + NAKM + NAK response received interrupt mask + 4 + 1 + + + ACKM + ACK response received/transmitted interrupt mask + 5 + 1 + + + NYET + response received interrupt mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK7 + FS_HCINTMSK7 + OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7) + 0x1EC + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt mask + 3 + 1 + + + NAKM + NAK response received interrupt mask + 4 + 1 + + + ACKM + ACK response received/transmitted interrupt mask + 5 + 1 + + + NYET + response received interrupt mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCTSIZ0 + FS_HCTSIZ0 + OTG_FS host channel-0 transfer size register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ1 + FS_HCTSIZ1 + OTG_FS host channel-1 transfer size register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ2 + FS_HCTSIZ2 + OTG_FS host channel-2 transfer size register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ3 + FS_HCTSIZ3 + OTG_FS host channel-3 transfer size register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ4 + FS_HCTSIZ4 + OTG_FS host channel-x transfer size register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ5 + FS_HCTSIZ5 + OTG_FS host channel-5 transfer size register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ6 + FS_HCTSIZ6 + OTG_FS host channel-6 transfer size register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ7 + FS_HCTSIZ7 + OTG_FS host channel-7 transfer size register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + + + OTG_FS_DEVICE + USB on the go full speed + USB_OTG_FS + 0x50000800 + + 0x0 + 0x400 + registers + + + + FS_DCFG + FS_DCFG + OTG_FS device configuration register (OTG_FS_DCFG) + 0x0 + 0x20 + read-write + 0x02200000 + + + DSPD + Device speed + 0 + 2 + + + NZLSOHSK + Non-zero-length status OUT handshake + 2 + 1 + + + DAD + Device address + 4 + 7 + + + PFIVL + Periodic frame interval + 11 + 2 + + + + + FS_DCTL + FS_DCTL + OTG_FS device control register (OTG_FS_DCTL) + 0x4 + 0x20 + 0x00000000 + + + RWUSIG + Remote wakeup signaling + 0 + 1 + read-write + + + SDIS + Soft disconnect + 1 + 1 + read-write + + + GINSTS + Global IN NAK status + 2 + 1 + read-only + + + GONSTS + Global OUT NAK status + 3 + 1 + read-only + + + TCTL + Test control + 4 + 3 + read-write + + + SGINAK + Set global IN NAK + 7 + 1 + read-write + + + CGINAK + Clear global IN NAK + 8 + 1 + read-write + + + SGONAK + Set global OUT NAK + 9 + 1 + read-write + + + CGONAK + Clear global OUT NAK + 10 + 1 + read-write + + + POPRGDNE + Power-on programming done + 11 + 1 + read-write + + + + + FS_DSTS + FS_DSTS + OTG_FS device status register (OTG_FS_DSTS) + 0x8 + 0x20 + read-only + 0x00000010 + + + SUSPSTS + Suspend status + 0 + 1 + + + ENUMSPD + Enumerated speed + 1 + 2 + + + EERR + Erratic error + 3 + 1 + + + FNSOF + Frame number of the received SOF + 8 + 14 + + + + + FS_DIEPMSK + FS_DIEPMSK + OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK) + 0x10 + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed interrupt mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt mask + 1 + 1 + + + TOM + Timeout condition mask (Non-isochronous endpoints) + 3 + 1 + + + ITTXFEMSK + IN token received when TxFIFO empty mask + 4 + 1 + + + INEPNMM + IN token received with EP mismatch mask + 5 + 1 + + + INEPNEM + IN endpoint NAK effective mask + 6 + 1 + + + + + FS_DOEPMSK + FS_DOEPMSK + OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK) + 0x14 + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed interrupt mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt mask + 1 + 1 + + + STUPM + SETUP phase done mask + 3 + 1 + + + OTEPDM + OUT token received when endpoint disabled mask + 4 + 1 + + + + + FS_DAINT + FS_DAINT + OTG_FS device all endpoints interrupt register (OTG_FS_DAINT) + 0x18 + 0x20 + read-only + 0x00000000 + + + IEPINT + IN endpoint interrupt bits + 0 + 16 + + + OEPINT + OUT endpoint interrupt bits + 16 + 16 + + + + + FS_DAINTMSK + FS_DAINTMSK + OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK) + 0x1C + 0x20 + read-write + 0x00000000 + + + IEPM + IN EP interrupt mask bits + 0 + 16 + + + OEPINT + OUT endpoint interrupt bits + 16 + 16 + + + + + DVBUSDIS + DVBUSDIS + OTG_FS device VBUS discharge time register + 0x28 + 0x20 + read-write + 0x000017D7 + + + VBUSDT + Device VBUS discharge time + 0 + 16 + + + + + DVBUSPULSE + DVBUSPULSE + OTG_FS device VBUS pulsing time register + 0x2C + 0x20 + read-write + 0x000005B8 + + + DVBUSP + Device VBUS pulsing time + 0 + 12 + + + + + DIEPEMPMSK + DIEPEMPMSK + OTG_FS device IN endpoint FIFO empty interrupt mask register + 0x34 + 0x20 + read-write + 0x00000000 + + + INEPTXFEM + IN EP Tx FIFO empty interrupt mask bits + 0 + 16 + + + + + FS_DIEPCTL0 + FS_DIEPCTL0 + OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0) + 0x100 + 0x20 + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 2 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-only + + + EPENA + Endpoint enable + 31 + 1 + read-only + + + + + DIEPCTL1 + DIEPCTL1 + OTG device endpoint-1 control register + 0x120 + 0x20 + 0x00000000 + + + EPENA + EPENA + 31 + 1 + read-write + + + EPDIS + EPDIS + 30 + 1 + read-write + + + SODDFRM_SD1PID + SODDFRM/SD1PID + 29 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + TXFNUM + TXFNUM + 22 + 4 + read-write + + + Stall + Stall + 21 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-write + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EONUM_DPID + EONUM/DPID + 16 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-write + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + + + DIEPCTL2 + DIEPCTL2 + OTG device endpoint-2 control register + 0x140 + 0x20 + 0x00000000 + + + EPENA + EPENA + 31 + 1 + read-write + + + EPDIS + EPDIS + 30 + 1 + read-write + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + TXFNUM + TXFNUM + 22 + 4 + read-write + + + Stall + Stall + 21 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-write + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EONUM_DPID + EONUM/DPID + 16 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-write + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + + + DIEPCTL3 + DIEPCTL3 + OTG device endpoint-3 control register + 0x160 + 0x20 + 0x00000000 + + + EPENA + EPENA + 31 + 1 + read-write + + + EPDIS + EPDIS + 30 + 1 + read-write + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + TXFNUM + TXFNUM + 22 + 4 + read-write + + + Stall + Stall + 21 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-write + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EONUM_DPID + EONUM/DPID + 16 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-write + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + + + DOEPCTL0 + DOEPCTL0 + device endpoint-0 control register + 0x300 + 0x20 + 0x00008000 + + + EPENA + EPENA + 31 + 1 + write-only + + + EPDIS + EPDIS + 30 + 1 + read-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + Stall + Stall + 21 + 1 + read-write + + + SNPM + SNPM + 20 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-only + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-only + + + MPSIZ + MPSIZ + 0 + 2 + read-only + + + + + DOEPCTL1 + DOEPCTL1 + device endpoint-1 control register + 0x320 + 0x20 + 0x00000000 + + + EPENA + EPENA + 31 + 1 + read-write + + + EPDIS + EPDIS + 30 + 1 + read-write + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + Stall + Stall + 21 + 1 + read-write + + + SNPM + SNPM + 20 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-write + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EONUM_DPID + EONUM/DPID + 16 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-write + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + + + DOEPCTL2 + DOEPCTL2 + device endpoint-2 control register + 0x340 + 0x20 + 0x00000000 + + + EPENA + EPENA + 31 + 1 + read-write + + + EPDIS + EPDIS + 30 + 1 + read-write + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + Stall + Stall + 21 + 1 + read-write + + + SNPM + SNPM + 20 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-write + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EONUM_DPID + EONUM/DPID + 16 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-write + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + + + DOEPCTL3 + DOEPCTL3 + device endpoint-3 control register + 0x360 + 0x20 + 0x00000000 + + + EPENA + EPENA + 31 + 1 + read-write + + + EPDIS + EPDIS + 30 + 1 + read-write + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + Stall + Stall + 21 + 1 + read-write + + + SNPM + SNPM + 20 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-write + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EONUM_DPID + EONUM/DPID + 16 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-write + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + + + DIEPINT0 + DIEPINT0 + device endpoint-x interrupt register + 0x108 + 0x20 + 0x00000080 + + + TXFE + TXFE + 7 + 1 + read-only + + + INEPNE + INEPNE + 6 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + XFRC + XFRC + 0 + 1 + read-write + + + + + DIEPINT1 + DIEPINT1 + device endpoint-1 interrupt register + 0x128 + 0x20 + 0x00000080 + + + TXFE + TXFE + 7 + 1 + read-only + + + INEPNE + INEPNE + 6 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + XFRC + XFRC + 0 + 1 + read-write + + + + + DIEPINT2 + DIEPINT2 + device endpoint-2 interrupt register + 0x148 + 0x20 + 0x00000080 + + + TXFE + TXFE + 7 + 1 + read-only + + + INEPNE + INEPNE + 6 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + XFRC + XFRC + 0 + 1 + read-write + + + + + DIEPINT3 + DIEPINT3 + device endpoint-3 interrupt register + 0x168 + 0x20 + 0x00000080 + + + TXFE + TXFE + 7 + 1 + read-only + + + INEPNE + INEPNE + 6 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + XFRC + XFRC + 0 + 1 + read-write + + + + + DOEPINT0 + DOEPINT0 + device endpoint-0 interrupt register + 0x308 + 0x20 + read-write + 0x00000080 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STUP + STUP + 3 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + XFRC + XFRC + 0 + 1 + + + + + DOEPINT1 + DOEPINT1 + device endpoint-1 interrupt register + 0x328 + 0x20 + read-write + 0x00000080 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STUP + STUP + 3 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + XFRC + XFRC + 0 + 1 + + + + + DOEPINT2 + DOEPINT2 + device endpoint-2 interrupt register + 0x348 + 0x20 + read-write + 0x00000080 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STUP + STUP + 3 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + XFRC + XFRC + 0 + 1 + + + + + DOEPINT3 + DOEPINT3 + device endpoint-3 interrupt register + 0x368 + 0x20 + read-write + 0x00000080 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STUP + STUP + 3 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + XFRC + XFRC + 0 + 1 + + + + + DIEPTSIZ0 + DIEPTSIZ0 + device endpoint-0 transfer size register + 0x110 + 0x20 + read-write + 0x00000000 + + + PKTCNT + Packet count + 19 + 2 + + + XFRSIZ + Transfer size + 0 + 7 + + + + + DOEPTSIZ0 + DOEPTSIZ0 + device OUT endpoint-0 transfer size register + 0x310 + 0x20 + read-write + 0x00000000 + + + STUPCNT + SETUP packet count + 29 + 2 + + + PKTCNT + Packet count + 19 + 1 + + + XFRSIZ + Transfer size + 0 + 7 + + + + + DIEPTSIZ1 + DIEPTSIZ1 + device endpoint-1 transfer size register + 0x130 + 0x20 + read-write + 0x00000000 + + + MCNT + Multi count + 29 + 2 + + + PKTCNT + Packet count + 19 + 10 + + + XFRSIZ + Transfer size + 0 + 19 + + + + + DIEPTSIZ2 + DIEPTSIZ2 + device endpoint-2 transfer size register + 0x150 + 0x20 + read-write + 0x00000000 + + + MCNT + Multi count + 29 + 2 + + + PKTCNT + Packet count + 19 + 10 + + + XFRSIZ + Transfer size + 0 + 19 + + + + + DIEPTSIZ3 + DIEPTSIZ3 + device endpoint-3 transfer size register + 0x170 + 0x20 + read-write + 0x00000000 + + + MCNT + Multi count + 29 + 2 + + + PKTCNT + Packet count + 19 + 10 + + + XFRSIZ + Transfer size + 0 + 19 + + + + + DTXFSTS0 + DTXFSTS0 + OTG_FS device IN endpoint transmit FIFO status register + 0x118 + 0x20 + read-only + 0x00000000 + + + INEPTFSAV + IN endpoint TxFIFO space available + 0 + 16 + + + + + DTXFSTS1 + DTXFSTS1 + OTG_FS device IN endpoint transmit FIFO status register + 0x138 + 0x20 + read-only + 0x00000000 + + + INEPTFSAV + IN endpoint TxFIFO space available + 0 + 16 + + + + + DTXFSTS2 + DTXFSTS2 + OTG_FS device IN endpoint transmit FIFO status register + 0x158 + 0x20 + read-only + 0x00000000 + + + INEPTFSAV + IN endpoint TxFIFO space available + 0 + 16 + + + + + DTXFSTS3 + DTXFSTS3 + OTG_FS device IN endpoint transmit FIFO status register + 0x178 + 0x20 + read-only + 0x00000000 + + + INEPTFSAV + IN endpoint TxFIFO space available + 0 + 16 + + + + + DOEPTSIZ1 + DOEPTSIZ1 + device OUT endpoint-1 transfer size register + 0x330 + 0x20 + read-write + 0x00000000 + + + RXDPID_STUPCNT + Received data PID/SETUP packet count + 29 + 2 + + + PKTCNT + Packet count + 19 + 10 + + + XFRSIZ + Transfer size + 0 + 19 + + + + + DOEPTSIZ2 + DOEPTSIZ2 + device OUT endpoint-2 transfer size register + 0x350 + 0x20 + read-write + 0x00000000 + + + RXDPID_STUPCNT + Received data PID/SETUP packet count + 29 + 2 + + + PKTCNT + Packet count + 19 + 10 + + + XFRSIZ + Transfer size + 0 + 19 + + + + + DOEPTSIZ3 + DOEPTSIZ3 + device OUT endpoint-3 transfer size register + 0x370 + 0x20 + read-write + 0x00000000 + + + RXDPID_STUPCNT + Received data PID/SETUP packet count + 29 + 2 + + + PKTCNT + Packet count + 19 + 10 + + + XFRSIZ + Transfer size + 0 + 19 + + + + + + + OTG_FS_PWRCLK + USB on the go full speed + USB_OTG_FS + 0x50000E00 + + 0x0 + 0x400 + registers + + + + FS_PCGCCTL + FS_PCGCCTL + OTG_FS power and clock gating control register (OTG_FS_PCGCCTL) + 0x0 + 0x20 + read-write + 0x00000000 + + + STPPCLK + Stop PHY clock + 0 + 1 + + + GATEHCLK + Gate HCLK + 1 + 1 + + + PHYSUSP + PHY Suspended + 4 + 1 + + + + + + + SWPMI1 + Single Wire Protocol Master Interface + SWPMI + 0x40008800 + + 0x0 + 0x400 + registers + + + SWPMI1 + SWPMI1 global interrupt + 76 + + + + CR + CR + SWPMI Configuration/Control register + 0x0 + 0x20 + read-write + 0x00000000 + + + RXDMA + Reception DMA enable + 0 + 1 + + + TXDMA + Transmission DMA enable + 1 + 1 + + + RXMODE + Reception buffering mode + 2 + 1 + + + TXMODE + Transmission buffering mode + 3 + 1 + + + LPBK + Loopback mode enable + 4 + 1 + + + SWPACT + Single wire protocol master interface activate + 5 + 1 + + + DEACT + Single wire protocol master interface deactivate + 10 + 1 + + + + + BRR + BRR + SWPMI Bitrate register + 0x4 + 0x20 + read-write + 0x00000001 + + + BR + Bitrate prescaler + 0 + 6 + + + + + ISR + ISR + SWPMI Interrupt and Status register + 0xC + 0x20 + read-only + 0x000002C2 + + + RXBFF + Receive buffer full flag + 0 + 1 + + + TXBEF + Transmit buffer empty flag + 1 + 1 + + + RXBERF + Receive CRC error flag + 2 + 1 + + + RXOVRF + Receive overrun error flag + 3 + 1 + + + TXUNRF + Transmit underrun error flag + 4 + 1 + + + RXNE + Receive data register not empty + 5 + 1 + + + TXE + Transmit data register empty + 6 + 1 + + + TCF + Transfer complete flag + 7 + 1 + + + SRF + Slave resume flag + 8 + 1 + + + SUSP + SUSPEND flag + 9 + 1 + + + DEACTF + DEACTIVATED flag + 10 + 1 + + + + + ICR + ICR + SWPMI Interrupt Flag Clear register + 0x10 + 0x20 + write-only + 0x00000000 + + + CRXBFF + Clear receive buffer full flag + 0 + 1 + + + CTXBEF + Clear transmit buffer empty flag + 1 + 1 + + + CRXBERF + Clear receive CRC error flag + 2 + 1 + + + CRXOVRF + Clear receive overrun error flag + 3 + 1 + + + CTXUNRF + Clear transmit underrun error flag + 4 + 1 + + + CTCF + Clear transfer complete flag + 7 + 1 + + + CSRF + Clear slave resume flag + 8 + 1 + + + + + IER + IER + SWPMI Interrupt Enable register + 0x14 + 0x20 + read-write + 0x00000000 + + + RXBFIE + Receive buffer full interrupt enable + 0 + 1 + + + TXBEIE + Transmit buffer empty interrupt enable + 1 + 1 + + + RXBERIE + Receive CRC error interrupt enable + 2 + 1 + + + RXOVRIE + Receive overrun error interrupt enable + 3 + 1 + + + TXUNRIE + Transmit underrun error interrupt enable + 4 + 1 + + + RIE + Receive interrupt enable + 5 + 1 + + + TIE + Transmit interrupt enable + 6 + 1 + + + TCIE + Transmit complete interrupt enable + 7 + 1 + + + SRIE + Slave resume interrupt enable + 8 + 1 + + + + + RFL + RFL + SWPMI Receive Frame Length register + 0x18 + 0x20 + read-only + 0x00000000 + + + RFL + Receive frame length + 0 + 5 + + + + + TDR + TDR + SWPMI Transmit data register + 0x1C + 0x20 + write-only + 0x00000000 + + + TD + Transmit data + 0 + 32 + + + + + RDR + RDR + SWPMI Receive data register + 0x20 + 0x20 + read-only + 0x00000000 + + + RD + received data + 0 + 32 + + + + + OR + OR + SWPMI Option register + 0x24 + 0x20 + read-write + 0x00000000 + + + SWP_TBYP + SWP transceiver bypass + 0 + 1 + + + SWP_CLASS + SWP class selection + 1 + 1 + + + + + + + OPAMP + Operational amplifiers + OPAMP + 0x40007800 + + 0x0 + 0x400 + registers + + + + OPAMP1_CSR + OPAMP1_CSR + OPAMP1 control/status register + 0x0 + 0x20 + read-write + 0x00000000 + + + OPAEN + Operational amplifier Enable + 0 + 1 + + + OPALPM + Operational amplifier Low Power Mode + 1 + 1 + + + OPAMODE + Operational amplifier PGA mode + 2 + 2 + + + PGA_GAIN + Operational amplifier Programmable amplifier gain value + 4 + 2 + + + VM_SEL + Inverting input selection + 8 + 2 + + + VP_SEL + Non inverted input selection + 10 + 1 + + + CALON + Calibration mode enabled + 12 + 1 + + + CALSEL + Calibration selection + 13 + 1 + + + USERTRIM + allows to switch from AOP offset trimmed values to AOP offset + 14 + 1 + + + CALOUT + Operational amplifier calibration output + 15 + 1 + + + OPA_RANGE + Operational amplifier power supply range for stability + 31 + 1 + + + + + OPAMP1_OTR + OPAMP1_OTR + OPAMP1 offset trimming register in normal mode + 0x4 + 0x20 + read-write + 0x00000000 + + + TRIMOFFSETN + Trim for NMOS differential pairs + 0 + 5 + + + TRIMOFFSETP + Trim for PMOS differential pairs + 8 + 5 + + + + + OPAMP1_LPOTR + OPAMP1_LPOTR + OPAMP1 offset trimming register in low-power mode + 0x8 + 0x20 + read-write + 0x00000000 + + + TRIMLPOFFSETN + Trim for NMOS differential pairs + 0 + 5 + + + TRIMLPOFFSETP + Trim for PMOS differential pairs + 8 + 5 + + + + + OPAMP2_CSR + OPAMP2_CSR + OPAMP2 control/status register + 0x10 + 0x20 + read-write + 0x00000000 + + + OPAEN + Operational amplifier Enable + 0 + 1 + + + OPALPM + Operational amplifier Low Power Mode + 1 + 1 + + + OPAMODE + Operational amplifier PGA mode + 2 + 2 + + + PGA_GAIN + Operational amplifier Programmable amplifier gain value + 4 + 2 + + + VM_SEL + Inverting input selection + 8 + 2 + + + VP_SEL + Non inverted input selection + 10 + 1 + + + CALON + Calibration mode enabled + 12 + 1 + + + CALSEL + Calibration selection + 13 + 1 + + + USERTRIM + allows to switch from AOP offset trimmed values to AOP offset + 14 + 1 + + + CALOUT + Operational amplifier calibration output + 15 + 1 + + + + + OPAMP2_OTR + OPAMP2_OTR + OPAMP2 offset trimming register in normal mode + 0x14 + 0x20 + read-write + 0x00000000 + + + TRIMOFFSETN + Trim for NMOS differential pairs + 0 + 5 + + + TRIMOFFSETP + Trim for PMOS differential pairs + 8 + 5 + + + + + OPAMP2_LPOTR + OPAMP2_LPOTR + OPAMP2 offset trimming register in low-power mode + 0x18 + 0x20 + read-write + 0x00000000 + + + TRIMLPOFFSETN + Trim for NMOS differential pairs + 0 + 5 + + + TRIMLPOFFSETP + Trim for PMOS differential pairs + 8 + 5 + + + + + + + FMC + Flexible memory controller + FMC + 0xA0000000 + + 0x0 + 0x400 + registers + + + FMC + FMC global Interrupt + 48 + + + + BCR1 + BCR1 + SRAM/NOR-Flash chip-select control register 1 + 0x0 + 0x20 + read-write + 0x000030D0 + + + MBKEN + MBKEN + 0 + 1 + + + MUXEN + MUXEN + 1 + 1 + + + MTYP + MTYP + 2 + 2 + + + MWID + MWID + 4 + 2 + + + FACCEN + FACCEN + 6 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WREN + WREN + 12 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + CCLKEN + CCLKEN + 20 + 1 + + + WFDIS + Write FIFO Disable + 21 + 1 + + + + + BTR1 + BTR1 + SRAM/NOR-Flash chip-select timing register 1 + 0x4 + 0x20 + read-write + 0xFFFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BCR2 + BCR2 + SRAM/NOR-Flash chip-select control register 2 + 0x8 + 0x20 + read-write + 0x000030D0 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + WREN + WREN + 12 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WRAPMOD + WRAPMOD + 10 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + FACCEN + FACCEN + 6 + 1 + + + MWID + MWID + 4 + 2 + + + MTYP + MTYP + 2 + 2 + + + MUXEN + MUXEN + 1 + 1 + + + MBKEN + MBKEN + 0 + 1 + + + + + BTR2 + BTR2 + SRAM/NOR-Flash chip-select timing register 2 + 0xC + 0x20 + read-write + 0xFFFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BCR3 + BCR3 + SRAM/NOR-Flash chip-select control register 3 + 0x10 + 0x20 + read-write + 0x000030D0 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + WREN + WREN + 12 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WRAPMOD + WRAPMOD + 10 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + FACCEN + FACCEN + 6 + 1 + + + MWID + MWID + 4 + 2 + + + MTYP + MTYP + 2 + 2 + + + MUXEN + MUXEN + 1 + 1 + + + MBKEN + MBKEN + 0 + 1 + + + + + BTR3 + BTR3 + SRAM/NOR-Flash chip-select timing register 3 + 0x14 + 0x20 + read-write + 0xFFFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BCR4 + BCR4 + SRAM/NOR-Flash chip-select control register 4 + 0x18 + 0x20 + read-write + 0x000030D0 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + WREN + WREN + 12 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WRAPMOD + WRAPMOD + 10 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + FACCEN + FACCEN + 6 + 1 + + + MWID + MWID + 4 + 2 + + + MTYP + MTYP + 2 + 2 + + + MUXEN + MUXEN + 1 + 1 + + + MBKEN + MBKEN + 0 + 1 + + + + + BTR4 + BTR4 + SRAM/NOR-Flash chip-select timing register 4 + 0x1C + 0x20 + read-write + 0xFFFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + PCR + PCR + PC Card/NAND Flash control register 3 + 0x80 + 0x20 + read-write + 0x00000018 + + + ECCPS + ECCPS + 17 + 3 + + + TAR + TAR + 13 + 4 + + + TCLR + TCLR + 9 + 4 + + + ECCEN + ECCEN + 6 + 1 + + + PWID + PWID + 4 + 2 + + + PTYP + PTYP + 3 + 1 + + + PBKEN + PBKEN + 2 + 1 + + + PWAITEN + PWAITEN + 1 + 1 + + + + + SR + SR + FIFO status and interrupt register 3 + 0x84 + 0x20 + 0x00000040 + + + FEMPT + FEMPT + 6 + 1 + read-only + + + IFEN + IFEN + 5 + 1 + read-write + + + ILEN + ILEN + 4 + 1 + read-write + + + IREN + IREN + 3 + 1 + read-write + + + IFS + IFS + 2 + 1 + read-write + + + ILS + ILS + 1 + 1 + read-write + + + IRS + IRS + 0 + 1 + read-write + + + + + PMEM + PMEM + Common memory space timing register 3 + 0x88 + 0x20 + read-write + 0xFCFCFCFC + + + MEMHIZx + MEMHIZx + 24 + 8 + + + MEMHOLDx + MEMHOLDx + 16 + 8 + + + MEMWAITx + MEMWAITx + 8 + 8 + + + MEMSETx + MEMSETx + 0 + 8 + + + + + PATT + PATT + Attribute memory space timing register 3 + 0x8C + 0x20 + read-write + 0xFCFCFCFC + + + ATTHIZx + ATTHIZx + 24 + 8 + + + ATTHOLDx + ATTHOLDx + 16 + 8 + + + ATTWAITx + ATTWAITx + 8 + 8 + + + ATTSETx + ATTSETx + 0 + 8 + + + + + ECCR + ECCR + ECC result register 3 + 0x94 + 0x20 + read-only + 0x00000000 + + + ECCx + ECCx + 0 + 32 + + + + + BWTR1 + BWTR1 + SRAM/NOR-Flash write timing registers 1 + 0x104 + 0x20 + read-write + 0x0FFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BWTR2 + BWTR2 + SRAM/NOR-Flash write timing registers 2 + 0x10C + 0x20 + read-write + 0x0FFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BWTR3 + BWTR3 + SRAM/NOR-Flash write timing registers 3 + 0x114 + 0x20 + read-write + 0x0FFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BWTR4 + BWTR4 + SRAM/NOR-Flash write timing registers 4 + 0x11C + 0x20 + read-write + 0x0FFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + + + CRS + Clock recovery system + CRS + 0x40006000 + + 0x0 + 0x400 + registers + + + CRS + HASH and CRS interrupt + 82 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00002000 + + + TRIM + HSI48 oscillator smooth trimming + 8 + 6 + + + SWSYNC + Generate software SYNC event + 7 + 1 + + + AUTOTRIMEN + Automatic trimming enable + 6 + 1 + + + CEN + Frequency error counter enable + 5 + 1 + + + ESYNCIE + Expected SYNC interrupt enable + 3 + 1 + + + ERRIE + Synchronization or trimming error interrupt enable + 2 + 1 + + + SYNCWARNIE + SYNC warning interrupt enable + 1 + 1 + + + SYNCOKIE + SYNC event OK interrupt enable + 0 + 1 + + + + + CFGR + CFGR + configuration register + 0x4 + 0x20 + read-write + 0x2022BB7F + + + SYNCPOL + SYNC polarity selection + 31 + 1 + + + SYNCSRC + SYNC signal source selection + 28 + 2 + + + SYNCDIV + SYNC divider + 24 + 3 + + + FELIM + Frequency error limit + 16 + 8 + + + RELOAD + Counter reload value + 0 + 16 + + + + + ISR + ISR + interrupt and status register + 0x8 + 0x20 + read-only + 0x00000000 + + + FECAP + Frequency error capture + 16 + 16 + + + FEDIR + Frequency error direction + 15 + 1 + + + TRIMOVF + Trimming overflow or underflow + 10 + 1 + + + SYNCMISS + SYNC missed + 9 + 1 + + + SYNCERR + SYNC error + 8 + 1 + + + ESYNCF + Expected SYNC flag + 3 + 1 + + + ERRF + Error flag + 2 + 1 + + + SYNCWARNF + SYNC warning flag + 1 + 1 + + + SYNCOKF + SYNC event OK flag + 0 + 1 + + + + + ICR + ICR + interrupt flag clear register + 0xC + 0x20 + read-write + 0x00000000 + + + ESYNCC + Expected SYNC clear flag + 3 + 1 + + + ERRC + Error clear flag + 2 + 1 + + + SYNCWARNC + SYNC warning clear flag + 1 + 1 + + + SYNCOKC + SYNC event OK clear flag + 0 + 1 + + + + + + + DCMI + Digital camera interface + DCMI + 0x50050000 + + 0x0 + 0x400 + registers + + + + CR + CR + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + ENABLE + DCMI enable + 14 + 1 + + + EDM + Extended data mode + 10 + 2 + + + FCRC + Frame capture rate control + 8 + 2 + + + VSPOL + Vertical synchronization polarity + 7 + 1 + + + HSPOL + Horizontal synchronization polarity + 6 + 1 + + + PCKPOL + Pixel clock polarity + 5 + 1 + + + ESS + Embedded synchronization select + 4 + 1 + + + JPEG + JPEG format + 3 + 1 + + + CROP + Crop feature + 2 + 1 + + + CM + Capture mode + 1 + 1 + + + CAPTURE + Capture enable + 0 + 1 + + + OELS + Odd/Even Line Select (Line Select Start) + 20 + 1 + + + LSM + Line Select mode + 19 + 1 + + + OEBS + Odd/Even Byte Select (Byte Select Start) + 18 + 1 + + + BSM + Byte Select mode + 16 + 2 + + + + + SR + SR + status register + 0x4 + 0x20 + read-only + 0x0000 + + + FNE + FIFO not empty + 2 + 1 + + + VSYNC + VSYNC + 1 + 1 + + + HSYNC + HSYNC + 0 + 1 + + + + + RIS + RIS + raw interrupt status register + 0x8 + 0x20 + read-only + 0x0000 + + + LINE_RIS + Line raw interrupt status + 4 + 1 + + + VSYNC_RIS + VSYNC raw interrupt status + 3 + 1 + + + ERR_RIS + Synchronization error raw interrupt status + 2 + 1 + + + OVR_RIS + Overrun raw interrupt status + 1 + 1 + + + FRAME_RIS + Capture complete raw interrupt status + 0 + 1 + + + + + IER + IER + interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + LINE_IE + Line interrupt enable + 4 + 1 + + + VSYNC_IE + VSYNC interrupt enable + 3 + 1 + + + ERR_IE + Synchronization error interrupt enable + 2 + 1 + + + OVR_IE + Overrun interrupt enable + 1 + 1 + + + FRAME_IE + Capture complete interrupt enable + 0 + 1 + + + + + MIS + MIS + masked interrupt status register + 0x10 + 0x20 + read-only + 0x0000 + + + LINE_MIS + Line masked interrupt status + 4 + 1 + + + VSYNC_MIS + VSYNC masked interrupt status + 3 + 1 + + + ERR_MIS + Synchronization error masked interrupt status + 2 + 1 + + + OVR_MIS + Overrun masked interrupt status + 1 + 1 + + + FRAME_MIS + Capture complete masked interrupt status + 0 + 1 + + + + + ICR + ICR + interrupt clear register + 0x14 + 0x20 + write-only + 0x0000 + + + LINE_ISC + line interrupt status clear + 4 + 1 + + + VSYNC_ISC + Vertical synch interrupt status clear + 3 + 1 + + + ERR_ISC + Synchronization error interrupt status clear + 2 + 1 + + + OVR_ISC + Overrun interrupt status clear + 1 + 1 + + + FRAME_ISC + Capture complete interrupt status clear + 0 + 1 + + + + + ESCR + ESCR + embedded synchronization code register + 0x18 + 0x20 + read-write + 0x0000 + + + FEC + Frame end delimiter code + 24 + 8 + + + LEC + Line end delimiter code + 16 + 8 + + + LSC + Line start delimiter code + 8 + 8 + + + FSC + Frame start delimiter code + 0 + 8 + + + + + ESUR + ESUR + embedded synchronization unmask register + 0x1C + 0x20 + read-write + 0x0000 + + + FEU + Frame end delimiter unmask + 24 + 8 + + + LEU + Line end delimiter unmask + 16 + 8 + + + LSU + Line start delimiter unmask + 8 + 8 + + + FSU + Frame start delimiter unmask + 0 + 8 + + + + + CWSTRT + CWSTRT + crop window start + 0x20 + 0x20 + read-write + 0x0000 + + + VST + Vertical start line count + 16 + 13 + + + HOFFCNT + Horizontal offset count + 0 + 14 + + + + + CWSIZE + CWSIZE + crop window size + 0x24 + 0x20 + read-write + 0x0000 + + + VLINE + Vertical line count + 16 + 14 + + + CAPCNT + Capture count + 0 + 14 + + + + + DR + DR + data register + 0x28 + 0x20 + read-only + 0x0000 + + + Byte3 + Data byte 3 + 24 + 8 + + + Byte2 + Data byte 2 + 16 + 8 + + + Byte1 + Data byte 1 + 8 + 8 + + + Byte0 + Data byte 0 + 0 + 8 + + + + + + + diff --git a/Lib/Vendor/SVD/STM32U5A9.svd b/Lib/Vendor/SVD/STM32U5A9.svd new file mode 100644 index 000000000..739ba965f --- /dev/null +++ b/Lib/Vendor/SVD/STM32U5A9.svd @@ -0,0 +1,295938 @@ + + + + STM32U5A9 + 1.0 + STM32U5A9 + + CM33 + r0p1 + little + true + true + 4 + false + + 8 + 32 + 0x20 + 0x0 + 0xFFFFFFFF + + + ADC1 + ADC1 + ADC + 0x42028000 + + 0x0 + 0xCC + registers + + + ADC12 + ADC1 (14 bits) global interrupt + 37 + + + + ADC_ISR + ADC_ISR + ADC interrupt and status register + 0x000 + 0x20 + 0x00000000 + + + LDORDY + LDORDY + 12 + 1 + read-only + + + AWD3 + AWD3 + 9 + 1 + read-write + + + AWD2 + AWD2 + 8 + 1 + read-write + + + AWD1 + AWD1 + 7 + 1 + read-write + + + JEOS + JEOS + 6 + 1 + read-write + + + JEOC + JEOC + 5 + 1 + read-write + + + OVR + OVR + 4 + 1 + read-write + + + EOS + EOS + 3 + 1 + read-write + + + EOC + EOC + 2 + 1 + read-write + + + EOSMP + EOSMP + 1 + 1 + read-write + + + ADRDY + ADRDY + 0 + 1 + read-write + + + + + ADC_IER + ADC_IER + ADC interrupt enable register + 0x04 + 0x20 + read-write + 0x00000000 + + + AWD3IE + AWD3IE + 9 + 1 + + + AWD2IE + AWD2IE + 8 + 1 + + + AWD1IE + AWD1IE + 7 + 1 + + + JEOSIE + JEOSIE + 6 + 1 + + + JEOCIE + JEOCIE + 5 + 1 + + + OVRIE + OVRIE + 4 + 1 + + + EOSIE + EOSIE + 3 + 1 + + + EOCIE + EOCIE + 2 + 1 + + + EOSMPIE + EOSMPIE + 1 + 1 + + + ADRDYIE + ADRDYIE + 0 + 1 + + + + + ADC_CR + ADC_CR + ADC control register + 0x08 + 0x20 + 0x20000000 + + + ADCAL + ADCAL + 31 + 1 + read-only + + + DEEPPWD + DEEPPWD + 29 + 1 + read-write + + + ADVREGEN + ADVREGEN + 28 + 1 + read-write + + + CALINDEX + CALINDEX + 24 + 4 + read-write + + + ADCALLIN + ADCALLIN + 16 + 1 + read-write + + + JADSTP + JADSTP + 5 + 1 + read-only + + + ADSTP + ADSTP + 4 + 1 + read-only + + + JADSTART + JADSTART + 3 + 1 + read-only + + + ADSTART + ADSTART + 2 + 1 + read-only + + + ADDIS + ADDIS + 1 + 1 + read-only + + + ADEN + ADEN + 0 + 1 + read-only + + + + + ADC_CFGR1 + ADC_CFGR1 + ADC configuration register + 0x0C + 0x20 + read-write + 0x80000000 + + + AWD1CH + AWD1CH + 26 + 5 + + + JAUTO + JAUTO + 25 + 1 + + + JAWD1EN + JAWD1EN + 24 + 1 + + + AWD1EN + AWD1EN + 23 + 1 + + + AWD1SGL + AWD1SGL + 22 + 1 + + + JDISCEN + JDISCEN + 20 + 1 + + + DISCNUM + DISCNUM + 17 + 3 + + + DISCEN + DISCEN + 16 + 1 + + + AUTDLY + AUTDLY + 14 + 1 + + + CONT + CONT + 13 + 1 + + + OVRMOD + OVRMOD + 12 + 1 + + + EXTEN + EXTEN + 10 + 2 + + + EXTSEL + EXTSEL + 5 + 5 + + + RES + RES + 2 + 2 + + + DMNGT + DMNGT + 0 + 2 + + + + + ADC_CFGR2 + ADC_CFGR2 + ADC configuration register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + LSHIFT + LSHIFT + 28 + 4 + + + LFTRIG + LFTRIG + 27 + 1 + + + OSR + OSR + 16 + 10 + + + SMPTRIG + SMPTRIG + 15 + 1 + + + SWTRIG + SWTRIG + 14 + 1 + + + BULB + BULB + 13 + 1 + + + ROVSM + ROVSM + 10 + 1 + + + TROVS + TROVS + 9 + 1 + + + OVSS + OVSS + 5 + 4 + + + JOVSE + JOVSE + 1 + 1 + + + ROVSE + ROVSE + 0 + 1 + + + + + ADC_SMPR1 + ADC_SMPR1 + ADC sample time register 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + SMP9 + SMP9 + 27 + 3 + + + SMP8 + SMP8 + 24 + 3 + + + SMP7 + SMP7 + 21 + 3 + + + SMP6 + SMP6 + 18 + 3 + + + SMP5 + SMP5 + 15 + 3 + + + SMP4 + SMP4 + 12 + 3 + + + SMP3 + SMP3 + 9 + 3 + + + SMP2 + SMP2 + 6 + 3 + + + SMP1 + SMP1 + 3 + 3 + + + SMP0 + SMP0 + 0 + 3 + + + + + ADC_SMPR2 + ADC_SMPR2 + ADC sample time register 2 + 0x18 + 0x20 + read-write + 0x00000000 + + + SMP19 + SMP19 + 27 + 3 + + + SMP18 + SMP18 + 24 + 3 + + + SMP17 + SMP17 + 21 + 3 + + + SMP16 + SMP16 + 18 + 3 + + + SMP15 + SMP15 + 15 + 3 + + + SMP14 + SMP14 + 12 + 3 + + + SMP13 + SMP13 + 9 + 3 + + + SMP12 + SMP12 + 6 + 3 + + + SMP11 + SMP11 + 3 + 3 + + + SMP10 + SMP10 + 0 + 3 + + + + + ADC_PCSEL + ADC_PCSEL + ADC channel preselection register + 0x1C + 0x20 + read-write + 0x00000000 + + + PCSEL19 + PCSEL19 + 19 + 1 + + + PCSEL18 + PCSEL18 + 18 + 1 + + + PCSEL17 + PCSEL17 + 17 + 1 + + + PCSEL16 + PCSEL16 + 16 + 1 + + + PCSEL15 + PCSEL15 + 15 + 1 + + + PCSEL14 + PCSEL14 + 14 + 1 + + + PCSEL13 + PCSEL13 + 13 + 1 + + + PCSEL12 + PCSEL12 + 12 + 1 + + + PCSEL11 + PCSEL11 + 11 + 1 + + + PCSEL10 + PCSEL10 + 10 + 1 + + + PCSEL9 + PCSEL9 + 9 + 1 + + + PCSEL8 + PCSEL8 + 8 + 1 + + + PCSEL7 + PCSEL7 + 7 + 1 + + + PCSEL6 + PCSEL6 + 6 + 1 + + + PCSEL5 + PCSEL5 + 5 + 1 + + + PCSEL4 + PCSEL4 + 4 + 1 + + + PCSEL3 + PCSEL3 + 3 + 1 + + + PCSEL2 + PCSEL2 + 2 + 1 + + + PCSEL1 + PCSEL1 + 1 + 1 + + + PCSEL0 + PCSEL0 + 0 + 1 + + + + + ADC_SQR1 + ADC_SQR1 + ADC regular sequence register 1 + 0x30 + 0x20 + read-write + 0x00000000 + + + SQ4 + SQ4 + 24 + 5 + + + SQ3 + SQ3 + 18 + 5 + + + SQ2 + SQ2 + 12 + 5 + + + SQ1 + SQ1 + 6 + 5 + + + L + L + 0 + 4 + + + + + ADC_SQR2 + ADC_SQR2 + ADC regular sequence register 2 + 0x34 + 0x20 + read-write + 0x00000000 + + + SQ9 + SQ9 + 24 + 5 + + + SQ8 + SQ8 + 18 + 5 + + + SQ7 + SQ7 + 12 + 5 + + + SQ6 + SQ6 + 6 + 5 + + + SQ5 + SQ5 + 0 + 5 + + + + + ADC_SQR3 + ADC_SQR3 + ADC regular sequence register 3 + 0x38 + 0x20 + read-write + 0x00000000 + + + SQ14 + SQ14 + 24 + 5 + + + SQ13 + SQ13 + 18 + 5 + + + SQ12 + SQ12 + 12 + 5 + + + SQ11 + SQ11 + 6 + 5 + + + SQ10 + SQ10 + 0 + 5 + + + + + ADC_SQR4 + ADC_SQR4 + ADC regular sequence register 4 + 0x3C + 0x20 + read-write + 0x00000000 + + + SQ16 + SQ16 + 6 + 5 + + + SQ15 + SQ15 + 0 + 5 + + + + + ADC_DR + ADC_DR + ADC regular Data Register + 0x40 + 0x20 + read-only + 0x00000000 + + + RDATA + RDATA + 0 + 32 + + + + + ADC_JSQR + ADC_JSQR + ADC injected sequence register + 0x4C + 0x20 + read-write + 0x00000000 + + + JSQ4 + JSQ4 + 27 + 5 + + + JSQ3 + JSQ3 + 21 + 5 + + + JSQ2 + JSQ2 + 15 + 5 + + + JSQ1 + JSQ1 + 9 + 5 + + + JEXTEN + JEXTEN + 7 + 2 + + + JEXTSEL + JEXTSEL + 2 + 5 + + + JL + JL + 0 + 2 + + + + + ADC_OFR1 + ADC_OFR1 + ADC offset register + 0x60 + 0x20 + read-write + 0x00000000 + + + OFFSET_CH + OFFSET_CH + 27 + 5 + + + SSAT + SSAT + 26 + 1 + + + USAT + USAT + 25 + 1 + + + POSOFF + POSOFF + 24 + 1 + + + OFFSET + OFFSET + 0 + 24 + + + + + ADC_OFR2 + ADC_OFR2 + ADC offset register + 0x64 + 0x20 + read-write + 0x00000000 + + + OFFSET_CH + OFFSET_CH + 27 + 5 + + + SSAT + SSAT + 26 + 1 + + + USAT + USAT + 25 + 1 + + + POSOFF + POSOFF + 24 + 1 + + + OFFSET + OFFSET + 0 + 24 + + + + + ADC_OFR3 + ADC_OFR3 + ADC offset register + 0x68 + 0x20 + read-write + 0x00000000 + + + OFFSET_CH + OFFSET_CH + 27 + 5 + + + SSAT + SSAT + 26 + 1 + + + USAT + USAT + 25 + 1 + + + POSOFF + POSOFF + 24 + 1 + + + OFFSET + OFFSET + 0 + 24 + + + + + ADC_OFR4 + ADC_OFR4 + ADC offset register + 0x6C + 0x20 + read-write + 0x00000000 + + + OFFSET_CH + OFFSET_CH + 27 + 5 + + + SSAT + SSAT + 26 + 1 + + + USAT + USAT + 25 + 1 + + + POSOFF + POSOFF + 24 + 1 + + + OFFSET + OFFSET + 0 + 24 + + + + + ADC_GCOMP + ADC_GCOMP + ADC gain compensation register + 0x70 + 0x20 + read-write + 0x00000000 + + + GCOMP + GCOMP + 31 + 1 + + + GCOMPCOEFF + GCOMPCOEFF + 0 + 14 + + + + + ADC_JDR1 + ADC_JDR1 + ADC injected data register + 0x80 + 0x20 + read-only + 0x00000000 + + + JDATA + JDATA + 0 + 32 + + + + + ADC_JDR2 + ADC_JDR2 + ADC injected data register + 0x84 + 0x20 + read-only + 0x00000000 + + + JDATA + JDATA + 0 + 32 + + + + + ADC_JDR3 + ADC_JDR3 + ADC injected data register + 0x88 + 0x20 + read-only + 0x00000000 + + + JDATA + JDATA + 0 + 32 + + + + + ADC_JDR4 + ADC_JDR4 + ADC injected data register + 0x8C + 0x20 + read-only + 0x00000000 + + + JDATA + JDATA + 0 + 32 + + + + + ADC_AWD2CR + ADC_AWD2CR + ADC analog watchdog 2 configuration register + 0xA0 + 0x20 + read-write + 0x00000000 + + + AWD2CH + AWD2CH + 0 + 20 + + + + + ADC_AWD3CR + ADC_AWD3CR + ADC analog watchdog 3 configuration register + 0xA4 + 0x20 + read-write + 0x00000000 + + + AWD3CH + AWD3CH + 0 + 20 + + + + + ADC_LTR1 + ADC_LTR1 + ADC watchdog threshold register 1 + 0xA8 + 0x20 + read-write + 0x00000000 + + + LTR1 + LTR1 + 0 + 25 + + + + + ADC_HTR1 + ADC_HTR1 + ADC watchdog threshold register 1 + 0xAC + 0x20 + read-write + 0x01FFFFFF + + + AWDFILT1 + AWDFILT1 + 29 + 3 + + + HTR1 + HTR1 + 0 + 25 + + + + + ADC_LTR2 + ADC_LTR2 + ADC watchdog lower threshold register 2 + 0xB0 + 0x20 + read-write + 0x00000000 + + + LTR2 + LTR2 + 0 + 25 + + + + + ADC_HTR2 + ADC_HTR2 + ADC watchdog higher threshold register 2 + 0xB4 + 0x20 + read-write + 0x01FFFFFF + + + HTR2 + HTR2 + 0 + 25 + + + + + ADC_LTR3 + ADC_LTR3 + ADC watchdog lower threshold register 3 + 0xB8 + 0x20 + read-write + 0x00000000 + + + LTR3 + LTR3 + 0 + 25 + + + + + ADC_HTR3 + ADC_HTR3 + ADC watchdog higher threshold register 3 + 0xBC + 0x20 + read-write + 0x01FFFFFF + + + HTR3 + HTR3 + 0 + 25 + + + + + ADC_DIFSEL + ADC_DIFSEL + ADC differential mode selection register + 0xC0 + 0x20 + read-write + 0x00000000 + + + DIFSEL + DIFSEL + 0 + 20 + + + + + ADC_CALFACT + ADC_CALFACT + ADC user control register + 0xC4 + 0x20 + 0x00000000 + + + CAPTURE_COEF + CAPTURE_COEF + 25 + 1 + read-write + + + LATCH_COEF + LATCH_COEF + 24 + 1 + read-write + + + VALIDITY + VALIDITY + 16 + 1 + read-only + + + I_APB_DATA + I_APB_DATA + 8 + 8 + read-only + + + I_APB_ADDR + I_APB_ADDR + 0 + 8 + read-only + + + + + ADC_CALFACT2 + ADC_CALFACT2 + ADC calibration factor register + 0xC8 + 0x20 + read-write + 0x00000000 + + + CALFACT + CALFACT + 0 + 32 + + + + + + + SEC_ADC1 + DCB->DSCSR->CDS == 0 + 0x52028000 + + + ADC2 + 0x42028100 + + + SEC_ADC2 + DCB->DSCSR->CDS == 0 + 0x52028100 + + + ADC12_Common + Analog-to-Digital Converter + ADC + 0x42028300 + + 0x0 + 0x14 + registers + + + + ADC12_CSR + ADC12_CSR + ADC common status register + 0x0 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + ADRDY_MST + Master ADC ready +This bit is a copy of the ADRDY bit in the corresponding ADC_ISR register. + 0 + 1 + read-only + + + EOSMP_MST + End of Sampling phase flag of the master ADC +This bit is a copy of the EOSMP bit in the corresponding ADC_ISR register. + 1 + 1 + read-only + + + EOC_MST + End of regular conversion of the master ADC +This bit is a copy of the EOC bit in the corresponding ADC_ISR register. + 2 + 1 + read-only + + + EOS_MST + End of regular sequence flag of the master ADC +This bit is a copy of the EOS bit in the corresponding ADC_ISR register. + 3 + 1 + read-only + + + OVR_MST + Overrun flag of the master ADC +This bit is a copy of the OVR bit in the corresponding ADC_ISR register. + 4 + 1 + read-only + + + JEOC_MST + End of injected conversion flag of the master ADC +This bit is a copy of the JEOC bit in the corresponding ADC_ISR register. + 5 + 1 + read-only + + + JEOS_MST + End of injected sequence flag of the master ADC +This bit is a copy of the JEOS bit in the corresponding ADC_ISR register. + 6 + 1 + read-only + + + AWD1_MST + Analog watchdog 1 flag of the master ADC +This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register. + 7 + 1 + read-only + + + AWD2_MST + Analog watchdog 2 flag of the master ADC +This bit is a copy of the AWD2 bit in the corresponding ADC_ISR register. + 8 + 1 + read-only + + + AWD3_MST + Analog watchdog 3 flag of the master ADC +This bit is a copy of the AWD3 bit in the corresponding ADC_ISR register. + 9 + 1 + read-only + + + LDORDY_MST + ADC voltage regulator ready flag of the master ADC +This bit is a copy of the LDORDY bit of the corresponding ADC_ISR register. + 12 + 1 + read-only + + + ADRDY_SLV + Slave ADC ready +This bit is a copy of the ADRDY bit in the corresponding ADCx+1_ISR register. + 16 + 1 + read-only + + + EOSMP_SLV + End of Sampling phase flag of the slave ADC +This bit is a copy of the EOSMP2 bit in the corresponding ADCx+1_ISR register. + 17 + 1 + read-only + + + EOC_SLV + End of regular conversion of the slave ADC +This bit is a copy of the EOC bit in the corresponding ADCx+1_ISR register. + 18 + 1 + read-only + + + EOS_SLV + End of regular sequence flag of the slave ADC +This bit is a copy of the EOS bit in the corresponding ADCx+1_ISR register. + 19 + 1 + read-only + + + OVR_SLV + Overrun flag of the slave ADC +This bit is a copy of the OVR bit in the corresponding ADCx+1_ISR register. + 20 + 1 + read-only + + + JEOC_SLV + End of injected conversion flag of the slave ADC +This bit is a copy of the JEOC bit in the corresponding ADCx+1_ISR register. + 21 + 1 + read-only + + + JEOS_SLV + End of injected sequence flag of the slave ADC +This bit is a copy of the JEOS bit in the corresponding ADCx+1_ISR register. + 22 + 1 + read-only + + + AWD1_SLV + Analog watchdog 1 flag of the slave ADC +This bit is a copy of the AWD1 bit in the corresponding ADCx+1_ISR register. + 23 + 1 + read-only + + + AWD2_SLV + Analog watchdog 2 flag of the slave ADC +This bit is a copy of the AWD2 bit in the corresponding ADCx+1_ISR register. + 24 + 1 + read-only + + + AWD3_SLV + Analog watchdog 3 flag of the slave ADC +This bit is a copy of the AWD3 bit in the corresponding ADCx+1_ISR register. + 25 + 1 + read-only + + + LDORDY_SLV + ADC voltage regulator ready flag of the slave ADC +This bit is a copy of the LDORDY bit of the corresponding ADCx+1_ISR register. + 28 + 1 + read-only + + + + + ADC12_CCR + ADC12_CCR + ADC_CCR system control register + 0x8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DUAL + Dual ADC mode selection +These bits are written by software to select the operating mode. +All the ADCs are independent: +The configurations 00001 to 01001 correspond to the following operating modes: Dual mode, master and slave ADCs working together: +All other combinations are reserved and must not be programmed +Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). + 0 + 5 + read-write + + + B_0x0 + Independent mode + 0x0 + + + B_0x1 + Combined regular simultaneous + injected simultaneous mode + 0x1 + + + B_0x2 + Combined regular simultaneous + alternate trigger mode + 0x2 + + + B_0x3 + Combined Interleaved mode + injected simultaneous mode + 0x3 + + + B_0x5 + Injected simultaneous mode only + 0x5 + + + B_0x6 + Regular simultaneous mode only + 0x6 + + + B_0x7 + Interleaved mode only + 0x7 + + + B_0x9 + Alternate trigger mode only + 0x9 + + + + + DELAY + Delay between the end of the master ADC sampling phase and the beginning of +the slave ADC sampling phase. +These bits are set and cleared by software. These bits are used in dual interleaved modes. Refer to for the value of ADC resolution versus DELAY bits values. +Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). + 8 + 4 + read-write + + + DAMDF + Dual ADC Mode Data Format +This bit-field is set and cleared by software. It specifies the data format in the common data register ADC12_CDR. +Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + 14 + 2 + read-write + + + B_0x0 + Dual ADC mode without data packing (ADC12_CDR and ADC12_CDR2 registers not used). + 0x0 + + + B_0x2 + Data formatting mode for 32 down to 10-bit resolution + 0x2 + + + B_0x3 + Data formatting mode for 8-bit resolution + 0x3 + + + + + PRESC + ADC prescaler +These bits are set and cleared by software to select the frequency of the ADC clock. The clock is common to all ADCs. +Others: Reserved, must not be used +Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). + 18 + 4 + read-write + + + B_0x0 + input ADC clock not divided + 0x0 + + + B_0x1 + input ADC clock divided by 2 + 0x1 + + + B_0x2 + input ADC clock divided by 4 + 0x2 + + + B_0x3 + input ADC clock divided by 6 + 0x3 + + + B_0x4 + input ADC clock divided by 8 + 0x4 + + + B_0x5 + input ADC clock divided by 10 + 0x5 + + + B_0x6 + input ADC clock divided by 12 + 0x6 + + + B_0x7 + input ADC clock divided by 16 + 0x7 + + + B_0x8 + input ADC clock divided by 32 + 0x8 + + + B_0x9 + input ADC clock divided by 64 + 0x9 + + + B_0xA + input ADC clock divided by 128 + 0xA + + + B_0xB + input ADC clock divided by 256 + 0xB + + + + + VREFEN + VREFINT enable +This bit is set and cleared by software to enable/disable the VREFINT buffer. +Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). + 22 + 1 + read-write + + + B_0x0 + VREFINT channel disabled + 0x0 + + + B_0x1 + VREFINT channel enabled + 0x1 + + + + + VSENSESEL + Temperature sensor voltage selection +This bit is set and cleared by software to control the temperature sensor channel. +Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). + 23 + 1 + read-write + + + B_0x0 + Temperature sensor channel disabled + 0x0 + + + B_0x1 + Temperature sensor channel enabled + 0x1 + + + + + VBATEN + VBAT enable +This bit is set and cleared by software to control the VBAT channel. +Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). + 24 + 1 + read-write + + + B_0x0 + VBAT channel disabled + 0x0 + + + B_0x1 + VBAT channel enabled + 0x1 + + + + + + + ADC12_CDR + ADC12_CDR + ADC common regular data register for dual mode + 0xc + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RDATA_MST + Regular data of the master ADC. +In dual mode, these bits contain the regular data of the master ADC. Refer to . +The data alignment is applied as described in offset (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, USAT, SSAT)) +In DAMDF[1:0] = 11 mode, bits 15:8 contains SLV_ADC_DR[7:0], bits 7:0 contains MST_ADC_DR[7:0]. + 0 + 16 + read-only + + + RDATA_SLV + Regular data of the slave ADC +In dual mode, these bits contain the regular data of the slave ADC. Refer to Dual ADC modes. +The data alignment is applied as described in offset (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, USAT, SSAT)) + 16 + 16 + read-only + + + + + ADC12_CDR2 + ADC12_CDR2 + ADC common regular data register for 32-bit dual mode + 0x10 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RDATA_ALT + Regular data of the master/slave alternated ADCs +In dual mode, these bits alternatively contains the regular 32-bit data of the master and the slave ADC. Refer to . +The data alignment is applied as described in (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, USAT, SSAT). + 0 + 32 + read-only + + + + + + + SEC_ADC12_Common + DCB->DSCSR->CDS == 0 + 0x52028300 + + + ADC4 + ADC4 + ADC + 0x46021000 + + 0x0 + 0x400 + registers + + + ADC4 + ADC4 (12 bits) global interrupt + 113 + + + + ADC_ISR + ADC_ISR + ADC interrupt and status register + 0x000 + 0x20 + read-write + 0x00000000 + + + LDORDY + LDORDY + 12 + 1 + + + EOCAL + EOCAL + 11 + 1 + + + AWD3 + AWD3 + 9 + 1 + + + AWD2 + AWD2 + 8 + 1 + + + AWD1 + AWD1 + 7 + 1 + + + OVR + OVR + 4 + 1 + + + EOS + EOS + 3 + 1 + + + EOC + EOC + 2 + 1 + + + EOSMP + EOSMP + 1 + 1 + + + ADRDY + ADRDY + 0 + 1 + + + + + ADC_IER + ADC_IER + ADC interrupt enable register + 0x04 + 0x20 + read-write + 0x00000000 + + + LDORDYIE + LDORDYIE + 12 + 1 + + + EOCALIE + EOCALIE + 11 + 1 + + + AWD3IE + AWD3IE + 9 + 1 + + + AWD2IE + AWD2IE + 8 + 1 + + + AWD1IE + AWD1IE + 7 + 1 + + + OVRIE + OVRIE + 4 + 1 + + + EOSIE + EOSIE + 3 + 1 + + + EOCIE + EOCIE + 2 + 1 + + + EOSMPIE + EOSMPIE + 1 + 1 + + + ADRDYIE + ADRDYIE + 0 + 1 + + + + + ADC_CR + ADC_CR + ADC control register + 0x08 + 0x20 + 0x00000000 + + + ADCAL + ADCAL + 31 + 1 + read-only + + + ADVREGEN + ADVREGEN + 28 + 1 + read-write + + + ADSTP + ADSTP + 4 + 1 + read-only + + + ADSTART + ADSTART + 2 + 1 + read-only + + + ADDIS + ADDIS + 1 + 1 + read-only + + + ADEN + ADEN + 0 + 1 + read-only + + + + + ADC_CFGR1 + ADC_CFGR1 + ADC configuration register + 0x0C + 0x20 + read-write + 0x00000000 + + + AWD1CH + AWD1CH + 26 + 5 + + + AWD1EN + AWD1EN + 23 + 1 + + + AWD1SGL + AWD1SGL + 22 + 1 + + + CHSELRMOD + CHSELRMOD + 21 + 1 + + + DISCEN + DISCEN + 16 + 1 + + + WAIT + WAIT + 14 + 1 + + + CONT + CONT + 13 + 1 + + + OVRMOD + OVRMOD + 12 + 1 + + + EXTEN + EXTEN + 10 + 2 + + + EXTSEL + EXTSEL + 6 + 3 + + + ALIGN + ALIGN + 5 + 1 + + + SCANDIR + SCANDIR + 4 + 1 + + + RES + RES + 2 + 2 + + + DMACFG + DMACFG + 1 + 1 + + + DMAEN + DMAEN + 0 + 1 + + + + + ADC_CFGR2 + ADC_CFGR2 + ADC configuration register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + LFTRIG + LFTRIG + 29 + 1 + + + TOVS + TOVS + 9 + 1 + + + OVSS + OVSS + 5 + 4 + + + OVSR + OVSR + 2 + 3 + + + OVSE + OVSE + 0 + 1 + + + + + ADC_SMPR + ADC_SMPR + ADC sample time register + 0x14 + 0x20 + read-write + 0x00000000 + + + SMPSEL23 + SMPSEL23 + 31 + 1 + + + SMPSEL22 + SMPSEL22 + 30 + 1 + + + SMPSEL21 + SMPSEL21 + 29 + 1 + + + SMPSEL20 + SMPSEL20 + 28 + 1 + + + SMPSEL19 + SMPSEL19 + 27 + 1 + + + SMPSEL18 + SMPSEL18 + 26 + 1 + + + SMPSEL17 + SMPSEL17 + 25 + 1 + + + SMPSEL16 + SMPSEL16 + 24 + 1 + + + SMPSEL15 + SMPSEL15 + 23 + 1 + + + SMPSEL14 + SMPSEL14 + 22 + 1 + + + SMPSEL13 + SMPSEL13 + 21 + 1 + + + SMPSEL12 + SMPSEL12 + 20 + 1 + + + SMPSEL11 + SMPSEL11 + 19 + 1 + + + SMPSEL10 + SMPSEL10 + 18 + 1 + + + SMPSEL9 + SMPSEL9 + 17 + 1 + + + SMPSEL8 + SMPSEL8 + 16 + 1 + + + SMPSEL7 + SMPSEL7 + 15 + 1 + + + SMPSEL6 + SMPSEL6 + 14 + 1 + + + SMPSEL5 + SMPSEL5 + 13 + 1 + + + SMPSEL4 + SMPSEL4 + 12 + 1 + + + SMPSEL3 + SMPSEL3 + 11 + 1 + + + SMPSEL2 + SMPSEL2 + 10 + 1 + + + SMPSEL1 + SMPSEL1 + 9 + 1 + + + SMPSEL0 + SMPSEL0 + 8 + 1 + + + SMP2 + SMP2 + 4 + 3 + + + SMP1 + SMP1 + 0 + 3 + + + + + ADC_AWD1TR + ADC_AWD1TR + ADC watchdog threshold register + 0x20 + 0x20 + read-write + 0x0FFF0000 + + + HT1 + HT1 + 16 + 12 + + + LT1 + LT1 + 0 + 12 + + + + + ADC_AWD2TR + ADC_AWD2TR + ADC watchdog threshold register + 0x24 + 0x20 + read-write + 0x0FFF0000 + + + HT2 + HT2 + 16 + 12 + + + LT2 + LT2 + 0 + 12 + + + + + ADC_CHSELRMOD0 + ADC_CHSELRMOD0 + ADC channel selection register [alternate] + 0x28 + 0x20 + read-write + 0x00000000 + + + CHSEL + CHSEL + 0 + 24 + + + + + ADC_CHSELRMOD1 + ADC_CHSELRMOD1 + ADC channel selection register [alternate] + ADC_CHSELRMOD0 + 0x28 + 0x20 + read-write + 0x00000000 + + + SQ8 + SQ8 + 28 + 4 + + + SQ7 + SQ7 + 24 + 4 + + + SQ6 + SQ6 + 20 + 4 + + + SQ5 + SQ5 + 16 + 4 + + + SQ4 + SQ4 + 12 + 4 + + + SQ3 + SQ3 + 8 + 4 + + + SQ2 + SQ2 + 4 + 4 + + + SQ1 + SQ1 + 0 + 4 + + + + + ADC_AWD3TR + ADC_AWD3TR + ADC watchdog threshold register + 0x2C + 0x20 + read-write + 0x0FFF0000 + + + HT3 + HT3 + 16 + 12 + + + LT3 + LT3 + 0 + 12 + + + + + ADC_DR + ADC_DR + ADC data register + 0x40 + 0x20 + read-only + 0x00000000 + + + DATA + DATA + 0 + 16 + + + + + ADC_PWR + ADC_PWR + ADC data register + 0x44 + 0x20 + read-write + 0x00000000 + + + VREFSECSMP + VREFSECSMP + 3 + 1 + + + VREFPROT + VREFPROT + 2 + 1 + + + DPD + DPD + 1 + 1 + + + AUTOFF + AUTOFF + 0 + 1 + + + + + ADC_AWD2CR + ADC_AWD2CR + ADC Analog Watchdog 2 Configuration register + 0xA0 + 0x20 + read-write + 0x00000000 + + + AWD2CH23 + AWD2CH23 + 23 + 1 + + + AWD2CH22 + AWD2CH22 + 22 + 1 + + + AWD2CH21 + AWD2CH21 + 21 + 1 + + + AWD2CH20 + AWD2CH20 + 20 + 1 + + + AWD2CH19 + AWD2CH19 + 19 + 1 + + + AWD2CH18 + AWD2CH18 + 18 + 1 + + + AWD2CH17 + AWD2CH17 + 17 + 1 + + + AWD2CH16 + AWD2CH16 + 16 + 1 + + + AWD2CH15 + AWD2CH15 + 15 + 1 + + + AWD2CH14 + AWD2CH14 + 14 + 1 + + + AWD2CH13 + AWD2CH13 + 13 + 1 + + + AWD2CH12 + AWD2CH12 + 12 + 1 + + + AWD2CH11 + AWD2CH11 + 11 + 1 + + + AWD2CH10 + AWD2CH10 + 10 + 1 + + + AWD2CH9 + AWD2CH9 + 9 + 1 + + + AWD2CH8 + AWD2CH8 + 8 + 1 + + + AWD2CH7 + AWD2CH7 + 7 + 1 + + + AWD2CH6 + AWD2CH6 + 6 + 1 + + + AWD2CH5 + AWD2CH5 + 5 + 1 + + + AWD2CH4 + AWD2CH4 + 4 + 1 + + + AWD2CH3 + AWD2CH3 + 3 + 1 + + + AWD2CH2 + AWD2CH2 + 2 + 1 + + + AWD2CH1 + AWD2CH1 + 1 + 1 + + + AWD2CH0 + AWD2CH0 + 0 + 1 + + + + + ADC_AWD3CR + ADC_AWD3CR + ADC Analog Watchdog 3 Configuration register + 0xA4 + 0x20 + read-write + 0x00000000 + + + AWD3CH23 + AWD3CH23 + 23 + 1 + + + AWD3CH22 + AWD3CH22 + 22 + 1 + + + AWD3CH21 + AWD3CH21 + 21 + 1 + + + AWD3CH20 + AWD3CH20 + 20 + 1 + + + AWD3CH19 + AWD3CH19 + 19 + 1 + + + AWD3CH18 + AWD3CH18 + 18 + 1 + + + AWD3CH17 + AWD3CH17 + 17 + 1 + + + AWD3CH16 + AWD3CH16 + 16 + 1 + + + AWD3CH15 + AWD3CH15 + 15 + 1 + + + AWD3CH14 + AWD3CH14 + 14 + 1 + + + AWD3CH13 + AWD3CH13 + 13 + 1 + + + AWD3CH12 + AWD3CH12 + 12 + 1 + + + AWD3CH11 + AWD3CH11 + 11 + 1 + + + AWD3CH10 + AWD3CH10 + 10 + 1 + + + AWD3CH9 + AWD3CH9 + 9 + 1 + + + AWD3CH8 + AWD3CH8 + 8 + 1 + + + AWD3CH7 + AWD3CH7 + 7 + 1 + + + AWD3CH6 + AWD3CH6 + 6 + 1 + + + AWD3CH5 + AWD3CH5 + 5 + 1 + + + AWD3CH4 + AWD3CH4 + 4 + 1 + + + AWD3CH3 + AWD3CH3 + 3 + 1 + + + AWD3CH2 + AWD3CH2 + 2 + 1 + + + AWD3CH1 + AWD3CH1 + 1 + 1 + + + AWD3CH0 + AWD3CH0 + 0 + 1 + + + + + ADC_CALFACT + ADC_CALFACT + ADC Calibration factor + 0xB4 + 0x20 + read-write + 0x00000000 + + + CALFACT + CALFACT + 0 + 7 + + + + + ADC_OR + ADC_OR + ADC option register + 0xD0 + 0x20 + read-write + 0x00000000 + + + CHN21SEL + CHN21SEL + 0 + 1 + + + + + ADC_CCR + ADC_CCR + ADC common configuration register + 0x308 + 0x20 + read-write + 0x00000000 + + + VBATEN + VBATEN + 24 + 1 + + + TSEN + TSEN + 23 + 1 + + + VREFEN + VREFEN + 22 + 1 + + + PRESC + PRESC + 18 + 4 + + + + + + + SEC_ADC4 + DCB->DSCSR->CDS == 0 + 0x56021000 + + + ADF1 + ADF1 + ADF + 0x46024000 + + 0x0 + 0x1000 + registers + + + ADF1_FLT0 + ADF1 filter 0 global interrupt + 112 + + + + ADF_GCR + ADF_GCR + ADF Global Control Register + 0x000 + 0x20 + read-write + 0x00000000 + + + TRGO + Trigger output control Set by software and reset by + 0 + 1 + + + + + ADF_CKGCR + ADF_CKGCR + ADF clock generator control register + 0x004 + 0x20 + read-write + 0x00000000 + + + CKGACTIVE + Clock generator active flag + 31 + 1 + + + PROCDIV + Divider to control the serial interface clock + 24 + 7 + + + CCKDIV + Divider to control the ADF_CCK clock + 16 + 4 + + + TRGSRC + Digital filter trigger signal selection + 12 + 4 + + + TRGSENS + CKGEN trigger sensitivity selection + 8 + 1 + + + CCK1DIR + ADF_CCK1 direction + 6 + 1 + + + CCK0DIR + ADF_CCK0 direction + 5 + 1 + + + CKGMOD + Clock generator mode + 4 + 1 + + + CCK1EN + ADF_CCK1 clock enable + 2 + 1 + + + CCK0EN + ADF_CCK0 clock enable + 1 + 1 + + + CKGDEN + CKGEN dividers enable + 0 + 1 + + + + + ADF_SITF0CR + ADF_SITF0CR + ADF serial interface control register 0 + 0x080 + 0x20 + read-write + 0x00001F00 + + + SITFACTIVE + SITFACTIVE + 31 + 1 + + + STH + STH + 8 + 5 + + + SITFMOD + SITFMOD + 4 + 2 + + + SCKSRC + SCKSRC + 1 + 2 + + + SITFEN + SITFEN + 0 + 1 + + + + + ADF_BSMX0CR + ADF_BSMX0CR + ADF bitstream matrix control register 0 + 0x084 + 0x20 + read-write + 0x00000000 + + + BSMXACTIVE + BSMX active flag + 31 + 1 + + + BSSEL + Bitstream selection + 0 + 5 + + + + + ADF_DFLT0CR + ADF_DFLT0CR + ADF digital filter control register 0 + 0x088 + 0x20 + read-write + 0x00000000 + + + DFLTACTIVE + DFLT0 active flag + 31 + 1 + + + DFLTRUN + DFLT0 run status flag + 30 + 1 + + + NBDIS + Number of samples to be discarded + 20 + 8 + + + TRGSRC + DFLT0 trigger signal selection + 12 + 4 + + + ACQMOD + DFLT0 trigger mode + 4 + 3 + + + FTH + RXFIFO threshold selection + 2 + 1 + + + DMAEN + DMA requests enable + 1 + 1 + + + DFLTEN + DFLT0 enable + 0 + 1 + + + + + ADF_DFLT0CICR + ADF_DFLT0CICR + ADF digital filer configuration register 0 + 0x08C + 0x20 + read-write + 0x00000000 + + + SCALE + Scaling factor selection + 20 + 6 + + + MCICD + CIC decimation ratio selection + 8 + 9 + + + CICMOD + Select the CIC order + 4 + 3 + + + DATSRC + Source data for the digital filter + 0 + 2 + + + + + ADF_DFLT0RSFR + ADF_DFLT0RSFR + ADF reshape filter configuration register 0 + 0x090 + 0x20 + read-write + 0x00000000 + + + HPFC + High-pass filter cut-off frequency + 8 + 2 + + + HPFBYP + High-pass filter bypass + 7 + 1 + + + RSFLTD + Reshaper filter decimation ratio + 4 + 1 + + + RSFLTBYP + Reshaper filter bypass + 0 + 1 + + + + + ADF_DLY0CR + ADF_DLY0CR + ADF delay control register 0 + 0x0A4 + 0x20 + read-write + 0x00000000 + + + SKPBF + Skip busy flag + 31 + 1 + + + SKPDLY + Delay to apply to a bitstream + 0 + 7 + + + + + ADF_DFLT0IER + ADF_DFLT0IER + ADF DFLT0 interrupt enable register + 0x0AC + 0x20 + read-write + 0x00000000 + + + SDLVLIE + SAD sound-level value ready enable + 13 + 1 + + + SDDETIE + Sound activity detection interrupt enable + 12 + 1 + + + RFOVRIE + Reshape filter overrun interrupt enable + 11 + 1 + + + CKABIE + Clock absence detection interrupt enable + 10 + 1 + + + SATIE + Saturation detection interrupt enable + 9 + 1 + + + DOVRIE + Data overflow interrupt enable + 1 + 1 + + + FTHIE + RXFIFO threshold interrupt enable + 0 + 1 + + + + + ADF_DFLT0ISR + ADF_DFLT0ISR + ADF DFLT0 interrupt status register 0 + 0x0B0 + 0x20 + 0x00000000 + + + SDLVLF + Sound level value ready flag + 13 + 1 + read-write + + + SDDETF + Sound activity detection flag + 12 + 1 + read-write + + + RFOVRF + Reshape filter overrun detection flag + 11 + 1 + read-write + + + CKABF + Clock absence detection flag + 10 + 1 + read-write + + + SATF + Saturation detection flag + 9 + 1 + read-write + + + RXNEF + RXFIFO not empty flag + 3 + 1 + read-only + + + DOVRF + Data overflow flag + 1 + 1 + read-write + + + FTHF + RXFIFO threshold flag + 0 + 1 + read-only + + + + + ADF_SADCR + ADF_SADCR + ADF SAD control register + 0x0B8 + 0x20 + 0x00000000 + + + SADACTIVE + SAD Active flag + 31 + 1 + read-only + + + SADMOD + SAD working mode + 12 + 2 + read-write + + + FRSIZE + Frame size + 8 + 3 + read-write + + + HYSTEN + Hysteresis enable + 7 + 1 + read-write + + + SADST + SAD state + 4 + 2 + read-only + + + DETCFG + Sound trigger event configuration + 3 + 1 + read-write + + + DATCAP + Data capture mode + 1 + 2 + read-write + + + SADEN + Sound activity detector enable + 0 + 1 + read-write + + + + + ADF_SADCFGR + ADF_SADCFGR + ADF SAD configuration register + 0x0BC + 0x20 + read-write + 0x00000000 + + + ANMIN + ANMIN + 16 + 13 + + + HGOVR + Hangover time window + 12 + 3 + + + LFRNB + LFRNB + 8 + 3 + + + ANSLP + ANSLP + 4 + 3 + + + SNTHR + SNTHR + 0 + 4 + + + + + ADF_SADSDLVR + ADF_SADSDLVR + ADF SAD sound level register + 0x0C0 + 0x20 + read-only + 0x00000000 + + + SDLVL + SDLVL + 0 + 15 + + + + + ADF_SADANLVR + ADF_SADANLVR + ADF SAD ambient noise level register + 0x0C4 + 0x20 + read-only + 0x00000000 + + + ANLVL + ANLVL + 0 + 15 + + + + + ADF_DFLT0DR + ADF_DFLT0DR + ADF digital filter data register 0 + 0x0F0 + 0x20 + read-only + 0x00000000 + + + DR + DR + 8 + 24 + + + + + + + SEC_ADF1 + DCB->DSCSR->CDS == 0 + 0x56024000 + + + AES + Advanced encryption standard hardware accelerator + AES + 0x420C0000 + + 0x0 + 0x400 + registers + + + AES + AES global interrupt + 93 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + IPRST + IPRST + 31 + 1 + + + KMOD + KMOD + 24 + 2 + + + NPBLB + NPBLB + 20 + 4 + + + KEYSIZE + KEYSIZE + 18 + 1 + + + CHMOD_2 + CHMOD_2 + 16 + 1 + + + GCMPH + GCMPH + 13 + 2 + + + DMAOUTEN + Enable DMA management of data output phase + 12 + 1 + + + DMAINEN + Enable DMA management of data input phase + 11 + 1 + + + CHMOD + AES chaining mode + 5 + 2 + + + MODE + AES operating mode + 3 + 2 + + + DATATYPE + Data type selection (for data in and data out to/from the cryptographic block) + 1 + 2 + + + EN + AES enable + 0 + 1 + + + + + SR + SR + status register + 0x4 + 0x20 + read-only + 0x00000000 + + + KEYVALID + Key Valid flag + 7 + 1 + + + BUSY + BUSY + 3 + 1 + + + WRERR + Write error flag + 2 + 1 + + + RDERR + Read error flag + 1 + 1 + + + CCF + Computation complete flag + 0 + 1 + + + + + DINR + DINR + data input register + 0x8 + 0x20 + write-only + 0x00000000 + + + DIN + Input data word + 0 + 32 + + + + + DOUTR + DOUTR + data output register + 0xC + 0x20 + read-only + 0x00000000 + + + DOUT + Output data word + 0 + 32 + + + + + KEYR0 + KEYR0 + key register 0 + 0x10 + 0x20 + write-only + 0x00000000 + + + KEY + Cryptographic key, bits [31:0] + 0 + 32 + + + + + KEYR1 + KEYR1 + key register 1 + 0x14 + 0x20 + write-only + 0x00000000 + + + KEY + Cryptographic key, bits [63:32] + 0 + 32 + + + + + KEYR2 + KEYR2 + key register 2 + 0x18 + 0x20 + write-only + 0x00000000 + + + KEYR + Cryptographic key, bits [95:64] + 0 + 32 + + + + + KEYR3 + KEYR3 + key register 3 + 0x1C + 0x20 + write-only + 0x00000000 + + + AES_KEYR3 + Cryptographic key, bits [127:96] + 0 + 32 + + + + + IVR0 + IVR0 + initialization vector register 0 + 0x20 + 0x20 + read-write + 0x00000000 + + + IVI + Initialization vector input, bits [31:0] + 0 + 32 + + + + + IVR1 + IVR1 + initialization vector register 1 + 0x24 + 0x20 + read-write + 0x00000000 + + + IVI + Initialization vector input, bits [63:32] + 0 + 32 + + + + + IVR2 + IVR2 + initialization vector register 2 + 0x28 + 0x20 + read-write + 0x00000000 + + + IVI + Initialization vector input, bits [95:64] + 0 + 32 + + + + + IVR3 + IVR3 + initialization vector register 3 + 0x2C + 0x20 + read-write + 0x00000000 + + + IVI + Initialization vector input, bits [127:96] + 0 + 32 + + + + + KEYR4 + KEYR4 + key register 4 + 0x30 + 0x20 + write-only + 0x00000000 + + + KEY + Cryptographic key, bits [159:128] + 0 + 32 + + + + + KEYR5 + KEYR5 + key register 5 + 0x34 + 0x20 + write-only + 0x00000000 + + + KEY + Cryptographic key, bits [191:160] + 0 + 32 + + + + + KEYR6 + KEYR6 + key register 6 + 0x38 + 0x20 + write-only + 0x00000000 + + + KEY + Cryptographic key, bits [223:192] + 0 + 32 + + + + + KEYR7 + KEYR7 + key register 7 + 0x3C + 0x20 + write-only + 0x00000000 + + + KEY + Cryptographic key, bits [255:224] + 0 + 32 + + + + + SUSP0R + SUSP0R + suspend registers + 0x40 + 0x20 + write-only + 0x00000000 + + + SUSP0 + AES suspend + 0 + 32 + + + + + SUSP1R + SUSP1R + suspend registers + 0x44 + 0x20 + write-only + 0x00000000 + + + SUSP1 + AES suspend + 0 + 32 + + + + + SUSP2R + SUSP2R + suspend registers + 0x48 + 0x20 + write-only + 0x00000000 + + + SUSP2 + AES suspend + 0 + 32 + + + + + SUSP3R + SUSP3R + suspend registers + 0x4C + 0x20 + write-only + 0x00000000 + + + SUSP3 + AES suspend + 0 + 32 + + + + + SUSP4R + SUSP4R + suspend registers + 0x50 + 0x20 + write-only + 0x00000000 + + + SUSP4 + AES suspend + 0 + 32 + + + + + SUSP5R + SUSP5R + suspend registers + 0x54 + 0x20 + write-only + 0x00000000 + + + SUSP5 + AES suspend + 0 + 32 + + + + + SUSP6R + SUSP6R + suspend registers + 0x58 + 0x20 + write-only + 0x00000000 + + + SUSP6 + AES suspend + 0 + 32 + + + + + SUSP7R + SUSP7R + suspend registers + 0x5C + 0x20 + write-only + 0x00000000 + + + SUSP7 + AES suspend + 0 + 32 + + + + + IER + IER + interrupt enable register + 0x300 + 0x20 + read-write + 0x00000000 + + + KEIE + Key error interrupt flag + 2 + 1 + + + RWEIE + Read or write error interrupt flag + 1 + 1 + + + CCFIE + Computation complete flag + 0 + 1 + + + + + ISR + ISR + interrupt status register + 0x304 + 0x20 + read-only + 0x00000000 + + + KEIF + Key error interrupt flag + 2 + 1 + + + RWEIF + Read or write error interrupt flag + 1 + 1 + + + CCF + Computation complete flag + 0 + 1 + + + + + ICR + ICR + interrupt clear register + 0x308 + 0x20 + write-only + 0x00000000 + + + KEIF + Key error interrupt flag clear + 2 + 1 + + + RWEIF + Read or write error interrupt flag clear + 1 + 1 + + + CCF + Computation complete flag clear + 0 + 1 + + + + + + + SEC_AES + DCB->DSCSR->CDS == 0 + 0x520C0000 + + + COMP + Comparator + COMP + 0x46005400 + + 0x0 + 0x400 + registers + + + COMP + COMP1 and COMP2 interrupts + 072 + + + + COMP1_CSR + COMP1_CSR + Comparator 1 control and status + register + 0x0 + 0x20 + 0x00000000 + + + COMP1_EN + Comparator 1 enable bit + 0 + 1 + read-write + + + COMP1_INMSEL + Comparator 1 Input Minus connection + configuration bit + 4 + 4 + read-write + + + COMP1_INPSEL + Comparator1 input plus selection + bit + 8 + 2 + read-write + + + COMP1_WINMODE + COMP1_WINMODE + 11 + 1 + read-write + + + COMP1_WINOUT + COMP1_WINOUT + 14 + 1 + read-write + + + COMP1_POLARITY + Comparator 1 polarity selection + bit + 15 + 1 + read-write + + + COMP1_HYST + Comparator 1 hysteresis selection + bits + 16 + 2 + read-write + + + COMP1_PWRMODE + COMP1_PWRMODE + 18 + 2 + read-write + + + COMP1_BLANKSEL + COMP1_BLANKSEL + 20 + 5 + read-write + + + COMP1_VALUE + Comparator 1 output status + bit + 30 + 1 + read-only + + + COMP1_LOCK + COMP1_CSR register lock + bit + 31 + 1 + read-write + + + + + COMP2_CSR + COMP2_CSR + Comparator 2 control and status + register + 0x4 + 0x20 + 0x00000000 + + + COM2_EN + Comparator 2 enable bit + 0 + 1 + read-write + + + COM2_INMSEL + Comparator 2 Input Minus connection + configuration bit + 4 + 4 + read-write + + + COM2_INPSEL + Comparator 2 input plus selection + bit + 8 + 2 + read-write + + + COM2_WINMODE + COM2_WINMODE + 11 + 1 + read-write + + + COM2_WINOUT + COM2_WINOUT + 14 + 1 + read-write + + + COM2_POLARITY + Comparator 2 polarity selection + bit + 15 + 1 + read-write + + + COM2_HYST + Comparator 2 hysteresis selection + bits + 16 + 2 + read-write + + + COM2_PWRMODE + COM2_PWRMODE + 18 + 2 + read-write + + + COM2_BLANKSEL + COM2_BLANKSEL + 20 + 5 + read-write + + + COM2_VALUE + Comparator 2 output status + bit + 30 + 1 + read-only + + + COM2_LOCK + COMP2_CSR register lock + bit + 31 + 1 + read-write + + + + + + + SEC_COMP + DCB->DSCSR->CDS == 0 + 0x56005400 + + + CORDIC + CORDIC Co-processor + CORDIC + 0x40021000 + + 0x0 + 0x400 + registers + + + CORDIC + CORDIC interrupt + 123 + + + + CSR + CSR + CORDIC Control Status register + 0x0 + 0x20 + 0x00000050 + + + FUNC + Function + 0 + 4 + read-write + + + PRECISION + Precision required (number of iterations) + 4 + 4 + read-write + + + SCALE + Scaling factor + 8 + 3 + read-write + + + IEN + Enable interrupt + 16 + 1 + read-write + + + DMAREN + Enable DMA read channel + 17 + 1 + read-write + + + DMAWEN + Enable DMA write channel + 18 + 1 + read-write + + + NRES + Number of results in the CORDIC_RDATA register + 19 + 1 + read-write + + + NARGS + Number of arguments expected by the CORDIC_WDATA register + 20 + 1 + read-write + + + RESSIZE + Width of output data + 21 + 1 + read-write + + + ARGSIZE + Width of input data + 22 + 1 + read-write + + + RRDY + Result ready flag + 31 + 1 + read-only + + + + + WDATA + WDATA + FMAC Write Data register + 0x4 + 0x20 + write-only + 0x00000000 + + + ARG + Function input arguments + 0 + 32 + + + + + RDATA + RDATA + FMAC Read Data register + 0x8 + 0x20 + read-only + 0x00000000 + + + RES + Function result + 0 + 32 + + + + + + + SEC_CORDIC + DCB->DSCSR->CDS == 0 + 0x50021000 + + + CRC + Cyclic redundancy check calculation + unit + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DR + DR + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DR + Data register bits + 0 + 32 + + + + + IDR + IDR + Independent data register + 0x4 + 0x20 + read-write + 0x00000000 + + + IDR + General-purpose 8-bit data register + bits + 0 + 32 + + + + + CR + CR + Control register + 0x8 + 0x20 + 0x00000000 + + + REV_OUT + Reverse output data + 7 + 1 + read-write + + + REV_IN + Reverse input data + 5 + 2 + read-write + + + POLYSIZE + Polynomial size + 3 + 2 + read-write + + + RESET + RESET bit + 0 + 1 + read-write + + + + + INIT + INIT + Initial CRC value + 0x10 + 0x20 + read-write + 0xFFFFFFFF + + + CRC_INIT + Programmable initial CRC + value + 0 + 32 + + + + + POL + POL + polynomial + 0x14 + 0x20 + read-write + 0x04C11DB7 + + + POL + Programmable polynomial + 0 + 32 + + + + + + + SEC_CRC + DCB->DSCSR->CDS == 0 + 0x50023000 + + + CRS + Clock recovery system + CRS + 0x40006000 + + 0x0 + 0x400 + registers + + + CRS + Clock recovery system global interrupt + 74 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00004000 + + + TRIM + HSI48 oscillator smooth + trimming + 8 + 7 + + + SWSYNC + Generate software SYNC + event + 7 + 1 + + + AUTOTRIMEN + Automatic trimming enable + 6 + 1 + + + CEN + Frequency error counter + enable + 5 + 1 + + + ESYNCIE + Expected SYNC interrupt + enable + 3 + 1 + + + ERRIE + Synchronization or trimming error + interrupt enable + 2 + 1 + + + SYNCWARNIE + SYNC warning interrupt + enable + 1 + 1 + + + SYNCOKIE + SYNC event OK interrupt + enable + 0 + 1 + + + + + CFGR + CFGR + configuration register + 0x4 + 0x20 + read-write + 0x2022BB7F + + + SYNCPOL + SYNC polarity selection + 31 + 1 + + + SYNCSRC + SYNC signal source + selection + 28 + 2 + + + SYNCDIV + SYNC divider + 24 + 3 + + + FELIM + Frequency error limit + 16 + 8 + + + RELOAD + Counter reload value + 0 + 16 + + + + + ISR + ISR + interrupt and status register + 0x8 + 0x20 + read-only + 0x00000000 + + + FECAP + Frequency error capture + 16 + 16 + + + FEDIR + Frequency error direction + 15 + 1 + + + TRIMOVF + Trimming overflow or + underflow + 10 + 1 + + + SYNCMISS + SYNC missed + 9 + 1 + + + SYNCERR + SYNC error + 8 + 1 + + + ESYNCF + Expected SYNC flag + 3 + 1 + + + ERRF + Error flag + 2 + 1 + + + SYNCWARNF + SYNC warning flag + 1 + 1 + + + SYNCOKF + SYNC event OK flag + 0 + 1 + + + + + ICR + ICR + interrupt flag clear register + 0xC + 0x20 + read-write + 0x00000000 + + + ESYNCC + Expected SYNC clear flag + 3 + 1 + + + ERRC + Error clear flag + 2 + 1 + + + SYNCWARNC + SYNC warning clear flag + 1 + 1 + + + SYNCOKC + SYNC event OK clear flag + 0 + 1 + + + + + + + SEC_CRS + DCB->DSCSR->CDS == 0 + 0x50006000 + + + DAC1 + Digital-to-analog converter + DAC + 0x46021800 + + 0x0 + 0x400 + registers + + + DAC1 + DAC1 global interrupt + 38 + + + + DAC_CR + DAC_CR + DAC control register + 0x0 + 0x20 + read-write + 0x00000000 + + + EN1 + DAC channel1 enable + 0 + 1 + + + TEN1 + DAC channel1 trigger enable + 1 + 1 + + + TSEL1 + DAC channel1 trigger selection + 2 + 4 + + + WAVE1 + DAC channel1 noise/triangle wave generation enable + 6 + 2 + + + MAMP1 + DAC channel1 mask/amplitude selector + 8 + 4 + + + DMAEN1 + DAC channel1 DMA enable + 12 + 1 + + + DMAUDRIE1 + DAC channel1 DMA Underrun Interrupt enable + 13 + 1 + + + CEN1 + DAC channel1 calibration enable + 14 + 1 + + + EN2 + DAC channel2 enable + 16 + 1 + + + TEN2 + DAC channel2 trigger enable + 17 + 1 + + + TSEL2 + DAC channel2 trigger selection + 18 + 4 + + + WAVE2 + DAC channel2 noise/triangle wave generation enable + 22 + 2 + + + MAMP2 + DAC channel2 mask/amplitude selector + 24 + 4 + + + DMAEN2 + DAC channel2 DMA enable + 28 + 1 + + + DMAUDRIE2 + DAC channel2 DMA underrun interrupt enable + 29 + 1 + + + CEN2 + DAC channel2 calibration enable + 30 + 1 + + + + + DAC_SWTRGR + DAC_SWTRGR + DAC software trigger register + 0x4 + 0x20 + write-only + 0x00000000 + + + SWTRIG1 + DAC channel1 software trigger + 0 + 1 + + + SWTRIG2 + DAC channel2 software trigger + 1 + 1 + + + + + DAC_DHR12R1 + DAC_DHR12R1 + DAC channel1 12-bit right-aligned data holding register + 0x8 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit right-aligned data + 0 + 12 + + + DACC1DHRB + DAC channel1 12-bit right-aligned data B + 16 + 12 + + + + + DAC_DHR12L1 + DAC_DHR12L1 + DAC channel1 12-bit left aligned data holding register + 0xC + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit left-aligned data + 4 + 12 + + + DACC1DHRB + DAC channel1 12-bit left-aligned data B + 20 + 12 + + + + + DAC_DHR8R1 + DAC_DHR8R1 + DAC channel1 8-bit right aligned data holding register + 0x10 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 8-bit right-aligned data + 0 + 8 + + + DACC1DHRB + DAC channel1 8-bit right-aligned Sdata + 8 + 8 + + + + + DAC_DHR12R2 + DAC_DHR12R2 + DAC channel2 12-bit right aligned data holding register + 0x14 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit right-aligned data + 0 + 12 + + + DACC2DHRB + DAC channel2 12-bit right-aligned data + 16 + 12 + + + + + DAC_DHR12L2 + DAC_DHR12L2 + DAC channel2 12-bit left aligned data holding register + 0x18 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit left-aligned data + 4 + 12 + + + DACC2DHRB + DAC channel2 12-bit left-aligned data B + 20 + 12 + + + + + DAC_DHR8R2 + DAC_DHR8R2 + DAC channel2 8-bit right-aligned data holding register + 0x1C + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 8-bit right-aligned data + 0 + 8 + + + DACC2DHRB + DAC channel2 8-bit right-aligned data + 8 + 8 + + + + + DAC_DHR12RD + DAC_DHR12RD + Dual DAC 12-bit right-aligned data holding register + 0x20 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit right-aligned data + 0 + 12 + + + DACC2DHR + DAC channel2 12-bit right-aligned data + 16 + 12 + + + + + DAC_DHR12LD + DAC_DHR12LD + DUAL DAC 12-bit left aligned data holding register + 0x24 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit left-aligned data + 4 + 12 + + + DACC2DHR + DAC channel2 12-bit left-aligned data + 20 + 12 + + + + + DAC_DHR8RD + DAC_DHR8RD + DUAL DAC 8-bit right aligned data holding register + 0x28 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 8-bit right-aligned data + 0 + 8 + + + DACC2DHR + DAC channel2 8-bit right-aligned data + 8 + 8 + + + + + DAC_DOR1 + DAC_DOR1 + DAC channel1 data output register + 0x2C + 0x20 + read-only + 0x00000000 + + + DACC1DOR + DAC channel1 data output + 0 + 12 + + + DACC1DORB + DAC channel1 data output + 16 + 12 + + + + + DAC_DOR2 + DAC_DOR2 + DAC channel2 data output register + 0x30 + 0x20 + read-only + 0x00000000 + + + DACC2DOR + DAC channel2 data output + 0 + 12 + + + DACC2DORB + DAC channel2 data output + 16 + 12 + + + + + DAC_SR + DAC_SR + DAC status register + 0x34 + 0x20 + 0x00000000 + + + DAC1RDY + DAC channel1 ready status bit + 11 + 1 + read-only + + + DORSTAT1 + DAC channel1 output register status bit + 12 + 1 + read-only + + + DMAUDR1 + DAC channel1 DMA underrun flag + 13 + 1 + read-write + + + CAL_FLAG1 + DAC Channel 1 calibration offset status + 14 + 1 + read-only + + + BWST1 + DAC Channel 1 busy writing sample time flag + 15 + 1 + read-only + + + DAC2RDY + DAC channel 2 ready status bit + 27 + 1 + read-only + + + DORSTAT2 + DAC channel 2 output register status bit + 28 + 1 + read-only + + + DMAUDR2 + DAC channel2 DMA underrun flag + 29 + 1 + read-write + + + CAL_FLAG2 + DAC Channel 2 calibration offset status + 30 + 1 + read-only + + + BWST2 + DAC Channel 2 busy writing sample time flag + 31 + 1 + read-only + + + + + DAC_CCR + DAC_CCR + DAC calibration control register + 0x38 + 0x20 + read-write + 0x00000000 + + + OTRIM1 + DAC Channel 1 offset trimming value + 0 + 5 + + + OTRIM2 + DAC Channel 2 offset trimming value + 16 + 5 + + + + + DAC_MCR + DAC_MCR + DAC mode control register + 0x3C + 0x20 + read-write + 0x00000000 + + + MODE1 + DAC Channel 1 mode + 0 + 3 + + + DMADOUBLE1 + DAC Channel1 DMA double data mode + 8 + 1 + + + SINFORMAT1 + Enable signed format for DAC channel1 + 9 + 1 + + + HFSEL + High frequency interface mode selection + 14 + 2 + + + MODE2 + DAC Channel 2 mode + 16 + 3 + + + DMADOUBLE2 + DAC Channel2 DMA double data mode + 24 + 1 + + + SINFORMAT2 + Enable signed format for DAC channel2 + 25 + 1 + + + + + DAC_SHSR1 + DAC_SHSR1 + DAC Sample and Hold sample time register 1 + 0x40 + 0x20 + read-write + 0x00000000 + + + TSAMPLE1 + DAC Channel 1 sample Time (only valid in sample &amp; hold mode) + 0 + 10 + + + + + DAC_SHSR2 + DAC_SHSR2 + DAC channel2 sample and hold sample time register + 0x44 + 0x20 + read-write + 0x00000000 + + + TSAMPLE2 + DAC Channel 2 sample Time (only valid in sample and hold mode) + 0 + 10 + + + + + DAC_SHHR + DAC_SHHR + DAC Sample and Hold hold time register + 0x48 + 0x20 + read-write + 0x00010001 + + + THOLD1 + DAC Channel 1 hold Time (only valid in sample and hold mode) + 0 + 10 + + + THOLD2 + DAC Channel 2 hold time (only valid in sample and hold mode) + 16 + 10 + + + + + DAC_SHRR + DAC_SHRR + DAC Sample and Hold refresh time register + 0x4C + 0x20 + read-write + 0x00010001 + + + TREFRESH1 + DAC Channel 1 refresh Time (only valid in sample and hold mode) + 0 + 8 + + + TREFRESH2 + DAC Channel 2 refresh Time (only valid in sample and hold mode) + 16 + 8 + + + + + DAC_AUTOCR + DAC_AUTOCR + Autonomous mode control register + 0x54 + 0x20 + read-write + 0x00000000 + + + AUTOMODE + DAC Autonomous mode + 22 + 1 + + + + + + + SEC_DAC1 + DCB->DSCSR->CDS == 0 + 0x56021800 + + + DBGMCU + MCU debug component + DBGMCU + 0xE0044000 + + 0x0 + 0x1000 + registers + + + + IDCODE + IDCODE + DBGMCU_IDCODE + 0x0 + 0x20 + read-only + 0x30016481 + + + DEV_ID + Device dentification + 0 + 12 + + + REV_ID + Revision + 16 + 16 + + + + + CR + CR + Debug MCU configuration + register + 0x4 + 0x20 + read-write + 0x00000000 + + + DBG_STOP + Debug Stop mode + 1 + 1 + + + DBG_STANDBY + Debug Standby mode + 2 + 1 + + + TRACE_IOEN + Trace pin assignment + control + 4 + 1 + + + TRACE_EN + trace port and clock + enable + 5 + 1 + + + TRACE_MODE + Trace pin assignment + control + 6 + 2 + + + + + APB1LFZR + APB1LFZR + Debug MCU APB1L peripheral freeze + register + 0x8 + 0x20 + read-write + 0x00000000 + + + DBG_TIM2_STOP + TIM2 stop in debug + 0 + 1 + + + DBG_TIM3_STOP + TIM3 stop in debug + 1 + 1 + + + DBG_TIM4_STOP + TIM4 stop in debug + 2 + 1 + + + DBG_TIM5_STOP + TIM5 stop in debug + 3 + 1 + + + DBG_TIM6_STOP + TIM6 stop in debug + 4 + 1 + + + DBG_TIM7_STOP + TIM7 stop in debug + 5 + 1 + + + DBG_WWDG_STOP + Window watchdog counter stop in debug + 11 + 1 + + + DBG_IWDG_STOP + Independent watchdog counter stop in debug + 12 + 1 + + + DBG_I2C1_STOP + I2C1 SMBUS timeout stop in debug + 21 + 1 + + + DBG_I2C2_STOP + I2C2 SMBUS timeout stop in debug + 22 + 1 + + + + + APB1HFZR + APB1HFZR + Debug MCU APB1H peripheral freeze register + 0xC + 0x20 + read-write + 0x00000000 + + + DBG_I2C4_STOP + I2C4 stop in debug + 1 + 1 + + + DBG_LPTIM2_STOP + LPTIM2 stop in debug + 5 + 1 + + + + + APB2FZR + APB2FZR + Debug MCU APB2 peripheral freeze register + 0x10 + 0x20 + read-write + 0x00000000 + + + DBG_TIM1_STOP + TIM1 counter stopped when core is + halted + 11 + 1 + + + DBG_TIM8_STOP + TIM8 stop in debug + 13 + 1 + + + DBG_TIM15_STOP + TIM15 counter stopped when core is + halted + 16 + 1 + + + DBG_TIM16_STOP + TIM16 counter stopped when core is + halted + 17 + 1 + + + DBG_TIM17_STOP + DBG_TIM17_STOP + 18 + 1 + + + + + APB3FZR + APB3FZR + Debug MCU APB3 peripheral freeze register + 0x14 + 0x20 + read-write + 0x00000000 + + + DBG_I2C3_STOP + I2C3 stop in debug + 10 + 1 + + + DBG_LPTIM1_STOP + LPTIM1 stop in debug + 17 + 1 + + + DBG_LPTIM3_STOP + LPTIM3 stop in debug + 18 + 1 + + + DBG_LPTIM4_STOP + LPTIM4 stop in debug + 19 + 1 + + + DBG_RTC_STOP + RTC stop in debug + 30 + 1 + + + + + AHB1FZR + AHB1FZR + Debug MCU AHB1 peripheral freeze register + 0x20 + 0x20 + read-write + 0x00000000 + + + DBG_GPDMA0_STOP + GPDMA channel 0 stop in debug + 0 + 1 + + + DBG_GPDMA1_STOP + GPDMA channel 1 stop in debug + 1 + 1 + + + DBG_GPDMA2_STOP + GPDMA channel 2 stop in debug + 2 + 1 + + + DBG_GPDMA3_STOP + GPDMA channel 3 stop in debug + 3 + 1 + + + DBG_GPDMA4_STOP + GPDMA channel 4 stop in debug + 4 + 1 + + + DBG_GPDMA5_STOP + GPDMA channel 5 stop in debug + 5 + 1 + + + DBG_GPDMA6_STOP + GPDMA channel 6 stop in debug + 6 + 1 + + + DBG_GPDMA7_STOP + GPDMA channel 7 stop in debug + 7 + 1 + + + DBG_GPDMA8_STOP + GPDMA channel 8 stop in debug + 8 + 1 + + + DBG_GPDMA9_STOP + GPDMA channel 9 stop in debug + 9 + 1 + + + DBG_GPDMA10_STOP + GPDMA channel 10 stop in debug + 10 + 1 + + + DBG_GPDMA11_STOP + GPDMA channel 11 stop in debug + 11 + 1 + + + DBG_GPDMA12_STOP + GPDMA channel 12 stop in debug + 12 + 1 + + + DBG_GPDMA13_STOP + GPDMA channel 13 stop in debug + 13 + 1 + + + DBG_GPDMA14_STOP + GPDMA channel 14 stop in debug + 14 + 1 + + + DBG_GPDMA15_STOP + GPDMA channel 15 stop in debug + 15 + 1 + + + + + AHB3FZR + AHB3FZR + Debug MCU AHB3 peripheral freeze register + 0x28 + 0x20 + read-write + 0x00000000 + + + DBG_LPDMA0_STOP + LPDMA channel 0 stop in debug + 0 + 1 + + + DBG_LPDMA1_STOP + LPDMA channel 1 stop in debug + 1 + 1 + + + DBG_LPDMA2_STOP + LPDMA channel 2 stop in debug + 2 + 1 + + + DBG_LPDMA3_STOP + LPDMA channel 3 stop in debug + 3 + 1 + + + + + SR + SR + DBGMCU status register + 0xFC + 0x20 + read-only + 0x00000001 + + + AP_PRESENT + AP_PRESENT + 0 + 8 + + + AP_LOCKED + AP_LOCKED + 8 + 8 + + + + + DBGMCU_DBG_AUTH_HOST + DBGMCU_DBG_AUTH_HOST + DBGMCU debug host authentication register + 0x100 + 0x20 + read-only + 0x00000000 + + + AUTH_KEY + AUTH_KEY + 0 + 32 + + + + + DBG_AUTH_DEVICE + DBG_AUTH_DEVICE + DBGMCU debug device authentication register + 0x104 + 0x20 + read-only + 0x00000000 + + + AUTH_ID + AUTH_ID + 0 + 16 + + + + + PIDR4 + PIDR4 + Debug MCU CoreSight peripheral identity register 4 + 0xFD0 + 0x20 + read-only + 0x00000000 + + + JEP106CON + JEP106 continuation code + 0 + 4 + + + KCOUNT_4 + register file size + 4 + 4 + + + + + PIDR0 + PIDR0 + Debug MCU CoreSight peripheral identity register 0 + 0xFE0 + 0x20 + read-only + 0x00000000 + + + PARTNUM + part number bits [7:0] + 0 + 8 + + + + + PIDR1 + PIDR1 + Debug MCU CoreSight peripheral identity register 1 + 0xFE4 + 0x20 + read-only + 0x00000000 + + + PARTNUM + part number bits [11:8] + 0 + 4 + + + JEP106ID + JEP106 identity code bits [3:0] + 4 + 4 + + + + + PIDR2 + PIDR2 + Debug MCU CoreSight peripheral identity register 2 + 0xFE8 + 0x20 + read-only + 0x0000000A + + + JEP106ID + JEP106 identity code bits [6:4] + 0 + 3 + + + JEDEC + JEDEC assigned value + 3 + 1 + + + REVISION + component revision number + 4 + 4 + + + + + PIDR3 + PIDR3 + Debug MCU CoreSight peripheral identity register 3 + 0xFEC + 0x20 + read-only + 0x00000000 + + + CMOD + customer modified + 0 + 4 + + + REVAND + metal fix version + 4 + 4 + + + + + CIDR0 + CIDR0 + Debug MCU CoreSight component identity register 0 + 0xFF0 + 0x20 + read-only + 0x0000000D + + + PREAMBLE + component identification bits [7:0] + 0 + 8 + + + + + CIDR1 + CIDR1 + Debug MCU CoreSight component identity register 1 + 0xFF4 + 0x20 + read-only + 0x000000F0 + + + PREAMBLE + component identification bits [11:8] + 0 + 4 + + + CLASS + component identification bits [15:12] - component class + 4 + 4 + + + + + CIDR2 + CIDR2 + Debug MCU CoreSight component identity register 2 + 0xFF8 + 0x20 + read-only + 0x00000005 + + + PREAMBLE + component identification bits [23:16] + 0 + 8 + + + + + CIDR3 + CIDR3 + Debug MCU CoreSight component identity register 3 + 0xFFC + 0x20 + read-only + 0x000000B1 + + + PREAMBLE + component identification bits [31:24] + 0 + 8 + + + + + + + DCACHE1 + DCACHE1 + DCACHE + 0x40031400 + + 0x0 + 0x400 + registers + + + DCACHE1 + Data cache global interrupt + 111 + + + + DCACHE_CR + DCACHE_CR + DCACHE control register + 0x0 + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + CACHEINV + CACHEINV + 1 + 1 + write-only + + + CACHECMD + CACHECMD + 8 + 3 + read-write + + + STARTCMD + STARTCMD + 11 + 1 + write-only + + + RHITMEN + RHITMEN + 16 + 1 + read-write + + + RMISSMEN + RMISSMEN + 17 + 1 + read-write + + + RHITMRST + RHITMRST + 18 + 1 + read-write + + + RMISSMRST + RMISSMRST + 19 + 1 + read-write + + + WHITMEN + WHITMEN + 20 + 1 + read-write + + + WMISSMEN + WMISSMEN + 21 + 1 + read-write + + + WHITMRST + WHITMRST + 22 + 1 + read-write + + + WMISSMRST + WMISSMRST + 23 + 1 + read-write + + + HBURST + HBURST + 31 + 1 + read-write + + + + + DCACHE_SR + DCACHE_SR + DCACHE status register + 0x4 + 0x20 + read-only + 0x00000001 + + + BUSYF + BUSYF + 0 + 1 + + + BSYENDF + BSYENDF + 1 + 1 + + + ERRF + ERRF + 2 + 1 + + + BUSYCMDF + BUSYCMDF + 3 + 1 + + + CMDENDF + CMDENDF + 4 + 1 + + + + + DCACHE_IER + DCACHE_IER + DCACHE interrupt enable + register + 0x8 + 0x20 + read-write + 0x00000000 + + + BSYENDIE + BSYENDIE + 1 + 1 + + + ERRIE + ERRIE + 2 + 1 + + + CMDENDIE + CMDENDIE + 4 + 1 + + + + + DCACHE_FCR + DCACHE_FCR + DCACHE flag clear register + 0xC + 0x20 + write-only + 0x00000000 + + + CBSYENDF + CBSYENDF + 1 + 1 + + + CERRF + CERRF + 2 + 1 + + + CCMDENDF + CCMDENDF + 4 + 1 + + + + + DCACHE_RHMONR + DCACHE_RHMONR + DCACHE read-hit monitor register + 0x10 + 0x20 + read-only + 0x00000000 + + + RHITMON + RHITMON + 0 + 32 + + + + + DCACHE_RMMONR + DCACHE_RMMONR + DCACHE read-miss monitor register + 0x14 + 0x20 + read-only + 0x00000000 + + + MRISSMON + RMISSMON + 0 + 16 + + + + + DCACHE_WHMONR + DCACHE_WHMONR + write-hit monitor register + 0x020 + 0x20 + read-only + 0x00000000 + + + WHITMON + WHITMON + 0 + 32 + + + + + DCACHE_WMMONR + DCACHE_WMMONR + write-miss monitor register + 0x024 + 0x20 + read-only + 0x00000000 + + + WMISSMON + WMISSMON + 0 + 16 + + + + + DCACHE_CMDRSADDRR + DCACHE_CMDRSADDRR + command range start address register + 0x028 + 0x20 + read-write + 0x00000000 + + + CMDSTARTADDR + CMDSTARTADDR + 4 + 28 + + + + + DCACHE_CMDREADDRR + DCACHE_CMDREADDRR + command range start address register + 0x02C + 0x20 + read-write + 0x00000000 + + + CMDENDADDR + CMDENDADDR + 4 + 28 + + + + + + + SEC_DCACHE1 + DCB->DSCSR->CDS == 0 + 0x50031400 + + + DCACHE2 + 0x40031800 + + DCACHE2 + Data cache 2 global interrupt + 138 + + + + SEC_DCACHE2 + DCB->DSCSR->CDS == 0 + 0x50031800 + + + DCMI + Digital camera interface + DCMI + 0x4202C000 + + 0x0 + 0x400 + registers + + + DCMI_PSSI + DCMI/PSSI global interrupt + 119 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + OELS + Odd/Even Line Select (Line Select Start) + 20 + 1 + + + LSM + Line Select mode + 19 + 1 + + + OEBS + Odd/Even Byte Select (Byte Select Start) + 18 + 1 + + + BSM + Byte Select mode + 16 + 2 + + + ENABLE + DCMI enable + 14 + 1 + + + EDM + Extended data mode + 10 + 2 + + + FCRC + Frame capture rate control + 8 + 2 + + + VSPOL + Vertical synchronization polarity + 7 + 1 + + + HSPOL + Horizontal synchronization polarity + 6 + 1 + + + PCKPOL + Pixel clock polarity + 5 + 1 + + + ESS + Embedded synchronization select + 4 + 1 + + + JPEG + JPEG format + 3 + 1 + + + CROP + Crop feature + 2 + 1 + + + CM + Capture mode + 1 + 1 + + + CAPTURE + Capture enable + 0 + 1 + + + + + SR + SR + status register + 0x4 + 0x20 + read-only + 0x00000000 + + + FNE + FIFO not empty + 2 + 1 + + + VSYNC + Vertical synchronization + 1 + 1 + + + HSYNC + Horizontal synchronization + 0 + 1 + + + + + RIS + RIS + raw interrupt status register + 0x8 + 0x20 + read-only + 0x00000000 + + + LINE_RIS + Line raw interrupt status + 4 + 1 + + + VSYNC_RIS + DCMI_VSYNC raw interrupt status + 3 + 1 + + + ERR_RIS + Synchronization error raw interrupt status + 2 + 1 + + + OVR_RIS + Overrun raw interrupt status + 1 + 1 + + + FRAME_RIS + Capture complete raw interrupt status + 0 + 1 + + + + + IER + IER + interrupt enable register + 0xC + 0x20 + read-write + 0x00000000 + + + LINE_IE + Line interrupt enable + 4 + 1 + + + VSYNC_IE + DCMI_VSYNC interrupt enable + 3 + 1 + + + ERR_IE + Synchronization error interrupt enable + 2 + 1 + + + OVR_IE + Overrun interrupt enable + 1 + 1 + + + FRAME_IE + Capture complete interrupt enable + 0 + 1 + + + + + MIS + MIS + masked interrupt status register + 0x10 + 0x20 + read-only + 0x00000000 + + + LINE_MIS + Line masked interrupt status + 4 + 1 + + + VSYNC_MIS + VSYNC masked interrupt status + 3 + 1 + + + ERR_MIS + Synchronization error masked interrupt status + 2 + 1 + + + OVR_MIS + Overrun masked interrupt status + 1 + 1 + + + FRAME_MIS + Capture complete masked interrupt status + 0 + 1 + + + + + ICR + ICR + interrupt clear register + 0x14 + 0x20 + write-only + 0x00000000 + + + LINE_ISC + line interrupt status clear + 4 + 1 + + + VSYNC_ISC + Vertical Synchronization interrupt status clear + 3 + 1 + + + ERR_ISC + Synchronization error interrupt status clear + 2 + 1 + + + OVR_ISC + Overrun interrupt status clear + 1 + 1 + + + FRAME_ISC + Capture complete interrupt status clear + 0 + 1 + + + + + ESCR + ESCR + background offset register + 0x18 + 0x20 + read-write + 0x00000000 + + + FEC + Frame end delimiter code + 24 + 8 + + + LEC + Line end delimiter code + 16 + 8 + + + LSC + Line start delimiter code + 8 + 8 + + + FSC + Frame start delimiter code + 0 + 8 + + + + + ESUR + ESUR + embedded synchronization unmask register + 0x1C + 0x20 + read-write + 0x00000000 + + + FEU + Frame end delimiter unmask + 24 + 8 + + + LEU + Line end delimiter unmask + 16 + 8 + + + LSU + Line start delimiter unmask + 8 + 8 + + + FSU + Frame start delimiter unmask + 0 + 8 + + + + + CWSTRT + CWSTRT + crop window start + 0x20 + 0x20 + read-write + 0x00000000 + + + VST + Vertical start line count + 16 + 13 + + + HOFFCNT + Horizontal offset count + 0 + 14 + + + + + CWSIZE + CWSIZE + crop window size + 0x24 + 0x20 + read-write + 0x00000000 + + + VLINE + Vertical line count + 16 + 14 + + + CAPCNT + Capture count + 0 + 14 + + + + + DR + DR + data register + 0x28 + 0x20 + read-only + 0x00000000 + + + BYTE3 + Data byte 3 + 24 + 8 + + + BYTE2 + Data byte 2 + 16 + 8 + + + BYTE1 + Data byte 1 + 8 + 8 + + + BYTE0 + Data byte 0 + 0 + 8 + + + + + + + SEC_DCMI + DCB->DSCSR->CDS == 0 + 0x5202C000 + + + DLYBOS1 + The delay block (DLYB) is used to generate an output clock that is dephased from the input clock + DLYB + 0x420CF000 + + 0x0 + 0x400 + registers + + + + DLYB_CR + DLYB_CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + DEN + Operational amplifier Enable + 0 + 1 + + + SEN + OPALPM + 1 + 1 + + + + + DLYB_CFGR + DLYB_CFGR + configuration register + 0x4 + 0x20 + 0x00000000 + + + SEL + SEL + 0 + 4 + read-write + + + UNIT + UNIT + 8 + 7 + read-write + + + LNG + LNG + 16 + 12 + read-only + + + LNGF + LNGF + 31 + 1 + read-only + + + + + + + SEC_DLYBOS1 + DCB->DSCSR->CDS == 0 + 0x520CF000 + + + DLYBOS2 + 0x420CF400 + + + SEC_DLYBOS2 + DCB->DSCSR->CDS == 0 + 0x520CF400 + + + DLYBSD1 + 0x420C8400 + + + SEC_DLYBSD1 + DCB->DSCSR->CDS == 0 + 0x520C8400 + + + DLYBSD2 + 0x420C8800 + + + SEC_DLYBSD2 + DCB->DSCSR->CDS == 0 + 0x520C8800 + + + DMA2D + DMA2D controller + DMA2D + 0x4002B000 + + 0x0 + 0xC00 + registers + + + DMA2D + DMA2D global interrupt + 118 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + MODE + DMA2D mode + 16 + 3 + + + CEIE + Configuration Error Interrupt + Enable + 13 + 1 + + + CTCIE + CLUT transfer complete interrupt enable + 12 + 1 + + + CAEIE + CLUT access error interrupt enable + 11 + 1 + + + TWIE + Transfer watermark interrupt enable + 10 + 1 + + + TCIE + Transfer complete interrupt enable + 9 + 1 + + + TEIE + Transfer error interrupt enable + 8 + 1 + + + LOM + Line Offset Mode + 6 + 1 + + + ABORT + Abort + 2 + 1 + + + SUSP + Suspend + 1 + 1 + + + START + Start + 0 + 1 + + + + + ISR + ISR + Interrupt Status Register + 0x4 + 0x20 + read-only + 0x00000000 + + + CEIF + Configuration error interrupt flag + 5 + 1 + + + CTCIF + CLUT transfer complete interrupt flag + 4 + 1 + + + CAEIF + CLUT access error interrupt flag + 3 + 1 + + + TWIF + Transfer watermark interrupt flag + 2 + 1 + + + TCIF + Transfer complete interrupt flag + 1 + 1 + + + TEIF + Transfer error interrupt flag + 0 + 1 + + + + + IFCR + IFCR + interrupt flag clear register + 0x8 + 0x20 + read-write + 0x00000000 + + + CCEIF + Clear configuration error interrupt flag + 5 + 1 + + + CCTCIF + Clear CLUT transfer complete interrupt flag + 4 + 1 + + + CAECIF + Clear CLUT access error interrupt flag + 3 + 1 + + + CTWIF + Clear transfer watermark interrupt flag + 2 + 1 + + + CTCIF + Clear transfer complete interrupt flag + 1 + 1 + + + CTEIF + Clear Transfer error interrupt flag + 0 + 1 + + + + + FGMAR + FGMAR + foreground memory address register + 0xC + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + FGOR + FGOR + foreground offset register + 0x10 + 0x20 + read-write + 0x00000000 + + + LO + Line offset + 0 + 16 + + + + + BGMAR + BGMAR + background memory address register + 0x14 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + BGOR + BGOR + background offset register + 0x18 + 0x20 + read-write + 0x00000000 + + + LO + Line offset + 0 + 16 + + + + + FGPFCCR + FGPFCCR + foreground PFC control register + 0x1C + 0x20 + read-write + 0x00000000 + + + ALPHA + Alpha value + 24 + 8 + + + RBS + Red Blue Swap + 21 + 1 + + + AI + Alpha Inverted + 20 + 1 + + + AM + Alpha mode + 16 + 2 + + + CS + CLUT size + 8 + 8 + + + START + Start + 5 + 1 + + + CCM + CLUT color mode + 4 + 1 + + + CM + Color mode + 0 + 4 + + + + + FGCOLR + FGCOLR + foreground color register + 0x20 + 0x20 + read-write + 0x00000000 + + + RED + Red Value + 16 + 8 + + + GREEN + Green Value + 8 + 8 + + + BLUE + Blue Value + 0 + 8 + + + + + BGPFCCR + BGPFCCR + background PFC control + register + 0x24 + 0x20 + read-write + 0x00000000 + + + ALPHA + Alpha value + 24 + 8 + + + RBS + Red Blue Swap + 21 + 1 + + + AI + Alpha Inverted + 20 + 1 + + + AM + Alpha mode + 16 + 2 + + + CS + CLUT size + 8 + 8 + + + START + Start + 5 + 1 + + + CCM + CLUT Color mode + 4 + 1 + + + CM + Color mode + 0 + 4 + + + + + BGCOLR + BGCOLR + background color register + 0x28 + 0x20 + read-write + 0x00000000 + + + RED + Red Value + 16 + 8 + + + GREEN + Green Value + 8 + 8 + + + BLUE + Blue Value + 0 + 8 + + + + + FGCMAR + FGCMAR + foreground CLUT memory address + register + 0x2C + 0x20 + read-write + 0x00000000 + + + MA + Memory Address + 0 + 32 + + + + + BGCMAR + BGCMAR + background CLUT memory address + register + 0x30 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + OPFCCR + OPFCCR + output PFC control register + 0x34 + 0x20 + read-write + 0x00000000 + + + RBS + Red Blue Swap + 21 + 1 + + + AI + Alpha Inverted + 20 + 1 + + + SB + Swap Bytes + 9 + 1 + + + CM + Color mode + 0 + 3 + + + + + OCOLR_RGB888 + OCOLR_RGB888 + output color register + 0x38 + 0x20 + read-write + 0x00000000 + + + APLHA + Alpha Channel Value + 24 + 8 + + + RED + Red Value + 16 + 8 + + + GREEN + Green Value + 8 + 8 + + + BLUE + Blue Value + 0 + 8 + + + + + OCOLR_RGB565 + OCOLR_RGB565 + output color register + OCOLR_RGB888 + 0x38 + 0x20 + read-write + 0x00000000 + + + RED + Red value in RGB565 mode + 11 + 5 + + + GREEN + Green value in RGB565 mode + 5 + 6 + + + BLUE + Blue value in RGB565 mode + 0 + 5 + + + + + OCOLR_ARGB1555 + OCOLR_ARGB1555 + output color register + OCOLR_RGB888 + 0x38 + 0x20 + read-write + 0x00000000 + + + A + Alpha channel value in ARGB1555 mode + 15 + 1 + + + RED + Red value in ARGB1555 mode + 10 + 5 + + + GREEN + Green value in ARGB1555 mode + 5 + 5 + + + BLUE + Blue value in ARGB1555 mode + 0 + 5 + + + + + OCOLR_ARGB4444 + OCOLR_ARGB4444 + output color register + OCOLR_RGB888 + 0x38 + 0x20 + read-write + 0x00000000 + + + ALPHA + Alpha channel value in ARGB4444 + 12 + 4 + + + RED + Red value in ARGB4444 mode + 8 + 4 + + + GREEN + Green value in ARGB4444 mode + 4 + 4 + + + BLUE + Blue value in ARGB4444 mode + 0 + 4 + + + + + OMAR + OMAR + output memory address register + 0x3C + 0x20 + read-write + 0x00000000 + + + MA + Memory Address + 0 + 32 + + + + + OOR + OOR + output offset register + 0x40 + 0x20 + read-write + 0x00000000 + + + LO + Line Offset + 0 + 16 + + + + + NLR + NLR + number of line register + 0x44 + 0x20 + read-write + 0x00000000 + + + PL + Pixel per lines + 16 + 14 + + + NL + Number of lines + 0 + 16 + + + + + LWR + LWR + line watermark register + 0x48 + 0x20 + read-write + 0x00000000 + + + LW + Line watermark + 0 + 16 + + + + + AMTCR + AMTCR + AHB master timer configuration + register + 0x4C + 0x20 + read-write + 0x00000000 + + + DT + Dead Time + 8 + 8 + + + EN + Enable + 0 + 1 + + + + + FGCLUT + FGCLUT + FGCLUT + 0x400 + 0x20 + read-write + 0x00000000 + + + APLHA + APLHA + 24 + 8 + + + RED + RED + 16 + 8 + + + GREEN + GREEN + 8 + 8 + + + BLUE + BLUE + 0 + 8 + + + + + BGCLUT + BGCLUT + BGCLUT + 0x800 + 0x20 + read-write + 0x00000000 + + + APLHA + APLHA + 24 + 8 + + + RED + RED + 16 + 8 + + + GREEN + GREEN + 8 + 8 + + + BLUE + BLUE + 0 + 8 + + + + + + + SEC_DMA2D + DCB->DSCSR->CDS == 0 + 0x5002B000 + + + DSI + DSI + DSI + 0x40016C00 + + 0x0 + 0x1000 + registers + + + DSIHOST + DSI global interrupt + 137 + + + + DSI_VR + DSI_VR + DSI Host version register + 0x0 + 0x20 + 0x3134312A + 0xFFFFFFFF + + + VERSION + Version of the DSI Host +This read-only register contains the version of the DSI Host + 0 + 32 + read-only + + + + + DSI_CR + DSI_CR + DSI Host control register + 0x4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +This bit configures the DSI Host in either power-up mode or to reset. + 0 + 1 + read-write + + + B_0x0 + DSI Host disabled (under reset) + 0x0 + + + B_0x1 + DSI Host enabled + 0x1 + + + + + + + DSI_CCR + DSI_CCR + DSI Host clock control register + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TXECKDIV + TX escape clock division +This field indicates the division factor for the TX escape clock source (lanebyteclk). The values 0 and 1 stop the TX_ESC clock generation. + 0 + 8 + read-write + + + TOCKDIV + Timeout clock division +This field indicates the division factor for the timeout clock used as the timing unit in the configuration of HS to LP and LP to HS transition error. + 8 + 8 + read-write + + + + + DSI_LVCIDR + DSI_LVCIDR + DSI Host LTDC VCID register + 0xc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + VCID + Virtual channel ID +These bits configure the virtual channel ID for the LTDC interface traffic. + 0 + 2 + read-write + + + + + DSI_LCOLCR + DSI_LCOLCR + DSI Host LTDC color coding register + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + COLC + Color coding +This field configures the DPI color coding. +Others: Reserved + 0 + 4 + read-write + + + B_0x0 + 16-bit configuration 1 + 0x0 + + + B_0x1 + 16-bit configuration 2 + 0x1 + + + B_0x2 + 16-bit configuration 3 + 0x2 + + + B_0x3 + 18-bit configuration 1 + 0x3 + + + B_0x4 + 18-bit configuration 2 + 0x4 + + + B_0x5 + 24-bit + 0x5 + + + + + LPE + Loosely packet enable +This bit enables the loosely packed variant to 18-bit configuration + 8 + 1 + read-write + + + B_0x0 + Loosely packet variant disabled + 0x0 + + + B_0x1 + Loosely packet variant enabled + 0x1 + + + + + + + DSI_LPCR + DSI_LPCR + DSI Host LTDC polarity configuration register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DEP + Data enable polarity +This bit configures the polarity of data enable pin. + 0 + 1 + read-write + + + B_0x0 + Data enable pin active high (default) + 0x0 + + + B_0x1 + Data enable pin active low + 0x1 + + + + + VSP + VSYNC polarity +This bit configures the polarity of VSYNC pin. + 1 + 1 + read-write + + + B_0x0 + Shutdown pin active high (default) + 0x0 + + + B_0x1 + Shutdown pin active low + 0x1 + + + + + HSP + HSYNC polarity +This bit configures the polarity of HSYNC pin. + 2 + 1 + read-write + + + B_0x0 + HSYNC pin active high (default) + 0x0 + + + B_0x1 + VSYNC pin active low + 0x1 + + + + + + + DSI_LPMCR + DSI_LPMCR + DSI Host low-power mode configuration register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + VLPSIZE + VACT largest packet size +This field is used for the transmission of commands in low-power mode. It defines the size, in bytes, of the largest packet that can fit in a line during VACT regions. + 0 + 8 + read-write + + + LPSIZE + Largest packet size +This field is used for the transmission of commands in low-power mode. It defines the size, in bytes, of the largest packet that can fit in a line during VSA, VBP and VFP regions. + 16 + 8 + read-write + + + + + DSI_PCR + DSI_PCR + DSI Host protocol configuration register + 0x2c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ETTXE + EoTp transmission enable +This bit enables the EoTP transmission. + 0 + 1 + read-write + + + B_0x0 + EoTp transmission is disabled. + 0x0 + + + B_0x1 + EoTp transmission is enabled. + 0x1 + + + + + ETRXE + EoTp reception enable +This bit enables the EoTp reception. + 1 + 1 + read-write + + + B_0x0 + EoTp reception is disabled. + 0x0 + + + B_0x1 + EoTp reception is enabled. + 0x1 + + + + + BTAE + Bus-turn-around enable +This bit enables the bus-turn-around (BTA) request. + 2 + 1 + read-write + + + B_0x0 + Bus-turn-around request is disabled. + 0x0 + + + B_0x1 + Bus-turn-around request is enabled. + 0x1 + + + + + ECCRXE + ECC reception enable +This bit enables the ECC reception, error correction and reporting. + 3 + 1 + read-write + + + B_0x0 + ECC reception is disabled. + 0x0 + + + B_0x1 + ECC reception is enabled. + 0x1 + + + + + CRCRXE + CRC reception enable +This bit enables the CRC reception and error reporting. + 4 + 1 + read-write + + + B_0x0 + CRC reception is disabled. + 0x0 + + + B_0x1 + CRC reception is enabled. + 0x1 + + + + + ETTXLPE + EoTp transmission in low-power enable +This bit enables the EoTP transmission in low-power. + 5 + 1 + read-write + + + B_0x0 + EoTp transmission in low-power is disabled. + 0x0 + + + B_0x1 + EoTp transmission in low-power is enabled. + 0x1 + + + + + + + DSI_GVCIDR + DSI_GVCIDR + DSI Host generic VCID register + 0x30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + VCIDRX + Virtual channel ID for reception +This field indicates the generic interface read-back virtual channel identification. + 0 + 2 + read-write + + + VCIDTX + Virtual channel ID for transmission +This field indicates the generic interface virtual channel identification where the generic packet is automatically generated and transmitted. + 16 + 2 + read-write + + + + + DSI_MCR + DSI_MCR + DSI Host mode configuration register + 0x34 + 0x20 + 0x00000001 + 0xFFFFFFFF + + + CMDM + Command mode +This bit configures the DSI Host in either video or command mode. + 0 + 1 + read-write + + + B_0x0 + DSI Host is configured in video mode. + 0x0 + + + B_0x1 + DSI Host is configured in command mode. + 0x1 + + + + + + + DSI_VMCR + DSI_VMCR + DSI Host video mode configuration register + 0x38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + VMT + Video mode type +This field configures the video mode transmission type : +1x: Burst mode + 0 + 2 + read-write + + + B_0x0 + Non-burst with sync pulses. + 0x0 + + + B_0x1 + Non-burst with sync events. + 0x1 + + + + + LPVSAE + Low-power vertical sync active enable +This bit enables to return to low-power inside the vertical sync time (VSA) period when timing allows. + 8 + 1 + read-write + + + B_0x0 + Return to low-power inside the VSA is disabled. + 0x0 + + + B_0x1 + Return to low-power inside the VSA is enabled + 0x1 + + + + + LPVBPE + Low-power vertical back-porch enable +This bit enables to return to low-power inside the vertical back-porch (VBP) period when timing allows. + 9 + 1 + read-write + + + B_0x0 + Return to low-power inside the VBP is disabled. + 0x0 + + + B_0x1 + Return to low-power inside the VBP is enabled. + 0x1 + + + + + LPVFPE + Low-power vertical front-porch enable +This bit enables to return to low-power inside the vertical front-porch (VFP) period when timing allows. + 10 + 1 + read-write + + + B_0x0 + Return to low-power inside the VFP is disabled. + 0x0 + + + B_0x1 + Return to low-power inside the VFP is enabled. + 0x1 + + + + + LPVAE + Low-power vertical active enable +This bit enables to return to low-power inside the vertical active (VACT) period when timing allows. + 11 + 1 + read-write + + + B_0x0 + Return to low-power inside the VACT is disabled. + 0x0 + + + B_0x1 + Return to low-power inside the VACT is enabled. + 0x1 + + + + + LPHBPE + Low-power horizontal back-porch enable +This bit enables the return to low-power inside the horizontal back-porch (HBP) period when timing allows. + 12 + 1 + read-write + + + B_0x0 + Return to low-power inside the HBP period is disabled. + 0x0 + + + B_0x1 + Return to low-power inside the HBP period is enabled. + 0x1 + + + + + LPHFPE + Low-power horizontal front-porch enable +This bit enables the return to low-power inside the horizontal front-porch (HFP) period when timing allows. + 13 + 1 + read-write + + + B_0x0 + Return to low-power inside the HFP period is disabled. + 0x0 + + + B_0x1 + Return to low-power inside the HFP period is enabled. + 0x1 + + + + + FBTAAE + Frame bus-turn-around acknowledge enable +This bit enables the request for an acknowledge response at the end of a frame. + 14 + 1 + read-write + + + B_0x0 + Acknowledge response at the end of a frame is disabled. + 0x0 + + + B_0x1 + Acknowledge response at the end of a frame is enabled. + 0x1 + + + + + LPCE + Low-power command enable +This bit enables the command transmission only in low-power mode. + 15 + 1 + read-write + + + B_0x0 + Command transmission in low-power mode is disabled. + 0x0 + + + B_0x1 + Command transmission in low-power mode is enabled. + 0x1 + + + + + PGE + Pattern generator enable +This bit enables the video mode pattern generator. + 16 + 1 + read-write + + + B_0x0 + Pattern generator is disabled. + 0x0 + + + B_0x1 + Pattern generator is enabled. + 0x1 + + + + + PGM + Pattern generator mode +This bit configures the pattern generator mode. + 20 + 1 + read-write + + + B_0x0 + Color bars (horizontal or vertical). + 0x0 + + + B_0x1 + BER pattern (vertical only). + 0x1 + + + + + PGO + Pattern generator orientation +This bit configures the color bar orientation. + 24 + 1 + read-write + + + B_0x0 + Vertical color bars. + 0x0 + + + B_0x1 + Horizontal color bars. + 0x1 + + + + + + + DSI_VPCR + DSI_VPCR + DSI Host video packet configuration register + 0x3c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + VPSIZE + Video packet size +This field configures the number of pixels in a single video packet. +For 18-bit not loosely packed data types, this number must be a multiple of 4. +For YCbCr data types, it must be a multiple of 2 as described in the DSI specification. + 0 + 14 + read-write + + + + + DSI_VCCR + DSI_VCCR + DSI Host video chunks configuration register + 0x40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NUMC + Number of chunks +This register configures the number of chunks to be transmitted during a line period (a chunk consists of a video packet and a null packet). +If set to 0 or 1, the video line is transmitted in a single packet. +If set to 1, the packet is part of a chunk, so a null packet follows it if NPSIZE > 0. Otherwise, multiple chunks are used to transmit each video line. + 0 + 13 + read-write + + + + + DSI_VNPCR + DSI_VNPCR + DSI Host video null packet configuration register + 0x44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NPSIZE + Null packet size +This field configures the number of bytes inside a null packet. +Setting to 0 disables the null packets. + 0 + 13 + read-write + + + + + DSI_VHSACR + DSI_VHSACR + DSI Host video HSA configuration register + 0x48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + HSA + Horizontal synchronism active duration +This fields configures the horizontal synchronism active period in lane byte clock cycles. + 0 + 12 + read-write + + + + + DSI_VHBPCR + DSI_VHBPCR + DSI Host video HBP configuration register + 0x4c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + HBP + Horizontal back-porch duration +This fields configures the horizontal back-porch period in lane byte clock cycles. + 0 + 12 + read-write + + + + + DSI_VLCR + DSI_VLCR + DSI Host video line configuration register + 0x50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + HLINE + Horizontal line duration +This fields configures the total of the horizontal line period (HSA+HBP+HACT+HFP) counted in lane byte clock cycles. + 0 + 15 + read-write + + + + + DSI_VVSACR + DSI_VVSACR + DSI Host video VSA configuration register + 0x54 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + VSA + Vertical synchronism active duration +This fields configures the vertical synchronism active period measured in number of horizontal lines. + 0 + 10 + read-write + + + + + DSI_VVBPCR + DSI_VVBPCR + DSI Host video VBP configuration register + 0x58 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + VBP + Vertical back-porch duration +This fields configures the vertical back-porch period measured in number of horizontal lines. + 0 + 10 + read-write + + + + + DSI_VVFPCR + DSI_VVFPCR + DSI Host video VFP configuration register + 0x5c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + VFP + Vertical front-porch duration +This fields configures the vertical front-porch period measured in number of horizontal lines. + 0 + 10 + read-write + + + + + DSI_VVACR + DSI_VVACR + DSI Host video VA configuration register + 0x60 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + VA + Vertical active duration +This fields configures the vertical active period measured in number of horizontal lines. + 0 + 14 + read-write + + + + + DSI_LCCR + DSI_LCCR + DSI Host LTDC command configuration register + 0x64 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CMDSIZE + Command size +This field configures the maximum allowed size for an LTDC write memory command, measured in pixels. Automatic partitioning of data obtained from LTDC is permanently enabled. + 0 + 16 + read-write + + + + + DSI_CMCR + DSI_CMCR + DSI Host command mode configuration register + 0x68 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TEARE + Tearing effect acknowledge request enable +This bit enables the tearing effect acknowledge request: + 0 + 1 + read-write + + + B_0x0 + Tearing effect acknowledge request is disabled. + 0x0 + + + B_0x1 + Tearing effect acknowledge request is enabled. + 0x1 + + + + + ARE + Acknowledge request enable +This bit enables the acknowledge request after each packet transmission: + 1 + 1 + read-write + + + B_0x0 + Acknowledge request is disabled. + 0x0 + + + B_0x1 + Acknowledge request is enabled. + 0x1 + + + + + GSW0TX + Generic short write zero parameters transmission +This bit configures the generic short write packet with zero parameters command transmission type: + 8 + 1 + read-write + + + B_0x0 + High-speed + 0x0 + + + B_0x1 + Low-power + 0x1 + + + + + GSW1TX + Generic short write one parameters transmission +This bit configures the generic short write packet with one parameters command transmission type: + 9 + 1 + read-write + + + B_0x0 + High-speed + 0x0 + + + B_0x1 + Low-power + 0x1 + + + + + GSW2TX + Generic short write two parameters transmission +This bit configures the generic short write packet with two parameters command transmission type: + 10 + 1 + read-write + + + B_0x0 + High-speed + 0x0 + + + B_0x1 + Low-power + 0x1 + + + + + GSR0TX + Generic short read zero parameters transmission +This bit configures the generic short read packet with zero parameters command transmission type: + 11 + 1 + read-write + + + B_0x0 + High-speed + 0x0 + + + B_0x1 + Low-power + 0x1 + + + + + GSR1TX + Generic short read one parameters transmission +This bit configures the generic short read packet with one parameters command transmission type: + 12 + 1 + read-write + + + B_0x0 + High-speed + 0x0 + + + B_0x1 + Low-power + 0x1 + + + + + GSR2TX + Generic short read two parameters transmission +This bit configures the generic short read packet with two parameters command transmission type: + 13 + 1 + read-write + + + B_0x0 + High-speed + 0x0 + + + B_0x1 + Low-power + 0x1 + + + + + GLWTX + Generic long write transmission +This bit configures the generic long write packet command transmission type : + 14 + 1 + read-write + + + B_0x0 + High-speed + 0x0 + + + B_0x1 + Low-power + 0x1 + + + + + DSW0TX + DCS short write zero parameter transmission +This bit configures the DCS short write packet with zero parameter command transmission type: + 16 + 1 + read-write + + + B_0x0 + High-speed + 0x0 + + + B_0x1 + Low-power + 0x1 + + + + + DSW1TX + DCS short read one parameter transmission +This bit configures the DCS short read packet with one parameter command transmission type: + 17 + 1 + read-write + + + B_0x0 + High-speed + 0x0 + + + B_0x1 + Low-power + 0x1 + + + + + DSR0TX + DCS short read zero parameter transmission +This bit configures the DCS short read packet with zero parameter command transmission type: + 18 + 1 + read-write + + + B_0x0 + High-speed + 0x0 + + + B_0x1 + Low-power + 0x1 + + + + + DLWTX + DCS long write transmission +This bit configures the DCS long write packet command transmission type: + 19 + 1 + read-write + + + B_0x0 + High-speed + 0x0 + + + B_0x1 + Low-power + 0x1 + + + + + MRDPS + Maximum read packet size +This bit configures the maximum read packet size command transmission type: + 24 + 1 + read-write + + + B_0x0 + High-speed + 0x0 + + + B_0x1 + Low-power + 0x1 + + + + + + + DSI_GHCR + DSI_GHCR + DSI Host generic header configuration register + 0x6c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DT + Type +This field configures the packet data type of the header packet. + 0 + 6 + read-write + + + VCID + Channel +This field configures the virtual channel ID of the header packet. + 6 + 2 + read-write + + + WCLSB + WordCount LSB +This field configures the less significant byte of the header packet word count for long packets, or data 0 for short packets. + 8 + 8 + read-write + + + WCMSB + WordCount MSB +This field configures the most significant byte of the header packet's word count for long packets, or data 1 for short packets. + 16 + 8 + read-write + + + + + DSI_GPDR + DSI_GPDR + DSI Host generic payload data register + 0x70 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DATA1 + Payload byte 1 +This field indicates the byte 1 of the packet payload. + 0 + 8 + read-write + + + DATA2 + Payload byte 2 +This field indicates the byte 2 of the packet payload. + 8 + 8 + read-write + + + DATA3 + Payload byte 3 +This field indicates the byte 3 of the packet payload. + 16 + 8 + read-write + + + DATA4 + Payload byte 4 +This field indicates the byte 4 of the packet payload. + 24 + 8 + read-write + + + + + DSI_GPSR + DSI_GPSR + DSI Host generic packet status register + 0x74 + 0x20 + 0x00050015 + 0xFFFFFFFF + + + CMDFE + Command FIFO empty +This bit indicates the empty status of the generic command FIFO: + 0 + 1 + read-only + + + B_0x0 + Write payload FIFO not empty + 0x0 + + + B_0x1 + Write payload FIFO empty + 0x1 + + + + + CMDFF + Command FIFO full +This bit indicates the full status of the generic command FIFO: + 1 + 1 + read-only + + + B_0x0 + Write payload FIFO not full + 0x0 + + + B_0x1 + Write payload FIFO full + 0x1 + + + + + PWRFE + Payload write FIFO empty +This bit indicates the empty status of the generic write payload FIFO: + 2 + 1 + read-only + + + B_0x0 + Write payload FIFO not empty + 0x0 + + + B_0x1 + Write payload FIFO empty + 0x1 + + + + + PWRFF + Payload write FIFO full +This bit indicates the full status of the generic write payload FIFO: + 3 + 1 + read-only + + + B_0x0 + Write payload FIFO not full + 0x0 + + + B_0x1 + Write payload FIFO full + 0x1 + + + + + PRDFE + Payload read FIFO empty +This bit indicates the empty status of the generic read payload FIFO: + 4 + 1 + read-only + + + B_0x0 + Read payload FIFO not empty + 0x0 + + + B_0x1 + Read payload FIFO empty + 0x1 + + + + + PRDFF + Payload read FIFO full +This bit indicates the full status of the generic read payload FIFO: + 5 + 1 + read-only + + + B_0x0 + Read payload FIFO not full + 0x0 + + + B_0x1 + Read payload FIFO ful. + 0x1 + + + + + RCB + Read command busy +This bit is set when a read command is issued and cleared when the entire response is stored in the FIFO: + 6 + 1 + read-only + + + B_0x0 + No read command on going + 0x0 + + + B_0x1 + Read command on going + 0x1 + + + + + CMDBE + Command buffer empty +This bit indicates the empty status of the generic payload internal buffer: + 16 + 1 + read-only + + + B_0x0 + Payload internal buffer not full + 0x0 + + + B_0x1 + Payload internal buffer full + 0x1 + + + + + CMDBF + Command buffer full +This bit indicates the full status of the generic command internal buffer: + 17 + 1 + read-only + + + B_0x0 + Command internal buffer not full + 0x0 + + + B_0x1 + Command internal buffer full + 0x1 + + + + + PBE + Payload buffer empty +This bit indicates the empty status of the generic payload internal buffer: + 18 + 1 + read-only + + + B_0x0 + Payload internal buffer not empty + 0x0 + + + B_0x1 + Payload internal buffer empty + 0x1 + + + + + PBF + Payload buffer full +This bit indicates the full status of the generic payload internal buffer: + 19 + 1 + read-only + + + B_0x0 + Payload internal buffer not full + 0x0 + + + B_0x1 + Payload internal buffer full + 0x1 + + + + + + + DSI_TCCR0 + DSI_TCCR0 + DSI Host timeout counter configuration register 0 + 0x78 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LPRX_TOCNT + Low-power reception timeout counter +This field configures the timeout counter that triggers a low-power reception timeout contention detection (measured in TOCKDIV cycles). + 0 + 16 + read-write + + + HSTX_TOCNT + High-speed transmission timeout counter +This field configures the timeout counter that triggers a high-speed transmission timeout contention detection (measured in TOCKDIV cycles). +If using the non-burst mode and there is no enough time to switch from high-speed to low-power and back in the period from one line data finishing to the next line sync start, the DSI link returns the low-power state once per frame, then configure the TOCKDIV and HSTX_TOCNT to be in accordance with: +HSTX_TOCNT * lanebyteclkperiod * TOCKDIV ≥ the time of one FRAME data transmission * (1 + 10%) +In burst mode, RGB pixel packets are time-compressed, leaving more time during a scan line. Therefore, if in burst mode and there is enough time to switch from high-speed to low-power and back in the period from one line data finishing to the next line sync start, the DSI link can return low-power mode and back in this time interval to save power. For this, configure the TOCKDIV and HSTX_TOCNT to be in accordance with: +HSTX_TOCNT * lanebyteclkperiod * TOCKDIV ≥ the time of one LINE data transmission * (1 + 10%) + 16 + 16 + read-write + + + + + DSI_TCCR1 + DSI_TCCR1 + DSI Host timeout counter configuration register 1 + 0x7c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + HSRD_TOCNT + High-speed read timeout counter +This field sets a period for which the DSI Host keeps the link still, after sending a high-speed read operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts. + 0 + 16 + read-write + + + + + DSI_TCCR2 + DSI_TCCR2 + DSI Host timeout counter configuration register 2 + 0x80 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LPRD_TOCNT + Low-power read timeout counter +This field sets a period for which the DSI Host keeps the link still, after sending a low-power read operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts. + 0 + 16 + read-write + + + + + DSI_TCCR3 + DSI_TCCR3 + DSI Host timeout counter configuration register 3 + 0x84 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + HSWR_TOCNT + High-speed write timeout counter +This field sets a period for which the DSI Host keeps the link inactive after sending a high-speed write operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts. + 0 + 16 + read-write + + + PM + Presp mode +When set to 1, this bit ensures that the peripheral response timeout caused by HSWR_TOCNT is used only once per LTDC frame in command mode, when both the following conditions are met: +dpivsync_edpiwms has risen and fallen. +Packets originated from LTDC in command mode have been transmitted and its FIFO is empty again. +In this scenario no non-LTDC command requests are sent to the D-PHY, even if there is traffic from generic interface ready to be sent, making it return to stop state. When it does so, PRESP_TO counter is activated and only when it finishes does the controller send any other traffic that is ready. + 24 + 1 + read-write + + + + + DSI_TCCR4 + DSI_TCCR4 + DSI Host timeout counter configuration register 4 + 0x88 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LPWR_TOCNT + Low-power write timeout counter +This field sets a period for which the DSI Host keeps the link still, after sending a low-power write operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts. + 0 + 16 + read-write + + + + + DSI_TCCR5 + DSI_TCCR5 + DSI Host timeout counter configuration register 5 + 0x8c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BTA_TOCNT + Bus-turn-around timeout counter +This field sets a period for which the DSI Host keeps the link still, after completing a bus-turn-around. This period is measured in cycles of lanebyteclk. The counting starts when the D‑PHY enters the Stop state and causes no interrupts. + 0 + 16 + read-write + + + + + DSI_CLCR + DSI_CLCR + DSI Host clock lane configuration register + 0x94 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DPCC + D-PHY clock control +This bit controls the D-PHY clock state: + 0 + 1 + read-write + + + B_0x0 + Clock lane is in low-power mode. + 0x0 + + + B_0x1 + Clock lane runs in high-speed mode. + 0x1 + + + + + ACR + Automatic clock lane control +This bit enables the automatic mechanism to stop providing clock in the clock lane when time allows. + 1 + 1 + read-write + + + B_0x0 + Automatic clock lane control disabled + 0x0 + + + B_0x1 + Automatic clock lane control enabled + 0x1 + + + + + + + DSI_CLTCR + DSI_CLTCR + DSI Host clock lane timer configuration register + 0x98 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LP2HS_TIME + Low-power to high-speed time +This field configures the maximum time that the D-PHY clock lane takes to go from low‑power to high-speed transmission measured in lane byte clock cycles. + 0 + 10 + read-write + + + HS2LP_TIME + High-speed to low-power time +This field configures the maximum time that the D-PHY clock lane takes to go from high‑speed to low-power transmission measured in lane byte clock cycles. + 16 + 10 + read-write + + + + + DSI_DLTCR + DSI_DLTCR + DSI Host data lane timer configuration register + 0x9c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LP2HS_TIME + Low-power to high-speed time +This field configures the maximum time that the D-PHY data lanes take to go from low-power to high-speed transmission measured in lane byte clock cycles. + 0 + 10 + read-write + + + HS2LP_TIME + High-speed to low-power time +This field configures the maximum time that the D-PHY data lanes take to go from high-speed to low-power transmission measured in lane byte clock cycles. + 16 + 10 + read-write + + + + + DSI_PCTLR + DSI_PCTLR + DSI Host PHY control register + 0xa0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DEN + Digital enable +When set to 0, this bit places the digital section of the D-PHY in the reset state + 1 + 1 + read-write + + + B_0x0 + The digital section of the D-PHY is in the reset state. + 0x0 + + + B_0x1 + The digital section of the D-PHY is enabled. + 0x1 + + + + + CKE + Clock enable +This bit enables the D-PHY clock lane module: + 2 + 1 + read-write + + + B_0x0 + D-PHY clock lane module is disabled. + 0x0 + + + B_0x1 + D-PHY clock lane module is enabled. + 0x1 + + + + + + + DSI_PCONFR + DSI_PCONFR + DSI Host PHY configuration register + 0xa4 + 0x20 + 0x00000001 + 0xFFFFFFFF + + + NL + Number of lanes +This field configures the number of active data lanes: +Others: Reserved + 0 + 2 + read-write + + + B_0x0 + One data lane (lane 0) + 0x0 + + + B_0x1 + Two data lanes (lanes 0 and 1) - Reset value + 0x1 + + + + + SW_TIME + Stop wait time +This field configures the minimum wait period to request a high-speed transmission after the Stop state. + 8 + 8 + read-write + + + + + DSI_PUCR + DSI_PUCR + DSI Host PHY ULPS control register + 0xa8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + URCL + ULPS request on clock lane +ULPS mode request on clock lane. + 0 + 1 + read-write + + + B_0x0 + No ULPS request + 0x0 + + + B_0x1 + Request ULPS mode on clock lane + 0x1 + + + + + UECL + ULPS exit on clock lane +ULPS mode exit on clock lane. + 1 + 1 + read-write + + + B_0x0 + No exit request + 0x0 + + + B_0x1 + Exit ULPS mode on clock lane + 0x1 + + + + + URDL + ULPS request on data lane +ULPS mode request on all active data lanes. + 2 + 1 + read-write + + + B_0x0 + No ULPS request + 0x0 + + + B_0x1 + Request ULPS mode on all active data lane UECL + 0x1 + + + + + UEDL + ULPS exit on data lane +ULPS mode exit on all active data lanes. + 3 + 1 + read-write + + + B_0x0 + No exit request + 0x0 + + + B_0x1 + Exit ULPS mode on all active data lane URDL + 0x1 + + + + + + + DSI_PTTCR + DSI_PTTCR + DSI Host PHY TX triggers configuration register + 0xac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TX_TRIG + Transmission trigger +Escape mode transmit trigger 0-3. +Only one bit of TX_TRIG is asserted at any given time. + 0 + 4 + read-write + + + + + DSI_PSR + DSI_PSR + DSI Host PHY status register + 0xb0 + 0x20 + 0x00001528 + 0xFFFFFFFF + + + PD + PHY direction +This bit indicates the status of phydirection D-PHY signal. + 1 + 1 + read-only + + + PSSC + PHY stop state clock lane +This bit indicates the status of phystopstateclklane D-PHY signal. + 2 + 1 + read-only + + + UANC + ULPS active not clock lane +This bit indicates the status of ulpsactivenotclklane D-PHY signal. + 3 + 1 + read-only + + + PSS0 + PHY stop state lane 0 +This bit indicates the status of phystopstate0lane D-PHY signal. + 4 + 1 + read-only + + + UAN0 + ULPS active not lane 1 +This bit indicates the status of ulpsactivenot0lane D-PHY signal. + 5 + 1 + read-only + + + RUE0 + RX ULPS escape lane 0 +This bit indicates the status of rxulpsesc0lane D-PHY signal. + 6 + 1 + read-only + + + PSS1 + PHY stop state lane 1 +This bit indicates the status of phystopstate1lane D-PHY signal. + 7 + 1 + read-only + + + UAN1 + ULPS active not lane 1 +This bit indicates the status of ulpsactivenot1lane D-PHY signal. + 8 + 1 + read-only + + + + + DSI_ISR0 + DSI_ISR0 + DSI Host interrupt and status register 0 + 0xbc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AE0 + Acknowledge error 0 +This bit retrieves the SoT error from the acknowledge error report. + 0 + 1 + read-only + + + AE1 + Acknowledge error 1 +This bit retrieves the SoT sync error from the acknowledge error report. + 1 + 1 + read-only + + + AE2 + Acknowledge error 2 +This bit retrieves the EoT sync error from the acknowledge error report. + 2 + 1 + read-only + + + AE3 + Acknowledge error 3 +This bit retrieves the escape mode entry command error from the acknowledge error report. + 3 + 1 + read-only + + + AE4 + Acknowledge error 4 +This bit retrieves the LP transmit sync error from the acknowledge error report. + 4 + 1 + read-only + + + AE5 + Acknowledge error 5 +This bit retrieves the peripheral timeout error from the acknowledge error report. + 5 + 1 + read-only + + + AE6 + Acknowledge error 6 +This bit retrieves the false control error from the acknowledge error report. + 6 + 1 + read-only + + + AE7 + Acknowledge error 7 +This bit retrieves the reserved (specific to the device) from the acknowledge error report. + 7 + 1 + read-only + + + AE8 + Acknowledge error 8 +This bit retrieves the ECC error, single-bit (detected and corrected) from the acknowledge error report. + 8 + 1 + read-only + + + AE9 + Acknowledge error 9 +This bit retrieves the ECC error, multi-bit (detected, not corrected) from the acknowledge error report. + 9 + 1 + read-only + + + AE10 + Acknowledge error 10 +This bit retrieves the checksum error (long packet only) from the acknowledge error report. + 10 + 1 + read-only + + + AE11 + Acknowledge error 11 +This bit retrieves the not recognized DSI data type from the acknowledge error report. + 11 + 1 + read-only + + + AE12 + Acknowledge error 12 +This bit retrieves the DSI VC ID Invalid from the acknowledge error report. + 12 + 1 + read-only + + + AE13 + Acknowledge error 13 +This bit retrieves the invalid transmission length from the acknowledge error report. + 13 + 1 + read-only + + + AE14 + Acknowledge error 14 +This bit retrieves the reserved (specific to the device) from the acknowledge error report. + 14 + 1 + read-only + + + AE15 + Acknowledge error 15 +This bit retrieves the DSI protocol violation from the acknowledge error report. + 15 + 1 + read-only + + + PE0 + PHY error 0 +This bit indicates the ErrEsc escape entry error from lane 0. + 16 + 1 + read-only + + + PE1 + PHY error 1 +This bit indicates the ErrSyncEsc low-power transmission synchronization error from lane 0. + 17 + 1 + read-only + + + PE2 + PHY error 2 +This bit indicates the ErrControl error from lane 0. + 18 + 1 + read-only + + + PE3 + PHY error 3 +This bit indicates the LP0 contention error ErrContentionLP0 from lane 0. + 19 + 1 + read-only + + + PE4 + PHY error 4 +This bit indicates the LP1 contention error ErrContentionLP1 from lane 0. + 20 + 1 + read-only + + + + + DSI_ISR1 + DSI_ISR1 + DSI Host interrupt and status register 1 + 0xc0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TOHSTX + Timeout high-speed transmission +This bit indicates that the high-speed transmission timeout counter reached the end and contention is detected. + 0 + 1 + read-only + + + TOLPRX + Timeout low-power reception +This bit indicates that the low-power reception timeout counter reached the end and contention is detected. + 1 + 1 + read-only + + + ECCSE + ECC single-bit error +This bit indicates that the ECC single error is detected and corrected in a received packet. + 2 + 1 + read-only + + + ECCME + ECC multi-bit error +This bit indicates that the ECC multiple error is detected in a received packet. + 3 + 1 + read-only + + + CRCE + CRC error +This bit indicates that the CRC error is detected in the received packet payload. + 4 + 1 + read-only + + + PSE + Packet size error +This bit indicates that the packet size error is detected during the packet reception. + 5 + 1 + read-only + + + EOTPE + EoTp error +This bit indicates that the EoTp packet is not received at the end of the incoming peripheral transmission. + 6 + 1 + read-only + + + LPWRE + LTDC payload write error +This bit indicates that during a DPI pixel line storage, the payload FIFO becomes full and the data stored is corrupted. + 7 + 1 + read-only + + + GCWRE + Generic command write error +This bit indicates that the system tried to write a command through the generic interface and the FIFO is full. Therefore, the command is not written. + 8 + 1 + read-only + + + GPWRE + Generic payload write error +This bit indicates that the system tried to write a payload data through the generic interface and the FIFO is full. Therefore, the payload is not written. + 9 + 1 + read-only + + + GPTXE + Generic payload transmit error +This bit indicates that during a generic interface packet build, the payload FIFO becomes empty and corrupt data is sent. + 10 + 1 + read-only + + + GPRDE + Generic payload read error +This bit indicates that during a DCS read data, the payload FIFO becomes empty and the data sent to the interface is corrupted. + 11 + 1 + read-only + + + GPRXE + Generic payload receive error +This bit indicates that during a generic interface packet read back, the payload FIFO becomes full and the received data is corrupted. + 12 + 1 + read-only + + + PBUE + Payload buffer underflow error +This bit indicates that underflow has occurred when reading payload to build DSI packet for video mode. + 19 + 1 + read-only + + + + + DSI_IER0 + DSI_IER0 + DSI Host interrupt enable register 0 + 0xc4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AE0IE + Acknowledge error 0 interrupt enable +This bit enables the interrupt generation on acknowledge error 0. + 0 + 1 + read-write + + + B_0x0 + Interrupt on acknowledge error 0 disabled + 0x0 + + + B_0x1 + Interrupt on acknowledge error 0 enabled + 0x1 + + + + + AE1IE + Acknowledge error 1 interrupt enable +This bit enables the interrupt generation on acknowledge error 1. + 1 + 1 + read-write + + + B_0x0 + Interrupt on acknowledge error 1 disabled + 0x0 + + + B_0x1 + Interrupt on acknowledge error 1 enabled + 0x1 + + + + + AE2IE + Acknowledge error 2 interrupt enable +This bit enables the interrupt generation on acknowledge error 2. + 2 + 1 + read-write + + + B_0x0 + Interrupt on acknowledge error 2 disabled + 0x0 + + + B_0x1 + Interrupt on acknowledge error 2 enabled + 0x1 + + + + + AE3IE + Acknowledge error 3 interrupt enable +This bit enables the interrupt generation on acknowledge error 3. + 3 + 1 + read-write + + + B_0x0 + Interrupt on acknowledge error 3 disabled + 0x0 + + + B_0x1 + Interrupt on acknowledge error 3 enabled + 0x1 + + + + + AE4IE + Acknowledge error 4 interrupt enable +This bit enables the interrupt generation on acknowledge error 4. + 4 + 1 + read-write + + + B_0x0 + Interrupt on acknowledge error 4 disabled + 0x0 + + + B_0x1 + Interrupt on acknowledge error 4 enabled + 0x1 + + + + + AE5IE + Acknowledge error 5 interrupt enable +This bit enables the interrupt generation on acknowledge error 5. + 5 + 1 + read-write + + + B_0x0 + Interrupt on acknowledge error 5 disabled + 0x0 + + + B_0x1 + Interrupt on acknowledge error 5 enabled + 0x1 + + + + + AE6IE + Acknowledge error 6 interrupt enable +This bit enables the interrupt generation on acknowledge error 6. + 6 + 1 + read-write + + + B_0x0 + Interrupt on acknowledge error 6 disabled + 0x0 + + + B_0x1 + Interrupt on acknowledge error 6 enabled + 0x1 + + + + + AE7IE + Acknowledge error 7 interrupt enable +This bit enables the interrupt generation on acknowledge error 7. + 7 + 1 + read-write + + + B_0x0 + Interrupt on acknowledge error 7 disabled + 0x0 + + + B_0x1 + Interrupt on acknowledge error 7 enabled + 0x1 + + + + + AE8IE + Acknowledge error 8 interrupt enable +This bit enables the interrupt generation on acknowledge error 8. + 8 + 1 + read-write + + + B_0x0 + Interrupt on acknowledge error 8 disabled + 0x0 + + + B_0x1 + Interrupt on acknowledge error 8 enabled + 0x1 + + + + + AE9IE + Acknowledge error 9 interrupt enable +This bit enables the interrupt generation on acknowledge error 9. + 9 + 1 + read-write + + + B_0x0 + Interrupt on acknowledge error 9 disabled + 0x0 + + + B_0x1 + Interrupt on acknowledge error 9 enabled + 0x1 + + + + + AE10IE + Acknowledge error 10 interrupt enable +This bit enables the interrupt generation on acknowledge error 10. + 10 + 1 + read-write + + + B_0x0 + Interrupt on acknowledge error 10 disabled + 0x0 + + + B_0x1 + Interrupt on acknowledge error 10 enable. + 0x1 + + + + + AE11IE + Acknowledge error 11 interrupt enable +This bit enables the interrupt generation on acknowledge error 11. + 11 + 1 + read-write + + + B_0x0 + Interrupt on acknowledge error 11 disabled + 0x0 + + + B_0x1 + Interrupt on acknowledge error 11 enabled + 0x1 + + + + + AE12IE + Acknowledge error 12 interrupt enable +This bit enables the interrupt generation on acknowledge error 12. + 12 + 1 + read-write + + + B_0x0 + Interrupt on acknowledge error 12 disabled + 0x0 + + + B_0x1 + Interrupt on acknowledge error 12 enabled + 0x1 + + + + + AE13IE + Acknowledge error 13 interrupt enable +This bit enables the interrupt generation on acknowledge error 13. + 13 + 1 + read-write + + + B_0x0 + Interrupt on acknowledge error 13 disabled + 0x0 + + + B_0x1 + Interrupt on acknowledge error 13 enabled + 0x1 + + + + + AE14IE + Acknowledge error 14 interrupt enable +This bit enables the interrupt generation on acknowledge error 14. + 14 + 1 + read-write + + + B_0x0 + Interrupt on acknowledge error 14 disabled + 0x0 + + + B_0x1 + Interrupt on acknowledge error 14 enabled + 0x1 + + + + + AE15IE + Acknowledge error 15 interrupt enable +This bit enables the interrupt generation on acknowledge error 15. + 15 + 1 + read-write + + + B_0x0 + Interrupt on acknowledge error 15 disabled + 0x0 + + + B_0x1 + Interrupt on acknowledge error 15 enabled + 0x1 + + + + + PE0IE + PHY error 0 interrupt enable +This bit enables the interrupt generation on PHY error 0. + 16 + 1 + read-write + + + B_0x0 + Interrupt on PHY error 0 disabled + 0x0 + + + B_0x1 + Interrupt on PHY error 0 enabled + 0x1 + + + + + PE1IE + PHY error 1 interrupt enable +This bit enables the interrupt generation on PHY error 1. + 17 + 1 + read-write + + + B_0x0 + Interrupt on PHY error 1 disabled + 0x0 + + + B_0x1 + Interrupt on PHY error 1 enabled + 0x1 + + + + + PE2IE + PHY error 2 interrupt enable +This bit enables the interrupt generation on PHY error 2. + 18 + 1 + read-write + + + B_0x0 + Interrupt on PHY error 2 disabled + 0x0 + + + B_0x1 + Interrupt on PHY error 2 enabled + 0x1 + + + + + PE3IE + PHY error 3 interrupt enable +This bit enables the interrupt generation on PHY error 4. + 19 + 1 + read-write + + + B_0x0 + Interrupt on PHY error 3 disabled + 0x0 + + + B_0x1 + Interrupt on PHY error 3 enabled + 0x1 + + + + + PE4IE + PHY error 4 interrupt enable +This bit enables the interrupt generation on PHY error 4. + 20 + 1 + read-write + + + B_0x0 + Interrupt on PHY error 4 disabled + 0x0 + + + B_0x1 + Interrupt on PHY error 4 enabled + 0x1 + + + + + + + DSI_IER1 + DSI_IER1 + DSI Host interrupt enable register 1 + 0xc8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TOHSTXIE + Timeout high-speed transmission interrupt enable +This bit enables the interrupt generation on timeout high-speed transmission . + 0 + 1 + read-write + + + B_0x0 + Interrupt on timeout high-speed transmission disabled + 0x0 + + + B_0x1 + Interrupt on timeout high-speed transmission enabled + 0x1 + + + + + TOLPRXIE + Timeout low-power reception interrupt enable +This bit enables the interrupt generation on timeout low-power reception. + 1 + 1 + read-write + + + B_0x0 + Interrupt on timeout low-power reception disabled + 0x0 + + + B_0x1 + Interrupt on timeout low-power reception enabled + 0x1 + + + + + ECCSEIE + ECC single-bit error interrupt enable +This bit enables the interrupt generation on ECC single-bit error. + 2 + 1 + read-write + + + B_0x0 + Interrupt on ECC single-bit error disabled + 0x0 + + + B_0x1 + Interrupt on ECC single-bit error enabled + 0x1 + + + + + ECCMEIE + ECC multi-bit error interrupt enable +This bit enables the interrupt generation on ECC multi-bit error. + 3 + 1 + read-write + + + B_0x0 + Interrupt on ECC multi-bit error disabled + 0x0 + + + B_0x1 + Interrupt on ECC multi-bit error enabled + 0x1 + + + + + CRCEIE + CRC error interrupt enable +This bit enables the interrupt generation on CRC error. + 4 + 1 + read-write + + + B_0x0 + Interrupt on CRC error disabled + 0x0 + + + B_0x1 + Interrupt on CRC error enabled + 0x1 + + + + + PSEIE + Packet size error interrupt enable +This bit enables the interrupt generation on packet size error. + 5 + 1 + read-write + + + B_0x0 + Interrupt on packet size error disabled + 0x0 + + + B_0x1 + Interrupt on packet size error enabled + 0x1 + + + + + EOTPEIE + EoTp error interrupt enable +This bit enables the interrupt generation on EoTp error. + 6 + 1 + read-write + + + B_0x0 + Interrupt on EoTp error disabled + 0x0 + + + B_0x1 + Interrupt on EoTp error enabled + 0x1 + + + + + LPWREIE + LTDC payload write error interrupt enable +This bit enables the interrupt generation on LTDC payload write error. + 7 + 1 + read-write + + + B_0x0 + Interrupt on LTDC payload write error disabled + 0x0 + + + B_0x1 + Interrupt on LTDC payload write error enabled + 0x1 + + + + + GCWREIE + Generic command write error interrupt enable +This bit enables the interrupt generation on generic command write error. + 8 + 1 + read-write + + + B_0x0 + Interrupt on generic command write error disabled + 0x0 + + + B_0x1 + Interrupt on generic command write error enabled + 0x1 + + + + + GPWREIE + Generic payload write error interrupt enable +This bit enables the interrupt generation on generic payload write error. + 9 + 1 + read-write + + + B_0x0 + Interrupt on generic payload write error disabled + 0x0 + + + B_0x1 + Interrupt on generic payload write error enabled + 0x1 + + + + + GPTXEIE + Generic payload transmit error interrupt enable +This bit enables the interrupt generation on generic payload transmit error. + 10 + 1 + read-write + + + B_0x0 + Interrupt on generic payload transmit error disabled + 0x0 + + + B_0x1 + Interrupt on generic payload transmit error enabled + 0x1 + + + + + GPRDEIE + Generic payload read error interrupt enable +This bit enables the interrupt generation on generic payload read error. + 11 + 1 + read-write + + + B_0x0 + Interrupt on generic payload read error disabled + 0x0 + + + B_0x1 + Interrupt on generic payload read error enabled + 0x1 + + + + + GPRXEIE + Generic payload receive error interrupt enable +This bit enables the interrupt generation on generic payload receive error. + 12 + 1 + read-write + + + B_0x0 + Interrupt on generic payload receive error disabled + 0x0 + + + B_0x1 + Interrupt on generic payload receive error enabled + 0x1 + + + + + PBUEIE + Payload buffer underflow error interrupt enable +This bit enables the interrupt generation on payload buffer underflow error. + 19 + 1 + read-write + + + B_0x0 + Interrupt on payload buffer underflow error disabled + 0x0 + + + B_0x1 + Interrupt on payload buffer underflow error enabled + 0x1 + + + + + + + DSI_FIR0 + DSI_FIR0 + DSI Host force interrupt register 0 + 0xd8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FAE0 + Force acknowledge error 0 +Writing one to this bit forces an acknowledge error 0. + 0 + 1 + write-only + + + FAE1 + Force acknowledge error 1 +Writing one to this bit forces an acknowledge error 1. + 1 + 1 + write-only + + + FAE2 + Force acknowledge error 2 +Writing one to this bit forces an acknowledge error 2. + 2 + 1 + write-only + + + FAE3 + Force acknowledge error 3 +Writing one to this bit forces an acknowledge error 3. + 3 + 1 + write-only + + + FAE4 + Force acknowledge error 4 +Writing one to this bit forces an acknowledge error 4. + 4 + 1 + write-only + + + FAE5 + Force acknowledge error 5 +Writing one to this bit forces an acknowledge error 5. + 5 + 1 + write-only + + + FAE6 + Force acknowledge error 6 +Writing one to this bit forces an acknowledge error 6. + 6 + 1 + write-only + + + FAE7 + Force acknowledge error 7 +Writing one to this bit forces an acknowledge error 7. + 7 + 1 + write-only + + + FAE8 + Force acknowledge error 8 +Writing one to this bit forces an acknowledge error 8. + 8 + 1 + write-only + + + FAE9 + Force acknowledge error 9 +Writing one to this bit forces an acknowledge error 9. + 9 + 1 + write-only + + + FAE10 + Force acknowledge error 10 +Writing one to this bit forces an acknowledge error 10. + 10 + 1 + write-only + + + FAE11 + Force acknowledge error 11 +Writing one to this bit forces an acknowledge error 11. + 11 + 1 + write-only + + + FAE12 + Force acknowledge error 12 +Writing one to this bit forces an acknowledge error 12. + 12 + 1 + write-only + + + FAE13 + Force acknowledge error 13 +Writing one to this bit forces an acknowledge error 13. + 13 + 1 + write-only + + + FAE14 + Force acknowledge error 14 +Writing one to this bit forces an acknowledge error 14. + 14 + 1 + write-only + + + FAE15 + Force acknowledge error 15 +Writing one to this bit forces an acknowledge error 15. + 15 + 1 + write-only + + + FPE0 + Force PHY error 0 +Writing one to this bit forces a PHY error 0. + 16 + 1 + write-only + + + FPE1 + Force PHY error 1 +Writing one to this bit forces a PHY error 1. + 17 + 1 + write-only + + + FPE2 + Force PHY error 2 +Writing one to this bit forces a PHY error 2. + 18 + 1 + write-only + + + FPE3 + Force PHY error 3 +Writing one to this bit forces a PHY error 3. + 19 + 1 + write-only + + + FPE4 + Force PHY error 4 +Writing one to this bit forces a PHY error 4. + 20 + 1 + write-only + + + + + DSI_FIR1 + DSI_FIR1 + DSI Host force interrupt register 1 + 0xdc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FTOHSTX + Force timeout high-speed transmission +Writing one to this bit forces a timeout high-speed transmission. + 0 + 1 + write-only + + + FTOLPRX + Force timeout low-power reception +Writing one to this bit forces a timeout low-power reception. + 1 + 1 + write-only + + + FECCSE + Force ECC single-bit error +Writing one to this bit forces a ECC single-bit error. + 2 + 1 + write-only + + + FECCME + Force ECC multi-bit error +Writing one to this bit forces a ECC multi-bit error. + 3 + 1 + write-only + + + FCRCE + Force CRC error +Writing one to this bit forces a CRC error. + 4 + 1 + write-only + + + FPSE + Force packet size error +Writing one to this bit forces a packet size error. + 5 + 1 + write-only + + + FEOTPE + Force EoTp error +Writing one to this bit forces a EoTp error. + 6 + 1 + write-only + + + FLPWRE + Force LTDC payload write error +Writing one to this bit forces a LTDC payload write error. + 7 + 1 + write-only + + + FGCWRE + Force generic command write error +Writing one to this bit forces a generic command write error. + 8 + 1 + write-only + + + FGPWRE + Force generic payload write error +Writing one to this bit forces a generic payload write error. + 9 + 1 + write-only + + + FGPTXE + Force generic payload transmit error +Writing one to this bit forces a generic payload transmit error. + 10 + 1 + write-only + + + FGPRDE + Force generic payload read error +Writing one to this bit forces a generic payload read error. + 11 + 1 + write-only + + + FGPRXE + Force generic payload receive error +Writing one to this bit forces a generic payload receive error. + 12 + 1 + write-only + + + FPBUE + Force payload buffer underflow error +Writing one to this bit forces a payload undrflow error. + 19 + 1 + write-only + + + + + DSI_DLTRCR + DSI_DLTRCR + DSI Host data lane timer read configuration register + 0xf4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MRD_TIME + Maximum read time +This field configures the maximum time required to perform a read command in lane byte clock cycles. This register can only be modified when no read command is in progress. + 0 + 15 + read-write + + + + + DSI_VSCR + DSI_VSCR + DSI Host video shadow control register + 0x100 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +When set to 1, DSI Host LTDC interface receives the active configuration from the auxiliary registers. +When this bit is set along with the UR bit, the auxiliary registers are automatically updated. + 0 + 1 + read-write + + + B_0x0 + Register update is disabled. + 0x0 + + + B_0x1 + Register update is enabled. + 0x1 + + + + + UR + Update register +When set to 1, the LTDC registers are copied to the auxiliary registers. After copying, this bit is auto cleared. + 8 + 1 + read-write + + + B_0x0 + No update requested + 0x0 + + + B_0x1 + Register update requested + 0x1 + + + + + + + DSI_LCVCIDR + DSI_LCVCIDR + DSI Host LTDC current VCID register + 0x10c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + VCID + Virtual channel ID +This field returns the virtual channel ID for the LTDC interface. + 0 + 2 + read-write + + + + + DSI_LCCCR + DSI_LCCCR + DSI Host LTDC current color coding register + 0x110 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + COLC + Color coding +This field returns the current LTDC interface color coding. +0110-1111: reserved +If LTDC interface in command mode is chosen and currently works in the command mode (CMDM=1), then 0110-1111: 24-bit + 0 + 4 + read-only + + + B_0x0 + 16-bit configuration 1 + 0x0 + + + B_0x1 + 16-bit configuration 2 + 0x1 + + + B_0x2 + 16-bit configuration 3 + 0x2 + + + B_0x3 + 18-bit configuration 1 + 0x3 + + + B_0x4 + 18-bit configuration 2 + 0x4 + + + B_0x5 + 24-bit + 0x5 + + + + + LPE + Loosely packed enable +This bit returns the current state of the loosely packed variant to 18-bit configurations. + 8 + 1 + read-only + + + B_0x0 + Loosely packed variant disabled + 0x0 + + + B_0x1 + Loosely packed variant enabled + 0x1 + + + + + + + DSI_LPMCCR + DSI_LPMCCR + DSI Host low-power mode current configuration register + 0x118 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + VLPSIZE + VACT largest packet size +This field returns the current size, in bytes, of the largest packet that can fit in a line during VACT regions, for the transmission of commands in low-power mode. + 0 + 8 + read-only + + + LPSIZE + Largest packet size +This field is returns the current size, in bytes, of the largest packet that can fit in a line during VSA, VBP and VFP regions, for the transmission of commands in low-power mode. + 16 + 8 + read-only + + + + + DSI_VMCCR + DSI_VMCCR + DSI Host video mode current configuration register + 0x138 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + VMT + Video mode type +This field returns the current video mode transmission type: +1x: Burst mode + 0 + 2 + read-only + + + B_0x0 + Non-burst with sync pulses + 0x0 + + + B_0x1 + Non-burst with sync events + 0x1 + + + + + LPVSAE + Low-power vertical sync time enable +This bit returns the current state of return to low-power inside the vertical sync time (VSA) period when timing allows. + 2 + 1 + read-only + + + B_0x0 + Return to low-power inside the VSA is disabled. + 0x0 + + + B_0x1 + Return to low-power inside the VSA is enabled + 0x1 + + + + + LPVBPE + Low-power vertical back-porch enable +This bit returns the current state of return to low-power inside the vertical back-porch (VBP) period when timing allows. + 3 + 1 + read-only + + + B_0x0 + Return to low-power inside the VBP is disabled. + 0x0 + + + B_0x1 + Return to low-power inside the VBP is enabled. + 0x1 + + + + + LPVFPE + Low-power vertical front-porch enable +This bit returns the current state of return to low-power inside the vertical front-porch (VFP) period when timing allows. + 4 + 1 + read-only + + + B_0x0 + Return to low-power inside the VFP is disabled. + 0x0 + + + B_0x1 + Return to low-power inside the VFP is enabled. + 0x1 + + + + + LPVAE + Low-power vertical active enable +This bit returns the current state of return to low-power inside the vertical active (VACT) period when timing allows. + 5 + 1 + read-only + + + B_0x0 + Return to low-power inside the VACT is disabled. + 0x0 + + + B_0x1 + Return to low-power inside the VACT is enabled. + 0x1 + + + + + LPHBPE + Low-power horizontal back-porch enable +This bit returns the current state of return to low-power inside the horizontal back-porch (HBP) period when timing allows. + 6 + 1 + read-only + + + B_0x0 + Return to low-power inside the HBP period is disabled. + 0x0 + + + B_0x1 + Return to low-power inside the HBP period is enabled. + 0x1 + + + + + LPHFE + Low-power horizontal front-porch enable +This bit returns the current state of return to low-power inside the horizontal front-porch (HFP) period when timing allows. + 7 + 1 + read-only + + + B_0x0 + Return to low-power inside the HFP period is disabled. + 0x0 + + + B_0x1 + Return to low-power inside the HFP period is enabled. + 0x1 + + + + + FBTAAE + Frame BTA acknowledge enable +This bit returns the current state of request for an acknowledge response at the end of a frame. + 8 + 1 + read-only + + + B_0x0 + Acknowledge response at the end of a frame is disabled. + 0x0 + + + B_0x1 + Acknowledge response at the end of a frame is enabled. + 0x1 + + + + + LPCE + Low-power command enable +This bit returns the current command transmission state in low-power mode. + 9 + 1 + read-only + + + B_0x0 + Command transmission in low-power mode is disabled. + 0x0 + + + B_0x1 + Command transmission in low-power mode is enabled. + 0x1 + + + + + + + DSI_VPCCR + DSI_VPCCR + DSI Host video packet current configuration register + 0x13c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + VPSIZE + Video packet size +This field returns the number of pixels in a single video packet. + 0 + 14 + read-only + + + + + DSI_VCCCR + DSI_VCCCR + DSI Host video chunks current configuration register + 0x140 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NUMC + Number of chunks +This field returns the number of chunks being transmitted during a line period. + 0 + 13 + read-only + + + + + DSI_VNPCCR + DSI_VNPCCR + DSI Host video null packet current configuration register + 0x144 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NPSIZE + Null packet size +This field returns the number of bytes inside a null packet. + 0 + 13 + read-only + + + + + DSI_VHSACCR + DSI_VHSACCR + DSI Host video HSA current configuration register + 0x148 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + HSA + Horizontal synchronism active duration +This fields returns the horizontal synchronism active period in lane byte clock cycles. + 0 + 12 + read-only + + + + + DSI_VHBPCCR + DSI_VHBPCCR + DSI Host video HBP current configuration register + 0x14c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + HBP + Horizontal back-porch duration +This field returns the horizontal back-porch period in lane byte clock cycles. + 0 + 12 + read-only + + + + + DSI_VLCCR + DSI_VLCCR + DSI Host video line current configuration register + 0x150 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + HLINE + Horizontal line duration +This field returns the current total of the horizontal line period (HSA+HBP+HACT+HFP) counted in lane byte clock cycles. + 0 + 15 + read-only + + + + + DSI_VVSACCR + DSI_VVSACCR + DSI Host video VSA current configuration register + 0x154 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + VSA + Vertical synchronism active duration +This field returns the current vertical synchronism active period measured in number of horizontal lines. + 0 + 10 + read-only + + + + + DSI_VVBPCCR + DSI_VVBPCCR + DSI Host video VBP current configuration register + 0x158 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + VBP + Vertical back-porch duration +This field returns the current vertical back-porch period measured in number of horizontal lines. + 0 + 10 + read-only + + + + + DSI_VVFPCCR + DSI_VVFPCCR + DSI Host video VFP current configuration register + 0x15c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + VFP + Vertical front-porch duration +This field returns the current vertical front-porch period measured in number of horizontal lines. + 0 + 10 + read-only + + + + + DSI_VVACCR + DSI_VVACCR + DSI Host video VA current configuration register + 0x160 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + VA + Vertical active duration +This field returns the current vertical active period measured in number of horizontal lines. + 0 + 14 + read-only + + + + + DSI_FBSR + DSI_FBSR + DSI Host FIFO and buffer status register + 0x168 + 0x20 + 0x00050015 + 0xFFFFFFFF + + + VCWFE + Video mode command write FIFO empty +This bit indicates the empty status of the video mode write command FIFO: + 0 + 1 + read-only + + + B_0x0 + Write command FIFO not empty + 0x0 + + + B_0x1 + Write command FIFO empty + 0x1 + + + + + VCWFF + Video mode command write FIFO full +This bit indicates the full status of the video mode write command FIFO: + 1 + 1 + read-only + + + B_0x0 + Write command FIFO not full + 0x0 + + + B_0x1 + Write command FIFO full + 0x1 + + + + + VPWFE + Video mode payload write FIFO empty +This bit indicates the empty status of the video mode write payload FIFO: + 2 + 1 + read-only + + + B_0x0 + Write payload FIFO not empty + 0x0 + + + B_0x1 + Write payload FIFO empty + 0x1 + + + + + VPWFF + Video mode payload write FIFO full +This bit indicates the full status of the video mode write payload FIFO: + 3 + 1 + read-only + + + B_0x0 + Write payload FIFO not full + 0x0 + + + B_0x1 + Write payload FIFO full + 0x1 + + + + + ACWFE + Adapted command mode command write FIFO empty +This bit indicates the empty status of the adapted command mode write command FIFO: + 4 + 1 + read-only + + + B_0x0 + Write command FIFO not empty + 0x0 + + + B_0x1 + Write command FIFO empty + 0x1 + + + + + ACWFF + Adapted command mode command write FIFO full +This bit indicates the full status of the adapted command mode write command FIFO: + 5 + 1 + read-only + + + B_0x0 + Write command FIFO not full + 0x0 + + + B_0x1 + Write command FIFO full + 0x1 + + + + + APWFE + Adapted command mode payload write FIFO empty +This bit indicates the empty status of the adapted command mode write payload FIFO: + 6 + 1 + read-only + + + B_0x0 + Write payload FIFO not empty + 0x0 + + + B_0x1 + Write payload FIFO empty + 0x1 + + + + + APWFF + Adapted command mode payload write FIFO full +This bit indicates the full status of the adapted command mode write payload FIFO: + 7 + 1 + read-only + + + B_0x0 + Write payload FIFO not full + 0x0 + + + B_0x1 + Write payload FIFO full + 0x1 + + + + + VPBE + Video mode payload buffer empty +This bit indicates the empty status of the video mode payload internal buffer: + 16 + 1 + read-only + + + B_0x0 + Payload internal buffer not empty + 0x0 + + + B_0x1 + Payload internal buffer empty + 0x1 + + + + + VPBF + Video mode payload buffer full +This bit indicates the full status of the video mode payload internal buffer: + 17 + 1 + read-only + + + B_0x0 + Payload internal buffer not full + 0x0 + + + B_0x1 + Payload internal buffer full + 0x1 + + + + + ACBE + Adapted command mode command buffer empty +This bit indicates the empty status of the adapted command mode command internal +buffer: + 20 + 1 + read-only + + + B_0x0 + Command internal buffer not empty + 0x0 + + + B_0x1 + Command internal buffer empty + 0x1 + + + + + ACBF + Adapted command mode command buffer full +This bit indicates the full status of the adapted command mode command internal +buffer: + 21 + 1 + read-only + + + B_0x0 + Command internal buffer not full + 0x0 + + + B_0x1 + Command internal buffer full + 0x1 + + + + + APBE + Adapted command mode payload buffer empty +This bit indicates the empty status of the adapted command mode payload internal +buffer: + 22 + 1 + read-only + + + B_0x0 + Payload internal buffer not empty + 0x0 + + + B_0x1 + Payload internal buffer empty + 0x1 + + + + + APBF + Adapted command mode payload buffer full +This bit indicates the full status of the adapted command mode payload internal buffer: + 23 + 1 + read-only + + + B_0x0 + Payload internal buffer not full + 0x0 + + + B_0x1 + Payload internal buffer full + 0x1 + + + + + + + DSI_WCFGR + DSI_WCFGR + DSI Wrapper configuration register + 0x400 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DSIM + DSI mode +This bit selects the mode for the video transmission. +This bit must only be changed when DSI Host is stopped (DSI_CR.EN = 0). + 0 + 1 + read-write + + + B_0x0 + Video mode + 0x0 + + + B_0x1 + Adapted command mode + 0x1 + + + + + COLMUX + Color multiplexing +This bit selects the color multiplexing used by DSI Host. +This field must only be changed when DSI is stopped (DSI_WCR.DSIEN = 0 and DSI_CR.EN = 0). + 1 + 3 + read-write + + + B_0x0 + 16-bit configuration 1 + 0x0 + + + B_0x1 + 16-bit configuration 2 + 0x1 + + + B_0x2 + 16-bit configuration 3 + 0x2 + + + B_0x3 + 18-bit configuration 1 + 0x3 + + + B_0x4 + 18-bit configuration 2 + 0x4 + + + B_0x5 + 24-bit + 0x5 + + + + + TESRC + TE source +This bit selects the tearing effect (TE) source. +This bit must only be changed when DSI Host is stopped (DSI_CR.EN = 0). + 4 + 1 + read-write + + + B_0x0 + DSI Link + 0x0 + + + B_0x1 + External pin + 0x1 + + + + + TEPOL + TE polarity +This bit selects the polarity of the external pin tearing effect (TE) source. +This bit must only be changed when DSI Host is stopped (DSI_CR.EN = 0). + 5 + 1 + read-write + + + B_0x0 + rising edge. + 0x0 + + + B_0x1 + falling edge. + 0x1 + + + + + AR + Automatic refresh +This bit selects the refresh mode in DBI mode. +This bit must only be changed when DSI Host is stopped (DSI_CR.EN = 0). + 6 + 1 + read-write + + + B_0x0 + automatic refresh mode disabled + 0x0 + + + B_0x1 + automatic refresh mode enabled + 0x1 + + + + + VSPOL + VSync polarity +This bit selects the VSync edge on which the LTDC is halted. +This bit must only be changed when DSI is stopped (DSI_WCR.DSIEN = 0 and DSI_CR.EN = 0). + 7 + 1 + read-write + + + B_0x0 + LTDC halted on a falling edge + 0x0 + + + B_0x1 + LTDC halted on a rising edge + 0x1 + + + + + + + DSI_WCR + DSI_WCR + DSI Wrapper control register + 0x404 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + COLM + Color mode +This bit controls the display color mode in video mode. + 0 + 1 + read-write + + + B_0x0 + Full color mode + 0x0 + + + B_0x1 + Eight color mode + 0x1 + + + + + SHTDN + Shutdown +This bit controls the display shutdown in video mode. + 1 + 1 + read-write + + + B_0x0 + display ON + 0x0 + + + B_0x1 + display OFF + 0x1 + + + + + LTDCEN + LTDC enable +This bit enables the LTDC for a frame transfer in adapted command mode. + 2 + 1 + read-write + + + B_0x0 + LTDC disabled + 0x0 + + + B_0x1 + LTDC enabled + 0x1 + + + + + DSIEN + DSI enable +This bit enables the DSI Wrapper. + 3 + 1 + read-write + + + B_0x0 + DSI disabled + 0x0 + + + B_0x1 + DSI enabled + 0x1 + + + + + + + DSI_WIER + DSI_WIER + DSI Wrapper interrupt enable register + 0x408 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TEIE + Tearing effect interrupt enable +This bit enables the tearing effect interrupt. + 0 + 1 + read-write + + + B_0x0 + Tearing effect interrupt disabled + 0x0 + + + B_0x1 + Tearing effect interrupt enabled + 0x1 + + + + + ERIE + End of refresh interrupt enable +This bit enables the end of refresh interrupt. + 1 + 1 + read-write + + + B_0x0 + End of refresh interrupt disabled + 0x0 + + + B_0x1 + End of refresh interrupt enabled + 0x1 + + + + + PLLLIE + PLL lock interrupt enable +This bit enables the PLL lock interrupt. + 9 + 1 + read-write + + + B_0x0 + PLL lock interrupt disabled + 0x0 + + + B_0x1 + PLL lock interrupt enabled + 0x1 + + + + + PLLUIE + PLL unlock interrupt enable +This bit enables the PLL unlock interrupt. + 10 + 1 + read-write + + + B_0x0 + PLL unlock interrupt disabled + 0x0 + + + B_0x1 + PLL unlock interrupt enabled + 0x1 + + + + + + + DSI_WISR + DSI_WISR + DSI Wrapper interrupt and status register + 0x40c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TEIF + Tearing effect interrupt flag +This bit is set when a tearing effect event occurs. + 0 + 1 + read-only + + + B_0x0 + No tearing effect event occurred + 0x0 + + + B_0x1 + Tearing effect event occurred + 0x1 + + + + + ERIF + End of refresh interrupt flag +This bit is set when the transfer of a frame in adapted command mode is finished. + 1 + 1 + read-only + + + B_0x0 + No end of refresh event occurred + 0x0 + + + B_0x1 + End of refresh event occurred + 0x1 + + + + + BUSY + Busy flag +This bit is set when the transfer of a frame in adapted command mode is ongoing. + 2 + 1 + read-only + + + B_0x0 + No transfer on going + 0x0 + + + B_0x1 + Transfer on going + 0x1 + + + + + PLLLS + PLL lock status +This bit is set when the PLL is locked and cleared when it is unlocked. + 8 + 1 + read-only + + + B_0x0 + PLL is unlocked. + 0x0 + + + B_0x1 + PLL is locked. + 0x1 + + + + + PLLLIF + PLL lock interrupt flag +This bit is set when the PLL becomes locked. + 9 + 1 + read-only + + + B_0x0 + No PLL lock event occurred + 0x0 + + + B_0x1 + PLL lock event occurred + 0x1 + + + + + PLLUIF + PLL unlock interrupt flag +This bit is set when the PLL becomes unlocked. + 10 + 1 + read-only + + + B_0x0 + No PLL unlock event occurred + 0x0 + + + B_0x1 + PLL unlock event occurred + 0x1 + + + + + + + DSI_WIFCR + DSI_WIFCR + DSI Wrapper interrupt flag clear register + 0x410 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CTEIF + Clear tearing effect interrupt flag +Write 1 clears the TEIF flag in the DSI_WSR register. + 0 + 1 + write-only + + + CERIF + Clear end of refresh interrupt flag +Write 1 clears the ERIF flag in the DSI_WSR register. + 1 + 1 + write-only + + + CPLLLIF + Clear PLL lock interrupt flag +Write 1 clears the PLLLIF flag in the DSI_WSR register. + 9 + 1 + write-only + + + CPLLUIF + Clear PLL unlock interrupt flag +Write 1 clears the PLLUIF flag in the DSI_WSR register. + 10 + 1 + write-only + + + + + DSI_WPCR0 + DSI_WPCR0 + DSI Wrapper PHY configuration register 0 + 0x418 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SWCL + Swap clock lane pins +This bit swaps the pins on clock lane. + 6 + 1 + read-write + + + B_0x0 + Regular clock lane pin configuration + 0x0 + + + B_0x1 + Swapped clock lane pin + 0x1 + + + + + SWDL0 + Swap data lane 0 pins +This bit swaps the pins on data lane 0. + 7 + 1 + read-write + + + B_0x0 + Regular clock lane pin configuration + 0x0 + + + B_0x1 + Swapped clock lane pin + 0x1 + + + + + SWDL1 + Swap data lane 1 pins +This bit swaps the pins on clock lane. + 8 + 1 + read-write + + + B_0x0 + Regular clock lane pin configuration + 0x0 + + + B_0x1 + Swapped clock lane pin + 0x1 + + + + + FTXSMCL + Force in TX Stop mode the clock lane +This bit forces the clock lane in TX stop mode. It is used to initialize a lane module in transmit mode. It causes the lane module to immediately jump to transmit control mode and to begin transmitting a stop state (LP-11). It can be used to go back in TX mode after a wrong BTA sequence. + 12 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Force the clock lane in TX Stop mode + 0x1 + + + + + FTXSMDL + Force in TX Stop mode the data lanes +This bit forces the data lanes in TX stop mode. It is used to initialize a lane module in transmit mode. It causes the lane module to immediately jump to transmit control mode and to begin transmitting a stop state (LP-11). It can be used to go back in TX mode after a wrong BTA sequence. + 13 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Force the data lanes in TX Stop mode + 0x1 + + + + + + + DSI_WRPCR + DSI_WRPCR + DSI Wrapper regulator and PLL control register + 0x430 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PLLEN + PLL enable +This bit enables the D-PHY PLL. + 0 + 1 + read-write + + + B_0x0 + PLL disabled + 0x0 + + + B_0x1 + PLL enabled + 0x1 + + + + + NDIV + PLL loop division factor +This field configures the PLL loop division factor. +2: PLL loop divided by 2x2 +... +511: PLL loop divided by 511x2 + 2 + 9 + read-write + + + B_0x0 + PLL loop divided by 1x2 + 0x0 + + + B_0x1 + PLL loop divided by 1x2 + 0x1 + + + + + IDF + PLL input division factor +This field configures the PLL input division factor. +2: PLL input divided by 2 +... +511: PLL input divided by 511 + 11 + 9 + read-write + + + B_0x0 + PLL input divided by 1 + 0x0 + + + B_0x1 + PLL input divided by 1 + 0x1 + + + + + ODF + PLL output division factor +This field configures the PLL output division factor. +2: PLL output divided by 2 +... +511: PLL output divided by 511 + 20 + 9 + read-write + + + B_0x0 + PLL output divided by 1 + 0x0 + + + B_0x1 + PLL output divided by 1 + 0x1 + + + + + + + DSI_BCFGR + DSI_BCFGR + DSI bias configuration register + 0x808 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PWRUP + Power-up +This bit powers-up the reference bias for the MIPI D-PHY + 6 + 1 + read-write + + + B_0x0 + Reference bias is powered down. + 0x0 + + + B_0x1 + Reference bias is powered up. + 0x1 + + + + + + + DSI_DPCBCR + DSI_DPCBCR + DSI D-PHY clock band control register + 0xc04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BC + Band control +This field selects the frequency band used by the D-PHY. +Others: Reserved + 3 + 5 + read-write + + + B_0x0 + 80 to 100 MHz + 0x0 + + + B_0x1 + 100 to 120 MHz + 0x1 + + + B_0x2 + 120 to 160 MHz + 0x2 + + + B_0x3 + 160 to 200 MHz + 0x3 + + + B_0x4 + 200 to 240 MHz + 0x4 + + + B_0x5 + 240 to 320 MHz + 0x5 + + + B_0x6 + 320 to 390 MHz + 0x6 + + + B_0x7 + 390 to 450 MHz + 0x7 + + + B_0x8 + 450 to 510 MHz + 0x8 + + + + + + + DSI_DPCSRCR + DSI_DPCSRCR + DSI D-PHY clock skew rate control register + 0xc34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SRC + Slew rate control +This field selects the slew rate for HS-TX speed. +Others: Reserved + 0 + 8 + read-write + + + B_0xE + 80 to 750 Mbit/s + 0xE + + + + + + + DSI_DPDL0BCR + DSI_DPDL0BCR + DSI D-PHY data lane 0 band control register + 0xc70 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BC + Band control +This field selects the frequency band used by the D-PHY. +Others: Reserved + 0 + 5 + read-write + + + B_0x0 + 80 to 100 MHz + 0x0 + + + B_0x1 + 100 to 120 MHz + 0x1 + + + B_0x2 + 120 to 160 MHz + 0x2 + + + B_0x3 + 160 to 200 MHz + 0x3 + + + B_0x4 + 200 to 240 MHz + 0x4 + + + B_0x5 + 240 to 320 MHz + 0x5 + + + B_0x6 + 320 to 390 MHz + 0x6 + + + B_0x7 + 390 to 450 MHz + 0x7 + + + B_0x8 + 450 to 510 MHz + 0x8 + + + + + + + DSI_DPDL0SRCR + DSI_DPDL0SRCR + DSI D-PHY data lane 0 skew rate control register + 0xca0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SRC + Slew rate control +This field selects the slew rate for HS-TX speed. +Others: Reserved + 0 + 8 + read-write + + + B_0xE + 80 to 750 Mbit/s + 0xE + + + + + + + DSI_DPDL1BCR + DSI_DPDL1BCR + DSI D-PHY data lane 1 band control register + 0xd08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BC + Band control +This field selects the frequency band used by the D-PHY. +Others: Reserved + 0 + 5 + read-write + + + B_0x0 + 80 to 100 MHz + 0x0 + + + B_0x1 + 100 to 120 MHz + 0x1 + + + B_0x2 + 120 to 160 MHz + 0x2 + + + B_0x3 + 160 to 200 MHz + 0x3 + + + B_0x4 + 200 to 240 MHz + 0x4 + + + B_0x5 + 240 to 320 MHz + 0x5 + + + B_0x6 + 320 to 390 MHz + 0x6 + + + B_0x7 + 390 to 450 MHz + 0x7 + + + B_0x8 + 450 to 510 MHz + 0x8 + + + + + + + DSI_DPDL1SRCR + DSI_DPDL1SRCR + DSI D-PHY data lane 1 skew rate control register + 0xd38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SRC + Slew rate control +This field selects the slew rate for HS-TX speed. +Others: Reserved + 0 + 8 + read-write + + + B_0xE + 80 to 750 Mbit/s + 0xE + + + + + + + + + SEC_DSI + DCB->DSCSR->CDS == 0 + 0x50016C00 + + + EXTI + External interrupt/event + controller + EXTI + 0x46022000 + + 0x0 + 0x400 + registers + + + PVD_PVM + Power voltage monitor/Analog voltage monitor + 001 + + + EXTI0 + EXTI line0 interrupt + 011 + + + EXTI1 + EXTI line1 interrupt + 012 + + + EXTI2 + EXTI line2 interrupt + 013 + + + EXTI3 + EXTI line3 interrupt + 014 + + + EXTI4 + EXTI line4 interrupt + 015 + + + EXTI5 + EXTI line5 interrupt + 016 + + + EXTI6 + EXTI line6 interrupt + 017 + + + EXTI7 + EXTI line7 interrupt + 018 + + + EXTI8 + EXTI line8 interrupt + 019 + + + EXTI9 + EXTI line9 interrupt + 020 + + + EXTI10 + EXTI line10 interrupt + 021 + + + EXTI11 + EXTI line11 interrupt + 022 + + + EXTI12 + EXTI line12 interrupt + 023 + + + EXTI13 + EXTI line13 interrupt + 024 + + + EXTI14 + EXTI line14 interrupt + 025 + + + EXTI15 + EXTI line15 interrupt + 026 + + + FPU + Floating point interrupt + 95 + + + LSECSSD + LSECSSD interrupt + 125 + + + GPU2D_IRQ + GPU2D interrupt + 132 + + + GPU2D_IRQSYS + GPU2D system interrupt + 133 + + + + EXTI_RTSR1 + EXTI_RTSR1 + EXTI rising trigger selection register + 0x000 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RT0 + Rising trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. +Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 0 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT1 + Rising trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. +Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 1 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT2 + Rising trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. +Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 2 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT3 + Rising trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. +Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 3 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT4 + Rising trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. +Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 4 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT5 + Rising trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. +Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 5 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT6 + Rising trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. +Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 6 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT7 + Rising trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. +Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 7 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT8 + Rising trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. +Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 8 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT9 + Rising trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. +Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 9 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT10 + Rising trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. +Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 10 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT11 + Rising trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. +Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 11 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT12 + Rising trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. +Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 12 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT13 + Rising trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. +Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 13 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT14 + Rising trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. +Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 14 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT15 + Rising trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. +Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 15 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT16 + Rising trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. +Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 16 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT17 + Rising trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. +Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 17 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT18 + Rising trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. +Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 18 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT19 + Rising trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. +Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 19 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT20 + Rising trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. +Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 20 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT21 + Rising trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. +Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 21 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT22 + Rising trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. +Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 22 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT23 + Rising trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. +Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 23 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT24 + Rising trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. +Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 24 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT25 + Rising trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. +Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 25 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + + + EXTI_FTSR1 + EXTI_FTSR1 + EXTI falling trigger selection register + 0x004 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FT0 + Falling trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. +Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 0 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and interrupt) for input line. + 0x1 + + + + + FT1 + Falling trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. +Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 1 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and interrupt) for input line. + 0x1 + + + + + FT2 + Falling trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. +Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 2 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and interrupt) for input line. + 0x1 + + + + + FT3 + Falling trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. +Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 3 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and interrupt) for input line. + 0x1 + + + + + FT4 + Falling trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. +Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 4 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and interrupt) for input line. + 0x1 + + + + + FT5 + Falling trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. +Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 5 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and interrupt) for input line. + 0x1 + + + + + FT6 + Falling trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. +Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 6 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and interrupt) for input line. + 0x1 + + + + + FT7 + Falling trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. +Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 7 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and interrupt) for input line. + 0x1 + + + + + FT8 + Falling trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. +Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 8 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and interrupt) for input line. + 0x1 + + + + + FT9 + Falling trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. +Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 9 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and interrupt) for input line. + 0x1 + + + + + FT10 + Falling trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. +Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 10 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and interrupt) for input line. + 0x1 + + + + + FT11 + Falling trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. +Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 11 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and interrupt) for input line. + 0x1 + + + + + FT12 + Falling trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. +Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 12 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and interrupt) for input line. + 0x1 + + + + + FT13 + Falling trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. +Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 13 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and interrupt) for input line. + 0x1 + + + + + FT14 + Falling trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. +Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 14 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and interrupt) for input line. + 0x1 + + + + + FT15 + Falling trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. +Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 15 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and interrupt) for input line. + 0x1 + + + + + FT16 + Falling trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. +Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 16 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and interrupt) for input line. + 0x1 + + + + + FT17 + Falling trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. +Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 17 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and interrupt) for input line. + 0x1 + + + + + FT18 + Falling trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. +Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 18 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and interrupt) for input line. + 0x1 + + + + + FT19 + Falling trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. +Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 19 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and interrupt) for input line. + 0x1 + + + + + FT20 + Falling trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. +Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 20 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and interrupt) for input line. + 0x1 + + + + + FT21 + Falling trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. +Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 21 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and interrupt) for input line. + 0x1 + + + + + FT22 + Falling trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. +Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 22 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and interrupt) for input line. + 0x1 + + + + + FT23 + Falling trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. +Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 23 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and interrupt) for input line. + 0x1 + + + + + FT24 + Falling trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. +Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 24 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and interrupt) for input line. + 0x1 + + + + + FT25 + Falling trigger event configuration bit of configurable event input x +When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. +Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 25 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and interrupt) for input line. + 0x1 + + + + + + + EXTI_SWIER1 + EXTI_SWIER1 + EXTI software interrupt event register + 0x008 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SWI0 + Software interrupt on event x +When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. +A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. +Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 0 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. + 0x1 + + + + + SWI1 + Software interrupt on event x +When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. +A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. +Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 1 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. + 0x1 + + + + + SWI2 + Software interrupt on event x +When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. +A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. +Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 2 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. + 0x1 + + + + + SWI3 + Software interrupt on event x +When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. +A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. +Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 3 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. + 0x1 + + + + + SWI4 + Software interrupt on event x +When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. +A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. +Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 4 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. + 0x1 + + + + + SWI5 + Software interrupt on event x +When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. +A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. +Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 5 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. + 0x1 + + + + + SWI6 + Software interrupt on event x +When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. +A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. +Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 6 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. + 0x1 + + + + + SWI7 + Software interrupt on event x +When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. +A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. +Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 7 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. + 0x1 + + + + + SWI8 + Software interrupt on event x +When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. +A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. +Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 8 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. + 0x1 + + + + + SWI9 + Software interrupt on event x +When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. +A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. +Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 9 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. + 0x1 + + + + + SWI10 + Software interrupt on event x +When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. +A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. +Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 10 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. + 0x1 + + + + + SWI11 + Software interrupt on event x +When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. +A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. +Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 11 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. + 0x1 + + + + + SWI12 + Software interrupt on event x +When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. +A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. +Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 12 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. + 0x1 + + + + + SWI13 + Software interrupt on event x +When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. +A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. +Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 13 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. + 0x1 + + + + + SWI14 + Software interrupt on event x +When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. +A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. +Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 14 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. + 0x1 + + + + + SWI15 + Software interrupt on event x +When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. +A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. +Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 15 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. + 0x1 + + + + + SWI16 + Software interrupt on event x +When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. +A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. +Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 16 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. + 0x1 + + + + + SWI17 + Software interrupt on event x +When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. +A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. +Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 17 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. + 0x1 + + + + + SWI18 + Software interrupt on event x +When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. +A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. +Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 18 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. + 0x1 + + + + + SWI19 + Software interrupt on event x +When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. +A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. +Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 19 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. + 0x1 + + + + + SWI20 + Software interrupt on event x +When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. +A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. +Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 20 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. + 0x1 + + + + + SWI21 + Software interrupt on event x +When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. +A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. +Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 21 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. + 0x1 + + + + + SWI22 + Software interrupt on event x +When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. +A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. +Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 22 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. + 0x1 + + + + + SWI23 + Software interrupt on event x +When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. +A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. +Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 23 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. + 0x1 + + + + + SWI24 + Software interrupt on event x +When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. +A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. +Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 24 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. + 0x1 + + + + + SWI25 + Software interrupt on event x +When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. +A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. +Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 25 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. + 0x1 + + + + + + + EXTI_RPR1 + EXTI_RPR1 + EXTI rising edge pending register + 0x00C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RPIF0 + configurable event inputs x rising edge pending bit +When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. +This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. +RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. +Note: If not present, consider this bit as reserved and keep at reset value. + 0 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF1 + configurable event inputs x rising edge pending bit +When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. +This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. +RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. +Note: If not present, consider this bit as reserved and keep at reset value. + 1 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF2 + configurable event inputs x rising edge pending bit +When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. +This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. +RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. +Note: If not present, consider this bit as reserved and keep at reset value. + 2 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF3 + configurable event inputs x rising edge pending bit +When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. +This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. +RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. +Note: If not present, consider this bit as reserved and keep at reset value. + 3 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF4 + configurable event inputs x rising edge pending bit +When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. +This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. +RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. +Note: If not present, consider this bit as reserved and keep at reset value. + 4 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF5 + configurable event inputs x rising edge pending bit +When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. +This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. +RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. +Note: If not present, consider this bit as reserved and keep at reset value. + 5 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF6 + configurable event inputs x rising edge pending bit +When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. +This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. +RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. +Note: If not present, consider this bit as reserved and keep at reset value. + 6 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF7 + configurable event inputs x rising edge pending bit +When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. +This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. +RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. +Note: If not present, consider this bit as reserved and keep at reset value. + 7 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF8 + configurable event inputs x rising edge pending bit +When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. +This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. +RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. +Note: If not present, consider this bit as reserved and keep at reset value. + 8 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF9 + configurable event inputs x rising edge pending bit +When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. +This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. +RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. +Note: If not present, consider this bit as reserved and keep at reset value. + 9 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF10 + configurable event inputs x rising edge pending bit +When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. +This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. +RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. +Note: If not present, consider this bit as reserved and keep at reset value. + 10 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF11 + configurable event inputs x rising edge pending bit +When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. +This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. +RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. +Note: If not present, consider this bit as reserved and keep at reset value. + 11 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF12 + configurable event inputs x rising edge pending bit +When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. +This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. +RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. +Note: If not present, consider this bit as reserved and keep at reset value. + 12 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF13 + configurable event inputs x rising edge pending bit +When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. +This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. +RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. +Note: If not present, consider this bit as reserved and keep at reset value. + 13 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF14 + configurable event inputs x rising edge pending bit +When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. +This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. +RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. +Note: If not present, consider this bit as reserved and keep at reset value. + 14 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF15 + configurable event inputs x rising edge pending bit +When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. +This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. +RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. +Note: If not present, consider this bit as reserved and keep at reset value. + 15 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF16 + configurable event inputs x rising edge pending bit +When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. +This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. +RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. +Note: If not present, consider this bit as reserved and keep at reset value. + 16 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF17 + configurable event inputs x rising edge pending bit +When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. +This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. +RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. +Note: If not present, consider this bit as reserved and keep at reset value. + 17 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF18 + configurable event inputs x rising edge pending bit +When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. +This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. +RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. +Note: If not present, consider this bit as reserved and keep at reset value. + 18 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF19 + configurable event inputs x rising edge pending bit +When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. +This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. +RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. +Note: If not present, consider this bit as reserved and keep at reset value. + 19 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF20 + configurable event inputs x rising edge pending bit +When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. +This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. +RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. +Note: If not present, consider this bit as reserved and keep at reset value. + 20 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF21 + configurable event inputs x rising edge pending bit +When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. +This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. +RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. +Note: If not present, consider this bit as reserved and keep at reset value. + 21 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF22 + configurable event inputs x rising edge pending bit +When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. +This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. +RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. +Note: If not present, consider this bit as reserved and keep at reset value. + 22 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF23 + configurable event inputs x rising edge pending bit +When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. +This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. +RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. +Note: If not present, consider this bit as reserved and keep at reset value. + 23 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF24 + configurable event inputs x rising edge pending bit +When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. +This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. +RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. +Note: If not present, consider this bit as reserved and keep at reset value. + 24 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF25 + configurable event inputs x rising edge pending bit +When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. +This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. +RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. +Note: If not present, consider this bit as reserved and keep at reset value. + 25 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + + + EXTI_FPR1 + EXTI_FPR1 + EXTI falling edge pending register + 0x010 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FPIF0 + configurable event inputs x falling edge pending bit +When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. +This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. +Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 0 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF1 + configurable event inputs x falling edge pending bit +When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. +This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. +Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 1 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF2 + configurable event inputs x falling edge pending bit +When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. +This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. +Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 2 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF3 + configurable event inputs x falling edge pending bit +When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. +This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. +Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 3 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF4 + configurable event inputs x falling edge pending bit +When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. +This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. +Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 4 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF5 + configurable event inputs x falling edge pending bit +When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. +This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. +Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 5 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF6 + configurable event inputs x falling edge pending bit +When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. +This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. +Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 6 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF7 + configurable event inputs x falling edge pending bit +When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. +This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. +Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 7 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF8 + configurable event inputs x falling edge pending bit +When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. +This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. +Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 8 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF9 + configurable event inputs x falling edge pending bit +When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. +This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. +Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 9 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF10 + configurable event inputs x falling edge pending bit +When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. +This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. +Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 10 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF11 + configurable event inputs x falling edge pending bit +When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. +This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. +Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 11 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF12 + configurable event inputs x falling edge pending bit +When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. +This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. +Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 12 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF13 + configurable event inputs x falling edge pending bit +When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. +This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. +Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 13 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF14 + configurable event inputs x falling edge pending bit +When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. +This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. +Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 14 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF15 + configurable event inputs x falling edge pending bit +When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. +This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. +Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 15 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF16 + configurable event inputs x falling edge pending bit +When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. +This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. +Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 16 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF17 + configurable event inputs x falling edge pending bit +When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. +This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. +Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 17 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF18 + configurable event inputs x falling edge pending bit +When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. +This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. +Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 18 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF19 + configurable event inputs x falling edge pending bit +When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. +This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. +Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 19 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF20 + configurable event inputs x falling edge pending bit +When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. +This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. +Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 20 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF21 + configurable event inputs x falling edge pending bit +When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. +This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. +Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 21 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF22 + configurable event inputs x falling edge pending bit +When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. +This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. +Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 22 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF23 + configurable event inputs x falling edge pending bit +When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. +This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. +Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 23 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF24 + configurable event inputs x falling edge pending bit +When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. +This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. +Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 24 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF25 + configurable event inputs x falling edge pending bit +When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. +This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. +Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 25 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + + + EXTI_SECCFGR1 + EXTI_SECCFGR1 + EXTI security configuration register + 0x014 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEC0 + Security enable on event input x +When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. +Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 0 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC1 + Security enable on event input x +When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. +Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 1 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC2 + Security enable on event input x +When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. +Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 2 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC3 + Security enable on event input x +When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. +Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 3 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC4 + Security enable on event input x +When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. +Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 4 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC5 + Security enable on event input x +When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. +Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 5 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC6 + Security enable on event input x +When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. +Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 6 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC7 + Security enable on event input x +When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. +Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 7 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC8 + Security enable on event input x +When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. +Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 8 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC9 + Security enable on event input x +When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. +Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 9 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC10 + Security enable on event input x +When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. +Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 10 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC11 + Security enable on event input x +When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. +Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 11 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC12 + Security enable on event input x +When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. +Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 12 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC13 + Security enable on event input x +When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. +Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 13 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC14 + Security enable on event input x +When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. +Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 14 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC15 + Security enable on event input x +When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. +Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 15 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC16 + Security enable on event input x +When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. +Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 16 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC17 + Security enable on event input x +When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. +Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 17 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC18 + Security enable on event input x +When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. +Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 18 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC19 + Security enable on event input x +When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. +Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 19 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC20 + Security enable on event input x +When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. +Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 20 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC21 + Security enable on event input x +When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. +Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 21 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC22 + Security enable on event input x +When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. +Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 22 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC23 + Security enable on event input x +When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. +Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 23 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC24 + Security enable on event input x +When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. +Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 24 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC25 + Security enable on event input x +When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. +Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 25 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + + + EXTI_PRIVCFGR1 + EXTI_PRIVCFGR1 + EXTI privilege configuration register + 0x018 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIV0 + Security enable on event input x +When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. +When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. +Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 0 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV1 + Security enable on event input x +When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. +When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. +Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 1 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV2 + Security enable on event input x +When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. +When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. +Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 2 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV3 + Security enable on event input x +When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. +When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. +Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 3 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV4 + Security enable on event input x +When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. +When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. +Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 4 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV5 + Security enable on event input x +When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. +When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. +Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 5 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV6 + Security enable on event input x +When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. +When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. +Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 6 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV7 + Security enable on event input x +When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. +When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. +Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 7 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV8 + Security enable on event input x +When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. +When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. +Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 8 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV9 + Security enable on event input x +When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. +When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. +Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 9 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV10 + Security enable on event input x +When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. +When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. +Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 10 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV11 + Security enable on event input x +When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. +When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. +Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 11 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV12 + Security enable on event input x +When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. +When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. +Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 12 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV13 + Security enable on event input x +When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. +When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. +Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 13 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV14 + Security enable on event input x +When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. +When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. +Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 14 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV15 + Security enable on event input x +When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. +When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. +Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 15 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV16 + Security enable on event input x +When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. +When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. +Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 16 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV17 + Security enable on event input x +When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. +When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. +Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 17 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV18 + Security enable on event input x +When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. +When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. +Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 18 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV19 + Security enable on event input x +When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. +When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. +Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 19 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV20 + Security enable on event input x +When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. +When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. +Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 20 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV21 + Security enable on event input x +When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. +When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. +Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 21 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV22 + Security enable on event input x +When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. +When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. +Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 22 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV23 + Security enable on event input x +When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. +When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. +Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 23 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV24 + Security enable on event input x +When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. +When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. +Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 24 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV25 + Security enable on event input x +When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. +When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. +Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 25 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + + + EXTI_EXTICR1 + EXTI_EXTICR1 + EXTI external interrupt selection register + 0x60 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EXTI0 + EXTIm GPIO port selection + 0 + 8 + read-write + + + EXTI1 + EXTIm+1 GPIO port selection + 8 + 8 + read-write + + + EXTI2 + EXTIm+2 GPIO port selection + 16 + 8 + read-write + + + EXTI3 + EXTIm+3 GPIO port selection + 24 + 8 + read-write + + + + + EXTI_EXTICR2 + EXTI_EXTICR2 + EXTI external interrupt selection register + 0x64 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EXTI4 + EXTIm GPIO port selection + 0 + 8 + read-write + + + EXTI5 + EXTIm+1 GPIO port selection + 8 + 8 + read-write + + + EXTI6 + EXTIm+2 GPIO port selection + 16 + 8 + read-write + + + EXTI7 + EXTIm+3 GPIO port selection + 24 + 8 + read-write + + + + + EXTI_EXTICR3 + EXTI_EXTICR3 + EXTI external interrupt selection register + 0x68 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EXTI8 + EXTIm GPIO port selection + 0 + 8 + read-write + + + EXTI9 + EXTIm+1 GPIO port selection + 8 + 8 + read-write + + + EXTI10 + EXTIm+2 GPIO port selection + 16 + 8 + read-write + + + EXTI11 + EXTIm+3 GPIO port selection + 24 + 8 + read-write + + + + + EXTI_EXTICR4 + EXTI_EXTICR4 + EXTI external interrupt selection register + 0x6C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EXTI12 + EXTIm GPIO port selection + 0 + 8 + read-write + + + EXTI13 + EXTIm+1 GPIO port selection + 8 + 8 + read-write + + + EXTI14 + EXTIm+2 GPIO port selection + 16 + 8 + read-write + + + EXTI15 + EXTIm+3 GPIO port selection + 24 + 8 + read-write + + + + + EXTI_LOCKR + EXTI_LOCKR + EXTI lock register + 0x070 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LOCK + Global security and privilege configuration registers (EXTI_SECCFGR and EXTI_PRIVCFGR) lock +This bit is written once after reset. + 0 + 1 + read-write + + + B_0x0 + Security and privilege configuration open, can be modified. + 0x0 + + + B_0x1 + Security and privilege configuration locked, can no longer be modified. + 0x1 + + + + + + + EXTI_IMR1 + EXTI_IMR1 + EXTI CPU wake-up with interrupt mask register + 0x080 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IM0 + CPU wake-up with interrupt mask on event input x +When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 0 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM1 + CPU wake-up with interrupt mask on event input x +When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 1 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM2 + CPU wake-up with interrupt mask on event input x +When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 2 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM3 + CPU wake-up with interrupt mask on event input x +When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 3 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM4 + CPU wake-up with interrupt mask on event input x +When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 4 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM5 + CPU wake-up with interrupt mask on event input x +When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 5 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM6 + CPU wake-up with interrupt mask on event input x +When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 6 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM7 + CPU wake-up with interrupt mask on event input x +When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 7 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM8 + CPU wake-up with interrupt mask on event input x +When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 8 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM9 + CPU wake-up with interrupt mask on event input x +When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 9 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM10 + CPU wake-up with interrupt mask on event input x +When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 10 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM11 + CPU wake-up with interrupt mask on event input x +When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 11 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM12 + CPU wake-up with interrupt mask on event input x +When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 12 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM13 + CPU wake-up with interrupt mask on event input x +When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 13 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM14 + CPU wake-up with interrupt mask on event input x +When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 14 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM15 + CPU wake-up with interrupt mask on event input x +When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 15 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM16 + CPU wake-up with interrupt mask on event input x +When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 16 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM17 + CPU wake-up with interrupt mask on event input x +When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 17 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM18 + CPU wake-up with interrupt mask on event input x +When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 18 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM19 + CPU wake-up with interrupt mask on event input x +When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 19 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM20 + CPU wake-up with interrupt mask on event input x +When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 20 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM21 + CPU wake-up with interrupt mask on event input x +When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 21 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM22 + CPU wake-up with interrupt mask on event input x +When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 22 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM23 + CPU wake-up with interrupt mask on event input x +When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 23 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM24 + CPU wake-up with interrupt mask on event input x +When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 24 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM25 + CPU wake-up with interrupt mask on event input x +When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 25 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + + + EXTI_EMR1 + EXTI_EMR1 + EXTI CPU wake-up with event mask register + 0x084 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EM0 + CPU wake-up with event generation mask on event input x +When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 0 + 1 + read-write + + + B_0x0 + Wake-up with event generation from line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from line x is unmasked. + 0x1 + + + + + EM1 + CPU wake-up with event generation mask on event input x +When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 1 + 1 + read-write + + + B_0x0 + Wake-up with event generation from line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from line x is unmasked. + 0x1 + + + + + EM2 + CPU wake-up with event generation mask on event input x +When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 2 + 1 + read-write + + + B_0x0 + Wake-up with event generation from line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from line x is unmasked. + 0x1 + + + + + EM3 + CPU wake-up with event generation mask on event input x +When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 3 + 1 + read-write + + + B_0x0 + Wake-up with event generation from line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from line x is unmasked. + 0x1 + + + + + EM4 + CPU wake-up with event generation mask on event input x +When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 4 + 1 + read-write + + + B_0x0 + Wake-up with event generation from line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from line x is unmasked. + 0x1 + + + + + EM5 + CPU wake-up with event generation mask on event input x +When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 5 + 1 + read-write + + + B_0x0 + Wake-up with event generation from line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from line x is unmasked. + 0x1 + + + + + EM6 + CPU wake-up with event generation mask on event input x +When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 6 + 1 + read-write + + + B_0x0 + Wake-up with event generation from line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from line x is unmasked. + 0x1 + + + + + EM7 + CPU wake-up with event generation mask on event input x +When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 7 + 1 + read-write + + + B_0x0 + Wake-up with event generation from line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from line x is unmasked. + 0x1 + + + + + EM8 + CPU wake-up with event generation mask on event input x +When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 8 + 1 + read-write + + + B_0x0 + Wake-up with event generation from line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from line x is unmasked. + 0x1 + + + + + EM9 + CPU wake-up with event generation mask on event input x +When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 9 + 1 + read-write + + + B_0x0 + Wake-up with event generation from line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from line x is unmasked. + 0x1 + + + + + EM10 + CPU wake-up with event generation mask on event input x +When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 10 + 1 + read-write + + + B_0x0 + Wake-up with event generation from line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from line x is unmasked. + 0x1 + + + + + EM11 + CPU wake-up with event generation mask on event input x +When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 11 + 1 + read-write + + + B_0x0 + Wake-up with event generation from line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from line x is unmasked. + 0x1 + + + + + EM12 + CPU wake-up with event generation mask on event input x +When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 12 + 1 + read-write + + + B_0x0 + Wake-up with event generation from line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from line x is unmasked. + 0x1 + + + + + EM13 + CPU wake-up with event generation mask on event input x +When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 13 + 1 + read-write + + + B_0x0 + Wake-up with event generation from line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from line x is unmasked. + 0x1 + + + + + EM14 + CPU wake-up with event generation mask on event input x +When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 14 + 1 + read-write + + + B_0x0 + Wake-up with event generation from line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from line x is unmasked. + 0x1 + + + + + EM15 + CPU wake-up with event generation mask on event input x +When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 15 + 1 + read-write + + + B_0x0 + Wake-up with event generation from line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from line x is unmasked. + 0x1 + + + + + EM16 + CPU wake-up with event generation mask on event input x +When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 16 + 1 + read-write + + + B_0x0 + Wake-up with event generation from line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from line x is unmasked. + 0x1 + + + + + EM17 + CPU wake-up with event generation mask on event input x +When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 17 + 1 + read-write + + + B_0x0 + Wake-up with event generation from line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from line x is unmasked. + 0x1 + + + + + EM18 + CPU wake-up with event generation mask on event input x +When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 18 + 1 + read-write + + + B_0x0 + Wake-up with event generation from line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from line x is unmasked. + 0x1 + + + + + EM19 + CPU wake-up with event generation mask on event input x +When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 19 + 1 + read-write + + + B_0x0 + Wake-up with event generation from line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from line x is unmasked. + 0x1 + + + + + EM20 + CPU wake-up with event generation mask on event input x +When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 20 + 1 + read-write + + + B_0x0 + Wake-up with event generation from line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from line x is unmasked. + 0x1 + + + + + EM21 + CPU wake-up with event generation mask on event input x +When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 21 + 1 + read-write + + + B_0x0 + Wake-up with event generation from line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from line x is unmasked. + 0x1 + + + + + EM22 + CPU wake-up with event generation mask on event input x +When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 22 + 1 + read-write + + + B_0x0 + Wake-up with event generation from line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from line x is unmasked. + 0x1 + + + + + EM23 + CPU wake-up with event generation mask on event input x +When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 23 + 1 + read-write + + + B_0x0 + Wake-up with event generation from line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from line x is unmasked. + 0x1 + + + + + EM24 + CPU wake-up with event generation mask on event input x +When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 24 + 1 + read-write + + + B_0x0 + Wake-up with event generation from line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from line x is unmasked. + 0x1 + + + + + EM25 + CPU wake-up with event generation mask on event input x +When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. +When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. +When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. +When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. +Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. + 25 + 1 + read-write + + + B_0x0 + Wake-up with event generation from line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from line x is unmasked. + 0x1 + + + + + + + + + SEC_EXTI + DCB->DSCSR->CDS == 0 + 0x56022000 + + + FDCAN1_RAM + FDCAN1_RAM + FDCAN + 0x4000AC00 + + 0x0 + 0x400 + registers + + + FDCAN1_IT0 + FDCAN1 Interrupt 0 + 039 + + + FDCAN1_IT1 + FDCAN1 Interrupt 1 + 040 + + + + FDCAN_CREL + FDCAN_CREL + FDCAN Core Release Register + 0x0 + 0x20 + read-only + 0x32141218 + + + REL + Core release + 28 + 4 + + + STEP + Step of Core release + 24 + 4 + + + SUBSTEP + Sub-step of Core release + 20 + 4 + + + YEAR + Timestamp Year + 16 + 4 + + + MON + Timestamp Month + 8 + 8 + + + DAY + Timestamp Day + 0 + 8 + + + + + FDCAN_ENDN + FDCAN_ENDN + FDCAN endian register + 0x4 + 0x20 + read-only + 0x87654321 + + + ETV + Endiannes Test Value + 0 + 32 + + + + + FDCAN_DBTP + FDCAN_DBTP + FDCAN Data Bit Timing and Prescaler + Register + 0xC + 0x20 + read-write + 0x00000A33 + + + DSJW + Synchronization Jump Width + 0 + 4 + + + DTSEG2 + Data time segment after sample + point + 4 + 4 + + + DTSEG1 + Data time segment after sample + point + 8 + 5 + + + DBRP + Data BIt Rate Prescaler + 16 + 5 + + + TDC + Transceiver Delay + Compensation + 23 + 1 + + + + + FDCAN_TEST + FDCAN_TEST + FDCAN Test Register + 0x10 + 0x20 + 0x00000000 + + + LBCK + Loop Back mode + 4 + 1 + read-write + + + TX + Loop Back mode + 5 + 2 + read-write + + + RX + Control of Transmit Pin + 7 + 1 + read-only + + + + + FDCAN_RWD + FDCAN_RWD + FDCAN RAM Watchdog Register + 0x14 + 0x20 + 0x00000000 + + + WDV + Watchdog value + 8 + 8 + read-only + + + WDC + Watchdog configuration + 0 + 8 + read-write + + + + + FDCAN_CCCR + FDCAN_CCCR + FDCAN CC Control Register + 0x18 + 0x20 + read-write + 0x00000001 + + + INIT + Initialization + 0 + 1 + + + CCE + Configuration Change + Enable + 1 + 1 + + + ASM + ASM Restricted Operation + Mode + 2 + 1 + + + CSA + Clock Stop Acknowledge + 3 + 1 + + + CSR + Clock Stop Request + 4 + 1 + + + MON + Bus Monitoring Mode + 5 + 1 + + + DAR + Disable Automatic + Retransmission + 6 + 1 + + + TEST + Test Mode Enable + 7 + 1 + + + FDOE + FD Operation Enable + 8 + 1 + + + BRSE + FDCAN Bit Rate Switching + 9 + 1 + + + PXHD + Protocol Exception Handling + Disable + 12 + 1 + + + EFBI + Edge Filtering during Bus + Integration + 13 + 1 + + + TXP + TXP + 14 + 1 + + + NISO + Non ISO Operation + 15 + 1 + + + + + FDCAN_NBTP + FDCAN_NBTP + FDCAN Nominal Bit Timing and Prescaler + Register + 0x1C + 0x20 + read-write + 0x06000A03 + + + NSJW + Nominal (Re)Synchronization Jump + Width + 25 + 7 + + + NBRP + Bit Rate Prescaler + 16 + 9 + + + NTSEG1 + Nominal Time segment before sample + point + 8 + 8 + + + NTSEG2 + Nominal Time segment after sample + point + 0 + 7 + + + + + FDCAN_TSCC + FDCAN_TSCC + FDCAN Timestamp Counter Configuration + Register + 0x20 + 0x20 + read-write + 0x00000000 + + + TCP + Timestamp Counter + Prescaler + 16 + 4 + + + TSS + Timestamp Select + 0 + 2 + + + + + FDCAN_TSCV + FDCAN_TSCV + FDCAN Timestamp Counter Value + Register + 0x24 + 0x20 + read-write + 0x00000000 + + + TSC + Timestamp Counter + 0 + 16 + + + + + FDCAN_TOCC + FDCAN_TOCC + FDCAN Timeout Counter Configuration + Register + 0x28 + 0x20 + read-write + 0xFFFF0000 + + + ETOC + Enable Timeout Counter + 0 + 1 + + + TOS + Timeout Select + 1 + 2 + + + TOP + Timeout Period + 16 + 16 + + + + + FDCAN_TOCV + FDCAN_TOCV + FDCAN Timeout Counter Value + Register + 0x2C + 0x20 + read-write + 0x0000FFFF + + + TOC + Timeout Counter + 0 + 16 + + + + + FDCAN_ECR + FDCAN_ECR + FDCAN Error Counter Register + 0x40 + 0x20 + 0x00000000 + + + CEL + AN Error Logging + 16 + 8 + read-write + + + RP + Receive Error Passive + 15 + 1 + read-only + + + REC + Receive Error Counter + 8 + 7 + read-only + + + TEC + Transmit Error Counter + 0 + 8 + read-only + + + + + FDCAN_PSR + FDCAN_PSR + FDCAN Protocol Status Register + 0x44 + 0x20 + 0x00000707 + + + LEC + Last Error Code + 0 + 3 + read-write + + + ACT + Activity + 3 + 2 + read-only + + + EP + Error Passive + 5 + 1 + read-only + + + EW + Warning Status + 6 + 1 + read-only + + + BO + Bus_Off Status + 7 + 1 + read-only + + + DLEC + Data Last Error Code + 8 + 3 + read-write + + + RESI + ESI flag of last received FDCAN + Message + 11 + 1 + read-write + + + RBRS + BRS flag of last received FDCAN + Message + 12 + 1 + read-write + + + REDL + Received FDCAN Message + 13 + 1 + read-write + + + PXE + Protocol Exception Event + 14 + 1 + read-write + + + TDCV + Transmitter Delay Compensation + Value + 16 + 7 + read-only + + + + + FDCAN_TDCR + FDCAN_TDCR + FDCAN Transmitter Delay Compensation + Register + 0x48 + 0x20 + read-write + 0x00000000 + + + TDCF + Transmitter Delay Compensation Filter + Window Length + 0 + 7 + + + TDCO + Transmitter Delay Compensation + Offset + 8 + 7 + + + + + FDCAN_IR + FDCAN_IR + FDCAN Interrupt Register + 0x50 + 0x20 + read-write + 0x00000000 + + + RF0N + RF0N + 0 + 1 + + + RF0F + RF0F + 1 + 1 + + + RF0L + RF0L + 2 + 1 + + + RF1N + RF1N + 3 + 1 + + + RF1F + RF1F + 4 + 1 + + + RF1L + RF1L + 5 + 1 + + + HPM + HPM + 6 + 1 + + + TC + TC + 7 + 1 + + + TCF + TCF + 8 + 1 + + + TFE + TFE + 9 + 1 + + + TEFN + TEFN + 10 + 1 + + + TEFF + TEFF + 11 + 1 + + + TEFL + TEFL + 12 + 1 + + + TSW + TSW + 13 + 1 + + + MRAF + MRAF + 14 + 1 + + + TOO + TOO + 15 + 1 + + + ELO + ELO + 16 + 1 + + + EP + EP + 17 + 1 + + + EW + EW + 18 + 1 + + + BO + BO + 19 + 1 + + + WDI + WDI + 20 + 1 + + + PEA + PEA + 21 + 1 + + + PED + PED + 22 + 1 + + + ARA + ARA + 23 + 1 + + + + + FDCAN_IE + FDCAN_IE + FDCAN Interrupt Enable + Register + 0x54 + 0x20 + read-write + 0x00000000 + + + RF0NE + Rx FIFO 0 New Message + Enable + 0 + 1 + + + RF0FE + Rx FIFO 0 Full Enable + 1 + 1 + + + RF0LE + Rx FIFO 0 Message Lost + Enable + 2 + 1 + + + RF1NE + Rx FIFO 1 New Message + Enable + 3 + 1 + + + RF1FE + Rx FIFO 1 Watermark Reached + Enable + 4 + 1 + + + RF1LE + Rx FIFO 1 Message Lost + Enable + 5 + 1 + + + HPME + High Priority Message + Enable + 6 + 1 + + + TCE + Transmission Completed + Enable + 7 + 1 + + + TCFE + Transmission Cancellation Finished + Enable + 8 + 1 + + + TEFE + Tx FIFO Empty Enable + 9 + 1 + + + TEFNE + Tx Event FIFO New Entry + Enable + 10 + 1 + + + TEFFE + Tx Event FIFO Full Enable + 11 + 1 + + + TEFLE + Tx Event FIFO Element Lost + Enable + 12 + 1 + + + TSWE + TSWE + 13 + 1 + + + MRAFE + Message RAM Access Failure + Enable + 14 + 1 + + + TOOE + Timeout Occurred Enable + 15 + 1 + + + ELOE + Error Logging Overflow + Enable + 16 + 1 + + + EPE + Error Passive Enable + 17 + 1 + + + EWE + Warning Status Enable + 18 + 1 + + + BOE + Bus_Off Status Enable + 19 + 1 + + + WDIE + Watchdog Interrupt Enable + 20 + 1 + + + PEAE + Protocol Error in Arbitration Phase + Enable + 21 + 1 + + + PEDE + Protocol Error in Data Phase + Enable + 22 + 1 + + + ARAE + Access to Reserved Address + Enable + 23 + 1 + + + + + FDCAN_ILS + FDCAN_ILS + FDCAN Interrupt Line Select + Register + 0x58 + 0x20 + read-write + 0x00000000 + + + RxFIFO0 + RxFIFO0 + 0 + 1 + + + RxFIFO1 + RxFIFO1 + 1 + 1 + + + SMSG + SMSG + 2 + 1 + + + TFERR + TFERR + 3 + 1 + + + MISC + MISC + 4 + 1 + + + BERR + BERR + 5 + 1 + + + PERR + PERR + 6 + 1 + + + + + FDCAN_ILE + FDCAN_ILE + FDCAN Interrupt Line Enable + Register + 0x5C + 0x20 + read-write + 0x00000000 + + + EINT0 + Enable Interrupt Line 0 + 0 + 1 + + + EINT1 + Enable Interrupt Line 1 + 1 + 1 + + + + + FDCAN_RXGFC + FDCAN_RXGFC + FDCAN Global Filter Configuration + Register + 0x80 + 0x20 + read-write + 0x00000000 + + + RRFE + Reject Remote Frames + Extended + 0 + 1 + + + RRFS + Reject Remote Frames + Standard + 1 + 1 + + + ANFE + Accept Non-matching Frames + Extended + 2 + 2 + + + ANFS + Accept Non-matching Frames + Standard + 4 + 2 + + + F1OM + F1OM + 8 + 1 + + + F0OM + F0OM + 9 + 1 + + + LSS + LSS + 16 + 5 + + + LSE + LSE + 24 + 4 + + + + + FDCAN_XIDAM + FDCAN_XIDAM + FDCAN Extended ID and Mask + Register + 0x84 + 0x20 + read-write + 0x1FFFFFFF + + + EIDM + Extended ID Mask + 0 + 29 + + + + + FDCAN_HPMS + FDCAN_HPMS + FDCAN High Priority Message Status + Register + 0x88 + 0x20 + read-only + 0x00000000 + + + BIDX + Buffer Index + 0 + 3 + + + MSI + Message Storage Indicator + 6 + 2 + + + FIDX + Filter Index + 8 + 5 + + + FLST + Filter List + 15 + 1 + + + + + FDCAN_RXF0S + FDCAN_RXF0S + FDCAN Rx FIFO 0 Status + Register + 0x90 + 0x20 + read-only + 0x00000000 + + + F0FL + Rx FIFO 0 Fill Level + 0 + 4 + + + F0GI + Rx FIFO 0 Get Index + 8 + 2 + + + F0PI + Rx FIFO 0 Put Index + 16 + 2 + + + F0F + Rx FIFO 0 Full + 24 + 1 + + + RF0L + Rx FIFO 0 Message Lost + 25 + 1 + + + + + FDCAN_RXF0A + FDCAN_RXF0A + CAN Rx FIFO 0 Acknowledge + Register + 0x94 + 0x20 + read-write + 0x00000000 + + + F0AI + Rx FIFO 0 Acknowledge + Index + 0 + 3 + + + + + FDCAN_RXF1S + FDCAN_RXF1S + FDCAN Rx FIFO 1 Status + Register + 0x98 + 0x20 + read-only + 0x00000000 + + + F1FL + Rx FIFO 1 Fill Level + 0 + 4 + + + F1GI + Rx FIFO 1 Get Index + 8 + 2 + + + F1PI + Rx FIFO 1 Put Index + 16 + 2 + + + F1F + Rx FIFO 1 Full + 24 + 1 + + + RF1L + Rx FIFO 1 Message Lost + 25 + 1 + + + + + FDCAN_RXF1A + FDCAN_RXF1A + FDCAN Rx FIFO 1 Acknowledge + Register + 0x9C + 0x20 + read-write + 0x00000000 + + + F1AI + Rx FIFO 1 Acknowledge + Index + 0 + 3 + + + + + FDCAN_TXBC + FDCAN_TXBC + FDCAN Tx buffer configuration register + 0xC0 + 0x20 + read-write + 0x00000000 + + + TFQM + Tx FIFO/Queue Mode + 24 + 1 + + + + + FDCAN_TXFQS + FDCAN_TXFQS + FDCAN Tx FIFO/Queue Status + Register + 0xC4 + 0x20 + read-only + 0x00000003 + + + TFFL + Tx FIFO Free Level + 0 + 3 + + + TFGI + TFGI + 8 + 2 + + + TFQPI + Tx FIFO/Queue Put Index + 16 + 2 + + + TFQF + Tx FIFO/Queue Full + 21 + 1 + + + + + FDCAN_TXBRP + FDCAN_TXBRP + FDCAN Tx Buffer Request Pending + Register + 0xC8 + 0x20 + read-only + 0x00000000 + + + TRP + Transmission Request + Pending + 0 + 3 + + + + + FDCAN_TXBAR + FDCAN_TXBAR + FDCAN Tx Buffer Add Request + Register + 0xCC + 0x20 + read-write + 0x00000000 + + + AR + Add Request + 0 + 3 + + + + + FDCAN_TXBCR + FDCAN_TXBCR + FDCAN Tx Buffer Cancellation Request + Register + 0xD0 + 0x20 + read-write + 0x00000000 + + + CR + Cancellation Request + 0 + 3 + + + + + FDCAN_TXBTO + FDCAN_TXBTO + FDCAN Tx Buffer Transmission Occurred + Register + 0xD4 + 0x20 + read-only + 0x00000000 + + + TO + Transmission Occurred. + 0 + 3 + + + + + FDCAN_TXBCF + FDCAN_TXBCF + FDCAN Tx Buffer Cancellation Finished + Register + 0xD8 + 0x20 + read-only + 0x00000000 + + + CF + Cancellation Finished + 0 + 3 + + + + + FDCAN_TXBTIE + FDCAN_TXBTIE + FDCAN Tx Buffer Transmission Interrupt + Enable Register + 0xDC + 0x20 + read-write + 0x00000000 + + + TIE + Transmission Interrupt + Enable + 0 + 3 + + + + + FDCAN_TXBCIE + FDCAN_TXBCIE + FDCAN Tx Buffer Cancellation Finished + Interrupt Enable Register + 0xE0 + 0x20 + read-write + 0x00000000 + + + CFIE + Cancellation Finished Interrupt + Enable + 0 + 3 + + + + + FDCAN_TXEFS + FDCAN_TXEFS + FDCAN Tx Event FIFO Status + Register + 0xE4 + 0x20 + read-only + 0x00000000 + + + EFFL + Event FIFO Fill Level + 0 + 3 + + + EFGI + Event FIFO Get Index. + 8 + 2 + + + EFPI + Event FIFO Put Index + 16 + 2 + + + EFF + Event FIFO Full. + 24 + 1 + + + TEFL + Tx Event FIFO Element + Lost. + 25 + 1 + + + + + FDCAN_TXEFA + FDCAN_TXEFA + FDCAN Tx Event FIFO Acknowledge + Register + 0xE8 + 0x20 + read-write + 0x00000000 + + + EFAI + Event FIFO Acknowledge + Index + 0 + 2 + + + + + FDCAN_CKDIV + FDCAN_CKDIV + FDCAN CFG clock divider register + 0x100 + 0x20 + read-write + 0x00000000 + + + PDIV + PDIV + 0 + 4 + + + + + + + SEC_FDCAN1_RAM + DCB->DSCSR->CDS == 0 + 0x5000AC00 + + + FDCAN1 + 0x4000A400 + + + SEC_FDCAN1 + DCB->DSCSR->CDS == 0 + 0x5000A400 + + + FLASH + Flash + Flash + 0x40022000 + + 0x0 + 0x400 + registers + + + FLASH + Flash memory non-secure global interrupt + 006 + + + FLASH_S + Flash memory secure global interrupt + 007 + + + + FLASH_ACR + FLASH_ACR + FLASH access control register + 0x0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LATENCY + Latency +These bits represent the ratio between the HCLK (AHB clock) period and the Flash memory access time. +... + 0 + 4 + read-write + + + B_0x0 + Zero wait state + 0x0 + + + B_0x1 + One wait state + 0x1 + + + B_0x2 + Two wait states + 0x2 + + + B_0xF + Fifteen wait states + 0xF + + + + + PRFTEN + Prefetch enable +This bit enables the prefetch buffer in the embedded Flash memory. + 8 + 1 + read-write + + + B_0x0 + Prefetch disabled + 0x0 + + + B_0x1 + Prefetch enabled + 0x1 + + + + + LPM + Low-power read mode +This bit puts the Flash memory in low-power read mode. + 11 + 1 + read-write + + + B_0x0 + Flash not in low-power read mode + 0x0 + + + B_0x1 + Flash in low-power read mode + 0x1 + + + + + PDREQ1 + Bank 1 power-down mode request +This bit is write-protected with FLASH_PDKEY1R. This bit requests bank 1 to enter power-down mode. When bank 1 enters power-down mode, this bit is cleared by hardware and the PDKEY1R is locked. + 12 + 1 + read-write + + + B_0x0 + No request for bank 1 to enter power-down mode + 0x0 + + + B_0x1 + Bank 1 requested to enter power-down mode + 0x1 + + + + + PDREQ2 + Bank 2 power-down mode request +This bit is write-protected with FLASH_PDKEY2R. This bit requests bank 2 to enter power-down mode. When bank 2 enters power-down mode, this bit is cleared by hardware and the PDKEY2R is locked. + 13 + 1 + read-write + + + B_0x0 + No request for bank 2 to enter power-down mode + 0x0 + + + B_0x1 + Bank 2 requested to enter power-down mode + 0x1 + + + + + SLEEP_PD + Flash memory power-down mode during Sleep mode +This bit determines whether the Flash memory is in power-down mode or Idle mode when the device is in Sleep mode. +The Flash must not be put in power-down while a program or an erase operation is on-going. + 14 + 1 + read-write + + + B_0x0 + Flash in Idle mode during Sleep mode + 0x0 + + + B_0x1 + Flash in power-down mode during Sleep mode + 0x1 + + + + + + + FLASH_NSKEYR + FLASH_NSKEYR + FLASH non-secure key register + 0x8 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + NSKEY + Flash memory non-secure key +The following values must be written consecutively to unlock the FLASH_NSCR register, allowing the Flash memory non-secure programming/erasing operations: +KEY1: 0x4567 0123 +KEY2: 0xCDEF 89AB + 0 + 32 + write-only + + + + + FLASH_SECKEYR + FLASH_SECKEYR + FLASH secure key register + 0xc + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + SECKEY + Flash memory secure key +The following values must be written consecutively to unlock the FLASH_SECCR register, allowing the Flash memory secure programming/erasing operations: +KEY1: 0x4567 0123 +KEY2: 0xCDEF 89AB + 0 + 32 + write-only + + + + + FLASH_OPTKEYR + FLASH_OPTKEYR + FLASH option key register + 0x10 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + OPTKEY + Option byte key +The following values must be written consecutively to unlock the FLASH_OPTR register allowing option byte programming/erasing operations: +KEY1: 0x0819 2A3B +KEY2: 0x4C5D 6E7F + 0 + 32 + write-only + + + + + FLASH_PDKEY1R + FLASH_PDKEY1R + FLASH bank 1 power-down key register + 0x18 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + PDKEY1 + Bank 1 power-down key +The following values must be written consecutively to unlock the PDREQ1 bit in FLASH_ACR: +PDKEY1_1: 0x0415 2637 +PDKEY1_2: 0xFAFB FCFD + 0 + 32 + write-only + + + + + FLASH_PDKEY2R + FLASH_PDKEY2R + FLASH bank 2 power-down key register + 0x1c + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + PDKEY2 + Bank 2 power-down key +The following values must be written consecutively to unlock the PDREQ2 bit in FLASH_ACR: +PDKEY2_1: 0x4051 6273 +PDKEY2_2: 0xAFBF CFDF + 0 + 32 + write-only + + + + + FLASH_NSSR + FLASH_NSSR + FLASH non-secure status register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFF0FFFF + + + EOP + Non-secure end of operation +This bit is set by hardware when one or more Flash memory non-secure operation (program/erase) has been completed successfully. This bit is set only if the non-secure end of operation interrupts are enabled (EOPIE = 1 in FLASH_NSCR). This bit is cleared by writing 1. + 0 + 1 + read-write + + + OPERR + Non-secure operation error +This bit is set by hardware when a Flash memory non-secure operation (program/erase) completes unsuccessfully. This bit is set only if non-secure error interrupts are enabled (NSERRIE = 1). This bit is cleared by writing 1. + 1 + 1 + read-write + + + PROGERR + Non-secure programming error +This bit is set by hardware when a non-secure quad-word address to be programmed contains a value different from all 1 before programming, except if the data to write is all 0. This bit is cleared by writing 1. + 3 + 1 + read-write + + + WRPERR + Non-secure write protection error +This bit is set by hardware when an non-secure address to be erased/programmed belongs to a write-protected part (by WRP, PCROP, HDP or RDP level 1) of the Flash memory. This bit is cleared by writing 1. +Refer to for full conditions of error flag setting. + 4 + 1 + read-write + + + PGAERR + Non-secure programming alignment error +This bit is set by hardware when the first word to be programmed is not aligned with a quad-word address, or the second, third or forth word does not belong to the same quad-word address. This bit is cleared by writing 1. + 5 + 1 + read-write + + + SIZERR + Non-secure size error +This bit is set by hardware when the size of the access is a byte or half-word during a non-secure program sequence. Only quad-word programming is allowed by means of successive word accesses. This bit is cleared by writing 1. + 6 + 1 + read-write + + + PGSERR + Non-secure programming sequence error +This bit is set by hardware when programming sequence is not correct. It is cleared by writing 1. +Refer to for full conditions of error flag setting. + 7 + 1 + read-write + + + OPTWERR + Option write error +This bit is set by hardware when the options bytes are written with an invalid configuration. It is cleared by writing 1. +Refer to for full conditions of error flag setting. + 13 + 1 + read-write + + + BSY + Non-secure busy +This indicates that a Flash memory secure or non-secure operation is in progress. This bit is set at the beginning of a Flash operation and reset when the operation finishes or when an error occurs. + 16 + 1 + read-only + + + WDW + Non-secure wait data to write +This bit indicates that the Flash memory write buffer has been written by a secure or non-secure operation. It is set when the first data is stored in the buffer and cleared when the write is performed in the Flash memory. + 17 + 1 + read-only + + + OEM1LOCK + OEM1 lock +This bit indicates that the OEM1 RDP key read during the OBL is not virgin. When set, the OEM1 RDP lock mechanism is active. + 18 + 1 + read-only + + + OEM2LOCK + OEM2 lock +This bit indicates that the OEM2 RDP key read during the OBL is not virgin. When set, the OEM2 RDP lock mechanism is active. + 19 + 1 + read-only + + + PD1 + Bank 1 in power-down mode +This bit indicates that the Flash memory bank 1 is in power-down state. It is reset when bank 1 is in normal mode or being awaken. + 20 + 1 + read-only + + + PD2 + Bank 2 in power-down mode +This bit indicates that the Flash memory bank 2 is in power-down state. It is reset when bank 2 is in normal mode or being awaken. + 21 + 1 + read-only + + + + + FLASH_SECSR + FLASH_SECSR + FLASH secure status register + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EOP + Secure end of operation +This bit is set by hardware when one or more Flash memory secure operation (program/erase) has been completed successfully. This bit is set only if the secure end of operation interrupts are enabled (EOPIE = 1 in FLASH_SECCR). This bit is cleared by writing 1. + 0 + 1 + read-write + + + OPERR + Secure operation error +This bit is set by hardware when a Flash memory secure operation (program/erase) completes unsuccessfully. This bit is set only if secure error interrupts are enabled (SECERRIE = 1). This bit is cleared by writing 1. + 1 + 1 + read-write + + + PROGERR + Secure programming error +This bit is set by hardware when a secure quad-word address to be programmed contains a value different from all 1 before programming, except if the data to write is all 0. This bit is cleared by writing 1. + 3 + 1 + read-write + + + WRPERR + Secure write protection error +This bit is set by hardware when an secure address to be erased/programmed belongs to a write-protected part (by WRP, PCROP, HDP or RDP level 1) of the Flash memory.This bit is cleared by writing 1. +Refer to for full conditions of error flag setting. + 4 + 1 + read-write + + + PGAERR + Secure programming alignment error +This bit is set by hardware when the first word to be programmed is not aligned with a quad-word address, or the second, third or forth word does not belong to the same quad-word address.This bit is cleared by writing 1. + 5 + 1 + read-write + + + SIZERR + Secure size error +This bit is set by hardware when the size of the access is a byte or half-word during a secure program sequence. Only quad-word programming is allowed by means of successive word accesses.This bit is cleared by writing 1. + 6 + 1 + read-write + + + PGSERR + Secure programming sequence error +This bit is set by hardware when programming sequence is not correct. It is cleared by writing 1. +Refer to for full conditions of error flag setting. + 7 + 1 + read-write + + + RDERR + Secure readout protection error +This bit is set by hardware when a read access is performed to a secure PCROP area and when a cacheable fetch access is performed to a secure PCROP area. An interrupt is generated if RDERRIE is set in FLASH_SECCR register. This bit is cleared by writing 1. + 14 + 1 + read-write + + + BSY + Secure busy +This bit indicates that a Flash memory secure or non-secure operation is in progress. This is set on the beginning of a Flash operation and reset when the operation finishes or when an error occurs. + 16 + 1 + read-only + + + WDW + Secure wait data to write +This bit indicates that the Flash memory write buffer has been written by a secure or non-secure operation. It is set when the first data is stored in the buffer and cleared when the write is performed in the Flash memory. + 17 + 1 + read-only + + + + + FLASH_NSCR + FLASH_NSCR + FLASH non-secure control register + 0x28 + 0x20 + read-write + 0xC0000000 + 0xFFFFFFFF + + + PG + Non-secure programming + 0 + 1 + read-write + + + B_0x0 + Non-secure Flash programming disabled + 0x0 + + + B_0x1 + Non-secure Flash programming enabled + 0x1 + + + + + PER + Non-secure page erase + 1 + 1 + read-write + + + B_0x0 + Non-secure page erase disabled + 0x0 + + + B_0x1 + Non-secure page erase enabled + 0x1 + + + + + MER1 + Non-secure bank 1 mass erase +This bit triggers the bank 1 non-secure mass erase (all bank 1 user pages) when set. + 2 + 1 + read-write + + + PNB + Non-secure page number selection +These bits select the page to erase. +... +... + 3 + 8 + read-write + + + B_0x0 + page 0 + 0x0 + + + B_0x1 + page 1 + 0x1 + + + B_0x7F + page 127 (upper page for STM32U575/585) + 0x7F + + + B_0xFF + page 255 (upper page for STM32U59x/5Ax) + 0xFF + + + + + BKER + Non-secure bank selection for page erase + 11 + 1 + read-write + + + B_0x0 + Bank 1 selected for non-secure page erase + 0x0 + + + B_0x1 + Bank 2 selected for non-secure page erase + 0x1 + + + + + BWR + Non-secure burst write programming mode +When set, this bit selects the burst write programming mode. + 14 + 1 + read-write + + + MER2 + Non-secure bank 2 mass erase +This bit triggers the bank 2 non-secure mass erase (all bank 2 user pages) when set. + 15 + 1 + read-write + + + STRT + Non-secure start +This bit triggers a non-secure erase operation when set. If MER1, MER2 and PER bits are reset and the STRT bit is set, the PGSERR bit in FLASH_NSSR is set (this condition is forbidden). +This bit is set only by software and is cleared when the BSY bit is cleared in FLASH_NSSR. + 16 + 1 + read-write + + + OPTSTRT + Options modification start +This bit triggers an options operation when set. It can not be written if OPTLOCK bit is set. This bit is set only by software, and is cleared when the BSY bit is cleared in FLASH_NSSR. + 17 + 1 + read-write + + + EOPIE + Non-secure end of operation interrupt enable +This bit enables the interrupt generation when the EOP bit in the FLASH_NSSR is set to 1. + 24 + 1 + read-write + + + B_0x0 + Non-secure EOP Interrupt disabled + 0x0 + + + B_0x1 + Non-secure EOP Interrupt enabled + 0x1 + + + + + ERRIE + Non-secure error interrupt enable +This bit enables the interrupt generation when the OPERR bit in the FLASH_NSSR is set to 1. + 25 + 1 + read-write + + + B_0x0 + Non-secure OPERR error interrupt disabled + 0x0 + + + B_0x1 + Non-secure OPERR error interrupt enabled + 0x1 + + + + + OBL_LAUNCH + Force the option byte loading +When set to 1, this bit forces the option byte reloading. This bit is cleared only when the option byte loading is complete. It cannot be written if OPTLOCK is set. + 27 + 1 + read-write + + + B_0x0 + Option byte loading complete + 0x0 + + + B_0x1 + Option byte loading requested + 0x1 + + + + + OPTLOCK + Option lock +This bit is set only. When set, all bits concerning user options in FLASH_NSCR register are locked. This bit is cleared by hardware after detecting the unlock sequence. The LOCK bit in the FLASH_NSCR must be cleared before doing the unlock sequence for OPTLOCK bit. +In case of an unsuccessful unlock operation, this bit remains set until the next reset. + 30 + 1 + read-write + + + LOCK + Non-secure lock +This bit is set only. When set, the FLASH_NSCR register is locked. It is cleared by hardware after detecting the unlock sequence in FLASH_NSKEYR register. +In case of an unsuccessful unlock operation, this bit remains set until the next system reset. + 31 + 1 + read-write + + + + + FLASH_SECCR + FLASH_SECCR + FLASH secure control register + 0x2c + 0x20 + read-write + 0x80000000 + 0xFFFFFFFF + + + PG + Secure programming + 0 + 1 + read-write + + + B_0x0 + Secure Flash programming disabled + 0x0 + + + B_0x1 + Secure Flash programming enabled + 0x1 + + + + + PER + Secure page erase + 1 + 1 + read-write + + + B_0x0 + Secure page erase disabled + 0x0 + + + B_0x1 + Secure page erase enabled + 0x1 + + + + + MER1 + Secure bank 1 mass erase +This bit triggers the bank 1 secure mass erase (all bank 1 user pages) when set. + 2 + 1 + read-write + + + PNB + Secure page number selection +These bits select the page to erase. +... +... + 3 + 8 + read-write + + + B_0x0 + page 0 + 0x0 + + + B_0x1 + page 1 + 0x1 + + + B_0x7F + page 127 (upper page for STM32U575/585) + 0x7F + + + B_0xFF + page 255 (upper page for STM32U59x/5Ax) + 0xFF + + + + + BKER + Secure bank selection for page erase + 11 + 1 + read-write + + + B_0x0 + Bank 1 selected for secure page erase + 0x0 + + + B_0x1 + Bank 2 selected for secure page erase + 0x1 + + + + + BWR + Secure burst write programming mode +When set, this bit selects the burst write programming mode. + 14 + 1 + read-write + + + MER2 + Secure bank 2 mass erase +This bit triggers the bank 2 secure mass erase (all bank 2 user pages) when set. + 15 + 1 + read-write + + + STRT + Secure start +This bit triggers a secure erase operation when set. If MER1, MER2 and PER bits are reset and the STRT bit is set, the PGSERR in the FLASH_SECSR is set (this condition is forbidden). +This bit is set only by software and is cleared when the BSY bit is cleared in FLASH_SECSR. + 16 + 1 + read-write + + + EOPIE + Secure End of operation interrupt enable +This bit enables the interrupt generation when the EOP bit in the FLASH_SECSR is set to 1. + 24 + 1 + read-write + + + B_0x0 + Secure EOP Interrupt disabled + 0x0 + + + B_0x1 + Secure EOP Interrupt enabled + 0x1 + + + + + ERRIE + Secure error interrupt enable +This bit enables the interrupt generation when the OPERR bit in the FLASH_SECSR is set to 1. + 25 + 1 + read-write + + + B_0x0 + Secure OPERR error interrupt disabled + 0x0 + + + B_0x1 + Secure OPERR error interrupt enabled + 0x1 + + + + + RDERRIE + Secure PCROP read error interrupt enable +This bit enables the interrupt generation when the RDERR bit in the FLASH_SECSR is set to 1. + 26 + 1 + read-write + + + B_0x0 + Secure PCROP read error interrupt disabled + 0x0 + + + B_0x1 + Secure PCROP read error interrupt enabled + 0x1 + + + + + INV + Flash memory security state invert +This bit inverts the Flash memory security state. + 29 + 1 + read-write + + + LOCK + Secure lock +This bit is set only. When set, the FLASH_SECCR register is locked. It is cleared by hardware after detecting the unlock sequence in FLASH_SECKEYR register. +In case of an unsuccessful unlock operation, this bit remains set until the next system reset. + 31 + 1 + read-write + + + + + FLASH_ECCR + FLASH_ECCR + FLASH ECC register + 0x30 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ADDR_ECC + ECC fail address +This field indicates which address is concerned by the ECC error correction or by the double ECC error detection. The address is given by bank from address 0x0 0000 to 0x1F FFF0. + 0 + 21 + read-only + + + BK_ECC + ECC fail bank +This bit indicates which bank is concerned by the ECC error correction or by the double ECC error detection. + 21 + 1 + read-only + + + B_0x0 + Bank 1 + 0x0 + + + B_0x1 + Bank 2 + 0x1 + + + + + SYSF_ECC + System Flash memory ECC fail +This bit indicates that the ECC error correction or double ECC error detection is located in the system Flash memory. + 22 + 1 + read-only + + + ECCIE + ECC correction interrupt enable +This bit enables the interrupt generation when the ECCC bit in the FLASH_ECCR register is set. + 24 + 1 + read-write + + + B_0x0 + ECCC interrupt disabled + 0x0 + + + B_0x1 + ECCC interrupt enabled. + 0x1 + + + + + ECCC + ECC correction +This bit is set by hardware when one ECC error has been detected and corrected (only if ECCC and ECCD were previously cleared). An interrupt is generated if ECCIE is set. This bit is cleared by writing 1. + 30 + 1 + read-write + + + ECCD + ECC detection +This bit is set by hardware when two ECC errors have been detected (only if ECCC and ECCD were previously cleared). When this bit is set, a NMI is generated. This bit is cleared by writing 1. + 31 + 1 + read-write + + + + + FLASH_OPSR + FLASH_OPSR + FLASH operation status register + 0x34 + 0x20 + read-only + 0x00000000 + 0x0F000000 + + + ADDR_OP + Interrupted operation address +This field indicates which address in the Flash memory was accessed when reset occurred. The address is given by bank from address 0x0 0000 to 0x1F FFF0. + 0 + 21 + read-only + + + BK_OP + Interrupted operation bank +This bit indicates which Flash memory bank was accessed when reset occurred + 21 + 1 + read-only + + + B_0x0 + Bank 1 + 0x0 + + + B_0x1 + Bank 2 + 0x1 + + + + + SYSF_OP + Operation in system Flash memory interrupted +This bit indicates that the reset occurred during an operation in the system Flash memory. + 22 + 1 + read-only + + + CODE_OP + Flash memory operation code +This field indicates which Flash memory operation has been interrupted by a system reset: + 29 + 3 + read-only + + + B_0x0 + No Flash operation interrupted by previous reset + 0x0 + + + B_0x1 + Single write operation interrupted + 0x1 + + + B_0x2 + Burst write operation interrupted + 0x2 + + + B_0x3 + Page erase operation interrupted + 0x3 + + + B_0x4 + Bank erase operation interrupted + 0x4 + + + B_0x5 + Mass erase operation interrupted + 0x5 + + + B_0x6 + Option change operation interrupted + 0x6 + + + + + + + FLASH_OPTR + FLASH_OPTR + FLASH option register + 0x40 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + RDP + Readout protection level +Others: Level 1 (memories readout protection active) +Note: Refer to for more details. + 0 + 8 + read-write + + + B_0xAA + Level 0 (readout protection not active) + 0xAA + + + B_0x55 + Level 0.5 (readout protection not active, only non-secure debug access is possible). Only available when TrustZone is active (TZEN=1) + 0x55 + + + B_0xCC + Level 2 (chip readout protection active) + 0xCC + + + + + BOR_LEV + BOR reset level +These bits contain the VDD supply level threshold that activates/releases the reset. + 8 + 3 + read-write + + + B_0x0 + BOR level 0 (reset level threshold around 1.7 V) + 0x0 + + + B_0x1 + BOR level 1 (reset level threshold around 2.0 V) + 0x1 + + + B_0x2 + BOR level 2 (reset level threshold around 2.2 V) + 0x2 + + + B_0x3 + BOR level 3 (reset level threshold around 2.5 V) + 0x3 + + + B_0x4 + BOR level 4 (reset level threshold around 2.8 V) + 0x4 + + + + + nRST_STOP + Reset generation in Stop mode + 12 + 1 + read-write + + + B_0x0 + Reset generated when entering the Stop mode + 0x0 + + + B_0x1 + No reset generated when entering the Stop mode + 0x1 + + + + + nRST_STDBY + Reset generation in Standby mode + 13 + 1 + read-write + + + B_0x0 + Reset generated when entering the Standby mode + 0x0 + + + B_0x1 + No reset generate when entering the Standby mode + 0x1 + + + + + nRST_SHDW + Reset generation in Shutdown mode + 14 + 1 + read-write + + + B_0x0 + Reset generated when entering the Shutdown mode + 0x0 + + + B_0x1 + No reset generated when entering the Shutdown mode + 0x1 + + + + + SRAM1345_RST + SRAM1, SRAM3, SRAM4 and SRAM5 erase upon system reset + 15 + 1 + read-write + + + B_0x0 + SRAM1, SRAM3, SRAM4 and SRAM5 erased when a system reset occurs + 0x0 + + + B_0x1 + SRAM1, SRAM3, SRAM4 and SRAM5 not erased when a system reset occurs + 0x1 + + + + + IWDG_SW + Independent watchdog selection + 16 + 1 + read-write + + + B_0x0 + Hardware independent watchdog selected + 0x0 + + + B_0x1 + Software independent watchdog selected + 0x1 + + + + + IWDG_STOP + Independent watchdog counter freeze in Stop mode + 17 + 1 + read-write + + + B_0x0 + Independent watchdog counter frozen in Stop mode + 0x0 + + + B_0x1 + Independent watchdog counter running in Stop mode + 0x1 + + + + + IWDG_STDBY + Independent watchdog counter freeze in Standby mode + 18 + 1 + read-write + + + B_0x0 + Independent watchdog counter frozen in Standby mode + 0x0 + + + B_0x1 + Independent watchdog counter running in Standby mode + 0x1 + + + + + WWDG_SW + Window watchdog selection + 19 + 1 + read-write + + + B_0x0 + Hardware window watchdog selected + 0x0 + + + B_0x1 + Software window watchdog selected + 0x1 + + + + + SWAP_BANK + Swap banks + 20 + 1 + read-write + + + B_0x0 + Bank 1 and bank 2 addresses not swapped + 0x0 + + + B_0x1 + Bank 1 and bank 2 addresses swapped + 0x1 + + + + + DUALBANK + Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices + 21 + 1 + read-write + + + B_0x0 + Single bank Flash with contiguous address in bank 1 + 0x0 + + + B_0x1 + Dual-bank Flash with contiguous addresses + 0x1 + + + + + BKPRAM_ECC + Backup RAM ECC detection and correction enable + 22 + 1 + read-write + + + B_0x0 + Backup RAM ECC check enabled + 0x0 + + + B_0x1 + Backup RAM ECC check disabled + 0x1 + + + + + SRAM3_ECC + SRAM3 ECC detection and correction enable + 23 + 1 + read-write + + + B_0x0 + SRAM3 ECC check enabled + 0x0 + + + B_0x1 + SRAM3 ECC check disabled + 0x1 + + + + + SRAM2_ECC + SRAM2 ECC detection and correction enable + 24 + 1 + read-write + + + B_0x0 + SRAM2 ECC check enabled + 0x0 + + + B_0x1 + SRAM2 ECC check disabled + 0x1 + + + + + SRAM2_RST + SRAM2 erase when system reset + 25 + 1 + read-write + + + B_0x0 + SRAM2 erased when a system reset occurs + 0x0 + + + B_0x1 + SRAM2 not erased when a system reset occurs + 0x1 + + + + + nSWBOOT0 + Software BOOT0 + 26 + 1 + read-write + + + B_0x0 + BOOT0 taken from the option bit nBOOT0 + 0x0 + + + B_0x1 + BOOT0 taken from PH3/BOOT0 pin + 0x1 + + + + + nBOOT0 + nBOOT0 option bit + 27 + 1 + read-write + + + B_0x0 + nBOOT0 = 0 + 0x0 + + + B_0x1 + nBOOT0 = 1 + 0x1 + + + + + PA15_PUPEN + PA15 pull-up enable + 28 + 1 + read-write + + + B_0x0 + USB power delivery dead-battery enabled/TDI pull-up deactivated + 0x0 + + + B_0x1 + USB power delivery dead-battery disabled/TDI pull-up activated + 0x1 + + + + + IO_VDD_HSLV + High-speed IO at low VDD voltage configuration bit +This bit can be set only with VDD below 2.5V + 29 + 1 + read-write + + + B_0x0 + High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V) + 0x0 + + + B_0x1 + High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V) + 0x1 + + + + + IO_VDDIO2_HSLV + High-speed IO at low VDDIO2 voltage configuration bit +This bit can be set only with VDDIO2 below 2.5 V. + 30 + 1 + read-write + + + B_0x0 + High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V) + 0x0 + + + B_0x1 + High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) + 0x1 + + + + + TZEN + Global TrustZone security enable + 31 + 1 + read-write + + + B_0x0 + Global TrustZone security disabled + 0x0 + + + B_0x1 + Global TrustZone security enabled + 0x1 + + + + + + + FLASH_NSBOOTADD0R + FLASH_NSBOOTADD0R + FLASH non-secure boot address 0 register + 0x44 + 0x20 + read-write + 0x0000000F + 0x0000000F + + + NSBOOTADD0 + Non-secure boot base address 0 +The non-secure boot memory address can be programmed to any address in the valid address range with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or nSWBOOT0 state. +Examples: +NSBOOTADD0[24:0] = 0x0100000: Boot from non-secure Flash memory (0x0800 0000) +NSBOOTADD0[24:0] = 0x017F200: Boot from system memory bootloader (0x0BF9 0000) +NSBOOTADD0[24:0] = 0x0400000: Boot from non-secure SRAM1 on S-Bus (0x2000 0000) + 7 + 25 + read-write + + + + + FLASH_NSBOOTADD1R + FLASH_NSBOOTADD1R + FLASH non-secure boot address 1 register + 0x48 + 0x20 + read-write + 0x0000000F + 0x0000000F + + + NSBOOTADD1 + Non-secure boot address 1 +The non-secure boot memory address can be programmed to any address in the valid address range with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or nSWBOOT0 state. +Examples: +NSBOOTADD1[24:0] = 0x0100000: Boot from non-secure Flash memory (0x0800 0000) +NSBOOTADD1[24:0] = 0x017F200: Boot from system memory bootloader (0x0BF9 0000) +NSBOOTADD1[24:0] = 0x0400000: Boot from non-secure SRAM1 on S-Bus (0x2000 0000) + 7 + 25 + read-write + + + + + FLASH_SECBOOTADD0R + FLASH_SECBOOTADD0R + FLASH secure boot address 0 register + 0x4c + 0x20 + read-write + 0x00000000 + 0x00000000 + + + BOOT_LOCK + Boot lock +When set, the boot is always forced to base address value programmed in SECBOOTADD0[24:0] option bytes whatever the boot selection option. When set, this bit can only be cleared by an RDP at level 0. + 0 + 1 + read-write + + + SECBOOTADD0 + Secure boot base address 0 +The secure boot memory address can be programmed to any address in the valid address range with a granularity of 128 bytes. This bits correspond to address [31:7] The SECBOOTADD0 option bytes are selected following the BOOT0 pin or nSWBOOT0 state. +Examples: +SECBOOTADD0[24:0] = 0x018 0000: Boot from secure Flash memory (0x0C00 0000) +SECBOOTADD0[24:0] = 0x01F F000: Boot from RSS (0x0FF8 0000) +SECBOOTADD0[24:0] = 0x060 0000: Boot from secure SRAM1 on S-Bus (0x3000 0000) + 7 + 25 + read-write + + + + + FLASH_SECWM1R1 + FLASH_SECWM1R1 + FLASH secure watermark1 register 1 + 0x50 + 0x20 + read-write + 0xFF00FF00 + 0xFF00FF00 + + + SECWM1_PSTRT + Start page of first secure area +This field contains the first page of the secure area in bank 1. + 0 + 8 + read-write + + + SECWM1_PEND + End page of first secure area +This field contains the last page of the secure area in bank 1. + 16 + 8 + read-write + + + + + FLASH_SECWM1R2 + FLASH_SECWM1R2 + FLASH secure watermark1 register 2 + 0x54 + 0x20 + read-write + 0x0F000F00 + 0x0F000F00 + + + PCROP1_PSTRT + Start page of first PCROP area +This field contains the first page of the PCROP area in bank 1. + 0 + 8 + read-write + + + PCROP1EN + PCROP1 area enable + 15 + 1 + read-write + + + B_0x0 + PCROP1 area disabled + 0x0 + + + B_0x1 + PCROP1 area enabled + 0x1 + + + + + HDP1_PEND + End page of first hide protection area +This field contains the last page of the HDP area in bank 1. + 16 + 8 + read-write + + + HDP1EN + Hide protection first area enable + 31 + 1 + read-write + + + B_0x0 + No HDP area 1 + 0x0 + + + B_0x1 + HDP first area enabled + 0x1 + + + + + + + FLASH_WRP1AR + FLASH_WRP1AR + FLASH WRP1 area A address register + 0x58 + 0x20 + read-write + 0x0F00FF00 + 0x0F00FF00 + + + WRP1A_PSTRT + bank 1 WPR first area A start page +This field contains the first page of the first WPR area for bank 1. + 0 + 8 + read-write + + + WRP1A_PEND + Bank 1 WPR first area A end page +This field contains the last page of the first WPR area in bank 1. + 16 + 8 + read-write + + + UNLOCK + Bank 1 WPR first area A unlock + 31 + 1 + read-write + + + B_0x0 + WRP1A start and end pages locked + 0x0 + + + B_0x1 + WRP1A start and end pages unlocked + 0x1 + + + + + + + FLASH_WRP1BR + FLASH_WRP1BR + FLASH WRP1 area B address register + 0x5c + 0x20 + read-write + 0x0F00FF00 + 0x0F00FF00 + + + WRP1B_PSTRT + Bank 1 WRP second area B start page +This field contains the first page of the second WRP area for bank 1. + 0 + 8 + read-write + + + WRP1B_PEND + Bank 1 WRP second area B end page +This field contains the last page of the second WRP area in bank 1. + 16 + 8 + read-write + + + UNLOCK + Bank 1 WPR second area B unlock + 31 + 1 + read-write + + + B_0x0 + WRP1B start and end pages locked + 0x0 + + + B_0x1 + WRP1B start and end pages unlocked + 0x1 + + + + + + + FLASH_SECWM2R1 + FLASH_SECWM2R1 + FLASH secure watermark2 register 1 + 0x60 + 0x20 + read-write + 0xFF00FF00 + 0xFF00FF00 + + + SECWM2_PSTRT + Start page of second secure area +This field contains the first page of the secure area in bank 2. + 0 + 8 + read-write + + + SECWM2_PEND + End page of second secure area +This field contains the last page of the secure area in bank 2. + 16 + 8 + read-write + + + + + FLASH_SECWM2R2 + FLASH_SECWM2R2 + FLASH secure watermark2 register 2 + 0x64 + 0x20 + read-write + 0x0F000F00 + 0x0F000F00 + + + PCROP2_PSTRT + Start page of PCROP2 area +PRCROP2_PSTRT contains the first page of the PCROP area in bank 2. + 0 + 8 + read-write + + + PCROP2EN + PCROP2 area enable + 15 + 1 + read-write + + + B_0x0 + PCROP2 area is disabled + 0x0 + + + B_0x1 + PCROP2 area is enabled + 0x1 + + + + + HDP2_PEND + End page of hide protection second area +HDP2_PEND contains the last page of the HDP area in bank 2. + 16 + 8 + read-write + + + HDP2EN + Hide protection second area enable + 31 + 1 + read-write + + + B_0x0 + No HDP area 2 + 0x0 + + + B_0x1 + HDP second area is enabled. + 0x1 + + + + + + + FLASH_WRP2AR + FLASH_WRP2AR + FLASH WPR2 area A address register + 0x68 + 0x20 + read-write + 0x0F00FF00 + 0x0F00FF00 + + + WRP2A_PSTRT + Bank 2 WPR first area A start page +This field contains the first page of the first WRP area for bank 2. + 0 + 8 + read-write + + + WRP2A_PEND + Bank 2 WPR first area A end page +This field contains the last page of the first WRP area in bank 2. + 16 + 8 + read-write + + + UNLOCK + Bank 2 WPR first area A unlock + 31 + 1 + read-write + + + B_0x0 + WRP2A start and end pages locked + 0x0 + + + B_0x1 + WRP2A start and end pages unlocked + 0x1 + + + + + + + FLASH_WRP2BR + FLASH_WRP2BR + FLASH WPR2 area B address register + 0x6c + 0x20 + read-write + 0x0F00FF00 + 0x0F00FF00 + + + WRP2B_PSTRT + Bank 2 WPR second area B start page +This field contains the first page of the second WRP area for bank 2. + 0 + 8 + read-write + + + WRP2B_PEND + Bank 2 WPR second area B end page +This field contains the last page of the second WRP area in bank 2. + 16 + 8 + read-write + + + UNLOCK + Bank 2 WPR second area B unlock + 31 + 1 + read-write + + + B_0x0 + WRP2B start and end pages locked + 0x0 + + + B_0x1 + WRP2B start and end pages unlocked + 0x1 + + + + + + + FLASH_OEM1KEYR1 + FLASH_OEM1KEYR1 + FLASH OEM1 key register 1 + 0x70 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + OEM1KEY + OEM1 least significant bytes key + 0 + 32 + write-only + + + + + FLASH_OEM1KEYR2 + FLASH_OEM1KEYR2 + FLASH OEM1 key register 2 + 0x74 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + OEM1KEY + OEM1 most significant bytes key + 0 + 32 + write-only + + + + + FLASH_OEM2KEYR1 + FLASH_OEM2KEYR1 + FLASH OEM2 key register 1 + 0x78 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + OEM2KEY + OEM2 least significant bytes key + 0 + 32 + write-only + + + + + FLASH_OEM2KEYR2 + FLASH_OEM2KEYR2 + FLASH OEM2 key register 2 + 0x7c + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + OEM2KEY + OEM2 most significant bytes key + 0 + 32 + write-only + + + + + FLASH_SEC1BBR1 + FLASH_SEC1BBR1 + FLASH secure block based bank 1 register 1 + 0x80 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SEC1BB0 + 0 + 1 + read-write + + + SEC1BB1 + 1 + 1 + read-write + + + SEC1BB2 + 2 + 1 + read-write + + + SEC1BB3 + 3 + 1 + read-write + + + SEC1BB4 + 4 + 1 + read-write + + + SEC1BB5 + 5 + 1 + read-write + + + SEC1BB6 + 6 + 1 + read-write + + + SEC1BB7 + 7 + 1 + read-write + + + SEC1BB8 + 8 + 1 + read-write + + + SEC1BB9 + 9 + 1 + read-write + + + SEC1BB10 + 10 + 1 + read-write + + + SEC1BB11 + 11 + 1 + read-write + + + SEC1BB12 + 12 + 1 + read-write + + + SEC1BB13 + 13 + 1 + read-write + + + SEC1BB14 + 14 + 1 + read-write + + + SEC1BB15 + 15 + 1 + read-write + + + SEC1BB16 + 16 + 1 + read-write + + + SEC1BB17 + 17 + 1 + read-write + + + SEC1BB18 + 18 + 1 + read-write + + + SEC1BB19 + 19 + 1 + read-write + + + SEC1BB20 + 20 + 1 + read-write + + + SEC1BB21 + 21 + 1 + read-write + + + SEC1BB22 + 22 + 1 + read-write + + + SEC1BB23 + 23 + 1 + read-write + + + SEC1BB24 + 24 + 1 + read-write + + + SEC1BB25 + 25 + 1 + read-write + + + SEC1BB26 + 26 + 1 + read-write + + + SEC1BB27 + 27 + 1 + read-write + + + SEC1BB28 + 28 + 1 + read-write + + + SEC1BB29 + 29 + 1 + read-write + + + SEC1BB30 + 30 + 1 + read-write + + + SEC1BB31 + 31 + 1 + read-write + + + + + FLASH_SEC1BBR2 + FLASH_SEC1BBR2 + FLASH secure block based bank 1 register 2 + 0x84 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SEC1BB0 + 0 + 1 + read-write + + + SEC1BB1 + 1 + 1 + read-write + + + SEC1BB2 + 2 + 1 + read-write + + + SEC1BB3 + 3 + 1 + read-write + + + SEC1BB4 + 4 + 1 + read-write + + + SEC1BB5 + 5 + 1 + read-write + + + SEC1BB6 + 6 + 1 + read-write + + + SEC1BB7 + 7 + 1 + read-write + + + SEC1BB8 + 8 + 1 + read-write + + + SEC1BB9 + 9 + 1 + read-write + + + SEC1BB10 + 10 + 1 + read-write + + + SEC1BB11 + 11 + 1 + read-write + + + SEC1BB12 + 12 + 1 + read-write + + + SEC1BB13 + 13 + 1 + read-write + + + SEC1BB14 + 14 + 1 + read-write + + + SEC1BB15 + 15 + 1 + read-write + + + SEC1BB16 + 16 + 1 + read-write + + + SEC1BB17 + 17 + 1 + read-write + + + SEC1BB18 + 18 + 1 + read-write + + + SEC1BB19 + 19 + 1 + read-write + + + SEC1BB20 + 20 + 1 + read-write + + + SEC1BB21 + 21 + 1 + read-write + + + SEC1BB22 + 22 + 1 + read-write + + + SEC1BB23 + 23 + 1 + read-write + + + SEC1BB24 + 24 + 1 + read-write + + + SEC1BB25 + 25 + 1 + read-write + + + SEC1BB26 + 26 + 1 + read-write + + + SEC1BB27 + 27 + 1 + read-write + + + SEC1BB28 + 28 + 1 + read-write + + + SEC1BB29 + 29 + 1 + read-write + + + SEC1BB30 + 30 + 1 + read-write + + + SEC1BB31 + 31 + 1 + read-write + + + + + FLASH_SEC1BBR3 + FLASH_SEC1BBR3 + FLASH secure block based bank 1 register 3 + 0x88 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SEC1BB0 + 0 + 1 + read-write + + + SEC1BB1 + 1 + 1 + read-write + + + SEC1BB2 + 2 + 1 + read-write + + + SEC1BB3 + 3 + 1 + read-write + + + SEC1BB4 + 4 + 1 + read-write + + + SEC1BB5 + 5 + 1 + read-write + + + SEC1BB6 + 6 + 1 + read-write + + + SEC1BB7 + 7 + 1 + read-write + + + SEC1BB8 + 8 + 1 + read-write + + + SEC1BB9 + 9 + 1 + read-write + + + SEC1BB10 + 10 + 1 + read-write + + + SEC1BB11 + 11 + 1 + read-write + + + SEC1BB12 + 12 + 1 + read-write + + + SEC1BB13 + 13 + 1 + read-write + + + SEC1BB14 + 14 + 1 + read-write + + + SEC1BB15 + 15 + 1 + read-write + + + SEC1BB16 + 16 + 1 + read-write + + + SEC1BB17 + 17 + 1 + read-write + + + SEC1BB18 + 18 + 1 + read-write + + + SEC1BB19 + 19 + 1 + read-write + + + SEC1BB20 + 20 + 1 + read-write + + + SEC1BB21 + 21 + 1 + read-write + + + SEC1BB22 + 22 + 1 + read-write + + + SEC1BB23 + 23 + 1 + read-write + + + SEC1BB24 + 24 + 1 + read-write + + + SEC1BB25 + 25 + 1 + read-write + + + SEC1BB26 + 26 + 1 + read-write + + + SEC1BB27 + 27 + 1 + read-write + + + SEC1BB28 + 28 + 1 + read-write + + + SEC1BB29 + 29 + 1 + read-write + + + SEC1BB30 + 30 + 1 + read-write + + + SEC1BB31 + 31 + 1 + read-write + + + + + FLASH_SEC1BBR4 + FLASH_SEC1BBR4 + FLASH secure block based bank 1 register 4 + 0x8c + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SEC1BB0 + 0 + 1 + read-write + + + SEC1BB1 + 1 + 1 + read-write + + + SEC1BB2 + 2 + 1 + read-write + + + SEC1BB3 + 3 + 1 + read-write + + + SEC1BB4 + 4 + 1 + read-write + + + SEC1BB5 + 5 + 1 + read-write + + + SEC1BB6 + 6 + 1 + read-write + + + SEC1BB7 + 7 + 1 + read-write + + + SEC1BB8 + 8 + 1 + read-write + + + SEC1BB9 + 9 + 1 + read-write + + + SEC1BB10 + 10 + 1 + read-write + + + SEC1BB11 + 11 + 1 + read-write + + + SEC1BB12 + 12 + 1 + read-write + + + SEC1BB13 + 13 + 1 + read-write + + + SEC1BB14 + 14 + 1 + read-write + + + SEC1BB15 + 15 + 1 + read-write + + + SEC1BB16 + 16 + 1 + read-write + + + SEC1BB17 + 17 + 1 + read-write + + + SEC1BB18 + 18 + 1 + read-write + + + SEC1BB19 + 19 + 1 + read-write + + + SEC1BB20 + 20 + 1 + read-write + + + SEC1BB21 + 21 + 1 + read-write + + + SEC1BB22 + 22 + 1 + read-write + + + SEC1BB23 + 23 + 1 + read-write + + + SEC1BB24 + 24 + 1 + read-write + + + SEC1BB25 + 25 + 1 + read-write + + + SEC1BB26 + 26 + 1 + read-write + + + SEC1BB27 + 27 + 1 + read-write + + + SEC1BB28 + 28 + 1 + read-write + + + SEC1BB29 + 29 + 1 + read-write + + + SEC1BB30 + 30 + 1 + read-write + + + SEC1BB31 + 31 + 1 + read-write + + + + + FLASH_SEC1BBR5 + FLASH_SEC1BBR5 + FLASH secure block based bank 1 register 5 + 0x90 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SEC1BB0 + 0 + 1 + read-write + + + SEC1BB1 + 1 + 1 + read-write + + + SEC1BB2 + 2 + 1 + read-write + + + SEC1BB3 + 3 + 1 + read-write + + + SEC1BB4 + 4 + 1 + read-write + + + SEC1BB5 + 5 + 1 + read-write + + + SEC1BB6 + 6 + 1 + read-write + + + SEC1BB7 + 7 + 1 + read-write + + + SEC1BB8 + 8 + 1 + read-write + + + SEC1BB9 + 9 + 1 + read-write + + + SEC1BB10 + 10 + 1 + read-write + + + SEC1BB11 + 11 + 1 + read-write + + + SEC1BB12 + 12 + 1 + read-write + + + SEC1BB13 + 13 + 1 + read-write + + + SEC1BB14 + 14 + 1 + read-write + + + SEC1BB15 + 15 + 1 + read-write + + + SEC1BB16 + 16 + 1 + read-write + + + SEC1BB17 + 17 + 1 + read-write + + + SEC1BB18 + 18 + 1 + read-write + + + SEC1BB19 + 19 + 1 + read-write + + + SEC1BB20 + 20 + 1 + read-write + + + SEC1BB21 + 21 + 1 + read-write + + + SEC1BB22 + 22 + 1 + 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HDP1 area granted + 0x0 + + + B_0x1 + Access to HDP1 area denied (SECWM1Ry option bytes modification blocked - refer to ) + 0x1 + + + + + HDP2_ACCDIS + HDP2 area access disable +When set, this bit is only cleared by a system reset. + 1 + 1 + read-write + + + B_0x0 + Access to HDP2 area granted + 0x0 + + + B_0x1 + Access to HDP2 area denied (SECWM2Ry option bytes modification bocked -refer to ) + 0x1 + + + + + + + FLASH_PRIVCFGR + FLASH_PRIVCFGR + FLASH privilege configuration register + 0xc4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SPRIV + Privileged protection for secure registers + 0 + 1 + read-write + + + NSPRIV + Privileged protection for non-secure registers + 1 + 1 + read-write + + + + + FLASH_PRIV1BBR1 + FLASH_PRIV1BBR1 + FLASH privilege block based bank 1 register 1 + 0xd0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRIV1BB0 + 0 + 1 + read-write + + + PRIV1BB1 + 1 + 1 + read-write + + + PRIV1BB2 + 2 + 1 + read-write + + + PRIV1BB3 + 3 + 1 + read-write + + + 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read-write + + + PRIV2BB28 + 28 + 1 + read-write + + + PRIV2BB29 + 29 + 1 + read-write + + + PRIV2BB30 + 30 + 1 + read-write + + + PRIV2BB31 + 31 + 1 + read-write + + + + + FLASH_PRIV2BBR6 + FLASH_PRIV2BBR6 + FLASH privilege block based bank 2 register 6 + 0x104 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRIV2BB0 + 0 + 1 + read-write + + + PRIV2BB1 + 1 + 1 + read-write + + + PRIV2BB2 + 2 + 1 + read-write + + + PRIV2BB3 + 3 + 1 + read-write + + + PRIV2BB4 + 4 + 1 + read-write + + + PRIV2BB5 + 5 + 1 + read-write + + + PRIV2BB6 + 6 + 1 + read-write + + + PRIV2BB7 + 7 + 1 + read-write + + + PRIV2BB8 + 8 + 1 + read-write + + + PRIV2BB9 + 9 + 1 + read-write + + + PRIV2BB10 + 10 + 1 + read-write + + + PRIV2BB11 + 11 + 1 + read-write + + + PRIV2BB12 + 12 + 1 + read-write + + + PRIV2BB13 + 13 + 1 + read-write + + + PRIV2BB14 + 14 + 1 + read-write + + + PRIV2BB15 + 15 + 1 + read-write + + + PRIV2BB16 + 16 + 1 + read-write + + + PRIV2BB17 + 17 + 1 + read-write + + + PRIV2BB18 + 18 + 1 + read-write + + + PRIV2BB19 + 19 + 1 + read-write + + + PRIV2BB20 + 20 + 1 + read-write + + + PRIV2BB21 + 21 + 1 + read-write + + + PRIV2BB22 + 22 + 1 + read-write + + + PRIV2BB23 + 23 + 1 + read-write + + + PRIV2BB24 + 24 + 1 + read-write + + + PRIV2BB25 + 25 + 1 + read-write + + + PRIV2BB26 + 26 + 1 + read-write + + + PRIV2BB27 + 27 + 1 + read-write + + + PRIV2BB28 + 28 + 1 + read-write + + + PRIV2BB29 + 29 + 1 + read-write + + + PRIV2BB30 + 30 + 1 + read-write + + + PRIV2BB31 + 31 + 1 + read-write + + + + + FLASH_PRIV2BBR7 + FLASH_PRIV2BBR7 + FLASH privilege block based bank 2 register 7 + 0x108 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRIV2BB0 + 0 + 1 + read-write + + + PRIV2BB1 + 1 + 1 + read-write + + + PRIV2BB2 + 2 + 1 + read-write + + + PRIV2BB3 + 3 + 1 + read-write + + + PRIV2BB4 + 4 + 1 + read-write + + + PRIV2BB5 + 5 + 1 + read-write + + + PRIV2BB6 + 6 + 1 + read-write + + + PRIV2BB7 + 7 + 1 + read-write + + + PRIV2BB8 + 8 + 1 + read-write + + + PRIV2BB9 + 9 + 1 + read-write + + + PRIV2BB10 + 10 + 1 + read-write + + + PRIV2BB11 + 11 + 1 + read-write + + + PRIV2BB12 + 12 + 1 + read-write + + + PRIV2BB13 + 13 + 1 + read-write + + + PRIV2BB14 + 14 + 1 + read-write + + + PRIV2BB15 + 15 + 1 + read-write + + + PRIV2BB16 + 16 + 1 + read-write + + + PRIV2BB17 + 17 + 1 + read-write + + + PRIV2BB18 + 18 + 1 + read-write + + + PRIV2BB19 + 19 + 1 + read-write + + + PRIV2BB20 + 20 + 1 + read-write + + + PRIV2BB21 + 21 + 1 + read-write + + + PRIV2BB22 + 22 + 1 + read-write + + + PRIV2BB23 + 23 + 1 + read-write + + + PRIV2BB24 + 24 + 1 + read-write + + + PRIV2BB25 + 25 + 1 + read-write + + + PRIV2BB26 + 26 + 1 + read-write + + + PRIV2BB27 + 27 + 1 + read-write + + + PRIV2BB28 + 28 + 1 + read-write + + + PRIV2BB29 + 29 + 1 + read-write + + + PRIV2BB30 + 30 + 1 + read-write + + + PRIV2BB31 + 31 + 1 + read-write + + + + + FLASH_PRIV2BBR8 + FLASH_PRIV2BBR8 + FLASH privilege block based bank 2 register 8 + 0x10c + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRIV2BB0 + 0 + 1 + read-write + + + PRIV2BB1 + 1 + 1 + read-write + + + PRIV2BB2 + 2 + 1 + read-write + + + PRIV2BB3 + 3 + 1 + read-write + + + PRIV2BB4 + 4 + 1 + read-write + + + PRIV2BB5 + 5 + 1 + read-write + + + PRIV2BB6 + 6 + 1 + read-write + + + PRIV2BB7 + 7 + 1 + read-write + + + PRIV2BB8 + 8 + 1 + read-write + + + PRIV2BB9 + 9 + 1 + read-write + + + PRIV2BB10 + 10 + 1 + read-write + + + PRIV2BB11 + 11 + 1 + read-write + + + PRIV2BB12 + 12 + 1 + read-write + + + PRIV2BB13 + 13 + 1 + read-write + + + PRIV2BB14 + 14 + 1 + read-write + + + PRIV2BB15 + 15 + 1 + read-write + + + PRIV2BB16 + 16 + 1 + read-write + + + PRIV2BB17 + 17 + 1 + read-write + + + PRIV2BB18 + 18 + 1 + read-write + + + PRIV2BB19 + 19 + 1 + read-write + + + PRIV2BB20 + 20 + 1 + read-write + + + PRIV2BB21 + 21 + 1 + read-write + + + PRIV2BB22 + 22 + 1 + read-write + + + PRIV2BB23 + 23 + 1 + read-write + + + PRIV2BB24 + 24 + 1 + read-write + + + PRIV2BB25 + 25 + 1 + read-write + + + PRIV2BB26 + 26 + 1 + read-write + + + PRIV2BB27 + 27 + 1 + read-write + + + PRIV2BB28 + 28 + 1 + read-write + + + PRIV2BB29 + 29 + 1 + read-write + + + PRIV2BB30 + 30 + 1 + read-write + + + PRIV2BB31 + 31 + 1 + read-write + + + + + + + SEC_FLASH + DCB->DSCSR->CDS == 0 + 0x50022000 + + + FMAC + Filter Math Accelerator + FMAC + 0x40021400 + + 0x0 + 0x400 + registers + + + FMAC + FMAC interrupt + 124 + + + + X1BUFCFG + X1BUFCFG + FMAC X1 Buffer Configuration register + 0x0 + 0x20 + read-write + 0x00000000 + + + X1_BASE + Base address of X1 buffer + 0 + 8 + + + X1_BUF_SIZE + Allocated size of X1 buffer in 16-bit words + 8 + 8 + + + FULL_WM + Watermark for buffer full flag + 24 + 2 + + + + + X2BUFCFG + X2BUFCFG + FMAC X2 Buffer Configuration register + 0x4 + 0x20 + read-write + 0x00000000 + + + X2_BASE + Base address of X2 buffer + 0 + 8 + + + X2_BUF_SIZE + Size of X2 buffer in 16-bit words + 8 + 8 + + + + + YBUFCFG + YBUFCFG + FMAC Y Buffer Configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + Y_BASE + Base address of Y buffer + 0 + 8 + + + Y_BUF_SIZE + Size of Y buffer in 16-bit words + 8 + 8 + + + EMPTY_WM + Watermark for buffer empty flag + 24 + 2 + + + + + PARAM + PARAM + FMAC Parameter register + 0xC + 0x20 + read-write + 0x00000000 + + + START + Enable execution + 31 + 1 + + + FUNC + Function + 24 + 7 + + + R + Input parameter R + 16 + 8 + + + Q + Input parameter Q + 8 + 8 + + + P + Input parameter P + 0 + 8 + + + + + CR + CR + FMAC Control register + 0x10 + 0x20 + read-write + 0x00000000 + + + RESET + Reset FMAC unit + 16 + 1 + + + CLIPEN + Enable clipping + 15 + 1 + + + DMAWEN + Enable DMA write channel requests + 9 + 1 + + + DMAREN + Enable DMA read channel requests + 8 + 1 + + + SATIEN + Enable saturation error interrupts + 4 + 1 + + + UNFLIEN + Enable underflow error interrupts + 3 + 1 + + + OVFLIEN + Enable overflow error interrupts + 2 + 1 + + + WIEN + Enable write interrupt + 1 + 1 + + + RIEN + Enable read interrupt + 0 + 1 + + + + + SR + SR + FMAC Status register + 0x14 + 0x20 + read-only + 0x00000001 + + + YEMPTY + Y buffer empty flag + 0 + 1 + + + X1FULL + X1 buffer full flag + 1 + 1 + + + OVFL + Overflow error flag + 8 + 1 + + + UNFL + Underflow error flag + 9 + 1 + + + SAT + Saturation error flag + 10 + 1 + + + + + WDATA + WDATA + FMAC Write Data register + 0x18 + 0x20 + write-only + 0x00000000 + + + WDATA + Write data + 0 + 16 + + + + + RDATA + RDATA + FMAC Read Data register + 0x1C + 0x20 + read-only + 0x00000000 + + + RDATA + Read data + 0 + 16 + + + + + + + SEC_FMAC + DCB->DSCSR->CDS == 0 + 0x50021400 + + + FMC + FMC + FMC + 0x420D0400 + + 0x0 + 0x400 + registers + + + FMC + FMC global interrupt + 75 + + + + BCR1 + BCR1 + SRAM/NOR-Flash chip-select control register for bank 1 + 0x0 + 0x20 + read-write + 0x000030DB + + + MBKEN + Memory bank enable bit + 0 + 1 + + + MUXEN + Address/data multiplexing enable bit + 1 + 1 + + + MTYP + Memory type + 2 + 2 + + + MWID + Memory data bus width + 4 + 2 + + + FACCEN + Flash access enable + 6 + 1 + + + BURSTEN + Burst enable bit + 8 + 1 + + + WAITPOL + Wait signal polarity bit + 9 + 1 + + + WAITCFG + Wait timing configuration + 11 + 1 + + + WREN + Write enable bit + 12 + 1 + + + WAITEN + Wait enable bit + 13 + 1 + + + EXTMOD + Extended mode enable + 14 + 1 + + + ASYNCWAIT + Wait signal during asynchronous + transfers + 15 + 1 + + + CPSIZE + CRAM Page Size + 16 + 3 + + + CBURSTRW + Write burst enable + 19 + 1 + + + CCLKEN + Continuous clock enable + 20 + 1 + + + WFDIS + Write FIFO disable + 21 + 1 + + + NBLSET + Byte lane (NBL) setup + 22 + 2 + + + FMCEN + FMC controller enable + 31 + 1 + + + + + BCR2 + BCR2 + SRAM/NOR-Flash chip-select control register for bank 2 + 0x8 + 0x20 + read-write + 0x000030D2 + + + MBKEN + Memory bank enable bit + 0 + 1 + + + MUXEN + Address/data multiplexing enable bit + 1 + 1 + + + MTYP + Memory type + 2 + 2 + + + MWID + Memory data bus width + 4 + 2 + + + FACCEN + Flash access enable + 6 + 1 + + + BURSTEN + Burst enable bit + 8 + 1 + + + WAITPOL + Wait signal polarity bit + 9 + 1 + + + WAITCFG + Wait timing configuration + 11 + 1 + + + WREN + Write enable bit + 12 + 1 + + + WAITEN + Wait enable bit + 13 + 1 + + + EXTMOD + Extended mode enable + 14 + 1 + + + ASYNCWAIT + Wait signal during asynchronous + transfers + 15 + 1 + + + CPSIZE + CRAM Page Size + 16 + 3 + + + CBURSTRW + Write burst enable + 19 + 1 + + + CCLKEN + Continuous clock enable + 20 + 1 + + + WFDIS + Write FIFO disable + 21 + 1 + + + NBLSET + Byte lane (NBL) setup + 22 + 2 + + + FMCEN + FMC controller enable + 31 + 1 + + + + + BCR3 + BCR3 + SRAM/NOR-Flash chip-select control register for bank 3 + 0x10 + 0x20 + read-write + 0x000030D2 + + + MBKEN + Memory bank enable bit + 0 + 1 + + + MUXEN + Address/data multiplexing enable bit + 1 + 1 + + + MTYP + Memory type + 2 + 2 + + + MWID + Memory data bus width + 4 + 2 + + + FACCEN + Flash access enable + 6 + 1 + + + BURSTEN + Burst enable bit + 8 + 1 + + + WAITPOL + Wait signal polarity bit + 9 + 1 + + + WAITCFG + Wait timing configuration + 11 + 1 + + + WREN + Write enable bit + 12 + 1 + + + WAITEN + Wait enable bit + 13 + 1 + + + EXTMOD + Extended mode enable + 14 + 1 + + + ASYNCWAIT + Wait signal during asynchronous + transfers + 15 + 1 + + + CPSIZE + CRAM Page Size + 16 + 3 + + + CBURSTRW + Write burst enable + 19 + 1 + + + CCLKEN + Continuous clock enable + 20 + 1 + + + WFDIS + Write FIFO disable + 21 + 1 + + + NBLSET + Byte lane (NBL) setup + 22 + 2 + + + FMCEN + FMC controller enable + 31 + 1 + + + + + BCR4 + BCR4 + SRAM/NOR-Flash chip-select control register for bank 4 + 0x18 + 0x20 + read-write + 0x000030D2 + + + MBKEN + Memory bank enable bit + 0 + 1 + + + MUXEN + Address/data multiplexing enable bit + 1 + 1 + + + MTYP + Memory type + 2 + 2 + + + MWID + Memory data bus width + 4 + 2 + + + FACCEN + Flash access enable + 6 + 1 + + + BURSTEN + Burst enable bit + 8 + 1 + + + WAITPOL + Wait signal polarity bit + 9 + 1 + + + WAITCFG + Wait timing configuration + 11 + 1 + + + WREN + Write enable bit + 12 + 1 + + + WAITEN + Wait enable bit + 13 + 1 + + + EXTMOD + Extended mode enable + 14 + 1 + + + ASYNCWAIT + Wait signal during asynchronous + transfers + 15 + 1 + + + CPSIZE + CRAM Page Size + 16 + 3 + + + CBURSTRW + Write burst enable + 19 + 1 + + + CCLKEN + Continuous clock enable + 20 + 1 + + + WFDIS + Write FIFO disable + 21 + 1 + + + NBLSET + Byte lane (NBL) setup + 22 + 2 + + + FMCEN + FMC controller enable + 31 + 1 + + + + + BTR1 + BTR1 + SRAM/NOR-Flash chip-select timing register for bank 1 + 0x4 + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + Address setup phase duration + 0 + 4 + + + ADDHLD + Address-hold phase duration + 4 + 4 + + + DATAST + Data-phase duration + 8 + 8 + + + BUSTURN + Bus turnaround phase duration + 16 + 4 + + + CLKDIV + Clock divide ratio (for FMC_CLK signal) + 20 + 4 + + + DATLAT + Data latency for synchronous memory + 24 + 4 + + + ACCMOD + Access mode + 28 + 2 + + + DATAHLD + Data hold phase duration + 30 + 2 + + + + + BTR2 + BTR2 + SRAM/NOR-Flash chip-select timing register for bank 2 + 0xC + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + Address setup phase duration + 0 + 4 + + + ADDHLD + Address-hold phase duration + 4 + 4 + + + DATAST + Data-phase duration + 8 + 8 + + + BUSTURN + Bus turnaround phase duration + 16 + 4 + + + CLKDIV + Clock divide ratio (for FMC_CLK signal) + 20 + 4 + + + DATLAT + Data latency for synchronous memory + 24 + 4 + + + ACCMOD + Access mode + 28 + 2 + + + DATAHLD + Data hold phase duration + 30 + 2 + + + + + BTR3 + BTR3 + SRAM/NOR-Flash chip-select timing register for bank 3 + 0x14 + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + Address setup phase duration + 0 + 4 + + + ADDHLD + Address-hold phase duration + 4 + 4 + + + DATAST + Data-phase duration + 8 + 8 + + + BUSTURN + Bus turnaround phase duration + 16 + 4 + + + CLKDIV + Clock divide ratio (for FMC_CLK signal) + 20 + 4 + + + DATLAT + Data latency for synchronous memory + 24 + 4 + + + ACCMOD + Access mode + 28 + 2 + + + DATAHLD + Data hold phase duration + 30 + 2 + + + + + BTR4 + BTR4 + SRAM/NOR-Flash chip-select timing register for bank 4 + 0x1C + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + Address setup phase duration + 0 + 4 + + + ADDHLD + Address-hold phase duration + 4 + 4 + + + DATAST + Data-phase duration + 8 + 8 + + + BUSTURN + Bus turnaround phase duration + 16 + 4 + + + CLKDIV + Clock divide ratio (for FMC_CLK signal) + 20 + 4 + + + DATLAT + Data latency for synchronous memory + 24 + 4 + + + ACCMOD + Access mode + 28 + 2 + + + DATAHLD + Data hold phase duration + 30 + 2 + + + + + BWTR1 + BWTR1 + SRAM/NOR-Flash write timing registers 1 + 0x104 + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + Address setup phase duration + 0 + 4 + + + ADDHLD + Address-hold phase duration + 4 + 4 + + + DATAST + Data-phase duration + 8 + 8 + + + BUSTURN + Bus turnaround phase duration + 16 + 4 + + + ACCMOD + Access mode + 28 + 2 + + + DATAHLD + Data hold phase duration + 30 + 2 + + + + + BWTR2 + BWTR2 + SRAM/NOR-Flash write timing registers 2 + 0x10C + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + Address setup phase duration + 0 + 4 + + + ADDHLD + Address-hold phase duration + 4 + 4 + + + DATAST + Data-phase duration + 8 + 8 + + + BUSTURN + Bus turnaround phase duration + 16 + 4 + + + ACCMOD + Access mode + 28 + 2 + + + DATAHLD + Data hold phase duration + 30 + 2 + + + + + BWTR3 + BWTR3 + SRAM/NOR-Flash write timing registers 3 + 0x114 + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + Address setup phase duration + 0 + 4 + + + ADDHLD + Address-hold phase duration + 4 + 4 + + + DATAST + Data-phase duration + 8 + 8 + + + BUSTURN + Bus turnaround phase duration + 16 + 4 + + + ACCMOD + Access mode + 28 + 2 + + + DATAHLD + Data hold phase duration + 30 + 2 + + + + + BWTR4 + BWTR4 + SRAM/NOR-Flash write timing registers 4 + 0x11C + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + Address setup phase duration + 0 + 4 + + + ADDHLD + Address-hold phase duration + 4 + 4 + + + DATAST + Data-phase duration + 8 + 8 + + + BUSTURN + Bus turnaround phase duration + 16 + 4 + + + ACCMOD + Access mode + 28 + 2 + + + DATAHLD + Data hold phase duration + 30 + 2 + + + + + PCSCNTR + PCSCNTR + PSRAM chip select counter register + 0x20 + 0x20 + read-write + 0x00000000 + + + CSCOUNT + Chip select counter + 0 + 16 + + + CNTB1EN + Counter Bank 1 enable + 16 + 1 + + + CNTB2EN + Counter Bank 2 enable + 17 + 1 + + + CNTB3EN + Counter Bank 3 enable + 18 + 1 + + + CNTB4EN + Counter Bank 4 enable + 19 + 1 + + + + + PCR + PCR + NAND Flash control registers + 0x80 + 0x20 + read-write + 0x00000018 + + + PWAITEN + Wait feature enable bit + 1 + 1 + + + PBKEN + NAND Flash memory bank enable bit + 2 + 1 + + + PTYP + Memory type + 3 + 1 + + + PWID + Data bus width + 4 + 2 + + + ECCEN + ECC computation logic enable bit + 6 + 1 + + + TCLR + CLE to RE delay + 9 + 4 + + + TAR + ALE to RE delay + 13 + 3 + + + ECCPS + ECC page size + 17 + 3 + + + + + SR + SR + status and interrupt register + 0x84 + 0x20 + 0x00000040 + + + IRS + Interrupt rising edge status The flag is + set by hardware and reset by software. Note: If this + bit is written by software to 1 it will be + set. + 0 + 1 + read-write + + + ILS + Interrupt high-level status The flag is + set by hardware and reset by software. + 1 + 1 + read-write + + + IFS + Interrupt falling edge status The flag + is set by hardware and reset by software. Note: If + this bit is written by software to 1 it will be + set. + 2 + 1 + read-write + + + IREN + Interrupt rising edge detection enable + bit + 3 + 1 + read-write + + + ILEN + Interrupt high-level detection enable + bit + 4 + 1 + read-write + + + IFEN + Interrupt falling edge detection enable + bit + 5 + 1 + read-write + + + FEMPT + FIFO empty. Read-only bit that provides + the status of the FIFO + 6 + 1 + read-only + + + + + PMEM + PMEM + Common memory space timing register + 0x88 + 0x20 + read-write + 0xFCFCFCFC + + + MEMSET + Common memory x setup time These bits + define the number of KCK_FMC (+1) clock cycles to set + up the address before the command assertion (NWE, + NOE), for NAND Flash read or write access to common + memory space: + 0 + 8 + + + MEMWAIT + Common memory wait time These bits + define the minimum number of KCK_FMC (+1) clock + cycles to assert the command (NWE, NOE), for NAND + Flash read or write access to common memory space. + The duration of command assertion is extended if the + wait signal (NWAIT) is active (low) at the end of the + programmed value of KCK_FMC: + 8 + 8 + + + MEMHOLD + Common memory hold time These bits + define the number of KCK_FMC clock cycles for write + accesses and KCK_FMC+1 clock cycles for read accesses + during which the address is held (and data for write + accesses) after the command is de-asserted (NWE, + NOE), for NAND Flash read or write access to common + memory space: + 16 + 8 + + + MEMHIZ + Common memory x data bus Hi-Z time These + bits define the number of KCK_FMC clock cycles during + which the data bus is kept Hi-Z after the start of a + NAND Flash write access to common memory space. This + is only valid for write transactions: + 24 + 8 + + + + + PATT + PATT + The FMC_PATT read/write register contains + the timing information for NAND Flash memory bank. It is + used for 8-bit accesses to the attribute memory space of + the NAND Flash for the last address write access if the + timing must differ from that of previous accesses (for + Ready/Busy management, refer to Section20.8.5: NAND Flash + prewait feature). + 0x8C + 0x20 + read-write + 0xFCFCFCFC + + + ATTSET + Attribute memory setup time These bits + define the number of KCK_FMC (+1) clock cycles to set + up address before the command assertion (NWE, NOE), + for NAND Flash read or write access to attribute + memory space: + 0 + 8 + + + ATTWAIT + Attribute memory wait time These bits + define the minimum number of x KCK_FMC (+1) clock + cycles to assert the command (NWE, NOE), for NAND + Flash read or write access to attribute memory space. + The duration for command assertion is extended if the + wait signal (NWAIT) is active (low) at the end of the + programmed value of KCK_FMC: + 8 + 8 + + + ATTHOLD + Attribute memory hold time These bits + define the number of KCK_FMC clock cycles during + which the address is held (and data for write access) + after the command de-assertion (NWE, NOE), for NAND + Flash read or write access to attribute memory + space: + 16 + 8 + + + ATTHIZ + Attribute memory data bus Hi-Z time + These bits define the number of KCK_FMC clock cycles + during which the data bus is kept in Hi-Z after the + start of a NAND Flash write access to attribute + memory space on socket. Only valid for writ + transaction: + 24 + 8 + + + + + ECCR + ECCR + This register contain the current error + correction code value computed by the ECC computation + modules of the FMC NAND controller. When the CPU + reads/writes the data from a NAND Flash memory page at + the correct address (refer to Section20.8.6: Computation + of the error correction code (ECC) in NAND Flash memory), + the data read/written from/to the NAND Flash memory are + processed automatically by the ECC computation module. + When X bytes have been read (according to the ECCPS field + in the FMC_PCR registers), the CPU must read the computed + ECC value from the FMC_ECC registers. It then verifies if + these computed parity data are the same as the parity + value recorded in the spare area, to determine whether a + page is valid, and, to correct it otherwise. The FMC_ECCR + register should be cleared after being read by setting + the ECCEN bit to 0. To compute a new data block, the + ECCEN bit must be set to 1. + 0x94 + 0x20 + read-only + 0x00000000 + + + ECC + ECC result This field contains the value + computed by the ECC computation logic. Table167 + describes the contents of these bit + fields. + 0 + 32 + + + + + + + SEC_FMC + DCB->DSCSR->CDS == 0 + 0x520D0400 + + + GFXMMU + GFXMMU + GFXMMU + 0x4002C000 + + 0x0 + 0x3000 + registers + + + GFXMMU + GFXMMU global error interrupt + 134 + + + + GFXMMU_CR + GFXMMU_CR + GFXMMU configuration register + 0x0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + B0OIE + Buffer 0 overflow interrupt enable +This bit enables the buffer 0 overflow interrupt. + 0 + 1 + read-write + + + B_0x0 + Interrupt disable + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + B1OIE + Buffer 1 overflow interrupt enable +This bit enables the buffer 1 overflow interrupt. + 1 + 1 + read-write + + + B_0x0 + Interrupt disable + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + B2OIE + Buffer 2 overflow interrupt enable +This bit enables the buffer 2 overflow interrupt. + 2 + 1 + read-write + + + B_0x0 + Interrupt disable + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + B3OIE + Buffer 3 overflow interrupt enable +This bit enables the buffer 3 overflow interrupt. + 3 + 1 + read-write + + + B_0x0 + Interrupt disable + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + AMEIE + AHB master error interrupt enable +This bit enables the AHB master error interrupt. + 4 + 1 + read-write + + + B_0x0 + Interrupt disable + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + BM192 + 192 Block mode +This bit defines the number of blocks per line + 6 + 1 + read-write + + + B_0x0 + 256 blocks per line + 0x0 + + + B_0x1 + 192 blocks per line + 0x1 + + + + + CE + Cache enable +This bit enables the cache unit. + 7 + 1 + read-write + + + B_0x0 + Cache disable + 0x0 + + + B_0x1 + Cache enable + 0x1 + + + + + CL + Cache lock +This bit lock the cache onto the buffer defined in the CLB field. + 8 + 1 + read-write + + + B_0x0 + Cache not locked + 0x0 + + + B_0x1 + Cache locked to a buffer + 0x1 + + + + + CLB + Cache lock buffer +This field select the buffer on which the cache is locked. + 9 + 2 + read-write + + + B_0x0 + Cache locked on buffer 0 + 0x0 + + + B_0x1 + Cache locked on buffer 1 + 0x1 + + + B_0x2 + Cache locked on buffer 2 + 0x2 + + + B_0x3 + Cache locked on buffer 3 + 0x3 + + + + + FC + Force caching +This bit force the caching into the cache regardless of the MPU attributes. +The cache must be enable (CE bit set). + 11 + 1 + read-write + + + B_0x0 + Caching not forced + 0x0 + + + B_0x1 + Caching forced + 0x1 + + + + + PD + Prefetch disable +This bit disables the prefetch of the cache. + 12 + 1 + read-write + + + B_0x0 + Prefetch enable + 0x0 + + + B_0x1 + Prefetch disable + 0x1 + + + + + OC + Outter cachability +This bit configure the cachability of an access generated by the GFXMMU cache. + 16 + 1 + read-write + + + B_0x0 + No cachable + 0x0 + + + B_0x1 + Cachable + 0x1 + + + + + OB + Outter bufferability +This bit configure the bufferability of an access generated by the GFXMMU cache. + 17 + 1 + read-write + + + B_0x0 + No bufferable + 0x0 + + + B_0x1 + Bufferable + 0x1 + + + + + + + GFXMMU_SR + GFXMMU_SR + GFXMMU status register + 0x4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + B0OF + Buffer 0 overflow flag +This bit is set when an overflow occurs during the offset calculation of the buffer 0. It is cleared by writing 1 to CB0OF. + 0 + 1 + read-only + + + B1OF + Buffer 1 overflow flag +This bit is set when an overflow occurs during the offset calculation of the buffer 1. It is cleared by writing 1 to CB1OF. + 1 + 1 + read-only + + + B2OF + Buffer 2 overflow flag +This bit is set when an overflow occurs during the offset calculation of the buffer 2. It is cleared by writing 1 to CB2OF. + 2 + 1 + read-only + + + B3OF + Buffer 3 overflow flag +This bit is set when an overflow occurs during the offset calculation of the buffer 3. It is cleared by writing 1 to CB3OF. + 3 + 1 + read-only + + + AMEF + AHB master error flag +This bit is set when an AHB error happens during a transaction. It is cleared by writing 1 to CAMEF. + 4 + 1 + read-only + + + + + GFXMMU_FCR + GFXMMU_FCR + GFXMMU flag clear register + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CB0OF + Clear buffer 0 overflow flag +Writing 1 clears the buffer 0 overflow flag in the GFXMMU_SR register. + 0 + 1 + read-write + + + CB1OF + Clear buffer 1 overflow flag +Writing 1 clears the buffer 1 overflow flag in the GFXMMU_SR register. + 1 + 1 + read-write + + + CB2OF + Clear buffer 2 overflow flag +Writing 1 clears the buffer 2 overflow flag in the GFXMMU_SR register. + 2 + 1 + read-write + + + CB3OF + Clear buffer 3 overflow flag +Writing 1 clears the buffer 3 overflow flag in the GFXMMU_SR register. + 3 + 1 + read-write + + + CAMEF + Clear AHB master error flag +Writing 1 clears the AHB master error flag in the GFXMMU_SR register. + 4 + 1 + read-write + + + + + GFXMMU_CCR + GFXMMU_CCR + GFXMMU cache control register + 0xc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FF + Force flush +When set, the cache entries are flushed. This bit is reset by hardware when the flushing is complete. Write 0 has no effect. + 0 + 1 + read-write + + + B_0x0 + Flushing process complete + 0x0 + + + B_0x1 + Force flush/flushing process on going + 0x1 + + + + + FI + Force invalidate +When set, the cache entries are invalidated. This bit is reset by hardware when the invalidation is complete. Write 0 has no effect. + 1 + 1 + read-write + + + B_0x0 + Invalidation process complete + 0x0 + + + B_0x1 + Force invalidation/invalidation process on going + 0x1 + + + + + + + GFXMMU_DVR + GFXMMU_DVR + GFXMMU default value register + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DV + Default value +This field indicates the default 32-bit value which is returned when a master accesses a virtual memory location not physically mapped. + 0 + 32 + read-write + + + + + GFXMMU_B0CR + GFXMMU_B0CR + GFXMMU buffer 0 configuration register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PBO + Physical buffer offset +Offset of the physical buffer. + 4 + 19 + read-write + + + PBBA + Physical buffer base address +Base address MSB of the physical buffer. + 23 + 9 + read-write + + + + + GFXMMU_B1CR + GFXMMU_B1CR + GFXMMU buffer 1 configuration register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PBO + Physical buffer offset +Offset of the physical buffer. + 4 + 19 + read-write + + + PBBA + Physical buffer base address +Base address MSB of the physical buffer. + 23 + 9 + read-write + + + + + GFXMMU_B2CR + GFXMMU_B2CR + GFXMMU buffer 2 configuration register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PBO + Physical buffer offset +Offset of the physical buffer. + 4 + 19 + read-write + + + PBBA + Physical buffer base address +Base address MSB of the physical buffer. + 23 + 9 + read-write + + + + + GFXMMU_B3CR + GFXMMU_B3CR + GFXMMU buffer 3 configuration register + 0x2c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PBO + Physical buffer offset +Offset of the physical buffer. + 4 + 19 + read-write + + + PBBA + Physical buffer base address +Base address MSB of the physical buffer. + 23 + 9 + read-write + + + + + GFXMMU_LUT0L + GFXMMU_LUT0L + GFXMMU LUT entry 0 low + 0x1000 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT0H + GFXMMU_LUT0H + GFXMMU LUT entry 0 high + 0x1004 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT1L + GFXMMU_LUT1L + GFXMMU LUT entry 1 low + 0x1008 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT1H + GFXMMU_LUT1H + GFXMMU LUT entry 1 high + 0x100c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT2L + GFXMMU_LUT2L + GFXMMU LUT entry 2 low + 0x1010 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT2H + GFXMMU_LUT2H + GFXMMU LUT entry 2 high + 0x1014 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT3L + GFXMMU_LUT3L + GFXMMU LUT entry 3 low + 0x1018 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT3H + GFXMMU_LUT3H + GFXMMU LUT entry 3 high + 0x101c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT4L + GFXMMU_LUT4L + GFXMMU LUT entry 4 low + 0x1020 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT4H + GFXMMU_LUT4H + GFXMMU LUT entry 4 high + 0x1024 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT5L + GFXMMU_LUT5L + GFXMMU LUT entry 5 low + 0x1028 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT5H + GFXMMU_LUT5H + GFXMMU LUT entry 5 high + 0x102c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT6L + GFXMMU_LUT6L + GFXMMU LUT entry 6 low + 0x1030 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT6H + GFXMMU_LUT6H + GFXMMU LUT entry 6 high + 0x1034 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT7L + GFXMMU_LUT7L + GFXMMU LUT entry 7 low + 0x1038 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT7H + GFXMMU_LUT7H + GFXMMU LUT entry 7 high + 0x103c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT8L + GFXMMU_LUT8L + GFXMMU LUT entry 8 low + 0x1040 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT8H + GFXMMU_LUT8H + GFXMMU LUT entry 8 high + 0x1044 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT9L + GFXMMU_LUT9L + GFXMMU LUT entry 9 low + 0x1048 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT9H + GFXMMU_LUT9H + GFXMMU LUT entry 9 high + 0x104c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT10L + GFXMMU_LUT10L + GFXMMU LUT entry 10 low + 0x1050 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT10H + GFXMMU_LUT10H + GFXMMU LUT entry 10 high + 0x1054 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT11L + GFXMMU_LUT11L + GFXMMU LUT entry 11 low + 0x1058 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT11H + GFXMMU_LUT11H + GFXMMU LUT entry 11 high + 0x105c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT12L + GFXMMU_LUT12L + GFXMMU LUT entry 12 low + 0x1060 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT12H + GFXMMU_LUT12H + GFXMMU LUT entry 12 high + 0x1064 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT13L + GFXMMU_LUT13L + GFXMMU LUT entry 13 low + 0x1068 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT13H + GFXMMU_LUT13H + GFXMMU LUT entry 13 high + 0x106c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT14L + GFXMMU_LUT14L + GFXMMU LUT entry 14 low + 0x1070 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT14H + GFXMMU_LUT14H + GFXMMU LUT entry 14 high + 0x1074 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT15L + GFXMMU_LUT15L + GFXMMU LUT entry 15 low + 0x1078 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT15H + GFXMMU_LUT15H + GFXMMU LUT entry 15 high + 0x107c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT16L + GFXMMU_LUT16L + GFXMMU LUT entry 16 low + 0x1080 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT16H + GFXMMU_LUT16H + GFXMMU LUT entry 16 high + 0x1084 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT17L + GFXMMU_LUT17L + GFXMMU LUT entry 17 low + 0x1088 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT17H + GFXMMU_LUT17H + GFXMMU LUT entry 17 high + 0x108c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT18L + GFXMMU_LUT18L + GFXMMU LUT entry 18 low + 0x1090 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT18H + GFXMMU_LUT18H + GFXMMU LUT entry 18 high + 0x1094 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT19L + GFXMMU_LUT19L + GFXMMU LUT entry 19 low + 0x1098 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT19H + GFXMMU_LUT19H + GFXMMU LUT entry 19 high + 0x109c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT20L + GFXMMU_LUT20L + GFXMMU LUT entry 20 low + 0x10a0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT20H + GFXMMU_LUT20H + GFXMMU LUT entry 20 high + 0x10a4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT21L + GFXMMU_LUT21L + GFXMMU LUT entry 21 low + 0x10a8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT21H + GFXMMU_LUT21H + GFXMMU LUT entry 21 high + 0x10ac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT22L + GFXMMU_LUT22L + GFXMMU LUT entry 22 low + 0x10b0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT22H + GFXMMU_LUT22H + GFXMMU LUT entry 22 high + 0x10b4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT23L + GFXMMU_LUT23L + GFXMMU LUT entry 23 low + 0x10b8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT23H + GFXMMU_LUT23H + GFXMMU LUT entry 23 high + 0x10bc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT24L + GFXMMU_LUT24L + GFXMMU LUT entry 24 low + 0x10c0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT24H + GFXMMU_LUT24H + GFXMMU LUT entry 24 high + 0x10c4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT25L + GFXMMU_LUT25L + GFXMMU LUT entry 25 low + 0x10c8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT25H + GFXMMU_LUT25H + GFXMMU LUT entry 25 high + 0x10cc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT26L + GFXMMU_LUT26L + GFXMMU LUT entry 26 low + 0x10d0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT26H + GFXMMU_LUT26H + GFXMMU LUT entry 26 high + 0x10d4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT27L + GFXMMU_LUT27L + GFXMMU LUT entry 27 low + 0x10d8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT27H + GFXMMU_LUT27H + GFXMMU LUT entry 27 high + 0x10dc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT28L + GFXMMU_LUT28L + GFXMMU LUT entry 28 low + 0x10e0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT28H + GFXMMU_LUT28H + GFXMMU LUT entry 28 high + 0x10e4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT29L + GFXMMU_LUT29L + GFXMMU LUT entry 29 low + 0x10e8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT29H + GFXMMU_LUT29H + GFXMMU LUT entry 29 high + 0x10ec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT30L + GFXMMU_LUT30L + GFXMMU LUT entry 30 low + 0x10f0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT30H + GFXMMU_LUT30H + GFXMMU LUT entry 30 high + 0x10f4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT31L + GFXMMU_LUT31L + GFXMMU LUT entry 31 low + 0x10f8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT31H + GFXMMU_LUT31H + GFXMMU LUT entry 31 high + 0x10fc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT32L + GFXMMU_LUT32L + GFXMMU LUT entry 32 low + 0x1100 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT32H + GFXMMU_LUT32H + GFXMMU LUT entry 32 high + 0x1104 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT33L + GFXMMU_LUT33L + GFXMMU LUT entry 33 low + 0x1108 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT33H + GFXMMU_LUT33H + GFXMMU LUT entry 33 high + 0x110c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT34L + GFXMMU_LUT34L + GFXMMU LUT entry 34 low + 0x1110 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT34H + GFXMMU_LUT34H + GFXMMU LUT entry 34 high + 0x1114 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT35L + GFXMMU_LUT35L + GFXMMU LUT entry 35 low + 0x1118 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT35H + GFXMMU_LUT35H + GFXMMU LUT entry 35 high + 0x111c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT36L + GFXMMU_LUT36L + GFXMMU LUT entry 36 low + 0x1120 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT36H + GFXMMU_LUT36H + GFXMMU LUT entry 36 high + 0x1124 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT37L + GFXMMU_LUT37L + GFXMMU LUT entry 37 low + 0x1128 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT37H + GFXMMU_LUT37H + GFXMMU LUT entry 37 high + 0x112c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT38L + GFXMMU_LUT38L + GFXMMU LUT entry 38 low + 0x1130 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT38H + GFXMMU_LUT38H + GFXMMU LUT entry 38 high + 0x1134 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT39L + GFXMMU_LUT39L + GFXMMU LUT entry 39 low + 0x1138 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT39H + GFXMMU_LUT39H + GFXMMU LUT entry 39 high + 0x113c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT40L + GFXMMU_LUT40L + GFXMMU LUT entry 40 low + 0x1140 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT40H + GFXMMU_LUT40H + GFXMMU LUT entry 40 high + 0x1144 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT41L + GFXMMU_LUT41L + GFXMMU LUT entry 41 low + 0x1148 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT41H + GFXMMU_LUT41H + GFXMMU LUT entry 41 high + 0x114c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT42L + GFXMMU_LUT42L + GFXMMU LUT entry 42 low + 0x1150 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT42H + GFXMMU_LUT42H + GFXMMU LUT entry 42 high + 0x1154 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT43L + GFXMMU_LUT43L + GFXMMU LUT entry 43 low + 0x1158 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT43H + GFXMMU_LUT43H + GFXMMU LUT entry 43 high + 0x115c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT44L + GFXMMU_LUT44L + GFXMMU LUT entry 44 low + 0x1160 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT44H + GFXMMU_LUT44H + GFXMMU LUT entry 44 high + 0x1164 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT45L + GFXMMU_LUT45L + GFXMMU LUT entry 45 low + 0x1168 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT45H + GFXMMU_LUT45H + GFXMMU LUT entry 45 high + 0x116c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT46L + GFXMMU_LUT46L + GFXMMU LUT entry 46 low + 0x1170 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT46H + GFXMMU_LUT46H + GFXMMU LUT entry 46 high + 0x1174 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT47L + GFXMMU_LUT47L + GFXMMU LUT entry 47 low + 0x1178 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT47H + GFXMMU_LUT47H + GFXMMU LUT entry 47 high + 0x117c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT48L + GFXMMU_LUT48L + GFXMMU LUT entry 48 low + 0x1180 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT48H + GFXMMU_LUT48H + GFXMMU LUT entry 48 high + 0x1184 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT49L + GFXMMU_LUT49L + GFXMMU LUT entry 49 low + 0x1188 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT49H + GFXMMU_LUT49H + GFXMMU LUT entry 49 high + 0x118c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT50L + GFXMMU_LUT50L + GFXMMU LUT entry 50 low + 0x1190 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT50H + GFXMMU_LUT50H + GFXMMU LUT entry 50 high + 0x1194 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT51L + GFXMMU_LUT51L + GFXMMU LUT entry 51 low + 0x1198 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT51H + GFXMMU_LUT51H + GFXMMU LUT entry 51 high + 0x119c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT52L + GFXMMU_LUT52L + GFXMMU LUT entry 52 low + 0x11a0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT52H + GFXMMU_LUT52H + GFXMMU LUT entry 52 high + 0x11a4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT53L + GFXMMU_LUT53L + GFXMMU LUT entry 53 low + 0x11a8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT53H + GFXMMU_LUT53H + GFXMMU LUT entry 53 high + 0x11ac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT54L + GFXMMU_LUT54L + GFXMMU LUT entry 54 low + 0x11b0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT54H + GFXMMU_LUT54H + GFXMMU LUT entry 54 high + 0x11b4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT55L + GFXMMU_LUT55L + GFXMMU LUT entry 55 low + 0x11b8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT55H + GFXMMU_LUT55H + GFXMMU LUT entry 55 high + 0x11bc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT56L + GFXMMU_LUT56L + GFXMMU LUT entry 56 low + 0x11c0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT56H + GFXMMU_LUT56H + GFXMMU LUT entry 56 high + 0x11c4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT57L + GFXMMU_LUT57L + GFXMMU LUT entry 57 low + 0x11c8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT57H + GFXMMU_LUT57H + GFXMMU LUT entry 57 high + 0x11cc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT58L + GFXMMU_LUT58L + GFXMMU LUT entry 58 low + 0x11d0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT58H + GFXMMU_LUT58H + GFXMMU LUT entry 58 high + 0x11d4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT59L + GFXMMU_LUT59L + GFXMMU LUT entry 59 low + 0x11d8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT59H + GFXMMU_LUT59H + GFXMMU LUT entry 59 high + 0x11dc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT60L + GFXMMU_LUT60L + GFXMMU LUT entry 60 low + 0x11e0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT60H + GFXMMU_LUT60H + GFXMMU LUT entry 60 high + 0x11e4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT61L + GFXMMU_LUT61L + GFXMMU LUT entry 61 low + 0x11e8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT61H + GFXMMU_LUT61H + GFXMMU LUT entry 61 high + 0x11ec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT62L + GFXMMU_LUT62L + GFXMMU LUT entry 62 low + 0x11f0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT62H + GFXMMU_LUT62H + GFXMMU LUT entry 62 high + 0x11f4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT63L + GFXMMU_LUT63L + GFXMMU LUT entry 63 low + 0x11f8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT63H + GFXMMU_LUT63H + GFXMMU LUT entry 63 high + 0x11fc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT64L + GFXMMU_LUT64L + GFXMMU LUT entry 64 low + 0x1200 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT64H + GFXMMU_LUT64H + GFXMMU LUT entry 64 high + 0x1204 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT65L + GFXMMU_LUT65L + GFXMMU LUT entry 65 low + 0x1208 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT65H + GFXMMU_LUT65H + GFXMMU LUT entry 65 high + 0x120c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT66L + GFXMMU_LUT66L + GFXMMU LUT entry 66 low + 0x1210 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT66H + GFXMMU_LUT66H + GFXMMU LUT entry 66 high + 0x1214 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT67L + GFXMMU_LUT67L + GFXMMU LUT entry 67 low + 0x1218 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT67H + GFXMMU_LUT67H + GFXMMU LUT entry 67 high + 0x121c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT68L + GFXMMU_LUT68L + GFXMMU LUT entry 68 low + 0x1220 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT68H + GFXMMU_LUT68H + GFXMMU LUT entry 68 high + 0x1224 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT69L + GFXMMU_LUT69L + GFXMMU LUT entry 69 low + 0x1228 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT69H + GFXMMU_LUT69H + GFXMMU LUT entry 69 high + 0x122c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT70L + GFXMMU_LUT70L + GFXMMU LUT entry 70 low + 0x1230 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT70H + GFXMMU_LUT70H + GFXMMU LUT entry 70 high + 0x1234 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT71L + GFXMMU_LUT71L + GFXMMU LUT entry 71 low + 0x1238 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT71H + GFXMMU_LUT71H + GFXMMU LUT entry 71 high + 0x123c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT72L + GFXMMU_LUT72L + GFXMMU LUT entry 72 low + 0x1240 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT72H + GFXMMU_LUT72H + GFXMMU LUT entry 72 high + 0x1244 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT73L + GFXMMU_LUT73L + GFXMMU LUT entry 73 low + 0x1248 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT73H + GFXMMU_LUT73H + GFXMMU LUT entry 73 high + 0x124c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT74L + GFXMMU_LUT74L + GFXMMU LUT entry 74 low + 0x1250 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT74H + GFXMMU_LUT74H + GFXMMU LUT entry 74 high + 0x1254 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT75L + GFXMMU_LUT75L + GFXMMU LUT entry 75 low + 0x1258 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT75H + GFXMMU_LUT75H + GFXMMU LUT entry 75 high + 0x125c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT76L + GFXMMU_LUT76L + GFXMMU LUT entry 76 low + 0x1260 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT76H + GFXMMU_LUT76H + GFXMMU LUT entry 76 high + 0x1264 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT77L + GFXMMU_LUT77L + GFXMMU LUT entry 77 low + 0x1268 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT77H + GFXMMU_LUT77H + GFXMMU LUT entry 77 high + 0x126c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT78L + GFXMMU_LUT78L + GFXMMU LUT entry 78 low + 0x1270 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT78H + GFXMMU_LUT78H + GFXMMU LUT entry 78 high + 0x1274 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT79L + GFXMMU_LUT79L + GFXMMU LUT entry 79 low + 0x1278 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT79H + GFXMMU_LUT79H + GFXMMU LUT entry 79 high + 0x127c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT80L + GFXMMU_LUT80L + GFXMMU LUT entry 80 low + 0x1280 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT80H + GFXMMU_LUT80H + GFXMMU LUT entry 80 high + 0x1284 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT81L + GFXMMU_LUT81L + GFXMMU LUT entry 81 low + 0x1288 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT81H + GFXMMU_LUT81H + GFXMMU LUT entry 81 high + 0x128c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT82L + GFXMMU_LUT82L + GFXMMU LUT entry 82 low + 0x1290 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT82H + GFXMMU_LUT82H + GFXMMU LUT entry 82 high + 0x1294 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT83L + GFXMMU_LUT83L + GFXMMU LUT entry 83 low + 0x1298 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT83H + GFXMMU_LUT83H + GFXMMU LUT entry 83 high + 0x129c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT84L + GFXMMU_LUT84L + GFXMMU LUT entry 84 low + 0x12a0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT84H + GFXMMU_LUT84H + GFXMMU LUT entry 84 high + 0x12a4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT85L + GFXMMU_LUT85L + GFXMMU LUT entry 85 low + 0x12a8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT85H + GFXMMU_LUT85H + GFXMMU LUT entry 85 high + 0x12ac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT86L + GFXMMU_LUT86L + GFXMMU LUT entry 86 low + 0x12b0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT86H + GFXMMU_LUT86H + GFXMMU LUT entry 86 high + 0x12b4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT87L + GFXMMU_LUT87L + GFXMMU LUT entry 87 low + 0x12b8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT87H + GFXMMU_LUT87H + GFXMMU LUT entry 87 high + 0x12bc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT88L + GFXMMU_LUT88L + GFXMMU LUT entry 88 low + 0x12c0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT88H + GFXMMU_LUT88H + GFXMMU LUT entry 88 high + 0x12c4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT89L + GFXMMU_LUT89L + GFXMMU LUT entry 89 low + 0x12c8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT89H + GFXMMU_LUT89H + GFXMMU LUT entry 89 high + 0x12cc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT90L + GFXMMU_LUT90L + GFXMMU LUT entry 90 low + 0x12d0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT90H + GFXMMU_LUT90H + GFXMMU LUT entry 90 high + 0x12d4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT91L + GFXMMU_LUT91L + GFXMMU LUT entry 91 low + 0x12d8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT91H + GFXMMU_LUT91H + GFXMMU LUT entry 91 high + 0x12dc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT92L + GFXMMU_LUT92L + GFXMMU LUT entry 92 low + 0x12e0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT92H + GFXMMU_LUT92H + GFXMMU LUT entry 92 high + 0x12e4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT93L + GFXMMU_LUT93L + GFXMMU LUT entry 93 low + 0x12e8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT93H + GFXMMU_LUT93H + GFXMMU LUT entry 93 high + 0x12ec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT94L + GFXMMU_LUT94L + GFXMMU LUT entry 94 low + 0x12f0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT94H + GFXMMU_LUT94H + GFXMMU LUT entry 94 high + 0x12f4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT95L + GFXMMU_LUT95L + GFXMMU LUT entry 95 low + 0x12f8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT95H + GFXMMU_LUT95H + GFXMMU LUT entry 95 high + 0x12fc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT96L + GFXMMU_LUT96L + GFXMMU LUT entry 96 low + 0x1300 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT96H + GFXMMU_LUT96H + GFXMMU LUT entry 96 high + 0x1304 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT97L + GFXMMU_LUT97L + GFXMMU LUT entry 97 low + 0x1308 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT97H + GFXMMU_LUT97H + GFXMMU LUT entry 97 high + 0x130c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT98L + GFXMMU_LUT98L + GFXMMU LUT entry 98 low + 0x1310 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT98H + GFXMMU_LUT98H + GFXMMU LUT entry 98 high + 0x1314 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT99L + GFXMMU_LUT99L + GFXMMU LUT entry 99 low + 0x1318 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT99H + GFXMMU_LUT99H + GFXMMU LUT entry 99 high + 0x131c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT100L + GFXMMU_LUT100L + GFXMMU LUT entry 100 low + 0x1320 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT100H + GFXMMU_LUT100H + GFXMMU LUT entry 100 high + 0x1324 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT101L + GFXMMU_LUT101L + GFXMMU LUT entry 101 low + 0x1328 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT101H + GFXMMU_LUT101H + GFXMMU LUT entry 101 high + 0x132c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT102L + GFXMMU_LUT102L + GFXMMU LUT entry 102 low + 0x1330 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT102H + GFXMMU_LUT102H + GFXMMU LUT entry 102 high + 0x1334 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT103L + GFXMMU_LUT103L + GFXMMU LUT entry 103 low + 0x1338 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT103H + GFXMMU_LUT103H + GFXMMU LUT entry 103 high + 0x133c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT104L + GFXMMU_LUT104L + GFXMMU LUT entry 104 low + 0x1340 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT104H + GFXMMU_LUT104H + GFXMMU LUT entry 104 high + 0x1344 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT105L + GFXMMU_LUT105L + GFXMMU LUT entry 105 low + 0x1348 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT105H + GFXMMU_LUT105H + GFXMMU LUT entry 105 high + 0x134c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT106L + GFXMMU_LUT106L + GFXMMU LUT entry 106 low + 0x1350 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT106H + GFXMMU_LUT106H + GFXMMU LUT entry 106 high + 0x1354 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT107L + GFXMMU_LUT107L + GFXMMU LUT entry 107 low + 0x1358 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT107H + GFXMMU_LUT107H + GFXMMU LUT entry 107 high + 0x135c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT108L + GFXMMU_LUT108L + GFXMMU LUT entry 108 low + 0x1360 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT108H + GFXMMU_LUT108H + GFXMMU LUT entry 108 high + 0x1364 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT109L + GFXMMU_LUT109L + GFXMMU LUT entry 109 low + 0x1368 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT109H + GFXMMU_LUT109H + GFXMMU LUT entry 109 high + 0x136c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT110L + GFXMMU_LUT110L + GFXMMU LUT entry 110 low + 0x1370 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT110H + GFXMMU_LUT110H + GFXMMU LUT entry 110 high + 0x1374 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT111L + GFXMMU_LUT111L + GFXMMU LUT entry 111 low + 0x1378 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT111H + GFXMMU_LUT111H + GFXMMU LUT entry 111 high + 0x137c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT112L + GFXMMU_LUT112L + GFXMMU LUT entry 112 low + 0x1380 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT112H + GFXMMU_LUT112H + GFXMMU LUT entry 112 high + 0x1384 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT113L + GFXMMU_LUT113L + GFXMMU LUT entry 113 low + 0x1388 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT113H + GFXMMU_LUT113H + GFXMMU LUT entry 113 high + 0x138c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT114L + GFXMMU_LUT114L + GFXMMU LUT entry 114 low + 0x1390 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT114H + GFXMMU_LUT114H + GFXMMU LUT entry 114 high + 0x1394 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT115L + GFXMMU_LUT115L + GFXMMU LUT entry 115 low + 0x1398 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT115H + GFXMMU_LUT115H + GFXMMU LUT entry 115 high + 0x139c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT116L + GFXMMU_LUT116L + GFXMMU LUT entry 116 low + 0x13a0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT116H + GFXMMU_LUT116H + GFXMMU LUT entry 116 high + 0x13a4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT117L + GFXMMU_LUT117L + GFXMMU LUT entry 117 low + 0x13a8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT117H + GFXMMU_LUT117H + GFXMMU LUT entry 117 high + 0x13ac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT118L + GFXMMU_LUT118L + GFXMMU LUT entry 118 low + 0x13b0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT118H + GFXMMU_LUT118H + GFXMMU LUT entry 118 high + 0x13b4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT119L + GFXMMU_LUT119L + GFXMMU LUT entry 119 low + 0x13b8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT119H + GFXMMU_LUT119H + GFXMMU LUT entry 119 high + 0x13bc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT120L + GFXMMU_LUT120L + GFXMMU LUT entry 120 low + 0x13c0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT120H + GFXMMU_LUT120H + GFXMMU LUT entry 120 high + 0x13c4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT121L + GFXMMU_LUT121L + GFXMMU LUT entry 121 low + 0x13c8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT121H + GFXMMU_LUT121H + GFXMMU LUT entry 121 high + 0x13cc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT122L + GFXMMU_LUT122L + GFXMMU LUT entry 122 low + 0x13d0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT122H + GFXMMU_LUT122H + GFXMMU LUT entry 122 high + 0x13d4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT123L + GFXMMU_LUT123L + GFXMMU LUT entry 123 low + 0x13d8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT123H + GFXMMU_LUT123H + GFXMMU LUT entry 123 high + 0x13dc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT124L + GFXMMU_LUT124L + GFXMMU LUT entry 124 low + 0x13e0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT124H + GFXMMU_LUT124H + GFXMMU LUT entry 124 high + 0x13e4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT125L + GFXMMU_LUT125L + GFXMMU LUT entry 125 low + 0x13e8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT125H + GFXMMU_LUT125H + GFXMMU LUT entry 125 high + 0x13ec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT126L + GFXMMU_LUT126L + GFXMMU LUT entry 126 low + 0x13f0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT126H + GFXMMU_LUT126H + GFXMMU LUT entry 126 high + 0x13f4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT127L + GFXMMU_LUT127L + GFXMMU LUT entry 127 low + 0x13f8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT127H + GFXMMU_LUT127H + GFXMMU LUT entry 127 high + 0x13fc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT128L + GFXMMU_LUT128L + GFXMMU LUT entry 128 low + 0x1400 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT128H + GFXMMU_LUT128H + GFXMMU LUT entry 128 high + 0x1404 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT129L + GFXMMU_LUT129L + GFXMMU LUT entry 129 low + 0x1408 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT129H + GFXMMU_LUT129H + GFXMMU LUT entry 129 high + 0x140c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT130L + GFXMMU_LUT130L + GFXMMU LUT entry 130 low + 0x1410 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT130H + GFXMMU_LUT130H + GFXMMU LUT entry 130 high + 0x1414 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT131L + GFXMMU_LUT131L + GFXMMU LUT entry 131 low + 0x1418 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT131H + GFXMMU_LUT131H + GFXMMU LUT entry 131 high + 0x141c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT132L + GFXMMU_LUT132L + GFXMMU LUT entry 132 low + 0x1420 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT132H + GFXMMU_LUT132H + GFXMMU LUT entry 132 high + 0x1424 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT133L + GFXMMU_LUT133L + GFXMMU LUT entry 133 low + 0x1428 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT133H + GFXMMU_LUT133H + GFXMMU LUT entry 133 high + 0x142c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT134L + GFXMMU_LUT134L + GFXMMU LUT entry 134 low + 0x1430 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT134H + GFXMMU_LUT134H + GFXMMU LUT entry 134 high + 0x1434 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT135L + GFXMMU_LUT135L + GFXMMU LUT entry 135 low + 0x1438 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT135H + GFXMMU_LUT135H + GFXMMU LUT entry 135 high + 0x143c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT136L + GFXMMU_LUT136L + GFXMMU LUT entry 136 low + 0x1440 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT136H + GFXMMU_LUT136H + GFXMMU LUT entry 136 high + 0x1444 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT137L + GFXMMU_LUT137L + GFXMMU LUT entry 137 low + 0x1448 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT137H + GFXMMU_LUT137H + GFXMMU LUT entry 137 high + 0x144c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT138L + GFXMMU_LUT138L + GFXMMU LUT entry 138 low + 0x1450 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT138H + GFXMMU_LUT138H + GFXMMU LUT entry 138 high + 0x1454 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT139L + GFXMMU_LUT139L + GFXMMU LUT entry 139 low + 0x1458 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT139H + GFXMMU_LUT139H + GFXMMU LUT entry 139 high + 0x145c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT140L + GFXMMU_LUT140L + GFXMMU LUT entry 140 low + 0x1460 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT140H + GFXMMU_LUT140H + GFXMMU LUT entry 140 high + 0x1464 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT141L + GFXMMU_LUT141L + GFXMMU LUT entry 141 low + 0x1468 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT141H + GFXMMU_LUT141H + GFXMMU LUT entry 141 high + 0x146c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT142L + GFXMMU_LUT142L + GFXMMU LUT entry 142 low + 0x1470 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT142H + GFXMMU_LUT142H + GFXMMU LUT entry 142 high + 0x1474 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT143L + GFXMMU_LUT143L + GFXMMU LUT entry 143 low + 0x1478 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT143H + GFXMMU_LUT143H + GFXMMU LUT entry 143 high + 0x147c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT144L + GFXMMU_LUT144L + GFXMMU LUT entry 144 low + 0x1480 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT144H + GFXMMU_LUT144H + GFXMMU LUT entry 144 high + 0x1484 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT145L + GFXMMU_LUT145L + GFXMMU LUT entry 145 low + 0x1488 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT145H + GFXMMU_LUT145H + GFXMMU LUT entry 145 high + 0x148c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT146L + GFXMMU_LUT146L + GFXMMU LUT entry 146 low + 0x1490 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT146H + GFXMMU_LUT146H + GFXMMU LUT entry 146 high + 0x1494 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT147L + GFXMMU_LUT147L + GFXMMU LUT entry 147 low + 0x1498 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT147H + GFXMMU_LUT147H + GFXMMU LUT entry 147 high + 0x149c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT148L + GFXMMU_LUT148L + GFXMMU LUT entry 148 low + 0x14a0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT148H + GFXMMU_LUT148H + GFXMMU LUT entry 148 high + 0x14a4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT149L + GFXMMU_LUT149L + GFXMMU LUT entry 149 low + 0x14a8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT149H + GFXMMU_LUT149H + GFXMMU LUT entry 149 high + 0x14ac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT150L + GFXMMU_LUT150L + GFXMMU LUT entry 150 low + 0x14b0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT150H + GFXMMU_LUT150H + GFXMMU LUT entry 150 high + 0x14b4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT151L + GFXMMU_LUT151L + GFXMMU LUT entry 151 low + 0x14b8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT151H + GFXMMU_LUT151H + GFXMMU LUT entry 151 high + 0x14bc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT152L + GFXMMU_LUT152L + GFXMMU LUT entry 152 low + 0x14c0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT152H + GFXMMU_LUT152H + GFXMMU LUT entry 152 high + 0x14c4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT153L + GFXMMU_LUT153L + GFXMMU LUT entry 153 low + 0x14c8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT153H + GFXMMU_LUT153H + GFXMMU LUT entry 153 high + 0x14cc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT154L + GFXMMU_LUT154L + GFXMMU LUT entry 154 low + 0x14d0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT154H + GFXMMU_LUT154H + GFXMMU LUT entry 154 high + 0x14d4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT155L + GFXMMU_LUT155L + GFXMMU LUT entry 155 low + 0x14d8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT155H + GFXMMU_LUT155H + GFXMMU LUT entry 155 high + 0x14dc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT156L + GFXMMU_LUT156L + GFXMMU LUT entry 156 low + 0x14e0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT156H + GFXMMU_LUT156H + GFXMMU LUT entry 156 high + 0x14e4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT157L + GFXMMU_LUT157L + GFXMMU LUT entry 157 low + 0x14e8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT157H + GFXMMU_LUT157H + GFXMMU LUT entry 157 high + 0x14ec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT158L + GFXMMU_LUT158L + GFXMMU LUT entry 158 low + 0x14f0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT158H + GFXMMU_LUT158H + GFXMMU LUT entry 158 high + 0x14f4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT159L + GFXMMU_LUT159L + GFXMMU LUT entry 159 low + 0x14f8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT159H + GFXMMU_LUT159H + GFXMMU LUT entry 159 high + 0x14fc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT160L + GFXMMU_LUT160L + GFXMMU LUT entry 160 low + 0x1500 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT160H + GFXMMU_LUT160H + GFXMMU LUT entry 160 high + 0x1504 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT161L + GFXMMU_LUT161L + GFXMMU LUT entry 161 low + 0x1508 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT161H + GFXMMU_LUT161H + GFXMMU LUT entry 161 high + 0x150c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT162L + GFXMMU_LUT162L + GFXMMU LUT entry 162 low + 0x1510 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT162H + GFXMMU_LUT162H + GFXMMU LUT entry 162 high + 0x1514 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT163L + GFXMMU_LUT163L + GFXMMU LUT entry 163 low + 0x1518 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT163H + GFXMMU_LUT163H + GFXMMU LUT entry 163 high + 0x151c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT164L + GFXMMU_LUT164L + GFXMMU LUT entry 164 low + 0x1520 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT164H + GFXMMU_LUT164H + GFXMMU LUT entry 164 high + 0x1524 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT165L + GFXMMU_LUT165L + GFXMMU LUT entry 165 low + 0x1528 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT165H + GFXMMU_LUT165H + GFXMMU LUT entry 165 high + 0x152c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT166L + GFXMMU_LUT166L + GFXMMU LUT entry 166 low + 0x1530 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT166H + GFXMMU_LUT166H + GFXMMU LUT entry 166 high + 0x1534 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT167L + GFXMMU_LUT167L + GFXMMU LUT entry 167 low + 0x1538 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT167H + GFXMMU_LUT167H + GFXMMU LUT entry 167 high + 0x153c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT168L + GFXMMU_LUT168L + GFXMMU LUT entry 168 low + 0x1540 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT168H + GFXMMU_LUT168H + GFXMMU LUT entry 168 high + 0x1544 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT169L + GFXMMU_LUT169L + GFXMMU LUT entry 169 low + 0x1548 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT169H + GFXMMU_LUT169H + GFXMMU LUT entry 169 high + 0x154c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT170L + GFXMMU_LUT170L + GFXMMU LUT entry 170 low + 0x1550 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT170H + GFXMMU_LUT170H + GFXMMU LUT entry 170 high + 0x1554 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT171L + GFXMMU_LUT171L + GFXMMU LUT entry 171 low + 0x1558 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT171H + GFXMMU_LUT171H + GFXMMU LUT entry 171 high + 0x155c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT172L + GFXMMU_LUT172L + GFXMMU LUT entry 172 low + 0x1560 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT172H + GFXMMU_LUT172H + GFXMMU LUT entry 172 high + 0x1564 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT173L + GFXMMU_LUT173L + GFXMMU LUT entry 173 low + 0x1568 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT173H + GFXMMU_LUT173H + GFXMMU LUT entry 173 high + 0x156c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT174L + GFXMMU_LUT174L + GFXMMU LUT entry 174 low + 0x1570 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT174H + GFXMMU_LUT174H + GFXMMU LUT entry 174 high + 0x1574 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT175L + GFXMMU_LUT175L + GFXMMU LUT entry 175 low + 0x1578 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT175H + GFXMMU_LUT175H + GFXMMU LUT entry 175 high + 0x157c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT176L + GFXMMU_LUT176L + GFXMMU LUT entry 176 low + 0x1580 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT176H + GFXMMU_LUT176H + GFXMMU LUT entry 176 high + 0x1584 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT177L + GFXMMU_LUT177L + GFXMMU LUT entry 177 low + 0x1588 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT177H + GFXMMU_LUT177H + GFXMMU LUT entry 177 high + 0x158c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT178L + GFXMMU_LUT178L + GFXMMU LUT entry 178 low + 0x1590 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT178H + GFXMMU_LUT178H + GFXMMU LUT entry 178 high + 0x1594 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT179L + GFXMMU_LUT179L + GFXMMU LUT entry 179 low + 0x1598 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT179H + GFXMMU_LUT179H + GFXMMU LUT entry 179 high + 0x159c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT180L + GFXMMU_LUT180L + GFXMMU LUT entry 180 low + 0x15a0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT180H + GFXMMU_LUT180H + GFXMMU LUT entry 180 high + 0x15a4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT181L + GFXMMU_LUT181L + GFXMMU LUT entry 181 low + 0x15a8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT181H + GFXMMU_LUT181H + GFXMMU LUT entry 181 high + 0x15ac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT182L + GFXMMU_LUT182L + GFXMMU LUT entry 182 low + 0x15b0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT182H + GFXMMU_LUT182H + GFXMMU LUT entry 182 high + 0x15b4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT183L + GFXMMU_LUT183L + GFXMMU LUT entry 183 low + 0x15b8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT183H + GFXMMU_LUT183H + GFXMMU LUT entry 183 high + 0x15bc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT184L + GFXMMU_LUT184L + GFXMMU LUT entry 184 low + 0x15c0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT184H + GFXMMU_LUT184H + GFXMMU LUT entry 184 high + 0x15c4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT185L + GFXMMU_LUT185L + GFXMMU LUT entry 185 low + 0x15c8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT185H + GFXMMU_LUT185H + GFXMMU LUT entry 185 high + 0x15cc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT186L + GFXMMU_LUT186L + GFXMMU LUT entry 186 low + 0x15d0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT186H + GFXMMU_LUT186H + GFXMMU LUT entry 186 high + 0x15d4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT187L + GFXMMU_LUT187L + GFXMMU LUT entry 187 low + 0x15d8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT187H + GFXMMU_LUT187H + GFXMMU LUT entry 187 high + 0x15dc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT188L + GFXMMU_LUT188L + GFXMMU LUT entry 188 low + 0x15e0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT188H + GFXMMU_LUT188H + GFXMMU LUT entry 188 high + 0x15e4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT189L + GFXMMU_LUT189L + GFXMMU LUT entry 189 low + 0x15e8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT189H + GFXMMU_LUT189H + GFXMMU LUT entry 189 high + 0x15ec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT190L + GFXMMU_LUT190L + GFXMMU LUT entry 190 low + 0x15f0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT190H + GFXMMU_LUT190H + GFXMMU LUT entry 190 high + 0x15f4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT191L + GFXMMU_LUT191L + GFXMMU LUT entry 191 low + 0x15f8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT191H + GFXMMU_LUT191H + GFXMMU LUT entry 191 high + 0x15fc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT192L + GFXMMU_LUT192L + GFXMMU LUT entry 192 low + 0x1600 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT192H + GFXMMU_LUT192H + GFXMMU LUT entry 192 high + 0x1604 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT193L + GFXMMU_LUT193L + GFXMMU LUT entry 193 low + 0x1608 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT193H + GFXMMU_LUT193H + GFXMMU LUT entry 193 high + 0x160c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT194L + GFXMMU_LUT194L + GFXMMU LUT entry 194 low + 0x1610 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT194H + GFXMMU_LUT194H + GFXMMU LUT entry 194 high + 0x1614 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT195L + GFXMMU_LUT195L + GFXMMU LUT entry 195 low + 0x1618 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT195H + GFXMMU_LUT195H + GFXMMU LUT entry 195 high + 0x161c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT196L + GFXMMU_LUT196L + GFXMMU LUT entry 196 low + 0x1620 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT196H + GFXMMU_LUT196H + GFXMMU LUT entry 196 high + 0x1624 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT197L + GFXMMU_LUT197L + GFXMMU LUT entry 197 low + 0x1628 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT197H + GFXMMU_LUT197H + GFXMMU LUT entry 197 high + 0x162c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT198L + GFXMMU_LUT198L + GFXMMU LUT entry 198 low + 0x1630 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT198H + GFXMMU_LUT198H + GFXMMU LUT entry 198 high + 0x1634 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT199L + GFXMMU_LUT199L + GFXMMU LUT entry 199 low + 0x1638 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT199H + GFXMMU_LUT199H + GFXMMU LUT entry 199 high + 0x163c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT200L + GFXMMU_LUT200L + GFXMMU LUT entry 200 low + 0x1640 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT200H + GFXMMU_LUT200H + GFXMMU LUT entry 200 high + 0x1644 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT201L + GFXMMU_LUT201L + GFXMMU LUT entry 201 low + 0x1648 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT201H + GFXMMU_LUT201H + GFXMMU LUT entry 201 high + 0x164c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT202L + GFXMMU_LUT202L + GFXMMU LUT entry 202 low + 0x1650 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT202H + GFXMMU_LUT202H + GFXMMU LUT entry 202 high + 0x1654 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT203L + GFXMMU_LUT203L + GFXMMU LUT entry 203 low + 0x1658 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT203H + GFXMMU_LUT203H + GFXMMU LUT entry 203 high + 0x165c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT204L + GFXMMU_LUT204L + GFXMMU LUT entry 204 low + 0x1660 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT204H + GFXMMU_LUT204H + GFXMMU LUT entry 204 high + 0x1664 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT205L + GFXMMU_LUT205L + GFXMMU LUT entry 205 low + 0x1668 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT205H + GFXMMU_LUT205H + GFXMMU LUT entry 205 high + 0x166c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT206L + GFXMMU_LUT206L + GFXMMU LUT entry 206 low + 0x1670 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT206H + GFXMMU_LUT206H + GFXMMU LUT entry 206 high + 0x1674 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT207L + GFXMMU_LUT207L + GFXMMU LUT entry 207 low + 0x1678 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT207H + GFXMMU_LUT207H + GFXMMU LUT entry 207 high + 0x167c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT208L + GFXMMU_LUT208L + GFXMMU LUT entry 208 low + 0x1680 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT208H + GFXMMU_LUT208H + GFXMMU LUT entry 208 high + 0x1684 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT209L + GFXMMU_LUT209L + GFXMMU LUT entry 209 low + 0x1688 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT209H + GFXMMU_LUT209H + GFXMMU LUT entry 209 high + 0x168c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT210L + GFXMMU_LUT210L + GFXMMU LUT entry 210 low + 0x1690 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT210H + GFXMMU_LUT210H + GFXMMU LUT entry 210 high + 0x1694 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT211L + GFXMMU_LUT211L + GFXMMU LUT entry 211 low + 0x1698 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT211H + GFXMMU_LUT211H + GFXMMU LUT entry 211 high + 0x169c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT212L + GFXMMU_LUT212L + GFXMMU LUT entry 212 low + 0x16a0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT212H + GFXMMU_LUT212H + GFXMMU LUT entry 212 high + 0x16a4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT213L + GFXMMU_LUT213L + GFXMMU LUT entry 213 low + 0x16a8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT213H + GFXMMU_LUT213H + GFXMMU LUT entry 213 high + 0x16ac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT214L + GFXMMU_LUT214L + GFXMMU LUT entry 214 low + 0x16b0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT214H + GFXMMU_LUT214H + GFXMMU LUT entry 214 high + 0x16b4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT215L + GFXMMU_LUT215L + GFXMMU LUT entry 215 low + 0x16b8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT215H + GFXMMU_LUT215H + GFXMMU LUT entry 215 high + 0x16bc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT216L + GFXMMU_LUT216L + GFXMMU LUT entry 216 low + 0x16c0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT216H + GFXMMU_LUT216H + GFXMMU LUT entry 216 high + 0x16c4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT217L + GFXMMU_LUT217L + GFXMMU LUT entry 217 low + 0x16c8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT217H + GFXMMU_LUT217H + GFXMMU LUT entry 217 high + 0x16cc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT218L + GFXMMU_LUT218L + GFXMMU LUT entry 218 low + 0x16d0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT218H + GFXMMU_LUT218H + GFXMMU LUT entry 218 high + 0x16d4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT219L + GFXMMU_LUT219L + GFXMMU LUT entry 219 low + 0x16d8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT219H + GFXMMU_LUT219H + GFXMMU LUT entry 219 high + 0x16dc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT220L + GFXMMU_LUT220L + GFXMMU LUT entry 220 low + 0x16e0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT220H + GFXMMU_LUT220H + GFXMMU LUT entry 220 high + 0x16e4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT221L + GFXMMU_LUT221L + GFXMMU LUT entry 221 low + 0x16e8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT221H + GFXMMU_LUT221H + GFXMMU LUT entry 221 high + 0x16ec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT222L + GFXMMU_LUT222L + GFXMMU LUT entry 222 low + 0x16f0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT222H + GFXMMU_LUT222H + GFXMMU LUT entry 222 high + 0x16f4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT223L + GFXMMU_LUT223L + GFXMMU LUT entry 223 low + 0x16f8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT223H + GFXMMU_LUT223H + GFXMMU LUT entry 223 high + 0x16fc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT224L + GFXMMU_LUT224L + GFXMMU LUT entry 224 low + 0x1700 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT224H + GFXMMU_LUT224H + GFXMMU LUT entry 224 high + 0x1704 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT225L + GFXMMU_LUT225L + GFXMMU LUT entry 225 low + 0x1708 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT225H + GFXMMU_LUT225H + GFXMMU LUT entry 225 high + 0x170c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT226L + GFXMMU_LUT226L + GFXMMU LUT entry 226 low + 0x1710 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT226H + GFXMMU_LUT226H + GFXMMU LUT entry 226 high + 0x1714 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT227L + GFXMMU_LUT227L + GFXMMU LUT entry 227 low + 0x1718 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT227H + GFXMMU_LUT227H + GFXMMU LUT entry 227 high + 0x171c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT228L + GFXMMU_LUT228L + GFXMMU LUT entry 228 low + 0x1720 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT228H + GFXMMU_LUT228H + GFXMMU LUT entry 228 high + 0x1724 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT229L + GFXMMU_LUT229L + GFXMMU LUT entry 229 low + 0x1728 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT229H + GFXMMU_LUT229H + GFXMMU LUT entry 229 high + 0x172c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT230L + GFXMMU_LUT230L + GFXMMU LUT entry 230 low + 0x1730 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT230H + GFXMMU_LUT230H + GFXMMU LUT entry 230 high + 0x1734 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT231L + GFXMMU_LUT231L + GFXMMU LUT entry 231 low + 0x1738 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT231H + GFXMMU_LUT231H + GFXMMU LUT entry 231 high + 0x173c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT232L + GFXMMU_LUT232L + GFXMMU LUT entry 232 low + 0x1740 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT232H + GFXMMU_LUT232H + GFXMMU LUT entry 232 high + 0x1744 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT233L + GFXMMU_LUT233L + GFXMMU LUT entry 233 low + 0x1748 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT233H + GFXMMU_LUT233H + GFXMMU LUT entry 233 high + 0x174c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT234L + GFXMMU_LUT234L + GFXMMU LUT entry 234 low + 0x1750 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT234H + GFXMMU_LUT234H + GFXMMU LUT entry 234 high + 0x1754 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT235L + GFXMMU_LUT235L + GFXMMU LUT entry 235 low + 0x1758 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT235H + GFXMMU_LUT235H + GFXMMU LUT entry 235 high + 0x175c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT236L + GFXMMU_LUT236L + GFXMMU LUT entry 236 low + 0x1760 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT236H + GFXMMU_LUT236H + GFXMMU LUT entry 236 high + 0x1764 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT237L + GFXMMU_LUT237L + GFXMMU LUT entry 237 low + 0x1768 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT237H + GFXMMU_LUT237H + GFXMMU LUT entry 237 high + 0x176c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT238L + GFXMMU_LUT238L + GFXMMU LUT entry 238 low + 0x1770 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT238H + GFXMMU_LUT238H + GFXMMU LUT entry 238 high + 0x1774 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT239L + GFXMMU_LUT239L + GFXMMU LUT entry 239 low + 0x1778 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT239H + GFXMMU_LUT239H + GFXMMU LUT entry 239 high + 0x177c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT240L + GFXMMU_LUT240L + GFXMMU LUT entry 240 low + 0x1780 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT240H + GFXMMU_LUT240H + GFXMMU LUT entry 240 high + 0x1784 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT241L + GFXMMU_LUT241L + GFXMMU LUT entry 241 low + 0x1788 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT241H + GFXMMU_LUT241H + GFXMMU LUT entry 241 high + 0x178c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT242L + GFXMMU_LUT242L + GFXMMU LUT entry 242 low + 0x1790 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT242H + GFXMMU_LUT242H + GFXMMU LUT entry 242 high + 0x1794 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT243L + GFXMMU_LUT243L + GFXMMU LUT entry 243 low + 0x1798 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT243H + GFXMMU_LUT243H + GFXMMU LUT entry 243 high + 0x179c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT244L + GFXMMU_LUT244L + GFXMMU LUT entry 244 low + 0x17a0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT244H + GFXMMU_LUT244H + GFXMMU LUT entry 244 high + 0x17a4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT245L + GFXMMU_LUT245L + GFXMMU LUT entry 245 low + 0x17a8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT245H + GFXMMU_LUT245H + GFXMMU LUT entry 245 high + 0x17ac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT246L + GFXMMU_LUT246L + GFXMMU LUT entry 246 low + 0x17b0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT246H + GFXMMU_LUT246H + GFXMMU LUT entry 246 high + 0x17b4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT247L + GFXMMU_LUT247L + GFXMMU LUT entry 247 low + 0x17b8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT247H + GFXMMU_LUT247H + GFXMMU LUT entry 247 high + 0x17bc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT248L + GFXMMU_LUT248L + GFXMMU LUT entry 248 low + 0x17c0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT248H + GFXMMU_LUT248H + GFXMMU LUT entry 248 high + 0x17c4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT249L + GFXMMU_LUT249L + GFXMMU LUT entry 249 low + 0x17c8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT249H + GFXMMU_LUT249H + GFXMMU LUT entry 249 high + 0x17cc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT250L + GFXMMU_LUT250L + GFXMMU LUT entry 250 low + 0x17d0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT250H + GFXMMU_LUT250H + GFXMMU LUT entry 250 high + 0x17d4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT251L + GFXMMU_LUT251L + GFXMMU LUT entry 251 low + 0x17d8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT251H + GFXMMU_LUT251H + GFXMMU LUT entry 251 high + 0x17dc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT252L + GFXMMU_LUT252L + GFXMMU LUT entry 252 low + 0x17e0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT252H + GFXMMU_LUT252H + GFXMMU LUT entry 252 high + 0x17e4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT253L + GFXMMU_LUT253L + GFXMMU LUT entry 253 low + 0x17e8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT253H + GFXMMU_LUT253H + GFXMMU LUT entry 253 high + 0x17ec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT254L + GFXMMU_LUT254L + GFXMMU LUT entry 254 low + 0x17f0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT254H + GFXMMU_LUT254H + GFXMMU LUT entry 254 high + 0x17f4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT255L + GFXMMU_LUT255L + GFXMMU LUT entry 255 low + 0x17f8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT255H + GFXMMU_LUT255H + GFXMMU LUT entry 255 high + 0x17fc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT256L + GFXMMU_LUT256L + GFXMMU LUT entry 256 low + 0x1800 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT256H + GFXMMU_LUT256H + GFXMMU LUT entry 256 high + 0x1804 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT257L + GFXMMU_LUT257L + GFXMMU LUT entry 257 low + 0x1808 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT257H + GFXMMU_LUT257H + GFXMMU LUT entry 257 high + 0x180c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT258L + GFXMMU_LUT258L + GFXMMU LUT entry 258 low + 0x1810 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT258H + GFXMMU_LUT258H + GFXMMU LUT entry 258 high + 0x1814 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT259L + GFXMMU_LUT259L + GFXMMU LUT entry 259 low + 0x1818 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT259H + GFXMMU_LUT259H + GFXMMU LUT entry 259 high + 0x181c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT260L + GFXMMU_LUT260L + GFXMMU LUT entry 260 low + 0x1820 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT260H + GFXMMU_LUT260H + GFXMMU LUT entry 260 high + 0x1824 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT261L + GFXMMU_LUT261L + GFXMMU LUT entry 261 low + 0x1828 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT261H + GFXMMU_LUT261H + GFXMMU LUT entry 261 high + 0x182c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT262L + GFXMMU_LUT262L + GFXMMU LUT entry 262 low + 0x1830 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT262H + GFXMMU_LUT262H + GFXMMU LUT entry 262 high + 0x1834 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT263L + GFXMMU_LUT263L + GFXMMU LUT entry 263 low + 0x1838 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT263H + GFXMMU_LUT263H + GFXMMU LUT entry 263 high + 0x183c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT264L + GFXMMU_LUT264L + GFXMMU LUT entry 264 low + 0x1840 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT264H + GFXMMU_LUT264H + GFXMMU LUT entry 264 high + 0x1844 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT265L + GFXMMU_LUT265L + GFXMMU LUT entry 265 low + 0x1848 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT265H + GFXMMU_LUT265H + GFXMMU LUT entry 265 high + 0x184c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT266L + GFXMMU_LUT266L + GFXMMU LUT entry 266 low + 0x1850 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT266H + GFXMMU_LUT266H + GFXMMU LUT entry 266 high + 0x1854 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT267L + GFXMMU_LUT267L + GFXMMU LUT entry 267 low + 0x1858 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT267H + GFXMMU_LUT267H + GFXMMU LUT entry 267 high + 0x185c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT268L + GFXMMU_LUT268L + GFXMMU LUT entry 268 low + 0x1860 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT268H + GFXMMU_LUT268H + GFXMMU LUT entry 268 high + 0x1864 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT269L + GFXMMU_LUT269L + GFXMMU LUT entry 269 low + 0x1868 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT269H + GFXMMU_LUT269H + GFXMMU LUT entry 269 high + 0x186c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT270L + GFXMMU_LUT270L + GFXMMU LUT entry 270 low + 0x1870 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT270H + GFXMMU_LUT270H + GFXMMU LUT entry 270 high + 0x1874 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT271L + GFXMMU_LUT271L + GFXMMU LUT entry 271 low + 0x1878 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT271H + GFXMMU_LUT271H + GFXMMU LUT entry 271 high + 0x187c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT272L + GFXMMU_LUT272L + GFXMMU LUT entry 272 low + 0x1880 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT272H + GFXMMU_LUT272H + GFXMMU LUT entry 272 high + 0x1884 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT273L + GFXMMU_LUT273L + GFXMMU LUT entry 273 low + 0x1888 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT273H + GFXMMU_LUT273H + GFXMMU LUT entry 273 high + 0x188c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT274L + GFXMMU_LUT274L + GFXMMU LUT entry 274 low + 0x1890 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT274H + GFXMMU_LUT274H + GFXMMU LUT entry 274 high + 0x1894 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT275L + GFXMMU_LUT275L + GFXMMU LUT entry 275 low + 0x1898 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT275H + GFXMMU_LUT275H + GFXMMU LUT entry 275 high + 0x189c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT276L + GFXMMU_LUT276L + GFXMMU LUT entry 276 low + 0x18a0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT276H + GFXMMU_LUT276H + GFXMMU LUT entry 276 high + 0x18a4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT277L + GFXMMU_LUT277L + GFXMMU LUT entry 277 low + 0x18a8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT277H + GFXMMU_LUT277H + GFXMMU LUT entry 277 high + 0x18ac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT278L + GFXMMU_LUT278L + GFXMMU LUT entry 278 low + 0x18b0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT278H + GFXMMU_LUT278H + GFXMMU LUT entry 278 high + 0x18b4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT279L + GFXMMU_LUT279L + GFXMMU LUT entry 279 low + 0x18b8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT279H + GFXMMU_LUT279H + GFXMMU LUT entry 279 high + 0x18bc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT280L + GFXMMU_LUT280L + GFXMMU LUT entry 280 low + 0x18c0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT280H + GFXMMU_LUT280H + GFXMMU LUT entry 280 high + 0x18c4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT281L + GFXMMU_LUT281L + GFXMMU LUT entry 281 low + 0x18c8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT281H + GFXMMU_LUT281H + GFXMMU LUT entry 281 high + 0x18cc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT282L + GFXMMU_LUT282L + GFXMMU LUT entry 282 low + 0x18d0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT282H + GFXMMU_LUT282H + GFXMMU LUT entry 282 high + 0x18d4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT283L + GFXMMU_LUT283L + GFXMMU LUT entry 283 low + 0x18d8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT283H + GFXMMU_LUT283H + GFXMMU LUT entry 283 high + 0x18dc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT284L + GFXMMU_LUT284L + GFXMMU LUT entry 284 low + 0x18e0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT284H + GFXMMU_LUT284H + GFXMMU LUT entry 284 high + 0x18e4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT285L + GFXMMU_LUT285L + GFXMMU LUT entry 285 low + 0x18e8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT285H + GFXMMU_LUT285H + GFXMMU LUT entry 285 high + 0x18ec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT286L + GFXMMU_LUT286L + GFXMMU LUT entry 286 low + 0x18f0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT286H + GFXMMU_LUT286H + GFXMMU LUT entry 286 high + 0x18f4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT287L + GFXMMU_LUT287L + GFXMMU LUT entry 287 low + 0x18f8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT287H + GFXMMU_LUT287H + GFXMMU LUT entry 287 high + 0x18fc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT288L + GFXMMU_LUT288L + GFXMMU LUT entry 288 low + 0x1900 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT288H + GFXMMU_LUT288H + GFXMMU LUT entry 288 high + 0x1904 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT289L + GFXMMU_LUT289L + GFXMMU LUT entry 289 low + 0x1908 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT289H + GFXMMU_LUT289H + GFXMMU LUT entry 289 high + 0x190c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT290L + GFXMMU_LUT290L + GFXMMU LUT entry 290 low + 0x1910 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT290H + GFXMMU_LUT290H + GFXMMU LUT entry 290 high + 0x1914 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT291L + GFXMMU_LUT291L + GFXMMU LUT entry 291 low + 0x1918 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT291H + GFXMMU_LUT291H + GFXMMU LUT entry 291 high + 0x191c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT292L + GFXMMU_LUT292L + GFXMMU LUT entry 292 low + 0x1920 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT292H + GFXMMU_LUT292H + GFXMMU LUT entry 292 high + 0x1924 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT293L + GFXMMU_LUT293L + GFXMMU LUT entry 293 low + 0x1928 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT293H + GFXMMU_LUT293H + GFXMMU LUT entry 293 high + 0x192c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT294L + GFXMMU_LUT294L + GFXMMU LUT entry 294 low + 0x1930 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT294H + GFXMMU_LUT294H + GFXMMU LUT entry 294 high + 0x1934 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT295L + GFXMMU_LUT295L + GFXMMU LUT entry 295 low + 0x1938 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT295H + GFXMMU_LUT295H + GFXMMU LUT entry 295 high + 0x193c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT296L + GFXMMU_LUT296L + GFXMMU LUT entry 296 low + 0x1940 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT296H + GFXMMU_LUT296H + GFXMMU LUT entry 296 high + 0x1944 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT297L + GFXMMU_LUT297L + GFXMMU LUT entry 297 low + 0x1948 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT297H + GFXMMU_LUT297H + GFXMMU LUT entry 297 high + 0x194c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT298L + GFXMMU_LUT298L + GFXMMU LUT entry 298 low + 0x1950 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT298H + GFXMMU_LUT298H + GFXMMU LUT entry 298 high + 0x1954 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT299L + GFXMMU_LUT299L + GFXMMU LUT entry 299 low + 0x1958 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT299H + GFXMMU_LUT299H + GFXMMU LUT entry 299 high + 0x195c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT300L + GFXMMU_LUT300L + GFXMMU LUT entry 300 low + 0x1960 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT300H + GFXMMU_LUT300H + GFXMMU LUT entry 300 high + 0x1964 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT301L + GFXMMU_LUT301L + GFXMMU LUT entry 301 low + 0x1968 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT301H + GFXMMU_LUT301H + GFXMMU LUT entry 301 high + 0x196c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT302L + GFXMMU_LUT302L + GFXMMU LUT entry 302 low + 0x1970 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT302H + GFXMMU_LUT302H + GFXMMU LUT entry 302 high + 0x1974 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT303L + GFXMMU_LUT303L + GFXMMU LUT entry 303 low + 0x1978 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT303H + GFXMMU_LUT303H + GFXMMU LUT entry 303 high + 0x197c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT304L + GFXMMU_LUT304L + GFXMMU LUT entry 304 low + 0x1980 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT304H + GFXMMU_LUT304H + GFXMMU LUT entry 304 high + 0x1984 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT305L + GFXMMU_LUT305L + GFXMMU LUT entry 305 low + 0x1988 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT305H + GFXMMU_LUT305H + GFXMMU LUT entry 305 high + 0x198c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT306L + GFXMMU_LUT306L + GFXMMU LUT entry 306 low + 0x1990 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT306H + GFXMMU_LUT306H + GFXMMU LUT entry 306 high + 0x1994 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT307L + GFXMMU_LUT307L + GFXMMU LUT entry 307 low + 0x1998 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT307H + GFXMMU_LUT307H + GFXMMU LUT entry 307 high + 0x199c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT308L + GFXMMU_LUT308L + GFXMMU LUT entry 308 low + 0x19a0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT308H + GFXMMU_LUT308H + GFXMMU LUT entry 308 high + 0x19a4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT309L + GFXMMU_LUT309L + GFXMMU LUT entry 309 low + 0x19a8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT309H + GFXMMU_LUT309H + GFXMMU LUT entry 309 high + 0x19ac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT310L + GFXMMU_LUT310L + GFXMMU LUT entry 310 low + 0x19b0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT310H + GFXMMU_LUT310H + GFXMMU LUT entry 310 high + 0x19b4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT311L + GFXMMU_LUT311L + GFXMMU LUT entry 311 low + 0x19b8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT311H + GFXMMU_LUT311H + GFXMMU LUT entry 311 high + 0x19bc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT312L + GFXMMU_LUT312L + GFXMMU LUT entry 312 low + 0x19c0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT312H + GFXMMU_LUT312H + GFXMMU LUT entry 312 high + 0x19c4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT313L + GFXMMU_LUT313L + GFXMMU LUT entry 313 low + 0x19c8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT313H + GFXMMU_LUT313H + GFXMMU LUT entry 313 high + 0x19cc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT314L + GFXMMU_LUT314L + GFXMMU LUT entry 314 low + 0x19d0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT314H + GFXMMU_LUT314H + GFXMMU LUT entry 314 high + 0x19d4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT315L + GFXMMU_LUT315L + GFXMMU LUT entry 315 low + 0x19d8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT315H + GFXMMU_LUT315H + GFXMMU LUT entry 315 high + 0x19dc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT316L + GFXMMU_LUT316L + GFXMMU LUT entry 316 low + 0x19e0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT316H + GFXMMU_LUT316H + GFXMMU LUT entry 316 high + 0x19e4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT317L + GFXMMU_LUT317L + GFXMMU LUT entry 317 low + 0x19e8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT317H + GFXMMU_LUT317H + GFXMMU LUT entry 317 high + 0x19ec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT318L + GFXMMU_LUT318L + GFXMMU LUT entry 318 low + 0x19f0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT318H + GFXMMU_LUT318H + GFXMMU LUT entry 318 high + 0x19f4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT319L + GFXMMU_LUT319L + GFXMMU LUT entry 319 low + 0x19f8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT319H + GFXMMU_LUT319H + GFXMMU LUT entry 319 high + 0x19fc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT320L + GFXMMU_LUT320L + GFXMMU LUT entry 320 low + 0x1a00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT320H + GFXMMU_LUT320H + GFXMMU LUT entry 320 high + 0x1a04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT321L + GFXMMU_LUT321L + GFXMMU LUT entry 321 low + 0x1a08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT321H + GFXMMU_LUT321H + GFXMMU LUT entry 321 high + 0x1a0c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT322L + GFXMMU_LUT322L + GFXMMU LUT entry 322 low + 0x1a10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT322H + GFXMMU_LUT322H + GFXMMU LUT entry 322 high + 0x1a14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT323L + GFXMMU_LUT323L + GFXMMU LUT entry 323 low + 0x1a18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT323H + GFXMMU_LUT323H + GFXMMU LUT entry 323 high + 0x1a1c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT324L + GFXMMU_LUT324L + GFXMMU LUT entry 324 low + 0x1a20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT324H + GFXMMU_LUT324H + GFXMMU LUT entry 324 high + 0x1a24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT325L + GFXMMU_LUT325L + GFXMMU LUT entry 325 low + 0x1a28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT325H + GFXMMU_LUT325H + GFXMMU LUT entry 325 high + 0x1a2c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT326L + GFXMMU_LUT326L + GFXMMU LUT entry 326 low + 0x1a30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT326H + GFXMMU_LUT326H + GFXMMU LUT entry 326 high + 0x1a34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT327L + GFXMMU_LUT327L + GFXMMU LUT entry 327 low + 0x1a38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT327H + GFXMMU_LUT327H + GFXMMU LUT entry 327 high + 0x1a3c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT328L + GFXMMU_LUT328L + GFXMMU LUT entry 328 low + 0x1a40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT328H + GFXMMU_LUT328H + GFXMMU LUT entry 328 high + 0x1a44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT329L + GFXMMU_LUT329L + GFXMMU LUT entry 329 low + 0x1a48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT329H + GFXMMU_LUT329H + GFXMMU LUT entry 329 high + 0x1a4c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT330L + GFXMMU_LUT330L + GFXMMU LUT entry 330 low + 0x1a50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT330H + GFXMMU_LUT330H + GFXMMU LUT entry 330 high + 0x1a54 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT331L + GFXMMU_LUT331L + GFXMMU LUT entry 331 low + 0x1a58 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT331H + GFXMMU_LUT331H + GFXMMU LUT entry 331 high + 0x1a5c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT332L + GFXMMU_LUT332L + GFXMMU LUT entry 332 low + 0x1a60 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT332H + GFXMMU_LUT332H + GFXMMU LUT entry 332 high + 0x1a64 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT333L + GFXMMU_LUT333L + GFXMMU LUT entry 333 low + 0x1a68 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT333H + GFXMMU_LUT333H + GFXMMU LUT entry 333 high + 0x1a6c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT334L + GFXMMU_LUT334L + GFXMMU LUT entry 334 low + 0x1a70 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT334H + GFXMMU_LUT334H + GFXMMU LUT entry 334 high + 0x1a74 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT335L + GFXMMU_LUT335L + GFXMMU LUT entry 335 low + 0x1a78 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT335H + GFXMMU_LUT335H + GFXMMU LUT entry 335 high + 0x1a7c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT336L + GFXMMU_LUT336L + GFXMMU LUT entry 336 low + 0x1a80 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT336H + GFXMMU_LUT336H + GFXMMU LUT entry 336 high + 0x1a84 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT337L + GFXMMU_LUT337L + GFXMMU LUT entry 337 low + 0x1a88 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT337H + GFXMMU_LUT337H + GFXMMU LUT entry 337 high + 0x1a8c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT338L + GFXMMU_LUT338L + GFXMMU LUT entry 338 low + 0x1a90 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT338H + GFXMMU_LUT338H + GFXMMU LUT entry 338 high + 0x1a94 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT339L + GFXMMU_LUT339L + GFXMMU LUT entry 339 low + 0x1a98 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT339H + GFXMMU_LUT339H + GFXMMU LUT entry 339 high + 0x1a9c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT340L + GFXMMU_LUT340L + GFXMMU LUT entry 340 low + 0x1aa0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT340H + GFXMMU_LUT340H + GFXMMU LUT entry 340 high + 0x1aa4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT341L + GFXMMU_LUT341L + GFXMMU LUT entry 341 low + 0x1aa8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT341H + GFXMMU_LUT341H + GFXMMU LUT entry 341 high + 0x1aac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT342L + GFXMMU_LUT342L + GFXMMU LUT entry 342 low + 0x1ab0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT342H + GFXMMU_LUT342H + GFXMMU LUT entry 342 high + 0x1ab4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT343L + GFXMMU_LUT343L + GFXMMU LUT entry 343 low + 0x1ab8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT343H + GFXMMU_LUT343H + GFXMMU LUT entry 343 high + 0x1abc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT344L + GFXMMU_LUT344L + GFXMMU LUT entry 344 low + 0x1ac0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT344H + GFXMMU_LUT344H + GFXMMU LUT entry 344 high + 0x1ac4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT345L + GFXMMU_LUT345L + GFXMMU LUT entry 345 low + 0x1ac8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT345H + GFXMMU_LUT345H + GFXMMU LUT entry 345 high + 0x1acc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT346L + GFXMMU_LUT346L + GFXMMU LUT entry 346 low + 0x1ad0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT346H + GFXMMU_LUT346H + GFXMMU LUT entry 346 high + 0x1ad4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT347L + GFXMMU_LUT347L + GFXMMU LUT entry 347 low + 0x1ad8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT347H + GFXMMU_LUT347H + GFXMMU LUT entry 347 high + 0x1adc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT348L + GFXMMU_LUT348L + GFXMMU LUT entry 348 low + 0x1ae0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT348H + GFXMMU_LUT348H + GFXMMU LUT entry 348 high + 0x1ae4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT349L + GFXMMU_LUT349L + GFXMMU LUT entry 349 low + 0x1ae8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT349H + GFXMMU_LUT349H + GFXMMU LUT entry 349 high + 0x1aec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT350L + GFXMMU_LUT350L + GFXMMU LUT entry 350 low + 0x1af0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT350H + GFXMMU_LUT350H + GFXMMU LUT entry 350 high + 0x1af4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT351L + GFXMMU_LUT351L + GFXMMU LUT entry 351 low + 0x1af8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT351H + GFXMMU_LUT351H + GFXMMU LUT entry 351 high + 0x1afc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT352L + GFXMMU_LUT352L + GFXMMU LUT entry 352 low + 0x1b00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT352H + GFXMMU_LUT352H + GFXMMU LUT entry 352 high + 0x1b04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT353L + GFXMMU_LUT353L + GFXMMU LUT entry 353 low + 0x1b08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT353H + GFXMMU_LUT353H + GFXMMU LUT entry 353 high + 0x1b0c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT354L + GFXMMU_LUT354L + GFXMMU LUT entry 354 low + 0x1b10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT354H + GFXMMU_LUT354H + GFXMMU LUT entry 354 high + 0x1b14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT355L + GFXMMU_LUT355L + GFXMMU LUT entry 355 low + 0x1b18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT355H + GFXMMU_LUT355H + GFXMMU LUT entry 355 high + 0x1b1c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT356L + GFXMMU_LUT356L + GFXMMU LUT entry 356 low + 0x1b20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT356H + GFXMMU_LUT356H + GFXMMU LUT entry 356 high + 0x1b24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT357L + GFXMMU_LUT357L + GFXMMU LUT entry 357 low + 0x1b28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT357H + GFXMMU_LUT357H + GFXMMU LUT entry 357 high + 0x1b2c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT358L + GFXMMU_LUT358L + GFXMMU LUT entry 358 low + 0x1b30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT358H + GFXMMU_LUT358H + GFXMMU LUT entry 358 high + 0x1b34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT359L + GFXMMU_LUT359L + GFXMMU LUT entry 359 low + 0x1b38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT359H + GFXMMU_LUT359H + GFXMMU LUT entry 359 high + 0x1b3c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT360L + GFXMMU_LUT360L + GFXMMU LUT entry 360 low + 0x1b40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT360H + GFXMMU_LUT360H + GFXMMU LUT entry 360 high + 0x1b44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT361L + GFXMMU_LUT361L + GFXMMU LUT entry 361 low + 0x1b48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT361H + GFXMMU_LUT361H + GFXMMU LUT entry 361 high + 0x1b4c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT362L + GFXMMU_LUT362L + GFXMMU LUT entry 362 low + 0x1b50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT362H + GFXMMU_LUT362H + GFXMMU LUT entry 362 high + 0x1b54 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT363L + GFXMMU_LUT363L + GFXMMU LUT entry 363 low + 0x1b58 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT363H + GFXMMU_LUT363H + GFXMMU LUT entry 363 high + 0x1b5c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT364L + GFXMMU_LUT364L + GFXMMU LUT entry 364 low + 0x1b60 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT364H + GFXMMU_LUT364H + GFXMMU LUT entry 364 high + 0x1b64 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT365L + GFXMMU_LUT365L + GFXMMU LUT entry 365 low + 0x1b68 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT365H + GFXMMU_LUT365H + GFXMMU LUT entry 365 high + 0x1b6c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT366L + GFXMMU_LUT366L + GFXMMU LUT entry 366 low + 0x1b70 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT366H + GFXMMU_LUT366H + GFXMMU LUT entry 366 high + 0x1b74 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT367L + GFXMMU_LUT367L + GFXMMU LUT entry 367 low + 0x1b78 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT367H + GFXMMU_LUT367H + GFXMMU LUT entry 367 high + 0x1b7c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT368L + GFXMMU_LUT368L + GFXMMU LUT entry 368 low + 0x1b80 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT368H + GFXMMU_LUT368H + GFXMMU LUT entry 368 high + 0x1b84 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT369L + GFXMMU_LUT369L + GFXMMU LUT entry 369 low + 0x1b88 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT369H + GFXMMU_LUT369H + GFXMMU LUT entry 369 high + 0x1b8c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT370L + GFXMMU_LUT370L + GFXMMU LUT entry 370 low + 0x1b90 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT370H + GFXMMU_LUT370H + GFXMMU LUT entry 370 high + 0x1b94 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT371L + GFXMMU_LUT371L + GFXMMU LUT entry 371 low + 0x1b98 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT371H + GFXMMU_LUT371H + GFXMMU LUT entry 371 high + 0x1b9c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT372L + GFXMMU_LUT372L + GFXMMU LUT entry 372 low + 0x1ba0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT372H + GFXMMU_LUT372H + GFXMMU LUT entry 372 high + 0x1ba4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT373L + GFXMMU_LUT373L + GFXMMU LUT entry 373 low + 0x1ba8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT373H + GFXMMU_LUT373H + GFXMMU LUT entry 373 high + 0x1bac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT374L + GFXMMU_LUT374L + GFXMMU LUT entry 374 low + 0x1bb0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT374H + GFXMMU_LUT374H + GFXMMU LUT entry 374 high + 0x1bb4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT375L + GFXMMU_LUT375L + GFXMMU LUT entry 375 low + 0x1bb8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT375H + GFXMMU_LUT375H + GFXMMU LUT entry 375 high + 0x1bbc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT376L + GFXMMU_LUT376L + GFXMMU LUT entry 376 low + 0x1bc0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT376H + GFXMMU_LUT376H + GFXMMU LUT entry 376 high + 0x1bc4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT377L + GFXMMU_LUT377L + GFXMMU LUT entry 377 low + 0x1bc8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT377H + GFXMMU_LUT377H + GFXMMU LUT entry 377 high + 0x1bcc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT378L + GFXMMU_LUT378L + GFXMMU LUT entry 378 low + 0x1bd0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT378H + GFXMMU_LUT378H + GFXMMU LUT entry 378 high + 0x1bd4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT379L + GFXMMU_LUT379L + GFXMMU LUT entry 379 low + 0x1bd8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT379H + GFXMMU_LUT379H + GFXMMU LUT entry 379 high + 0x1bdc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT380L + GFXMMU_LUT380L + GFXMMU LUT entry 380 low + 0x1be0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT380H + GFXMMU_LUT380H + GFXMMU LUT entry 380 high + 0x1be4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT381L + GFXMMU_LUT381L + GFXMMU LUT entry 381 low + 0x1be8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT381H + GFXMMU_LUT381H + GFXMMU LUT entry 381 high + 0x1bec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT382L + GFXMMU_LUT382L + GFXMMU LUT entry 382 low + 0x1bf0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT382H + GFXMMU_LUT382H + GFXMMU LUT entry 382 high + 0x1bf4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT383L + GFXMMU_LUT383L + GFXMMU LUT entry 383 low + 0x1bf8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT383H + GFXMMU_LUT383H + GFXMMU LUT entry 383 high + 0x1bfc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT384L + GFXMMU_LUT384L + GFXMMU LUT entry 384 low + 0x1c00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT384H + GFXMMU_LUT384H + GFXMMU LUT entry 384 high + 0x1c04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT385L + GFXMMU_LUT385L + GFXMMU LUT entry 385 low + 0x1c08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT385H + GFXMMU_LUT385H + GFXMMU LUT entry 385 high + 0x1c0c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT386L + GFXMMU_LUT386L + GFXMMU LUT entry 386 low + 0x1c10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT386H + GFXMMU_LUT386H + GFXMMU LUT entry 386 high + 0x1c14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT387L + GFXMMU_LUT387L + GFXMMU LUT entry 387 low + 0x1c18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT387H + GFXMMU_LUT387H + GFXMMU LUT entry 387 high + 0x1c1c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT388L + GFXMMU_LUT388L + GFXMMU LUT entry 388 low + 0x1c20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT388H + GFXMMU_LUT388H + GFXMMU LUT entry 388 high + 0x1c24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT389L + GFXMMU_LUT389L + GFXMMU LUT entry 389 low + 0x1c28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT389H + GFXMMU_LUT389H + GFXMMU LUT entry 389 high + 0x1c2c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT390L + GFXMMU_LUT390L + GFXMMU LUT entry 390 low + 0x1c30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT390H + GFXMMU_LUT390H + GFXMMU LUT entry 390 high + 0x1c34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT391L + GFXMMU_LUT391L + GFXMMU LUT entry 391 low + 0x1c38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT391H + GFXMMU_LUT391H + GFXMMU LUT entry 391 high + 0x1c3c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT392L + GFXMMU_LUT392L + GFXMMU LUT entry 392 low + 0x1c40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT392H + GFXMMU_LUT392H + GFXMMU LUT entry 392 high + 0x1c44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT393L + GFXMMU_LUT393L + GFXMMU LUT entry 393 low + 0x1c48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT393H + GFXMMU_LUT393H + GFXMMU LUT entry 393 high + 0x1c4c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT394L + GFXMMU_LUT394L + GFXMMU LUT entry 394 low + 0x1c50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT394H + GFXMMU_LUT394H + GFXMMU LUT entry 394 high + 0x1c54 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT395L + GFXMMU_LUT395L + GFXMMU LUT entry 395 low + 0x1c58 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT395H + GFXMMU_LUT395H + GFXMMU LUT entry 395 high + 0x1c5c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT396L + GFXMMU_LUT396L + GFXMMU LUT entry 396 low + 0x1c60 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT396H + GFXMMU_LUT396H + GFXMMU LUT entry 396 high + 0x1c64 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT397L + GFXMMU_LUT397L + GFXMMU LUT entry 397 low + 0x1c68 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT397H + GFXMMU_LUT397H + GFXMMU LUT entry 397 high + 0x1c6c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT398L + GFXMMU_LUT398L + GFXMMU LUT entry 398 low + 0x1c70 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT398H + GFXMMU_LUT398H + GFXMMU LUT entry 398 high + 0x1c74 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT399L + GFXMMU_LUT399L + GFXMMU LUT entry 399 low + 0x1c78 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT399H + GFXMMU_LUT399H + GFXMMU LUT entry 399 high + 0x1c7c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT400L + GFXMMU_LUT400L + GFXMMU LUT entry 400 low + 0x1c80 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT400H + GFXMMU_LUT400H + GFXMMU LUT entry 400 high + 0x1c84 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT401L + GFXMMU_LUT401L + GFXMMU LUT entry 401 low + 0x1c88 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT401H + GFXMMU_LUT401H + GFXMMU LUT entry 401 high + 0x1c8c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT402L + GFXMMU_LUT402L + GFXMMU LUT entry 402 low + 0x1c90 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT402H + GFXMMU_LUT402H + GFXMMU LUT entry 402 high + 0x1c94 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT403L + GFXMMU_LUT403L + GFXMMU LUT entry 403 low + 0x1c98 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT403H + GFXMMU_LUT403H + GFXMMU LUT entry 403 high + 0x1c9c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT404L + GFXMMU_LUT404L + GFXMMU LUT entry 404 low + 0x1ca0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT404H + GFXMMU_LUT404H + GFXMMU LUT entry 404 high + 0x1ca4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT405L + GFXMMU_LUT405L + GFXMMU LUT entry 405 low + 0x1ca8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT405H + GFXMMU_LUT405H + GFXMMU LUT entry 405 high + 0x1cac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT406L + GFXMMU_LUT406L + GFXMMU LUT entry 406 low + 0x1cb0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT406H + GFXMMU_LUT406H + GFXMMU LUT entry 406 high + 0x1cb4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT407L + GFXMMU_LUT407L + GFXMMU LUT entry 407 low + 0x1cb8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT407H + GFXMMU_LUT407H + GFXMMU LUT entry 407 high + 0x1cbc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT408L + GFXMMU_LUT408L + GFXMMU LUT entry 408 low + 0x1cc0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT408H + GFXMMU_LUT408H + GFXMMU LUT entry 408 high + 0x1cc4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT409L + GFXMMU_LUT409L + GFXMMU LUT entry 409 low + 0x1cc8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT409H + GFXMMU_LUT409H + GFXMMU LUT entry 409 high + 0x1ccc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT410L + GFXMMU_LUT410L + GFXMMU LUT entry 410 low + 0x1cd0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT410H + GFXMMU_LUT410H + GFXMMU LUT entry 410 high + 0x1cd4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT411L + GFXMMU_LUT411L + GFXMMU LUT entry 411 low + 0x1cd8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT411H + GFXMMU_LUT411H + GFXMMU LUT entry 411 high + 0x1cdc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT412L + GFXMMU_LUT412L + GFXMMU LUT entry 412 low + 0x1ce0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT412H + GFXMMU_LUT412H + GFXMMU LUT entry 412 high + 0x1ce4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT413L + GFXMMU_LUT413L + GFXMMU LUT entry 413 low + 0x1ce8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT413H + GFXMMU_LUT413H + GFXMMU LUT entry 413 high + 0x1cec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT414L + GFXMMU_LUT414L + GFXMMU LUT entry 414 low + 0x1cf0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT414H + GFXMMU_LUT414H + GFXMMU LUT entry 414 high + 0x1cf4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT415L + GFXMMU_LUT415L + GFXMMU LUT entry 415 low + 0x1cf8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT415H + GFXMMU_LUT415H + GFXMMU LUT entry 415 high + 0x1cfc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT416L + GFXMMU_LUT416L + GFXMMU LUT entry 416 low + 0x1d00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT416H + GFXMMU_LUT416H + GFXMMU LUT entry 416 high + 0x1d04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT417L + GFXMMU_LUT417L + GFXMMU LUT entry 417 low + 0x1d08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT417H + GFXMMU_LUT417H + GFXMMU LUT entry 417 high + 0x1d0c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT418L + GFXMMU_LUT418L + GFXMMU LUT entry 418 low + 0x1d10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT418H + GFXMMU_LUT418H + GFXMMU LUT entry 418 high + 0x1d14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT419L + GFXMMU_LUT419L + GFXMMU LUT entry 419 low + 0x1d18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT419H + GFXMMU_LUT419H + GFXMMU LUT entry 419 high + 0x1d1c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT420L + GFXMMU_LUT420L + GFXMMU LUT entry 420 low + 0x1d20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT420H + GFXMMU_LUT420H + GFXMMU LUT entry 420 high + 0x1d24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT421L + GFXMMU_LUT421L + GFXMMU LUT entry 421 low + 0x1d28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT421H + GFXMMU_LUT421H + GFXMMU LUT entry 421 high + 0x1d2c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT422L + GFXMMU_LUT422L + GFXMMU LUT entry 422 low + 0x1d30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT422H + GFXMMU_LUT422H + GFXMMU LUT entry 422 high + 0x1d34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT423L + GFXMMU_LUT423L + GFXMMU LUT entry 423 low + 0x1d38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT423H + GFXMMU_LUT423H + GFXMMU LUT entry 423 high + 0x1d3c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT424L + GFXMMU_LUT424L + GFXMMU LUT entry 424 low + 0x1d40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT424H + GFXMMU_LUT424H + GFXMMU LUT entry 424 high + 0x1d44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT425L + GFXMMU_LUT425L + GFXMMU LUT entry 425 low + 0x1d48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT425H + GFXMMU_LUT425H + GFXMMU LUT entry 425 high + 0x1d4c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT426L + GFXMMU_LUT426L + GFXMMU LUT entry 426 low + 0x1d50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT426H + GFXMMU_LUT426H + GFXMMU LUT entry 426 high + 0x1d54 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT427L + GFXMMU_LUT427L + GFXMMU LUT entry 427 low + 0x1d58 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT427H + GFXMMU_LUT427H + GFXMMU LUT entry 427 high + 0x1d5c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT428L + GFXMMU_LUT428L + GFXMMU LUT entry 428 low + 0x1d60 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT428H + GFXMMU_LUT428H + GFXMMU LUT entry 428 high + 0x1d64 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT429L + GFXMMU_LUT429L + GFXMMU LUT entry 429 low + 0x1d68 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT429H + GFXMMU_LUT429H + GFXMMU LUT entry 429 high + 0x1d6c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT430L + GFXMMU_LUT430L + GFXMMU LUT entry 430 low + 0x1d70 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT430H + GFXMMU_LUT430H + GFXMMU LUT entry 430 high + 0x1d74 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT431L + GFXMMU_LUT431L + GFXMMU LUT entry 431 low + 0x1d78 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT431H + GFXMMU_LUT431H + GFXMMU LUT entry 431 high + 0x1d7c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT432L + GFXMMU_LUT432L + GFXMMU LUT entry 432 low + 0x1d80 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT432H + GFXMMU_LUT432H + GFXMMU LUT entry 432 high + 0x1d84 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT433L + GFXMMU_LUT433L + GFXMMU LUT entry 433 low + 0x1d88 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT433H + GFXMMU_LUT433H + GFXMMU LUT entry 433 high + 0x1d8c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT434L + GFXMMU_LUT434L + GFXMMU LUT entry 434 low + 0x1d90 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT434H + GFXMMU_LUT434H + GFXMMU LUT entry 434 high + 0x1d94 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT435L + GFXMMU_LUT435L + GFXMMU LUT entry 435 low + 0x1d98 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT435H + GFXMMU_LUT435H + GFXMMU LUT entry 435 high + 0x1d9c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT436L + GFXMMU_LUT436L + GFXMMU LUT entry 436 low + 0x1da0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT436H + GFXMMU_LUT436H + GFXMMU LUT entry 436 high + 0x1da4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT437L + GFXMMU_LUT437L + GFXMMU LUT entry 437 low + 0x1da8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT437H + GFXMMU_LUT437H + GFXMMU LUT entry 437 high + 0x1dac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT438L + GFXMMU_LUT438L + GFXMMU LUT entry 438 low + 0x1db0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT438H + GFXMMU_LUT438H + GFXMMU LUT entry 438 high + 0x1db4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT439L + GFXMMU_LUT439L + GFXMMU LUT entry 439 low + 0x1db8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT439H + GFXMMU_LUT439H + GFXMMU LUT entry 439 high + 0x1dbc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT440L + GFXMMU_LUT440L + GFXMMU LUT entry 440 low + 0x1dc0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT440H + GFXMMU_LUT440H + GFXMMU LUT entry 440 high + 0x1dc4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT441L + GFXMMU_LUT441L + GFXMMU LUT entry 441 low + 0x1dc8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT441H + GFXMMU_LUT441H + GFXMMU LUT entry 441 high + 0x1dcc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT442L + GFXMMU_LUT442L + GFXMMU LUT entry 442 low + 0x1dd0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT442H + GFXMMU_LUT442H + GFXMMU LUT entry 442 high + 0x1dd4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT443L + GFXMMU_LUT443L + GFXMMU LUT entry 443 low + 0x1dd8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT443H + GFXMMU_LUT443H + GFXMMU LUT entry 443 high + 0x1ddc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT444L + GFXMMU_LUT444L + GFXMMU LUT entry 444 low + 0x1de0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT444H + GFXMMU_LUT444H + GFXMMU LUT entry 444 high + 0x1de4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT445L + GFXMMU_LUT445L + GFXMMU LUT entry 445 low + 0x1de8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT445H + GFXMMU_LUT445H + GFXMMU LUT entry 445 high + 0x1dec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT446L + GFXMMU_LUT446L + GFXMMU LUT entry 446 low + 0x1df0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT446H + GFXMMU_LUT446H + GFXMMU LUT entry 446 high + 0x1df4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT447L + GFXMMU_LUT447L + GFXMMU LUT entry 447 low + 0x1df8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT447H + GFXMMU_LUT447H + GFXMMU LUT entry 447 high + 0x1dfc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT448L + GFXMMU_LUT448L + GFXMMU LUT entry 448 low + 0x1e00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT448H + GFXMMU_LUT448H + GFXMMU LUT entry 448 high + 0x1e04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT449L + GFXMMU_LUT449L + GFXMMU LUT entry 449 low + 0x1e08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT449H + GFXMMU_LUT449H + GFXMMU LUT entry 449 high + 0x1e0c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT450L + GFXMMU_LUT450L + GFXMMU LUT entry 450 low + 0x1e10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT450H + GFXMMU_LUT450H + GFXMMU LUT entry 450 high + 0x1e14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT451L + GFXMMU_LUT451L + GFXMMU LUT entry 451 low + 0x1e18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT451H + GFXMMU_LUT451H + GFXMMU LUT entry 451 high + 0x1e1c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT452L + GFXMMU_LUT452L + GFXMMU LUT entry 452 low + 0x1e20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT452H + GFXMMU_LUT452H + GFXMMU LUT entry 452 high + 0x1e24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT453L + GFXMMU_LUT453L + GFXMMU LUT entry 453 low + 0x1e28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT453H + GFXMMU_LUT453H + GFXMMU LUT entry 453 high + 0x1e2c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT454L + GFXMMU_LUT454L + GFXMMU LUT entry 454 low + 0x1e30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT454H + GFXMMU_LUT454H + GFXMMU LUT entry 454 high + 0x1e34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT455L + GFXMMU_LUT455L + GFXMMU LUT entry 455 low + 0x1e38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT455H + GFXMMU_LUT455H + GFXMMU LUT entry 455 high + 0x1e3c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT456L + GFXMMU_LUT456L + GFXMMU LUT entry 456 low + 0x1e40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT456H + GFXMMU_LUT456H + GFXMMU LUT entry 456 high + 0x1e44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT457L + GFXMMU_LUT457L + GFXMMU LUT entry 457 low + 0x1e48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT457H + GFXMMU_LUT457H + GFXMMU LUT entry 457 high + 0x1e4c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT458L + GFXMMU_LUT458L + GFXMMU LUT entry 458 low + 0x1e50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT458H + GFXMMU_LUT458H + GFXMMU LUT entry 458 high + 0x1e54 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT459L + GFXMMU_LUT459L + GFXMMU LUT entry 459 low + 0x1e58 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT459H + GFXMMU_LUT459H + GFXMMU LUT entry 459 high + 0x1e5c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT460L + GFXMMU_LUT460L + GFXMMU LUT entry 460 low + 0x1e60 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT460H + GFXMMU_LUT460H + GFXMMU LUT entry 460 high + 0x1e64 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT461L + GFXMMU_LUT461L + GFXMMU LUT entry 461 low + 0x1e68 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT461H + GFXMMU_LUT461H + GFXMMU LUT entry 461 high + 0x1e6c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT462L + GFXMMU_LUT462L + GFXMMU LUT entry 462 low + 0x1e70 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT462H + GFXMMU_LUT462H + GFXMMU LUT entry 462 high + 0x1e74 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT463L + GFXMMU_LUT463L + GFXMMU LUT entry 463 low + 0x1e78 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT463H + GFXMMU_LUT463H + GFXMMU LUT entry 463 high + 0x1e7c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT464L + GFXMMU_LUT464L + GFXMMU LUT entry 464 low + 0x1e80 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT464H + GFXMMU_LUT464H + GFXMMU LUT entry 464 high + 0x1e84 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT465L + GFXMMU_LUT465L + GFXMMU LUT entry 465 low + 0x1e88 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT465H + GFXMMU_LUT465H + GFXMMU LUT entry 465 high + 0x1e8c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT466L + GFXMMU_LUT466L + GFXMMU LUT entry 466 low + 0x1e90 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT466H + GFXMMU_LUT466H + GFXMMU LUT entry 466 high + 0x1e94 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT467L + GFXMMU_LUT467L + GFXMMU LUT entry 467 low + 0x1e98 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT467H + GFXMMU_LUT467H + GFXMMU LUT entry 467 high + 0x1e9c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT468L + GFXMMU_LUT468L + GFXMMU LUT entry 468 low + 0x1ea0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT468H + GFXMMU_LUT468H + GFXMMU LUT entry 468 high + 0x1ea4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT469L + GFXMMU_LUT469L + GFXMMU LUT entry 469 low + 0x1ea8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT469H + GFXMMU_LUT469H + GFXMMU LUT entry 469 high + 0x1eac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT470L + GFXMMU_LUT470L + GFXMMU LUT entry 470 low + 0x1eb0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT470H + GFXMMU_LUT470H + GFXMMU LUT entry 470 high + 0x1eb4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT471L + GFXMMU_LUT471L + GFXMMU LUT entry 471 low + 0x1eb8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT471H + GFXMMU_LUT471H + GFXMMU LUT entry 471 high + 0x1ebc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT472L + GFXMMU_LUT472L + GFXMMU LUT entry 472 low + 0x1ec0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT472H + GFXMMU_LUT472H + GFXMMU LUT entry 472 high + 0x1ec4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT473L + GFXMMU_LUT473L + GFXMMU LUT entry 473 low + 0x1ec8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT473H + GFXMMU_LUT473H + GFXMMU LUT entry 473 high + 0x1ecc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT474L + GFXMMU_LUT474L + GFXMMU LUT entry 474 low + 0x1ed0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT474H + GFXMMU_LUT474H + GFXMMU LUT entry 474 high + 0x1ed4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT475L + GFXMMU_LUT475L + GFXMMU LUT entry 475 low + 0x1ed8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT475H + GFXMMU_LUT475H + GFXMMU LUT entry 475 high + 0x1edc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT476L + GFXMMU_LUT476L + GFXMMU LUT entry 476 low + 0x1ee0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT476H + GFXMMU_LUT476H + GFXMMU LUT entry 476 high + 0x1ee4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT477L + GFXMMU_LUT477L + GFXMMU LUT entry 477 low + 0x1ee8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT477H + GFXMMU_LUT477H + GFXMMU LUT entry 477 high + 0x1eec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT478L + GFXMMU_LUT478L + GFXMMU LUT entry 478 low + 0x1ef0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT478H + GFXMMU_LUT478H + GFXMMU LUT entry 478 high + 0x1ef4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT479L + GFXMMU_LUT479L + GFXMMU LUT entry 479 low + 0x1ef8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT479H + GFXMMU_LUT479H + GFXMMU LUT entry 479 high + 0x1efc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT480L + GFXMMU_LUT480L + GFXMMU LUT entry 480 low + 0x1f00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT480H + GFXMMU_LUT480H + GFXMMU LUT entry 480 high + 0x1f04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT481L + GFXMMU_LUT481L + GFXMMU LUT entry 481 low + 0x1f08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT481H + GFXMMU_LUT481H + GFXMMU LUT entry 481 high + 0x1f0c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT482L + GFXMMU_LUT482L + GFXMMU LUT entry 482 low + 0x1f10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT482H + GFXMMU_LUT482H + GFXMMU LUT entry 482 high + 0x1f14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT483L + GFXMMU_LUT483L + GFXMMU LUT entry 483 low + 0x1f18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT483H + GFXMMU_LUT483H + GFXMMU LUT entry 483 high + 0x1f1c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT484L + GFXMMU_LUT484L + GFXMMU LUT entry 484 low + 0x1f20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT484H + GFXMMU_LUT484H + GFXMMU LUT entry 484 high + 0x1f24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT485L + GFXMMU_LUT485L + GFXMMU LUT entry 485 low + 0x1f28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT485H + GFXMMU_LUT485H + GFXMMU LUT entry 485 high + 0x1f2c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT486L + GFXMMU_LUT486L + GFXMMU LUT entry 486 low + 0x1f30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT486H + GFXMMU_LUT486H + GFXMMU LUT entry 486 high + 0x1f34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT487L + GFXMMU_LUT487L + GFXMMU LUT entry 487 low + 0x1f38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT487H + GFXMMU_LUT487H + GFXMMU LUT entry 487 high + 0x1f3c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT488L + GFXMMU_LUT488L + GFXMMU LUT entry 488 low + 0x1f40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT488H + GFXMMU_LUT488H + GFXMMU LUT entry 488 high + 0x1f44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT489L + GFXMMU_LUT489L + GFXMMU LUT entry 489 low + 0x1f48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT489H + GFXMMU_LUT489H + GFXMMU LUT entry 489 high + 0x1f4c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT490L + GFXMMU_LUT490L + GFXMMU LUT entry 490 low + 0x1f50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT490H + GFXMMU_LUT490H + GFXMMU LUT entry 490 high + 0x1f54 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT491L + GFXMMU_LUT491L + GFXMMU LUT entry 491 low + 0x1f58 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT491H + GFXMMU_LUT491H + GFXMMU LUT entry 491 high + 0x1f5c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT492L + GFXMMU_LUT492L + GFXMMU LUT entry 492 low + 0x1f60 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT492H + GFXMMU_LUT492H + GFXMMU LUT entry 492 high + 0x1f64 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT493L + GFXMMU_LUT493L + GFXMMU LUT entry 493 low + 0x1f68 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT493H + GFXMMU_LUT493H + GFXMMU LUT entry 493 high + 0x1f6c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT494L + GFXMMU_LUT494L + GFXMMU LUT entry 494 low + 0x1f70 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT494H + GFXMMU_LUT494H + GFXMMU LUT entry 494 high + 0x1f74 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT495L + GFXMMU_LUT495L + GFXMMU LUT entry 495 low + 0x1f78 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT495H + GFXMMU_LUT495H + GFXMMU LUT entry 495 high + 0x1f7c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT496L + GFXMMU_LUT496L + GFXMMU LUT entry 496 low + 0x1f80 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT496H + GFXMMU_LUT496H + GFXMMU LUT entry 496 high + 0x1f84 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT497L + GFXMMU_LUT497L + GFXMMU LUT entry 497 low + 0x1f88 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT497H + GFXMMU_LUT497H + GFXMMU LUT entry 497 high + 0x1f8c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT498L + GFXMMU_LUT498L + GFXMMU LUT entry 498 low + 0x1f90 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT498H + GFXMMU_LUT498H + GFXMMU LUT entry 498 high + 0x1f94 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT499L + GFXMMU_LUT499L + GFXMMU LUT entry 499 low + 0x1f98 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT499H + GFXMMU_LUT499H + GFXMMU LUT entry 499 high + 0x1f9c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT500L + GFXMMU_LUT500L + GFXMMU LUT entry 500 low + 0x1fa0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT500H + GFXMMU_LUT500H + GFXMMU LUT entry 500 high + 0x1fa4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT501L + GFXMMU_LUT501L + GFXMMU LUT entry 501 low + 0x1fa8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT501H + GFXMMU_LUT501H + GFXMMU LUT entry 501 high + 0x1fac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT502L + GFXMMU_LUT502L + GFXMMU LUT entry 502 low + 0x1fb0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT502H + GFXMMU_LUT502H + GFXMMU LUT entry 502 high + 0x1fb4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT503L + GFXMMU_LUT503L + GFXMMU LUT entry 503 low + 0x1fb8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT503H + GFXMMU_LUT503H + GFXMMU LUT entry 503 high + 0x1fbc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT504L + GFXMMU_LUT504L + GFXMMU LUT entry 504 low + 0x1fc0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT504H + GFXMMU_LUT504H + GFXMMU LUT entry 504 high + 0x1fc4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT505L + GFXMMU_LUT505L + GFXMMU LUT entry 505 low + 0x1fc8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT505H + GFXMMU_LUT505H + GFXMMU LUT entry 505 high + 0x1fcc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT506L + GFXMMU_LUT506L + GFXMMU LUT entry 506 low + 0x1fd0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT506H + GFXMMU_LUT506H + GFXMMU LUT entry 506 high + 0x1fd4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT507L + GFXMMU_LUT507L + GFXMMU LUT entry 507 low + 0x1fd8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT507H + GFXMMU_LUT507H + GFXMMU LUT entry 507 high + 0x1fdc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT508L + GFXMMU_LUT508L + GFXMMU LUT entry 508 low + 0x1fe0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT508H + GFXMMU_LUT508H + GFXMMU LUT entry 508 high + 0x1fe4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT509L + GFXMMU_LUT509L + GFXMMU LUT entry 509 low + 0x1fe8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT509H + GFXMMU_LUT509H + GFXMMU LUT entry 509 high + 0x1fec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT510L + GFXMMU_LUT510L + GFXMMU LUT entry 510 low + 0x1ff0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT510H + GFXMMU_LUT510H + GFXMMU LUT entry 510 high + 0x1ff4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT511L + GFXMMU_LUT511L + GFXMMU LUT entry 511 low + 0x1ff8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT511H + GFXMMU_LUT511H + GFXMMU LUT entry 511 high + 0x1ffc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT512L + GFXMMU_LUT512L + GFXMMU LUT entry 512 low + 0x2000 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT512H + GFXMMU_LUT512H + GFXMMU LUT entry 512 high + 0x2004 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT513L + GFXMMU_LUT513L + GFXMMU LUT entry 513 low + 0x2008 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT513H + GFXMMU_LUT513H + GFXMMU LUT entry 513 high + 0x200c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT514L + GFXMMU_LUT514L + GFXMMU LUT entry 514 low + 0x2010 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT514H + GFXMMU_LUT514H + GFXMMU LUT entry 514 high + 0x2014 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT515L + GFXMMU_LUT515L + GFXMMU LUT entry 515 low + 0x2018 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT515H + GFXMMU_LUT515H + GFXMMU LUT entry 515 high + 0x201c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT516L + GFXMMU_LUT516L + GFXMMU LUT entry 516 low + 0x2020 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT516H + GFXMMU_LUT516H + GFXMMU LUT entry 516 high + 0x2024 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT517L + GFXMMU_LUT517L + GFXMMU LUT entry 517 low + 0x2028 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT517H + GFXMMU_LUT517H + GFXMMU LUT entry 517 high + 0x202c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT518L + GFXMMU_LUT518L + GFXMMU LUT entry 518 low + 0x2030 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT518H + GFXMMU_LUT518H + GFXMMU LUT entry 518 high + 0x2034 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT519L + GFXMMU_LUT519L + GFXMMU LUT entry 519 low + 0x2038 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT519H + GFXMMU_LUT519H + GFXMMU LUT entry 519 high + 0x203c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT520L + GFXMMU_LUT520L + GFXMMU LUT entry 520 low + 0x2040 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT520H + GFXMMU_LUT520H + GFXMMU LUT entry 520 high + 0x2044 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT521L + GFXMMU_LUT521L + GFXMMU LUT entry 521 low + 0x2048 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT521H + GFXMMU_LUT521H + GFXMMU LUT entry 521 high + 0x204c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT522L + GFXMMU_LUT522L + GFXMMU LUT entry 522 low + 0x2050 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT522H + GFXMMU_LUT522H + GFXMMU LUT entry 522 high + 0x2054 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT523L + GFXMMU_LUT523L + GFXMMU LUT entry 523 low + 0x2058 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT523H + GFXMMU_LUT523H + GFXMMU LUT entry 523 high + 0x205c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT524L + GFXMMU_LUT524L + GFXMMU LUT entry 524 low + 0x2060 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT524H + GFXMMU_LUT524H + GFXMMU LUT entry 524 high + 0x2064 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT525L + GFXMMU_LUT525L + GFXMMU LUT entry 525 low + 0x2068 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT525H + GFXMMU_LUT525H + GFXMMU LUT entry 525 high + 0x206c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT526L + GFXMMU_LUT526L + GFXMMU LUT entry 526 low + 0x2070 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT526H + GFXMMU_LUT526H + GFXMMU LUT entry 526 high + 0x2074 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT527L + GFXMMU_LUT527L + GFXMMU LUT entry 527 low + 0x2078 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT527H + GFXMMU_LUT527H + GFXMMU LUT entry 527 high + 0x207c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT528L + GFXMMU_LUT528L + GFXMMU LUT entry 528 low + 0x2080 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT528H + GFXMMU_LUT528H + GFXMMU LUT entry 528 high + 0x2084 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT529L + GFXMMU_LUT529L + GFXMMU LUT entry 529 low + 0x2088 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT529H + GFXMMU_LUT529H + GFXMMU LUT entry 529 high + 0x208c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT530L + GFXMMU_LUT530L + GFXMMU LUT entry 530 low + 0x2090 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT530H + GFXMMU_LUT530H + GFXMMU LUT entry 530 high + 0x2094 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT531L + GFXMMU_LUT531L + GFXMMU LUT entry 531 low + 0x2098 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT531H + GFXMMU_LUT531H + GFXMMU LUT entry 531 high + 0x209c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT532L + GFXMMU_LUT532L + GFXMMU LUT entry 532 low + 0x20a0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT532H + GFXMMU_LUT532H + GFXMMU LUT entry 532 high + 0x20a4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT533L + GFXMMU_LUT533L + GFXMMU LUT entry 533 low + 0x20a8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT533H + GFXMMU_LUT533H + GFXMMU LUT entry 533 high + 0x20ac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT534L + GFXMMU_LUT534L + GFXMMU LUT entry 534 low + 0x20b0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT534H + GFXMMU_LUT534H + GFXMMU LUT entry 534 high + 0x20b4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT535L + GFXMMU_LUT535L + GFXMMU LUT entry 535 low + 0x20b8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT535H + GFXMMU_LUT535H + GFXMMU LUT entry 535 high + 0x20bc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT536L + GFXMMU_LUT536L + GFXMMU LUT entry 536 low + 0x20c0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT536H + GFXMMU_LUT536H + GFXMMU LUT entry 536 high + 0x20c4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT537L + GFXMMU_LUT537L + GFXMMU LUT entry 537 low + 0x20c8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT537H + GFXMMU_LUT537H + GFXMMU LUT entry 537 high + 0x20cc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT538L + GFXMMU_LUT538L + GFXMMU LUT entry 538 low + 0x20d0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT538H + GFXMMU_LUT538H + GFXMMU LUT entry 538 high + 0x20d4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT539L + GFXMMU_LUT539L + GFXMMU LUT entry 539 low + 0x20d8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT539H + GFXMMU_LUT539H + GFXMMU LUT entry 539 high + 0x20dc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT540L + GFXMMU_LUT540L + GFXMMU LUT entry 540 low + 0x20e0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT540H + GFXMMU_LUT540H + GFXMMU LUT entry 540 high + 0x20e4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT541L + GFXMMU_LUT541L + GFXMMU LUT entry 541 low + 0x20e8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT541H + GFXMMU_LUT541H + GFXMMU LUT entry 541 high + 0x20ec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT542L + GFXMMU_LUT542L + GFXMMU LUT entry 542 low + 0x20f0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT542H + GFXMMU_LUT542H + GFXMMU LUT entry 542 high + 0x20f4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT543L + GFXMMU_LUT543L + GFXMMU LUT entry 543 low + 0x20f8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT543H + GFXMMU_LUT543H + GFXMMU LUT entry 543 high + 0x20fc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT544L + GFXMMU_LUT544L + GFXMMU LUT entry 544 low + 0x2100 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT544H + GFXMMU_LUT544H + GFXMMU LUT entry 544 high + 0x2104 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT545L + GFXMMU_LUT545L + GFXMMU LUT entry 545 low + 0x2108 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT545H + GFXMMU_LUT545H + GFXMMU LUT entry 545 high + 0x210c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT546L + GFXMMU_LUT546L + GFXMMU LUT entry 546 low + 0x2110 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT546H + GFXMMU_LUT546H + GFXMMU LUT entry 546 high + 0x2114 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT547L + GFXMMU_LUT547L + GFXMMU LUT entry 547 low + 0x2118 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT547H + GFXMMU_LUT547H + GFXMMU LUT entry 547 high + 0x211c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT548L + GFXMMU_LUT548L + GFXMMU LUT entry 548 low + 0x2120 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT548H + GFXMMU_LUT548H + GFXMMU LUT entry 548 high + 0x2124 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT549L + GFXMMU_LUT549L + GFXMMU LUT entry 549 low + 0x2128 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT549H + GFXMMU_LUT549H + GFXMMU LUT entry 549 high + 0x212c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT550L + GFXMMU_LUT550L + GFXMMU LUT entry 550 low + 0x2130 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT550H + GFXMMU_LUT550H + GFXMMU LUT entry 550 high + 0x2134 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT551L + GFXMMU_LUT551L + GFXMMU LUT entry 551 low + 0x2138 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT551H + GFXMMU_LUT551H + GFXMMU LUT entry 551 high + 0x213c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT552L + GFXMMU_LUT552L + GFXMMU LUT entry 552 low + 0x2140 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT552H + GFXMMU_LUT552H + GFXMMU LUT entry 552 high + 0x2144 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT553L + GFXMMU_LUT553L + GFXMMU LUT entry 553 low + 0x2148 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT553H + GFXMMU_LUT553H + GFXMMU LUT entry 553 high + 0x214c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT554L + GFXMMU_LUT554L + GFXMMU LUT entry 554 low + 0x2150 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT554H + GFXMMU_LUT554H + GFXMMU LUT entry 554 high + 0x2154 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT555L + GFXMMU_LUT555L + GFXMMU LUT entry 555 low + 0x2158 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT555H + GFXMMU_LUT555H + GFXMMU LUT entry 555 high + 0x215c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT556L + GFXMMU_LUT556L + GFXMMU LUT entry 556 low + 0x2160 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT556H + GFXMMU_LUT556H + GFXMMU LUT entry 556 high + 0x2164 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT557L + GFXMMU_LUT557L + GFXMMU LUT entry 557 low + 0x2168 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT557H + GFXMMU_LUT557H + GFXMMU LUT entry 557 high + 0x216c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT558L + GFXMMU_LUT558L + GFXMMU LUT entry 558 low + 0x2170 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT558H + GFXMMU_LUT558H + GFXMMU LUT entry 558 high + 0x2174 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT559L + GFXMMU_LUT559L + GFXMMU LUT entry 559 low + 0x2178 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT559H + GFXMMU_LUT559H + GFXMMU LUT entry 559 high + 0x217c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT560L + GFXMMU_LUT560L + GFXMMU LUT entry 560 low + 0x2180 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT560H + GFXMMU_LUT560H + GFXMMU LUT entry 560 high + 0x2184 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT561L + GFXMMU_LUT561L + GFXMMU LUT entry 561 low + 0x2188 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT561H + GFXMMU_LUT561H + GFXMMU LUT entry 561 high + 0x218c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT562L + GFXMMU_LUT562L + GFXMMU LUT entry 562 low + 0x2190 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT562H + GFXMMU_LUT562H + GFXMMU LUT entry 562 high + 0x2194 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT563L + GFXMMU_LUT563L + GFXMMU LUT entry 563 low + 0x2198 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT563H + GFXMMU_LUT563H + GFXMMU LUT entry 563 high + 0x219c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT564L + GFXMMU_LUT564L + GFXMMU LUT entry 564 low + 0x21a0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT564H + GFXMMU_LUT564H + GFXMMU LUT entry 564 high + 0x21a4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT565L + GFXMMU_LUT565L + GFXMMU LUT entry 565 low + 0x21a8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT565H + GFXMMU_LUT565H + GFXMMU LUT entry 565 high + 0x21ac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT566L + GFXMMU_LUT566L + GFXMMU LUT entry 566 low + 0x21b0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT566H + GFXMMU_LUT566H + GFXMMU LUT entry 566 high + 0x21b4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT567L + GFXMMU_LUT567L + GFXMMU LUT entry 567 low + 0x21b8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT567H + GFXMMU_LUT567H + GFXMMU LUT entry 567 high + 0x21bc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT568L + GFXMMU_LUT568L + GFXMMU LUT entry 568 low + 0x21c0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT568H + GFXMMU_LUT568H + GFXMMU LUT entry 568 high + 0x21c4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT569L + GFXMMU_LUT569L + GFXMMU LUT entry 569 low + 0x21c8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT569H + GFXMMU_LUT569H + GFXMMU LUT entry 569 high + 0x21cc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT570L + GFXMMU_LUT570L + GFXMMU LUT entry 570 low + 0x21d0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT570H + GFXMMU_LUT570H + GFXMMU LUT entry 570 high + 0x21d4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT571L + GFXMMU_LUT571L + GFXMMU LUT entry 571 low + 0x21d8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT571H + GFXMMU_LUT571H + GFXMMU LUT entry 571 high + 0x21dc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT572L + GFXMMU_LUT572L + GFXMMU LUT entry 572 low + 0x21e0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT572H + GFXMMU_LUT572H + GFXMMU LUT entry 572 high + 0x21e4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT573L + GFXMMU_LUT573L + GFXMMU LUT entry 573 low + 0x21e8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT573H + GFXMMU_LUT573H + GFXMMU LUT entry 573 high + 0x21ec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT574L + GFXMMU_LUT574L + GFXMMU LUT entry 574 low + 0x21f0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT574H + GFXMMU_LUT574H + GFXMMU LUT entry 574 high + 0x21f4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT575L + GFXMMU_LUT575L + GFXMMU LUT entry 575 low + 0x21f8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT575H + GFXMMU_LUT575H + GFXMMU LUT entry 575 high + 0x21fc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT576L + GFXMMU_LUT576L + GFXMMU LUT entry 576 low + 0x2200 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT576H + GFXMMU_LUT576H + GFXMMU LUT entry 576 high + 0x2204 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT577L + GFXMMU_LUT577L + GFXMMU LUT entry 577 low + 0x2208 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT577H + GFXMMU_LUT577H + GFXMMU LUT entry 577 high + 0x220c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT578L + GFXMMU_LUT578L + GFXMMU LUT entry 578 low + 0x2210 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT578H + GFXMMU_LUT578H + GFXMMU LUT entry 578 high + 0x2214 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT579L + GFXMMU_LUT579L + GFXMMU LUT entry 579 low + 0x2218 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT579H + GFXMMU_LUT579H + GFXMMU LUT entry 579 high + 0x221c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT580L + GFXMMU_LUT580L + GFXMMU LUT entry 580 low + 0x2220 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT580H + GFXMMU_LUT580H + GFXMMU LUT entry 580 high + 0x2224 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT581L + GFXMMU_LUT581L + GFXMMU LUT entry 581 low + 0x2228 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT581H + GFXMMU_LUT581H + GFXMMU LUT entry 581 high + 0x222c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT582L + GFXMMU_LUT582L + GFXMMU LUT entry 582 low + 0x2230 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT582H + GFXMMU_LUT582H + GFXMMU LUT entry 582 high + 0x2234 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT583L + GFXMMU_LUT583L + GFXMMU LUT entry 583 low + 0x2238 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT583H + GFXMMU_LUT583H + GFXMMU LUT entry 583 high + 0x223c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT584L + GFXMMU_LUT584L + GFXMMU LUT entry 584 low + 0x2240 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT584H + GFXMMU_LUT584H + GFXMMU LUT entry 584 high + 0x2244 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT585L + GFXMMU_LUT585L + GFXMMU LUT entry 585 low + 0x2248 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT585H + GFXMMU_LUT585H + GFXMMU LUT entry 585 high + 0x224c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT586L + GFXMMU_LUT586L + GFXMMU LUT entry 586 low + 0x2250 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT586H + GFXMMU_LUT586H + GFXMMU LUT entry 586 high + 0x2254 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT587L + GFXMMU_LUT587L + GFXMMU LUT entry 587 low + 0x2258 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT587H + GFXMMU_LUT587H + GFXMMU LUT entry 587 high + 0x225c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT588L + GFXMMU_LUT588L + GFXMMU LUT entry 588 low + 0x2260 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT588H + GFXMMU_LUT588H + GFXMMU LUT entry 588 high + 0x2264 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT589L + GFXMMU_LUT589L + GFXMMU LUT entry 589 low + 0x2268 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT589H + GFXMMU_LUT589H + GFXMMU LUT entry 589 high + 0x226c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT590L + GFXMMU_LUT590L + GFXMMU LUT entry 590 low + 0x2270 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT590H + GFXMMU_LUT590H + GFXMMU LUT entry 590 high + 0x2274 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT591L + GFXMMU_LUT591L + GFXMMU LUT entry 591 low + 0x2278 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT591H + GFXMMU_LUT591H + GFXMMU LUT entry 591 high + 0x227c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT592L + GFXMMU_LUT592L + GFXMMU LUT entry 592 low + 0x2280 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT592H + GFXMMU_LUT592H + GFXMMU LUT entry 592 high + 0x2284 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT593L + GFXMMU_LUT593L + GFXMMU LUT entry 593 low + 0x2288 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT593H + GFXMMU_LUT593H + GFXMMU LUT entry 593 high + 0x228c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT594L + GFXMMU_LUT594L + GFXMMU LUT entry 594 low + 0x2290 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT594H + GFXMMU_LUT594H + GFXMMU LUT entry 594 high + 0x2294 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT595L + GFXMMU_LUT595L + GFXMMU LUT entry 595 low + 0x2298 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT595H + GFXMMU_LUT595H + GFXMMU LUT entry 595 high + 0x229c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT596L + GFXMMU_LUT596L + GFXMMU LUT entry 596 low + 0x22a0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT596H + GFXMMU_LUT596H + GFXMMU LUT entry 596 high + 0x22a4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT597L + GFXMMU_LUT597L + GFXMMU LUT entry 597 low + 0x22a8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT597H + GFXMMU_LUT597H + GFXMMU LUT entry 597 high + 0x22ac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT598L + GFXMMU_LUT598L + GFXMMU LUT entry 598 low + 0x22b0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT598H + GFXMMU_LUT598H + GFXMMU LUT entry 598 high + 0x22b4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT599L + GFXMMU_LUT599L + GFXMMU LUT entry 599 low + 0x22b8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT599H + GFXMMU_LUT599H + GFXMMU LUT entry 599 high + 0x22bc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT600L + GFXMMU_LUT600L + GFXMMU LUT entry 600 low + 0x22c0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT600H + GFXMMU_LUT600H + GFXMMU LUT entry 600 high + 0x22c4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT601L + GFXMMU_LUT601L + GFXMMU LUT entry 601 low + 0x22c8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT601H + GFXMMU_LUT601H + GFXMMU LUT entry 601 high + 0x22cc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT602L + GFXMMU_LUT602L + GFXMMU LUT entry 602 low + 0x22d0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT602H + GFXMMU_LUT602H + GFXMMU LUT entry 602 high + 0x22d4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT603L + GFXMMU_LUT603L + GFXMMU LUT entry 603 low + 0x22d8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT603H + GFXMMU_LUT603H + GFXMMU LUT entry 603 high + 0x22dc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT604L + GFXMMU_LUT604L + GFXMMU LUT entry 604 low + 0x22e0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT604H + GFXMMU_LUT604H + GFXMMU LUT entry 604 high + 0x22e4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT605L + GFXMMU_LUT605L + GFXMMU LUT entry 605 low + 0x22e8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT605H + GFXMMU_LUT605H + GFXMMU LUT entry 605 high + 0x22ec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT606L + GFXMMU_LUT606L + GFXMMU LUT entry 606 low + 0x22f0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT606H + GFXMMU_LUT606H + GFXMMU LUT entry 606 high + 0x22f4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT607L + GFXMMU_LUT607L + GFXMMU LUT entry 607 low + 0x22f8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT607H + GFXMMU_LUT607H + GFXMMU LUT entry 607 high + 0x22fc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT608L + GFXMMU_LUT608L + GFXMMU LUT entry 608 low + 0x2300 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT608H + GFXMMU_LUT608H + GFXMMU LUT entry 608 high + 0x2304 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT609L + GFXMMU_LUT609L + GFXMMU LUT entry 609 low + 0x2308 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT609H + GFXMMU_LUT609H + GFXMMU LUT entry 609 high + 0x230c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT610L + GFXMMU_LUT610L + GFXMMU LUT entry 610 low + 0x2310 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT610H + GFXMMU_LUT610H + GFXMMU LUT entry 610 high + 0x2314 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT611L + GFXMMU_LUT611L + GFXMMU LUT entry 611 low + 0x2318 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT611H + GFXMMU_LUT611H + GFXMMU LUT entry 611 high + 0x231c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT612L + GFXMMU_LUT612L + GFXMMU LUT entry 612 low + 0x2320 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT612H + GFXMMU_LUT612H + GFXMMU LUT entry 612 high + 0x2324 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT613L + GFXMMU_LUT613L + GFXMMU LUT entry 613 low + 0x2328 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT613H + GFXMMU_LUT613H + GFXMMU LUT entry 613 high + 0x232c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT614L + GFXMMU_LUT614L + GFXMMU LUT entry 614 low + 0x2330 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT614H + GFXMMU_LUT614H + GFXMMU LUT entry 614 high + 0x2334 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT615L + GFXMMU_LUT615L + GFXMMU LUT entry 615 low + 0x2338 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT615H + GFXMMU_LUT615H + GFXMMU LUT entry 615 high + 0x233c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT616L + GFXMMU_LUT616L + GFXMMU LUT entry 616 low + 0x2340 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT616H + GFXMMU_LUT616H + GFXMMU LUT entry 616 high + 0x2344 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT617L + GFXMMU_LUT617L + GFXMMU LUT entry 617 low + 0x2348 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT617H + GFXMMU_LUT617H + GFXMMU LUT entry 617 high + 0x234c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT618L + GFXMMU_LUT618L + GFXMMU LUT entry 618 low + 0x2350 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT618H + GFXMMU_LUT618H + GFXMMU LUT entry 618 high + 0x2354 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT619L + GFXMMU_LUT619L + GFXMMU LUT entry 619 low + 0x2358 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT619H + GFXMMU_LUT619H + GFXMMU LUT entry 619 high + 0x235c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT620L + GFXMMU_LUT620L + GFXMMU LUT entry 620 low + 0x2360 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT620H + GFXMMU_LUT620H + GFXMMU LUT entry 620 high + 0x2364 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT621L + GFXMMU_LUT621L + GFXMMU LUT entry 621 low + 0x2368 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT621H + GFXMMU_LUT621H + GFXMMU LUT entry 621 high + 0x236c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT622L + GFXMMU_LUT622L + GFXMMU LUT entry 622 low + 0x2370 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT622H + GFXMMU_LUT622H + GFXMMU LUT entry 622 high + 0x2374 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT623L + GFXMMU_LUT623L + GFXMMU LUT entry 623 low + 0x2378 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT623H + GFXMMU_LUT623H + GFXMMU LUT entry 623 high + 0x237c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT624L + GFXMMU_LUT624L + GFXMMU LUT entry 624 low + 0x2380 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT624H + GFXMMU_LUT624H + GFXMMU LUT entry 624 high + 0x2384 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT625L + GFXMMU_LUT625L + GFXMMU LUT entry 625 low + 0x2388 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT625H + GFXMMU_LUT625H + GFXMMU LUT entry 625 high + 0x238c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT626L + GFXMMU_LUT626L + GFXMMU LUT entry 626 low + 0x2390 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT626H + GFXMMU_LUT626H + GFXMMU LUT entry 626 high + 0x2394 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT627L + GFXMMU_LUT627L + GFXMMU LUT entry 627 low + 0x2398 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT627H + GFXMMU_LUT627H + GFXMMU LUT entry 627 high + 0x239c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT628L + GFXMMU_LUT628L + GFXMMU LUT entry 628 low + 0x23a0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT628H + GFXMMU_LUT628H + GFXMMU LUT entry 628 high + 0x23a4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT629L + GFXMMU_LUT629L + GFXMMU LUT entry 629 low + 0x23a8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT629H + GFXMMU_LUT629H + GFXMMU LUT entry 629 high + 0x23ac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT630L + GFXMMU_LUT630L + GFXMMU LUT entry 630 low + 0x23b0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT630H + GFXMMU_LUT630H + GFXMMU LUT entry 630 high + 0x23b4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT631L + GFXMMU_LUT631L + GFXMMU LUT entry 631 low + 0x23b8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT631H + GFXMMU_LUT631H + GFXMMU LUT entry 631 high + 0x23bc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT632L + GFXMMU_LUT632L + GFXMMU LUT entry 632 low + 0x23c0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT632H + GFXMMU_LUT632H + GFXMMU LUT entry 632 high + 0x23c4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT633L + GFXMMU_LUT633L + GFXMMU LUT entry 633 low + 0x23c8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT633H + GFXMMU_LUT633H + GFXMMU LUT entry 633 high + 0x23cc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT634L + GFXMMU_LUT634L + GFXMMU LUT entry 634 low + 0x23d0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT634H + GFXMMU_LUT634H + GFXMMU LUT entry 634 high + 0x23d4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT635L + GFXMMU_LUT635L + GFXMMU LUT entry 635 low + 0x23d8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT635H + GFXMMU_LUT635H + GFXMMU LUT entry 635 high + 0x23dc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT636L + GFXMMU_LUT636L + GFXMMU LUT entry 636 low + 0x23e0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT636H + GFXMMU_LUT636H + GFXMMU LUT entry 636 high + 0x23e4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT637L + GFXMMU_LUT637L + GFXMMU LUT entry 637 low + 0x23e8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT637H + GFXMMU_LUT637H + GFXMMU LUT entry 637 high + 0x23ec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT638L + GFXMMU_LUT638L + GFXMMU LUT entry 638 low + 0x23f0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT638H + GFXMMU_LUT638H + GFXMMU LUT entry 638 high + 0x23f4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT639L + GFXMMU_LUT639L + GFXMMU LUT entry 639 low + 0x23f8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT639H + GFXMMU_LUT639H + GFXMMU LUT entry 639 high + 0x23fc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT640L + GFXMMU_LUT640L + GFXMMU LUT entry 640 low + 0x2400 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT640H + GFXMMU_LUT640H + GFXMMU LUT entry 640 high + 0x2404 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT641L + GFXMMU_LUT641L + GFXMMU LUT entry 641 low + 0x2408 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT641H + GFXMMU_LUT641H + GFXMMU LUT entry 641 high + 0x240c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT642L + GFXMMU_LUT642L + GFXMMU LUT entry 642 low + 0x2410 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT642H + GFXMMU_LUT642H + GFXMMU LUT entry 642 high + 0x2414 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT643L + GFXMMU_LUT643L + GFXMMU LUT entry 643 low + 0x2418 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT643H + GFXMMU_LUT643H + GFXMMU LUT entry 643 high + 0x241c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT644L + GFXMMU_LUT644L + GFXMMU LUT entry 644 low + 0x2420 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT644H + GFXMMU_LUT644H + GFXMMU LUT entry 644 high + 0x2424 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT645L + GFXMMU_LUT645L + GFXMMU LUT entry 645 low + 0x2428 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT645H + GFXMMU_LUT645H + GFXMMU LUT entry 645 high + 0x242c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT646L + GFXMMU_LUT646L + GFXMMU LUT entry 646 low + 0x2430 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT646H + GFXMMU_LUT646H + GFXMMU LUT entry 646 high + 0x2434 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT647L + GFXMMU_LUT647L + GFXMMU LUT entry 647 low + 0x2438 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT647H + GFXMMU_LUT647H + GFXMMU LUT entry 647 high + 0x243c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT648L + GFXMMU_LUT648L + GFXMMU LUT entry 648 low + 0x2440 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT648H + GFXMMU_LUT648H + GFXMMU LUT entry 648 high + 0x2444 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT649L + GFXMMU_LUT649L + GFXMMU LUT entry 649 low + 0x2448 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT649H + GFXMMU_LUT649H + GFXMMU LUT entry 649 high + 0x244c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT650L + GFXMMU_LUT650L + GFXMMU LUT entry 650 low + 0x2450 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT650H + GFXMMU_LUT650H + GFXMMU LUT entry 650 high + 0x2454 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT651L + GFXMMU_LUT651L + GFXMMU LUT entry 651 low + 0x2458 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT651H + GFXMMU_LUT651H + GFXMMU LUT entry 651 high + 0x245c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT652L + GFXMMU_LUT652L + GFXMMU LUT entry 652 low + 0x2460 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT652H + GFXMMU_LUT652H + GFXMMU LUT entry 652 high + 0x2464 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT653L + GFXMMU_LUT653L + GFXMMU LUT entry 653 low + 0x2468 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT653H + GFXMMU_LUT653H + GFXMMU LUT entry 653 high + 0x246c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT654L + GFXMMU_LUT654L + GFXMMU LUT entry 654 low + 0x2470 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT654H + GFXMMU_LUT654H + GFXMMU LUT entry 654 high + 0x2474 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT655L + GFXMMU_LUT655L + GFXMMU LUT entry 655 low + 0x2478 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT655H + GFXMMU_LUT655H + GFXMMU LUT entry 655 high + 0x247c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT656L + GFXMMU_LUT656L + GFXMMU LUT entry 656 low + 0x2480 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT656H + GFXMMU_LUT656H + GFXMMU LUT entry 656 high + 0x2484 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT657L + GFXMMU_LUT657L + GFXMMU LUT entry 657 low + 0x2488 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT657H + GFXMMU_LUT657H + GFXMMU LUT entry 657 high + 0x248c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT658L + GFXMMU_LUT658L + GFXMMU LUT entry 658 low + 0x2490 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT658H + GFXMMU_LUT658H + GFXMMU LUT entry 658 high + 0x2494 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT659L + GFXMMU_LUT659L + GFXMMU LUT entry 659 low + 0x2498 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT659H + GFXMMU_LUT659H + GFXMMU LUT entry 659 high + 0x249c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT660L + GFXMMU_LUT660L + GFXMMU LUT entry 660 low + 0x24a0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT660H + GFXMMU_LUT660H + GFXMMU LUT entry 660 high + 0x24a4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT661L + GFXMMU_LUT661L + GFXMMU LUT entry 661 low + 0x24a8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT661H + GFXMMU_LUT661H + GFXMMU LUT entry 661 high + 0x24ac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT662L + GFXMMU_LUT662L + GFXMMU LUT entry 662 low + 0x24b0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT662H + GFXMMU_LUT662H + GFXMMU LUT entry 662 high + 0x24b4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT663L + GFXMMU_LUT663L + GFXMMU LUT entry 663 low + 0x24b8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT663H + GFXMMU_LUT663H + GFXMMU LUT entry 663 high + 0x24bc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT664L + GFXMMU_LUT664L + GFXMMU LUT entry 664 low + 0x24c0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT664H + GFXMMU_LUT664H + GFXMMU LUT entry 664 high + 0x24c4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT665L + GFXMMU_LUT665L + GFXMMU LUT entry 665 low + 0x24c8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT665H + GFXMMU_LUT665H + GFXMMU LUT entry 665 high + 0x24cc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT666L + GFXMMU_LUT666L + GFXMMU LUT entry 666 low + 0x24d0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT666H + GFXMMU_LUT666H + GFXMMU LUT entry 666 high + 0x24d4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT667L + GFXMMU_LUT667L + GFXMMU LUT entry 667 low + 0x24d8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT667H + GFXMMU_LUT667H + GFXMMU LUT entry 667 high + 0x24dc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT668L + GFXMMU_LUT668L + GFXMMU LUT entry 668 low + 0x24e0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT668H + GFXMMU_LUT668H + GFXMMU LUT entry 668 high + 0x24e4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT669L + GFXMMU_LUT669L + GFXMMU LUT entry 669 low + 0x24e8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT669H + GFXMMU_LUT669H + GFXMMU LUT entry 669 high + 0x24ec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT670L + GFXMMU_LUT670L + GFXMMU LUT entry 670 low + 0x24f0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT670H + GFXMMU_LUT670H + GFXMMU LUT entry 670 high + 0x24f4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT671L + GFXMMU_LUT671L + GFXMMU LUT entry 671 low + 0x24f8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT671H + GFXMMU_LUT671H + GFXMMU LUT entry 671 high + 0x24fc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT672L + GFXMMU_LUT672L + GFXMMU LUT entry 672 low + 0x2500 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT672H + GFXMMU_LUT672H + GFXMMU LUT entry 672 high + 0x2504 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT673L + GFXMMU_LUT673L + GFXMMU LUT entry 673 low + 0x2508 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT673H + GFXMMU_LUT673H + GFXMMU LUT entry 673 high + 0x250c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT674L + GFXMMU_LUT674L + GFXMMU LUT entry 674 low + 0x2510 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT674H + GFXMMU_LUT674H + GFXMMU LUT entry 674 high + 0x2514 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT675L + GFXMMU_LUT675L + GFXMMU LUT entry 675 low + 0x2518 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT675H + GFXMMU_LUT675H + GFXMMU LUT entry 675 high + 0x251c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT676L + GFXMMU_LUT676L + GFXMMU LUT entry 676 low + 0x2520 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT676H + GFXMMU_LUT676H + GFXMMU LUT entry 676 high + 0x2524 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT677L + GFXMMU_LUT677L + GFXMMU LUT entry 677 low + 0x2528 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT677H + GFXMMU_LUT677H + GFXMMU LUT entry 677 high + 0x252c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT678L + GFXMMU_LUT678L + GFXMMU LUT entry 678 low + 0x2530 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT678H + GFXMMU_LUT678H + GFXMMU LUT entry 678 high + 0x2534 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT679L + GFXMMU_LUT679L + GFXMMU LUT entry 679 low + 0x2538 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT679H + GFXMMU_LUT679H + GFXMMU LUT entry 679 high + 0x253c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT680L + GFXMMU_LUT680L + GFXMMU LUT entry 680 low + 0x2540 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT680H + GFXMMU_LUT680H + GFXMMU LUT entry 680 high + 0x2544 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT681L + GFXMMU_LUT681L + GFXMMU LUT entry 681 low + 0x2548 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT681H + GFXMMU_LUT681H + GFXMMU LUT entry 681 high + 0x254c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT682L + GFXMMU_LUT682L + GFXMMU LUT entry 682 low + 0x2550 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT682H + GFXMMU_LUT682H + GFXMMU LUT entry 682 high + 0x2554 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT683L + GFXMMU_LUT683L + GFXMMU LUT entry 683 low + 0x2558 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT683H + GFXMMU_LUT683H + GFXMMU LUT entry 683 high + 0x255c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT684L + GFXMMU_LUT684L + GFXMMU LUT entry 684 low + 0x2560 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT684H + GFXMMU_LUT684H + GFXMMU LUT entry 684 high + 0x2564 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT685L + GFXMMU_LUT685L + GFXMMU LUT entry 685 low + 0x2568 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT685H + GFXMMU_LUT685H + GFXMMU LUT entry 685 high + 0x256c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT686L + GFXMMU_LUT686L + GFXMMU LUT entry 686 low + 0x2570 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT686H + GFXMMU_LUT686H + GFXMMU LUT entry 686 high + 0x2574 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT687L + GFXMMU_LUT687L + GFXMMU LUT entry 687 low + 0x2578 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT687H + GFXMMU_LUT687H + GFXMMU LUT entry 687 high + 0x257c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT688L + GFXMMU_LUT688L + GFXMMU LUT entry 688 low + 0x2580 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT688H + GFXMMU_LUT688H + GFXMMU LUT entry 688 high + 0x2584 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT689L + GFXMMU_LUT689L + GFXMMU LUT entry 689 low + 0x2588 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT689H + GFXMMU_LUT689H + GFXMMU LUT entry 689 high + 0x258c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT690L + GFXMMU_LUT690L + GFXMMU LUT entry 690 low + 0x2590 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT690H + GFXMMU_LUT690H + GFXMMU LUT entry 690 high + 0x2594 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT691L + GFXMMU_LUT691L + GFXMMU LUT entry 691 low + 0x2598 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT691H + GFXMMU_LUT691H + GFXMMU LUT entry 691 high + 0x259c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT692L + GFXMMU_LUT692L + GFXMMU LUT entry 692 low + 0x25a0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT692H + GFXMMU_LUT692H + GFXMMU LUT entry 692 high + 0x25a4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT693L + GFXMMU_LUT693L + GFXMMU LUT entry 693 low + 0x25a8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT693H + GFXMMU_LUT693H + GFXMMU LUT entry 693 high + 0x25ac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT694L + GFXMMU_LUT694L + GFXMMU LUT entry 694 low + 0x25b0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT694H + GFXMMU_LUT694H + GFXMMU LUT entry 694 high + 0x25b4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT695L + GFXMMU_LUT695L + GFXMMU LUT entry 695 low + 0x25b8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT695H + GFXMMU_LUT695H + GFXMMU LUT entry 695 high + 0x25bc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT696L + GFXMMU_LUT696L + GFXMMU LUT entry 696 low + 0x25c0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT696H + GFXMMU_LUT696H + GFXMMU LUT entry 696 high + 0x25c4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT697L + GFXMMU_LUT697L + GFXMMU LUT entry 697 low + 0x25c8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT697H + GFXMMU_LUT697H + GFXMMU LUT entry 697 high + 0x25cc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT698L + GFXMMU_LUT698L + GFXMMU LUT entry 698 low + 0x25d0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT698H + GFXMMU_LUT698H + GFXMMU LUT entry 698 high + 0x25d4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT699L + GFXMMU_LUT699L + GFXMMU LUT entry 699 low + 0x25d8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT699H + GFXMMU_LUT699H + GFXMMU LUT entry 699 high + 0x25dc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT700L + GFXMMU_LUT700L + GFXMMU LUT entry 700 low + 0x25e0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT700H + GFXMMU_LUT700H + GFXMMU LUT entry 700 high + 0x25e4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT701L + GFXMMU_LUT701L + GFXMMU LUT entry 701 low + 0x25e8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT701H + GFXMMU_LUT701H + GFXMMU LUT entry 701 high + 0x25ec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT702L + GFXMMU_LUT702L + GFXMMU LUT entry 702 low + 0x25f0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT702H + GFXMMU_LUT702H + GFXMMU LUT entry 702 high + 0x25f4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT703L + GFXMMU_LUT703L + GFXMMU LUT entry 703 low + 0x25f8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT703H + GFXMMU_LUT703H + GFXMMU LUT entry 703 high + 0x25fc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT704L + GFXMMU_LUT704L + GFXMMU LUT entry 704 low + 0x2600 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT704H + GFXMMU_LUT704H + GFXMMU LUT entry 704 high + 0x2604 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT705L + GFXMMU_LUT705L + GFXMMU LUT entry 705 low + 0x2608 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT705H + GFXMMU_LUT705H + GFXMMU LUT entry 705 high + 0x260c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT706L + GFXMMU_LUT706L + GFXMMU LUT entry 706 low + 0x2610 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT706H + GFXMMU_LUT706H + GFXMMU LUT entry 706 high + 0x2614 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT707L + GFXMMU_LUT707L + GFXMMU LUT entry 707 low + 0x2618 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT707H + GFXMMU_LUT707H + GFXMMU LUT entry 707 high + 0x261c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT708L + GFXMMU_LUT708L + GFXMMU LUT entry 708 low + 0x2620 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT708H + GFXMMU_LUT708H + GFXMMU LUT entry 708 high + 0x2624 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT709L + GFXMMU_LUT709L + GFXMMU LUT entry 709 low + 0x2628 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT709H + GFXMMU_LUT709H + GFXMMU LUT entry 709 high + 0x262c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT710L + GFXMMU_LUT710L + GFXMMU LUT entry 710 low + 0x2630 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT710H + GFXMMU_LUT710H + GFXMMU LUT entry 710 high + 0x2634 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT711L + GFXMMU_LUT711L + GFXMMU LUT entry 711 low + 0x2638 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT711H + GFXMMU_LUT711H + GFXMMU LUT entry 711 high + 0x263c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT712L + GFXMMU_LUT712L + GFXMMU LUT entry 712 low + 0x2640 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT712H + GFXMMU_LUT712H + GFXMMU LUT entry 712 high + 0x2644 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT713L + GFXMMU_LUT713L + GFXMMU LUT entry 713 low + 0x2648 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT713H + GFXMMU_LUT713H + GFXMMU LUT entry 713 high + 0x264c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT714L + GFXMMU_LUT714L + GFXMMU LUT entry 714 low + 0x2650 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT714H + GFXMMU_LUT714H + GFXMMU LUT entry 714 high + 0x2654 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT715L + GFXMMU_LUT715L + GFXMMU LUT entry 715 low + 0x2658 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT715H + GFXMMU_LUT715H + GFXMMU LUT entry 715 high + 0x265c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT716L + GFXMMU_LUT716L + GFXMMU LUT entry 716 low + 0x2660 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT716H + GFXMMU_LUT716H + GFXMMU LUT entry 716 high + 0x2664 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT717L + GFXMMU_LUT717L + GFXMMU LUT entry 717 low + 0x2668 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT717H + GFXMMU_LUT717H + GFXMMU LUT entry 717 high + 0x266c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT718L + GFXMMU_LUT718L + GFXMMU LUT entry 718 low + 0x2670 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT718H + GFXMMU_LUT718H + GFXMMU LUT entry 718 high + 0x2674 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT719L + GFXMMU_LUT719L + GFXMMU LUT entry 719 low + 0x2678 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT719H + GFXMMU_LUT719H + GFXMMU LUT entry 719 high + 0x267c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT720L + GFXMMU_LUT720L + GFXMMU LUT entry 720 low + 0x2680 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT720H + GFXMMU_LUT720H + GFXMMU LUT entry 720 high + 0x2684 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT721L + GFXMMU_LUT721L + GFXMMU LUT entry 721 low + 0x2688 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT721H + GFXMMU_LUT721H + GFXMMU LUT entry 721 high + 0x268c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT722L + GFXMMU_LUT722L + GFXMMU LUT entry 722 low + 0x2690 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT722H + GFXMMU_LUT722H + GFXMMU LUT entry 722 high + 0x2694 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT723L + GFXMMU_LUT723L + GFXMMU LUT entry 723 low + 0x2698 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT723H + GFXMMU_LUT723H + GFXMMU LUT entry 723 high + 0x269c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT724L + GFXMMU_LUT724L + GFXMMU LUT entry 724 low + 0x26a0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT724H + GFXMMU_LUT724H + GFXMMU LUT entry 724 high + 0x26a4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT725L + GFXMMU_LUT725L + GFXMMU LUT entry 725 low + 0x26a8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT725H + GFXMMU_LUT725H + GFXMMU LUT entry 725 high + 0x26ac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT726L + GFXMMU_LUT726L + GFXMMU LUT entry 726 low + 0x26b0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT726H + GFXMMU_LUT726H + GFXMMU LUT entry 726 high + 0x26b4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT727L + GFXMMU_LUT727L + GFXMMU LUT entry 727 low + 0x26b8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT727H + GFXMMU_LUT727H + GFXMMU LUT entry 727 high + 0x26bc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT728L + GFXMMU_LUT728L + GFXMMU LUT entry 728 low + 0x26c0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT728H + GFXMMU_LUT728H + GFXMMU LUT entry 728 high + 0x26c4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT729L + GFXMMU_LUT729L + GFXMMU LUT entry 729 low + 0x26c8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT729H + GFXMMU_LUT729H + GFXMMU LUT entry 729 high + 0x26cc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT730L + GFXMMU_LUT730L + GFXMMU LUT entry 730 low + 0x26d0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT730H + GFXMMU_LUT730H + GFXMMU LUT entry 730 high + 0x26d4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT731L + GFXMMU_LUT731L + GFXMMU LUT entry 731 low + 0x26d8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT731H + GFXMMU_LUT731H + GFXMMU LUT entry 731 high + 0x26dc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT732L + GFXMMU_LUT732L + GFXMMU LUT entry 732 low + 0x26e0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT732H + GFXMMU_LUT732H + GFXMMU LUT entry 732 high + 0x26e4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT733L + GFXMMU_LUT733L + GFXMMU LUT entry 733 low + 0x26e8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT733H + GFXMMU_LUT733H + GFXMMU LUT entry 733 high + 0x26ec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT734L + GFXMMU_LUT734L + GFXMMU LUT entry 734 low + 0x26f0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT734H + GFXMMU_LUT734H + GFXMMU LUT entry 734 high + 0x26f4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT735L + GFXMMU_LUT735L + GFXMMU LUT entry 735 low + 0x26f8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT735H + GFXMMU_LUT735H + GFXMMU LUT entry 735 high + 0x26fc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT736L + GFXMMU_LUT736L + GFXMMU LUT entry 736 low + 0x2700 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT736H + GFXMMU_LUT736H + GFXMMU LUT entry 736 high + 0x2704 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT737L + GFXMMU_LUT737L + GFXMMU LUT entry 737 low + 0x2708 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT737H + GFXMMU_LUT737H + GFXMMU LUT entry 737 high + 0x270c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT738L + GFXMMU_LUT738L + GFXMMU LUT entry 738 low + 0x2710 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT738H + GFXMMU_LUT738H + GFXMMU LUT entry 738 high + 0x2714 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT739L + GFXMMU_LUT739L + GFXMMU LUT entry 739 low + 0x2718 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT739H + GFXMMU_LUT739H + GFXMMU LUT entry 739 high + 0x271c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT740L + GFXMMU_LUT740L + GFXMMU LUT entry 740 low + 0x2720 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT740H + GFXMMU_LUT740H + GFXMMU LUT entry 740 high + 0x2724 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT741L + GFXMMU_LUT741L + GFXMMU LUT entry 741 low + 0x2728 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT741H + GFXMMU_LUT741H + GFXMMU LUT entry 741 high + 0x272c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT742L + GFXMMU_LUT742L + GFXMMU LUT entry 742 low + 0x2730 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT742H + GFXMMU_LUT742H + GFXMMU LUT entry 742 high + 0x2734 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT743L + GFXMMU_LUT743L + GFXMMU LUT entry 743 low + 0x2738 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT743H + GFXMMU_LUT743H + GFXMMU LUT entry 743 high + 0x273c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT744L + GFXMMU_LUT744L + GFXMMU LUT entry 744 low + 0x2740 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT744H + GFXMMU_LUT744H + GFXMMU LUT entry 744 high + 0x2744 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT745L + GFXMMU_LUT745L + GFXMMU LUT entry 745 low + 0x2748 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT745H + GFXMMU_LUT745H + GFXMMU LUT entry 745 high + 0x274c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT746L + GFXMMU_LUT746L + GFXMMU LUT entry 746 low + 0x2750 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT746H + GFXMMU_LUT746H + GFXMMU LUT entry 746 high + 0x2754 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT747L + GFXMMU_LUT747L + GFXMMU LUT entry 747 low + 0x2758 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT747H + GFXMMU_LUT747H + GFXMMU LUT entry 747 high + 0x275c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT748L + GFXMMU_LUT748L + GFXMMU LUT entry 748 low + 0x2760 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT748H + GFXMMU_LUT748H + GFXMMU LUT entry 748 high + 0x2764 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT749L + GFXMMU_LUT749L + GFXMMU LUT entry 749 low + 0x2768 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT749H + GFXMMU_LUT749H + GFXMMU LUT entry 749 high + 0x276c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT750L + GFXMMU_LUT750L + GFXMMU LUT entry 750 low + 0x2770 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT750H + GFXMMU_LUT750H + GFXMMU LUT entry 750 high + 0x2774 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT751L + GFXMMU_LUT751L + GFXMMU LUT entry 751 low + 0x2778 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT751H + GFXMMU_LUT751H + GFXMMU LUT entry 751 high + 0x277c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT752L + GFXMMU_LUT752L + GFXMMU LUT entry 752 low + 0x2780 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT752H + GFXMMU_LUT752H + GFXMMU LUT entry 752 high + 0x2784 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT753L + GFXMMU_LUT753L + GFXMMU LUT entry 753 low + 0x2788 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT753H + GFXMMU_LUT753H + GFXMMU LUT entry 753 high + 0x278c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT754L + GFXMMU_LUT754L + GFXMMU LUT entry 754 low + 0x2790 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT754H + GFXMMU_LUT754H + GFXMMU LUT entry 754 high + 0x2794 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT755L + GFXMMU_LUT755L + GFXMMU LUT entry 755 low + 0x2798 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT755H + GFXMMU_LUT755H + GFXMMU LUT entry 755 high + 0x279c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT756L + GFXMMU_LUT756L + GFXMMU LUT entry 756 low + 0x27a0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT756H + GFXMMU_LUT756H + GFXMMU LUT entry 756 high + 0x27a4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT757L + GFXMMU_LUT757L + GFXMMU LUT entry 757 low + 0x27a8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT757H + GFXMMU_LUT757H + GFXMMU LUT entry 757 high + 0x27ac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT758L + GFXMMU_LUT758L + GFXMMU LUT entry 758 low + 0x27b0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT758H + GFXMMU_LUT758H + GFXMMU LUT entry 758 high + 0x27b4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT759L + GFXMMU_LUT759L + GFXMMU LUT entry 759 low + 0x27b8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT759H + GFXMMU_LUT759H + GFXMMU LUT entry 759 high + 0x27bc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT760L + GFXMMU_LUT760L + GFXMMU LUT entry 760 low + 0x27c0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT760H + GFXMMU_LUT760H + GFXMMU LUT entry 760 high + 0x27c4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT761L + GFXMMU_LUT761L + GFXMMU LUT entry 761 low + 0x27c8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT761H + GFXMMU_LUT761H + GFXMMU LUT entry 761 high + 0x27cc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT762L + GFXMMU_LUT762L + GFXMMU LUT entry 762 low + 0x27d0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT762H + GFXMMU_LUT762H + GFXMMU LUT entry 762 high + 0x27d4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT763L + GFXMMU_LUT763L + GFXMMU LUT entry 763 low + 0x27d8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT763H + GFXMMU_LUT763H + GFXMMU LUT entry 763 high + 0x27dc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT764L + GFXMMU_LUT764L + GFXMMU LUT entry 764 low + 0x27e0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT764H + GFXMMU_LUT764H + GFXMMU LUT entry 764 high + 0x27e4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT765L + GFXMMU_LUT765L + GFXMMU LUT entry 765 low + 0x27e8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT765H + GFXMMU_LUT765H + GFXMMU LUT entry 765 high + 0x27ec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT766L + GFXMMU_LUT766L + GFXMMU LUT entry 766 low + 0x27f0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT766H + GFXMMU_LUT766H + GFXMMU LUT entry 766 high + 0x27f4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT767L + GFXMMU_LUT767L + GFXMMU LUT entry 767 low + 0x27f8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT767H + GFXMMU_LUT767H + GFXMMU LUT entry 767 high + 0x27fc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT768L + GFXMMU_LUT768L + GFXMMU LUT entry 768 low + 0x2800 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT768H + GFXMMU_LUT768H + GFXMMU LUT entry 768 high + 0x2804 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT769L + GFXMMU_LUT769L + GFXMMU LUT entry 769 low + 0x2808 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT769H + GFXMMU_LUT769H + GFXMMU LUT entry 769 high + 0x280c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT770L + GFXMMU_LUT770L + GFXMMU LUT entry 770 low + 0x2810 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT770H + GFXMMU_LUT770H + GFXMMU LUT entry 770 high + 0x2814 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT771L + GFXMMU_LUT771L + GFXMMU LUT entry 771 low + 0x2818 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT771H + GFXMMU_LUT771H + GFXMMU LUT entry 771 high + 0x281c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT772L + GFXMMU_LUT772L + GFXMMU LUT entry 772 low + 0x2820 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT772H + GFXMMU_LUT772H + GFXMMU LUT entry 772 high + 0x2824 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT773L + GFXMMU_LUT773L + GFXMMU LUT entry 773 low + 0x2828 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT773H + GFXMMU_LUT773H + GFXMMU LUT entry 773 high + 0x282c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT774L + GFXMMU_LUT774L + GFXMMU LUT entry 774 low + 0x2830 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT774H + GFXMMU_LUT774H + GFXMMU LUT entry 774 high + 0x2834 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT775L + GFXMMU_LUT775L + GFXMMU LUT entry 775 low + 0x2838 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT775H + GFXMMU_LUT775H + GFXMMU LUT entry 775 high + 0x283c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT776L + GFXMMU_LUT776L + GFXMMU LUT entry 776 low + 0x2840 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT776H + GFXMMU_LUT776H + GFXMMU LUT entry 776 high + 0x2844 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT777L + GFXMMU_LUT777L + GFXMMU LUT entry 777 low + 0x2848 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT777H + GFXMMU_LUT777H + GFXMMU LUT entry 777 high + 0x284c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT778L + GFXMMU_LUT778L + GFXMMU LUT entry 778 low + 0x2850 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT778H + GFXMMU_LUT778H + GFXMMU LUT entry 778 high + 0x2854 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT779L + GFXMMU_LUT779L + GFXMMU LUT entry 779 low + 0x2858 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT779H + GFXMMU_LUT779H + GFXMMU LUT entry 779 high + 0x285c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT780L + GFXMMU_LUT780L + GFXMMU LUT entry 780 low + 0x2860 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT780H + GFXMMU_LUT780H + GFXMMU LUT entry 780 high + 0x2864 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT781L + GFXMMU_LUT781L + GFXMMU LUT entry 781 low + 0x2868 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT781H + GFXMMU_LUT781H + GFXMMU LUT entry 781 high + 0x286c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT782L + GFXMMU_LUT782L + GFXMMU LUT entry 782 low + 0x2870 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT782H + GFXMMU_LUT782H + GFXMMU LUT entry 782 high + 0x2874 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT783L + GFXMMU_LUT783L + GFXMMU LUT entry 783 low + 0x2878 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT783H + GFXMMU_LUT783H + GFXMMU LUT entry 783 high + 0x287c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT784L + GFXMMU_LUT784L + GFXMMU LUT entry 784 low + 0x2880 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT784H + GFXMMU_LUT784H + GFXMMU LUT entry 784 high + 0x2884 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT785L + GFXMMU_LUT785L + GFXMMU LUT entry 785 low + 0x2888 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT785H + GFXMMU_LUT785H + GFXMMU LUT entry 785 high + 0x288c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT786L + GFXMMU_LUT786L + GFXMMU LUT entry 786 low + 0x2890 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT786H + GFXMMU_LUT786H + GFXMMU LUT entry 786 high + 0x2894 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT787L + GFXMMU_LUT787L + GFXMMU LUT entry 787 low + 0x2898 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT787H + GFXMMU_LUT787H + GFXMMU LUT entry 787 high + 0x289c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT788L + GFXMMU_LUT788L + GFXMMU LUT entry 788 low + 0x28a0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT788H + GFXMMU_LUT788H + GFXMMU LUT entry 788 high + 0x28a4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT789L + GFXMMU_LUT789L + GFXMMU LUT entry 789 low + 0x28a8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT789H + GFXMMU_LUT789H + GFXMMU LUT entry 789 high + 0x28ac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT790L + GFXMMU_LUT790L + GFXMMU LUT entry 790 low + 0x28b0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT790H + GFXMMU_LUT790H + GFXMMU LUT entry 790 high + 0x28b4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT791L + GFXMMU_LUT791L + GFXMMU LUT entry 791 low + 0x28b8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT791H + GFXMMU_LUT791H + GFXMMU LUT entry 791 high + 0x28bc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT792L + GFXMMU_LUT792L + GFXMMU LUT entry 792 low + 0x28c0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT792H + GFXMMU_LUT792H + GFXMMU LUT entry 792 high + 0x28c4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT793L + GFXMMU_LUT793L + GFXMMU LUT entry 793 low + 0x28c8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT793H + GFXMMU_LUT793H + GFXMMU LUT entry 793 high + 0x28cc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT794L + GFXMMU_LUT794L + GFXMMU LUT entry 794 low + 0x28d0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT794H + GFXMMU_LUT794H + GFXMMU LUT entry 794 high + 0x28d4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT795L + GFXMMU_LUT795L + GFXMMU LUT entry 795 low + 0x28d8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT795H + GFXMMU_LUT795H + GFXMMU LUT entry 795 high + 0x28dc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT796L + GFXMMU_LUT796L + GFXMMU LUT entry 796 low + 0x28e0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT796H + GFXMMU_LUT796H + GFXMMU LUT entry 796 high + 0x28e4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT797L + GFXMMU_LUT797L + GFXMMU LUT entry 797 low + 0x28e8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT797H + GFXMMU_LUT797H + GFXMMU LUT entry 797 high + 0x28ec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT798L + GFXMMU_LUT798L + GFXMMU LUT entry 798 low + 0x28f0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT798H + GFXMMU_LUT798H + GFXMMU LUT entry 798 high + 0x28f4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT799L + GFXMMU_LUT799L + GFXMMU LUT entry 799 low + 0x28f8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT799H + GFXMMU_LUT799H + GFXMMU LUT entry 799 high + 0x28fc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT800L + GFXMMU_LUT800L + GFXMMU LUT entry 800 low + 0x2900 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT800H + GFXMMU_LUT800H + GFXMMU LUT entry 800 high + 0x2904 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT801L + GFXMMU_LUT801L + GFXMMU LUT entry 801 low + 0x2908 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT801H + GFXMMU_LUT801H + GFXMMU LUT entry 801 high + 0x290c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT802L + GFXMMU_LUT802L + GFXMMU LUT entry 802 low + 0x2910 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT802H + GFXMMU_LUT802H + GFXMMU LUT entry 802 high + 0x2914 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT803L + GFXMMU_LUT803L + GFXMMU LUT entry 803 low + 0x2918 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT803H + GFXMMU_LUT803H + GFXMMU LUT entry 803 high + 0x291c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT804L + GFXMMU_LUT804L + GFXMMU LUT entry 804 low + 0x2920 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT804H + GFXMMU_LUT804H + GFXMMU LUT entry 804 high + 0x2924 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT805L + GFXMMU_LUT805L + GFXMMU LUT entry 805 low + 0x2928 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT805H + GFXMMU_LUT805H + GFXMMU LUT entry 805 high + 0x292c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT806L + GFXMMU_LUT806L + GFXMMU LUT entry 806 low + 0x2930 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT806H + GFXMMU_LUT806H + GFXMMU LUT entry 806 high + 0x2934 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT807L + GFXMMU_LUT807L + GFXMMU LUT entry 807 low + 0x2938 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT807H + GFXMMU_LUT807H + GFXMMU LUT entry 807 high + 0x293c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT808L + GFXMMU_LUT808L + GFXMMU LUT entry 808 low + 0x2940 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT808H + GFXMMU_LUT808H + GFXMMU LUT entry 808 high + 0x2944 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT809L + GFXMMU_LUT809L + GFXMMU LUT entry 809 low + 0x2948 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT809H + GFXMMU_LUT809H + GFXMMU LUT entry 809 high + 0x294c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT810L + GFXMMU_LUT810L + GFXMMU LUT entry 810 low + 0x2950 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT810H + GFXMMU_LUT810H + GFXMMU LUT entry 810 high + 0x2954 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT811L + GFXMMU_LUT811L + GFXMMU LUT entry 811 low + 0x2958 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT811H + GFXMMU_LUT811H + GFXMMU LUT entry 811 high + 0x295c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT812L + GFXMMU_LUT812L + GFXMMU LUT entry 812 low + 0x2960 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT812H + GFXMMU_LUT812H + GFXMMU LUT entry 812 high + 0x2964 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT813L + GFXMMU_LUT813L + GFXMMU LUT entry 813 low + 0x2968 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT813H + GFXMMU_LUT813H + GFXMMU LUT entry 813 high + 0x296c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT814L + GFXMMU_LUT814L + GFXMMU LUT entry 814 low + 0x2970 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT814H + GFXMMU_LUT814H + GFXMMU LUT entry 814 high + 0x2974 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT815L + GFXMMU_LUT815L + GFXMMU LUT entry 815 low + 0x2978 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT815H + GFXMMU_LUT815H + GFXMMU LUT entry 815 high + 0x297c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT816L + GFXMMU_LUT816L + GFXMMU LUT entry 816 low + 0x2980 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT816H + GFXMMU_LUT816H + GFXMMU LUT entry 816 high + 0x2984 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT817L + GFXMMU_LUT817L + GFXMMU LUT entry 817 low + 0x2988 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT817H + GFXMMU_LUT817H + GFXMMU LUT entry 817 high + 0x298c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT818L + GFXMMU_LUT818L + GFXMMU LUT entry 818 low + 0x2990 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT818H + GFXMMU_LUT818H + GFXMMU LUT entry 818 high + 0x2994 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT819L + GFXMMU_LUT819L + GFXMMU LUT entry 819 low + 0x2998 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT819H + GFXMMU_LUT819H + GFXMMU LUT entry 819 high + 0x299c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT820L + GFXMMU_LUT820L + GFXMMU LUT entry 820 low + 0x29a0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT820H + GFXMMU_LUT820H + GFXMMU LUT entry 820 high + 0x29a4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT821L + GFXMMU_LUT821L + GFXMMU LUT entry 821 low + 0x29a8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT821H + GFXMMU_LUT821H + GFXMMU LUT entry 821 high + 0x29ac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT822L + GFXMMU_LUT822L + GFXMMU LUT entry 822 low + 0x29b0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT822H + GFXMMU_LUT822H + GFXMMU LUT entry 822 high + 0x29b4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT823L + GFXMMU_LUT823L + GFXMMU LUT entry 823 low + 0x29b8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT823H + GFXMMU_LUT823H + GFXMMU LUT entry 823 high + 0x29bc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT824L + GFXMMU_LUT824L + GFXMMU LUT entry 824 low + 0x29c0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT824H + GFXMMU_LUT824H + GFXMMU LUT entry 824 high + 0x29c4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT825L + GFXMMU_LUT825L + GFXMMU LUT entry 825 low + 0x29c8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT825H + GFXMMU_LUT825H + GFXMMU LUT entry 825 high + 0x29cc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT826L + GFXMMU_LUT826L + GFXMMU LUT entry 826 low + 0x29d0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT826H + GFXMMU_LUT826H + GFXMMU LUT entry 826 high + 0x29d4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT827L + GFXMMU_LUT827L + GFXMMU LUT entry 827 low + 0x29d8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT827H + GFXMMU_LUT827H + GFXMMU LUT entry 827 high + 0x29dc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT828L + GFXMMU_LUT828L + GFXMMU LUT entry 828 low + 0x29e0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT828H + GFXMMU_LUT828H + GFXMMU LUT entry 828 high + 0x29e4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT829L + GFXMMU_LUT829L + GFXMMU LUT entry 829 low + 0x29e8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT829H + GFXMMU_LUT829H + GFXMMU LUT entry 829 high + 0x29ec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT830L + GFXMMU_LUT830L + GFXMMU LUT entry 830 low + 0x29f0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT830H + GFXMMU_LUT830H + GFXMMU LUT entry 830 high + 0x29f4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT831L + GFXMMU_LUT831L + GFXMMU LUT entry 831 low + 0x29f8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT831H + GFXMMU_LUT831H + GFXMMU LUT entry 831 high + 0x29fc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT832L + GFXMMU_LUT832L + GFXMMU LUT entry 832 low + 0x2a00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT832H + GFXMMU_LUT832H + GFXMMU LUT entry 832 high + 0x2a04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT833L + GFXMMU_LUT833L + GFXMMU LUT entry 833 low + 0x2a08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT833H + GFXMMU_LUT833H + GFXMMU LUT entry 833 high + 0x2a0c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT834L + GFXMMU_LUT834L + GFXMMU LUT entry 834 low + 0x2a10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT834H + GFXMMU_LUT834H + GFXMMU LUT entry 834 high + 0x2a14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT835L + GFXMMU_LUT835L + GFXMMU LUT entry 835 low + 0x2a18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT835H + GFXMMU_LUT835H + GFXMMU LUT entry 835 high + 0x2a1c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT836L + GFXMMU_LUT836L + GFXMMU LUT entry 836 low + 0x2a20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT836H + GFXMMU_LUT836H + GFXMMU LUT entry 836 high + 0x2a24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT837L + GFXMMU_LUT837L + GFXMMU LUT entry 837 low + 0x2a28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT837H + GFXMMU_LUT837H + GFXMMU LUT entry 837 high + 0x2a2c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT838L + GFXMMU_LUT838L + GFXMMU LUT entry 838 low + 0x2a30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT838H + GFXMMU_LUT838H + GFXMMU LUT entry 838 high + 0x2a34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT839L + GFXMMU_LUT839L + GFXMMU LUT entry 839 low + 0x2a38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT839H + GFXMMU_LUT839H + GFXMMU LUT entry 839 high + 0x2a3c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT840L + GFXMMU_LUT840L + GFXMMU LUT entry 840 low + 0x2a40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT840H + GFXMMU_LUT840H + GFXMMU LUT entry 840 high + 0x2a44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT841L + GFXMMU_LUT841L + GFXMMU LUT entry 841 low + 0x2a48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT841H + GFXMMU_LUT841H + GFXMMU LUT entry 841 high + 0x2a4c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT842L + GFXMMU_LUT842L + GFXMMU LUT entry 842 low + 0x2a50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT842H + GFXMMU_LUT842H + GFXMMU LUT entry 842 high + 0x2a54 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT843L + GFXMMU_LUT843L + GFXMMU LUT entry 843 low + 0x2a58 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT843H + GFXMMU_LUT843H + GFXMMU LUT entry 843 high + 0x2a5c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT844L + GFXMMU_LUT844L + GFXMMU LUT entry 844 low + 0x2a60 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT844H + GFXMMU_LUT844H + GFXMMU LUT entry 844 high + 0x2a64 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT845L + GFXMMU_LUT845L + GFXMMU LUT entry 845 low + 0x2a68 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT845H + GFXMMU_LUT845H + GFXMMU LUT entry 845 high + 0x2a6c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT846L + GFXMMU_LUT846L + GFXMMU LUT entry 846 low + 0x2a70 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT846H + GFXMMU_LUT846H + GFXMMU LUT entry 846 high + 0x2a74 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT847L + GFXMMU_LUT847L + GFXMMU LUT entry 847 low + 0x2a78 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT847H + GFXMMU_LUT847H + GFXMMU LUT entry 847 high + 0x2a7c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT848L + GFXMMU_LUT848L + GFXMMU LUT entry 848 low + 0x2a80 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT848H + GFXMMU_LUT848H + GFXMMU LUT entry 848 high + 0x2a84 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT849L + GFXMMU_LUT849L + GFXMMU LUT entry 849 low + 0x2a88 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT849H + GFXMMU_LUT849H + GFXMMU LUT entry 849 high + 0x2a8c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT850L + GFXMMU_LUT850L + GFXMMU LUT entry 850 low + 0x2a90 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT850H + GFXMMU_LUT850H + GFXMMU LUT entry 850 high + 0x2a94 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT851L + GFXMMU_LUT851L + GFXMMU LUT entry 851 low + 0x2a98 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT851H + GFXMMU_LUT851H + GFXMMU LUT entry 851 high + 0x2a9c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT852L + GFXMMU_LUT852L + GFXMMU LUT entry 852 low + 0x2aa0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT852H + GFXMMU_LUT852H + GFXMMU LUT entry 852 high + 0x2aa4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT853L + GFXMMU_LUT853L + GFXMMU LUT entry 853 low + 0x2aa8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT853H + GFXMMU_LUT853H + GFXMMU LUT entry 853 high + 0x2aac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT854L + GFXMMU_LUT854L + GFXMMU LUT entry 854 low + 0x2ab0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT854H + GFXMMU_LUT854H + GFXMMU LUT entry 854 high + 0x2ab4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT855L + GFXMMU_LUT855L + GFXMMU LUT entry 855 low + 0x2ab8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT855H + GFXMMU_LUT855H + GFXMMU LUT entry 855 high + 0x2abc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT856L + GFXMMU_LUT856L + GFXMMU LUT entry 856 low + 0x2ac0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT856H + GFXMMU_LUT856H + GFXMMU LUT entry 856 high + 0x2ac4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT857L + GFXMMU_LUT857L + GFXMMU LUT entry 857 low + 0x2ac8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT857H + GFXMMU_LUT857H + GFXMMU LUT entry 857 high + 0x2acc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT858L + GFXMMU_LUT858L + GFXMMU LUT entry 858 low + 0x2ad0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT858H + GFXMMU_LUT858H + GFXMMU LUT entry 858 high + 0x2ad4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT859L + GFXMMU_LUT859L + GFXMMU LUT entry 859 low + 0x2ad8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT859H + GFXMMU_LUT859H + GFXMMU LUT entry 859 high + 0x2adc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT860L + GFXMMU_LUT860L + GFXMMU LUT entry 860 low + 0x2ae0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT860H + GFXMMU_LUT860H + GFXMMU LUT entry 860 high + 0x2ae4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT861L + GFXMMU_LUT861L + GFXMMU LUT entry 861 low + 0x2ae8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT861H + GFXMMU_LUT861H + GFXMMU LUT entry 861 high + 0x2aec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT862L + GFXMMU_LUT862L + GFXMMU LUT entry 862 low + 0x2af0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT862H + GFXMMU_LUT862H + GFXMMU LUT entry 862 high + 0x2af4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT863L + GFXMMU_LUT863L + GFXMMU LUT entry 863 low + 0x2af8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT863H + GFXMMU_LUT863H + GFXMMU LUT entry 863 high + 0x2afc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT864L + GFXMMU_LUT864L + GFXMMU LUT entry 864 low + 0x2b00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT864H + GFXMMU_LUT864H + GFXMMU LUT entry 864 high + 0x2b04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT865L + GFXMMU_LUT865L + GFXMMU LUT entry 865 low + 0x2b08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT865H + GFXMMU_LUT865H + GFXMMU LUT entry 865 high + 0x2b0c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT866L + GFXMMU_LUT866L + GFXMMU LUT entry 866 low + 0x2b10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT866H + GFXMMU_LUT866H + GFXMMU LUT entry 866 high + 0x2b14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT867L + GFXMMU_LUT867L + GFXMMU LUT entry 867 low + 0x2b18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT867H + GFXMMU_LUT867H + GFXMMU LUT entry 867 high + 0x2b1c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT868L + GFXMMU_LUT868L + GFXMMU LUT entry 868 low + 0x2b20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT868H + GFXMMU_LUT868H + GFXMMU LUT entry 868 high + 0x2b24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT869L + GFXMMU_LUT869L + GFXMMU LUT entry 869 low + 0x2b28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT869H + GFXMMU_LUT869H + GFXMMU LUT entry 869 high + 0x2b2c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT870L + GFXMMU_LUT870L + GFXMMU LUT entry 870 low + 0x2b30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT870H + GFXMMU_LUT870H + GFXMMU LUT entry 870 high + 0x2b34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT871L + GFXMMU_LUT871L + GFXMMU LUT entry 871 low + 0x2b38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT871H + GFXMMU_LUT871H + GFXMMU LUT entry 871 high + 0x2b3c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT872L + GFXMMU_LUT872L + GFXMMU LUT entry 872 low + 0x2b40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT872H + GFXMMU_LUT872H + GFXMMU LUT entry 872 high + 0x2b44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT873L + GFXMMU_LUT873L + GFXMMU LUT entry 873 low + 0x2b48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT873H + GFXMMU_LUT873H + GFXMMU LUT entry 873 high + 0x2b4c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT874L + GFXMMU_LUT874L + GFXMMU LUT entry 874 low + 0x2b50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT874H + GFXMMU_LUT874H + GFXMMU LUT entry 874 high + 0x2b54 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT875L + GFXMMU_LUT875L + GFXMMU LUT entry 875 low + 0x2b58 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT875H + GFXMMU_LUT875H + GFXMMU LUT entry 875 high + 0x2b5c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT876L + GFXMMU_LUT876L + GFXMMU LUT entry 876 low + 0x2b60 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT876H + GFXMMU_LUT876H + GFXMMU LUT entry 876 high + 0x2b64 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT877L + GFXMMU_LUT877L + GFXMMU LUT entry 877 low + 0x2b68 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT877H + GFXMMU_LUT877H + GFXMMU LUT entry 877 high + 0x2b6c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT878L + GFXMMU_LUT878L + GFXMMU LUT entry 878 low + 0x2b70 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT878H + GFXMMU_LUT878H + GFXMMU LUT entry 878 high + 0x2b74 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT879L + GFXMMU_LUT879L + GFXMMU LUT entry 879 low + 0x2b78 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT879H + GFXMMU_LUT879H + GFXMMU LUT entry 879 high + 0x2b7c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT880L + GFXMMU_LUT880L + GFXMMU LUT entry 880 low + 0x2b80 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT880H + GFXMMU_LUT880H + GFXMMU LUT entry 880 high + 0x2b84 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT881L + GFXMMU_LUT881L + GFXMMU LUT entry 881 low + 0x2b88 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT881H + GFXMMU_LUT881H + GFXMMU LUT entry 881 high + 0x2b8c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT882L + GFXMMU_LUT882L + GFXMMU LUT entry 882 low + 0x2b90 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT882H + GFXMMU_LUT882H + GFXMMU LUT entry 882 high + 0x2b94 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT883L + GFXMMU_LUT883L + GFXMMU LUT entry 883 low + 0x2b98 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT883H + GFXMMU_LUT883H + GFXMMU LUT entry 883 high + 0x2b9c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT884L + GFXMMU_LUT884L + GFXMMU LUT entry 884 low + 0x2ba0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT884H + GFXMMU_LUT884H + GFXMMU LUT entry 884 high + 0x2ba4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT885L + GFXMMU_LUT885L + GFXMMU LUT entry 885 low + 0x2ba8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT885H + GFXMMU_LUT885H + GFXMMU LUT entry 885 high + 0x2bac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT886L + GFXMMU_LUT886L + GFXMMU LUT entry 886 low + 0x2bb0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT886H + GFXMMU_LUT886H + GFXMMU LUT entry 886 high + 0x2bb4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT887L + GFXMMU_LUT887L + GFXMMU LUT entry 887 low + 0x2bb8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT887H + GFXMMU_LUT887H + GFXMMU LUT entry 887 high + 0x2bbc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT888L + GFXMMU_LUT888L + GFXMMU LUT entry 888 low + 0x2bc0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT888H + GFXMMU_LUT888H + GFXMMU LUT entry 888 high + 0x2bc4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT889L + GFXMMU_LUT889L + GFXMMU LUT entry 889 low + 0x2bc8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT889H + GFXMMU_LUT889H + GFXMMU LUT entry 889 high + 0x2bcc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT890L + GFXMMU_LUT890L + GFXMMU LUT entry 890 low + 0x2bd0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT890H + GFXMMU_LUT890H + GFXMMU LUT entry 890 high + 0x2bd4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT891L + GFXMMU_LUT891L + GFXMMU LUT entry 891 low + 0x2bd8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT891H + GFXMMU_LUT891H + GFXMMU LUT entry 891 high + 0x2bdc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT892L + GFXMMU_LUT892L + GFXMMU LUT entry 892 low + 0x2be0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT892H + GFXMMU_LUT892H + GFXMMU LUT entry 892 high + 0x2be4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT893L + GFXMMU_LUT893L + GFXMMU LUT entry 893 low + 0x2be8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT893H + GFXMMU_LUT893H + GFXMMU LUT entry 893 high + 0x2bec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT894L + GFXMMU_LUT894L + GFXMMU LUT entry 894 low + 0x2bf0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT894H + GFXMMU_LUT894H + GFXMMU LUT entry 894 high + 0x2bf4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT895L + GFXMMU_LUT895L + GFXMMU LUT entry 895 low + 0x2bf8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT895H + GFXMMU_LUT895H + GFXMMU LUT entry 895 high + 0x2bfc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT896L + GFXMMU_LUT896L + GFXMMU LUT entry 896 low + 0x2c00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT896H + GFXMMU_LUT896H + GFXMMU LUT entry 896 high + 0x2c04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT897L + GFXMMU_LUT897L + GFXMMU LUT entry 897 low + 0x2c08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT897H + GFXMMU_LUT897H + GFXMMU LUT entry 897 high + 0x2c0c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT898L + GFXMMU_LUT898L + GFXMMU LUT entry 898 low + 0x2c10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT898H + GFXMMU_LUT898H + GFXMMU LUT entry 898 high + 0x2c14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT899L + GFXMMU_LUT899L + GFXMMU LUT entry 899 low + 0x2c18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT899H + GFXMMU_LUT899H + GFXMMU LUT entry 899 high + 0x2c1c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT900L + GFXMMU_LUT900L + GFXMMU LUT entry 900 low + 0x2c20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT900H + GFXMMU_LUT900H + GFXMMU LUT entry 900 high + 0x2c24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT901L + GFXMMU_LUT901L + GFXMMU LUT entry 901 low + 0x2c28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT901H + GFXMMU_LUT901H + GFXMMU LUT entry 901 high + 0x2c2c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT902L + GFXMMU_LUT902L + GFXMMU LUT entry 902 low + 0x2c30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT902H + GFXMMU_LUT902H + GFXMMU LUT entry 902 high + 0x2c34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT903L + GFXMMU_LUT903L + GFXMMU LUT entry 903 low + 0x2c38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT903H + GFXMMU_LUT903H + GFXMMU LUT entry 903 high + 0x2c3c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT904L + GFXMMU_LUT904L + GFXMMU LUT entry 904 low + 0x2c40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT904H + GFXMMU_LUT904H + GFXMMU LUT entry 904 high + 0x2c44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT905L + GFXMMU_LUT905L + GFXMMU LUT entry 905 low + 0x2c48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT905H + GFXMMU_LUT905H + GFXMMU LUT entry 905 high + 0x2c4c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT906L + GFXMMU_LUT906L + GFXMMU LUT entry 906 low + 0x2c50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT906H + GFXMMU_LUT906H + GFXMMU LUT entry 906 high + 0x2c54 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT907L + GFXMMU_LUT907L + GFXMMU LUT entry 907 low + 0x2c58 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT907H + GFXMMU_LUT907H + GFXMMU LUT entry 907 high + 0x2c5c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT908L + GFXMMU_LUT908L + GFXMMU LUT entry 908 low + 0x2c60 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT908H + GFXMMU_LUT908H + GFXMMU LUT entry 908 high + 0x2c64 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT909L + GFXMMU_LUT909L + GFXMMU LUT entry 909 low + 0x2c68 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT909H + GFXMMU_LUT909H + GFXMMU LUT entry 909 high + 0x2c6c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT910L + GFXMMU_LUT910L + GFXMMU LUT entry 910 low + 0x2c70 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT910H + GFXMMU_LUT910H + GFXMMU LUT entry 910 high + 0x2c74 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT911L + GFXMMU_LUT911L + GFXMMU LUT entry 911 low + 0x2c78 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT911H + GFXMMU_LUT911H + GFXMMU LUT entry 911 high + 0x2c7c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT912L + GFXMMU_LUT912L + GFXMMU LUT entry 912 low + 0x2c80 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT912H + GFXMMU_LUT912H + GFXMMU LUT entry 912 high + 0x2c84 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT913L + GFXMMU_LUT913L + GFXMMU LUT entry 913 low + 0x2c88 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT913H + GFXMMU_LUT913H + GFXMMU LUT entry 913 high + 0x2c8c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT914L + GFXMMU_LUT914L + GFXMMU LUT entry 914 low + 0x2c90 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT914H + GFXMMU_LUT914H + GFXMMU LUT entry 914 high + 0x2c94 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT915L + GFXMMU_LUT915L + GFXMMU LUT entry 915 low + 0x2c98 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT915H + GFXMMU_LUT915H + GFXMMU LUT entry 915 high + 0x2c9c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT916L + GFXMMU_LUT916L + GFXMMU LUT entry 916 low + 0x2ca0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT916H + GFXMMU_LUT916H + GFXMMU LUT entry 916 high + 0x2ca4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT917L + GFXMMU_LUT917L + GFXMMU LUT entry 917 low + 0x2ca8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT917H + GFXMMU_LUT917H + GFXMMU LUT entry 917 high + 0x2cac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT918L + GFXMMU_LUT918L + GFXMMU LUT entry 918 low + 0x2cb0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT918H + GFXMMU_LUT918H + GFXMMU LUT entry 918 high + 0x2cb4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT919L + GFXMMU_LUT919L + GFXMMU LUT entry 919 low + 0x2cb8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT919H + GFXMMU_LUT919H + GFXMMU LUT entry 919 high + 0x2cbc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT920L + GFXMMU_LUT920L + GFXMMU LUT entry 920 low + 0x2cc0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT920H + GFXMMU_LUT920H + GFXMMU LUT entry 920 high + 0x2cc4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT921L + GFXMMU_LUT921L + GFXMMU LUT entry 921 low + 0x2cc8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT921H + GFXMMU_LUT921H + GFXMMU LUT entry 921 high + 0x2ccc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT922L + GFXMMU_LUT922L + GFXMMU LUT entry 922 low + 0x2cd0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT922H + GFXMMU_LUT922H + GFXMMU LUT entry 922 high + 0x2cd4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT923L + GFXMMU_LUT923L + GFXMMU LUT entry 923 low + 0x2cd8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT923H + GFXMMU_LUT923H + GFXMMU LUT entry 923 high + 0x2cdc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT924L + GFXMMU_LUT924L + GFXMMU LUT entry 924 low + 0x2ce0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT924H + GFXMMU_LUT924H + GFXMMU LUT entry 924 high + 0x2ce4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT925L + GFXMMU_LUT925L + GFXMMU LUT entry 925 low + 0x2ce8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT925H + GFXMMU_LUT925H + GFXMMU LUT entry 925 high + 0x2cec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT926L + GFXMMU_LUT926L + GFXMMU LUT entry 926 low + 0x2cf0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT926H + GFXMMU_LUT926H + GFXMMU LUT entry 926 high + 0x2cf4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT927L + GFXMMU_LUT927L + GFXMMU LUT entry 927 low + 0x2cf8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT927H + GFXMMU_LUT927H + GFXMMU LUT entry 927 high + 0x2cfc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT928L + GFXMMU_LUT928L + GFXMMU LUT entry 928 low + 0x2d00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT928H + GFXMMU_LUT928H + GFXMMU LUT entry 928 high + 0x2d04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT929L + GFXMMU_LUT929L + GFXMMU LUT entry 929 low + 0x2d08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT929H + GFXMMU_LUT929H + GFXMMU LUT entry 929 high + 0x2d0c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT930L + GFXMMU_LUT930L + GFXMMU LUT entry 930 low + 0x2d10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT930H + GFXMMU_LUT930H + GFXMMU LUT entry 930 high + 0x2d14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT931L + GFXMMU_LUT931L + GFXMMU LUT entry 931 low + 0x2d18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT931H + GFXMMU_LUT931H + GFXMMU LUT entry 931 high + 0x2d1c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT932L + GFXMMU_LUT932L + GFXMMU LUT entry 932 low + 0x2d20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT932H + GFXMMU_LUT932H + GFXMMU LUT entry 932 high + 0x2d24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT933L + GFXMMU_LUT933L + GFXMMU LUT entry 933 low + 0x2d28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT933H + GFXMMU_LUT933H + GFXMMU LUT entry 933 high + 0x2d2c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT934L + GFXMMU_LUT934L + GFXMMU LUT entry 934 low + 0x2d30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT934H + GFXMMU_LUT934H + GFXMMU LUT entry 934 high + 0x2d34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT935L + GFXMMU_LUT935L + GFXMMU LUT entry 935 low + 0x2d38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT935H + GFXMMU_LUT935H + GFXMMU LUT entry 935 high + 0x2d3c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT936L + GFXMMU_LUT936L + GFXMMU LUT entry 936 low + 0x2d40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT936H + GFXMMU_LUT936H + GFXMMU LUT entry 936 high + 0x2d44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT937L + GFXMMU_LUT937L + GFXMMU LUT entry 937 low + 0x2d48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT937H + GFXMMU_LUT937H + GFXMMU LUT entry 937 high + 0x2d4c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT938L + GFXMMU_LUT938L + GFXMMU LUT entry 938 low + 0x2d50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT938H + GFXMMU_LUT938H + GFXMMU LUT entry 938 high + 0x2d54 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT939L + GFXMMU_LUT939L + GFXMMU LUT entry 939 low + 0x2d58 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT939H + GFXMMU_LUT939H + GFXMMU LUT entry 939 high + 0x2d5c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT940L + GFXMMU_LUT940L + GFXMMU LUT entry 940 low + 0x2d60 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT940H + GFXMMU_LUT940H + GFXMMU LUT entry 940 high + 0x2d64 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT941L + GFXMMU_LUT941L + GFXMMU LUT entry 941 low + 0x2d68 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT941H + GFXMMU_LUT941H + GFXMMU LUT entry 941 high + 0x2d6c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT942L + GFXMMU_LUT942L + GFXMMU LUT entry 942 low + 0x2d70 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT942H + GFXMMU_LUT942H + GFXMMU LUT entry 942 high + 0x2d74 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT943L + GFXMMU_LUT943L + GFXMMU LUT entry 943 low + 0x2d78 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT943H + GFXMMU_LUT943H + GFXMMU LUT entry 943 high + 0x2d7c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT944L + GFXMMU_LUT944L + GFXMMU LUT entry 944 low + 0x2d80 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT944H + GFXMMU_LUT944H + GFXMMU LUT entry 944 high + 0x2d84 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT945L + GFXMMU_LUT945L + GFXMMU LUT entry 945 low + 0x2d88 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT945H + GFXMMU_LUT945H + GFXMMU LUT entry 945 high + 0x2d8c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT946L + GFXMMU_LUT946L + GFXMMU LUT entry 946 low + 0x2d90 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT946H + GFXMMU_LUT946H + GFXMMU LUT entry 946 high + 0x2d94 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT947L + GFXMMU_LUT947L + GFXMMU LUT entry 947 low + 0x2d98 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT947H + GFXMMU_LUT947H + GFXMMU LUT entry 947 high + 0x2d9c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT948L + GFXMMU_LUT948L + GFXMMU LUT entry 948 low + 0x2da0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT948H + GFXMMU_LUT948H + GFXMMU LUT entry 948 high + 0x2da4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT949L + GFXMMU_LUT949L + GFXMMU LUT entry 949 low + 0x2da8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT949H + GFXMMU_LUT949H + GFXMMU LUT entry 949 high + 0x2dac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT950L + GFXMMU_LUT950L + GFXMMU LUT entry 950 low + 0x2db0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT950H + GFXMMU_LUT950H + GFXMMU LUT entry 950 high + 0x2db4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT951L + GFXMMU_LUT951L + GFXMMU LUT entry 951 low + 0x2db8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT951H + GFXMMU_LUT951H + GFXMMU LUT entry 951 high + 0x2dbc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT952L + GFXMMU_LUT952L + GFXMMU LUT entry 952 low + 0x2dc0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT952H + GFXMMU_LUT952H + GFXMMU LUT entry 952 high + 0x2dc4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT953L + GFXMMU_LUT953L + GFXMMU LUT entry 953 low + 0x2dc8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT953H + GFXMMU_LUT953H + GFXMMU LUT entry 953 high + 0x2dcc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT954L + GFXMMU_LUT954L + GFXMMU LUT entry 954 low + 0x2dd0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT954H + GFXMMU_LUT954H + GFXMMU LUT entry 954 high + 0x2dd4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT955L + GFXMMU_LUT955L + GFXMMU LUT entry 955 low + 0x2dd8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT955H + GFXMMU_LUT955H + GFXMMU LUT entry 955 high + 0x2ddc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT956L + GFXMMU_LUT956L + GFXMMU LUT entry 956 low + 0x2de0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT956H + GFXMMU_LUT956H + GFXMMU LUT entry 956 high + 0x2de4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT957L + GFXMMU_LUT957L + GFXMMU LUT entry 957 low + 0x2de8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT957H + GFXMMU_LUT957H + GFXMMU LUT entry 957 high + 0x2dec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT958L + GFXMMU_LUT958L + GFXMMU LUT entry 958 low + 0x2df0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT958H + GFXMMU_LUT958H + GFXMMU LUT entry 958 high + 0x2df4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT959L + GFXMMU_LUT959L + GFXMMU LUT entry 959 low + 0x2df8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT959H + GFXMMU_LUT959H + GFXMMU LUT entry 959 high + 0x2dfc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT960L + GFXMMU_LUT960L + GFXMMU LUT entry 960 low + 0x2e00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT960H + GFXMMU_LUT960H + GFXMMU LUT entry 960 high + 0x2e04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT961L + GFXMMU_LUT961L + GFXMMU LUT entry 961 low + 0x2e08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT961H + GFXMMU_LUT961H + GFXMMU LUT entry 961 high + 0x2e0c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT962L + GFXMMU_LUT962L + GFXMMU LUT entry 962 low + 0x2e10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT962H + GFXMMU_LUT962H + GFXMMU LUT entry 962 high + 0x2e14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT963L + GFXMMU_LUT963L + GFXMMU LUT entry 963 low + 0x2e18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT963H + GFXMMU_LUT963H + GFXMMU LUT entry 963 high + 0x2e1c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT964L + GFXMMU_LUT964L + GFXMMU LUT entry 964 low + 0x2e20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT964H + GFXMMU_LUT964H + GFXMMU LUT entry 964 high + 0x2e24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT965L + GFXMMU_LUT965L + GFXMMU LUT entry 965 low + 0x2e28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT965H + GFXMMU_LUT965H + GFXMMU LUT entry 965 high + 0x2e2c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT966L + GFXMMU_LUT966L + GFXMMU LUT entry 966 low + 0x2e30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT966H + GFXMMU_LUT966H + GFXMMU LUT entry 966 high + 0x2e34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT967L + GFXMMU_LUT967L + GFXMMU LUT entry 967 low + 0x2e38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT967H + GFXMMU_LUT967H + GFXMMU LUT entry 967 high + 0x2e3c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT968L + GFXMMU_LUT968L + GFXMMU LUT entry 968 low + 0x2e40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT968H + GFXMMU_LUT968H + GFXMMU LUT entry 968 high + 0x2e44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT969L + GFXMMU_LUT969L + GFXMMU LUT entry 969 low + 0x2e48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT969H + GFXMMU_LUT969H + GFXMMU LUT entry 969 high + 0x2e4c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT970L + GFXMMU_LUT970L + GFXMMU LUT entry 970 low + 0x2e50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT970H + GFXMMU_LUT970H + GFXMMU LUT entry 970 high + 0x2e54 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT971L + GFXMMU_LUT971L + GFXMMU LUT entry 971 low + 0x2e58 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT971H + GFXMMU_LUT971H + GFXMMU LUT entry 971 high + 0x2e5c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT972L + GFXMMU_LUT972L + GFXMMU LUT entry 972 low + 0x2e60 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT972H + GFXMMU_LUT972H + GFXMMU LUT entry 972 high + 0x2e64 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT973L + GFXMMU_LUT973L + GFXMMU LUT entry 973 low + 0x2e68 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT973H + GFXMMU_LUT973H + GFXMMU LUT entry 973 high + 0x2e6c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT974L + GFXMMU_LUT974L + GFXMMU LUT entry 974 low + 0x2e70 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT974H + GFXMMU_LUT974H + GFXMMU LUT entry 974 high + 0x2e74 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT975L + GFXMMU_LUT975L + GFXMMU LUT entry 975 low + 0x2e78 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT975H + GFXMMU_LUT975H + GFXMMU LUT entry 975 high + 0x2e7c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT976L + GFXMMU_LUT976L + GFXMMU LUT entry 976 low + 0x2e80 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT976H + GFXMMU_LUT976H + GFXMMU LUT entry 976 high + 0x2e84 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT977L + GFXMMU_LUT977L + GFXMMU LUT entry 977 low + 0x2e88 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT977H + GFXMMU_LUT977H + GFXMMU LUT entry 977 high + 0x2e8c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT978L + GFXMMU_LUT978L + GFXMMU LUT entry 978 low + 0x2e90 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT978H + GFXMMU_LUT978H + GFXMMU LUT entry 978 high + 0x2e94 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT979L + GFXMMU_LUT979L + GFXMMU LUT entry 979 low + 0x2e98 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT979H + GFXMMU_LUT979H + GFXMMU LUT entry 979 high + 0x2e9c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT980L + GFXMMU_LUT980L + GFXMMU LUT entry 980 low + 0x2ea0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT980H + GFXMMU_LUT980H + GFXMMU LUT entry 980 high + 0x2ea4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT981L + GFXMMU_LUT981L + GFXMMU LUT entry 981 low + 0x2ea8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT981H + GFXMMU_LUT981H + GFXMMU LUT entry 981 high + 0x2eac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT982L + GFXMMU_LUT982L + GFXMMU LUT entry 982 low + 0x2eb0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT982H + GFXMMU_LUT982H + GFXMMU LUT entry 982 high + 0x2eb4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT983L + GFXMMU_LUT983L + GFXMMU LUT entry 983 low + 0x2eb8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT983H + GFXMMU_LUT983H + GFXMMU LUT entry 983 high + 0x2ebc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT984L + GFXMMU_LUT984L + GFXMMU LUT entry 984 low + 0x2ec0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT984H + GFXMMU_LUT984H + GFXMMU LUT entry 984 high + 0x2ec4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT985L + GFXMMU_LUT985L + GFXMMU LUT entry 985 low + 0x2ec8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT985H + GFXMMU_LUT985H + GFXMMU LUT entry 985 high + 0x2ecc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT986L + GFXMMU_LUT986L + GFXMMU LUT entry 986 low + 0x2ed0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT986H + GFXMMU_LUT986H + GFXMMU LUT entry 986 high + 0x2ed4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT987L + GFXMMU_LUT987L + GFXMMU LUT entry 987 low + 0x2ed8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT987H + GFXMMU_LUT987H + GFXMMU LUT entry 987 high + 0x2edc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT988L + GFXMMU_LUT988L + GFXMMU LUT entry 988 low + 0x2ee0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT988H + GFXMMU_LUT988H + GFXMMU LUT entry 988 high + 0x2ee4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT989L + GFXMMU_LUT989L + GFXMMU LUT entry 989 low + 0x2ee8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT989H + GFXMMU_LUT989H + GFXMMU LUT entry 989 high + 0x2eec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT990L + GFXMMU_LUT990L + GFXMMU LUT entry 990 low + 0x2ef0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT990H + GFXMMU_LUT990H + GFXMMU LUT entry 990 high + 0x2ef4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT991L + GFXMMU_LUT991L + GFXMMU LUT entry 991 low + 0x2ef8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT991H + GFXMMU_LUT991H + GFXMMU LUT entry 991 high + 0x2efc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT992L + GFXMMU_LUT992L + GFXMMU LUT entry 992 low + 0x2f00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT992H + GFXMMU_LUT992H + GFXMMU LUT entry 992 high + 0x2f04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT993L + GFXMMU_LUT993L + GFXMMU LUT entry 993 low + 0x2f08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT993H + GFXMMU_LUT993H + GFXMMU LUT entry 993 high + 0x2f0c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT994L + GFXMMU_LUT994L + GFXMMU LUT entry 994 low + 0x2f10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT994H + GFXMMU_LUT994H + GFXMMU LUT entry 994 high + 0x2f14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT995L + GFXMMU_LUT995L + GFXMMU LUT entry 995 low + 0x2f18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT995H + GFXMMU_LUT995H + GFXMMU LUT entry 995 high + 0x2f1c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT996L + GFXMMU_LUT996L + GFXMMU LUT entry 996 low + 0x2f20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT996H + GFXMMU_LUT996H + GFXMMU LUT entry 996 high + 0x2f24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT997L + GFXMMU_LUT997L + GFXMMU LUT entry 997 low + 0x2f28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT997H + GFXMMU_LUT997H + GFXMMU LUT entry 997 high + 0x2f2c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT998L + GFXMMU_LUT998L + GFXMMU LUT entry 998 low + 0x2f30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT998H + GFXMMU_LUT998H + GFXMMU LUT entry 998 high + 0x2f34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT999L + GFXMMU_LUT999L + GFXMMU LUT entry 999 low + 0x2f38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT999H + GFXMMU_LUT999H + GFXMMU LUT entry 999 high + 0x2f3c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT1000L + GFXMMU_LUT1000L + GFXMMU LUT entry 1000 low + 0x2f40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT1000H + GFXMMU_LUT1000H + GFXMMU LUT entry 1000 high + 0x2f44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT1001L + GFXMMU_LUT1001L + GFXMMU LUT entry 1001 low + 0x2f48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT1001H + GFXMMU_LUT1001H + GFXMMU LUT entry 1001 high + 0x2f4c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT1002L + GFXMMU_LUT1002L + GFXMMU LUT entry 1002 low + 0x2f50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT1002H + GFXMMU_LUT1002H + GFXMMU LUT entry 1002 high + 0x2f54 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT1003L + GFXMMU_LUT1003L + GFXMMU LUT entry 1003 low + 0x2f58 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT1003H + GFXMMU_LUT1003H + GFXMMU LUT entry 1003 high + 0x2f5c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT1004L + GFXMMU_LUT1004L + GFXMMU LUT entry 1004 low + 0x2f60 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT1004H + GFXMMU_LUT1004H + GFXMMU LUT entry 1004 high + 0x2f64 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT1005L + GFXMMU_LUT1005L + GFXMMU LUT entry 1005 low + 0x2f68 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT1005H + GFXMMU_LUT1005H + GFXMMU LUT entry 1005 high + 0x2f6c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT1006L + GFXMMU_LUT1006L + GFXMMU LUT entry 1006 low + 0x2f70 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT1006H + GFXMMU_LUT1006H + GFXMMU LUT entry 1006 high + 0x2f74 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT1007L + GFXMMU_LUT1007L + GFXMMU LUT entry 1007 low + 0x2f78 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT1007H + GFXMMU_LUT1007H + GFXMMU LUT entry 1007 high + 0x2f7c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT1008L + GFXMMU_LUT1008L + GFXMMU LUT entry 1008 low + 0x2f80 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT1008H + GFXMMU_LUT1008H + GFXMMU LUT entry 1008 high + 0x2f84 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT1009L + GFXMMU_LUT1009L + GFXMMU LUT entry 1009 low + 0x2f88 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT1009H + GFXMMU_LUT1009H + GFXMMU LUT entry 1009 high + 0x2f8c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT1010L + GFXMMU_LUT1010L + GFXMMU LUT entry 1010 low + 0x2f90 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT1010H + GFXMMU_LUT1010H + GFXMMU LUT entry 1010 high + 0x2f94 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT1011L + GFXMMU_LUT1011L + GFXMMU LUT entry 1011 low + 0x2f98 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT1011H + GFXMMU_LUT1011H + GFXMMU LUT entry 1011 high + 0x2f9c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT1012L + GFXMMU_LUT1012L + GFXMMU LUT entry 1012 low + 0x2fa0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT1012H + GFXMMU_LUT1012H + GFXMMU LUT entry 1012 high + 0x2fa4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT1013L + GFXMMU_LUT1013L + GFXMMU LUT entry 1013 low + 0x2fa8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT1013H + GFXMMU_LUT1013H + GFXMMU LUT entry 1013 high + 0x2fac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT1014L + GFXMMU_LUT1014L + GFXMMU LUT entry 1014 low + 0x2fb0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT1014H + GFXMMU_LUT1014H + GFXMMU LUT entry 1014 high + 0x2fb4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT1015L + GFXMMU_LUT1015L + GFXMMU LUT entry 1015 low + 0x2fb8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT1015H + GFXMMU_LUT1015H + GFXMMU LUT entry 1015 high + 0x2fbc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT1016L + GFXMMU_LUT1016L + GFXMMU LUT entry 1016 low + 0x2fc0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT1016H + GFXMMU_LUT1016H + GFXMMU LUT entry 1016 high + 0x2fc4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT1017L + GFXMMU_LUT1017L + GFXMMU LUT entry 1017 low + 0x2fc8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT1017H + GFXMMU_LUT1017H + GFXMMU LUT entry 1017 high + 0x2fcc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT1018L + GFXMMU_LUT1018L + GFXMMU LUT entry 1018 low + 0x2fd0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT1018H + GFXMMU_LUT1018H + GFXMMU LUT entry 1018 high + 0x2fd4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT1019L + GFXMMU_LUT1019L + GFXMMU LUT entry 1019 low + 0x2fd8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT1019H + GFXMMU_LUT1019H + GFXMMU LUT entry 1019 high + 0x2fdc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT1020L + GFXMMU_LUT1020L + GFXMMU LUT entry 1020 low + 0x2fe0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT1020H + GFXMMU_LUT1020H + GFXMMU LUT entry 1020 high + 0x2fe4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT1021L + GFXMMU_LUT1021L + GFXMMU LUT entry 1021 low + 0x2fe8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT1021H + GFXMMU_LUT1021H + GFXMMU LUT entry 1021 high + 0x2fec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT1022L + GFXMMU_LUT1022L + GFXMMU LUT entry 1022 low + 0x2ff0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT1022H + GFXMMU_LUT1022H + GFXMMU LUT entry 1022 high + 0x2ff4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + GFXMMU_LUT1023L + GFXMMU_LUT1023L + GFXMMU LUT entry 1023 low + 0x2ff8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +Line enable. + 0 + 1 + read-write + + + B_0x0 + Line is disabled (no MMU evaluation is performed) + 0x0 + + + B_0x1 + Line is enabled (MMU evaluation is performed) + 0x1 + + + + + FVB + First Valid Block +Number of the first valid block of line number x. + 8 + 8 + read-write + + + LVB + Last Valid Block +Number of the last valid block of line number X. + 16 + 8 + read-write + + + + + GFXMMU_LUT1023H + GFXMMU_LUT1023H + GFXMMU LUT entry 1023 high + 0x2ffc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LO + Line offset +Line offset of line number x (i.e. offset of block 0 of line x) + 4 + 18 + read-write + + + + + + + SEC_GFXMMU + DCB->DSCSR->CDS == 0 + 0x5002C000 + + + GPDMA1 + GPDMA1 + GPDMA + 0x40020000 + + 0x0 + 0x1000 + registers + + + GPDMA1_CH0 + GPDMA1 channel 0 global interrupt + 029 + + + GPDMA1_CH1 + GPDMA1 channel 1 global interrupt + 030 + + + GPDMA1_CH2 + GPDMA1 channel 2 global interrupt + 031 + + + GPDMA1_CH3 + GPDMA1 channel 3 global interrupt + 032 + + + GPDMA1_CH4 + GPDMA1 channel 4 global interrupt + 033 + + + GPDMA1_CH5 + GPDMA1 channel 5 global interrupt + 034 + + + GPDMA1_CH6 + GPDMA1 channel 6 global interrupt + 035 + + + GPDMA1_CH7 + GPDMA1 channel 7 global interrupt + 036 + + + GPDMA1_CH8 + GPDMA1 channel 8 global interrupt + 080 + + + GPDMA1_CH9 + GPDMA1 channel 9 global interrupt + 081 + + + GPDMA1_CH10 + GPDMA1 channel 10 global interrupt + 082 + + + GPDMA1_CH11 + GPDMA1 channel 11 global interrupt + 083 + + + GPDMA1_CH12 + GPDMA1 channel 12 global interrupt + 084 + + + GPDMA1_CH13 + GPDMA1 channel 13 global interrupt + 085 + + + GPDMA1_CH14 + GPDMA1 channel 14 global interrupt + 086 + + + GPDMA1_CH15 + GPDMA1 channel 15 global interrupt + 087 + + + + GPDMA_SECCFGR + GPDMA_SECCFGR + GPDMA secure configuration register + 0x0 + 0x20 + read-write + 0x00000000 + + + SEC0 + SEC0 + 0 + 1 + + + SEC1 + SEC1 + 1 + 1 + + + SEC2 + SEC2 + 2 + 1 + + + SEC3 + SEC3 + 3 + 1 + + + SEC4 + SEC4 + 4 + 1 + + + SEC5 + SEC5 + 5 + 1 + + + SEC6 + SEC6 + 6 + 1 + + + SEC7 + SEC7 + 7 + 1 + + + SEC8 + SEC8 + 8 + 1 + + + SEC9 + SEC9 + 9 + 1 + + + SEC10 + SEC10 + 10 + 1 + + + SEC11 + SEC11 + 11 + 1 + + + SEC12 + SEC12 + 12 + 1 + + + SEC13 + SEC13 + 13 + 1 + + + SEC14 + SEC14 + 14 + 1 + + + SEC15 + SEC15 + 15 + 1 + + + + + GPDMA_PRIVCFGR + GPDMA_PRIVCFGR + GPDMA privileged configuration register + 0x4 + 0x20 + read-write + 0x00000000 + + + PRIV0 + PRIV0 + 0 + 1 + + + PRIV1 + PRIV1 + 1 + 1 + + + PRIV2 + PRIV2 + 2 + 1 + + + PRIV3 + PRIV3 + 3 + 1 + + + PRIV4 + PRIV4 + 4 + 1 + + + PRIV5 + PRIV5 + 5 + 1 + + + PRIV6 + PRIV6 + 6 + 1 + + + PRIV7 + PRIV7 + 7 + 1 + + + PRIV8 + PRIV8 + 8 + 1 + + + PRIV9 + PRIV9 + 9 + 1 + + + PRIV10 + PRIV10 + 10 + 1 + + + PRIV11 + PRIV11 + 11 + 1 + + + PRIV12 + PRIV12 + 12 + 1 + + + PRIV13 + PRIV13 + 13 + 1 + + + PRIV14 + PRIV14 + 14 + 1 + + + PRIV15 + PRIV15 + 15 + 1 + + + + + MISR + MISR + non-secure masked interrupt status register + 0xC + 0x20 + read-only + 0x00000000 + + + MIS0 + MIS0 + 0 + 1 + + + MIS1 + MIS1 + 1 + 1 + + + MIS2 + MIS2 + 2 + 1 + + + MIS3 + MIS3 + 3 + 1 + + + MIS4 + MIS4 + 4 + 1 + + + MIS5 + MIS5 + 5 + 1 + + + MIS6 + MIS6 + 6 + 1 + + + MIS7 + MIS7 + 7 + 1 + + + MIS8 + MIS8 + 8 + 1 + + + MIS9 + MIS9 + 9 + 1 + + + MIS10 + MIS10 + 10 + 1 + + + MIS11 + MIS11 + 11 + 1 + + + MIS12 + MIS12 + 12 + 1 + + + MIS13 + MIS13 + 13 + 1 + + + MIS14 + MIS14 + 14 + 1 + + + MIS15 + MIS15 + 15 + 1 + + + + + SMISR + SMISR + secure masked interrupt status register + 0x10 + 0x20 + read-only + 0x00000000 + + + MIS0 + MIS0 + 0 + 1 + + + MIS1 + MIS1 + 1 + 1 + + + MIS2 + MIS2 + 2 + 1 + + + MIS3 + MIS3 + 3 + 1 + + + MIS4 + MIS4 + 4 + 1 + + + MIS5 + MIS5 + 5 + 1 + + + MIS6 + MIS6 + 6 + 1 + + + MIS7 + MIS7 + 7 + 1 + + + MIS8 + MIS8 + 8 + 1 + + + MIS9 + MIS9 + 9 + 1 + + + MIS10 + MIS10 + 10 + 1 + + + MIS11 + MIS11 + 11 + 1 + + + MIS12 + MIS12 + 12 + 1 + + + MIS13 + MIS13 + 13 + 1 + + + MIS14 + MIS14 + 14 + 1 + + + MIS15 + MIS15 + 15 + 1 + + + + + GPDMA_C0LBAR + GPDMA_C0LBAR + channel x linked-list base address register + 0x50 + 0x20 + read-write + 0x00000000 + + + LBA + linked-list base address of DMA channel x + 16 + 16 + + + + + GPDMA_C0FCR + GPDMA_C0FCR + GPDMA channel x flag clear register + 0x5C + 0x20 + write-only + 0x00000000 + + + TCF + transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag + 8 + 1 + + + HTF + half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag + 9 + 1 + + + DTEF + data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag + 10 + 1 + + + ULEF + update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag + 11 + 1 + + + USEF + user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag + 12 + 1 + + + SUSPF + completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag + 13 + 1 + + + TOF + trigger overrun flag clear + 14 + 1 + + + + + GPDMA_C0SR + GPDMA_C0SR + channel x status register + 0x60 + 0x20 + read-only + 0x00000001 + + + IDLEF + idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state). + 0 + 1 + + + TCF + transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. + 8 + 1 + + + HTF + half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination. + 9 + 1 + + + DTEF + data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer + 10 + 1 + + + ULEF + update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory + 11 + 1 + + + USEF + user setting error flag - 0: no user setting error event - 1: a user setting error event occurred + 12 + 1 + + + SUSPF + completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred + 13 + 1 + + + FIFOL + monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1. + 16 + 8 + + + + + GPDMA_C0CR + GPDMA_C0CR + channel x control register + 0x64 + 0x20 + read-write + 0x00000000 + + + EN + enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. + 0 + 1 + + + RESET + reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. + 1 + 1 + + + SUSP + suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence. + 2 + 1 + + + TCIE + transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 8 + 1 + + + HTIE + half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 9 + 1 + + + DTEIE + data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 10 + 1 + + + ULEIE + update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 11 + 1 + + + USEIE + user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 12 + 1 + + + SUSPIE + completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 13 + 1 + + + LSM + Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1. + 16 + 1 + + + LAP + linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 17 + 1 + + + PRIO + priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 22 + 2 + + + + + GPDMA_C0TR1 + GPDMA_C0TR1 + GPDMA channel x transfer register 1 + 0x90 + 0x20 + read-write + 0x00000000 + + + SDW_LOG2 + binary logarithm of the source data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: a source block size must be a multiple of the source data width (c.f. GPDMA_CxBR1.BNDT[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: A source burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxSAR[2:0] and address offset GPDMA_CxTR3.SAO[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. + 0 + 2 + + + SINC + source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address, pointed by DMA_CxSAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. + 3 + 1 + + + SBL_1 + source burst length minus 1 , between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0, then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst transfer must have an aligned address (c.f. start address GPDMA_CxSAR and address offset GPDMA_CxTR3.SAO) with its data width (byte, half-word or word). Else a user setting error is reported and none transfer is issued.Note: If a burst transfer would have crossed a 1kB address boundary on a AHB transfer, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the AHB protocol.Note: If a burst transfer is of length greater than the FIFO size of the channel x, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the FIFO size. Transfer performance is lower, with DMA re-arbitration between effective and lower burst(s)/singles, but data integrity is guaranteed. + 4 + 6 + + + PAM + PAM + 11 + 2 + + + SBX + source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word, this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1: the two consecutive bytes within the unaligned half-word of each source word are exchanged + 13 + 1 + + + SAP + source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 14 + 1 + + + SSEC + security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when GPDMA_SECCFGR.SECx=0.When is de-asserted GPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer from the source is non-secure.If GPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure + 15 + 1 + + + DDW_LOG2 + binary logarithm of the destination data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: A destination burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxDAR[2:0] and address offset GPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: When configured in packing mode (i.e. if PAM[1]=1 and destination data width different from source data width), a source block size must be a multiple of the destination data width (c.f. GPDMA_CxBR1.BNDT[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. + 16 + 2 + + + DINC + destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address, pointed by DMA_CxDAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. + 19 + 1 + + + DBL_1 + destination burst length minus 1 , between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0, then burst can be named as single.Each data/beat has a width defined by the destination data width i.e. DDW_LOG2[1:0].Note: A burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxDAR[2:0] and address offset GPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: If a burst transfer would have crossed a 1kB address boundary on a AHB transfer, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the AHB protocol.Note: If a burst transfer is of length greater than the FIFO size of the channel x, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the FIFO size. Transfer performance is lower, with DMA re-arbitration between effective and lower burst(s)/singles, but data integrity is guaranteed. + 20 + 6 + + + DBX + destination byte exchangeIf destination data size is a byte, this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word + 26 + 1 + + + DHX + destination half-word exchangeIf destination data size is shorter than a word, this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each destination word + 27 + 1 + + + DAP + destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 30 + 1 + + + DSEC + security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when GPDMA_SECCFGR.SECx=0.When is de-asserted GPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer to the destination is non-secure.If GPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure + 31 + 1 + + + + + GPDMA_C0TR2 + GPDMA_C0TR2 + GPDMA channel x transfer register 2 + 0x94 + 0x20 + read-write + 0x00000000 + + + REQSEL + DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting. + 0 + 7 + + + SWREQ + Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored. + 9 + 1 + + + DREQ + Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port) + 10 + 1 + + + BREQ + BREQ + 11 + 1 + + + TRIGM + Trigger mode + 14 + 2 + + + TRIGSEL + Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00. + 16 + 6 + + + TRIGPOL + Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00 + 24 + 2 + + + TCEM + Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated. + 30 + 2 + + + + + GPDMA_C0BR1 + GPDMA_C0BR1 + GPDMA channel x block register 1 + 0x98 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data bytes to transfer from the source + 0 + 16 + + + + + GPDMA_C0SAR + GPDMA_C0SAR + GPDMA channel x source address register + 0x9C + 0x20 + read-write + 0x00000000 + + + SA + source address + 0 + 32 + + + + + GPDMA_C0DAR + GPDMA_C0DAR + GPDMA channel x destination address register + 0xA0 + 0x20 + read-write + 0x00000000 + + + DA + destination address + 0 + 32 + + + + + GPDMA_C0LLR + GPDMA_C0LLR + GPDMA channel x linked-list address register + 0xCC + 0x20 + read-write + 0x00000000 + + + LA + pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored. + 2 + 14 + + + ULL + Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update + 16 + 1 + + + UDA + Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update + 27 + 1 + + + USA + Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update + 28 + 1 + + + UB1 + Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update + 29 + 1 + + + UT2 + Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update + 30 + 1 + + + UT1 + Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update + 31 + 1 + + + + + GPDMA_C1LBAR + GPDMA_C1LBAR + channel x linked-list base address register + 0xD0 + 0x20 + read-write + 0x00000000 + + + LBA + linked-list base address of DMA channel x + 16 + 16 + + + + + GPDMA_C1FCR + GPDMA_C1FCR + GPDMA channel x flag clear register + 0xDC + 0x20 + write-only + 0x00000000 + + + TCF + transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag + 8 + 1 + + + HTF + half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag + 9 + 1 + + + DTEF + data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag + 10 + 1 + + + ULEF + update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag + 11 + 1 + + + USEF + user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag + 12 + 1 + + + SUSPF + completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag + 13 + 1 + + + TOF + trigger overrun flag clear + 14 + 1 + + + + + GPDMA_C1SR + GPDMA_C1SR + channel x status register + 0xE0 + 0x20 + read-only + 0x00000001 + + + IDLEF + idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state). + 0 + 1 + + + TCF + transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. + 8 + 1 + + + HTF + half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination. + 9 + 1 + + + DTEF + data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer + 10 + 1 + + + ULEF + update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory + 11 + 1 + + + USEF + user setting error flag - 0: no user setting error event - 1: a user setting error event occurred + 12 + 1 + + + SUSPF + completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred + 13 + 1 + + + FIFOL + monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1. + 16 + 8 + + + + + GPDMA_C1CR + GPDMA_C1CR + channel x control register + 0xE4 + 0x20 + read-write + 0x00000000 + + + EN + enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. + 0 + 1 + + + RESET + reset + 1 + 1 + + + SUSP + suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence. + 2 + 1 + + + TCIE + transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 8 + 1 + + + HTIE + half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 9 + 1 + + + DTEIE + data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 10 + 1 + + + ULEIE + update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 11 + 1 + + + USEIE + user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 12 + 1 + + + SUSPIE + completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 13 + 1 + + + LSM + Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1. + 16 + 1 + + + LAP + linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 17 + 1 + + + PRIO + priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 22 + 2 + + + + + GPDMA_C1TR1 + GPDMA_C1TR1 + GPDMA channel x transfer register 1 + 0x110 + 0x20 + read-write + 0x00000000 + + + SDW_LOG2 + binary logarithm of the source data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: a source block size must be a multiple of the source data width (c.f. GPDMA_CxBR1.BNDT[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: A source burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxSAR[2:0] and address offset GPDMA_CxTR3.SAO[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. + 0 + 2 + + + SINC + source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address, pointed by DMA_CxSAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. + 3 + 1 + + + SBL_1 + source burst length minus 1 , between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0, then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst transfer must have an aligned address (c.f. start address GPDMA_CxSAR and address offset GPDMA_CxTR3.SAO) with its data width (byte, half-word or word). Else a user setting error is reported and none transfer is issued.Note: If a burst transfer would have crossed a 1kB address boundary on a AHB transfer, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the AHB protocol.Note: If a burst transfer is of length greater than the FIFO size of the channel x, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the FIFO size. Transfer performance is lower, with DMA re-arbitration between effective and lower burst(s)/singles, but data integrity is guaranteed. + 4 + 6 + + + PAM + PAM + 11 + 2 + + + SBX + source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word, this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1: the two consecutive bytes within the unaligned half-word of each source word are exchanged + 13 + 1 + + + SAP + source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 14 + 1 + + + SSEC + security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when GPDMA_SECCFGR.SECx=0.When is de-asserted GPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer from the source is non-secure.If GPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure + 15 + 1 + + + DDW_LOG2 + binary logarithm of the destination data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: A destination burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxDAR[2:0] and address offset GPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: When configured in packing mode (i.e. if PAM[1]=1 and destination data width different from source data width), a source block size must be a multiple of the destination data width (c.f. GPDMA_CxBR1.BNDT[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. + 16 + 2 + + + DINC + destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address, pointed by DMA_CxDAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. + 19 + 1 + + + DBL_1 + destination burst length minus 1 , between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0, then burst can be named as single.Each data/beat has a width defined by the destination data width i.e. DDW_LOG2[1:0].Note: A burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxDAR[2:0] and address offset GPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: If a burst transfer would have crossed a 1kB address boundary on a AHB transfer, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the AHB protocol.Note: If a burst transfer is of length greater than the FIFO size of the channel x, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the FIFO size. Transfer performance is lower, with DMA re-arbitration between effective and lower burst(s)/singles, but data integrity is guaranteed. + 20 + 6 + + + DBX + destination byte exchangeIf destination data size is a byte, this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word + 26 + 1 + + + DHX + destination half-word exchangeIf destination data size is shorter than a word, this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each destination word + 27 + 1 + + + DAP + destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 30 + 1 + + + DSEC + security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when GPDMA_SECCFGR.SECx=0.When is de-asserted GPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer to the destination is non-secure.If GPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure + 31 + 1 + + + + + GPDMA_C1TR2 + GPDMA_C1TR2 + GPDMA channel x transfer register 2 + 0x114 + 0x20 + read-write + 0x00000000 + + + REQSEL + DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting. + 0 + 7 + + + SWREQ + Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored. + 9 + 1 + + + DREQ + Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port) + 10 + 1 + + + BREQ + BREQ + 11 + 1 + + + TRIGM + TRIGM mode + 14 + 2 + + + TRIGSEL + Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00. + 16 + 6 + + + TRIGPOL + Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00 + 24 + 2 + + + TCEM + Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated. + 30 + 2 + + + + + GPDMA_C1BR1 + GPDMA_C1BR1 + GPDMA channel x block register 1 + 0x118 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data bytes to transfer from the source + 0 + 16 + + + + + GPDMA_C1SAR + GPDMA_C1SAR + GPDMA channel x source address register + 0x11C + 0x20 + read-write + 0x00000000 + + + SA + source address + 0 + 32 + + + + + GPDMA_C1DAR + GPDMA_C1DAR + GPDMA channel x destination address register + 0x120 + 0x20 + read-write + 0x00000000 + + + DA + destination address + 0 + 32 + + + + + GPDMA_C1LLR + GPDMA_C1LLR + GPDMA channel x linked-list address register + 0x14C + 0x20 + read-write + 0x00000000 + + + LA + pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored. + 2 + 14 + + + ULL + Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update + 16 + 1 + + + UDA + Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update + 27 + 1 + + + USA + Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update + 28 + 1 + + + UB1 + Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update + 29 + 1 + + + UT2 + Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update + 30 + 1 + + + UT1 + Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update + 31 + 1 + + + + + GPDMA_C2LBAR + GPDMA_C2LBAR + channel x linked-list base address register + 0x150 + 0x20 + read-write + 0x00000000 + + + LBA + linked-list base address of DMA channel x + 16 + 16 + + + + + GPDMA_C2FCR + GPDMA_C2FCR + GPDMA channel x flag clear register + 0x15C + 0x20 + write-only + 0x00000000 + + + TCF + transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag + 8 + 1 + + + HTF + half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag + 9 + 1 + + + DTEF + data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag + 10 + 1 + + + ULEF + update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag + 11 + 1 + + + USEF + user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag + 12 + 1 + + + SUSPF + completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag + 13 + 1 + + + TOF + trigger overrun flag clear + 14 + 1 + + + + + GPDMA_C2SR + GPDMA_C2SR + channel x status register + 0x160 + 0x20 + read-only + 0x00000001 + + + IDLEF + idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state). + 0 + 1 + + + TCF + transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. + 8 + 1 + + + HTF + half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination. + 9 + 1 + + + DTEF + data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer + 10 + 1 + + + ULEF + update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory + 11 + 1 + + + USEF + user setting error flag - 0: no user setting error event - 1: a user setting error event occurred + 12 + 1 + + + SUSPF + completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred + 13 + 1 + + + FIFOL + monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1. + 16 + 8 + + + + + GPDMA_C2CR + GPDMA_C2CR + channel x control register + 0x164 + 0x20 + read-write + 0x00000000 + + + EN + enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. + 0 + 1 + + + RESET + reset + 1 + 1 + + + SUSP + suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence. + 2 + 1 + + + TCIE + transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 8 + 1 + + + HTIE + half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 9 + 1 + + + DTEIE + data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 10 + 1 + + + ULEIE + update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 11 + 1 + + + USEIE + user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 12 + 1 + + + SUSPIE + completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 13 + 1 + + + LSM + Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1. + 16 + 1 + + + LAP + linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 17 + 1 + + + PRIO + priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 22 + 2 + + + + + GPDMA_C2TR1 + GPDMA_C2TR1 + GPDMA channel x transfer register 1 + 0x190 + 0x20 + read-write + 0x00000000 + + + SDW_LOG2 + binary logarithm of the source data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: a source block size must be a multiple of the source data width (c.f. GPDMA_CxBR1.BNDT[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: A source burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxSAR[2:0] and address offset GPDMA_CxTR3.SAO[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. + 0 + 2 + + + SINC + source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address, pointed by DMA_CxSAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. + 3 + 1 + + + SBL_1 + source burst length minus 1 , between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0, then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst transfer must have an aligned address (c.f. start address GPDMA_CxSAR and address offset GPDMA_CxTR3.SAO) with its data width (byte, half-word or word). Else a user setting error is reported and none transfer is issued.Note: If a burst transfer would have crossed a 1kB address boundary on a AHB transfer, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the AHB protocol.Note: If a burst transfer is of length greater than the FIFO size of the channel x, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the FIFO size. Transfer performance is lower, with DMA re-arbitration between effective and lower burst(s)/singles, but data integrity is guaranteed. + 4 + 6 + + + PAM + PAM + 11 + 2 + + + SBX + source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word, this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1: the two consecutive bytes within the unaligned half-word of each source word are exchanged + 13 + 1 + + + SAP + source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 14 + 1 + + + SSEC + security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when GPDMA_SECCFGR.SECx=0.When is de-asserted GPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer from the source is non-secure.If GPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure + 15 + 1 + + + DDW_LOG2 + binary logarithm of the destination data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: A destination burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxDAR[2:0] and address offset GPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: When configured in packing mode (i.e. if PAM[1]=1 and destination data width different from source data width), a source block size must be a multiple of the destination data width (c.f. GPDMA_CxBR1.BNDT[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. + 16 + 2 + + + DINC + destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address, pointed by DMA_CxDAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. + 19 + 1 + + + DBL_1 + destination burst length minus 1 , between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0, then burst can be named as single.Each data/beat has a width defined by the destination data width i.e. DDW_LOG2[1:0].Note: A burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxDAR[2:0] and address offset GPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: If a burst transfer would have crossed a 1kB address boundary on a AHB transfer, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the AHB protocol.Note: If a burst transfer is of length greater than the FIFO size of the channel x, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the FIFO size. Transfer performance is lower, with DMA re-arbitration between effective and lower burst(s)/singles, but data integrity is guaranteed. + 20 + 6 + + + DBX + destination byte exchangeIf destination data size is a byte, this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word + 26 + 1 + + + DHX + destination half-word exchangeIf destination data size is shorter than a word, this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each destination word + 27 + 1 + + + DAP + destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 30 + 1 + + + DSEC + security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when GPDMA_SECCFGR.SECx=0.When is de-asserted GPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer to the destination is non-secure.If GPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure + 31 + 1 + + + + + GPDMA_C2TR2 + GPDMA_C2TR2 + GPDMA channel x transfer register 2 + 0x194 + 0x20 + read-write + 0x00000000 + + + REQSEL + DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting. + 0 + 7 + + + SWREQ + Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored. + 9 + 1 + + + DREQ + Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port) + 10 + 1 + + + BREQ + BREQ + 11 + 1 + + + TRIGM + Trigger mode + 14 + 2 + + + TRIGSEL + Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00. + 16 + 6 + + + TRIGPOL + Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00 + 24 + 2 + + + TCEM + Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated. + 30 + 2 + + + + + GPDMA_C2BR1 + GPDMA_C2BR1 + GPDMA channel x block register 1 + 0x198 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data bytes to transfer from the source + 0 + 16 + + + + + GPDMA_C2SAR + GPDMA_C2SAR + GPDMA channel x source address register + 0x19C + 0x20 + read-write + 0x00000000 + + + SA + source address + 0 + 32 + + + + + GPDMA_C2DAR + GPDMA_C2DAR + GPDMA channel x destination address register + 0x1A0 + 0x20 + read-write + 0x00000000 + + + DA + destination address + 0 + 32 + + + + + GPDMA_C2LLR + GPDMA_C2LLR + GPDMA channel x linked-list address register + 0x1CC + 0x20 + read-write + 0x00000000 + + + LA + pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored. + 2 + 14 + + + ULL + Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update + 16 + 1 + + + UDA + Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update + 27 + 1 + + + USA + Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update + 28 + 1 + + + UB1 + Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update + 29 + 1 + + + UT2 + Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update + 30 + 1 + + + UT1 + Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update + 31 + 1 + + + + + GPDMA_C3LBAR + GPDMA_C3LBAR + channel x linked-list base address register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + LBA + linked-list base address of DMA channel x + 16 + 16 + + + + + GPDMA_C3FCR + GPDMA_C3FCR + GPDMA channel x flag clear register + 0x1DC + 0x20 + write-only + 0x00000000 + + + TCF + transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag + 8 + 1 + + + HTF + half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag + 9 + 1 + + + DTEF + data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag + 10 + 1 + + + ULEF + update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag + 11 + 1 + + + USEF + user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag + 12 + 1 + + + SUSPF + completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag + 13 + 1 + + + TOF + trigger overrun flag clear + 14 + 1 + + + + + GPDMA_C3SR + GPDMA_C3SR + channel x status register + 0x1E0 + 0x20 + read-only + 0x00000001 + + + IDLEF + idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state). + 0 + 1 + + + TCF + transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. + 8 + 1 + + + HTF + half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination. + 9 + 1 + + + DTEF + data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer + 10 + 1 + + + ULEF + update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory + 11 + 1 + + + USEF + user setting error flag - 0: no user setting error event - 1: a user setting error event occurred + 12 + 1 + + + SUSPF + completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred + 13 + 1 + + + FIFOL + monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1. + 16 + 8 + + + + + GPDMA_C3CR + GPDMA_C3CR + channel x control register + 0x1E4 + 0x20 + read-write + 0x00000000 + + + EN + enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. + 0 + 1 + + + RESET + reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel. i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence. + 1 + 1 + + + SUSP + suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence. + 2 + 1 + + + TCIE + transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 8 + 1 + + + HTIE + half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 9 + 1 + + + DTEIE + data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 10 + 1 + + + ULEIE + update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 11 + 1 + + + USEIE + user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 12 + 1 + + + SUSPIE + completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 13 + 1 + + + LSM + Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1. + 16 + 1 + + + LAP + linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 17 + 1 + + + PRIO + priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 22 + 2 + + + + + GPDMA_C3TR1 + GPDMA_C3TR1 + GPDMA channel x transfer register 1 + 0x210 + 0x20 + read-write + 0x00000000 + + + SDW_LOG2 + binary logarithm of the source data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: a source block size must be a multiple of the source data width (c.f. GPDMA_CxBR1.BNDT[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: A source burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxSAR[2:0] and address offset GPDMA_CxTR3.SAO[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. + 0 + 2 + + + SINC + source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address, pointed by DMA_CxSAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. + 3 + 1 + + + SBL_1 + source burst length minus 1 , between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0, then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst transfer must have an aligned address (c.f. start address GPDMA_CxSAR and address offset GPDMA_CxTR3.SAO) with its data width (byte, half-word or word). Else a user setting error is reported and none transfer is issued.Note: If a burst transfer would have crossed a 1kB address boundary on a AHB transfer, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the AHB protocol.Note: If a burst transfer is of length greater than the FIFO size of the channel x, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the FIFO size. Transfer performance is lower, with DMA re-arbitration between effective and lower burst(s)/singles, but data integrity is guaranteed. + 4 + 6 + + + PAM + PAM + 11 + 2 + + + SBX + source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word, this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1: the two consecutive bytes within the unaligned half-word of each source word are exchanged + 13 + 1 + + + SAP + source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 14 + 1 + + + SSEC + security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when GPDMA_SECCFGR.SECx=0.When is de-asserted GPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer from the source is non-secure.If GPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure + 15 + 1 + + + DDW_LOG2 + binary logarithm of the destination data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: A destination burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxDAR[2:0] and address offset GPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: When configured in packing mode (i.e. if PAM[1]=1 and destination data width different from source data width), a source block size must be a multiple of the destination data width (c.f. GPDMA_CxBR1.BNDT[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. + 16 + 2 + + + DINC + destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address, pointed by DMA_CxDAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. + 19 + 1 + + + DBL_1 + destination burst length minus 1 , between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0, then burst can be named as single.Each data/beat has a width defined by the destination data width i.e. DDW_LOG2[1:0].Note: A burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxDAR[2:0] and address offset GPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: If a burst transfer would have crossed a 1kB address boundary on a AHB transfer, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the AHB protocol.Note: If a burst transfer is of length greater than the FIFO size of the channel x, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the FIFO size. Transfer performance is lower, with DMA re-arbitration between effective and lower burst(s)/singles, but data integrity is guaranteed. + 20 + 6 + + + DBX + destination byte exchangeIf destination data size is a byte, this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word + 26 + 1 + + + DHX + destination half-word exchangeIf destination data size is shorter than a word, this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each destination word + 27 + 1 + + + DAP + destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 30 + 1 + + + DSEC + security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when GPDMA_SECCFGR.SECx=0.When is de-asserted GPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer to the destination is non-secure.If GPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure + 31 + 1 + + + + + GPDMA_C3TR2 + GPDMA_C3TR2 + GPDMA channel x transfer register 2 + 0x214 + 0x20 + read-write + 0x00000000 + + + REQSEL + DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting. + 0 + 7 + + + SWREQ + Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored. + 9 + 1 + + + DREQ + Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port) + 10 + 1 + + + BREQ + BREQ + 11 + 1 + + + TRIGM + Trigger mode + 14 + 2 + + + TRIGSEL + Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00. + 16 + 6 + + + TRIGPOL + Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00 + 24 + 2 + + + TCEM + Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated. + 30 + 2 + + + + + GPDMA_C4TR2 + GPDMA_C4TR2 + GPDMA channel x transfer register 2 + 0x294 + 0x20 + read-write + 0x00000000 + + + REQSEL + DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting. + 0 + 7 + + + SWREQ + Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored. + 9 + 1 + + + DREQ + Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port) + 10 + 1 + + + BREQ + BREQ + 11 + 1 + + + TRIGM + Trigger mode: rst read of a/each block transfer is conditioned by one hit trigger. + 14 + 2 + + + TRIGSEL + Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00. + 16 + 6 + + + TRIGPOL + Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00 + 24 + 2 + + + TCEM + Transfer complete event mode + 30 + 2 + + + + + GPDMA_C5TR2 + GPDMA_C5TR2 + GPDMA channel x transfer register 2 + 0x314 + 0x20 + read-write + 0x00000000 + + + REQSEL + DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting. + 0 + 7 + + + SWREQ + Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored. + 9 + 1 + + + DREQ + Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port) + 10 + 1 + + + BREQ + BREQ + 11 + 1 + + + TRIGM + Trigger mode + 14 + 2 + + + TRIGSEL + Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00. + 16 + 6 + + + TRIGPOL + Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00 + 24 + 2 + + + TCEM + Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated. + 30 + 2 + + + + + GPDMA_C6TR2 + GPDMA_C6TR2 + GPDMA channel x transfer register 2 + 0x394 + 0x20 + read-write + 0x00000000 + + + REQSEL + DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting. + 0 + 7 + + + SWREQ + Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored. + 9 + 1 + + + DREQ + Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port) + 10 + 1 + + + BREQ + BREQ + 11 + 1 + + + TRIGM + Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11, these bits are ignored. Else, a DMA transfer is conditioned by (at least) one trigger hit, either at: - 00: at block level (for channel x=12 to 15: for each block if a 2D/repeated block is configured i.e. if GPDMA_CxBR1.BRC[10:0]! = 0): the first burst read of a/each block transfer is conditioned by one hit trigger. - 01: at 2D/repeated block level for channel x=12 to 15; same as 00 for channel x=0 to 11 + 14 + 2 + + + TRIGSEL + Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00. + 16 + 6 + + + TRIGPOL + Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00 + 24 + 2 + + + TCEM + Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated. + 30 + 2 + + + + + GPDMA_C7TR2 + GPDMA_C7TR2 + GPDMA channel x transfer register 2 + 0x414 + 0x20 + read-write + 0x00000000 + + + REQSEL + DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting. + 0 + 7 + + + SWREQ + Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored. + 9 + 1 + + + DREQ + Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port) + 10 + 1 + + + BREQ + BREQ + 11 + 1 + + + TRIGM + Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11, these bits are ignored. Else, a DMA transfer is conditioned by (at least) one trigger hit, either at: - 00: at block level (for channel x=12 to 15: for each block if a 2D/repeated block is configured i.e. if GPDMA_CxBR1.BRC[10:0]! = 0): the first burst read of a/each block transfer is conditioned by one hit trigger. - 01: at 2D/repeated block level for channel x=12 to 15; same as 00 for channel x=0 to 11: the first burst read of a 2D/repeated block transfer is conditioned by one hit trigger. + 14 + 2 + + + TRIGSEL + Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00. + 16 + 6 + + + TRIGPOL + Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00 + 24 + 2 + + + TCEM + Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated. + 30 + 2 + + + + + GPDMA_C8TR2 + GPDMA_C8TR2 + GPDMA channel x transfer register 2 + 0x494 + 0x20 + read-write + 0x00000000 + + + REQSEL + DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting. + 0 + 7 + + + SWREQ + Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored. + 9 + 1 + + + DREQ + Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port) + 10 + 1 + + + BREQ + BREQ + 11 + 1 + + + TRIGM + Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11, these bits are ignored. Else, a DMA transfer is conditioned by (at least) one trigger hit, either at: - 00: at block level (for channel x=12 to 15: for each block if a 2D/repeated block is configured i.e. if GPDMA_CxBR1.BRC[10:0]! = 0): the first burst read of a/each block transfer is conditioned by one hit trigger. - 01: at 2D/repeated block level for channel x=12 to 15; same as 00 for channel x=0 to 11: the first burst read of a 2D/repeated block transfer is conditioned by one hit trigger. + 14 + 2 + + + TRIGSEL + Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00. + 16 + 6 + + + TRIGPOL + Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00 + 24 + 2 + + + TCEM + Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated. + 30 + 2 + + + + + GPDMA_C9TR2 + GPDMA_C9TR2 + GPDMA channel x transfer register 2 + 0x514 + 0x20 + read-write + 0x00000000 + + + REQSEL + DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting. + 0 + 7 + + + SWREQ + Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored. + 9 + 1 + + + DREQ + Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port) + 10 + 1 + + + BREQ + BREQ + 11 + 1 + + + TRIGM + Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11, these bits are ignored. Else, a DMA transfer is conditioned by (at least) one trigger hit, either at: - 00: at block level (for channel x=12 to 15: for each block if a 2D/repeated block is configured i.e. if GPDMA_CxBR1.BRC[10:0]! = 0): the first burst read of a/each block transfer is conditioned by one hit trigger. - 01: at 2D/repeated block level for channel x=12 to 15; same as 00 for channel x=0 to 11: the first burst read of a 2D/repeated block transfer is conditioned by one hit trigger. + 14 + 2 + + + TRIGSEL + Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00. + 16 + 6 + + + TRIGPOL + Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00 + 24 + 2 + + + TCEM + Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated. + 30 + 2 + + + + + GPDMA_C10TR2 + GPDMA_C10TR2 + GPDMA channel x transfer register 2 + 0x594 + 0x20 + read-write + 0x00000000 + + + REQSEL + DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting. + 0 + 7 + + + SWREQ + Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored. + 9 + 1 + + + DREQ + Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port) + 10 + 1 + + + BREQ + BREQ + 11 + 1 + + + TRIGM + Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11, these bits are ignored. Else, a DMA transfer is conditioned by (at least) one trigger hit, either at: - 00: at block level (for channel x=12 to 15: for each block if a 2D/repeated block is configured i.e. if GPDMA_CxBR1.BRC[10:0]! = 0): the first burst read of a/each block transfer is conditioned by one hit trigger. - 01: at 2D/repeated block level for channel x=12 to 15; same as 00 for channel x=0 to 11: the first burst read of a 2D/repeated block transfer is conditioned by one hit trigger. + 14 + 2 + + + TRIGSEL + Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00. + 16 + 6 + + + TRIGPOL + Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00 + 24 + 2 + + + TCEM + Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated. + 30 + 2 + + + + + GPDMA_C11TR2 + GPDMA_C11TR2 + GPDMA channel x transfer register 2 + 0x614 + 0x20 + read-write + 0x00000000 + + + REQSEL + DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting. + 0 + 7 + + + SWREQ + Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored. + 9 + 1 + + + DREQ + Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port) + 10 + 1 + + + BREQ + BREQ + 11 + 1 + + + TRIGM + Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring, trashing the (possible) memorized hit of the formerly defined LLIn trigger. After that a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, this new second trigger hitn+2 is lost and not memorized. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, if TRIGM[1:0]=11 and (SWREQ=1 or (SWREQ=0 and DREQ=0)), the shortened burst transfer (by single(s) or/and by burst(s) of lower length) is conditioned once by the trigger. Note: When the programmed destination burst is internally shortened by single(s) or/and by burst(s) of lower length (e.g. vs FIFO size, vs block size, 1kB/4kB boundary address crossing): if the trigger is conditioning the programmed destination burst (if TRIGM[1:0]=11 and SWREQ=0 and DREQ=1), this shortened destination burst transfer is conditioned once by the trigger. + 14 + 2 + + + TRIGSEL + Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00. + 16 + 6 + + + TRIGPOL + Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00 + 24 + 2 + + + TCEM + Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated. + 30 + 2 + + + + + GPDMA_C12TR2 + GPDMA_C12TR2 + GPDMA channel x transfer register 2 + 0x694 + 0x20 + read-write + 0x00000000 + + + REQSEL + DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting. + 0 + 7 + + + SWREQ + Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored. + 9 + 1 + + + DREQ + Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port) + 10 + 1 + + + BREQ + BREQ + 11 + 1 + + + TRIGM + Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring, trashing the (possible) memorized hit of the formerly defined LLIn trigger. After that a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, this new second trigger hitn+2 is lost and not memorized. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, if TRIGM[1:0]=11 and (SWREQ=1 or (SWREQ=0 and DREQ=0)), the shortened burst transfer (by single(s) or/and by burst(s) of lower length) is conditioned once by the trigger. Note: When the programmed destination burst is internally shortened by single(s) or/and by burst(s) of lower length (e.g. vs FIFO size, vs block size, 1kB/4kB boundary address crossing): if the trigger is conditioning the programmed destination burst (if TRIGM[1:0]=11 and SWREQ=0 and DREQ=1), this shortened destination burst transfer is conditioned once by the trigger. + 14 + 2 + + + TRIGSEL + Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00. + 16 + 6 + + + TRIGPOL + Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00 + 24 + 2 + + + TCEM + Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated. + 30 + 2 + + + + + GPDMA_C13TR2 + GPDMA_C13TR2 + GPDMA channel x transfer register 2 + 0x714 + 0x20 + read-write + 0x00000000 + + + REQSEL + DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting. + 0 + 7 + + + SWREQ + Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored. + 9 + 1 + + + DREQ + Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port) + 10 + 1 + + + BREQ + BREQ + 11 + 1 + + + TRIGM + Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring, trashing the (possible) memorized hit of the formerly defined LLIn trigger. After that a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, this new second trigger hitn+2 is lost and not memorized. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, if TRIGM[1:0]=11 and (SWREQ=1 or (SWREQ=0 and DREQ=0)), the shortened burst transfer (by single(s) or/and by burst(s) of lower length) is conditioned once by the trigger. Note: When the programmed destination burst is internally shortened by single(s) or/and by burst(s) of lower length (e.g. vs FIFO size, vs block size, 1kB/4kB boundary address crossing): if the trigger is conditioning the programmed destination burst (if TRIGM[1:0]=11 and SWREQ=0 and DREQ=1), this shortened destination burst transfer is conditioned once by the trigger. + 14 + 2 + + + TRIGSEL + Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00. + 16 + 6 + + + TRIGPOL + Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00 + 24 + 2 + + + TCEM + Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated. + 30 + 2 + + + + + GPDMA_C14TR2 + GPDMA_C14TR2 + GPDMA channel x transfer register 2 + 0x794 + 0x20 + read-write + 0x00000000 + + + REQSEL + DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting. + 0 + 7 + + + SWREQ + Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored. + 9 + 1 + + + DREQ + Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port) + 10 + 1 + + + BREQ + BREQ + 11 + 1 + + + TRIGM + Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring, trashing the (possible) memorized hit of the formerly defined LLIn trigger. After that a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, this new second trigger hitn+2 is lost and not memorized. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, if TRIGM[1:0]=11 and (SWREQ=1 or (SWREQ=0 and DREQ=0)), the shortened burst transfer (by single(s) or/and by burst(s) of lower length) is conditioned once by the trigger. Note: When the programmed destination burst is internally shortened by single(s) or/and by burst(s) of lower length (e.g. vs FIFO size, vs block size, 1kB/4kB boundary address crossing): if the trigger is conditioning the programmed destination burst (if TRIGM[1:0]=11 and SWREQ=0 and DREQ=1), this shortened destination burst transfer is conditioned once by the trigger. + 14 + 2 + + + TRIGSEL + Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00. + 16 + 6 + + + TRIGPOL + Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00 + 24 + 2 + + + TCEM + Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated. + 30 + 2 + + + + + GPDMA_C15TR2 + GPDMA_C15TR2 + GPDMA channel x transfer register 2 + 0x814 + 0x20 + read-write + 0x00000000 + + + REQSEL + DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting. + 0 + 7 + + + SWREQ + Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored. + 9 + 1 + + + DREQ + Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port) + 10 + 1 + + + BREQ + BREQ + 11 + 1 + + + TRIGM + Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring, trashing the (possible) memorized hit of the formerly defined LLIn trigger. After that a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, this new second trigger hitn+2 is lost and not memorized. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, if TRIGM[1:0]=11 and (SWREQ=1 or (SWREQ=0 and DREQ=0)), the shortened burst transfer (by single(s) or/and by burst(s) of lower length) is conditioned once by the trigger. Note: When the programmed destination burst is internally shortened by single(s) or/and by burst(s) of lower length (e.g. vs FIFO size, vs block size, 1kB/4kB boundary address crossing): if the trigger is conditioning the programmed destination burst (if TRIGM[1:0]=11 and SWREQ=0 and DREQ=1), this shortened destination burst transfer is conditioned once by the trigger. + 14 + 2 + + + TRIGSEL + Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00. + 16 + 6 + + + TRIGPOL + Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00 + 24 + 2 + + + TCEM + Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated. + 30 + 2 + + + + + GPDMA_C3BR1 + GPDMA_C3BR1 + GPDMA channel x block register 1 + 0x218 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data bytes to transfer from the source + 0 + 16 + + + + + GPDMA_C4BR1 + GPDMA_C4BR1 + GPDMA channel x block register 1 + 0x298 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data bytes to transfer from the source + 0 + 16 + + + + + GPDMA_C5BR1 + GPDMA_C5BR1 + GPDMA channel x block register 1 + 0x318 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data bytes to transfer from the source + 0 + 16 + + + + + GPDMA_C6BR1 + GPDMA_C6BR1 + GPDMA channel x block register 1 + 0x398 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data bytes to transfer from the source + 0 + 16 + + + + + GPDMA_C7BR1 + GPDMA_C7BR1 + GPDMA channel x block register 1 + 0x418 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data bytes to transfer from the source + 0 + 16 + + + + + GPDMA_C8BR1 + GPDMA_C8BR1 + GPDMA channel x block register 1 + 0x498 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data bytes to transfer from the source + 0 + 16 + + + + + GPDMA_C9BR1 + GPDMA_C9BR1 + GPDMA channel x block register 1 + 0x518 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data bytes to transfer from the source + 0 + 16 + + + + + GPDMA_C10BR1 + GPDMA_C10BR1 + GPDMA channel x block register 1 + 0x598 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data bytes to transfer from the source + 0 + 16 + + + + + GPDMA_C11BR1 + GPDMA_C11BR1 + GPDMA channel x block register 1 + 0x618 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data bytes to transfer from the source + 0 + 16 + + + + + GPDMA_C12BR1 + GPDMA_C12BR1 + GPDMA channel x block register 1 + 0x698 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data bytes to transfer from the source + 0 + 16 + + + BRC + BRC + 16 + 11 + + + SDEC + SDEC + 28 + 1 + + + DDEC + DDEC + 29 + 1 + + + BRSDEC + BRSDEC + 30 + 1 + + + BRDDEC + BRDDEC + 31 + 1 + + + + + GPDMA_C13BR1 + GPDMA_C13BR1 + GPDMA channel x block register 1 + 0x718 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data bytes to transfer from the source + 0 + 16 + + + BRC + BRC + 16 + 11 + + + SDEC + SDEC + 28 + 1 + + + DDEC + DDEC + 29 + 1 + + + BRSDEC + BRSDEC + 30 + 1 + + + BRDDEC + BRDDEC + 31 + 1 + + + + + GPDMA_C14BR1 + GPDMA_C14BR1 + GPDMA channel x block register 1 + 0x798 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data bytes to transfer from the source + 0 + 16 + + + BRC + BRC + 16 + 11 + + + SDEC + SDEC + 28 + 1 + + + DDEC + DDEC + 29 + 1 + + + BRSDEC + BRSDEC + 30 + 1 + + + BRDDEC + BRDDEC + 31 + 1 + + + + + GPDMA_C15BR1 + GPDMA_C15BR1 + GPDMA channel x block register 1 + 0x818 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data bytes to transfer from the source + 0 + 16 + + + BRC + BRC + 16 + 11 + + + SDEC + SDEC + 28 + 1 + + + DDEC + DDEC + 29 + 1 + + + BRSDEC + BRSDEC + 30 + 1 + + + BRDDEC + BRDDEC + 31 + 1 + + + + + GPDMA_C3SAR + GPDMA_C3SAR + GPDMA channel x source address register + 0x21C + 0x20 + read-write + 0x00000000 + + + SA + source address + 0 + 32 + + + + + GPDMA_C4SAR + GPDMA_C4SAR + GPDMA channel x source address register + 0x29C + 0x20 + read-write + 0x00000000 + + + SA + source address + 0 + 32 + + + + + GPDMA_C5SAR + GPDMA_C5SAR + GPDMA channel x source address register + 0x31C + 0x20 + read-write + 0x00000000 + + + SA + source address + 0 + 32 + + + + + GPDMA_C6SAR + GPDMA_C6SAR + GPDMA channel x source address register + 0x39C + 0x20 + read-write + 0x00000000 + + + SA + source address + 0 + 32 + + + + + GPDMA_C7SAR + GPDMA_C7SAR + GPDMA channel x source address register + 0x41C + 0x20 + read-write + 0x00000000 + + + SA + source address + 0 + 32 + + + + + GPDMA_C8SAR + GPDMA_C8SAR + GPDMA channel x source address register + 0x49C + 0x20 + read-write + 0x00000000 + + + SA + source address + 0 + 32 + + + + + GPDMA_C9SAR + GPDMA_C9SAR + GPDMA channel x source address register + 0x51C + 0x20 + read-write + 0x00000000 + + + SA + source address + 0 + 32 + + + + + GPDMA_C10SAR + GPDMA_C10SAR + GPDMA channel x source address register + 0x59C + 0x20 + read-write + 0x00000000 + + + SA + source address + 0 + 32 + + + + + GPDMA_C11SAR + GPDMA_C11SAR + GPDMA channel x source address register + 0x61C + 0x20 + read-write + 0x00000000 + + + SA + source address + 0 + 32 + + + + + GPDMA_C12SAR + GPDMA_C12SAR + GPDMA channel x source address register + 0x69C + 0x20 + read-write + 0x00000000 + + + SA + source address + 0 + 32 + + + + + GPDMA_C13SAR + GPDMA_C13SAR + GPDMA channel x source address register + 0x71C + 0x20 + read-write + 0x00000000 + + + SA + source address + 0 + 32 + + + + + GPDMA_C14SAR + GPDMA_C14SAR + GPDMA channel x source address register + 0x79C + 0x20 + read-write + 0x00000000 + + + SA + source address + 0 + 32 + + + + + GPDMA_C15SAR + GPDMA_C15SAR + GPDMA channel x source address register + 0x81C + 0x20 + read-write + 0x00000000 + + + SA + source address + 0 + 32 + + + + + GPDMA_C3DAR + GPDMA_C3DAR + GPDMA channel x destination address register + 0x220 + 0x20 + read-write + 0x00000000 + + + DA + destination address + 0 + 32 + + + + + GPDMA_C4DAR + GPDMA_C4DAR + GPDMA channel x destination address register + 0x2A0 + 0x20 + read-write + 0x00000000 + + + DA + destination address + 0 + 32 + + + + + GPDMA_C5DAR + GPDMA_C5DAR + GPDMA channel x destination address register + 0x320 + 0x20 + read-write + 0x00000000 + + + DA + destination address + 0 + 32 + + + + + GPDMA_C6DAR + GPDMA_C6DAR + GPDMA channel x destination address register + 0x3A0 + 0x20 + read-write + 0x00000000 + + + DA + destination address + 0 + 32 + + + + + GPDMA_C7DAR + GPDMA_C7DAR + GPDMA channel x destination address register + 0x420 + 0x20 + read-write + 0x00000000 + + + DA + destination address + 0 + 32 + + + + + GPDMA_C8DAR + GPDMA_C8DAR + GPDMA channel x destination address register + 0x4A0 + 0x20 + read-write + 0x00000000 + + + DA + destination address + 0 + 32 + + + + + GPDMA_C9DAR + GPDMA_C9DAR + GPDMA channel x destination address register + 0x520 + 0x20 + read-write + 0x00000000 + + + DA + destination address + 0 + 32 + + + + + GPDMA_C10DAR + GPDMA_C10DAR + GPDMA channel x destination address register + 0x5A0 + 0x20 + read-write + 0x00000000 + + + DA + destination address + 0 + 32 + + + + + GPDMA_C11DAR + GPDMA_C11DAR + GPDMA channel x destination address register + 0x620 + 0x20 + read-write + 0x00000000 + + + DA + destination address + 0 + 32 + + + + + GPDMA_C12DAR + GPDMA_C12DAR + GPDMA channel x destination address register + 0x6A0 + 0x20 + read-write + 0x00000000 + + + DA + destination address + 0 + 32 + + + + + GPDMA_C13DAR + GPDMA_C13DAR + GPDMA channel x destination address register + 0x720 + 0x20 + read-write + 0x00000000 + + + DA + destination address + 0 + 32 + + + + + GPDMA_C14DAR + GPDMA_C14DAR + GPDMA channel x destination address register + 0x7A0 + 0x20 + read-write + 0x00000000 + + + DA + destination address + 0 + 32 + + + + + GPDMA_C15DAR + GPDMA_C15DAR + GPDMA channel x destination address register + 0x820 + 0x20 + read-write + 0x00000000 + + + DA + destination address + 0 + 32 + + + + + GPDMA_C3LLR + GPDMA_C3LLR + GPDMA channel x linked-list address register + 0x24C + 0x20 + read-write + 0x00000000 + + + LA + pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored. + 2 + 14 + + + ULL + Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update + 16 + 1 + + + UDA + Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update + 27 + 1 + + + USA + Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update + 28 + 1 + + + UB1 + Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update + 29 + 1 + + + UT2 + Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update + 30 + 1 + + + UT1 + Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update + 31 + 1 + + + + + GPDMA_C4LLR + GPDMA_C4LLR + GPDMA channel x linked-list address register + 0x2CC + 0x20 + read-write + 0x00000000 + + + LA + pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored. + 2 + 14 + + + ULL + Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update + 16 + 1 + + + UDA + Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update + 27 + 1 + + + USA + Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update + 28 + 1 + + + UB1 + Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update + 29 + 1 + + + UT2 + Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update + 30 + 1 + + + UT1 + Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update + 31 + 1 + + + + + GPDMA_C5LLR + GPDMA_C5LLR + GPDMA channel x linked-list address register + 0x34C + 0x20 + read-write + 0x00000000 + + + LA + pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored. + 2 + 14 + + + ULL + Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update + 16 + 1 + + + UDA + Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update + 27 + 1 + + + USA + Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update + 28 + 1 + + + UB1 + Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update + 29 + 1 + + + UT2 + Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update + 30 + 1 + + + UT1 + Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update + 31 + 1 + + + + + GPDMA_C6LLR + GPDMA_C6LLR + GPDMA channel x linked-list address register + 0x3CC + 0x20 + read-write + 0x00000000 + + + LA + pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored. + 2 + 14 + + + ULL + Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update + 16 + 1 + + + UDA + Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update + 27 + 1 + + + USA + Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update + 28 + 1 + + + UB1 + Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update + 29 + 1 + + + UT2 + Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update + 30 + 1 + + + UT1 + Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update + 31 + 1 + + + + + GPDMA_C7LLR + GPDMA_C7LLR + GPDMA channel x linked-list address register + 0x44C + 0x20 + read-write + 0x00000000 + + + LA + pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored. + 2 + 14 + + + ULL + Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update + 16 + 1 + + + UDA + Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update + 27 + 1 + + + USA + Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update + 28 + 1 + + + UB1 + Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update + 29 + 1 + + + UT2 + Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update + 30 + 1 + + + UT1 + Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update + 31 + 1 + + + + + GPDMA_C8LLR + GPDMA_C8LLR + GPDMA channel x linked-list address register + 0x4CC + 0x20 + read-write + 0x00000000 + + + LA + pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored. + 2 + 14 + + + ULL + Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update + 16 + 1 + + + UDA + Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update + 27 + 1 + + + USA + Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update + 28 + 1 + + + UB1 + Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update + 29 + 1 + + + UT2 + Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update + 30 + 1 + + + UT1 + Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update + 31 + 1 + + + + + GPDMA_C9LLR + GPDMA_C9LLR + GPDMA channel x linked-list address register + 0x54C + 0x20 + read-write + 0x00000000 + + + LA + pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored. + 2 + 14 + + + ULL + Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update + 16 + 1 + + + UDA + Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update + 27 + 1 + + + USA + Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update + 28 + 1 + + + UB1 + Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update + 29 + 1 + + + UT2 + Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update + 30 + 1 + + + UT1 + Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update + 31 + 1 + + + + + GPDMA_C10LLR + GPDMA_C10LLR + GPDMA channel x linked-list address register + 0x5CC + 0x20 + read-write + 0x00000000 + + + LA + pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored. + 2 + 14 + + + ULL + Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update + 16 + 1 + + + UDA + Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update + 27 + 1 + + + USA + Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update + 28 + 1 + + + UB1 + Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update + 29 + 1 + + + UT2 + Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update + 30 + 1 + + + UT1 + Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update + 31 + 1 + + + + + GPDMA_C11LLR + GPDMA_C11LLR + GPDMA channel x linked-list address register + 0x64C + 0x20 + read-write + 0x00000000 + + + LA + pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored. + 2 + 14 + + + ULL + Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update + 16 + 1 + + + UDA + Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update + 27 + 1 + + + USA + Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update + 28 + 1 + + + UB1 + Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update + 29 + 1 + + + UT2 + Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update + 30 + 1 + + + UT1 + Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update + 31 + 1 + + + + + GPDMA_C12LLR + GPDMA_C12LLR + GPDMA channel x linked-list address register + 0x6CC + 0x20 + read-write + 0x00000000 + + + LA + pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored. + 2 + 14 + + + ULL + Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update + 16 + 1 + + + UB2 + Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update + 25 + 1 + + + UT3 + Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update + 26 + 1 + + + UDA + Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update + 27 + 1 + + + USA + Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update + 28 + 1 + + + UB1 + Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update + 29 + 1 + + + UT2 + Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update + 30 + 1 + + + UT1 + Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update + 31 + 1 + + + + + GPDMA_C13LLR + GPDMA_C13LLR + GPDMA channel x linked-list address register + 0x74C + 0x20 + read-write + 0x00000000 + + + LA + pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored. + 2 + 14 + + + ULL + Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update + 16 + 1 + + + UB2 + Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update + 25 + 1 + + + UT3 + Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update + 26 + 1 + + + UDA + Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update + 27 + 1 + + + USA + Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update + 28 + 1 + + + UB1 + Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update + 29 + 1 + + + UT2 + Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update + 30 + 1 + + + UT1 + Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update + 31 + 1 + + + + + GPDMA_C14LLR + GPDMA_C14LLR + GPDMA channel x linked-list address register + 0x7CC + 0x20 + read-write + 0x00000000 + + + LA + pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored. + 2 + 14 + + + ULL + Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update + 16 + 1 + + + UB2 + Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update + 25 + 1 + + + UT3 + Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update + 26 + 1 + + + UDA + Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update + 27 + 1 + + + USA + Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update + 28 + 1 + + + UB1 + Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update + 29 + 1 + + + UT2 + Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update + 30 + 1 + + + UT1 + Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update + 31 + 1 + + + + + GPDMA_C15LLR + GPDMA_C15LLR + GPDMA channel x linked-list address register + 0x84C + 0x20 + read-write + 0x00000000 + + + LA + pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored. + 2 + 14 + + + ULL + Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update + 16 + 1 + + + UB2 + Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update + 25 + 1 + + + UT3 + Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update + 26 + 1 + + + UDA + Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update + 27 + 1 + + + USA + Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update + 28 + 1 + + + UB1 + Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update + 29 + 1 + + + UT2 + Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update + 30 + 1 + + + UT1 + Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update + 31 + 1 + + + + + GPDMA_C4LBAR + GPDMA_C4LBAR + channel x linked-list base address register + 0x250 + 0x20 + read-write + 0x00000000 + + + LBA + linked-list base address of DMA channel x + 16 + 16 + + + + + GPDMA_C5LBAR + GPDMA_C5LBAR + channel x linked-list base address register + 0x2D0 + 0x20 + read-write + 0x00000000 + + + LBA + linked-list base address of DMA channel x + 16 + 16 + + + + + GPDMA_C6LBAR + GPDMA_C6LBAR + channel x linked-list base address register + 0x350 + 0x20 + read-write + 0x00000000 + + + LBA + linked-list base address of DMA channel x + 16 + 16 + + + + + GPDMA_C7LBAR + GPDMA_C7LBAR + channel x linked-list base address register + 0x3D0 + 0x20 + read-write + 0x00000000 + + + LBA + linked-list base address of DMA channel x + 16 + 16 + + + + + GPDMA_C8LBAR + GPDMA_C8LBAR + channel x linked-list base address register + 0x450 + 0x20 + read-write + 0x00000000 + + + LBA + linked-list base address of DMA channel x + 16 + 16 + + + + + GPDMA_C9LBAR + GPDMA_C9LBAR + channel x linked-list base address register + 0x4D0 + 0x20 + read-write + 0x00000000 + + + LBA + linked-list base address of DMA channel x + 16 + 16 + + + + + GPDMA_C10LBAR + GPDMA_C10LBAR + channel x linked-list base address register + 0x550 + 0x20 + read-write + 0x00000000 + + + LBA + linked-list base address of DMA channel x + 16 + 16 + + + + + GPDMA_C11LBAR + GPDMA_C11LBAR + channel x linked-list base address register + 0x5D0 + 0x20 + read-write + 0x00000000 + + + LBA + linked-list base address of DMA channel x + 16 + 16 + + + + + GPDMA_C12LBAR + GPDMA_C12LBAR + channel x linked-list base address register + 0x650 + 0x20 + read-write + 0x00000000 + + + LBA + linked-list base address of DMA channel x + 16 + 16 + + + + + GPDMA_C13LBAR + GPDMA_C13LBAR + channel x linked-list base address register + 0x6D0 + 0x20 + read-write + 0x00000000 + + + LBA + linked-list base address of DMA channel x + 16 + 16 + + + + + GPDMA_C14LBAR + GPDMA_C14LBAR + channel x linked-list base address register + 0x750 + 0x20 + read-write + 0x00000000 + + + LBA + linked-list base address of DMA channel x + 16 + 16 + + + + + GPDMA_C15LBAR + GPDMA_C15LBAR + channel x linked-list base address register + 0x7D0 + 0x20 + read-write + 0x00000000 + + + LBA + linked-list base address of DMA channel x + 16 + 16 + + + + + GPDMA_C4FCR + GPDMA_C4FCR + GPDMA channel x flag clear register + 0x25C + 0x20 + write-only + 0x00000000 + + + TCF + transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag + 8 + 1 + + + HTF + half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag + 9 + 1 + + + DTEF + data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag + 10 + 1 + + + ULEF + update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag + 11 + 1 + + + USEF + user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag + 12 + 1 + + + SUSPF + completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag + 13 + 1 + + + TOF + trigger overrun flag clear + 14 + 1 + + + + + GPDMA_C5FCR + GPDMA_C5FCR + GPDMA channel x flag clear register + 0x2DC + 0x20 + write-only + 0x00000000 + + + TCF + transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag + 8 + 1 + + + HTF + half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag + 9 + 1 + + + DTEF + data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag + 10 + 1 + + + ULEF + update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag + 11 + 1 + + + USEF + user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag + 12 + 1 + + + SUSPF + completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag + 13 + 1 + + + TOF + trigger overrun flag clear + 14 + 1 + + + + + GPDMA_C6FCR + GPDMA_C6FCR + GPDMA channel x flag clear register + 0x35C + 0x20 + write-only + 0x00000000 + + + TCF + transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag + 8 + 1 + + + HTF + half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag + 9 + 1 + + + DTEF + data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag + 10 + 1 + + + ULEF + update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag + 11 + 1 + + + USEF + user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag + 12 + 1 + + + SUSPF + completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag + 13 + 1 + + + TOF + trigger overrun flag clear + 14 + 1 + + + + + GPDMA_C7FCR + GPDMA_C7FCR + GPDMA channel x flag clear register + 0x3DC + 0x20 + write-only + 0x00000000 + + + TCF + transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag + 8 + 1 + + + HTF + half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag + 9 + 1 + + + DTEF + data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag + 10 + 1 + + + ULEF + update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag + 11 + 1 + + + USEF + user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag + 12 + 1 + + + SUSPF + completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag + 13 + 1 + + + TOF + trigger overrun flag clear + 14 + 1 + + + + + GPDMA_C8FCR + GPDMA_C8FCR + GPDMA channel x flag clear register + 0x45C + 0x20 + write-only + 0x00000000 + + + TCF + transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag + 8 + 1 + + + HTF + half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag + 9 + 1 + + + DTEF + data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag + 10 + 1 + + + ULEF + update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag + 11 + 1 + + + USEF + user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag + 12 + 1 + + + SUSPF + completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag + 13 + 1 + + + TOF + trigger overrun flag clear + 14 + 1 + + + + + GPDMA_C9FCR + GPDMA_C9FCR + GPDMA channel x flag clear register + 0x4DC + 0x20 + write-only + 0x00000000 + + + TCF + transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag + 8 + 1 + + + HTF + half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag + 9 + 1 + + + DTEF + data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag + 10 + 1 + + + ULEF + update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag + 11 + 1 + + + USEF + user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag + 12 + 1 + + + SUSPF + completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag + 13 + 1 + + + TOF + trigger overrun flag clear + 14 + 1 + + + + + GPDMA_C10FCR + GPDMA_C10FCR + GPDMA channel x flag clear register + 0x55C + 0x20 + write-only + 0x00000000 + + + TCF + transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag + 8 + 1 + + + HTF + half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag + 9 + 1 + + + DTEF + data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag + 10 + 1 + + + ULEF + update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag + 11 + 1 + + + USEF + user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag + 12 + 1 + + + SUSPF + completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag + 13 + 1 + + + TOF + trigger overrun flag clear + 14 + 1 + + + + + GPDMA_C11FCR + GPDMA_C11FCR + GPDMA channel x flag clear register + 0x5DC + 0x20 + write-only + 0x00000000 + + + TCF + transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag + 8 + 1 + + + HTF + half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag + 9 + 1 + + + DTEF + data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag + 10 + 1 + + + ULEF + update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag + 11 + 1 + + + USEF + user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag + 12 + 1 + + + SUSPF + completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag + 13 + 1 + + + TOF + trigger overrun flag clear + 14 + 1 + + + + + GPDMA_C12FCR + GPDMA_C12FCR + GPDMA channel x flag clear register + 0x65C + 0x20 + write-only + 0x00000000 + + + TCF + transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag + 8 + 1 + + + HTF + half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag + 9 + 1 + + + DTEF + data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag + 10 + 1 + + + ULEF + update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag + 11 + 1 + + + USEF + user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag + 12 + 1 + + + SUSPF + completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag + 13 + 1 + + + TOF + trigger overrun flag clear + 14 + 1 + + + + + GPDMA_C13FCR + GPDMA_C13FCR + GPDMA channel x flag clear register + 0x6DC + 0x20 + write-only + 0x00000000 + + + TCF + transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag + 8 + 1 + + + HTF + half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag + 9 + 1 + + + DTEF + data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag + 10 + 1 + + + ULEF + update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag + 11 + 1 + + + USEF + user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag + 12 + 1 + + + SUSPF + completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag + 13 + 1 + + + TOF + trigger overrun flag clear + 14 + 1 + + + + + GPDMA_C14FCR + GPDMA_C14FCR + GPDMA channel x flag clear register + 0x75C + 0x20 + write-only + 0x00000000 + + + TCF + transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag + 8 + 1 + + + HTF + half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag + 9 + 1 + + + DTEF + data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag + 10 + 1 + + + ULEF + update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag + 11 + 1 + + + USEF + user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag + 12 + 1 + + + SUSPF + completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag + 13 + 1 + + + TOF + trigger overrun flag clear + 14 + 1 + + + + + GPDMA_C15FCR + GPDMA_C15FCR + GPDMA channel x flag clear register + 0x7DC + 0x20 + write-only + 0x00000000 + + + TCF + transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag + 8 + 1 + + + HTF + half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag + 9 + 1 + + + DTEF + data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag + 10 + 1 + + + ULEF + update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag + 11 + 1 + + + USEF + user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag + 12 + 1 + + + SUSPF + completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag + 13 + 1 + + + TOF + trigger overrun flag clear + 14 + 1 + + + + + GPDMA_C4SR + GPDMA_C4SR + channel x status register + 0x260 + 0x20 + read-only + 0x00000001 + + + IDLEF + idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state). + 0 + 1 + + + TCF + transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. + 8 + 1 + + + HTF + half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination. + 9 + 1 + + + DTEF + data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer + 10 + 1 + + + ULEF + update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory + 11 + 1 + + + USEF + user setting error flag - 0: no user setting error event - 1: a user setting error event occurred + 12 + 1 + + + SUSPF + completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred + 13 + 1 + + + FIFOL + monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1. + 16 + 8 + + + + + GPDMA_C5SR + GPDMA_C5SR + channel x status register + 0x2E0 + 0x20 + read-only + 0x00000001 + + + IDLEF + idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state). + 0 + 1 + + + TCF + transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. + 8 + 1 + + + HTF + half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination. + 9 + 1 + + + DTEF + data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer + 10 + 1 + + + ULEF + update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory + 11 + 1 + + + USEF + user setting error flag - 0: no user setting error event - 1: a user setting error event occurred + 12 + 1 + + + SUSPF + completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred + 13 + 1 + + + FIFOL + monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1. + 16 + 8 + + + + + GPDMA_C6SR + GPDMA_C6SR + channel x status register + 0x360 + 0x20 + read-only + 0x00000001 + + + IDLEF + idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state). + 0 + 1 + + + TCF + transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. + 8 + 1 + + + HTF + half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination. + 9 + 1 + + + DTEF + data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer + 10 + 1 + + + ULEF + update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory + 11 + 1 + + + USEF + user setting error flag - 0: no user setting error event - 1: a user setting error event occurred + 12 + 1 + + + SUSPF + completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred + 13 + 1 + + + FIFOL + monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1. + 16 + 8 + + + + + GPDMA_C7SR + GPDMA_C7SR + channel x status register + 0x3E0 + 0x20 + read-only + 0x00000001 + + + IDLEF + idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state). + 0 + 1 + + + TCF + transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. + 8 + 1 + + + HTF + half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination. + 9 + 1 + + + DTEF + data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer + 10 + 1 + + + ULEF + update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory + 11 + 1 + + + USEF + user setting error flag - 0: no user setting error event - 1: a user setting error event occurred + 12 + 1 + + + SUSPF + completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred + 13 + 1 + + + FIFOL + monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1. + 16 + 8 + + + + + GPDMA_C8SR + GPDMA_C8SR + channel x status register + 0x460 + 0x20 + read-only + 0x00000001 + + + IDLEF + idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state). + 0 + 1 + + + TCF + transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. + 8 + 1 + + + HTF + half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination. + 9 + 1 + + + DTEF + data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer + 10 + 1 + + + ULEF + update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory + 11 + 1 + + + USEF + user setting error flag - 0: no user setting error event - 1: a user setting error event occurred + 12 + 1 + + + SUSPF + completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred + 13 + 1 + + + FIFOL + monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1. + 16 + 8 + + + + + GPDMA_C9SR + GPDMA_C9SR + channel x status register + 0x4E0 + 0x20 + read-only + 0x00000001 + + + IDLEF + idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state). + 0 + 1 + + + TCF + transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. + 8 + 1 + + + HTF + half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination. + 9 + 1 + + + DTEF + data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer + 10 + 1 + + + ULEF + update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory + 11 + 1 + + + USEF + user setting error flag - 0: no user setting error event - 1: a user setting error event occurred + 12 + 1 + + + SUSPF + completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred + 13 + 1 + + + FIFOL + monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1. + 16 + 8 + + + + + GPDMA_C10SR + GPDMA_C10SR + channel x status register + 0x560 + 0x20 + read-only + 0x00000001 + + + IDLEF + idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state). + 0 + 1 + + + TCF + transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. + 8 + 1 + + + HTF + half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination. + 9 + 1 + + + DTEF + data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer + 10 + 1 + + + ULEF + update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory + 11 + 1 + + + USEF + user setting error flag - 0: no user setting error event - 1: a user setting error event occurred + 12 + 1 + + + SUSPF + completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred + 13 + 1 + + + FIFOL + monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1. + 16 + 8 + + + + + GPDMA_C11SR + GPDMA_C11SR + channel x status register + 0x5E0 + 0x20 + read-only + 0x00000001 + + + IDLEF + idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state). + 0 + 1 + + + TCF + transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. + 8 + 1 + + + HTF + half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination. + 9 + 1 + + + DTEF + data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer + 10 + 1 + + + ULEF + update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory + 11 + 1 + + + USEF + user setting error flag - 0: no user setting error event - 1: a user setting error event occurred + 12 + 1 + + + SUSPF + completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred + 13 + 1 + + + FIFOL + monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1. + 16 + 8 + + + + + GPDMA_C12SR + GPDMA_C12SR + channel x status register + 0x660 + 0x20 + read-only + 0x00000001 + + + IDLEF + idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state). + 0 + 1 + + + TCF + transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. + 8 + 1 + + + HTF + half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination. + 9 + 1 + + + DTEF + data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer + 10 + 1 + + + ULEF + update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory + 11 + 1 + + + USEF + user setting error flag - 0: no user setting error event - 1: a user setting error event occurred + 12 + 1 + + + SUSPF + completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred + 13 + 1 + + + FIFOL + monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1. + 16 + 8 + + + + + GPDMA_C13SR + GPDMA_C13SR + channel x status register + 0x6E0 + 0x20 + read-only + 0x00000001 + + + IDLEF + idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state). + 0 + 1 + + + TCF + transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. + 8 + 1 + + + HTF + half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination. + 9 + 1 + + + DTEF + data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer + 10 + 1 + + + ULEF + update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory + 11 + 1 + + + USEF + user setting error flag - 0: no user setting error event - 1: a user setting error event occurred + 12 + 1 + + + SUSPF + completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred + 13 + 1 + + + FIFOL + monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1. + 16 + 8 + + + + + GPDMA_C14SR + GPDMA_C14SR + channel x status register + 0x760 + 0x20 + read-only + 0x00000001 + + + IDLEF + idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state). + 0 + 1 + + + TCF + transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. + 8 + 1 + + + HTF + half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination. + 9 + 1 + + + DTEF + data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer + 10 + 1 + + + ULEF + update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory + 11 + 1 + + + USEF + user setting error flag - 0: no user setting error event - 1: a user setting error event occurred + 12 + 1 + + + SUSPF + completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred + 13 + 1 + + + FIFOL + monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1. + 16 + 8 + + + + + GPDMA_C15SR + GPDMA_C15SR + channel x status register + 0x7E0 + 0x20 + read-only + 0x00000001 + + + IDLEF + idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state). + 0 + 1 + + + TCF + transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. + 8 + 1 + + + HTF + half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination. + 9 + 1 + + + DTEF + data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer + 10 + 1 + + + ULEF + update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory + 11 + 1 + + + USEF + user setting error flag - 0: no user setting error event - 1: a user setting error event occurred + 12 + 1 + + + SUSPF + completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred + 13 + 1 + + + FIFOL + monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1. + 16 + 8 + + + + + GPDMA_C4CR + GPDMA_C4CR + channel x control register + 0x264 + 0x20 + read-write + 0x00000000 + + + EN + enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. + 0 + 1 + + + RESET + reset + 1 + 1 + + + SUSP + suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence. + 2 + 1 + + + TCIE + transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 8 + 1 + + + HTIE + half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 9 + 1 + + + DTEIE + data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 10 + 1 + + + ULEIE + update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 11 + 1 + + + USEIE + user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 12 + 1 + + + SUSPIE + completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 13 + 1 + + + LSM + Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1. + 16 + 1 + + + LAP + linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 17 + 1 + + + PRIO + priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 22 + 2 + + + + + GPDMA_C5CR + GPDMA_C5CR + channel x control register + 0x2E4 + 0x20 + read-write + 0x00000000 + + + EN + enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. + 0 + 1 + + + RESET + reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence. + 1 + 1 + + + SUSP + suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence. + 2 + 1 + + + TCIE + transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 8 + 1 + + + HTIE + half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 9 + 1 + + + DTEIE + data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 10 + 1 + + + ULEIE + update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 11 + 1 + + + USEIE + user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 12 + 1 + + + SUSPIE + completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 13 + 1 + + + LSM + Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1. + 16 + 1 + + + LAP + linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 17 + 1 + + + PRIO + priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 22 + 2 + + + + + GPDMA_C6CR + GPDMA_C6CR + channel x control register + 0x364 + 0x20 + read-write + 0x00000000 + + + EN + enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. + 0 + 1 + + + RESET + reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence. + 1 + 1 + + + SUSP + suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence. + 2 + 1 + + + TCIE + transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 8 + 1 + + + HTIE + half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 9 + 1 + + + DTEIE + data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 10 + 1 + + + ULEIE + update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 11 + 1 + + + USEIE + user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 12 + 1 + + + SUSPIE + completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 13 + 1 + + + LSM + Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1. + 16 + 1 + + + LAP + linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 17 + 1 + + + PRIO + priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 22 + 2 + + + + + GPDMA_C7CR + GPDMA_C7CR + channel x control register + 0x3E4 + 0x20 + read-write + 0x00000000 + + + EN + enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. + 0 + 1 + + + RESET + reset + 1 + 1 + + + SUSP + suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence. + 2 + 1 + + + TCIE + transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 8 + 1 + + + HTIE + half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 9 + 1 + + + DTEIE + data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 10 + 1 + + + ULEIE + update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 11 + 1 + + + USEIE + user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 12 + 1 + + + SUSPIE + completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 13 + 1 + + + LSM + Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1. + 16 + 1 + + + LAP + linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 17 + 1 + + + PRIO + priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 22 + 2 + + + + + GPDMA_C8CR + GPDMA_C8CR + channel x control register + 0x464 + 0x20 + read-write + 0x00000000 + + + EN + enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. + 0 + 1 + + + RESET + reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence. + 1 + 1 + + + SUSP + suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence. + 2 + 1 + + + TCIE + transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 8 + 1 + + + HTIE + half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 9 + 1 + + + DTEIE + data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 10 + 1 + + + ULEIE + update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 11 + 1 + + + USEIE + user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 12 + 1 + + + SUSPIE + completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 13 + 1 + + + LSM + Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1. + 16 + 1 + + + LAP + linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 17 + 1 + + + PRIO + priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 22 + 2 + + + + + GPDMA_C9CR + GPDMA_C9CR + channel x control register + 0x4E4 + 0x20 + read-write + 0x00000000 + + + EN + enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. + 0 + 1 + + + RESET + reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence. + 1 + 1 + + + SUSP + suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence. + 2 + 1 + + + TCIE + transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 8 + 1 + + + HTIE + half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 9 + 1 + + + DTEIE + data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 10 + 1 + + + ULEIE + update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 11 + 1 + + + USEIE + user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 12 + 1 + + + SUSPIE + completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 13 + 1 + + + LSM + Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1. + 16 + 1 + + + LAP + linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 17 + 1 + + + PRIO + priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 22 + 2 + + + + + GPDMA_C10CR + GPDMA_C10CR + channel x control register + 0x564 + 0x20 + read-write + 0x00000000 + + + EN + enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. + 0 + 1 + + + RESET + reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence. + 1 + 1 + + + SUSP + suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence. + 2 + 1 + + + TCIE + transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 8 + 1 + + + HTIE + half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 9 + 1 + + + DTEIE + data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 10 + 1 + + + ULEIE + update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 11 + 1 + + + USEIE + user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 12 + 1 + + + SUSPIE + completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 13 + 1 + + + LSM + Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1. + 16 + 1 + + + LAP + linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 17 + 1 + + + PRIO + priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 22 + 2 + + + + + GPDMA_C11CR + GPDMA_C11CR + channel x control register + 0x5E4 + 0x20 + read-write + 0x00000000 + + + EN + enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. + 0 + 1 + + + RESET + reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence. + 1 + 1 + + + SUSP + suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence. + 2 + 1 + + + TCIE + transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 8 + 1 + + + HTIE + half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 9 + 1 + + + DTEIE + data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 10 + 1 + + + ULEIE + update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 11 + 1 + + + USEIE + user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 12 + 1 + + + SUSPIE + completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 13 + 1 + + + LSM + Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1. + 16 + 1 + + + LAP + linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 17 + 1 + + + PRIO + priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 22 + 2 + + + + + GPDMA_C12CR + GPDMA_C12CR + channel x control register + 0x664 + 0x20 + read-write + 0x00000000 + + + EN + enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. + 0 + 1 + + + RESET + reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence. + 1 + 1 + + + SUSP + suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence. + 2 + 1 + + + TCIE + transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 8 + 1 + + + HTIE + half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 9 + 1 + + + DTEIE + data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 10 + 1 + + + ULEIE + update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 11 + 1 + + + USEIE + user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 12 + 1 + + + SUSPIE + completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 13 + 1 + + + LSM + Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1. + 16 + 1 + + + LAP + linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 17 + 1 + + + PRIO + priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 22 + 2 + + + + + GPDMA_C13CR + GPDMA_C13CR + channel x control register + 0x6E4 + 0x20 + read-write + 0x00000000 + + + EN + enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. + 0 + 1 + + + RESET + reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence. + 1 + 1 + + + SUSP + suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence. + 2 + 1 + + + TCIE + transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 8 + 1 + + + HTIE + half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 9 + 1 + + + DTEIE + data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 10 + 1 + + + ULEIE + update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 11 + 1 + + + USEIE + user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 12 + 1 + + + SUSPIE + completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 13 + 1 + + + LSM + Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1. + 16 + 1 + + + LAP + linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 17 + 1 + + + PRIO + priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 22 + 2 + + + + + GPDMA_C14CR + GPDMA_C14CR + channel x control register + 0x764 + 0x20 + read-write + 0x00000000 + + + EN + enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. + 0 + 1 + + + RESET + reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence. + 1 + 1 + + + SUSP + suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence. + 2 + 1 + + + TCIE + transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 8 + 1 + + + HTIE + half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 9 + 1 + + + DTEIE + data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 10 + 1 + + + ULEIE + update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 11 + 1 + + + USEIE + user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 12 + 1 + + + SUSPIE + completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 13 + 1 + + + LSM + Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1. + 16 + 1 + + + LAP + linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 17 + 1 + + + PRIO + priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 22 + 2 + + + + + GPDMA_C15CR + GPDMA_C15CR + channel x control register + 0x7E4 + 0x20 + read-write + 0x00000000 + + + EN + enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. + 0 + 1 + + + RESET + reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence. + 1 + 1 + + + SUSP + suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence. + 2 + 1 + + + TCIE + transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 8 + 1 + + + HTIE + half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 9 + 1 + + + DTEIE + data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 10 + 1 + + + ULEIE + update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 11 + 1 + + + USEIE + user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 12 + 1 + + + SUSPIE + completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 13 + 1 + + + LSM + Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1. + 16 + 1 + + + LAP + linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 17 + 1 + + + PRIO + priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 22 + 2 + + + + + GPDMA_C12TR3 + GPDMA_C12TR3 + GPDMA channel x transfer register 3 + 0x6A4 + 0x20 + read-write + 0x00000000 + + + SAO + source address offset increment The source address, pointed by GPDMA_CxSAR, is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode i.e. if GPDMA_CxTR1.SINC=1. Note: A source address offset must be aligned with the programmed data width of a source burst (c.f. SAO[2:0] vs GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. + 0 + 13 + + + DAO + destination address offset increment The destination address, pointed by GPDMA_CxDAR, is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode i.e. if GPDMA_CxTR1.DINC=1. Note: A destination address offset must be aligned with the programmed data width of a destination burst (c.f. DAO[2:0] vs GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. Note: When the source block size is not a multiple of the destination burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional GPDMA_CxTR3.SAO[12:0] is not applied. + 16 + 13 + + + + + GPDMA_C13TR3 + GPDMA_C13TR3 + GPDMA channel x transfer register 3 + 0x724 + 0x20 + read-write + 0x00000000 + + + SAO + source address offset increment The source address, pointed by GPDMA_CxSAR, is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode i.e. if GPDMA_CxTR1.SINC=1. Note: A source address offset must be aligned with the programmed data width of a source burst (c.f. SAO[2:0] vs GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. + 0 + 13 + + + DAO + destination address offset increment The destination address, pointed by GPDMA_CxDAR, is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode i.e. if GPDMA_CxTR1.DINC=1. Note: A destination address offset must be aligned with the programmed data width of a destination burst (c.f. DAO[2:0] vs GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. Note: When the source block size is not a multiple of the destination burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional GPDMA_CxTR3.SAO[12:0] is not applied. + 16 + 13 + + + + + GPDMA_C14TR3 + GPDMA_C14TR3 + GPDMA channel x transfer register 3 + 0x7A4 + 0x20 + read-write + 0x00000000 + + + SAO + source address offset increment The source address, pointed by GPDMA_CxSAR, is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode i.e. if GPDMA_CxTR1.SINC=1. Note: A source address offset must be aligned with the programmed data width of a source burst (c.f. SAO[2:0] vs GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. + 0 + 13 + + + DAO + destination address offset increment The destination address, pointed by GPDMA_CxDAR, is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode i.e. if GPDMA_CxTR1.DINC=1. Note: A destination address offset must be aligned with the programmed data width of a destination burst (c.f. DAO[2:0] vs GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. Note: When the source block size is not a multiple of the destination burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional GPDMA_CxTR3.SAO[12:0] is not applied. + 16 + 13 + + + + + GPDMA_C15TR3 + GPDMA_C15TR3 + GPDMA channel x transfer register 3 + 0x824 + 0x20 + read-write + 0x00000000 + + + SAO + source address offset increment The source address, pointed by GPDMA_CxSAR, is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode i.e. if GPDMA_CxTR1.SINC=1. Note: A source address offset must be aligned with the programmed data width of a source burst (c.f. SAO[2:0] vs GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. + 0 + 13 + + + DAO + destination address offset increment The destination address, pointed by GPDMA_CxDAR, is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode i.e. if GPDMA_CxTR1.DINC=1. Note: A destination address offset must be aligned with the programmed data width of a destination burst (c.f. DAO[2:0] vs GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. Note: When the source block size is not a multiple of the destination burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional GPDMA_CxTR3.SAO[12:0] is not applied. + 16 + 13 + + + + + GPDMA_C12BR2 + GPDMA_C12BR2 + GPDMA channel x block register 2 + 0x6A8 + 0x20 + read-write + 0x00000000 + + + BRSAO + Block repeated source address offset For a channel with 2D addressing capability, this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a block transfer. Note: A block repeated source address offset must be aligned with the programmed data width of a source burst (c.f. BRSAO[2:0] vs GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. + 0 + 16 + + + BRDAO + Block repeated destination address offset For a channel with 2D addressing capability, this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the end of a block transfer. Note: A block repeated destination address offset must be aligned with the programmed data width of a destination burst (c.f. BRDAO[2:0] vs GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. + 16 + 16 + + + + + GPDMA_C13BR2 + GPDMA_C13BR2 + GPDMA channel x block register 2 + 0x728 + 0x20 + read-write + 0x00000000 + + + BRSAO + Block repeated source address offset For a channel with 2D addressing capability, this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a block transfer. Note: A block repeated source address offset must be aligned with the programmed data width of a source burst (c.f. BRSAO[2:0] vs GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. + 0 + 16 + + + BRDAO + Block repeated destination address offset For a channel with 2D addressing capability, this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the end of a block transfer. Note: A block repeated destination address offset must be aligned with the programmed data width of a destination burst (c.f. BRDAO[2:0] vs GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. + 16 + 16 + + + + + GPDMA_C14BR2 + GPDMA_C14BR2 + GPDMA channel x block register 2 + 0x7A8 + 0x20 + read-write + 0x00000000 + + + BRSAO + Block repeated source address offset For a channel with 2D addressing capability, this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a block transfer. Note: A block repeated source address offset must be aligned with the programmed data width of a source burst (c.f. BRSAO[2:0] vs GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. + 0 + 16 + + + BRDAO + Block repeated destination address offset For a channel with 2D addressing capability, this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the end of a block transfer. Note: A block repeated destination address offset must be aligned with the programmed data width of a destination burst (c.f. BRDAO[2:0] vs GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. + 16 + 16 + + + + + GPDMA_C15BR2 + GPDMA_C15BR2 + GPDMA channel x block register 2 + 0x828 + 0x20 + read-write + 0x00000000 + + + BRSAO + Block repeated source address offset For a channel with 2D addressing capability, this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a block transfer. Note: A block repeated source address offset must be aligned with the programmed data width of a source burst (c.f. BRSAO[2:0] vs GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. + 0 + 16 + + + BRDAO + Block repeated destination address offset For a channel with 2D addressing capability, this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the end of a block transfer. Note: A block repeated destination address offset must be aligned with the programmed data width of a destination burst (c.f. BRDAO[2:0] vs GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. + 16 + 16 + + + + + + + SEC_GPDMA1 + DCB->DSCSR->CDS == 0 + 0x50020000 + + + GPIOA + General-purpose I/Os + GPIO + 0x42020000 + + 0x0 + 0x400 + registers + + + + GPIO_MODER + GPIO_MODER + GPIO port mode register + 0x00 + 0x20 + 0xABFFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + + + GPIO_OTYPER + GPIO_OTYPER + GPIO port output type register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIO_OSPEEDR + GPIO_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + 0x0C000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + + + GPIO_PUPDR + GPIO_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + 0x64000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + + + GPIO_IDR + GPIO_IDR + GPIO port input data register + 0x10 + 0x20 + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + read-only + + + ID1 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + read-only + + + ID2 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + read-only + + + ID3 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + read-only + + + ID4 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + read-only + + + ID5 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + read-only + + + ID6 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + read-only + + + ID7 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + read-only + + + ID8 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + read-only + + + ID9 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + read-only + + + ID10 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + read-only + + + ID11 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + read-only + + + ID12 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + read-only + + + ID13 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + read-only + + + ID14 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + read-only + + + ID15 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + read-only + + + + + GPIO_ODR + GPIO_ODR + GPIO port output data register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + read-write + + + OD1 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + read-write + + + OD2 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + read-write + + + OD3 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + read-write + + + OD4 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + read-write + + + OD5 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + read-write + + + OD6 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + read-write + + + OD7 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + read-write + + + OD8 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + read-write + + + OD9 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + read-write + + + OD10 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + read-write + + + OD11 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + read-write + + + OD12 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + read-write + + + OD13 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + read-write + + + OD14 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + read-write + + + OD15 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + read-write + + + + + GPIO_BSRR + GPIO_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS1 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS2 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS3 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS4 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS5 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS6 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS7 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS8 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS9 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS10 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS11 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS12 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS13 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS14 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS15 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BR0 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + + + GPIO_LCKR + GPIO_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +- LOCK key write sequence: +WR LCKR[16] = 1 + LCKR[15:0] +WR LCKR[16] = 0 + LCKR[15:0] +WR LCKR[16] = 1 + LCKR[15:0] +- LOCK key read +RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) +Note: During the lock key write sequence, the value of LCK[15:0] must not change. +Note: Any error in the lock sequence aborts the LOCK. +Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. + 0x1 + + + + + + + GPIO_AFRL + GPIO_AFRL + GPIO alternate function low register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIO_AFRH + GPIO_AFRH + GPIO alternate function high register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIO_BRR + GPIO_BRR + GPIO port bit reset register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + + + GPIO_HSLVR + GPIO_HSLVR + GPIO high-speed low-voltage register + 0x2C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + HSLV0 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV1 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV2 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV3 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV4 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV5 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV6 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV7 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV8 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV9 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV10 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV11 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV12 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV13 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV14 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV15 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + + + GPIO_SECCFGR + GPIO_SECCFGR + GPIO secure configuration register + 0x30 + 0x20 + 0x0000FFFF + 0xFFFFFFFF + + + SEC0 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC1 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC2 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC3 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC4 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC5 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC6 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC7 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC8 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC9 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC10 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC11 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC12 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC13 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC14 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC15 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + + + + + SEC_GPIOA + DCB->DSCSR->CDS == 0 + 0x52020000 + + + GPIOB + General-purpose I/Os + GPIO + 0x42020400 + + 0x0 + 0x400 + registers + + + + GPIO_MODER + GPIO_MODER + GPIO port mode register + 0x00 + 0x20 + 0xFFFFFEBF + 0xFFFFFFFF + + + MODE0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + + + GPIO_OTYPER + GPIO_OTYPER + GPIO port output type register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIO_OSPEEDR + GPIO_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + 0x000000C0 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + + + GPIO_PUPDR + GPIO_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + 0x00000100 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + + + GPIO_IDR + GPIO_IDR + GPIO port input data register + 0x10 + 0x20 + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + read-only + + + ID1 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + read-only + + + ID2 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + read-only + + + ID3 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + read-only + + + ID4 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + read-only + + + ID5 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + read-only + + + ID6 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + read-only + + + ID7 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + read-only + + + ID8 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + read-only + + + ID9 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + read-only + + + ID10 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + read-only + + + ID11 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + read-only + + + ID12 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + read-only + + + ID13 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + read-only + + + ID14 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + read-only + + + ID15 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + read-only + + + + + GPIO_ODR + GPIO_ODR + GPIO port output data register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + read-write + + + OD1 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + read-write + + + OD2 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + read-write + + + OD3 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + read-write + + + OD4 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + read-write + + + OD5 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + read-write + + + OD6 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + read-write + + + OD7 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + read-write + + + OD8 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + read-write + + + OD9 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + read-write + + + OD10 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + read-write + + + OD11 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + read-write + + + OD12 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + read-write + + + OD13 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + read-write + + + OD14 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + read-write + + + OD15 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + read-write + + + + + GPIO_BSRR + GPIO_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS1 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS2 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS3 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS4 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS5 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS6 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS7 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS8 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS9 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS10 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS11 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS12 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS13 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS14 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS15 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BR0 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + + + GPIO_LCKR + GPIO_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +- LOCK key write sequence: +WR LCKR[16] = 1 + LCKR[15:0] +WR LCKR[16] = 0 + LCKR[15:0] +WR LCKR[16] = 1 + LCKR[15:0] +- LOCK key read +RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) +Note: During the lock key write sequence, the value of LCK[15:0] must not change. +Note: Any error in the lock sequence aborts the LOCK. +Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. + 0x1 + + + + + + + GPIO_AFRL + GPIO_AFRL + GPIO alternate function low register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIO_AFRH + GPIO_AFRH + GPIO alternate function high register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIO_BRR + GPIO_BRR + GPIO port bit reset register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + + + GPIO_HSLVR + GPIO_HSLVR + GPIO high-speed low-voltage register + 0x2C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + HSLV0 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV1 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV2 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV3 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV4 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV5 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV6 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV7 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV8 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV9 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV10 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV11 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV12 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV13 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV14 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV15 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + + + GPIO_SECCFGR + GPIO_SECCFGR + GPIO secure configuration register + 0x30 + 0x20 + 0x0000FFFF + 0xFFFFFFFF + + + SEC0 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC1 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC2 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC3 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC4 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC5 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC6 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC7 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC8 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC9 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC10 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC11 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC12 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC13 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC14 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC15 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + + + + + SEC_GPIOB + DCB->DSCSR->CDS == 0 + 0x52020400 + + + GPIOC + General-purpose I/Os + GPIO + 0x42020800 + + 0x0 + 0x400 + registers + + + + GPIO_MODER + GPIO_MODER + GPIO port mode register + 0x00 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + + + GPIO_OTYPER + GPIO_OTYPER + GPIO port output type register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIO_OSPEEDR + GPIO_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + + + GPIO_PUPDR + GPIO_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + + + GPIO_IDR + GPIO_IDR + GPIO port input data register + 0x10 + 0x20 + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + read-only + + + ID1 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + read-only + + + ID2 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + read-only + + + ID3 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + read-only + + + ID4 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + read-only + + + ID5 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + read-only + + + ID6 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + read-only + + + ID7 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + read-only + + + ID8 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + read-only + + + ID9 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + read-only + + + ID10 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + read-only + + + ID11 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + read-only + + + ID12 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + read-only + + + ID13 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + read-only + + + ID14 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + read-only + + + ID15 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + read-only + + + + + GPIO_ODR + GPIO_ODR + GPIO port output data register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + read-write + + + OD1 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + read-write + + + OD2 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + read-write + + + OD3 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + read-write + + + OD4 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + read-write + + + OD5 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + read-write + + + OD6 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + read-write + + + OD7 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + read-write + + + OD8 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + read-write + + + OD9 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + read-write + + + OD10 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + read-write + + + OD11 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + read-write + + + OD12 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + read-write + + + OD13 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + read-write + + + OD14 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + read-write + + + OD15 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + read-write + + + + + GPIO_BSRR + GPIO_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS1 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS2 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS3 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS4 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS5 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS6 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS7 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS8 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS9 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS10 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS11 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS12 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS13 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS14 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS15 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BR0 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + + + GPIO_LCKR + GPIO_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +- LOCK key write sequence: +WR LCKR[16] = 1 + LCKR[15:0] +WR LCKR[16] = 0 + LCKR[15:0] +WR LCKR[16] = 1 + LCKR[15:0] +- LOCK key read +RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) +Note: During the lock key write sequence, the value of LCK[15:0] must not change. +Note: Any error in the lock sequence aborts the LOCK. +Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. + 0x1 + + + + + + + GPIO_AFRL + GPIO_AFRL + GPIO alternate function low register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIO_AFRH + GPIO_AFRH + GPIO alternate function high register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIO_BRR + GPIO_BRR + GPIO port bit reset register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + + + GPIO_HSLVR + GPIO_HSLVR + GPIO high-speed low-voltage register + 0x2C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + HSLV0 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV1 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV2 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV3 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV4 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV5 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV6 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV7 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV8 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV9 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV10 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV11 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV12 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV13 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV14 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV15 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + + + GPIO_SECCFGR + GPIO_SECCFGR + GPIO secure configuration register + 0x30 + 0x20 + 0x0000FFFF + 0xFFFFFFFF + + + SEC0 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC1 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC2 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC3 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC4 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC5 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC6 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC7 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC8 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC9 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC10 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC11 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC12 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC13 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC14 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC15 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + + + + + SEC_GPIOC + DCB->DSCSR->CDS == 0 + 0x52020800 + + + GPIOD + 0x42020C00 + + + SEC_GPIOD + DCB->DSCSR->CDS == 0 + 0x52020C00 + + + GPIOE + 0x42021000 + + + SEC_GPIOE + DCB->DSCSR->CDS == 0 + 0x52021000 + + + GPIOF + 0x42021400 + + + SEC_GPIOF + DCB->DSCSR->CDS == 0 + 0x52021400 + + + GPIOG + 0x42021800 + + + SEC_GPIOG + DCB->DSCSR->CDS == 0 + 0x52021800 + + + GPIOH + General-purpose I/Os + GPIO + 0x42021C00 + + 0x0 + 0x400 + registers + + + + GPIO_MODER + GPIO_MODER + GPIO port mode register + 0x00 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + + + GPIO_OTYPER + GPIO_OTYPER + GPIO port output type register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIO_OSPEEDR + GPIO_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + + + GPIO_PUPDR + GPIO_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + + + GPIO_IDR + GPIO_IDR + GPIO port input data register + 0x10 + 0x20 + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + read-only + + + ID1 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + read-only + + + ID2 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + read-only + + + ID3 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + read-only + + + ID4 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + read-only + + + ID5 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + read-only + + + ID6 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + read-only + + + ID7 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + read-only + + + ID8 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + read-only + + + ID9 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + read-only + + + ID10 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + read-only + + + ID11 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + read-only + + + ID12 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + read-only + + + ID13 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + read-only + + + ID14 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + read-only + + + ID15 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + read-only + + + + + GPIO_ODR + GPIO_ODR + GPIO port output data register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + read-write + + + OD1 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + read-write + + + OD2 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + read-write + + + OD3 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + read-write + + + OD4 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + read-write + + + OD5 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + read-write + + + OD6 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + read-write + + + OD7 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + read-write + + + OD8 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + read-write + + + OD9 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + read-write + + + OD10 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + read-write + + + OD11 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + read-write + + + OD12 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + read-write + + + OD13 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + read-write + + + OD14 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + read-write + + + OD15 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + read-write + + + + + GPIO_BSRR + GPIO_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS1 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS2 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS3 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS4 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS5 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS6 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS7 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS8 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS9 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS10 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS11 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS12 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS13 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS14 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS15 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BR0 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + + + GPIO_LCKR + GPIO_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +- LOCK key write sequence: +WR LCKR[16] = 1 + LCKR[15:0] +WR LCKR[16] = 0 + LCKR[15:0] +WR LCKR[16] = 1 + LCKR[15:0] +- LOCK key read +RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) +Note: During the lock key write sequence, the value of LCK[15:0] must not change. +Note: Any error in the lock sequence aborts the LOCK. +Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. + 0x1 + + + + + + + GPIO_AFRL + GPIO_AFRL + GPIO alternate function low register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIO_AFRH + GPIO_AFRH + GPIO alternate function high register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIO_BRR + GPIO_BRR + GPIO port bit reset register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + + + GPIO_HSLVR + GPIO_HSLVR + GPIO high-speed low-voltage register + 0x2C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + HSLV0 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV1 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV2 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV3 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV4 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV5 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV6 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV7 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV8 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV9 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV10 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV11 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV12 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV13 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV14 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV15 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + + + GPIO_SECCFGR + GPIO_SECCFGR + GPIO secure configuration register + 0x30 + 0x20 + 0x0000FFFF + 0xFFFFFFFF + + + SEC0 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC1 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC2 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC3 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC4 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC5 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC6 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC7 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC8 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC9 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC10 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC11 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC12 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC13 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC14 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC15 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + + + + + SEC_GPIOH + DCB->DSCSR->CDS == 0 + 0x52021C00 + + + GPIOI + General-purpose I/Os + GPIO + 0x42022000 + + 0x0 + 0x400 + registers + + + + GPIO_MODER + GPIO_MODER + GPIO port mode register + 0x00 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + + + GPIO_OTYPER + GPIO_OTYPER + GPIO port output type register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIO_OSPEEDR + GPIO_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + + + GPIO_PUPDR + GPIO_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + + + GPIO_IDR + GPIO_IDR + GPIO port input data register + 0x10 + 0x20 + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + read-only + + + ID1 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + read-only + + + ID2 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + read-only + + + ID3 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + read-only + + + ID4 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + read-only + + + ID5 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + read-only + + + ID6 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + read-only + + + ID7 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + read-only + + + ID8 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + read-only + + + ID9 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + read-only + + + ID10 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + read-only + + + ID11 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + read-only + + + ID12 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + read-only + + + ID13 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + read-only + + + ID14 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + read-only + + + ID15 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + read-only + + + + + GPIO_ODR + GPIO_ODR + GPIO port output data register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + read-write + + + OD1 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + read-write + + + OD2 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + read-write + + + OD3 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + read-write + + + OD4 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + read-write + + + OD5 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + read-write + + + OD6 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + read-write + + + OD7 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + read-write + + + OD8 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + read-write + + + OD9 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + read-write + + + OD10 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + read-write + + + OD11 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + read-write + + + OD12 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + read-write + + + OD13 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + read-write + + + OD14 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + read-write + + + OD15 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + read-write + + + + + GPIO_BSRR + GPIO_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS1 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS2 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS3 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS4 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS5 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS6 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS7 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS8 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS9 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS10 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS11 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS12 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS13 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS14 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS15 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BR0 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + + + GPIO_LCKR + GPIO_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +- LOCK key write sequence: +WR LCKR[16] = 1 + LCKR[15:0] +WR LCKR[16] = 0 + LCKR[15:0] +WR LCKR[16] = 1 + LCKR[15:0] +- LOCK key read +RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) +Note: During the lock key write sequence, the value of LCK[15:0] must not change. +Note: Any error in the lock sequence aborts the LOCK. +Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. + 0x1 + + + + + + + GPIO_AFRL + GPIO_AFRL + GPIO alternate function low register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIO_AFRH + GPIO_AFRH + GPIO alternate function high register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIO_BRR + GPIO_BRR + GPIO port bit reset register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + + + GPIO_HSLVR + GPIO_HSLVR + GPIO high-speed low-voltage register + 0x2C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + HSLV0 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV1 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV2 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV3 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV4 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV5 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV6 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV7 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV8 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV9 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV10 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV11 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV12 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV13 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV14 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV15 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + + + GPIO_SECCFGR + GPIO_SECCFGR + GPIO secure configuration register + 0x30 + 0x20 + 0x0000FFFF + 0xFFFFFFFF + + + SEC0 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC1 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC2 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC3 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC4 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC5 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC6 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC7 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC8 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC9 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC10 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC11 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC12 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC13 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC14 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC15 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + + + + + SEC_GPIOI + DCB->DSCSR->CDS == 0 + 0x52022000 + + + GPIOJ + General-purpose I/Os + GPIO + 0x42022400 + + 0x0 + 0x400 + registers + + + + GPIO_MODER + GPIO_MODER + GPIO port mode register + 0x00 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + + + GPIO_OTYPER + GPIO_OTYPER + GPIO port output type register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIO_OSPEEDR + GPIO_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + + + GPIO_PUPDR + GPIO_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + PUPD15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + + + GPIO_IDR + GPIO_IDR + GPIO port input data register + 0x10 + 0x20 + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + read-only + + + ID1 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + read-only + + + ID2 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + read-only + + + ID3 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + read-only + + + ID4 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + read-only + + + ID5 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + read-only + + + ID6 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + read-only + + + ID7 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + read-only + + + ID8 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + read-only + + + ID9 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + read-only + + + ID10 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + read-only + + + ID11 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + read-only + + + ID12 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + read-only + + + ID13 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + read-only + + + ID14 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + read-only + + + ID15 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + read-only + + + + + GPIO_ODR + GPIO_ODR + GPIO port output data register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + read-write + + + OD1 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + read-write + + + OD2 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + read-write + + + OD3 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + read-write + + + OD4 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + read-write + + + OD5 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + read-write + + + OD6 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + read-write + + + OD7 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + read-write + + + OD8 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + read-write + + + OD9 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + read-write + + + OD10 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + read-write + + + OD11 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + read-write + + + OD12 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + read-write + + + OD13 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + read-write + + + OD14 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + read-write + + + OD15 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + read-write + + + + + GPIO_BSRR + GPIO_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS1 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS2 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS3 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS4 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS5 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS6 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS7 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS8 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS9 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS10 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS11 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS12 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS13 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS14 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS15 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BR0 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSy and BRy are set, BSy has priority. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + + + GPIO_LCKR + GPIO_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0 +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +- LOCK key write sequence: +WR LCKR[16] = 1 + LCKR[15:0] +WR LCKR[16] = 0 + LCKR[15:0] +WR LCKR[16] = 1 + LCKR[15:0] +- LOCK key read +RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) +Note: During the lock key write sequence, the value of LCK[15:0] must not change. +Note: Any error in the lock sequence aborts the LOCK. +Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. + 0x1 + + + + + + + GPIO_AFRL + GPIO_AFRL + GPIO alternate function low register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIO_AFRH + GPIO_AFRH + GPIO alternate function high register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x I/O pin y +These bits are written by the software to configure alternate function I/Os. +Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIO_BRR + GPIO_BRR + GPIO port bit reset register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + + + GPIO_HSLVR + GPIO_HSLVR + GPIO high-speed low-voltage register + 0x2C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + HSLV0 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV1 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV2 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV3 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV4 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV5 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV6 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV7 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV8 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV9 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV10 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV11 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV12 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV13 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV14 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV15 + Port x high-speed low-voltage configuration +These bits are written by software to optimize the I/O speed when the I/O supply is low. +Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. +Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. +Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. +Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + + + GPIO_SECCFGR + GPIO_SECCFGR + GPIO secure configuration register + 0x30 + 0x20 + 0x0000FFFF + 0xFFFFFFFF + + + SEC0 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 0 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC1 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 1 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC2 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 2 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC3 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 3 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC4 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 4 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC5 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 5 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC6 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 6 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC7 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 7 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC8 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 8 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC9 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 9 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC10 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 10 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC11 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 11 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC12 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 12 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC13 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 13 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC14 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 14 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + SEC15 + I/O pin of Port x secure bit enable y +These bits are written by software to enable or disable the I/O port pin security. +Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. + 15 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. + 0x1 + + + + + + + + + SEC_GPIOJ + DCB->DSCSR->CDS == 0 + 0x52022400 + + + GTZC1_MPCBB1 + GTZC1_MPCBB1 + GTZC + 0x40032C00 + + 0x0 + 0x400 + registers + + + GTZC + GTZC1/GTZC2 global interrupt + 008 + + + + MPCBB1_CR + MPCBB1_CR + MPCBB control register + 0x0 + 0x20 + read-write + 0x00000000 + + + GLOCK + lock the control register of the MPCBB until next reset + 0 + 1 + + + INVSECSTATE + SRAMx clocks security state + 30 + 1 + + + SRWILADIS + secure read/write illegal access disable + 31 + 1 + + + + + MPCBB1_CFGLOCK1 + MPCBB1_CFGLOCK1 + GTZC1 SRAMz MPCBB configuration lock register 1 + 0x10 + 0x20 + read-write + 0x00000000 + + + SPLCK0 + SPLCK0 + 0 + 1 + + + SPLCK1 + SPLCK1 + 1 + 1 + + + SPLCK2 + SPLCK2 + 2 + 1 + + + SPLCK3 + SPLCK3 + 3 + 1 + + + SPLCK4 + SPLCK4 + 4 + 1 + + + SPLCK5 + SPLCK5 + 5 + 1 + + + SPLCK6 + SPLCK6 + 6 + 1 + + + SPLCK7 + SPLCK7 + 7 + 1 + + + SPLCK8 + SPLCK8 + 8 + 1 + + + SPLCK9 + SPLCK9 + 9 + 1 + + + SPLCK10 + SPLCK10 + 10 + 1 + + + SPLCK11 + SPLCK11 + 11 + 1 + + + SPLCK12 + SPLCK12 + 12 + 1 + + + SPLCK13 + SPLCK13 + 13 + 1 + + + SPLCK14 + SPLCK14 + 14 + 1 + + + SPLCK15 + SPLCK15 + 15 + 1 + + + SPLCK16 + SPLCK16 + 16 + 1 + + + SPLCK17 + SPLCK17 + 17 + 1 + + + SPLCK18 + SPLCK18 + 18 + 1 + + + SPLCK19 + SPLCK19 + 19 + 1 + + + SPLCK20 + SPLCK20 + 20 + 1 + + + SPLCK21 + SPLCK21 + 21 + 1 + + + SPLCK22 + SPLCK22 + 22 + 1 + + + SPLCK23 + SPLCK23 + 23 + 1 + + + SPLCK24 + SPLCK24 + 24 + 1 + + + SPLCK25 + SPLCK25 + 25 + 1 + + + SPLCK26 + SPLCK26 + 26 + 1 + + + SPLCK27 + SPLCK27 + 27 + 1 + + + SPLCK28 + SPLCK28 + 28 + 1 + + + SPLCK29 + SPLCK29 + 29 + 1 + + + SPLCK30 + SPLCK30 + 30 + 1 + + + SPLCK31 + SPLCK31 + 31 + 1 + + + + + MPCBB1_CFGLOCK2 + MPCBB1_CFGLOCK2 + GTZC1 SRAMz MPCBB configuration lock register 2 + 0x14 + 0x20 + read-write + 0x00000000 + + + SPLCK32 + SPLCK32 + 0 + 1 + + + SPLCK33 + SPLCK33 + 1 + 1 + + + SPLCK34 + SPLCK34 + 2 + 1 + + + SPLCK35 + SPLCK35 + 3 + 1 + + + SPLCK36 + SPLCK36 + 4 + 1 + + + SPLCK37 + SPLCK37 + 5 + 1 + + + SPLCK38 + SPLCK38 + 6 + 1 + + + SPLCK39 + SPLCK39 + 7 + 1 + + + SPLCK40 + SPLCK40 + 8 + 1 + + + SPLCK41 + SPLCK41 + 9 + 1 + + + SPLCK42 + SPLCK42 + 10 + 1 + + + SPLCK43 + SPLCK43 + 11 + 1 + + + SPLCK44 + SPLCK44 + 12 + 1 + + + SPLCK45 + SPLCK45 + 13 + 1 + + + SPLCK46 + SPLCK46 + 14 + 1 + + + SPLCK47 + SPLCK47 + 15 + 1 + + + SPLCK48 + SPLCK48 + 16 + 1 + + + SPLCK49 + SPLCK49 + 17 + 1 + + + SPLCK50 + SPLCK50 + 18 + 1 + + + SPLCK51 + SPLCK51 + 19 + 1 + + + + + MPCBB1_SECCFGR0 + MPCBB1_SECCFGR0 + MPCBBx security configuration for super-block x register + 0x100 + 0x20 + read-write + 0xFFFFFFFF + + + SEC0 + SEC0 + 0 + 1 + + + SEC1 + SEC1 + 1 + 1 + + + SEC2 + SEC2 + 2 + 1 + + + SEC3 + SEC3 + 3 + 1 + + + SEC4 + SEC4 + 4 + 1 + + + SEC5 + SEC5 + 5 + 1 + + + SEC6 + SEC6 + 6 + 1 + + + SEC7 + SEC7 + 7 + 1 + + + SEC8 + SEC8 + 8 + 1 + + + SEC9 + SEC9 + 9 + 1 + + + SEC10 + SEC10 + 10 + 1 + + + SEC11 + SEC11 + 11 + 1 + + + SEC12 + SEC12 + 12 + 1 + + + SEC13 + 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flag for SRAM5 + 30 + 1 + + + MPCBB5_REGF + illegal access flag for MPCBB5 registers + 31 + 1 + + + + + FCR1 + FCR1 + TZIC flag clear register 1 + 0x20 + 0x20 + write-only + 0x00000000 + + + CTIM2F + clear the illegal access flag for TIM2 + 0 + 1 + + + CTIM3F + clear the illegal access flag for TIM3 + 1 + 1 + + + CTIM4F + clear the illegal access flag for TIM4 + 2 + 1 + + + CTIM5F + clear the illegal access flag for TIM5 + 3 + 1 + + + CTIM6F + clear the illegal access flag for TIM6 + 4 + 1 + + + CTIM7F + clear the illegal access flag for TIM7 + 5 + 1 + + + CWWDGF + clear the illegal access flag for WWDG + 6 + 1 + + + CIWDGF + clear the illegal access flag for IWDG + 7 + 1 + + + CSPI2F + clear the illegal access flag for SPI2 + 8 + 1 + + + CUSART2F + clear the illegal access flag for USART2 + 9 + 1 + + + CUSART3F + clear the illegal access flag for USART3 + 10 + 1 + + + CUART4F + clear the illegal access flag for UART4 + 11 + 1 + + + CUART5F + clear the illegal access flag for UART5 + 12 + 1 + + + CI2C1F + clear the illegal access flag for I2C1 + 13 + 1 + + + CI2C2F + clear the illegal access flag for I2C2 + 14 + 1 + + + CCRSF + clear the illegal access flag for CRS + 15 + 1 + + + CI2C4F + clear the illegal access flag for I2C4 + 16 + 1 + + + CLPTIM2F + clear the illegal access flag for LPTIM2 + 17 + 1 + + + CFDCAN1F + clear the illegal access flag for FDCAN1 + 18 + 1 + + + CUCPD1F + clear the illegal access flag for UCPD1 + 19 + 1 + + + CUSART6F + clear the illegal access flag for USART6 + 21 + 1 + + + CI2C5F + clear the illegal access flag for I2C5 + 22 + 1 + + + CI2C6F + clear the illegal access flag for I2C6 + 23 + 1 + + + + + FCR2 + FCR2 + TZIC flag clear register 2 + 0x24 + 0x20 + write-only + 0x00000000 + + + CTIM1F + clear the illegal access flag for TIM1 + 0 + 1 + + + CSPI1F + clear the illegal access flag for SPI1 + 1 + 1 + + + CTIM8F + clear the illegal access flag for TIM8 + 2 + 1 + + + CUSART1F + clear the illegal access flag for USART1 + 3 + 1 + + + CTIM15F + clear the illegal access flag for TIM5 + 4 + 1 + + + CTIM16F + clear the illegal access flag for TIM6 + 5 + 1 + + + CTIM17F + clear the illegal access flag for TIM7 + 6 + 1 + + + CSAI1F + clear the illegal access flag for SAI1 + 7 + 1 + + + CSAI2F + clear the illegal access flag for SAI2 + 8 + 1 + + + CLTDCF + clear the illegal access flag for LTDC + 9 + 1 + + + CDSIF + clear the illegal access flag for DSI + 10 + 1 + + + + + FCR3 + FCR3 + TZIC flag clear register 3 + 0x28 + 0x20 + write-only + 0x00000000 + + + CMDF1F + clear the illegal access flag for MDF1 + 0 + 1 + + + CCORDICF + clear the illegal access flag for CORDIC + 1 + 1 + + + CFMACF + clear the illegal access flag for FMAC + 2 + 1 + + + CCRCF + clear the illegal access flag for CRC + 3 + 1 + + + CTSCF + clear the illegal access flag for TSC + 4 + 1 + + + CDMA2DF + clear the illegal access flag for register of DMA2D + 5 + 1 + + + CICACHE_REGF + clear the illegal access flag for ICACHE registers + 6 + 1 + + + CDCACHE1_REGF + clear the illegal access flag for DCACHE1 registers + 7 + 1 + + + CADC12F + clear the illegal access flag for ADC1 and ADC2 + 8 + 1 + + + CDCMIF + clear the illegal access flag for DCMI + 9 + 1 + + + COTGF + clear the illegal access flag for OTG_FS + 10 + 1 + + + CAESF + clear the illegal access flag for AES + 11 + 1 + + + CHASHF + clear the illegal access flag for HASH + 12 + 1 + + + CRNGF + clear the illegal access flag for RNG + 13 + 1 + + + CPKAF + clear the illegal access flag for PKA + 14 + 1 + + + CSAESF + clear the illegal access flag for SAES + 15 + 1 + + + COCTOSPIMF + clear the illegal access flag for OCTOSPIM + 16 + 1 + + + CSDMMC1F + clear the illegal access flag for SDMMC2 + 17 + 1 + + + CSDMMC2F + clear the illegal access flag for SDMMC1 + 18 + 1 + + + CFSMC_REGF + clear the illegal access flag for FSMC registers + 19 + 1 + + + COCTOSPI1_REGF + clear the illegal access flag for OCTOSPI1 registers + 20 + 1 + + + COCTOSPI2_REGF + clear the illegal access flag for OCTOSPI2 registers + 21 + 1 + + + CRAMCFGF + clear the illegal access flag for RAMCFG + 22 + 1 + + + CGPU2DF + clear the illegal access flag for GPU2D + 23 + 1 + + + CGFXMMUF + clear the illegal access flag for GFXMMU + 24 + 1 + + + CGFXMMU_REGF + clear the illegal access flag for GFXMMU registers + 25 + 1 + + + CHSPI1_REGF + clear the illegal access flag for GFXMMU registers + 26 + 1 + + + CDCACHE2_REGF + clear the illegal access flag for GFXMMU registers + 27 + 1 + + + + + FCR4 + FCR4 + TZIC flag clear register 4 + 0x2C + 0x20 + write-only + 0x00000000 + + + CGPDMA1F + clear the illegal access flag for GPDMA1 + 0 + 1 + + + CFLASH_REGF + clear the illegal access flag for FLASH registers + 1 + 1 + + + CFLASHF + clear the illegal access flag for FLASH memory + 2 + 1 + + + COTFDEC1F + clear the illegal access flag for OTFDEC1 + 3 + 1 + + + COTFDEC2F + clear the illegal access flag for OTFDEC2 + 4 + 1 + + + CTZSC1F + clear the illegal access flag for GTZC1 TZSC registers + 14 + 1 + + + CTZIC1F + clear the illegal access flag for GTZC1 TZIC registers + 15 + 1 + + + COCTOSPI1_MEMF + clear the illegal access flag for MPCWM1 (OCTOSPI1) memory bank + 16 + 1 + + + CFSMC_MEMF + clear the illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3 + 17 + 1 + + + CBKPSRAMF + clear the illegal access flag for MPCWM3 (BKPSRAM) memory bank + 18 + 1 + + + COCTOSPI2_MEMF + clear the illegal access flag for OCTOSPI2 memory bank + 19 + 1 + + + CHSPI1_MEMF + clear the illegal access flag for HSPI1 memory bank + 20 + 1 + + + CSRAM1F + clear the illegal access flag for SRAM1 + 24 + 1 + + + CMPCBB1_REGF + clear the illegal access flag for MPCBB1 registers + 25 + 1 + + + CSRAM2F + clear the illegal access flag for SRAM2 + 26 + 1 + + + CMPCBB2_REGF + clear the illegal access flag for MPCBB2 registers + 27 + 1 + + + CSRAM3F + clear the illegal access flag for SRAM3 + 28 + 1 + + + CMPCBB3_REGF + clear the illegal access flag for MPCBB3 registers + 29 + 1 + + + CSRAM5F + clear the illegal access flag for SRAM5 + 30 + 1 + + + CMPCBB5_REGF + clear the illegal access flag for MPCBB5 registers + 31 + 1 + + + + + + + SEC_GTZC1_TZIC + DCB->DSCSR->CDS == 0 + 0x50032800 + + + GTZC1_TZSC + GTZC1_TZSC + GTZC + 0x40032400 + + 0x0 + 0x400 + registers + + + + TZSC_CR + TZSC_CR + TZSC control register + 0x0 + 0x20 + read-write + 0x00000000 + + + LCK + lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx +registers until next reset + 0 + 1 + + + + + TZSC_SECCFGR1 + TZSC_SECCFGR1 + TZSC secure configuration register 1 + 0x10 + 0x20 + read-write + 0x00000000 + + + TIM2SEC + secure access mode for TIM2 + 0 + 1 + + + TIM3SEC + secure access mode for TIM3 + 1 + 1 + + + TIM4SEC + secure access mode for TIM4 + 2 + 1 + + + TIM5SEC + secure access mode for TIM5 + 3 + 1 + + + TIM6SEC + secure access mode for TIM6 + 4 + 1 + + + TIM7SEC + secure access mode for TIM7 + 5 + 1 + + + WWDGSEC + secure access mode for WWDG + 6 + 1 + + + IWDGSEC + secure access mode for IWDG + 7 + 1 + + + SPI2SEC + secure access mode for SPI2 + 8 + 1 + + + USART2SEC + secure access mode for USART2 + 9 + 1 + + + USART3SEC + secure access mode for USART3 + 10 + 1 + + + UART4SEC + secure access mode for UART4 + 11 + 1 + + + UART5SEC + secure access mode for UART5 + 12 + 1 + + + I2C1SEC + secure access mode for I2C1 + 13 + 1 + + + I2C2SEC + secure access mode for I2C2 + 14 + 1 + + + CRSSEC + secure access mode for CRS + 15 + 1 + + + I2C4SEC + secure access mode for I2C4 + 16 + 1 + + + LPTIM2SEC + secure access mode for LPTIM2 + 17 + 1 + + + FDCAN1SEC + secure access mode for FDCAN1 + 18 + 1 + + + UCPD1SEC + secure access mode for UCPD1 + 19 + 1 + + + USART6SEC + USART6SEC + 21 + 1 + + + I2C5SEC + I2C5SEC + 22 + 1 + + + I2C6SEC + I2C6SEC + 23 + 1 + + + + + TZSC_SECCFGR2 + TZSC_SECCFGR2 + TZSC secure configuration register 2 + 0x14 + 0x20 + read-write + 0x00000000 + + + TIM1SEC + secure access mode for TIM1 + 0 + 1 + + + SPI1SEC + secure access mode for SPI1 + 1 + 1 + + + TIM8SEC + secure access mode for TIM8 + 2 + 1 + + + USART1SEC + secure access mode for USART1 + 3 + 1 + + + TIM15SEC + secure access mode for TIM5 + 4 + 1 + + + TIM16SEC + secure access mode for TIM6 + 5 + 1 + + + TIM17SEC + secure access mode for TIM7 + 6 + 1 + + + SAI1SEC + secure access mode for SAI1 + 7 + 1 + + + SAI2SEC + secure access mode for SAI2 + 8 + 1 + + + LTDCSEC + LTDCSEC + 9 + 1 + + + DSISEC + DSISEC + 10 + 1 + + + + + TZSC_SECCFGR3 + TZSC_SECCFGR3 + TZSC secure configuration register 3 + 0x18 + 0x20 + read-write + 0x00000000 + + + MDF1SEC + secure access mode for MDF1 + 0 + 1 + + + CORDICSEC + secure access mode for CORDIC + 1 + 1 + + + FMACSEC + secure access mode for FMAC + 2 + 1 + + + CRCSEC + secure access mode for CRC + 3 + 1 + + + TSCSEC + secure access mode for TSC + 4 + 1 + + + DMA2DSEC + secure access mode for register of DMA2D + 5 + 1 + + + ICACHE_REGSEC + secure access mode for ICACHE registers + 6 + 1 + + + DCACHE1_REGSEC + secure access mode for DCACHE1 registers + 7 + 1 + + + ADC1SEC + secure access mode for ADC1 + 8 + 1 + + + DCMISEC + secure access mode for DCMI + 9 + 1 + + + OTGFSSEC + secure access mode for OTG_FS + 10 + 1 + + + AESSEC + secure access mode for AES + 11 + 1 + + + HASHSEC + secure access mode for HASH + 12 + 1 + + + RNGSEC + secure access mode for RNG + 13 + 1 + + + PKASEC + secure access mode for PKA + 14 + 1 + + + SAESSEC + secure access mode for SAES + 15 + 1 + + + OCTOSPIMSEC + secure access mode for OCTOSPIM + 16 + 1 + + + SDMMC1SEC + secure access mode for SDMMC2 + 17 + 1 + + + SDMMC2SEC + secure access mode for SDMMC1 + 18 + 1 + + + FSMC_REGSEC + secure access mode for FSMC registers + 19 + 1 + + + OCTOSPI1_REGSEC + secure access mode for OCTOSPI1 registers + 20 + 1 + + + OCTOSPI2_REGSEC + secure access mode for OCTOSPI2 registers + 21 + 1 + + + RAMCFGSEC + secure access mode for RAMCFG + 22 + 1 + + + GPU2DSEC + GPU2DSEC + 23 + 1 + + + GFXMMUSEC + GFXMMUSEC + 24 + 1 + + + GFXMMU_REGSEC + GFXMMU_REGSEC + 25 + 1 + + + HSPI1_REGSEC + HSPI1_REGSEC + 26 + 1 + + + DCACHE2_REGSEC + DCACHE2_REGSEC + 27 + 1 + + + + + TZSC_PRIVCFGR1 + TZSC_PRIVCFGR1 + TZSC privilege configuration register 1 + 0x20 + 0x20 + read-write + 0x00000000 + + + TIM2PRIV + privileged access mode for TIM2 + 0 + 1 + + + TIM3PRIV + privileged access mode for TIM3 + 1 + 1 + + + TIM4PRIV + privileged access mode for TIM4 + 2 + 1 + + + TIM5PRIV + privileged access mode for TIM5 + 3 + 1 + + + TIM6PRIV + privileged access mode for TIM6 + 4 + 1 + + + TIM7PRIV + privileged access mode for TIM7 + 5 + 1 + + + WWDGPRIV + privileged access mode for WWDG + 6 + 1 + + + IWDGPRIV + privileged access mode for IWDG + 7 + 1 + + + SPI2PRIV + privileged access mode for SPI2 + 8 + 1 + + + USART2PRIV + privileged access mode for USART2 + 9 + 1 + + + USART3PRIV + privileged access mode for USART3 + 10 + 1 + + + UART4PRIV + privileged access mode for UART4 + 11 + 1 + + + UART5PRIV + privileged access mode for UART5 + 12 + 1 + + + I2C1PRIV + privileged access mode for I2C1 + 13 + 1 + + + I2C2PRIV + privileged access mode for I2C2 + 14 + 1 + + + CRSPRIV + privileged access mode for CRS + 15 + 1 + + + I2C4PRIV + privileged access mode for I2C4 + 16 + 1 + + + LPTIM2PRIV + privileged access mode for LPTIM2 + 17 + 1 + + + FDCAN1PRIV + privileged access mode for FDCAN1 + 18 + 1 + + + UCPD1PRIV + privileged access mode for UCPD1 + 19 + 1 + + + USART6PRIV + USART6PRIV + 21 + 1 + + + I2C5PRIV + I2C5PRIV + 22 + 1 + + + I2C6PRIV + I2C6PRIV + 23 + 1 + + + + + TZSC_PRIVCFGR2 + TZSC_PRIVCFGR2 + TZSC privilege configuration register 2 + 0x24 + 0x20 + read-write + 0x00000000 + + + TIM1PRIV + privileged access mode for TIM1 + 0 + 1 + + + SPI1PRIV + privileged access mode for SPI1PRIV + 1 + 1 + + + TIM8PRIV + privileged access mode for TIM8 + 2 + 1 + + + USART1PRIV + privileged access mode for USART1 + 3 + 1 + + + TIM15PRIV + privileged access mode for TIM15 + 4 + 1 + + + TIM16PRIV + privileged access mode for TIM16 + 5 + 1 + + + TIM17PRIV + privileged access mode for TIM17 + 6 + 1 + + + SAI1PRIV + privileged access mode for SAI1 + 7 + 1 + + + SAI2PRIV + privileged access mode for SAI2 + 8 + 1 + + + LTDCPRIV + LTDCPRIV + 9 + 1 + + + DSIPRIV + DSIPRIV + 10 + 1 + + + + + TZSC_PRIVCFGR3 + TZSC_PRIVCFGR3 + TZSC privilege configuration register 3 + 0x28 + 0x20 + read-write + 0x00000000 + + + MDF1PRIV + privileged access mode for MDF1 + 0 + 1 + + + CORDICPRIV + privileged access mode for CORDIC + 1 + 1 + + + FMACPRIV + privileged access mode for FMAC + 2 + 1 + + + CRCPRIV + privileged access mode for CRC + 3 + 1 + + + TSCPRIV + privileged access mode for TSC + 4 + 1 + + + DMA2DPRIV + privileged access mode for register of DMA2D + 5 + 1 + + + ICACHE_REGPRIV + privileged access mode for ICACHE registers + 6 + 1 + + + DCACHE1_REGPRIV + privileged access mode for DCACHE1 registers + 7 + 1 + + + ADC1PRIV + privileged access mode for ADC1 + 8 + 1 + + + DCMIPRIV + privileged access mode for DCMI + 9 + 1 + + + OTGFSPRIV + privileged access mode for OTG_FS + 10 + 1 + + + AESPRIV + privileged access mode for AES + 11 + 1 + + + HASHPRIV + privileged access mode for HASH + 12 + 1 + + + RNGPRIV + privileged access mode for RNG + 13 + 1 + + + PKAPRIV + privileged access mode for PKA + 14 + 1 + + + SAESPRIV + privileged access mode for SAES + 15 + 1 + + + OCTOSPIMPRIV + privileged access mode for OCTOSPIM + 16 + 1 + + + SDMMC1PRIV + privileged access mode for SDMMC2 + 17 + 1 + + + SDMMC2PRIV + privileged access mode for SDMMC1 + 18 + 1 + + + FSMC_REGPRIV + privileged access mode for FSMC registers + 19 + 1 + + + OCTOSPI1_REGPRIV + privileged access mode for OCTOSPI1 + 20 + 1 + + + OCTOSPI2_REGPRIV + privileged access mode for OCTOSPI2 + 21 + 1 + + + RAMCFGPRIV + privileged access mode for RAMCFG + 22 + 1 + + + GPU2DPRIV + GPU2DPRIV + 23 + 1 + + + GFXMMUPRIV + GFXMMUPRIV + 24 + 1 + + + GFXMMU_REGPRIV + GFXMMU_REGPRIV + 25 + 1 + + + HSPI1_REGPRIV + HSPI1_REGPRIV + 26 + 1 + + + DCACHE2_REGPRIV + DCACHE2_REGPRIV + 27 + 1 + + + + + TZSC_MPCWM1ACFGR + TZSC_MPCWM1ACFGR + TZSC memory 1 sub-region A watermark configuration register + 0x40 + 0x20 + read-write + 0x00000000 + + + SREN + Sub-region enable + 0 + 1 + + + SRLOCK + Sub-region lock + 1 + 1 + + + SEC + Secure sub-region + 8 + 1 + + + PRIV + Privileged sub-region + 9 + 1 + + + + + TZSC_MPCWM1AR + TZSC_MPCWM1AR + TZSC memory 1 sub-region A watermark register + 0x44 + 0x20 + read-write + 0x00000000 + + + SUBA_START + Start of sub-region A + 0 + 11 + + + SUBA_LENGTH + Length of sub-region A + 16 + 12 + + + + + TZSC_MPCWM1BCFGR + TZSC_MPCWM1BCFGR + TZSC memory 1 sub-region B watermark configuration register + 0x48 + 0x20 + read-write + 0x00000000 + + + SREN + Sub-region enable + 0 + 1 + + + SRLOCK + Sub-region lock + 1 + 1 + + + SEC + Secure sub-region + 8 + 1 + + + PRIV + Privileged sub-region + 9 + 1 + + + + + TZSC_MPCWM1BR + TZSC_MPCWM1BR + TZSC memory 1 sub-region B watermark register + 0x4C + 0x20 + read-write + 0x00000000 + + + SUBB_START + Start of sub-region A + 0 + 11 + + + SUBB_LENGTH + Length of sub-region A + 16 + 12 + + + + + TZSC_MPCWM2ACFGR + TZSC_MPCWM2ACFGR + TZSC memory 2 sub-region A watermark configuration register + 0x50 + 0x20 + read-write + 0x00000000 + + + SREN + Sub-region enable + 0 + 1 + + + SRLOCK + Sub-region lock + 1 + 1 + + + SEC + Secure sub-region + 8 + 1 + + + PRIV + Privileged sub-region + 9 + 1 + + + + + TZSC_MPCWM2AR + TZSC_MPCWM2AR + TZSC memory 2 sub-region A watermark register + 0x54 + 0x20 + read-write + 0x00000000 + + + SUBA_START + Start of sub-region A + 0 + 11 + + + SUBA_LENGTH + Length of sub-region A + 16 + 12 + + + + + TZSC_MPCWM2BCFGR + TZSC_MPCWM2BCFGR + TZSC memory 2 sub-region B watermark configuration register + 0x58 + 0x20 + read-write + 0x00000000 + + + SREN + Sub-region enable + 0 + 1 + + + SRLOCK + Sub-region lock + 1 + 1 + + + SEC + Secure sub-region + 8 + 1 + + + PRIV + Privileged sub-region + 9 + 1 + + + + + TZSC_MPCWM2BR + TZSC_MPCWM2BR + TZSC memory 2 sub-region B watermark register + 0x5C + 0x20 + read-write + 0x00000000 + + + SUBB_START + Start of sub-region A + 0 + 11 + + + SUBB_LENGTH + Length of sub-region A + 16 + 12 + + + + + TZSC_MPCWM3ACFGR + TZSC_MPCWM3ACFGR + TZSC memory 3 sub-region A watermark configuration register + 0x60 + 0x20 + read-write + 0x00000000 + + + SREN + Sub-region enable + 0 + 1 + + + SRLOCK + Sub-region lock + 1 + 1 + + + SEC + Secure sub-region + 8 + 1 + + + PRIV + Privileged sub-region + 9 + 1 + + + + + TZSC_MPCWM3AR + TZSC_MPCWM3AR + TZSC memory 3 sub-region A watermark register + 0x64 + 0x20 + read-write + 0x00000000 + + + SUBA_START + Start of sub-region A + 0 + 11 + + + SUBA_LENGTH + Length of sub-region A + 16 + 12 + + + + + TZSC_MPCWM4ACFGR + TZSC_MPCWM4ACFGR + TZSC memory 4 sub-region A watermark configuration register + 0x70 + 0x20 + read-write + 0x00000000 + + + SREN + Sub-region enable + 0 + 1 + + + SRLOCK + Sub-region lock + 1 + 1 + + + SEC + Secure sub-region + 8 + 1 + + + PRIV + Privileged sub-region + 9 + 1 + + + + + TZSC_MPCWM4AR + TZSC_MPCWM4AR + TZSC memory 4 sub-region A watermark register + 0x74 + 0x20 + read-write + 0x00000000 + + + SUBA_START + Start of sub-region A + 0 + 11 + + + SUBA_LENGTH + Length of sub-region A + 16 + 12 + + + + + TZSC_MPCWM5ACFGR + TZSC_MPCWM5ACFGR + TZSC memory 5 sub-region A watermark configuration register + 0x80 + 0x20 + read-write + 0x00000000 + + + SREN + Sub-region enable + 0 + 1 + + + SRLOCK + Sub-region lock + 1 + 1 + + + SEC + Secure sub-region + 8 + 1 + + + PRIV + Privileged sub-region + 9 + 1 + + + + + TZSC_MPCWM5AR + TZSC_MPCWM5AR + TZSC memory 5 sub-region A watermark register + 0x84 + 0x20 + read-write + 0x00000000 + + + SUBA_START + Start of sub-region A + 0 + 11 + + + SUBA_LENGTH + Length of sub-region A + 16 + 12 + + + + + TZSC_MPCWM5BCFGR + TZSC_MPCWM5BCFGR + TZSC memory 5 sub-region B watermark configuration register + 0x88 + 0x20 + read-write + 0x00000000 + + + SREN + Sub-region enable + 0 + 1 + + + SRLOCK + Sub-region lock + 1 + 1 + + + SEC + Secure sub-region + 8 + 1 + + + PRIV + Privileged sub-region + 9 + 1 + + + + + TZSC_MPCWM5BR + TZSC_MPCWM5BR + TZSC memory 5 sub-region B watermark register + 0x8C + 0x20 + read-write + 0x00000000 + + + SUBB_START + Start of sub-region A + 0 + 11 + + + SUBB_LENGTH + Length of sub-region A + 16 + 12 + + + + + TZSC_MPCWM6ACFGR + TZSC_MPCWM6ACFGR + TZSC memory 6 sub-region B watermark configuration register + 0x90 + 0x20 + read-write + 0x00000000 + + + SREN + Sub-region enable + 0 + 1 + + + SRLOCK + Sub-region lock + 1 + 1 + + + SEC + Secure sub-region + 8 + 1 + + + PRIV + Privileged sub-region + 9 + 1 + + + + + TZSC_MPCWM6AR + TZSC_MPCWM6AR + TZSC memory 6 sub-region B watermark register + 0x94 + 0x20 + read-write + 0x00000000 + + + SUBA_START + Start of sub-region A + 0 + 11 + + + SUBA_LENGTH + Length of sub-region A + 16 + 12 + + + + + TZSC_MPCWM6BCFGR + TZSC_MPCWM6BCFGR + TZSC memory 6 sub-region B watermark configuration register + 0x98 + 0x20 + read-write + 0x00000000 + + + SREN + Sub-region enable + 0 + 1 + + + SRLOCK + Sub-region lock + 1 + 1 + + + SEC + Secure sub-region + 8 + 1 + + + PRIV + Privileged sub-region + 9 + 1 + + + + + TZSC_MPCWM6BR + TZSC_MPCWM6BR + TZSC memory 6 sub-region B watermark register + 0x9C + 0x20 + read-write + 0x00000000 + + + SUBB_START + Start of sub-region A + 0 + 11 + + + SUBB_LENGTH + Length of sub-region A + 16 + 12 + + + + + + + SEC_GTZC1_TZSC + DCB->DSCSR->CDS == 0 + 0x50032400 + + + GTZC2_MPCBB4 + GTZC2_MPCBB4 + GTZC + 0x46023800 + + 0x0 + 0x400 + registers + + + + MPCBB4_CR + MPCBB4_CR + MPCBB control register + 0x0 + 0x20 + read-write + 0x00000000 + + + GLOCK + lock the control register of the MPCBB until next reset + 0 + 1 + + + INVSECSTATE + SRAMx clocks security state + 30 + 1 + + + SRWILADIS + secure read/write illegal access disable + 31 + 1 + + + + + MPCBB4_CFGLOCK + MPCBB4_CFGLOCK + GTZC2 SRAM4 MPCBB configuration lock register + 0x10 + 0x20 + read-write + 0x00000000 + + + SPLCK0 + Security/privilege configuration lock for super-block 0 + 0 + 1 + + + + + MPCBB4_SECCFGR0 + MPCBB4_SECCFGR0 + MPCBB security configuration for super-block 0 register + 0x100 + 0x20 + read-write + 0xFFFFFFFF + + + SEC0 + SEC0 + 0 + 1 + + + SEC1 + SEC1 + 1 + 1 + + + SEC2 + SEC2 + 2 + 1 + + + SEC3 + SEC3 + 3 + 1 + + + SEC4 + SEC4 + 4 + 1 + + + SEC5 + SEC5 + 5 + 1 + + + SEC6 + SEC6 + 6 + 1 + + + SEC7 + SEC7 + 7 + 1 + + + SEC8 + SEC8 + 8 + 1 + + + SEC9 + SEC9 + 9 + 1 + + + SEC10 + SEC10 + 10 + 1 + + + SEC11 + SEC11 + 11 + 1 + + + SEC12 + SEC12 + 12 + 1 + + + SEC13 + SEC13 + 13 + 1 + + + SEC14 + SEC14 + 14 + 1 + + + SEC15 + SEC15 + 15 + 1 + + + SEC16 + SEC16 + 16 + 1 + + + SEC17 + SEC17 + 17 + 1 + + + SEC18 + SEC18 + 18 + 1 + + + SEC19 + SEC19 + 19 + 1 + + + SEC20 + SEC20 + 20 + 1 + + + SEC21 + SEC21 + 21 + 1 + + + SEC22 + SEC22 + 22 + 1 + + + SEC23 + SEC23 + 23 + 1 + + + SEC24 + SEC24 + 24 + 1 + + + SEC25 + SEC25 + 25 + 1 + + + SEC26 + SEC26 + 26 + 1 + + + SEC27 + SEC27 + 27 + 1 + + + SEC28 + SEC28 + 28 + 1 + + + SEC29 + SEC29 + 29 + 1 + + + SEC30 + SEC30 + 30 + 1 + + + SEC31 + SEC31 + 31 + 1 + + + + + MPCBB4_PRIVCFGR0 + MPCBB4_PRIVCFGR0 + MPCBB privileged configuration for super-block 0 register + 0x200 + 0x20 + read-write + 0xFFFFFFFF + + + PRIV0 + PRIV0 + 0 + 1 + + + PRIV1 + PRIV1 + 1 + 1 + + + PRIV2 + PRIV2 + 2 + 1 + + + PRIV3 + PRIV3 + 3 + 1 + + + PRIV4 + PRIV4 + 4 + 1 + + + PRIV5 + PRIV5 + 5 + 1 + + + PRIV6 + PRIV6 + 6 + 1 + + + PRIV7 + PRIV7 + 7 + 1 + + + PRIV8 + PRIV8 + 8 + 1 + + + PRIV9 + PRIV9 + 9 + 1 + + + PRIV10 + PRIV10 + 10 + 1 + + + PRIV11 + PRIV11 + 11 + 1 + + + PRIV12 + PRIV12 + 12 + 1 + + + PRIV13 + PRIV13 + 13 + 1 + + + PRIV14 + PRIV14 + 14 + 1 + + + PRIV15 + PRIV15 + 15 + 1 + + + PRIV16 + PRIV16 + 16 + 1 + + + PRIV17 + PRIV17 + 17 + 1 + + + PRIV18 + PRIV18 + 18 + 1 + + + PRIV19 + PRIV19 + 19 + 1 + + + PRIV20 + PRIV20 + 20 + 1 + + + PRIV21 + PRIV21 + 21 + 1 + + + PRIV22 + PRIV22 + 22 + 1 + + + PRIV23 + PRIV23 + 23 + 1 + + + PRIV24 + PRIV24 + 24 + 1 + + + PRIV25 + PRIV25 + 25 + 1 + + + PRIV26 + PRIV26 + 26 + 1 + + + PRIV27 + PRIV27 + 27 + 1 + + + PRIV28 + PRIV28 + 28 + 1 + + + PRIV29 + PRIV29 + 29 + 1 + + + PRIV30 + PRIV30 + 30 + 1 + + + PRIV31 + PRIV31 + 31 + 1 + + + + + + + SEC_GTZC2_MPCBB4 + DCB->DSCSR->CDS == 0 + 0x56023800 + + + GTZC2_TZIC + GTZC2_TZIC + GTZC + 0x46023400 + + 0x0 + 0x400 + registers + + + + IER1 + IER1 + TZIC interrupt enable register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + SPI3IE + illegal access interrupt enable for SPI3 + 0 + 1 + + + LPUART1IE + illegal access interrupt enable for LPUART1 + 1 + 1 + + + I2C3IE + illegal access interrupt enable for I2C3 + 2 + 1 + + + LPTIM1IE + illegal access interrupt enable for LPTIM1 + 3 + 1 + + + LPTIM3IE + illegal access interrupt enable for LPTIM3 + 4 + 1 + + + LPTIM4IE + illegal access interrupt enable for LPTIM4 + 5 + 1 + + + OPAMPIE + illegal access interrupt enable for OPAMP + 6 + 1 + + + COMPIE + illegal access interrupt enable for COMP + 7 + 1 + + + ADC2IE + illegal access interrupt enable for ADC2 + 8 + 1 + + + VREFBUFIE + illegal access interrupt enable for VREFBUF + 9 + 1 + + + DAC1IE + illegal access interrupt enable for DAC1 + 11 + 1 + + + ADF1IE + illegal access interrupt enable for ADF1 + 12 + 1 + + + + + IER2 + IER2 + TZIC interrupt enable register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + SYSCFGIE + illegal access interrupt enable for SYSCFG + 0 + 1 + + + RTCIE + illegal access interrupt enable for RTC + 1 + 1 + + + TAMPIE + illegal access interrupt enable for TAMP + 2 + 1 + + + PWRIE + illegal access interrupt enable for PWR + 3 + 1 + + + RCCIE + illegal access interrupt enable for RCC + 4 + 1 + + + LPDMA1IE + illegal access interrupt enable for LPDMA + 5 + 1 + + + EXTIIE + illegal access interrupt enable for EXTI + 6 + 1 + + + TZSC2IE + illegal access interrupt enable for GTZC2 TZSC registers + 14 + 1 + + + TZIC2IE + illegal access interrupt enable for GTZC2 TZIC registers + 15 + 1 + + + SRAM4IE + illegal access interrupt enable for SRAM4 + 24 + 1 + + + MPCBB4_REGIE + illegal access interrupt enable for MPCBB4 registers + 25 + 1 + + + + + SR1 + SR1 + TZIC status register 1 + 0x10 + 0x20 + read-only + 0x00000000 + + + SPI3F + illegal access flag for SPI3 + 0 + 1 + + + LPUART1F + illegal access flag for LPUART1 + 1 + 1 + + + I2C3F + illegal access flag for I2C3 + 2 + 1 + + + LPTIM1F + illegal access flag for LPTIM1 + 3 + 1 + + + LPTIM3F + illegal access flag for LPTIM3 + 4 + 1 + + + LPTIM4F + illegal access flag for LPTIM4 + 5 + 1 + + + OPAMPF + illegal access flag for OPAMP + 6 + 1 + + + COMPF + illegal access flag for COMP + 7 + 1 + + + ADC2F + illegal access flag for ADC2 + 8 + 1 + + + VREFBUFF + illegal access flag for VREFBUF + 9 + 1 + + + DAC1F + illegal access flag for DAC1 + 11 + 1 + + + ADF1F + illegal access flag for ADF1 + 12 + 1 + + + + + SR2 + SR2 + TZIC status register 2 + 0x14 + 0x20 + read-only + 0x00000000 + + + SYSCFGF + illegal access flag for SYSCFG + 0 + 1 + + + RTCF + illegal access flag for RTC + 1 + 1 + + + TAMPF + illegal access flag for TAMP + 2 + 1 + + + PWRF + illegal access flag for PWRUSART1F + 3 + 1 + + + RCCF + illegal access flag for RCC + 4 + 1 + + + LPDMA1F + illegal access flag for LPDMA + 5 + 1 + + + EXTIF + illegal access flag for EXTI + 6 + 1 + + + TZSC2F + illegal access flag for GTZC2 TZSC registers + 14 + 1 + + + TZIC2F + illegal access flag for GTZC2 TZIC registers + 15 + 1 + + + SRAM4F + illegal access flag for SRAM4 + 24 + 1 + + + MPCBB4_REGF + illegal access flag for MPCBB4 registers + 25 + 1 + + + + + FCR1 + FCR1 + TZIC flag clear register 1 + 0x20 + 0x20 + write-only + 0x00000000 + + + CSPI3F + clear the illegal access flag for SPI3 + 0 + 1 + + + CLPUART1F + clear the illegal access flag for LPUART1 + 1 + 1 + + + CI2C3F + clear the illegal access flag for I2C3 + 2 + 1 + + + CLPTIM1F + clear the illegal access flag for LPTIM1 + 3 + 1 + + + CLPTIM3F + clear the illegal access flag for LPTIM3 + 4 + 1 + + + CLPTIM4F + clear the illegal access flag for LPTIM4 + 5 + 1 + + + COPAMPF + clear the illegal access flag for OPAMP + 6 + 1 + + + CCOMPF + clear the illegal access flag for COMP + 7 + 1 + + + CADC2F + clear the illegal access flag for ADC2 + 8 + 1 + + + CVREFBUFF + clear the illegal access flag for VREFBUF + 9 + 1 + + + CDAC1F + clear the illegal access flag for DAC1 + 11 + 1 + + + CADF1F + clear the illegal access flag for ADF1 + 12 + 1 + + + + + FCR2 + FCR2 + TZIC flag clear register 2 + 0x24 + 0x20 + write-only + 0x00000000 + + + CSYSCFGF + clear the illegal access flag for SYSCFG + 0 + 1 + + + CRTCF + clear the illegal access flag for RTC + 1 + 1 + + + CTAMPF + clear the illegal access flag for TAMP + 2 + 1 + + + CPWRF + clear the illegal access flag for PWR + 3 + 1 + + + CRCCF + clear the illegal access flag for RCC + 4 + 1 + + + CLPDMA1F + clear the illegal access flag for LPDMA + 5 + 1 + + + CEXTIF + clear the illegal access flag for EXTI + 6 + 1 + + + CTZSC2F + clear the illegal access flag for GTZC2 TZSC registers + 14 + 1 + + + CTZIC2F + clear the illegal access flag for GTZC2 TZIC registers + 15 + 1 + + + CSRAM4F + clear the illegal access flag for SRAM4 + 24 + 1 + + + CMPCBB4_REGF + clear the illegal access flag for MPCBB4 registers + 25 + 1 + + + + + + + SEC_GTZC2_TZIC + DCB->DSCSR->CDS == 0 + 0x56023400 + + + GTZC2_TZSC + GTZC2_TZSC + GTZC + 0x46023000 + + 0x0 + 0x400 + registers + + + + TZSC_CR + TZSC_CR + TZSC control register + 0x0 + 0x20 + read-write + 0x00000000 + + + LCK + lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx +registers until next reset + 0 + 1 + + + + + TZSC_SECCFGR1 + TZSC_SECCFGR1 + TZSC secure configuration register 1 + 0x10 + 0x20 + read-write + 0x00000000 + + + SPI3SEC + secure access mode for SPI3 + 0 + 1 + + + LPUART1SEC + secure access mode for LPUART1 + 1 + 1 + + + I2C3SEC + secure access mode for I2C3 + 2 + 1 + + + LPTIM1SEC + secure access mode for LPTIM1 + 3 + 1 + + + LPTIM3SEC + secure access mode for LPTIM3 + 4 + 1 + + + LPTIM4SEC + secure access mode for LPTIM4 + 5 + 1 + + + OPAMPSEC + secure access mode for OPAMP + 6 + 1 + + + COMPSEC + secure access mode for COMP + 7 + 1 + + + ADC2SEC + secure access mode for ADC2 + 8 + 1 + + + VREFBUFSEC + secure access mode for VREFBUF + 9 + 1 + + + DAC1SEC + secure access mode for DAC1 + 11 + 1 + + + ADF1SEC + secure access mode for ADF1 + 12 + 1 + + + + + TZSC_PRIVCFGR1 + TZSC_PRIVCFGR1 + TZSC privilege configuration register 1 + 0x20 + 0x20 + read-write + 0x00000000 + + + SPI3PRIV + privileged access mode for SPI3 + 0 + 1 + + + LPUART1PRIV + privileged access mode for LPUART1 + 1 + 1 + + + I2C3PRIV + privileged access mode for I2C3 + 2 + 1 + + + LPTIM1PRIV + privileged access mode for LPTIM1 + 3 + 1 + + + LPTIM3PRIV + privileged access mode for LPTIM3 + 4 + 1 + + + LPTIM4PRIV + privileged access mode for LPTIM4 + 5 + 1 + + + OPAMPPRIV + privileged access mode for OPAMP + 6 + 1 + + + COMPPRIV + privileged access mode for COMP + 7 + 1 + + + ADC2PRIV + privileged access mode for ADC2 + 8 + 1 + + + VREFBUFPRIV + privileged access mode for VREFBUF + 9 + 1 + + + DAC1PRIV + privileged access mode for DAC1 + 11 + 1 + + + ADF1PRIV + privileged access mode for ADF1 + 12 + 1 + + + + + + + SEC_GTZC2_TZSC + DCB->DSCSR->CDS == 0 + 0x56023000 + + + HASH + Hash processor + HASH + 0x420C0400 + + 0x0 + 0x400 + registers + + + HASH + HASH interrupt + 96 + + + + CR + CR + control register + 0x0 + 0x20 + 0x00000000 + + + INIT + Initialize message digest calculation + 2 + 1 + write-only + + + DMAE + DMA enable + 3 + 1 + read-write + + + DATATYPE + Data type selection + 4 + 2 + read-write + + + MODE + Mode selection + 6 + 1 + read-write + + + ALGO + Algorithm selection + 17 + 2 + read-write + + + NBW + Number of words already pushed + 8 + 4 + read-only + + + DINNE + DIN not empty + 12 + 1 + read-only + + + MDMAT + Multiple DMA Transfers + 13 + 1 + read-write + + + LKEY + Long key selection + 16 + 1 + read-write + + + + + DIN + DIN + data input register + 0x4 + 0x20 + write-only + 0x00000000 + + + DATAIN + Data input + 0 + 32 + + + + + STR + STR + start register + 0x8 + 0x20 + 0x00000000 + + + DCAL + Digest calculation + 8 + 1 + write-only + + + NBLW + Number of valid bits in the last word of the message + 0 + 5 + read-write + + + + + HRA0 + HRA0 + HASH aliased digest register 0 + 0xC + 0x20 + read-only + 0x00000000 + + + H0 + H0 + 0 + 32 + + + + + HRA1 + HRA1 + HASH aliased digest register 1 + 0x10 + 0x20 + read-only + 0x00000000 + + + H1 + H1 + 0 + 32 + + + + + HRA2 + HRA2 + HASH aliased digest register 2 + 0x14 + 0x20 + read-only + 0x00000000 + + + H2 + H2 + 0 + 32 + + + + + HRA3 + HRA3 + HASH aliased digest register 3 + 0x18 + 0x20 + read-only + 0x00000000 + + + H3 + H3 + 0 + 32 + + + + + HRA4 + HRA4 + HASH aliased digest register 4 + 0x1C + 0x20 + read-only + 0x00000000 + + + H4 + H4 + 0 + 32 + + + + + HR0 + HR0 + digest register 0 + 0x310 + 0x20 + read-only + 0x00000000 + + + H0 + H0 + 0 + 32 + + + + + HR1 + HR1 + digest register 1 + 0x314 + 0x20 + read-only + 0x00000000 + + + H1 + H1 + 0 + 32 + + + + + HR2 + HR2 + digest register 4 + 0x318 + 0x20 + read-only + 0x00000000 + + + H2 + H2 + 0 + 32 + + + + + HR3 + HR3 + digest register 3 + 0x31C + 0x20 + read-only + 0x00000000 + + + H3 + H3 + 0 + 32 + + + + + HR4 + HR4 + digest register 4 + 0x320 + 0x20 + read-only + 0x00000000 + + + H4 + H4 + 0 + 32 + + + + + HR5 + HR5 + supplementary digest register 5 + 0x324 + 0x20 + read-only + 0x00000000 + + + H5 + H5 + 0 + 32 + + + + + HR6 + HR6 + supplementary digest register 6 + 0x328 + 0x20 + read-only + 0x00000000 + + + H6 + H6 + 0 + 32 + + + + + HR7 + HR7 + supplementary digest register 7 + 0x32C + 0x20 + read-only + 0x00000000 + + + H7 + H7 + 0 + 32 + + + + + IMR + IMR + interrupt enable register + 0x20 + 0x20 + read-write + 0x00000000 + + + DCIE + Digest calculation completion interrupt enable + 1 + 1 + + + DINIE + Data input interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x24 + 0x20 + 0x00000001 + + + BUSY + Busy bit + 3 + 1 + read-only + + + DMAS + DMA Status + 2 + 1 + read-only + + + DCIS + Digest calculation completion interrupt status + 1 + 1 + read-write + + + DINIS + Data input interrupt status + 0 + 1 + read-write + + + NBWE + Number of words expected + 16 + 5 + read-only + + + DINNE + DIN not empty + 15 + 1 + read-only + + + NBWP + Number of words already pushed + 9 + 5 + read-only + + + + + CSR0 + CSR0 + context swap registers + 0xF8 + 0x20 + read-write + 0x00000000 + + + CS0 + CS0 + 0 + 32 + + + + + CSR1 + CSR1 + context swap registers + 0xFC + 0x20 + read-write + 0x00000000 + + + CS1 + CS1 + 0 + 32 + + + + + CSR2 + CSR2 + context swap registers + 0x100 + 0x20 + read-write + 0x00000000 + + + CS2 + CS2 + 0 + 32 + + + + + CSR3 + CSR3 + context swap registers + 0x104 + 0x20 + read-write + 0x00000000 + + + CS3 + CS3 + 0 + 32 + + + + + CSR4 + CSR4 + context swap registers + 0x108 + 0x20 + read-write + 0x00000000 + + + CS4 + CS4 + 0 + 32 + + + + + CSR5 + CSR5 + context swap registers + 0x10C + 0x20 + read-write + 0x00000000 + + + CS5 + CS5 + 0 + 32 + + + + + CSR6 + CSR6 + context swap registers + 0x110 + 0x20 + read-write + 0x00000000 + + + CS6 + CS6 + 0 + 32 + + + + + CSR7 + CSR7 + context swap registers + 0x114 + 0x20 + read-write + 0x00000000 + + + CS7 + CS7 + 0 + 32 + + + + + CSR8 + CSR8 + context swap registers + 0x118 + 0x20 + read-write + 0x00000000 + + + CS8 + CS8 + 0 + 32 + + + + + CSR9 + CSR9 + context swap registers + 0x11C + 0x20 + read-write + 0x00000000 + + + CS9 + CS9 + 0 + 32 + + + + + CSR10 + CSR10 + context swap registers + 0x120 + 0x20 + read-write + 0x00000000 + + + CS10 + CS10 + 0 + 32 + + + + + CSR11 + CSR11 + context swap registers + 0x124 + 0x20 + read-write + 0x00000000 + + + CS11 + CS11 + 0 + 32 + + + + + CSR12 + CSR12 + context swap registers + 0x128 + 0x20 + read-write + 0x00000000 + + + CS12 + CS12 + 0 + 32 + + + + + CSR13 + CSR13 + context swap registers + 0x12C + 0x20 + read-write + 0x00000000 + + + CS13 + CS13 + 0 + 32 + + + + + CSR14 + CSR14 + context swap registers + 0x130 + 0x20 + read-write + 0x00000000 + + + CS14 + CS14 + 0 + 32 + + + + + CSR15 + CSR15 + context swap registers + 0x134 + 0x20 + read-write + 0x00000000 + + + CS15 + CS15 + 0 + 32 + + + + + CSR16 + CSR16 + context swap registers + 0x138 + 0x20 + read-write + 0x00000000 + + + CS16 + CS16 + 0 + 32 + + + + + CSR17 + CSR17 + context swap registers + 0x13C + 0x20 + read-write + 0x00000000 + + + CS17 + CS17 + 0 + 32 + + + + + CSR18 + CSR18 + context swap registers + 0x140 + 0x20 + read-write + 0x00000000 + + + CS18 + CS18 + 0 + 32 + + + + + CSR19 + CSR19 + context swap registers + 0x144 + 0x20 + read-write + 0x00000000 + + + CS19 + CS19 + 0 + 32 + + + + + CSR20 + CSR20 + context swap registers + 0x148 + 0x20 + read-write + 0x00000000 + + + CS20 + CS20 + 0 + 32 + + + + + CSR21 + CSR21 + context swap registers + 0x14C + 0x20 + read-write + 0x00000000 + + + CS21 + CS21 + 0 + 32 + + + + + CSR22 + CSR22 + context swap registers + 0x150 + 0x20 + read-write + 0x00000000 + + + CS22 + CS22 + 0 + 32 + + + + + CSR23 + CSR23 + context swap registers + 0x154 + 0x20 + read-write + 0x00000000 + + + CS23 + CS23 + 0 + 32 + + + + + CSR24 + CSR24 + context swap registers + 0x158 + 0x20 + read-write + 0x00000000 + + + CS24 + CS24 + 0 + 32 + + + + + CSR25 + CSR25 + context swap registers + 0x15C + 0x20 + read-write + 0x00000000 + + + CS25 + CS25 + 0 + 32 + + + + + CSR26 + CSR26 + context swap registers + 0x160 + 0x20 + read-write + 0x00000000 + + + CS26 + CS26 + 0 + 32 + + + + + CSR27 + CSR27 + context swap registers + 0x164 + 0x20 + read-write + 0x00000000 + + + CS27 + CS27 + 0 + 32 + + + + + CSR28 + CSR28 + context swap registers + 0x168 + 0x20 + read-write + 0x00000000 + + + CS28 + CS28 + 0 + 32 + + + + + CSR29 + CSR29 + context swap registers + 0x16C + 0x20 + read-write + 0x00000000 + + + CS29 + CS29 + 0 + 32 + + + + + CSR30 + CSR30 + context swap registers + 0x170 + 0x20 + read-write + 0x00000000 + + + CS30 + CS30 + 0 + 32 + + + + + CSR31 + CSR31 + context swap registers + 0x174 + 0x20 + read-write + 0x00000000 + + + CS31 + CS31 + 0 + 32 + + + + + CSR32 + CSR32 + context swap registers + 0x178 + 0x20 + read-write + 0x00000000 + + + CS32 + CS32 + 0 + 32 + + + + + CSR33 + CSR33 + context swap registers + 0x17C + 0x20 + read-write + 0x00000000 + + + CS33 + CS33 + 0 + 32 + + + + + CSR34 + CSR34 + context swap registers + 0x180 + 0x20 + read-write + 0x00000000 + + + CS34 + CS34 + 0 + 32 + + + + + CSR35 + CSR35 + context swap registers + 0x184 + 0x20 + read-write + 0x00000000 + + + CS35 + CS35 + 0 + 32 + + + + + CSR36 + CSR36 + context swap registers + 0x188 + 0x20 + read-write + 0x00000000 + + + CS36 + CS36 + 0 + 32 + + + + + CSR37 + CSR37 + context swap registers + 0x18C + 0x20 + read-write + 0x00000000 + + + CS37 + CS37 + 0 + 32 + + + + + CSR38 + CSR38 + context swap registers + 0x190 + 0x20 + read-write + 0x00000000 + + + CS38 + CS38 + 0 + 32 + + + + + CSR39 + CSR39 + context swap registers + 0x194 + 0x20 + read-write + 0x00000000 + + + CS39 + CS39 + 0 + 32 + + + + + CSR40 + CSR40 + context swap registers + 0x198 + 0x20 + read-write + 0x00000000 + + + CS40 + CS40 + 0 + 32 + + + + + CSR41 + CSR41 + context swap registers + 0x19C + 0x20 + read-write + 0x00000000 + + + CS41 + CS41 + 0 + 32 + + + + + CSR42 + CSR42 + context swap registers + 0x1A0 + 0x20 + read-write + 0x00000000 + + + CS42 + CS42 + 0 + 32 + + + + + CSR43 + CSR43 + context swap registers + 0x1A4 + 0x20 + read-write + 0x00000000 + + + CS43 + CS43 + 0 + 32 + + + + + CSR44 + CSR44 + context swap registers + 0x1A8 + 0x20 + read-write + 0x00000000 + + + CS44 + CS44 + 0 + 32 + + + + + CSR45 + CSR45 + context swap registers + 0x1AC + 0x20 + read-write + 0x00000000 + + + CS45 + CS45 + 0 + 32 + + + + + CSR46 + CSR46 + context swap registers + 0x1B0 + 0x20 + read-write + 0x00000000 + + + CS46 + CS46 + 0 + 32 + + + + + CSR47 + CSR47 + context swap registers + 0x1B4 + 0x20 + read-write + 0x00000000 + + + CS47 + CS47 + 0 + 32 + + + + + CSR48 + CSR48 + context swap registers + 0x1B8 + 0x20 + read-write + 0x00000000 + + + CS48 + CS48 + 0 + 32 + + + + + CSR49 + CSR49 + context swap registers + 0x1BC + 0x20 + read-write + 0x00000000 + + + CS49 + CS49 + 0 + 32 + + + + + CSR50 + CSR50 + context swap registers + 0x1C0 + 0x20 + read-write + 0x00000000 + + + CS50 + CS50 + 0 + 32 + + + + + CSR51 + CSR51 + context swap registers + 0x1C4 + 0x20 + read-write + 0x00000000 + + + CS51 + CS51 + 0 + 32 + + + + + CSR52 + CSR52 + context swap registers + 0x1C8 + 0x20 + read-write + 0x00000000 + + + CS52 + CS52 + 0 + 32 + + + + + CSR53 + CSR53 + context swap registers + 0x1CC + 0x20 + read-write + 0x00000000 + + + CS53 + CS53 + 0 + 32 + + + + + + + SEC_HASH + DCB->DSCSR->CDS == 0 + 0x520C0400 + + + HSPI1 + HSPI1 + HSPI + 0x420D3400 + + 0x0 + 0x400 + registers + + + HSPI1 + Hexadeca-SPI1 global interrupt + 131 + + + + HSPI_CR + HSPI_CR + HSPI control register + 0x0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +This bit enables the HSPI. +Note: The DMA request can be aborted without having received the ACK in case this EN bit is cleared during the operation. +In case this bit is set to 0 during a DMA transfer, the REQ signal to DMA returns to inactive state without waiting for the ACK signal from DMA to be active. + 0 + 1 + read-write + + + B_0x0 + HSPI disabled + 0x0 + + + B_0x1 + HSPI enabled + 0x1 + + + + + ABORT + Abort request +This bit aborts the on-going command sequence. It is automatically reset once the abort is completed. This bit stops the current transfer. +Note: This bit is always read as 0. + 1 + 1 + read-write + + + B_0x0 + No abort requested + 0x0 + + + B_0x1 + Abort requested + 0x1 + + + + + DMAEN + DMA enable +In Indirect mode, the DMA can be used to input or output data via HSPI_DR. DMA transfers are initiated when FTF is set. +Note: Resetting the DMAEN bit while a DMA transfer is ongoing, breaks the handshake with the DMA. Do not write this bit during DMA operation. + 2 + 1 + read-write + + + B_0x0 + DMA disabled for Indirect mode + 0x0 + + + B_0x1 + DMA enabled for Indirect mode + 0x1 + + + + + TCEN + Timeout counter enable +This bit is valid only when the Memory-mapped mode (FMODE[1:0] = 11) is selected. This bit enables the timeout counter. + 3 + 1 + read-write + + + B_0x0 + Timeout counter is disabled, and thus the chip-select (nCS) remains active indefinitely after an access in Memory-mapped mode. + 0x0 + + + B_0x1 + Timeout counter is enabled, and thus the chip-select is released in the Memory-mapped mode after TIMEOUT[15:0] cycles of external device inactivity. + 0x1 + + + + + DMM + Dual-memory mode +This bit activates the Dual-memory mode, where two external devices are used simultaneously to double the throughput and the capacity + 6 + 1 + read-write + + + B_0x0 + Dual-quad mode disabled + 0x0 + + + B_0x1 + Dual-quad mode enabled + 0x1 + + + + + FSEL + Memory select +This bit is the mirror of bit 30. Refer to the description of MSEL[1:0] above. +This bit is set when 1 is written in bit 30 or bit 7. When this bit is set, both b30 and b7 are read as 1. +This bit is reset when bit 30 and bit7 are set to 0. When this bit is reset, both bit 30 and bit7 are read as 0. + 7 + 1 + read-write + + + FTHRES + FIFO threshold level +This field defines, in Indirect mode, the threshold number of bytes in the FIFO that causes the FIFO threshold flag FTF in HSPI_SR, to be set. +... +Note: If DMAEN = 1, the DMA controller for the corresponding channel must be disabled before changing the FTHRES[5:0] value. + 8 + 6 + read-write + + + B_0x0 + FTF is set if there are one or more free bytes available to be written to in the FIFO in Indirect-write mode, or if there are one or more valid bytes can be read from the FIFO in Indirect-read mode. + 0x0 + + + B_0x1 + FTF is set if there are two or more free bytes available to be written to in the FIFO in Indirect-write mode, or if there are two or more valid bytes can be read from the FIFO in Indirect-read mode. + 0x1 + + + B_0x3F + FTF is set if there are 64 free bytes available to be written to in the FIFO in Indirect-write mode, or if there are 64 valid bytes can be read from the FIFO in Indirect-read mode. + 0x3F + + + + + TEIE + Transfer error interrupt enable +This bit enables the transfer error interrupt. + 16 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + TCIE + Transfer complete interrupt enable +This bit enables the transfer complete interrupt. + 17 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + FTIE + FIFO threshold interrupt enable +This bit enables the FIFO threshold interrupt. + 18 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + SMIE + Status match interrupt enable +This bit enables the status match interrupt. + 19 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + TOIE + Timeout interrupt enable +This bit enables the timeout interrupt. + 20 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + APMS + Automatic-polling mode stop +This bit determines if the automatic polling is stopped after a match. + 22 + 1 + read-write + + + B_0x0 + Automatic-polling mode is stopped only by abort or by disabling the HSPI. + 0x0 + + + B_0x1 + Automatic-polling mode stops as soon as there is a match. + 0x1 + + + + + PMM + Polling match mode +This bit indicates which method must be used to determine a match during the Automatic-polling mode. + 23 + 1 + read-write + + + B_0x0 + AND-match mode, SMF is set if all the unmasked bits received from the device match the corresponding bits in the match register. + 0x0 + + + B_0x1 + OR-match mode, SMF is set if any of the unmasked bits received from the device matches its corresponding bit in the match register. + 0x1 + + + + + FMODE + Functional mode +This field defines the HSPI functional mode of operation. +If DMAEN = 1 already, then the DMA controller for the corresponding channel must be disabled before changing the FMODE[1:0] value. If FMODE[1:0] and FTHRES[4:0] are wrongly updated while DMAEN = 1, the DMA request signal automatically goes to inactive state. + 28 + 2 + read-write + + + B_0x0 + Indirect-write mode + 0x0 + + + B_0x1 + Indirect-read mode + 0x1 + + + B_0x2 + Automatic-polling mode + 0x2 + + + B_0x3 + Memory-mapped mode + 0x3 + + + + + MSEL + Flash select +These bits select the memory to be addressed in Single, Dual, Quad or Octal mode in single‑memory configuration (when DMM = 0). +- when in Quad mode: +- when in Octal mode or Dual-quad mode: +0x: data exchanged over IO[7:0] +1x: data exchanged over IO[15:8] +These bits are ignored when in dual-octal configuration (data on 8 bits and DMM = 1) or 16‑bit configuration (data exchanged over IO[15:0]). + 30 + 2 + read-write + + + B_0x0 + data exchanged over IO[3:0] + 0x0 + + + B_0x1 + data exchanged over IO[7:4] + 0x1 + + + B_0x2 + data exchanged over IO11:8] + 0x2 + + + B_0x3 + data exchanged over IO[15:12] + 0x3 + + + + + + + HSPI_DCR1 + HSPI_DCR1 + HSPI device configuration register 1 + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CKMODE + Mode 0/Mode 3 +This bit indicates the level taken by the CLK between commands (when nCS = 1). + 0 + 1 + read-write + + + B_0x0 + CLK must stay low while nCS is high (chip-select released). This is referred to as Mode 0. + 0x0 + + + B_0x1 + CLK must stay high while nCS is high (chip-select released). This is referred to as Mode 3. + 0x1 + + + + + FRCK + Free running clock +This bit configures the free running clock. + 1 + 1 + read-write + + + B_0x0 + CLK is not free running. + 0x0 + + + B_0x1 + CLK is free running (always provided). + 0x1 + + + + + DLYBYP + Delay block bypass + 3 + 1 + read-write + + + B_0x0 + The internal sampling clock (called feedback clock) or the DQS data strobe external signal is delayed by the delay block (for more details on this block, refer to the dedicated section of the reference manual as it is not part of the HSPI). + 0x0 + + + B_0x1 + The delay block is bypassed, so the internal sampling clock or the DQS data strobe external signal is not affected by the delay block. The delay is shorter than when the delay block is not bypassed, even with the delay value set to minimum value in delay block. + 0x1 + + + + + CSHT + Chip-select high time +CSHT + 1 defines the minimum number of CLK cycles where the chip-select (nCS) must remain high between commands issued to the external device. +... +63: nCS stays high for at least 64 cycles between external device commands. +Note: When the extended CSHT timeout feature is not supported, CSHT[5:3] are reserved and the number of cycles is limited to eight (refer to implementation). + 8 + 6 + read-write + + + B_0x0 + nCS stays high for at least 1 cycle between external device commands. + 0x0 + + + B_0x1 + nCS stays high for at least 2 cycles between external device commands. + 0x1 + + + + + DEVSIZE + Device size +This field defines the size of the external device using the following formula: +Number of bytes in device = 2[DEVSIZE+1]. +DEVSIZE+1 is effectively the number of address bits required to address the external device. The device capacity can be up to 4 Gbytes (addressed using 32-bits) in Indirect mode, but the addressable space in Memory-mapped mode is limited to 256 Mbytes. +In Regular-command mode, if DMM = 1, DEVSIZE[4:0] indicates the total capacity of the two devices together. + 16 + 5 + read-write + + + MTYP + Memory type +This bit indicates the type of memory to be supported. +Note: In this mode, DQS signal polarity is inverted with respect to the memory clock signal. This is the default value and care must be taken to change MTYP[2:0] for memories different from Micron. +Others: Reserved + 24 + 3 + read-write + + + B_0x0 + Micron mode, D0/D1 ordering in DTR 8-data-bit mode. Regular SPI protocol in Octal-, Quad-, Dual- and Single-SPI modes + 0x0 + + + B_0x1 + Macronix mode, D1/D0 ordering in DTR 8-data-bit mode. Regular SPI protocol in Octal-, Quad-, Dual-, and Single-SPI modes + 0x1 + + + B_0x2 + Standard mode + 0x2 + + + B_0x3 + Macronix RAM mode, D1/D0 ordering in DTR 8-data-bit mode. Regular SPI protocol in Octal-, Quad-, Dual-, and Single-SPI with dedicated address mapping. + 0x3 + + + B_0x4 + HyperBus memory mode, the protocol follows the HyperBus specification. 8-data-bit DTR mode must be selected. + 0x4 + + + B_0x5 + HyperBus register mode, addressing register space. The memory-mapped accesses in this mode must be non-cacheable, or Indirect read/write modes must be used. + 0x5 + + + + + + + HSPI_DCR2 + HSPI_DCR2 + HSPI device configuration register 2 + 0xc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRESCALER + Clock prescaler +This field defines the scaler factor for generating the CLK based on the kernel clock (value + 1). +2: FCLK = FKERNEL/3 +... +255: FCLK = FKERNEL/256 +For odd clock division factors, the CLK duty cycle is not 50 %. The clock signal remains low one cycle longer than it stays high. +Writing this field automatically starts a new calibration of high-speed interface DLL at the start of next transfer, except in case HSPI_CALOSR or HSPI_CALISR have been written in the meantime. BUSY stays high during the whole calibration execution. + 0 + 8 + read-write + + + B_0x0 + FCLK = FKERNEL, kernel clock used directly as HSPICLK (prescaler bypassed). In this case, if the DDR mode is used, it is mandatory to provide to the HSPI a kernel clock that has 50% duty-cycle. + 0x0 + + + B_0x1 + FCLK = FKERNEL/2 + 0x1 + + + + + WRAPSIZE + Wrap size +This field indicates the wrap size to which the memory is configured. For memories which have a separate command for wrapped instructions, this field indicates the wrap-size associated with the command held in the HSPI_WPIR register. +110-111: Reserved + 16 + 3 + read-write + + + B_0x0 + Wrapped reads are not supported by the memory. + 0x0 + + + B_0x2 + External memory supports wrap size of 16 bytes. + 0x2 + + + B_0x3 + External memory supports wrap size of 32 bytes. + 0x3 + + + B_0x4 + External memory supports wrap size of 64 bytes. + 0x4 + + + B_0x5 + External memory supports wrap size of 128 bytes. + 0x5 + + + + + + + HSPI_DCR3 + HSPI_DCR3 + HSPI device configuration register 3 + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MAXTRAN + Maximum transfer +This field enables the communication regulation feature. +The nCS is released every MAXTRAN+1 clock cycles when the other HSPI request the access to the bus. +others: Maximum communication is set to MAXTRAN+1 bytes + 0 + 8 + read-write + + + B_0x0 + Maximum communication disabled + 0x0 + + + + + CSBOUND + CS boundary +This field enables the transaction boundary feature. When active, a minimum value of 3 is recommended. +The nCS is released on each boundary of 2CSBOUND bytes. +others: CS boundary set to 2CSBOUND bytes + 16 + 5 + read-write + + + B_0x0 + CS boundary disabled + 0x0 + + + + + + + HSPI_DCR4 + HSPI_DCR4 + HSPI device configuration register 4 + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + REFRESH + Refresh rate +This field enables the refresh rate feature. +The nCS is released every REFRESH+1 clock cycles for writes, and REFRESH+4 clock cycles for reads. +Note: These two values can be extended with few clock cycles when refresh occurs during a byte transmission in single, dual or quad mode, because the byte transmission must be completed. +others: Maximum communication length is set to REFRESH+1 clock cycles. + 0 + 32 + read-write + + + B_0x0 + Refresh disabled + 0x0 + + + + + + + HSPI_SR + HSPI_SR + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TEF + Transfer error flag +This bit is set in Indirect mode when an invalid address is being accessed in Indirect mode. +It is cleared by writing 1 to CTEF. + 0 + 1 + read-only + + + TCF + Transfer complete flag +This bit is set in Indirect mode when the programmed number of data has been transferred or in any mode when the transfer has been aborted.It is cleared by writing 1 to CTCF. + 1 + 1 + read-only + + + FTF + FIFO threshold flag +In Indirect mode, this bit is set when the FIFO threshold has been reached, or if there is any data left in the FIFO after the reads from the external device are complete. +It is cleared automatically as soon as the threshold condition is no longer true. +In Automatic-polling mode this bit is set every time the status register is read, and the bit is cleared when the data register is read. + 2 + 1 + read-only + + + SMF + Status match flag +This bit is set in Automatic-polling mode when the unmasked received data matches the corresponding bits in the match register (HSPI_PSMAR). +It is cleared by writing 1 to CSMF. + 3 + 1 + read-only + + + TOF + Timeout flag +This bit is set when timeout occurs. It is cleared by writing 1 to CTOF. + 4 + 1 + read-only + + + BUSY + Busy +This bit is set when an operation is ongoing. It is cleared automatically when the operation with the external device is finished and the FIFO is empty. + 5 + 1 + read-only + + + FLEVEL + FIFO level +This field gives the number of valid bytes that are being held in the FIFO. FLEVEL = 0 when the FIFO is empty, and 64 when it is full. +In Automatic-status polling mode, FLEVEL is zero. + 8 + 7 + read-only + + + + + HSPI_FCR + HSPI_FCR + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CTEF + Clear transfer error flag +Writing 1 clears the TEF flag in the HSPI_SR register. + 0 + 1 + write-only + + + CTCF + Clear transfer complete flag +Writing 1 clears the TCF flag in the HSPI_SR register. + 1 + 1 + write-only + + + CSMF + Clear status match flag +Writing 1 clears the SMF flag in the HSPI_SR register. + 3 + 1 + write-only + + + CTOF + Clear timeout flag +Writing 1 clears the TOF flag in the HSPI_SR register. + 4 + 1 + write-only + + + + + HSPI_DLR + HSPI_DLR + HSPI data length register + 0x40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DL + [31: 0]: Data length +Number of data to be retrieved (value+1) in Indirect and Status-polling modes. A value not greater than three (indicating 4 bytes) must be used for status polling-mode. +All 1's in Indirect mode means undefined length, where HSPI continues until the end of the memory, as defined by DEVSIZE. +0x0000_0000: 1 byte is to be transferred. +0x0000_0001: 2 bytes are to be transferred. +0x0000_0002: 3 bytes are to be transferred. +0x0000_0003: 4 bytes are to be transferred. +... +0xFFFF_FFFD: 4,294,967,294 (4G-2) bytes are to be transferred. +0xFFFF_FFFE: 4,294,967,295 (4G-1) bytes are to be transferred. +0xFFFF_FFFF: undefined length; all bytes, until the end of the external device, (as defined by DEVSIZE) are to be transferred. Continue reading indefinitely if DEVSIZE = 0x1F. +DL[0] is stuck at 1 in Dual-memory mode (DMM = 1) even when 0 is written to this bit, thus assuring that each access transfers an even number of bytes. +This field has no effect when in Memory-mapped mode. + 0 + 32 + read-write + + + + + HSPI_AR + HSPI_AR + 0x48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ADDRESS + Address +Address to be sent to the external device. In HyperBus mode, this field must be even as this protocol is 16-bit word oriented. In dual-memory mode, AR[0] is forced to 1. +Writes to this field are ignored when BUSY = 1 or when FMODE = 11 (Memory-mapped mode). + 0 + 32 + read-write + + + + + HSPI_DR + HSPI_DR + 0x50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DATA + [31: 0]: Data +Data to be sent/received to/from the external SPI device +In Indirect-write mode, data written to this register is stored on the FIFO before it is sent to the external device during the data phase. If the FIFO is too full, a write operation is stalled until the FIFO has enough space to accept the amount of data being written. +In Indirect-read mode, reading this register gives (via the FIFO) the data that was received from the external device. If the FIFO does not have as many bytes as requested by the read operation and if BUSY = 1, the read operation is stalled until enough data is present or until the transfer is complete, whichever happens first. +In Automatic-polling mode, this register contains the last data read from the external device (without masking). +Word, half-word, and byte accesses to this register are supported. In Indirect-write mode, a byte write adds 1 byte to the FIFO, a half-word write 2 bytes, and a word write 4 bytes. +Similarly, in Indirect-read mode, a byte read removes 1 byte from the FIFO, a halfword read 2 bytes, and a word read 4 bytes. Accesses in Indirect mode must be aligned to the bottom of this register: A byte read must read DATA[7:0] and a half-word read must read DATA[15:0]. + 0 + 32 + read-write + + + + + HSPI_PSMKR + HSPI_PSMKR + HSPI polling status mask register + 0x80 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MASK + Status mask +Mask to be applied to the status bytes received in Polling mode +For bit n: + 0 + 32 + read-write + + + B_0x0 + Bit n of the data received in Automatic-polling mode is masked and its value is not considered in the matching logic. + 0x0 + + + B_0x1 + Bit n of the data received in Automatic-polling mode is unmasked and its value is considered in the matching logic. + 0x1 + + + + + + + HSPI_PSMAR + HSPI_PSMAR + HSPI polling status match register + 0x88 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MATCH + [31: 0]: Status match +Value to be compared with the masked status register to get a match + 0 + 32 + read-write + + + + + HSPI_PIR + HSPI_PIR + HSPI polling interval register + 0x90 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + INTERVAL + [15: 0]: Polling interval +Number of CLK cycle between a read during the automatic-polling phases + 0 + 16 + read-write + + + + + HSPI_CCR + HSPI_CCR + HSPI communication configuration register + 0x100 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IMODE + Instruction mode +This field defines the instruction phase mode of operation. +101-111: Reserved + 0 + 3 + read-write + + + B_0x0 + No instruction + 0x0 + + + B_0x1 + Instruction on a single line + 0x1 + + + B_0x2 + Instruction on two lines + 0x2 + + + B_0x3 + Instruction on four lines + 0x3 + + + B_0x4 + Instruction on eight lines + 0x4 + + + + + IDTR + Instruction double transfer rate +This bit sets the DTR mode for the instruction phase. + 3 + 1 + read-write + + + B_0x0 + DTR mode disabled for instruction phase + 0x0 + + + B_0x1 + DTR mode enabled for instruction phase + 0x1 + + + + + ISIZE + Instruction size +This bit defines instruction size. + 4 + 2 + read-write + + + B_0x0 + 8-bit instruction + 0x0 + + + B_0x1 + 16-bit instruction + 0x1 + + + B_0x2 + 24-bit instruction + 0x2 + + + B_0x3 + 32-bit instruction + 0x3 + + + + + ADMODE + Address mode +This field defines the address phase mode of operation. +101-111: Reserved + 8 + 3 + read-write + + + B_0x0 + No address + 0x0 + + + B_0x1 + Address on a single line + 0x1 + + + B_0x2 + Address on two lines + 0x2 + + + B_0x3 + Address on four lines + 0x3 + + + B_0x4 + Address on eight lines + 0x4 + + + + + ADDTR + Address double transfer rate +This bit sets the DTR mode for the address phase. + 11 + 1 + read-write + + + B_0x0 + DTR mode disabled for address phase + 0x0 + + + B_0x1 + DTR mode enabled for address phase + 0x1 + + + + + ADSIZE + Address size +This field defines address size. + 12 + 2 + read-write + + + B_0x0 + 8-bit address + 0x0 + + + B_0x1 + 16-bit address + 0x1 + + + B_0x2 + 24-bit address + 0x2 + + + B_0x3 + 32-bit address + 0x3 + + + + + ABMODE + Alternate-byte mode +This field defines the alternate byte phase mode of operation. +100-111: Reserved + 16 + 3 + read-write + + + B_0x0 + No alternate bytes + 0x0 + + + B_0x1 + Alternate bytes on a single line + 0x1 + + + B_0x2 + Alternate bytes on two lines + 0x2 + + + B_0x3 + Alternate bytes on four lines + 0x3 + + + + + ABDTR + Alternate bytes double transfer rate +This bit sets the DTR mode for the alternate bytes phase. +This field can be written only when BUSY = 0. + 19 + 1 + read-write + + + B_0x0 + DTR mode disabled for alternate bytes phase + 0x0 + + + B_0x1 + DTR mode enabled for alternate bytes phase + 0x1 + + + + + ABSIZE + Alternate bytes size +This bit defines alternate bytes size. + 20 + 2 + read-write + + + B_0x0 + 8-bit alternate bytes + 0x0 + + + B_0x1 + 16-bit alternate bytes + 0x1 + + + B_0x2 + 24-bit alternate bytes + 0x2 + + + B_0x3 + 32-bit alternate bytes + 0x3 + + + + + DMODE + Data mode +This field defines the data phase mode of operation. +110-111: Reserved + 24 + 3 + read-write + + + B_0x0 + No data + 0x0 + + + B_0x1 + Data on a single line + 0x1 + + + B_0x2 + Data on two lines + 0x2 + + + B_0x3 + Data on four lines + 0x3 + + + B_0x4 + Data on eight lines + 0x4 + + + B_0x5 + data on 16 lines + 0x5 + + + + + DDTR + Data double transfer rate +This bit sets the DTR mode for the data phase. + 27 + 1 + read-write + + + B_0x0 + DTR mode disabled for data phase + 0x0 + + + B_0x1 + DTR mode enabled for data phase + 0x1 + + + + + DQSE + DQS enable +This bit enables the data strobe management. + 29 + 1 + read-write + + + B_0x0 + DQS disabled + 0x0 + + + B_0x1 + DQS enabled + 0x1 + + + + + SIOO + Send instruction only once mode +This bit has no effect when IMODE = 00 (see ). + 31 + 1 + read-write + + + B_0x0 + Send instruction on every transaction + 0x0 + + + B_0x1 + Send instruction only for the first command + 0x1 + + + + + + + HSPI_TCR + HSPI_TCR + HSPI timing configuration register + 0x108 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DCYC + Number of dummy cycles +This field defines the duration of the dummy phase. +In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). + 0 + 5 + read-write + + + DHQC + Delay hold quarter cycle + 28 + 1 + read-write + + + B_0x0 + No delay hold + 0x0 + + + B_0x1 + 1/4 cycle hold + 0x1 + + + + + SSHIFT + Sample shift +By default, the HSPI samples data 1/2 of a CLK cycle after the data is driven by the external device. +This bit allows the data to be sampled later in order to consider the external signal delays. +The software must ensure that SSHIFT = 0 when the data phase is configured in DTR mode (when DDTR = 1.) + 30 + 1 + read-write + + + B_0x0 + No shift + 0x0 + + + B_0x1 + 1/2 cycle shift + 0x1 + + + + + + + HSPI_IR + HSPI_IR + HSPI instruction register + 0x110 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + INSTRUCTION + Instruction +Instruction to be sent to the external SPI device + 0 + 32 + read-write + + + + + HSPI_ABR + HSPI_ABR + HSPI alternate bytes register + 0x120 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ALTERNATE + [31: 0]: Alternate bytes +Optional data to be send to the external SPI device right after the address. + 0 + 32 + read-write + + + + + HSPI_LPTR + HSPI_LPTR + HSPI low-power timeout register + 0x130 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIMEOUT + [15: 0]: Timeout period +After each access in Memory-mapped mode, the HSPI prefetches the subsequent bytes and hold them in the FIFO. +This field indicates how many CLK cycles the HSPI waits after the clock becomes inactive and until it raises the nCS, putting the external device in a lower-consumption state. + 0 + 16 + read-write + + + + + HSPI_WPCCR + HSPI_WPCCR + HSPI wrap communication configuration register + 0x140 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IMODE + Instruction mode +This field defines the instruction phase mode of operation. +101-111: Reserved + 0 + 3 + read-write + + + B_0x0 + No instruction + 0x0 + + + B_0x1 + Instruction on a single line + 0x1 + + + B_0x2 + Instruction on two lines + 0x2 + + + B_0x3 + Instruction on four lines + 0x3 + + + B_0x4 + Instruction on eight lines + 0x4 + + + + + IDTR + Instruction double transfer rate +This bit sets the DTR mode for the instruction phase. + 3 + 1 + read-write + + + B_0x0 + DTR mode disabled for instruction phase + 0x0 + + + B_0x1 + DTR mode enabled for instruction phase + 0x1 + + + + + ISIZE + Instruction size +This field defines instruction size. + 4 + 2 + read-write + + + B_0x0 + 8-bit instruction + 0x0 + + + B_0x1 + 16-bit instruction + 0x1 + + + B_0x2 + 24-bit instruction + 0x2 + + + B_0x3 + 32-bit instruction + 0x3 + + + + + ADMODE + Address mode +This field defines the address phase mode of operation. +101-111: Reserved + 8 + 3 + read-write + + + B_0x0 + No address + 0x0 + + + B_0x1 + Address on a single line + 0x1 + + + B_0x2 + Address on two lines + 0x2 + + + B_0x3 + Address on four lines + 0x3 + + + B_0x4 + Address on eight lines + 0x4 + + + + + ADDTR + Address double transfer rate +This bit sets the DTR mode for the address phase. + 11 + 1 + read-write + + + B_0x0 + DTR mode disabled for address phase + 0x0 + + + B_0x1 + DTR mode enabled for address phase + 0x1 + + + + + ADSIZE + Address size +This field defines address size. + 12 + 2 + read-write + + + B_0x0 + 8-bit address + 0x0 + + + B_0x1 + 16-bit address + 0x1 + + + B_0x2 + 24-bit address + 0x2 + + + B_0x3 + 32-bit address + 0x3 + + + + + ABMODE + Alternate-byte mode +This field defines the alternate byte phase mode of operation. + 16 + 3 + read-write + + + B_0x0 + No alternate bytes + 0x0 + + + B_0x1 + Alternate bytes on a single line + 0x1 + + + B_0x2 + Alternate bytes on two lines + 0x2 + + + B_0x3 + Alternate bytes on four lines + 0x3 + + + B_0x4 + Alternate bytes on eight lines + 0x4 + + + B_0x5 + Alternate bytes on 16 lines + 0x5 + + + + + ABDTR + Alternate bytes double transfer rate +This bit sets the DTR mode for the alternate bytes phase. + 19 + 1 + read-write + + + B_0x0 + DTR mode disabled for alternate bytes phase + 0x0 + + + B_0x1 + DTR mode enabled for alternate bytes phase + 0x1 + + + + + ABSIZE + Alternate bytes size +This bit defines alternate bytes size. + 20 + 2 + read-write + + + B_0x0 + 8-bit alternate bytes + 0x0 + + + B_0x1 + 16-bit alternate bytes + 0x1 + + + B_0x2 + 24-bit alternate bytes + 0x2 + + + B_0x3 + 32-bit alternate bytes + 0x3 + + + + + DMODE + Data mode +This field defines the data phase mode of operation. +101; Data on 16 lines +110-111: Reserved + 24 + 3 + read-write + + + B_0x0 + No data + 0x0 + + + B_0x1 + Data on a single line + 0x1 + + + B_0x2 + Data on two lines + 0x2 + + + B_0x3 + Data on four lines + 0x3 + + + B_0x4 + Data on eight lines + 0x4 + + + + + DDTR + Data double transfer rate +This bit sets the DTR mode for the data phase. + 27 + 1 + read-write + + + B_0x0 + DTR mode disabled for data phase + 0x0 + + + B_0x1 + DTR mode enabled for data phase + 0x1 + + + + + DQSE + DQS enable +This bit enables the data strobe management. + 29 + 1 + read-write + + + B_0x0 + DQS disabled + 0x0 + + + B_0x1 + DQS enabled + 0x1 + + + + + + + HSPI_WPTCR + HSPI_WPTCR + HSPI wrap timing configuration register + 0x148 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DCYC + Number of dummy cycles +This field defines the duration of the dummy phase. +In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended to have at least 5 dummy cycles when using memories with DQS activated. + 0 + 5 + read-write + + + DHQC + Delay hold quarter cycle +Add a quarter cycle delay on the outputs in DTR communication to match hold requirement. + 28 + 1 + read-write + + + B_0x0 + No quarter cycle delay + 0x0 + + + B_0x1 + Quarter cycle delay inserted + 0x1 + + + + + SSHIFT + Sample shift +By default, the HSPI samples data 1/2 of a CLK cycle after the data is driven by the external device. +This bit allows the data to be sampled later in order to consider the external signal delays. +The firmware must assure that SSHIFT=0 when the data phase is configured in DTR mode (when DDTR = 1). + 30 + 1 + read-write + + + B_0x0 + No shift + 0x0 + + + B_0x1 + 1/2 cycle shift + 0x1 + + + + + + + HSPI_WPIR + HSPI_WPIR + HSPI wrap instruction register + 0x150 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + INSTRUCTION + [31: 0]: Instruction +Instruction to be sent to the external SPI device + 0 + 32 + read-write + + + + + HSPI_WPABR + HSPI_WPABR + HSPI wrap alternate bytes register + 0x160 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ALTERNATE + [31: 0]: Alternate bytes +Optional data to be sent to the external SPI device right after the address + 0 + 32 + read-write + + + + + HSPI_WCCR + HSPI_WCCR + HSPI write communication configuration register + 0x180 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IMODE + Instruction mode +This field defines the instruction phase mode of operation. +101-111: Reserved + 0 + 3 + read-write + + + B_0x0 + No instruction + 0x0 + + + B_0x1 + Instruction on a single line + 0x1 + + + B_0x2 + Instruction on two lines + 0x2 + + + B_0x3 + Instruction on four lines + 0x3 + + + B_0x4 + Instruction on eight lines + 0x4 + + + + + IDTR + Instruction double transfer rate +This bit sets the DTR mode for the instruction phase. + 3 + 1 + read-write + + + B_0x0 + DTR mode disabled for instruction phase + 0x0 + + + B_0x1 + DTR mode enabled for instruction phase + 0x1 + + + + + ISIZE + Instruction size +This bit defines instruction size: + 4 + 2 + read-write + + + B_0x0 + 8-bit instruction + 0x0 + + + B_0x1 + 16-bit instruction + 0x1 + + + B_0x2 + 24-bit instruction + 0x2 + + + B_0x3 + 32-bit instruction + 0x3 + + + + + ADMODE + Address mode +This field defines the address phase mode of operation. +101-111: Reserved + 8 + 3 + read-write + + + B_0x0 + No address + 0x0 + + + B_0x1 + Address on a single line + 0x1 + + + B_0x2 + Address on two lines + 0x2 + + + B_0x3 + Address on four lines + 0x3 + + + B_0x4 + Address on eight lines + 0x4 + + + + + ADDTR + Address double transfer rate +This bit sets the DTR mode for the address phase. + 11 + 1 + read-write + + + B_0x0 + DTR mode disabled for address phase + 0x0 + + + B_0x1 + DTR mode enabled for address phase + 0x1 + + + + + ADSIZE + Address size +This field defines address size. + 12 + 2 + read-write + + + B_0x0 + 8-bit address + 0x0 + + + B_0x1 + 16-bit address + 0x1 + + + B_0x2 + 24-bit address + 0x2 + + + B_0x3 + 32-bit address + 0x3 + + + + + ABMODE + Alternate-byte mode +This field defines the alternate-byte phase mode of operation. +101-111: Reserved + 16 + 3 + read-write + + + B_0x0 + No alternate bytes + 0x0 + + + B_0x1 + Alternate bytes on a single line + 0x1 + + + B_0x2 + Alternate bytes on two lines + 0x2 + + + B_0x3 + Alternate bytes on four lines + 0x3 + + + B_0x4 + Alternate bytes on eight lines + 0x4 + + + + + ABDTR + Alternate bytes double-transfer rate +This bit sets the DTR mode for the alternate-bytes phase. + 19 + 1 + read-write + + + B_0x0 + DTR mode disabled for alternate-bytes phase + 0x0 + + + B_0x1 + DTR mode enabled for alternate-bytes phase + 0x1 + + + + + ABSIZE + Alternate bytes size +This field defines alternate bytes size: + 20 + 2 + read-write + + + B_0x0 + 8-bit alternate bytes + 0x0 + + + B_0x1 + 16-bit alternate bytes + 0x1 + + + B_0x2 + 24-bit alternate bytes + 0x2 + + + B_0x3 + 32-bit alternate bytes + 0x3 + + + + + DMODE + Data mode +This field defines the data phase mode of operation. + 24 + 3 + read-write + + + B_0x0 + No data + 0x0 + + + B_0x1 + Data on a single line + 0x1 + + + B_0x2 + Data on two lines + 0x2 + + + B_0x3 + Data on four lines + 0x3 + + + B_0x4 + Data on eight lines + 0x4 + + + B_0x5 + Data on 16 lines + 0x5 + + + + + DDTR + data double transfer rate +This bit sets the DTR mode for the data phase. + 27 + 1 + read-write + + + B_0x0 + DTR mode disabled for data phase + 0x0 + + + B_0x1 + DTR mode enabled for data phase + 0x1 + + + + + DQSE + DQS enable +This bit enables the data strobe management. + 29 + 1 + read-write + + + B_0x0 + DQS disabled + 0x0 + + + B_0x1 + DQS enabled + 0x1 + + + + + + + HSPI_WTCR + HSPI_WTCR + HSPI write timing configuration register + 0x188 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DCYC + Number of dummy cycles +This field defines the duration of the dummy phase. +In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended to have at least 5 dummy cycles when using memories with DQS activated. + 0 + 5 + read-write + + + + + HSPI_WIR + HSPI_WIR + HSPI write instruction register + 0x190 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + INSTRUCTION + Instruction +Instruction to be sent to the external SPI device + 0 + 32 + read-write + + + + + HSPI_WABR + HSPI_WABR + HSPI write alternate bytes register + 0x1a0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ALTERNATE + [31: 0]: Alternate bytes +Optional data to be sent to the external SPI device right after the address + 0 + 32 + read-write + + + + + HSPI_HLCR + HSPI_HLCR + HSPI HyperBus latency configuration register + 0x200 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LM + Latency mode +This bit selects the Latency mode. + 0 + 1 + read-write + + + B_0x0 + Variable initial latency + 0x0 + + + B_0x1 + Fixed latency + 0x1 + + + + + WZL + Write zero latency +This bit enables zero latency on write operations. + 1 + 1 + read-write + + + B_0x0 + Latency on write accesses + 0x0 + + + B_0x1 + No latency on write accesses + 0x1 + + + + + TACC + [7: 0]: Access time +Device access time expressed in number of communication clock cycles + 8 + 8 + read-write + + + TRWR + Read write recovery time +Device read write recovery time expressed in number of communication clock cycles + 16 + 8 + read-write + + + + + HSPI_CALFCR + HSPI_CALFCR + HSPI full-cycle calibration configuration + 0x210 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FINE + [6: 0]: Fine calibration +The unitary value of delay for this field depends on product technology (refer to the product datasheet). + 0 + 7 + read-only + + + COARSE + [4: 0]: Coarse calibration +The unitary value of delay for this field depends on product technology (refer to the product datasheet). + 16 + 5 + read-only + + + CALMAX + Max value +This bit gets set when the memory-clock period is outside the range of DLLM, in which case HSPI_CALFCR and HSPI_CALSR are updated with the values for the maximum delay. + 31 + 1 + read-only + + + + + HSPI_CALMR + HSPI_CALMR + HSPI DLL master calibration configuration + 0x218 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FINE + [6: 0]: Fine calibration +The unitary value of delay for this field depends on product technology (refer to the product datasheet). + 0 + 7 + read-write + + + COARSE + [4: 0]: Coarse calibration +The unitary value of delay for this field depends on product technology (refer to the product datasheet). + 16 + 5 + read-write + + + + + HSPI_CALSOR + HSPI_CALSOR + HSPI DLL slave output calibration configuration + 0x220 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FINE + [6: 0]: Fine calibration +The unitary value of delay for this field depends on product technology (refer to the product datasheet). + 0 + 7 + read-write + + + COARSE + [4: 0]: Coarse calibration +The unitary value of delay for this field depends on product technology (refer to the product datasheet). + 16 + 5 + read-write + + + + + HSPI_CALSIR + HSPI_CALSIR + HSPI DLL slave input calibration configuration + 0x228 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FINE + [6: 0]: Fine calibration +The unitary value of delay for this field depends on product technology (refer to the product datasheet). + 0 + 7 + read-write + + + COARSE + [4: 0]: Coarse calibration +The unitary value of delay for this field depends on product technology (refer to the product datasheet). + 16 + 5 + read-write + + + + + + + SEC_HSPI1 + DCB->DSCSR->CDS == 0 + 0x520D3400 + + + I2C1 + Inter-integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1_EV + I2C1 event interrupt + 055 + + + I2C1_ER + I2C1 error interrupt + 056 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + PE + Peripheral enable + 0 + 1 + + + TXIE + TX Interrupt enable + 1 + 1 + + + RXIE + RX Interrupt enable + 2 + 1 + + + ADDRIE + Address match interrupt enable (slave + only) + 3 + 1 + + + NACKIE + Not acknowledge received interrupt + enable + 4 + 1 + + + STOPIE + STOP detection Interrupt + enable + 5 + 1 + + + TCIE + Transfer Complete interrupt + enable + 6 + 1 + + + ERRIE + Error interrupts enable + 7 + 1 + + + DNF + Digital noise filter + 8 + 4 + + + ANFOFF + Analog noise filter OFF + 12 + 1 + + + TXDMAEN + DMA transmission requests + enable + 14 + 1 + + + RXDMAEN + DMA reception requests + enable + 15 + 1 + + + SBC + Slave byte control + 16 + 1 + + + NOSTRETCH + Clock stretching disable + 17 + 1 + + + WUPEN + Wakeup from STOP enable + 18 + 1 + + + GCEN + General call enable + 19 + 1 + + + SMBHEN + SMBus Host address enable + 20 + 1 + + + SMBDEN + SMBus Device Default address + enable + 21 + 1 + + + ALERTEN + SMBUS alert enable + 22 + 1 + + + PECEN + PEC enable + 23 + 1 + + + FMP + Fast-mode Plus 20 mA drive enable + 24 + 1 + + + ADDRACLR + Address match flag (ADDR) automatic clear + 30 + 1 + + + STOPFACLR + STOP detection flag (STOPF) automatic clear + 31 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + PECBYTE + Packet error checking byte + 26 + 1 + + + AUTOEND + Automatic end mode (master + mode) + 25 + 1 + + + RELOAD + NBYTES reload mode + 24 + 1 + + + NBYTES + Number of bytes + 16 + 8 + + + NACK + NACK generation (slave + mode) + 15 + 1 + + + STOP + Stop generation (master + mode) + 14 + 1 + + + START + Start generation + 13 + 1 + + + HEAD10R + 10-bit address header only read + direction (master receiver mode) + 12 + 1 + + + ADD10 + 10-bit addressing mode (master + mode) + 11 + 1 + + + RD_WRN + Transfer direction (master + mode) + 10 + 1 + + + SADD + Slave address bit (master + mode) + 0 + 10 + + + + + OAR1 + OAR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x00000000 + + + OA1 + Interface address + 0 + 10 + + + OA1MODE + Own Address 1 10-bit mode + 10 + 1 + + + OA1EN + Own Address 1 enable + 15 + 1 + + + + + OAR2 + OAR2 + Own address register 2 + 0xC + 0x20 + read-write + 0x00000000 + + + OA2 + Interface address + 1 + 7 + + + OA2MSK + Own Address 2 masks + 8 + 3 + + + OA2EN + Own Address 2 enable + 15 + 1 + + + + + TIMINGR + TIMINGR + Timing register + 0x10 + 0x20 + read-write + 0x00000000 + + + SCLL + SCL low period (master + mode) + 0 + 8 + + + SCLH + SCL high period (master + mode) + 8 + 8 + + + SDADEL + Data hold time + 16 + 4 + + + SCLDEL + Data setup time + 20 + 4 + + + PRESC + Timing prescaler + 28 + 4 + + + + + TIMEOUTR + TIMEOUTR + Status register 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + TIMEOUTA + Bus timeout A + 0 + 12 + + + TIDLE + Idle clock timeout + detection + 12 + 1 + + + TIMOUTEN + Clock timeout enable + 15 + 1 + + + TIMEOUTB + Bus timeout B + 16 + 12 + + + TEXTEN + Extended clock timeout + enable + 31 + 1 + + + + + ISR + ISR + Interrupt and Status register + 0x18 + 0x20 + 0x00000001 + + + ADDCODE + Address match code (Slave + mode) + 17 + 7 + read-only + + + DIR + Transfer direction (Slave + mode) + 16 + 1 + read-only + + + BUSY + Bus busy + 15 + 1 + read-only + + + ALERT + SMBus alert + 13 + 1 + read-only + + + TIMEOUT + Timeout or t_low detection + flag + 12 + 1 + read-only + + + PECERR + PEC Error in reception + 11 + 1 + read-only + + + OVR + Overrun/Underrun (slave + mode) + 10 + 1 + read-only + + + ARLO + Arbitration lost + 9 + 1 + read-only + + + BERR + Bus error + 8 + 1 + read-only + + + TCR + Transfer Complete Reload + 7 + 1 + read-only + + + TC + Transfer Complete (master + mode) + 6 + 1 + read-only + + + STOPF + Stop detection flag + 5 + 1 + read-only + + + NACKF + Not acknowledge received + flag + 4 + 1 + read-only + + + ADDR + Address matched (slave + mode) + 3 + 1 + read-only + + + RXNE + Receive data register not empty + (receivers) + 2 + 1 + read-only + + + TXIS + Transmit interrupt status + (transmitters) + 1 + 1 + read-write + + + TXE + Transmit data register empty + (transmitters) + 0 + 1 + read-write + + + + + ICR + ICR + Interrupt clear register + 0x1C + 0x20 + write-only + 0x00000000 + + + ALERTCF + Alert flag clear + 13 + 1 + + + TIMOUTCF + Timeout detection flag + clear + 12 + 1 + + + PECCF + PEC Error flag clear + 11 + 1 + + + OVRCF + Overrun/Underrun flag + clear + 10 + 1 + + + ARLOCF + Arbitration lost flag + clear + 9 + 1 + + + BERRCF + Bus error flag clear + 8 + 1 + + + STOPCF + Stop detection flag clear + 5 + 1 + + + NACKCF + Not Acknowledge flag clear + 4 + 1 + + + ADDRCF + Address Matched flag clear + 3 + 1 + + + + + PECR + PECR + PEC register + 0x20 + 0x20 + read-only + 0x00000000 + + + PEC + Packet error checking + register + 0 + 8 + + + + + RXDR + RXDR + Receive data register + 0x24 + 0x20 + read-only + 0x00000000 + + + RXDATA + 8-bit receive data + 0 + 8 + + + + + TXDR + TXDR + Transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + + + TXDATA + 8-bit transmit data + 0 + 8 + + + + + I2C_AUTOCR + I2C_AUTOCR + I2C Autonomous mode control register + 0x2C + 0x20 + read-write + 0x00000000 + + + TCDMAEN + DMA request enable on Transfer Complete event + 6 + 1 + + + TCRDMAEN + DMA request enable on Transfer Complete Reload event + 7 + 1 + + + TRIGSEL + Trigger selection + 16 + 4 + + + TRIGPOL + Trigger polarity + 20 + 1 + + + TRIGEN + Trigger enable + 21 + 1 + + + + + + + SEC_I2C1 + DCB->DSCSR->CDS == 0 + 0x50005400 + + + I2C2 + 0x40005800 + + I2C2_EV + I2C2 event interrupt + 057 + + + I2C2_ER + I2C2 error interrupt + 058 + + + + SEC_I2C2 + DCB->DSCSR->CDS == 0 + 0x50005800 + + + I2C3 + 0x46002800 + + I2C3_EV + I2C3 event interrupt + 088 + + + I2C3_ER + I2C3 error interrupt + 089 + + + + SEC_I2C3 + DCB->DSCSR->CDS == 0 + 0x56002800 + + + I2C4 + 0x40008400 + + I2C4_ER + I2C4 error interrupt + 100 + + + I2C4_EV + I2C4 event interrupt + 101 + + + + SEC_I2C4 + DCB->DSCSR->CDS == 0 + 0x50008400 + + + I2C5 + 0x40009800 + + I2C5_ER + I2C5 error interrupt + 127 + + + I2C5_EV + I2C5 event interrupt + 128 + + + + SEC_I2C5 + DCB->DSCSR->CDS == 0 + 0x50009800 + + + I2C6 + 0x40009C00 + + I2C6_ER + I2C6 error interrupt + 129 + + + I2C6_EV + I2C6 event interrupt + 130 + + + + SEC_I2C6 + DCB->DSCSR->CDS == 0 + 0x50009C00 + + + ICache + ICache + ICache + 0x40030400 + + 0x0 + 0x400 + registers + + + ICACHE + Instruction cache global interrupt + 107 + + + + ICACHE_CR + ICACHE_CR + ICACHE control register + 0x0 + 0x20 + 0x00000004 + + + EN + EN + 0 + 1 + read-write + + + CACHEINV + CACHEINV + 1 + 1 + write-only + + + WAYSEL + WAYSEL + 2 + 1 + read-write + + + HITMEN + HITMEN + 16 + 1 + read-write + + + MISSMEN + MISSMEN + 17 + 1 + read-write + + + HITMRST + HITMRST + 18 + 1 + read-write + + + MISSMRST + MISSMRST + 19 + 1 + read-write + + + + + ICACHE_SR + ICACHE_SR + ICACHE status register + 0x4 + 0x20 + read-only + 0x00000001 + + + BUSYF + BUSYF + 0 + 1 + + + BSYENDF + BSYENDF + 1 + 1 + + + ERRF + ERRF + 2 + 1 + + + + + ICACHE_IER + ICACHE_IER + ICACHE interrupt enable + register + 0x8 + 0x20 + read-write + 0x00000000 + + + BSYENDIE + BSYENDIE + 1 + 1 + + + ERRIE + ERRIE + 2 + 1 + + + + + ICACHE_FCR + ICACHE_FCR + ICACHE flag clear register + 0xC + 0x20 + write-only + 0x00000000 + + + CBSYENDF + CBSYENDF + 1 + 1 + + + CERRF + CERRF + 2 + 1 + + + + + ICACHE_HMONR + ICACHE_HMONR + ICACHE hit monitor register + 0x10 + 0x20 + read-only + 0x00000000 + + + HITMON + HITMON + 0 + 32 + + + + + ICACHE_MMONR + ICACHE_MMONR + ICACHE miss monitor register + 0x14 + 0x20 + read-only + 0x00000000 + + + MISSMON + MISSMON + 0 + 16 + + + + + ICACHE_CRR0 + ICACHE_CRR0 + ICACHE region configuration + register + 0x20 + 0x20 + read-write + 0x00000200 + + + BASEADDR + BASEADDR + 0 + 8 + + + RSIZE + RSIZE + 9 + 3 + + + REN + REN + 15 + 1 + + + REMAPADDR + REMAPADDR + 16 + 11 + + + MSTSEL + MSTSEL + 28 + 1 + + + HBURST + HBURST + 31 + 1 + + + + + ICACHE_CRR1 + ICACHE_CRR1 + ICACHE region configuration + register + 0x24 + 0x20 + read-write + 0x00000200 + + + BASEADDR + BASEADDR + 0 + 8 + + + RSIZE + RSIZE + 9 + 3 + + + REN + REN + 15 + 1 + + + REMAPADDR + REMAPADDR + 16 + 11 + + + MSTSEL + MSTSEL + 28 + 1 + + + HBURST + HBURST + 31 + 1 + + + + + ICACHE_CRR2 + ICACHE_CRR2 + ICACHE region configuration + register + 0x28 + 0x20 + read-write + 0x00000200 + + + BASEADDR + BASEADDR + 0 + 8 + + + RSIZE + RSIZE + 9 + 3 + + + REN + REN + 15 + 1 + + + REMAPADDR + REMAPADDR + 16 + 11 + + + MSTSEL + MSTSEL + 28 + 1 + + + HBURST + HBURST + 31 + 1 + + + + + ICACHE_CRR3 + ICACHE_CRR3 + ICACHE region configuration + register + 0x2C + 0x20 + read-write + 0x00000200 + + + BASEADDR + BASEADDR + 0 + 8 + + + RSIZE + RSIZE + 9 + 3 + + + REN + REN + 15 + 1 + + + REMAPADDR + REMAPADDR + 16 + 11 + + + MSTSEL + MSTSEL + 28 + 1 + + + HBURST + HBURST + 31 + 1 + + + + + + + SEC_ICache + DCB->DSCSR->CDS == 0 + 0x50030400 + + + IWDG + Independent watchdog + IWDG + 0x40003000 + + 0x0 + 0x400 + registers + + + IWDG + Independent watchdog interrupt + 27 + + + + KR + KR + Key register + 0x0 + 0x20 + write-only + 0x00000000 + + + KEY + Key value (write only, read + 0x0000) + 0 + 16 + + + + + PR + PR + Prescaler register + 0x4 + 0x20 + read-write + 0x00000000 + + + PR + Prescaler divider + 0 + 4 + + + + + RLR + RLR + Reload register + 0x8 + 0x20 + read-write + 0x00000FFF + + + RL + Watchdog counter reload + value + 0 + 12 + + + + + SR + SR + Status register + 0xC + 0x20 + read-only + 0x00000000 + + + EWIF + Watchdog Early interrupt flag + 14 + 1 + + + EWU + Watchdog interrupt comparator value update + 3 + 1 + + + WVU + Watchdog counter window value + update + 2 + 1 + + + RVU + Watchdog counter reload value + update + 1 + 1 + + + PVU + Watchdog prescaler value + update + 0 + 1 + + + + + WINR + WINR + Window register + 0x10 + 0x20 + read-write + 0x00000FFF + + + WIN + Watchdog counter window + value + 0 + 12 + + + + + EWCR + EWCR + IWDG early wakeup interrupt register + 0x14 + 0x20 + read-write + 0x00000000 + + + EWIT + Watchdog counter window value + 0 + 12 + + + EWIC + Watchdog early interrupt acknowledge + 14 + 1 + + + EWIE + Watchdog early interrupt enable + 15 + 1 + + + + + + + SEC_IWDG + DCB->DSCSR->CDS == 0 + 0x50003000 + + + LPDMA1 + LPDMA1 + LPDMA + 0x46025000 + + 0x0 + 0x1000 + registers + + + LPDMA1_CH0 + LPDMA1 SmartRun channel 0 global interrupt + 114 + + + LPDMA1_CH1 + LPDMA1 SmartRun channel 1 global interrupt + 115 + + + LPDMA1_CH2 + LPDMA1 SmartRun channel 2 global interrupt + 116 + + + LPDMA1_CH3 + LPDMA1 SmartRun channel 3 global interrupt + 117 + + + + LPDMA_SECCFGR + LPDMA_SECCFGR + LPDMA secure configuration register + 0x0 + 0x20 + read-write + 0x00000000 + + + SEC0 + SEC0 + 0 + 1 + + + SEC1 + SEC1 + 1 + 1 + + + SEC2 + SEC2 + 2 + 1 + + + SEC3 + SEC3 + 3 + 1 + + + + + LPDMA_PRIVCFGR + LPDMA_PRIVCFGR + LPDMA privileged configuration register + 0x4 + 0x20 + read-write + 0x00000000 + + + PRIV0 + PRIV0 + 0 + 1 + + + PRIV1 + PRIV1 + 1 + 1 + + + PRIV2 + PRIV2 + 2 + 1 + + + PRIV3 + PRIV3 + 3 + 1 + + + + + MISR + MISR + LPDMA non-secure masked interrupt status register + 0xC + 0x20 + read-only + 0x00000000 + + + MIS0 + MIS0 + 0 + 1 + + + MIS1 + MIS1 + 1 + 1 + + + MIS2 + MIS2 + 2 + 1 + + + MIS3 + MIS3 + 3 + 1 + + + + + SMISR + SMISR + LPDMA secure masked interrupt status register + 0x10 + 0x20 + read-only + 0x00000000 + + + MIS0 + MIS0 + 0 + 1 + + + MIS1 + MIS1 + 1 + 1 + + + MIS2 + MIS2 + 2 + 1 + + + MIS3 + MIS3 + 3 + 1 + + + + + LPDMA_C0LBAR + LPDMA_C0LBAR + channel x linked-list base address register + 0x50 + 0x20 + read-write + 0x00000000 + + + LBA + linked-list base address of DMA channel x + 16 + 16 + + + + + LPDMA_C0FCR + LPDMA_C0FCR + LPDMA channel x flag clear register + 0x5C + 0x20 + write-only + 0x00000000 + + + TCF + transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag + 8 + 1 + + + HTF + half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag + 9 + 1 + + + DTEF + data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag + 10 + 1 + + + ULEF + update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag + 11 + 1 + + + USEF + user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag + 12 + 1 + + + SUSPF + completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag + 13 + 1 + + + + + LPDMA_C0SR + LPDMA_C0SR + channel x status register + 0x60 + 0x20 + read-only + 0x00000001 + + + IDLEF + idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state). + 0 + 1 + + + TCF + transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. LPDMA_CxTR2.TCEM[1:0]. + 8 + 1 + + + HTF + half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. LPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of LPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (LPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination. + 9 + 1 + + + DTEF + data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer + 10 + 1 + + + ULEF + update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory + 11 + 1 + + + USEF + user setting error flag - 0: no user setting error event - 1: a user setting error event occurred + 12 + 1 + + + SUSPF + completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred + 13 + 1 + + + + + LPDMA_C0CR + LPDMA_C0CR + channel x control register + 0x64 + 0x20 + read-write + 0x00000000 + + + EN + enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. + 0 + 1 + + + RESET + reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. LPDMA_CxSR.SUSPF=1 and LPDMA_CxSR.IDLEF=1 and LPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. LPDMA_CxSR.IDLEF=1 and LPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers LPDMA_CxBR1, LPDMA_CxSAR and LPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence. + 1 + 1 + + + SUSP + suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence. + 2 + 1 + + + TCIE + transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 8 + 1 + + + HTIE + half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 9 + 1 + + + DTEIE + data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 10 + 1 + + + ULEIE + update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 11 + 1 + + + USEIE + user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 12 + 1 + + + SUSPIE + completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 13 + 1 + + + LSM + Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then LPDMA_CxBR1.BRC[10:0]=0 and LPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (LPDMA_CxBR1.BRC[10:0]=0 and LPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by LPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1. + 16 + 1 + + + PRIO + priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 22 + 2 + + + + + LPDMA_C0TR1 + LPDMA_C0TR1 + LPDMA channel x transfer register 1 + 0x90 + 0x20 + read-write + 0x00000000 + + + SDW_LOG2 + binary logarithm of the source data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: a source block size must be a multiple of the source data width (c.f. LPDMA_CxBR1.BNDT[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: A source burst transfer must have an aligned address with its data width (c.f. start address LPDMA_CxSAR[2:0] and address offset LPDMA_CxTR3.SAO[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. + 0 + 2 + + + SINC + source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address, pointed by DMA_CxSAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. + 3 + 1 + + + PAM + PAM + 11 + 2 + + + SSEC + security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when LPDMA_SECCFGR.SECx=0.When is de-asserted LPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer from the source is non-secure.If LPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure + 15 + 1 + + + DDW_LOG2 + binary logarithm of the destination data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: A destination burst transfer must have an aligned address with its data width (c.f. start address LPDMA_CxDAR[2:0] and address offset LPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: When configured in packing mode (i.e. if PAM[1]=1 and destination data width different from source data width), a source block size must be a multiple of the destination data width (c.f. LPDMA_CxBR1.BNDT[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. + 16 + 2 + + + DINC + destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address, pointed by DMA_CxDAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. + 19 + 1 + + + DSEC + security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when LPDMA_SECCFGR.SECx=0.When is de-asserted LPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer to the destination is non-secure.If LPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure + 31 + 1 + + + + + LPDMA_C0TR2 + LPDMA_C0TR2 + LPDMA channel x transfer register 2 + 0x94 + 0x20 + read-write + 0x00000000 + + + REQSEL + DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if LPDMA_CxCR.EN=1 and LPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting. + 0 + 5 + + + SWREQ + Software request When LPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored. + 9 + 1 + + + BREQ + BREQ + 11 + 1 + + + TRIGM + Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when LPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11, these bits are ignored. Else, a DMA transfer is conditioned by (at least) one trigger hit, either at: - 00: at block level (for channel x=12 to 15: for each block if a 2D/repeated block is configured i.e. if LPDMA_CxBR1.BRC[10:0]! = 0): the first burst read of a/each block transfer is conditioned by one hit trigger. - 01: at 2D/repeated block level for channel x=12 to 15; same as 00 for channel x=0 to 11 + 14 + 2 + + + TRIGSEL + Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00. + 16 + 5 + + + TRIGPOL + Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00 + 24 + 2 + + + TCEM + Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when LPDMA_CxBR1.BRC[10:0]= 0 and LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address LPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the LPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated. + 30 + 2 + + + + + LPDMA_C0BR1 + LPDMA_C0BR1 + LPDMA channel x block register 1 + 0x98 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data bytes to transfer from the source + 0 + 16 + + + + + LPDMA_C0SAR + LPDMA_C0SAR + LPDMA channel x source address register + 0x9C + 0x20 + read-write + 0x00000000 + + + SA + source address + 0 + 32 + + + + + LPDMA_C0DAR + LPDMA_C0DAR + LPDMA channel x destination address register + 0xA0 + 0x20 + read-write + 0x00000000 + + + DA + destination address + 0 + 32 + + + + + LPDMA_C0LLR + LPDMA_C0LLR + LPDMA channel x linked-list address register + 0xCC + 0x20 + read-write + 0x00000000 + + + LA + pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly LPDMA_CxCTR1, LPDMA_CxTR2, LPDMA_CxBR1, LPDMA_CxSAR, LPDMA_CxDAR and LPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored. + 2 + 14 + + + ULL + Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update + 16 + 1 + + + UDA + Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update + 27 + 1 + + + USA + Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update + 28 + 1 + + + UB1 + Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0, the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no LPDMA_CxBR1 update (LPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: LPDMA_CxBR1 update + 29 + 1 + + + UT2 + Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update + 30 + 1 + + + UT1 + Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update + 31 + 1 + + + + + LPDMA_C1LBAR + LPDMA_C1LBAR + channel x linked-list base address register + 0xD0 + 0x20 + read-write + 0x00000000 + + + LBA + linked-list base address of DMA channel x + 16 + 16 + + + + + LPDMA_C1FCR + LPDMA_C1FCR + LPDMA channel x flag clear register + 0xDC + 0x20 + write-only + 0x00000000 + + + TCF + transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag + 8 + 1 + + + HTF + half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag + 9 + 1 + + + DTEF + data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag + 10 + 1 + + + ULEF + update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag + 11 + 1 + + + USEF + user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag + 12 + 1 + + + SUSPF + completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag + 13 + 1 + + + + + LPDMA_C1SR + LPDMA_C1SR + channel x status register + 0xE0 + 0x20 + read-only + 0x00000001 + + + IDLEF + idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state). + 0 + 1 + + + TCF + transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. LPDMA_CxTR2.TCEM[1:0]. + 8 + 1 + + + HTF + half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. LPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of LPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (LPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination. + 9 + 1 + + + DTEF + data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer + 10 + 1 + + + ULEF + update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory + 11 + 1 + + + USEF + user setting error flag - 0: no user setting error event - 1: a user setting error event occurred + 12 + 1 + + + SUSPF + completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred + 13 + 1 + + + + + LPDMA_C1CR + LPDMA_C1CR + channel x control register + 0xE4 + 0x20 + read-write + 0x00000000 + + + EN + enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. + 0 + 1 + + + RESET + reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. LPDMA_CxSR.SUSPF=1 and LPDMA_CxSR.IDLEF=1 and LPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. LPDMA_CxSR.IDLEF=1 and LPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers LPDMA_CxBR1, LPDMA_CxSAR and LPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence. + 1 + 1 + + + SUSP + suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence. + 2 + 1 + + + TCIE + transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 8 + 1 + + + HTIE + half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 9 + 1 + + + DTEIE + data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 10 + 1 + + + ULEIE + update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 11 + 1 + + + USEIE + user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 12 + 1 + + + SUSPIE + completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 13 + 1 + + + LSM + Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then LPDMA_CxBR1.BRC[10:0]=0 and LPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (LPDMA_CxBR1.BRC[10:0]=0 and LPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by LPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1. + 16 + 1 + + + PRIO + priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 22 + 2 + + + + + LPDMA_C1TR1 + LPDMA_C1TR1 + LPDMA channel x transfer register 1 + 0x110 + 0x20 + read-write + 0x00000000 + + + SDW_LOG2 + binary logarithm of the source data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: a source block size must be a multiple of the source data width (c.f. LPDMA_CxBR1.BNDT[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: A source burst transfer must have an aligned address with its data width (c.f. start address LPDMA_CxSAR[2:0] and address offset LPDMA_CxTR3.SAO[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. + 0 + 2 + + + SINC + source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address, pointed by DMA_CxSAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. + 3 + 1 + + + PAM + PAM + 11 + 2 + + + SSEC + security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when LPDMA_SECCFGR.SECx=0.When is de-asserted LPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer from the source is non-secure.If LPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure + 15 + 1 + + + DDW_LOG2 + binary logarithm of the destination data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: A destination burst transfer must have an aligned address with its data width (c.f. start address LPDMA_CxDAR[2:0] and address offset LPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: When configured in packing mode (i.e. if PAM[1]=1 and destination data width different from source data width), a source block size must be a multiple of the destination data width (c.f. LPDMA_CxBR1.BNDT[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. + 16 + 2 + + + DINC + destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address, pointed by DMA_CxDAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. + 19 + 1 + + + DSEC + security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when LPDMA_SECCFGR.SECx=0.When is de-asserted LPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer to the destination is non-secure.If LPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure + 31 + 1 + + + + + LPDMA_C1TR2 + LPDMA_C1TR2 + LPDMA channel x transfer register 2 + 0x114 + 0x20 + read-write + 0x00000000 + + + REQSEL + DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if LPDMA_CxCR.EN=1 and LPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting. + 0 + 5 + + + SWREQ + Software request When LPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored. + 9 + 1 + + + BREQ + BREQ + 11 + 1 + + + TRIGM + Trigger mode + 14 + 2 + + + TRIGSEL + Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00. + 16 + 5 + + + TRIGPOL + Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00 + 24 + 2 + + + TCEM + Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when LPDMA_CxBR1.BRC[10:0]= 0 and LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address LPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the LPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated. + 30 + 2 + + + + + LPDMA_C1BR1 + LPDMA_C1BR1 + LPDMA channel x block register 1 + 0x118 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data bytes to transfer from the source + 0 + 16 + + + + + LPDMA_C1SAR + LPDMA_C1SAR + LPDMA channel x source address register + 0x11C + 0x20 + read-write + 0x00000000 + + + SA + source address + 0 + 32 + + + + + LPDMA_C1DAR + LPDMA_C1DAR + LPDMA channel x destination address register + 0x120 + 0x20 + read-write + 0x00000000 + + + DA + destination address + 0 + 32 + + + + + LPDMA_C1LLR + LPDMA_C1LLR + LPDMA channel x linked-list address register + 0x14C + 0x20 + read-write + 0x00000000 + + + LA + pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly LPDMA_CxCTR1, LPDMA_CxTR2, LPDMA_CxBR1, LPDMA_CxSAR, LPDMA_CxDAR and LPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored. + 2 + 14 + + + ULL + Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update + 16 + 1 + + + UDA + Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update + 27 + 1 + + + USA + Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update + 28 + 1 + + + UB1 + Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0, the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no LPDMA_CxBR1 update (LPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: LPDMA_CxBR1 update + 29 + 1 + + + UT2 + Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update + 30 + 1 + + + UT1 + Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update + 31 + 1 + + + + + LPDMA_C2LBAR + LPDMA_C2LBAR + channel x linked-list base address register + 0x150 + 0x20 + read-write + 0x00000000 + + + LBA + linked-list base address of DMA channel x + 16 + 16 + + + + + LPDMA_C2FCR + LPDMA_C2FCR + LPDMA channel x flag clear register + 0x15C + 0x20 + write-only + 0x00000000 + + + TCF + transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag + 8 + 1 + + + HTF + half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag + 9 + 1 + + + DTEF + data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag + 10 + 1 + + + ULEF + update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag + 11 + 1 + + + USEF + user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag + 12 + 1 + + + SUSPF + completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag + 13 + 1 + + + + + LPDMA_C2SR + LPDMA_C2SR + channel x status register + 0x160 + 0x20 + read-only + 0x00000001 + + + IDLEF + idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state). + 0 + 1 + + + TCF + transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. LPDMA_CxTR2.TCEM[1:0]. + 8 + 1 + + + HTF + half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. LPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of LPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (LPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination. + 9 + 1 + + + DTEF + data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer + 10 + 1 + + + ULEF + update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory + 11 + 1 + + + USEF + user setting error flag - 0: no user setting error event - 1: a user setting error event occurred + 12 + 1 + + + SUSPF + completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred + 13 + 1 + + + + + LPDMA_C2CR + LPDMA_C2CR + channel x control register + 0x164 + 0x20 + read-write + 0x00000000 + + + EN + enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. + 0 + 1 + + + RESET + reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. LPDMA_CxSR.SUSPF=1 and LPDMA_CxSR.IDLEF=1 and LPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. LPDMA_CxSR.IDLEF=1 and LPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers LPDMA_CxBR1, LPDMA_CxSAR and LPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence. + 1 + 1 + + + SUSP + suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence. + 2 + 1 + + + TCIE + transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 8 + 1 + + + HTIE + half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 9 + 1 + + + DTEIE + data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 10 + 1 + + + ULEIE + update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 11 + 1 + + + USEIE + user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 12 + 1 + + + SUSPIE + completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 13 + 1 + + + LSM + Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then LPDMA_CxBR1.BRC[10:0]=0 and LPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (LPDMA_CxBR1.BRC[10:0]=0 and LPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by LPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1. + 16 + 1 + + + PRIO + priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 22 + 2 + + + + + LPDMA_C2TR1 + LPDMA_C2TR1 + LPDMA channel x transfer register 1 + 0x190 + 0x20 + read-write + 0x00000000 + + + SDW_LOG2 + binary logarithm of the source data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: a source block size must be a multiple of the source data width (c.f. LPDMA_CxBR1.BNDT[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: A source burst transfer must have an aligned address with its data width (c.f. start address LPDMA_CxSAR[2:0] and address offset LPDMA_CxTR3.SAO[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. + 0 + 2 + + + SINC + source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address, pointed by DMA_CxSAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. + 3 + 1 + + + PAM + PAM + 11 + 2 + + + SSEC + security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when LPDMA_SECCFGR.SECx=0.When is de-asserted LPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer from the source is non-secure.If LPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure + 15 + 1 + + + DDW_LOG2 + binary logarithm of the destination data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: A destination burst transfer must have an aligned address with its data width (c.f. start address LPDMA_CxDAR[2:0] and address offset LPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: When configured in packing mode (i.e. if PAM[1]=1 and destination data width different from source data width), a source block size must be a multiple of the destination data width (c.f. LPDMA_CxBR1.BNDT[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. + 16 + 2 + + + DINC + destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address, pointed by DMA_CxDAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. + 19 + 1 + + + DSEC + security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when LPDMA_SECCFGR.SECx=0.When is de-asserted LPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer to the destination is non-secure.If LPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure + 31 + 1 + + + + + LPDMA_C2TR2 + LPDMA_C2TR2 + LPDMA channel x transfer register 2 + 0x194 + 0x20 + read-write + 0x00000000 + + + REQSEL + DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if LPDMA_CxCR.EN=1 and LPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting. + 0 + 5 + + + SWREQ + Software request When LPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored. + 9 + 1 + + + BREQ + BREQ + 11 + 1 + + + TRIGM + Trigger mode + 14 + 2 + + + TRIGSEL + Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00. + 16 + 5 + + + TRIGPOL + Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00 + 24 + 2 + + + TCEM + Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when LPDMA_CxBR1.BRC[10:0]= 0 and LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address LPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the LPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated. + 30 + 2 + + + + + LPDMA_C2BR1 + LPDMA_C2BR1 + LPDMA channel x block register 1 + 0x198 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data bytes to transfer from the source + 0 + 16 + + + + + LPDMA_C2SAR + LPDMA_C2SAR + LPDMA channel x source address register + 0x19C + 0x20 + read-write + 0x00000000 + + + SA + source address + 0 + 32 + + + + + LPDMA_C2DAR + LPDMA_C2DAR + LPDMA channel x destination address register + 0x1A0 + 0x20 + read-write + 0x00000000 + + + DA + destination address + 0 + 32 + + + + + LPDMA_C2LLR + LPDMA_C2LLR + LPDMA channel x linked-list address register + 0x1CC + 0x20 + read-write + 0x00000000 + + + LA + pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly LPDMA_CxCTR1, LPDMA_CxTR2, LPDMA_CxBR1, LPDMA_CxSAR, LPDMA_CxDAR and LPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored. + 2 + 14 + + + ULL + Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update + 16 + 1 + + + UDA + Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update + 27 + 1 + + + USA + Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update + 28 + 1 + + + UB1 + Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0, the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no LPDMA_CxBR1 update (LPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: LPDMA_CxBR1 update + 29 + 1 + + + UT2 + Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update + 30 + 1 + + + UT1 + Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update + 31 + 1 + + + + + LPDMA_C3LBAR + LPDMA_C3LBAR + channel x linked-list base address register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + LBA + linked-list base address of DMA channel x + 16 + 16 + + + + + LPDMA_C3FCR + LPDMA_C3FCR + LPDMA channel x flag clear register + 0x1DC + 0x20 + write-only + 0x00000000 + + + TCF + transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag + 8 + 1 + + + HTF + half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag + 9 + 1 + + + DTEF + data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag + 10 + 1 + + + ULEF + update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag + 11 + 1 + + + USEF + user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag + 12 + 1 + + + SUSPF + completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag + 13 + 1 + + + + + LPDMA_C3SR + LPDMA_C3SR + channel x status register + 0x1E0 + 0x20 + read-only + 0x00000001 + + + IDLEF + idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state). + 0 + 1 + + + TCF + transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. LPDMA_CxTR2.TCEM[1:0]. + 8 + 1 + + + HTF + half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. LPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of LPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (LPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination. + 9 + 1 + + + DTEF + data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer + 10 + 1 + + + ULEF + update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory + 11 + 1 + + + USEF + user setting error flag - 0: no user setting error event - 1: a user setting error event occurred + 12 + 1 + + + SUSPF + completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred + 13 + 1 + + + + + LPDMA_C3CR + LPDMA_C3CR + channel x control register + 0x1E4 + 0x20 + read-write + 0x00000000 + + + EN + enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. + 0 + 1 + + + RESET + reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. LPDMA_CxSR.SUSPF=1 and LPDMA_CxSR.IDLEF=1 and LPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. LPDMA_CxSR.IDLEF=1 and LPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers LPDMA_CxBR1, LPDMA_CxSAR and LPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence. + 1 + 1 + + + SUSP + suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence. + 2 + 1 + + + TCIE + transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 8 + 1 + + + HTIE + half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 9 + 1 + + + DTEIE + data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 10 + 1 + + + ULEIE + update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 11 + 1 + + + USEIE + user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 12 + 1 + + + SUSPIE + completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled + 13 + 1 + + + LSM + Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then LPDMA_CxBR1.BRC[10:0]=0 and LPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (LPDMA_CxBR1.BRC[10:0]=0 and LPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by LPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1. + 16 + 1 + + + PRIO + priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1. + 22 + 2 + + + + + LPDMA_C3TR1 + LPDMA_C3TR1 + LPDMA channel x transfer register 1 + 0x210 + 0x20 + read-write + 0x00000000 + + + SDW_LOG2 + binary logarithm of the source data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: a source block size must be a multiple of the source data width (c.f. LPDMA_CxBR1.BNDT[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: A source burst transfer must have an aligned address with its data width (c.f. start address LPDMA_CxSAR[2:0] and address offset LPDMA_CxTR3.SAO[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. + 0 + 2 + + + SINC + source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address, pointed by DMA_CxSAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. + 3 + 1 + + + PAM + PAM + 11 + 2 + + + SSEC + security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when LPDMA_SECCFGR.SECx=0.When is de-asserted LPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer from the source is non-secure.If LPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure + 15 + 1 + + + DDW_LOG2 + binary logarithm of the destination data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: A destination burst transfer must have an aligned address with its data width (c.f. start address LPDMA_CxDAR[2:0] and address offset LPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: When configured in packing mode (i.e. if PAM[1]=1 and destination data width different from source data width), a source block size must be a multiple of the destination data width (c.f. LPDMA_CxBR1.BNDT[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. + 16 + 2 + + + DINC + destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address, pointed by DMA_CxDAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. + 19 + 1 + + + DSEC + security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when LPDMA_SECCFGR.SECx=0.When is de-asserted LPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer to the destination is non-secure.If LPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure + 31 + 1 + + + + + LPDMA_C3TR2 + LPDMA_C3TR2 + LPDMA channel x transfer register 2 + 0x214 + 0x20 + read-write + 0x00000000 + + + REQSEL + DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if LPDMA_CxCR.EN=1 and LPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting. + 0 + 5 + + + SWREQ + Software request When LPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored. + 9 + 1 + + + BREQ + BREQ + 11 + 1 + + + TRIGM + Trigger mode + 14 + 2 + + + TRIGSEL + Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00. + 16 + 5 + + + TRIGPOL + Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00 + 24 + 2 + + + TCEM + Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when LPDMA_CxBR1.BRC[10:0]= 0 and LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address LPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the LPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated. + 30 + 2 + + + + + LPDMA_C3BR1 + LPDMA_C3BR1 + LPDMA channel x block register 1 + 0x218 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data bytes to transfer from the source + 0 + 16 + + + + + LPDMA_C3SAR + LPDMA_C3SAR + LPDMA channel x source address register + 0x21C + 0x20 + read-write + 0x00000000 + + + SA + source address + 0 + 32 + + + + + LPDMA_C3DAR + LPDMA_C3DAR + LPDMA channel x destination address register + 0x220 + 0x20 + read-write + 0x00000000 + + + DA + destination address + 0 + 32 + + + + + LPDMA_C3LLR + LPDMA_C3LLR + LPDMA channel x linked-list address register + 0x24C + 0x20 + read-write + 0x00000000 + + + LA + pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly LPDMA_CxCTR1, LPDMA_CxTR2, LPDMA_CxBR1, LPDMA_CxSAR, LPDMA_CxDAR and LPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored. + 2 + 14 + + + ULL + Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update + 16 + 1 + + + UDA + Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update + 27 + 1 + + + USA + Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update + 28 + 1 + + + UB1 + Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0, the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no LPDMA_CxBR1 update (LPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: LPDMA_CxBR1 update + 29 + 1 + + + UT2 + Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update + 30 + 1 + + + UT1 + Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update + 31 + 1 + + + + + + + SEC_LPDMA1 + DCB->DSCSR->CDS == 0 + 0x56025000 + + + LPGPIO1 + LPGPIO1 + LPGPIO + 0x46020000 + + 0x0 + 0x400 + registers + + + + LPGPIO_MODER + LPGPIO_MODER + LPGPIO port mode register + 0x000 + 0x20 + read-write + 0x00000000 + + + MODE15 + MODE15 + 15 + 1 + + + MODE14 + MODE14 + 14 + 1 + + + MODE13 + MODE13 + 13 + 1 + + + MODE12 + MODE12 + 12 + 1 + + + MODE11 + MODE11 + 11 + 1 + + + MODE10 + MODE10 + 10 + 1 + + + MODE9 + MODE9 + 9 + 1 + + + MODE8 + MODE8 + 8 + 1 + + + MODE7 + MODE7 + 7 + 1 + + + MODE6 + MODE6 + 6 + 1 + + + MODE5 + MODE5 + 5 + 1 + + + MODE4 + MODE4 + 4 + 1 + + + MODE3 + MODE3 + 3 + 1 + + + MODE2 + MODE2 + 2 + 1 + + + MODE1 + MODE1 + 1 + 1 + + + MODE0 + MODE0 + 0 + 1 + + + + + LPGPIO_IDR + LPGPIO_IDR + LPGPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + ID15 + ID15 + 15 + 1 + + + ID14 + ID14 + 14 + 1 + + + ID13 + ID13 + 13 + 1 + + + ID12 + ID12 + 12 + 1 + + + ID11 + ID11 + 11 + 1 + + + ID10 + ID10 + 10 + 1 + + + ID9 + ID9 + 9 + 1 + + + ID8 + ID8 + 8 + 1 + + + ID7 + ID7 + 7 + 1 + + + ID6 + ID6 + 6 + 1 + + + ID5 + ID5 + 5 + 1 + + + ID4 + ID4 + 4 + 1 + + + ID3 + ID3 + 3 + 1 + + + ID2 + ID2 + 2 + 1 + + + ID1 + ID1 + 1 + 1 + + + ID0 + ID0 + 0 + 1 + + + + + LPGPIO_ODR + LPGPIO_ODR + LPGPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + OD15 + OD15 + 15 + 1 + + + OD14 + OD14 + 14 + 1 + + + OD13 + OD13 + 13 + 1 + + + OD12 + OD12 + 12 + 1 + + + OD11 + OD11 + 11 + 1 + + + OD10 + OD10 + 10 + 1 + + + OD9 + OD9 + 9 + 1 + + + OD8 + OD8 + 8 + 1 + + + OD7 + OD7 + 7 + 1 + + + OD6 + OD6 + 6 + 1 + + + OD5 + OD5 + 5 + 1 + + + OD4 + OD4 + 4 + 1 + + + OD3 + OD3 + 3 + 1 + + + OD2 + OD2 + 2 + 1 + + + OD1 + OD1 + 1 + 1 + + + OD0 + OD0 + 0 + 1 + + + + + LPGPIO_BSRR + LPGPIO_BSRR + LPGPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + + + BR15 + BR15 + 31 + 1 + + + BR14 + BR14 + 30 + 1 + + + BR13 + BR13 + 29 + 1 + + + BR12 + BR12 + 28 + 1 + + + BR11 + BR11 + 27 + 1 + + + BR10 + BR10 + 26 + 1 + + + BR9 + BR9 + 25 + 1 + + + BR8 + BR8 + 24 + 1 + + + BR7 + BR7 + 23 + 1 + + + BR6 + BR6 + 22 + 1 + + + BR5 + BR5 + 21 + 1 + + + BR4 + BR4 + 20 + 1 + + + BR3 + BR3 + 19 + 1 + + + BR2 + BR2 + 18 + 1 + + + BR1 + BR1 + 17 + 1 + + + BR0 + BR0 + 16 + 1 + + + BS15 + BS15 + 15 + 1 + + + BS14 + BS14 + 14 + 1 + + + BS13 + BS13 + 13 + 1 + + + BS12 + BS12 + 12 + 1 + + + BS11 + BS11 + 11 + 1 + + + BS10 + BS10 + 10 + 1 + + + BS9 + BS9 + 9 + 1 + + + BS8 + BS8 + 8 + 1 + + + BS7 + BS7 + 7 + 1 + + + BS6 + BS6 + 6 + 1 + + + BS5 + BS5 + 5 + 1 + + + BS4 + BS4 + 4 + 1 + + + BS3 + BS3 + 3 + 1 + + + BS2 + BS2 + 2 + 1 + + + BS1 + BS1 + 1 + 1 + + + BS0 + BS0 + 0 + 1 + + + + + LPGPIO_BRR + LPGPIO_BRR + LPGPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR15 + BR15 + 15 + 1 + + + BR14 + BR14 + 14 + 1 + + + BR13 + BR13 + 13 + 1 + + + BR12 + BR12 + 12 + 1 + + + BR11 + BR11 + 11 + 1 + + + BR10 + BR10 + 10 + 1 + + + BR9 + BR9 + 9 + 1 + + + BR8 + BR8 + 8 + 1 + + + BR7 + BR7 + 7 + 1 + + + BR6 + BR6 + 6 + 1 + + + BR5 + BR5 + 5 + 1 + + + BR4 + BR4 + 4 + 1 + + + BR3 + BR3 + 3 + 1 + + + BR2 + BR2 + 2 + 1 + + + BR1 + BR1 + 1 + 1 + + + BR0 + BR0 + 0 + 1 + + + + + + + SEC_LPGPIO1 + DCB->DSCSR->CDS == 0 + 0x56020000 + + + LPTIM1 + Low power timer + LPTIM + 0x46004400 + + 0x0 + 0x400 + registers + + + LPTIM1 + LPTIM1 global interrupt + 067 + + + + ISR_output + ISR_output + Interrupt and Status Register (output mode) + 0x0 + 0x20 + read-only + 0x00000000 + + + DIEROK + Interrupt enable register update OK + 24 + 1 + + + CMP2OK + Compare register 2 update OK + 19 + 1 + + + CC2IF + Compare 2 interrupt flag + 9 + 1 + + + REPOK + Repetition register update + Ok + 8 + 1 + + + UE + LPTIM update event + occurred + 7 + 1 + + + DOWN + Counter direction change up to + down + 6 + 1 + + + UP + Counter direction change down to + up + 5 + 1 + + + ARROK + Autoreload register update + OK + 4 + 1 + + + CMP1OK + Compare register 1 update OK + 3 + 1 + + + EXTTRIG + External trigger edge + event + 2 + 1 + + + ARRM + Autoreload match + 1 + 1 + + + CC1IF + Compare 1 interrupt flag + 0 + 1 + + + + + ISR_input + ISR_input + Interrupt and Status Register (intput mode) + ISR_output + 0x0 + 0x20 + read-only + 0x00000000 + + + DIEROK + Interrupt enable register update OK + 24 + 1 + + + CC2OF + Capture 2 over-capture flag + 13 + 1 + + + CC1OF + Capture 1 over-capture flag + 12 + 1 + + + CC2IF + Capture 2 interrupt flag + 9 + 1 + + + REPOK + Repetition register update + Ok + 8 + 1 + + + UE + LPTIM update event + occurred + 7 + 1 + + + DOWN + Counter direction change up to + down + 6 + 1 + + + UP + Counter direction change down to + up + 5 + 1 + + + ARROK + Autoreload register update + OK + 4 + 1 + + + EXTTRIG + External trigger edge + event + 2 + 1 + + + ARRM + Autoreload match + 1 + 1 + + + CC1IF + Compare 1 interrupt flag + 0 + 1 + + + + + ICR_output + ICR_output + Interrupt Clear Register (output mode) + 0x4 + 0x20 + write-only + 0x00000000 + + + DIEROKCF + Interrupt enable register update OK clear flag + 24 + 1 + + + CMP2OKCF + Compare register 2 update OK clear flag + 19 + 1 + + + CC2CF + Capture/compare 2 clear flag + 9 + 1 + + + REPOKCF + Repetition register update OK clear + flag + 8 + 1 + + + UECF + Update event clear flag + 7 + 1 + + + DOWNCF + Direction change to down Clear + Flag + 6 + 1 + + + UPCF + Direction change to UP Clear + Flag + 5 + 1 + + + ARROKCF + Autoreload register update OK Clear + Flag + 4 + 1 + + + CMP1OKCF + Compare register 1 update OK Clear + Flag + 3 + 1 + + + EXTTRIGCF + External trigger valid edge Clear + Flag + 2 + 1 + + + ARRMCF + Autoreload match Clear + Flag + 1 + 1 + + + CC1IF + Capture/compare 1 clear flag + 0 + 1 + + + + + ICR_input + ICR_input + Interrupt Clear Register (intput mode) + ICR_output + 0x4 + 0x20 + write-only + 0x00000000 + + + DIEROKCF + Interrupt enable register update OK clear flag + 24 + 1 + + + CC2OCF + Capture/compare 2 over-capture clear flag + 13 + 1 + + + CC1OCF + Capture/compare 1 over-capture clear flag + 12 + 1 + + + CC2CF + Capture/compare 2 clear flag + 9 + 1 + + + REPOKCF + Repetition register update OK clear + flag + 8 + 1 + + + UECF + Update event clear flag + 7 + 1 + + + DOWNCF + Direction change to down Clear + Flag + 6 + 1 + + + UPCF + Direction change to UP Clear + Flag + 5 + 1 + + + ARROKCF + Autoreload register update OK Clear + Flag + 4 + 1 + + + EXTTRIGCF + External trigger valid edge Clear + Flag + 2 + 1 + + + ARRMCF + Autoreload match Clear + Flag + 1 + 1 + + + CC1IF + Capture/compare 1 clear flag + 0 + 1 + + + + + DIER_output + DIER_output + LPTIM interrupt Enable Register (output mode) + 0x8 + 0x20 + read-write + 0x00000000 + + + UEDE + Update event DMA request enable + 23 + 1 + + + CMP2OKIE + Compare register 2 update OK interrupt enable + 19 + 1 + + + CC2IE + Capture/compare 2 interrupt enable + 9 + 1 + + + REPOKIE + REPOKIE + 8 + 1 + + + UEIE + Update event interrupt + enable + 7 + 1 + + + DOWNIE + Direction change to down Interrupt + Enable + 6 + 1 + + + UPIE + Direction change to UP Interrupt + Enable + 5 + 1 + + + ARROKIE + Autoreload register update OK Interrupt + Enable + 4 + 1 + + + CMP1OKIE + Compare register 1 update OK Interrupt + Enable + 3 + 1 + + + EXTTRIGIE + External trigger valid edge Interrupt + Enable + 2 + 1 + + + ARRMIE + Autoreload match Interrupt + Enable + 1 + 1 + + + CC1IF + Capture/compare 1 clear flag + 0 + 1 + + + + + DIER_input + DIER_input + LPTIM interrupt Enable Register (intput mode) + DIER_output + 0x8 + 0x20 + read-write + 0x00000000 + + + CC2DE + Capture/compare 2 DMA request enable + 25 + 1 + + + CC1DE + Capture/compare 1 DMA request enable + 16 + 1 + + + CC2OIE + Capture/compare 2 over-capture interrupt enable + 13 + 1 + + + CC1OIE + Capture/compare 1 over-capture interrupt enable + 12 + 1 + + + CC2IE + Capture/compare 2 interrupt enable + 9 + 1 + + + REPOKIE + REPOKIE + 8 + 1 + + + UEIE + Update event interrupt + enable + 7 + 1 + + + DOWNIE + Direction change to down Interrupt + Enable + 6 + 1 + + + UPIE + Direction change to UP Interrupt + Enable + 5 + 1 + + + ARROKIE + Autoreload register update OK Interrupt + Enable + 4 + 1 + + + EXTTRIGIE + External trigger valid edge Interrupt + Enable + 2 + 1 + + + ARRMIE + Autoreload match Interrupt + Enable + 1 + 1 + + + CC1IF + Capture/compare 1 clear flag + 0 + 1 + + + + + CFGR + CFGR + Configuration Register + 0xC + 0x20 + read-write + 0x00000000 + + + ENC + Encoder mode enable + 24 + 1 + + + COUNTMODE + counter mode enabled + 23 + 1 + + + PRELOAD + Registers update mode + 22 + 1 + + + WAVPOL + Waveform shape polarity + 21 + 1 + + + WAVE + Waveform shape + 20 + 1 + + + TIMOUT + Timeout enable + 19 + 1 + + + TRIGEN + Trigger enable and + polarity + 17 + 2 + + + TRIGSEL + Trigger selector + 13 + 3 + + + PRESC + Clock prescaler + 9 + 3 + + + TRGFLT + Configurable digital filter for + trigger + 6 + 2 + + + CKFLT + Configurable digital filter for external + clock + 3 + 2 + + + CKPOL + Clock Polarity + 1 + 2 + + + CKSEL + Clock selector + 0 + 1 + + + + + CR + CR + Control Register + 0x10 + 0x20 + read-write + 0x00000000 + + + RSTARE + Reset after read enable + 4 + 1 + + + COUNTRST + Counter reset + 3 + 1 + + + CNTSTRT + Timer start in continuous + mode + 2 + 1 + + + SNGSTRT + LPTIM start in single mode + 1 + 1 + + + ENABLE + LPTIM Enable + 0 + 1 + + + + + CCR1 + CCR1 + Compare Register + 0x14 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/compare 1 value + 0 + 16 + + + + + ARR + ARR + Autoreload Register + 0x18 + 0x20 + read-write + 0x00000001 + + + ARR + Auto reload value + 0 + 16 + + + + + CNT + CNT + Counter Register + 0x1C + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 16 + + + + + CFGR2 + CFGR2 + LPTIM configuration register 2 + 0x24 + 0x20 + read-write + 0x00000000 + + + IC2SEL + LPTIM input capture 2 selection + 20 + 2 + + + IC1SEL + LPTIM input capture 1 selection + 16 + 2 + + + IN2SEL + LPTIM input 2 selection + 4 + 2 + + + IN1SEL + LPTIM input 1 selection + 0 + 2 + + + + + RCR + RCR + LPTIM repetition register + 0x28 + 0x20 + read-write + 0x00000000 + + + REP + Repetition register value + 0 + 8 + + + + + CCMR1 + CCMR1 + LPTIM capture/compare mode register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + CC1SEL + Capture/compare 1 selection + 0 + 1 + + + CC1E + Capture/compare 1 output enable + 1 + 1 + + + CC1P + Capture/compare 1 output polarity + 2 + 2 + + + IC1PSC + Input capture 1 prescaler + 8 + 2 + + + IC1F + Input capture 1 filter + 12 + 2 + + + CC2SEL + Capture/compare 2 selection + 16 + 1 + + + CC2E + Capture/compare 2 output enable + 17 + 1 + + + CC2P + Capture/compare 2 output polarity + 18 + 2 + + + IC2PSC + Input capture 2 prescaler + 24 + 2 + + + IC2F + Input capture 2 filter + 28 + 2 + + + + + CCR2 + CCR2 + LPTIM Compare Register 2 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/compare 2 value + 0 + 16 + + + + + + + SEC_LPTIM1 + DCB->DSCSR->CDS == 0 + 0x56004400 + + + LPTIM2 + 0x40009400 + + LPTIM2 + LPTIM2 global interrupt + 068 + + + + SEC_LPTIM2 + DCB->DSCSR->CDS == 0 + 0x50009400 + + + LPTIM3 + 0x46004800 + + LPTIM3 + LPTIM3 global interrupt + 098 + + + + SEC_LPTIM3 + DCB->DSCSR->CDS == 0 + 0x56004800 + + + LPTIM4 + Low power timer + LPTIM + 0x46004C00 + + 0x0 + 0x400 + registers + + + LPTIM4 + LPTIM4 global interrupt + 110 + + + + ISR + ISR + Interrupt and Status Register + 0x0 + 0x20 + read-only + 0x00000000 + + + DIEROK + Interrupt enable register update OK + 24 + 1 + + + REPOK + Repetition register update + Ok + 8 + 1 + + + UE + LPTIM update event + occurred + 7 + 1 + + + DOWN + Counter direction change up to + down + 6 + 1 + + + UP + Counter direction change down to + up + 5 + 1 + + + ARROK + Autoreload register update + OK + 4 + 1 + + + CMP1OK + Compare register 1 update OK + 3 + 1 + + + EXTTRIG + External trigger edge + event + 2 + 1 + + + ARRM + Autoreload match + 1 + 1 + + + CC1IF + Compare 1 interrupt flag + 0 + 1 + + + + + ICR + ICR + Interrupt Clear Register + 0x4 + 0x20 + write-only + 0x00000000 + + + DIEROKCF + Interrupt enable register update OK clear flag + 24 + 1 + + + REPOKCF + Repetition register update OK clear + flag + 8 + 1 + + + UECF + Update event clear flag + 7 + 1 + + + DOWNCF + Direction change to down Clear + Flag + 6 + 1 + + + UPCF + Direction change to UP Clear + Flag + 5 + 1 + + + ARROKCF + Autoreload register update OK Clear + Flag + 4 + 1 + + + CMP1OKCF + Compare register 1 update OK Clear + Flag + 3 + 1 + + + EXTTRIGCF + External trigger valid edge Clear + Flag + 2 + 1 + + + ARRMCF + Autoreload match Clear + Flag + 1 + 1 + + + CC1IF + Capture/compare 1 clear flag + 0 + 1 + + + + + DIER + DIER + LPTIM interrupt Enable Register + 0x8 + 0x20 + read-write + 0x00000000 + + + REPOKIE + REPOKIE + 8 + 1 + + + UEIE + Update event interrupt + enable + 7 + 1 + + + DOWNIE + Direction change to down Interrupt + Enable + 6 + 1 + + + UPIE + Direction change to UP Interrupt + Enable + 5 + 1 + + + ARROKIE + Autoreload register update OK Interrupt + Enable + 4 + 1 + + + CMP1OKIE + Compare register 1 update OK Interrupt + Enable + 3 + 1 + + + EXTTRIGIE + External trigger valid edge Interrupt + Enable + 2 + 1 + + + ARRMIE + Autoreload match Interrupt + Enable + 1 + 1 + + + CC1IF + Capture/compare 1 clear flag + 0 + 1 + + + + + CFGR + CFGR + Configuration Register + 0xC + 0x20 + read-write + 0x00000000 + + + ENC + Encoder mode enable + 24 + 1 + + + COUNTMODE + counter mode enabled + 23 + 1 + + + PRELOAD + Registers update mode + 22 + 1 + + + WAVPOL + Waveform shape polarity + 21 + 1 + + + WAVE + Waveform shape + 20 + 1 + + + TIMOUT + Timeout enable + 19 + 1 + + + TRIGEN + Trigger enable and + polarity + 17 + 2 + + + TRIGSEL + Trigger selector + 13 + 3 + + + PRESC + Clock prescaler + 9 + 3 + + + TRGFLT + Configurable digital filter for + trigger + 6 + 2 + + + CKFLT + Configurable digital filter for external + clock + 3 + 2 + + + CKPOL + Clock Polarity + 1 + 2 + + + CKSEL + Clock selector + 0 + 1 + + + + + CR + CR + Control Register + 0x10 + 0x20 + read-write + 0x00000000 + + + RSTARE + Reset after read enable + 4 + 1 + + + COUNTRST + Counter reset + 3 + 1 + + + CNTSTRT + Timer start in continuous + mode + 2 + 1 + + + SNGSTRT + LPTIM start in single mode + 1 + 1 + + + ENABLE + LPTIM Enable + 0 + 1 + + + + + CCR1 + CCR1 + Compare Register + 0x14 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/compare 1 value + 0 + 16 + + + + + ARR + ARR + Autoreload Register + 0x18 + 0x20 + read-write + 0x00000001 + + + ARR + Auto reload value + 0 + 16 + + + + + CNT + CNT + Counter Register + 0x1C + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 16 + + + + + CFGR2 + CFGR2 + LPTIM configuration register 2 + 0x24 + 0x20 + read-write + 0x00000000 + + + IC2SEL + LPTIM input capture 2 selection + 20 + 2 + + + IC1SEL + LPTIM input capture 1 selection + 16 + 2 + + + IN2SEL + LPTIM input 2 selection + 4 + 2 + + + IN1SEL + LPTIM input 1 selection + 0 + 2 + + + + + RCR + RCR + LPTIM repetition register + 0x28 + 0x20 + read-write + 0x00000000 + + + REP + Repetition register value + 0 + 8 + + + + + CCMR1 + CCMR1 + LPTIM capture/compare mode register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + CC1SEL + Capture/compare 1 selection + 0 + 1 + + + CC1E + Capture/compare 1 output enable + 1 + 1 + + + CC1P + Capture/compare 1 output polarity + 2 + 2 + + + IC1PSC + Input capture 1 prescaler + 8 + 2 + + + IC1F + Input capture 1 filter + 12 + 2 + + + CC2SEL + Capture/compare 2 selection + 16 + 1 + + + CC2E + Capture/compare 2 output enable + 17 + 1 + + + CC2P + Capture/compare 2 output polarity + 18 + 2 + + + IC2PSC + Input capture 2 prescaler + 24 + 2 + + + IC2F + Input capture 2 filter + 28 + 2 + + + + + CCR2 + CCR2 + LPTIM Compare Register 2 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/compare 2 value + 0 + 16 + + + + + + + SEC_LPTIM4 + DCB->DSCSR->CDS == 0 + 0x56004C00 + + + LPUART1 + Universal synchronous asynchronous receiver + transmitter + LPUART + 0x46002400 + + 0x0 + 0x400 + registers + + + LPUART1 + LPUART1 global interrupt + 066 + + + + CR1_enabled + CR1_enabled + Control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + RXFFIE + RXFFIE + 31 + 1 + + + TXFEIE + TXFEIE + 30 + 1 + + + FIFOEN + FIFOEN + 29 + 1 + + + M1 + Word length + 28 + 1 + + + DEAT + DEAT + 21 + 5 + + + DEDT + DEDT + 16 + 5 + + + CMIE + Character match interrupt + enable + 14 + 1 + + + MME + Mute mode enable + 13 + 1 + + + M0 + Word length + 12 + 1 + + + WAKE + Receiver wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXFNFIE + TXFIFO not full interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt + enable + 6 + 1 + + + RXFNEIE + RXFNEIE + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + UESM + USART enable in Stop mode + 1 + 1 + + + UE + USART enable + 0 + 1 + + + + + CR1_disabled + CR1_disabled + Control register 1 + CR1_enabled + 0x0 + 0x20 + read-write + 0x0000 + + + FIFOEN + FIFOEN + 29 + 1 + + + M1 + Word length + 28 + 1 + + + DEAT + DEAT + 21 + 5 + + + DEDT + DEDT + 16 + 5 + + + CMIE + Character match interrupt + enable + 14 + 1 + + + MME + Mute mode enable + 13 + 1 + + + M0 + Word length + 12 + 1 + + + WAKE + Receiver wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXFNFIE + TXFIFO not full interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt + enable + 6 + 1 + + + RXFNEIE + RXFNEIE + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + UESM + USART enable in Stop mode + 1 + 1 + + + UE + USART enable + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + ADD + Address of the LPUART node + 24 + 8 + + + MSBFIRST + Most significant bit first + 19 + 1 + + + DATAINV + Binary data inversion + 18 + 1 + + + TXINV + TX pin active level + inversion + 17 + 1 + + + RXINV + RX pin active level + inversion + 16 + 1 + + + SWAP + Swap TX/RX pins + 15 + 1 + + + STOP + STOP bits + 12 + 2 + + + ADDM7 + 7-bit Address Detection/4-bit Address + Detection + 4 + 1 + + + + + CR3 + CR3 + Control register 3 + 0x8 + 0x20 + read-write + 0x0000 + + + TXFTCFG + TXFTCFG + 29 + 3 + + + RXFTIE + RXFTIE + 28 + 1 + + + RXFTCFG + RXFTCFG + 25 + 3 + + + TXFTIE + TXFTIE + 23 + 1 + + + DEP + Driver enable polarity + selection + 15 + 1 + + + DEM + Driver enable mode + 14 + 1 + + + DDRE + DMA Disable on Reception + Error + 13 + 1 + + + OVRDIS + Overrun Disable + 12 + 1 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSE + CTS enable + 9 + 1 + + + RTSE + RTS enable + 8 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + DMAR + DMA enable receiver + 6 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + + + BRR + BRR + Baud rate register + 0xC + 0x20 + read-write + 0x0000 + + + BRR + BRR + 0 + 20 + + + + + RQR + RQR + Request register + 0x18 + 0x20 + write-only + 0x0000 + + + TXFRQ + TXFRQ + 4 + 1 + + + RXFRQ + Receive data flush request + 3 + 1 + + + MMRQ + Mute mode request + 2 + 1 + + + SBKRQ + Send break request + 1 + 1 + + + + + ISR_enabled + ISR_enabled + Interrupt and status register + 0x1C + 0x20 + read-only + 0x008000C0 + + + TXFT + TXFT + 27 + 1 + + + RXFT + RXFT + 26 + 1 + + + RXFF + RXFF + 24 + 1 + + + TXFF + TXFF + 23 + 1 + + + REACK + REACK + 22 + 1 + + + TEACK + TEACK + 21 + 1 + + + RWU + RWU + 19 + 1 + + + SBKF + SBKF + 18 + 1 + + + CMF + CMF + 17 + 1 + + + BUSY + BUSY + 16 + 1 + + + CTS + CTS + 10 + 1 + + + CTSIF + CTSIF + 9 + 1 + + + TXFNF + TXFNF + 7 + 1 + + + TC + TC + 6 + 1 + + + RXFNE + RXFNE + 5 + 1 + + + IDLE + IDLE + 4 + 1 + + + ORE + ORE + 3 + 1 + + + NE + NE + 2 + 1 + + + FE + FE + 1 + 1 + + + PE + PE + 0 + 1 + + + + + ISR_disabled + ISR_disabled + Interrupt and status register + ISR_enabled + 0x1C + 0x20 + read-only + 0x000000C0 + + + REACK + REACK + 22 + 1 + + + TEACK + TEACK + 21 + 1 + + + RWU + RWU + 19 + 1 + + + SBKF + SBKF + 18 + 1 + + + CMF + CMF + 17 + 1 + + + BUSY + BUSY + 16 + 1 + + + CTS + CTS + 10 + 1 + + + CTSIF + CTSIF + 9 + 1 + + + TXE + TXE + 7 + 1 + + + TC + TC + 6 + 1 + + + RXNE + RXNE + 5 + 1 + + + IDLE + IDLE + 4 + 1 + + + ORE + ORE + 3 + 1 + + + NE + NE + 2 + 1 + + + FE + FE + 1 + 1 + + + PE + PE + 0 + 1 + + + + + ICR + ICR + Interrupt flag clear register + 0x20 + 0x20 + write-only + 0x0000 + + + CMCF + Character match clear flag + 17 + 1 + + + CTSCF + CTS clear flag + 9 + 1 + + + TCCF + Transmission complete clear + flag + 6 + 1 + + + IDLECF + Idle line detected clear + flag + 4 + 1 + + + ORECF + Overrun error clear flag + 3 + 1 + + + NECF + Noise detected clear flag + 2 + 1 + + + FECF + Framing error clear flag + 1 + 1 + + + PECF + Parity error clear flag + 0 + 1 + + + + + RDR + RDR + Receive data register + 0x24 + 0x20 + read-only + 0x0000 + + + RDR + Receive data value + 0 + 9 + + + + + TDR + TDR + Transmit data register + 0x28 + 0x20 + read-write + 0x0000 + + + TDR + Transmit data value + 0 + 9 + + + + + PRESC + PRESC + prescaler register + 0x2C + 0x20 + read-write + 0x0000 + + + PRESCALER + PRESCALER + 0 + 4 + + + + + AUTOCR + AUTOCR + Autonomous mode control register + 0x30 + 0x20 + read-write + 0x80000000 + + + TDN + TDN + 0 + 16 + + + TRIGPOL + TRIGPOL + 16 + 1 + + + TRIGEN + TRIGEN + 17 + 1 + + + IDLEDIS + IDLEDIS + 18 + 1 + + + TRIGSEL + TRIGSEL + 19 + 4 + + + + + + + SEC_LPUART1 + DCB->DSCSR->CDS == 0 + 0x56002400 + + + LTDC + LTDC + LTDC + 0x40016800 + + 0x0 + 0x400 + registers + + + LCD_TFT + LTDC global interrupt + 135 + + + LCD_TFT_ERR + LTDC global error interrupt + 136 + + + + LTDC_SSCR + LTDC_SSCR + LTDC synchronization size configuration register + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + VSH + vertical synchronization height (in units of horizontal scan line) +These bits define the vertical Synchronization height minus 1. It represents the number of horizontal synchronization lines. + 0 + 11 + read-write + + + HSW + horizontal synchronization width (in units of pixel clock period) +These bits define the number of Horizontal Synchronization pixel minus 1. + 16 + 12 + read-write + + + + + LTDC_BPCR + LTDC_BPCR + LTDC back porch configuration register + 0xc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AVBP + accumulated Vertical back porch (in units of horizontal scan line) +These bits define the accumulated vertical back porch width that includes the vertical synchronization and vertical back porch lines minus 1. +The vertical back porch is the number of horizontal scan lines at a start of frame to the start of the first active scan line of the next frame. + 0 + 11 + read-write + + + AHBP + accumulated horizontal back porch (in units of pixel clock period) +These bits define the accumulated horizontal back porch width that includes the horizontal synchronization and horizontal back porch pixels minus 1. +The horizontal back porch is the period between horizontal synchronization going inactive and the start of the active display part of the next scan line. + 16 + 12 + read-write + + + + + LTDC_AWCR + LTDC_AWCR + LTDC active width configuration register + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AAH + accumulated active height (in units of horizontal scan line) +These bits define the accumulated height which includes the vertical synchronization, vertical back porch and the active height lines minus 1. The active height is the number of active lines in the panel. +Refer to device datasheet for maximum active height supported following maximum pixel clock. + 0 + 11 + read-write + + + AAW + accumulated active width (in units of pixel clock period) +These bits define the accumulated active width which includes the horizontal synchronization, horizontal back porch and active pixels minus 1. +The active width is the number of pixels in active display area of the panel scan line. +Refer to device datasheet for maximum active width supported following maximum pixel clock. + 16 + 12 + read-write + + + + + LTDC_TWCR + LTDC_TWCR + LTDC total width configuration register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TOTALH + total height (in units of horizontal scan line) +These bits defines the accumulated height which includes the vertical synchronization, vertical back porch, the active height and vertical front porch height lines minus 1. + 0 + 11 + read-write + + + TOTALW + total width (in units of pixel clock period) +These bits defines the accumulated total width which includes the horizontal synchronization, horizontal back porch, active width and horizontal front porch pixels minus 1. + 16 + 12 + read-write + + + + + LTDC_GCR + LTDC_GCR + LTDC global control register + 0x18 + 0x20 + 0x00002220 + 0xFFFFFFFF + + + LTDCEN + LCD-TFT controller enable +This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + LTDC disabled + 0x0 + + + B_0x1 + LTDC enabled + 0x1 + + + + + DBW + dither blue width +These bits return the dither blue bits. + 4 + 3 + read-only + + + DGW + dither green width +These bits return the dither green bits. + 8 + 3 + read-only + + + DRW + dither red width +These bits return the Dither Red Bits. + 12 + 3 + read-only + + + DEN + dither enable +This bit is set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + dither disabled + 0x0 + + + B_0x1 + dither enabled + 0x1 + + + + + PCPOL + pixel clock polarity +This bit is set and cleared by software. + 28 + 1 + read-write + + + B_0x0 + pixel clock polarity is active low. + 0x0 + + + B_0x1 + pixel clock is active high. + 0x1 + + + + + DEPOL + not data enable polarity +This bit is set and cleared by software. + 29 + 1 + read-write + + + B_0x0 + not data enable polarity is active low. + 0x0 + + + B_0x1 + not data enable polarity is active high. + 0x1 + + + + + VSPOL + vertical synchronization polarity +This bit is set and cleared by software. + 30 + 1 + read-write + + + B_0x0 + vertical synchronization is active low. + 0x0 + + + B_0x1 + vertical synchronization is active high. + 0x1 + + + + + HSPOL + horizontal synchronization polarity +This bit is set and cleared by software. + 31 + 1 + read-write + + + B_0x0 + horizontal synchronization polarity is active low. + 0x0 + + + B_0x1 + horizontal synchronization polarity is active high. + 0x1 + + + + + + + LTDC_SRCR + LTDC_SRCR + LTDC shadow reload configuration register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IMR + immediate reload +This bit is set by software and cleared only by hardware after reload. + 0 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + The shadow registers are reloaded immediately. + 0x1 + + + + + VBR + vertical blanking reload +This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set). + 1 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area). + 0x1 + + + + + + + LTDC_BCCR + LTDC_BCCR + LTDC background color configuration register + 0x2c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BCBLUE + background color blue value +These bits configure the background blue value. + 0 + 8 + read-write + + + BCGREEN + background color green value +These bits configure the background green value. + 8 + 8 + read-write + + + BCRED + background color red value +These bits configure the background red value. + 16 + 8 + read-write + + + + + LTDC_IER + LTDC_IER + LTDC interrupt enable register + 0x34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LIE + line interrupt enable +This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + line interrupt disable + 0x0 + + + B_0x1 + line interrupt enable + 0x1 + + + + + FUIE + FIFO underrun interrupt enable +This bit is set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + FIFO underrun interrupt disable + 0x0 + + + B_0x1 + FIFO underrun Interrupt enable + 0x1 + + + + + TERRIE + transfer error interrupt enable +This bit is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + transfer error interrupt disable + 0x0 + + + B_0x1 + transfer error interrupt enable + 0x1 + + + + + RRIE + register reload interrupt enable +This bit is set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + register reload interrupt disable + 0x0 + + + B_0x1 + register reload interrupt enable + 0x1 + + + + + + + LTDC_ISR + LTDC_ISR + LTDC interrupt status register + 0x38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LIF + line interrupt flag + 0 + 1 + read-only + + + B_0x0 + no line interrupt generated + 0x0 + + + B_0x1 + line interrupt generated when a programmed line is reached + 0x1 + + + + + FUIF + FIFO underrun interrupt flag + 1 + 1 + read-only + + + B_0x0 + no FIFO underrun interrupt generated. + 0x0 + + + B_0x1 + FIFO underrun interrupt generated, if one of the layer FIFOs is empty and pixel data is read from the FIFO + 0x1 + + + + + TERRIF + transfer error interrupt flag + 2 + 1 + read-only + + + B_0x0 + no transfer error interrupt generated + 0x0 + + + B_0x1 + transfer error interrupt generated when a bus error occurs + 0x1 + + + + + RRIF + register reload interrupt flag + 3 + 1 + read-only + + + B_0x0 + no register reload interrupt generated + 0x0 + + + B_0x1 + register reload interrupt generated when a vertical blanking reload occurs (and the first line after the active area is reached) + 0x1 + + + + + + + LTDC_ICR + LTDC_ICR + 0x3c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CLIF + clears the line interrupt flag + 0 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clears the LIF flag in the LTDC_ISR register. + 0x1 + + + + + CFUIF + clears the FIFO underrun interrupt flag + 1 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clears the FUDERRIF flag in the LTDC_ISR register. + 0x1 + + + + + CTERRIF + clears the transfer error interrupt flag + 2 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clears the TERRIF flag in the LTDC_ISR register. + 0x1 + + + + + CRRIF + clears register reload interrupt flag + 3 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clears the RRIF flag in the LTDC_ISR register + 0x1 + + + + + + + LTDC_LIPCR + LTDC_LIPCR + LTDC line interrupt position configuration register + 0x40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LIPOS + line interrupt position +These bits configure the line interrupt position. + 0 + 11 + read-write + + + + + LTDC_CPSR + LTDC_CPSR + 0x44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CYPOS + current Y position +These bits return the current Y position. + 0 + 16 + read-only + + + CXPOS + current X position +These bits return the current X position. + 16 + 16 + read-only + + + + + LTDC_CDSR + LTDC_CDSR + LTDC current display status register + 0x48 + 0x20 + 0x0000000F + 0xFFFFFFFF + + + VDES + vertical data enable display status + 0 + 1 + read-only + + + B_0x0 + active low + 0x0 + + + B_0x1 + active high + 0x1 + + + + + HDES + horizontal data enable display status + 1 + 1 + read-only + + + B_0x0 + active low + 0x0 + + + B_0x1 + active high + 0x1 + + + + + VSYNCS + vertical synchronization display status + 2 + 1 + read-only + + + B_0x0 + active low + 0x0 + + + B_0x1 + active high + 0x1 + + + + + HSYNCS + horizontal synchronization display status + 3 + 1 + read-only + + + B_0x0 + active low + 0x0 + + + B_0x1 + active high + 0x1 + + + + + + + LTDC_L1CR + LTDC_L1CR + 0x84 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LEN + layer enable +This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + layer disable + 0x0 + + + B_0x1 + layer enable + 0x1 + + + + + COLKEN + color keying enable +This bit is set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + color keying disable + 0x0 + + + B_0x1 + color keying enable + 0x1 + + + + + CLUTEN + color look-up table enable +This bit is set and cleared by software. +The CLUT is only meaningful for L8, AL44 and AL88 pixel format. Refer to table (CLUT) + 4 + 1 + read-write + + + B_0x0 + color look-up table disable + 0x0 + + + B_0x1 + color look-up table enable + 0x1 + + + + + + + LTDC_L1WHPCR + LTDC_L1WHPCR + LTDC layer 1 window horizontal position configuration register + 0x88 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WHSTPOS + window horizontal start position +These bits configure the first visible pixel of a line of the layer window. +WHSTPOS[11:0] must be ≤ AAW[11:0] bits (programmed in LTDC_AWCR register). + 0 + 12 + read-write + + + WHSPPOS + window horizontal stop position +These bits configure the last visible pixel of a line of the layer window. +WHSPPOS[11:0] must be ≥ AHBP[11:0] bits + 1 (programmed in LTDC_BPCR register). + 16 + 12 + read-write + + + + + LTDC_L1WVPCR + LTDC_L1WVPCR + LTDC layer 1 window vertical position configuration register + 0x8c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WVSTPOS + window vertical start position +These bits configure the first visible line of the layer window. +WVSTPOS[10:0] must be ≤ AAH[10:0] bits (programmed in LTDC_AWCR register). + 0 + 11 + read-write + + + WVSPPOS + window vertical stop position +These bits configure the last visible line of the layer window. +WVSPPOS[10:0] must be ≥ AVBP[10:0] bits + 1 (programmed in LTDC_BPCR register). + 16 + 11 + read-write + + + + + LTDC_L1CKCR + LTDC_L1CKCR + LTDC layer 1 color keying configuration register + 0x90 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CKBLUE + color key blue value + 0 + 8 + read-write + + + CKGREEN + color key green value + 8 + 8 + read-write + + + CKRED + color key red value + 16 + 8 + read-write + + + + + LTDC_L1PFCR + LTDC_L1PFCR + LTDC layer 1 pixel format configuration register + 0x94 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PF + pixel format +These bits configure the pixel format + 0 + 3 + read-write + + + B_0x0 + ARGB8888 + 0x0 + + + B_0x1 + RGB888 + 0x1 + + + B_0x2 + RGB565 + 0x2 + + + B_0x3 + ARGB1555 + 0x3 + + + B_0x4 + ARGB4444 + 0x4 + + + B_0x5 + L8 (8-bit luminance) + 0x5 + + + B_0x6 + AL44 (4-bit alpha, 4-bit luminance) + 0x6 + + + B_0x7 + AL88 (8-bit alpha, 8-bit luminance) + 0x7 + + + + + + + LTDC_L1CACR + LTDC_L1CACR + LTDC layer 1 constant alpha configuration register + 0x98 + 0x20 + 0x000000FF + 0xFFFFFFFF + + + CONSTA + constant alpha +These bits configure the constant alpha used for blending. The constant alpha is divided by 255 by hardware. +Example: if the programmed constant alpha is 0xFF, the constant alpha value is 255 / 255 = 1. + 0 + 8 + read-write + + + + + LTDC_L1DCCR + LTDC_L1DCCR + LTDC layer 1 default color configuration register + 0x9c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DCBLUE + default color blue +These bits configure the default blue value. + 0 + 8 + read-write + + + DCGREEN + default color green +These bits configure the default green value. + 8 + 8 + read-write + + + DCRED + default color red +These bits configure the default red value. + 16 + 8 + read-write + + + DCALPHA + default color alpha +These bits configure the default alpha value. + 24 + 8 + read-write + + + + + LTDC_L1BFCR + LTDC_L1BFCR + LTDC layer 1 blending factors configuration register + 0xa0 + 0x20 + 0x00000607 + 0xFFFFFFFF + + + BF2 + blending factor 2 +These bits select the blending factor F2 + 0 + 3 + read-write + + + B_0x5 + 1 - constant alpha + 0x5 + + + B_0x7 + 1 - (pixel alpha x constant alpha) + 0x7 + + + + + BF1 + blending factor 1 +These bits select the blending factor F1. + 8 + 3 + read-write + + + B_0x4 + constant alpha + 0x4 + + + B_0x6 + pixel alpha x constant alpha + 0x6 + + + + + + + LTDC_L1CFBAR + LTDC_L1CFBAR + LTDC layer 1 color frame buffer address register + 0xac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CFBADD + color frame buffer start address +These bits define the color frame buffer start address. + 0 + 32 + read-write + + + + + LTDC_L1CFBLR + LTDC_L1CFBLR + LTDC layer 1 color frame buffer length register + 0xb0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CFBLL + color frame buffer line length +These bits define the length of one line of pixels in bytes + 3. +The line length is computed as follows: +active high width *  number of bytes per pixel + 3. + 0 + 13 + read-write + + + CFBP + color frame buffer pitch in bytes +These bits define the pitch that is the increment from the start of one line of pixels to the start of the next line in bytes. + 16 + 13 + read-write + + + + + LTDC_L1CFBLNR + LTDC_L1CFBLNR + LTDC layer 1 color frame buffer line number register + 0xb4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CFBLNBR + frame buffer line number +These bits define the number of lines in the frame buffer that corresponds to the active high width. + 0 + 11 + read-write + + + + + LTDC_L1CLUTWR + LTDC_L1CLUTWR + LTDC layer 1 CLUT write register + 0xc4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BLUE + blue value +These bits configure the blue value. + 0 + 8 + write-only + + + GREEN + green value +These bits configure the green value. + 8 + 8 + write-only + + + RED + red value +These bits configure the red value. + 16 + 8 + write-only + + + CLUTADD + CLUT address +These bits configure the CLUT address (color position within the CLUT) of each RGB value. + 24 + 8 + write-only + + + + + LTDC_L2CR + LTDC_L2CR + 0x104 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LEN + layer enable +This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + layer disable + 0x0 + + + B_0x1 + layer enable + 0x1 + + + + + COLKEN + color keying enable +This bit is set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + color keying disable + 0x0 + + + B_0x1 + color keying enable + 0x1 + + + + + CLUTEN + color look-up table enable +This bit is set and cleared by software. +The CLUT is only meaningful for L8, AL44 and AL88 pixel format. Refer to table (CLUT) + 4 + 1 + read-write + + + B_0x0 + color look-up table disable + 0x0 + + + B_0x1 + color look-up table enable + 0x1 + + + + + + + LTDC_L2WHPCR + LTDC_L2WHPCR + LTDC layer 2 window horizontal position configuration register + 0x108 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WHSTPOS + window horizontal start position +These bits configure the first visible pixel of a line of the layer window. +WHSTPOS[11:0] must be ≤ AAW[11:0] bits (programmed in LTDC_AWCR register). + 0 + 12 + read-write + + + WHSPPOS + window horizontal stop position +These bits configure the last visible pixel of a line of the layer window. +WHSPPOS[11:0] must be ≥ AHBP[11:0] bits + 1 (programmed in LTDC_BPCR register). + 16 + 12 + read-write + + + + + LTDC_L2WVPCR + LTDC_L2WVPCR + LTDC layer 2 window vertical position configuration register + 0x10c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WVSTPOS + window vertical start position +These bits configure the first visible line of the layer window. +WVSTPOS[10:0] must be ≤ AAH[10:0] bits (programmed in LTDC_AWCR register). + 0 + 11 + read-write + + + WVSPPOS + window vertical stop position +These bits configure the last visible line of the layer window. +WVSPPOS[10:0] must be ≥ AVBP[10:0] bits + 1 (programmed in LTDC_BPCR register). + 16 + 11 + read-write + + + + + LTDC_L2CKCR + LTDC_L2CKCR + LTDC layer 2 color keying configuration register + 0x110 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CKBLUE + color key blue value + 0 + 8 + read-write + + + CKGREEN + color key green value + 8 + 8 + read-write + + + CKRED + color key red value + 16 + 8 + read-write + + + + + LTDC_L2PFCR + LTDC_L2PFCR + LTDC layer 2 pixel format configuration register + 0x114 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PF + pixel format +These bits configure the pixel format + 0 + 3 + read-write + + + B_0x0 + ARGB8888 + 0x0 + + + B_0x1 + RGB888 + 0x1 + + + B_0x2 + RGB565 + 0x2 + + + B_0x3 + ARGB1555 + 0x3 + + + B_0x4 + ARGB4444 + 0x4 + + + B_0x5 + L8 (8-bit luminance) + 0x5 + + + B_0x6 + AL44 (4-bit alpha, 4-bit luminance) + 0x6 + + + B_0x7 + AL88 (8-bit alpha, 8-bit luminance) + 0x7 + + + + + + + LTDC_L2CACR + LTDC_L2CACR + LTDC layer 2 constant alpha configuration register + 0x118 + 0x20 + 0x000000FF + 0xFFFFFFFF + + + CONSTA + constant alpha +These bits configure the constant alpha used for blending. The constant alpha is divided by 255 by hardware. +Example: if the programmed constant alpha is 0xFF, the constant alpha value is 255 / 255 = 1. + 0 + 8 + read-write + + + + + LTDC_L2DCCR + LTDC_L2DCCR + LTDC layer 2 default color configuration register + 0x11c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DCBLUE + default color blue +These bits configure the default blue value. + 0 + 8 + read-write + + + DCGREEN + default color green +These bits configure the default green value. + 8 + 8 + read-write + + + DCRED + default color red +These bits configure the default red value. + 16 + 8 + read-write + + + DCALPHA + default color alpha +These bits configure the default alpha value. + 24 + 8 + read-write + + + + + LTDC_L2BFCR + LTDC_L2BFCR + LTDC layer 2 blending factors configuration register + 0x120 + 0x20 + 0x00000607 + 0xFFFFFFFF + + + BF2 + blending factor 2 +These bits select the blending factor F2 + 0 + 3 + read-write + + + B_0x5 + 1 - constant alpha + 0x5 + + + B_0x7 + 1 - (pixel alpha x constant alpha) + 0x7 + + + + + BF1 + blending factor 1 +These bits select the blending factor F1. + 8 + 3 + read-write + + + B_0x4 + constant alpha + 0x4 + + + B_0x6 + pixel alpha x constant alpha + 0x6 + + + + + + + LTDC_L2CFBAR + LTDC_L2CFBAR + LTDC layer 2 color frame buffer address register + 0x12c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CFBADD + color frame buffer start address +These bits define the color frame buffer start address. + 0 + 32 + read-write + + + + + LTDC_L2CFBLR + LTDC_L2CFBLR + LTDC layer 2 color frame buffer length register + 0x130 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CFBLL + color frame buffer line length +These bits define the length of one line of pixels in bytes + 3. +The line length is computed as follows: +active high width *  number of bytes per pixel + 3. + 0 + 13 + read-write + + + CFBP + color frame buffer pitch in bytes +These bits define the pitch that is the increment from the start of one line of pixels to the start of the next line in bytes. + 16 + 13 + read-write + + + + + LTDC_L2CFBLNR + LTDC_L2CFBLNR + LTDC layer 2 color frame buffer line number register + 0x134 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CFBLNBR + frame buffer line number +These bits define the number of lines in the frame buffer that corresponds to the active high width. + 0 + 11 + read-write + + + + + LTDC_L2CLUTWR + LTDC_L2CLUTWR + LTDC layer 2 CLUT write register + 0x144 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BLUE + blue value +These bits configure the blue value. + 0 + 8 + write-only + + + GREEN + green value +These bits configure the green value. + 8 + 8 + write-only + + + RED + red value +These bits configure the red value. + 16 + 8 + write-only + + + CLUTADD + CLUT address +These bits configure the CLUT address (color position within the CLUT) of each RGB value. + 24 + 8 + write-only + + + + + + + SEC_LTDC + DCB->DSCSR->CDS == 0 + 0x50016800 + + + MDF1 + Multi-function digital filter + MDF + 0x40025000 + + 0x0 + 0x1000 + registers + + + MDF1_FLT0 + MDF1 filter 0 global interrupt + 102 + + + MDF1_FLT1 + MDF1 filter 1 global interrupt + 103 + + + MDF1_FLT2 + MDF1 filter 2 global interrupt + 104 + + + MDF1_FLT3 + MDF1 filter 3 global interrupt + 105 + + + MDF1_FLT4 + MDF1 filter 4 global interrupt + 121 + + + MDF1_FLT5 + MDF1 filter 5 global interrupt + 122 + + + + GCR + GCR + MDF global control register + 0x0 + 0x20 + read-write + 0x00000000 + + + TRGO + TRGO + 0 + 1 + + + ILVNB + ILVNB + 4 + 4 + + + + + CKGCR + CKGCR + MDF clock generator control register + 0x004 + 0x20 + read-write + 0x00000000 + + + CKGDEN + CKGDEN + 0 + 1 + + + CCK0EN + CCK0EN + 1 + 1 + + + CCK1EN + CCK1EN + 2 + 1 + + + CKGMOD + CKGMOD + 4 + 1 + + + CCK0DIR + CCK0DIR + 5 + 1 + + + CCK1DIR + CCK1DIR + 6 + 1 + + + TRGSENS + TRGSENS + 8 + 1 + + + TRGSRC + TRGSRC + 12 + 4 + + + CCKDIV + CCKDIV + 16 + 4 + + + PROCDIV + PROCDIV + 24 + 7 + + + CKGACTIVE + CKGACTIVE + 31 + 1 + + + + + MDF_SITF0CR + MDF_SITF0CR + This register is used to control the serial interfaces (SITFx). + 0x80 + 0x20 + 0x00001F00 + + + SITFEN + Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled + 0 + 1 + read-write + + + SCKSRC + Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx, not allowed in LF_MASTER SPI mode This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 1 + 2 + read-write + + + SITFMOD + Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0, falling edge = logic 1 - 11: Manchester mode: rising edge = logic 1, falling edge = logic 0 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 2 + read-write + + + STH + Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode, in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In addition this field is used to define the timeout value for the clock absence detection in Normal SPI mode. Values of STH[4:0] lower than 4 are invalid. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 8 + 5 + read-write + + + SITFACTIVE + Serial interface Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the serial interface is effectively enabled (active) or not. The protected fields of this function can only be updated when the SITFACTIVE is set , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SITFEN and a transition on SITFACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The serial interface is not active, and can be configured if needed - 1: The serial interface is active, and protected fields cannot be configured. + 31 + 1 + read-only + + + + + MDF_SITF1CR + MDF_SITF1CR + This register is used to control the serial interfaces (SITFx). + 0x100 + 0x20 + 0x00001F00 + + + SITFEN + Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled + 0 + 1 + read-write + + + SCKSRC + Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx, not allowed in LF_MASTER SPI mode This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 1 + 2 + read-write + + + SITFMOD + Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0, falling edge = logic 1 - 11: Manchester mode: rising edge = logic 1, falling edge = logic 0 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 2 + read-write + + + STH + Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode, in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In addition this field is used to define the timeout value for the clock absence detection in Normal SPI mode. Values of STH[4:0] lower than 4 are invalid. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 8 + 5 + read-write + + + SITFACTIVE + Serial interface Active flag + 31 + 1 + read-only + + + + + MDF_SITF2CR + MDF_SITF2CR + This register is used to control the serial interfaces (SITFx). + 0x180 + 0x20 + 0x00001F00 + + + SITFEN + Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled + 0 + 1 + read-write + + + SCKSRC + Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx, not allowed in LF_MASTER SPI mode This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 1 + 2 + read-write + + + SITFMOD + Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0, falling edge = logic 1 - 11: Manchester mode: rising edge = logic 1, falling edge = logic 0 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 2 + read-write + + + STH + Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode, in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In addition this field is used to define the timeout value for the clock absence detection in Normal SPI mode. Values of STH[4:0] lower than 4 are invalid. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 8 + 5 + read-write + + + SITFACTIVE + Serial interface Active flag + 31 + 1 + read-only + + + + + MDF_SITF3CR + MDF_SITF3CR + This register is used to control the serial interfaces (SITFx). + 0x200 + 0x20 + 0x00001F00 + + + SITFEN + Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled + 0 + 1 + read-write + + + SCKSRC + Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx, not allowed in LF_MASTER SPI mode This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 1 + 2 + read-write + + + SITFMOD + Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0, falling edge = logic 1 - 11: Manchester mode: rising edge = logic 1, falling edge = logic 0 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 2 + read-write + + + STH + Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode, in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In addition this field is used to define the timeout value for the clock absence detection in Normal SPI mode. Values of STH[4:0] lower than 4 are invalid. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 8 + 5 + read-write + + + SITFACTIVE + Serial interface Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the serial interface is effectively enabled (active) or not. The protected fields of this function can only be updated when the SITFACTIVE is set , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SITFEN and a transition on SITFACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The serial interface is not active, and can be configured if needed - 1: The serial interface is active, and protected fields cannot be configured. + 31 + 1 + read-only + + + + + MDF_SITF4CR + MDF_SITF4CR + This register is used to control the serial interfaces (SITFx). + 0x280 + 0x20 + 0x00001F00 + + + SITFEN + Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled + 0 + 1 + read-write + + + SCKSRC + Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx, not allowed in LF_MASTER SPI mode This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 1 + 2 + read-write + + + SITFMOD + Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0, falling edge = logic 1 - 11: Manchester mode: rising edge = logic 1, falling edge = logic 0 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 2 + read-write + + + STH + Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode, in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In addition this field is used to define the timeout value for the clock absence detection in Normal SPI mode. Values of STH[4:0] lower than 4 are invalid. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 8 + 5 + read-write + + + SITFACTIVE + Serial interface Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the serial interface is effectively enabled (active) or not. The protected fields of this function can only be updated when the SITFACTIVE is set , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SITFEN and a transition on SITFACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The serial interface is not active, and can be configured if needed - 1: The serial interface is active, and protected fields cannot be configured. + 31 + 1 + read-only + + + + + MDF_SITF5CR + MDF_SITF5CR + This register is used to control the serial interfaces (SITFx). + 0x300 + 0x20 + 0x00001F00 + + + SITFEN + Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled + 0 + 1 + read-write + + + SCKSRC + Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx, not allowed in LF_MASTER SPI mode This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 1 + 2 + read-write + + + SITFMOD + Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0, falling edge = logic 1 - 11: Manchester mode: rising edge = logic 1, falling edge = logic 0 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 2 + read-write + + + STH + Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode, in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In addition this field is used to define the timeout value for the clock absence detection in Normal SPI mode. Values of STH[4:0] lower than 4 are invalid. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 8 + 5 + read-write + + + SITFACTIVE + Serial interface Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the serial interface is effectively enabled (active) or not. The protected fields of this function can only be updated when the SITFACTIVE is set , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SITFEN and a transition on SITFACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The serial interface is not active, and can be configured if needed - 1: The serial interface is active, and protected fields cannot be configured. + 31 + 1 + read-only + + + + + MDF_BSMX0CR + MDF_BSMX0CR + This register is used to select the bitstream to be provided to the corresponding digital filter and to the SCD. + 0x84 + 0x20 + 0x00000000 + + + BSSEL + Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an input which is not instantiated, the MDF will select the valid stream bs[x]_F having the higher index number. - 00000: The bitstream bs[0]_R is provided to DFLTx and SCDx - 00001: The bitstream bs[0]_F is provided to DFLTx and SCDx - 00010: The bitstream bs[1]_R is provided to DFLTx and SCDx (if instantiated) - 00011: The bitstream bs[1]_F is provided to DFLTx and SCDx (if instantiated) ... - 11110: The bitstream bs[15]_R is provided to DFLTx and SCDx (if instantiated) - 11111: The bitstream bs[15]_F is provided to DFLTx and SCDx (if instantiated) This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 0 + 5 + read-write + + + BSMXACTIVE + BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set . The BSMXACTIVE flag is a logical between OLDACTIVE, DFLTACTIVE, and SCDACTIVE flags. Both of them must be set in order update BSSEL[4:0] field. - 0: The BSMX is not active, and can be configured if needed - 1: The BSMX is active, and protected fields cannot be configured. + 31 + 1 + read-only + + + + + MDF_BSMX1CR + MDF_BSMX1CR + This register is used to select the bitstream to be provided to the corresponding digital filter and to the SCD. + 0x104 + 0x20 + 0x00000000 + + + BSSEL + Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an input which is not instantiated, the MDF will select the valid stream bs[x]_F having the higher index number. - 00000: The bitstream bs[0]_R is provided to DFLTx and SCDx - 00001: The bitstream bs[0]_F is provided to DFLTx and SCDx - 00010: The bitstream bs[1]_R is provided to DFLTx and SCDx (if instantiated) - 00011: The bitstream bs[1]_F is provided to DFLTx and SCDx (if instantiated) ... - 11110: The bitstream bs[15]_R is provided to DFLTx and SCDx (if instantiated) - 11111: The bitstream bs[15]_F is provided to DFLTx and SCDx (if instantiated) This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 0 + 5 + read-write + + + BSMXACTIVE + BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set . The BSMXACTIVE flag is a logical between OLDACTIVE, DFLTACTIVE, and SCDACTIVE flags. Both of them must be set in order update BSSEL[4:0] field. - 0: The BSMX is not active, and can be configured if needed - 1: The BSMX is active, and protected fields cannot be configured. + 31 + 1 + read-only + + + + + MDF_BSMX2CR + MDF_BSMX2CR + This register is used to select the bitstream to be provided to the corresponding digital filter and to the SCD. + 0x184 + 0x20 + 0x00000000 + + + BSSEL + Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an input which is not instantiated, the MDF will select the valid stream bs[x]_F having the higher index number. - 00000: The bitstream bs[0]_R is provided to DFLTx and SCDx - 00001: The bitstream bs[0]_F is provided to DFLTx and SCDx - 00010: The bitstream bs[1]_R is provided to DFLTx and SCDx (if instantiated) - 00011: The bitstream bs[1]_F is provided to DFLTx and SCDx (if instantiated) ... - 11110: The bitstream bs[15]_R is provided to DFLTx and SCDx (if instantiated) - 11111: The bitstream bs[15]_F is provided to DFLTx and SCDx (if instantiated) This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 0 + 5 + read-write + + + BSMXACTIVE + BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set to a . The BSMXACTIVE flag is a logical between OLDACTIVE, DFLTACTIVE, and SCDACTIVE flags. Both of them must be set to in order update BSSEL[4:0] field. - 0: The BSMX is not active, and can be configured if needed - 1: The BSMX is active, and protected fields cannot be configured. + 31 + 1 + read-only + + + + + MDF_BSMX3CR + MDF_BSMX3CR + This register is used to select the bitstream to be provided to the corresponding digital filter and to the SCD. + 0x204 + 0x20 + 0x00000000 + + + BSSEL + Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an input which is not instantiated, the MDF will select the valid stream bs[x]_F having the higher index number. - 00000: The bitstream bs[0]_R is provided to DFLTx and SCDx - 00001: The bitstream bs[0]_F is provided to DFLTx and SCDx - 00010: The bitstream bs[1]_R is provided to DFLTx and SCDx (if instantiated) - 00011: The bitstream bs[1]_F is provided to DFLTx and SCDx (if instantiated) ... - 11110: The bitstream bs[15]_R is provided to DFLTx and SCDx (if instantiated) - 11111: The bitstream bs[15]_F is provided to DFLTx and SCDx (if instantiated) This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 0 + 5 + read-write + + + BSMXACTIVE + BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set to a . The BSMXACTIVE flag is a logical between OLDACTIVE, DFLTACTIVE, and SCDACTIVE flags. Both of them must be set to a in order update BSSEL[4:0] field. - 0: The BSMX is not active, and can be configured if needed - 1: The BSMX is active, and protected fields cannot be configured. + 31 + 1 + read-only + + + + + MDF_BSMX4CR + MDF_BSMX4CR + This register is used to select the bitstream to be provided to the corresponding digital filter and to the SCD. + 0x284 + 0x20 + 0x00000000 + + + BSSEL + Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an input which is not instantiated, the MDF will select the valid stream bs[x]_F having the higher index number. - 00000: The bitstream bs[0]_R is provided to DFLTx and SCDx - 00001: The bitstream bs[0]_F is provided to DFLTx and SCDx - 00010: The bitstream bs[1]_R is provided to DFLTx and SCDx (if instantiated) - 00011: The bitstream bs[1]_F is provided to DFLTx and SCDx (if instantiated) ... - 11110: The bitstream bs[15]_R is provided to DFLTx and SCDx (if instantiated) - 11111: The bitstream bs[15]_F is provided to DFLTx and SCDx (if instantiated) This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 0 + 5 + read-write + + + BSMXACTIVE + BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set to . The BSMXACTIVE flag is a logical between OLDACTIVE, DFLTACTIVE, and SCDACTIVE flags. Both of them must be set to in order update BSSEL[4:0] field. - 0: The BSMX is not active, and can be configured if needed - 1: The BSMX is active, and protected fields cannot be configured. + 31 + 1 + read-only + + + + + MDF_BSMX5CR + MDF_BSMX5CR + This register is used to select the bitstream to be provided to the corresponding digital filter and to the SCD. + 0x304 + 0x20 + 0x00000000 + + + BSSEL + Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an input which is not instantiated, the MDF will select the valid stream bs[x]_F having the higher index number. - 00000: The bitstream bs[0]_R is provided to DFLTx and SCDx - 00001: The bitstream bs[0]_F is provided to DFLTx and SCDx - 00010: The bitstream bs[1]_R is provided to DFLTx and SCDx (if instantiated) - 00011: The bitstream bs[1]_F is provided to DFLTx and SCDx (if instantiated) ... - 11110: The bitstream bs[15]_R is provided to DFLTx and SCDx (if instantiated) - 11111: The bitstream bs[15]_F is provided to DFLTx and SCDx (if instantiated) This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 0 + 5 + read-write + + + BSMXACTIVE + BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set to . The BSMXACTIVE flag is a logical between OLDACTIVE, DFLTACTIVE, and SCDACTIVE flags. Both of them must be set to in order update BSSEL[4:0] field. - 0: The BSMX is not active, and can be configured if needed - 1: The BSMX is active, and protected fields cannot be configured. + 31 + 1 + read-only + + + + + MDF_DFLT0CR + MDF_DFLT0CR + This register is used to control the digital filter x. + 0x88 + 0x20 + 0x00000000 + + + DFLTEN + Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the proper trigger event occurs if ACQMOD = 01x . The serial or parallel interface delivering the samples shall be enabled as well. - 0: The acquisition is stopped immediately - 1: The acquisition is immediately started if ACQMOD = 00x or 1xx , + 0 + 1 + write-only + + + DMAEN + DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The DMA interface for the corresponding digital filter is enabled This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 1 + 1 + read-write + + + FTH + RXFIFO Threshold selection Set and cleared by software. + 2 + 1 + read-write + + + ACQMOD + Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous, continuous acquisition mode - 001: Asynchronous, single-shot acquisition mode - 010: Synchronous, continuous acquisition mode - 011: Synchronous, single-shot acquisition mode - 100: Window, continuous acquisition mode - 101: Synchronous, snapshot mode others: same a 000 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 3 + read-write + + + TRGSENS + Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the acquisition Note that when the trigger source is TRGO or OLDx event, TRGSENS value is not taken into account. When TRGO is selected, the sensitivity is forced to falling edge, when OLDx event is selected, the sensitivity is forced to rising edge. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 8 + 1 + read-write + + + TRGSRC + Digital filter Trigger signal selection, Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0] is selected ... - 1111: mdf_trg[13] is selected This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 12 + 4 + read-write + + + SNPSFMT + Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register, leaving a data resolution of 23 bits. - 1: The integrator counter (INT_CNT) is inserted at position [15:9] of MDF_SNPSxDR register, leaving a data resolution of 16 bits. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 16 + 1 + read-write + + + NBDIS + Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... - 255: 255 samples discarded This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 20 + 8 + read-write + + + DFLTRUN + Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running, and ready to accept a new trigger event - 1: The digital filter is running + 30 + 1 + read-only + + + DFLTACTIVE + Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active, and can be re-enabled again (via DFLTEN bit) if needed - 1: The digital filter is active + 31 + 1 + read-only + + + + + MDF_DFLT1CR + MDF_DFLT1CR + This register is used to control the digital filter x. + 0x108 + 0x20 + 0x00000000 + + + DFLTEN + Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the proper trigger event occurs if ACQMOD = 01x . The serial or parallel interface delivering the samples shall be enabled as well. - 0: The acquisition is stopped immediately - 1: The acquisition is immediately started if ACQMOD = 00x or 1xx , + 0 + 1 + write-only + + + DMAEN + DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The DMA interface for the corresponding digital filter is enabled This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 1 + 1 + read-write + + + FTH + RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO threshold. This bit is not significant for RXFIFOs working in interleaved transfer mode. Refer to Section 1.4.13.4: Using the interleaved transfer mode for details. - 0: RXFIFO threshold event generated when the RXFIFO is not empty - 1: RXFIFO threshold event generated when the RXFIFO is half-full This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 2 + 1 + read-write + + + ACQMOD + Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous, continuous acquisition mode - 001: Asynchronous, single-shot acquisition mode - 010: Synchronous, continuous acquisition mode - 011: Synchronous, single-shot acquisition mode - 100: Window, continuous acquisition mode - 101: Synchronous, snapshot mode others: same a 000 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 3 + read-write + + + TRGSENS + Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the acquisition Note that when the trigger source is TRGO or OLDx event, TRGSENS value is not taken into account. When TRGO is selected, the sensitivity is forced to falling edge, when OLDx event is selected, the sensitivity is forced to rising edge. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 8 + 1 + read-write + + + TRGSRC + Digital filter Trigger signal selection, Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0] is selected ... - 1111: mdf_trg[13] is selected This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 12 + 4 + read-write + + + SNPSFMT + Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register, leaving a data resolution of 23 bits. - 1: The integrator counter (INT_CNT) is inserted at position [15:9] of MDF_SNPSxDR register, leaving a data resolution of 16 bits. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 16 + 1 + read-write + + + NBDIS + Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... - 255: 255 samples discarded This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 20 + 8 + read-write + + + DFLTRUN + Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running, and ready to accept a new trigger event - 1: The digital filter is running + 30 + 1 + read-only + + + DFLTACTIVE + Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active, and can be re-enabled again (via DFLTEN bit) if needed - 1: The digital filter is active + 31 + 1 + read-only + + + + + MDF_DFLT2CR + MDF_DFLT2CR + This register is used to control the digital filter 2. + 0x188 + 0x20 + 0x00000000 + + + DFLTEN + Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the proper trigger event occurs if ACQMOD = 01x . The serial or parallel interface delivering the samples shall be enabled as well. - 0: The acquisition is stopped immediately - 1: The acquisition is immediately started if ACQMOD = 00x or 1xx , + 0 + 1 + write-only + + + DMAEN + DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The DMA interface for the corresponding digital filter is enabled This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 1 + 1 + read-write + + + FTH + RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO threshold. This bit is not significant for RXFIFOs working in a interleaved transfer mode. Refer to Section 1.4.13.4: Using the interleaved transfer mode for details. - 0: RXFIFO threshold event generated when the RXFIFO is not empty - 1: RXFIFO threshold event generated when the RXFIFO is half-full This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 2 + 1 + read-write + + + ACQMOD + Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous, continuous acquisition mode - 001: Asynchronous, single-shot acquisition mode - 010: Synchronous, continuous acquisition mode - 011: Synchronous, single-shot acquisition mode - 100: Window, continuous acquisition mode - 101: Synchronous, snapshot mode others: same a 000 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 3 + read-write + + + TRGSENS + Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the acquisition Note that when the trigger source is TRGO or OLDx event, TRGSENS value is not taken into account. When TRGO is selected, the sensitivity is forced to falling edge, when OLDx event is selected, the sensitivity is forced to rising edge. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 8 + 1 + read-write + + + TRGSRC + Digital filter Trigger signal selection, Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0] is selected ... - 1111: mdf_trg[13] is selected This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 12 + 4 + read-write + + + SNPSFMT + Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register, leaving a data resolution of 23 bits. - 1: The integrator counter (INT_CNT) is inserted at position [15:9] of MDF_SNPSxDR register, leaving a data resolution of 16 bits. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 16 + 1 + read-write + + + NBDIS + Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... - 255: 255 samples discarded This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 20 + 8 + read-write + + + DFLTRUN + Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running, and ready to accept a new trigger event - 1: The digital filter is running + 30 + 1 + read-only + + + DFLTACTIVE + Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active, and can be re-enabled again (via DFLTEN bit) if needed - 1: The digital filter is active + 31 + 1 + read-only + + + + + MDF_DFLT3CR + MDF_DFLT3CR + This register is used to control the digital filter 3. + 0x208 + 0x20 + 0x00000000 + + + DFLTEN + Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the proper trigger event occurs if ACQMOD = 01x . The serial or parallel interface delivering the samples shall be enabled as well. - 0: The acquisition is stopped immediately - 1: The acquisition is immediately started if ACQMOD = 00x or 1xx , + 0 + 1 + write-only + + + DMAEN + DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The DMA interface for the corresponding digital filter is enabled This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 1 + 1 + read-write + + + FTH + RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO threshold. This bit is not significant for RXFIFOs working in a interleaved transfer mode. Refer to Section 1.4.13.4: Using the interleaved transfer mode for details. - 0: RXFIFO threshold event generated when the RXFIFO is not empty - 1: RXFIFO threshold event generated when the RXFIFO is half-full This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 2 + 1 + read-write + + + ACQMOD + Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous, continuous acquisition mode - 001: Asynchronous, single-shot acquisition mode - 010: Synchronous, continuous acquisition mode - 011: Synchronous, single-shot acquisition mode - 100: Window, continuous acquisition mode - 101: Synchronous, snapshot mode others: same a 000 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 3 + read-write + + + TRGSENS + Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the acquisition Note that when the trigger source is TRGO or OLDx event, TRGSENS value is not taken into account. When TRGO is selected, the sensitivity is forced to falling edge, when OLDx event is selected, the sensitivity is forced to rising edge. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 8 + 1 + read-write + + + TRGSRC + Digital filter Trigger signal selection, Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0] is selected ... - 1111: mdf_trg[13] is selected This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 12 + 4 + read-write + + + SNPSFMT + Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register, leaving a data resolution of 23 bits. - 1: The integrator counter (INT_CNT) is inserted at position [15:9] of MDF_SNPSxDR register, leaving a data resolution of 16 bits. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 16 + 1 + read-write + + + NBDIS + Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... - 255: 255 samples discarded This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 20 + 8 + read-write + + + DFLTRUN + Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running, and ready to accept a new trigger event - 1: The digital filter is running + 30 + 1 + read-only + + + DFLTACTIVE + Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active, and can be re-enabled again (via DFLTEN bit) if needed - 1: The digital filter is active + 31 + 1 + read-only + + + + + MDF_DFLT4CR + MDF_DFLT4CR + This register is used to control the digital filter 4. + 0x288 + 0x20 + 0x00000000 + + + DFLTEN + Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the proper trigger event occurs if ACQMOD = 01x . The serial or parallel interface delivering the samples shall be enabled as well. - 0: The acquisition is stopped immediately - 1: The acquisition is immediately started if ACQMOD = 00x or 1xx , + 0 + 1 + write-only + + + DMAEN + DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The DMA interface for the corresponding digital filter is enabled This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 1 + 1 + read-write + + + FTH + RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO threshold. This bit is not significant for RXFIFOs working in a interleaved transfer mode. Refer to Section 1.4.13.4: Using the interleaved transfer mode for details. - 0: RXFIFO threshold event generated when the RXFIFO is not empty - 1: RXFIFO threshold event generated when the RXFIFO is half-full This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 2 + 1 + read-write + + + ACQMOD + Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous, continuous acquisition mode - 001: Asynchronous, single-shot acquisition mode - 010: Synchronous, continuous acquisition mode - 011: Synchronous, single-shot acquisition mode - 100: Window, continuous acquisition mode - 101: Synchronous, snapshot mode others: same a 000 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 3 + read-write + + + TRGSENS + Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the acquisition Note that when the trigger source is TRGO or OLDx event, TRGSENS value is not taken into account. When TRGO is selected, the sensitivity is forced to falling edge, when OLDx event is selected, the sensitivity is forced to rising edge. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 8 + 1 + read-write + + + TRGSRC + Digital filter Trigger signal selection, Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0] is selected ... - 1111: mdf_trg[13] is selected This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 12 + 4 + read-write + + + SNPSFMT + Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register, leaving a data resolution of 23 bits. - 1: The integrator counter (INT_CNT) is inserted at position [15:9] of MDF_SNPSxDR register, leaving a data resolution of 16 bits. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 16 + 1 + read-write + + + NBDIS + Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... - 255: 255 samples discarded This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 20 + 8 + read-write + + + DFLTRUN + Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running, and ready to accept a new trigger event - 1: The digital filter is running + 30 + 1 + read-only + + + DFLTACTIVE + Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active, and can be re-enabled again (via DFLTEN bit) if needed - 1: The digital filter is active + 31 + 1 + read-only + + + + + MDF_DFLT5CR + MDF_DFLT5CR + This register is used to control the digital filter x. + 0x308 + 0x20 + 0x00000000 + + + DFLTEN + Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the proper trigger event occurs if ACQMOD = 01x . The serial or parallel interface delivering the samples shall be enabled as well. - 0: The acquisition is stopped immediately - 1: The acquisition is immediately started if ACQMOD = 00x or 1xx , + 0 + 1 + write-only + + + DMAEN + DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The DMA interface for the corresponding digital filter is enabled This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 1 + 1 + read-write + + + FTH + RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO threshold. This bit is not significant for RXFIFOs working in interleaved transfer mode. Refer to Section 1.4.13.4: Using the interleaved transfer mode for details. - 0: RXFIFO threshold event generated when the RXFIFO is not empty - 1: RXFIFO threshold event generated when the RXFIFO is half-full This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 2 + 1 + read-write + + + ACQMOD + Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous, continuous acquisition mode - 001: Asynchronous, single-shot acquisition mode - 010: Synchronous, continuous acquisition mode - 011: Synchronous, single-shot acquisition mode - 100: Window, continuous acquisition mode - 101: Synchronous, snapshot mode others: same a 000 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 3 + read-write + + + TRGSENS + Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the acquisition Note that when the trigger source is TRGO or OLDx event, TRGSENS value is not taken into account. When TRGO is selected, the sensitivity is forced to falling edge, when OLDx event is selected, the sensitivity is forced to rising edge. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 8 + 1 + read-write + + + TRGSRC + Digital filter Trigger signal selection, Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0] is selected ... - 1111: mdf_trg[13] is selected This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 12 + 4 + read-write + + + SNPSFMT + Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register, leaving a data resolution of 23 bits. - 1: The integrator counter (INT_CNT) is inserted at position [15:9] of MDF_SNPSxDR register, leaving a data resolution of 16 bits. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 16 + 1 + read-write + + + NBDIS + Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... - 255: 255 samples discarded This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 20 + 8 + read-write + + + DFLTRUN + Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running, and ready to accept a new trigger event - 1: The digital filter is running + 30 + 1 + read-only + + + DFLTACTIVE + Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active, and can be re-enabled again (via DFLTEN bit) if needed - 1: The digital filter is active + 31 + 1 + read-only + + + + + MDF_DFLT0CICR + MDF_DFLT0CICR + This register is used to control the main CIC filter. + 0x8C + 32 + read-write + 0x00000000 + + + DATSRC + Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 0 + 2 + + + CICMOD + Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx , the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary CIC (ACIC), used for the out-off limit detector - 000: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in FastSinc filter - 001: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc1 filter - 010: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc2 filter - 011: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc3 filter - 100: The CIC is configured in single sinc4 filter others: The CIC is configured in single sinc5 filter This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 3 + + + MCICD + CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0: Decimation ratio is 2 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 511: Decimation ratio is 512 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 8 + 9 + + + SCALE + Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back the SCALE[5:0] field will inform the application on the current gain value. - 100000: - 48.2 dB, or shift right by 8 bits (default value) - 100001: - 44.6 dB, - 100010: - 42.1 dB, or shift right by 7 bits - 100011: - 38.6 dB, ... - 101110: -6 dB, or shift right by 1 bit - 101111: -2.5 dB, - 000000: 0 dB - 000001: + 3.5 dB, - 000010: + 6 dB, or shift left by 1 bit ... - 011000: + 72 dB, or shift left by 12 bits + 20 + 6 + + + + + MDF_DFLT1CICR + MDF_DFLT1CICR + This register is used to control the main CIC filter. + 0x10C + 32 + read-write + 0x00000000 + + + DATSRC + Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 0 + 2 + + + CICMOD + Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx , the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary CIC (ACIC), used for the out-off limit detector - 000: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in FastSinc filter - 001: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc1 filter - 010: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc2 filter - 011: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc3 filter - 100: The CIC is configured in single sinc4 filter others: The CIC is configured in single sinc5 filter This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 3 + + + MCICD + CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0: Decimation ratio is 2 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 511: Decimation ratio is 512 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 8 + 9 + + + SCALE + Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back the SCALE[5:0] field will inform the application on the current gain value. - 100000: - 48.2 dB, or shift right by 8 bits (default value) - 100001: - 44.6 dB, - 100010: - 42.1 dB, or shift right by 7 bits - 100011: - 38.6 dB, ... - 101110: -6 dB, or shift right by 1 bit - 101111: -2.5 dB, - 000000: 0 dB - 000001: + 3.5 dB, - 000010: + 6 dB, or shift left by 1 bit ... - 011000: + 72 dB, or shift left by 12 bits + 20 + 6 + + + + + MDF_DFLT2CICR + MDF_DFLT2CICR + This register is used to control the main CIC filter. + 0x18C + 32 + read-write + 0x00000000 + + + DATSRC + Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 0 + 2 + + + CICMOD + Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx , the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary CIC (ACIC), used for the out-off limit detector - 000: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in FastSinc filter - 001: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc1 filter - 010: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc2 filter - 011: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc3 filter - 100: The CIC is configured in single sinc4 filter others: The CIC is configured in single sinc5 filter This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 3 + + + MCICD + CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0: Decimation ratio is 2 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 511: Decimation ratio is 512 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 8 + 9 + + + SCALE + Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back the SCALE[5:0] field will inform the application on the current gain value. - 100000: - 48.2 dB, or shift right by 8 bits (default value) - 100001: - 44.6 dB, - 100010: - 42.1 dB, or shift right by 7 bits - 100011: - 38.6 dB, ... - 101110: -6 dB, or shift right by 1 bit - 101111: -2.5 dB, - 000000: 0 dB - 000001: + 3.5 dB, - 000010: + 6 dB, or shift left by 1 bit ... - 011000: + 72 dB, or shift left by 12 bits + 20 + 6 + + + + + MDF_DFLT3CICR + MDF_DFLT3CICR + This register is used to control the main CIC filter. + 0x20C + 32 + read-write + 0x00000000 + + + DATSRC + Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 0 + 2 + + + CICMOD + Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx , the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary CIC (ACIC), used for the out-off limit detector - 000: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in FastSinc filter - 001: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc1 filter - 010: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc2 filter - 011: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc3 filter - 100: The CIC is configured in single sinc4 filter others: The CIC is configured in single sinc5 filter This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 3 + + + MCICD + CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0: Decimation ratio is 2 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 511: Decimation ratio is 512 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 8 + 9 + + + SCALE + Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back the SCALE[5:0] field will inform the application on the current gain value. - 100000: - 48.2 dB, or shift right by 8 bits (default value) - 100001: - 44.6 dB, - 100010: - 42.1 dB, or shift right by 7 bits - 100011: - 38.6 dB, ... - 101110: -6 dB, or shift right by 1 bit - 101111: -2.5 dB, - 000000: 0 dB - 000001: + 3.5 dB, - 000010: + 6 dB, or shift left by 1 bit ... - 011000: + 72 dB, or shift left by 12 bits + 20 + 6 + + + + + MDF_DFLT4CICR + MDF_DFLT4CICR + This register is used to control the main CIC filter. + 0x28C + 32 + read-write + 0x00000000 + + + DATSRC + Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 0 + 2 + + + CICMOD + Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx , the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary CIC (ACIC), used for the out-off limit detector - 000: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in FastSinc filter - 001: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc1 filter - 010: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc2 filter - 011: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc3 filter - 100: The CIC is configured in single sinc4 filter others: The CIC is configured in single sinc5 filter This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 3 + + + MCICD + CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0: Decimation ratio is 2 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 511: Decimation ratio is 512 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 8 + 9 + + + SCALE + Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back the SCALE[5:0] field will inform the application on the current gain value. - 100000: - 48.2 dB, or shift right by 8 bits (default value) - 100001: - 44.6 dB, - 100010: - 42.1 dB, or shift right by 7 bits - 100011: - 38.6 dB, ... - 101110: -6 dB, or shift right by 1 bit - 101111: -2.5 dB, - 000000: 0 dB - 000001: + 3.5 dB, - 000010: + 6 dB, or shift left by 1 bit ... - 011000: + 72 dB, or shift left by 12 bits + 20 + 6 + + + + + MDF_DFLT5CICR + MDF_DFLT5CICR + This register is used to control the main CIC filter. + 0x30C + 32 + read-write + 0x00000000 + + + DATSRC + Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 0 + 2 + + + CICMOD + Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx , the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary CIC (ACIC), used for the out-off limit detector - 000: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in FastSinc filter - 001: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc1 filter - 010: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc2 filter - 011: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc3 filter - 100: The CIC is configured in single sinc4 filter others: The CIC is configured in single sinc5 filter This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 3 + + + MCICD + CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0: Decimation ratio is 2 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 511: Decimation ratio is 512 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 8 + 9 + + + SCALE + Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back the SCALE[5:0] field will inform the application on the current gain value. - 100000: - 48.2 dB, or shift right by 8 bits (default value) - 100001: - 44.6 dB, - 100010: - 42.1 dB, or shift right by 7 bits - 100011: - 38.6 dB, ... - 101110: -6 dB, or shift right by 1 bit - 101111: -2.5 dB, - 000000: 0 dB - 000001: + 3.5 dB, - 000010: + 6 dB, or shift left by 1 bit ... - 011000: + 72 dB, or shift left by 12 bits + 20 + 6 + + + + + MDF_DFLT0RSFR + MDF_DFLT0RSFR + This register is used to control the reshape and HPF filters. + 0x90 + 0x20 + read-write + 0x00000000 + + + RSFLTBYP + Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 0 + 1 + + + RSFLTD + Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 1 + + + HPFBYP + High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 7 + 1 + + + HPFC + High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off frequency = 0.00125 x FPCM - 10: Cut-off frequency = 0.00250 x FPCM - 11: Cut-off frequency = 0.00950 x FPCM This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 8 + 2 + + + + + MDF_DFLT1RSFR + MDF_DFLT1RSFR + This register is used to control the reshape and HPF filters. + 0x110 + 0x20 + read-write + 0x00000000 + + + RSFLTBYP + Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 0 + 1 + + + RSFLTD + Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 1 + + + HPFBYP + High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 7 + 1 + + + HPFC + High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off frequency = 0.00125 x FPCM - 10: Cut-off frequency = 0.00250 x FPCM - 11: Cut-off frequency = 0.00950 x FPCM This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 8 + 2 + + + + + MDF_DFLT2RSFR + MDF_DFLT2RSFR + This register is used to control the reshape and HPF filters. + 0x190 + 0x20 + read-write + 0x00000000 + + + RSFLTBYP + Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 0 + 1 + + + RSFLTD + Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 1 + + + HPFBYP + High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 7 + 1 + + + HPFC + High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off frequency = 0.00125 x FPCM - 10: Cut-off frequency = 0.00250 x FPCM - 11: Cut-off frequency = 0.00950 x FPCM This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 8 + 2 + + + + + MDF_DFLT3RSFR + MDF_DFLT3RSFR + This register is used to control the reshape and HPF filters. + 0x210 + 0x20 + read-write + 0x00000000 + + + RSFLTBYP + Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 0 + 1 + + + RSFLTD + Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 1 + + + HPFBYP + High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 7 + 1 + + + HPFC + High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off frequency = 0.00125 x FPCM - 10: Cut-off frequency = 0.00250 x FPCM - 11: Cut-off frequency = 0.00950 x FPCM This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 8 + 2 + + + + + MDF_DFLT4RSFR + MDF_DFLT4RSFR + This register is used to control the reshape and HPF filters. + 0x290 + 0x20 + read-write + 0x00000000 + + + RSFLTBYP + Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 0 + 1 + + + RSFLTD + Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 1 + + + HPFBYP + High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 7 + 1 + + + HPFC + High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off frequency = 0.00125 x FPCM - 10: Cut-off frequency = 0.00250 x FPCM - 11: Cut-off frequency = 0.00950 x FPCM This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 8 + 2 + + + + + MDF_DFLT5RSFR + MDF_DFLT5RSFR + This register is used to control the reshape and HPF filters. + 0x310 + 0x20 + read-write + 0x00000000 + + + RSFLTBYP + Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 0 + 1 + + + RSFLTD + Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 1 + + + HPFBYP + High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 7 + 1 + + + HPFC + High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off frequency = 0.00125 x FPCM - 10: Cut-off frequency = 0.00250 x FPCM - 11: Cut-off frequency = 0.00950 x FPCM This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 8 + 2 + + + + + MDF_DFLT0INTR + MDF_DFLT0INTR + This register is used to the integrator (INT) settings. + 0x94 + 0x20 + read-write + 0x00000000 + + + INTDIV + Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The integrator data outputs are divided by 32 - 10: The integrator data outputs are divided by 4 - 11: The integrator data outputs are not divided This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 0 + 2 + + + INTVAL + Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1, meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3 ... - 127: The integration value is 128 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 7 + + + + + MDF_DFLT1INTR + MDF_DFLT1INTR + This register is used to the integrator (INT) settings. + 0x114 + 0x20 + read-write + 0x00000000 + + + INTDIV + Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The integrator data outputs are divided by 32 - 10: The integrator data outputs are divided by 4 - 11: The integrator data outputs are not divided This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 0 + 2 + + + INTVAL + Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1, meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3 ... - 127: The integration value is 128 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 7 + + + + + MDF_DFLT2INTR + MDF_DFLT2INTR + This register is used to the integrator (INT) settings. + 0x194 + 0x20 + read-write + 0x00000000 + + + INTDIV + Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The integrator data outputs are divided by 32 - 10: The integrator data outputs are divided by 4 - 11: The integrator data outputs are not divided This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 0 + 2 + + + INTVAL + Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1, meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3 ... - 127: The integration value is 128 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 7 + + + + + MDF_DFLT3INTR + MDF_DFLT3INTR + This register is used to the integrator (INT) settings. + 0x214 + 0x20 + read-write + 0x00000000 + + + INTDIV + Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The integrator data outputs are divided by 32 - 10: The integrator data outputs are divided by 4 - 11: The integrator data outputs are not divided This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 0 + 2 + + + INTVAL + Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1, meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3 ... - 127: The integration value is 128 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 7 + + + + + MDF_DFLT4INTR + MDF_DFLT4INTR + This register is used to the integrator (INT) settings. + 0x294 + 0x20 + read-write + 0x00000000 + + + INTDIV + Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The integrator data outputs are divided by 32 - 10: The integrator data outputs are divided by 4 - 11: The integrator data outputs are not divided This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 0 + 2 + + + INTVAL + Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1, meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3 ... - 127: The integration value is 128 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 7 + + + + + MDF_DFLT5INTR + MDF_DFLT5INTR + This register is used to the integrator (INT) settings. + 0x314 + 0x20 + read-write + 0x00000000 + + + INTDIV + Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The integrator data outputs are divided by 32 - 10: The integrator data outputs are divided by 4 - 11: The integrator data outputs are not divided This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 0 + 2 + + + INTVAL + Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1, meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3 ... - 127: The integration value is 128 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 7 + + + + + MDF_OLD0CR + MDF_OLD0CR + This register is used to configure the Out-of Limit Detector function. + 0x98 + 0x20 + 0x00000000 + + + OLDEN + Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled, including the ACIC filter working in continuous mode. + 0 + 1 + read-write + + + THINB + Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 1 + 1 + read-write + + + BKOLD + Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 4 + read-write + + + ACICN + OLD CIC order selection Set and cleared by software. This field allows the application to select the type, and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1 filter type - 10: Sinc2 filter type - 11: Sinc3 filter type This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 12 + 2 + read-write + + + ACICD + OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio is given by (ACICD+1). - 0: Decimation ratio is 1 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 31: Decimation ratio is 32 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 17 + 5 + read-write + + + OLDACTIVE + OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the OLDACTIVE is set to , please refer to Section 1.4.15: Register protection for details. The delay between a transition on OLDEN and a transition on OLDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The OLD is not active, and can be configured if needed - 1: The OLD is active, and protected fields cannot be configured. + 31 + 1 + read-only + + + + + MDF_OLD1CR + MDF_OLD1CR + This register is used to configure the Out-of Limit Detector function. + 0x118 + 0x20 + 0x00000000 + + + OLDEN + Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled, including the ACIC filter working in continuous mode. + 0 + 1 + read-write + + + THINB + Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 1 + 1 + read-write + + + BKOLD + Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 4 + read-write + + + ACICN + OLD CIC order selection Set and cleared by software. This field allows the application to select the type, and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1 filter type - 10: Sinc2 filter type - 11: Sinc3 filter type This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 12 + 2 + read-write + + + ACICD + OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio is given by (ACICD+1). - 0: Decimation ratio is 1 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 31: Decimation ratio is 32 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 17 + 5 + read-write + + + OLDACTIVE + OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the OLDACTIVE is set to , please refer to Section 1.4.15: Register protection for details. The delay between a transition on OLDEN and a transition on OLDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The OLD is not active, and can be configured if needed - 1: The OLD is active, and protected fields cannot be configured. + 31 + 1 + read-only + + + + + MDF_OLD2CR + MDF_OLD2CR + This register is used to configure the Out-of Limit Detector function. + 0x198 + 0x20 + 0x00000000 + + + OLDEN + Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled, including the ACIC filter working in continuous mode. + 0 + 1 + read-write + + + THINB + Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 1 + 1 + read-write + + + BKOLD + Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 4 + read-write + + + ACICN + OLD CIC order selection Set and cleared by software. This field allows the application to select the type, and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1 filter type - 10: Sinc2 filter type - 11: Sinc3 filter type This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 12 + 2 + read-write + + + ACICD + OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio is given by (ACICD+1). - 0: Decimation ratio is 1 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 31: Decimation ratio is 32 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 17 + 5 + read-write + + + OLDACTIVE + OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the OLDACTIVE is set to , please refer to Section 1.4.15: Register protection for details. The delay between a transition on OLDEN and a transition on OLDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The OLD is not active, and can be configured if needed - 1: The OLD is active, and protected fields cannot be configured. + 31 + 1 + read-only + + + + + MDF_OLD3CR + MDF_OLD3CR + This register is used to configure the Out-of Limit Detector function. + 0x218 + 0x20 + 0x00000000 + + + OLDEN + Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled, including the ACIC filter working in continuous mode. + 0 + 1 + read-write + + + THINB + Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 1 + 1 + read-write + + + BKOLD + Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 4 + read-write + + + ACICN + OLD CIC order selection Set and cleared by software. This field allows the application to select the type, and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1 filter type - 10: Sinc2 filter type - 11: Sinc3 filter type This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 12 + 2 + read-write + + + ACICD + OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio is given by (ACICD+1). - 0: Decimation ratio is 1 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 31: Decimation ratio is 32 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 17 + 5 + read-write + + + OLDACTIVE + OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the OLDACTIVE is set to , please refer to Section 1.4.15: Register protection for details. The delay between a transition on OLDEN and a transition on OLDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The OLD is not active, and can be configured if needed - 1: The OLD is active, and protected fields cannot be configured. + 31 + 1 + read-only + + + + + MDF_OLD4CR + MDF Out-Of Limit Detector Control Register 0 + This register is used to configure the Out-of Limit Detector function. + 0x298 + 0x20 + 0x00000000 + + + OLDEN + Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled, including the ACIC filter working in continuous mode. + 0 + 1 + read-write + + + THINB + Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 1 + 1 + read-write + + + BKOLD + Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 4 + read-write + + + ACICN + OLD CIC order selection Set and cleared by software. This field allows the application to select the type, and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1 filter type - 10: Sinc2 filter type - 11: Sinc3 filter type This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 12 + 2 + read-write + + + ACICD + OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio is given by (ACICD+1). - 0: Decimation ratio is 1 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 31: Decimation ratio is 32 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 17 + 5 + read-write + + + OLDACTIVE + OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the OLDACTIVE is set to , please refer to Section 1.4.15: Register protection for details. The delay between a transition on OLDEN and a transition on OLDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The OLD is not active, and can be configured if needed - 1: The OLD is active, and protected fields cannot be configured. + 31 + 1 + read-only + + + + + MDF_OLD5CR + MDF_OLD5CR + This register is used to configure the Out-of Limit Detector function. + 0x318 + 0x20 + 0x00000000 + + + OLDEN + Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled, including the ACIC filter working in continuous mode. + 0 + 1 + read-write + + + THINB + Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 1 + 1 + read-write + + + BKOLD + Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 4 + read-write + + + ACICN + OLD CIC order selection Set and cleared by software. This field allows the application to select the type, and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1 filter type - 10: Sinc2 filter type - 11: Sinc3 filter type This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 12 + 2 + read-write + + + ACICD + OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio is given by (ACICD+1). - 0: Decimation ratio is 1 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 31: Decimation ratio is 32 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 17 + 5 + read-write + + + OLDACTIVE + OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the OLDACTIVE is set to , please refer to Section 1.4.15: Register protection for details. The delay between a transition on OLDEN and a transition on OLDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The OLD is not active, and can be configured if needed - 1: The OLD is active, and protected fields cannot be configured. + 31 + 1 + read-only + + + + + MDF_OLD0THLR + MDF_OLD0THLR + This register is used for the adjustment of the Out-off Limit low threshold. + 0x9C + 0x20 + read-write + 0x00000000 + + + OLDTHL + OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 0 + 26 + + + + + MDF_OLD1THLR + MDF_OLD1THLR + This register is used for the adjustment of the Out-off Limit low threshold. + 0x11C + 0x20 + read-write + 0x00000000 + + + OLDTHL + OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 0 + 26 + + + + + MDF_OLD2THLR + MDF_OLD2THLR + This register is used for the adjustment of the Out-off Limit low threshold. + 0x19C + 0x20 + read-write + 0x00000000 + + + OLDTHL + OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 0 + 26 + + + + + MDF_OLD3THLR + MDF_OLD3THLR + This register is used for the adjustment of the Out-off Limit low threshold. + 0x21C + 0x20 + read-write + 0x00000000 + + + OLDTHL + OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 0 + 26 + + + + + MDF_OLD4THLR + MDF_OLD4THLR + This register is used for the adjustment of the Out-off Limit low threshold. + 0x29C + 0x20 + read-write + 0x00000000 + + + OLDTHL + OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 0 + 26 + + + + + MDF_OLD5THLR + MDF_OLD5THLR + This register is used for the adjustment of the Out-off Limit low threshold. + 0x31C + 0x20 + read-write + 0x00000000 + + + OLDTHL + OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 0 + 26 + + + + + MDF_OLD0THHR + MDF_OLD0THHR + This register is used for the adjustment of the Out-off Limit high threshold. + 0xA0 + 0x20 + read-write + 0x00000000 + + + OLDTHH + OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected, please refer to Section 1.4.15: Register protection for details + 0 + 26 + + + + + MDF_OLD1THHR + MDF_OLD1THHR + This register is used for the adjustment of the Out-off Limit high threshold. + 0x120 + 0x20 + read-write + 0x00000000 + + + OLDTHH + OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected, please refer to Section 1.4.15: Register protection for details + 0 + 26 + + + + + MDF_OLD2THHR + MDF_OLD2THHR + This register is used for the adjustment of the Out-off Limit high threshold. + 0x1A0 + 0x20 + read-write + 0x00000000 + + + OLDTHH + OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected, please refer to Section 1.4.15: Register protection for details + 0 + 26 + + + + + MDF_OLD3THHR + MDF_OLD3THHR + This register is used for the adjustment of the Out-off Limit high threshold. + 0x220 + 0x20 + read-write + 0x00000000 + + + OLDTHH + OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected, please refer to Section 1.4.15: Register protection for details + 0 + 26 + + + + + MDF_OLD4THHR + MDF_OLD4THHR + This register is used for the adjustment of the Out-off Limit high threshold. + 0x2A0 + 0x20 + read-write + 0x00000000 + + + OLDTHH + OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected, please refer to Section 1.4.15: Register protection for details + 0 + 26 + + + + + MDF_OLD5THHR + MDF_OLD5THHR + This register is used for the adjustment of the Out-off Limit high threshold. + 0x320 + 0x20 + read-write + 0x00000000 + + + OLDTHH + OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected, please refer to Section 1.4.15: Register protection for details + 0 + 26 + + + + + MDF_DLY0CR + MDF_DLY0CR + This register is used for the adjustment stream delays. + 0xA4 + 0x20 + 0x00000000 + + + SKPDLY + Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field, if SKPBF = 0 , and the corresponding bit DFLTEN = 1 . If SKPBF = 1 the value written into the register is ignored by the delay state machine. - 0: No input sample skipped, - 1: 1 input sample skipped, ... - 127: 127 input sample skipped, + 0 + 7 + read-write + + + SKPBF + Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid SKPDLY[6:0] is still under precessing. + 31 + 1 + read-only + + + + + MDF_DLY1CR + MDF_DLY1CR + This register is used for the adjustment stream delays. + 0x124 + 0x20 + 0x00000000 + + + SKPDLY + Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field, if SKPBF = 0 , and the corresponding bit DFLTEN = 1 . If SKPBF = 1 the value written into the register is ignored by the delay state machine. - 0: No input sample skipped, - 1: 1 input sample skipped, ... - 127: 127 input sample skipped, + 0 + 7 + read-write + + + SKPBF + Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid SKPDLY[6:0] is still under precessing. + 31 + 1 + read-only + + + + + MDF_DLY2CR + MDF_DLY2CR + This register is used for the adjustment stream delays. + 0x1A4 + 0x20 + 0x00000000 + + + SKPDLY + Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field, if SKPBF = 0 , and the corresponding bit DFLTEN = 1 . If SKPBF = 1 the value written into the register is ignored by the delay state machine. - 0: No input sample skipped, - 1: 1 input sample skipped, ... - 127: 127 input sample skipped, + 0 + 7 + read-write + + + SKPBF + Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid SKPDLY[6:0] is still under precessing. + 31 + 1 + read-only + + + + + MDF_DLY3CR + MDF_DLY3CR + This register is used for the adjustment stream delays. + 0x224 + 0x20 + 0x00000000 + + + SKPDLY + Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field, if SKPBF = 0 , and the corresponding bit DFLTEN = 1 . If SKPBF = 1 the value written into the register is ignored by the delay state machine. - 0: No input sample skipped, - 1: 1 input sample skipped, ... - 127: 127 input sample skipped, + 0 + 7 + read-write + + + SKPBF + Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid SKPDLY[6:0] is still under precessing. + 31 + 1 + read-only + + + + + MDF_DLY4CR + MDF_DLY4CR + This register is used for the adjustment stream delays. + 0x2A4 + 0x20 + 0x00000000 + + + SKPDLY + Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field, if SKPBF = 0 , and the corresponding bit DFLTEN = 1 . If SKPBF = 1 the value written into the register is ignored by the delay state machine. - 0: No input sample skipped, - 1: 1 input sample skipped, ... - 127: 127 input sample skipped, + 0 + 7 + read-write + + + SKPBF + Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid SKPDLY[6:0] is still under precessing. + 31 + 1 + read-only + + + + + MDF_DLY5CR + MDF_DLY5CR + This register is used for the adjustment stream delays. + 0x324 + 0x20 + 0x00000000 + + + SKPDLY + Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field, if SKPBF = 0 , and the corresponding bit DFLTEN = 1 . If SKPBF = 1 the value written into the register is ignored by the delay state machine. - 0: No input sample skipped, - 1: 1 input sample skipped, ... - 127: 127 input sample skipped, + 0 + 7 + read-write + + + SKPBF + Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid SKPDLY[6:0] is still under precessing. + 31 + 1 + read-only + + + + + MDF_SCD0CR + MDF_SCD0CR + This register is used for the adjustment stream delays. + 0xA8 + 0x20 + 0x00000000 + + + SCDEN + Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled, - 1: The short circuit detector is enabled, + 0 + 1 + read-write + + + BKSCD + Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 4 + read-write + + + SCDT + Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given input stream. - 0: 2 consecutive 1 s or 0 s will generate an event, - 1: 2 consecutive 1 s or 0 s will generate an event - 2: 3 consecutive 1 s or 0 s will generate an event, ... - 255: 256 consecutive 1 s or 0 s will generate an event, This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 12 + 8 + read-write + + + SCDACTIVE + SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to a , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SCDEN and a transition on SCDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The SCD is not active, and can be configured if needed - 1: The SCD is active, and protected fields cannot be configured. + 31 + 1 + read-only + + + + + MDF_SCD1CR + MDF_SCD1CR + This register is used for the adjustment stream delays. + 0x128 + 0x20 + 0x00000000 + + + SCDEN + Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled, - 1: The short circuit detector is enabled, + 0 + 1 + read-write + + + BKSCD + Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 4 + read-write + + + SCDT + Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given input stream. - 0: 2 consecutive 1 s or 0 s will generate an event, - 1: 2 consecutive 1 s or 0 s will generate an event - 2: 3 consecutive 1 s or 0 s will generate an event, ... - 255: 256 consecutive 1 s or 0 s will generate an event, This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 12 + 8 + read-write + + + SCDACTIVE + SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to a , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SCDEN and a transition on SCDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The SCD is not active, and can be configured if needed - 1: The SCD is active, and protected fields cannot be configured. + 31 + 1 + read-only + + + + + MDF_SCD2CR + MDF_SCD2CR + This register is used for the adjustment stream delays. + 0x1A8 + 0x20 + 0x00000000 + + + SCDEN + Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled, - 1: The short circuit detector is enabled, + 0 + 1 + read-write + + + BKSCD + Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 4 + read-write + + + SCDT + Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given input stream. - 0: 2 consecutive 1 s or 0 s will generate an event, - 1: 2 consecutive 1 s or 0 s will generate an event - 2: 3 consecutive 1 s or 0 s will generate an event, ... - 255: 256 consecutive 1 s or 0 s will generate an event, This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 12 + 8 + read-write + + + SCDACTIVE + SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to a , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SCDEN and a transition on SCDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The SCD is not active, and can be configured if needed - 1: The SCD is active, and protected fields cannot be configured. + 31 + 1 + read-only + + + + + MDF_SCD3CR + MDF_SCD3CR + This register is used for the adjustment stream delays. + 0x228 + 0x20 + 0x00000000 + + + SCDEN + Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled, - 1: The short circuit detector is enabled, + 0 + 1 + read-write + + + BKSCD + Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 4 + read-write + + + SCDT + Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given input stream. - 0: 2 consecutive 1 s or 0 s will generate an event, - 1: 2 consecutive 1 s or 0 s will generate an event - 2: 3 consecutive 1 s or 0 s will generate an event, ... - 255: 256 consecutive 1 s or 0 s will generate an event, This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 12 + 8 + read-write + + + SCDACTIVE + SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to a , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SCDEN and a transition on SCDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The SCD is not active, and can be configured if needed - 1: The SCD is active, and protected fields cannot be configured. + 31 + 1 + read-only + + + + + MDF_SCD4CR + MDF_SCD4CR + This register is used for the adjustment stream delays. + 0x2A8 + 0x20 + 0x00000000 + + + SCDEN + Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled, - 1: The short circuit detector is enabled, + 0 + 1 + read-write + + + BKSCD + Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 4 + read-write + + + SCDT + Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given input stream. - 0: 2 consecutive 1 s or 0 s will generate an event, - 1: 2 consecutive 1 s or 0 s will generate an event - 2: 3 consecutive 1 s or 0 s will generate an event, ... - 255: 256 consecutive 1 s or 0 s will generate an event, This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 12 + 8 + read-write + + + SCDACTIVE + SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to a a , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SCDEN and a transition on SCDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The SCD is not active, and can be configured if needed - 1: The SCD is active, and protected fields cannot be configured. + 31 + 1 + read-only + + + + + MDF_SCD5CR + MDF_SCD5CR + This register is used for the adjustment stream delays. + 0x328 + 0x20 + 0x00000000 + + + SCDEN + Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled, - 1: The short circuit detector is enabled, + 0 + 1 + read-write + + + BKSCD + Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 4 + 4 + read-write + + + SCDT + Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given input stream. - 0: 2 consecutive 1 s or 0 s will generate an event, - 1: 2 consecutive 1 s or 0 s will generate an event - 2: 3 consecutive 1 s or 0 s will generate an event, ... - 255: 256 consecutive 1 s or 0 s will generate an event, This field can be write-protected, please refer to Section 1.4.15: Register protection for details. + 12 + 8 + read-write + + + SCDACTIVE + SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to a a , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SCDEN and a transition on SCDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The SCD is not active, and can be configured if needed - 1: The SCD is active, and protected fields cannot be configured. + 31 + 1 + read-only + + + + + MDF_DFLT0IER + MDF_DFLT0IER + This register is used for allowing or not the events to generate an interrupt. + 0xAC + 0x20 + read-write + 0x00000000 + + + FTHIE + RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled + 0 + 1 + + + DOVRIE + Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled + 1 + 1 + + + SSDRIE + Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled + 2 + 1 + + + OLDIE + Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled + 4 + 1 + + + SSOVRIE + Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled + 7 + 1 + read-write + + + SCDIE + Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled + 8 + 1 + read-write + + + SATIE + Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled + 9 + 1 + read-write + + + CKABIE + Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled + 10 + 1 + + + RFOVRIE + Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled + 11 + 1 + + + + + MDF_DFLT0ISR + MDF_DFLT0ISR + MDF DFLT0 interrupt status register 0 + 0xB0 + 0x20 + 0x00000000 + + + FTHF + FTHF + 0 + 1 + read-only + + + DOVRF + Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected, writing 0 has no effect. - 1: Reading 1 means that an overflow is detected, writing 1 clears this flag. + 1 + 1 + read-write + + + SSDRF + Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on , writing 0 has no effect. - 1: Reading 1 means that a new data is available on , writing 1 clears this flag. + 2 + 1 + read-write + + + RXNEF + RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty. + 3 + 1 + read-only + + + OLDF + Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected, writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected, writing 1 clears THHF, THLF and OLDF flags. + 4 + 1 + read-write + + + THLF + Low threshold status flag Set by hardware, and cleared by software by writing this bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was higher than OLDTHL when the last OLD event occurred. - 1: The signal was lower than OLDTHL when the last OLD event occurred. + 5 + 1 + read-only + + + THHF + High threshold status flag Set by hardware, and cleared by software by writing this bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHH when the last OLD event occurred. - 1: The signal was higher than OLDTHH when the last OLD event occurred. + 6 + 1 + read-only + + + SSOVRF + Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected, writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is detected, writing 1 clears this flag. + 7 + 1 + read-write + + + SCDF + Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected, writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected, writing 1 clears this flag. + 8 + 1 + read-write + + + SATF + Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected, writing 0 has no effect. - 1: Reading 1 means that a saturation is detected, writing 1 clears this flag. + 9 + 1 + read-write + + + CKABF + Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected, writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected, writing 1 clears this flag. + 10 + 1 + read-write + + + RFOVRF + Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected, writing 0 has no effect. - 1: Reading 1 means that reshape filter overrun is detected, writing 1 clears this flag. + 11 + 1 + read-write + + + + + MDF_DFLT1IER + MDF_DFLT1IER + MDF DFLTx interrupt enable register x + 0x12C + 0x20 + read-write + 0x00000000 + + + FTHIE + RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled + 0 + 1 + + + DOVRIE + Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled + 1 + 1 + + + SSDRIE + Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled + 2 + 1 + + + OLDIE + Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled + 4 + 1 + + + SSOVRIE + Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled + 7 + 1 + + + SCDIE + Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled + 8 + 1 + + + SATIE + Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled + 9 + 1 + + + CKABIE + Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled + 10 + 1 + + + RFOVRIE + Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled + 11 + 1 + + + + + MDF_DFLT2IER + MDF_DFLT2IER + MDF DFLTx interrupt enable register x + 0x1AC + 0x20 + read-write + 0x00000000 + + + FTHIE + RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled + 0 + 1 + + + DOVRIE + Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled + 1 + 1 + + + SSDRIE + Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled + 2 + 1 + + + OLDIE + Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled + 4 + 1 + + + SSOVRIE + Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled + 7 + 1 + + + SCDIE + Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled + 8 + 1 + + + SATIE + Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled + 9 + 1 + + + CKABIE + Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled + 10 + 1 + + + RFOVRIE + Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled + 11 + 1 + + + + + MDF_DFLT3IER + MDF_DFLT3IER + MDF DFLTx interrupt enable register x + 0x22C + 0x20 + read-write + 0x00000000 + + + FTHIE + RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled + 0 + 1 + + + DOVRIE + Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled + 1 + 1 + + + SSDRIE + Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled + 2 + 1 + + + OLDIE + Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled + 4 + 1 + + + SSOVRIE + Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled + 7 + 1 + + + SCDIE + Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled + 8 + 1 + + + SATIE + Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled + 9 + 1 + + + CKABIE + Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled + 10 + 1 + + + RFOVRIE + Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled + 11 + 1 + + + + + MDF_DFLT4IER + MDF_DFLT4IER + MDF DFLTx interrupt enable register x + 0x2AC + 0x20 + read-write + 0x00000000 + + + FTHIE + RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled + 0 + 1 + + + DOVRIE + Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled + 1 + 1 + + + SSDRIE + Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled + 2 + 1 + + + OLDIE + Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled + 4 + 1 + + + SSOVRIE + Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled + 7 + 1 + + + SCDIE + Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled + 8 + 1 + + + SATIE + Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled + 9 + 1 + + + CKABIE + Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled + 10 + 1 + + + RFOVRIE + Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled + 11 + 1 + + + + + MDF_DFLT5IER + MDF_DFLT5IER + MDF DFLTx interrupt enable register x + 0x32C + 0x20 + read-write + 0x00000000 + + + FTHIE + RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled + 0 + 1 + + + DOVRIE + Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled + 1 + 1 + + + SSDRIE + Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled + 2 + 1 + + + OLDIE + Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled + 4 + 1 + + + SSOVRIE + Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled + 7 + 1 + + + SCDIE + Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled + 8 + 1 + + + SATIE + Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled + 9 + 1 + + + CKABIE + Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled + 10 + 1 + + + RFOVRIE + Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled + 11 + 1 + + + + + MDF_DFLT1ISR + MDF_DFLT1ISR + This register contains the status flags for each digital filter path. + 0x130 + 0x20 + 0x00000000 + + + FTHF + RXFIFO threshold flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that the RXFIFO threshold is not reached, writing 0 has no effect. - 1: Reading 1 means that the RXFIFO reached the threshold, writing 1 clears this flag. + 0 + 1 + read-only + + + DOVRF + Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected, writing 0 has no effect. - 1: Reading 1 means that an overflow is detected, writing 1 clears this flag. + 1 + 1 + read-write + + + SSDRF + Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on MDF_SNPSxDR, writing 0 has no effect. - 1: Reading 1 means that a new data is available on MDF_SNPSxDR, writing 1 clears this flag. + 2 + 1 + read-write + + + RXNEF + RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty. + 3 + 1 + read-only + + + OLDF + Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected, writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected, writing 1 clears THHF, THLF and OLDF flags. + 4 + 1 + read-write + + + THLF + Low threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHL, when the last OLD event occurred - 1: The signal was higher than OLDTHL, when the last OLD event occurred + 5 + 1 + read-only + + + THHF + High threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHH, when the last OLD event occurred - 1: The signal was higher than OLDTHH, when the last OLD event occurred + 6 + 1 + read-only + + + SSOVRF + Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected, writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is detected, writing 1 clears this flag. + 7 + 1 + read-write + + + SCDF + Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected, writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected, writing 1 clears this flag. + 8 + 1 + read-write + + + SATF + Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected, writing 0 has no effect. - 1: Reading 1 means that a saturation is detected, writing 1 clears this flag. + 9 + 1 + read-write + + + CKABF + Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected, writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected, writing 1 clears this flag. + 10 + 1 + read-write + + + RFOVRF + Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected, writing 0 has no effect. - 1: Reading 1 means that reshape filter overrun is detected, writing 1 clears this flag. + 11 + 1 + read-write + + + + + MDF_DFLT2ISR + MDF_DFLT2ISR + This register contains the status flags for each digital filter path. + 0x1B0 + 0x20 + 0x00000000 + + + FTHF + RXFIFO threshold flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that the RXFIFO threshold is not reached, writing 0 has no effect. - 1: Reading 1 means that the RXFIFO reached the threshold, writing 1 clears this flag. + 0 + 1 + read-only + + + DOVRF + Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected, writing 0 has no effect. - 1: Reading 1 means that an overflow is detected, writing 1 clears this flag. + 1 + 1 + read-write + + + SSDRF + Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on MDF_SNPSxDR, writing 0 has no effect. - 1: Reading 1 means that a new data is available on MDF_SNPSxDR, writing 1 clears this flag. + 2 + 1 + read-write + + + RXNEF + RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty. + 3 + 1 + read-only + + + OLDF + Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected, writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected, writing 1 clears THHF, THLF and OLDF flags. + 4 + 1 + read-write + + + THLF + Low threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHL, when the last OLD event occurred - 1: The signal was higher than OLDTHL, when the last OLD event occurred + 5 + 1 + read-only + + + THHF + High threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHH, when the last OLD event occurred - 1: The signal was higher than OLDTHH, when the last OLD event occurred + 6 + 1 + read-only + + + SSOVRF + Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected, writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is detected, writing 1 clears this flag. + 7 + 1 + read-write + + + SCDF + Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected, writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected, writing 1 clears this flag. + 8 + 1 + read-write + + + SATF + Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected, writing 0 has no effect. - 1: Reading 1 means that a saturation is detected, writing 1 clears this flag. + 9 + 1 + read-write + + + CKABF + Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected, writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected, writing 1 clears this flag. + 10 + 1 + read-write + + + RFOVRF + Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected, writing 0 has no effect. - 1: Reading 1 means that reshape filter overrun is detected, writing 1 clears this flag. + 11 + 1 + read-write + + + + + MDF_DFLT3ISR + MDF_DFLT3ISR + This register contains the status flags for each digital filter path. + 0x230 + 0x20 + 0x00000000 + + + FTHF + RXFIFO threshold flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that the RXFIFO threshold is not reached, writing 0 has no effect. - 1: Reading 1 means that the RXFIFO reached the threshold, writing 1 clears this flag. + 0 + 1 + read-only + + + DOVRF + Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected, writing 0 has no effect. - 1: Reading 1 means that an overflow is detected, writing 1 clears this flag. + 1 + 1 + read-write + + + SSDRF + Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on MDF_SNPSxDR, writing 0 has no effect. - 1: Reading 1 means that a new data is available on MDF_SNPSxDR, writing 1 clears this flag. + 2 + 1 + read-write + + + RXNEF + RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty. + 3 + 1 + read-only + + + OLDF + Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected, writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected, writing 1 clears THHF, THLF and OLDF flags. + 4 + 1 + read-write + + + THLF + Low threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHL, when the last OLD event occurred - 1: The signal was higher than OLDTHL, when the last OLD event occurred + 5 + 1 + read-only + + + THHF + High threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHH, when the last OLD event occurred - 1: The signal was higher than OLDTHH, when the last OLD event occurred + 6 + 1 + read-only + + + SSOVRF + Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected, writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is detected, writing 1 clears this flag. + 7 + 1 + read-write + + + SCDF + Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected, writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected, writing 1 clears this flag. + 8 + 1 + read-write + + + SATF + Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected, writing 0 has no effect. - 1: Reading 1 means that a saturation is detected, writing 1 clears this flag. + 9 + 1 + read-write + + + CKABF + Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected, writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected, writing 1 clears this flag. + 10 + 1 + read-write + + + RFOVRF + Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected, writing 0 has no effect. - 1: Reading 1 means that reshape filter overrun is detected, writing 1 clears this flag. + 11 + 1 + read-write + + + + + MDF_DFLT4ISR + MDF_DFLT4ISR + This register contains the status flags for each digital filter path. + 0x2B0 + 0x20 + 0x00000000 + + + FTHF + RXFIFO threshold flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that the RXFIFO threshold is not reached, writing 0 has no effect. - 1: Reading 1 means that the RXFIFO reached the threshold, writing 1 clears this flag. + 0 + 1 + read-only + + + DOVRF + Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected, writing 0 has no effect. - 1: Reading 1 means that an overflow is detected, writing 1 clears this flag. + 1 + 1 + read-write + + + SSDRF + Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on MDF_SNPSxDR, writing 0 has no effect. - 1: Reading 1 means that a new data is available on MDF_SNPSxDR, writing 1 clears this flag. + 2 + 1 + read-write + + + RXNEF + RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty. + 3 + 1 + read-only + + + OLDF + Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected, writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected, writing 1 clears THHF, THLF and OLDF flags. + 4 + 1 + read-write + + + THLF + Low threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHL, when the last OLD event occurred - 1: The signal was higher than OLDTHL, when the last OLD event occurred + 5 + 1 + read-only + + + THHF + High threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHH, when the last OLD event occurred - 1: The signal was higher than OLDTHH, when the last OLD event occurred + 6 + 1 + read-only + + + SSOVRF + Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected, writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is detected, writing 1 clears this flag. + 7 + 1 + read-write + + + SCDF + Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected, writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected, writing 1 clears this flag. + 8 + 1 + read-write + + + SATF + Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected, writing 0 has no effect. - 1: Reading 1 means that a saturation is detected, writing 1 clears this flag. + 9 + 1 + read-write + + + CKABF + Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected, writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected, writing 1 clears this flag. + 10 + 1 + read-write + + + RFOVRF + Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected, writing 0 has no effect. - 1: Reading 1 means that reshape filter overrun is detected, writing 1 clears this flag. + 11 + 1 + read-write + + + + + MDF_DFLT5ISR + MDF_DFLT5ISR + This register contains the status flags for each digital filter path. + 0x330 + 0x20 + 0x00000000 + + + FTHF + RXFIFO threshold flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that the RXFIFO threshold is not reached, writing 0 has no effect. - 1: Reading 1 means that the RXFIFO reached the threshold, writing 1 clears this flag. + 0 + 1 + read-only + + + DOVRF + Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected, writing 0 has no effect. - 1: Reading 1 means that an overflow is detected, writing 1 clears this flag. + 1 + 1 + read-write + + + SSDRF + Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on MDF_SNPSxDR, writing 0 has no effect. - 1: Reading 1 means that a new data is available on MDF_SNPSxDR, writing 1 clears this flag. + 2 + 1 + read-write + + + RXNEF + RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty. + 3 + 1 + read-only + + + OLDF + Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected, writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected, writing 1 clears THHF, THLF and OLDF flags. + 4 + 1 + read-write + + + THLF + Low threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHL, when the last OLD event occurred - 1: The signal was higher than OLDTHL, when the last OLD event occurred + 5 + 1 + read-only + + + THHF + High threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHH, when the last OLD event occurred - 1: The signal was higher than OLDTHH, when the last OLD event occurred + 6 + 1 + read-only + + + SSOVRF + Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected, writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is detected, writing 1 clears this flag. + 7 + 1 + read-write + + + SCDF + Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected, writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected, writing 1 clears this flag. + 8 + 1 + read-write + + + SATF + Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected, writing 0 has no effect. - 1: Reading 1 means that a saturation is detected, writing 1 clears this flag. + 9 + 1 + read-write + + + CKABF + Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected, writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected, writing 1 clears this flag. + 10 + 1 + read-write + + + RFOVRF + Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected, writing 0 has no effect. - 1: Reading 1 means that reshape filter overrun is detected, writing 1 clears this flag. + 11 + 1 + read-write + + + + + MDF_OEC0CR + MDF_OEC0CR + This register contains the offset compensation value. + 0xB4 + 0x20 + read-write + 0x00000000 + + + OFFSET + Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied, this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the application on the current offset value. OFFSET[25:0] represents the value to be subtracted to the signal before going to the SCALE. + 0 + 26 + read-write + + + + + MDF_OEC1CR + MDF_OEC1CR + This register contains the offset compensation value. + 0x134 + 0x20 + read-write + 0x00000000 + + + OFFSET + Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied, this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the application on the current offset value. OFFSET[25:0] represents the value to be subtracted to the signal before going to the SCALE. + 0 + 26 + read-write + + + + + MDF_OEC2CR + MDF_OEC2CR + This register contains the offset compensation value. + 0x1B4 + 0x20 + read-write + 0x00000000 + + + OFFSET + Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied, this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the application on the current offset value. OFFSET[25:0] represents the value to be subtracted to the signal before going to the SCALE. + 0 + 26 + read-write + + + + + MDF_OEC3CR + MDF_OEC3CR + This register contains the offset compensation value. + 0x234 + 0x20 + read-write + 0x00000000 + + + OFFSET + Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied, this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the application on the current offset value. OFFSET[25:0] represents the value to be subtracted to the signal before going to the SCALE. + 0 + 26 + read-write + + + + + MDF_OEC4CR + MDF_OEC4CR + This register contains the offset compensation value. + 0x2B4 + 0x20 + read-write + 0x00000000 + + + OFFSET + Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied, this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the application on the current offset value. OFFSET[25:0] represents the value to be subtracted to the signal before going to the SCALE. + 0 + 26 + read-write + + + + + MDF_OEC5CR + MDF_OEC5CR + This register contains the offset compensation value. + 0x334 + 0x20 + read-write + 0x00000000 + + + OFFSET + Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied, this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the application on the current offset value. OFFSET[25:0] represents the value to be subtracted to the signal before going to the SCALE. + 0 + 26 + read-write + + + + + MDF_SNPS0DR + MDF_SNPS0DR + This register is used to read the data processed by each digital filter in snapshot mode. + 0xEC + 0x20 + read-only + 0x00000000 + + + MCICDC + Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT) + 0 + 9 + + + EXTSDR + Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter, If SNPSFMT = 1 , this field contains the INT accumulator counter value at the moment of the last trigger event occurs (INT_CNT). + 9 + 7 + + + SDR + Contains the 16 MSB of the last valid data processed by the digital filter. + 16 + 16 + + + + + MDF_SNPS1DR + MDF_SNPS1DR + This register is used to read the data processed by each digital filter in snapshot mode. + 0x16C + 0x20 + read-only + 0x00000000 + + + MCICDC + Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT) + 0 + 9 + + + EXTSDR + Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter, If SNPSFMT = 1 , this field contains the INT accumulator counter value at the moment of the last trigger event occurs (INT_CNT). + 9 + 7 + + + SDR + Contains the 16 MSB of the last valid data processed by the digital filter. + 16 + 16 + + + + + MDF_SNPS2DR + MDF_SNPS2DR + This register is used to read the data processed by each digital filter in snapshot mode. + 0x1EC + 0x20 + read-only + 0x00000000 + + + MCICDC + Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT) + 0 + 9 + + + EXTSDR + Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter, If SNPSFMT = 1 , this field contains the INT accumulator counter value at the moment of the last trigger event occurs (INT_CNT). + 9 + 7 + + + SDR + Contains the 16 MSB of the last valid data processed by the digital filter. + 16 + 16 + + + + + MDF_SNPS3DR + MDF_SNPS3DR + This register is used to read the data processed by each digital filter in snapshot mode. + 0x26C + 0x20 + read-only + 0x00000000 + + + MCICDC + Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT) + 0 + 9 + + + EXTSDR + Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter, If SNPSFMT = 1 , this field contains the INT accumulator counter value at the moment of the last trigger event occurs (INT_CNT). + 9 + 7 + + + SDR + Contains the 16 MSB of the last valid data processed by the digital filter. + 16 + 16 + + + + + MDF_SNPS4DR + MDF_SNPS4DR + This register is used to read the data processed by each digital filter in snapshot mode. + 0x2EC + 0x20 + read-only + 0x00000000 + + + MCICDC + Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT) + 0 + 9 + + + EXTSDR + Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter, If SNPSFMT = 1 , this field contains the INT accumulator counter value at the moment of the last trigger event occurs (INT_CNT). + 9 + 7 + + + SDR + Contains the 16 MSB of the last valid data processed by the digital filter. + 16 + 16 + + + + + MDF_SNPS5DR + MDF_SNPS5DR + This register is used to read the data processed by each digital filter in snapshot mode. + 0x36C + 0x20 + read-only + 0x00000000 + + + MCICDC + Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT) + 0 + 9 + + + EXTSDR + Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter, If SNPSFMT = 1 , this field contains the INT accumulator counter value at the moment of the last trigger event occurs (INT_CNT). + 9 + 7 + + + SDR + Contains the 16 MSB of the last valid data processed by the digital filter. + 16 + 16 + + + + + MDF_DFLT0DR + MDF_DFLT0DR + This register is used to read the data processed by each digital filter. + 0xF0 + 0x20 + read-only + 0x00000000 + + + DR + Data processed by digital filter. + 8 + 24 + + + + + MDF_DFLT1DR + MDF_DFLT1DR + This register is used to read the data processed by each digital filter. + 0x170 + 0x20 + read-only + 0x00000000 + + + DR + Data processed by digital filter. + 8 + 24 + + + + + MDF_DFLT2DR + MDF_DFLT2DR + This register is used to read the data processed by each digital filter. + 0x1F0 + 0x20 + read-only + 0x00000000 + + + DR + Data processed by digital filter. + 8 + 24 + + + + + MDF_DFLT3DR + MDF_DFLT3DR + This register is used to read the data processed by each digital filter. + 0x270 + 0x20 + read-only + 0x00000000 + + + DR + Data processed by digital filter. + 8 + 24 + + + + + MDF_DFLT4DR + MDF_DFLT4DR + This register is used to read the data processed by each digital filter. + 0x2F0 + 0x20 + read-only + 0x00000000 + + + DR + Data processed by digital filter. + 8 + 24 + + + + + MDF_DFLT5DR + MDF_DFLT5DR + This register is used to read the data processed by each digital filter. + 0x370 + 0x20 + read-only + 0x00000000 + + + DR + Data processed by digital filter. + 8 + 24 + + + + + + + SEC_MDF1 + DCB->DSCSR->CDS == 0 + 0x50025000 + + + OCTOSPI1 + OctoSPI + OctoSPI + 0x420D1400 + + 0x0 + 0x400 + registers + + + OCTOSPI1 + OCTOSPI1 global interrupt + 076 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + FMODE + Functional mode + 28 + 2 + + + PMM + Polling match mode + 23 + 1 + + + APMS + Automatic poll mode stop + 22 + 1 + + + TOIE + TimeOut interrupt enable + 20 + 1 + + + SMIE + Status match interrupt + enable + 19 + 1 + + + FTIE + FIFO threshold interrupt + enable + 18 + 1 + + + TCIE + Transfer complete interrupt + enable + 17 + 1 + + + TEIE + Transfer error interrupt + enable + 16 + 1 + + + FTHRES + IFO threshold level + 8 + 5 + + + FSEL + FLASH memory selection + 7 + 1 + + + DQM + Dual-quad mode + 6 + 1 + + + TCEN + Timeout counter enable + 3 + 1 + + + DMAEN + DMA enable + 2 + 1 + + + ABORT + Abort request + 1 + 1 + + + EN + Enable + 0 + 1 + + + + + DCR1 + DCR1 + device configuration register 1 + 0x8 + 0x20 + read-write + 0x00000000 + + + CKMODE + Mode 0 / mode 3 + 0 + 1 + + + FRCK + Free running clock + 1 + 1 + + + DLYBYP + Delay block bypass + 3 + 1 + + + CSHT + Chip-select high time + 8 + 6 + + + DEVSIZE + Device size + 16 + 5 + + + MTYP + Memory type + 24 + 3 + + + + + DCR2 + DCR2 + device configuration register 2 + 0xC + 0x20 + read-write + 0x00000000 + + + PRESCALER + Clock prescaler + 0 + 8 + + + WRAPSIZE + Wrap size + 16 + 3 + + + + + DCR3 + DCR3 + device configuration register 3 + 0x10 + 0x20 + read-write + 0x00000000 + + + MAXTRAN + Maximum transfer + 0 + 8 + + + CSBOUND + CS boundary + 16 + 5 + + + + + DCR4 + DCR4 + DCR4 + 0x14 + 0x20 + read-write + 0x00000000 + + + REFRESH + Refresh rate + 0 + 32 + + + + + SR + SR + status register + 0x20 + 0x20 + read-only + 0x00000000 + + + TEF + Transfer error flag + 0 + 1 + + + TCF + transfer complete flag + 1 + 1 + + + FTF + FIFO threshold flag + 2 + 1 + + + SMF + status match flag + 3 + 1 + + + TOF + timeout flag + 4 + 1 + + + BUSY + BUSY + 5 + 1 + + + FLEVEL + FIFO level + 8 + 6 + + + + + FCR + FCR + flag clear register + 0x24 + 0x20 + write-only + 0x00000000 + + + CTEF + Clear Transfer error flag + 0 + 1 + + + CTCF + Clear transfer complete flag + 1 + 1 + + + CSMF + Clear status match flag + 3 + 1 + + + CTOF + Clear timeout flag + 4 + 1 + + + + + DLR + DLR + data length register + 0x40 + 0x20 + read-write + 0x00000000 + + + DL + Data length + 0 + 32 + + + + + AR + AR + address register + 0x48 + 0x20 + read-write + 0x00000000 + + + ADDRESS + ADDRESS + 0 + 32 + + + + + DR + DR + data register + 0x50 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + PSMKR + PSMKR + polling status mask register + 0x80 + 0x20 + read-write + 0x00000000 + + + MASK + Status MASK + 0 + 32 + + + + + PSMAR + PSMAR + polling status match register + 0x88 + 0x20 + read-write + 0x00000000 + + + MATCH + Status match + 0 + 32 + + + + + PIR + PIR + polling interval register + 0x90 + 0x20 + read-write + 0x00000000 + + + INTERVAL + polling interval + 0 + 16 + + + + + CCR + CCR + communication configuration + register + 0x100 + 0x20 + read-write + 0x00000000 + + + IMODE + Instruction mode + 0 + 3 + + + IDTR + Instruction double transfer + rate + 3 + 1 + + + ISIZE + Instruction size + 4 + 2 + + + ADMODE + Address mode + 8 + 3 + + + ADDTR + Address double transfer + rate + 11 + 1 + + + ADSIZE + Address size + 12 + 2 + + + ABMODE + Alternate byte mode + 16 + 3 + + + ABDTR + Alternate bytes double transfer + rate + 19 + 1 + + + ABSIZE + Alternate bytes size + 20 + 2 + + + DMODE + Data mode + 24 + 3 + + + DDTR + Alternate bytes double transfer + rate + 27 + 1 + + + DQSE + DQS enable + 29 + 1 + + + SIOO + Send instruction only once + mode + 31 + 1 + + + + + TCR + TCR + timing configuration register + 0x108 + 0x20 + read-write + 0x00000000 + + + DCYC + Number of dummy cycles + 0 + 5 + + + DHQC + Delay hold quarter cycle + 28 + 1 + + + SSHIFT + Sample shift + 30 + 1 + + + + + IR + IR + instruction register + 0x110 + 0x20 + read-write + 0x00000000 + + + INSTRUCTION + INSTRUCTION + 0 + 32 + + + + + ABR + ABR + alternate bytes register + 0x120 + 0x20 + read-write + 0x00000000 + + + ALTERNATE + Alternate bytes + 0 + 32 + + + + + LPTR + LPTR + low-power timeout register + 0x130 + 0x20 + read-write + 0x00000000 + + + TIMEOUT + Timeout period + 0 + 16 + + + + + WPCCR + WPCCR + wrap communication configuration + register + 0x140 + 0x20 + read-write + 0x00000000 + + + IMODE + Instruction mode + 0 + 3 + + + IDTR + Instruction double transfer + rate + 3 + 1 + + + ISIZE + Instruction size + 4 + 2 + + + ADMODE + Address mode + 8 + 3 + + + ADDTR + Address double transfer + rate + 11 + 1 + + + ADSIZE + Address size + 12 + 2 + + + ABMODE + Alternate byte mode + 16 + 3 + + + ABDTR + Alternate bytes double transfer + rate + 19 + 1 + + + ABSIZE + Alternate bytes size + 20 + 2 + + + DMODE + Data mode + 24 + 3 + + + DDTR + alternate bytes double transfer + rate + 27 + 1 + + + DQSE + DQS enable + 29 + 1 + + + + + WPTCR + WPTCR + wrap timing configuration + register + 0x148 + 0x20 + read-write + 0x00000000 + + + DCYC + Number of dummy cycles + 0 + 5 + + + DHQC + Delay hold quarter cycle + 28 + 1 + + + SSHIFT + Sample shift + 30 + 1 + + + + + WPIR + WPIR + wrap instruction register + 0x150 + 0x20 + read-write + 0x00000000 + + + INSTRUCTION + INSTRUCTION + 0 + 32 + + + + + WPABR + WPABR + wrap alternate bytes register + 0x160 + 0x20 + read-write + 0x00000000 + + + ALTERNATE + Alternate bytes + 0 + 32 + + + + + WCCR + WCCR + write communication configuration register + 0x180 + 0x20 + read-write + 0x00000000 + + + IMODE + Instruction mode + 0 + 3 + + + IDTR + Instruction double transfer + rate + 3 + 1 + + + ISIZE + Instruction size + 4 + 2 + + + ADMODE + Address mode + 8 + 3 + + + ADDTR + Address double transfer + rate + 11 + 1 + + + ADSIZE + Address size + 12 + 2 + + + ABMODE + Alternate byte mode + 16 + 3 + + + ABDTR + Alternate bytes double transfer + rate + 19 + 1 + + + ABSIZE + Alternate bytes size + 20 + 2 + + + DMODE + Data mode + 24 + 3 + + + DDTR + alternate bytes double transfer + rate + 27 + 1 + + + DQSE + DQS enable + 29 + 1 + + + + + WTCR + WTCR + write timing configuration register + 0x188 + 0x20 + read-write + 0x00000000 + + + DCYC + Number of dummy cycles + 0 + 5 + + + + + WIR + WIR + write instruction register + 0x190 + 0x20 + read-write + 0x00000000 + + + INSTRUCTION + INSTRUCTION + 0 + 32 + + + + + WABR + WABR + write alternate bytes register + 0x1A0 + 0x20 + read-write + 0x00000000 + + + ALTERNATE + ALTERNATE + 0 + 32 + + + + + HLCR + HLCR + HyperBus latency configuration + register + 0x200 + 0x20 + read-write + 0x00000000 + + + LM + Latency mode + 0 + 1 + + + WZL + Write zero latency + 1 + 1 + + + TACC + Access time + 8 + 8 + + + TRWR + Read write recovery time + 16 + 8 + + + + + + + SEC_OCTOSPI1 + DCB->DSCSR->CDS == 0 + 0x520D1400 + + + OCTOSPI2 + 0x420D2400 + + OCTOSPI2 + OCTOSPI2 global interrupt + 120 + + + + SEC_OCTOSPI2 + DCB->DSCSR->CDS == 0 + 0x520D2400 + + + OCTOSPIM + OCTOSPI I/O manager + OctoSPI + 0x420C4000 + + 0x0 + 0x400 + registers + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + REQ2ACK_TIME + REQ to ACK time + 16 + 8 + + + MUXEN + Multiplexed mode enable + 0 + 1 + + + + + P1CR + P1CR + OCTOSPI I/O manager Port 1 configuration register + 0x4 + 0x20 + read-write + 0x03010111 + + + IOHSRC + IOHSR + 25 + 2 + + + IOHEN + IOHEN + 24 + 1 + + + IOLSRC + IOLSRC + 17 + 2 + + + IOLEN + IOLEN + 16 + 1 + + + NCSSRC + NCSSRC + 9 + 1 + + + NCSEN + NCSEN + 8 + 1 + + + DQSSRC + DQSSRC + 5 + 1 + + + DQSEN + DQSEN + 4 + 1 + + + CLKSRC + CLKSRC + 1 + 1 + + + CLKEN + CLKEN + 0 + 1 + + + + + P2CR + P2CR + OCTOSPI I/O manager Port 2 configuration register + 0x8 + 0x20 + read-write + 0x07050333 + + + IOHSRC + IOHSR + 25 + 2 + + + IOHEN + IOHEN + 24 + 1 + + + IOLSRC + IOLSRC + 17 + 2 + + + IOLEN + IOLEN + 16 + 1 + + + NCSSRC + NCSSRC + 9 + 1 + + + NCSEN + NCSEN + 8 + 1 + + + DQSSRC + DQSSRC + 5 + 1 + + + DQSEN + DQSEN + 4 + 1 + + + CLKSRC + CLKSRC + 1 + 1 + + + CLKEN + CLKEN + 0 + 1 + + + + + + + SEC_OCTOSPIM + DCB->DSCSR->CDS == 0 + 0x520C4000 + + + OPAMP + Operational amplifiers + OPAMP + 0x46005000 + + 0x0 + 0x400 + registers + + + + OPAMP1_CSR + OPAMP1_CSR + OPAMP1 control/status register + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OPAEN + OPAMP enable + 0 + 1 + read-write + + + B_0x0 + OPAMP disabled + 0x0 + + + B_0x1 + OPAMP enabled + 0x1 + + + + + OPALPM + OPAMP low-power mode +The OPAMP must be disabled to change this configuration. + 1 + 1 + read-write + + + B_0x0 + normal mode + 0x0 + + + B_0x1 + low-power mode + 0x1 + + + + + OPAMODE + OPAMP PGA mode +00 and 01: internal PGA disabled + 2 + 2 + read-write + + + B_0x2 + internal PGA enabled, gain programmed in PGA_GAIN + 0x2 + + + B_0x3 + internal follower + 0x3 + + + + + PGA_GAIN + OPAMP programmable amplifier gain value + 4 + 2 + read-write + + + B_0x0 + internal PGA gain 2 + 0x0 + + + B_0x1 + internal PGA gain 4 + 0x1 + + + B_0x2 + internal PGA gain 8 + 0x2 + + + B_0x3 + internal PGA gain 16 + 0x3 + + + + + VM_SEL + Inverting input selection +These bits are used only when OPAMODE = 00, 01 or 10. +1x: inverting input not externally connected + 8 + 2 + read-write + + + B_0x0 + GPIO connected to VINM (valid also in PGA mode for filtering) + 0x0 + + + B_0x1 + dedicated low-leakage input connected to VINM (valid also in PGA mode for filtering) + 0x1 + + + + + VP_SEL + Non-inverted input selection + 10 + 1 + read-write + + + B_0x0 + GPIO connected to VINP + 0x0 + + + B_0x1 + DAC connected to VINP + 0x1 + + + + + CALON + Calibration mode enable + 12 + 1 + read-write + + + B_0x0 + normal mode + 0x0 + + + B_0x1 + calibration mode (all switches opened by hardware) + 0x1 + + + + + CALSEL + Calibration selection + 13 + 1 + read-write + + + B_0x0 + NMOS calibration (200�mV applied on OPAMP inputs) + 0x0 + + + B_0x1 + PMOS calibration (V<sub>DDA </sub>- 200 mV applied on OPAMP inputs) + 0x1 + + + + + USERTRIM + ‘factory’ or ‘user’ offset trimmed values selection +This bit is active for normal and low-power modes. + 14 + 1 + read-write + + + B_0x0 + ‘factory’ trim code used + 0x0 + + + B_0x1 + ‘user’ trim code used + 0x1 + + + + + CALOUT + OPAMP calibration output +During the calibration mode, the offset is trimmed when this signal toggles. + 15 + 1 + read-only + + + OPAHSM + OPAMP high-speed mode +This bit is effective for both normal and low-power modes. + 30 + 1 + read-write + + + B_0x0 + normal mode (standard slew rate) + 0x0 + + + B_0x1 + increased consumption to improve the slew rate + 0x1 + + + + + OPA_RANGE + OPAMP range setting +This bit must be set before enabling the OPAMP and this bit affects all OPAMP instances. + 31 + 1 + read-write + + + B_0x0 + reserved + 0x0 + + + B_0x1 + OPAMP range set + 0x1 + + + + + + + OPAMP1_OTR + OPAMP1_OTR + OPAMP1 offset trimming register in normal mode + 0x04 + 0x20 + 0x00000000 + 0xFFFF0000 + + + TRIMOFFSETN + Trim for NMOS differential pairs + 0 + 5 + read-write + + + TRIMOFFSETP + Trim for PMOS differential pairs + 8 + 5 + read-write + + + + + OPAMP1_LPOTR + OPAMP1_LPOTR + OPAMP1 offset trimming register in low-power mode + 0x08 + 0x20 + 0x00000000 + 0xFFFF0000 + + + TRIMLPOFFSETN + Low-power mode trim for NMOS differential pairs + 0 + 5 + read-write + + + TRIMLPOFFSETP + Low-power mode trim for PMOS differential pairs + 8 + 5 + read-write + + + + + OPAMP2_CRS + OPAMP2_CRS + OPAMP2 control/status register + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OPAEN + OPAMP enable + 0 + 1 + read-write + + + B_0x0 + OPAMP disabled + 0x0 + + + B_0x1 + OPAMP enabled + 0x1 + + + + + OPALPM + OPAMP low-power mode +The OPAMP must be disabled to change this configuration. + 1 + 1 + read-write + + + B_0x0 + normal mode + 0x0 + + + B_0x1 + low-power mode + 0x1 + + + + + OPAMODE + OPAMP PGA mode +00 and 01: internal PGA disabled + 2 + 2 + read-write + + + B_0x2 + internal PGA enabled, gain programmed in PGA_GAIN + 0x2 + + + B_0x3 + internal follower + 0x3 + + + + + PGA_GAIN + OPAMP programmable amplifier gain value + 4 + 2 + read-write + + + B_0x0 + internal PGA gain 2 + 0x0 + + + B_0x1 + internal PGA gain 4 + 0x1 + + + B_0x2 + internal PGA gain 8 + 0x2 + + + B_0x3 + internal PGA gain 16 + 0x3 + + + + + VM_SEL + Inverting input selection +These bits are used only when OPAMODE = 00, 01 or 10. +in PGA mode for filtering) +1x: inverting input not externally connected + 8 + 2 + read-write + + + B_0x0 + GPIO connected to VINM (valid also in PGA mode for filtering) + 0x0 + + + B_0x1 + dedicated low-leakage input connected to VINM (valid also + 0x1 + + + + + VP_SEL + Non inverted input selection + 10 + 1 + read-write + + + B_0x0 + GPIO connected to VINP + 0x0 + + + B_0x1 + DAC connected to VINP + 0x1 + + + + + CALON + Calibration mode enable + 12 + 1 + read-write + + + B_0x0 + normal mode + 0x0 + + + B_0x1 + calibration mode (all switches opened by hardware) + 0x1 + + + + + CALSEL + Calibration selection + 13 + 1 + read-write + + + B_0x0 + NMOS calibration (200 mV applied on OPAMP inputs) + 0x0 + + + B_0x1 + PMOS calibration (V<sub>DDA </sub>- 200 mV applied on OPAMP inputs) + 0x1 + + + + + USERTRIM + ‘factory’ or ‘user’ offset trimmed values selection +This bit is active for normal and low-power modes. + 14 + 1 + read-write + + + B_0x0 + ‘factory’ trim code used + 0x0 + + + B_0x1 + ‘user’ trim code used + 0x1 + + + + + CALOUT + OPAMP calibration output +During calibration mode, the offset is trimmed when this signal toggles. + 15 + 1 + read-only + + + OPAHSM + OPAMP high-speed mode +This bit is effective for both normal and high-speed modes. + 30 + 1 + read-write + + + B_0x0 + normal mode (standard slew rate) + 0x0 + + + B_0x1 + increased consumption to improve the slew rate + 0x1 + + + + + + + OPAMP2_OTR + OPAMP2_OTR + OPAMP2 offset trimming register in normal mode + 0x14 + 0x20 + 0x00000000 + 0xFFFF0000 + + + TRIMOFFSETN + Trim for NMOS differential pairs + 0 + 5 + read-write + + + TRIMOFFSETP + Trim for PMOS differential pairs + 8 + 5 + read-write + + + + + OPAMP2_LPOTR + OPAMP2_LPOTR + OPAMP2 offset trimming register in low-power mode + 0x18 + 0x20 + 0x00000000 + 0xFFFF0000 + + + TRIMLPOFFSETN + Low-power mode trim for NMOS differential pairs + 0 + 5 + read-write + + + TRIMLPOFFSETP + Low-power mode trim for PMOS differential pairs + 8 + 5 + read-write + + + + + + + SEC_OPAMP + DCB->DSCSR->CDS == 0 + 0x56005000 + + + OTFDEC1 + On-The-Fly Decryption engine + OTFDEC + 0x420C5000 + + 0x0 + 0x400 + registers + + + OTFDEC1 + OTFDEC1 secure global interrupt + 108 + + + + CR + CR + OTFDEC control register + 0x0 + 0x20 + read-write + 0x00000000 + + + ENC + Encryption mode bit + 0 + 1 + + + + + PRIVCFGR + PRIVCFGR + OTFDEC privileged access control configuration register + 0x10 + 0x20 + read-write + 0x00000000 + + + PRIV + Encryption mode bit + 0 + 1 + + + + + R1CFGR + R1CFGR + OTFDEC region x configuration + register + 0x20 + 0x20 + 0x00000000 + + + REG_EN + region on-the-fly decryption + enable + 0 + 1 + read-write + + + CONFIGLOCK + region config lock + 1 + 1 + read-write + + + KEYLOCK + region key lock + 2 + 1 + read-write + + + MODE + operating mode + 4 + 2 + read-write + + + KEYCRC + region key 8-bit CRC + 8 + 8 + read-only + + + REG1_VERSION + region firmware version + 16 + 16 + read-write + + + + + R2CFGR + R2CFGR + OTFDEC region x configuration + register + 0x50 + 0x20 + 0x00000000 + + + REG_EN + region on-the-fly decryption + enable + 0 + 1 + read-write + + + CONFIGLOCK + region config lock + 1 + 1 + read-write + + + KEYLOCK + region key lock + 2 + 1 + read-write + + + MODE + operating mode + 4 + 2 + read-write + + + KEYCRC + region key 8-bit CRC + 8 + 8 + read-only + + + REG2_VERSION + region firmware version + 16 + 16 + read-write + + + + + R3CFGR + R3CFGR + OTFDEC region x configuration + register + 0x80 + 0x20 + 0x00000000 + + + REG_EN + region on-the-fly decryption + enable + 0 + 1 + read-write + + + CONFIGLOCK + region config lock + 1 + 1 + read-write + + + KEYLOCK + region key lock + 2 + 1 + read-write + + + MODE + operating mode + 4 + 2 + read-write + + + KEYCRC + region key 8-bit CRC + 8 + 8 + read-only + + + REG3_VERSION + region firmware version + 16 + 16 + read-write + + + + + R4CFGR + R4CFGR + OTFDEC region x configuration + register + 0xB0 + 0x20 + 0x00000000 + + + REG_EN + region on-the-fly decryption + enable + 0 + 1 + read-write + + + CONFIGLOCK + region config lock + 1 + 1 + read-write + + + KEYLOCK + region key lock + 2 + 1 + read-write + + + MODE + operating mode + 4 + 2 + read-write + + + KEYCRC + region key 8-bit CRC + 8 + 8 + read-only + + + REG4_VERSION + region firmware version + 16 + 16 + read-write + + + + + R1STARTADDR + R1STARTADDR + OTFDEC region x start address + register + 0x24 + 0x20 + read-write + 0x00000000 + + + REG1_START_ADDR + Region AXI start address + 0 + 32 + + + + + R2STARTADDR + R2STARTADDR + OTFDEC region x start address + register + 0x54 + 0x20 + read-write + 0x00000000 + + + REG2_START_ADDR + Region AXI start address + 0 + 32 + + + + + R3STARTADDR + R3STARTADDR + OTFDEC region x start address + register + 0x84 + 0x20 + read-write + 0x00000000 + + + REG3_START_ADDR + Region AXI start address + 0 + 32 + + + + + R4STARTADDR + R4STARTADDR + OTFDEC region x start address + register + 0xB4 + 0x20 + read-write + 0x00000000 + + + REG4_START_ADDR + Region AXI start address + 0 + 32 + + + + + R1ENDADDR + R1ENDADDR + OTFDEC region x end address + register + 0x28 + 0x20 + read-write + 0x00000FFF + + + REG1_END_ADDR + Region AXI end address + 0 + 32 + + + + + R2ENDADDR + R2ENDADDR + OTFDEC region x end address + register + 0x58 + 0x20 + read-write + 0x00000FFF + + + REG2_END_ADDR + Region AXI end address + 0 + 32 + + + + + R3ENDADDR + R3ENDADDR + OTFDEC region x end address + register + 0x88 + 0x20 + read-write + 0x00000FFF + + + REG3_END_ADDR + Region AXI end address + 0 + 32 + + + + + R4ENDADDR + R4ENDADDR + OTFDEC region x end address + register + 0xB8 + 0x20 + read-write + 0x00000FFF + + + REG4_END_ADDR + Region AXI end address + 0 + 32 + + + + + R1NONCER0 + R1NONCER0 + OTFDEC region x nonce register + 0 + 0x2C + 0x20 + read-write + 0x00000000 + + + REG1_NONCE + REG1_NONCE + 0 + 32 + + + + + R2NONCER0 + R2NONCER0 + OTFDEC region x nonce register + 0 + 0x5C + 0x20 + read-write + 0x00000000 + + + REG2_NONCE + REG2_NONCE + 0 + 32 + + + + + R3NONCER0 + R3NONCER0 + OTFDEC region x nonce register + 0 + R4ENDADDR + 0x8C + 0x20 + read-write + 0x00000000 + + + REG3_NONCE + REG3_NONCE + 0 + 32 + + + + + R4NONCER0 + R4NONCER0 + OTFDEC region x nonce register + 0 + 0xBC + 0x20 + read-write + 0x00000000 + + + REG4_NONCE + REG4_NONCE + 0 + 32 + + + + + R1NONCER1 + R1NONCER1 + OTFDEC region x nonce register + 1 + 0x30 + 0x20 + read-write + 0x00000000 + + + REG1_NONCE + Region nonce + 0 + 32 + + + + + R2NONCER1 + R2NONCER1 + OTFDEC region x nonce register + 1 + 0x60 + 0x20 + read-write + 0x00000000 + + + REG2_NONCE + Region nonce, bits + [63:32]REGx_NONCE[63:32] + 0 + 32 + + + + + R3NONCER1 + R3NONCER1 + OTFDEC region x nonce register + 1 + 0x90 + 0x20 + read-write + 0x00000000 + + + REG3_NONCE + REG3_NONCE + 0 + 32 + + + + + R4NONCER1 + R4NONCER1 + OTFDEC region x nonce register + 1 + 0xC0 + 0x20 + read-write + 0x00000000 + + + REG4_NONCE + REG4_NONCE + 0 + 32 + + + + + R1KEYR0 + R1KEYR0 + OTFDEC region x key register 0 + 0x34 + 0x20 + write-only + 0x00000000 + + + REG1_KEY + REG1_KEY + 0 + 32 + + + + + R2KEYR0 + R2KEYR0 + OTFDEC region x key register 0 + 0x64 + 0x20 + write-only + 0x00000000 + + + REG2_KEY + REG2_KEY + 0 + 32 + + + + + R3KEYR0 + R3KEYR0 + OTFDEC region x key register 0 + 0x94 + 0x20 + write-only + 0x00000000 + + + REG3_KEY + REG3_KEY + 0 + 32 + + + + + R4KEYR0 + R4KEYR0 + OTFDEC region x key register 0 + 0xC4 + 0x20 + write-only + 0x00000000 + + + REG4_KEY + REG4_KEY + 0 + 32 + + + + + R1KEYR1 + R1KEYR1 + OTFDEC region x key register 1 + 0x38 + 0x20 + write-only + 0x00000000 + + + REG1_KEY + REG1_KEY + 0 + 32 + + + + + R2KEYR1 + R2KEYR1 + OTFDEC region x key register 1 + 0x68 + 0x20 + write-only + 0x00000000 + + + REG2_KEY + REG2_KEY + 0 + 32 + + + + + R3KEYR1 + R3KEYR1 + OTFDEC region x key register 1 + 0x98 + 0x20 + write-only + 0x00000000 + + + REG3_KEY + REG3_KEY + 0 + 32 + + + + + R4KEYR1 + R4KEYR1 + OTFDEC region x key register 1 + 0xC8 + 0x20 + write-only + 0x00000000 + + + REG4_KEY + REG4_KEY + 0 + 32 + + + + + R1KEYR2 + R1KEYR2 + OTFDEC region x key register 2 + 0x3C + 0x20 + write-only + 0x00000000 + + + REG1_KEY + REG1_KEY + 0 + 32 + + + + + R2KEYR2 + R2KEYR2 + OTFDEC region x key register 2 + 0x6C + 0x20 + write-only + 0x00000000 + + + REG2_KEY_ + REG2_KEY_ + 0 + 32 + + + + + R3KEYR2 + R3KEYR2 + OTFDEC region x key register 2 + 0x9C + 0x20 + write-only + 0x00000000 + + + REG3_KEY + REG3_KEY + 0 + 32 + + + + + R4KEYR2 + R4KEYR2 + OTFDEC region x key register 2 + 0xCC + 0x20 + write-only + 0x00000000 + + + REG4_KEY + REG4_KEY + 0 + 32 + + + + + R1KEYR3 + R1KEYR3 + OTFDEC region x key register 3 + 0x40 + 0x20 + write-only + 0x00000000 + + + REG1_KEY + REG1_KEY + 0 + 32 + + + + + R2KEYR3 + R2KEYR3 + OTFDEC region x key register 3 + 0x70 + 0x20 + write-only + 0x00000000 + + + REG2_KEY + REG2_KEY + 0 + 32 + + + + + R3KEYR3 + R3KEYR3 + OTFDEC region x key register 3 + 0xA0 + 0x20 + write-only + 0x00000000 + + + REG3_KEY + REG3_KEY + 0 + 32 + + + + + R4KEYR3 + R4KEYR3 + OTFDEC region x key register 3 + 0xD0 + 0x20 + write-only + 0x00000000 + + + REG4_KEY + REG4_KEY + 0 + 32 + + + + + ISR + ISR + OTFDEC interrupt status + register + 0x300 + 0x20 + read-only + 0x00000000 + + + SEIF + Security Error Interrupt Flag + status + 0 + 1 + + + XONEIF + Execute-only execute-Never Error + Interrupt Flag status + 1 + 1 + + + KEIF + Key Error Interrupt Flag + status + 2 + 1 + + + + + ICR + ICR + OTFDEC interrupt clear + register + 0x304 + 0x20 + read-only + 0x00000000 + + + SEIF + SEIF + 0 + 1 + + + XONEIF + Execute-only execute-Never Error + Interrupt Flag clear + 1 + 1 + + + KEIF + KEIF + 2 + 1 + + + + + IER + IER + OTFDEC interrupt enable + register + 0x308 + 0x20 + read-write + 0x00000000 + + + SEIE + Security Error Interrupt + Enable + 0 + 1 + + + XONEIE + XONEIE + 1 + 1 + + + KEIE + KEIE + 2 + 1 + + + + + + + SEC_OTFDEC1 + DCB->DSCSR->CDS == 0 + 0x520C5000 + + + OTFDEC2 + 0x420C5400 + + OTFDEC2 + OTFDEC2 secure global interrupt + 109 + + + + SEC_OTFDEC2 + DCB->DSCSR->CDS == 0 + 0x520C5400 + + + OTG_HS + OTG_HS + OTG_HS + 0x42040000 + + 0x0 + 0x20000 + registers + + + OTG_HS + USB OTG global interrupt + 073 + + + + GOTGCTL + GOTGCTL + The GOTGCTL register controls the behavior and reflects the status of the OTG function of the core. + 0x0 + 0x20 + 0x00010000 + + + SRQSCS + SRQSCS + 0 + 1 + read-only + + + SRQ + SRQ + 1 + 1 + read-write + + + VBVALOEN + VBVALOEN + 2 + 1 + read-write + + + VBVALOVAL + VBVALOVAL + 3 + 1 + read-write + + + AVALOEN + AVALOEN + 4 + 1 + read-write + + + AVALOVAL + AVALOVAL + 5 + 1 + read-write + + + BVALOEN + BVALOEN + 6 + 1 + read-write + + + BVALOVAL + BVALOVAL + 7 + 1 + read-write + + + HNGSCS + HNGSCS + 8 + 1 + read-only + + + HNPRQ + HNPRQ + 9 + 1 + read-write + + + HSHNPEN + HSHNPEN + 10 + 1 + read-write + + + DHNPEN + DHNPEN + 11 + 1 + read-write + + + EHEN + EHEN + 12 + 1 + read-write + + + CIDSTS + CIDSTS + 16 + 1 + read-only + + + DBCT + DBCT + 17 + 1 + read-only + + + ASVLD + ASVLD + 18 + 1 + read-only + + + BSVLD + BSVLD + 19 + 1 + read-only + + + OTGVER + OTGVER + 20 + 1 + read-write + + + CURMOD + CURMOD + 21 + 1 + read-only + + + + + GOTGINT + GOTGINT + The application reads this register whenever there is an OTG interrupt and clears the bits in this register to clear the OTG interrupt. + 0x4 + 0x20 + read-write + 0x00000000 + + + SEDET + SEDET + 2 + 1 + + + SRSSCHG + SRSSCHG + 8 + 1 + + + HNSSCHG + HNSSCHG + 9 + 1 + + + HNGDET + HNGDET + 17 + 1 + + + ADTOCHG + ADTOCHG + 18 + 1 + + + DBCDNE + DBCDNE + 19 + 1 + + + + + GAHBCFG + GAHBCFG + This register can be used to configure the core after power-on or a change in mode. This register mainly contains AHB system-related configuration parameters. Do not change this register after the initial programming. The application must program this register before starting any transactions on either the AHB or the USB. + 0x8 + 0x20 + read-write + 0x00000000 + + + GINTMSK + GINTMSK + 0 + 1 + + + TXFELVL + TXFELVL + 7 + 1 + + + PTXFELVL + PTXFELVL + 8 + 1 + + + + + GUSBCFG + GUSBCFG + This register can be used to configure the core after power-on or a changing to host mode or device mode. It contains USB and USB-PHY related configuration parameters. The application must program this register before starting any transactions on either the AHB or the USB. Do not make changes to this register after the initial programming. + 0xC + 0x20 + 0x00001400 + + + TOCAL + TOCAL + 0 + 3 + read-write + + + PHYSEL + PHYSEL + 6 + 1 + read-only + + + SRPCAP + SRPCAP + 8 + 1 + read-write + + + HNPCAP + HNPCAP + 9 + 1 + read-write + + + TRDT + TRDT + 10 + 4 + read-write + + + PHYLPC + PHYLPC + 15 + 1 + read-write + + + TSDPS + TSDPS + 22 + 1 + read-write + + + FHMOD + FHMOD + 29 + 1 + read-write + + + FDMOD + FDMOD + 30 + 1 + read-write + + + + + GRSTCTL + GRSTCTL + The application uses this register to reset various hardware features inside the core. + 0x10 + 0x20 + 0x80000000 + + + CSRST + CSRST + 0 + 1 + read-only + + + PSRST + PSRST + 1 + 1 + read-write + + + FSRST + FSRST + 2 + 1 + read-write + + + RXFFLSH + RXFFLSH + 4 + 1 + read-write + + + TXFFLSH + TXFFLSH + 5 + 1 + read-write + + + TXFNUM + TXFNUM + 6 + 5 + read-write + + + DMAREQ + DMAREQ + 30 + 1 + read-only + + + AHBIDL + AHBIDL + 31 + 1 + read-only + + + + + GINTSTS + GINTSTS + This register interrupts the application for system-level events in the current mode (device mode or host mode). Some of the bits in this register are valid only in host mode, while others are valid in device mode only. This register also indicates the current mode. To clear the interrupt status bits of the rc_w1 type, the application must write 1 into the bit. The FIFO status interrupts are read-only; once software reads from or writes to the FIFO while servicing these interrupts, FIFO interrupt conditions are cleared automatically. The application must clear the GINTSTS register at initialization before unmasking the interrupt bit to avoid any interrupts generated prior to initialization. + 0x14 + 0x20 + 0x04000020 + + + CMOD + CMOD + 0 + 1 + read-only + + + MMIS + MMIS + 1 + 1 + read-write + + + OTGINT + OTGINT + 2 + 1 + read-only + + + SOF + SOF + 3 + 1 + read-write + + + RXFLVL + RXFLVL + 4 + 1 + read-only + + + NPTXFE + NPTXFE + 5 + 1 + read-only + + + GINAKEFF + GINAKEFF + 6 + 1 + read-only + + + GONAKEFF + GONAKEFF + 7 + 1 + read-only + + + ESUSP + ESUSP + 10 + 1 + read-write + + + USBSUSP + USBSUSP + 11 + 1 + read-write + + + USBRST + USBRST + 12 + 1 + read-write + + + ENUMDNE + ENUMDNE + 13 + 1 + read-write + + + ISOODRP + ISOODRP + 14 + 1 + read-write + + + EOPF + EOPF + 15 + 1 + read-write + + + IEPINT + IEPINT + 18 + 1 + read-only + + + OEPINT + OEPINT + 19 + 1 + read-only + + + IISOIXFR + IISOIXFR + 20 + 1 + read-write + + + IPXFR + IPXFR + 21 + 1 + read-write + + + DATAFSUSP + DATAFSUSP + 22 + 1 + read-write + + + RSTDET + RSTDET + 23 + 1 + read-write + + + HPRTINT + HPRTINT + 24 + 1 + read-only + + + HCINT + HCINT + 25 + 1 + read-only + + + PTXFE + PTXFE + 26 + 1 + read-only + + + LPMINT + LPMINT + 27 + 1 + read-write + + + CIDSCHG + CIDSCHG + 28 + 1 + read-write + + + DISCINT + DISCINT + 29 + 1 + read-write + + + SRQINT + SRQINT + 30 + 1 + read-write + + + WKUPINT + WKUPINT + 31 + 1 + read-write + + + + + GINTMSK + GINTMSK + This register works with the core interrupt register to interrupt the application. When an interrupt bit is masked, the interrupt associated with that bit is not generated. However, the core interrupt (GINTSTS) register bit corresponding to that interrupt is still set. + 0x18 + 0x20 + 0x00000000 + + + MMISM + MMISM + 1 + 1 + read-write + + + OTGINT + OTGINT + 2 + 1 + read-write + + + SOFM + SOFM + 3 + 1 + read-write + + + RXFLVLM + RXFLVLM + 4 + 1 + read-write + + + NPTXFEM + NPTXFEM + 5 + 1 + read-write + + + GINAKEFFM + GINAKEFFM + 6 + 1 + read-write + + + GONAKEFFM + GONAKEFFM + 7 + 1 + read-write + + + ESUSPM + ESUSPM + 10 + 1 + read-write + + + USBSUSPM + USBSUSPM + 11 + 1 + read-write + + + USBRST + USBRST + 12 + 1 + read-write + + + ENUMDNEM + ENUMDNEM + 13 + 1 + read-write + + + ISOODRPM + ISOODRPM + 14 + 1 + read-write + + + EOPFM + EOPFM + 15 + 1 + read-write + + + IEPINT + IEPINT + 18 + 1 + read-write + + + OEPINT + OEPINT + 19 + 1 + read-write + + + IISOIXFRM + IISOIXFRM + 20 + 1 + read-write + + + IPXFRM + IPXFRM + 21 + 1 + read-write + + + FSUSPM + FSUSPM + 22 + 1 + read-write + + + RSTDETM + RSTDETM + 23 + 1 + read-write + + + PRTIM + PRTIM + 24 + 1 + read-write + + + HCIM + HCIM + 25 + 1 + read-write + + + PTXFEM + PTXFEM + 26 + 1 + read-write + + + LPMINTM + LPMINTM + 27 + 1 + read-write + + + CIDSCHGM + CIDSCHGM + 28 + 1 + read-write + + + DISCINT + DISCINT + 29 + 1 + read-write + + + SRQIM + SRQIM + 30 + 1 + read-write + + + WUIM + WUIM + 31 + 1 + read-write + + + + + GRXSTSR_DEVICE + GRXSTSR_DEVICE + This description is for register GRXSTSR in Device mode. A read to the receive status debug read register returns the contents of the top of the receive FIFO. The core ignores the receive status read when the receive FIFO is empty and returns a value of 0x00000000. + 0x1C + 0x20 + read-only + 0x00000000 + + + EPNUM + EPNUM + 0 + 4 + + + BCNT + BCNT + 4 + 11 + + + DPID + DPID + 15 + 2 + + + PKTSTS + PKTSTS + 17 + 4 + + + FRMNUM + FRMNUM + 21 + 4 + + + STSPHST + STSPHST + 27 + 1 + + + + + GRXSTSR_HOST + GRXSTSR_HOST + This description is for register GRXSTSR in Host mode + GRXSTSR_DEVICE + 0x1C + 0x20 + read-only + 0x00000000 + + + CHNUM + CHNUM + 0 + 4 + + + BCNT + BCNT + 4 + 11 + + + DPID + DPID + 15 + 2 + + + PKTSTS + PKTSTS + 17 + 4 + + + + + GRXSTSP_DEVICE + GRXSTSP__DEVICE + This description is for register GRXSTSP in Device mode. Similarly to GRXSTSR (receive status debug read register) where a read returns the contents of the top of the receive FIFO, a read to GRXSTSP (receive status read and pop register) additionally pops the top data entry out of the Rx FIFO. The core ignores the receive status pop/read when the receive FIFO is empty and returns a value of 0x00000000. The application must only pop the receive status FIFO when the receive FIFO non-empty bit of the core interrupt register (RXFLVL bit in GINTSTS) is asserted. + 0x20 + 0x20 + read-only + 0x00000000 + + + EPNUM + EPNUM + 0 + 4 + + + BCNT + BCNT + 4 + 11 + + + DPID + DPID + 15 + 2 + + + PKTSTS + PKTSTS + 17 + 4 + + + FRMNUM + FRMNUM + 21 + 4 + + + STSPHST + STSPHST + 27 + 1 + + + + + GRXSTSP_HOST + GRXSTSP_HOST + This description is for register GRXSTSP in HOST mode + GRXSTSP_DEVICE + 0x20 + 0x20 + read-only + 0x00000000 + + + CHNUM + CHNUM + 0 + 4 + + + BCNT + BCNT + 4 + 11 + + + DPID + DPID + 15 + 2 + + + PKTSTS + PKTSTS + 17 + 4 + + + + + GRXFSIZ + GRXFSIZ + The application can program the RAM size that must be allocated to the Rx FIFO. + 0x24 + 0x20 + read-write + 0x00000400 + + + RXFD + RXFD + 0 + 16 + + + + + HNPTXFSIZ + HNPTXFSIZ + Host mode + 0x28 + 0x20 + read-write + 0x02000200 + + + NPTXFSA + NPTXFSA + 0 + 16 + + + NPTXFD + NPTXFD + 16 + 16 + + + + + HNPTXSTS + HNPTXSTS + In device mode, this register is not valid. This read-only register contains the free space information for the non-periodic Tx FIFO and the non-periodic transmit request queue. + 0x2C + 0x20 + read-only + 0x00080400 + + + NPTXFSAV + NPTXFSAV + 0 + 16 + + + NPTQXSAV + NPTQXSAV + 16 + 8 + + + NPTXQTOP + NPTXQTOP + 24 + 7 + + + + + GCCFG + GCCFG + OTG general core configuration register + 0x38 + 0x20 + 0x00000000 + + + DCDET + DCDET + 0 + 1 + read-only + + + PDET + PDET + 1 + 1 + read-only + + + SDET + SDET + 2 + 1 + read-only + + + PS2DET + PS2DET + 3 + 1 + read-only + + + PWRDWN + PWRDWN + 16 + 1 + read-write + + + BCDEN + BCDEN + 17 + 1 + read-write + + + DCDEN + DCDEN + 18 + 1 + read-write + + + PDEN + PDEN + 19 + 1 + read-write + + + SDEN + SDEN + 20 + 1 + read-write + + + VBDEN + VBDEN + 21 + 1 + read-write + + + + + CID + CID + This is a register containing the Product ID as reset value. + 0x3C + 0x20 + read-write + 0x00003100 + + + PRODUCT_ID + PRODUCT_ID + 0 + 32 + + + + + GLPMCFG + GLPMCFG + OTG core LPM configuration register + 0x54 + 0x20 + 0x00000000 + + + LPMEN + LPMEN + 0 + 1 + read-write + + + LPMACK + LPMACK + 1 + 1 + read-write + + + BESL + BESL + 2 + 4 + read-write + + + REMWAKE + REMWAKE + 6 + 1 + read-write + + + L1SSEN + L1SSEN + 7 + 1 + read-write + + + BESLTHRS + BESLTHRS + 8 + 4 + read-write + + + L1DSEN + L1DSEN + 12 + 1 + read-write + + + LPMRSP + LPMRSP + 13 + 2 + read-only + + + SLPSTS + SLPSTS + 15 + 1 + read-only + + + L1RSMOK + L1RSMOK + 16 + 1 + read-only + + + LPMCHIDX + LPMCHIDX + 17 + 4 + read-write + + + LPMRCNT + LPMRCNT + 21 + 3 + read-write + + + SNDLPM + SNDLPM + 24 + 1 + read-write + + + LPMRCNTSTS + LPMRCNTSTS + 25 + 3 + read-only + + + ENBESL + ENBESL + 28 + 1 + read-write + + + + + HPTXFSIZ + HPTXFSIZ + OTG host periodic transmit FIFO size register + 0x100 + 0x20 + read-write + 0x02000800 + + + PTXSA + PTXSA + 0 + 16 + + + PTXFSIZ + PTXFSIZ + 16 + 16 + + + + + DIEPTXF1 + DIEPTXF1 + OTG device IN endpoint transmit FIFO 1 size register + 0x104 + 0x20 + read-write + 0x02000400 + + + INEPTXSA + INEPTXSA + 0 + 16 + + + INEPTXFD + INEPTXFD + 16 + 16 + + + + + DIEPTXF2 + DIEPTXF2 + OTG device IN endpoint transmit FIFO 2 size register + 0x108 + 0x20 + read-write + 0x02000600 + + + INEPTXSA + INEPTXSA + 0 + 16 + + + INEPTXFD + INEPTXFD + 16 + 16 + + + + + DIEPTXF3 + DIEPTXF3 + OTG device IN endpoint transmit FIFO 3 size register + 0x10C + 0x20 + read-write + 0x02000800 + + + INEPTXSA + INEPTXSA + 0 + 16 + + + INEPTXFD + INEPTXFD + 16 + 16 + + + + + DIEPTXF4 + DIEPTXF4 + OTG device IN endpoint transmit FIFO 4 size register + 0x110 + 0x20 + read-write + 0x02000A00 + + + INEPTXSA + INEPTXSA + 0 + 16 + + + INEPTXFD + INEPTXFD + 16 + 16 + + + + + DIEPTXF5 + DIEPTXF5 + OTG device IN endpoint transmit FIFO 5 size register + 0x114 + 0x20 + read-write + 0x02000C00 + + + INEPTXSA + INEPTXSA + 0 + 16 + + + INEPTXFD + INEPTXFD + 16 + 16 + + + + + DIEPTXF6 + DIEPTXF6 + OTG device IN endpoint transmit FIFO 6 size register + 0x118 + 0x20 + read-write + 0x02000E00 + + + INEPTXSA + INEPTXSA + 0 + 16 + + + INEPTXFD + INEPTXFD + 16 + 16 + + + + + DIEPTXF7 + DIEPTXF7 + OTG device IN endpoint transmit FIFO 7 size register + 0x11C + 0x20 + read-write + 0x02001000 + + + INEPTXSA + INEPTXSA + 0 + 16 + + + INEPTXFD + INEPTXFD + 16 + 16 + + + + + DIEPTXF8 + DIEPTXF8 + OTG device IN endpoint transmit FIFO 8 size register + 0x120 + 0x20 + read-write + 0x02001200 + + + INEPTXSA + INEPTXSA + 0 + 16 + + + INEPTXFD + INEPTXFD + 16 + 16 + + + + + HCFG + HCFG + This register configures the core after power-on. Do not make changes to this register after initializing the host. + 0x400 + 0x20 + 0x00000000 + + + FSLSPCS + FSLSPCS + 0 + 2 + read-write + + + FSLSS + FSLSS + 2 + 1 + read-only + + + + + HFIR + HFIR + This register stores the frame interval information for the current speed to which the OTG controller has enumerated. + 0x404 + 0x20 + read-write + 0x0000EA60 + + + FRIVL + FRIVL + 0 + 16 + + + RLDCTRL + RLDCTRL + 16 + 1 + + + + + HFNUM + HFNUM + This register indicates the current frame number. It also indicates the time remaining (in terms of the number of PHY clocks) in the current frame. + 0x408 + 0x20 + read-only + 0x00003FFF + + + FRNUM + FRNUM + 0 + 16 + + + FTREM + FTREM + 16 + 16 + + + + + HPTXSTS + HPTXSTS + This read-only register contains the free space information for the periodic Tx FIFO and the periodic transmit request queue. + 0x410 + 0x20 + read-only + 0x00080100 + + + PTXFSAVL + PTXFSAVL + 0 + 16 + + + PTXQSAV + PTXQSAV + 16 + 8 + + + PTXQTOP + PTXQTOP + 24 + 8 + + + + + HAINT + HAINT + When a significant event occurs on a channel, the host all channels interrupt register interrupts the application using the host channels interrupt bit of the core interrupt register (HCINT bit in GINTSTS). This is shown in Figure724. There is one interrupt bit per channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the application sets and clears bits in the corresponding host channel-x interrupt register. + 0x414 + 0x20 + read-only + 0x00000000 + + + HAINT + HAINT + 0 + 16 + + + + + HAINTMSK + HAINTMSK + The host all channel interrupt mask register works with the host all channel interrupt register to interrupt the application when an event occurs on a channel. There is one interrupt mask bit per channel, up to a maximum of 16 bits. + 0x418 + 0x20 + read-write + 0x00000000 + + + HAINTM + HAINTM + 0 + 16 + + + + + HPRT + HPRT + This register is available only in host mode. Currently, the OTG host supports only one port. A single register holds USB port-related information such as USB reset, enable, suspend, resume, connect status, and test mode for each port. It is shown in Figure724. The rc_w1 bits in this register can trigger an interrupt to the application through the host port interrupt bit of the core interrupt register (HPRTINT bit in GINTSTS). On a port interrupt, the application must read this register and clear the bit that caused the interrupt. For the rc_w1 bits, the application must write a 1 to the bit to clear the interrupt. + 0x440 + 0x20 + 0x00000000 + + + PCSTS + PCSTS + 0 + 1 + read-only + + + PCDET + PCDET + 1 + 1 + read-write + + + PENA + PENA + 2 + 1 + read-write + + + PENCHNG + PENCHNG + 3 + 1 + read-write + + + POCA + POCA + 4 + 1 + read-only + + + POCCHNG + POCCHNG + 5 + 1 + read-write + + + PRES + PRES + 6 + 1 + read-write + + + PSUSP + PSUSP + 7 + 1 + read-write + + + PRST + PRST + 8 + 1 + read-write + + + PLSTS + PLSTS + 10 + 2 + read-only + + + PPWR + PPWR + 12 + 1 + read-write + + + PTCTL + PTCTL + 13 + 4 + read-write + + + PSPD + PSPD + 17 + 2 + read-only + + + + + HCCHAR0 + HCCHAR0 + OTG host channel 0 characteristics register + 0x500 + 0x20 + read-write + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + + + EPNUM + EPNUM + 11 + 4 + + + EPDIR + EPDIR + 15 + 1 + + + LSDEV + LSDEV + 17 + 1 + + + EPTYP + EPTYP + 18 + 2 + + + MCNT + MCNT + 20 + 2 + + + DAD + DAD + 22 + 7 + + + ODDFRM + ODDFRM + 29 + 1 + + + CHDIS + CHDIS + 30 + 1 + + + CHENA + CHENA + 31 + 1 + + + + + HCSPLT0 + HCSPLT0 + OTG host channel 0 split control register + 0x504 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port address + This field is the port number of the recipient transaction translator. + 0 + 7 + read-write + + + HUBADDR + Hub address + This field holds the device address of the transaction translator’s hub. + 7 + 7 + read-write + + + XACTPOS + Transaction position + This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. + 14 + 2 + read-write + + + B_0x3 + All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) + 0x3 + + + B_0x2 + Begin. This is the first data payload of this transaction (which is larger than 188 bytes) + 0x2 + + + B_0x0 + Mid. This is the middle payload of this transaction (which is larger than 188 bytes) + 0x0 + + + B_0x1 + End. This is the last payload of this transaction (which is larger than 188 bytes) + 0x1 + + + + + COMPLSPLT + Do complete split + The application sets this bit to request the OTG host to perform a complete split transaction. + 16 + 1 + read-write + + + SPLITEN + Split enable + The application sets this bit to indicate that this channel is enabled to perform split transactions. + 31 + 1 + read-write + + + + + HCSPLT1 + HCSPLT1 + OTG host channel 1 split control register + 0x524 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port address + This field is the port number of the recipient transaction translator. + 0 + 7 + read-write + + + HUBADDR + Hub address + This field holds the device address of the transaction translator’s hub. + 7 + 7 + read-write + + + XACTPOS + Transaction position + This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. + 14 + 2 + read-write + + + B_0x3 + All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) + 0x3 + + + B_0x2 + Begin. This is the first data payload of this transaction (which is larger than 188 bytes) + 0x2 + + + B_0x0 + Mid. This is the middle payload of this transaction (which is larger than 188 bytes) + 0x0 + + + B_0x1 + End. This is the last payload of this transaction (which is larger than 188 bytes) + 0x1 + + + + + COMPLSPLT + Do complete split + The application sets this bit to request the OTG host to perform a complete split transaction. + 16 + 1 + read-write + + + SPLITEN + Split enable + The application sets this bit to indicate that this channel is enabled to perform split transactions. + 31 + 1 + read-write + + + + + HCSPLT2 + HCSPLT2 + OTG host channel 2 split control register + 0x544 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port address + This field is the port number of the recipient transaction translator. + 0 + 7 + read-write + + + HUBADDR + Hub address + This field holds the device address of the transaction translator’s hub. + 7 + 7 + read-write + + + XACTPOS + Transaction position + This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. + 14 + 2 + read-write + + + B_0x3 + All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) + 0x3 + + + B_0x2 + Begin. This is the first data payload of this transaction (which is larger than 188 bytes) + 0x2 + + + B_0x0 + Mid. This is the middle payload of this transaction (which is larger than 188 bytes) + 0x0 + + + B_0x1 + End. This is the last payload of this transaction (which is larger than 188 bytes) + 0x1 + + + + + COMPLSPLT + Do complete split + The application sets this bit to request the OTG host to perform a complete split transaction. + 16 + 1 + read-write + + + SPLITEN + Split enable + The application sets this bit to indicate that this channel is enabled to perform split transactions. + 31 + 1 + read-write + + + + + HCSPLT3 + HCSPLT3 + OTG host channel 3 split control register + 0x564 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port address + This field is the port number of the recipient transaction translator. + 0 + 7 + read-write + + + HUBADDR + Hub address + This field holds the device address of the transaction translator’s hub. + 7 + 7 + read-write + + + XACTPOS + Transaction position + This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. + 14 + 2 + read-write + + + B_0x3 + All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) + 0x3 + + + B_0x2 + Begin. This is the first data payload of this transaction (which is larger than 188 bytes) + 0x2 + + + B_0x0 + Mid. This is the middle payload of this transaction (which is larger than 188 bytes) + 0x0 + + + B_0x1 + End. This is the last payload of this transaction (which is larger than 188 bytes) + 0x1 + + + + + COMPLSPLT + Do complete split + The application sets this bit to request the OTG host to perform a complete split transaction. + 16 + 1 + read-write + + + SPLITEN + Split enable + The application sets this bit to indicate that this channel is enabled to perform split transactions. + 31 + 1 + read-write + + + + + HCSPLT4 + HCSPLT4 + OTG host channel 4 split control register + 0x584 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port address + This field is the port number of the recipient transaction translator. + 0 + 7 + read-write + + + HUBADDR + Hub address + This field holds the device address of the transaction translator’s hub. + 7 + 7 + read-write + + + XACTPOS + Transaction position + This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. + 14 + 2 + read-write + + + B_0x3 + All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) + 0x3 + + + B_0x2 + Begin. This is the first data payload of this transaction (which is larger than 188 bytes) + 0x2 + + + B_0x0 + Mid. This is the middle payload of this transaction (which is larger than 188 bytes) + 0x0 + + + B_0x1 + End. This is the last payload of this transaction (which is larger than 188 bytes) + 0x1 + + + + + COMPLSPLT + Do complete split + The application sets this bit to request the OTG host to perform a complete split transaction. + 16 + 1 + read-write + + + SPLITEN + Split enable + The application sets this bit to indicate that this channel is enabled to perform split transactions. + 31 + 1 + read-write + + + + + HCSPLT5 + HCSPLT5 + OTG host channel 5 split control register + 0x5A4 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port address + This field is the port number of the recipient transaction translator. + 0 + 7 + read-write + + + HUBADDR + Hub address + This field holds the device address of the transaction translator’s hub. + 7 + 7 + read-write + + + XACTPOS + Transaction position + This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. + 14 + 2 + read-write + + + B_0x3 + All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) + 0x3 + + + B_0x2 + Begin. This is the first data payload of this transaction (which is larger than 188 bytes) + 0x2 + + + B_0x0 + Mid. This is the middle payload of this transaction (which is larger than 188 bytes) + 0x0 + + + B_0x1 + End. This is the last payload of this transaction (which is larger than 188 bytes) + 0x1 + + + + + COMPLSPLT + Do complete split + The application sets this bit to request the OTG host to perform a complete split transaction. + 16 + 1 + read-write + + + SPLITEN + Split enable + The application sets this bit to indicate that this channel is enabled to perform split transactions. + 31 + 1 + read-write + + + + + HCSPLT6 + HCSPLT6 + OTG host channel 6 split control register + 0x5C4 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port address + This field is the port number of the recipient transaction translator. + 0 + 7 + read-write + + + HUBADDR + Hub address + This field holds the device address of the transaction translator’s hub. + 7 + 7 + read-write + + + XACTPOS + Transaction position + This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. + 14 + 2 + read-write + + + B_0x3 + All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) + 0x3 + + + B_0x2 + Begin. This is the first data payload of this transaction (which is larger than 188 bytes) + 0x2 + + + B_0x0 + Mid. This is the middle payload of this transaction (which is larger than 188 bytes) + 0x0 + + + B_0x1 + End. This is the last payload of this transaction (which is larger than 188 bytes) + 0x1 + + + + + COMPLSPLT + Do complete split + The application sets this bit to request the OTG host to perform a complete split transaction. + 16 + 1 + read-write + + + SPLITEN + Split enable + The application sets this bit to indicate that this channel is enabled to perform split transactions. + 31 + 1 + read-write + + + + + HCSPLT7 + HCSPLT7 + OTG host channel 7 split control register + 0x5E4 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port address + This field is the port number of the recipient transaction translator. + 0 + 7 + read-write + + + HUBADDR + Hub address + This field holds the device address of the transaction translator’s hub. + 7 + 7 + read-write + + + XACTPOS + Transaction position + This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. + 14 + 2 + read-write + + + B_0x3 + All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) + 0x3 + + + B_0x2 + Begin. This is the first data payload of this transaction (which is larger than 188 bytes) + 0x2 + + + B_0x0 + Mid. This is the middle payload of this transaction (which is larger than 188 bytes) + 0x0 + + + B_0x1 + End. This is the last payload of this transaction (which is larger than 188 bytes) + 0x1 + + + + + COMPLSPLT + Do complete split + The application sets this bit to request the OTG host to perform a complete split transaction. + 16 + 1 + read-write + + + SPLITEN + Split enable + The application sets this bit to indicate that this channel is enabled to perform split transactions. + 31 + 1 + read-write + + + + + HCSPLT8 + HCSPLT8 + OTG host channel 8 split control register + 0x604 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port address + This field is the port number of the recipient transaction translator. + 0 + 7 + read-write + + + HUBADDR + Hub address + This field holds the device address of the transaction translator’s hub. + 7 + 7 + read-write + + + XACTPOS + Transaction position + This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. + 14 + 2 + read-write + + + B_0x3 + All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) + 0x3 + + + B_0x2 + Begin. This is the first data payload of this transaction (which is larger than 188 bytes) + 0x2 + + + B_0x0 + Mid. This is the middle payload of this transaction (which is larger than 188 bytes) + 0x0 + + + B_0x1 + End. This is the last payload of this transaction (which is larger than 188 bytes) + 0x1 + + + + + COMPLSPLT + Do complete split + The application sets this bit to request the OTG host to perform a complete split transaction. + 16 + 1 + read-write + + + SPLITEN + Split enable + The application sets this bit to indicate that this channel is enabled to perform split transactions. + 31 + 1 + read-write + + + + + HCSPLT9 + HCSPLT9 + OTG host channel 9 split control register + 0x624 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port address + This field is the port number of the recipient transaction translator. + 0 + 7 + read-write + + + HUBADDR + Hub address + This field holds the device address of the transaction translator’s hub. + 7 + 7 + read-write + + + XACTPOS + Transaction position + This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. + 14 + 2 + read-write + + + B_0x3 + All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) + 0x3 + + + B_0x2 + Begin. This is the first data payload of this transaction (which is larger than 188 bytes) + 0x2 + + + B_0x0 + Mid. This is the middle payload of this transaction (which is larger than 188 bytes) + 0x0 + + + B_0x1 + End. This is the last payload of this transaction (which is larger than 188 bytes) + 0x1 + + + + + COMPLSPLT + Do complete split + The application sets this bit to request the OTG host to perform a complete split transaction. + 16 + 1 + read-write + + + SPLITEN + Split enable + The application sets this bit to indicate that this channel is enabled to perform split transactions. + 31 + 1 + read-write + + + + + HCSPLT10 + HCSPLT10 + OTG host channel 10 split control register + 0x644 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port address + This field is the port number of the recipient transaction translator. + 0 + 7 + read-write + + + HUBADDR + Hub address + This field holds the device address of the transaction translator’s hub. + 7 + 7 + read-write + + + XACTPOS + Transaction position + This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. + 14 + 2 + read-write + + + B_0x3 + All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) + 0x3 + + + B_0x2 + Begin. This is the first data payload of this transaction (which is larger than 188 bytes) + 0x2 + + + B_0x0 + Mid. This is the middle payload of this transaction (which is larger than 188 bytes) + 0x0 + + + B_0x1 + End. This is the last payload of this transaction (which is larger than 188 bytes) + 0x1 + + + + + COMPLSPLT + Do complete split + The application sets this bit to request the OTG host to perform a complete split transaction. + 16 + 1 + read-write + + + SPLITEN + Split enable + The application sets this bit to indicate that this channel is enabled to perform split transactions. + 31 + 1 + read-write + + + + + HCSPLT11 + HCSPLT11 + OTG host channel 11 split control register + 0x664 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port address + This field is the port number of the recipient transaction translator. + 0 + 7 + read-write + + + HUBADDR + Hub address + This field holds the device address of the transaction translator’s hub. + 7 + 7 + read-write + + + XACTPOS + Transaction position + This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. + 14 + 2 + read-write + + + B_0x3 + All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) + 0x3 + + + B_0x2 + Begin. This is the first data payload of this transaction (which is larger than 188 bytes) + 0x2 + + + B_0x0 + Mid. This is the middle payload of this transaction (which is larger than 188 bytes) + 0x0 + + + B_0x1 + End. This is the last payload of this transaction (which is larger than 188 bytes) + 0x1 + + + + + COMPLSPLT + Do complete split + The application sets this bit to request the OTG host to perform a complete split transaction. + 16 + 1 + read-write + + + SPLITEN + Split enable + The application sets this bit to indicate that this channel is enabled to perform split transactions. + 31 + 1 + read-write + + + + + HCSPLT12 + HCSPLT12 + OTG host channel 0 split control register + 0x684 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port address + This field is the port number of the recipient transaction translator. + 0 + 7 + read-write + + + HUBADDR + Hub address + This field holds the device address of the transaction translator’s hub. + 7 + 7 + read-write + + + XACTPOS + Transaction position + This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. + 14 + 2 + read-write + + + B_0x3 + All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) + 0x3 + + + B_0x2 + Begin. This is the first data payload of this transaction (which is larger than 188 bytes) + 0x2 + + + B_0x0 + Mid. This is the middle payload of this transaction (which is larger than 188 bytes) + 0x0 + + + B_0x1 + End. This is the last payload of this transaction (which is larger than 188 bytes) + 0x1 + + + + + COMPLSPLT + Do complete split + The application sets this bit to request the OTG host to perform a complete split transaction. + 16 + 1 + read-write + + + SPLITEN + Split enable + The application sets this bit to indicate that this channel is enabled to perform split transactions. + 31 + 1 + read-write + + + + + HCSPLT13 + HCSPLT13 + OTG host channel 13 split control register + 0x6A4 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port address + This field is the port number of the recipient transaction translator. + 0 + 7 + read-write + + + HUBADDR + Hub address + This field holds the device address of the transaction translator’s hub. + 7 + 7 + read-write + + + XACTPOS + Transaction position + This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. + 14 + 2 + read-write + + + B_0x3 + All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) + 0x3 + + + B_0x2 + Begin. This is the first data payload of this transaction (which is larger than 188 bytes) + 0x2 + + + B_0x0 + Mid. This is the middle payload of this transaction (which is larger than 188 bytes) + 0x0 + + + B_0x1 + End. This is the last payload of this transaction (which is larger than 188 bytes) + 0x1 + + + + + COMPLSPLT + Do complete split + The application sets this bit to request the OTG host to perform a complete split transaction. + 16 + 1 + read-write + + + SPLITEN + Split enable + The application sets this bit to indicate that this channel is enabled to perform split transactions. + 31 + 1 + read-write + + + + + HCSPLT14 + HCSPLT14 + OTG host channel 14 split control register + 0x6C4 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port address + This field is the port number of the recipient transaction translator. + 0 + 7 + read-write + + + HUBADDR + Hub address + This field holds the device address of the transaction translator’s hub. + 7 + 7 + read-write + + + XACTPOS + Transaction position + This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. + 14 + 2 + read-write + + + B_0x3 + All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) + 0x3 + + + B_0x2 + Begin. This is the first data payload of this transaction (which is larger than 188 bytes) + 0x2 + + + B_0x0 + Mid. This is the middle payload of this transaction (which is larger than 188 bytes) + 0x0 + + + B_0x1 + End. This is the last payload of this transaction (which is larger than 188 bytes) + 0x1 + + + + + COMPLSPLT + Do complete split + The application sets this bit to request the OTG host to perform a complete split transaction. + 16 + 1 + read-write + + + SPLITEN + Split enable + The application sets this bit to indicate that this channel is enabled to perform split transactions. + 31 + 1 + read-write + + + + + HCSPLT15 + HCSPLT15 + OTG host channel 15 split control register + 0x6E4 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port address + This field is the port number of the recipient transaction translator. + 0 + 7 + read-write + + + HUBADDR + Hub address + This field holds the device address of the transaction translator’s hub. + 7 + 7 + read-write + + + XACTPOS + Transaction position + This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. + 14 + 2 + read-write + + + B_0x3 + All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) + 0x3 + + + B_0x2 + Begin. This is the first data payload of this transaction (which is larger than 188 bytes) + 0x2 + + + B_0x0 + Mid. This is the middle payload of this transaction (which is larger than 188 bytes) + 0x0 + + + B_0x1 + End. This is the last payload of this transaction (which is larger than 188 bytes) + 0x1 + + + + + COMPLSPLT + Do complete split + The application sets this bit to request the OTG host to perform a complete split transaction. + 16 + 1 + read-write + + + SPLITEN + Split enable + The application sets this bit to indicate that this channel is enabled to perform split transactions. + 31 + 1 + read-write + + + + + HCINT0 + HCINT0 + This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. + 0x508 + 0x20 + read-write + 0x00000000 + + + XFRC + XFRC + 0 + 1 + + + CHH + CHH + 1 + 1 + + + STALL + STALL + 3 + 1 + + + NAK + NAK + 4 + 1 + + + ACK + ACK + 5 + 1 + + + TXERR + TXERR + 7 + 1 + + + BBERR + BBERR + 8 + 1 + + + FRMOR + FRMOR + 9 + 1 + + + DTERR + DTERR + 10 + 1 + + + + + HCINTMSK0 + HCINTMSK0 + This register reflects the mask for each channel status described in the previous section. + 0x50C + 0x20 + read-write + 0x00000000 + + + XFRCM + XFRCM + 0 + 1 + + + CHHM + CHHM + 1 + 1 + + + STALLM + STALLM + 3 + 1 + + + NAKM + NAKM + 4 + 1 + + + ACKM + ACKM + 5 + 1 + + + TXERRM + TXERRM + 7 + 1 + + + BBERRM + BBERRM + 8 + 1 + + + FRMORM + FRMORM + 9 + 1 + + + DTERRM + DTERRM + 10 + 1 + + + + + HCTSIZ0 + HCTSIZ0 + OTG host channel 0 transfer size register + 0x510 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + DPID + DPID + 29 + 2 + + + DOPNG + DOPNG + 31 + 1 + + + + + HCDMA0 + HCDMA0 + OTG host channel 0 DMA address register + 0x514 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA address + This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. + 0 + 32 + + + + + HCDMA1 + HCDMA1 + OTG host channel 1 DMA address register + 0x534 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA address + This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. + 0 + 32 + + + + + HCDMA2 + HCDMA2 + OTG host channel 2 DMA address register + 0x554 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA address + This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. + 0 + 32 + + + + + HCDMA3 + HCDMA3 + OTG host channel 3 DMA address register + 0x574 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA address + This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. + 0 + 32 + + + + + HCDMA4 + HCDMA4 + OTG host channel 4 DMA address register + 0x594 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA address + This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. + 0 + 32 + + + + + HCDMA5 + HCDMA5 + OTG host channel 5 DMA address register + 0x5B4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA address + This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. + 0 + 32 + + + + + HCDMA6 + HCDMA6 + OTG host channel 6 DMA address register + 0x5D4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA address + This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. + 0 + 32 + + + + + HCDMA7 + HCDMA7 + OTG host channel 7 DMA address register + 0x5F4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA address + This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. + 0 + 32 + + + + + HCDMA8 + HCDMA8 + OTG host channel 8 DMA address register + 0x614 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA address + This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. + 0 + 32 + + + + + HCDMA9 + HCDMA9 + OTG host channel 9 DMA address register + 0x634 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA address + This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. + 0 + 32 + + + + + HCDMA10 + HCDMA10 + OTG host channel 10 DMA address register + 0x654 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA address + This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. + 0 + 32 + + + + + HCDMA11 + HCDMA11 + OTG host channel 11 DMA address register + 0x674 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA address + This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. + 0 + 32 + + + + + HCDMA12 + HCDMA12 + OTG host channel 12 DMA address register + 0x694 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA address + This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. + 0 + 32 + + + + + HCDMA13 + HCDMA13 + OTG host channel 13 DMA address register + 0x6B4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA address + This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. + 0 + 32 + + + + + HCDMA14 + HCDMA14 + OTG host channel 14 DMA address register + 0x6D4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA address + This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. + 0 + 32 + + + + + HCDMA15 + HCDMA15 + OTG host channel 15 DMA address register + 0x6F4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA address + This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. + 0 + 32 + + + + + HCCHAR1 + HCCHAR1 + OTG host channel 1 characteristics register + 0x520 + 0x20 + read-write + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + + + EPNUM + EPNUM + 11 + 4 + + + EPDIR + EPDIR + 15 + 1 + + + LSDEV + LSDEV + 17 + 1 + + + EPTYP + EPTYP + 18 + 2 + + + MCNT + MCNT + 20 + 2 + + + DAD + DAD + 22 + 7 + + + ODDFRM + ODDFRM + 29 + 1 + + + CHDIS + CHDIS + 30 + 1 + + + CHENA + CHENA + 31 + 1 + + + + + HCINT1_DEVICE + HCINT1 + This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. + 0x528 + 0x20 + read-write + 0x00000000 + + + XFRC + XFRC + 0 + 1 + + + CHH + CHH + 1 + 1 + + + STALL + STALL + 3 + 1 + + + NAK + NAK + 4 + 1 + + + ACK + ACK + 5 + 1 + + + TXERR + TXERR + 7 + 1 + + + BBERR + BBERR + 8 + 1 + + + FRMOR + FRMOR + 9 + 1 + + + DTERR + DTERR + 10 + 1 + + + + + HCINTMSK1 + HCINTMSK1 + This register reflects the mask for each channel status described in the previous section. + 0x52C + 0x20 + read-write + 0x00000000 + + + XFRCM + XFRCM + 0 + 1 + + + CHHM + CHHM + 1 + 1 + + + STALLM + STALLM + 3 + 1 + + + NAKM + NAKM + 4 + 1 + + + ACKM + ACKM + 5 + 1 + + + TXERRM + TXERRM + 7 + 1 + + + BBERRM + BBERRM + 8 + 1 + + + FRMORM + FRMORM + 9 + 1 + + + DTERRM + DTERRM + 10 + 1 + + + + + HCTSIZ1 + HCTSIZ1 + OTG host channel 1 transfer size register + 0x530 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + DPID + DPID + 29 + 2 + + + DOPNG + DOPNG + 31 + 1 + + + + + HCCHAR2 + HCCHAR2 + OTG host channel 2 characteristics register + 0x540 + 0x20 + read-write + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + + + EPNUM + EPNUM + 11 + 4 + + + EPDIR + EPDIR + 15 + 1 + + + LSDEV + LSDEV + 17 + 1 + + + EPTYP + EPTYP + 18 + 2 + + + MCNT + MCNT + 20 + 2 + + + DAD + DAD + 22 + 7 + + + ODDFRM + ODDFRM + 29 + 1 + + + CHDIS + CHDIS + 30 + 1 + + + CHENA + CHENA + 31 + 1 + + + + + HCINT2 + HCINT2 + This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. + 0x548 + 0x20 + read-write + 0x00000000 + + + XFRC + XFRC + 0 + 1 + + + CHH + CHH + 1 + 1 + + + STALL + STALL + 3 + 1 + + + NAK + NAK + 4 + 1 + + + ACK + ACK + 5 + 1 + + + TXERR + TXERR + 7 + 1 + + + BBERR + BBERR + 8 + 1 + + + FRMOR + FRMOR + 9 + 1 + + + DTERR + DTERR + 10 + 1 + + + + + HCINTMSK2 + HCINTMSK2 + This register reflects the mask for each channel status described in the previous section. + 0x54C + 0x20 + read-write + 0x00000000 + + + XFRCM + XFRCM + 0 + 1 + + + CHHM + CHHM + 1 + 1 + + + STALLM + STALLM + 3 + 1 + + + NAKM + NAKM + 4 + 1 + + + ACKM + ACKM + 5 + 1 + + + TXERRM + TXERRM + 7 + 1 + + + BBERRM + BBERRM + 8 + 1 + + + FRMORM + FRMORM + 9 + 1 + + + DTERRM + DTERRM + 10 + 1 + + + + + HCTSIZ2 + HCTSIZ2 + OTG host channel 2 transfer size register + 0x550 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + DPID + DPID + 29 + 2 + + + DOPNG + DOPNG + 31 + 1 + + + + + HCCHAR3 + HCCHAR3 + OTG host channel 3 characteristics register + 0x560 + 0x20 + read-write + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + + + EPNUM + EPNUM + 11 + 4 + + + EPDIR + EPDIR + 15 + 1 + + + LSDEV + LSDEV + 17 + 1 + + + EPTYP + EPTYP + 18 + 2 + + + MCNT + MCNT + 20 + 2 + + + DAD + DAD + 22 + 7 + + + ODDFRM + ODDFRM + 29 + 1 + + + CHDIS + CHDIS + 30 + 1 + + + CHENA + CHENA + 31 + 1 + + + + + HCINT3 + HCINT3 + This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. + 0x568 + 0x20 + read-write + 0x00000000 + + + XFRC + XFRC + 0 + 1 + + + CHH + CHH + 1 + 1 + + + STALL + STALL + 3 + 1 + + + NAK + NAK + 4 + 1 + + + ACK + ACK + 5 + 1 + + + TXERR + TXERR + 7 + 1 + + + BBERR + BBERR + 8 + 1 + + + FRMOR + FRMOR + 9 + 1 + + + DTERR + DTERR + 10 + 1 + + + + + HCINTMSK3 + HCINTMSK3 + This register reflects the mask for each channel status described in the previous section. + 0x56C + 0x20 + read-write + 0x00000000 + + + XFRCM + XFRCM + 0 + 1 + + + CHHM + CHHM + 1 + 1 + + + STALLM + STALLM + 3 + 1 + + + NAKM + NAKM + 4 + 1 + + + ACKM + ACKM + 5 + 1 + + + TXERRM + TXERRM + 7 + 1 + + + BBERRM + BBERRM + 8 + 1 + + + FRMORM + FRMORM + 9 + 1 + + + DTERRM + DTERRM + 10 + 1 + + + + + HCTSIZ3 + HCTSIZ3 + OTG host channel 3 transfer size register + 0x570 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + DPID + DPID + 29 + 2 + + + DOPNG + DOPNG + 31 + 1 + + + + + HCCHAR4 + HCCHAR4 + OTG host channel 4 characteristics register + 0x580 + 0x20 + read-write + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + + + EPNUM + EPNUM + 11 + 4 + + + EPDIR + EPDIR + 15 + 1 + + + LSDEV + LSDEV + 17 + 1 + + + EPTYP + EPTYP + 18 + 2 + + + MCNT + MCNT + 20 + 2 + + + DAD + DAD + 22 + 7 + + + ODDFRM + ODDFRM + 29 + 1 + + + CHDIS + CHDIS + 30 + 1 + + + CHENA + CHENA + 31 + 1 + + + + + HCINT4 + HCINT4 + This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. + 0x588 + 0x20 + read-write + 0x00000000 + + + XFRC + XFRC + 0 + 1 + + + CHH + CHH + 1 + 1 + + + STALL + STALL + 3 + 1 + + + NAK + NAK + 4 + 1 + + + ACK + ACK + 5 + 1 + + + TXERR + TXERR + 7 + 1 + + + BBERR + BBERR + 8 + 1 + + + FRMOR + FRMOR + 9 + 1 + + + DTERR + DTERR + 10 + 1 + + + + + HCINTMSK4 + HCINTMSK4 + This register reflects the mask for each channel status described in the previous section. + 0x58C + 0x20 + read-write + 0x00000000 + + + XFRCM + XFRCM + 0 + 1 + + + CHHM + CHHM + 1 + 1 + + + STALLM + STALLM + 3 + 1 + + + NAKM + NAKM + 4 + 1 + + + ACKM + ACKM + 5 + 1 + + + TXERRM + TXERRM + 7 + 1 + + + BBERRM + BBERRM + 8 + 1 + + + FRMORM + FRMORM + 9 + 1 + + + DTERRM + DTERRM + 10 + 1 + + + + + HCTSIZ4 + HCTSIZ4 + OTG host channel 4 transfer size register + 0x590 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + DPID + DPID + 29 + 2 + + + DOPNG + DOPNG + 31 + 1 + + + + + HCCHAR5 + HCCHAR5 + OTG host channel 5 characteristics register + 0x5A0 + 0x20 + read-write + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + + + EPNUM + EPNUM + 11 + 4 + + + EPDIR + EPDIR + 15 + 1 + + + LSDEV + LSDEV + 17 + 1 + + + EPTYP + EPTYP + 18 + 2 + + + MCNT + MCNT + 20 + 2 + + + DAD + DAD + 22 + 7 + + + ODDFRM + ODDFRM + 29 + 1 + + + CHDIS + CHDIS + 30 + 1 + + + CHENA + CHENA + 31 + 1 + + + + + HCINT5 + HCINT5 + This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. + 0x5A8 + 0x20 + read-write + 0x00000000 + + + XFRC + XFRC + 0 + 1 + + + CHH + CHH + 1 + 1 + + + STALL + STALL + 3 + 1 + + + NAK + NAK + 4 + 1 + + + ACK + ACK + 5 + 1 + + + TXERR + TXERR + 7 + 1 + + + BBERR + BBERR + 8 + 1 + + + FRMOR + FRMOR + 9 + 1 + + + DTERR + DTERR + 10 + 1 + + + + + HCINTMSK5 + HCINTMSK5 + This register reflects the mask for each channel status described in the previous section. + 0x5AC + 0x20 + read-write + 0x00000000 + + + XFRCM + XFRCM + 0 + 1 + + + CHHM + CHHM + 1 + 1 + + + STALLM + STALLM + 3 + 1 + + + NAKM + NAKM + 4 + 1 + + + ACKM + ACKM + 5 + 1 + + + TXERRM + TXERRM + 7 + 1 + + + BBERRM + BBERRM + 8 + 1 + + + FRMORM + FRMORM + 9 + 1 + + + DTERRM + DTERRM + 10 + 1 + + + + + HCTSIZ5 + HCTSIZ5 + OTG host channel 5 transfer size register + 0x5B0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + DPID + DPID + 29 + 2 + + + DOPNG + DOPNG + 31 + 1 + + + + + HCCHAR6 + HCCHAR6 + OTG host channel 6 characteristics register + 0x5C0 + 0x20 + read-write + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + + + EPNUM + EPNUM + 11 + 4 + + + EPDIR + EPDIR + 15 + 1 + + + LSDEV + LSDEV + 17 + 1 + + + EPTYP + EPTYP + 18 + 2 + + + MCNT + MCNT + 20 + 2 + + + DAD + DAD + 22 + 7 + + + ODDFRM + ODDFRM + 29 + 1 + + + CHDIS + CHDIS + 30 + 1 + + + CHENA + CHENA + 31 + 1 + + + + + HCINT6 + HCINT6 + This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. + 0x5C8 + 0x20 + read-write + 0x00000000 + + + XFRC + XFRC + 0 + 1 + + + CHH + CHH + 1 + 1 + + + STALL + STALL + 3 + 1 + + + NAK + NAK + 4 + 1 + + + ACK + ACK + 5 + 1 + + + TXERR + TXERR + 7 + 1 + + + BBERR + BBERR + 8 + 1 + + + FRMOR + FRMOR + 9 + 1 + + + DTERR + DTERR + 10 + 1 + + + + + HCINTMSK6 + HCINTMSK6 + This register reflects the mask for each channel status described in the previous section. + 0x5CC + 0x20 + read-write + 0x00000000 + + + XFRCM + XFRCM + 0 + 1 + + + CHHM + CHHM + 1 + 1 + + + STALLM + STALLM + 3 + 1 + + + NAKM + NAKM + 4 + 1 + + + ACKM + ACKM + 5 + 1 + + + TXERRM + TXERRM + 7 + 1 + + + BBERRM + BBERRM + 8 + 1 + + + FRMORM + FRMORM + 9 + 1 + + + DTERRM + DTERRM + 10 + 1 + + + + + HCTSIZ6 + HCTSIZ6 + OTG host channel 6 transfer size register + 0x5D0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + DPID + DPID + 29 + 2 + + + DOPNG + DOPNG + 31 + 1 + + + + + HCCHAR7 + HCCHAR7 + OTG host channel 7 characteristics register + 0x5E0 + 0x20 + read-write + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + + + EPNUM + EPNUM + 11 + 4 + + + EPDIR + EPDIR + 15 + 1 + + + LSDEV + LSDEV + 17 + 1 + + + EPTYP + EPTYP + 18 + 2 + + + MCNT + MCNT + 20 + 2 + + + DAD + DAD + 22 + 7 + + + ODDFRM + ODDFRM + 29 + 1 + + + CHDIS + CHDIS + 30 + 1 + + + CHENA + CHENA + 31 + 1 + + + + + HCINT7 + HCINT7 + This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. + 0x5E8 + 0x20 + read-write + 0x00000000 + + + XFRC + XFRC + 0 + 1 + + + CHH + CHH + 1 + 1 + + + STALL + STALL + 3 + 1 + + + NAK + NAK + 4 + 1 + + + ACK + ACK + 5 + 1 + + + TXERR + TXERR + 7 + 1 + + + BBERR + BBERR + 8 + 1 + + + FRMOR + FRMOR + 9 + 1 + + + DTERR + DTERR + 10 + 1 + + + + + HCINTMSK7 + HCINTMSK7 + This register reflects the mask for each channel status described in the previous section. + 0x5EC + 0x20 + read-write + 0x00000000 + + + XFRCM + XFRCM + 0 + 1 + + + CHHM + CHHM + 1 + 1 + + + STALLM + STALLM + 3 + 1 + + + NAKM + NAKM + 4 + 1 + + + ACKM + ACKM + 5 + 1 + + + TXERRM + TXERRM + 7 + 1 + + + BBERRM + BBERRM + 8 + 1 + + + FRMORM + FRMORM + 9 + 1 + + + DTERRM + DTERRM + 10 + 1 + + + + + HCTSIZ7 + HCTSIZ7 + OTG host channel 7 transfer size register + 0x5F0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + DPID + DPID + 29 + 2 + + + DOPNG + DOPNG + 31 + 1 + + + + + HCCHAR8 + HCCHAR8 + OTG host channel 8 characteristics register + 0x600 + 0x20 + read-write + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + + + EPNUM + EPNUM + 11 + 4 + + + EPDIR + EPDIR + 15 + 1 + + + LSDEV + LSDEV + 17 + 1 + + + EPTYP + EPTYP + 18 + 2 + + + MCNT + MCNT + 20 + 2 + + + DAD + DAD + 22 + 7 + + + ODDFRM + ODDFRM + 29 + 1 + + + CHDIS + CHDIS + 30 + 1 + + + CHENA + CHENA + 31 + 1 + + + + + HCINT8 + HCINT8 + This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. + 0x608 + 0x20 + read-write + 0x00000000 + + + XFRC + XFRC + 0 + 1 + + + CHH + CHH + 1 + 1 + + + STALL + STALL + 3 + 1 + + + NAK + NAK + 4 + 1 + + + ACK + ACK + 5 + 1 + + + TXERR + TXERR + 7 + 1 + + + BBERR + BBERR + 8 + 1 + + + FRMOR + FRMOR + 9 + 1 + + + DTERR + DTERR + 10 + 1 + + + + + HCINTMSK8 + HCINTMSK8 + This register reflects the mask for each channel status described in the previous section. + 0x60C + 0x20 + read-write + 0x00000000 + + + XFRCM + XFRCM + 0 + 1 + + + CHHM + CHHM + 1 + 1 + + + STALLM + STALLM + 3 + 1 + + + NAKM + NAKM + 4 + 1 + + + ACKM + ACKM + 5 + 1 + + + TXERRM + TXERRM + 7 + 1 + + + BBERRM + BBERRM + 8 + 1 + + + FRMORM + FRMORM + 9 + 1 + + + DTERRM + DTERRM + 10 + 1 + + + + + HCTSIZ8 + HCTSIZ8 + OTG host channel 8 transfer size register + 0x610 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + DPID + DPID + 29 + 2 + + + DOPNG + DOPNG + 31 + 1 + + + + + HCCHAR9 + HCCHAR9 + OTG host channel 9 characteristics register + 0x620 + 0x20 + read-write + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + + + EPNUM + EPNUM + 11 + 4 + + + EPDIR + EPDIR + 15 + 1 + + + LSDEV + LSDEV + 17 + 1 + + + EPTYP + EPTYP + 18 + 2 + + + MCNT + MCNT + 20 + 2 + + + DAD + DAD + 22 + 7 + + + ODDFRM + ODDFRM + 29 + 1 + + + CHDIS + CHDIS + 30 + 1 + + + CHENA + CHENA + 31 + 1 + + + + + HCINT9 + HCINT9 + This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. + 0x628 + 0x20 + read-write + 0x00000000 + + + XFRC + XFRC + 0 + 1 + + + CHH + CHH + 1 + 1 + + + STALL + STALL + 3 + 1 + + + NAK + NAK + 4 + 1 + + + ACK + ACK + 5 + 1 + + + TXERR + TXERR + 7 + 1 + + + BBERR + BBERR + 8 + 1 + + + FRMOR + FRMOR + 9 + 1 + + + DTERR + DTERR + 10 + 1 + + + + + HCINTMSK9 + HCINTMSK9 + This register reflects the mask for each channel status described in the previous section. + 0x62C + 0x20 + read-write + 0x00000000 + + + XFRCM + XFRCM + 0 + 1 + + + CHHM + CHHM + 1 + 1 + + + STALLM + STALLM + 3 + 1 + + + NAKM + NAKM + 4 + 1 + + + ACKM + ACKM + 5 + 1 + + + TXERRM + TXERRM + 7 + 1 + + + BBERRM + BBERRM + 8 + 1 + + + FRMORM + FRMORM + 9 + 1 + + + DTERRM + DTERRM + 10 + 1 + + + + + HCTSIZ9 + HCTSIZ9 + OTG host channel 9 transfer size register + 0x630 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + DPID + DPID + 29 + 2 + + + DOPNG + DOPNG + 31 + 1 + + + + + HCCHAR10 + HCCHAR10 + OTG host channel 10 characteristics register + 0x640 + 0x20 + read-write + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + + + EPNUM + EPNUM + 11 + 4 + + + EPDIR + EPDIR + 15 + 1 + + + LSDEV + LSDEV + 17 + 1 + + + EPTYP + EPTYP + 18 + 2 + + + MCNT + MCNT + 20 + 2 + + + DAD + DAD + 22 + 7 + + + ODDFRM + ODDFRM + 29 + 1 + + + CHDIS + CHDIS + 30 + 1 + + + CHENA + CHENA + 31 + 1 + + + + + HCINT10 + HCINT10 + This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. + 0x648 + 0x20 + read-write + 0x00000000 + + + XFRC + XFRC + 0 + 1 + + + CHH + CHH + 1 + 1 + + + STALL + STALL + 3 + 1 + + + NAK + NAK + 4 + 1 + + + ACK + ACK + 5 + 1 + + + TXERR + TXERR + 7 + 1 + + + BBERR + BBERR + 8 + 1 + + + FRMOR + FRMOR + 9 + 1 + + + DTERR + DTERR + 10 + 1 + + + + + HCINTMSK10 + HCINTMSK10 + This register reflects the mask for each channel status described in the previous section. + 0x64C + 0x20 + read-write + 0x00000000 + + + XFRCM + XFRCM + 0 + 1 + + + CHHM + CHHM + 1 + 1 + + + STALLM + STALLM + 3 + 1 + + + NAKM + NAKM + 4 + 1 + + + ACKM + ACKM + 5 + 1 + + + TXERRM + TXERRM + 7 + 1 + + + BBERRM + BBERRM + 8 + 1 + + + FRMORM + FRMORM + 9 + 1 + + + DTERRM + DTERRM + 10 + 1 + + + + + HCTSIZ10 + HCTSIZ10 + OTG host channel 10 transfer size register + 0x650 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + DPID + DPID + 29 + 2 + + + DOPNG + DOPNG + 31 + 1 + + + + + HCCHAR11 + HCCHAR11 + OTG host channel 11 characteristics register + 0x660 + 0x20 + read-write + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + + + EPNUM + EPNUM + 11 + 4 + + + EPDIR + EPDIR + 15 + 1 + + + LSDEV + LSDEV + 17 + 1 + + + EPTYP + EPTYP + 18 + 2 + + + MCNT + MCNT + 20 + 2 + + + DAD + DAD + 22 + 7 + + + ODDFRM + ODDFRM + 29 + 1 + + + CHDIS + CHDIS + 30 + 1 + + + CHENA + CHENA + 31 + 1 + + + + + HCCHAR12 + HCCHAR12 + OTG host channel 12 characteristics register + 0x680 + 0x20 + read-write + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + + + EPNUM + EPNUM + 11 + 4 + + + EPDIR + EPDIR + 15 + 1 + + + LSDEV + LSDEV + 17 + 1 + + + EPTYP + EPTYP + 18 + 2 + + + MCNT + MCNT + 20 + 2 + + + DAD + DAD + 22 + 7 + + + ODDFRM + ODDFRM + 29 + 1 + + + CHDIS + CHDIS + 30 + 1 + + + CHENA + CHENA + 31 + 1 + + + + + HCCHAR13 + HCCHAR13 + OTG host channel 13 characteristics register + 0x6A0 + 0x20 + read-write + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + + + EPNUM + EPNUM + 11 + 4 + + + EPDIR + EPDIR + 15 + 1 + + + LSDEV + LSDEV + 17 + 1 + + + EPTYP + EPTYP + 18 + 2 + + + MCNT + MCNT + 20 + 2 + + + DAD + DAD + 22 + 7 + + + ODDFRM + ODDFRM + 29 + 1 + + + CHDIS + CHDIS + 30 + 1 + + + CHENA + CHENA + 31 + 1 + + + + + HCCHAR14 + HCCHAR14 + OTG host channel 14 characteristics register + 0x6C0 + 0x20 + read-write + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + + + EPNUM + EPNUM + 11 + 4 + + + EPDIR + EPDIR + 15 + 1 + + + LSDEV + LSDEV + 17 + 1 + + + EPTYP + EPTYP + 18 + 2 + + + MCNT + MCNT + 20 + 2 + + + DAD + DAD + 22 + 7 + + + ODDFRM + ODDFRM + 29 + 1 + + + CHDIS + CHDIS + 30 + 1 + + + CHENA + CHENA + 31 + 1 + + + + + HCCHAR15 + HCCHAR15 + OTG host channel 15 characteristics register + 0x6E0 + 0x20 + read-write + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + + + EPNUM + EPNUM + 11 + 4 + + + EPDIR + EPDIR + 15 + 1 + + + LSDEV + LSDEV + 17 + 1 + + + EPTYP + EPTYP + 18 + 2 + + + MCNT + MCNT + 20 + 2 + + + DAD + DAD + 22 + 7 + + + ODDFRM + ODDFRM + 29 + 1 + + + CHDIS + CHDIS + 30 + 1 + + + CHENA + CHENA + 31 + 1 + + + + + HCINT11 + HCINT11 + This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. + 0x668 + 0x20 + read-write + 0x00000000 + + + XFRC + XFRC + 0 + 1 + + + CHH + CHH + 1 + 1 + + + STALL + STALL + 3 + 1 + + + NAK + NAK + 4 + 1 + + + ACK + ACK + 5 + 1 + + + TXERR + TXERR + 7 + 1 + + + BBERR + BBERR + 8 + 1 + + + FRMOR + FRMOR + 9 + 1 + + + DTERR + DTERR + 10 + 1 + + + + + HCINT12 + HCINT12 + This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. + 0x688 + 0x20 + read-write + 0x00000000 + + + XFRC + XFRC + 0 + 1 + + + CHH + CHH + 1 + 1 + + + STALL + STALL + 3 + 1 + + + NAK + NAK + 4 + 1 + + + ACK + ACK + 5 + 1 + + + TXERR + TXERR + 7 + 1 + + + BBERR + BBERR + 8 + 1 + + + FRMOR + FRMOR + 9 + 1 + + + DTERR + DTERR + 10 + 1 + + + + + HCINT13 + HCINT13 + This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. + 0x6A8 + 0x20 + read-write + 0x00000000 + + + XFRC + XFRC + 0 + 1 + + + CHH + CHH + 1 + 1 + + + STALL + STALL + 3 + 1 + + + NAK + NAK + 4 + 1 + + + ACK + ACK + 5 + 1 + + + TXERR + TXERR + 7 + 1 + + + BBERR + BBERR + 8 + 1 + + + FRMOR + FRMOR + 9 + 1 + + + DTERR + DTERR + 10 + 1 + + + + + HCINT14 + HCINT14 + This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. + 0x6C8 + 0x20 + read-write + 0x00000000 + + + XFRC + XFRC + 0 + 1 + + + CHH + CHH + 1 + 1 + + + STALL + STALL + 3 + 1 + + + NAK + NAK + 4 + 1 + + + ACK + ACK + 5 + 1 + + + TXERR + TXERR + 7 + 1 + + + BBERR + BBERR + 8 + 1 + + + FRMOR + FRMOR + 9 + 1 + + + DTERR + DTERR + 10 + 1 + + + + + HCINT15 + HCINT15 + This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. + 0x6E8 + 0x20 + read-write + 0x00000000 + + + XFRC + XFRC + 0 + 1 + + + CHH + CHH + 1 + 1 + + + STALL + STALL + 3 + 1 + + + NAK + NAK + 4 + 1 + + + ACK + ACK + 5 + 1 + + + TXERR + TXERR + 7 + 1 + + + BBERR + BBERR + 8 + 1 + + + FRMOR + FRMOR + 9 + 1 + + + DTERR + DTERR + 10 + 1 + + + + + HCINTMSK11 + HCINTMSK11 + This register reflects the mask for each channel status described in the previous section. + 0x66C + 0x20 + read-write + 0x00000000 + + + XFRCM + XFRCM + 0 + 1 + + + CHHM + CHHM + 1 + 1 + + + STALLM + STALLM + 3 + 1 + + + NAKM + NAKM + 4 + 1 + + + ACKM + ACKM + 5 + 1 + + + TXERRM + TXERRM + 7 + 1 + + + BBERRM + BBERRM + 8 + 1 + + + FRMORM + FRMORM + 9 + 1 + + + DTERRM + DTERRM + 10 + 1 + + + + + HCINTMSK12 + HCINTMSK12 + This register reflects the mask for each channel status described in the previous section. + 0x68C + 0x20 + read-write + 0x00000000 + + + XFRCM + XFRCM + 0 + 1 + + + CHHM + CHHM + 1 + 1 + + + STALLM + STALLM + 3 + 1 + + + NAKM + NAKM + 4 + 1 + + + ACKM + ACKM + 5 + 1 + + + TXERRM + TXERRM + 7 + 1 + + + BBERRM + BBERRM + 8 + 1 + + + FRMORM + FRMORM + 9 + 1 + + + DTERRM + DTERRM + 10 + 1 + + + + + HCINTMSK13 + HCINTMSK13 + This register reflects the mask for each channel status described in the previous section. + 0x6AC + 0x20 + read-write + 0x00000000 + + + XFRCM + XFRCM + 0 + 1 + + + CHHM + CHHM + 1 + 1 + + + STALLM + STALLM + 3 + 1 + + + NAKM + NAKM + 4 + 1 + + + ACKM + ACKM + 5 + 1 + + + TXERRM + TXERRM + 7 + 1 + + + BBERRM + BBERRM + 8 + 1 + + + FRMORM + FRMORM + 9 + 1 + + + DTERRM + DTERRM + 10 + 1 + + + + + HCINTMSK14 + HCINTMSK14 + This register reflects the mask for each channel status described in the previous section. + 0x6CC + 0x20 + read-write + 0x00000000 + + + XFRCM + XFRCM + 0 + 1 + + + CHHM + CHHM + 1 + 1 + + + STALLM + STALLM + 3 + 1 + + + NAKM + NAKM + 4 + 1 + + + ACKM + ACKM + 5 + 1 + + + TXERRM + TXERRM + 7 + 1 + + + BBERRM + BBERRM + 8 + 1 + + + FRMORM + FRMORM + 9 + 1 + + + DTERRM + DTERRM + 10 + 1 + + + + + HCINTMSK15 + HCINTMSK15 + This register reflects the mask for each channel status described in the previous section. + 0x6EC + 0x20 + read-write + 0x00000000 + + + XFRCM + XFRCM + 0 + 1 + + + CHHM + CHHM + 1 + 1 + + + STALLM + STALLM + 3 + 1 + + + NAKM + NAKM + 4 + 1 + + + ACKM + ACKM + 5 + 1 + + + TXERRM + TXERRM + 7 + 1 + + + BBERRM + BBERRM + 8 + 1 + + + FRMORM + FRMORM + 9 + 1 + + + DTERRM + DTERRM + 10 + 1 + + + + + HCTSIZ11 + HCTSIZ11 + OTG host channel 11 transfer size register + 0x670 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + DPID + DPID + 29 + 2 + + + DOPNG + DOPNG + 31 + 1 + + + + + HCTSIZ12 + HCTSIZ12 + OTG host channel 12 transfer size register + 0x690 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + DPID + DPID + 29 + 2 + + + DOPNG + DOPNG + 31 + 1 + + + + + HCTSIZ13 + HCTSIZ13 + OTG host channel 13 transfer size register + 0x6B0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + DPID + DPID + 29 + 2 + + + DOPNG + DOPNG + 31 + 1 + + + + + HCTSIZ14 + HCTSIZ14 + OTG host channel 14 transfer size register + 0x6D0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + DPID + DPID + 29 + 2 + + + DOPNG + DOPNG + 31 + 1 + + + + + HCTSIZ15 + HCTSIZ15 + OTG host channel 15 transfer size register + 0x6F0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + DPID + DPID + 29 + 2 + + + DOPNG + DOPNG + 31 + 1 + + + + + DCFG + DCFG + This register configures the core in device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming. + 0x800 + 0x20 + read-write + 0x02200000 + + + DSPD + DSPD + 0 + 2 + + + NZLSOHSK + NZLSOHSK + 2 + 1 + + + DAD + DAD + 4 + 7 + + + PFIVL + PFIVL + 11 + 2 + + + ERRATIM + ERRATIM + 15 + 1 + + + + + DCTL + DCTL + OTG device control register + 0x804 + 0x20 + 0x00000002 + + + RWUSIG + RWUSIG + 0 + 1 + read-write + + + SDIS + SDIS + 1 + 1 + read-write + + + GINSTS + GINSTS + 2 + 1 + read-only + + + GONSTS + GONSTS + 3 + 1 + read-only + + + TCTL + TCTL + 4 + 3 + read-write + + + SGINAK + SGINAK + 7 + 1 + write-only + + + CGINAK + CGINAK + 8 + 1 + write-only + + + SGONAK + SGONAK + 9 + 1 + write-only + + + CGONAK + CGONAK + 10 + 1 + write-only + + + POPRGDNE + POPRGDNE + 11 + 1 + read-write + + + DSBESLRJCT + DSBESLRJCT + 18 + 1 + read-write + + + + + DSTS + DSTS + This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from the device all interrupts (DAINT) register. + 0x808 + 0x20 + read-only + 0x00000010 + + + SUSPSTS + SUSPSTS + 0 + 1 + + + ENUMSPD + ENUMSPD + 1 + 2 + + + EERR + EERR + 3 + 1 + + + FNSOF + FNSOF + 8 + 14 + + + DEVLNSTS + DEVLNSTS + 22 + 2 + + + + + DIEPMSK + DIEPMSK + This register works with each of the DIEPINTx registers for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the DIEPINTx register can be masked by writing to the corresponding bit in this register. Status bits are masked by default. + 0x810 + 0x20 + read-write + 0x00000000 + + + XFRCM + XFRCM + 0 + 1 + + + EPDM + EPDM + 1 + 1 + + + AHBERRM + AHBERRM + 2 + 1 + + + TOM + TOM + 3 + 1 + + + ITTXFEMSK + ITTXFEMSK + 4 + 1 + + + INEPNMM + INEPNMM + 5 + 1 + + + INEPNEM + INEPNEM + 6 + 1 + + + TXFURM + TXFURM + 8 + 1 + + + NAKM + NAKM + 13 + 1 + + + + + DOEPMSK + DOEPMSK + This register works with each of the DOEPINTx registers for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific status in the DOEPINTx register can be masked by writing into the corresponding bit in this register. Status bits are masked by default. + 0x814 + 0x20 + read-write + 0x00000000 + + + XFRCM + XFRCM + 0 + 1 + + + EPDM + EPDM + 1 + 1 + + + AHBERRM + AHBERRM + 2 + 1 + + + STUPM + STUPM + 3 + 1 + + + OTEPDM + OTEPDM + 4 + 1 + + + STSPHSRXM + STSPHSRXM + 5 + 1 + + + B2BSTUPM + B2BSTUPM + 6 + 1 + + + OUTPKTERRM + OUTPKTERRM + 8 + 1 + + + BERRM + BERRM + 12 + 1 + + + NAKMSK + NAKMSK + 13 + 1 + + + NYETMSK + NYETMSK + 14 + 1 + + + + + DAINT + DAINT + When a significant event occurs on an endpoint, a DAINT register interrupts the application using the device OUT endpoints interrupt bit or device IN endpoints interrupt bit of the GINTSTS register (OEPINT or IEPINT in GINTSTS, respectively). There is one interrupt bit per endpoint, up to a maximum of 16 bits for OUT endpoints and 16 bits for IN endpoints. For a bidirectional endpoint, the corresponding IN and OUT interrupt bits are used. Bits in this register are set and cleared when the application sets and clears bits in the corresponding device endpoint-x interrupt register (DIEPINTx/DOEPINTx). + 0x818 + 0x20 + read-only + 0x00000000 + + + IEPINT + IEPINT + 0 + 16 + + + OEPINT + OEPINT + 16 + 16 + + + + + DAINTMSK + DAINTMSK + The DAINTMSK register works with the device endpoint interrupt register to interrupt the application when an event occurs on a device endpoint. However, the DAINT register bit corresponding to that interrupt is still set. + 0x81C + 0x20 + read-write + 0x00000000 + + + IEPM + IEPM + 0 + 16 + + + OEPM + OEPM + 16 + 16 + + + + + DVBUSDIS + DVBUSDIS + This register specifies the VBUS discharge time after VBUS pulsing during SRP. + 0x828 + 0x20 + read-write + 0x000017D7 + + + VBUSDT + VBUSDT + 0 + 16 + + + + + DVBUSPULSE + DVBUSPULSE + This register specifies the VBUS pulsing time during SRP. + 0x82C + 0x20 + read-write + 0x000005B8 + + + DVBUSP + DVBUSP + 0 + 16 + + + + + DTHRCTL + DTHRCTL + OTG device threshold control register + 0x830 + 0x20 + read-write + 0x00000000 + + + NONISOTHREN + Nonisochronous IN endpoints threshold enable + When this bit is set, the core enables thresholding for nonisochronous IN endpoints. + 0 + 1 + read-write + + + ISOTHREN + ISO IN endpoint threshold enable + When this bit is set, the core enables thresholding for isochronous IN endpoints. + 1 + 1 + read-write + + + TXTHRLEN + Transmit threshold length + This field specifies the transmit thresholding size in 32-bit words. This field specifies the amount of data in bytes to be in the corresponding endpoint transmit FIFO, before the core can start transmitting on the USB. The threshold length has to be at least eight 32-bit words. This field controls both isochronous and nonisochronous IN endpoint thresholds. The recommended value for TXTHRLEN is to be the same as the programmed AHB burst length (HBSTLEN bit in OTG_GAHBCFG). + 2 + 9 + read-write + + + RXTHREN + Receive threshold enable + When this bit is set, the core enables thresholding in the receive direction. + 16 + 1 + read-write + + + RXTHRLEN + Receive threshold length + This field specifies the receive thresholding size in 32-bit words. This field also specifies the amount of data received on the USB before the core can start transmitting on the AHB. The threshold length has to be at least eight 32-bit words. The recommended value for RXTHRLEN is to be the same as the programmed AHB burst length (HBSTLEN bit in OTG_GAHBCFG). + 17 + 9 + read-write + + + ARPEN + Arbiter parking enable + This bit controls internal DMA arbiter parking for IN endpoints. When thresholding is enabled and this bit is set to one, then the arbiter parks on the IN endpoint for which there is a token received on the USB. This is done to avoid getting into underrun conditions. By default parking is enabled. + 27 + 1 + read-write + + + + + DIEPEMPMSK + DIEPEMPMSK + This register is used to control the IN endpoint FIFO empty interrupt generation (TXFE_DIEPINTx). + 0x834 + 0x20 + read-write + 0x00000000 + + + INEPTXFEM + INEPTXFEM + 0 + 16 + + + + + HS_DOEPEACHMSK1 + HS_DOEPEACHMSK1 + OTG device each OUT endpoint-1 interrupt mask register + 0x884 + 0x20 + read-write + 0x00000000 + + + XFRCM + XFRCM + 0 + 1 + + + EPDM + EPDM + 1 + 1 + + + AHBERRM + AHBERRM + 2 + 1 + + + STUPM + STUPM + 3 + 1 + + + OTEPDM + OTEPDM + 4 + 1 + + + B2BSTUPM + B2BSTUPM + 6 + 1 + + + OUTPKTERRM + OUTPKTERRM + 8 + 1 + + + BNAM + BNAM + 9 + 1 + + + BERRM + BERRM + 12 + 1 + + + NAKMSK + NAKMSK + 13 + 1 + + + NYETMSK + NYETMSK + 14 + 1 + + + + + DIEPCTL0 + DIEPCTL0 + The application uses this register to control the behavior of each logical endpoint other than endpoint 0. + 0x900 + 0x20 + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 2 + read-write + + + USBAEP + USBAEP + 15 + 1 + read-only + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EPTYP + EPTYP + 18 + 2 + read-write + + + STALL + STALL + 21 + 1 + read-write + + + TXFNUM + TXFNUM + 22 + 4 + read-write + + + CNAK + CNAK + 26 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + EPDIS + EPDIS + 30 + 1 + read-write + + + EPENA + EPENA + 31 + 1 + read-write + + + + + DIEPINT0 + DIEPINT0 + This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. + 0x908 + 0x20 + 0x00000080 + + + XFRC + XFRC + 0 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + INEPNM + INEPNM + 5 + 1 + read-write + + + INEPNE + INEPNE + 6 + 1 + read-only + + + TXFE + TXFE + 7 + 1 + read-only + + + PKTDRPSTS + PKTDRPSTS + 11 + 1 + read-write + + + NAK + NAK + 13 + 1 + read-write + + + + + DIEPTSIZ0 + DIEPTSIZ0 + The application must modify this register before enabling endpoint 0. + 0x910 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 7 + + + PKTCNT + PKTCNT + 19 + 2 + + + + + DTXFSTS0 + DTXFSTS0 + This read-only register contains the free space information for the device IN endpoint Tx FIFO. + 0x918 + 0x20 + read-only + 0x00000200 + + + INEPTFSAV + INEPTFSAV + 0 + 16 + + + + + DIEPCTL1 + DIEPCTL1 + The application uses this register to control the behavior of each logical endpoint other than endpoint 0. + 0x920 + 0x20 + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + USBAEP + USBAEP + 15 + 1 + read-write + + + EONUM_DPIP + EONUM_DPIP + 16 + 1 + read-only + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EPTYP + EPTYP + 18 + 2 + read-write + + + STALL + STALL + 21 + 1 + read-write + + + TXFNUM + TXFNUM + 22 + 4 + read-write + + + CNAK + CNAK + 26 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID_SEVNFRM + 28 + 1 + write-only + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + EPDIS + EPDIS + 30 + 1 + read-write + + + EPENA + EPENA + 31 + 1 + read-write + + + + + DIEPINT1 + DIEPINT1 + This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. + 0x928 + 0x20 + 0x00000080 + + + XFRC + XFRC + 0 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + INEPNM + INEPNM + 5 + 1 + read-write + + + INEPNE + INEPNE + 6 + 1 + read-only + + + TXFE + TXFE + 7 + 1 + read-only + + + PKTDRPSTS + PKTDRPSTS + 11 + 1 + read-write + + + NAK + NAK + 13 + 1 + read-write + + + + + DIEPTSIZ1 + DIEPTSIZ1 + The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. + 0x930 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + MCNT + MCNT + 29 + 2 + + + + + DIEPDMA1 + DIEPDMA1 + OTG device IN endpoint 1 DMA address register + 0x934 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + DTXFSTS1 + DTXFSTS1 + This read-only register contains the free space information for the device IN endpoint Tx FIFO. + 0x938 + 0x20 + read-only + 0x00000200 + + + INEPTFSAV + INEPTFSAV + 0 + 16 + + + + + DIEPCTL2 + DIEPCTL2 + The application uses this register to control the behavior of each logical endpoint other than endpoint 0. + 0x940 + 0x20 + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + USBAEP + USBAEP + 15 + 1 + read-write + + + EONUM_DPIP + EONUM_DPIP + 16 + 1 + read-only + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EPTYP + EPTYP + 18 + 2 + read-write + + + STALL + STALL + 21 + 1 + read-write + + + TXFNUM + TXFNUM + 22 + 4 + read-write + + + CNAK + CNAK + 26 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID_SEVNFRM + 28 + 1 + write-only + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + EPDIS + EPDIS + 30 + 1 + read-write + + + EPENA + EPENA + 31 + 1 + read-write + + + + + DIEPINT2 + DIEPINT2 + This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. + 0x948 + 0x20 + 0x00000080 + + + XFRC + XFRC + 0 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + INEPNM + INEPNM + 5 + 1 + read-write + + + INEPNE + INEPNE + 6 + 1 + read-only + + + TXFE + TXFE + 7 + 1 + read-only + + + PKTDRPSTS + PKTDRPSTS + 11 + 1 + read-write + + + NAK + NAK + 13 + 1 + read-write + + + + + DIEPTSIZ2 + DIEPTSIZ2 + The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. + 0x950 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + MCNT + MCNT + 29 + 2 + + + + + DIEPDMA2 + DIEPDMA2 + OTG device IN endpoint 2 DMA address register + 0x954 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + DTXFSTS2 + DTXFSTS2 + This read-only register contains the free space information for the device IN endpoint Tx FIFO. + 0x958 + 0x20 + read-only + 0x00000200 + + + INEPTFSAV + INEPTFSAV + 0 + 16 + + + + + DIEPCTL3 + DIEPCTL3 + The application uses this register to control the behavior of each logical endpoint other than endpoint 0. + 0x960 + 0x20 + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + USBAEP + USBAEP + 15 + 1 + read-write + + + EONUM_DPIP + EONUM_DPIP + 16 + 1 + read-only + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EPTYP + EPTYP + 18 + 2 + read-write + + + STALL + STALL + 21 + 1 + read-write + + + TXFNUM + TXFNUM + 22 + 4 + read-write + + + CNAK + CNAK + 26 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID_SEVNFRM + 28 + 1 + write-only + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + EPDIS + EPDIS + 30 + 1 + read-write + + + EPENA + EPENA + 31 + 1 + read-write + + + + + DIEPINT3 + DIEPINT3 + This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. + 0x968 + 0x20 + 0x00000080 + + + XFRC + XFRC + 0 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + INEPNM + INEPNM + 5 + 1 + read-write + + + INEPNE + INEPNE + 6 + 1 + read-only + + + TXFE + TXFE + 7 + 1 + read-only + + + PKTDRPSTS + PKTDRPSTS + 11 + 1 + read-write + + + NAK + NAK + 13 + 1 + read-write + + + + + DIEPTSIZ3 + DIEPTSIZ3 + The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. + 0x970 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + MCNT + MCNT + 29 + 2 + + + + + DIEPDMA3 + DIEPDMA3 + OTG device IN endpoint 3 DMA address register + 0x974 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + DTXFSTS3 + DTXFSTS3 + This read-only register contains the free space information for the device IN endpoint Tx FIFO. + 0x978 + 0x20 + read-only + 0x00000200 + + + INEPTFSAV + INEPTFSAV + 0 + 16 + + + + + DIEPCTL4 + DIEPCTL4 + The application uses this register to control the behavior of each logical endpoint other than endpoint 0. + 0x980 + 0x20 + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + USBAEP + USBAEP + 15 + 1 + read-write + + + EONUM_DPIP + EONUM_DPIP + 16 + 1 + read-only + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EPTYP + EPTYP + 18 + 2 + read-write + + + STALL + STALL + 21 + 1 + read-write + + + TXFNUM + TXFNUM + 22 + 4 + read-write + + + CNAK + CNAK + 26 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID_SEVNFRM + 28 + 1 + write-only + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + EPDIS + EPDIS + 30 + 1 + read-write + + + EPENA + EPENA + 31 + 1 + read-write + + + + + DIEPINT4 + DIEPINT4 + This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. + 0x988 + 0x20 + 0x00000080 + + + XFRC + XFRC + 0 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + INEPNM + INEPNM + 5 + 1 + read-write + + + INEPNE + INEPNE + 6 + 1 + read-only + + + TXFE + TXFE + 7 + 1 + read-only + + + PKTDRPSTS + PKTDRPSTS + 11 + 1 + read-write + + + NAK + NAK + 13 + 1 + read-write + + + + + DIEPTSIZ4 + DIEPTSIZ4 + The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. + 0x990 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + MCNT + MCNT + 29 + 2 + + + + + DIEPDMA4 + DIEPDMA4 + OTG device IN endpoint 4 DMA address register + 0x994 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + DTXFSTS4 + DTXFSTS4 + This read-only register contains the free space information for the device IN endpoint Tx FIFO. + 0x998 + 0x20 + read-only + 0x00000200 + + + INEPTFSAV + INEPTFSAV + 0 + 16 + + + + + DIEPCTL5 + DIEPCTL5 + The application uses this register to control the behavior of each logical endpoint other than endpoint 0. + 0x9A0 + 0x20 + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + USBAEP + USBAEP + 15 + 1 + read-write + + + EONUM_DPIP + EONUM_DPIP + 16 + 1 + read-only + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EPTYP + EPTYP + 18 + 2 + read-write + + + STALL + STALL + 21 + 1 + read-write + + + TXFNUM + TXFNUM + 22 + 4 + read-write + + + CNAK + CNAK + 26 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID_SEVNFRM + 28 + 1 + write-only + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + EPDIS + EPDIS + 30 + 1 + read-write + + + EPENA + EPENA + 31 + 1 + read-write + + + + + DIEPINT5 + DIEPINT5 + This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. + 0x9A8 + 0x20 + 0x00000080 + + + XFRC + XFRC + 0 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + INEPNM + INEPNM + 5 + 1 + read-write + + + INEPNE + INEPNE + 6 + 1 + read-only + + + TXFE + TXFE + 7 + 1 + read-only + + + PKTDRPSTS + PKTDRPSTS + 11 + 1 + read-write + + + NAK + NAK + 13 + 1 + read-write + + + + + DIEPTSIZ5 + DIEPTSIZ5 + The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. + 0x9B0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + MCNT + MCNT + 29 + 2 + + + + + DIEPDMA5 + DIEPDMA5 + OTG device IN endpoint 5 DMA address register + 0x9B4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + DTXFSTS5 + DTXFSTS5 + This read-only register contains the free space information for the device IN endpoint Tx FIFO. + 0x9B8 + 0x20 + read-only + 0x00000200 + + + INEPTFSAV + INEPTFSAV + 0 + 16 + + + + + DIEPINT6 + DIEPINT6 + This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. + 0x9C8 + 0x20 + 0x00000080 + + + XFRC + XFRC + 0 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + AHBERR + AHBERR + 2 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + INEPNM + INEPNM + 5 + 1 + read-write + + + INEPNE + INEPNE + 6 + 1 + read-only + + + TXFE + TXFE + 7 + 1 + read-only + + + TXFIFOUDRN + TXFIFOUDRN + 8 + 1 + read-write + + + BNA + BNA + 9 + 1 + read-write + + + PKTDRPSTS + PKTDRPSTS + 11 + 1 + read-write + + + NAK + NAK + 13 + 1 + read-write + + + + + DIEPTSIZ6 + DIEPTSIZ6 + The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. + 0x9D0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + MCNT + MCNT + 29 + 2 + + + + + DIEPDMA6 + DIEPDMA6 + OTG device IN endpoint 6 DMA address register + 0x9D4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + DIEPINT7 + DIEPINT7 + This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. + 0x9E8 + 0x20 + 0x00000080 + + + XFRC + XFRC + 0 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + AHBERR + AHBERR + 2 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + INEPNM + INEPNM + 5 + 1 + read-write + + + INEPNE + INEPNE + 6 + 1 + read-only + + + TXFE + TXFE + 7 + 1 + read-only + + + TXFIFOUDRN + TXFIFOUDRN + 8 + 1 + read-write + + + BNA + BNA + 9 + 1 + read-write + + + PKTDRPSTS + PKTDRPSTS + 11 + 1 + read-write + + + NAK + NAK + 13 + 1 + read-write + + + + + DIEPTSIZ7 + DIEPTSIZ7 + The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. + 0x9F0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + MCNT + MCNT + 29 + 2 + + + + + DIEPDMA7 + DIEPDMA7 + OTG device IN endpoint 7 DMA address register + 0x9F4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + DIEPINT8 + DIEPINT8 + This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. + 0xA08 + 0x20 + 0x00000080 + + + XFRC + XFRC + 0 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + AHBERR + AHBERR + 2 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + INEPNM + INEPNM + 5 + 1 + read-write + + + INEPNE + INEPNE + 6 + 1 + read-only + + + TXFE + TXFE + 7 + 1 + read-only + + + TXFIFOUDRN + TXFIFOUDRN + 8 + 1 + read-write + + + BNA + BNA + 9 + 1 + read-write + + + PKTDRPSTS + PKTDRPSTS + 11 + 1 + read-write + + + NAK + NAK + 13 + 1 + read-write + + + + + DIEPTSIZ8 + DIEPTSIZ8 + The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. + 0xA10 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + MCNT + MCNT + 29 + 2 + + + + + DIEPDMA8 + DIEPDMA8 + OTG device IN endpoint 8 DMA address register + 0xA14 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + DOEPCTL0 + DOEPCTL0 + This section describes the DOEPCTL0 register. + 0xB00 + 0x20 + 0x00008000 + + + MPSIZ + MPSIZ + 0 + 2 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-only + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EPTYP + EPTYP + 18 + 2 + read-only + + + SNPM + SNPM + 20 + 1 + read-write + + + STALL + STALL + 21 + 1 + read-write + + + CNAK + CNAK + 26 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + EPDIS + EPDIS + 30 + 1 + read-only + + + EPENA + EPENA + 31 + 1 + write-only + + + + + DOEPINT0 + DOEPINT0 + This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. + 0xB08 + 0x20 + read-write + 0x00000080 + + + XFRC + XFRC + 0 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + AHBERR + AHBERR + 2 + 1 + + + STUP + STUP + 3 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STSPHSRX + STSPHSRX + 5 + 1 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OUTPKTERR + OUTPKTERR + 8 + 1 + + + BNA + BNA + 9 + 1 + + + BERR + BERR + 12 + 1 + + + NAK + NAK + 13 + 1 + + + NYET + NYET + 14 + 1 + + + STPKTRX + STPKTRX + 15 + 1 + + + + + DOEPTSIZ0 + DOEPTSIZ0 + The application must modify this register before enabling endpoint 0. + 0xB10 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 7 + + + PKTCNT + PKTCNT + 19 + 1 + + + STUPCNT + STUPCNT + 29 + 2 + + + + + DOEPDMA0 + DOEPDMA0 + OTG device OUT endpoint 0 DMA address register + 0xB14 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + DOEPCTL1 + DOEPCTL1 + The application uses this register to control the behavior of each logical endpoint other than endpoint 0. + 0xB20 + 0x20 + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + USBAEP + USBAEP + 15 + 1 + read-write + + + EONUM_DPIP + EONUM_DPIP + 16 + 1 + read-only + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EPTYP + EPTYP + 18 + 2 + read-write + + + SNPM + SNPM + 20 + 1 + read-write + + + STALL + STALL + 21 + 1 + read-write + + + CNAK + CNAK + 26 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID_SEVNFRM + 28 + 1 + write-only + + + SD1PID_SODDFRM + SD1PID_SODDFRM + 29 + 1 + write-only + + + EPDIS + EPDIS + 30 + 1 + read-write + + + EPENA + EPENA + 31 + 1 + read-write + + + + + DOEPINT1 + DOEPINT1 + This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. + 0xB28 + 0x20 + read-write + 0x00000080 + + + XFRC + XFRC + 0 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + AHBERR + AHBERR + 2 + 1 + + + STUP + STUP + 3 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STSPHSRX + STSPHSRX + 5 + 1 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OUTPKTERR + OUTPKTERR + 8 + 1 + + + BNA + BNA + 9 + 1 + + + BERR + BERR + 12 + 1 + + + NAK + NAK + 13 + 1 + + + NYET + NYET + 14 + 1 + + + STPKTRX + STPKTRX + 15 + 1 + + + + + DOEPTSIZ1 + DOEPTSIZ1 + The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. + 0xB30 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + RXDPID_STUPCNT + RXDPID_STUPCNT + 29 + 2 + + + + + DOEPDMA1 + DOEPDMA1 + OTG device OUT endpoint 1 DMA address register + 0xB34 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + DOEPCTL2 + DOEPCTL2 + The application uses this register to control the behavior of each logical endpoint other than endpoint 0. + 0xB40 + 0x20 + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + USBAEP + USBAEP + 15 + 1 + read-write + + + EONUM_DPIP + EONUM_DPIP + 16 + 1 + read-only + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EPTYP + EPTYP + 18 + 2 + read-write + + + SNPM + SNPM + 20 + 1 + read-write + + + STALL + STALL + 21 + 1 + read-write + + + CNAK + CNAK + 26 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID_SEVNFRM + 28 + 1 + write-only + + + SD1PID_SODDFRM + SD1PID_SODDFRM + 29 + 1 + write-only + + + EPDIS + EPDIS + 30 + 1 + read-write + + + EPENA + EPENA + 31 + 1 + read-write + + + + + DOEPINT2 + DOEPINT2 + This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. + 0xB48 + 0x20 + read-write + 0x00000080 + + + XFRC + XFRC + 0 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + AHBERR + AHBERR + 2 + 1 + + + STUP + STUP + 3 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STSPHSRX + STSPHSRX + 5 + 1 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OUTPKTERR + OUTPKTERR + 8 + 1 + + + BNA + BNA + 9 + 1 + + + BERR + BERR + 12 + 1 + + + NAK + NAK + 13 + 1 + + + NYET + NYET + 14 + 1 + + + STPKTRX + STPKTRX + 15 + 1 + + + + + DOEPTSIZ2 + DOEPTSIZ2 + The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. + 0xB50 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + RXDPID_STUPCNT + RXDPID_STUPCNT + 29 + 2 + + + + + DOEPDMA2 + DOEPDMA2 + OTG device OUT endpoint 2 DMA address register + 0xB54 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + DOEPCTL3 + DOEPCTL3 + The application uses this register to control the behavior of each logical endpoint other than endpoint 0. + 0xB60 + 0x20 + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + USBAEP + USBAEP + 15 + 1 + read-write + + + EONUM_DPIP + EONUM_DPIP + 16 + 1 + read-only + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EPTYP + EPTYP + 18 + 2 + read-write + + + SNPM + SNPM + 20 + 1 + read-write + + + STALL + STALL + 21 + 1 + read-write + + + CNAK + CNAK + 26 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID_SEVNFRM + 28 + 1 + write-only + + + SD1PID_SODDFRM + SD1PID_SODDFRM + 29 + 1 + write-only + + + EPDIS + EPDIS + 30 + 1 + read-write + + + EPENA + EPENA + 31 + 1 + read-write + + + + + DOEPINT3 + DOEPINT3 + This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. + 0xB68 + 0x20 + read-write + 0x00000080 + + + XFRC + XFRC + 0 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + AHBERR + AHBERR + 2 + 1 + + + STUP + STUP + 3 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STSPHSRX + STSPHSRX + 5 + 1 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OUTPKTERR + OUTPKTERR + 8 + 1 + + + BNA + BNA + 9 + 1 + + + BERR + BERR + 12 + 1 + + + NAK + NAK + 13 + 1 + + + NYET + NYET + 14 + 1 + + + STPKTRX + STPKTRX + 15 + 1 + + + + + DOEPTSIZ3 + DOEPTSIZ3 + The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. + 0xB70 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + RXDPID_STUPCNT + RXDPID_STUPCNT + 29 + 2 + + + + + DOEPDMA3 + DOEPDMA3 + OTG device OUT endpoint 3 DMA address register + 0xB74 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + DOEPCTL4 + DOEPCTL4 + The application uses this register to control the behavior of each logical endpoint other than endpoint 0. + 0xB80 + 0x20 + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + USBAEP + USBAEP + 15 + 1 + read-write + + + EONUM_DPIP + EONUM_DPIP + 16 + 1 + read-only + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EPTYP + EPTYP + 18 + 2 + read-write + + + SNPM + SNPM + 20 + 1 + read-write + + + STALL + STALL + 21 + 1 + read-write + + + CNAK + CNAK + 26 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID_SEVNFRM + 28 + 1 + write-only + + + SD1PID_SODDFRM + SD1PID_SODDFRM + 29 + 1 + write-only + + + EPDIS + EPDIS + 30 + 1 + read-write + + + EPENA + EPENA + 31 + 1 + read-write + + + + + DOEPINT4 + DOEPINT4 + This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. + 0xB88 + 0x20 + read-write + 0x00000080 + + + XFRC + XFRC + 0 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + AHBERR + AHBERR + 2 + 1 + + + STUP + STUP + 3 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STSPHSRX + STSPHSRX + 5 + 1 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OUTPKTERR + OUTPKTERR + 8 + 1 + + + BNA + BNA + 9 + 1 + + + BERR + BERR + 12 + 1 + + + NAK + NAK + 13 + 1 + + + NYET + NYET + 14 + 1 + + + STPKTRX + STPKTRX + 15 + 1 + + + + + DOEPTSIZ4 + DOEPTSIZ4 + The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. + 0xB90 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + RXDPID_STUPCNT + RXDPID_STUPCNT + 29 + 2 + + + + + DOEPDMA4 + DOEPDMA4 + OTG device OUT endpoint 4 DMA address register + 0xB94 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + DOEPCTL5 + DOEPCTL5 + The application uses this register to control the behavior of each logical endpoint other than endpoint 0. + 0xBA0 + 0x20 + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + USBAEP + USBAEP + 15 + 1 + read-write + + + EONUM_DPIP + EONUM_DPIP + 16 + 1 + read-only + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EPTYP + EPTYP + 18 + 2 + read-write + + + SNPM + SNPM + 20 + 1 + read-write + + + STALL + STALL + 21 + 1 + read-write + + + CNAK + CNAK + 26 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID_SEVNFRM + 28 + 1 + write-only + + + SD1PID_SODDFRM + SD1PID_SODDFRM + 29 + 1 + write-only + + + EPDIS + EPDIS + 30 + 1 + read-write + + + EPENA + EPENA + 31 + 1 + read-write + + + + + DOEPINT5 + DOEPINT5 + This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. + 0xBA8 + 0x20 + read-write + 0x00000080 + + + XFRC + XFRC + 0 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + AHBERR + AHBERR + 2 + 1 + + + STUP + STUP + 3 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STSPHSRX + STSPHSRX + 5 + 1 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OUTPKTERR + OUTPKTERR + 8 + 1 + + + BNA + BNA + 9 + 1 + + + BERR + BERR + 12 + 1 + + + NAK + NAK + 13 + 1 + + + NYET + NYET + 14 + 1 + + + STPKTRX + STPKTRX + 15 + 1 + + + + + DOEPTSIZ5 + DOEPTSIZ5 + The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. + 0xBB0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + RXDPID_STUPCNT + RXDPID_STUPCNT + 29 + 2 + + + + + DOEPDMA5 + DOEPDMA5 + OTG device OUT endpoint 5 DMA address register + 0xBB4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + DOEPCTL6 + DOEPCTL6 + The application uses this register to control the behavior of each logical endpoint other than endpoint 0. + 0xBC0 + 0x20 + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + USBAEP + USBAEP + 15 + 1 + read-write + + + EONUM_DPIP + EONUM_DPIP + 16 + 1 + read-only + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EPTYP + EPTYP + 18 + 2 + read-write + + + SNPM + SNPM + 20 + 1 + read-write + + + STALL + STALL + 21 + 1 + read-write + + + CNAK + CNAK + 26 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID_SEVNFRM + 28 + 1 + write-only + + + SD1PID_SODDFRM + SD1PID_SODDFRM + 29 + 1 + write-only + + + EPDIS + EPDIS + 30 + 1 + read-write + + + EPENA + EPENA + 31 + 1 + read-write + + + + + DOEPINT6 + DOEPINT6 + This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. + 0xBC8 + 0x20 + read-write + 0x00000080 + + + XFRC + XFRC + 0 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + AHBERR + AHBERR + 2 + 1 + + + STUP + STUP + 3 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STSPHSRX + STSPHSRX + 5 + 1 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OUTPKTERR + OUTPKTERR + 8 + 1 + + + BNA + BNA + 9 + 1 + + + BERR + BERR + 12 + 1 + + + NAK + NAK + 13 + 1 + + + NYET + NYET + 14 + 1 + + + STPKTRX + STPKTRX + 15 + 1 + + + + + DOEPTSIZ6 + DOEPTSIZ6 + The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. + 0xBD0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + RXDPID_STUPCNT + RXDPID_STUPCNT + 29 + 2 + + + + + DOEPDMA6 + DOEPDMA6 + OTG device OUT endpoint 6 DMA address register + 0xBD4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + DOEPCTL7 + DOEPCTL7 + The application uses this register to control the behavior of each logical endpoint other than endpoint 0. + 0xBE0 + 0x20 + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + USBAEP + USBAEP + 15 + 1 + read-write + + + EONUM_DPIP + EONUM_DPIP + 16 + 1 + read-only + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EPTYP + EPTYP + 18 + 2 + read-write + + + SNPM + SNPM + 20 + 1 + read-write + + + STALL + STALL + 21 + 1 + read-write + + + CNAK + CNAK + 26 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID_SEVNFRM + 28 + 1 + write-only + + + SD1PID_SODDFRM + SD1PID_SODDFRM + 29 + 1 + write-only + + + EPDIS + EPDIS + 30 + 1 + read-write + + + EPENA + EPENA + 31 + 1 + read-write + + + + + DOEPINT7 + DOEPINT7 + This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. + 0xBE8 + 0x20 + read-write + 0x00000080 + + + XFRC + XFRC + 0 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + AHBERR + AHBERR + 2 + 1 + + + STUP + STUP + 3 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STSPHSRX + STSPHSRX + 5 + 1 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OUTPKTERR + OUTPKTERR + 8 + 1 + + + BNA + BNA + 9 + 1 + + + BERR + BERR + 12 + 1 + + + NAK + NAK + 13 + 1 + + + NYET + NYET + 14 + 1 + + + STPKTRX + STPKTRX + 15 + 1 + + + + + DOEPTSIZ7 + DOEPTSIZ7 + The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. + 0xBF0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + RXDPID_STUPCNT + RXDPID_STUPCNT + 29 + 2 + + + + + DOEPDMA7 + DOEPDMA7 + OTG device OUT endpoint 7 DMA address register + 0xBF4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + DOEPCTL8 + DOEPCTL8 + The application uses this register to control the behavior of each logical endpoint other than endpoint 0. + 0xC00 + 0x20 + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + USBAEP + USBAEP + 15 + 1 + read-write + + + EONUM_DPIP + EONUM_DPIP + 16 + 1 + read-only + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EPTYP + EPTYP + 18 + 2 + read-write + + + SNPM + SNPM + 20 + 1 + read-write + + + STALL + STALL + 21 + 1 + read-write + + + CNAK + CNAK + 26 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID_SEVNFRM + 28 + 1 + write-only + + + SD1PID_SODDFRM + SD1PID_SODDFRM + 29 + 1 + write-only + + + EPDIS + EPDIS + 30 + 1 + read-write + + + EPENA + EPENA + 31 + 1 + read-write + + + + + DOEPINT8 + DOEPINT8 + This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. + 0xC08 + 0x20 + read-write + 0x00000080 + + + XFRC + XFRC + 0 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + AHBERR + AHBERR + 2 + 1 + + + STUP + STUP + 3 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STSPHSRX + STSPHSRX + 5 + 1 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OUTPKTERR + OUTPKTERR + 8 + 1 + + + BNA + BNA + 9 + 1 + + + BERR + BERR + 12 + 1 + + + NAK + NAK + 13 + 1 + + + NYET + NYET + 14 + 1 + + + STPKTRX + STPKTRX + 15 + 1 + + + + + DOEPTSIZ8 + DOEPTSIZ8 + The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. + 0xC10 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + RXDPID_STUPCNT + RXDPID_STUPCNT + 29 + 2 + + + + + DOEPDMA8 + DOEPDMA8 + OTG device OUT endpoint 8 DMA address register + 0xC14 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + PCGCCTL + PCGCCTL + This register is available in host and device modes. + 0xE00 + 0x20 + 0x200B8000 + + + STPPCLK + STPPCLK + 0 + 1 + read-write + + + GATEHCLK + GATEHCLK + 1 + 1 + read-write + + + PHYSUSP + PHYSUSP + 4 + 1 + read-only + + + ENL1GTG + ENL1GTG + 5 + 1 + read-write + + + PHYSLEEP + PHYSLEEP + 6 + 1 + read-only + + + SUSP + SUSP + 7 + 1 + read-only + + + + + + + SEC_OTG_HS + DCB->DSCSR->CDS == 0 + 0x52040000 + + + PKA + Private key accelerator + PKA + 0x420C2000 + + 0x0 + 0x2000 + registers + + + PKA + PKA global interrupt + 097 + + + + CR + CR + Control register + 0x0 + 0x20 + read-write + 0x00000000 + + + OPERRIE + Operation error interrupt enable + 21 + 1 + + + ADDRERRIE + Address error interrupt + enable + 20 + 1 + + + RAMERRIE + RAM error interrupt enable + 19 + 1 + + + PROCENDIE + End of operation interrupt + enable + 17 + 1 + + + MODE + PKA Operation Mode + 8 + 6 + + + START + Start the operation + 1 + 1 + + + EN + Peripheral Enable + 0 + 1 + + + + + SR + SR + PKA status register + 0x4 + 0x20 + read-only + 0x00000000 + + + INITOK + INITOK + 0 + 1 + + + BUSY + PKA operation is in + progress + 16 + 1 + + + PROCENDF + PKA End of Operation flag + 17 + 1 + + + RAMERRF + RAMERRF + 19 + 1 + + + ADDRERRF + ADDRERRF + 20 + 1 + + + OPERRF + OPERRF + 21 + 1 + + + + + CLRFR + CLRFR + PKA clear flag register + 0x8 + 0x20 + write-only + 0x00000000 + + + PROCENDFC + Clear PKA End of Operation + flag + 17 + 1 + + + RAMERRFC + RAMERRFC + 19 + 1 + + + ADDRERRFC + ADDRERRFC + 20 + 1 + + + OPERRFC + OPERRFC + 21 + 1 + + + + + + + SEC_PKA + DCB->DSCSR->CDS == 0 + 0x520C2000 + + + PSSI + PSSI + PSSI + 0x4202C400 + + 0x0 + 0x400 + registers + + + + CR + CR + PSSI control register + 0x0 + 0x20 + read-write + 0x40000000 + + + CKPOL + Parallel data clock polarity + This bit configures the capture edge of the parallel clock or the edge used for driving outputs, depending on OUTEN. + 5 + 1 + + + DEPOL + Data enable (PSSI_DE) polarity + This bit indicates the level on the PSSI_DE pin when the data are not valid on the parallel interface. + 6 + 1 + + + RDYPOL + Ready (PSSI_RDY) polarity + This bit indicates the level on the PSSI_RDY pin when the data are not valid on the parallel interface. + 8 + 1 + + + EDM + Extended data mode + 10 + 2 + + + ENABLE + PSSI enable + The contents of the FIFO are flushed when ENABLE is cleared to 0. + Note: When ENABLE=1, the content of PSSI_CR must not be changed, except for the ENABLE bit itself. All configuration bits can change as soon as ENABLE changes from 0 to 1. + The DMA controller and all PSSI configuration registers must be programmed correctly before setting the ENABLE bit to 1. + The ENABLE bit and the DCMI ENABLE bit (bit 15 of DCMI_CR) must not be set to 1 at the same time. + 14 + 1 + + + DERDYCFG + Data enable and ready configuration + When the PSSI_RDY function is mapped to the PSSI_DE pin (settings 101 or 111), it is still the RDYPOL bit which determines its polarity. Similarly, when the PSSI_DE function is mapped to the PSSI_RDY pin (settings 110 or 111), it is still the DEPOL bit which determines its polarity. + 18 + 3 + + + DMAEN + DMA enable bit + 30 + 1 + + + OUTEN + Data direction selection bit + 31 + 1 + + + + + SR + SR + PSSI status register + 0x4 + 0x20 + read-only + 0x00000000 + + + RTT4B + RTT4B + 2 + 1 + + + RTT1B + RTT1B + 3 + 1 + + + + + RIS + RIS + PSSI raw interrupt status register + 0x8 + 0x20 + read-only + 0x00000000 + + + OVR_RIS + OVR_RIS + 1 + 1 + + + + + IER + IER + PSSI interrupt enable register + 0xC + 0x20 + read-write + 0x00000000 + + + OVR_IE + OVR_IE + 1 + 1 + + + + + MIS + MIS + PSSI masked interrupt status register + 0x10 + 0x20 + read-only + 0x00000000 + + + OVR_MIS + OVR_MIS + 1 + 1 + + + + + ICR + ICR + PSSI interrupt clear register + 0x14 + 0x20 + write-only + 0x00000000 + + + OVR_ISC + OVR_ISC + 1 + 1 + + + + + DR + DR + PSSI data register + 0x28 + 0x20 + read-write + 0xC0000000 + + + BYTE0 + Data byte 0 + 0 + 8 + + + BYTE1 + Data byte 1 + 8 + 8 + + + BYTE2 + Data byte 2 + 16 + 8 + + + BYTE3 + Data byte 3 + 24 + 8 + + + + + + + SEC_PSSI + DCB->DSCSR->CDS == 0 + 0x5202C400 + + + PWR + Power control + PWR + 0x46020800 + + 0x0 + 0x400 + registers + + + PWR_S3WU + PWR wakeup from Stop 3 interrupt + 077 + + + + PWR_CR1 + PWR_CR1 + PWR control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LPMS + Low-power mode selection +These bits select the low-power mode entered when the CPU enters the Deepsleep mode. +10x: Standby mode (Standby mode also entered if LPMS = 11X in PWR_CR1 +with BREN = 1 in PWR_BDCR1) +11x: Shutdown mode if BREN = 0 in PWR_BDCR1 + 0 + 3 + read-write + + + B_0x0 + Stop 0 mode + 0x0 + + + B_0x1 + Stop 1 mode + 0x1 + + + B_0x2 + Stop 2 mode + 0x2 + + + B_0x3 + Stop 3 mode + 0x3 + + + + + RRSB1 + SRAM2 page 1 retention in Stop 3 and Standby modes +This bit is used to keep the SRAM2 page 1 content in Stop 3 and Standby modes. The SRAM2 page 1 corresponds to the first 8 Kbytes of the SRAM2 +(from SRAM2 base address to SRAM2 base address + 0x1FFF). +Note: This bit has no effect in Shutdown mode. + 5 + 1 + read-write + + + B_0x0 + SRAM2 page1 content not retained in Stop 3 and Standby modes + 0x0 + + + B_0x1 + SRAM2 page1 content retained in Stop 3 and Standby modes + 0x1 + + + + + RRSB2 + SRAM2 page 2 retention in Stop 3 and Standby modes +This bit is used to keep the SRAM2 page 2 content in Stop 3 and Standby modes. The SRAM2 page 2 corresponds to the last 56 Kbytes of the SRAM2 +(from SRAM2 base address + 0x2000 to SRAM2 base address + 0xFFFF). +Note: This bit has no effect in Shutdown mode. + 6 + 1 + read-write + + + B_0x0 + SRAM2 page2 content not retained in Stop3 and Standby modes + 0x0 + + + B_0x1 + SRAM2 page2 content retained in Stop 3 and Standby modes + 0x1 + + + + + ULPMEN + BOR ultra-low power mode +This bit is used to reduce the consumption by configuring the BOR in discontinuous mode. +This bit must be set to reach the lowest power consumption in the low-power modes. + 7 + 1 + read-write + + + B_0x0 + BOR operating in continuous (normal) mode in Stop 1, Stop 2, Stop 3 and Standby modes and when the regulator is in range 4 (Run, Sleep or Stop 0 mode) + 0x0 + + + B_0x1 + BOR operating in discontinuous (ultra-low power) mode in Stop 1, Stop 2, Stop 3 and Standby modes, and when the regulator is in range 4 (Run, Sleep or Stop 0 mode) + 0x1 + + + + + SRAM1PD + SRAM1 power down +This bit is used to reduce the consumption by powering off the SRAM1. + 8 + 1 + read-write + + + B_0x0 + SRAM1 powered on + 0x0 + + + B_0x1 + SRAM1 powered off + 0x1 + + + + + SRAM2PD + SRAM2 power down +This bit is used to reduce the consumption by powering off the SRAM2. + 9 + 1 + read-write + + + B_0x0 + SRAM2 powered on + 0x0 + + + B_0x1 + SRAM2 powered off + 0x1 + + + + + SRAM3PD + SRAM3 power down +This bit is used to reduce the consumption by powering off the SRAM3. + 10 + 1 + read-write + + + B_0x0 + SRAM3 powered on + 0x0 + + + B_0x1 + SRAM3 powered off + 0x1 + + + + + SRAM4PD + SRAM4 power down +This bit is used to reduce the consumption by powering off the SRAM4. + 11 + 1 + read-write + + + B_0x0 + SRAM4 powered on + 0x0 + + + B_0x1 + SRAM4 powered off + 0x1 + + + + + SRAM5PD + SRAM5 power down +This bit is used to reduce the consumption by powering off the SRAM5. +Note: This bit is only available in STM32U59x/5Ax. It is reserved in STM32U575/585. + 12 + 1 + read-write + + + B_0x0 + SRAM5 powered on + 0x0 + + + B_0x1 + SRAM5 powered off + 0x1 + + + + + + + PWR_CR2 + PWR_CR2 + PWR control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SRAM1PDS1 + SRAM1 page 1 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) + 0 + 1 + read-write + + + B_0x0 + SRAM1 page 1 content retained in Stop modes + 0x0 + + + B_0x1 + SRAM1 page 1 content lost in Stop modes + 0x1 + + + + + SRAM1PDS2 + SRAM1 page 2 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) + 1 + 1 + read-write + + + B_0x0 + SRAM1 page 2 content retained in Stop modes + 0x0 + + + B_0x1 + SRAM1 page 2 content lost in Stop modes + 0x1 + + + + + SRAM1PDS3 + SRAM1 page 3 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) + 2 + 1 + read-write + + + B_0x0 + SRAM1 page 3 content retained in Stop modes + 0x0 + + + B_0x1 + SRAM1 page 3 content lost in Stop modes + 0x1 + + + + + SRAM2PDS1 + SRAM2 page 1 (8 Kbytes) power-down in Stop modes (Stop 0, 1, 2) +Note: The SRAM2 page 1 retention in Stop 3 is controlled by RRSB1 bit in PWR_CR1. + 4 + 1 + read-write + + + B_0x0 + SRAM2 page 1 content retained in Stop modes + 0x0 + + + B_0x1 + SRAM2 page 1 content lost in Stop modes + 0x1 + + + + + SRAM2PDS2 + SRAM2 page 2 (56 Kbytes) power-down in Stop modes (Stop 0, 1, 2) +Note: The SRAM2 page 2 retention in Stop 3 is controlled by RRSB2 bit in PWR_CR1. + 5 + 1 + read-write + + + B_0x0 + SRAM2 page 2 content retained in Stop modes + 0x0 + + + B_0x1 + SRAM2 page 2 content lost in Stop modes + 0x1 + + + + + SRAM4PDS + SRAM4 power-down in Stop modes (Stop 0, 1, 2, 3) + 6 + 1 + read-write + + + B_0x0 + SRAM4 content retained in Stop modes + 0x0 + + + B_0x1 + SRAM4 content lost in Stop modes + 0x1 + + + + + DC2RAMPDS + DCACHE2 SRAM power-down in Stop modes (Stop 0, 1, 2, 3) +Note: This bit is only available in STM32U59x/5Ax. It is reserved in STM32U575/585. + 7 + 1 + read-write + + + B_0x0 + DCACHE2 SRAM content retained in Stop modes + 0x0 + + + B_0x1 + DCACHE2 SRAM content lost in Stop modes + 0x1 + + + + + ICRAMPDS + ICACHE SRAM power-down in Stop modes (Stop 0, 1, 2, 3) + 8 + 1 + read-write + + + B_0x0 + ICACHE SRAM content retained in Stop modes + 0x0 + + + B_0x1 + ICACHE SRAM content lost in Stop modes + 0x1 + + + + + DC1RAMPDS + DCACHE1 SRAM power-down in Stop modes (Stop 0, 1, 2, 3) + 9 + 1 + read-write + + + B_0x0 + DCACHE1 SRAM content retained in Stop modes + 0x0 + + + B_0x1 + DCACHE1 SRAM content lost in Stop modes + 0x1 + + + + + DMA2DRAMPDS + DMA2D SRAM power-down in Stop modes (Stop 0, 1, 2, 3) + 10 + 1 + read-write + + + B_0x0 + DMA2D SRAM content retained in Stop modes + 0x0 + + + B_0x1 + DMA2D SRAM content lost in Stop modes + 0x1 + + + + + PRAMPDS + FMAC, FDCAN and USB peripherals SRAM power-down in Stop modes (Stop 0, 1, 2, 3) + 11 + 1 + read-write + + + B_0x0 + FMAC, FDCAN and USB peripherals SRAM content retained in Stop modes + 0x0 + + + B_0x1 + FMAC, FDCAN and USB peripherals SRAM content lost in Stop modes + 0x1 + + + + + PKARAMPDS + PKA32 SRAM power-down in Stop modes (Stop 0, 1, 2, 3) + 12 + 1 + read-write + + + B_0x0 + PKA SRAM content retained in Stop modes + 0x0 + + + B_0x1 + PKA SRAM content lost in Stop modes + 0x1 + + + + + SRAM4FWU + SRAM4 fast wakeup from Stop 0, Stop 1 and Stop 2 modes +This bit is used to obtain the best trade-off between low-power consumption and wakeup time. SRAM4 wakeup time increases the wakeup time when exiting Stop 0, 1 and 2 modes, and also increases the LPDMA access time to SRAM4 during Stop modes. + 13 + 1 + read-write + + + B_0x0 + SRAM4 enters low-power mode in Stop 0, 1 and 2 modes (source biasing for lower-power consumption). + 0x0 + + + B_0x1 + SRAM4 remains in normal mode in Stop 0, 1 and 2 modes (higher consumption but no SRAM4 wakeup time). + 0x1 + + + + + FLASHFWU + Flash memory fast wakeup from Stop 0 and Stop 1 modes +This bit is used to obtain the best trade-off between low-power consumption and wakeup time when exiting the Stop 0 or Stop 1 modes. +When this bit is set, the Flash memory remains in normal mode in Stop 0 and Stop 1 modes, which offers a faster startup time with higher consumption. + 14 + 1 + read-write + + + B_0x0 + Flash memory enters low-power mode in Stop 0 and Stop 1 modes (lower-power consumption). + 0x0 + + + B_0x1 + Flash memory remains in normal mode in Stop 0 and Stop 1 modes (faster wakeup time). + 0x1 + + + + + SRAM3PDS1 + SRAM3 page 1 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) + 16 + 1 + read-write + + + B_0x0 + SRAM3 page 1 content retained in Stop modes + 0x0 + + + B_0x1 + SRAM3 page 1 content lost in Stop modes + 0x1 + + + + + SRAM3PDS2 + SRAM3 page 2 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) + 17 + 1 + read-write + + + B_0x0 + SRAM3 page 2 content retained in Stop modes + 0x0 + + + B_0x1 + SRAM3 page 2 content lost in Stop modes + 0x1 + + + + + SRAM3PDS3 + SRAM3 page 3 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) + 18 + 1 + read-write + + + B_0x0 + SRAM3 page 3 content retained in Stop modes + 0x0 + + + B_0x1 + SRAM3 page 3 content lost in Stop modes + 0x1 + + + + + SRAM3PDS4 + SRAM3 page 4 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) + 19 + 1 + read-write + + + B_0x0 + SRAM3 page 4 content retained in Stop modes + 0x0 + + + B_0x1 + SRAM3 page 4 content lost in Stop modes + 0x1 + + + + + SRAM3PDS5 + SRAM3 page 5 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) + 20 + 1 + read-write + + + B_0x0 + SRAM3 page 5 content retained in Stop modes + 0x0 + + + B_0x1 + SRAM3 page 5 content lost in Stop modes + 0x1 + + + + + SRAM3PDS6 + SRAM3 page 6 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) + 21 + 1 + read-write + + + B_0x0 + SRAM3 page 6 content retained in Stop modes + 0x0 + + + B_0x1 + SRAM3 page 6 content lost in Stop modes + 0x1 + + + + + SRAM3PDS7 + SRAM3 page 7 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) + 22 + 1 + read-write + + + B_0x0 + SRAM3 page 7 content retained in Stop modes + 0x0 + + + B_0x1 + SRAM3 page 7 content lost in Stop modes + 0x1 + + + + + SRAM3PDS8 + SRAM3 page 8 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) + 23 + 1 + read-write + + + B_0x0 + SRAM3 page 8 content retained in Stop modes + 0x0 + + + B_0x1 + SRAM3 page 8 content lost in Stop modes + 0x1 + + + + + GPRAMPDS + Graphic peripherals (LTDC, GFXMMU) SRAM power-down in Stop modes (Stop 0, 1, 2, 3) +Note: LTDC SRAM content is always lost in Stop 2 and Stop 3 modes. It can be retained only in Stop 0 and Stop 1 modes. +This bit is only available in STM32U59x/5Ax. It is reserved in STM32U575/585. + 24 + 1 + read-write + + + B_0x0 + Graphic peripherals SRAM content retained in Stop modes + 0x0 + + + B_0x1 + Graphic peripherals SRAM content lost in Stop modes + 0x1 + + + + + DSIRAMPDS + DSI SRAM power-down in Stop modes (Stop 0, 1) +DSI SRAM content is always lost in Stop 2 and Stop 3 modes. +Note: This bit is only available in STM32U59x/5Ax. It is reserved in STM32U575/585. + 25 + 1 + read-write + + + B_0x0 + DSI SRAM content retained in Stop 0 and Stop 1 modes + 0x0 + + + B_0x1 + DSI SRAM content lost in Stop 0 and Stop 1 modes + 0x1 + + + + + SRDRUN + SmartRun domain in Run mode + 31 + 1 + read-write + + + B_0x0 + SmartRun domain AHB3 and APB3 clocks disabled by default in Stop 0,1, 2 modes + 0x0 + + + B_0x1 + SmartRun domain AHB3 and APB3 clocks kept enabled in Stop 0,1, 2 modes + 0x1 + + + + + + + PWR_CR3 + PWR_CR3 + PWR control register 3 + 0x8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + REGSEL + Regulator selection +Note: REGSEL is reserved and must be kept at reset value in packages without SMPS. + 1 + 1 + read-write + + + B_0x0 + LDO selected + 0x0 + + + B_0x1 + SMPS selected + 0x1 + + + + + FSTEN + Fast soft start + 2 + 1 + read-write + + + B_0x0 + LDO/SMPS fast startup disabled (limited inrush current) + 0x0 + + + B_0x1 + LDO/SMPS fast startup enabled + 0x1 + + + + + + + PWR_VOSR + PWR_VOSR + PWR voltage scaling register + 0xc + 0x20 + read-write + 0x00008000 + 0xFFFFFFFF + + + USBBOOSTRDY + USB EPOD booster ready +This bit is set to 1 by hardware when the power booster startup time is reached. The USB clock can be provided only after this bit is set. +Note: This bit is only available in STM32U59x/5Ax. It is reserved in STM32U575/585. + 13 + 1 + read-only + + + B_0x0 + USB power booster not ready + 0x0 + + + B_0x1 + USB power booster ready + 0x1 + + + + + BOOSTRDY + EPOD booster ready +This bit is set to 1 by hardware when the power booster startup time is reached. The system clock frequency can be switched higher than 50 MHz only after this bit is set. + 14 + 1 + read-only + + + B_0x0 + Power booster not ready + 0x0 + + + B_0x1 + Power booster ready + 0x1 + + + + + VOSRDY + Ready bit for VCORE voltage scaling output selection + 15 + 1 + read-only + + + B_0x0 + Not ready, voltage level < VOS selected level + 0x0 + + + B_0x1 + Ready, voltage level ≥ VOS selected level + 0x1 + + + + + VOS + Voltage scaling range selection +This field is protected against non-secure access when SYSCLKSEC = 1 in RCC_SECCFGR. It is protected against unprivileged access when SYSCLKSEC = 1 in RCC_SECCFGR and SPRIV = 1 in PWR_PRIVCFGR, or when SYSCLKSEC = 0 and NSPRIV = 1. + 16 + 2 + read-write + + + B_0x0 + Range 4 (lowest power) + 0x0 + + + B_0x1 + Range 3 + 0x1 + + + B_0x2 + Range 2 + 0x2 + + + B_0x3 + Range 1 (highest frequency). This value cannot be written when VCOREMEN = 1 in TAMP_OR register. + 0x3 + + + + + BOOSTEN + EPOD booster enable +This bit is protected against non-secure access when SYSCLKSEC = 1 in RCC_SECCFGR. It is protected against unprivileged access when SYSCLKSEC = 1 in RCC_SECCFGR and SPRIV = 1 in PWR_PRIVCFGR, or when SYSCLKSEC = 0 and NSPRIV = 1. +This bit must be set in range 1 and range 2 before increasing the system clock frequency above 50 MHz. +This bit is reset when going into Stop modes (0, 1, 2, 3). + 18 + 1 + read-write + + + B_0x0 + Booster disabled + 0x0 + + + B_0x1 + Booster enabled + 0x1 + + + + + USBPWREN + USB power enable +This bit is protected against non-secure access when SYSCLKSEC = 1 in RCC_SECCFGR. It is protected against unprivileged access when SYSCLKSEC = 1 in RCC_SECCFGR and SPRIV = 1 in PWR_PRIVCFGR, or when SYSCLKSEC = 0 and NSPRIV = 1. +Note: This bit is only available in STM32U59x/5Ax. It is reserved in STM32U575/585. + 19 + 1 + read-write + + + B_0x0 + USB power disabled + 0x0 + + + B_0x1 + USB power enabled + 0x1 + + + + + USBBOOSTEN + USB EPOD booster enable +This bit is protected against non-secure access when SYSCLKSEC = 1 in RCC_SECCFGR. It is protected against unprivileged access when SYSCLKSEC = 1 in RCC_SECCFGR and SPRIV = 1 in PWR_PRIVCFGR, or when SYSCLKSEC = 0 and NSPRIV = 1. +This bit must be set in range 1 and range 2 before enabling the USB peripheral. +This bit is reset when going into Stop modes (0, 1, 2, 3). +Note: This bit is only available in STM32U59x/5Ax. It is reserved in STM32U575/585. + 20 + 1 + read-write + + + B_0x0 + USB booster disabled + 0x0 + + + B_0x1 + USB booster enabled + 0x1 + + + + + + + PWR_SVMCR + PWR_SVMCR + PWR supply voltage monitoring control register + 0x10 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PVDE + Power voltage detector enable + 4 + 1 + read-write + + + B_0x0 + Power voltage detector disabled + 0x0 + + + B_0x1 + Power voltage detector enabled + 0x1 + + + + + PVDLS + Power voltage detector level selection +These bits select the voltage threshold detected by the power voltage detector: + 5 + 3 + read-write + + + B_0x0 + VPVD0 around 2.0 V + 0x0 + + + B_0x1 + VPVD1 around 2.2 V + 0x1 + + + B_0x2 + VPVD2 around 2.4 V + 0x2 + + + B_0x3 + VPVD3 around 2.5 V + 0x3 + + + B_0x4 + VPVD4 around 2.6 V + 0x4 + + + B_0x5 + VPVD5 around 2.8 V + 0x5 + + + B_0x6 + VPVD6 around 2.9 V + 0x6 + + + B_0x7 + External input analog voltage PVD_IN (compared internally to VREFINT) + 0x7 + + + + + UVMEN + VDDUSB independent USB voltage monitor enable + 24 + 1 + read-write + + + B_0x0 + VDDUSB voltage monitor disabled + 0x0 + + + B_0x1 + VDDUSB voltage monitor enabled + 0x1 + + + + + IO2VMEN + VDDIO2 independent I/Os voltage monitor enable + 25 + 1 + read-write + + + B_0x0 + VDDIO2 voltage monitor disabled + 0x0 + + + B_0x1 + VDDIO2 voltage monitor enabled + 0x1 + + + + + AVM1EN + VDDA independent analog supply voltage monitor 1 enable (1.6 V threshold) + 26 + 1 + read-write + + + B_0x0 + VDDA voltage monitor 1 disabled + 0x0 + + + B_0x1 + VDDA voltage monitor 1 enabled + 0x1 + + + + + AVM2EN + VDDA independent analog supply voltage monitor 2 enable (1.8 V threshold) + 27 + 1 + read-write + + + B_0x0 + VDDA voltage monitor 2 disabled + 0x0 + + + B_0x1 + VDDA voltage monitor 2 enabled + 0x1 + + + + + USV + VDDUSB independent USB supply valid +This bit is used to validate the VDDUSB supply for electrical and logical isolation purpose. +Setting this bit is mandatory to use the USB OTG peripheral. If VDDUSB is not always present in the application, the VDDUSB voltage monitor can be used to determine whether this supply is ready or not. + 28 + 1 + read-write + + + B_0x0 + VDDUSB not present: logical and electrical isolation is applied to ignore this supply. + 0x0 + + + B_0x1 + VDDUSB valid + 0x1 + + + + + IO2SV + VDDIO2 independent I/Os supply valid +This bit is used to validate the VDDIO2 supply for electrical and logical isolation purpose. +Setting this bit is mandatory to use PG[15:2]. If VDDIO2 is not always present in the application, the VDDIO2 voltage monitor can be used to determine whether this supply is ready or not. + 29 + 1 + read-write + + + B_0x0 + VDDIO2 not present: logical and electrical isolation is applied to ignore this supply. + 0x0 + + + B_0x1 + VDDIO2 valid + 0x1 + + + + + ASV + VDDA independent analog supply valid +This bit is used to validate the VDDA supply for electrical and logical isolation purpose. +Setting this bit is mandatory to use the analog peripherals. If VDDA is not always present in the application, the VDDA voltage monitor can be used to determine whether this supply is ready or not. + 30 + 1 + read-write + + + B_0x0 + VDDA not present: logical and electrical isolation is applied to ignore this supply. + 0x0 + + + B_0x1 + VDDA valid + 0x1 + + + + + + + PWR_WUCR1 + PWR_WUCR1 + PWR wakeup control register 1 + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + WUPEN1 + Wakeup pin WKUP1 enable + 0 + 1 + read-write + + + B_0x0 + Wakeup pin WKUP1 disabled + 0x0 + + + B_0x1 + Wakeup pin WKUP1 enabled + 0x1 + + + + + WUPEN2 + Wakeup pin WKUP2 enable + 1 + 1 + read-write + + + B_0x0 + Wakeup pin WKUP2 disabled + 0x0 + + + B_0x1 + Wakeup pin WKUP2 enabled + 0x1 + + + + + WUPEN3 + Wakeup pin WKUP3 enable + 2 + 1 + read-write + + + B_0x0 + Wakeup pin WKUP3 disabled + 0x0 + + + B_0x1 + Wakeup pin WKUP3 enabled + 0x1 + + + + + WUPEN4 + Wakeup pin WKUP4 enable + 3 + 1 + read-write + + + B_0x0 + Wakeup pin WKUP4 disabled + 0x0 + + + B_0x1 + Wakeup pin WKUP4 enabled + 0x1 + + + + + WUPEN5 + Wakeup pin WKUP5 enable + 4 + 1 + read-write + + + B_0x0 + Wakeup pin WKUP5 disabled + 0x0 + + + B_0x1 + Wakeup pin WKUP5 enabled + 0x1 + + + + + WUPEN6 + Wakeup pin WKUP6 enable + 5 + 1 + read-write + + + B_0x0 + Wakeup pin WKUP6 disabled + 0x0 + + + B_0x1 + Wakeup pin WKUP6 enabled + 0x1 + + + + + WUPEN7 + Wakeup pin WKUP7 enable + 6 + 1 + read-write + + + B_0x0 + Wakeup pin WKUP7 disabled + 0x0 + + + B_0x1 + Wakeup pin WKUP7 enabled + 0x1 + + + + + WUPEN8 + Wakeup pin WKUP8 enable + 7 + 1 + read-write + + + B_0x0 + Wakeup pin WKUP8 disabled + 0x0 + + + B_0x1 + Wakeup pin WKUP8 enabled + 0x1 + + + + + + + PWR_WUCR2 + PWR_WUCR2 + PWR wakeup control register 2 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + WUPP1 + Wakeup pin WKUP1 polarity. +This bit must be configured when WUPEN1 = 0. + 0 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUPP2 + Wakeup pin WKUP2 polarity +This bit must be configured when WUPEN2 = 0. + 1 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUPP3 + Wakeup pin WKUP3 polarity +This bit must be configured when WUPEN3 = 0. + 2 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUPP4 + Wakeup pin WKUP4 polarity +This bit must be configured when WUPEN4 = 0. + 3 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUPP5 + Wakeup pin WKUP5 polarity +This bit must be configured when WUPEN5 = 0. + 4 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUPP6 + Wakeup pin WKUP6 polarity +This bit must be configured when WUPEN6 = 0. + 5 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUPP7 + Wakeup pin WKUP7 polarity +This bit must be configured when WUPEN7 = 0. + 6 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUPP8 + Wakeup pin WKUP8 polarity +This bit must be configured when WUPEN8 = 0. + 7 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + + + PWR_WUCR3 + PWR_WUCR3 + PWR wakeup control register 3 + 0x1c + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + WUSEL1 + Wakeup pin WKUP1 selection +This field must be configured when WUPEN1 = 0. + 0 + 2 + read-write + + + B_0x0 + WKUP0_0 + 0x0 + + + B_0x1 + WKUP0_1 + 0x1 + + + B_0x2 + WKUP0_2 + 0x2 + + + B_0x3 + WKUP0_3 + 0x3 + + + + + WUSEL2 + Wakeup pin WKUP2 selection +This field must be configured when WUPEN2 = 0. + 2 + 2 + read-write + + + B_0x0 + WKUP2_0 + 0x0 + + + B_0x1 + WKUP2_1 + 0x1 + + + B_0x2 + WKUP2_2 + 0x2 + + + B_0x3 + WKUP2_3 + 0x3 + + + + + WUSEL3 + Wakeup pin WKUP3 selection +This field must be configured when WUPEN3 = 0. + 4 + 2 + read-write + + + B_0x0 + WKUP3_0 + 0x0 + + + B_0x1 + WKUP3_1 + 0x1 + + + B_0x2 + WKUP3_2 + 0x2 + + + B_0x3 + WKUP3_3 + 0x3 + + + + + WUSEL4 + Wakeup pin WKUP4 selection +This field must be configured when WUPEN4 = 0. + 6 + 2 + read-write + + + B_0x0 + WKUP4_0 + 0x0 + + + B_0x1 + WKUP4_1 + 0x1 + + + B_0x2 + WKUP4_2 + 0x2 + + + B_0x3 + WKUP4_3 + 0x3 + + + + + WUSEL5 + Wakeup pin WKUP5 selection +This field must be configured when WUPEN5 = 0. + 8 + 2 + read-write + + + B_0x0 + WKUP5_0 + 0x0 + + + B_0x1 + WKUP5_1 + 0x1 + + + B_0x2 + WKUP5_2 + 0x2 + + + B_0x3 + WKUP5_3 + 0x3 + + + + + WUSEL6 + Wakeup pin WKUP6 selection +This field must be configured when WUPEN6 = 0. + 10 + 2 + read-write + + + B_0x0 + WKUP6_0 + 0x0 + + + B_0x1 + WKUP6_1 + 0x1 + + + B_0x2 + WKUP6_2 + 0x2 + + + B_0x3 + WKUP6_3 + 0x3 + + + + + WUSEL7 + Wakeup pin WKUP7 selection +This field must be configured when WUPEN7 = 0. + 12 + 2 + read-write + + + B_0x0 + WKUP7_0 + 0x0 + + + B_0x1 + WKUP7_1 + 0x1 + + + B_0x2 + WKUP7_2 + 0x2 + + + B_0x3 + WKUP7_3 + 0x3 + + + + + WUSEL8 + Wakeup pin WKUP8 selection +This field must be configured when WUPEN8 = 0. + 14 + 2 + read-write + + + B_0x0 + WKUP8_0 + 0x0 + + + B_0x1 + WKUP8_1 + 0x1 + + + B_0x2 + WKUP8_2 + 0x2 + + + B_0x3 + WKUP8_3 + 0x3 + + + + + + + PWR_BDCR1 + PWR_BDCR1 + PWR Backup domain control register 1 + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BREN + Backup RAM retention in Standby and VBAT modes +When this bit is set, the backup RAM content is kept in Standby and VBAT modes. +If BREN is reset, the backup RAM can still be used in Run, Sleep and Stop modes. However, its content is lost in Standby, Shutdown and VBAT modes. This bit can be written only when the regulator is LDO, which must be configured before switching to SMPS. +Note: Backup RAM cannot be preserved in Shutdown mode. + 0 + 1 + read-write + + + B_0x0 + Backup RAM content lost in Standby and VBAT modes + 0x0 + + + B_0x1 + Backup RAM content preserved in Standby and VBAT modes + 0x1 + + + + + MONEN + Backup domain voltage and temperature monitoring enable + 4 + 1 + read-write + + + B_0x0 + Backup domain voltage and temperature monitoring disabled + 0x0 + + + B_0x1 + Backup domain voltage and temperature monitoring enabled + 0x1 + + + + + + + PWR_BDCR2 + PWR_BDCR2 + PWR Backup domain control register 2 + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + VBE + VBAT charging enable + 0 + 1 + read-write + + + B_0x0 + VBAT battery charging disabled + 0x0 + + + B_0x1 + VBAT battery charging enabled + 0x1 + + + + + VBRS + VBAT charging resistor selection + 1 + 1 + read-write + + + B_0x0 + Charge VBAT through a 5 kΩ resistor + 0x0 + + + B_0x1 + Charge VBAT through a 1.5 kΩ resistor + 0x1 + + + + + + + PWR_DBPR + PWR_DBPR + PWR disable Backup domain register + 0x28 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DBP + Disable Backup domain write protection +In reset state, all registers and SRAM in Backup domain are protected against parasitic write access. This bit must be set to enable the write access to these registers. + 0 + 1 + read-write + + + B_0x0 + Write access to Backup domain disabled + 0x0 + + + B_0x1 + Write access to Backup domain enabled + 0x1 + + + + + + + PWR_UCPDR + PWR_UCPDR + PWR USB Type-C™ and Power Delivery register + 0x2c + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UCPD_DBDIS + UCPD dead battery disable +After exiting reset, the USB Type-C “dead battery” behavior is enabled, which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it in all cases, either to stop this pull-down or to handover control to the UCPD (the UCPD must be initialized before doing the disable). + 0 + 1 + read-write + + + B_0x0 + UCPD dead battery pull-down behavior enabled on UCPDx_CC1 and UCPDx_CC2 pins + 0x0 + + + B_0x1 + UCPD dead battery pull-down behavior disabled on UCPDx_CC1 and UCPDx_CC2 pins + 0x1 + + + + + UCPD_STBY + UCPD Standby mode +When set, this bit is used to memorize the UCPD configuration in Standby mode. +This bit must be written to 1 just before entering Standby mode when using UCPD. +It must be written to 0 after exiting the Standby mode and before writing any UCPD registers. + 1 + 1 + read-write + + + + + PWR_SECCFGR + PWR_SECCFGR + PWR security configuration register + 0x30 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + WUP1SEC + WUP1 secure protection + 0 + 1 + read-write + + + B_0x0 + Bits related to the WKUP1 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written with secure or non-secure access. + 0x0 + + + B_0x1 + Bits related to the WKUP1 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written only with secure access. + 0x1 + + + + + WUP2SEC + WUP2 secure protection + 1 + 1 + read-write + + + B_0x0 + Bits related to the WKUP2 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written with secure or non-secure access. + 0x0 + + + B_0x1 + Bits related to the WKUP2 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written only with secure access. + 0x1 + + + + + WUP3SEC + WUP3 secure protection + 2 + 1 + read-write + + + B_0x0 + Bits related to the WKUP3 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written with secure or non-secure access. + 0x0 + + + B_0x1 + Bits related to the WKUP3 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written only with secure access. + 0x1 + + + + + WUP4SEC + WUP4 secure protection + 3 + 1 + read-write + + + B_0x0 + Bits related to the WKUP4 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written with secure or non-secure access. + 0x0 + + + B_0x1 + Bits related to the WKUP4 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written only with secure access. + 0x1 + + + + + WUP5SEC + WUP5 secure protection + 4 + 1 + read-write + + + B_0x0 + Bits related to the WKUP5 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written with secure or non-secure access. + 0x0 + + + B_0x1 + Bits related to the WKUP5 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written only with secure access. + 0x1 + + + + + WUP6SEC + WUP6 secure protection + 5 + 1 + read-write + + + B_0x0 + Bits related to the WKUP6 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written with secure or non-secure access. + 0x0 + + + B_0x1 + Bits related to the WKUP6 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written only with secure access. + 0x1 + + + + + WUP7SEC + WUP7 secure protection + 6 + 1 + read-write + + + B_0x0 + Bits related to the WKUP7 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written with secure or non-secure access. + 0x0 + + + B_0x1 + Bits related to the WKUP7 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written only with secure access. + 0x1 + + + + + WUP8SEC + WUP8 secure protection + 7 + 1 + read-write + + + B_0x0 + Bits related to the WKUP8 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written with secure or non-secure access. + 0x0 + + + B_0x1 + Bits related to the WKUP8 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written only with secure access. + 0x1 + + + + + LPMSEC + Low-power modes secure protection + 12 + 1 + read-write + + + B_0x0 + PWR_CR1, PWR_CR2 and CSSF in the PWR_SR can be read and written with secure or non-secure access. + 0x0 + + + B_0x1 + PWR_CR1, PWR_CR2, and CSSF in the PWR_SR can be read and written only with secure access. + 0x1 + + + + + VDMSEC + Voltage detection and monitoring secure protection + 13 + 1 + read-write + + + B_0x0 + PWR_SVMCR and PWR_CR3 can be read and written with secure or non-secure access. + 0x0 + + + B_0x1 + PWR_SVMCR and PWR_CR3 can be read and written only with secure access. + 0x1 + + + + + VBSEC + Backup domain secure protection + 14 + 1 + read-write + + + B_0x0 + PWR_BDCR1, PWR_BDCR2 and PWR_DBPR can be read and written with secure or non-secure access. + 0x0 + + + B_0x1 + PWR_BDCR1, PWR_BDCR2 and PWR_DBPR can be read and written only with secure access. + 0x1 + + + + + APCSEC + Pull-up/pull-down secure protection + 15 + 1 + read-write + + + B_0x0 + PWR_APCR can be read and written with secure or non-secure access. + 0x0 + + + B_0x1 + PWR_APCR can be read and written only with secure access. + 0x1 + + + + + + + PWR_PRIVCFGR + PWR_PRIVCFGR + PWR privilege control register + 0x34 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SPRIV + PWR secure functions privilege configuration +This bit is set and reset by software. It can be written only by a secure privileged access. + 0 + 1 + read-write + + + B_0x0 + Read and write to PWR secure functions can be done by privileged or unprivileged access. + 0x0 + + + B_0x1 + Read and write to PWR secure functions can be done by privileged access only. + 0x1 + + + + + NSPRIV + PWR non-secure functions privilege configuration +This bit is set and reset by software. It can be written only by privileged access, secure or non-secure. + 1 + 1 + read-write + + + B_0x0 + Read and write to PWR non-secure functions can be done by privileged or unprivileged access. + 0x0 + + + B_0x1 + Read and write to PWR non-secure functions can be done by privileged access only. + 0x1 + + + + + + + PWR_SR + PWR_SR + PWR status register + 0x38 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CSSF + Clear Stop and Standby flags +This bit is protected against non-secure access when LPMSEC = 1 in PWR_SECCFGR. +This bit is protected against unprivileged access when LPMSEC = 1 and SPRIV = 1 in PWR_PRIVCFGR, or when LPMSEC = 0 and NSPRIV = 1. +Writing 1 to this bit clears the STOPF and SBF flags. + 0 + 1 + write-only + + + STOPF + Stop flag +This bit is set by hardware when the device enters a Stop mode, and is cleared by software by writing 1 to the CSSF bit. + 1 + 1 + read-only + + + B_0x0 + The device did not enter any Stop mode. + 0x0 + + + B_0x1 + The device entered a Stop mode. + 0x1 + + + + + SBF + Standby flag +This bit is set by hardware when the device enters the Standby mode, and is cleared by writing 1 to the CSSF bit, or by a power-on reset. It is not cleared by the system reset. + 2 + 1 + read-only + + + B_0x0 + The device did not enter Standby mode. + 0x0 + + + B_0x1 + The device entered Standby mode. + 0x1 + + + + + + + PWR_SVMSR + PWR_SVMSR + PWR supply voltage monitoring status register + 0x3c + 0x20 + read-only + 0x00008000 + 0xFFFFFFFF + + + REGS + Regulator selection + 1 + 1 + read-only + + + B_0x0 + LDO selected + 0x0 + + + B_0x1 + SMPS selected + 0x1 + + + + + PVDO + VDD voltage detector output + 4 + 1 + read-only + + + B_0x0 + VDD is equal or above the PVD threshold selected by PVDLS[2:0]. + 0x0 + + + B_0x1 + VDD is below the PVD threshold selected by PVDLS[2:0]. + 0x1 + + + + + ACTVOSRDY + Voltage level ready for currently used VOS + 15 + 1 + read-only + + + B_0x0 + VCORE is above or below the current voltage scaling provided by ACTVOS[1:0]. + 0x0 + + + B_0x1 + VCORE is equal to the current voltage scaling provided by ACTVOS[1:0] + 0x1 + + + + + ACTVOS + VOS currently applied to VCORE +This field provides the last VOS value. + 16 + 2 + read-only + + + B_0x0 + Range 4 (lowest power) + 0x0 + + + B_0x1 + Range 3 + 0x1 + + + B_0x2 + Range 2 + 0x2 + + + B_0x3 + Range 1 (highest frequency) + 0x3 + + + + + VDDUSBRDY + VDDUSB ready + 24 + 1 + read-only + + + B_0x0 + VDDUSB is below the threshold of the VDDUSB voltage monitor. + 0x0 + + + B_0x1 + VDDUSB is equal or above the threshold of the VDDUSB voltage monitor. + 0x1 + + + + + VDDIO2RDY + VDDIO2 ready + 25 + 1 + read-only + + + B_0x0 + VDDIO2 is below the threshold of the VDDIO2 voltage monitor. + 0x0 + + + B_0x1 + VDDIO2 is equal or above the threshold of the VDDIO2 voltage monitor. + 0x1 + + + + + VDDA1RDY + VDDA ready versus 1.6V voltage monitor + 26 + 1 + read-only + + + B_0x0 + VDDA is below the threshold of the VDDA voltage monitor 1 (around 1.6 V). + 0x0 + + + B_0x1 + VDDA is equal or above the threshold of the VDDA voltage monitor 1 (around 1.6 V). + 0x1 + + + + + VDDA2RDY + VDDA ready versus 1.8 V voltage monitor + 27 + 1 + read-only + + + B_0x0 + VDDA is below the threshold of the VDDA voltage monitor 2 (around 1.8 V). + 0x0 + + + B_0x1 + VDDA is equal or above the threshold of the VDDA voltage monitor 2 (around 1.8 V). + 0x1 + + + + + + + PWR_BDSR + PWR_BDSR + PWR Backup domain status register + 0x40 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + VBATH + Backup domain voltage level monitoring versus high threshold + 1 + 1 + read-only + + + B_0x0 + Backup domain voltage level < high threshold + 0x0 + + + B_0x1 + Backup domain voltage level ≥ high threshold + 0x1 + + + + + TEMPL + Temperature level monitoring versus low threshold + 2 + 1 + read-only + + + B_0x0 + Temperature > low threshold + 0x0 + + + B_0x1 + Temperature ≤ low threshold + 0x1 + + + + + TEMPH + Temperature level monitoring versus high threshold + 3 + 1 + read-only + + + B_0x0 + Temperature < high threshold + 0x0 + + + B_0x1 + Temperature ≥ high threshold + 0x1 + + + + + + + PWR_WUSR + PWR_WUSR + PWR wakeup status register + 0x44 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + WUF1 + Wakeup flag 1 +This bit is set when a wakeup event is detected on WKUP1 pin. This bit is cleared by writing 1 in the CWUF1 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN1 = 0. + 0 + 1 + read-only + + + WUF2 + Wakeup flag 2 +This bit is set when a wakeup event is detected on WKUP2 pin. This bit is cleared by writing 1 in the CWUF2 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN2 = 0. + 1 + 1 + read-only + + + WUF3 + Wakeup flag 3 +This bit is set when a wakeup event is detected on WKUP3 pin. This bit is cleared by writing 1 in the CWUF3 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN3 = 0. + 2 + 1 + read-only + + + WUF4 + Wakeup flag 4 +This bit is set when a wakeup event is detected on WKUP4 pin. This bit is cleared by writing 1 in the CWUF4 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN4 = 0. + 3 + 1 + read-only + + + WUF5 + Wakeup flag 5 +This bit is set when a wakeup event is detected on WKUP5 pin. This bit is cleared by writing 1 in the CWUF5 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN5 = 0. + 4 + 1 + read-only + + + WUF6 + Wakeup flag 6 +This bit is set when a wakeup event is detected on WKUP6 pin. This bit is cleared by writing 1 in the CWUF6 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN6 = 0. +If WUSEL = 11, this bit is cleared by hardware when all internal wakeup source are cleared. + 5 + 1 + read-only + + + WUF7 + Wakeup flag 7 +This bit is set when a wakeup event is detected on WKUP7 pin. This bit is cleared by writing 1 in the CWUF7 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN7 = 0. +If WUSEL = 11, this bit is cleared by hardware when all internal wakeup source are cleared. + 6 + 1 + read-only + + + WUF8 + Wakeup flag 8 +This bit is set when a wakeup event is detected on WKUP8 pin. This bit is cleared by writing 1 in the CWUF8 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN8 = 0. +If WUSEL = 11, this bit is cleared by hardware when all internal wakeup source are cleared. + 7 + 1 + read-only + + + + + PWR_WUSCR + PWR_WUSCR + PWR wakeup status clear register + 0x48 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CWUF1 + Wakeup flag 1 +Writing 1 to this bit clears the WUF1 flag in PWR_WUSR. + 0 + 1 + write-only + + + CWUF2 + Wakeup flag 2 +Writing 1 to this bit clears the WUF2 flag in PWR_WUSR. + 1 + 1 + write-only + + + CWUF3 + Wakeup flag 3 +Writing 1 to this bit clears the WUF3 flag in PWR_WUSR. + 2 + 1 + write-only + + + CWUF4 + Wakeup flag 4 +Writing 1 to this bit clears the WUF4 flag in PWR_WUSR. + 3 + 1 + write-only + + + CWUF5 + Wakeup flag 5 +Writing 1 to this bit clears the WUF5 flag in PWR_WUSR. + 4 + 1 + write-only + + + CWUF6 + Wakeup flag 6 +Writing 1 to this bit clears the WUF6 flag in PWR_WUSR. + 5 + 1 + write-only + + + CWUF7 + Wakeup flag 7 +Writing 1 to this bit clears the WUF7 flag in PWR_WUSR. + 6 + 1 + write-only + + + CWUF8 + Wakeup flag 8 +Writing 1 to this bit clears the WUF8 flag in PWR_WUSR. + 7 + 1 + write-only + + + + + PWR_APCR + PWR_APCR + PWR apply pull configuration register + 0x4c + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + APC + Apply pull-up and pull-down configuration +When this bit is set, the I/O pull-up and pull-down configurations defined in PWR_PUCRx and PWR_PDCRx are applied. When this bit is cleared, PWR_PUCRx and PWR_PDCRx are not applied to the I/Os. + 0 + 1 + read-write + + + + + PWR_PUCRA + PWR_PUCRA + PWR port A pull-up control register + 0x50 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PU0 + 0 + 1 + read-write + + + PU1 + 1 + 1 + read-write + + + PU2 + 2 + 1 + read-write + + + PU3 + 3 + 1 + read-write + + + PU4 + 4 + 1 + read-write + + + PU5 + 5 + 1 + read-write + + + PU6 + 6 + 1 + read-write + + + PU7 + 7 + 1 + read-write + + + PU8 + 8 + 1 + read-write + + + PU9 + 9 + 1 + read-write + + + PU10 + 10 + 1 + read-write + + + PU11 + 11 + 1 + read-write + + + PU12 + 12 + 1 + read-write + + + PU13 + 13 + 1 + read-write + + + PU15 + Port A pull-up bit 15 +When set, this bit activates the pull-up on PA15 when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding PD15 bit is also set. + 15 + 1 + read-write + + + + + PWR_PDCRA + PWR_PDCRA + PWR port A pull-down control register + 0x54 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PD0 + 0 + 1 + read-write + + + PD1 + 1 + 1 + read-write + + + PD2 + 2 + 1 + read-write + + + PD3 + 3 + 1 + read-write + + + PD4 + 4 + 1 + read-write + + + PD5 + 5 + 1 + read-write + + + PD6 + 6 + 1 + read-write + + + PD7 + 7 + 1 + read-write + + + PD8 + 8 + 1 + read-write + + + PD9 + 9 + 1 + read-write + + + PD10 + 10 + 1 + read-write + + + PD11 + 11 + 1 + read-write + + + PD12 + 12 + 1 + read-write + + + PD14 + Port A pull-down bit 14 +When set, this bit activates the pull-down on PA14 when the APC bit is set in PWR_APCR. + 14 + 1 + read-write + + + + + PWR_PUCRB + PWR_PUCRB + PWR port B pull-up control register + 0x58 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PU0 + 0 + 1 + read-write + + + PU1 + 1 + 1 + read-write + + + PU2 + 2 + 1 + read-write + + + PU3 + 3 + 1 + read-write + + + PU4 + 4 + 1 + read-write + + + PU5 + 5 + 1 + read-write + + + PU6 + 6 + 1 + read-write + + + PU7 + 7 + 1 + read-write + + + PU8 + 8 + 1 + read-write + + + PU9 + 9 + 1 + read-write + + + PU10 + 10 + 1 + read-write + + + PU11 + 11 + 1 + read-write + + + PU12 + 12 + 1 + read-write + + + PU13 + 13 + 1 + read-write + + + PU14 + 14 + 1 + read-write + + + PU15 + 15 + 1 + read-write + + + + + PWR_PDCRB + PWR_PDCRB + PWR port B pull-down control register + 0x5c + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PD0 + 0 + 1 + read-write + + + PD1 + 1 + 1 + read-write + + + PD2 + 2 + 1 + read-write + + + PD3 + 3 + 1 + read-write + + + PD5 + 5 + 1 + read-write + + + PD6 + 6 + 1 + read-write + + + PD7 + 7 + 1 + read-write + + + PD8 + 8 + 1 + read-write + + + PD9 + 9 + 1 + read-write + + + PD10 + 10 + 1 + read-write + + + PD11 + 11 + 1 + read-write + + + PD12 + 12 + 1 + read-write + + + PD13 + 13 + 1 + read-write + + + PD14 + 14 + 1 + read-write + + + PD15 + 15 + 1 + read-write + + + + + PWR_PUCRC + PWR_PUCRC + Power port C pull up control register + 0x60 + 0x20 + read-write + 0x00000000 + + + PU0 + PU0 + 0 + 1 + + + PU1 + PU1 + 1 + 1 + + + PU2 + PU2 + 2 + 1 + + + PU3 + PU3 + 3 + 1 + + + PU4 + PU4 + 4 + 1 + + + PU5 + PU5 + 5 + 1 + + + PU6 + PU6 + 6 + 1 + + + PU7 + PU7 + 7 + 1 + + + PU8 + PU8 + 8 + 1 + + + PU9 + PU9 + 9 + 1 + + + PU10 + PU10 + 10 + 1 + + + PU11 + PU11 + 11 + 1 + + + PU12 + PU12 + 12 + 1 + + + PU13 + PU13 + 13 + 1 + + + PU14 + PU14 + 14 + 1 + + + PU15 + PU15 + 15 + 1 + + + + + PWR_PDCRC + PWR_PDCRC + PWR port C pull-down control register + 0x64 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PD0 + 0 + 1 + read-write + + + PD1 + 1 + 1 + read-write + + + PD2 + 2 + 1 + read-write + + + PD3 + 3 + 1 + read-write + + + PD4 + 4 + 1 + read-write + + + PD5 + 5 + 1 + read-write + + + PD6 + 6 + 1 + read-write + + + PD7 + 7 + 1 + read-write + + + PD8 + 8 + 1 + read-write + + + PD9 + 9 + 1 + read-write + + + PD10 + 10 + 1 + read-write + + + PD11 + 11 + 1 + read-write + + + PD12 + 12 + 1 + read-write + + + PD13 + 13 + 1 + read-write + + + PD14 + 14 + 1 + read-write + + + PD15 + 15 + 1 + read-write + + + + + PWR_PUCRD + PWR_PUCRD + PWR port D pull-up control register + 0x68 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PU0 + 0 + 1 + read-write + + + PU1 + 1 + 1 + read-write + + + PU2 + 2 + 1 + read-write + + + PU3 + 3 + 1 + read-write + + + PU4 + 4 + 1 + read-write + + + PU5 + 5 + 1 + read-write + + + PU6 + 6 + 1 + read-write + + + PU7 + 7 + 1 + read-write + + + PU8 + 8 + 1 + read-write + + + PU9 + 9 + 1 + read-write + + + PU10 + 10 + 1 + read-write + + + PU11 + 11 + 1 + read-write + + + PU12 + 12 + 1 + read-write + + + PU13 + 13 + 1 + read-write + + + PU14 + 14 + 1 + read-write + + + PU15 + 15 + 1 + read-write + + + + + PWR_PDCRD + PWR_PDCRD + PWR port D pull-down control register + 0x6c + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PD0 + 0 + 1 + read-write + + + PD1 + 1 + 1 + read-write + + + PD2 + 2 + 1 + read-write + + + PD3 + 3 + 1 + read-write + + + PD4 + 4 + 1 + read-write + + + PD5 + 5 + 1 + read-write + + + PD6 + 6 + 1 + read-write + + + PD7 + 7 + 1 + read-write + + + PD8 + 8 + 1 + read-write + + + PD9 + 9 + 1 + read-write + + + PD10 + 10 + 1 + read-write + + + PD11 + 11 + 1 + read-write + + + PD12 + 12 + 1 + read-write + + + PD13 + 13 + 1 + read-write + + + PD14 + 14 + 1 + read-write + + + PD15 + 15 + 1 + read-write + + + + + PWR_PUCRE + PWR_PUCRE + PWR port E pull-up control register + 0x70 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PU0 + 0 + 1 + read-write + + + PU1 + 1 + 1 + read-write + + + PU2 + 2 + 1 + read-write + + + PU3 + 3 + 1 + read-write + + + PU4 + 4 + 1 + read-write + + + PU5 + 5 + 1 + read-write + + + PU6 + 6 + 1 + read-write + + + PU7 + 7 + 1 + read-write + + + PU8 + 8 + 1 + read-write + + + PU9 + 9 + 1 + read-write + + + PU10 + 10 + 1 + read-write + + + PU11 + 11 + 1 + read-write + + + PU12 + 12 + 1 + read-write + + + PU13 + 13 + 1 + read-write + + + PU14 + 14 + 1 + read-write + + + PU15 + 15 + 1 + read-write + + + + + PWR_PDCRE + PWR_PDCRE + PWR port E pull-down control register + 0x74 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PD0 + 0 + 1 + read-write + + + PD1 + 1 + 1 + read-write + + + PD2 + 2 + 1 + read-write + + + PD3 + 3 + 1 + read-write + + + PD4 + 4 + 1 + read-write + + + PD5 + 5 + 1 + read-write + + + PD6 + 6 + 1 + read-write + + + PD7 + 7 + 1 + read-write + + + PD8 + 8 + 1 + read-write + + + PD9 + 9 + 1 + read-write + + + PD10 + 10 + 1 + read-write + + + PD11 + 11 + 1 + read-write + + + PD12 + 12 + 1 + read-write + + + PD13 + 13 + 1 + read-write + + + PD14 + 14 + 1 + read-write + + + PD15 + 15 + 1 + read-write + + + + + PWR_PUCRF + PWR_PUCRF + PWR port F pull-up control register + 0x78 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PU0 + 0 + 1 + read-write + + + PU1 + 1 + 1 + read-write + + + PU2 + 2 + 1 + read-write + + + PU3 + 3 + 1 + read-write + + + PU4 + 4 + 1 + read-write + + + PU5 + 5 + 1 + read-write + + + PU6 + 6 + 1 + read-write + + + PU7 + 7 + 1 + read-write + + + PU8 + 8 + 1 + read-write + + + PU9 + 9 + 1 + read-write + + + PU10 + 10 + 1 + read-write + + + PU11 + 11 + 1 + read-write + + + PU12 + 12 + 1 + read-write + + + PU13 + 13 + 1 + read-write + + + PU14 + 14 + 1 + read-write + + + PU15 + 15 + 1 + read-write + + + + + PWR_PDCRF + PWR_PDCRF + PWR port F pull-down control register + 0x7c + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PD0 + 0 + 1 + read-write + + + PD1 + 1 + 1 + read-write + + + PD2 + 2 + 1 + read-write + + + PD3 + 3 + 1 + read-write + + + PD4 + 4 + 1 + read-write + + + PD5 + 5 + 1 + read-write + + + PD6 + 6 + 1 + read-write + + + PD7 + 7 + 1 + read-write + + + PD8 + 8 + 1 + read-write + + + PD9 + 9 + 1 + read-write + + + PD10 + 10 + 1 + read-write + + + PD11 + 11 + 1 + read-write + + + PD12 + 12 + 1 + read-write + + + PD13 + 13 + 1 + read-write + + + PD14 + 14 + 1 + read-write + + + PD15 + 15 + 1 + read-write + + + + + PWR_PUCRG + PWR_PUCRG + PWR port G pull-up control register + 0x80 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PU0 + 0 + 1 + read-write + + + PU1 + 1 + 1 + read-write + + + PU2 + 2 + 1 + read-write + + + PU3 + 3 + 1 + read-write + + + PU4 + 4 + 1 + read-write + + + PU5 + 5 + 1 + read-write + + + PU6 + 6 + 1 + read-write + + + PU7 + 7 + 1 + read-write + + + PU8 + 8 + 1 + read-write + + + PU9 + 9 + 1 + read-write + + + PU10 + 10 + 1 + read-write + + + PU11 + 11 + 1 + read-write + + + PU12 + 12 + 1 + read-write + + + PU13 + 13 + 1 + read-write + + + PU14 + 14 + 1 + read-write + + + PU15 + 15 + 1 + read-write + + + + + PWR_PDCRG + PWR_PDCRG + PWR port G pull-down control register + 0x84 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PD0 + 0 + 1 + read-write + + + PD1 + 1 + 1 + read-write + + + PD2 + 2 + 1 + read-write + + + PD3 + 3 + 1 + read-write + + + PD4 + 4 + 1 + read-write + + + PD5 + 5 + 1 + read-write + + + PD6 + 6 + 1 + read-write + + + PD7 + 7 + 1 + read-write + + + PD8 + 8 + 1 + read-write + + + PD9 + 9 + 1 + read-write + + + PD10 + 10 + 1 + read-write + + + PD11 + 11 + 1 + read-write + + + PD12 + 12 + 1 + read-write + + + PD13 + 13 + 1 + read-write + + + PD14 + 14 + 1 + read-write + + + PD15 + 15 + 1 + read-write + + + + + PWR_PUCRH + PWR_PUCRH + PWR port H pull-up control register + 0x88 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PU0 + 0 + 1 + read-write + + + PU1 + 1 + 1 + read-write + + + PU2 + 2 + 1 + read-write + + + PU3 + 3 + 1 + read-write + + + PU4 + 4 + 1 + read-write + + + PU5 + 5 + 1 + read-write + + + PU6 + 6 + 1 + read-write + + + PU7 + 7 + 1 + read-write + + + PU8 + 8 + 1 + read-write + + + PU9 + 9 + 1 + read-write + + + PU10 + 10 + 1 + read-write + + + PU11 + 11 + 1 + read-write + + + PU12 + 12 + 1 + read-write + + + PU13 + 13 + 1 + read-write + + + PU14 + 14 + 1 + read-write + + + PU15 + 15 + 1 + read-write + + + + + PWR_PDCRH + PWR_PDCRH + PWR port H pull-down control register + 0x8c + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PD0 + 0 + 1 + read-write + + + PD1 + 1 + 1 + read-write + + + PD2 + 2 + 1 + read-write + + + PD3 + 3 + 1 + read-write + + + PD4 + 4 + 1 + read-write + + + PD5 + 5 + 1 + read-write + + + PD6 + 6 + 1 + read-write + + + PD7 + 7 + 1 + read-write + + + PD8 + 8 + 1 + read-write + + + PD9 + 9 + 1 + read-write + + + PD10 + 10 + 1 + read-write + + + PD11 + 11 + 1 + read-write + + + PD12 + 12 + 1 + read-write + + + PD13 + 13 + 1 + read-write + + + PD14 + 14 + 1 + read-write + + + PD15 + 15 + 1 + read-write + + + + + PWR_PUCRI + PWR_PUCRI + PWR port I pull-up control register + 0x90 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PU0 + 0 + 1 + read-write + + + PU1 + 1 + 1 + read-write + + + PU2 + 2 + 1 + read-write + + + PU3 + 3 + 1 + read-write + + + PU4 + 4 + 1 + read-write + + + PU5 + 5 + 1 + read-write + + + PU6 + 6 + 1 + read-write + + + PU7 + 7 + 1 + read-write + + + PU8 + 8 + 1 + read-write + + + PU9 + 9 + 1 + read-write + + + PU10 + 10 + 1 + read-write + + + PU11 + 11 + 1 + read-write + + + PU12 + 12 + 1 + read-write + + + PU13 + 13 + 1 + read-write + + + PU14 + 14 + 1 + read-write + + + PU15 + 15 + 1 + read-write + + + + + PWR_PDCRI + PWR_PDCRI + PWR port I pull-down control register + 0x94 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PD0 + 0 + 1 + read-write + + + PD1 + 1 + 1 + read-write + + + PD2 + 2 + 1 + read-write + + + PD3 + 3 + 1 + read-write + + + PD4 + 4 + 1 + read-write + + + PD5 + 5 + 1 + read-write + + + PD6 + 6 + 1 + read-write + + + PD7 + 7 + 1 + read-write + + + PD8 + 8 + 1 + read-write + + + PD9 + 9 + 1 + read-write + + + PD10 + 10 + 1 + read-write + + + PD11 + 11 + 1 + read-write + + + PD12 + 12 + 1 + read-write + + + PD13 + 13 + 1 + read-write + + + PD14 + 14 + 1 + read-write + + + PD15 + 15 + 1 + read-write + + + + + PWR_PUCRJ + PWR_PUCRJ + PWR port J pull-up control register + 0x98 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PU0 + 0 + 1 + read-write + + + PU1 + 1 + 1 + read-write + + + PU2 + 2 + 1 + read-write + + + PU3 + 3 + 1 + read-write + + + PU4 + 4 + 1 + read-write + + + PU5 + 5 + 1 + read-write + + + PU6 + 6 + 1 + read-write + + + PU7 + 7 + 1 + read-write + + + PU8 + 8 + 1 + read-write + + + PU9 + 9 + 1 + read-write + + + PU10 + 10 + 1 + read-write + + + PU11 + 11 + 1 + read-write + + + + + PWR_PDCRJ + PWR_PDCRJ + PWR port J pull-down control register + 0x9c + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PD0 + 0 + 1 + read-write + + + PD1 + 1 + 1 + read-write + + + PD2 + 2 + 1 + read-write + + + PD3 + 3 + 1 + read-write + + + PD4 + 4 + 1 + read-write + + + PD5 + 5 + 1 + read-write + + + PD6 + 6 + 1 + read-write + + + PD7 + 7 + 1 + read-write + + + PD8 + 8 + 1 + read-write + + + PD9 + 9 + 1 + read-write + + + PD10 + 10 + 1 + read-write + + + PD11 + 11 + 1 + read-write + + + + + PWR_CR4 + PWR_CR4 + PWR control register 4 + 0xa8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SRAM1PDS4 + 0 + 1 + read-write + + + SRAM1PDS5 + 1 + 1 + read-write + + + SRAM1PDS6 + 2 + 1 + read-write + + + SRAM1PDS7 + 3 + 1 + read-write + + + SRAM1PDS8 + 4 + 1 + read-write + + + SRAM1PDS9 + 5 + 1 + read-write + + + SRAM1PDS10 + 6 + 1 + read-write + + + SRAM1PDS11 + 7 + 1 + read-write + + + SRAM1PDS12 + 8 + 1 + read-write + + + SRAM3PDS9 + 10 + 1 + read-write + + + SRAM3PDS10 + 11 + 1 + read-write + + + SRAM3PDS11 + 12 + 1 + read-write + + + SRAM3PDS12 + 13 + 1 + read-write + + + SRAM3PDS13 + 14 + 1 + read-write + + + SRAM5PDS1 + 16 + 1 + read-write + + + SRAM5PDS2 + 17 + 1 + read-write + + + SRAM5PDS3 + 18 + 1 + read-write + + + SRAM5PDS4 + 19 + 1 + read-write + + + SRAM5PDS5 + 20 + 1 + read-write + + + SRAM5PDS6 + 21 + 1 + read-write + + + SRAM5PDS7 + 22 + 1 + read-write + + + SRAM5PDS8 + 23 + 1 + read-write + + + SRAM5PDS9 + 24 + 1 + read-write + + + SRAM5PDS10 + 25 + 1 + read-write + + + SRAM5PDS11 + 26 + 1 + read-write + + + SRAM5PDS12 + 27 + 1 + read-write + + + SRAM5PDS13 + 28 + 1 + read-write + + + + + + + SEC_PWR + DCB->DSCSR->CDS == 0 + 0x56020800 + + + RAMCFG + RAMCFG + RAMCFG + 0x40026000 + + 0x0 + 0x1000 + registers + + + RAMCFG + RAM configuration global interrupt + 5 + + + + M1CR + M1CR + RAMCFG SRAM x control register + 0x0 + 0x20 + read-write + 0x00000000 + + + ECCE + ECCE + 0 + 1 + + + ALE + ALE + 4 + 1 + + + SRAMER + SRAMER + 8 + 1 + + + WSC + WSC + 16 + 3 + + + + + M1ISR + M1ISR + RAMCFG RAMx interrupt status register + 0x8 + 0x20 + read-only + 0x00000000 + + + SEDC + SEDC + 0 + 1 + + + DED + DED + 1 + 1 + + + SRAMBUSY + SRAMBUSY + 8 + 1 + + + + + RAM1ERKEYR + RAM1ERKEYR + RAMCFG SRAM x erase key register + 0x28 + 0x20 + write-only + 0x00000000 + + + ERASEKEY + ERASEKEY + 0 + 8 + + + + + M2CR + M2CR + RAMCFG SRAM x control register + 0x40 + 0x20 + read-write + 0x00000000 + + + ECCE + ECCE + 0 + 1 + + + ALE + ALE + 4 + 1 + + + SRAMER + SRAMER + 8 + 1 + + + WSC + WSC + 16 + 3 + + + + + M2IER + M2IER + RAMCFG SRAM x interrupt enable register + 0x44 + 0x20 + read-write + 0x00000000 + + + SEIE + SEIE + 0 + 1 + + + DEIE + DEIE + 1 + 1 + + + ECCNMI + ECCNMI + 3 + 1 + + + + + M2ISR + M2ISR + RAMCFG RAMx interrupt status register + 0x48 + 0x20 + read-only + 0x00000000 + + + SEDC + SEDC + 0 + 1 + + + DED + DED + 1 + 1 + + + SRAMBUSY + SRAMBUSY + 8 + 1 + + + + + M2SEAR + M2SEAR + RAMCFG RAM x ECC single error address register + 0x4C + 0x20 + read-only + 0x00000000 + + + ESEA + ESEA + 0 + 32 + + + + + M2DEAR + M2DEAR + RAMCFG RAM x ECC double error address register + 0x50 + 0x20 + read-only + 0x00000000 + + + EDEA + EDEA + 0 + 32 + + + + + M2ICR + M2ICR + RAMCFG RAM x interrupt clear register x + 0x54 + 0x20 + read-write + 0x00000000 + + + CSEDC + CSEDC + 0 + 1 + + + CDED + CDED + 1 + 1 + + + + + M2WPR1 + M2WPR1 + RAMCFG SRAM2 write protection register 1 + 0x58 + 0x20 + read-write + 0x00000000 + + + P0WP + P0WP + 0 + 1 + + + P1WP + P1WP + 1 + 1 + + + P2WP + P2WP + 2 + 1 + + + P3WP + P3WP + 3 + 1 + + + P4WP + P4WP + 4 + 1 + + + P5WP + P5WP + 5 + 1 + + + P6WP + P6WP + 6 + 1 + + + P7WP + P7WP + 7 + 1 + + + P8WP + P8WP + 8 + 1 + + + P9WP + P9WP + 9 + 1 + + + P10WP + P10WP + 10 + 1 + + + P11WP + P11WP + 11 + 1 + + + P12WP + P12WP + 12 + 1 + + + P13WP + P13WP + 13 + 1 + + + P14WP + P14WP + 14 + 1 + + + P15WP + P15WP + 15 + 1 + + + P16WP + P16WP + 16 + 1 + + + P17WP + P17WP + 17 + 1 + + + P18WP + P18WP + 18 + 1 + + + P19WP + P19WP + 19 + 1 + + + P20WP + P20WP + 20 + 1 + + + P21WP + P21WP + 21 + 1 + + + P22WP + P22WP + 22 + 1 + + + P23WP + P23WP + 23 + 1 + + + P24WP + P24WP + 24 + 1 + + + P25WP + P25WP + 25 + 1 + + + P26WP + P26WP + 26 + 1 + + + P27WP + P27WP + 27 + 1 + + + P28WP + P28WP + 28 + 1 + + + P29WP + P29WP + 29 + 1 + + + P30WP + P30WP + 30 + 1 + + + P31WP + P31WP + 31 + 1 + + + + + M2WPR2 + M2WPR2 + RAMCFG SRAM2 write protection register 2 + 0x5C + 0x20 + read-write + 0x00000000 + + + P32WP + P32WP + 0 + 1 + + + P33WP + P33WP + 1 + 1 + + + P34WP + P34WP + 2 + 1 + + + P35WP + P35WP + 3 + 1 + + + P36WP + P36WP + 4 + 1 + + + P37WP + P37WP + 5 + 1 + + + P38WP + P38WP + 6 + 1 + + + P39WP + P39WP + 7 + 1 + + + P40WP + P40WP + 8 + 1 + + + P41WP + P41WP + 9 + 1 + + + P42WP + P42WP + 10 + 1 + + + P43WP + P43WP + 11 + 1 + + + P44WP + P44WP + 12 + 1 + + + P45WP + P45WP + 13 + 1 + + + P46WP + P46WP + 14 + 1 + + + P47WP + P47WP + 15 + 1 + + + P48WP + P48WP + 16 + 1 + + + P49WP + P49WP + 17 + 1 + + + P50WP + P50WP + 18 + 1 + + + P51WP + P51WP + 19 + 1 + + + P52WP + P52WP + 20 + 1 + + + P53WP + P53WP + 21 + 1 + + + P54WP + P54WP + 22 + 1 + + + P55WP + P55WP + 23 + 1 + + + P56WP + P56WP + 24 + 1 + + + P57WP + P57WP + 25 + 1 + + + P58WP + P58WP + 26 + 1 + + + P59WP + P59WP + 27 + 1 + + + P60WP + P60WP + 28 + 1 + + + P61WP + P61WP + 29 + 1 + + + P62WP + P62WP + 30 + 1 + + + P63WP + P63WP + 31 + 1 + + + + + M2ECCKEYR + M2ECCKEYR + RAMCFG SRAM x ECC key register + 0x64 + 0x20 + write-only + 0x00000000 + + + ECCKEY + ECCKEY + 0 + 8 + + + + + M2ERKEYR + M2ERKEYR + RAMCFG SRAM x erase key register + 0x68 + 0x20 + write-only + 0x00000000 + + + ERASEKEY + ERASEKEY + 0 + 8 + + + + + M3CR + M3CR + RAMCFG SRAM x control register + 0x80 + 0x20 + read-write + 0x00000000 + + + ECCE + ECCE + 0 + 1 + + + ALE + ALE + 4 + 1 + + + SRAMER + SRAMER + 8 + 1 + + + WSC + WSC + 16 + 3 + + + + + M3IER + M3IER + RAMCFG SRAM x interrupt enable register + 0x84 + 0x20 + read-write + 0x00000000 + + + SEIE + SEIE + 0 + 1 + + + DEIE + DEIE + 1 + 1 + + + ECCNMI + ECCNMI + 3 + 1 + + + + + M3ISR + M3ISR + RAMCFG RAMx interrupt status register + 0x88 + 0x20 + read-only + 0x00000000 + + + SEDC + SEDC + 0 + 1 + + + DED + DED + 1 + 1 + + + SRAMBUSY + SRAMBUSY + 8 + 1 + + + + + M3SEAR + M3SEAR + RAMCFG RAM x ECC single error address register + 0x8C + 0x20 + read-only + 0x00000000 + + + ESEA + ESEA + 0 + 32 + + + + + M3DEAR + M3DEAR + RAMCFG RAM x ECC double error address register + 0x90 + 0x20 + read-only + 0x00000000 + + + EDEA + EDEA + 0 + 32 + + + + + M3ICR + M3ICR + RAMCFG RAM x interrupt clear register x + 0x94 + 0x20 + read-write + 0x00000000 + + + CSEDC + CSEDC + 0 + 1 + + + CDED + CDED + 1 + 1 + + + + + M3ECCKEYR + M3ECCKEYR + RAMCFG SRAM x ECC key register + 0xA4 + 0x20 + write-only + 0x00000000 + + + ECCKEY + ECCKEY + 0 + 8 + + + + + M3ERKEYR + M3ERKEYR + RAMCFG SRAM x erase key register + 0xA8 + 0x20 + write-only + 0x00000000 + + + ERASEKEY + ERASEKEY + 0 + 8 + + + + + M4CR + M4CR + RAMCFG SRAM x control register + 0xC0 + 0x20 + read-write + 0x00000000 + + + ECCE + ECCE + 0 + 1 + + + ALE + ALE + 4 + 1 + + + SRAMER + SRAMER + 8 + 1 + + + WSC + WSC + 16 + 3 + + + + + M4ISR + M4ISR + RAMCFG RAMx interrupt status register + 0xC8 + 0x20 + read-only + 0x00000000 + + + SEDC + SEDC + 0 + 1 + + + DED + DED + 1 + 1 + + + SRAMBUSY + SRAMBUSY + 8 + 1 + + + + + M4ERKEYR + M4ERKEYR + RAMCFG SRAM x erase key register + 0xE8 + 0x20 + write-only + 0x00000000 + + + ERASEKEY + ERASEKEY + 0 + 8 + + + + + M5CR + M5CR + RAMCFG SRAM x control register + 0x100 + 0x20 + read-write + 0x00000000 + + + ECCE + ECCE + 0 + 1 + + + ALE + ALE + 4 + 1 + + + SRAMER + SRAMER + 8 + 1 + + + WSC + WSC + 16 + 3 + + + + + M5IER + M5IER + RAMCFG SRAM x interrupt enable register + 0x104 + 0x20 + read-write + 0x00000000 + + + SEIE + SEIE + 0 + 1 + + + DEIE + DEIE + 1 + 1 + + + ECCNMI + ECCNMI + 3 + 1 + + + + + M5ISR + M5ISR + RAMCFG RAMx interrupt status register + 0x108 + 0x20 + read-only + 0x00000000 + + + SEDC + SEDC + 0 + 1 + + + DED + DED + 1 + 1 + + + SRAMBUSY + SRAMBUSY + 8 + 1 + + + + + M5SEAR + M5SEAR + RAMCFG RAM x ECC single error address register + 0x10C + 0x20 + read-only + 0x00000000 + + + ESEA + ESEA + 0 + 32 + + + + + M5DEAR + M5DEAR + RAMCFG RAM x ECC double error address register + 0x110 + 0x20 + read-only + 0x00000000 + + + EDEA + EDEA + 0 + 32 + + + + + M5ICR + M5ICR + RAMCFG RAM x interrupt clear register x + 0x114 + 0x20 + read-write + 0x00000000 + + + CSEDC + CSEDC + 0 + 1 + + + CDED + CDED + 1 + 1 + + + + + M5ECCKEYR + M5ECCKEYR + RAMCFG RAM x interrupt clear register x + 0x124 + 0x20 + read-write + 0x00000000 + + + ECCKEY + ECCKEY + 0 + 8 + + + + + M5ERKEYR + M5ERKEYR + 0x128 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ERASEKEY + Erase write protection key +The following steps are required to unlock the write protection of the SRAMER bit in the RAMCFG_MxCR register. +1) Write 0xCA into ERASEKEY[7:0]. +2) Write 0x53 into ERASEKEY[7:0]. +Note: Writing a wrong key reactivates the write protection. + 0 + 8 + write-only + + + + + M6CR + M6CR + memory x control register + 0x140 + 0x20 + read-write + 0x00000000 + + + ECCE + ECCE + 0 + 1 + + + ALE + ALE + 4 + 1 + + + SRAMER + SRAMER + 8 + 1 + + + WSC + WSC + 16 + 3 + + + + + M6ISR + M6ISR + 0x148 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + SEDC + ECC single error detected and corrected +Note: This bit is reserved and must be kept at reset value in SRAM1, SRAM4 and SRAM5 interrupt status registers. + 0 + 1 + read-only + + + B_0x0 + No single error + 0x0 + + + B_0x1 + Single error detected and corrected + 0x1 + + + + + DED + ECC double error detected +Note: This bit is reserved and must be kept at reset value in SRAM1, SRAM4 and SRAM5 interrupt status registers. + 1 + 1 + read-only + + + B_0x0 + No double error + 0x0 + + + B_0x1 + Double error detected + 0x1 + + + + + SRAMBUSY + SRAM busy with erase operation +Note: Depending on the SRAM, the erase operation can be performed due to software request, system reset if the option bit is enabled, tamper detection or readout protection regression. Refer to . + 8 + 1 + read-only + + + B_0x0 + No erase operation on going + 0x0 + + + B_0x1 + Erase operation on going + 0x1 + + + + + + + M6ERKEYR + M6ERKEYR + 0x168 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ERASEKEY + Erase write protection key +The following steps are required to unlock the write protection of the SRAMER bit in the RAMCFG_MxCR register. +1) Write 0xCA into ERASEKEY[7:0]. +2) Write 0x53 into ERASEKEY[7:0]. +Note: Writing a wrong key reactivates the write protection. + 0 + 8 + write-only + + + + + + + SEC_RAMCFG + DCB->DSCSR->CDS == 0 + 0x50026000 + + + RCC + Reset and clock control + RCC + 0x46020C00 + + 0x0 + 0x400 + registers + + + RCC + RCC non-secure global interrupt + 009 + + + RCC_S + RCC secure global interrupt + 010 + + + + RCC_CR + RCC_CR + RCC clock control register + 0x000 + 0x20 + 0x00000035 + 0xFFFFFFFF + + + MSISON + MSIS clock enable +This bit is set and cleared by software. It is cleared by hardware to stop the MSIS oscillator when entering Stop, Standby or Shutdown mode. This bit is set by hardware to force the�MSIS oscillator on when exiting Standby or Shutdown mode. It is set by hardware to force the MSIS oscillator ON when STOPWUCK = 0 when exiting Stop modes, or in case of a failure of the HSE oscillator. +Set by hardware when used directly or indirectly as system clock. + 0 + 1 + read-write + + + B_0x0 + MSIS (MSI system) oscillator off + 0x0 + + + B_0x1 + MSIS (MSI system) oscillator on + 0x1 + + + + + MSIKERON + MSI enable for some peripheral kernels +This bit is set and cleared by software to force MSI ON even in Stop modes. Keeping the MSI on in Stop mode allows the communication speed not to be reduced by the MSI startup time. This bit has no effect on MSISON and MSIKON values (see Section�11.4.24 for more details). This bit must be configured at 0 before entering Stop 3 mode. + 1 + 1 + read-write + + + B_0x0 + No effect on MSI oscillator + 0x0 + + + B_0x1 + MSI oscillator forced ON even in Stop mode + 0x1 + + + + + MSISRDY + MSIS clock ready flag +This bit is set by hardware to indicate that the MSIS oscillator is stable. It is set only when MSIS is enabled by software (by setting MSISON). +Note: Once the MSISON bit is cleared, MSISRDY goes low after six MSIS clock cycles. + 2 + 1 + read-only + + + B_0x0 + MSIS (MSI system) oscillator not ready + 0x0 + + + B_0x1 + MSIS (MSI system) oscillator ready + 0x1 + + + + + MSIPLLEN + MSI clock PLL-mode enable +This bit is set and cleared by software to enable/disable the PLL part of the MSI clock source. +MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware). A hardware protection prevents from enabling MSIPLLEN if LSE is not ready. This bit is cleared by hardware when LSE is disabled (LSEON = 0) or when the CSS on LSE detects a LSE failure (see RCC_CSR). + 3 + 1 + read-write + + + B_0x0 + MSI PLL-mode OFF + 0x0 + + + B_0x1 + MSI PLL-mode ON + 0x1 + + + + + MSIKON + MSIK clock enable +This bit is set and cleared by software. It is cleared by hardware to stop the MSIK when entering Stop, Standby, or Shutdown mode. This bit is set by hardware to force the MSIK oscillator ON when exiting Standby or Shutdown mode. It is set by hardware to force the MSIK oscillator on when STOPWUCK = 0 or STOPKERWUCK�=�0 when exiting Stop modes, or in case of a failure of the HSE oscillator. + 4 + 1 + read-write + + + B_0x0 + MSIK (MSI kernel) oscillator disabled + 0x0 + + + B_0x1 + MSIK (MSI kernel) oscillator enabled + 0x1 + + + + + MSIKRDY + MSIK clock ready flag +This bit is set by hardware to indicate that the MSIK is stable. It is set only when MSI kernel oscillator is enabled by software by setting MSIKON. +Note: Once MSIKON bit is cleared, MSIKRDY goes low after six MSIK oscillator clock cycles. + 5 + 1 + read-only + + + B_0x0 + MSIK (MSI kernel) oscillator not ready + 0x0 + + + B_0x1 + MSIK (MSI kernel) oscillator ready + 0x1 + + + + + MSIPLLSEL + MSI clock with PLL mode selection +This bit is set and cleared by software to select which MSI output clock uses the PLL mode. It�can be written only when the MSI PLL mode is disabled (MSIPLLEN = 0). +Note: If the MSI kernel clock output uses the same oscillator source than the MSI system clock output, then the PLL mode is applied to both clock outputs. + 6 + 1 + read-write + + + B_0x0 + PLL mode applied to MSIK (MSI kernel) clock output + 0x0 + + + B_0x1 + PLL mode applied to MSIS (MSI system) clock output + 0x1 + + + + + MSIPLLFAST + MSI PLL mode fast startup +This bit is set and reset by software to enable/disable the fast PLL mode start-up of the MSI clock source. This bit is used only if PLL mode is selected (MSIPLLEN = 1). +The fast start-up feature is not active the first time the PLL mode is selected. The�fast start-up is active when the MSI in PLL mode returns from switch off. + 7 + 1 + read-write + + + B_0x0 + MSI PLL normal start-up + 0x0 + + + B_0x1 + MSI PLL fast start-up + 0x1 + + + + + HSION + HSI16 clock enable +This bit is set and cleared by software. It is cleared by hardware to stop the HSI16 oscillator when entering Stop, Standby, or Shutdown mode. This bit is set by hardware to force the�HSI16 oscillator on when STOPWUCK = 1 when leaving Stop modes, or in case of failure of the HSE crystal oscillator. This bit is set by hardware if the HSI16 is used directly or indirectly as system clock. + 8 + 1 + read-write + + + B_0x0 + HSI16 oscillator off + 0x0 + + + B_0x1 + HSI16 oscillator on + 0x1 + + + + + HSIKERON + HSI16 enable for some peripheral kernels +This bit is set and cleared by software to force HSI16 ON even in Stop modes. Keeping HSI16 on in Stop mode allows the communication speed not to be reduced by the HSI16 startup time. This bit has no effect on HSION value. Refer to Section�11.4.24 for more details. +This bit must be configured at 0 before entering Stop 3 mode. + 9 + 1 + read-write + + + B_0x0 + No effect on HSI16 oscillator + 0x0 + + + B_0x1 + HSI16 oscillator forced on even in Stop mode + 0x1 + + + + + HSIRDY + HSI16 clock ready flag +This bit is set by hardware to indicate that HSI16 oscillator is stable. It is set only when HSI16 is enabled by software (by setting HSION). +Note: Once the HSION bit is cleared, HSIRDY goes low after six HSI16 clock cycles. + 10 + 1 + read-only + + + B_0x0 + HSI16 oscillator not ready + 0x0 + + + B_0x1 + HSI16 oscillator ready + 0x1 + + + + + HSI48ON + HSI48 clock enable +This bit is set and cleared by software. It is cleared by hardware to stop the HSI48 when entering in Stop, Standby, or Shutdown modes. + 12 + 1 + read-write + + + B_0x0 + HSI48 oscillator off + 0x0 + + + B_0x1 + HSI48 oscillator on + 0x1 + + + + + HSI48RDY + HSI48 clock ready flag +This bit is set by hardware to indicate that HSI48 oscillator is stable. Itis set only when HSI48 is enabled by software (by setting HSI48ON). + 13 + 1 + read-only + + + B_0x0 + HSI48 oscillator not ready + 0x0 + + + B_0x1 + HSI48 oscillator ready + 0x1 + + + + + SHSION + SHSI clock enable +This bit is set and cleared by software. It is cleared by hardware to stop the SHSI when entering in Stop, Standby, or Shutdown modes. + 14 + 1 + read-write + + + B_0x0 + SHSI oscillator off + 0x0 + + + B_0x1 + SHSI oscillator on + 0x1 + + + + + SHSIRDY + SHSI clock ready flag +This bit is set by hardware to indicate that the SHSI oscillator is stable. It is set only when SHSI is enabled by software (by setting SHSION). +Note: Once the SHSION bit is cleared, SHSIRDY goes low after six SHSI clock cycles. + 15 + 1 + read-only + + + B_0x0 + SHSI oscillator not ready + 0x0 + + + B_0x1 + SHSI oscillator ready + 0x1 + + + + + HSEON + HSE clock enable +This bit is set and cleared by software. It is cleared by hardware to stop the HSE oscillator when entering Stop, Standby, or Shutdown mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock. + 16 + 1 + read-write + + + B_0x0 + HSE oscillator off + 0x0 + + + B_0x1 + HSE oscillator on + 0x1 + + + + + HSERDY + HSE clock ready flag +This bit is set by hardware to indicate that the HSE oscillator is stable. +Note: Once the HSEON bit is cleared, HSERDY goes low after six HSE clock cycles. + 17 + 1 + read-only + + + B_0x0 + HSE oscillator not ready + 0x0 + + + B_0x1 + HSE oscillator ready + 0x1 + + + + + HSEBYP + HSE crystal oscillator bypass +This bit is set and cleared by software to bypass the oscillator with an external clock. The�external clock must be enabled with the HSEON bit set, to be used by the device. This�bit can be written only if the HSE oscillator is disabled. + 18 + 1 + read-write + + + B_0x0 + HSE crystal oscillator not bypassed + 0x0 + + + B_0x1 + HSE crystal oscillator bypassed with external clock + 0x1 + + + + + CSSON + Clock security system enable +This bit is set by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset. + 19 + 1 + read-write + + + B_0x0 + clock security system OFF (clock detector OFF) + 0x0 + + + B_0x1 + clock security system ON (clock detector ON if the HSE oscillator is stable, OFF if not). + 0x1 + + + + + HSEEXT + HSE external clock bypass mode +This bit is set and reset by software to select the external clock mode in bypass mode. External clock mode must be configured with HSEON bit to be used by the device. This bit can be written only if the HSE oscillator is disabled. This bit is active only if the HSE bypass mode is enabled. + 20 + 1 + read-write + + + B_0x0 + external HSE clock analog mode + 0x0 + + + B_0x1 + external HSE clock digital mode (through I/O Schmitt trigger) + 0x1 + + + + + PLL1ON + PLL1 enable +This bit is set and cleared by software to enable the main PLL. It is cleared by hardware when entering Stop, Standby, or Shutdown mode. This bit cannot be reset if the PLL1 clock is used as the system clock. + 24 + 1 + read-write + + + B_0x0 + PLL1 OFF + 0x0 + + + B_0x1 + PLL1 ON + 0x1 + + + + + PLL1RDY + PLL1 clock ready flag +This bit is set by hardware to indicate that the PLL1 is locked. + 25 + 1 + read-only + + + B_0x0 + PLL1 unlocked + 0x0 + + + B_0x1 + PLL1 locked + 0x1 + + + + + PLL2ON + PLL2 enable +This bit is set and cleared by software to enable PLL2. It is cleared by hardware when entering Stop, Standby, or Shutdown mode. + 26 + 1 + read-write + + + B_0x0 + PLL2 OFF + 0x0 + + + B_0x1 + PLL2 ON + 0x1 + + + + + PLL2RDY + PLL2 clock ready flag +This bit is set by hardware to indicate that the PLL2 is locked. + 27 + 1 + read-only + + + B_0x0 + PLL2 unlocked + 0x0 + + + B_0x1 + PLL2 locked + 0x1 + + + + + PLL3ON + PLL3 enable +This bit is set and cleared by software to enable PLL3. It is cleared by hardware when entering Stop, Standby, or Shutdown mode. + 28 + 1 + read-write + + + B_0x0 + PLL3 OFF + 0x0 + + + B_0x1 + PLL3 ON + 0x1 + + + + + PLL3RDY + PLL3 clock ready flag +This bit is set by hardware to indicate that the PLL3 is locked. + 29 + 1 + read-only + + + B_0x0 + PLL3 unlocked + 0x0 + + + B_0x1 + PLL3 locked + 0x1 + + + + + + + RCC_ICSCR1 + RCC_ICSCR1 + RCC internal clock sources calibration register 1 + 0x008 + 0x20 + 0x44000000 + 0xFFF00000 + + + MSICAL3 + MSIRC3 clock calibration for MSI ranges 12 to 15 +These bits are initialized at startup with the factory-programmed MSIRC3 calibration trim value for ranges 12 to 15. When MSITRIM3 is written, MSICAL3 is updated with the sum of MSITRIM3[4:0] and the factory calibration trim value MSIRC2[4:0]. +There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level. + 0 + 5 + read-only + + + MSICAL2 + MSIRC2 clock calibration for MSI ranges 8 to 11 +These bits are initialized at startup with the factory-programmed MSIRC2 calibration trim value for ranges 8 to 11. When MSITRIM2 is written, MSICAL2 is updated with the sum of MSITRIM2[4:0] and the factory calibration trim value MSIRC2[4:0]. +There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level. + 5 + 5 + read-only + + + MSICAL1 + MSIRC1 clock calibration for MSI ranges 4 to 7 +These bits are initialized at startup with the factory-programmed MSIRC1 calibration trim value for ranges 4 to 7. When MSITRIM1 is written, MSICAL1 is updated with the sum of MSITRIM1[4:0] and the factory calibration trim value MSIRC1[4:0]. +There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level. + 10 + 5 + read-only + + + MSICAL0 + MSIRC0 clock calibration for MSI ranges 0 to 3 +These bits are initialized at startup with the factory-programmed MSIRC0 calibration trim value for ranges 0 to 3. When MSITRIM0 is written, MSICAL0 is updated with the sum of MSITRIM0[4:0] and the factory-programmed calibration trim value MSIRC0[4:0]. +There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level. + 15 + 5 + read-only + + + MSIBIAS + MSI bias mode selection +This bit is set by software to select the MSI bias mode. By default, the MSI bias is in�continuous mode in order to maintain the output clocks accuracy. Setting this bit reduces the MSI consumption when the regulator is in range 4, or when the device is in Stop 1 or Stop�2 mode, but it�decreases the MSI accuracy + 22 + 1 + read-write + + + B_0x0 + MSI bias continuous mode (clock accuracy fast settling time) + 0x0 + + + B_0x1 + MSI bias sampling mode when the regulator is in range 4, or when the device is in�Stop�1�or Stop 2 (ultra-low-power mode) + 0x1 + + + + + MSIRGSEL + MSI clock range selection +This bit is set by software to select the MSIS and MSIK clocks range with MSISRANGE[3:0] and MSIKRANGE[3:0]. Write 0 has no effect. +After exiting Standby or Shutdown mode, or after a reset, this bit is at 0 and the MSIS and MSIK ranges are provided by MSISSRANGE[3:0] and MSIKSRANGE[3:0] in RCC_CSR. + 23 + 1 + read-write + + + B_0x0 + MSIS/MSIK ranges provided by MSISSRANGE[3:0] and MSIKSRANGE[3:0] in RCC_CSR + 0x0 + + + B_0x1 + MSIS/MSIK ranges provided by MSISRANGE[3:0] and MSIKRANGE[3:0] in�RCC_ICSCR1 + 0x1 + + + + + MSIKRANGE + MSIK clock ranges +These bits are configured by software to choose the frequency range of MSIK oscillator when MSIRGSEL is set. 16 frequency ranges are available: +Note: MSIKRANGE can be modified when MSIK is off (MSISON = 0) or when MSIK is ready (MSIKRDY�=�1). MSIKRANGE must NOT be modified when MSIK is on and NOT ready (MSIKON = 1 and MSIKRDY = 0) +Note: MSIKRANGE is kept when the device wakes up from Stop mode, except when the�MSIK range is above 24 MHz. In this case MSIKRANGE is changed by hardware into�range 2 (24 MHz). + 24 + 4 + read-write + + + B_0x0 + range 0 around 48�MHz + 0x0 + + + B_0x1 + range 1 around 24�MHz + 0x1 + + + B_0x2 + range 2 around 16�MHz + 0x2 + + + B_0x3 + range 3 around 12�MHz + 0x3 + + + B_0x4 + range 4 around 4�MHz (reset value) + 0x4 + + + B_0x5 + range 5 around 2�MHz + 0x5 + + + B_0x6 + range 6 around 1.33�MHz + 0x6 + + + B_0x7 + range 7 around 1�MHz + 0x7 + + + B_0x8 + range 8 around 3.072�MHz + 0x8 + + + B_0x9 + range 9 around 1.536�MHz + 0x9 + + + B_0xA + range 10 around 1.024�MHz + 0xA + + + B_0xB + range 11 around 768�kHz + 0xB + + + B_0xC + range 12 around 400�kHz + 0xC + + + B_0xD + range 13 around 200�kHz + 0xD + + + B_0xE + range 14 around 133 kHz + 0xE + + + B_0xF + range 15 around 100�kHz + 0xF + + + + + MSISRANGE + MSIS clock ranges +These bits are configured by software to choose the frequency range of MSIS oscillator when MSIRGSEL is set. 16 frequency ranges are available: +Note: MSISRANGE can be modified when MSIS is off (MSISON = 0) or when MSIS is ready (MSISRDY�=�1). MSISRANGE must NOT be modified when MSIS is on and NOT ready (MSISON�=�1 and MSISRDY�=�0) +Note: MSISRANGE is kept when the device wakes up from Stop mode, except when the�MSIS range is above 24 MHz. In this case MSISRANGE is changed by hardware into range 2 (24 MHz). + 28 + 4 + read-write + + + B_0x0 + range 0 around 48�MHz + 0x0 + + + B_0x1 + range 1 around 24�MHz + 0x1 + + + B_0x2 + range 2 around 16�MHz + 0x2 + + + B_0x3 + range 3 around 12�MHz + 0x3 + + + B_0x4 + range 4 around 4�MHz (reset value) + 0x4 + + + B_0x5 + range 5 around 2�MHz + 0x5 + + + B_0x6 + range 6 around 1.33�MHz + 0x6 + + + B_0x7 + range 7 around 1�MHz + 0x7 + + + B_0x8 + range 8 around 3.072�MHz + 0x8 + + + B_0x9 + range 9 around 1.536�MHz + 0x9 + + + B_0xA + range 10 around 1.024�MHz + 0xA + + + B_0xB + range 11 around 768�kHz + 0xB + + + B_0xC + range 12 around 400�kHz + 0xC + + + B_0xD + range 13 around 200�kHz + 0xD + + + B_0xE + range 14 around 133 kHz + 0xE + + + B_0xF + range 15 around 100�kHz + 0xF + + + + + + + RCC_ICSCR2 + RCC_ICSCR2 + RCC internal clock sources calibration register 2 + 0x00C + 0x20 + 0x00084210 + 0xFFFFFFFF + + + MSITRIM3 + MSI clock trimming for ranges 12 to 15 +These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC3[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI. + 0 + 5 + read-write + + + MSITRIM2 + MSI clock trimming for ranges 8 to 11 +These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC2[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI. + 5 + 5 + read-write + + + MSITRIM1 + MSI clock trimming for ranges 4 to 7 +These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC1[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI. + 10 + 5 + read-write + + + MSITRIM0 + MSI clock trimming for ranges 0 to 3 +These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC0[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI. + 15 + 5 + read-write + + + + + RCC_ICSCR3 + RCC_ICSCR3 + RCC internal clock sources calibration register 3 + 0x010 + 0x20 + 0x00100000 + 0xFFFFF000 + + + HSICAL + HSI clock calibration +These bits are initialized at startup with the factory-programmed HSI calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value. + 0 + 12 + read-only + + + HSITRIM + HSI clock trimming +These bits provide an additional user-programmable trimming value that is added to HSICAL[11:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the HSI. + 16 + 5 + read-write + + + + + RCC_CRRCR + RCC_CRRCR + RCC clock recovery RC register + 0x014 + 0x20 + 0x00000000 + 0xFFFFF000 + + + HSI48CAL + HSI48 clock calibration +These bits are initialized at startup with the factory-programmed HSI48 calibration trim value. + 0 + 9 + read-only + + + + + RCC_CFGR1 + RCC_CFGR1 + RCC clock configuration register 1 + 0x01C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SW + system clock switch +This bitfield is set and cleared by software to select system clock source (SYSCLK). It is configured by hardware to force MSIS oscillator selection when exiting Standby or Shutdown mode. This bitfield is configured by hardware to force MSIS or HSI16 oscillator selection when exiting Stop mode or in case of HSE oscillator failure, depending on STOPWUCK. + 0 + 2 + read-write + + + B_0x0 + MSIS selected as system clock + 0x0 + + + B_0x1 + HSI16 selected as system clock + 0x1 + + + B_0x2 + HSE selected as system clock + 0x2 + + + B_0x3 + PLL pll1_r_ck selected as system clock + 0x3 + + + + + SWS + system clock switch status +This bitfield is set and cleared by hardware to indicate which clock source is used as system clock. + 2 + 2 + read-only + + + B_0x0 + MSIS oscillator used as system clock + 0x0 + + + B_0x1 + HSI16 oscillator used as system clock + 0x1 + + + B_0x2 + HSE used as system clock + 0x2 + + + B_0x3 + PLL pll1_r_ck used as system clock + 0x3 + + + + + STOPWUCK + wake-up from Stop and CSS backup clock selection +This bit is set and cleared by software to select the system clock used when exiting Stop mode. The selected clock is also used as emergency clock for the clock security system on�HSE. +STOPWUCK must not be modified when the CSS is enabled by HSECSSON in�RCC_CR, and the system clock is HSE (SWS = 10) or a switch on HSE is�requested (SW�=�10). + 4 + 1 + read-write + + + B_0x0 + MSIS oscillator selected as wake-up from stop clock and CSS backup clock + 0x0 + + + B_0x1 + HSI16 oscillator selected as wake-up from stop clock and CSS backup clock + 0x1 + + + + + STOPKERWUCK + wake-up from Stop kernel clock automatic enable selection +This bit is set and cleared by software to enable automatically another oscillator when exiting Stop mode. This oscillator can be used as independent kernel clock by peripherals. + 5 + 1 + read-write + + + B_0x0 + MSIK oscillator automatically enabled when exiting Stop mode + 0x0 + + + B_0x1 + HSI16 oscillator automatically enabled when exiting Stop mode + 0x1 + + + + + MCOSEL + microcontroller clock output +This bitfield is set and cleared by software. +Others: reserved +Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. + 24 + 4 + read-write + + + B_0x0 + MCO output disabled, no clock on MCO + 0x0 + + + B_0x1 + SYSCLK system clock selected + 0x1 + + + B_0x2 + MSIS clock selected + 0x2 + + + B_0x3 + HSI16 clock selected + 0x3 + + + B_0x4 + HSE clock selected + 0x4 + + + B_0x5 + Main PLL clock pll1_r_ck selected + 0x5 + + + B_0x6 + LSI clock selected + 0x6 + + + B_0x7 + LSE clock selected + 0x7 + + + B_0x8 + Internal HSI48 clock selected + 0x8 + + + B_0x9 + MSIK clock selected + 0x9 + + + + + MCOPRE + microcontroller clock output prescaler +This bitfield is set and cleared by software. It is highly recommended to change this prescaler before MCO output is enabled. +Others: not allowed + 28 + 3 + read-write + + + B_0x0 + MCO divided by 1 + 0x0 + + + B_0x1 + MCO divided by 2 + 0x1 + + + B_0x2 + MCO divided by 4 + 0x2 + + + B_0x3 + MCO divided by 8 + 0x3 + + + B_0x4 + MCO divided by 16 + 0x4 + + + + + + + RCC_CFGR2 + RCC_CFGR2 + RCC clock configuration register 2 + 0x020 + 0x20 + 0x00006000 + 0xFFFFFFFF + + + HPRE + AHB prescaler +This bitfiled is set and cleared by software to control the division factor of the AHB clock (HCLK). +Depending on the device voltage range, the software must set these bits correctly to ensure that the system frequency does not exceed the maximum allowed frequency (for more details, refer to Table�118). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account. +0xxx: SYSCLK not divided + 0 + 4 + read-write + + + B_0x8 + SYSCLK divided by 2 + 0x8 + + + B_0x9 + SYSCLK divided by 4 + 0x9 + + + B_0xA + SYSCLK divided by 8 + 0xA + + + B_0xB + SYSCLK divided by 16 + 0xB + + + B_0xC + SYSCLK divided by 64 + 0xC + + + B_0xD + SYSCLK divided by 128 + 0xD + + + B_0xE + SYSCLK divided by 256 + 0xE + + + B_0xF + SYSCLK divided by 512 + 0xF + + + + + PPRE1 + APB1 prescaler +This bitfiled is set and cleared by software to control the division factor of APB1 clock (PCLK1). +0xx: PCLK1 not divided + 4 + 3 + read-write + + + B_0x4 + PCLK1 divided by 2 + 0x4 + + + B_0x5 + PCLK1 divided by 4 + 0x5 + + + B_0x6 + PCLK1 divided by 8 + 0x6 + + + B_0x7 + PCLK1 divided by 16 + 0x7 + + + + + PPRE2 + APB2 prescaler +This bitfiled is set and cleared by software to control the division factor of APB2 clock (PCLK2). +0xx: PCLK2 not divided + 8 + 3 + read-write + + + B_0x4 + PCLK2 divided by 2 + 0x4 + + + B_0x5 + PCLK2 divided by 4 + 0x5 + + + B_0x6 + PCLK2 divided by 8 + 0x6 + + + B_0x7 + PCLK2 divided by 16 + 0x7 + + + + + DPRE + DSI PHY prescaler +This bitfiled is set and cleared by software to control the division factor of DSI PHY bus clock (DCLK). +0xx: DCLK not divided +Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value. + 12 + 3 + read-write + + + B_0x4 + DCLK divided by 2 + 0x4 + + + B_0x5 + DCLK divided by 4 + 0x5 + + + B_0x6 + DCLK divided by 8 + 0x6 + + + B_0x7 + DCLK divided by 16 + 0x7 + + + + + AHB1DIS + AHB1 clock disable +This bit can be set in order to further reduce power consumption, when none of the AHB1 peripherals (except those listed hereafter) are used and when their clocks are disabled in RCC_AHB1ENR. When this bit is set, all the AHB1 peripherals clocks are off, except for FLASH, BKPSRAM, ICACHE, DCACHE1 and SRAM1. + 16 + 1 + read-write + + + B_0x0 + AHB1 clock enabled, distributed to peripherals according to their dedicated clock enable control bits + 0x0 + + + B_0x1 + AHB1 clock disabled + 0x1 + + + + + AHB2DIS1 + AHB2_1 clock disable +This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR1 (except SRAM2 and SRAM3) are used and when their clocks are disabled in RCC_AHB2ENR1. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2ENR1 are off, except for SRAM2 and SRAM3. + 17 + 1 + read-write + + + B_0x0 + AHB2_1 clock enabled, distributed to peripherals according to their dedicated clock enable control bits + 0x0 + + + B_0x1 + AHB2_1 clock disabled + 0x1 + + + + + AHB2DIS2 + AHB2_2 clock disable +This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR2 are used and when their clocks are disabled in RCC_AHB2ENR2. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2ENR2 are off. + 18 + 1 + read-write + + + B_0x0 + AHB2_2 clock enabled, distributed to peripherals according to their dedicated clock enable control bits + 0x0 + + + B_0x1 + AHB2_2 clock disabled + 0x1 + + + + + APB1DIS + APB1 clock disable +This bit can be set in order to further reduce power consumption, when none of the APB1 peripherals (except IWDG) are used and when their clocks are disabled in RCC_APB1ENR. When this bit is set, all the APB1 peripherals clocks are off, except for IWDG. + 19 + 1 + read-write + + + B_0x0 + APB1 clock enabled, distributed to peripherals according to their dedicated clock enable control bits + 0x0 + + + B_0x1 + APB1 clock disabled + 0x1 + + + + + APB2DIS + APB2 clock disable +This bit can be set in order to further reduce power consumption, when none of the APB2 peripherals are used and when their clocks are disabled in RCC_APB2ENR. When this bit is set, all APB2 peripherals clocks are off. + 20 + 1 + read-write + + + B_0x0 + APB2 clock enabled, distributed to peripherals according to their dedicated clock enable control bits + 0x0 + + + B_0x1 + APB2 clock disabled + 0x1 + + + + + + + RCC_CFGR3 + RCC_CFGR3 + RCC clock configuration register 3 + 0x024 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PPRE3 + APB3 prescaler +This bitfield is set and cleared by software to control the division factor of the APB3 clock (PCLK3). +0xx: HCLK not divided + 4 + 3 + read-write + + + B_0x4 + HCLK divided by 2 + 0x4 + + + B_0x5 + HCLK divided by 4 + 0x5 + + + B_0x6 + HCLK divided by 8 + 0x6 + + + B_0x7 + HCLK divided by 16 + 0x7 + + + + + AHB3DIS + AHB3 clock disable +This bit can be set in order to further reduce power consumption, when none of the AHB3 peripherals (except SRAM4) are used and when their clocks are disabled in RCC_AHB3ENR. When this bit is set, all the AHB3 peripherals clocks are off, except for SRAM4. + 16 + 1 + read-write + + + B_0x0 + AHB3 clock enabled, distributed to peripherals according to their dedicated clock enable control bits + 0x0 + + + B_0x1 + AHB3 clock disabled + 0x1 + + + + + APB3DIS + APB3 clock disable +This bit can be set in order to further reduce power consumption, when none of the APB3 peripherals from RCC_APB3ENR are used and when their clocks are disabled in RCC_APB3ENR. When this bit is set, all the APB3 peripherals clocks are off. + 17 + 1 + read-write + + + B_0x0 + APB3 clock enabled, distributed to peripherals according to their dedicated clock enable control bits + 0x0 + + + B_0x1 + APB3 clock disabled + 0x1 + + + + + + + RCC_PLL1CFGR + RCC_PLL1CFGR + RCC PLL1 configuration register + 0x028 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PLL1SRC + PLL1 entry clock source +This bitfield is set and cleared by software to select PLL1 clock source. It can be written only when the PLL1 is disabled. In order to save power, when no PLL1 is used, this bitfield value must be zero. + 0 + 2 + read-write + + + B_0x0 + No clock sent to PLL1 + 0x0 + + + B_0x1 + MSIS clock selected as PLL1 clock entry + 0x1 + + + B_0x2 + HSI16 clock selected as PLL1 clock entry + 0x2 + + + B_0x3 + HSE clock selected as PLL1 clock entry + 0x3 + + + + + PLL1RGE + PLL1 input frequency range +This bit is set and reset by software to select the proper reference frequency range used for PLL1. It must be written before enabling the PLL1. +00-01-10: PLL1 input (ref1_ck) clock range frequency between 4 and 8 MHz + 2 + 2 + read-write + + + B_0x3 + PLL1 input (ref1_ck) clock range frequency between 8 and 16 MHz + 0x3 + + + + + PLL1FRACEN + PLL1 fractional latch enable +This bit is set and reset by software to latch the content of PLL1FRACN in the ΣΔ modulator. In order to latch the PLL1FRACN value into the ΣΔ modulator, PLL1FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL1FRACN into the modulator (see PLL initialization phase for details). + 4 + 1 + read-write + + + PLL1M + Prescaler for PLL1 +This bitfield is set and cleared by software to configure the prescaler of the PLL1. The VCO1 input frequency is PLL1 input clock frequency/PLL1M. +This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). +... + 8 + 4 + read-write + + + B_0x0 + division by 1 (bypass) + 0x0 + + + B_0x1 + division by 2 + 0x1 + + + B_0x2 + division by 3 + 0x2 + + + B_0xF + division by 16 + 0xF + + + + + PLL1MBOOST + Prescaler for EPOD booster input clock +This bitfield is set and cleared by software to configure the prescaler of the PLL1, used for the EPOD booster. The EPOD booster input frequency is PLL1�input�clock�frequency/PLL1MBOOST. +This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0) and EPODboost mode is disabled (see Section�10: Power control (PWR)). +others: reserved + 12 + 4 + read-write + + + B_0x0 + division by 1 (bypass) + 0x0 + + + B_0x1 + division by 2 + 0x1 + + + B_0x2 + division by 4 + 0x2 + + + B_0x3 + division by 6 + 0x3 + + + B_0x4 + division by 8 + 0x4 + + + B_0x5 + division by 10 + 0x5 + + + B_0x6 + division by 12 + 0x6 + + + B_0x7 + division by 14 + 0x7 + + + B_0x8 + division by 16 + 0x8 + + + + + PLL1PEN + PLL1 DIVP divider output enable +This bit is set and reset by software to enable the pll1_p_ck output of the PLL1. To save power, PLL1PEN and PLL1P bits must be set to 0 when pll1_p_ck is not used. + 16 + 1 + read-write + + + B_0x0 + pll1_p_ck output disabled + 0x0 + + + B_0x1 + pll1_p_ck output enabled + 0x1 + + + + + PLL1QEN + PLL1 DIVQ divider output enable +This bit is set and reset by software to enable the pll1_q_ck output of the PLL1. To save power, PLL1QEN and PLL1Q bits must be set to 0 when pll1_q_ck is not used. + 17 + 1 + read-write + + + B_0x0 + pll1_q_ck output disabled + 0x0 + + + B_0x1 + pll1_q_ck output enabled + 0x1 + + + + + PLL1REN + PLL1 DIVR divider output enable +This bit is set and reset by software to enable the pll1_r_ck output of the PLL1. To save power, PLL1RENPLL2REN and PLL1R bits must be set to 0 when pll1_r_ck is not used. This bit can be cleared only when the PLL1 is not used as SYSCLK. + 18 + 1 + read-write + + + B_0x0 + pll1_r_ck output disabled + 0x0 + + + B_0x1 + pll1_r_ck output enabled + 0x1 + + + + + + + RCC_PLL2CFGR + RCC_PLL2CFGR + RCC PLL2 configuration register + 0x02C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PLL2SRC + PLL2 entry clock source +This bitfield is set and cleared by software to select PLL2 clock source. It can be written only when the PLL2 is disabled. To save power, when no PLL2 is used, this bitfield value must be�zero. + 0 + 2 + read-write + + + B_0x0 + No clock sent to PLL2 + 0x0 + + + B_0x1 + MSIS clock selected as PLL2 clock entry + 0x1 + + + B_0x2 + HSI16 clock selected as PLL2 clock entry + 0x2 + + + B_0x3 + HSE clock selected as PLL2 clock entry + 0x3 + + + + + PLL2RGE + PLL2 input frequency range +This bitfield is set and reset by software to select the proper reference frequency range used for�PLL2. It must be written before enabling the PLL2. +00-01-10: PLL2 input (ref2_ck) clock range frequency between 4 and 8 MHz + 2 + 2 + read-write + + + B_0x3 + PLL2 input (ref2_ck) clock range frequency between 8 and 16 MHz + 0x3 + + + + + PLL2FRACEN + PLL2 fractional latch enable +This bit is set and reset by software to latch the content of PLL2FRACN in the ΣΔ modulator. In order to latch the PLL2FRACN value into the ΣΔ modulator, PLL2FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL2FRACN into the modulator (see PLL initialization phase for details). + 4 + 1 + read-write + + + PLL2M + Prescaler for PLL2 +This bitfield is set and cleared by software to configure the prescaler of the PLL2. The VCO2 input frequency is PLL2 input clock frequency/PLL2M. +This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). +... + 8 + 4 + read-write + + + B_0x0 + division by 1 (bypass) + 0x0 + + + B_0x1 + division by 2 + 0x1 + + + B_0x2 + division by 3 + 0x2 + + + B_0xF + division by 16 + 0xF + + + + + PLL2PEN + PLL2 DIVP divider output enable +This bit is set and reset by software to enable the pll2_p_ck output of the PLL2. To save power, PLL2PEN and PLL2P bits must be set to 0 when pll2_p_ck is not used. + 16 + 1 + read-write + + + B_0x0 + pll2_p_ck output disabled + 0x0 + + + B_0x1 + pll2_p_ck output enabled + 0x1 + + + + + PLL2QEN + PLL2 DIVQ divider output enable +This bit is set and reset by software to enable the pll2_q_ck output of the PLL2. To save power, PLL2QEN and PLL2Q bits must be set to 0 when pll2_q_ck is not used. + 17 + 1 + read-write + + + B_0x0 + pll2_q_ck output disabled + 0x0 + + + B_0x1 + pll2_q_ck output enabled + 0x1 + + + + + PLL2REN + PLL2 DIVR divider output enable +This bit is set and reset by software to enable the pll2_r_ck output of the PLL2. To save power, PLL2REN and PLL2R bits must be set to 0 when pll2_r_ck is not used. + 18 + 1 + read-write + + + B_0x0 + pll2_r_ck output disabled + 0x0 + + + B_0x1 + pll2_r_ck output enabled + 0x1 + + + + + + + RCC_PLL3CFGR + RCC_PLL3CFGR + RCC PLL3 configuration register + 0x030 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PLL3SRC + PLL3 entry clock source +This bitfield is set and cleared by software to select PLL3 clock source. It can be written only when the PLL3 is disabled. To save power, when no PLL3 is used, this bitfield value must be�zero. + 0 + 2 + read-write + + + B_0x0 + No clock sent to PLL3 + 0x0 + + + B_0x1 + MSIS clock selected as PLL3 clock entry + 0x1 + + + B_0x2 + HSI16 clock selected as PLL3 clock entry + 0x2 + + + B_0x3 + HSE clock selected as PLL3 clock entry + 0x3 + + + + + PLL3RGE + PLL3 input frequency range +This bit is set and reset by software to select the proper reference frequency range used for�PLL3. It must be written before enabling the PLL3. +00-01-10: PLL3 input (ref3_ck) clock range frequency between 4 and 8 MHz + 2 + 2 + read-write + + + B_0x3 + PLL3 input (ref3_ck) clock range frequency between 8 and 16 MHz + 0x3 + + + + + PLL3FRACEN + PLL3 fractional latch enable +This bit is set and reset by software to latch the content of PLL3FRACN in the ΣΔ modulator. In order to latch the PLL3FRACN value into the ΣΔ modulator, PLL3FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL3FRACN into the modulator (see PLL initialization phase for details). + 4 + 1 + read-write + + + PLL3M + Prescaler for PLL3 +This bitfield is set and cleared by software to configure the prescaler of the PLL3. The VCO3 input frequency is PLL3 input clock frequency/PLL3M. This bitfield can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0). +... + 8 + 4 + read-write + + + B_0x0 + division by 1 (bypass) + 0x0 + + + B_0x1 + division by 2 + 0x1 + + + B_0x2 + division by 3 + 0x2 + + + B_0xF + division by 16 + 0xF + + + + + PLL3PEN + PLL3 DIVP divider output enable +This bit is set and reset by software to enable the pll3_p_ck output of the PLL3. To save power, PLL3PEN and PLL3P bits must be set to 0 when pll3_p_ck is not used. + 16 + 1 + read-write + + + B_0x0 + pll3_p_ck output disabled + 0x0 + + + B_0x1 + pll3_p_ck output enabled + 0x1 + + + + + PLL3QEN + PLL3 DIVQ divider output enable +This bit is set and reset by software to enable the pll3_q_ck output of the PLL3. To save power, PLL3QEN and PLL3Q bits must be set to 0 when pll3_q_ck is not used. + 17 + 1 + read-write + + + B_0x0 + pll3_q_ck output disabled + 0x0 + + + B_0x1 + pll3_q_ck output enabled + 0x1 + + + + + PLL3REN + PLL3 DIVR divider output enable +This bit is set and reset by software to enable the pll3_r_ck output of the PLL3. To save power, PLL3REN and PLL3R bits must be set to 0 when pll3_r_ck is not used. + 18 + 1 + read-write + + + B_0x0 + pll3_r_ck output disabled + 0x0 + + + B_0x1 + pll3_r_ck output enabled + 0x1 + + + + + + + RCC_PLL1DIVR + RCC_PLL1DIVR + RCC PLL1 dividers register + 0x034 + 0x20 + 0x01010280 + 0xFFFFFFFF + + + PLL1N + Multiplication factor for PLL1 VCO +This bitfield is set and reset by software to control the multiplication factor of the VCO. It can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0). +... +... +Others: reserved +VCO output frequency = F<sub>ref1_ck</sub> x PLL1N, when fractional value 0 has been loaded in PLL1FRACN, with: +PLL1N between 4 and 512 +input frequency F<sub>ref1_ck</sub> between 4 and 16�MHz + 0 + 9 + read-write + + + B_0x003 + PLL1N = 4 + 0x003 + + + B_0x004 + PLL1N = 5 + 0x004 + + + B_0x005 + PLL1N = 6 + 0x005 + + + B_0x080 + PLL1N = 129 (default after reset) + 0x080 + + + B_0x1FF + PLL1N = 512 + 0x1FF + + + + + PLL1P + PLL1 DIVP division factor +This bitfield is set and reset by software to control the frequency of the pll1_p_ck clock. It can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). +... + 9 + 7 + read-write + + + B_0x0 + Not allowed + 0x0 + + + B_0x1 + pll1_p_ck = vco1_ck / 2 (default after reset) + 0x1 + + + B_0x2 + pll1_p_ck = vco1_ck + 0x2 + + + B_0x3 + pll1_p_ck = vco1_ck / 4 + 0x3 + + + B_0x7F + pll1_p_ck = vco1_ck / 128 + 0x7F + + + + + PLL1Q + PLL1 DIVQ division factor +This bitfield is set and reset by software to control the frequency of the pll1_q_ck clock. It can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). +... + 16 + 7 + read-write + + + B_0x0 + pll1_q_ck = vco1_ck + 0x0 + + + B_0x1 + pll1_q_ck = vco1_ck / 2 (default after reset) + 0x1 + + + B_0x2 + pll1_q_ck = vco1_ck / 3 + 0x2 + + + B_0x3 + pll1_q_ck = vco1_ck / 4 + 0x3 + + + B_0x7F + pll1_q_ck = vco1_ck / 128 + 0x7F + + + + + PLL1R + PLL1 DIVR division factor +This bitfield is set and reset by software to control frequency of the pll1_r_ck clock. It can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). Only division by one and even division factors are allowed. +... + 24 + 7 + read-write + + + B_0x0 + Not allowed + 0x0 + + + B_0x1 + pll1_r_ck = vco1_ck / 2 (default after reset) + 0x1 + + + B_0x2 + pll1_r_ck = vco1_ck / 3 + 0x2 + + + B_0x3 + pll1_r_ck = vco1_ck / 4 + 0x3 + + + B_0x7F + pll1_r_ck = vco1_ck / 128 + 0x7F + + + + + + + RCC_PLL1FRACR + RCC_PLL1FRACR + RCC PLL1 fractional divider register + 0x038 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PLL1FRACN + Fractional part of the multiplication factor for PLL1 VCO +This bitfield is set and reset by software to control the fractional part of the VCO multiplication factor. It can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO. +VCO output frequency = F<sub>ref1_ck</sub> x (PLL1N + (PLL1FRACN / 2<sup>13</sup>)), with: +PLL1N must be between 4 and 512. +PLL1FRACN can be between 0 and 2<sup>13</sup>- 1. +The input frequency F<sub>ref1_ck</sub> must be between 4 and 16 MHz. +To change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as�follows: +Set PLL1FRACEN = 0. +Write the new fractional value into PLL1FRACN. +Set PLL1FRACEN = 1. + 3 + 13 + read-write + + + + + RCC_PLL2DIVR + RCC_PLL2DIVR + RCC PLL2 dividers configuration register + 0x03C + 0x20 + 0x01010280 + 0xFFFFFFFF + + + PLL2N + Multiplication factor for PLL2 VCO +This bitfield is set and reset by software to control the multiplication factor of the VCO. It can be written only when the PLL is disabled (PLL2ON = 0 and PLL2RDY = 0). +... +... +Others: reserved +VCO output frequency = F<sub>ref2_ck</sub> x PLL2N, when fractional value 0 has been loaded in PLL2FRACN, with: +PLL2N between 4 and 512 +input frequency F<sub>ref2_ck</sub> between 1MHz and 16MHz + 0 + 9 + read-write + + + B_0x003 + PLL2N = 4 + 0x003 + + + B_0x004 + PLL2N = 5 + 0x004 + + + B_0x005 + PLL2N = 6 + 0x005 + + + B_0x080 + PLL2N = 129 (default after reset) + 0x080 + + + B_0x1FF + PLL2N = 512 + 0x1FF + + + + + PLL2P + PLL2 DIVP division factor +This bitfield is set and reset by software to control the frequency of the pll2_p_ck clock. It can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). +... + 9 + 7 + read-write + + + B_0x0 + pll2_p_ck = vco2_ck + 0x0 + + + B_0x1 + pll2_p_ck = vco2_ck / 2 (default after reset) + 0x1 + + + B_0x2 + pll2_p_ck = vco2_ck / 3 + 0x2 + + + B_0x3 + pll2_p_ck = vco2_ck / 4 + 0x3 + + + B_0x7F + pll2_p_ck = vco2_ck / 128 + 0x7F + + + + + PLL2Q + PLL2 DIVQ division factor +This bitfield is set and reset by software to control the frequency of the pll2_q_ck clock. It can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). +... + 16 + 7 + read-write + + + B_0x0 + pll2_q_ck = vco2_ck + 0x0 + + + B_0x1 + pll2_q_ck = vco2_ck / 2 (default after reset) + 0x1 + + + B_0x2 + pll2_q_ck = vco2_ck / 3 + 0x2 + + + B_0x3 + pll2_q_ck = vco2_ck / 4 + 0x3 + + + B_0x7F + pll2_q_ck = vco2_ck / 128 + 0x7F + + + + + PLL2R + PLL2 DIVR division factor +This bitfield is set and reset by software to control the frequency of the pll2_r_ck clock. It can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). +... + 24 + 7 + read-write + + + B_0x0 + pll2_r_ck = vco2_ck + 0x0 + + + B_0x1 + pll2_r_ck = vco2_ck / 2 (default after reset) + 0x1 + + + B_0x2 + pll2_r_ck = vco2_ck / 3 + 0x2 + + + B_0x3 + pll2_r_ck = vco2_ck / 4 + 0x3 + + + B_0x7F + pll2_r_ck = vco2_ck / 128 + 0x7F + + + + + + + RCC_PLL2FRACR + RCC_PLL2FRACR + RCC PLL2 fractional divider register + 0x040 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PLL2FRACN + Fractional part of the multiplication factor for PLL2 VCO +This bitfield is set and reset by software to control the fractional part of the VCO multiplication factor. It can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO. +VCO output frequency = F<sub>ref2_ck</sub> x (PLL2N + (PLL2FRACN / 2<sup>13</sup>)), with +PLL2N must be between 4 and 512. +PLL2FRACN can be between 0 and 2<sup>13 </sup>- 1. +The input frequency F<sub>ref2_ck</sub> must be between 4 and 16 MHz. +In order to change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: +Set the bit PLL2FRACEN to 0. +Write the new fractional value into PLL2FRACN. +Set the bit PLL2FRACEN to 1. + 3 + 13 + read-write + + + + + RCC_PLL3DIVR + RCC_PLL3DIVR + RCC PLL3 dividers configuration register + 0x044 + 0x20 + 0x01010280 + 0xFFFFFFFF + + + PLL3N + Multiplication factor for PLL3 VCO +This bitfield is set and reset by software to control the multiplication factor of the VCO. It can be written only when the PLL is disabled (PLL3ON = 0 and PLL3RDY = 0). +... +... +Others: reserved +VCO output frequency = F<sub>ref3_ck</sub> x PLL3N, when fractional value 0 has been loaded in PLL3FRACN, with: +PLL3N between 4 and 512 +input frequency F<sub>ref3_ck</sub> between 4 and 16MHz + 0 + 9 + read-write + + + B_0x003 + PLL3N = 4 + 0x003 + + + B_0x004 + PLL3N = 5 + 0x004 + + + B_0x005 + PLL3N = 6 + 0x005 + + + B_0x080 + PLL3N = 129 (default after reset) + 0x080 + + + B_0x1FF + PLL3N = 512 + 0x1FF + + + + + PLL3P + PLL3 DIVP division factor +This bitfield is set and reset by software to control the frequency of the pll3_p_ck clock. It can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0). +... + 9 + 7 + read-write + + + B_0x0 + pll3_p_ck = vco3_ck + 0x0 + + + B_0x1 + pll3_p_ck = vco3_ck / 2 (default after reset) + 0x1 + + + B_0x2 + pll3_p_ck = vco3_ck / 3 + 0x2 + + + B_0x3 + pll3_p_ck = vco3_ck / 4 + 0x3 + + + B_0x7F + pll3_p_ck = vco3_ck / 128 + 0x7F + + + + + PLL3Q + PLL3 DIVQ division factor +This bitfield is set and reset by software to control the frequency of the pll3_q_ck clock. It can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0). +... + 16 + 7 + read-write + + + B_0x0 + pll3_q_ck = vco3_ck + 0x0 + + + B_0x1 + pll3_q_ck = vco3_ck / 2 (default after reset) + 0x1 + + + B_0x2 + pll3_q_ck = vco3_ck / 3 + 0x2 + + + B_0x3 + pll3_q_ck = vco3_ck / 4 + 0x3 + + + B_0x7F + pll3_q_ck = vco3_ck / 128 + 0x7F + + + + + PLL3R + PLL3 DIVR division factor +This bitfield is set and reset by software to control the frequency of the pll3_r_ck clock. It can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0). +... + 24 + 7 + read-write + + + B_0x0 + pll3_r_ck = vco3_ck + 0x0 + + + B_0x1 + pll3_r_ck = vco3_ck / 2 (default after reset) + 0x1 + + + B_0x2 + pll3_r_ck = vco3_ck / 3 + 0x2 + + + B_0x3 + pll3_r_ck = vco3_ck / 4 + 0x3 + + + B_0x7F + pll3_r_ck = vco3_ck / 128 + 0x7F + + + + + + + RCC_PLL3FRACR + RCC_PLL3FRACR + RCC PLL3 fractional divider register + 0x048 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PLL3FRACN + Fractional part of the multiplication factor for PLL3 VCO +This bitfield is set and reset by software to control the fractional part of the VCO multiplication factor. It can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO. +VCO output frequency = F<sub>ref3_ck</sub> x (PLL3N + (PLL3FRACN / 2<sup>13</sup>)), with: +PLL3N must be between 4 and 512. +PLL3FRACN can be between 0 and 2<sup>13 </sup>- 1. +The input frequency F<sub>ref3_ck</sub> must be between 4 and 16 MHz. +In order to change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: +Set the bit PLL3FRACEN to 0. +Write the new fractional value into PLL3FRACN. +Set the bit PLL3FRACEN to 1. + 3 + 13 + read-write + + + + + RCC_CIER + RCC_CIER + RCC clock interrupt enable register + 0x050 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LSIRDYIE + LSI ready interrupt enable +This bit is set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization. + 0 + 1 + read-write + + + B_0x0 + LSI ready interrupt disabled + 0x0 + + + B_0x1 + LSI ready interrupt enabled + 0x1 + + + + + LSERDYIE + LSE ready interrupt enable +This bit is set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization. + 1 + 1 + read-write + + + B_0x0 + LSE ready interrupt disabled + 0x0 + + + B_0x1 + LSE ready interrupt enabled + 0x1 + + + + + MSISRDYIE + MSIS ready interrupt enable +This bit is set and cleared by software to enable/disable interrupt caused by the MSIS oscillator stabilization. + 2 + 1 + read-write + + + B_0x0 + MSIS ready interrupt disabled + 0x0 + + + B_0x1 + MSIS ready interrupt enabled + 0x1 + + + + + HSIRDYIE + HSI16 ready interrupt enable +This bit is set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization. + 3 + 1 + read-write + + + B_0x0 + HSI16 ready interrupt disabled + 0x0 + + + B_0x1 + HSI16 ready interrupt enabled + 0x1 + + + + + HSERDYIE + HSE ready interrupt enable +This bit is set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization. + 4 + 1 + read-write + + + B_0x0 + HSE ready interrupt disabled + 0x0 + + + B_0x1 + HSE ready interrupt enabled + 0x1 + + + + + HSI48RDYIE + HSI48 ready interrupt enable +This bit is set and cleared by software to enable/disable interrupt caused by the HSI48 oscillator stabilization. + 5 + 1 + read-write + + + B_0x0 + HSI48 ready interrupt disabled + 0x0 + + + B_0x1 + HSI48 ready interrupt enabled + 0x1 + + + + + PLL1RDYIE + PLL ready interrupt enable +This bit is set and cleared by software to enable/disable interrupt caused by PLL1 lock. + 6 + 1 + read-write + + + B_0x0 + PLL1 lock interrupt disabled + 0x0 + + + B_0x1 + PLL1 lock interrupt enabled + 0x1 + + + + + PLL2RDYIE + PLL2 ready interrupt enable +This bit is set and cleared by software to enable/disable interrupt caused by PLL2 lock. + 7 + 1 + read-write + + + B_0x0 + PLL2 lock interrupt disabled + 0x0 + + + B_0x1 + PLL2 lock interrupt enabled + 0x1 + + + + + PLL3RDYIE + PLL3 ready interrupt enable +This bit is set and cleared by software to enable/disable interrupt caused by PLL3 lock. + 8 + 1 + read-write + + + B_0x0 + PLL3 lock interrupt disabled + 0x0 + + + B_0x1 + PLL3 lock interrupt enabled + 0x1 + + + + + MSIKRDYIE + MSIK ready interrupt enable +This bit is set and cleared by software to enable/disable interrupt caused by the MSIK oscillator stabilization. + 11 + 1 + read-write + + + B_0x0 + MSIK ready interrupt disabled + 0x0 + + + B_0x1 + MSIK ready interrupt enabled + 0x1 + + + + + SHSIRDYIE + SHSI ready interrupt enable +This bit is set and cleared by software to enable/disable interrupt caused by the SHSI oscillator stabilization. + 12 + 1 + read-write + + + B_0x0 + SHSI ready interrupt disabled + 0x0 + + + B_0x1 + SHSI ready interrupt enabled + 0x1 + + + + + + + RCC_CIFR + RCC_CIFR + RCC clock interrupt flag register + 0x054 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LSIRDYF + LSI ready interrupt flag +This bit is set by hardware when the LSI clock becomes stable and LSIRDYIE is set. It is cleared by software by�setting the LSIRDYC bit. + 0 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by the LSI oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the LSI oscillator + 0x1 + + + + + LSERDYF + LSE ready interrupt flag +This bit is set by hardware when the LSE clock becomes stable and LSERDYIE is set. It is cleared by software by setting the LSERDYC bit. + 1 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by the LSE oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the LSE oscillator + 0x1 + + + + + MSISRDYF + MSIS ready interrupt flag +This bit is set by hardware when the MSIS clock becomes stable and MSISRDYIE is set. It�is cleared by software by setting the MSISRDYC bit. + 2 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by the MSIS oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the MSIS oscillator + 0x1 + + + + + HSIRDYF + HSI16 ready interrupt flag +This bit is set by hardware when the HSI16 clock becomes stable and HSIRDYIE = 1 in�response to setting the HSION (see RCC_CR). When HSION = 0 but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. This bit is cleared by software by setting the HSIRDYC bit. + 3 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by the HSI16 oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the HSI16 oscillator + 0x1 + + + + + HSERDYF + HSE ready interrupt flag +This bit is set by hardware when the HSE clock becomes stable and HSERDYIE is set. It is cleared by software by setting the HSERDYC bit. + 4 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by the HSE oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the HSE oscillator + 0x1 + + + + + HSI48RDYF + HSI48 ready interrupt flag +This bit is set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set. it�is cleared by software by setting the HSI48RDYC bit. + 5 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by the HSI48 oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the HSI48 oscillator + 0x1 + + + + + PLL1RDYF + PLL1 ready interrupt flag +This bit is set by hardware when the PLL1 locks and PLL1RDYIE is set. It is cleared by software by setting the PLL1RDYC bit. + 6 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by PLL1 lock + 0x0 + + + B_0x1 + Clock ready interrupt caused by PLL1 lock + 0x1 + + + + + PLL2RDYF + PLL2 ready interrupt flag +This bit is set by hardware when the PLL2 locks and PLL2RDYIE is set. It is cleared by software by setting the PLL2RDYC bit. + 7 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by PLL2 lock + 0x0 + + + B_0x1 + Clock ready interrupt caused by PLL2 lock + 0x1 + + + + + PLL3RDYF + PLL3 ready interrupt flag +This bit is set by hardware when the PLL3 locks and PLL3RDYIE is set. It is cleared by software by setting the PLL3RDYC bit. + 8 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by PLL3 lock + 0x0 + + + B_0x1 + Clock ready interrupt caused by PLL3 lock + 0x1 + + + + + CSSF + Clock security system interrupt flag +This bit is set by hardware when a failure is detected in the HSE oscillator. It is cleared by software by setting the CSSC bit. + 10 + 1 + read-only + + + B_0x0 + No clock security interrupt caused by HSE clock failure + 0x0 + + + B_0x1 + Clock security interrupt caused by HSE clock failure + 0x1 + + + + + MSIKRDYF + MSIK ready interrupt flag +This bit is set by hardware when the MSIK clock becomes stable and MSIKRDYIE is set. It is cleared by software by setting the MSIKRDYC bit. + 11 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by the MSIK oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the MSIK oscillator + 0x1 + + + + + SHSIRDYF + SHSI ready interrupt flag +This bit is set by hardware when the SHSI clock becomes stable and SHSIRDYIE is set. It is cleared by software by setting the SHSIRDYC bit. + 12 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by the SHSI oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the SHSI oscillator + 0x1 + + + + + + + RCC_CICR + RCC_CICR + RCC clock interrupt clear register + 0x058 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LSIRDYC + LSI ready interrupt clear +Writing this bit to 1 clears the LSIRDYF flag. Writing 0 has no effect. + 0 + 1 + write-only + + + LSERDYC + LSE ready interrupt clear +Writing this bit to 1 clears the LSERDYF flag. Writing 0 has no effect. + 1 + 1 + write-only + + + MSISRDYC + MSIS ready interrupt clear +Writing this bit to 1 clears the MSISRDYF flag. Writing 0 has no effect. + 2 + 1 + write-only + + + HSIRDYC + HSI16 ready interrupt clear +Writing this bit to 1 clears the HSIRDYF flag. Writing 0 has no effect. + 3 + 1 + write-only + + + HSERDYC + HSE ready interrupt clear +Writing this bit to 1 clears the HSERDYF flag. Writing 0 has no effect. + 4 + 1 + write-only + + + HSI48RDYC + HSI48 ready interrupt clear +Writing this bit to 1 clears the HSI48RDYF flag. Writing 0 has no effect. + 5 + 1 + write-only + + + PLL1RDYC + PLL1 ready interrupt clear +Writing this bit to 1 clears the PLL1RDYF flag. Writing 0 has no effect. + 6 + 1 + write-only + + + PLL2RDYC + PLL2 ready interrupt clear +Writing this bit to 1 clears the PLL2RDYF flag. Writing 0 has no effect. + 7 + 1 + write-only + + + PLL3RDYC + PLL3 ready interrupt clear +Writing this bit to 1 clears the PLL3RDYF flag. Writing 0 has no effect. + 8 + 1 + write-only + + + CSSC + Clock security system interrupt clear +Writing this bit to 1 clears the CSSF flag. Writing 0 has no effect. + 10 + 1 + write-only + + + MSIKRDYC + MSIK oscillator ready interrupt clear +Writing this bit to 1 clears the MSIKRDYF flag. Writing 0 has no effect. + 11 + 1 + write-only + + + SHSIRDYC + SHSI oscillator ready interrupt clear +Writing this bit to 1 clears the SHSIRDYF flag. Writing 0 has no effect. + 12 + 1 + write-only + + + + + RCC_AHB1RSTR + RCC_AHB1RSTR + RCC AHB1 peripheral reset register + 0x060 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + GPDMA1RST + GPDMA1 reset +This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the GPDMA1. + 0x1 + + + + + CORDICRST + CORDIC reset +This bit is set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the CORDIC. + 0x1 + + + + + FMACRST + FMAC reset +This bit is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the FMAC. + 0x1 + + + + + MDF1RST + MDF1 reset +This bit is set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the MDF1. + 0x1 + + + + + CRCRST + CRC reset +This bit is set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the CRC. + 0x1 + + + + + JPEGRST + JPEG reset +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 15 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the JPEG. + 0x1 + + + + + TSCRST + TSC reset +This bit is set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the TSC. + 0x1 + + + + + RAMCFGRST + RAMCFG reset +This bit is set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the RAMCFG. + 0x1 + + + + + DMA2DRST + DMA2D reset +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 18 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the DMA2D. + 0x1 + + + + + GFXMMURST + GFXMMU reset +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 19 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the GFXMMU. + 0x1 + + + + + GPU2DRST + GPU2D reset +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 20 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the GPU2D. + 0x1 + + + + + + + RCC_AHB2RSTR1 + RCC_AHB2RSTR1 + RCC AHB2 peripheral reset register 1 + 0x064 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + GPIOARST + I/O port A reset +This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the I/O port A. + 0x1 + + + + + GPIOBRST + I/O port B reset +This bit is set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the I/O port B. + 0x1 + + + + + GPIOCRST + I/O port C reset +This bit is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the I/O port C. + 0x1 + + + + + GPIODRST + I/O port D reset +This bit is set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the I/O port D. + 0x1 + + + + + GPIOERST + I/O port E reset +This bit is set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the I/O port E. + 0x1 + + + + + GPIOFRST + I/O port F reset +This bit is set and cleared by software. +This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. +Note: If not present, consider this bit as reserved and keep it at reset value. + 5 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset I/O port F + 0x1 + + + + + GPIOGRST + I/O port G reset +This bit is set and cleared by software. + 6 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the I/O port G. + 0x1 + + + + + GPIOHRST + I/O port H reset +This bit is set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the I/O port H. + 0x1 + + + + + GPIOIRST + I/O port I reset +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 8 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the I/O port .I + 0x1 + + + + + GPIOJRST + I/O port J reset +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 9 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the I/O port J. + 0x1 + + + + + ADC12RST + ADC1 and ADC2 reset +This bit is set and cleared by software. +Note: This bit impacts ADC1 in STM32U535/545/575/585, and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx. + 10 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the ADC1 and ADC2. + 0x1 + + + + + DCMI_PSSIRST + DCMI and PSSI reset +This bit is set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the DCMI and PSSI. + 0x1 + + + + + OTGRST + OTG_FS or OTG_HS reset +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 14 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the OTG_FS or OTG_HS. + 0x1 + + + + + AESRST + AES hardware accelerator reset +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 16 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the AES. + 0x1 + + + + + HASHRST + HASH reset +This bit is set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the HASH. + 0x1 + + + + + RNGRST + RNG reset +This bit is set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the RNG. + 0x1 + + + + + PKARST + PKA reset +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 19 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the PKA. + 0x1 + + + + + SAESRST + SAES hardware accelerator reset +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 20 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the SAES. + 0x1 + + + + + OCTOSPIMRST + OCTOSPIM reset +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 21 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the OCTOSPIM. + 0x1 + + + + + OTFDEC1RST + OTFDEC1 reset +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 23 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the OTFDEC1. + 0x1 + + + + + OTFDEC2RST + OTFDEC2 reset +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 24 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the OTFDEC2. + 0x1 + + + + + SDMMC1RST + SDMMC1 reset +This bit is set and cleared by software. + 27 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the SDMMC1. + 0x1 + + + + + SDMMC2RST + SDMMC2 reset +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 28 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the SDMMC2. + 0x1 + + + + + + + RCC_AHB2RSTR2 + RCC_AHB2RSTR2 + RCC AHB2 peripheral reset register 2 + 0x068 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FSMCRST + Flexible memory controller reset +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the FSMC + 0x1 + + + + + OCTOSPI1RST + OCTOSPI1 reset +This bit is set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the OCTOSPI1. + 0x1 + + + + + OCTOSPI2RST + OCTOSPI2 reset +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 8 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the OCTOSPI2. + 0x1 + + + + + HSPI1RST + HSPI1 reset +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 12 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the HSPI1. + 0x1 + + + + + + + RCC_AHB3RSTR + RCC_AHB3RSTR + RCC AHB3 peripheral reset register + 0x06C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LPGPIO1RST + LPGPIO1 reset +This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the LPGPIO1. + 0x1 + + + + + ADC4RST + ADC4 reset +This bit is set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the ADC4 interface. + 0x1 + + + + + DAC1RST + DAC1 reset +This bit is set and cleared by software. + 6 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the DAC1. + 0x1 + + + + + LPDMA1RST + LPDMA1 reset +This bit is set and cleared by software. + 9 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the LPDMA1. + 0x1 + + + + + ADF1RST + ADF1 reset +This bit is set and cleared by software. + 10 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the ADF1. + 0x1 + + + + + + + RCC_APB1RSTR1 + RCC_APB1RSTR1 + RCC APB1 peripheral reset register 1 + 0x074 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIM2RST + TIM2 reset +This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the TIM2. + 0x1 + + + + + TIM3RST + TIM3 reset +This bit is set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the TIM3. + 0x1 + + + + + TIM4RST + TIM4 reset +This bit is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the TIM4. + 0x1 + + + + + TIM5RST + TIM5 reset +This bit is set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the TIM5. + 0x1 + + + + + TIM6RST + TIM6 reset +This bit is set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the TIM6. + 0x1 + + + + + TIM7RST + TIM7 reset +This bit is set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the TIM7. + 0x1 + + + + + SPI2RST + SPI2 reset +This bit is set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the SPI2. + 0x1 + + + + + USART2RST + USART2 reset +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series.Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 17 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the USART2 + 0x1 + + + + + USART3RST + USART3 reset +This bit is set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the USART3. + 0x1 + + + + + UART4RST + UART4 reset +This bit is set and cleared by software. + 19 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the UART4. + 0x1 + + + + + UART5RST + UART5 reset +This bit is set and cleared by software. + 20 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the UART5. + 0x1 + + + + + I2C1RST + I2C1 reset +This bit is set and cleared by software. + 21 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the I2C1. + 0x1 + + + + + I2C2RST + I2C2 reset +This bit is set and cleared by software. + 22 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the I2C2. + 0x1 + + + + + CRSRST + CRS reset +This bit is set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the CRS. + 0x1 + + + + + USART6RST + USART6 reset +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 25 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the USART6. + 0x1 + + + + + + + RCC_APB1RSTR2 + RCC_APB1RSTR2 + RCC APB1 peripheral reset register 2 + 0x078 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + I2C4RST + I2C4 reset +This bit is set and cleared by software + 1 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the I2C4. + 0x1 + + + + + LPTIM2RST + LPTIM2 reset +This bit is set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the LPTIM2. + 0x1 + + + + + I2C5RST + I2C5 reset +This bit is set and cleared by software +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 6 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the I2C5. + 0x1 + + + + + I2C6RST + I2C6 reset +This bit is set and cleared by software +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 7 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the I2C6. + 0x1 + + + + + FDCAN1RST + FDCAN1 reset +This bit is set and cleared by software. + 9 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the FDCAN1. + 0x1 + + + + + UCPD1RST + UCPD1 reset +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 23 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the UCPD1. + 0x1 + + + + + + + RCC_APB2RSTR + RCC_APB2RSTR + RCC APB2 peripheral reset register + 0x07C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIM1RST + TIM1 reset +This bit is set and cleared by software. + 11 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the TIM1. + 0x1 + + + + + SPI1RST + SPI1 reset +This bit is set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the SPI1. + 0x1 + + + + + TIM8RST + TIM8 reset +This bit is set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the TIM8. + 0x1 + + + + + USART1RST + USART1 reset +This bit is set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the USART1. + 0x1 + + + + + TIM15RST + TIM15 reset +This bit is set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the TIM15. + 0x1 + + + + + TIM16RST + TIM16 reset +This bit is set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the TIM16. + 0x1 + + + + + TIM17RST + TIM17 reset +This bit is set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the TIM17. + 0x1 + + + + + SAI1RST + SAI1 reset +This bit is set and cleared by software. + 21 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the SAI1. + 0x1 + + + + + SAI2RST + SAI2 reset +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 22 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the SAI2. + 0x1 + + + + + USBRST + USB reset +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 24 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the USB. + 0x1 + + + + + GFXTIMRST + GFXTIM reset +This bit is set and cleared by software. +Note: .This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 25 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the GFXTIM. + 0x1 + + + + + LTDCRST + LTDC reset +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 26 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the LTDC. + 0x1 + + + + + DSIRST + DSI reset +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 27 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the DSI. + 0x1 + + + + + + + RCC_APB3RSTR + RCC_APB3RSTR + RCC APB3 peripheral reset register + 0x080 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SYSCFGRST + SYSCFG reset +This bit is set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the SYSCFG. + 0x1 + + + + + SPI3RST + SPI3 reset +This bit is set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the SPI3. + 0x1 + + + + + LPUART1RST + LPUART1 reset +This bit is set and cleared by software. + 6 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the LPUART1. + 0x1 + + + + + I2C3RST + I2C3 reset +This bit is set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the I2C3. + 0x1 + + + + + LPTIM1RST + LPTIM1 reset +This bit is set and cleared by software. + 11 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the LPTIM1. + 0x1 + + + + + LPTIM3RST + LPTIM3 reset +This bit is set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the LPTIM3. + 0x1 + + + + + LPTIM4RST + LPTIM4 reset +This bit is set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the LPTIM4. + 0x1 + + + + + OPAMPRST + OPAMP reset +This bit is set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the OPAMP. + 0x1 + + + + + COMPRST + COMP reset +This bit is set and cleared by software. + 15 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the COMP. + 0x1 + + + + + VREFRST + VREFBUF reset +This bit is set and cleared by software. + 20 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the VREFBUF. + 0x1 + + + + + + + RCC_AHB1ENR + RCC_AHB1ENR + RCC AHB1 peripheral clock enable register + 0x088 + 0x20 + 0xD0200100 + 0xFFFFFFFF + + + GPDMA1EN + GPDMA1 clock enable +This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + GPDMA1 clock disabled + 0x0 + + + B_0x1 + GPDMA1 clock enabled + 0x1 + + + + + CORDICEN + CORDIC clock enable +This bit is set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + CORDIC clock disabled + 0x0 + + + B_0x1 + CORDIC clock enabled + 0x1 + + + + + FMACEN + FMAC clock enable +This bit is set and reset by software. + 2 + 1 + read-write + + + B_0x0 + FMAC clock disabled + 0x0 + + + B_0x1 + FMAC clock enabled + 0x1 + + + + + MDF1EN + MDF1 clock enable +This bit is set and reset by software. + 3 + 1 + read-write + + + B_0x0 + MDF1 clock disabled + 0x0 + + + B_0x1 + MDF1 clock enabled + 0x1 + + + + + FLASHEN + FLASH clock enable +This bit is set and cleared by software. This bit can be disabled only when the flash memory is in power-down mode. + 8 + 1 + read-write + + + B_0x0 + FLASH clock disabled + 0x0 + + + B_0x1 + FLASH clock enabled + 0x1 + + + + + CRCEN + CRC clock enable +This bit is set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + CRC clock disabled + 0x0 + + + B_0x1 + CRC clock enabled + 0x1 + + + + + JPEGEN + JPEG clock enable +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 15 + 1 + read-write + + + B_0x0 + JPEG clock disabled + 0x0 + + + B_0x1 + JPEG clock enabled + 0x1 + + + + + TSCEN + Touch sensing controller clock enable +This bit is set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + TSC clock disabled + 0x0 + + + B_0x1 + TSC clock enabled + 0x1 + + + + + RAMCFGEN + RAMCFG clock enable +This bit is set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + RAMCFG clock disabled + 0x0 + + + B_0x1 + RAMCFG clock enabled + 0x1 + + + + + DMA2DEN + DMA2D clock enable +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 18 + 1 + read-write + + + B_0x0 + DMA2D clock disabled + 0x0 + + + B_0x1 + DMA2D clock enabled + 0x1 + + + + + GFXMMUEN + GFXMMU clock enable +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 19 + 1 + read-write + + + B_0x0 + GFXMMU clock disabled + 0x0 + + + B_0x1 + GFXMMU clock enabled + 0x1 + + + + + GPU2DEN + GPU2D clock enable +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 20 + 1 + read-write + + + B_0x0 + GPU2D clock disabled + 0x0 + + + B_0x1 + GPU2D clock enabled + 0x1 + + + + + DCACHE2EN + DCACHE2 clock enable +This bit is set and reset by software. +Note: DCACHE2 clock must be enabled to access memories, even if the DCACHE2 is bypassed. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 21 + 1 + read-write + + + B_0x0 + DCACHE2 clock disabled + 0x0 + + + B_0x1 + DCACHE2 clock enabled + 0x1 + + + + + GTZC1EN + GTZC1 clock enable +This bit is set and reset by software. + 24 + 1 + read-write + + + B_0x0 + GTZC1 clock disabled + 0x0 + + + B_0x1 + GTZC1 clock enabled + 0x1 + + + + + BKPSRAMEN + BKPSRAM clock enable +This bit is set and reset by software. + 28 + 1 + read-write + + + B_0x0 + BKPSRAM clock disabled + 0x0 + + + B_0x1 + BKPSRAM clock enabled + 0x1 + + + + + DCACHE1EN + DCACHE1 clock enable +This bit is set and reset by software. +Note: DCACHE1 clock must be enabled when external memories are accessed through OCTOSPI1, OCTOSPI2, HSPI1 or FSMC, even if the DCACHE1 is bypassed. + 30 + 1 + read-write + + + B_0x0 + DCACHE1 clock disabled + 0x0 + + + B_0x1 + DCACHE1 clock enabled + 0x1 + + + + + SRAM1EN + SRAM1 clock enable +This bit is set and reset by software. + 31 + 1 + read-write + + + B_0x0 + SRAM1 clock disabled + 0x0 + + + B_0x1 + SRAM1 clock enabled + 0x1 + + + + + + + RCC_AHB2ENR1 + RCC_AHB2ENR1 + RCC AHB2 peripheral clock enable register 1 + 0x08C + 0x20 + 0xC0000000 + 0xFFFFFFFF + + + GPIOAEN + I/O port A clock enable +This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + I/O port A clock disabled + 0x0 + + + B_0x1 + I/O port A clock enabled + 0x1 + + + + + GPIOBEN + I/O port B clock enable +This bit is set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + I/O port B clock disabled + 0x0 + + + B_0x1 + I/O port B clock enabled + 0x1 + + + + + GPIOCEN + I/O port C clock enable +This bit is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + I/O port C clock disabled + 0x0 + + + B_0x1 + I/O port C clock enabled + 0x1 + + + + + GPIODEN + I/O port D clock enable +This bit is set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + I/O port D clock disabled + 0x0 + + + B_0x1 + I/O port D clock enabled + 0x1 + + + + + GPIOEEN + I/O port E clock enable +This bit is set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + I/O port E clock disabled + 0x0 + + + B_0x1 + I/O port E clock enabled + 0x1 + + + + + GPIOFEN + I/O port F clock enable +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 5 + 1 + read-write + + + B_0x0 + I/O port F clock disabled + 0x0 + + + B_0x1 + I/O port F clock enabled + 0x1 + + + + + GPIOGEN + I/O port G clock enable +This bit is set and cleared by software. + 6 + 1 + read-write + + + B_0x0 + I/O port G clock disabled + 0x0 + + + B_0x1 + I/O port G clock enabled + 0x1 + + + + + GPIOHEN + I/O port H clock enable +This bit is set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + I/O port H clock disabled + 0x0 + + + B_0x1 + I/O port H clock enabled + 0x1 + + + + + GPIOIEN + I/O port I clock enable +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 8 + 1 + read-write + + + B_0x0 + I/O port I clock disabled + 0x0 + + + B_0x1 + I/O port I clock enabled + 0x1 + + + + + GPIOJEN + I/O port J clock enable +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 9 + 1 + read-write + + + B_0x0 + I/O port J clock disabled + 0x0 + + + B_0x1 + I/O port J clock enabled + 0x1 + + + + + ADC12EN + ADC1 and ADC2 clock enable +This bit is set and cleared by software. +Note: This bit impacts ADC1 in STM32U535/545/575/585, and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx. + 10 + 1 + read-write + + + B_0x0 + ADC1 and ADC2 clock disabled + 0x0 + + + B_0x1 + ADC1 and ADC2 clock enabled + 0x1 + + + + + DCMI_PSSIEN + DCMI and PSSI clock enable +This bit is set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + DCMI and PSSI clock disabled + 0x0 + + + B_0x1 + DCMI and PSSI clock enabled + 0x1 + + + + + OTGEN + OTG_FS or OTG_HS clock enable +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 14 + 1 + read-write + + + B_0x0 + OTG_FS or OTG_HS clock disabled + 0x0 + + + B_0x1 + OTG_FS or OTG_HS clock enabled + 0x1 + + + + + OTGHSPHYEN + OTG_HS PHY clock enable +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 15 + 1 + read-write + + + B_0x0 + OTG_HS PHY clock disabled + 0x0 + + + B_0x1 + OTG_HS PHY clock enabled + 0x1 + + + + + AESEN + AES clock enable +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 16 + 1 + read-write + + + B_0x0 + AES clock disabled + 0x0 + + + B_0x1 + AES clock enabled + 0x1 + + + + + HASHEN + HASH clock enable +This bit is set and cleared by software + 17 + 1 + read-write + + + B_0x0 + HASH clock disabled + 0x0 + + + B_0x1 + HASH clock enabled + 0x1 + + + + + RNGEN + RNG clock enable +This bit is set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + RNG clock disabled + 0x0 + + + B_0x1 + RNG clock enabled + 0x1 + + + + + PKAEN + PKA clock enable +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 19 + 1 + read-write + + + B_0x0 + PKA clock disabled + 0x0 + + + B_0x1 + PKA clock enabled + 0x1 + + + + + SAESEN + SAES clock enable +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 20 + 1 + read-write + + + B_0x0 + SAES clock disabled + 0x0 + + + B_0x1 + SAES clock enabled + 0x1 + + + + + OCTOSPIMEN + OCTOSPIM clock enable +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 21 + 1 + read-write + + + B_0x0 + OCTOSPIM clock disabled + 0x0 + + + B_0x1 + OCTOSPIM clock enabled + 0x1 + + + + + OTFDEC1EN + OTFDEC1 clock enable +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 23 + 1 + read-write + + + B_0x0 + OTFDEC1 clock disabled + 0x0 + + + B_0x1 + OTFDEC1 clock enabled + 0x1 + + + + + OTFDEC2EN + OTFDEC2 clock enable +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 24 + 1 + read-write + + + B_0x0 + OTFDEC2 clock disabled + 0x0 + + + B_0x1 + OTFDEC2 clock enabled + 0x1 + + + + + SDMMC1EN + SDMMC1 clock enable +This bit is set and cleared by software. + 27 + 1 + read-write + + + B_0x0 + SDMMC1 clock disabled + 0x0 + + + B_0x1 + SDMMC1 clock enabled + 0x1 + + + + + SDMMC2EN + SDMMC2 clock enable +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 28 + 1 + read-write + + + B_0x0 + SDMMC2 clock disabled + 0x0 + + + B_0x1 + SDMMC2 clock enabled + 0x1 + + + + + SRAM2EN + SRAM2 clock enable +This bit is set and reset by software. + 30 + 1 + read-write + + + B_0x0 + SRAM2 clock disabled + 0x0 + + + B_0x1 + SRAM2 clock enabled + 0x1 + + + + + SRAM3EN + SRAM3 clock enable +This bit is set and reset by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 31 + 1 + read-write + + + B_0x0 + SRAM3 clock disabled + 0x0 + + + B_0x1 + SRAM3 clock enabled + 0x1 + + + + + + + RCC_AHB2ENR2 + RCC_AHB2ENR2 + RCC AHB2 peripheral clock enable register 2 + 0x090 + 0x20 + 0x80000000 + 0xFFFFFFFF + + + FSMCEN + FSMC clock enable +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 0 + 1 + read-write + + + B_0x0 + FSMC clock disabled + 0x0 + + + B_0x1 + FSMC clock enabled + 0x1 + + + + + OCTOSPI1EN + OCTOSPI1 clock enable +This bit is set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + OCTOSPI1 clock disabled + 0x0 + + + B_0x1 + OCTOSPI1 clock enabled + 0x1 + + + + + OCTOSPI2EN + OCTOSPI2 clock enable +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 8 + 1 + read-write + + + B_0x0 + OCTOSPI2 clock disabled + 0x0 + + + B_0x1 + OCTOSPI2 clock enabled + 0x1 + + + + + HSPI1EN + HSPI1 clock enable +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 12 + 1 + read-write + + + B_0x0 + HSPI1 clock disabled + 0x0 + + + B_0x1 + HSPI1 clock enabled + 0x1 + + + + + SRAM6EN + SRAM6 clock enable +This bit is set and reset by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 30 + 1 + read-write + + + B_0x0 + SRAM6 clock disabled + 0x0 + + + B_0x1 + SRAM6 clock enabled + 0x1 + + + + + SRAM5EN + SRAM5 clock enable +This bit is set and reset by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 31 + 1 + read-write + + + B_0x0 + SRAM5 clock disabled + 0x0 + + + B_0x1 + SRAM5 clock enabled + 0x1 + + + + + + + RCC_AHB3ENR + RCC_AHB3ENR + RCC AHB3 peripheral clock enable register + 0x094 + 0x20 + 0x80000000 + 0xFFFFFFFF + + + LPGPIO1EN + LPGPIO1 enable +This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + LPGPIO1 clock disabled + 0x0 + + + B_0x1 + LPGPIO1 clock enabled + 0x1 + + + + + PWREN + PWR clock enable +This bit is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + PWR clock disabled + 0x0 + + + B_0x1 + PWR clock enabled + 0x1 + + + + + ADC4EN + ADC4 clock enable +This bit is set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + ADC4 clock disabled + 0x0 + + + B_0x1 + ADC4 clock enabled + 0x1 + + + + + DAC1EN + DAC1 clock enable +This bit is set and cleared by software. + 6 + 1 + read-write + + + B_0x0 + DAC1 clock disabled + 0x0 + + + B_0x1 + DAC1 clock enabled + 0x1 + + + + + LPDMA1EN + LPDMA1 clock enable +This bit is set and cleared by software. + 9 + 1 + read-write + + + B_0x0 + LPDMA1 clock disabled + 0x0 + + + B_0x1 + LPDMA1 clock enabled + 0x1 + + + + + ADF1EN + ADF1 clock enable +This bit is set and cleared by software. + 10 + 1 + read-write + + + B_0x0 + ADF1 clock disabled + 0x0 + + + B_0x1 + ADF1 clock enabled + 0x1 + + + + + GTZC2EN + GTZC2 clock enable +This bit is set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + GTZC2 clock disabled + 0x0 + + + B_0x1 + GTZC2 clock enabled + 0x1 + + + + + SRAM4EN + SRAM4 clock enable +This bit is set and reset by software. + 31 + 1 + read-write + + + B_0x0 + SRAM4 clock disabled + 0x0 + + + B_0x1 + SRAM4 clock enabled + 0x1 + + + + + + + RCC_APB1ENR1 + RCC_APB1ENR1 + RCC APB1 peripheral clock enable register 1 + 0x09C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIM2EN + TIM2 clock enable +This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + TIM2 clock disabled + 0x0 + + + B_0x1 + TIM2 clock enabled + 0x1 + + + + + TIM3EN + TIM3 clock enable +This bit is set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + TIM3 clock disabled + 0x0 + + + B_0x1 + TIM3 clock enabled + 0x1 + + + + + TIM4EN + TIM4 clock enable +This bit is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + TIM4 clock disabled + 0x0 + + + B_0x1 + TIM4 clock enabled + 0x1 + + + + + TIM5EN + TIM5 clock enable +This bit is set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + TIM5 clock disabled + 0x0 + + + B_0x1 + TIM5 clock enabled + 0x1 + + + + + TIM6EN + TIM6 clock enable +This bit is set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + TIM6 clock disabled + 0x0 + + + B_0x1 + TIM6 clock enabled + 0x1 + + + + + TIM7EN + TIM7 clock enable +This bit is set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + TIM7 clock disabled + 0x0 + + + B_0x1 + TIM7 clock enabled + 0x1 + + + + + WWDGEN + WWDG clock enable +This bit is set by software to enable the window watchdog clock. It is reset by hardware system reset. This bit can also be set by hardware if the WWDG_SW option bit is reset. + 11 + 1 + read-write + + + B_0x0 + WWDG clock disabled + 0x0 + + + B_0x1 + WWDG clock enabled + 0x1 + + + + + SPI2EN + SPI2 clock enable +This bit is set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + SPI2 clock disabled + 0x0 + + + B_0x1 + SPI2 clock enabled + 0x1 + + + + + USART2EN + USART2 clock enable +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 17 + 1 + read-write + + + B_0x0 + USART2 clock disabled + 0x0 + + + B_0x1 + USART2 clock enabled + 0x1 + + + + + USART3EN + USART3 clock enable +This bit is set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + USART3 clock disabled + 0x0 + + + B_0x1 + USART3 clock enabled + 0x1 + + + + + UART4EN + UART4 clock enable +This bit is set and cleared by software. + 19 + 1 + read-write + + + B_0x0 + UART4 clock disabled + 0x0 + + + B_0x1 + UART4 clock enabled + 0x1 + + + + + UART5EN + UART5 clock enable +This bit is set and cleared by software. + 20 + 1 + read-write + + + B_0x0 + UART5 clock disabled + 0x0 + + + B_0x1 + UART5 clock enabled + 0x1 + + + + + I2C1EN + I2C1 clock enable +This bit is set and cleared by software. + 21 + 1 + read-write + + + B_0x0 + I2C1 clock disabled + 0x0 + + + B_0x1 + I2C1 clock enabled + 0x1 + + + + + I2C2EN + I2C2 clock enable +This bit is set and cleared by software. + 22 + 1 + read-write + + + B_0x0 + I2C2 clock disabled + 0x0 + + + B_0x1 + I2C2 clock enabled + 0x1 + + + + + CRSEN + CRS clock enable +This bit is set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + CRS clock disabled + 0x0 + + + B_0x1 + CRS clock enabled + 0x1 + + + + + USART6EN + USART6 clock enable +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 25 + 1 + read-write + + + B_0x0 + USART6 clock disabled + 0x0 + + + B_0x1 + USART6 clock enabled + 0x1 + + + + + + + RCC_APB1ENR2 + RCC_APB1ENR2 + RCC APB1 peripheral clock enable register 2 + 0x0A0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + I2C4EN + I2C4 clock enable +This bit is set and cleared by software + 1 + 1 + read-write + + + B_0x0 + I2C4 clock disabled + 0x0 + + + B_0x1 + I2C4 clock enabled + 0x1 + + + + + LPTIM2EN + LPTIM2 clock enable +This bit is set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + LPTIM2 clock disabled + 0x0 + + + B_0x1 + LPTIM2 clock enabled + 0x1 + + + + + I2C5EN + I2C5 clock enable +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 6 + 1 + read-write + + + B_0x0 + I2C5 clock disabled + 0x0 + + + B_0x1 + I2C5 clock enabled + 0x1 + + + + + I2C6EN + I2C6 clock enable +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 7 + 1 + read-write + + + B_0x0 + I2C6 clock disabled + 0x0 + + + B_0x1 + I2C6 clock enabled + 0x1 + + + + + FDCAN1EN + FDCAN1 clock enable +This bit is set and cleared by software. + 9 + 1 + read-write + + + B_0x0 + FDCAN1 clock disabled + 0x0 + + + B_0x1 + FDCAN1 clock enabled + 0x1 + + + + + UCPD1EN + UCPD1 clock enable +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 23 + 1 + read-write + + + B_0x0 + UCPD1 clock disabled + 0x0 + + + B_0x1 + UCPD1 clock enabled + 0x1 + + + + + + + RCC_APB2ENR + RCC_APB2ENR + RCC APB2 peripheral clock enable register + 0x0A4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIM1EN + TIM1 clock enable +This bit is set and cleared by software. + 11 + 1 + read-write + + + B_0x0 + TIM1 clock disabled + 0x0 + + + B_0x1 + TIM1 clock enabled + 0x1 + + + + + SPI1EN + SPI1 clock enable +This bit is set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + SPI1 clock disabled + 0x0 + + + B_0x1 + SPI1 clock enabled + 0x1 + + + + + TIM8EN + TIM8 clock enable +This bit is set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + TIM8 clock disabled + 0x0 + + + B_0x1 + TIM8 clock enabled + 0x1 + + + + + USART1EN + USART1clock enable +This bit is set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + USART1 clock disabled + 0x0 + + + B_0x1 + USART1 clock enabled + 0x1 + + + + + TIM15EN + TIM15 clock enable +This bit is set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + TIM15 clock disabled + 0x0 + + + B_0x1 + TIM15 clock enabled + 0x1 + + + + + TIM16EN + TIM16 clock enable +This bit is set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + TIM16 clock disabled + 0x0 + + + B_0x1 + TIM16 clock enabled + 0x1 + + + + + TIM17EN + TIM17 clock enable +This bit is set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + TIM17 clock disabled + 0x0 + + + B_0x1 + TIM17 clock enabled + 0x1 + + + + + SAI1EN + SAI1 clock enable +This bit is set and cleared by software. + 21 + 1 + read-write + + + B_0x0 + SAI1 clock disabled + 0x0 + + + B_0x1 + SAI1 clock enabled + 0x1 + + + + + SAI2EN + SAI2 clock enable +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 22 + 1 + read-write + + + B_0x0 + SAI2 clock disabled + 0x0 + + + B_0x1 + SAI2 clock enabled + 0x1 + + + + + USBEN + USB clock enable +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 24 + 1 + read-write + + + B_0x0 + USB clock disabled + 0x0 + + + B_0x1 + USB clock enabled + 0x1 + + + + + GFXTIMEN + GFXTIM clock enable +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 25 + 1 + read-write + + + B_0x0 + GFXTIM clock disabled + 0x0 + + + B_0x1 + GFXTIM clock enabled + 0x1 + + + + + LTDCEN + LTDC clock enable +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 26 + 1 + read-write + + + B_0x0 + LTDC clock disabled + 0x0 + + + B_0x1 + LTDC clock enabled + 0x1 + + + + + DSIEN + DSI clock enable +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 27 + 1 + read-write + + + B_0x0 + DSI clock disabled + 0x0 + + + B_0x1 + DSI clock enabled + 0x1 + + + + + + + RCC_APB3ENR + RCC_APB3ENR + RCC APB3 peripheral clock enable register + 0x0A8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SYSCFGEN + SYSCFG clock enable +This bit is set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + SYSCFG clock disabled + 0x0 + + + B_0x1 + SYSCFG clock enabled + 0x1 + + + + + SPI3EN + SPI3 clock enable +This bit is set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + SPI3 clock disabled + 0x0 + + + B_0x1 + SPI3 clock enabled + 0x1 + + + + + LPUART1EN + LPUART1 clock enable +This bit is set and cleared by software. + 6 + 1 + read-write + + + B_0x0 + LPUART1 clock disabled + 0x0 + + + B_0x1 + LPUART1 clock enabled + 0x1 + + + + + I2C3EN + I2C3 clock enable +This bit is set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + I2C3 clock disabled + 0x0 + + + B_0x1 + I2C3 clock enabled + 0x1 + + + + + LPTIM1EN + LPTIM1 clock enable +This bit is set and cleared by software. + 11 + 1 + read-write + + + B_0x0 + LPTIM1 clock disabled + 0x0 + + + B_0x1 + LPTIM1 clock enabled + 0x1 + + + + + LPTIM3EN + LPTIM3 clock enable +This bit is set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + LPTIM3 clock disabled + 0x0 + + + B_0x1 + LPTIM3 clock enabled + 0x1 + + + + + LPTIM4EN + LPTIM4 clock enable +This bit is set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + LPTIM4 clock disabled + 0x0 + + + B_0x1 + LPTIM4 clock enabled + 0x1 + + + + + OPAMPEN + OPAMP clock enable +This bit is set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + OPAMP clock disabled + 0x0 + + + B_0x1 + OPAMP clock enabled + 0x1 + + + + + COMPEN + COMP clock enable +This bit is set and cleared by software. + 15 + 1 + read-write + + + B_0x0 + COMP clock disabled + 0x0 + + + B_0x1 + COMP clock enabled + 0x1 + + + + + VREFEN + VREFBUF clock enable +This bit is set and cleared by software. + 20 + 1 + read-write + + + B_0x0 + VREFBUF clock disabled + 0x0 + + + B_0x1 + VREFBUF clock enabled + 0x1 + + + + + RTCAPBEN + RTC and TAMP APB clock enable +This bit is set and cleared by software. + 21 + 1 + read-write + + + B_0x0 + RTC and TAMP APB clock disabled + 0x0 + + + B_0x1 + RTC and TAMP APB clock enabled + 0x1 + + + + + + + RCC_AHB1SMENR + RCC_AHB1SMENR + RCC AHB1 peripheral clock enable in Sleep and Stop modes register + 0x0B0 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + GPDMA1SMEN + GPDMA1 clocks enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit must be set to allow the peripheral to wake up from Stop modes. + 0 + 1 + read-write + + + B_0x0 + GPDMA1 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + GPDMA1 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + CORDICSMEN + CORDIC clocks enable during Sleep and Stop modes +This bit is set and cleared by software during Sleep mode. + 1 + 1 + read-write + + + B_0x0 + CORDIC clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + CORDIC clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + FMACSMEN + FMAC clocks enable during Sleep and Stop modes. +This bit is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + FMAC clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + FMAC clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + MDF1SMEN + MDF1 clocks enable during Sleep and Stop modes. +This bit is set and cleared by software. +Note: This bit must be set to allow the peripheral to wake up from Stop modes. + 3 + 1 + read-write + + + B_0x0 + MDF1 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + MDF1 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + FLASHSMEN + FLASH clocks enable during Sleep and Stop modes +This bit is set and cleared by software. + 8 + 1 + read-write + + + B_0x0 + FLASH clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + FLASH clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + CRCSMEN + CRC clocks enable during Sleep and Stop modes +This bit is set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + CRC clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + CRC clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + JPEGSMEN + JPEG clocks enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 15 + 1 + read-write + + + B_0x0 + JPEG clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + JPEG clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + TSCSMEN + TSC clocks enable during Sleep and Stop modes +This bit is set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + TSC clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + TSC clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + RAMCFGSMEN + RAMCFG clock enable during Sleep and Stop modes +This bit is set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + RAMCFG clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + RAMCFG clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + DMA2DSMEN + DMA2D clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 18 + 1 + read-write + + + B_0x0 + DMA2D clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + DMA2D clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + GFXMMUSMEN + GFXMMU clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 19 + 1 + read-write + + + B_0x0 + GFXMMU clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + GFXMMU clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + GPU2DSMEN + GPU2D clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 20 + 1 + read-write + + + B_0x0 + GPU2D clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + GPU2D clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + DCACHE2SMEN + DCACHE2 clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 21 + 1 + read-write + + + B_0x0 + DCACHE2 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + DCACHE2 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + GTZC1SMEN + GTZC1 clock enable during Sleep and Stop modes +This bit is set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + GTZC1 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + GTZC1 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + BKPSRAMSMEN + BKPSRAM clock enable during Sleep and Stop modes +This bit is set and cleared by software + 28 + 1 + read-write + + + B_0x0 + BKPSRAM clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + BKPSRAM clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + ICACHESMEN + ICACHE clock enable during Sleep and Stop modes +This bit is set and cleared by software. + 29 + 1 + read-write + + + B_0x0 + ICACHE clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + ICACHE clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + DCACHE1SMEN + DCACHE1 clock enable during Sleep and Stop modes +This bit is set and cleared by software. + 30 + 1 + read-write + + + B_0x0 + DCACHE1 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + DCACHE1 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + SRAM1SMEN + SRAM1 clock enable during Sleep and Stop modes +This bit is set and cleared by software. + 31 + 1 + read-write + + + B_0x0 + SRAM1 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + SRAM1 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + + + RCC_AHB2SMENR1 + RCC_AHB2SMENR1 + RCC AHB2 peripheral clock enable in Sleep and Stop modes register 1 + 0x0B4 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + GPIOASMEN + I/O port A clocks enable during Sleep and Stop modes +This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + I/O port A clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + I/O port A clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + GPIOBSMEN + I/O port B clocks enable during Sleep and Stop modes +This bit is set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + I/O port B clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + I/O port B clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + GPIOCSMEN + I/O port C clocks enable during Sleep and Stop modes +This bit is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + I/O port C clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + I/O port C clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + GPIODSMEN + I/O port D clocks enable during Sleep and Stop modes +This bit is set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + I/O port D clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + I/O port D clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + GPIOESMEN + I/O port E clocks enable during Sleep and Stop modes +This bit is set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + I/O port E clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + I/O port E clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + GPIOFSMEN + I/O port F clocks enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 5 + 1 + read-write + + + B_0x0 + I/O port F clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + I/O port F clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + GPIOGSMEN + I/O port G clocks enable during Sleep and Stop modes +This bit is set and cleared by software. + 6 + 1 + read-write + + + B_0x0 + I/O port G clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + I/O port G clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + GPIOHSMEN + I/O port H clocks enable during Sleep and Stop modes +This bit is set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + I/O port H clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + I/O port H clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + GPIOISMEN + I/O port I clocks enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 8 + 1 + read-write + + + B_0x0 + I/O port I clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + I/O port I clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + GPIOJSMEN + I/O port J clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 9 + 1 + read-write + + + B_0x0 + I/O port J clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + I/O port J clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + ADC12SMEN + ADC1 and ADC2 clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit impacts ADC1 in STM32U535/545/575/585 and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx. + 10 + 1 + read-write + + + B_0x0 + ADC1 and ADC2 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + ADC1 and ADC2 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + DCMI_PSSISMEN + DCMI and PSSI clock enable during Sleep and Stop modes +This bit is set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + DCMI and PSSI clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + DCMI and PSSI clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + OTGSMEN + OTG_FS and OTG_HS clocks enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 14 + 1 + read-write + + + B_0x0 + OTG_FS and OTG_HS clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + OTG_FS and OTG_HS clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + OTGHSPHYSMEN + OTG_HS PHY clock enable during Sleep and Stop modes +This bit is set and cleared by software +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 15 + 1 + read-write + + + B_0x0 + OTG_HS PHY clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + OTG_HS PHY clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + AESSMEN + AES clock enable during Sleep and Stop modes +This bit is set and cleared by software +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 16 + 1 + read-write + + + B_0x0 + AES clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + AES clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + HASHSMEN + HASH clock enable during Sleep and Stop modes +This bit is set and cleared by software + 17 + 1 + read-write + + + B_0x0 + HASH clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + HASH clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + RNGSMEN + RNG clock enable during Sleep and Stop modes +This bit is set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + RNG clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + RNG clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + PKASMEN + PKA clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 19 + 1 + read-write + + + B_0x0 + PKA clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + PKA clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + SAESSMEN + SAES accelerator clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 20 + 1 + read-write + + + B_0x0 + SAES clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + SAES clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + OCTOSPIMSMEN + OCTOSPIM clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 21 + 1 + read-write + + + B_0x0 + OCTOSPIM clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + OCTOSPIM clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + OTFDEC1SMEN + OTFDEC1 clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 23 + 1 + read-write + + + B_0x0 + OTFDEC1 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + OTFDEC1 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + OTFDEC2SMEN + OTFDEC2 clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 24 + 1 + read-write + + + B_0x0 + OTFDEC2 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + OTFDEC2 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + SDMMC1SMEN + SDMMC1 clock enable during Sleep and Stop modes +This bit is set and cleared by software. + 27 + 1 + read-write + + + B_0x0 + SDMMC1 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + SDMMC1 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + SDMMC2SMEN + SDMMC2 clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 28 + 1 + read-write + + + B_0x0 + SDMMC2 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + SDMMC2 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + SRAM2SMEN + SRAM2 clock enable during Sleep and Stop modes +This bit is set and cleared by software. + 30 + 1 + read-write + + + B_0x0 + SRAM2 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + SRAM2 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + SRAM3SMEN + SRAM3 clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 31 + 1 + read-write + + + B_0x0 + SRAM3 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + SRAM3 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + + + RCC_AHB2SMENR2 + RCC_AHB2SMENR2 + RCC AHB2 peripheral clock enable in Sleep and Stop modes register 2 + 0x0B8 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + FSMCSMEN + FSMC clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 0 + 1 + read-write + + + B_0x0 + FSMC clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + FSMC clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + OCTOSPI1SMEN + OCTOSPI1 clock enable during Sleep and Stop modes +This bit is set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + OCTOSPI1 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + OCTOSPI1 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + OCTOSPI2SMEN + OCTOSPI2 clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 8 + 1 + read-write + + + B_0x0 + OCTOSPI2 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + OCTOSPI2 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + HSPI1SMEN + HSPI1 clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 12 + 1 + read-write + + + B_0x0 + HSPI1 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + HSP1I clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + SRAM6SMEN + SRAM6 clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 30 + 1 + read-write + + + B_0x0 + SRAM6 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + SRAM6 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + SRAM5SMEN + SRAM5 clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 31 + 1 + read-write + + + B_0x0 + SRAM5 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + SRAM5 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + + + RCC_AHB3SMENR + RCC_AHB3SMENR + RCC AHB3 peripheral clock enable in Sleep and Stop modes register + 0x0BC + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + LPGPIO1SMEN + LPGPIO1 enable during Sleep and Stop modes +This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + LPGPIO1 clock disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + LPGPIO1 clock enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + PWRSMEN + PWR clock enable during Sleep and Stop modes +This bit is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + PWR clock disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + PWR clock enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + ADC4SMEN + ADC4 clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit must be set to allow the peripheral to wake up from Stop modes. + 5 + 1 + read-write + + + B_0x0 + ADC4 clock disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + ADC4 clock enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + DAC1SMEN + DAC1 clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit must be set to allow the peripheral to wake up from Stop modes. + 6 + 1 + read-write + + + B_0x0 + DAC1 clock disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + DAC1 clock enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + LPDMA1SMEN + LPDMA1 clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit must be set to allow the peripheral to wake up from Stop modes. + 9 + 1 + read-write + + + B_0x0 + LPDMA1 clock disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + LPDMA1 clock enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + ADF1SMEN + ADF1 clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit must be set to allow the peripheral to wake up from Stop modes. + 10 + 1 + read-write + + + B_0x0 + ADF1 clock disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + ADF1 clock enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + GTZC2SMEN + GTZC2 clock enable during Sleep and Stop modes +This bit is set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + GTZC2 clock disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + GTZC2 clock enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + SRAM4SMEN + SRAM4 clock enable during Sleep and Stop modes +This bit is set and cleared by software. + 31 + 1 + read-write + + + B_0x0 + SRAM4 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + SRAM4 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + + + RCC_APB1SMENR1 + RCC_APB1SMENR1 + RCC APB1 peripheral clock enable in Sleep and Stop modes register 1 + 0x0C4 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + TIM2SMEN + TIM2 clock enable during Sleep and Stop modes +This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + TIM2 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM2 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + TIM3SMEN + TIM3 clock enable during Sleep and Stop modes +This bit is set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + TIM3 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM3 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + TIM4SMEN + TIM4 clock enable during Sleep and Stop modes +This bit is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + TIM4 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM4 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + TIM5SMEN + TIM5 clock enable during Sleep and Stop modes +This bit is set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + TIM5 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM5 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + TIM6SMEN + TIM6 clock enable during Sleep and Stop modes +This bit is set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + TIM6 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM6 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + TIM7SMEN + TIM7 clock enable during Sleep and Stop modes +This bit is set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + TIM7 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM7 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + WWDGSMEN + Window watchdog clock enable during Sleep and Stop modes +This bit is set and cleared by software. It is forced to one by hardware when the hardware WWDG option is activated. + 11 + 1 + read-write + + + B_0x0 + Window watchdog clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + Window watchdog clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + SPI2SMEN + SPI2 clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit must be set to allow the peripheral to wake up from Stop modes. + 14 + 1 + read-write + + + B_0x0 + SPI2 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + SPI2 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + USART2SMEN + USART2 clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit must be set to allow the peripheral to wake up from Stop modes. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 17 + 1 + read-write + + + B_0x0 + USART2 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + USART2 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + USART3SMEN + USART3 clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit must be set to allow the peripheral to wake up from Stop modes. + 18 + 1 + read-write + + + B_0x0 + USART3 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + USART3 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + UART4SMEN + UART4 clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit must be set to allow the peripheral to wake up from Stop modes. + 19 + 1 + read-write + + + B_0x0 + UART4 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + UART4 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + UART5SMEN + UART5 clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit must be set to allow the peripheral to wake up from Stop modes. + 20 + 1 + read-write + + + B_0x0 + UART5 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + UART5 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + I2C1SMEN + I2C1 clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit must be set to allow the peripheral to wake up from Stop modes. + 21 + 1 + read-write + + + B_0x0 + I2C1 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + I2C1 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + I2C2SMEN + I2C2 clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit must be set to allow the peripheral to wake up from Stop modes. + 22 + 1 + read-write + + + B_0x0 + I2C2 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + I2C2 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + CRSSMEN + CRS clock enable during Sleep and Stop modes +This bit is set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + CRS clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + CRS clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + USART6SMEN + USART6 clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit must be set to allow the peripheral to wake up from Stop modes. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 25 + 1 + read-write + + + B_0x0 + USART6 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + USART6 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + + + RCC_APB1SMENR2 + RCC_APB1SMENR2 + RCC APB1 peripheral clocks enable in Sleep and Stop modes register 2 + 0x0C8 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + I2C4SMEN + I2C4 clock enable during Sleep and Stop modes +This bit is set and cleared by software +Note: This bit must be set to allow the peripheral to wake up from Stop modes. + 1 + 1 + read-write + + + B_0x0 + I2C4 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + I2C4 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + LPTIM2SMEN + LPTIM2 clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit must be set to allow the peripheral to wake up from Stop modes. + 5 + 1 + read-write + + + B_0x0 + LPTIM2 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + LPTIM2 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + I2C5SMEN + I2C5 clock enable during Sleep and Stop modes +This bit is set and cleared by software +Note: This bit must be set to allow the peripheral to wake up from Stop modes. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 6 + 1 + read-write + + + B_0x0 + I2C5 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + I2C5 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + I2C6SMEN + I2C6 clock enable during Sleep and Stop modes +This bit is set and cleared by software +Note: This bit must be set to allow the peripheral to wake up from Stop modes. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 7 + 1 + read-write + + + B_0x0 + I2C6 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + I2C6 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + FDCAN1SMEN + FDCAN1 clock enable during Sleep and Stop modes +This bit is set and cleared by software. + 9 + 1 + read-write + + + B_0x0 + FDCAN1 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + FDCAN1 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + UCPD1SMEN + UCPD1 clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 23 + 1 + read-write + + + B_0x0 + UCPD1 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + UCPD1 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + + + RCC_APB2SMENR + RCC_APB2SMENR + RCC APB2 peripheral clocks enable in Sleep and Stop modes register + 0x0CC + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + TIM1SMEN + TIM1 clock enable during Sleep and Stop modes +This bit is set and cleared by software. + 11 + 1 + read-write + + + B_0x0 + TIM1 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM1 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + SPI1SMEN + SPI1 clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit must be set to allow the peripheral to wake up from Stop modes. + 12 + 1 + read-write + + + B_0x0 + SPI1 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + SPI1 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + TIM8SMEN + TIM8 clock enable during Sleep and Stop modes +This bit is set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + TIM8 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM8 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + USART1SMEN + USART1 clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit must be set to allow the peripheral to wake up from Stop modes. + 14 + 1 + read-write + + + B_0x0 + USART1clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + USART1clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + TIM15SMEN + TIM15 clock enable during Sleep and Stop modes +This bit is set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + TIM15 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM15 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + TIM16SMEN + TIM16 clock enable during Sleep and Stop modes +This bit is set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + TIM16 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM16 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + TIM17SMEN + TIM17 clock enable during Sleep and Stop modes +This bit is set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + TIM17 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM17 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + SAI1SMEN + SAI1 clock enable during Sleep and Stop modes +This bit is set and cleared by software. + 21 + 1 + read-write + + + B_0x0 + SAI1 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + SAI1 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + SAI2SMEN + SAI2 clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series.Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 22 + 1 + read-write + + + B_0x0 + SAI2 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + SAI2 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + USBSMEN + USB clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 24 + 1 + read-write + + + B_0x0 + USB clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + USB clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + GFXTIMSMEN + GFXTIM clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 25 + 1 + read-write + + + B_0x0 + GFXTIM clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + GFXTIM clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + LTDCSMEN + LTDC clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 26 + 1 + read-write + + + B_0x0 + LTDC clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + LTDC clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + DSISMEN + DSI clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 27 + 1 + read-write + + + B_0x0 + DSI clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + DSI clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + + + RCC_APB3SMENR + RCC_APB3SMENR + RCC APB3 peripheral clock enable in Sleep and Stop modes register + 0x0D0 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + SYSCFGSMEN + SYSCFG clock enable during Sleep and Stop modes +This bit is set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + SYSCFG clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + SYSCFG clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + SPI3SMEN + SPI3 clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit must be set to allow the peripheral to wake up from Stop modes. + 5 + 1 + read-write + + + B_0x0 + SPI3 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + SPI3 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + LPUART1SMEN + LPUART1 clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit must be set to allow the peripheral to wake up from Stop modes. + 6 + 1 + read-write + + + B_0x0 + LPUART1 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + LPUART1 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + I2C3SMEN + I2C3 clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit must be set to allow the peripheral to wake up from Stop modes. + 7 + 1 + read-write + + + B_0x0 + I2C3 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + I2C3 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + LPTIM1SMEN + LPTIM1 clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit must be set to allow the peripheral to wake up from Stop modes. + 11 + 1 + read-write + + + B_0x0 + LPTIM1 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + LPTIM1 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + LPTIM3SMEN + LPTIM3 clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit must be set to allow the peripheral to wake up from Stop modes. + 12 + 1 + read-write + + + B_0x0 + LPTIM3 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + LPTIM3 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + LPTIM4SMEN + LPTIM4 clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit must be set to allow the peripheral to wake up from Stop modes. + 13 + 1 + read-write + + + B_0x0 + LPTIM4 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + LPTIM4 clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + OPAMPSMEN + OPAMP clock enable during Sleep and Stop modes +This bit is set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + OPAMP clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + OPAMP clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + COMPSMEN + COMP clock enable during Sleep and Stop modes +This bit is set and cleared by software. + 15 + 1 + read-write + + + B_0x0 + COMP clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + COMP clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + VREFSMEN + VREFBUF clock enable during Sleep and Stop modes +This bit is set and cleared by software. + 20 + 1 + read-write + + + B_0x0 + VREFBUF clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + VREFBUF clocks enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + RTCAPBSMEN + RTC and TAMP APB clock enable during Sleep and Stop modes +This bit is set and cleared by software. +Note: This bit must be set to allow the peripheral to wake up from Stop modes. + 21 + 1 + read-write + + + B_0x0 + RTC and TAMP APB clock disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + RTC and TAMP APB clock enabled by the clock gating during Sleep and Stop modes + 0x1 + + + + + + + RCC_SRDAMR + RCC_SRDAMR + RCC SmartRun domain peripheral autonomous mode register + 0x0D8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SPI3AMEN + SPI3 autonomous mode enable in Stop 0,1, 2 mode +This bit is set and cleared by software. +Note: This bit must be set to allow the peripheral to wake up from Stop modes. + 5 + 1 + read-write + + + B_0x0 + SPI3 autonomous mode disabled during Stop 0/1/2 mode + 0x0 + + + B_0x1 + SPI3 autonomous mode enabled during Stop 0/1/2 mode + 0x1 + + + + + LPUART1AMEN + LPUART1 autonomous mode enable in Stop 0/1/2 mode +This bit is set and cleared by software. +Note: This bit must be set to allow the peripheral to wake up from Stop modes. + 6 + 1 + read-write + + + B_0x0 + LPUART1 autonomous mode disabled during Stop 0/1/2 mode + 0x0 + + + B_0x1 + LPUART1 autonomous mode enabled during Stop 0/1/2 mode + 0x1 + + + + + I2C3AMEN + I2C3 autonomous mode enable in Stop 0/1/2 mode +This bit is set and cleared by software. +Note: This bit must be set to allow the peripheral to wake up from Stop modes. + 7 + 1 + read-write + + + B_0x0 + I2C3 autonomous mode disabled during Stop 0/1/2 mode + 0x0 + + + B_0x1 + I2C3 autonomous mode enabled during Stop 0/1/2 mode + 0x1 + + + + + LPTIM1AMEN + LPTIM1 autonomous mode enable in Stop 0/1/2 mode +This bit is set and cleared by software. +Note: This bit must be set to allow the peripheral to wake up from Stop modes. + 11 + 1 + read-write + + + B_0x0 + LPTIM1 autonomous mode disabled during Stop 0/1/2 mode + 0x0 + + + B_0x1 + LPTIM1 autonomous mode enabled during Stop 0/1/2 mode + 0x1 + + + + + LPTIM3AMEN + LPTIM3 autonomous mode enable in Stop 0/1/2 mode +This bit is set and cleared by software. +Note: This bit must be set to allow the peripheral to wake up from Stop modes. + 12 + 1 + read-write + + + B_0x0 + LPTIM3 autonomous mode disabled during Stop 0/1/2 mode + 0x0 + + + B_0x1 + LPTIM3 autonomous mode enabled during Stop 0/1/2 mode + 0x1 + + + + + LPTIM4AMEN + LPTIM4 autonomous mode enable in Stop 0/1/2 mode +This bit is set and cleared by software. +Note: This bit must be set to allow the peripheral to wake up from Stop modes. + 13 + 1 + read-write + + + B_0x0 + LPTIM4 autonomous mode disabled during Stop 0/1/2 mode + 0x0 + + + B_0x1 + LPTIM4 autonomous mode enabled during Stop 0/1/2 mode + 0x1 + + + + + OPAMPAMEN + OPAMP autonomous mode enable in Stop 0/1/2 mode +This bit is set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + OPAMP autonomous mode disabled during Stop 0/1/2 mode + 0x0 + + + B_0x1 + OPAMP autonomous mode enabled during Stop 0/1/2 mode + 0x1 + + + + + COMPAMEN + COMP autonomous mode enable in Stop 0/1/2 mode +This bit is set and cleared by software. + 15 + 1 + read-write + + + B_0x0 + COMP autonomous mode disabled during Stop 0/1/2 mode + 0x0 + + + B_0x1 + COMP autonomous mode enabled during Stop 0/1/2 mode + 0x1 + + + + + VREFAMEN + VREFBUF autonomous mode enable in Stop 0/1/2 mode +This bit is set and cleared by software. + 20 + 1 + read-write + + + B_0x0 + VREFBUF autonomous mode disabled during Stop 0/1/2 mode + 0x0 + + + B_0x1 + VREFBUF autonomous mode enabled during Stop 0/1/2 mode + 0x1 + + + + + RTCAPBAMEN + RTC and TAMP autonomous mode enable in Stop 0/1/2 mode +This bit is set and cleared by software. +Note: This bit must be set to allow the peripheral to wake up from Stop modes. + 21 + 1 + read-write + + + B_0x0 + RTC and TAMP autonomous mode disabled during Stop 0/1/2mode + 0x0 + + + B_0x1 + RTC and TAMP autonomous mode enabled during Stop 0/1/2 mode + 0x1 + + + + + ADC4AMEN + ADC4 autonomous mode enable in Stop 0/1/2 mode +This bit is set and cleared by software. +Note: This bit must be set to allow the peripheral to wake up from Stop modes. + 25 + 1 + read-write + + + B_0x0 + ADC4 autonomous mode disabled during Stop 0/1/2 mode + 0x0 + + + B_0x1 + ADC4 autonomous mode enabled during Stop 0/1/2 mode + 0x1 + + + + + LPGPIO1AMEN + LPGPIO1 autonomous mode enable in Stop 0/1/2 mode +This bit is set and cleared by software. + 26 + 1 + read-write + + + B_0x0 + LPGPIO1 autonomous mode disabled during Stop 0/1/2 mode + 0x0 + + + B_0x1 + LPGPIO1 autonomous mode enabled during Stop 0/1/2 mode + 0x1 + + + + + DAC1AMEN + DAC1 autonomous mode enable in Stop 0/1/2 mode +This bit is set and cleared by software. +Note: This bit must be set to allow the peripheral to wake up from Stop modes. + 27 + 1 + read-write + + + B_0x0 + DAC1 autonomous mode disabled during Stop 0/1/2 mode + 0x0 + + + B_0x1 + DAC1 autonomous mode enabled during Stop 0/1/2 mode + 0x1 + + + + + LPDMA1AMEN + LPDMA1 autonomous mode enable in Stop 0/1/2 mode +This bit is set and cleared by software. +Note: This bit must be set to allow the peripheral to wake up from Stop modes. + 28 + 1 + read-write + + + B_0x0 + LPDMA1 autonomous mode disabled during Stop 0/1/2 mode + 0x0 + + + B_0x1 + LPDMA1 autonomous mode enabled during Stop 0/1/2 mode + 0x1 + + + + + ADF1AMEN + ADF1 autonomous mode enable in Stop 0/1/2 mode +This bit is set and cleared by software. +Note: This bit must be set to allow the peripheral to wake up from Stop modes. + 29 + 1 + read-write + + + B_0x0 + ADF1 autonomous mode disabled during Stop 0/1/2 mode + 0x0 + + + B_0x1 + ADF1 autonomous mode enabled during Stop 0/1/2 mode + 0x1 + + + + + SRAM4AMEN + SRAM4 autonomous mode enable in Stop 0/1/2 mode +This bit is set and cleared by software. + 31 + 1 + read-write + + + B_0x0 + SRAM4 autonomous mode disabled during Stop 0/1/2 mode + 0x0 + + + B_0x1 + SRAM4 autonomous mode enabled during Stop 0/1/2 mode + 0x1 + + + + + + + RCC_CCIPR1 + RCC_CCIPR1 + RCC peripherals independent clock configuration register 1 + 0x0E0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + USART1SEL + USART1 kernel clock source selection +These bits are used to select the USART1 kernel clock source. +Note: The USART1 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16 or LSE. + 0 + 2 + read-write + + + B_0x0 + PCLK2 selected + 0x0 + + + B_0x1 + SYSCLK selected + 0x1 + + + B_0x2 + HSI16 selected + 0x2 + + + B_0x3 + LSE selected + 0x3 + + + + + USART2SEL + USART2 kernel clock source selection +These bits are used to select the USART2 kernel clock source. +The USART2 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16 or LSE. +Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value. + 2 + 2 + read-write + + + B_0x0 + PCLK1 selected + 0x0 + + + B_0x1 + SYSCLK selected + 0x1 + + + B_0x2 + HSI16 selected + 0x2 + + + B_0x3 + LSE selected + 0x3 + + + + + USART3SEL + USART3 kernel clock source selection +These bits are used to select the USART3 kernel clock source. +Note: The USART3 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16 or LSE. + 4 + 2 + read-write + + + B_0x0 + PCLK1 selected + 0x0 + + + B_0x1 + SYSCLK selected + 0x1 + + + B_0x2 + HSI16 selected + 0x2 + + + B_0x3 + LSE selected + 0x3 + + + + + UART4SEL + UART4 kernel clock source selection +These bits are used to select the UART4 kernel clock source. +Note: The UART4 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16 or LSE. + 6 + 2 + read-write + + + B_0x0 + PCLK1 selected + 0x0 + + + B_0x1 + SYSCLK selected + 0x1 + + + B_0x2 + HSI16 selected + 0x2 + + + B_0x3 + LSE selected + 0x3 + + + + + UART5SEL + UART5 kernel clock source selection +These bits are used to select the UART5 kernel clock source. +Note: The UART5 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16 or LSE. + 8 + 2 + read-write + + + B_0x0 + PCLK1 selected + 0x0 + + + B_0x1 + SYSCLK selected + 0x1 + + + B_0x2 + HSI16 selected + 0x2 + + + B_0x3 + LSE selected + 0x3 + + + + + I2C1SEL + I2C1 kernel clock source selection +These bits are used to select the I2C1 kernel clock source. +Note: The I2C1 is functional in Stop 0 and Stop 1 mode sonly when the kernel clock is HSI16�or MSIK. + 10 + 2 + read-write + + + B_0x0 + PCLK1 selected + 0x0 + + + B_0x1 + SYSCLK selected + 0x1 + + + B_0x2 + HSI16 selected + 0x2 + + + B_0x3 + MSIK selected + 0x3 + + + + + I2C2SEL + I2C2 kernel clock source selection +These bits are used to select the I2C2 kernel clock source. +Note: The I2C2 is functional in Stop 0 and Stop 1 mode sonly when the kernel clock is HSI16�or MSIK. + 12 + 2 + read-write + + + B_0x0 + PCLK1 selected + 0x0 + + + B_0x1 + SYSCLK selected + 0x1 + + + B_0x2 + HSI16 selected + 0x2 + + + B_0x3 + MSIK selected + 0x3 + + + + + I2C4SEL + I2C4 kernel clock source selection +These bits are used to select the I2C4 kernel clock source. +Note: The I2C4 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16�or MSIK. + 14 + 2 + read-write + + + B_0x0 + PCLK1 selected + 0x0 + + + B_0x1 + SYSCLK selected + 0x1 + + + B_0x2 + HSI16 selected + 0x2 + + + B_0x3 + MSIK selected + 0x3 + + + + + SPI2SEL + SPI2 kernel clock source selection +These bits are used to select the SPI2 kernel clock source. +Note: The SPI2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK. + 16 + 2 + read-write + + + B_0x0 + PCLK1 selected + 0x0 + + + B_0x1 + SYSCLK selected + 0x1 + + + B_0x2 + HSI16 selected + 0x2 + + + B_0x3 + MSIK selected + 0x3 + + + + + LPTIM2SEL + Low-power timer 2 kernel clock source selection +These bits are used to select the LPTIM2 kernel clock source. +Note: The LPTIM2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is LSI, LSE or HSI16 if HSIKERON = 1. + 18 + 2 + read-write + + + B_0x0 + PCLK1 selected + 0x0 + + + B_0x1 + LSI selected + 0x1 + + + B_0x2 + HSI16 selected + 0x2 + + + B_0x3 + LSE selected + 0x3 + + + + + SPI1SEL + SPI1 kernel clock source selection +These bits are used to select the SPI1 kernel clock source. +Note: The SPI1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK. + 20 + 2 + read-write + + + B_0x0 + PCLK2 selected + 0x0 + + + B_0x1 + SYSCLK selected + 0x1 + + + B_0x2 + HSI16 selected + 0x2 + + + B_0x3 + MSIK selected + 0x3 + + + + + SYSTICKSEL + SysTick clock source selection +These bits are used to select the SysTick clock source. +Note: When LSE or LSI is selected, the AHB frequency must be at least four times higher than the LSI or LSE frequency. In addition, a jitter up to one HCLK cycle is introduced, due to the LSE or LSI sampling with HCLK in the SysTick circuitry. + 22 + 2 + read-write + + + B_0x0 + HCLK/8 selected + 0x0 + + + B_0x1 + LSI selected + 0x1 + + + B_0x2 + LSE selected + 0x2 + + + B_0x3 + reserved + 0x3 + + + + + FDCAN1SEL + FDCAN1 kernel clock source selection +These bits are used to select the FDCAN1 kernel clock source. + 24 + 2 + read-write + + + B_0x0 + HSE clock selected + 0x0 + + + B_0x1 + PLL1“Q” (pll1_q_ck) selected + 0x1 + + + B_0x2 + PLL2 “P” (pll2_p_ck) selected + 0x2 + + + B_0x3 + reserved + 0x3 + + + + + ICLKSEL + Intermediate clock source selection +These bits are used to select the clock source for the OTG_FS, the USB, and the SDMMC. + 26 + 2 + read-write + + + B_0x0 + HSI48 clock selected + 0x0 + + + B_0x1 + PLL2 “Q” (pll2_q_ck) selected + 0x1 + + + B_0x2 + PLL1 “Q” (pll1_q_ck) selected + 0x2 + + + B_0x3 + MSIK clock selected + 0x3 + + + + + TIMICSEL + Clock sources for TIM16,TIM17, and LPTIM2 internal input capture +When TIMICSEL2 is set, the TIM16, TIM17, and LPTIM2 internal input capture can be connected either to HSI/256, MSI/4, or MSI/1024. Depending on TIMICSEL[1:0] value, MSI is either MSIK or MSIS. +When TIMICSEL2 is cleared, the HSI, MSIK, and MSIS clock sources cannot be selected as�TIM16, TIM17, or LPTIM2 internal input capture. +0xx: HSI, MSIK and MSIS dividers disabled +Note: The clock division must be disabled (TIMICSEL configured to 0xx) before selecting or changing a clock sources division. + 29 + 3 + read-write + + + B_0x4 + HSI/256, MSIS/1024 and MSIS/4 generated and can be selected by TIM16, TIM17, and LPTIM2 as internal input capture + 0x4 + + + B_0x5 + HSI/256, MSIS/1024 and MSIK/4 generated and can be selected by TIM16, TIM17, and LPTIM2 as internal input capture + 0x5 + + + B_0x6 + HSI/256, MSIK/1024 and MSIS/4 generated and can be selected by TIM16, TIM17 ,and LPTIM2 as internal input capture + 0x6 + + + B_0x7 + HSI/256, MSIK/1024 and MSIK/4 generated and can be selected by TIM16, TIM17, and LPTIM2 as internal input capture + 0x7 + + + + + + + RCC_CCIPR2 + RCC_CCIPR2 + RCC peripherals independent clock configuration register 2 + 0x0E4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MDF1SEL + MDF1 kernel clock source selection +These bits are used to select the MDF1 kernel clock source. +others: reserved + 0 + 3 + read-write + + + B_0x0 + HCLK selected + 0x0 + + + B_0x1 + PLL1 “P” (pll1_p_ck) selected + 0x1 + + + B_0x2 + PLL3 “Q” (pll3_q_ck) selected + 0x2 + + + B_0x3 + input pin AUDIOCLK selected + 0x3 + + + B_0x4 + MSIK clock selected + 0x4 + + + + + SAI1SEL + SAI1 kernel clock source selection +These bits are used to select the SAI1 kernel clock source. +others: reserved +Note: If the selected clock is the external clock and this clock is stopped, a switch to another clock is impossible. + 5 + 3 + read-write + + + B_0x0 + PLL2 “P” (pll2_p_ck) selected + 0x0 + + + B_0x1 + PLL3 “P” (pll3_p_ck) selected + 0x1 + + + B_0x2 + PLL1 “P” (pll1_p_ck) selected + 0x2 + + + B_0x3 + input pin AUDIOCLK selected + 0x3 + + + B_0x4 + HSI16 clock selected + 0x4 + + + + + SAI2SEL + SAI2 kernel clock source selection +These bits are used to select the SAI2 kernel clock source. +others: reserved +If the selected clock is the external clock and this clock is stopped, a switch to another clock is impossible. +Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value. + 8 + 3 + read-write + + + B_0x0 + PLL2 “P” (pll2_p_ck) selected + 0x0 + + + B_0x1 + PLL3 “P” (pll3_p_ck) selected + 0x1 + + + B_0x2 + PLL1 “P” (pll1_p_ck) selected + 0x2 + + + B_0x3 + input pin AUDIOCLK selected + 0x3 + + + B_0x4 + HSI16 clock selected + 0x4 + + + + + SAESSEL + SAES kernel clock source selection +This bit is used to select the SAES kernel clock source. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 11 + 1 + read-write + + + B_0x0 + SHSI selected + 0x0 + + + B_0x1 + SHSI / 2 selected, can be used in range 4 + 0x1 + + + + + RNGSEL + RNG kernel clock source selection +These bits are used to select the RNG kernel clock source. + 12 + 2 + read-write + + + B_0x0 + HSI48 selected + 0x0 + + + B_0x1 + HSI48 / 2 selected, can be used in range 4 + 0x1 + + + B_0x2 + HSI16 selected + 0x2 + + + B_0x3 + reserved + 0x3 + + + + + SDMMCSEL + SDMMC1 and SDMMC2 kernel clock source selection +This bit is used to select the SDMMC kernel clock source. It is recommended to change it only after reset and before enabling the SDMMC. + 14 + 1 + read-write + + + B_0x0 + ICLK clock selected + 0x0 + + + B_0x1 + PLL1 “P” (pll1_p_ck) selected, in case higher than 48 MHz is needed (for SDR50 mode) + 0x1 + + + + + DSISEL + DSI kernel clock source selection +This bit is used to select the DSI kernel clock source. +This bit is only available on some devices in the STM32U5 Series. +Refer to the device datasheet for availability of its associated peripheral. +Note: If not present, consider this bit as reserved and keep it at reset value. + 15 + 1 + read-write + + + B_0x0 + PLL3 “P” (pll3_p_ck) selected + 0x0 + + + B_0x1 + DSI PHY PLL output selected + 0x1 + + + + + USART6SEL + USART6 kernel clock source selection +These bits are used to select the USART6 kernel clock source. +The USART6 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16 or LSE. +Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value. + 16 + 2 + read-write + + + B_0x0 + PCLK1 selected + 0x0 + + + B_0x1 + SYSCLK selected + 0x1 + + + B_0x2 + HSI16 selected + 0x2 + + + B_0x3 + LSE selected + 0x3 + + + + + LTDCSEL + LTDC kernel clock source selection +This bit is used to select the LTDC kernel clock source. +Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. + 18 + 1 + read-write + + + B_0x0 + PLL3 “R” (pll3_r_ck) selected + 0x0 + + + B_0x1 + PLL2 “R” (pll2_r_ck) selected + 0x1 + + + + + OCTOSPISEL + OCTOSPI1 and OCTOSPI2 kernel clock source selection +These bits are used to select the OCTOSPI1 and OCTOSPI2 kernel clock source. + 20 + 2 + read-write + + + B_0x0 + SYSCLK selected + 0x0 + + + B_0x1 + MSIK selected + 0x1 + + + B_0x2 + PLL1 “Q” (pll1_q_ck) selected, can be up to 200 MHz + 0x2 + + + B_0x3 + PLL2 “Q” (pll2_q_ck) selected, can be up to 200 MHz + 0x3 + + + + + HSPI1SEL + HSPI1 kernel clock source selection +These bits are used to select the HSPI1 kernel clock source. +Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value. + 22 + 2 + read-write + + + B_0x0 + SYSCLK selected + 0x0 + + + B_0x1 + PLL1 “Q” (pll1_q_ck) selected, can be up to 200 MHz + 0x1 + + + B_0x2 + PLL2 “Q” (pll2_q_ck) selected, can be up to 200 MHz + 0x2 + + + B_0x3 + PLL3 “R” (pll3_r_ck) selected, can be up to 200 MHz + 0x3 + + + + + I2C5SEL + I2C5 kernel clock source selection +These bits are used to select the I2C5 kernel clock source. +The I2C5 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16�or MSIK. +Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value. + 24 + 2 + read-write + + + B_0x0 + PCLK1 selected + 0x0 + + + B_0x1 + SYSCLK selected + 0x1 + + + B_0x2 + HSI16 selected + 0x2 + + + B_0x3 + MSIK selected + 0x3 + + + + + I2C6SEL + I2C6 kernel clock source selection +These bits are used to select the I2C6 kernel clock source. +The I2C6 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16�or MSIK. +Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value. + 26 + 2 + read-write + + + B_0x0 + PCLK1 selected + 0x0 + + + B_0x1 + SYSCLK selected + 0x1 + + + B_0x2 + HSI16 selected + 0x2 + + + B_0x3 + MSIK selected + 0x3 + + + + + OTGHSSEL + OTG_HS PHY kernel clock source selection +These bits are used to select the OTG_HS PHY kernel clock source. +Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value. + 30 + 2 + read-write + + + B_0x0 + HSE selected + 0x0 + + + B_0x1 + PLL1 “P” (pll1_q_ck) selected, + 0x1 + + + B_0x2 + HSE/2 selected + 0x2 + + + B_0x3 + PLL1 “P” divided by 2 (pll1_p_ck/2) selected + 0x3 + + + + + + + RCC_CCIPR3 + RCC_CCIPR3 + RCC peripherals independent clock configuration register 3 + 0x0E8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LPUART1SEL + LPUART1 kernel clock source selection +These bits are used to select the LPUART1 kernel clock source. +others: reserved +Note: The LPUART1 is functional in Stop 0, Stop 1, and Stop 2 modes only when the kernel clock is HSI16, LSE, or MSIK. + 0 + 3 + read-write + + + B_0x0 + PCLK3 selected + 0x0 + + + B_0x1 + SYSCLK selected + 0x1 + + + B_0x2 + HSI16 selected + 0x2 + + + B_0x3 + LSE selected + 0x3 + + + B_0x4 + MSIK selected + 0x4 + + + + + SPI3SEL + SPI3 kernel clock source selection +These bits are used to select the SPI3 kernel clock source. +Note: The SPI3 is functional in Stop 0, Stop 1, and Stop 2 modes only when the kernel clock is HSI16 or MSIK. + 3 + 2 + read-write + + + B_0x0 + PCLK3 selected + 0x0 + + + B_0x1 + SYSCLK selected + 0x1 + + + B_0x2 + HSI16 selected + 0x2 + + + B_0x3 + MSIK selected + 0x3 + + + + + I2C3SEL + I2C3 kernel clock source selection +These bits are used to select the I2C3 kernel clock source. +Note: The I2C3 is functional in Stop 0, Stop 1, and Stop 2 modes only when the kernel clock is HSI16 or MSIK. + 6 + 2 + read-write + + + B_0x0 + PCLK3 selected + 0x0 + + + B_0x1 + SYSCLK selected + 0x1 + + + B_0x2 + HSI16 selected + 0x2 + + + B_0x3 + MSIK selected + 0x3 + + + + + LPTIM34SEL + LPTIM3 and LPTIM4 kernel clock source selection +These bits are used to select the LPTIM3 and LPTIM4 kernel clock source. +Note: The LPTIM3 and LPTIM4 are functional in Stop 0, Stop 1, and Stop 2 modes only when the kernel clock is LSI, LSE, HSI16 with HSIKERON = 1, or MSIK with MSIKERON�=�1. + 8 + 2 + read-write + + + B_0x0 + MSIK clock selected + 0x0 + + + B_0x1 + LSI selected + 0x1 + + + B_0x2 + HSI selected + 0x2 + + + B_0x3 + LSE selected + 0x3 + + + + + LPTIM1SEL + LPTIM1 kernel clock source selection +These bits are used to select the LPTIM1 kernel clock source. +Note: The LPTIM1 is functional in Stop 0, Stop 1, and Stop 2 modes only when the kernel clock is LSI, LSE, HSI16 with HSIKERON = 1, or MSIK with MSIKERON = 1. + 10 + 2 + read-write + + + B_0x0 + MSIK clock selected + 0x0 + + + B_0x1 + LSI selected + 0x1 + + + B_0x2 + HSI16 selected + 0x2 + + + B_0x3 + LSE selected + 0x3 + + + + + ADCDACSEL + ADC1, ADC2, ADC4 and DAC1 kernel clock source selection +These bits are used to select the ADC1, ADC2, ADC4, and DAC1 kernel clock source. +others: reserved +Note: The ADC1, ADC2, ADC4, and DAC1 are functional in Stop 0, Stop 1, and Stop 2 modes only when the kernel clock is HSI16 or MSIK (only ADC4 and DAC1 are functional in�Stop 2 mode). + 12 + 3 + read-write + + + B_0x0 + HCLK clock selected + 0x0 + + + B_0x1 + SYSCLK selected + 0x1 + + + B_0x2 + PLL2 “R” (pll2_r_ck) selected + 0x2 + + + B_0x3 + HSE clock selected + 0x3 + + + B_0x4 + HSI16 clock selected + 0x4 + + + B_0x5 + MSIK clock selected + 0x5 + + + + + DAC1SEL + DAC1 sample-and-hold clock source selection +This bit is used to select the DAC1 sample-and-hold clock source. + 15 + 1 + read-write + + + B_0x0 + LSE selected + 0x0 + + + B_0x1 + LSI selected + 0x1 + + + + + ADF1SEL + ADF1 kernel clock source selection +These bits are used to select the ADF1 kernel clock source. +others: reserved +Note: The ADF1 is functional in Stop 0, Stop 1, and Stop 2 modes only when the kernel clock is AUDIOCLK or MSIK. + 16 + 3 + read-write + + + B_0x0 + HCLK selected + 0x0 + + + B_0x1 + PLL1 “P” (pll1_p_ck) selected + 0x1 + + + B_0x2 + PLL3 “Q” (pll3_q_ck) selected + 0x2 + + + B_0x3 + input pin AUDIOCLK selected + 0x3 + + + B_0x4 + MSIK clock selected + 0x4 + + + + + + + RCC_BDCR + RCC_BDCR + RCC backup domain control register + 0x00F0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LSEON + LSE oscillator enable +This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + LSE oscillator off + 0x0 + + + B_0x1 + LSE oscillator on + 0x1 + + + + + LSERDY + LSE oscillator ready +This bit is set and cleared by hardware to indicate when the external 32�kHz oscillator is stable. After LSEON is cleared, this LSERDY bit goes low after six external low-speed oscillator clock cycles. + 1 + 1 + read-only + + + B_0x0 + LSE oscillator not ready + 0x0 + + + B_0x1 + LSE oscillator ready + 0x1 + + + + + LSEBYP + LSE oscillator bypass +This bit is set and cleared by software to bypass oscillator in debug mode. It can be written only when the external 32�kHz oscillator is disabled (LSEON = 0 and LSERDY = 0). + 2 + 1 + read-write + + + B_0x0 + LSE oscillator not bypassed + 0x0 + + + B_0x1 + LSE oscillator bypassed + 0x1 + + + + + LSEDRV + LSE oscillator drive capability +This bitfield is set by software to modulate the drive capability of the LSE oscillator. It can be written only when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0). +Note: The oscillator is in ‘Xtal mode’ when it is not in bypass mode. + 3 + 2 + read-write + + + B_0x0 + ‘Xtal mode’ lower driving capability + 0x0 + + + B_0x1 + ‘Xtal mode’ medium-low driving capability + 0x1 + + + B_0x2 + ‘Xtal mode’ medium-high driving capability + 0x2 + + + B_0x3 + ‘Xtal mode’ higher driving capability + 0x3 + + + + + LSECSSON + CSS on LSE enable +This bit is set by software to enable the CSS on LSE. It must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected. +Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD�=�1). In that case, the software must disable this LSECSSON bit. + 5 + 1 + read-write + + + B_0x0 + CSS on LSE OFF + 0x0 + + + B_0x1 + CSS on LSE ON + 0x1 + + + + + LSECSSD + CSS on LSE failure detection +This bit is set by hardware to indicate when a failure is detected by the CCS on the external 32�kHz oscillator (LSE). + 6 + 1 + read-only + + + B_0x0 + No failure detected on LSE + 0x0 + + + B_0x1 + Failure detected on LSE + 0x1 + + + + + LSESYSEN + LSE system clock (LSESYS) enable +This bit is set by software to enable always the LSE system clock generated by RCC, which can be used by any peripheral when its source clock is the LSE, or at system level if one of LSCOSEL, MCO, or MSI PLL mode is needed. + 7 + 1 + read-write + + + B_0x0 + LSE can be used only for RTC, TAMP, and CSS on LSE. + 0x0 + + + B_0x1 + LSE can be used by any other peripheral or function. + 0x1 + + + + + RTCSEL + RTC and TAMP clock source selection +This bit is set by software to select the clock source for the RTC and TAMP. Once the RTC and TAMP clock source has been selected, it cannot be changed anymore unless the�backup domain is reset, or unless a failure is detected on LSE (LSECSSD is set). BDRST bit can be used to reset them. + 8 + 2 + read-write + + + B_0x0 + No clock selected + 0x0 + + + B_0x1 + LSE oscillator clock selected + 0x1 + + + B_0x2 + LSI oscillator clock selected + 0x2 + + + B_0x3 + HSE oscillator clock divided by 32 selected + 0x3 + + + + + LSESYSRDY + LSE system clock (LSESYS) ready +This bit is set and cleared by hardware to indicate when the LSE system clock is stable.When LSESYSEN is set, this LSESYSRDY flag is set after two LSE clock cycles. +The LSE clock must be already enabled and stable (LSEON and LSERDY are set). +When the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles. + 11 + 1 + read-only + + + B_0x0 + LSESYS clock not ready + 0x0 + + + B_0x1 + LSESYS clock ready + 0x1 + + + + + LSEGFON + LSE clock glitch filter enable +This bit is set and cleared by hardware to enable the LSE glitch filter. It can be written only when the LSE is disabled (LSEON = 0 and LSERDY = 0). + 12 + 1 + read-write + + + B_0x0 + LSE glitch filter disabled + 0x0 + + + B_0x1 + LSE glitch filter enabled + 0x1 + + + + + RTCEN + RTC and TAMP clock enable +This bit is set and cleared by software. + 15 + 1 + read-write + + + B_0x0 + RTC and TAMP clock disabled + 0x0 + + + B_0x1 + RTC and TAMP clock enabled + 0x1 + + + + + BDRST + Backup domain software reset +This bit is set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + Reset not activated + 0x0 + + + B_0x1 + Reset the entire backup domain. + 0x1 + + + + + LSCOEN + Low-speed clock output (LSCO) enable +This bit is set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + LSCO disabled + 0x0 + + + B_0x1 + LSCO enabled + 0x1 + + + + + LSCOSEL + Low-speed clock output selection +This bit is set and cleared by software. + 25 + 1 + read-write + + + B_0x0 + LSI clock selected + 0x0 + + + B_0x1 + LSE clock selected + 0x1 + + + + + LSION + LSI oscillator enable +This bit is set and cleared by software. The LSI oscillator is disabled 60��s maximum after the LSION bit is cleared. + 26 + 1 + read-write + + + B_0x0 + LSI oscillator OFF + 0x0 + + + B_0x1 + LSI oscillator ON + 0x1 + + + + + LSIRDY + LSI oscillator ready +This bit is set and cleared by hardware to indicate when the LSI oscillator is stable. After�LSION is cleared, LSIRDY goes low after three internal low-speed oscillator clock cycles. This bit is set when the LSI is used by IWDG or RTC, even if LSION = 0. + 27 + 1 + read-write + + + B_0x0 + LSI oscillator not ready + 0x0 + + + B_0x1 + LSI oscillator ready + 0x1 + + + + + LSIPREDIV + Low-speed clock divider configuration +This bit is set and cleared by software to enable the LSI division. It can be written only when the LSI is disabled (LSION = 0 and LSIRDY = 0). If the LSI was previously enabled, it is necessary to wait for at least 60 μs after clearing LSION bit (synchronization time for LSI to be really disabled), before writing LSIPREDIV. The LSIPREDIV cannot be changed if the LSI is used by the IWDG or by the RTC. + 28 + 1 + read-write + + + B_0x0 + LSI not divided + 0x0 + + + B_0x1 + LSI divided by 128 + 0x1 + + + + + + + RCC_CSR + RCC_CSR + RCC control/status register + 0x0F4 + 0x20 + 0x0C004400 + 0xFFFFFFFF + + + MSIKSRANGE + MSIK range after Standby mode +This bit is set by software to chose the MSIK frequency at startup. It is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4�MHz. MSIKSRANGE can be written only when MSIRGSEL = 1. +others: reserved +Note: Changing this bitfield does not change the current MSIK frequency. + 8 + 4 + read-write + + + B_0x4 + range 4 around 4M�Hz (reset value) + 0x4 + + + B_0x5 + range 5 around 2�MHz + 0x5 + + + B_0x6 + range 6 around 1.33�MHz + 0x6 + + + B_0x7 + range 7 around 1�MHz + 0x7 + + + B_0x8 + range 8 around 3.072�MHz + 0x8 + + + + + MSISSRANGE + MSIS range after Standby mode +This bitfield is set by software to chose the MSIS frequency at startup. It is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4�MHz. MSISSRANGE can be written only when MSIRGSEL = 1. +others: reserved +Note: Changing this bitfield does not change the current MSIS frequency. + 12 + 4 + read-write + + + B_0x4 + range 4 around 4M�Hz (reset value) + 0x4 + + + B_0x5 + range 5 around 2�MHz + 0x5 + + + B_0x6 + range 6 around 1.33�MHz + 0x6 + + + B_0x7 + range 7 around 1�MHz + 0x7 + + + B_0x8 + range 8 around 3.072�MHz + 0x8 + + + + + RMVF + Remove reset flag +This bit is set by software to clear the reset flags. + 23 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear the reset flags. + 0x1 + + + + + OBLRSTF + Option-byte loader reset flag +This bit is set by hardware when a reset from the option-byte loading occurs. It is cleared by�writing to the RMVF bit. + 25 + 1 + read-only + + + B_0x0 + No reset from option-byte loading occurred + 0x0 + + + B_0x1 + Reset from option-byte loading occurred + 0x1 + + + + + PINRSTF + NRST pin reset flag +This bit is set by hardware when a reset from the NRST pin occurs. It is cleared by writing to�the RMVF bit. + 26 + 1 + read-only + + + B_0x0 + No reset from NRST pin occurred + 0x0 + + + B_0x1 + Reset from NRST pin occurred + 0x1 + + + + + BORRSTF + Brownout reset or an exit from Shutdown mode reset flag +This bit is set by hardware when a brownout reset or an exit from Shutdown mode reset occurs. It is cleared by writing to the RMVF bit. + 27 + 1 + read-only + + + B_0x0 + No BOR/exit from Shutdown mode reset occurred + 0x0 + + + B_0x1 + BOR/exit from Shutdown mode reset occurred + 0x1 + + + + + SFTRSTF + Software reset flag +This bit is set by hardware when a software reset occurs. It is cleared by writing to RMVF. + 28 + 1 + read-only + + + B_0x0 + No software reset occurred + 0x0 + + + B_0x1 + Software reset occurred + 0x1 + + + + + IWDGRSTF + Independent watchdog reset flag +This bit is set by hardware when an independent watchdog reset domain occurs. It is cleared by writing to the RMVF bit. + 29 + 1 + read-only + + + B_0x0 + No independent watchdog reset occurred + 0x0 + + + B_0x1 + Independent watchdog reset occurred + 0x1 + + + + + WWDGRSTF + Window watchdog reset flag +This bit is set by hardware when a window watchdog reset occurs. It is cleared by writing to�the RMVF bit. + 30 + 1 + read-only + + + B_0x0 + No window watchdog reset occurred + 0x0 + + + B_0x1 + Window watchdog reset occurred + 0x1 + + + + + LPWRRSTF + Low-power reset flag +This bit is set by hardware when a reset occurs due to a Stop, Standby, or Shutdown mode entry, whereas the corresponding NRST_STOP, NRST_STBY, or NRST_SHDW option bit is cleared. This bit is cleared by writing to the RMVF bit. + 31 + 1 + read-only + + + B_0x0 + No illegal low-power mode reset occurred + 0x0 + + + B_0x1 + Illegal low-power mode reset occurred + 0x1 + + + + + + + RCC_SECCFGR + RCC_SECCFGR + RCC secure configuration register + 0x110 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + HSISEC + HSI clock configuration and status bit security +This bit is set and reset by software. + 0 + 1 + read-write + + + B_0x0 + non secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + HSESEC + HSE clock configuration bits, status bit and HSE_CSS security +This bit is set and reset by software. + 1 + 1 + read-write + + + B_0x0 + non secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + MSISEC + MSI clock configuration and status bit security +This bit is set and reset by software. + 2 + 1 + read-write + + + B_0x0 + non secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + LSISEC + LSI clock configuration and status bit security +This bit is set and reset by software. + 3 + 1 + read-write + + + B_0x0 + non secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + LSESEC + LSE clock configuration and status bit security +This bit is set and reset by software. + 4 + 1 + read-write + + + B_0x0 + non secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + SYSCLKSEC + SYSCLK clock selection, STOPWUCK bit, clock output on MCO configuration security +This bit is set and reset by software. + 5 + 1 + read-write + + + B_0x0 + non secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + PRESCSEC + AHBx/APBx prescaler configuration bits security +This bit is set and reset by software. + 6 + 1 + read-write + + + B_0x0 + non secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + PLL1SEC + PLL1 clock configuration and status bit security +This bit is set and reset by software. + 7 + 1 + read-write + + + B_0x0 + non secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + PLL2SEC + PLL2 clock configuration and status bit security +Set and reset by software. + 8 + 1 + read-write + + + B_0x0 + non secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + PLL3SEC + PLL3 clock configuration and status bit security +This bit is set and reset by software. + 9 + 1 + read-write + + + B_0x0 + non secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + ICLKSEC + Intermediate clock source selection security +This bit is set and reset by software. + 10 + 1 + read-write + + + B_0x0 + non secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + HSI48SEC + HSI48 clock configuration and status bit security +This bit is set and reset by software. + 11 + 1 + read-write + + + B_0x0 + non secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + RMVFSEC + Remove reset flag security +This bit is set and reset by software. + 12 + 1 + read-write + + + B_0x0 + non secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + + + RCC_PRIVCFGR + RCC_PRIVCFGR + RCC privilege configuration register + 0x114 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SPRIV + RCC secure function privilege configuration +This bit is set and reset by software. It can be written only by a secure privileged access. + 0 + 1 + read-write + + + B_0x0 + Read and write to RCC secure functions can be done by privileged or unprivileged access. + 0x0 + + + B_0x1 + Read and write to RCC secure functions can be done by privileged access only. + 0x1 + + + + + NSPRIV + RCC non-secure function privilege configuration +This bit is set and reset by software. It can be written only by privileged access, secure or non-secure. + 1 + 1 + read-write + + + B_0x0 + Read and write to RCC non-secure functions can be done by privileged or unprivileged access. + 0x0 + + + B_0x1 + Read and write to RCC non-secure functions can be done by privileged access only. + 0x1 + + + + + + + + + SEC_RCC + DCB->DSCSR->CDS == 0 + 0x56020C00 + + + RNG + Random number generator + RNG + 0x420C0800 + + 0x0 + 0x400 + registers + + + RNG + RNG global interrupt + 94 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + CONFIGLOCK + RNG Config Lock + 31 + 1 + + + CONDRST + Conditioning soft reset + 30 + 1 + + + RNG_CONFIG1 + RNG configuration 1 + 20 + 6 + + + CLKDIV + Clock divider factor + 16 + 4 + + + RNG_CONFIG2 + RNG configuration 2 + 13 + 3 + + + NISTC + Non NIST compliant + 12 + 1 + + + RNG_CONFIG3 + RNG configuration 3 + 8 + 4 + + + ARDIS + Auto reset disable + 7 + 1 + + + CED + Clock error detection + 5 + 1 + + + IE + Interrupt Enable + 3 + 1 + + + RNGEN + True random number generator enable + 2 + 1 + + + + + SR + SR + status register + 0x4 + 0x20 + 0x00000000 + + + SEIS + Seed error interrupt status + 6 + 1 + read-write + + + CEIS + Clock error interrupt status + 5 + 1 + read-write + + + SECS + Seed error current status + 2 + 1 + read-only + + + CECS + Clock error current status + 1 + 1 + read-only + + + DRDY + Data ready + 0 + 1 + read-only + + + + + DR + DR + data register + 0x8 + 0x20 + read-only + 0x00000000 + + + RNDATA + Random data + 0 + 32 + + + + + HTCR + HTCR + health test control register + 0x10 + 0x20 + read-write + 0x00006274 + + + HTCFG + health test configuration + 0 + 32 + + + + + + + SEC_RNG + DCB->DSCSR->CDS == 0 + 0x520C0800 + + + RTC + Real-time clock + RTC + 0x46007800 + + 0x0 + 0x400 + registers + + + RTC + RTC global non-secure interrupts + 002 + + + RTC_S + RTC global secure interrupts + 003 + + + + TR + TR + time register + 0x0 + 0x20 + read-write + 0x00000000 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + DR + DR + date register + 0x4 + 0x20 + read-write + 0x00002101 + + + YT + Year tens in BCD format + 20 + 4 + + + YU + Year units in BCD format + 16 + 4 + + + WDU + Week day units + 13 + 3 + + + MT + Month tens in BCD format + 12 + 1 + + + MU + Month units in BCD format + 8 + 4 + + + DT + Date tens in BCD format + 4 + 2 + + + DU + Date units in BCD format + 0 + 4 + + + + + SSR + SSR + RTC sub second register + 0x8 + 0x20 + read-only + 0x00000000 + + + SS + SS + 0 + 32 + + + + + ICSR + ICSR + RTC initialization control and status + register + 0xC + 0x20 + 0x00000007 + + + WUTWF + Wakeup timer write flag + 2 + 1 + read-only + + + SHPF + Shift operation pending + 3 + 1 + read-only + + + INITS + Initialization status flag + 4 + 1 + read-only + + + RSF + Registers synchronization + flag + 5 + 1 + read-write + + + INITF + Initialization flag + 6 + 1 + read-only + + + INIT + Initialization mode + 7 + 1 + read-write + + + BIN + BIN + 8 + 2 + read-write + + + BCDU + BCDU + 10 + 3 + read-write + + + RECALPF + Recalibration pending Flag + 16 + 1 + read-only + + + + + PRER + PRER + prescaler register + 0x10 + 0x20 + read-write + 0x007F00FF + + + PREDIV_A + Asynchronous prescaler + factor + 16 + 7 + + + PREDIV_S + Synchronous prescaler + factor + 0 + 15 + + + + + WUTR + WUTR + wakeup timer register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + WUT + Wakeup auto-reload value + bits + 0 + 16 + + + WUTOCLR + WUTOCLR + 16 + 16 + + + + + CR + CR + RTC control register + 0x18 + 0x20 + 0x00000000 + + + WUCKSEL + WUCKSEL + 0 + 3 + read-write + + + TSEDGE + TSEDGE + 3 + 1 + read-write + + + REFCKON + REFCKON + 4 + 1 + read-write + + + BYPSHAD + BYPSHAD + 5 + 1 + read-write + + + FMT + FMT + 6 + 1 + read-write + + + SSRUIE + SSRUIE + 7 + 1 + read-write + + + ALRAE + ALRAE + 8 + 1 + read-write + + + ALRBE + ALRBE + 9 + 1 + read-write + + + WUTE + WUTE + 10 + 1 + read-write + + + TSE + TSE + 11 + 1 + read-write + + + ALRAIE + ALRAIE + 12 + 1 + read-write + + + ALRBIE + ALRBIE + 13 + 1 + read-write + + + WUTIE + WUTIE + 14 + 1 + read-write + + + TSIE + TSIE + 15 + 1 + read-write + + + ADD1H + ADD1H + 16 + 1 + write-only + + + SUB1H + SUB1H + 17 + 1 + write-only + + + BKP + BKP + 18 + 1 + read-write + + + COSEL + COSEL + 19 + 1 + read-write + + + POL + POL + 20 + 1 + read-write + + + OSEL + OSEL + 21 + 2 + read-write + + + COE + COE + 23 + 1 + read-write + + + ITSE + ITSE + 24 + 1 + read-write + + + TAMPTS + TAMPTS + 25 + 1 + read-write + + + TAMPOE + TAMPOE + 26 + 1 + read-write + + + ALRAFCLR + ALRAFCLR + 27 + 1 + read-write + + + ALRBFCLR + ALRBFCLR + 28 + 1 + read-write + + + TAMPALRM_PU + TAMPALRM_PU + 29 + 1 + read-write + + + TAMPALRM_TYPE + TAMPALRM_TYPE + 30 + 1 + read-write + + + OUT2EN + OUT2EN + 31 + 1 + read-write + + + + + PRIVCR + PRIVCR + RTC privilege mode control + register + 0x1C + 0x20 + read-write + 0x00000000 + + + PRIV + PRIV + 15 + 1 + + + INITPRIV + INITPRIV + 14 + 1 + + + CALPRIV + CALPRIV + 13 + 1 + + + TSPRIV + TSPRIV + 3 + 1 + + + WUTPRIV + WUTPRIV + 2 + 1 + + + ALRBPRIV + ALRBPRIV + 1 + 1 + + + ALRAPRIV + ALRAPRIV + 0 + 1 + + + + + SECCFGR + SECCFGR + RTC secure mode control + register + 0x20 + 0x20 + read-write + 0x00000000 + + + SEC + SEC + 15 + 1 + + + INITSEC + INITSEC + 14 + 1 + + + CALSEC + CALSEC + 13 + 1 + + + TSSEC + TSSEC + 3 + 1 + + + WUTSEC + WUTSEC + 2 + 1 + + + ALRBSEC + ALRBSEC + 1 + 1 + + + ALRASEC + ALRASEC + 0 + 1 + + + + + WPR + WPR + write protection register + 0x24 + 0x20 + write-only + 0x00000000 + + + KEY + Write protection key + 0 + 8 + + + + + CALR + CALR + calibration register + 0x28 + 0x20 + read-write + 0x00000000 + + + CALP + Increase frequency of RTC by 488.5 + ppm + 15 + 1 + + + CALW8 + Use an 8-second calibration cycle + period + 14 + 1 + + + CALW16 + Use a 16-second calibration cycle + period + 13 + 1 + + + LPCAL + LPCAL + 12 + 1 + + + CALM + Calibration minus + 0 + 9 + + + + + SHIFTR + SHIFTR + shift control register + 0x2C + 0x20 + write-only + 0x00000000 + + + ADD1S + Add one second + 31 + 1 + + + SUBFS + Subtract a fraction of a + second + 0 + 15 + + + + + TSTR + TSTR + time stamp time register + 0x30 + 0x20 + read-only + 0x00000000 + + + SU + Second units in BCD format + 0 + 4 + + + ST + Second tens in BCD format + 4 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + MNT + Minute tens in BCD format + 12 + 3 + + + HU + Hour units in BCD format + 16 + 4 + + + HT + Hour tens in BCD format + 20 + 2 + + + PM + AM/PM notation + 22 + 1 + + + + + TSDR + TSDR + time stamp date register + 0x34 + 0x20 + read-only + 0x00000000 + + + WDU + Week day units + 13 + 3 + + + MT + Month tens in BCD format + 12 + 1 + + + MU + Month units in BCD format + 8 + 4 + + + DT + Date tens in BCD format + 4 + 2 + + + DU + Date units in BCD format + 0 + 4 + + + + + TSSSR + TSSSR + timestamp sub second register + 0x38 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value + 0 + 32 + + + + + ALRMAR + ALRMAR + alarm A register + 0x40 + 0x20 + read-write + 0x00000000 + + + MSK4 + Alarm A date mask + 31 + 1 + + + WDSEL + Week day selection + 30 + 1 + + + DT + Date tens in BCD format + 28 + 2 + + + DU + Date units or day in BCD + format + 24 + 4 + + + MSK3 + Alarm A hours mask + 23 + 1 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MSK2 + Alarm A minutes mask + 15 + 1 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + MSK1 + Alarm A seconds mask + 7 + 1 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + ALRMASSR + ALRMASSR + alarm A sub second register + 0x44 + 0x20 + read-write + 0x00000000 + + + SSCLR + SSCLR + 31 + 1 + + + MASKSS + Mask the most-significant bits starting + at this bit + 24 + 6 + + + SS + Sub seconds value + 0 + 15 + + + + + ALRMBR + ALRMBR + alarm B register + 0x48 + 0x20 + read-write + 0x00000000 + + + MSK4 + Alarm B date mask + 31 + 1 + + + WDSEL + Week day selection + 30 + 1 + + + DT + Date tens in BCD format + 28 + 2 + + + DU + Date units or day in BCD + format + 24 + 4 + + + MSK3 + Alarm B hours mask + 23 + 1 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MSK2 + Alarm B minutes mask + 15 + 1 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + MSK1 + Alarm B seconds mask + 7 + 1 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + ALRMBSSR + ALRMBSSR + alarm B sub second register + 0x4C + 0x20 + read-write + 0x00000000 + + + SSCLR + SSCLR + 31 + 1 + + + MASKSS + Mask the most-significant bits starting + at this bit + 24 + 6 + + + SS + Sub seconds value + 0 + 15 + + + + + SR + SR + RTC status register + 0x50 + 0x20 + read-only + 0x00000000 + + + ALRAF + ALRAF + 0 + 1 + + + ALRBF + ALRBF + 1 + 1 + + + WUTF + WUTF + 2 + 1 + + + TSF + TSF + 3 + 1 + + + TSOVF + TSOVF + 4 + 1 + + + ITSF + ITSF + 5 + 1 + + + SSRUF + SSRUF + 6 + 1 + + + + + MISR + MISR + RTC non-secure masked interrupt status + register + 0x54 + 0x20 + read-only + 0x00000000 + + + ALRAMF + ALRAMF + 0 + 1 + + + ALRBMF + ALRBMF + 1 + 1 + + + WUTMF + WUTMF + 2 + 1 + + + TSMF + TSMF + 3 + 1 + + + TSOVMF + TSOVMF + 4 + 1 + + + ITSMF + ITSMF + 5 + 1 + + + SSRUMF + SSRUMF + 6 + 1 + + + + + SMISR + SMISR + RTC secure masked interrupt status + register + 0x58 + 0x20 + read-only + 0x00000000 + + + ALRAMF + ALRAMF + 0 + 1 + + + ALRBMF + ALRBMF + 1 + 1 + + + WUTMF + WUTMF + 2 + 1 + + + TSMF + TSMF + 3 + 1 + + + TSOVMF + TSOVMF + 4 + 1 + + + ITSMF + ITSMF + 5 + 1 + + + SSRUMF + SSRUMF + 6 + 1 + + + + + SCR + SCR + RTC status clear register + 0x5C + 0x20 + write-only + 0x00000000 + + + CALRAF + CALRAF + 0 + 1 + + + CALRBF + CALRBF + 1 + 1 + + + CWUTF + CWUTF + 2 + 1 + + + CTSF + CTSF + 3 + 1 + + + CTSOVF + CTSOVF + 4 + 1 + + + CITSF + CITSF + 5 + 1 + + + CSSRUF + CSSRUF + 6 + 1 + + + + + ALRABINR + ALRABINR + RTC alarm A binary mode register + 0x70 + 0x20 + read-write + 0x00000000 + + + SS + Synchronous counter alarm value in Binary mode + 0 + 32 + + + + + ALRBBINR + ALRBBINR + RTC alarm B binary mode register + 0x74 + 0x20 + read-write + 0x00000000 + + + SS + Synchronous counter alarm value in Binary mode + 0 + 32 + + + + + + + SEC_RTC + DCB->DSCSR->CDS == 0 + 0x56007800 + + + SAES + Secure AES coprocessor + SAES + 0x420C0C00 + + 0x0 + 0x400 + registers + + + SAES + Secure AES + 28 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + IPRST + IPRST + 31 + 1 + + + KEYSEL + KEYSEL + 28 + 3 + + + KSHAREID + KSHAREID + 26 + 2 + + + KMOD + KMOD + 24 + 2 + + + KEYPROT + KEYPROT + 19 + 1 + + + KEYSIZE + KEYSIZE + 18 + 1 + + + DMAOUTEN + DMAOUTEN + 12 + 1 + + + DMAINEN + DMAINEN + 11 + 1 + + + CHMOD + CHMOD + 5 + 2 + + + MODE + MODE + 3 + 2 + + + DATATYPE + DATATYPE + 1 + 2 + + + EN + SAES enable + 0 + 1 + + + + + SR + SR + status register + 0x4 + 0x20 + read-only + 0x00000000 + + + KEYVALID + Key Valid flag + 7 + 1 + + + BUSY + BUSY + 3 + 1 + + + WRERR + Write error flag + 2 + 1 + + + RDERR + Read error flag + 1 + 1 + + + CCF + Computation complete flag + 0 + 1 + + + + + DINR + DINR + data input register + 0x8 + 0x20 + write-only + 0x00000000 + + + DIN + Input data word + 0 + 32 + + + + + DOUTR + DOUTR + data output register + 0xC + 0x20 + read-only + 0x00000000 + + + DOUT + Output data word + 0 + 32 + + + + + KEYR0 + KEYR0 + key register 0 + 0x10 + 0x20 + write-only + 0x00000000 + + + KEY + Cryptographic key, bits [31:0] + 0 + 32 + + + + + KEYR1 + KEYR1 + key register 1 + 0x14 + 0x20 + write-only + 0x00000000 + + + KEY + Cryptographic key, bits [63:32] + 0 + 32 + + + + + KEYR2 + KEYR2 + key register 2 + 0x18 + 0x20 + write-only + 0x00000000 + + + KEYR + Cryptographic key, bits [95:64] + 0 + 32 + + + + + KEYR3 + KEYR3 + key register 3 + 0x1C + 0x20 + write-only + 0x00000000 + + + SAES_KEYR3 + Cryptographic key, bits [127:96] + 0 + 32 + + + + + IVR0 + IVR0 + initialization vector register 0 + 0x20 + 0x20 + read-write + 0x00000000 + + + IVI + Initialization vector input, bits [31:0] + 0 + 32 + + + + + IVR1 + IVR1 + initialization vector register 1 + 0x24 + 0x20 + read-write + 0x00000000 + + + IVI + Initialization vector input, bits [63:32] + 0 + 32 + + + + + IVR2 + IVR2 + initialization vector register 2 + 0x28 + 0x20 + read-write + 0x00000000 + + + IVI + Initialization vector input, bits [95:64] + 0 + 32 + + + + + IVR3 + IVR3 + initialization vector register 3 + 0x2C + 0x20 + read-write + 0x00000000 + + + IVI + Initialization vector input, bits [127:96] + 0 + 32 + + + + + KEYR4 + KEYR4 + key register 4 + 0x30 + 0x20 + write-only + 0x00000000 + + + KEY + Cryptographic key, bits [159:128] + 0 + 32 + + + + + KEYR5 + KEYR5 + key register 5 + 0x34 + 0x20 + write-only + 0x00000000 + + + KEY + Cryptographic key, bits [191:160] + 0 + 32 + + + + + KEYR6 + KEYR6 + key register 6 + 0x38 + 0x20 + write-only + 0x00000000 + + + KEY + Cryptographic key, bits [223:192] + 0 + 32 + + + + + KEYR7 + KEYR7 + key register 7 + 0x3C + 0x20 + write-only + 0x00000000 + + + KEY + Cryptographic key, bits [255:224] + 0 + 32 + + + + + DPACFGR + DPACFGR + configuration register + 0x100 + 0x20 + 0x00000008 + + + CONFIGLOCK + CONFIGLOCK + 31 + 1 + read-only + + + TRIMCFG + TRIMCFG + 3 + 2 + read-write + + + RESEED + RESEED + 2 + 1 + read-write + + + REDCFG + REDCFG + 1 + 1 + read-write + + + + + IER + IER + interrupt enable register + 0x300 + 0x20 + read-write + 0x00000000 + + + RNGEIE + RNGEIE + 3 + 1 + + + KEIE + Key error interrupt enable + 2 + 1 + + + RWEIE + Read or write error interrupt enable + 1 + 1 + + + CCFIE + Computation complete flag interrupt enable + 0 + 1 + + + + + ISR + ISR + interrupt status register + 0x304 + 0x20 + read-only + 0x00000000 + + + RNGEIF + RNGEIF + 3 + 1 + + + KEIF + Key error interrupt flag + 2 + 1 + + + RWEIF + Read or write error interrupt flag + 1 + 1 + + + CCF + Computation complete flag + 0 + 1 + + + + + ICR + ICR + interrupt clear register + 0x308 + 0x20 + write-only + 0x00000000 + + + RNGEIF + RNGEIF + 3 + 1 + + + KEIF + Key error interrupt flag clear + 2 + 1 + + + RWEIF + Read or write error interrupt flag clear + 1 + 1 + + + CCF + Computation complete flag clear + 0 + 1 + + + + + + + SEC_SAES + DCB->DSCSR->CDS == 0 + 0x520C0C00 + + + SAI1 + Serial audio interface + SAI + 0x40015400 + + 0x0 + 0x400 + registers + + + SAI1 + SAI1 global interrupt + 090 + + + + GCR + GCR + Global configuration register + 0x0 + 0x20 + read-write + 0x00000000 + + + SYNCIN + Synchronization inputs + 0 + 2 + + + SYNCOUT + Synchronization outputs + 4 + 2 + + + + + ACR1 + ACR1 + A Configuration register 1 + 0x4 + 0x20 + read-write + 0x00000040 + + + MCKEN + MCKEN + 27 + 1 + + + OSR + OSR + 26 + 1 + + + MCKDIV + Master clock divider + 20 + 6 + + + NODIV + No divider + 19 + 1 + + + DMAEN + DMA enable + 17 + 1 + + + SAIAEN + Audio block A enable + 16 + 1 + + + OUTDRIV + Output drive + 13 + 1 + + + MONO + Mono mode + 12 + 1 + + + SYNCEN + Synchronization enable + 10 + 2 + + + CKSTR + Clock strobing edge + 9 + 1 + + + LSBFIRST + Least significant bit + first + 8 + 1 + + + DS + Data size + 5 + 3 + + + PRTCFG + Protocol configuration + 2 + 2 + + + MODE + Audio block mode + 0 + 2 + + + + + BCR1 + BCR1 + B Configuration register 1 + 0x24 + 0x20 + read-write + 0x00000040 + + + MCKEN + MCKEN + 27 + 1 + + + OSR + OSR + 26 + 1 + + + MCKDIV + Master clock divider + 20 + 6 + + + NODIV + No divider + 19 + 1 + + + DMAEN + DMA enable + 17 + 1 + + + SAIAEN + Audio block A enable + 16 + 1 + + + OUTDRIV + Output drive + 13 + 1 + + + MONO + Mono mode + 12 + 1 + + + SYNCEN + Synchronization enable + 10 + 2 + + + CKSTR + Clock strobing edge + 9 + 1 + + + LSBFIRST + Least significant bit + first + 8 + 1 + + + DS + Data size + 5 + 3 + + + PRTCFG + Protocol configuration + 2 + 2 + + + MODE + Audio block mode + 0 + 2 + + + + + ACR2 + ACR2 + A Configuration register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + COMP + Companding mode + 14 + 2 + + + CPL + Complement bit + 13 + 1 + + + MUTECN + Mute counter + 7 + 6 + + + MUTEVAL + Mute value + 6 + 1 + + + MUTE + Mute + 5 + 1 + + + TRIS + Tristate management on data + line + 4 + 1 + + + FFLUSH + FIFO flush + 3 + 1 + + + FTH + FIFO threshold + 0 + 3 + + + + + BCR2 + BCR2 + B Configuration register 2 + 0x28 + 0x20 + read-write + 0x00000000 + + + COMP + Companding mode + 14 + 2 + + + CPL + Complement bit + 13 + 1 + + + MUTECN + Mute counter + 7 + 6 + + + MUTEVAL + Mute value + 6 + 1 + + + MUTE + Mute + 5 + 1 + + + TRIS + Tristate management on data + line + 4 + 1 + + + FFLUSH + FIFO flush + 3 + 1 + + + FTH + FIFO threshold + 0 + 3 + + + + + AFRCR + AFRCR + A frame configuration register + 0xC + 0x20 + 0x00000007 + + + FSOFF + Frame synchronization + offset + 18 + 1 + read-write + + + FSPOL + Frame synchronization + polarity + 17 + 1 + read-write + + + FSDEF + Frame synchronization + definition + 16 + 1 + read-only + + + FSALL + Frame synchronization active level + length + 8 + 7 + read-write + + + FRL + Frame length + 0 + 8 + read-write + + + + + BFRCR + BFRCR + B frame configuration register + 0x2C + 0x20 + 0x00000007 + + + FSOFF + Frame synchronization + offset + 18 + 1 + read-write + + + FSPOL + Frame synchronization + polarity + 17 + 1 + read-write + + + FSDEF + Frame synchronization + definition + 16 + 1 + read-only + + + FSALL + Frame synchronization active level + length + 8 + 7 + read-write + + + FRL + Frame length + 0 + 8 + read-write + + + + + ASLOTR + ASLOTR + A Slot register + 0x10 + 0x20 + read-write + 0x00000000 + + + SLOTEN + Slot enable + 16 + 16 + + + NBSLOT + Number of slots in an audio + frame + 8 + 4 + + + SLOTSZ + Slot size + 6 + 2 + + + FBOFF + First bit offset + 0 + 5 + + + + + BSLOTR + BSLOTR + B Slot register + 0x30 + 0x20 + read-write + 0x00000000 + + + SLOTEN + Slot enable + 16 + 16 + + + NBSLOT + Number of slots in an audio + frame + 8 + 4 + + + SLOTSZ + Slot size + 6 + 2 + + + FBOFF + First bit offset + 0 + 5 + + + + + AIM + AIM + A Interrupt mask register + 0x14 + 0x20 + read-write + 0x00000000 + + + LFSDETIE + Late frame synchronization detection + interrupt enable + 6 + 1 + + + AFSDETIE + Anticipated frame synchronization + detection interrupt enable + 5 + 1 + + + CNRDYIE + Codec not ready interrupt + enable + 4 + 1 + + + FREQIE + FIFO request interrupt + enable + 3 + 1 + + + WCKCFGIE + Wrong clock configuration interrupt + enable + 2 + 1 + + + MUTEDETIE + Mute detection interrupt + enable + 1 + 1 + + + OVRUDRIE + Overrun/underrun interrupt + enable + 0 + 1 + + + + + BIM + BIM + B Interrupt mask register + 0x34 + 0x20 + read-write + 0x00000000 + + + LFSDETIE + Late frame synchronization detection + interrupt enable + 6 + 1 + + + AFSDETIE + Anticipated frame synchronization + detection interrupt enable + 5 + 1 + + + CNRDYIE + Codec not ready interrupt + enable + 4 + 1 + + + FREQIE + FIFO request interrupt + enable + 3 + 1 + + + WCKCFGIE + Wrong clock configuration interrupt + enable + 2 + 1 + + + MUTEDETIE + Mute detection interrupt + enable + 1 + 1 + + + OVRUDRIE + Overrun/underrun interrupt + enable + 0 + 1 + + + + + ASR + ASR + A Status register + 0x18 + 0x20 + read-only + 0x00000008 + + + FLVL + FIFO level threshold + 16 + 3 + + + LFSDET + Late frame synchronization + detection + 6 + 1 + + + AFSDET + Anticipated frame synchronization + detection + 5 + 1 + + + CNRDY + Codec not ready + 4 + 1 + + + FREQ + FIFO request + 3 + 1 + + + WCKCFG + Wrong clock configuration flag. This bit + is read only + 2 + 1 + + + MUTEDET + Mute detection + 1 + 1 + + + OVRUDR + Overrun / underrun + 0 + 1 + + + + + BSR + BSR + B Status register + 0x38 + 0x20 + read-only + 0x00000008 + + + FLVL + FIFO level threshold + 16 + 3 + + + LFSDET + Late frame synchronization + detection + 6 + 1 + + + AFSDET + Anticipated frame synchronization + detection + 5 + 1 + + + CNRDY + Codec not ready + 4 + 1 + + + FREQ + FIFO request + 3 + 1 + + + WCKCFG + Wrong clock configuration + flag + 2 + 1 + + + MUTEDET + Mute detection + 1 + 1 + + + OVRUDR + Overrun / underrun + 0 + 1 + + + + + ACLRFR + ACLRFR + A Clear flag register + 0x1C + 0x20 + write-only + 0x00000000 + + + CLFSDET + Clear late frame synchronization + detection flag + 6 + 1 + + + CAFSDET + Clear anticipated frame synchronization + detection flag + 5 + 1 + + + CCNRDY + Clear codec not ready flag + 4 + 1 + + + CWCKCFG + Clear wrong clock configuration + flag + 2 + 1 + + + CMUTEDET + Mute detection flag + 1 + 1 + + + COVRUDR + Clear overrun / underrun + 0 + 1 + + + + + BCLRFR + BCLRFR + B Clear flag register + 0x3C + 0x20 + write-only + 0x00000000 + + + CLFSDET + Clear late frame synchronization + detection flag + 6 + 1 + + + CAFSDET + Clear anticipated frame synchronization + detection flag + 5 + 1 + + + CCNRDY + Clear codec not ready flag + 4 + 1 + + + CWCKCFG + Clear wrong clock configuration + flag + 2 + 1 + + + CMUTEDET + Mute detection flag + 1 + 1 + + + COVRUDR + Clear overrun / underrun + 0 + 1 + + + + + ADR + ADR + A Data register + 0x20 + 0x20 + read-write + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + BDR + BDR + B Data register + 0x40 + 0x20 + read-write + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + PDMCR + PDMCR + PDM control register + 0x44 + 0x20 + read-write + 0x00000000 + + + PDMEN + PDM enable + 0 + 1 + + + MICNBR + MICNBR + 4 + 2 + + + CKEN1 + Clock enable of bitstream clock number + 1 + 8 + 1 + + + CKEN2 + CKEN2 + 9 + 1 + + + CKEN3 + CKEN3 + 10 + 1 + + + CKEN4 + CKEN4 + 11 + 1 + + + + + PDMDLY + PDMDLY + PDM delay register + 0x48 + 0x20 + read-write + 0x00000000 + + + DLYM1L + Delay line adjust for first microphone + of pair 1 + 0 + 3 + + + DLYM1R + Delay line adjust for second microphone + of pair 1 + 4 + 3 + + + DLYM2L + Delay line for first microphone of pair + 2 + 8 + 3 + + + DLYM2R + Delay line for second microphone of pair + 2 + 12 + 3 + + + DLYM3L + DLYM3L + 16 + 3 + + + DLYM3R + DLYM3R + 20 + 3 + + + DLYM4L + DLYM4L + 24 + 3 + + + DLYM4R + DLYM4R + 28 + 3 + + + + + + + SEC_SAI1 + DCB->DSCSR->CDS == 0 + 0x50015400 + + + SAI2 + 0x40015800 + + SAI2 + SAI2 global interrupt + 091 + + + + SEC_SAI2 + DCB->DSCSR->CDS == 0 + 0x50015800 + + + SDMMC1 + Secure digital input/output MultiMediaCard interface + SDMMC + 0x420C8000 + + 0x0 + 0x400 + registers + + + SDMMC1 + SDMMC1 global interrupt + 78 + + + + POWER + POWER + power control register + 0x0 + 0x20 + read-write + 0x00000000 + + + PWRCTRL + SDMMC state control bits + 0 + 2 + + + VSWITCH + Voltage switch sequence start + 2 + 1 + + + VSWITCHEN + Voltage switch procedure enable + 3 + 1 + + + DIRPOL + Data and command direction signals polarity selection + 4 + 1 + + + + + CLKCR + CLKCR + clock control register + 0x4 + 0x20 + read-write + 0x00000000 + + + SELCLKRX + Receive clock selection + 20 + 2 + + + BUSSPEED + Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50,DDR50, SDR104 + 19 + 1 + + + DDR + Data rate signaling selection + 18 + 1 + + + HWFC_EN + HW Flow Control enable + 17 + 1 + + + NEGEDGE + SDIO_CK dephasing selection bit + 16 + 1 + + + WIDBUS + Wide bus mode enable bit + 14 + 2 + + + PWRSAV + Power saving configuration bit + 12 + 1 + + + CLKDIV + Clock divide factor + 0 + 10 + + + + + ARGR + ARGR + argument register + 0x8 + 0x20 + read-write + 0x00000000 + + + CMDARG + Command argument + 0 + 32 + + + + + CMDR + CMDR + command register + 0xC + 0x20 + read-write + 0x00000000 + + + CMDSUSPEND + The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end + 16 + 1 + + + BOOTEN + Enable boot mode procedure + 15 + 1 + + + BOOTMODE + Select the boot mode procedure to be used + 14 + 1 + + + DTHOLD + Hold new data block transmission and reception in the DPSM + 13 + 1 + + + CPSMEN + Command path state machine (CPSM) Enable bit + 12 + 1 + + + WAITPEND + CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM + 11 + 1 + + + WAITINT + CPSM waits for interrupt request + 10 + 1 + + + WAITRESP + Wait for response bits + 8 + 2 + + + CMDSTOP + The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM + 7 + 1 + + + CMDTRANS + The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM + 6 + 1 + + + CMDINDEX + Command index + 0 + 6 + + + + + RESPCMDR + RESPCMD + command response register + 0x10 + 0x20 + read-only + 0x00000000 + + + RESPCMD + Response command index + 0 + 6 + + + + + RESP1 + RESP1 + response 1 register + 0x14 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS1 + CARDSTATUS1 + 0 + 32 + + + + + RESP2 + RESP2 + response 2 register + 0x18 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS2 + CARDSTATUS2 + 0 + 32 + + + + + RESP3 + RESP3 + response 3 register + 0x1C + 0x20 + read-only + 0x00000000 + + + CARDSTATUS3 + CARDSTATUS3 + 0 + 32 + + + + + RESP4 + RESP4 + response 4 register + 0x20 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS4 + CARDSTATUS4 + 0 + 32 + + + + + DTIMER + DTIMER + data timer register + 0x24 + 0x20 + read-write + 0x00000000 + + + DATATIME + Data and R1b busy timeout period + 0 + 32 + + + + + DLENR + DLENR + data length register + 0x28 + 0x20 + read-write + 0x00000000 + + + DATALENGTH + Data length value + 0 + 25 + + + + + DCTRL + DCTRL + data control register + 0x2C + 0x20 + read-write + 0x00000000 + + + FIFORST + FIFO reset, will flush any remaining data + 13 + 1 + + + BOOTACKEN + Enable the reception of the boot acknowledgment + 12 + 1 + + + SDIOEN + SD I/O enable functions + 11 + 1 + + + RWMOD + Read wait mode + 10 + 1 + + + RWSTOP + Read wait stop + 9 + 1 + + + RWSTART + Read wait start + 8 + 1 + + + DBLOCKSIZE + Data block size + 4 + 4 + + + DTMODE + Data transfer mode selection + 2 + 2 + + + DTDIR + Data transfer direction selection + 1 + 1 + + + DTEN + DTEN + 0 + 1 + + + + + DCNTR + DCNTR + data counter register + 0x30 + 0x20 + read-only + 0x00000000 + + + DATACOUNT + Data count value + 0 + 25 + + + + + STAR + STAR + status register + 0x34 + 0x20 + read-only + 0x00000000 + + + IDMABTC + IDMA buffer transfer complete + 28 + 1 + + + IDMATE + IDMA transfer error + 27 + 1 + + + CKSTOP + SDMMC_CK stopped in Voltage switch procedure + 26 + 1 + + + VSWEND + Voltage switch critical timing section completion + 25 + 1 + + + ACKTIMEOUT + Boot acknowledgment timeout + 24 + 1 + + + ACKFAIL + Boot acknowledgment received (boot acknowledgment check fail) + 23 + 1 + + + SDIOIT + SDIO interrupt received + 22 + 1 + + + BUSYD0END + end of SDMMC_D0 Busy following a CMD response detected + 21 + 1 + + + BUSYD0 + Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response + 20 + 1 + + + RXFIFOE + Receive FIFO empty + 19 + 1 + + + TXFIFOE + Transmit FIFO empty + 18 + 1 + + + RXFIFOF + Receive FIFO full + 17 + 1 + + + TXFIFOF + Transmit FIFO full + 16 + 1 + + + RXFIFOHF + Receive FIFO half full + 15 + 1 + + + TXFIFOHE + Transmit FIFO half empty + 14 + 1 + + + CPSMACT + Command path state machine active, i.e. not in Idle state + 13 + 1 + + + DPSMACT + Data path state machine active, i.e. not in Idle state + 12 + 1 + + + DABORT + Data transfer aborted by CMD12 + 11 + 1 + + + DBCKEND + Data block sent/received + 10 + 1 + + + DHOLD + Data transfer Hold + 9 + 1 + + + DATAEND + Data transfer ended correctly + 8 + 1 + + + CMDSENT + Command sent (no response required) + 7 + 1 + + + CMDREND + Command response received (CRC check passed, or no CRC) + 6 + 1 + + + RXOVERR + Received FIFO overrun error (masked by hardware when IDMA is enabled) + 5 + 1 + + + TXUNDERR + Transmit FIFO underrun error (masked by hardware when IDMA is enabled) + 4 + 1 + + + DTIMEOUT + Data timeout + 3 + 1 + + + CTIMEOUT + Command response timeout + 2 + 1 + + + DCRCFAIL + Data block sent/received (CRC check failed) + 1 + 1 + + + CCRCFAIL + Command response received (CRC check failed) + 0 + 1 + + + + + ICR + ICR + interrupt clear register + 0x38 + 0x20 + read-write + 0x00000000 + + + IDMABTCC + IDMA buffer transfer complete clear bit + 28 + 1 + + + IDMATEC + IDMA transfer error clear bit + 27 + 1 + + + CKSTOPC + CKSTOP flag clear bit + 26 + 1 + + + VSWENDC + VSWEND flag clear bit + 25 + 1 + + + ACKTIMEOUTC + ACKTIMEOUT flag clear bit + 24 + 1 + + + ACKFAILC + ACKFAIL flag clear bit + 23 + 1 + + + SDIOITC + SDIOIT flag clear bit + 22 + 1 + + + BUSYD0ENDC + BUSYD0END flag clear bit + 21 + 1 + + + DABORTC + DABORT flag clear bit + 11 + 1 + + + DBCKENDC + DBCKEND flag clear bit + 10 + 1 + + + DHOLDC + DHOLD flag clear bit + 9 + 1 + + + DATAENDC + DATAEND flag clear bit + 8 + 1 + + + CMDSENTC + CMDSENT flag clear bit + 7 + 1 + + + CMDRENDC + CMDREND flag clear bit + 6 + 1 + + + RXOVERRC + RXOVERR flag clear bit + 5 + 1 + + + TXUNDERRC + TXUNDERR flag clear bit + 4 + 1 + + + DTIMEOUTC + DTIMEOUT flag clear bit + 3 + 1 + + + CTIMEOUTC + CTIMEOUT flag clear bit + 2 + 1 + + + DCRCFAILC + DCRCFAIL flag clear bit + 1 + 1 + + + CCRCFAILC + CCRCFAIL flag clear bit + 0 + 1 + + + + + MASKR + MASKR + mask register + 0x3C + 0x20 + read-write + 0x00000000 + + + IDMABTCIE + IDMA buffer transfer complete interrupt enable + 28 + 1 + + + CKSTOPIE + Voltage Switch clock stopped interrupt enable + 26 + 1 + + + VSWENDIE + Voltage switch critical timing section completion interrupt enable + 25 + 1 + + + ACKTIMEOUTIE + Acknowledgment timeout interrupt enable + 24 + 1 + + + ACKFAILIE + Acknowledgment Fail interrupt enable + 23 + 1 + + + SDIOITIE + SDIO mode interrupt received interrupt enable + 22 + 1 + + + BUSYD0ENDIE + BUSYD0END interrupt enable + 21 + 1 + + + TXFIFOEIE + Tx FIFO empty interrupt enable + 18 + 1 + + + RXFIFOFIE + Rx FIFO full interrupt enable + 17 + 1 + + + RXFIFOHFIE + Rx FIFO half full interrupt enable + 15 + 1 + + + TXFIFOHEIE + Tx FIFO half empty interrupt enable + 14 + 1 + + + DABORTIE + Data transfer aborted interrupt enable + 11 + 1 + + + DBCKENDIE + Data block end interrupt enable + 10 + 1 + + + DHOLDIE + Data hold interrupt enable + 9 + 1 + + + DATAENDIE + Data end interrupt enable + 8 + 1 + + + CMDSENTIE + Command sent interrupt enable + 7 + 1 + + + CMDRENDIE + Command response received interrupt enable + 6 + 1 + + + RXOVERRIE + Rx FIFO overrun error interrupt enable + 5 + 1 + + + TXUNDERRIE + Tx FIFO underrun error interrupt enable + 4 + 1 + + + DTIMEOUTIE + Data timeout interrupt enable + 3 + 1 + + + CTIMEOUTIE + Command timeout interrupt enable + 2 + 1 + + + DCRCFAILIE + Data CRC fail interrupt enable + 1 + 1 + + + CCRCFAILIE + Command CRC fail interrupt enable + 0 + 1 + + + + + ACKTIMER + ACKTIMER + acknowledgment timer register + 0x040 + 0x20 + read-write + 0x00000000 + + + ACKTIME + Boot acknowledgment timeout period + 0 + 25 + + + + + FIFOR0 + FIFOR0 + data FIFO register 0 + 0x80 + 0x20 + read-write + 0x00000000 + + + FIFODATA + Receive and transmit FIFO data + 0 + 32 + + + + + FIFOR1 + FIFOR1 + data FIFO register 1 + 0x84 + 0x20 + read-write + 0x00000000 + + + FIFODATA + Receive and transmit FIFO data + 0 + 32 + + + + + FIFOR2 + FIFOR2 + data FIFO register 2 + 0x88 + 0x20 + read-write + 0x00000000 + + + FIFODATA + Receive and transmit FIFO data + 0 + 32 + + + + + FIFOR3 + FIFOR3 + data FIFO register 3 + 0x8C + 0x20 + read-write + 0x00000000 + + + FIFODATA + Receive and transmit FIFO data + 0 + 32 + + + + + FIFOR4 + FIFOR4 + data FIFO register 4 + 0x90 + 0x20 + read-write + 0x00000000 + + + FIFODATA + Receive and transmit FIFO data + 0 + 32 + + + + + FIFOR5 + FIFOR5 + data FIFO register 5 + 0x94 + 0x20 + read-write + 0x00000000 + + + FIFODATA + Receive and transmit FIFO data + 0 + 32 + + + + + FIFOR6 + FIFOR6 + data FIFO register 6 + 0x98 + 0x20 + read-write + 0x00000000 + + + FIFODATA + Receive and transmit FIFO data + 0 + 32 + + + + + FIFOR7 + FIFOR7 + data FIFO register 7 + 0x9C + 0x20 + read-write + 0x00000000 + + + FIFODATA + Receive and transmit FIFO data + 0 + 32 + + + + + FIFOR8 + FIFOR8 + data FIFO register 8 + 0xA0 + 0x20 + read-write + 0x00000000 + + + FIFODATA + Receive and transmit FIFO data + 0 + 32 + + + + + FIFOR9 + FIFOR9 + data FIFO register 9 + 0xA4 + 0x20 + read-write + 0x00000000 + + + FIFODATA + Receive and transmit FIFO data + 0 + 32 + + + + + FIFOR10 + FIFOR10 + data FIFO register 10 + 0xA8 + 0x20 + read-write + 0x00000000 + + + FIFODATA + Receive and transmit FIFO data + 0 + 32 + + + + + FIFOR11 + FIFOR11 + data FIFO register 11 + 0xAC + 0x20 + read-write + 0x00000000 + + + FIFODATA + Receive and transmit FIFO data + 0 + 32 + + + + + FIFOR12 + FIFOR12 + data FIFO register 12 + 0xB0 + 0x20 + read-write + 0x00000000 + + + FIFODATA + Receive and transmit FIFO data + 0 + 32 + + + + + FIFOR13 + FIFOR13 + data FIFO register 13 + 0xB4 + 0x20 + read-write + 0x00000000 + + + FIFODATA + Receive and transmit FIFO data + 0 + 32 + + + + + FIFOR14 + FIFOR14 + data FIFO register 14 + 0xB8 + 0x20 + read-write + 0x00000000 + + + FIFODATA + Receive and transmit FIFO data + 0 + 32 + + + + + FIFOR15 + FIFOR15 + data FIFO register 15 + 0xBC + 0x20 + read-write + 0x00000000 + + + FIFODATA + Receive and transmit FIFO data + 0 + 32 + + + + + SDMMC_IDMACTRLR + SDMMC_IDMACTRLR + DMA control register + 0x50 + 0x20 + read-write + 0x00000000 + + + IDMAEN + IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). + 0 + 1 + + + IDMABMODE + Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). + 1 + 1 + + + + + SDMMC_IDMABSIZER + SDMMC_IDMABSIZER + buffer size register + 0x54 + 0x20 + read-write + 0x00000000 + + + IDMABNDT + Number of bytes per buffer + 5 + 12 + + + + + SDMMC_IDMABASER + SDMMC_IDMABASER + buffer base address register + 0x58 + 0x20 + read-write + 0x00000000 + + + IDMABASE + Buffer memory base address bits [31:2], shall be word aligned (bit [1:0] are always 0 and read only) + 0 + 32 + + + + + SDMMC_IDMALAR + SDMMC_IDMALAR + linked list address register + 0x064 + 0x20 + read-write + 0x00000000 + + + ULA + Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode) + 31 + 1 + + + ULS + Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1) + 30 + 1 + + + ABR + Acknowledge linked list buffer ready + 29 + 1 + + + IDMALA + Acknowledge linked list buffer ready + 2 + 14 + + + + + SDMMC_IDMABAR + SDMMC_IDMABAR + linked list memory base register + 0x068 + 0x20 + read-write + 0x00000000 + + + IDMABA + Word aligned Linked list memory base address + 2 + 30 + + + + + + + SEC_SDMMC1 + DCB->DSCSR->CDS == 0 + 0x520C8000 + + + SDMMC2 + 0x420C8C00 + + SDMMC2 + SDMMC2 global interrupt + 79 + + + + SEC_SDMMC2 + DCB->DSCSR->CDS == 0 + 0x520C8C00 + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global interrupt + 059 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + 0x0000 + + + IOLOCK + IOLOCK + 16 + 1 + read-write + + + TCRCINI + TCRCINI + 15 + 1 + read-write + + + RCRCINI + RCRCINI + 14 + 1 + read-write + + + CRC33_17 + CRC33_17 + 13 + 1 + read-write + + + SSI + SSI + 12 + 1 + read-write + + + HDDIR + HDDIR + 11 + 1 + read-write + + + CSUSP + CSUSP + 10 + 1 + write-only + + + CSTART + CSTART + 9 + 1 + read-write + + + MASRX + MASRX + 8 + 1 + read-write + + + SPE + SPE + 0 + 1 + read-write + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + TSIZE + TSIZE + 0 + 16 + + + + + CFG1 + CFG1 + configuration register 1 + 0x8 + 0x20 + read-write + 0x00070007 + + + BPASS + BPASS + 31 + 1 + + + MBR + Master baud rate + 28 + 3 + + + CRCEN + Hardware CRC computation + enable + 22 + 1 + + + CRCSIZE + Length of CRC frame to be transacted and + compared + 16 + 5 + + + TXDMAEN + Tx DMA stream enable + 15 + 1 + + + RXDMAEN + Rx DMA stream enable + 14 + 1 + + + UDRCFG + Behavior of slave transmitter at + underrun condition + 9 + 1 + + + FTHVL + threshold level + 5 + 4 + + + DSIZE + Number of bits in at single SPI data + frame + 0 + 5 + + + + + CFG2 + CFG2 + configuration register 2 + 0xC + 0x20 + read-write + 0x00000000 + + + AFCNTR + Alternate function GPIOs + control + 31 + 1 + + + SSOM + SS output management in master + mode + 30 + 1 + + + SSOE + SS output enable + 29 + 1 + + + SSIOP + SS input/output polarity + 28 + 1 + + + SSM + Software management of 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Capture/Compare 4 interrupt + enable + 4 + 1 + + + CC3IE + Capture/Compare 3 interrupt + enable + 3 + 1 + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + TERRF + Transition error interrupt flag + 23 + 1 + + + IERRF + Index error interrupt flag + 22 + 1 + + + DIRF + Direction change interrupt flag + 21 + 1 + + + IDXF + Index interrupt flag + 20 + 1 + + + CC4OF + Capture/Compare 4 overcapture flag + 12 + 1 + + + CC3OF + Capture/Compare 3 overcapture + flag + 11 + 1 + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + CC4IF + Capture/Compare 4 interrupt + flag + 4 + 1 + + + CC3IF + Capture/Compare 3 interrupt + flag + 3 + 1 + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + TG + Trigger generation + 6 + 1 + + + CC4G + Capture/compare 4 + generation + 4 + 1 + + + CC3G + Capture/compare 3 + generation + 3 + 1 + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2M_bit3 + Output Compare 2 mode - bit + 3 + 24 + 1 + + + OC1M_bit3 + Output Compare 1 mode - bit + 3 + 16 + 1 + + + OC2CE + Output compare 2 clear + enable + 15 + 1 + + + OC2M + Output compare 2 mode + 12 + 3 + + + OC2PE + Output compare 2 preload + enable + 11 + 1 + + + OC2FE + Output compare 2 fast + enable + 10 + 1 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + OC1CE + Output compare 1 clear + enable + 7 + 1 + + + OC1M + Output compare 1 mode + 4 + 3 + + + OC1PE + Output compare 1 preload + enable + 3 + 1 + + + OC1FE + Output compare 1 fast + enable + 2 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/compare 2 + selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR2_Output + CCMR2_Output + capture/compare mode register 2 (output + mode) + 0x1C + 0x20 + read-write + 0x00000000 + + + OC4M_bit3 + Output Compare 2 mode - bit + 3 + 24 + 1 + + + OC3M_bit3 + Output Compare 1 mode - bit + 3 + 16 + 1 + + + OC4CE + Output compare 4 clear + enable + 15 + 1 + + + OC4M + Output compare 4 mode + 12 + 3 + + + OC4PE + Output compare 4 preload + enable + 11 + 1 + + + OC4FE + Output compare 4 fast + enable + 10 + 1 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + OC3CE + Output compare 3 clear + enable + 7 + 1 + + + OC3M + Output compare 3 mode + 4 + 3 + + + OC3PE + Output compare 3 preload + enable + 3 + 1 + + + OC3FE + Output compare 3 fast + enable + 2 + 1 + + + CC3S + Capture/Compare 3 + selection + 0 + 2 + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (input + mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + IC3F + Input capture 3 filter + 4 + 4 + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + CC3S + Capture/Compare 3 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC4NP + Capture/Compare 4 output + Polarity + 15 + 1 + + + CC4P + Capture/Compare 3 output + Polarity + 13 + 1 + + + CC4E + Capture/Compare 4 output + enable + 12 + 1 + + + CC3NP + Capture/Compare 3 output + Polarity + 11 + 1 + + + CC3P + Capture/Compare 3 output + Polarity + 9 + 1 + + + CC3E + Capture/Compare 3 output + enable + 8 + 1 + + + CC2NP + Capture/Compare 2 output + Polarity + 7 + 1 + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT_H + Most significant part counter value (on + TIM2 and TIM5) + 16 + 15 + + + CNT_L + Least significant part of counter + value + 0 + 16 + + + CNT_bit31 + Most significant bit of counter value + (on TIM2 and TIM5) + 31 + 1 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0xFFFFFFFF + + + ARR_H + High Auto-reload value (TIM2 + only) + 16 + 16 + + + ARR_L + Low Auto-reload value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1_H + High Capture/Compare 1 value (TIM2 + only) + 16 + 16 + + + CCR1_L + Low Capture/Compare 1 + value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2_H + High Capture/Compare 2 value (TIM2 + only) + 16 + 16 + + + CCR2_L + Low Capture/Compare 2 + value + 0 + 16 + + + + + CCR3 + CCR3 + capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + CCR3_H + High Capture/Compare value (TIM2 + only) + 16 + 16 + + + CCR3_L + Low Capture/Compare value + 0 + 16 + + + + + CCR4 + CCR4 + capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + + + CCR4_H + High Capture/Compare value (TIM2 + only) + 16 + 16 + + + CCR4_L + Low Capture/Compare value + 0 + 16 + + + + + ECR + ECR + DMA address for full transfer + 0x58 + 0x20 + read-write + 0x0000 + + + PWPRSC + Pulse width prescaler + 24 + 3 + + + PW + Pulse width + 16 + 8 + + + IPOS + Index positioning + 6 + 2 + + + FIDX + First index + 5 + 1 + + + IDIR + Index direction + 1 + 2 + + + IE + Index enable + 0 + 1 + + + + + TISEL + TISEL + timer input selection register + 0x5C + 0x20 + read-write + 0x0000 + + + TI4SEL + Selects tim_ti4[0..15] input + 24 + 4 + + + TI3SEL + Selects tim_ti3[0..15] input + 16 + 4 + + + TI2SEL + Selects tim_ti2[0..15] input + 8 + 4 + + + TI1SEL + Selects tim_ti1[0..15] input + 0 + 4 + + + + + AF1 + AF1 + alternate function register 1 + 0x60 + 0x20 + read-write + 0x0000 + + + ETRSEL + etr_in source selection + 14 + 4 + + + + + AF2 + AF2 + alternate function register 2 + 0x64 + 0x20 + read-write + 0x0000 + + + OCRSEL + ocref_clr source selection + 16 + 3 + + + + + DCR + DCR + DMA control register + 0x3DC + 0x20 + read-write + 0x0000 + + + DBSS + DMA burst source selection + 16 + 4 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x3E0 + 0x20 + read-write + 0x0000 + + + ETRSEL + DMA register for burst accesses + 0 + 32 + + + + + + + SEC_TIM2 + DCB->DSCSR->CDS == 0 + 0x50000000 + + + TIM3 + 0x40000400 + + TIM3 + TIM3 global interrupt + 046 + + + + SEC_TIM3 + DCB->DSCSR->CDS == 0 + 0x50000400 + + + TIM4 + 0x40000800 + + TIM4 + TIM4 global interrupt + 047 + + + + SEC_TIM4 + DCB->DSCSR->CDS == 0 + 0x50000800 + + + TIM5 + 0x40000C00 + + TIM5 + TIM5 global interrupt + 048 + + + + SEC_TIM5 + DCB->DSCSR->CDS == 0 + 0x50000C00 + + + TIM6 + General-purpose-timers + TIM + 0x40001000 + + 0x0 + 0x400 + registers + + + TIM6 + TIM6 global interrupt + 49 + + + + CR1 + CR1 + control register 1 + 0x000 + 0x20 + read-write + 0x0000 + + + DITHEN + Dithering Enable + 12 + 1 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x004 + 0x20 + read-write + 0x0000 + + + MMS + Master mode selection + 4 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0x0C + 0x20 + read-write + 0x0000 + + + UDE + UDE + 8 + 1 + + + UIE + UIE + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + UIF + UIF + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + UG + UG + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x0000 + + + UIFCPY + UIFCPY + 31 + 1 + + + CNT + CNT + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + PSC + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x0000FFFF + + + ARR + ARR + 0 + 20 + + + + + + + SEC_TIM6 + DCB->DSCSR->CDS == 0 + 0x50001000 + + + TIM7 + 0x40001400 + + TIM7 + TIM7 global interrupt + 50 + + + + SEC_TIM7 + DCB->DSCSR->CDS == 0 + 0x50001400 + + + TIM8 + 0x40013400 + + TIM8_BRK + TIM8 Break Interrupt + 051 + + + TIM8_UP + TIM8 Update Interrupt + 052 + + + TIM8_TRG_COM + TIM8 Trigger and Commutation + Interrupt + 053 + + + TIM8_CC + TIM8 Capture Compare Interrupt + 054 + + + + SEC_TIM8 + DCB->DSCSR->CDS == 0 + 0x50013400 + + + TIM15 + General purpose timers + TIM + 0x40014000 + + 0x0 + 0x400 + registers + + + TIM15 + TIM15 global interrupt + 069 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + DITHEN + Dithering enable + 12 + 1 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + OIS2 + Output idle state 2 (OC2 + output) + 10 + 1 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + TI1S + TI1 selection + 7 + 1 + + + MMS + Master mode selection + 4 + 2 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + CCUS + Capture/compare control update + selection + 2 + 1 + + + CCPC + Capture/compare preloaded + control + 0 + 1 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + TS_4_3 + Trigger selection + 20 + 2 + + + SMS_3 + Slave mode selection + 16 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + MSM + Master/slave mode + 7 + 1 + + + TS_2_0 + Trigger selection + 4 + 3 + + + SMS + Slave mode selection + 0 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + COMDE + COM DMA request enable + 13 + 1 + + + CC2DE + Capture/Compare 2 DMA request + enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC2OF + Capture/Compare 2 overcapture + flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + 0x0000 + + + BG + Break generation + 7 + 1 + write-only + + + TG + Trigger generation + 6 + 1 + write-only + + + COMG + Capture/Compare control update + generation + 5 + 1 + read-write + + + CC2G + Capture/Compare 2 + generation + 2 + 1 + write-only + + + CC1G + Capture/compare 1 + generation + 1 + 1 + write-only + + + UG + Update generation + 0 + 1 + write-only + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2M_bit3 + Output Compare 2 mode - bit + 3 + 24 + 1 + + + OC1M_bit3 + Output Compare 1 mode + 16 + 1 + + + OC2M + Output Compare 2 mode + 12 + 3 + + + OC2PE + Output Compare 2 preload + enable + 11 + 1 + + + OC2FE + Output compare 2 fast enable + 10 + 1 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + OC1CE + Output compare 1 clear enable + 7 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC2NP + Capture/Compare 2 complementary output + polarity + 7 + 1 + + + CC2P + Capture/Compare 2 output + polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output + enable + 2 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + 0x00000000 + + + UIFCPY + UIF Copy + 31 + 1 + read-only + + + CNT + counter value + 0 + 16 + read-write + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x0000FFFF + + + ARR + Auto-reload value + 0 + 20 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + REP + Repetition counter value + 0 + 8 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 20 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/Compare 2 value + 0 + 20 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x0000 + + + BKBID + Break Bidirectional + 28 + 1 + + + BKDSRM + Break Disarm + 26 + 1 + + + BKF + Break filter + 16 + 4 + + + MOE + Main output enable + 15 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + BKP + Break polarity + 13 + 1 + + + BKE + Break enable + 12 + 1 + + + OSSR + Off-state selection for Run + mode + 11 + 1 + + + OSSI + Off-state selection for Idle + mode + 10 + 1 + + + LOCK + Lock configuration + 8 + 2 + + + DTG + Dead-time generator setup + 0 + 8 + + + + + DTR2 + DTR2 + timer deadtime register 2 + 0x54 + 0x20 + read-write + 0x0000 + + + DTPE + Deadtime preload enable + 17 + 1 + + + DTAE + Deadtime asymmetric enable + 16 + 1 + + + DTGF + Dead-time falling edge generator setup + 0 + 8 + + + + + TISEL + TISEL + input selection register + 0x5C + 0x20 + read-write + 0x0000 + + + TI2SEL + selects tim_ti2_in[0..15] input + 8 + 4 + + + TI1SEL + selects tim_ti1_in[0..15] input + 0 + 4 + + + + + AF1 + AF1 + alternate function register 1 + 0x60 + 0x20 + read-write + 0x0000 + + + BKCMP4P + tim_brk_cmp4 input polarity + 13 + 1 + + + BKCMP3P + tim_brk_cmp3 input polarity + 12 + 1 + + + BKCMP2P + tim_brk_cmp2 input polarity + 11 + 1 + + + BKCMP1P + tim_brk_cmp1 input polarity + 10 + 1 + + + BKINP + TIMx_BKIN input polarity + 9 + 1 + + + BKCMP7E + tim_brk_cmp7 enable + 7 + 1 + + + BKCMP6E + tim_brk_cmp6 enable + 6 + 1 + + + BKCMP5E + tim_brk_cmp5 enable + 5 + 1 + + + BKCMP4E + tim_brk_cmp4 enable + 4 + 1 + + + BKCMP3E + tim_brk_cmp3 enable + 3 + 1 + + + BKCMP2E + tim_brk_cmp2 enable + 2 + 1 + + + BKCMP1E + tim_brk_cmp1 enable + 1 + 1 + + + BKINE + TIMx_BKIN input enable + 0 + 1 + + + + + AF2 + AF2 + alternate function register 2 + 0x64 + 0x20 + read-write + 0x00000001 + + + OCRSEL + ocref_clr source selection + 16 + 3 + + + + + DCR + DCR + DMA control register + 0x3DC + 0x20 + read-write + 0x0000 + + + DBSS + DMA burst source selection + 16 + 4 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x3E0 + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst accesses + 0 + 32 + + + + + + + SEC_TIM15 + DCB->DSCSR->CDS == 0 + 0x50014000 + + + TIM16 + General purpose timers + TIM + 0x40014400 + + 0x0 + 0x400 + registers + + + TIM16 + TIM16 global interrupt + 070 + + + + CR1 + CR1 + control register 1 + 0x00 + 0x20 + read-write + 0x0000 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + OPM + One pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + CCUS + Capture/compare control update + selection + 2 + 1 + + + CCPC + Capture/compare preloaded + control + 0 + 1 + + + + + DIER + DIER + DMA/interrupt enable register + 0x0C + 0x20 + read-write + 0x0000 + + + COMDE + COM DMA request enable + 13 + 1 + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC1OF + CC1OF + 9 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + CC1IF + Capture/Compare 1 interrupt flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + BG + Break generation + 7 + 1 + + + COMG + Capture/Compare control update + generation + 5 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC1M_2 + Output Compare 1 mode + 16 + 1 + + + OC1CE + Output Compare 1 clear enable + 7 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output + enable + 2 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + 0x00000000 + + + UIFCPY + UIF Copy + 31 + 1 + read-only + + + CNT + CNT + 0 + 16 + read-write + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0xFFFF + + + ARR + Auto-reload value + 0 + 20 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + REP + Repetition counter value + 0 + 8 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 20 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x0000 + + + BKBID + Break Bidirectional + 28 + 1 + + + BKDSRM + Break Disarm + 26 + 1 + + + MOE + Main output enable + 15 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + BKP + Break polarity + 13 + 1 + + + BKE + Break enable + 12 + 1 + + + OSSR + Off-state selection for Run + mode + 11 + 1 + + + OSSI + Off-state selection for Idle + mode + 10 + 1 + + + LOCK + Lock configuration + 8 + 2 + + + DTG + Dead-time generator setup + 0 + 8 + + + + + OR1 + OR1 + option register 1 + 0x50 + 0x20 + read-write + 0x0000 + + + HSE32EN + HSE Divided by 32 enable + 0 + 1 + + + + + DTR2 + DTR2 + timer deadtime register 2 + 0x54 + 0x20 + read-write + 0x0000 + + + DTPE + Deadtime preload enable + 17 + 1 + + + DTAE + Deadtime asymmetric enable + 16 + 1 + + + DTGF + Deadtime asymmetric enable + 0 + 8 + + + + + TISEL + TISEL + TIM17 option register 1 + 0x5C + 0x20 + read-write + 0x00000000 + + + TI1SEL + selects tim_ti1_in[0..15] input + 0 + 4 + + + + + AF1 + AF1 + alternate function register 1 + 0x60 + 0x20 + read-write + 0x00000001 + + + BKCMP4P + tim_brk_cmp4 input polarity + 13 + 1 + + + BKCMP3P + tim_brk_cmp3 input polarity + 12 + 1 + + + BKCMP2P + tim_brk_cmp2 input polarity + 11 + 1 + + + BKCMP1P + tim_brk_cmp1 input polarity + 10 + 1 + + + BKINP + TIMx_BKIN input polarity + 9 + 1 + + + BKCMP7E + tim_brk_cmp7 enable + 7 + 1 + + + BKCMP6E + tim_brk_cmp6 enable + 6 + 1 + + + BKCMP5E + tim_brk_cmp5 enable + 5 + 1 + + + BKCMP4E + tim_brk_cmp4 enable + 4 + 1 + + + BKCMP3E + tim_brk_cmp3 enable + 3 + 1 + + + BKCMP2E + tim_brk_cmp2 enable + 2 + 1 + + + BKCMP1E + tim_brk_cmp1 enable + 1 + 1 + + + BKINE + TIMx_BKIN input enable + 0 + 1 + + + + + AF2 + AF2 + alternate function register 2 + 0x64 + 0x20 + read-write + 0x00000001 + + + OCRSEL + tim_ocref_clr source selection + 16 + 3 + + + + + DCR + DCR + DMA control register + 0x3DC + 0x20 + read-write + 0x00000001 + + + DBSS + DMA burst source selection + 16 + 4 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + TIM17 option register 1 + 0x3E0 + 0x20 + read-write + 0x00000001 + + + DMAB + DMA register for burst accesses + 0 + 32 + + + + + + + SEC_TIM16 + DCB->DSCSR->CDS == 0 + 0x50014400 + + + TIM17 + 0x40014800 + + TIM17 + TIM17 global interrupt + 071 + + + + SEC_TIM17 + DCB->DSCSR->CDS == 0 + 0x50014800 + + + TSC + Touch sensing controller + TSC + 0x40024000 + + 0x0 + 0x400 + registers + + + TSC + TSC global interrupt + 092 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + CTPH + Charge transfer pulse high + 28 + 4 + + + CTPL + Charge transfer pulse low + 24 + 4 + + + SSD + Spread spectrum deviation + 17 + 7 + + + SSE + Spread spectrum enable + 16 + 1 + + + SSPSC + Spread spectrum prescaler + 15 + 1 + + + PGPSC + pulse generator prescaler + 12 + 3 + + + MCV + Max count value + 5 + 3 + + + IODEF + I/O Default mode + 4 + 1 + + + SYNCPOL + Synchronization pin + polarity + 3 + 1 + + + AM + Acquisition mode + 2 + 1 + + + START + Start a new acquisition + 1 + 1 + + + TSCE + Touch sensing controller + enable + 0 + 1 + + + + + IER + IER + interrupt enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + MCEIE + Max count error interrupt + enable + 1 + 1 + + + EOAIE + End of acquisition interrupt + enable + 0 + 1 + + + + + ICR + ICR + interrupt clear register + 0x8 + 0x20 + read-write + 0x00000000 + + + MCEIC + Max count error interrupt + clear + 1 + 1 + + + EOAIC + End of acquisition interrupt + clear + 0 + 1 + + + + + ISR + ISR + interrupt status register + 0xC + 0x20 + read-only + 0x00000000 + + + MCEF + Max count error flag + 1 + 1 + + + EOAF + End of acquisition flag + 0 + 1 + + + + + IOHCR + IOHCR + I/O hysteresis control + register + 0x10 + 0x20 + read-write + 0xFFFFFFFF + + + G8_IO4 + G8_IO4 + 31 + 1 + + + G8_IO3 + G8_IO3 + 30 + 1 + + + G8_IO2 + G8_IO2 + 29 + 1 + + + G8_IO1 + G8_IO1 + 28 + 1 + + + G7_IO4 + G7_IO4 + 27 + 1 + + + G7_IO3 + G7_IO3 + 26 + 1 + + + G7_IO2 + G7_IO2 + 25 + 1 + + + G7_IO1 + G7_IO1 + 24 + 1 + + + G6_IO4 + G6_IO4 + 23 + 1 + + + G6_IO3 + G6_IO3 + 22 + 1 + + + G6_IO2 + G6_IO2 + 21 + 1 + + + G6_IO1 + G6_IO1 + 20 + 1 + + + G5_IO4 + G5_IO4 + 19 + 1 + + + G5_IO3 + G5_IO3 + 18 + 1 + + + G5_IO2 + G5_IO2 + 17 + 1 + + + G5_IO1 + G5_IO1 + 16 + 1 + + + G4_IO4 + G4_IO4 + 15 + 1 + + + G4_IO3 + G4_IO3 + 14 + 1 + + + G4_IO2 + G4_IO2 + 13 + 1 + + + G4_IO1 + G4_IO1 + 12 + 1 + + + G3_IO4 + G3_IO4 + 11 + 1 + + + G3_IO3 + G3_IO3 + 10 + 1 + + + G3_IO2 + G3_IO2 + 9 + 1 + + + G3_IO1 + G3_IO1 + 8 + 1 + + + G2_IO4 + G2_IO4 + 7 + 1 + + + G2_IO3 + G2_IO3 + 6 + 1 + + + G2_IO2 + G2_IO2 + 5 + 1 + + + G2_IO1 + G2_IO1 + 4 + 1 + + + G1_IO4 + G1_IO4 + 3 + 1 + + + G1_IO3 + G1_IO3 + 2 + 1 + + + G1_IO2 + G1_IO2 + 1 + 1 + + + G1_IO1 + G1_IO1 + 0 + 1 + + + + + IOASCR + IOASCR + I/O analog switch control + register + 0x18 + 0x20 + read-write + 0x00000000 + + + G8_IO4 + G8_IO4 + 31 + 1 + + + G8_IO3 + G8_IO3 + 30 + 1 + + + G8_IO2 + G8_IO2 + 29 + 1 + + + G8_IO1 + G8_IO1 + 28 + 1 + + + G7_IO4 + G7_IO4 + 27 + 1 + + + G7_IO3 + G7_IO3 + 26 + 1 + + + G7_IO2 + G7_IO2 + 25 + 1 + + + G7_IO1 + G7_IO1 + 24 + 1 + + + G6_IO4 + G6_IO4 + 23 + 1 + + + G6_IO3 + G6_IO3 + 22 + 1 + + + G6_IO2 + G6_IO2 + 21 + 1 + + + G6_IO1 + G6_IO1 + 20 + 1 + + + G5_IO4 + G5_IO4 + 19 + 1 + + + G5_IO3 + G5_IO3 + 18 + 1 + + + G5_IO2 + G5_IO2 + 17 + 1 + + + G5_IO1 + G5_IO1 + 16 + 1 + + + G4_IO4 + G4_IO4 + 15 + 1 + + + G4_IO3 + G4_IO3 + 14 + 1 + + + G4_IO2 + G4_IO2 + 13 + 1 + + + G4_IO1 + G4_IO1 + 12 + 1 + + + G3_IO4 + G3_IO4 + 11 + 1 + + + G3_IO3 + G3_IO3 + 10 + 1 + + + G3_IO2 + G3_IO2 + 9 + 1 + + + G3_IO1 + G3_IO1 + 8 + 1 + + + G2_IO4 + G2_IO4 + 7 + 1 + + + G2_IO3 + G2_IO3 + 6 + 1 + + + G2_IO2 + G2_IO2 + 5 + 1 + + + G2_IO1 + G2_IO1 + 4 + 1 + + + G1_IO4 + G1_IO4 + 3 + 1 + + + G1_IO3 + G1_IO3 + 2 + 1 + + + G1_IO2 + G1_IO2 + 1 + 1 + + + G1_IO1 + G1_IO1 + 0 + 1 + + + + + IOSCR + IOSCR + I/O sampling control register + 0x20 + 0x20 + read-write + 0x00000000 + + + G8_IO4 + G8_IO4 + 31 + 1 + + + G8_IO3 + G8_IO3 + 30 + 1 + + + G8_IO2 + G8_IO2 + 29 + 1 + + + G8_IO1 + G8_IO1 + 28 + 1 + + + G7_IO4 + G7_IO4 + 27 + 1 + + + G7_IO3 + G7_IO3 + 26 + 1 + + + G7_IO2 + G7_IO2 + 25 + 1 + + + G7_IO1 + G7_IO1 + 24 + 1 + + + G6_IO4 + G6_IO4 + 23 + 1 + + + G6_IO3 + G6_IO3 + 22 + 1 + + + G6_IO2 + G6_IO2 + 21 + 1 + + + G6_IO1 + G6_IO1 + 20 + 1 + + + G5_IO4 + G5_IO4 + 19 + 1 + + + G5_IO3 + G5_IO3 + 18 + 1 + + + G5_IO2 + G5_IO2 + 17 + 1 + + + G5_IO1 + G5_IO1 + 16 + 1 + + + G4_IO4 + G4_IO4 + 15 + 1 + + + G4_IO3 + G4_IO3 + 14 + 1 + + + G4_IO2 + G4_IO2 + 13 + 1 + + + G4_IO1 + G4_IO1 + 12 + 1 + + + G3_IO4 + G3_IO4 + 11 + 1 + + + G3_IO3 + G3_IO3 + 10 + 1 + + + G3_IO2 + G3_IO2 + 9 + 1 + + + G3_IO1 + G3_IO1 + 8 + 1 + + + G2_IO4 + G2_IO4 + 7 + 1 + + + G2_IO3 + G2_IO3 + 6 + 1 + + + G2_IO2 + G2_IO2 + 5 + 1 + + + G2_IO1 + G2_IO1 + 4 + 1 + + + G1_IO4 + G1_IO4 + 3 + 1 + + + G1_IO3 + G1_IO3 + 2 + 1 + + + G1_IO2 + G1_IO2 + 1 + 1 + + + G1_IO1 + G1_IO1 + 0 + 1 + + + + + IOCCR + IOCCR + I/O channel control register + 0x28 + 0x20 + read-write + 0x00000000 + + + G8_IO4 + G8_IO4 + 31 + 1 + + + G8_IO3 + G8_IO3 + 30 + 1 + + + G8_IO2 + G8_IO2 + 29 + 1 + + + G8_IO1 + G8_IO1 + 28 + 1 + + + G7_IO4 + G7_IO4 + 27 + 1 + + + G7_IO3 + G7_IO3 + 26 + 1 + + + G7_IO2 + G7_IO2 + 25 + 1 + + + G7_IO1 + G7_IO1 + 24 + 1 + + + G6_IO4 + G6_IO4 + 23 + 1 + + + G6_IO3 + G6_IO3 + 22 + 1 + + + G6_IO2 + G6_IO2 + 21 + 1 + + + G6_IO1 + G6_IO1 + 20 + 1 + + + G5_IO4 + G5_IO4 + 19 + 1 + + + G5_IO3 + G5_IO3 + 18 + 1 + + + G5_IO2 + G5_IO2 + 17 + 1 + + + G5_IO1 + G5_IO1 + 16 + 1 + + + G4_IO4 + G4_IO4 + 15 + 1 + + + G4_IO3 + G4_IO3 + 14 + 1 + + + G4_IO2 + G4_IO2 + 13 + 1 + + + G4_IO1 + G4_IO1 + 12 + 1 + + + G3_IO4 + G3_IO4 + 11 + 1 + + + G3_IO3 + G3_IO3 + 10 + 1 + + + G3_IO2 + G3_IO2 + 9 + 1 + + + G3_IO1 + G3_IO1 + 8 + 1 + + + G2_IO4 + G2_IO4 + 7 + 1 + + + G2_IO3 + G2_IO3 + 6 + 1 + + + G2_IO2 + G2_IO2 + 5 + 1 + + + G2_IO1 + G2_IO1 + 4 + 1 + + + G1_IO4 + G1_IO4 + 3 + 1 + + + G1_IO3 + G1_IO3 + 2 + 1 + + + G1_IO2 + G1_IO2 + 1 + 1 + + + G1_IO1 + G1_IO1 + 0 + 1 + + + + + IOGCSR + IOGCSR + I/O group control status + register + 0x30 + 0x20 + 0x00000000 + + + G8S + Analog I/O group x status + 23 + 1 + read-only + + + G7S + Analog I/O group x status + 22 + 1 + read-only + + + G6S + Analog I/O group x status + 21 + 1 + read-only + + + G5S + Analog I/O group x status + 20 + 1 + read-only + + + G4S + Analog I/O group x status + 19 + 1 + read-only + + + G3S + Analog I/O group x status + 18 + 1 + read-only + + + G2S + Analog I/O group x status + 17 + 1 + read-only + + + G1S + Analog I/O group x status + 16 + 1 + read-only + + + G8E + Analog I/O group x enable + 7 + 1 + read-write + + + G7E + Analog I/O group x enable + 6 + 1 + read-write + + + G6E + Analog I/O group x enable + 5 + 1 + read-write + + + G5E + Analog I/O group x enable + 4 + 1 + read-write + + + G4E + Analog I/O group x enable + 3 + 1 + read-write + + + G3E + Analog I/O group x enable + 2 + 1 + read-write + + + G2E + Analog I/O group x enable + 1 + 1 + read-write + + + G1E + Analog I/O group x enable + 0 + 1 + read-write + + + + + IOG1CR + IOG1CR + I/O group x counter register + 0x34 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG2CR + IOG2CR + I/O group x counter register + 0x38 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG3CR + IOG3CR + I/O group x counter register + 0x3C + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG4CR + IOG4CR + I/O group x counter register + 0x40 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG5CR + IOG5CR + I/O group x counter register + 0x44 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG6CR + IOG6CR + I/O group x counter register + 0x48 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG7CR + IOG7CR + I/O group x counter register + 0x4C + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG8CR + IOG8CR + I/O group x counter register + 0x50 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + + + SEC_TSC + DCB->DSCSR->CDS == 0 + 0x50024000 + + + UCPD1 + USB Power Delivery interface + UCPD + 0x4000DC00 + + 0x0 + 0x400 + registers + + + UCPD1 + UCPD1 global interrupt + 106 + + + + CFGR1 + CFGR1 + UCPD configuration register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + HBITCLKDIV + HBITCLKDIV + 0 + 6 + + + IFRGAP + IFRGAP + 6 + 5 + + + TRANSWIN + TRANSWIN + 11 + 5 + + + PSC_USBPDCLK + PSC_USBPDCLK + 17 + 3 + + + RXORDSETEN + RXORDSETEN + 20 + 9 + + + TXDMAEN + TXDMAEN + 29 + 1 + + + RXDMAEN + RXDMAEN: + 30 + 1 + + + UCPDEN + UCPDEN + 31 + 1 + + + + + CFGR2 + CFGR2 + UCPD configuration register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + RXFILTDIS + RXFILTDIS + 0 + 1 + + + RXFILT2N3 + RXFILT2N3 + 1 + 1 + + + FORCECLK + FORCECLK + 2 + 1 + + + WUPEN + WUPEN + 3 + 1 + + + + + CFGR3 + CFGR3 + UCPD configuration register 3 + 0x8 + 0x20 + read-write + 0x00000000 + + + TRIM1_NG_CCRPD + TRIM1_NG_CCRPD + 0 + 4 + + + TRIM1_NG_CC3A0 + TRIM1_NG_CC3A0 + 9 + 4 + + + TRIM2_NG_CCRPD + TRIM2_NG_CCRPD + 16 + 4 + + + TRIM2_NG_CC3A0 + TRIM2_NG_CC3A0 + 25 + 4 + + + + + CR + CR + UCPD control register + 0xC + 0x20 + read-write + 0x00000000 + + + TXMODE + TXMODE + 0 + 2 + + + TXSEND + TXSEND + 2 + 1 + + + TXHRST + TXHRST + 3 + 1 + + + RXMODE + RXMODE + 4 + 1 + + + PHYRXEN + PHYRXEN + 5 + 1 + + + PHYCCSEL + PHYCCSEL + 6 + 1 + + + ANASUBMODE + ANASUBMODE + 7 + 2 + + + ANAMODE + ANAMODE + 9 + 1 + + + CCENABLE + CCENABLE + 10 + 2 + + + FRSRXEN + FRSRXEN + 16 + 1 + + + FRSTX + FRSTX + 17 + 1 + + + RDCH + RDCH + 18 + 1 + + + CC1TCDIS + CC1TCDIS + 20 + 1 + + + CC2TCDIS + CC2TCDIS + 21 + 1 + + + + + IMR + IMR + UCPD Interrupt Mask Register + 0x10 + 0x20 + read-write + 0x00000000 + + + TXISIE + TXISIE + 0 + 1 + + + TXMSGDISCIE + TXMSGDISCIE + 1 + 1 + + + TXMSGSENTIE + TXMSGSENTIE + 2 + 1 + + + TXMSGABTIE + TXMSGABTIE + 3 + 1 + + + HRSTDISCIE + HRSTDISCIE + 4 + 1 + + + HRSTSENTIE + HRSTSENTIE + 5 + 1 + + + TXUNDIE + TXUNDIE + 6 + 1 + + + RXNEIE + RXNEIE + 8 + 1 + + + RXORDDETIE + RXORDDETIE + 9 + 1 + + + RXHRSTDETIE + RXHRSTDETIE + 10 + 1 + + + RXOVRIE + RXOVRIE + 11 + 1 + + + RXMSGENDIE + RXMSGENDIE + 12 + 1 + + + TYPECEVT1IE + TYPECEVT1IE + 14 + 1 + + + TYPECEVT2IE + TYPECEVT2IE + 15 + 1 + + + FRSEVTIE + FRSEVTIE + 20 + 1 + + + + + SR + SR + UCPD Status Register + 0x14 + 0x20 + read-only + 0x00000000 + + + TXIS + TXIS + 0 + 1 + + + TXMSGDISC + TXMSGDISC + 1 + 1 + + + TXMSGSENT + TXMSGSENT + 2 + 1 + + + TXMSGABT + TXMSGABT + 3 + 1 + + + HRSTDISC + HRSTDISC + 4 + 1 + + + HRSTSENT + HRSTSENT + 5 + 1 + + + TXUND + TXUND + 6 + 1 + + + RXNE + RXNE + 8 + 1 + + + RXORDDET + RXORDDET + 9 + 1 + + + RXHRSTDET + RXHRSTDET + 10 + 1 + + + RXOVR + RXOVR + 11 + 1 + + + RXMSGEND + RXMSGEND + 12 + 1 + + + RXERR + RXERR + 13 + 1 + + + TYPECEVT1 + TYPECEVT1 + 14 + 1 + + + TYPECEVT2 + TYPECEVT2 + 15 + 1 + + + TYPEC_VSTATE_CC1 + TYPEC_VSTATE_CC1 + 16 + 2 + + + TYPEC_VSTATE_CC2 + TYPEC_VSTATE_CC2 + 18 + 2 + + + FRSEVT + FRSEVT + 20 + 1 + + + + + ICR + ICR + UCPD Interrupt Clear Register + 0x18 + 0x20 + write-only + 0x00000000 + + + TXMSGDISCCF + TXMSGDISCCF + 1 + 1 + + + TXMSGSENTCF + TXMSGSENTCF + 2 + 1 + + + TXMSGABTCF + TXMSGABTCF + 3 + 1 + + + HRSTDISCCF + HRSTDISCCF + 4 + 1 + + + HRSTSENTCF + HRSTSENTCF + 5 + 1 + + + TXUNDCF + TXUNDCF + 6 + 1 + + + RXORDDETCF + RXORDDETCF + 9 + 1 + + + RXHRSTDETCF + RXHRSTDETCF + 10 + 1 + + + RXOVRCF + RXOVRCF + 11 + 1 + + + RXMSGENDCF + RXMSGENDCF + 12 + 1 + + + TYPECEVT1CF + TYPECEVT1CF + 14 + 1 + + + TYPECEVT2CF + TYPECEVT2CF + 15 + 1 + + + FRSEVTCF + FRSEVTCF + 20 + 1 + + + + + TX_ORDSET + TX_ORDSET + UCPD Tx Ordered Set Type + Register + 0x1C + 0x20 + read-write + 0x00000000 + + + TXORDSET + TXORDSET + 0 + 20 + + + + + TX_PAYSZ + TX_PAYSZ + UCPD Tx payload size Register + 0x20 + 0x20 + read-write + 0x00000000 + + + TXPAYSZ + TXPAYSZ + 0 + 10 + + + + + TXDR + TXDR + UCPD Tx Data Register + 0x24 + 0x20 + read-write + 0x00000000 + + + TXDATA + TXDATA + 0 + 8 + + + + + RX_ORDSET + RX_ORDSET + UCPD Rx Ordered Set Register + 0x28 + 0x20 + read-only + 0x00000000 + + + RXORDSET + RXORDSET + 0 + 3 + + + RXSOP3OF4 + RXSOP3OF4 + 3 + 1 + + + RXSOPKINVALID + RXSOPKINVALID + 4 + 3 + + + + + RX_PAYSZ + RX_PAYSZ + UCPD Rx payload size Register + 0x2C + 0x20 + read-only + 0x00000000 + + + RXPAYSZ + RXPAYSZ + 0 + 10 + + + + + RXDR + RXDR + UCPD Receive Data Register + 0x30 + 0x20 + read-only + 0x00000000 + + + RXDATA + RXDATA + 0 + 8 + + + + + RX_ORDEXT1 + RX_ORDEXT1 + UCPD Rx Ordered Set Extension + Register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + RXSOPX1 + RXSOPX1 + 0 + 20 + + + + + RX_ORDEXT2 + RX_ORDEXT2 + UCPD Rx Ordered Set Extension + Register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + RXSOPX2 + RXSOPX2 + 0 + 20 + + + + + + + SEC_UCPD1 + DCB->DSCSR->CDS == 0 + 0x5000DC00 + + + USART1 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40013800 + + 0x0 + 0x400 + registers + + + USART1 + USART1 global interrupt + 061 + + + + CR1_enabled + CR1_enabled + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + M1 + Word length + 28 + 1 + + + EOBIE + End of Block interruptenable + 27 + 1 + + + RTOIE + Receiver timeout interrupt + 26 + 1 + + + DEAT + DEAT + 21 + 5 + + + DEDT + DEDT + 16 + 5 + + + OVER8 + Oversampling mode + 15 + 1 + + + CMIE + Character match interrupt + enable + 14 + 1 + + + MME + Mute mode enable + 13 + 1 + + + M0 + Word length + 12 + 1 + + + WAKE + Receiver wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXFNFIE + TXFIFO not full interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt + enable + 6 + 1 + + + RXFNEIE + RXFIFO not empty interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + UESM + USART enable in Stop mode + 1 + 1 + + + UE + USART enable + 0 + 1 + + + FIFOEN + FIFOEN + 29 + 1 + + + TXFEIE + TXFEIE + 30 + 1 + + + RXFFIE + RXFFIE + 31 + 1 + + + + + CR1_disabled + CR1_disabled + Control register 1 + CR1_enabled + 0x0 + 0x20 + read-write + 0x0000 + + + M1 + Word length + 28 + 1 + + + EOBIE + End of Block interrupt + enable + 27 + 1 + + + RTOIE + Receiver timeout interrupt + enable + 26 + 1 + + + DEAT + DEAT + 21 + 5 + + + DEDT + DEDT + 16 + 5 + + + OVER8 + Oversampling mode + 15 + 1 + + + CMIE + Character match interrupt + enable + 14 + 1 + + + MME + Mute mode enable + 13 + 1 + + + M0 + Word length + 12 + 1 + + + WAKE + Receiver wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXFNFIE + TXFIFO not full interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt + enable + 6 + 1 + + + RXFNEIE + RXFIFO not empty interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + UESM + USART enable in Stop mode + 1 + 1 + + + UE + USART enable + 0 + 1 + + + FIFOEN + FIFOEN + 29 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + ADD + Address of the USART node + 24 + 8 + + + RTOEN + Receiver timeout enable + 23 + 1 + + + ABRMOD + Auto baud rate mode + 21 + 2 + + + ABREN + Auto baud rate enable + 20 + 1 + + + MSBFIRST + Most significant bit first + 19 + 1 + + + DATAINV + Binary data inversion + 18 + 1 + + + TXINV + TX pin active level + inversion + 17 + 1 + + + RXINV + RX pin active level + inversion + 16 + 1 + + + SWAP + Swap TX/RX pins + 15 + 1 + + + LINEN + LIN mode enable + 14 + 1 + + + STOP + STOP bits + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CPOL + Clock polarity + 10 + 1 + + + CPHA + Clock phase + 9 + 1 + + + LBCL + Last bit clock pulse + 8 + 1 + + + LBDIE + LIN break detection interrupt + enable + 6 + 1 + + + LBDL + LIN break detection length + 5 + 1 + + + ADDM7 + 7-bit Address Detection/4-bit Address + Detection + 4 + 1 + + + SLVEN + SLVEN + 0 + 1 + + + DIS_NSS + DIS_NSS + 3 + 1 + + + + + CR3 + CR3 + Control register 3 + 0x8 + 0x20 + read-write + 0x0000 + + + SCARCNT + Smartcard auto-retry count + 17 + 3 + + + DEP + Driver enable polarity + selection + 15 + 1 + + + DEM + Driver enable mode + 14 + 1 + + + DDRE + DMA Disable on Reception + Error + 13 + 1 + + + OVRDIS + Overrun Disable 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CMCF + Character match clear flag + 17 + 1 + + + EOBCF + End of block clear flag + 12 + 1 + + + RTOCF + Receiver timeout clear + flag + 11 + 1 + + + CTSCF + CTS clear flag + 9 + 1 + + + LBDCF + LIN break detection clear + flag + 8 + 1 + + + TCCF + Transmission complete clear + flag + 6 + 1 + + + IDLECF + Idle line detected clear + flag + 4 + 1 + + + ORECF + Overrun error clear flag + 3 + 1 + + + NECF + Noise detected clear flag + 2 + 1 + + + FECF + Framing error clear flag + 1 + 1 + + + PECF + Parity error clear flag + 0 + 1 + + + TXFECF + TXFECF + 5 + 1 + + + TCBGTCF + TCBGTCF + 7 + 1 + + + UDRCF + UDRCF + 13 + 1 + + + + + RDR + RDR + Receive data register + 0x24 + 0x20 + read-only + 0x0000 + + + RDR + Receive data value + 0 + 9 + + + + + TDR + TDR + Transmit data register + 0x28 + 0x20 + read-write + 0x0000 + + + TDR + Transmit data value + 0 + 9 + + + + + PRESC + PRESC + PRESC + 0x2C + 0x20 + read-write + 0x0000 + + + PRESCALER + PRESCALER + 0 + 4 + + + + + AUTOCR + AUTOCR + AUTOCR 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VREFBUF_CSR + VREFBUF_CSR + VREFBUF control and status register + 0x0 + 0x20 + 0x00000002 + + + ENVR + ENVR + 0 + 1 + read-write + + + HIZ + HIZ + 1 + 1 + read-write + + + VRR + VRR + 3 + 1 + read-only + + + VRS + VRS + 4 + 3 + read-write + + + + + VREFBUF_CCR + VREFBUF_CCR + VREFBUF calibration control register + 0x4 + 0x20 + read-write + 0x00000000 + + + TRIM + TRIM + 0 + 6 + + + + + + + SEC_VREFBUF + DCB->DSCSR->CDS == 0 + 0x56007400 + + + WWDG + System window watchdog + WWDG + 0x40002C00 + + 0x0 + 0x400 + registers + + + WWDG + Window Watchdog interrupt + 000 + + + + CR + CR + Control register + 0x0 + 0x20 + read-write + 0x0000007F + + + WDGA + Activation bit + 7 + 1 + + + T + 7-bit counter (MSB to LSB) + 0 + 7 + + + + + CFR + CFR + Configuration register + 0x4 + 0x20 + read-write + 0x0000007F + + + WDGTB + Timer base + 11 + 3 + + + EWI + Early wakeup interrupt + 9 + 1 + + + W + 7-bit window value + 0 + 7 + + + + + SR + SR + Status register + 0x8 + 0x20 + read-write + 0x00000000 + + + EWIF + Early wakeup interrupt + flag + 0 + 1 + + + + + + + SEC_WWDG + DCB->DSCSR->CDS == 0 + 0x50002C00 + + + DCB + Debug Control Block + DCB + 0xE000EE08 + + 0x0 + 0x5 + registers + + + + DSCSR + DSCSR + Debug Security Control and Status Register + 0x0 + 0x20 + read-write + 0x00000000 + + + CDS + Current domain Secure + 16 + 1 + + + + + + +