Qualcomm AI Engine Direct - Enabling Support for Qualcomm Chipsets for Snapdragon 7+ Gen 3 (pytorch#22542)

### Summary
Adding SoC support for SM7675 (Snapdragon 7+ Gen 3) and SM8635
(Snapdragon 8s Gen 3), both HTP V73.

Scope of Support:
- Quantized HTP: supported*. Quantized HTP validated across
8a8w/16a4w/16a2w, per-channel, block-wise, and QAT paths, plus the full
quantized utils suite. See test cases in the Test Plan section. I did
not run the whole quantized ops/model suite, which is why support is
denoted with a (*).
- FP16: not supported. QNN rejects these SoCs for FP16 (`"The SocModel
doesn't support FP16"`), so FP16 lowering does not produce a delegated
graph. Note it also does not degrade gracefully today: models containing
ops on the partitioner's non-decompose list (e.g. `linear`,
`layer_norm`) fail to export rather than falling back to CPU.

Note that these changes need the fix added in
pytorch#22543 for the tests to pass.

### Test plan
```
python backends/qualcomm/tests/test_qnn_delegate.py \
  TestQNNQuantizedOperator.test_qnn_backend_16a4w_conv2d \
  TestQNNQuantizedOperator.test_qnn_backend_16a4w_linear \
  TestQNNQuantizedOperator.test_qnn_backend_16a4w_layer_norm \
  TestQNNQuantizedOperator.test_qnn_backend_16a4w_conv2d \
  -v --soc_model SM8635 --host aisw-local-vm3 --device 4603496b \
  --build_folder build-android

python backends/qualcomm/tests/test_qnn_delegate.py \
 TestQNNQuantizedOperator.test_qnn_backend_sort \
 TestQNNQuantizedOperator.test_qnn_backend_conv2d \
 TestQNNQuantizedOperator.test_qnn_backend_linear \
 TestQNNQuantizedOperator.test_qnn_backend_layer_norm \
 TestQNNQuantizedOperator.test_qnn_backend_element_wise_add \
  -v --soc_model SM8635 --host aisw-local-vm3 --device 4603496b \
  --build_folder build-android

python backends/qualcomm/tests/test_qnn_delegate.py \
  TestQNNQuantizedOperator.test_qnn_backend_16a2w_conv2d \
  TestQNNQuantizedOperator.test_qnn_backend_16a2w_linear \
  TestQNNQuantizedOperator.test_qnn_backend_16a4w_per_channel_linear \
  TestQNNQuantizedOperator.test_qnn_backend_16a4w_per_channel_linear_with_bias \
  TestQNNQuantizedOperator.test_qnn_backend_16a4w_conv2d_qat \
  TestQNNQuantizedOperator.test_qnn_backend_16a4w_block_conv2d_qat \
  -v --soc_model SM8635 --host aisw-local-vm3 --device 4603496b \
  --build_folder build-android

python backends/qualcomm/tests/test_qnn_delegate.py   TestQNNQuantizedUtils -v   --soc_model SM8635   --host aisw-local-vm3   --device 4603496b   --build_folder build-android
```

Author: qti-horodnic

backends/qualcomm/serialization/qc_compiler_spec.fbs

@@ -48,10 +48,12 @@ enum QcomChipset: int {
   SA8295 = 39,
   SA8797 = 72,
   SC8380XP = 60,
+  SM7675 = 70,
   SM8350 = 30,
   SM8450 = 36,
   SM8475 = 42,
   SM8550 = 43,
+  SM8635 = 68,
   SM8650 = 57,
   SM8750 = 69,
   SM8850 = 87,

backends/qualcomm/serialization/qc_schema.py

@@ -55,10 +55,12 @@ class QcomChipset(IntEnum):
     SA8295 = 39  # v68
     SA8797 = 72  # v81
     SC8380XP = 60  # v73
+    SM7675 = 70  # v73
     SM8350 = 30  # v68
     SM8450 = 36  # v69
     SM8475 = 42  # v69
     SM8550 = 43  # v73
+    SM8635 = 68  # v73
     SM8650 = 57  # v75
     SM8750 = 69  # v79
     SM8850 = 87  # v81
@@ -86,11 +88,13 @@ class SocInfo:
     QcomChipset.SA8295: SocInfo(QcomChipset.SA8295, HtpInfo(HtpArch.V68, 8)),
     QcomChipset.SA8797: SocInfo(QcomChipset.SA8797, HtpInfo(HtpArch.V81, 16)),
     QcomChipset.SC8380XP: SocInfo(QcomChipset.SC8380XP, HtpInfo(HtpArch.V73, 8)),
+    QcomChipset.SM7675: SocInfo(QcomChipset.SM7675, HtpInfo(HtpArch.V73, 4)),
     QcomChipset.SM8350: SocInfo(QcomChipset.SM8350, HtpInfo(HtpArch.V68, 4)),
     QcomChipset.SM8450: SocInfo(QcomChipset.SM8450, HtpInfo(HtpArch.V69, 8)),
     QcomChipset.SM8475: SocInfo(QcomChipset.SM8475, HtpInfo(HtpArch.V69, 8)),
     QcomChipset.SM8550: SocInfo(QcomChipset.SM8550, HtpInfo(HtpArch.V73, 8)),
     QcomChipset.SA8255: SocInfo(QcomChipset.SA8255, HtpInfo(HtpArch.V73, 8)),
+    QcomChipset.SM8635: SocInfo(QcomChipset.SM8635, HtpInfo(HtpArch.V73, 4)),
     QcomChipset.SM8650: SocInfo(QcomChipset.SM8650, HtpInfo(HtpArch.V75, 8)),
     QcomChipset.SM8750: SocInfo(QcomChipset.SM8750, HtpInfo(HtpArch.V79, 8)),
     QcomChipset.SM8850: SocInfo(

backends/qualcomm/utils/utils.py

@@ -1199,9 +1199,11 @@ def generate_qnn_executorch_compiler_spec(  # noqa: C901
     Args:
         soc_model: The SoC you plan to run the compiled model. Please check
             QcomChipset for supported SoC.
+            SM7675(Snapdragon 7+ Gen 3)
             SM8450 (Snapdragon 8 Gen 1)
             SM8475(Snapdragon 8 Gen 1+)
             SM8550(Snapdragon 8 Gen 2)
+            SM8635(Snapdragon 8s Gen 3)
             SM8650(Snapdragon 8 Gen 3)
             SM8750(Snapdragon 8 Elite)
             SM8850(Snapdragon 8 Elite Gen 5)
@@ -1332,7 +1334,9 @@ def get_soc_to_htp_arch_map():
         "SM8450": HtpArch.V69,
         "SM8475": HtpArch.V69,
         "SM8550": HtpArch.V73,
+        "SM7675": HtpArch.V73,
         "SA8255": HtpArch.V73,
+        "SM8635": HtpArch.V73,
         "SM8650": HtpArch.V75,
         "SM8750": HtpArch.V79,
         "SM8850": HtpArch.V81,
@@ -1362,11 +1366,13 @@ def get_soc_to_chipset_map():
         "SA8295": QcomChipset.SA8295,
         "SA8797": QcomChipset.SA8797,
         "SC8380XP": QcomChipset.SC8380XP,
+        "SM7675": QcomChipset.SM7675,
         "SM8350": QcomChipset.SM8350,
         "SM8450": QcomChipset.SM8450,
         "SM8475": QcomChipset.SM8475,
         "SM8550": QcomChipset.SM8550,
         "SA8255": QcomChipset.SA8255,
+        "SM8635": QcomChipset.SM8635,
         "SM8650": QcomChipset.SM8650,
         "SM8750": QcomChipset.SM8750,
         "SM8850": QcomChipset.SM8850,